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r8169:prevent enable hardware tx/rx too early
[mirror_ubuntu-zesty-kernel.git] / drivers / net / ethernet / realtek / r8169.c
CommitLineData
1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
18#include <linux/mii.h>
19#include <linux/if_vlan.h>
20#include <linux/crc32.h>
21#include <linux/in.h>
22#include <linux/ip.h>
23#include <linux/tcp.h>
a6b7a407 24#include <linux/interrupt.h>
1da177e4 25#include <linux/dma-mapping.h>
e1759441 26#include <linux/pm_runtime.h>
bca03d5f 27#include <linux/firmware.h>
ba04c7c9 28#include <linux/pci-aspm.h>
70c71606 29#include <linux/prefetch.h>
e974604b 30#include <linux/ipv6.h>
31#include <net/ip6_checksum.h>
1da177e4
LT		 32
33#include <asm/io.h>
34#include <asm/irq.h>
35
865c652d 36#define RTL8169_VERSION "2.3LK-NAPI"
1da177e4
LT		 37#define MODULENAME "r8169"
38#define PFX MODULENAME ": "
39
bca03d5f 40#define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
41#define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
01dc7fec 42#define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
43#define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
70090424 44#define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
c2218925
HW		 45#define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
46#define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
5a5e4443 47#define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
7e18dca1 48#define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
b3d7b2f2 49#define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
45dd95c4 50#define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw"
5598bfe5 51#define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
58152cd4 52#define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw"
beb330a4 53#define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw"
57538c4a 54#define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw"
6e1d0b89
CHL		 55#define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw"
56#define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw"
57#define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw"
58#define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw"
bca03d5f 59
1da177e4
LT		 60#ifdef RTL8169_DEBUG
61#define assert(expr) \
5b0384f4
FR		 62 if (!(expr)) { \
63 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
b39d66a8 64 #expr,__FILE__,__func__,__LINE__); \
5b0384f4 65 }
06fa7358
JP		 66#define dprintk(fmt, args...) \
67 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
1da177e4
LT		 68#else
69#define assert(expr) do {} while (0)
70#define dprintk(fmt, args...) do {} while (0)
71#endif /* RTL8169_DEBUG */
72
b57b7e5a 73#define R8169_MSG_DEFAULT \
f0e837d9 74 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 75
477206a0
JD		 76#define TX_SLOTS_AVAIL(tp) \
77 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
78
79/* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
80#define TX_FRAGS_READY_FOR(tp,nr_frags) \
81 (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
1da177e4 82
1da177e4
LT		 83/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
84 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 85static const int multicast_filter_limit = 32;
1da177e4 86
9c14ceaf 87#define MAX_READ_REQUEST_SHIFT 12
aee77e4a 88#define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
1da177e4
LT		 89#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
90
91#define R8169_REGS_SIZE 256
92#define R8169_NAPI_WEIGHT 64
93#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
9fba0812 94#define NUM_RX_DESC 256U /* Number of Rx descriptor registers */
1da177e4
LT		 95#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
96#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
97
98#define RTL8169_TX_TIMEOUT (6*HZ)
99#define RTL8169_PHY_TIMEOUT (10*HZ)
100
101/* write/read MMIO register */
102#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
103#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
104#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
105#define RTL_R8(reg) readb (ioaddr + (reg))
106#define RTL_R16(reg) readw (ioaddr + (reg))
06f555f3 107#define RTL_R32(reg) readl (ioaddr + (reg))
1da177e4
LT		 108
109enum mac_version {
85bffe6c
FR		 110 RTL_GIGA_MAC_VER_01 = 0,
111 RTL_GIGA_MAC_VER_02,
112 RTL_GIGA_MAC_VER_03,
113 RTL_GIGA_MAC_VER_04,
114 RTL_GIGA_MAC_VER_05,
115 RTL_GIGA_MAC_VER_06,
116 RTL_GIGA_MAC_VER_07,
117 RTL_GIGA_MAC_VER_08,
118 RTL_GIGA_MAC_VER_09,
119 RTL_GIGA_MAC_VER_10,
120 RTL_GIGA_MAC_VER_11,
121 RTL_GIGA_MAC_VER_12,
122 RTL_GIGA_MAC_VER_13,
123 RTL_GIGA_MAC_VER_14,
124 RTL_GIGA_MAC_VER_15,
125 RTL_GIGA_MAC_VER_16,
126 RTL_GIGA_MAC_VER_17,
127 RTL_GIGA_MAC_VER_18,
128 RTL_GIGA_MAC_VER_19,
129 RTL_GIGA_MAC_VER_20,
130 RTL_GIGA_MAC_VER_21,
131 RTL_GIGA_MAC_VER_22,
132 RTL_GIGA_MAC_VER_23,
133 RTL_GIGA_MAC_VER_24,
134 RTL_GIGA_MAC_VER_25,
135 RTL_GIGA_MAC_VER_26,
136 RTL_GIGA_MAC_VER_27,
137 RTL_GIGA_MAC_VER_28,
138 RTL_GIGA_MAC_VER_29,
139 RTL_GIGA_MAC_VER_30,
140 RTL_GIGA_MAC_VER_31,
141 RTL_GIGA_MAC_VER_32,
142 RTL_GIGA_MAC_VER_33,
70090424 143 RTL_GIGA_MAC_VER_34,
c2218925
HW		 144 RTL_GIGA_MAC_VER_35,
145 RTL_GIGA_MAC_VER_36,
7e18dca1 146 RTL_GIGA_MAC_VER_37,
b3d7b2f2 147 RTL_GIGA_MAC_VER_38,
5598bfe5 148 RTL_GIGA_MAC_VER_39,
c558386b
HW		 149 RTL_GIGA_MAC_VER_40,
150 RTL_GIGA_MAC_VER_41,
57538c4a 151 RTL_GIGA_MAC_VER_42,
58152cd4 152 RTL_GIGA_MAC_VER_43,
45dd95c4 153 RTL_GIGA_MAC_VER_44,
6e1d0b89
CHL		 154 RTL_GIGA_MAC_VER_45,
155 RTL_GIGA_MAC_VER_46,
156 RTL_GIGA_MAC_VER_47,
157 RTL_GIGA_MAC_VER_48,
935e2218
CHL		 158 RTL_GIGA_MAC_VER_49,
159 RTL_GIGA_MAC_VER_50,
160 RTL_GIGA_MAC_VER_51,
85bffe6c 161 RTL_GIGA_MAC_NONE = 0xff,
1da177e4
LT		 162};
163
2b7b4318
FR		 164enum rtl_tx_desc_version {
165 RTL_TD_0 = 0,
166 RTL_TD_1 = 1,
167};
168
d58d46b5
FR		 169#define JUMBO_1K ETH_DATA_LEN
170#define JUMBO_4K (4*1024 - ETH_HLEN - 2)
171#define JUMBO_6K (6*1024 - ETH_HLEN - 2)
172#define JUMBO_7K (7*1024 - ETH_HLEN - 2)
173#define JUMBO_9K (9*1024 - ETH_HLEN - 2)
174
175#define _R(NAME,TD,FW,SZ,B) { \
176 .name = NAME, \
177 .txd_version = TD, \
178 .fw_name = FW, \
179 .jumbo_max = SZ, \
180 .jumbo_tx_csum = B \
181}
1da177e4 182
3c6bee1d 183static const struct {
1da177e4 184 const char *name;
2b7b4318 185 enum rtl_tx_desc_version txd_version;
953a12cc 186 const char *fw_name;
d58d46b5
FR		 187 u16 jumbo_max;
188 bool jumbo_tx_csum;
85bffe6c
FR		 189} rtl_chip_infos[] = {
190 /* PCI devices. */
191 [RTL_GIGA_MAC_VER_01] =
d58d46b5 192 _R("RTL8169", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 193 [RTL_GIGA_MAC_VER_02] =
d58d46b5 194 _R("RTL8169s", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 195 [RTL_GIGA_MAC_VER_03] =
d58d46b5 196 _R("RTL8110s", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 197 [RTL_GIGA_MAC_VER_04] =
d58d46b5 198 _R("RTL8169sb/8110sb", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 199 [RTL_GIGA_MAC_VER_05] =
d58d46b5 200 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 201 [RTL_GIGA_MAC_VER_06] =
d58d46b5 202 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c
FR		 203 /* PCI-E devices. */
204 [RTL_GIGA_MAC_VER_07] =
d58d46b5 205 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
85bffe6c 206 [RTL_GIGA_MAC_VER_08] =
d58d46b5 207 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
85bffe6c 208 [RTL_GIGA_MAC_VER_09] =
d58d46b5 209 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
85bffe6c 210 [RTL_GIGA_MAC_VER_10] =
d58d46b5 211 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 212 [RTL_GIGA_MAC_VER_11] =
d58d46b5 213 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
85bffe6c 214 [RTL_GIGA_MAC_VER_12] =
d58d46b5 215 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
85bffe6c 216 [RTL_GIGA_MAC_VER_13] =
d58d46b5 217 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 218 [RTL_GIGA_MAC_VER_14] =
d58d46b5 219 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 220 [RTL_GIGA_MAC_VER_15] =
d58d46b5 221 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 222 [RTL_GIGA_MAC_VER_16] =
d58d46b5 223 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 224 [RTL_GIGA_MAC_VER_17] =
f75761b6 225 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
85bffe6c 226 [RTL_GIGA_MAC_VER_18] =
d58d46b5 227 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 228 [RTL_GIGA_MAC_VER_19] =
d58d46b5 229 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 230 [RTL_GIGA_MAC_VER_20] =
d58d46b5 231 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 232 [RTL_GIGA_MAC_VER_21] =
d58d46b5 233 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 234 [RTL_GIGA_MAC_VER_22] =
d58d46b5 235 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 236 [RTL_GIGA_MAC_VER_23] =
d58d46b5 237 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 238 [RTL_GIGA_MAC_VER_24] =
d58d46b5 239 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 240 [RTL_GIGA_MAC_VER_25] =
d58d46b5
FR		 241 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1,
242 JUMBO_9K, false),
85bffe6c 243 [RTL_GIGA_MAC_VER_26] =
d58d46b5
FR		 244 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2,
245 JUMBO_9K, false),
85bffe6c 246 [RTL_GIGA_MAC_VER_27] =
d58d46b5 247 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
85bffe6c 248 [RTL_GIGA_MAC_VER_28] =
d58d46b5 249 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
85bffe6c 250 [RTL_GIGA_MAC_VER_29] =
d58d46b5
FR		 251 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
252 JUMBO_1K, true),
85bffe6c 253 [RTL_GIGA_MAC_VER_30] =
d58d46b5
FR		 254 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
255 JUMBO_1K, true),
85bffe6c 256 [RTL_GIGA_MAC_VER_31] =
d58d46b5 257 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
85bffe6c 258 [RTL_GIGA_MAC_VER_32] =
d58d46b5
FR		 259 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1,
260 JUMBO_9K, false),
85bffe6c 261 [RTL_GIGA_MAC_VER_33] =
d58d46b5
FR		 262 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2,
263 JUMBO_9K, false),
70090424 264 [RTL_GIGA_MAC_VER_34] =
d58d46b5
FR		 265 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
266 JUMBO_9K, false),
c2218925 267 [RTL_GIGA_MAC_VER_35] =
d58d46b5
FR		 268 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_1,
269 JUMBO_9K, false),
c2218925 270 [RTL_GIGA_MAC_VER_36] =
d58d46b5
FR		 271 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_2,
272 JUMBO_9K, false),
7e18dca1
HW		 273 [RTL_GIGA_MAC_VER_37] =
274 _R("RTL8402", RTL_TD_1, FIRMWARE_8402_1,
275 JUMBO_1K, true),
b3d7b2f2
HW		 276 [RTL_GIGA_MAC_VER_38] =
277 _R("RTL8411", RTL_TD_1, FIRMWARE_8411_1,
278 JUMBO_9K, false),
5598bfe5
HW		 279 [RTL_GIGA_MAC_VER_39] =
280 _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_1,
281 JUMBO_1K, true),
c558386b 282 [RTL_GIGA_MAC_VER_40] =
beb330a4 283 _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_2,
c558386b
HW		 284 JUMBO_9K, false),
285 [RTL_GIGA_MAC_VER_41] =
286 _R("RTL8168g/8111g", RTL_TD_1, NULL, JUMBO_9K, false),
57538c4a 287 [RTL_GIGA_MAC_VER_42] =
288 _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_3,
289 JUMBO_9K, false),
58152cd4 290 [RTL_GIGA_MAC_VER_43] =
291 _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_2,
292 JUMBO_1K, true),
45dd95c4 293 [RTL_GIGA_MAC_VER_44] =
294 _R("RTL8411", RTL_TD_1, FIRMWARE_8411_2,
295 JUMBO_9K, false),
6e1d0b89
CHL		 296 [RTL_GIGA_MAC_VER_45] =
297 _R("RTL8168h/8111h", RTL_TD_1, FIRMWARE_8168H_1,
298 JUMBO_9K, false),
299 [RTL_GIGA_MAC_VER_46] =
300 _R("RTL8168h/8111h", RTL_TD_1, FIRMWARE_8168H_2,
301 JUMBO_9K, false),
302 [RTL_GIGA_MAC_VER_47] =
303 _R("RTL8107e", RTL_TD_1, FIRMWARE_8107E_1,
304 JUMBO_1K, false),
305 [RTL_GIGA_MAC_VER_48] =
306 _R("RTL8107e", RTL_TD_1, FIRMWARE_8107E_2,
307 JUMBO_1K, false),
935e2218
CHL		 308 [RTL_GIGA_MAC_VER_49] =
309 _R("RTL8168ep/8111ep", RTL_TD_1, NULL,
310 JUMBO_9K, false),
311 [RTL_GIGA_MAC_VER_50] =
312 _R("RTL8168ep/8111ep", RTL_TD_1, NULL,
313 JUMBO_9K, false),
314 [RTL_GIGA_MAC_VER_51] =
315 _R("RTL8168ep/8111ep", RTL_TD_1, NULL,
316 JUMBO_9K, false),
953a12cc 317};
85bffe6c 318#undef _R
953a12cc 319
bcf0bf90
FR		 320enum cfg_version {
321 RTL_CFG_0 = 0x00,
322 RTL_CFG_1,
323 RTL_CFG_2
324};
325
9baa3c34 326static const struct pci_device_id rtl8169_pci_tbl[] = {
bcf0bf90 327 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 328 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
d81bf551 329 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 330 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90 331 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
2a35cfa5
FR		 332 { PCI_VENDOR_ID_DLINK, 0x4300,
333 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0, RTL_CFG_1 },
bcf0bf90 334 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
93a3aa25 335 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 },
bc1660b5 336 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 337 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
338 { PCI_VENDOR_ID_LINKSYS, 0x1032,
339 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
11d2e282
CM		 340 { 0x0001, 0x8168,
341 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
1da177e4
LT		 342 {0,},
343};
344
345MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
346
6f0333b8 347static int rx_buf_sz = 16383;
4300e8c7 348static int use_dac;
b57b7e5a
SH		 349static struct {
350 u32 msg_enable;
351} debug = { -1 };
1da177e4 352
07d3f51f
FR		 353enum rtl_registers {
354 MAC0 = 0, /* Ethernet hardware address. */
773d2021 355 MAC4 = 4,
07d3f51f
FR		 356 MAR0 = 8, /* Multicast filter. */
357 CounterAddrLow = 0x10,
358 CounterAddrHigh = 0x14,
359 TxDescStartAddrLow = 0x20,
360 TxDescStartAddrHigh = 0x24,
361 TxHDescStartAddrLow = 0x28,
362 TxHDescStartAddrHigh = 0x2c,
363 FLASH = 0x30,
364 ERSR = 0x36,
365 ChipCmd = 0x37,
366 TxPoll = 0x38,
367 IntrMask = 0x3c,
368 IntrStatus = 0x3e,
4f6b00e5 369
07d3f51f 370 TxConfig = 0x40,
4f6b00e5
HW		 371#define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
372#define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
2b7b4318 373
4f6b00e5
HW		 374 RxConfig = 0x44,
375#define RX128_INT_EN (1 << 15) /* 8111c and later */
376#define RX_MULTI_EN (1 << 14) /* 8111c only */
377#define RXCFG_FIFO_SHIFT 13
378 /* No threshold before first PCI xfer */
379#define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
beb330a4 380#define RX_EARLY_OFF (1 << 11)
4f6b00e5
HW		 381#define RXCFG_DMA_SHIFT 8
382 /* Unlimited maximum PCI burst. */
383#define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
2b7b4318 384
07d3f51f
FR		 385 RxMissed = 0x4c,
386 Cfg9346 = 0x50,
387 Config0 = 0x51,
388 Config1 = 0x52,
389 Config2 = 0x53,
d387b427
FR		 390#define PME_SIGNAL (1 << 5) /* 8168c and later */
391
07d3f51f
FR		 392 Config3 = 0x54,
393 Config4 = 0x55,
394 Config5 = 0x56,
395 MultiIntr = 0x5c,
396 PHYAR = 0x60,
07d3f51f
FR		 397 PHYstatus = 0x6c,
398 RxMaxSize = 0xda,
399 CPlusCmd = 0xe0,
400 IntrMitigate = 0xe2,
401 RxDescAddrLow = 0xe4,
402 RxDescAddrHigh = 0xe8,
f0298f81 403 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
404
405#define NoEarlyTx 0x3f /* Max value : no early transmit. */
406
407 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
408
409#define TxPacketMax (8064 >> 7)
3090bd9a 410#define EarlySize 0x27
f0298f81 411
07d3f51f
FR		 412 FuncEvent = 0xf0,
413 FuncEventMask = 0xf4,
414 FuncPresetState = 0xf8,
935e2218
CHL		 415 IBCR0 = 0xf8,
416 IBCR2 = 0xf9,
417 IBIMR0 = 0xfa,
418 IBISR0 = 0xfb,
07d3f51f 419 FuncForceEvent = 0xfc,
1da177e4
LT		 420};
421
f162a5d1
FR		 422enum rtl8110_registers {
423 TBICSR = 0x64,
424 TBI_ANAR = 0x68,
425 TBI_LPAR = 0x6a,
426};
427
428enum rtl8168_8101_registers {
429 CSIDR = 0x64,
430 CSIAR = 0x68,
431#define CSIAR_FLAG 0x80000000
432#define CSIAR_WRITE_CMD 0x80000000
433#define CSIAR_BYTE_ENABLE 0x0f
434#define CSIAR_BYTE_ENABLE_SHIFT 12
435#define CSIAR_ADDR_MASK 0x0fff
7e18dca1
HW		 436#define CSIAR_FUNC_CARD 0x00000000
437#define CSIAR_FUNC_SDIO 0x00010000
438#define CSIAR_FUNC_NIC 0x00020000
45dd95c4 439#define CSIAR_FUNC_NIC2 0x00010000
065c27c1 440 PMCH = 0x6f,
f162a5d1
FR		 441 EPHYAR = 0x80,
442#define EPHYAR_FLAG 0x80000000
443#define EPHYAR_WRITE_CMD 0x80000000
444#define EPHYAR_REG_MASK 0x1f
445#define EPHYAR_REG_SHIFT 16
446#define EPHYAR_DATA_MASK 0xffff
5a5e4443 447 DLLPR = 0xd0,
4f6b00e5 448#define PFM_EN (1 << 6)
6e1d0b89 449#define TX_10M_PS_EN (1 << 7)
f162a5d1
FR		 450 DBG_REG = 0xd1,
451#define FIX_NAK_1 (1 << 4)
452#define FIX_NAK_2 (1 << 3)
5a5e4443
HW		 453 TWSI = 0xd2,
454 MCU = 0xd3,
4f6b00e5 455#define NOW_IS_OOB (1 << 7)
c558386b
HW		 456#define TX_EMPTY (1 << 5)
457#define RX_EMPTY (1 << 4)
458#define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
5a5e4443
HW		 459#define EN_NDP (1 << 3)
460#define EN_OOB_RESET (1 << 2)
c558386b 461#define LINK_LIST_RDY (1 << 1)
daf9df6d 462 EFUSEAR = 0xdc,
463#define EFUSEAR_FLAG 0x80000000
464#define EFUSEAR_WRITE_CMD 0x80000000
465#define EFUSEAR_READ_CMD 0x00000000
466#define EFUSEAR_REG_MASK 0x03ff
467#define EFUSEAR_REG_SHIFT 8
468#define EFUSEAR_DATA_MASK 0xff
6e1d0b89
CHL		 469 MISC_1 = 0xf2,
470#define PFM_D3COLD_EN (1 << 6)
f162a5d1
FR		 471};
472
c0e45c1c 473enum rtl8168_registers {
4f6b00e5
HW		 474 LED_FREQ = 0x1a,
475 EEE_LED = 0x1b,
b646d900 476 ERIDR = 0x70,
477 ERIAR = 0x74,
478#define ERIAR_FLAG 0x80000000
479#define ERIAR_WRITE_CMD 0x80000000
480#define ERIAR_READ_CMD 0x00000000
481#define ERIAR_ADDR_BYTE_ALIGN 4
b646d900 482#define ERIAR_TYPE_SHIFT 16
4f6b00e5
HW		 483#define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
484#define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
485#define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
935e2218 486#define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT)
4f6b00e5
HW		 487#define ERIAR_MASK_SHIFT 12
488#define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
489#define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
6e1d0b89 490#define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT)
c558386b 491#define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
4f6b00e5 492#define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
c0e45c1c 493 EPHY_RXER_NUM = 0x7c,
494 OCPDR = 0xb0, /* OCP GPHY access */
495#define OCPDR_WRITE_CMD 0x80000000
496#define OCPDR_READ_CMD 0x00000000
497#define OCPDR_REG_MASK 0x7f
498#define OCPDR_GPHY_REG_SHIFT 16
499#define OCPDR_DATA_MASK 0xffff
500 OCPAR = 0xb4,
501#define OCPAR_FLAG 0x80000000
502#define OCPAR_GPHY_WRITE_CMD 0x8000f060
503#define OCPAR_GPHY_READ_CMD 0x0000f060
c558386b 504 GPHY_OCP = 0xb8,
01dc7fec 505 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
506 MISC = 0xf0, /* 8168e only. */
cecb5fd7 507#define TXPLA_RST (1 << 29)
5598bfe5 508#define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
4f6b00e5 509#define PWM_EN (1 << 22)
c558386b 510#define RXDV_GATED_EN (1 << 19)
5598bfe5 511#define EARLY_TALLY_EN (1 << 16)
c0e45c1c 512};
513
07d3f51f 514enum rtl_register_content {
1da177e4 515 /* InterruptStatusBits */
07d3f51f
FR		 516 SYSErr = 0x8000,
517 PCSTimeout = 0x4000,
518 SWInt = 0x0100,
519 TxDescUnavail = 0x0080,
520 RxFIFOOver = 0x0040,
521 LinkChg = 0x0020,
522 RxOverflow = 0x0010,
523 TxErr = 0x0008,
524 TxOK = 0x0004,
525 RxErr = 0x0002,
526 RxOK = 0x0001,
1da177e4
LT		 527
528 /* RxStatusDesc */
e03f33af 529 RxBOVF = (1 << 24),
9dccf611
FR		 530 RxFOVF = (1 << 23),
531 RxRWT = (1 << 22),
532 RxRES = (1 << 21),
533 RxRUNT = (1 << 20),
534 RxCRC = (1 << 19),
1da177e4
LT		 535
536 /* ChipCmdBits */
4f6b00e5 537 StopReq = 0x80,
07d3f51f
FR		 538 CmdReset = 0x10,
539 CmdRxEnb = 0x08,
540 CmdTxEnb = 0x04,
541 RxBufEmpty = 0x01,
1da177e4 542
275391a4
FR		 543 /* TXPoll register p.5 */
544 HPQ = 0x80, /* Poll cmd on the high prio queue */
545 NPQ = 0x40, /* Poll cmd on the low prio queue */
546 FSWInt = 0x01, /* Forced software interrupt */
547
1da177e4 548 /* Cfg9346Bits */
07d3f51f
FR		 549 Cfg9346_Lock = 0x00,
550 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 551
552 /* rx_mode_bits */
07d3f51f
FR		 553 AcceptErr = 0x20,
554 AcceptRunt = 0x10,
555 AcceptBroadcast = 0x08,
556 AcceptMulticast = 0x04,
557 AcceptMyPhys = 0x02,
558 AcceptAllPhys = 0x01,
1687b566 559#define RX_CONFIG_ACCEPT_MASK 0x3f
1da177e4 560
1da177e4
LT		 561 /* TxConfigBits */
562 TxInterFrameGapShift = 24,
563 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
564
5d06a99f 565 /* Config1 register p.24 */
f162a5d1
FR		 566 LEDS1 = (1 << 7),
567 LEDS0 = (1 << 6),
f162a5d1
FR		 568 Speed_down = (1 << 4),
569 MEMMAP = (1 << 3),
570 IOMAP = (1 << 2),
571 VPD = (1 << 1),
5d06a99f
FR		 572 PMEnable = (1 << 0), /* Power Management Enable */
573
6dccd16b 574 /* Config2 register p. 25 */
57538c4a 575 ClkReqEn = (1 << 7), /* Clock Request Enable */
2ca6cf06 576 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
6dccd16b
FR		 577 PCI_Clock_66MHz = 0x01,
578 PCI_Clock_33MHz = 0x00,
579
61a4dcc2
FR		 580 /* Config3 register p.25 */
581 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
582 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
d58d46b5 583 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
b51ecea8 584 Rdy_to_L23 = (1 << 1), /* L23 Enable */
f162a5d1 585 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
61a4dcc2 586
d58d46b5
FR		 587 /* Config4 register */
588 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
589
5d06a99f 590 /* Config5 register p.27 */
61a4dcc2
FR		 591 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
592 MWF = (1 << 5), /* Accept Multicast wakeup frame */
593 UWF = (1 << 4), /* Accept Unicast wakeup frame */
cecb5fd7 594 Spi_en = (1 << 3),
61a4dcc2 595 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f 596 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
57538c4a 597 ASPM_en = (1 << 0), /* ASPM enable */
5d06a99f 598
1da177e4
LT		 599 /* TBICSR p.28 */
600 TBIReset = 0x80000000,
601 TBILoopback = 0x40000000,
602 TBINwEnable = 0x20000000,
603 TBINwRestart = 0x10000000,
604 TBILinkOk = 0x02000000,
605 TBINwComplete = 0x01000000,
606
607 /* CPlusCmd p.31 */
f162a5d1
FR		 608 EnableBist = (1 << 15), // 8168 8101
609 Mac_dbgo_oe = (1 << 14), // 8168 8101
610 Normal_mode = (1 << 13), // unused
611 Force_half_dup = (1 << 12), // 8168 8101
612 Force_rxflow_en = (1 << 11), // 8168 8101
613 Force_txflow_en = (1 << 10), // 8168 8101
614 Cxpl_dbg_sel = (1 << 9), // 8168 8101
615 ASF = (1 << 8), // 8168 8101
616 PktCntrDisable = (1 << 7), // 8168 8101
617 Mac_dbgo_sel = 0x001c, // 8168
1da177e4
LT		 618 RxVlan = (1 << 6),
619 RxChkSum = (1 << 5),
620 PCIDAC = (1 << 4),
621 PCIMulRW = (1 << 3),
0e485150
FR		 622 INTT_0 = 0x0000, // 8168
623 INTT_1 = 0x0001, // 8168
624 INTT_2 = 0x0002, // 8168
625 INTT_3 = 0x0003, // 8168
1da177e4
LT		 626
627 /* rtl8169_PHYstatus */
07d3f51f
FR		 628 TBI_Enable = 0x80,
629 TxFlowCtrl = 0x40,
630 RxFlowCtrl = 0x20,
631 _1000bpsF = 0x10,
632 _100bps = 0x08,
633 _10bps = 0x04,
634 LinkStatus = 0x02,
635 FullDup = 0x01,
1da177e4 636
1da177e4 637 /* _TBICSRBit */
07d3f51f 638 TBILinkOK = 0x02000000,
d4a3a0fc
SH		 639
640 /* DumpCounterCommand */
07d3f51f 641 CounterDump = 0x8,
6e1d0b89
CHL		 642
643 /* magic enable v2 */
644 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */
1da177e4
LT		 645};
646
2b7b4318
FR		 647enum rtl_desc_bit {
648 /* First doubleword. */
1da177e4
LT		 649 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
650 RingEnd = (1 << 30), /* End of descriptor ring */
651 FirstFrag = (1 << 29), /* First segment of a packet */
652 LastFrag = (1 << 28), /* Final segment of a packet */
2b7b4318
FR		 653};
654
655/* Generic case. */
656enum rtl_tx_desc_bit {
657 /* First doubleword. */
658 TD_LSO = (1 << 27), /* Large Send Offload */
659#define TD_MSS_MAX 0x07ffu /* MSS value */
1da177e4 660
2b7b4318
FR		 661 /* Second doubleword. */
662 TxVlanTag = (1 << 17), /* Add VLAN tag */
663};
664
665/* 8169, 8168b and 810x except 8102e. */
666enum rtl_tx_desc_bit_0 {
667 /* First doubleword. */
668#define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
669 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
670 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
671 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
672};
673
674/* 8102e, 8168c and beyond. */
675enum rtl_tx_desc_bit_1 {
bdfa4ed6 676 /* First doubleword. */
677 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */
e974604b 678 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */
bdfa4ed6 679#define GTTCPHO_SHIFT 18
e974604b 680#define GTTCPHO_MAX 0x7fU
bdfa4ed6 681
2b7b4318 682 /* Second doubleword. */
e974604b 683#define TCPHO_SHIFT 18
684#define TCPHO_MAX 0x3ffU
2b7b4318 685#define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
e974604b 686 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */
687 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */
2b7b4318
FR		 688 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
689 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
690};
1da177e4 691
2b7b4318 692enum rtl_rx_desc_bit {
1da177e4
LT		 693 /* Rx private */
694 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
695 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
696
697#define RxProtoUDP (PID1)
698#define RxProtoTCP (PID0)
699#define RxProtoIP (PID1 | PID0)
700#define RxProtoMask RxProtoIP
701
702 IPFail = (1 << 16), /* IP checksum failed */
703 UDPFail = (1 << 15), /* UDP/IP checksum failed */
704 TCPFail = (1 << 14), /* TCP/IP checksum failed */
705 RxVlanTag = (1 << 16), /* VLAN tag available */
706};
707
708#define RsvdMask 0x3fffc000
709
710struct TxDesc {
6cccd6e7
REB		 711 __le32 opts1;
712 __le32 opts2;
713 __le64 addr;
1da177e4
LT		 714};
715
716struct RxDesc {
6cccd6e7
REB		 717 __le32 opts1;
718 __le32 opts2;
719 __le64 addr;
1da177e4
LT		 720};
721
722struct ring_info {
723 struct sk_buff *skb;
724 u32 len;
725 u8 __pad[sizeof(void *) - sizeof(u32)];
726};
727
f23e7fda 728enum features {
ccdffb9a
FR		 729 RTL_FEATURE_WOL = (1 << 0),
730 RTL_FEATURE_MSI = (1 << 1),
731 RTL_FEATURE_GMII = (1 << 2),
f23e7fda
FR		 732};
733
355423d0
IV		 734struct rtl8169_counters {
735 __le64 tx_packets;
736 __le64 rx_packets;
737 __le64 tx_errors;
738 __le32 rx_errors;
739 __le16 rx_missed;
740 __le16 align_errors;
741 __le32 tx_one_collision;
742 __le32 tx_multi_collision;
743 __le64 rx_unicast;
744 __le64 rx_broadcast;
745 __le32 rx_multicast;
746 __le16 tx_aborted;
747 __le16 tx_underun;
748};
749
da78dbff 750enum rtl_flag {
6c4a70c5 751 RTL_FLAG_TASK_ENABLED,
da78dbff
FR		 752 RTL_FLAG_TASK_SLOW_PENDING,
753 RTL_FLAG_TASK_RESET_PENDING,
754 RTL_FLAG_TASK_PHY_PENDING,
755 RTL_FLAG_MAX
756};
757
8027aa24
JW		 758struct rtl8169_stats {
759 u64 packets;
760 u64 bytes;
761 struct u64_stats_sync syncp;
762};
763
1da177e4
LT		 764struct rtl8169_private {
765 void __iomem *mmio_addr; /* memory map physical address */
cecb5fd7 766 struct pci_dev *pci_dev;
c4028958 767 struct net_device *dev;
bea3348e 768 struct napi_struct napi;
b57b7e5a 769 u32 msg_enable;
2b7b4318
FR		 770 u16 txd_version;
771 u16 mac_version;
1da177e4
LT		 772 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
773 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
1da177e4 774 u32 dirty_tx;
8027aa24
JW		 775 struct rtl8169_stats rx_stats;
776 struct rtl8169_stats tx_stats;
1da177e4
LT		 777 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
778 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
779 dma_addr_t TxPhyAddr;
780 dma_addr_t RxPhyAddr;
6f0333b8 781 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
1da177e4 782 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
1da177e4
LT		 783 struct timer_list timer;
784 u16 cp_cmd;
da78dbff
FR		 785
786 u16 event_slow;
c0e45c1c 787
788 struct mdio_ops {
24192210
FR		 789 void (*write)(struct rtl8169_private *, int, int);
790 int (*read)(struct rtl8169_private *, int);
c0e45c1c 791 } mdio_ops;
792
065c27c1 793 struct pll_power_ops {
794 void (*down)(struct rtl8169_private *);
795 void (*up)(struct rtl8169_private *);
796 } pll_power_ops;
797
d58d46b5
FR		 798 struct jumbo_ops {
799 void (*enable)(struct rtl8169_private *);
800 void (*disable)(struct rtl8169_private *);
801 } jumbo_ops;
802
beb1fe18 803 struct csi_ops {
52989f0e
FR		 804 void (*write)(struct rtl8169_private *, int, int);
805 u32 (*read)(struct rtl8169_private *, int);
beb1fe18
HW		 806 } csi_ops;
807
54405cde 808 int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
ccdffb9a 809 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
4da19633 810 void (*phy_reset_enable)(struct rtl8169_private *tp);
07ce4064 811 void (*hw_start)(struct net_device *);
4da19633 812 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
1da177e4 813 unsigned int (*link_ok)(void __iomem *);
8b4ab28d 814 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
5888d3fc 815 bool (*tso_csum)(struct rtl8169_private *, struct sk_buff *, u32 *);
4422bcd4
FR		 816
817 struct {
da78dbff
FR		 818 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
819 struct mutex mutex;
4422bcd4
FR		 820 struct work_struct work;
821 } wk;
822
f23e7fda 823 unsigned features;
ccdffb9a
FR		 824
825 struct mii_if_info mii;
355423d0 826 struct rtl8169_counters counters;
e1759441 827 u32 saved_wolopts;
e03f33af 828 u32 opts1_mask;
f1e02ed1 829
b6ffd97f
FR		 830 struct rtl_fw {
831 const struct firmware *fw;
1c361efb
FR		 832
833#define RTL_VER_SIZE 32
834
835 char version[RTL_VER_SIZE];
836
837 struct rtl_fw_phy_action {
838 __le32 *code;
839 size_t size;
840 } phy_action;
b6ffd97f 841 } *rtl_fw;
497888cf 842#define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
c558386b
HW		 843
844 u32 ocp_base;
1da177e4
LT		 845};
846
979b6c13 847MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 848MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 849module_param(use_dac, int, 0);
4300e8c7 850MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 851module_param_named(debug, debug.msg_enable, int, 0);
852MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 853MODULE_LICENSE("GPL");
854MODULE_VERSION(RTL8169_VERSION);
bca03d5f 855MODULE_FIRMWARE(FIRMWARE_8168D_1);
856MODULE_FIRMWARE(FIRMWARE_8168D_2);
01dc7fec 857MODULE_FIRMWARE(FIRMWARE_8168E_1);
858MODULE_FIRMWARE(FIRMWARE_8168E_2);
bbb8af75 859MODULE_FIRMWARE(FIRMWARE_8168E_3);
5a5e4443 860MODULE_FIRMWARE(FIRMWARE_8105E_1);
c2218925
HW		 861MODULE_FIRMWARE(FIRMWARE_8168F_1);
862MODULE_FIRMWARE(FIRMWARE_8168F_2);
7e18dca1 863MODULE_FIRMWARE(FIRMWARE_8402_1);
b3d7b2f2 864MODULE_FIRMWARE(FIRMWARE_8411_1);
45dd95c4 865MODULE_FIRMWARE(FIRMWARE_8411_2);
5598bfe5 866MODULE_FIRMWARE(FIRMWARE_8106E_1);
58152cd4 867MODULE_FIRMWARE(FIRMWARE_8106E_2);
beb330a4 868MODULE_FIRMWARE(FIRMWARE_8168G_2);
57538c4a 869MODULE_FIRMWARE(FIRMWARE_8168G_3);
6e1d0b89
CHL		 870MODULE_FIRMWARE(FIRMWARE_8168H_1);
871MODULE_FIRMWARE(FIRMWARE_8168H_2);
a3bf5c42
FR		 872MODULE_FIRMWARE(FIRMWARE_8107E_1);
873MODULE_FIRMWARE(FIRMWARE_8107E_2);
1da177e4 874
da78dbff
FR		 875static void rtl_lock_work(struct rtl8169_private *tp)
876{
877 mutex_lock(&tp->wk.mutex);
878}
879
880static void rtl_unlock_work(struct rtl8169_private *tp)
881{
882 mutex_unlock(&tp->wk.mutex);
883}
884
d58d46b5
FR		 885static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
886{
7d7903b2
JL		 887 pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL,
888 PCI_EXP_DEVCTL_READRQ, force);
d58d46b5
FR		 889}
890
ffc46952
FR		 891struct rtl_cond {
892 bool (*check)(struct rtl8169_private *);
893 const char *msg;
894};
895
896static void rtl_udelay(unsigned int d)
897{
898 udelay(d);
899}
900
901static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
902 void (*delay)(unsigned int), unsigned int d, int n,
903 bool high)
904{
905 int i;
906
907 for (i = 0; i < n; i++) {
908 delay(d);
909 if (c->check(tp) == high)
910 return true;
911 }
82e316ef
FR		 912 netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
913 c->msg, !high, n, d);
ffc46952
FR		 914 return false;
915}
916
917static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
918 const struct rtl_cond *c,
919 unsigned int d, int n)
920{
921 return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
922}
923
924static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
925 const struct rtl_cond *c,
926 unsigned int d, int n)
927{
928 return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
929}
930
931static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
932 const struct rtl_cond *c,
933 unsigned int d, int n)
934{
935 return rtl_loop_wait(tp, c, msleep, d, n, true);
936}
937
938static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
939 const struct rtl_cond *c,
940 unsigned int d, int n)
941{
942 return rtl_loop_wait(tp, c, msleep, d, n, false);
943}
944
945#define DECLARE_RTL_COND(name) \
946static bool name ## _check(struct rtl8169_private *); \
947 \
948static const struct rtl_cond name = { \
949 .check = name ## _check, \
950 .msg = #name \
951}; \
952 \
953static bool name ## _check(struct rtl8169_private *tp)
954
c558386b
HW		 955static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
956{
957 if (reg & 0xffff0001) {
958 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
959 return true;
960 }
961 return false;
962}
963
964DECLARE_RTL_COND(rtl_ocp_gphy_cond)
965{
966 void __iomem *ioaddr = tp->mmio_addr;
967
968 return RTL_R32(GPHY_OCP) & OCPAR_FLAG;
969}
970
971static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
972{
973 void __iomem *ioaddr = tp->mmio_addr;
974
975 if (rtl_ocp_reg_failure(tp, reg))
976 return;
977
978 RTL_W32(GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
979
980 rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
981}
982
983static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
984{
985 void __iomem *ioaddr = tp->mmio_addr;
986
987 if (rtl_ocp_reg_failure(tp, reg))
988 return 0;
989
990 RTL_W32(GPHY_OCP, reg << 15);
991
992 return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
993 (RTL_R32(GPHY_OCP) & 0xffff) : ~0;
994}
995
c558386b
HW		 996static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
997{
998 void __iomem *ioaddr = tp->mmio_addr;
999
1000 if (rtl_ocp_reg_failure(tp, reg))
1001 return;
1002
1003 RTL_W32(OCPDR, OCPAR_FLAG | (reg << 15) | data);
c558386b
HW		 1004}
1005
1006static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
1007{
1008 void __iomem *ioaddr = tp->mmio_addr;
1009
1010 if (rtl_ocp_reg_failure(tp, reg))
1011 return 0;
1012
1013 RTL_W32(OCPDR, reg << 15);
1014
3a83ad12 1015 return RTL_R32(OCPDR);
c558386b
HW		 1016}
1017
1018#define OCP_STD_PHY_BASE 0xa400
1019
1020static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
1021{
1022 if (reg == 0x1f) {
1023 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
1024 return;
1025 }
1026
1027 if (tp->ocp_base != OCP_STD_PHY_BASE)
1028 reg -= 0x10;
1029
1030 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
1031}
1032
1033static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
1034{
1035 if (tp->ocp_base != OCP_STD_PHY_BASE)
1036 reg -= 0x10;
1037
1038 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
1039}
1040
eee3786f 1041static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
1042{
1043 if (reg == 0x1f) {
1044 tp->ocp_base = value << 4;
1045 return;
1046 }
1047
1048 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
1049}
1050
1051static int mac_mcu_read(struct rtl8169_private *tp, int reg)
1052{
1053 return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
1054}
1055
ffc46952
FR		 1056DECLARE_RTL_COND(rtl_phyar_cond)
1057{
1058 void __iomem *ioaddr = tp->mmio_addr;
1059
1060 return RTL_R32(PHYAR) & 0x80000000;
1061}
1062
24192210 1063static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
1da177e4 1064{
24192210 1065 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 1066
24192210 1067 RTL_W32(PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
1da177e4 1068
ffc46952 1069 rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
024a07ba 1070 /*
81a95f04
TT		 1071 * According to hardware specs a 20us delay is required after write
1072 * complete indication, but before sending next command.
024a07ba 1073 */
81a95f04 1074 udelay(20);
1da177e4
LT		 1075}
1076
24192210 1077static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1da177e4 1078{
24192210 1079 void __iomem *ioaddr = tp->mmio_addr;
ffc46952 1080 int value;
1da177e4 1081
24192210 1082 RTL_W32(PHYAR, 0x0 | (reg & 0x1f) << 16);
1da177e4 1083
ffc46952
FR		 1084 value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
1085 RTL_R32(PHYAR) & 0xffff : ~0;
1086
81a95f04
TT		 1087 /*
1088 * According to hardware specs a 20us delay is required after read
1089 * complete indication, but before sending next command.
1090 */
1091 udelay(20);
1092
1da177e4
LT		 1093 return value;
1094}
1095
935e2218
CHL		 1096DECLARE_RTL_COND(rtl_ocpar_cond)
1097{
1098 void __iomem *ioaddr = tp->mmio_addr;
1099
1100 return RTL_R32(OCPAR) & OCPAR_FLAG;
1101}
1102
24192210 1103static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
c0e45c1c 1104{
24192210 1105 void __iomem *ioaddr = tp->mmio_addr;
c0e45c1c 1106
24192210 1107 RTL_W32(OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
c0e45c1c 1108 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
1109 RTL_W32(EPHY_RXER_NUM, 0);
1110
ffc46952 1111 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
c0e45c1c 1112}
1113
24192210 1114static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
c0e45c1c 1115{
24192210
FR		 1116 r8168dp_1_mdio_access(tp, reg,
1117 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
c0e45c1c 1118}
1119
24192210 1120static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
c0e45c1c 1121{
24192210 1122 void __iomem *ioaddr = tp->mmio_addr;
c0e45c1c 1123
24192210 1124 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
c0e45c1c 1125
1126 mdelay(1);
1127 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
1128 RTL_W32(EPHY_RXER_NUM, 0);
1129
ffc46952
FR		 1130 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
1131 RTL_R32(OCPDR) & OCPDR_DATA_MASK : ~0;
c0e45c1c 1132}
1133
e6de30d6 1134#define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
1135
1136static void r8168dp_2_mdio_start(void __iomem *ioaddr)
1137{
1138 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1139}
1140
1141static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
1142{
1143 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1144}
1145
24192210 1146static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
e6de30d6 1147{
24192210
FR		 1148 void __iomem *ioaddr = tp->mmio_addr;
1149
e6de30d6 1150 r8168dp_2_mdio_start(ioaddr);
1151
24192210 1152 r8169_mdio_write(tp, reg, value);
e6de30d6 1153
1154 r8168dp_2_mdio_stop(ioaddr);
1155}
1156
24192210 1157static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
e6de30d6 1158{
24192210 1159 void __iomem *ioaddr = tp->mmio_addr;
e6de30d6 1160 int value;
1161
1162 r8168dp_2_mdio_start(ioaddr);
1163
24192210 1164 value = r8169_mdio_read(tp, reg);
e6de30d6 1165
1166 r8168dp_2_mdio_stop(ioaddr);
1167
1168 return value;
1169}
1170
4da19633 1171static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
dacf8154 1172{
24192210 1173 tp->mdio_ops.write(tp, location, val);
dacf8154
FR		 1174}
1175
4da19633 1176static int rtl_readphy(struct rtl8169_private *tp, int location)
1177{
24192210 1178 return tp->mdio_ops.read(tp, location);
4da19633 1179}
1180
1181static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1182{
1183 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1184}
1185
76564428 1186static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
daf9df6d 1187{
1188 int val;
1189
4da19633 1190 val = rtl_readphy(tp, reg_addr);
76564428 1191 rtl_writephy(tp, reg_addr, (val & ~m) | p);
daf9df6d 1192}
1193
ccdffb9a
FR		 1194static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1195 int val)
1196{
1197 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 1198
4da19633 1199 rtl_writephy(tp, location, val);
ccdffb9a
FR		 1200}
1201
1202static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1203{
1204 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 1205
4da19633 1206 return rtl_readphy(tp, location);
ccdffb9a
FR		 1207}
1208
ffc46952
FR		 1209DECLARE_RTL_COND(rtl_ephyar_cond)
1210{
1211 void __iomem *ioaddr = tp->mmio_addr;
1212
1213 return RTL_R32(EPHYAR) & EPHYAR_FLAG;
1214}
1215
fdf6fc06 1216static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
dacf8154 1217{
fdf6fc06 1218 void __iomem *ioaddr = tp->mmio_addr;
dacf8154
FR		 1219
1220 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1221 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1222
ffc46952
FR		 1223 rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1224
1225 udelay(10);
dacf8154
FR		 1226}
1227
fdf6fc06 1228static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
dacf8154 1229{
fdf6fc06 1230 void __iomem *ioaddr = tp->mmio_addr;
dacf8154
FR		 1231
1232 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1233
ffc46952
FR		 1234 return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1235 RTL_R32(EPHYAR) & EPHYAR_DATA_MASK : ~0;
dacf8154
FR		 1236}
1237
935e2218
CHL		 1238DECLARE_RTL_COND(rtl_eriar_cond)
1239{
1240 void __iomem *ioaddr = tp->mmio_addr;
1241
1242 return RTL_R32(ERIAR) & ERIAR_FLAG;
1243}
1244
fdf6fc06
FR		 1245static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1246 u32 val, int type)
133ac40a 1247{
fdf6fc06 1248 void __iomem *ioaddr = tp->mmio_addr;
133ac40a
HW		 1249
1250 BUG_ON((addr & 3) || (mask == 0));
1251 RTL_W32(ERIDR, val);
1252 RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1253
ffc46952 1254 rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
133ac40a
HW		 1255}
1256
fdf6fc06 1257static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
133ac40a 1258{
fdf6fc06 1259 void __iomem *ioaddr = tp->mmio_addr;
133ac40a
HW		 1260
1261 RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1262
ffc46952
FR		 1263 return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1264 RTL_R32(ERIDR) : ~0;
133ac40a
HW		 1265}
1266
706123d0 1267static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
fdf6fc06 1268 u32 m, int type)
133ac40a
HW		 1269{
1270 u32 val;
1271
fdf6fc06
FR		 1272 val = rtl_eri_read(tp, addr, type);
1273 rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
133ac40a
HW		 1274}
1275
935e2218
CHL		 1276static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1277{
1278 void __iomem *ioaddr = tp->mmio_addr;
1279
1280 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1281 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1282 RTL_R32(OCPDR) : ~0;
1283}
1284
1285static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1286{
1287 return rtl_eri_read(tp, reg, ERIAR_OOB);
1288}
1289
1290static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1291{
1292 switch (tp->mac_version) {
1293 case RTL_GIGA_MAC_VER_27:
1294 case RTL_GIGA_MAC_VER_28:
1295 case RTL_GIGA_MAC_VER_31:
1296 return r8168dp_ocp_read(tp, mask, reg);
1297 case RTL_GIGA_MAC_VER_49:
1298 case RTL_GIGA_MAC_VER_50:
1299 case RTL_GIGA_MAC_VER_51:
1300 return r8168ep_ocp_read(tp, mask, reg);
1301 default:
1302 BUG();
1303 return ~0;
1304 }
1305}
1306
1307static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1308 u32 data)
1309{
1310 void __iomem *ioaddr = tp->mmio_addr;
1311
1312 RTL_W32(OCPDR, data);
1313 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1314 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1315}
1316
1317static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1318 u32 data)
1319{
1320 rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1321 data, ERIAR_OOB);
1322}
1323
1324static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
1325{
1326 switch (tp->mac_version) {
1327 case RTL_GIGA_MAC_VER_27:
1328 case RTL_GIGA_MAC_VER_28:
1329 case RTL_GIGA_MAC_VER_31:
1330 r8168dp_ocp_write(tp, mask, reg, data);
1331 break;
1332 case RTL_GIGA_MAC_VER_49:
1333 case RTL_GIGA_MAC_VER_50:
1334 case RTL_GIGA_MAC_VER_51:
1335 r8168ep_ocp_write(tp, mask, reg, data);
1336 break;
1337 default:
1338 BUG();
1339 break;
1340 }
1341}
1342
2a9b4d96
CHL		 1343static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
1344{
1345 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd, ERIAR_EXGMAC);
1346
1347 ocp_write(tp, 0x1, 0x30, 0x00000001);
1348}
1349
1350#define OOB_CMD_RESET 0x00
1351#define OOB_CMD_DRIVER_START 0x05
1352#define OOB_CMD_DRIVER_STOP 0x06
1353
1354static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1355{
1356 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1357}
1358
1359DECLARE_RTL_COND(rtl_ocp_read_cond)
1360{
1361 u16 reg;
1362
1363 reg = rtl8168_get_ocp_reg(tp);
1364
1365 return ocp_read(tp, 0x0f, reg) & 0x00000800;
1366}
1367
935e2218 1368DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
2a9b4d96 1369{
935e2218
CHL		 1370 return ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1371}
1372
1373DECLARE_RTL_COND(rtl_ocp_tx_cond)
1374{
1375 void __iomem *ioaddr = tp->mmio_addr;
1376
1377 return RTL_R8(IBISR0) & 0x02;
1378}
2a9b4d96 1379
935e2218
CHL		 1380static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1381{
1382 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
2a9b4d96
CHL		 1383 rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
1384}
1385
935e2218 1386static void rtl8168ep_driver_start(struct rtl8169_private *tp)
2a9b4d96 1387{
935e2218
CHL		 1388 ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1389 ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1390 rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1391}
1392
1393static void rtl8168_driver_start(struct rtl8169_private *tp)
1394{
1395 switch (tp->mac_version) {
1396 case RTL_GIGA_MAC_VER_27:
1397 case RTL_GIGA_MAC_VER_28:
1398 case RTL_GIGA_MAC_VER_31:
1399 rtl8168dp_driver_start(tp);
1400 break;
1401 case RTL_GIGA_MAC_VER_49:
1402 case RTL_GIGA_MAC_VER_50:
1403 case RTL_GIGA_MAC_VER_51:
1404 rtl8168ep_driver_start(tp);
1405 break;
1406 default:
1407 BUG();
1408 break;
1409 }
1410}
2a9b4d96 1411
935e2218
CHL		 1412static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1413{
1414 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
2a9b4d96
CHL		 1415 rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
1416}
1417
935e2218
CHL		 1418static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1419{
1420 void __iomem *ioaddr = tp->mmio_addr;
1421
1422 RTL_W8(IBCR2, RTL_R8(IBCR2) & ~0x01);
1423 rtl_msleep_loop_wait_low(tp, &rtl_ocp_tx_cond, 50, 2000);
1424 RTL_W8(IBISR0, RTL_R8(IBISR0) | 0x20);
1425 RTL_W8(IBCR0, RTL_R8(IBCR0) & ~0x01);
1426 ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1427 ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1428 rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1429}
1430
1431static void rtl8168_driver_stop(struct rtl8169_private *tp)
1432{
1433 switch (tp->mac_version) {
1434 case RTL_GIGA_MAC_VER_27:
1435 case RTL_GIGA_MAC_VER_28:
1436 case RTL_GIGA_MAC_VER_31:
1437 rtl8168dp_driver_stop(tp);
1438 break;
1439 case RTL_GIGA_MAC_VER_49:
1440 case RTL_GIGA_MAC_VER_50:
1441 case RTL_GIGA_MAC_VER_51:
1442 rtl8168ep_driver_stop(tp);
1443 break;
1444 default:
1445 BUG();
1446 break;
1447 }
1448}
1449
1450static int r8168dp_check_dash(struct rtl8169_private *tp)
2a9b4d96
CHL		 1451{
1452 u16 reg = rtl8168_get_ocp_reg(tp);
1453
1454 return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
1455}
1456
935e2218
CHL		 1457static int r8168ep_check_dash(struct rtl8169_private *tp)
1458{
1459 return (ocp_read(tp, 0x0f, 0x128) & 0x00000001) ? 1 : 0;
1460}
1461
1462static int r8168_check_dash(struct rtl8169_private *tp)
1463{
1464 switch (tp->mac_version) {
1465 case RTL_GIGA_MAC_VER_27:
1466 case RTL_GIGA_MAC_VER_28:
1467 case RTL_GIGA_MAC_VER_31:
1468 return r8168dp_check_dash(tp);
1469 case RTL_GIGA_MAC_VER_49:
1470 case RTL_GIGA_MAC_VER_50:
1471 case RTL_GIGA_MAC_VER_51:
1472 return r8168ep_check_dash(tp);
1473 default:
1474 return 0;
1475 }
1476}
1477
c28aa385 1478struct exgmac_reg {
1479 u16 addr;
1480 u16 mask;
1481 u32 val;
1482};
1483
fdf6fc06 1484static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
c28aa385 1485 const struct exgmac_reg *r, int len)
1486{
1487 while (len-- > 0) {
fdf6fc06 1488 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
c28aa385 1489 r++;
1490 }
1491}
1492
ffc46952
FR		 1493DECLARE_RTL_COND(rtl_efusear_cond)
1494{
1495 void __iomem *ioaddr = tp->mmio_addr;
1496
1497 return RTL_R32(EFUSEAR) & EFUSEAR_FLAG;
1498}
1499
fdf6fc06 1500static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
daf9df6d 1501{
fdf6fc06 1502 void __iomem *ioaddr = tp->mmio_addr;
daf9df6d 1503
1504 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1505
ffc46952
FR		 1506 return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1507 RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
daf9df6d 1508}
1509
9085cdfa
FR		 1510static u16 rtl_get_events(struct rtl8169_private *tp)
1511{
1512 void __iomem *ioaddr = tp->mmio_addr;
1513
1514 return RTL_R16(IntrStatus);
1515}
1516
1517static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1518{
1519 void __iomem *ioaddr = tp->mmio_addr;
1520
1521 RTL_W16(IntrStatus, bits);
1522 mmiowb();
1523}
1524
1525static void rtl_irq_disable(struct rtl8169_private *tp)
1526{
1527 void __iomem *ioaddr = tp->mmio_addr;
1528
1529 RTL_W16(IntrMask, 0);
1530 mmiowb();
1531}
1532
3e990ff5
FR		 1533static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1534{
1535 void __iomem *ioaddr = tp->mmio_addr;
1536
1537 RTL_W16(IntrMask, bits);
1538}
1539
da78dbff
FR		 1540#define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1541#define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1542#define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1543
1544static void rtl_irq_enable_all(struct rtl8169_private *tp)
1545{
1546 rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1547}
1548
811fd301 1549static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1da177e4 1550{
811fd301 1551 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 1552
9085cdfa 1553 rtl_irq_disable(tp);
da78dbff 1554 rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
811fd301 1555 RTL_R8(ChipCmd);
1da177e4
LT		 1556}
1557
4da19633 1558static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1da177e4 1559{
4da19633 1560 void __iomem *ioaddr = tp->mmio_addr;
1561
1da177e4
LT		 1562 return RTL_R32(TBICSR) & TBIReset;
1563}
1564
4da19633 1565static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1da177e4 1566{
4da19633 1567 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1da177e4
LT		 1568}
1569
1570static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1571{
1572 return RTL_R32(TBICSR) & TBILinkOk;
1573}
1574
1575static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1576{
1577 return RTL_R8(PHYstatus) & LinkStatus;
1578}
1579
4da19633 1580static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1da177e4 1581{
4da19633 1582 void __iomem *ioaddr = tp->mmio_addr;
1583
1da177e4
LT		 1584 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1585}
1586
4da19633 1587static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1da177e4
LT		 1588{
1589 unsigned int val;
1590
4da19633 1591 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1592 rtl_writephy(tp, MII_BMCR, val & 0xffff);
1da177e4
LT		 1593}
1594
70090424
HW		 1595static void rtl_link_chg_patch(struct rtl8169_private *tp)
1596{
1597 void __iomem *ioaddr = tp->mmio_addr;
1598 struct net_device *dev = tp->dev;
1599
1600 if (!netif_running(dev))
1601 return;
1602
b3d7b2f2
HW		 1603 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1604 tp->mac_version == RTL_GIGA_MAC_VER_38) {
70090424 1605 if (RTL_R8(PHYstatus) & _1000bpsF) {
fdf6fc06
FR		 1606 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1607 ERIAR_EXGMAC);
1608 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1609 ERIAR_EXGMAC);
70090424 1610 } else if (RTL_R8(PHYstatus) & _100bps) {
fdf6fc06
FR		 1611 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1612 ERIAR_EXGMAC);
1613 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1614 ERIAR_EXGMAC);
70090424 1615 } else {
fdf6fc06
FR		 1616 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1617 ERIAR_EXGMAC);
1618 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1619 ERIAR_EXGMAC);
70090424
HW		 1620 }
1621 /* Reset packet filter */
706123d0 1622 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
70090424 1623 ERIAR_EXGMAC);
706123d0 1624 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
70090424 1625 ERIAR_EXGMAC);
c2218925
HW		 1626 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1627 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1628 if (RTL_R8(PHYstatus) & _1000bpsF) {
fdf6fc06
FR		 1629 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1630 ERIAR_EXGMAC);
1631 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1632 ERIAR_EXGMAC);
c2218925 1633 } else {
fdf6fc06
FR		 1634 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1635 ERIAR_EXGMAC);
1636 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1637 ERIAR_EXGMAC);
c2218925 1638 }
7e18dca1
HW		 1639 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1640 if (RTL_R8(PHYstatus) & _10bps) {
fdf6fc06
FR		 1641 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1642 ERIAR_EXGMAC);
1643 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1644 ERIAR_EXGMAC);
7e18dca1 1645 } else {
fdf6fc06
FR		 1646 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1647 ERIAR_EXGMAC);
7e18dca1 1648 }
70090424
HW		 1649 }
1650}
1651
e4fbce74 1652static void __rtl8169_check_link_status(struct net_device *dev,
cecb5fd7
FR		 1653 struct rtl8169_private *tp,
1654 void __iomem *ioaddr, bool pm)
1da177e4 1655{
1da177e4 1656 if (tp->link_ok(ioaddr)) {
70090424 1657 rtl_link_chg_patch(tp);
e1759441 1658 /* This is to cancel a scheduled suspend if there's one. */
e4fbce74
RW		 1659 if (pm)
1660 pm_request_resume(&tp->pci_dev->dev);
1da177e4 1661 netif_carrier_on(dev);
1519e57f
FR		 1662 if (net_ratelimit())
1663 netif_info(tp, ifup, dev, "link up\n");
b57b7e5a 1664 } else {
1da177e4 1665 netif_carrier_off(dev);
bf82c189 1666 netif_info(tp, ifdown, dev, "link down\n");
e4fbce74 1667 if (pm)
10953db8 1668 pm_schedule_suspend(&tp->pci_dev->dev, 5000);
b57b7e5a 1669 }
1da177e4
LT		 1670}
1671
e4fbce74
RW		 1672static void rtl8169_check_link_status(struct net_device *dev,
1673 struct rtl8169_private *tp,
1674 void __iomem *ioaddr)
1675{
1676 __rtl8169_check_link_status(dev, tp, ioaddr, false);
1677}
1678
e1759441
RW		 1679#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1680
1681static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
61a4dcc2 1682{
61a4dcc2
FR		 1683 void __iomem *ioaddr = tp->mmio_addr;
1684 u8 options;
e1759441 1685 u32 wolopts = 0;
61a4dcc2
FR		 1686
1687 options = RTL_R8(Config1);
1688 if (!(options & PMEnable))
e1759441 1689 return 0;
61a4dcc2
FR		 1690
1691 options = RTL_R8(Config3);
1692 if (options & LinkUp)
e1759441 1693 wolopts |= WAKE_PHY;
6e1d0b89 1694 switch (tp->mac_version) {
ac85bcdb
CHL		 1695 case RTL_GIGA_MAC_VER_34:
1696 case RTL_GIGA_MAC_VER_35:
1697 case RTL_GIGA_MAC_VER_36:
1698 case RTL_GIGA_MAC_VER_37:
1699 case RTL_GIGA_MAC_VER_38:
1700 case RTL_GIGA_MAC_VER_40:
1701 case RTL_GIGA_MAC_VER_41:
1702 case RTL_GIGA_MAC_VER_42:
1703 case RTL_GIGA_MAC_VER_43:
1704 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 1705 case RTL_GIGA_MAC_VER_45:
1706 case RTL_GIGA_MAC_VER_46:
ac85bcdb
CHL		 1707 case RTL_GIGA_MAC_VER_47:
1708 case RTL_GIGA_MAC_VER_48:
935e2218
CHL		 1709 case RTL_GIGA_MAC_VER_49:
1710 case RTL_GIGA_MAC_VER_50:
1711 case RTL_GIGA_MAC_VER_51:
6e1d0b89
CHL		 1712 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
1713 wolopts |= WAKE_MAGIC;
1714 break;
1715 default:
1716 if (options & MagicPacket)
1717 wolopts |= WAKE_MAGIC;
1718 break;
1719 }
61a4dcc2
FR		 1720
1721 options = RTL_R8(Config5);
1722 if (options & UWF)
e1759441 1723 wolopts |= WAKE_UCAST;
61a4dcc2 1724 if (options & BWF)
e1759441 1725 wolopts |= WAKE_BCAST;
61a4dcc2 1726 if (options & MWF)
e1759441 1727 wolopts |= WAKE_MCAST;
61a4dcc2 1728
e1759441 1729 return wolopts;
61a4dcc2
FR		 1730}
1731
e1759441 1732static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
61a4dcc2
FR		 1733{
1734 struct rtl8169_private *tp = netdev_priv(dev);
e1759441 1735
da78dbff 1736 rtl_lock_work(tp);
e1759441
RW		 1737
1738 wol->supported = WAKE_ANY;
1739 wol->wolopts = __rtl8169_get_wol(tp);
1740
da78dbff 1741 rtl_unlock_work(tp);
e1759441
RW		 1742}
1743
1744static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1745{
61a4dcc2 1746 void __iomem *ioaddr = tp->mmio_addr;
6e1d0b89 1747 unsigned int i, tmp;
350f7596 1748 static const struct {
61a4dcc2
FR		 1749 u32 opt;
1750 u16 reg;
1751 u8 mask;
1752 } cfg[] = {
61a4dcc2 1753 { WAKE_PHY, Config3, LinkUp },
61a4dcc2
FR		 1754 { WAKE_UCAST, Config5, UWF },
1755 { WAKE_BCAST, Config5, BWF },
1756 { WAKE_MCAST, Config5, MWF },
6e1d0b89
CHL		 1757 { WAKE_ANY, Config5, LanWake },
1758 { WAKE_MAGIC, Config3, MagicPacket }
61a4dcc2 1759 };
851e6022 1760 u8 options;
61a4dcc2 1761
61a4dcc2
FR		 1762 RTL_W8(Cfg9346, Cfg9346_Unlock);
1763
6e1d0b89 1764 switch (tp->mac_version) {
ac85bcdb
CHL		 1765 case RTL_GIGA_MAC_VER_34:
1766 case RTL_GIGA_MAC_VER_35:
1767 case RTL_GIGA_MAC_VER_36:
1768 case RTL_GIGA_MAC_VER_37:
1769 case RTL_GIGA_MAC_VER_38:
1770 case RTL_GIGA_MAC_VER_40:
1771 case RTL_GIGA_MAC_VER_41:
1772 case RTL_GIGA_MAC_VER_42:
1773 case RTL_GIGA_MAC_VER_43:
1774 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 1775 case RTL_GIGA_MAC_VER_45:
1776 case RTL_GIGA_MAC_VER_46:
ac85bcdb
CHL		 1777 case RTL_GIGA_MAC_VER_47:
1778 case RTL_GIGA_MAC_VER_48:
935e2218
CHL		 1779 case RTL_GIGA_MAC_VER_49:
1780 case RTL_GIGA_MAC_VER_50:
1781 case RTL_GIGA_MAC_VER_51:
6e1d0b89
CHL		 1782 tmp = ARRAY_SIZE(cfg) - 1;
1783 if (wolopts & WAKE_MAGIC)
706123d0 1784 rtl_w0w1_eri(tp,
6e1d0b89
CHL		 1785 0x0dc,
1786 ERIAR_MASK_0100,
1787 MagicPacket_v2,
1788 0x0000,
1789 ERIAR_EXGMAC);
1790 else
706123d0 1791 rtl_w0w1_eri(tp,
6e1d0b89
CHL		 1792 0x0dc,
1793 ERIAR_MASK_0100,
1794 0x0000,
1795 MagicPacket_v2,
1796 ERIAR_EXGMAC);
1797 break;
1798 default:
1799 tmp = ARRAY_SIZE(cfg);
1800 break;
1801 }
1802
1803 for (i = 0; i < tmp; i++) {
851e6022 1804 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
e1759441 1805 if (wolopts & cfg[i].opt)
61a4dcc2
FR		 1806 options |= cfg[i].mask;
1807 RTL_W8(cfg[i].reg, options);
1808 }
1809
851e6022
FR		 1810 switch (tp->mac_version) {
1811 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1812 options = RTL_R8(Config1) & ~PMEnable;
1813 if (wolopts)
1814 options |= PMEnable;
1815 RTL_W8(Config1, options);
1816 break;
1817 default:
d387b427
FR		 1818 options = RTL_R8(Config2) & ~PME_SIGNAL;
1819 if (wolopts)
1820 options |= PME_SIGNAL;
1821 RTL_W8(Config2, options);
851e6022
FR		 1822 break;
1823 }
1824
61a4dcc2 1825 RTL_W8(Cfg9346, Cfg9346_Lock);
e1759441
RW		 1826}
1827
1828static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1829{
1830 struct rtl8169_private *tp = netdev_priv(dev);
1831
da78dbff 1832 rtl_lock_work(tp);
61a4dcc2 1833
f23e7fda
FR		 1834 if (wol->wolopts)
1835 tp->features |= RTL_FEATURE_WOL;
1836 else
1837 tp->features &= ~RTL_FEATURE_WOL;
e1759441 1838 __rtl8169_set_wol(tp, wol->wolopts);
da78dbff
FR		 1839
1840 rtl_unlock_work(tp);
61a4dcc2 1841
ea80907f 1842 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1843
61a4dcc2
FR		 1844 return 0;
1845}
1846
31bd204f
FR		 1847static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1848{
85bffe6c 1849 return rtl_chip_infos[tp->mac_version].fw_name;
31bd204f
FR		 1850}
1851
1da177e4
LT		 1852static void rtl8169_get_drvinfo(struct net_device *dev,
1853 struct ethtool_drvinfo *info)
1854{
1855 struct rtl8169_private *tp = netdev_priv(dev);
b6ffd97f 1856 struct rtl_fw *rtl_fw = tp->rtl_fw;
1da177e4 1857
68aad78c
RJ		 1858 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1859 strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1860 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1c361efb 1861 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
8ac72d16
RJ		 1862 if (!IS_ERR_OR_NULL(rtl_fw))
1863 strlcpy(info->fw_version, rtl_fw->version,
1864 sizeof(info->fw_version));
1da177e4
LT		 1865}
1866
1867static int rtl8169_get_regs_len(struct net_device *dev)
1868{
1869 return R8169_REGS_SIZE;
1870}
1871
1872static int rtl8169_set_speed_tbi(struct net_device *dev,
54405cde 1873 u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1da177e4
LT		 1874{
1875 struct rtl8169_private *tp = netdev_priv(dev);
1876 void __iomem *ioaddr = tp->mmio_addr;
1877 int ret = 0;
1878 u32 reg;
1879
1880 reg = RTL_R32(TBICSR);
1881 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1882 (duplex == DUPLEX_FULL)) {
1883 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1884 } else if (autoneg == AUTONEG_ENABLE)
1885 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1886 else {
bf82c189
JP		 1887 netif_warn(tp, link, dev,
1888 "incorrect speed setting refused in TBI mode\n");
1da177e4
LT		 1889 ret = -EOPNOTSUPP;
1890 }
1891
1892 return ret;
1893}
1894
1895static int rtl8169_set_speed_xmii(struct net_device *dev,
54405cde 1896 u8 autoneg, u16 speed, u8 duplex, u32 adv)
1da177e4
LT		 1897{
1898 struct rtl8169_private *tp = netdev_priv(dev);
3577aa1b 1899 int giga_ctrl, bmcr;
54405cde 1900 int rc = -EINVAL;
1da177e4 1901
716b50a3 1902 rtl_writephy(tp, 0x1f, 0x0000);
1da177e4
LT		 1903
1904 if (autoneg == AUTONEG_ENABLE) {
3577aa1b 1905 int auto_nego;
1906
4da19633 1907 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
54405cde
ON		 1908 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1909 ADVERTISE_100HALF | ADVERTISE_100FULL);
1910
1911 if (adv & ADVERTISED_10baseT_Half)
1912 auto_nego |= ADVERTISE_10HALF;
1913 if (adv & ADVERTISED_10baseT_Full)
1914 auto_nego |= ADVERTISE_10FULL;
1915 if (adv & ADVERTISED_100baseT_Half)
1916 auto_nego |= ADVERTISE_100HALF;
1917 if (adv & ADVERTISED_100baseT_Full)
1918 auto_nego |= ADVERTISE_100FULL;
1919
3577aa1b 1920 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1da177e4 1921
4da19633 1922 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
3577aa1b 1923 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
bcf0bf90 1924
3577aa1b 1925 /* The 8100e/8101e/8102e do Fast Ethernet only. */
826e6cbd 1926 if (tp->mii.supports_gmii) {
54405cde
ON		 1927 if (adv & ADVERTISED_1000baseT_Half)
1928 giga_ctrl |= ADVERTISE_1000HALF;
1929 if (adv & ADVERTISED_1000baseT_Full)
1930 giga_ctrl |= ADVERTISE_1000FULL;
1931 } else if (adv & (ADVERTISED_1000baseT_Half |
1932 ADVERTISED_1000baseT_Full)) {
bf82c189
JP		 1933 netif_info(tp, link, dev,
1934 "PHY does not support 1000Mbps\n");
54405cde 1935 goto out;
bcf0bf90 1936 }
1da177e4 1937
3577aa1b 1938 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1939
4da19633 1940 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1941 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
3577aa1b 1942 } else {
1943 giga_ctrl = 0;
1944
1945 if (speed == SPEED_10)
1946 bmcr = 0;
1947 else if (speed == SPEED_100)
1948 bmcr = BMCR_SPEED100;
1949 else
54405cde 1950 goto out;
3577aa1b 1951
1952 if (duplex == DUPLEX_FULL)
1953 bmcr |= BMCR_FULLDPLX;
2584fbc3
RS		 1954 }
1955
4da19633 1956 rtl_writephy(tp, MII_BMCR, bmcr);
3577aa1b 1957
cecb5fd7
FR		 1958 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1959 tp->mac_version == RTL_GIGA_MAC_VER_03) {
3577aa1b 1960 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
4da19633 1961 rtl_writephy(tp, 0x17, 0x2138);
1962 rtl_writephy(tp, 0x0e, 0x0260);
3577aa1b 1963 } else {
4da19633 1964 rtl_writephy(tp, 0x17, 0x2108);
1965 rtl_writephy(tp, 0x0e, 0x0000);
3577aa1b 1966 }
1967 }
1968
54405cde
ON		 1969 rc = 0;
1970out:
1971 return rc;
1da177e4
LT		 1972}
1973
1974static int rtl8169_set_speed(struct net_device *dev,
54405cde 1975 u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1da177e4
LT		 1976{
1977 struct rtl8169_private *tp = netdev_priv(dev);
1978 int ret;
1979
54405cde 1980 ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
4876cc1e
FR		 1981 if (ret < 0)
1982 goto out;
1da177e4 1983
4876cc1e
FR		 1984 if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1985 (advertising & ADVERTISED_1000baseT_Full)) {
1da177e4 1986 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
4876cc1e
FR		 1987 }
1988out:
1da177e4
LT		 1989 return ret;
1990}
1991
1992static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1993{
1994 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4
LT		 1995 int ret;
1996
4876cc1e
FR		 1997 del_timer_sync(&tp->timer);
1998
da78dbff 1999 rtl_lock_work(tp);
cecb5fd7 2000 ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
25db0338 2001 cmd->duplex, cmd->advertising);
da78dbff 2002 rtl_unlock_work(tp);
5b0384f4 2003
1da177e4
LT		 2004 return ret;
2005}
2006
c8f44aff
MM		 2007static netdev_features_t rtl8169_fix_features(struct net_device *dev,
2008 netdev_features_t features)
1da177e4 2009{
d58d46b5
FR		 2010 struct rtl8169_private *tp = netdev_priv(dev);
2011
2b7b4318 2012 if (dev->mtu > TD_MSS_MAX)
350fb32a 2013 features &= ~NETIF_F_ALL_TSO;
1da177e4 2014
d58d46b5
FR		 2015 if (dev->mtu > JUMBO_1K &&
2016 !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
2017 features &= ~NETIF_F_IP_CSUM;
2018
350fb32a 2019 return features;
1da177e4
LT		 2020}
2021
da78dbff
FR		 2022static void __rtl8169_set_features(struct net_device *dev,
2023 netdev_features_t features)
1da177e4
LT		 2024{
2025 struct rtl8169_private *tp = netdev_priv(dev);
da78dbff 2026 void __iomem *ioaddr = tp->mmio_addr;
929a031d 2027 u32 rx_config;
1da177e4 2028
929a031d 2029 rx_config = RTL_R32(RxConfig);
2030 if (features & NETIF_F_RXALL)
2031 rx_config |= (AcceptErr | AcceptRunt);
2032 else
2033 rx_config &= ~(AcceptErr | AcceptRunt);
1da177e4 2034
929a031d 2035 RTL_W32(RxConfig, rx_config);
350fb32a 2036
929a031d 2037 if (features & NETIF_F_RXCSUM)
2038 tp->cp_cmd |= RxChkSum;
2039 else
2040 tp->cp_cmd &= ~RxChkSum;
6bbe021d 2041
929a031d 2042 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2043 tp->cp_cmd |= RxVlan;
2044 else
2045 tp->cp_cmd &= ~RxVlan;
2046
2047 tp->cp_cmd |= RTL_R16(CPlusCmd) & ~(RxVlan | RxChkSum);
2048
2049 RTL_W16(CPlusCmd, tp->cp_cmd);
2050 RTL_R16(CPlusCmd);
da78dbff 2051}
1da177e4 2052
da78dbff
FR		 2053static int rtl8169_set_features(struct net_device *dev,
2054 netdev_features_t features)
2055{
2056 struct rtl8169_private *tp = netdev_priv(dev);
2057
929a031d 2058 features &= NETIF_F_RXALL | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX;
2059
da78dbff 2060 rtl_lock_work(tp);
85911d71 2061 if (features ^ dev->features)
929a031d 2062 __rtl8169_set_features(dev, features);
da78dbff 2063 rtl_unlock_work(tp);
1da177e4
LT		 2064
2065 return 0;
2066}
2067
da78dbff 2068
810f4893 2069static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1da177e4 2070{
eab6d18d 2071 return (vlan_tx_tag_present(skb)) ?
1da177e4
LT		 2072 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
2073}
2074
7a8fc77b 2075static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1da177e4
LT		 2076{
2077 u32 opts2 = le32_to_cpu(desc->opts2);
1da177e4 2078
7a8fc77b 2079 if (opts2 & RxVlanTag)
86a9bad3 2080 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1da177e4
LT		 2081}
2082
ccdffb9a 2083static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 2084{
2085 struct rtl8169_private *tp = netdev_priv(dev);
2086 void __iomem *ioaddr = tp->mmio_addr;
2087 u32 status;
2088
2089 cmd->supported =
2090 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
2091 cmd->port = PORT_FIBRE;
2092 cmd->transceiver = XCVR_INTERNAL;
2093
2094 status = RTL_R32(TBICSR);
2095 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
2096 cmd->autoneg = !!(status & TBINwEnable);
2097
70739497 2098 ethtool_cmd_speed_set(cmd, SPEED_1000);
1da177e4 2099 cmd->duplex = DUPLEX_FULL; /* Always set */
ccdffb9a
FR		 2100
2101 return 0;
1da177e4
LT		 2102}
2103
ccdffb9a 2104static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 2105{
2106 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a
FR		 2107
2108 return mii_ethtool_gset(&tp->mii, cmd);
1da177e4
LT		 2109}
2110
2111static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2112{
2113 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 2114 int rc;
1da177e4 2115
da78dbff 2116 rtl_lock_work(tp);
ccdffb9a 2117 rc = tp->get_settings(dev, cmd);
da78dbff 2118 rtl_unlock_work(tp);
1da177e4 2119
ccdffb9a 2120 return rc;
1da177e4
LT		 2121}
2122
2123static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2124 void *p)
2125{
5b0384f4 2126 struct rtl8169_private *tp = netdev_priv(dev);
15edae91
PW		 2127 u32 __iomem *data = tp->mmio_addr;
2128 u32 *dw = p;
2129 int i;
1da177e4 2130
da78dbff 2131 rtl_lock_work(tp);
15edae91
PW		 2132 for (i = 0; i < R8169_REGS_SIZE; i += 4)
2133 memcpy_fromio(dw++, data++, 4);
da78dbff 2134 rtl_unlock_work(tp);
1da177e4
LT		 2135}
2136
b57b7e5a
SH		 2137static u32 rtl8169_get_msglevel(struct net_device *dev)
2138{
2139 struct rtl8169_private *tp = netdev_priv(dev);
2140
2141 return tp->msg_enable;
2142}
2143
2144static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
2145{
2146 struct rtl8169_private *tp = netdev_priv(dev);
2147
2148 tp->msg_enable = value;
2149}
2150
d4a3a0fc
SH		 2151static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
2152 "tx_packets",
2153 "rx_packets",
2154 "tx_errors",
2155 "rx_errors",
2156 "rx_missed",
2157 "align_errors",
2158 "tx_single_collisions",
2159 "tx_multi_collisions",
2160 "unicast",
2161 "broadcast",
2162 "multicast",
2163 "tx_aborted",
2164 "tx_underrun",
2165};
2166
b9f2c044 2167static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 2168{
b9f2c044
JG		 2169 switch (sset) {
2170 case ETH_SS_STATS:
2171 return ARRAY_SIZE(rtl8169_gstrings);
2172 default:
2173 return -EOPNOTSUPP;
2174 }
d4a3a0fc
SH		 2175}
2176
ffc46952
FR		 2177DECLARE_RTL_COND(rtl_counters_cond)
2178{
2179 void __iomem *ioaddr = tp->mmio_addr;
2180
2181 return RTL_R32(CounterAddrLow) & CounterDump;
2182}
2183
355423d0 2184static void rtl8169_update_counters(struct net_device *dev)
d4a3a0fc
SH		 2185{
2186 struct rtl8169_private *tp = netdev_priv(dev);
2187 void __iomem *ioaddr = tp->mmio_addr;
cecb5fd7 2188 struct device *d = &tp->pci_dev->dev;
d4a3a0fc
SH		 2189 struct rtl8169_counters *counters;
2190 dma_addr_t paddr;
2191 u32 cmd;
2192
355423d0
IV		 2193 /*
2194 * Some chips are unable to dump tally counters when the receiver
2195 * is disabled.
2196 */
2197 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
2198 return;
d4a3a0fc 2199
48addcc9 2200 counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
d4a3a0fc
SH		 2201 if (!counters)
2202 return;
2203
2204 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
284901a9 2205 cmd = (u64)paddr & DMA_BIT_MASK(32);
d4a3a0fc
SH		 2206 RTL_W32(CounterAddrLow, cmd);
2207 RTL_W32(CounterAddrLow, cmd | CounterDump);
2208
ffc46952
FR		 2209 if (rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000))
2210 memcpy(&tp->counters, counters, sizeof(*counters));
d4a3a0fc
SH		 2211
2212 RTL_W32(CounterAddrLow, 0);
2213 RTL_W32(CounterAddrHigh, 0);
2214
48addcc9 2215 dma_free_coherent(d, sizeof(*counters), counters, paddr);
d4a3a0fc
SH		 2216}
2217
355423d0
IV		 2218static void rtl8169_get_ethtool_stats(struct net_device *dev,
2219 struct ethtool_stats *stats, u64 *data)
2220{
2221 struct rtl8169_private *tp = netdev_priv(dev);
2222
2223 ASSERT_RTNL();
2224
2225 rtl8169_update_counters(dev);
2226
2227 data[0] = le64_to_cpu(tp->counters.tx_packets);
2228 data[1] = le64_to_cpu(tp->counters.rx_packets);
2229 data[2] = le64_to_cpu(tp->counters.tx_errors);
2230 data[3] = le32_to_cpu(tp->counters.rx_errors);
2231 data[4] = le16_to_cpu(tp->counters.rx_missed);
2232 data[5] = le16_to_cpu(tp->counters.align_errors);
2233 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
2234 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
2235 data[8] = le64_to_cpu(tp->counters.rx_unicast);
2236 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
2237 data[10] = le32_to_cpu(tp->counters.rx_multicast);
2238 data[11] = le16_to_cpu(tp->counters.tx_aborted);
2239 data[12] = le16_to_cpu(tp->counters.tx_underun);
2240}
2241
d4a3a0fc
SH		 2242static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2243{
2244 switch(stringset) {
2245 case ETH_SS_STATS:
2246 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
2247 break;
2248 }
2249}
2250
7282d491 2251static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 2252 .get_drvinfo = rtl8169_get_drvinfo,
2253 .get_regs_len = rtl8169_get_regs_len,
2254 .get_link = ethtool_op_get_link,
2255 .get_settings = rtl8169_get_settings,
2256 .set_settings = rtl8169_set_settings,
b57b7e5a
SH		 2257 .get_msglevel = rtl8169_get_msglevel,
2258 .set_msglevel = rtl8169_set_msglevel,
1da177e4 2259 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 2260 .get_wol = rtl8169_get_wol,
2261 .set_wol = rtl8169_set_wol,
d4a3a0fc 2262 .get_strings = rtl8169_get_strings,
b9f2c044 2263 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 2264 .get_ethtool_stats = rtl8169_get_ethtool_stats,
e1593bb1 2265 .get_ts_info = ethtool_op_get_ts_info,
1da177e4
LT		 2266};
2267
07d3f51f 2268static void rtl8169_get_mac_version(struct rtl8169_private *tp,
5d320a20 2269 struct net_device *dev, u8 default_version)
1da177e4 2270{
5d320a20 2271 void __iomem *ioaddr = tp->mmio_addr;
0e485150
FR		 2272 /*
2273 * The driver currently handles the 8168Bf and the 8168Be identically
2274 * but they can be identified more specifically through the test below
2275 * if needed:
2276 *
2277 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 2278 *
2279 * Same thing for the 8101Eb and the 8101Ec:
2280 *
2281 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 2282 */
3744100e 2283 static const struct rtl_mac_info {
1da177e4 2284 u32 mask;
e3cf0cc0 2285 u32 val;
1da177e4
LT		 2286 int mac_version;
2287 } mac_info[] = {
935e2218
CHL		 2288 /* 8168EP family. */
2289 { 0x7cf00000, 0x50200000, RTL_GIGA_MAC_VER_51 },
2290 { 0x7cf00000, 0x50100000, RTL_GIGA_MAC_VER_50 },
2291 { 0x7cf00000, 0x50000000, RTL_GIGA_MAC_VER_49 },
2292
6e1d0b89
CHL		 2293 /* 8168H family. */
2294 { 0x7cf00000, 0x54100000, RTL_GIGA_MAC_VER_46 },
2295 { 0x7cf00000, 0x54000000, RTL_GIGA_MAC_VER_45 },
2296
c558386b 2297 /* 8168G family. */
45dd95c4 2298 { 0x7cf00000, 0x5c800000, RTL_GIGA_MAC_VER_44 },
57538c4a 2299 { 0x7cf00000, 0x50900000, RTL_GIGA_MAC_VER_42 },
c558386b
HW		 2300 { 0x7cf00000, 0x4c100000, RTL_GIGA_MAC_VER_41 },
2301 { 0x7cf00000, 0x4c000000, RTL_GIGA_MAC_VER_40 },
2302
c2218925 2303 /* 8168F family. */
b3d7b2f2 2304 { 0x7c800000, 0x48800000, RTL_GIGA_MAC_VER_38 },
c2218925
HW		 2305 { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36 },
2306 { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35 },
2307
01dc7fec 2308 /* 8168E family. */
70090424 2309 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 },
01dc7fec 2310 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 },
2311 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
2312 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
2313
5b538df9 2314 /* 8168D family. */
daf9df6d 2315 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
2316 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
daf9df6d 2317 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
5b538df9 2318
e6de30d6 2319 /* 8168DP family. */
2320 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
2321 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
4804b3b3 2322 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
e6de30d6 2323
ef808d50 2324 /* 8168C family. */
17c99297 2325 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
ef3386f0 2326 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
ef808d50 2327 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
7f3e3d3a 2328 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
e3cf0cc0
FR		 2329 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
2330 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
197ff761 2331 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
6fb07058 2332 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
ef808d50 2333 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
e3cf0cc0
FR		 2334
2335 /* 8168B family. */
2336 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
2337 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
2338 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
2339 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
2340
2341 /* 8101 family. */
5598bfe5
HW		 2342 { 0x7cf00000, 0x44900000, RTL_GIGA_MAC_VER_39 },
2343 { 0x7c800000, 0x44800000, RTL_GIGA_MAC_VER_39 },
7e18dca1 2344 { 0x7c800000, 0x44000000, RTL_GIGA_MAC_VER_37 },
36a0e6c2 2345 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 },
5a5e4443
HW		 2346 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 },
2347 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
2348 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
2857ffb7
FR		 2349 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
2350 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
2351 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
2352 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
2353 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
2354 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
e3cf0cc0 2355 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2857ffb7 2356 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
e3cf0cc0 2357 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2857ffb7
FR		 2358 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
2359 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
e3cf0cc0
FR		 2360 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
2361 /* FIXME: where did these entries come from ? -- FR */
2362 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
2363 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
2364
2365 /* 8110 family. */
2366 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
2367 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
2368 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
2369 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
2370 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
2371 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
2372
f21b75e9
JD		 2373 /* Catch-all */
2374 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
3744100e
FR		 2375 };
2376 const struct rtl_mac_info *p = mac_info;
1da177e4
LT		 2377 u32 reg;
2378
e3cf0cc0
FR		 2379 reg = RTL_R32(TxConfig);
2380 while ((reg & p->mask) != p->val)
1da177e4
LT		 2381 p++;
2382 tp->mac_version = p->mac_version;
5d320a20
FR		 2383
2384 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2385 netif_notice(tp, probe, dev,
2386 "unknown MAC, using family default\n");
2387 tp->mac_version = default_version;
58152cd4 2388 } else if (tp->mac_version == RTL_GIGA_MAC_VER_42) {
2389 tp->mac_version = tp->mii.supports_gmii ?
2390 RTL_GIGA_MAC_VER_42 :
2391 RTL_GIGA_MAC_VER_43;
6e1d0b89
CHL		 2392 } else if (tp->mac_version == RTL_GIGA_MAC_VER_45) {
2393 tp->mac_version = tp->mii.supports_gmii ?
2394 RTL_GIGA_MAC_VER_45 :
2395 RTL_GIGA_MAC_VER_47;
2396 } else if (tp->mac_version == RTL_GIGA_MAC_VER_46) {
2397 tp->mac_version = tp->mii.supports_gmii ?
2398 RTL_GIGA_MAC_VER_46 :
2399 RTL_GIGA_MAC_VER_48;
5d320a20 2400 }
1da177e4
LT		 2401}
2402
2403static void rtl8169_print_mac_version(struct rtl8169_private *tp)
2404{
bcf0bf90 2405 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 2406}
2407
867763c1
FR		 2408struct phy_reg {
2409 u16 reg;
2410 u16 val;
2411};
2412
4da19633 2413static void rtl_writephy_batch(struct rtl8169_private *tp,
2414 const struct phy_reg *regs, int len)
867763c1
FR		 2415{
2416 while (len-- > 0) {
4da19633 2417 rtl_writephy(tp, regs->reg, regs->val);
867763c1
FR		 2418 regs++;
2419 }
2420}
2421
bca03d5f 2422#define PHY_READ 0x00000000
2423#define PHY_DATA_OR 0x10000000
2424#define PHY_DATA_AND 0x20000000
2425#define PHY_BJMPN 0x30000000
eee3786f 2426#define PHY_MDIO_CHG 0x40000000
bca03d5f 2427#define PHY_CLEAR_READCOUNT 0x70000000
2428#define PHY_WRITE 0x80000000
2429#define PHY_READCOUNT_EQ_SKIP 0x90000000
2430#define PHY_COMP_EQ_SKIPN 0xa0000000
2431#define PHY_COMP_NEQ_SKIPN 0xb0000000
2432#define PHY_WRITE_PREVIOUS 0xc0000000
2433#define PHY_SKIPN 0xd0000000
2434#define PHY_DELAY_MS 0xe0000000
bca03d5f 2435
960aee6c
HW		 2436struct fw_info {
2437 u32 magic;
2438 char version[RTL_VER_SIZE];
2439 __le32 fw_start;
2440 __le32 fw_len;
2441 u8 chksum;
2442} __packed;
2443
1c361efb
FR		 2444#define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2445
2446static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
bca03d5f 2447{
b6ffd97f 2448 const struct firmware *fw = rtl_fw->fw;
960aee6c 2449 struct fw_info *fw_info = (struct fw_info *)fw->data;
1c361efb
FR		 2450 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2451 char *version = rtl_fw->version;
2452 bool rc = false;
2453
2454 if (fw->size < FW_OPCODE_SIZE)
2455 goto out;
960aee6c
HW		 2456
2457 if (!fw_info->magic) {
2458 size_t i, size, start;
2459 u8 checksum = 0;
2460
2461 if (fw->size < sizeof(*fw_info))
2462 goto out;
2463
2464 for (i = 0; i < fw->size; i++)
2465 checksum += fw->data[i];
2466 if (checksum != 0)
2467 goto out;
2468
2469 start = le32_to_cpu(fw_info->fw_start);
2470 if (start > fw->size)
2471 goto out;
2472
2473 size = le32_to_cpu(fw_info->fw_len);
2474 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2475 goto out;
2476
2477 memcpy(version, fw_info->version, RTL_VER_SIZE);
2478
2479 pa->code = (__le32 *)(fw->data + start);
2480 pa->size = size;
2481 } else {
1c361efb
FR		 2482 if (fw->size % FW_OPCODE_SIZE)
2483 goto out;
2484
2485 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2486
2487 pa->code = (__le32 *)fw->data;
2488 pa->size = fw->size / FW_OPCODE_SIZE;
2489 }
2490 version[RTL_VER_SIZE - 1] = 0;
2491
2492 rc = true;
2493out:
2494 return rc;
2495}
2496
fd112f2e
FR		 2497static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2498 struct rtl_fw_phy_action *pa)
1c361efb 2499{
fd112f2e 2500 bool rc = false;
1c361efb 2501 size_t index;
bca03d5f 2502
1c361efb
FR		 2503 for (index = 0; index < pa->size; index++) {
2504 u32 action = le32_to_cpu(pa->code[index]);
42b82dc1 2505 u32 regno = (action & 0x0fff0000) >> 16;
bca03d5f 2506
42b82dc1 2507 switch(action & 0xf0000000) {
2508 case PHY_READ:
2509 case PHY_DATA_OR:
2510 case PHY_DATA_AND:
eee3786f 2511 case PHY_MDIO_CHG:
42b82dc1 2512 case PHY_CLEAR_READCOUNT:
2513 case PHY_WRITE:
2514 case PHY_WRITE_PREVIOUS:
2515 case PHY_DELAY_MS:
2516 break;
2517
2518 case PHY_BJMPN:
2519 if (regno > index) {
fd112f2e 2520 netif_err(tp, ifup, tp->dev,
cecb5fd7 2521 "Out of range of firmware\n");
fd112f2e 2522 goto out;
42b82dc1 2523 }
2524 break;
2525 case PHY_READCOUNT_EQ_SKIP:
1c361efb 2526 if (index + 2 >= pa->size) {
fd112f2e 2527 netif_err(tp, ifup, tp->dev,
cecb5fd7 2528 "Out of range of firmware\n");
fd112f2e 2529 goto out;
42b82dc1 2530 }
2531 break;
2532 case PHY_COMP_EQ_SKIPN:
2533 case PHY_COMP_NEQ_SKIPN:
2534 case PHY_SKIPN:
1c361efb 2535 if (index + 1 + regno >= pa->size) {
fd112f2e 2536 netif_err(tp, ifup, tp->dev,
cecb5fd7 2537 "Out of range of firmware\n");
fd112f2e 2538 goto out;
42b82dc1 2539 }
bca03d5f 2540 break;
2541
42b82dc1 2542 default:
fd112f2e 2543 netif_err(tp, ifup, tp->dev,
42b82dc1 2544 "Invalid action 0x%08x\n", action);
fd112f2e 2545 goto out;
bca03d5f 2546 }
2547 }
fd112f2e
FR		 2548 rc = true;
2549out:
2550 return rc;
2551}
bca03d5f 2552
fd112f2e
FR		 2553static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2554{
2555 struct net_device *dev = tp->dev;
2556 int rc = -EINVAL;
2557
2558 if (!rtl_fw_format_ok(tp, rtl_fw)) {
2559 netif_err(tp, ifup, dev, "invalid firwmare\n");
2560 goto out;
2561 }
2562
2563 if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2564 rc = 0;
2565out:
2566 return rc;
2567}
2568
2569static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2570{
2571 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
eee3786f 2572 struct mdio_ops org, *ops = &tp->mdio_ops;
fd112f2e
FR		 2573 u32 predata, count;
2574 size_t index;
2575
2576 predata = count = 0;
eee3786f 2577 org.write = ops->write;
2578 org.read = ops->read;
42b82dc1 2579
1c361efb
FR		 2580 for (index = 0; index < pa->size; ) {
2581 u32 action = le32_to_cpu(pa->code[index]);
bca03d5f 2582 u32 data = action & 0x0000ffff;
42b82dc1 2583 u32 regno = (action & 0x0fff0000) >> 16;
2584
2585 if (!action)
2586 break;
bca03d5f 2587
2588 switch(action & 0xf0000000) {
42b82dc1 2589 case PHY_READ:
2590 predata = rtl_readphy(tp, regno);
2591 count++;
2592 index++;
2593 break;
2594 case PHY_DATA_OR:
2595 predata |= data;
2596 index++;
2597 break;
2598 case PHY_DATA_AND:
2599 predata &= data;
2600 index++;
2601 break;
2602 case PHY_BJMPN:
2603 index -= regno;
2604 break;
eee3786f 2605 case PHY_MDIO_CHG:
2606 if (data == 0) {
2607 ops->write = org.write;
2608 ops->read = org.read;
2609 } else if (data == 1) {
2610 ops->write = mac_mcu_write;
2611 ops->read = mac_mcu_read;
2612 }
2613
42b82dc1 2614 index++;
2615 break;
2616 case PHY_CLEAR_READCOUNT:
2617 count = 0;
2618 index++;
2619 break;
bca03d5f 2620 case PHY_WRITE:
42b82dc1 2621 rtl_writephy(tp, regno, data);
2622 index++;
2623 break;
2624 case PHY_READCOUNT_EQ_SKIP:
cecb5fd7 2625 index += (count == data) ? 2 : 1;
bca03d5f 2626 break;
42b82dc1 2627 case PHY_COMP_EQ_SKIPN:
2628 if (predata == data)
2629 index += regno;
2630 index++;
2631 break;
2632 case PHY_COMP_NEQ_SKIPN:
2633 if (predata != data)
2634 index += regno;
2635 index++;
2636 break;
2637 case PHY_WRITE_PREVIOUS:
2638 rtl_writephy(tp, regno, predata);
2639 index++;
2640 break;
2641 case PHY_SKIPN:
2642 index += regno + 1;
2643 break;
2644 case PHY_DELAY_MS:
2645 mdelay(data);
2646 index++;
2647 break;
2648
bca03d5f 2649 default:
2650 BUG();
2651 }
2652 }
eee3786f 2653
2654 ops->write = org.write;
2655 ops->read = org.read;
bca03d5f 2656}
2657
f1e02ed1 2658static void rtl_release_firmware(struct rtl8169_private *tp)
2659{
b6ffd97f
FR		 2660 if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2661 release_firmware(tp->rtl_fw->fw);
2662 kfree(tp->rtl_fw);
2663 }
2664 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
f1e02ed1 2665}
2666
953a12cc 2667static void rtl_apply_firmware(struct rtl8169_private *tp)
f1e02ed1 2668{
b6ffd97f 2669 struct rtl_fw *rtl_fw = tp->rtl_fw;
f1e02ed1 2670
2671 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
eef63cc1 2672 if (!IS_ERR_OR_NULL(rtl_fw))
b6ffd97f 2673 rtl_phy_write_fw(tp, rtl_fw);
953a12cc
FR		 2674}
2675
2676static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2677{
2678 if (rtl_readphy(tp, reg) != val)
2679 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2680 else
2681 rtl_apply_firmware(tp);
f1e02ed1 2682}
2683
4da19633 2684static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1da177e4 2685{
350f7596 2686 static const struct phy_reg phy_reg_init[] = {
0b9b571d 2687 { 0x1f, 0x0001 },
2688 { 0x06, 0x006e },
2689 { 0x08, 0x0708 },
2690 { 0x15, 0x4000 },
2691 { 0x18, 0x65c7 },
1da177e4 2692
0b9b571d 2693 { 0x1f, 0x0001 },
2694 { 0x03, 0x00a1 },
2695 { 0x02, 0x0008 },
2696 { 0x01, 0x0120 },
2697 { 0x00, 0x1000 },
2698 { 0x04, 0x0800 },
2699 { 0x04, 0x0000 },
1da177e4 2700
0b9b571d 2701 { 0x03, 0xff41 },
2702 { 0x02, 0xdf60 },
2703 { 0x01, 0x0140 },
2704 { 0x00, 0x0077 },
2705 { 0x04, 0x7800 },
2706 { 0x04, 0x7000 },
2707
2708 { 0x03, 0x802f },
2709 { 0x02, 0x4f02 },
2710 { 0x01, 0x0409 },
2711 { 0x00, 0xf0f9 },
2712 { 0x04, 0x9800 },
2713 { 0x04, 0x9000 },
2714
2715 { 0x03, 0xdf01 },
2716 { 0x02, 0xdf20 },
2717 { 0x01, 0xff95 },
2718 { 0x00, 0xba00 },
2719 { 0x04, 0xa800 },
2720 { 0x04, 0xa000 },
2721
2722 { 0x03, 0xff41 },
2723 { 0x02, 0xdf20 },
2724 { 0x01, 0x0140 },
2725 { 0x00, 0x00bb },
2726 { 0x04, 0xb800 },
2727 { 0x04, 0xb000 },
2728
2729 { 0x03, 0xdf41 },
2730 { 0x02, 0xdc60 },
2731 { 0x01, 0x6340 },
2732 { 0x00, 0x007d },
2733 { 0x04, 0xd800 },
2734 { 0x04, 0xd000 },
2735
2736 { 0x03, 0xdf01 },
2737 { 0x02, 0xdf20 },
2738 { 0x01, 0x100a },
2739 { 0x00, 0xa0ff },
2740 { 0x04, 0xf800 },
2741 { 0x04, 0xf000 },
2742
2743 { 0x1f, 0x0000 },
2744 { 0x0b, 0x0000 },
2745 { 0x00, 0x9200 }
2746 };
1da177e4 2747
4da19633 2748 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1da177e4
LT		 2749}
2750
4da19633 2751static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
5615d9f1 2752{
350f7596 2753 static const struct phy_reg phy_reg_init[] = {
a441d7b6
FR		 2754 { 0x1f, 0x0002 },
2755 { 0x01, 0x90d0 },
2756 { 0x1f, 0x0000 }
2757 };
2758
4da19633 2759 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5615d9f1
FR		 2760}
2761
4da19633 2762static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2e955856 2763{
2764 struct pci_dev *pdev = tp->pci_dev;
2e955856 2765
ccbae55e
SS		 2766 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2767 (pdev->subsystem_device != 0xe000))
2e955856 2768 return;
2769
4da19633 2770 rtl_writephy(tp, 0x1f, 0x0001);
2771 rtl_writephy(tp, 0x10, 0xf01b);
2772 rtl_writephy(tp, 0x1f, 0x0000);
2e955856 2773}
2774
4da19633 2775static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2e955856 2776{
350f7596 2777 static const struct phy_reg phy_reg_init[] = {
2e955856 2778 { 0x1f, 0x0001 },
2779 { 0x04, 0x0000 },
2780 { 0x03, 0x00a1 },
2781 { 0x02, 0x0008 },
2782 { 0x01, 0x0120 },
2783 { 0x00, 0x1000 },
2784 { 0x04, 0x0800 },
2785 { 0x04, 0x9000 },
2786 { 0x03, 0x802f },
2787 { 0x02, 0x4f02 },
2788 { 0x01, 0x0409 },
2789 { 0x00, 0xf099 },
2790 { 0x04, 0x9800 },
2791 { 0x04, 0xa000 },
2792 { 0x03, 0xdf01 },
2793 { 0x02, 0xdf20 },
2794 { 0x01, 0xff95 },
2795 { 0x00, 0xba00 },
2796 { 0x04, 0xa800 },
2797 { 0x04, 0xf000 },
2798 { 0x03, 0xdf01 },
2799 { 0x02, 0xdf20 },
2800 { 0x01, 0x101a },
2801 { 0x00, 0xa0ff },
2802 { 0x04, 0xf800 },
2803 { 0x04, 0x0000 },
2804 { 0x1f, 0x0000 },
2805
2806 { 0x1f, 0x0001 },
2807 { 0x10, 0xf41b },
2808 { 0x14, 0xfb54 },
2809 { 0x18, 0xf5c7 },
2810 { 0x1f, 0x0000 },
2811
2812 { 0x1f, 0x0001 },
2813 { 0x17, 0x0cc0 },
2814 { 0x1f, 0x0000 }
2815 };
2816
4da19633 2817 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2e955856 2818
4da19633 2819 rtl8169scd_hw_phy_config_quirk(tp);
2e955856 2820}
2821
4da19633 2822static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
8c7006aa 2823{
350f7596 2824 static const struct phy_reg phy_reg_init[] = {
8c7006aa 2825 { 0x1f, 0x0001 },
2826 { 0x04, 0x0000 },
2827 { 0x03, 0x00a1 },
2828 { 0x02, 0x0008 },
2829 { 0x01, 0x0120 },
2830 { 0x00, 0x1000 },
2831 { 0x04, 0x0800 },
2832 { 0x04, 0x9000 },
2833 { 0x03, 0x802f },
2834 { 0x02, 0x4f02 },
2835 { 0x01, 0x0409 },
2836 { 0x00, 0xf099 },
2837 { 0x04, 0x9800 },
2838 { 0x04, 0xa000 },
2839 { 0x03, 0xdf01 },
2840 { 0x02, 0xdf20 },
2841 { 0x01, 0xff95 },
2842 { 0x00, 0xba00 },
2843 { 0x04, 0xa800 },
2844 { 0x04, 0xf000 },
2845 { 0x03, 0xdf01 },
2846 { 0x02, 0xdf20 },
2847 { 0x01, 0x101a },
2848 { 0x00, 0xa0ff },
2849 { 0x04, 0xf800 },
2850 { 0x04, 0x0000 },
2851 { 0x1f, 0x0000 },
2852
2853 { 0x1f, 0x0001 },
2854 { 0x0b, 0x8480 },
2855 { 0x1f, 0x0000 },
2856
2857 { 0x1f, 0x0001 },
2858 { 0x18, 0x67c7 },
2859 { 0x04, 0x2000 },
2860 { 0x03, 0x002f },
2861 { 0x02, 0x4360 },
2862 { 0x01, 0x0109 },
2863 { 0x00, 0x3022 },
2864 { 0x04, 0x2800 },
2865 { 0x1f, 0x0000 },
2866
2867 { 0x1f, 0x0001 },
2868 { 0x17, 0x0cc0 },
2869 { 0x1f, 0x0000 }
2870 };
2871
4da19633 2872 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
8c7006aa 2873}
2874
4da19633 2875static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
236b8082 2876{
350f7596 2877 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2878 { 0x10, 0xf41b },
2879 { 0x1f, 0x0000 }
2880 };
2881
4da19633 2882 rtl_writephy(tp, 0x1f, 0x0001);
2883 rtl_patchphy(tp, 0x16, 1 << 0);
236b8082 2884
4da19633 2885 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2886}
2887
4da19633 2888static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
236b8082 2889{
350f7596 2890 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2891 { 0x1f, 0x0001 },
2892 { 0x10, 0xf41b },
2893 { 0x1f, 0x0000 }
2894 };
2895
4da19633 2896 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2897}
2898
4da19633 2899static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2900{
350f7596 2901 static const struct phy_reg phy_reg_init[] = {
867763c1
FR		 2902 { 0x1f, 0x0000 },
2903 { 0x1d, 0x0f00 },
2904 { 0x1f, 0x0002 },
2905 { 0x0c, 0x1ec8 },
2906 { 0x1f, 0x0000 }
2907 };
2908
4da19633 2909 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
867763c1
FR		 2910}
2911
4da19633 2912static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
ef3386f0 2913{
350f7596 2914 static const struct phy_reg phy_reg_init[] = {
ef3386f0
FR		 2915 { 0x1f, 0x0001 },
2916 { 0x1d, 0x3d98 },
2917 { 0x1f, 0x0000 }
2918 };
2919
4da19633 2920 rtl_writephy(tp, 0x1f, 0x0000);
2921 rtl_patchphy(tp, 0x14, 1 << 5);
2922 rtl_patchphy(tp, 0x0d, 1 << 5);
ef3386f0 2923
4da19633 2924 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
ef3386f0
FR		 2925}
2926
4da19633 2927static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2928{
350f7596 2929 static const struct phy_reg phy_reg_init[] = {
a3f80671
FR		 2930 { 0x1f, 0x0001 },
2931 { 0x12, 0x2300 },
867763c1
FR		 2932 { 0x1f, 0x0002 },
2933 { 0x00, 0x88d4 },
2934 { 0x01, 0x82b1 },
2935 { 0x03, 0x7002 },
2936 { 0x08, 0x9e30 },
2937 { 0x09, 0x01f0 },
2938 { 0x0a, 0x5500 },
2939 { 0x0c, 0x00c8 },
2940 { 0x1f, 0x0003 },
2941 { 0x12, 0xc096 },
2942 { 0x16, 0x000a },
f50d4275
FR		 2943 { 0x1f, 0x0000 },
2944 { 0x1f, 0x0000 },
2945 { 0x09, 0x2000 },
2946 { 0x09, 0x0000 }
867763c1
FR		 2947 };
2948
4da19633 2949 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2950
4da19633 2951 rtl_patchphy(tp, 0x14, 1 << 5);
2952 rtl_patchphy(tp, 0x0d, 1 << 5);
2953 rtl_writephy(tp, 0x1f, 0x0000);
867763c1
FR		 2954}
2955
4da19633 2956static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
7da97ec9 2957{
350f7596 2958 static const struct phy_reg phy_reg_init[] = {
f50d4275 2959 { 0x1f, 0x0001 },
7da97ec9 2960 { 0x12, 0x2300 },
f50d4275
FR		 2961 { 0x03, 0x802f },
2962 { 0x02, 0x4f02 },
2963 { 0x01, 0x0409 },
2964 { 0x00, 0xf099 },
2965 { 0x04, 0x9800 },
2966 { 0x04, 0x9000 },
2967 { 0x1d, 0x3d98 },
7da97ec9
FR		 2968 { 0x1f, 0x0002 },
2969 { 0x0c, 0x7eb8 },
f50d4275
FR		 2970 { 0x06, 0x0761 },
2971 { 0x1f, 0x0003 },
2972 { 0x16, 0x0f0a },
7da97ec9
FR		 2973 { 0x1f, 0x0000 }
2974 };
2975
4da19633 2976 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2977
4da19633 2978 rtl_patchphy(tp, 0x16, 1 << 0);
2979 rtl_patchphy(tp, 0x14, 1 << 5);
2980 rtl_patchphy(tp, 0x0d, 1 << 5);
2981 rtl_writephy(tp, 0x1f, 0x0000);
7da97ec9
FR		 2982}
2983
4da19633 2984static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
197ff761 2985{
350f7596 2986 static const struct phy_reg phy_reg_init[] = {
197ff761
FR		 2987 { 0x1f, 0x0001 },
2988 { 0x12, 0x2300 },
2989 { 0x1d, 0x3d98 },
2990 { 0x1f, 0x0002 },
2991 { 0x0c, 0x7eb8 },
2992 { 0x06, 0x5461 },
2993 { 0x1f, 0x0003 },
2994 { 0x16, 0x0f0a },
2995 { 0x1f, 0x0000 }
2996 };
2997
4da19633 2998 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
197ff761 2999
4da19633 3000 rtl_patchphy(tp, 0x16, 1 << 0);
3001 rtl_patchphy(tp, 0x14, 1 << 5);
3002 rtl_patchphy(tp, 0x0d, 1 << 5);
3003 rtl_writephy(tp, 0x1f, 0x0000);
197ff761
FR		 3004}
3005
4da19633 3006static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
6fb07058 3007{
4da19633 3008 rtl8168c_3_hw_phy_config(tp);
6fb07058
FR		 3009}
3010
bca03d5f 3011static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
5b538df9 3012{
350f7596 3013 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 3014 /* Channel Estimation */
5b538df9 3015 { 0x1f, 0x0001 },
daf9df6d 3016 { 0x06, 0x4064 },
3017 { 0x07, 0x2863 },
3018 { 0x08, 0x059c },
3019 { 0x09, 0x26b4 },
3020 { 0x0a, 0x6a19 },
3021 { 0x0b, 0xdcc8 },
3022 { 0x10, 0xf06d },
3023 { 0x14, 0x7f68 },
3024 { 0x18, 0x7fd9 },
3025 { 0x1c, 0xf0ff },
3026 { 0x1d, 0x3d9c },
5b538df9 3027 { 0x1f, 0x0003 },
daf9df6d 3028 { 0x12, 0xf49f },
3029 { 0x13, 0x070b },
3030 { 0x1a, 0x05ad },
bca03d5f 3031 { 0x14, 0x94c0 },
3032
3033 /*
3034 * Tx Error Issue
cecb5fd7 3035 * Enhance line driver power
bca03d5f 3036 */
5b538df9 3037 { 0x1f, 0x0002 },
daf9df6d 3038 { 0x06, 0x5561 },
3039 { 0x1f, 0x0005 },
3040 { 0x05, 0x8332 },
bca03d5f 3041 { 0x06, 0x5561 },
3042
3043 /*
3044 * Can not link to 1Gbps with bad cable
3045 * Decrease SNR threshold form 21.07dB to 19.04dB
3046 */
3047 { 0x1f, 0x0001 },
3048 { 0x17, 0x0cc0 },
daf9df6d 3049
5b538df9 3050 { 0x1f, 0x0000 },
bca03d5f 3051 { 0x0d, 0xf880 }
daf9df6d 3052 };
3053
4da19633 3054 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
daf9df6d 3055
bca03d5f 3056 /*
3057 * Rx Error Issue
3058 * Fine Tune Switching regulator parameter
3059 */
4da19633 3060 rtl_writephy(tp, 0x1f, 0x0002);
76564428
CHL		 3061 rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
3062 rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
daf9df6d 3063
fdf6fc06 3064 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
350f7596 3065 static const struct phy_reg phy_reg_init[] = {
daf9df6d 3066 { 0x1f, 0x0002 },
3067 { 0x05, 0x669a },
3068 { 0x1f, 0x0005 },
3069 { 0x05, 0x8330 },
3070 { 0x06, 0x669a },
3071 { 0x1f, 0x0002 }
3072 };
3073 int val;
3074
4da19633 3075 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 3076
4da19633 3077 val = rtl_readphy(tp, 0x0d);
daf9df6d 3078
3079 if ((val & 0x00ff) != 0x006c) {
350f7596 3080 static const u32 set[] = {
daf9df6d 3081 0x0065, 0x0066, 0x0067, 0x0068,
3082 0x0069, 0x006a, 0x006b, 0x006c
3083 };
3084 int i;
3085
4da19633 3086 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 3087
3088 val &= 0xff00;
3089 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 3090 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 3091 }
3092 } else {
350f7596 3093 static const struct phy_reg phy_reg_init[] = {
daf9df6d 3094 { 0x1f, 0x0002 },
3095 { 0x05, 0x6662 },
3096 { 0x1f, 0x0005 },
3097 { 0x05, 0x8330 },
3098 { 0x06, 0x6662 }
3099 };
3100
4da19633 3101 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 3102 }
3103
bca03d5f 3104 /* RSET couple improve */
4da19633 3105 rtl_writephy(tp, 0x1f, 0x0002);
3106 rtl_patchphy(tp, 0x0d, 0x0300);
3107 rtl_patchphy(tp, 0x0f, 0x0010);
daf9df6d 3108
bca03d5f 3109 /* Fine tune PLL performance */
4da19633 3110 rtl_writephy(tp, 0x1f, 0x0002);
76564428
CHL		 3111 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3112 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 3113
4da19633 3114 rtl_writephy(tp, 0x1f, 0x0005);
3115 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 3116
3117 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
bca03d5f 3118
4da19633 3119 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 3120}
3121
bca03d5f 3122static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 3123{
350f7596 3124 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 3125 /* Channel Estimation */
daf9df6d 3126 { 0x1f, 0x0001 },
3127 { 0x06, 0x4064 },
3128 { 0x07, 0x2863 },
3129 { 0x08, 0x059c },
3130 { 0x09, 0x26b4 },
3131 { 0x0a, 0x6a19 },
3132 { 0x0b, 0xdcc8 },
3133 { 0x10, 0xf06d },
3134 { 0x14, 0x7f68 },
3135 { 0x18, 0x7fd9 },
3136 { 0x1c, 0xf0ff },
3137 { 0x1d, 0x3d9c },
3138 { 0x1f, 0x0003 },
3139 { 0x12, 0xf49f },
3140 { 0x13, 0x070b },
3141 { 0x1a, 0x05ad },
3142 { 0x14, 0x94c0 },
3143
bca03d5f 3144 /*
3145 * Tx Error Issue
cecb5fd7 3146 * Enhance line driver power
bca03d5f 3147 */
daf9df6d 3148 { 0x1f, 0x0002 },
3149 { 0x06, 0x5561 },
3150 { 0x1f, 0x0005 },
3151 { 0x05, 0x8332 },
bca03d5f 3152 { 0x06, 0x5561 },
3153
3154 /*
3155 * Can not link to 1Gbps with bad cable
3156 * Decrease SNR threshold form 21.07dB to 19.04dB
3157 */
3158 { 0x1f, 0x0001 },
3159 { 0x17, 0x0cc0 },
daf9df6d 3160
3161 { 0x1f, 0x0000 },
bca03d5f 3162 { 0x0d, 0xf880 }
5b538df9
FR		 3163 };
3164
4da19633 3165 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
5b538df9 3166
fdf6fc06 3167 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
350f7596 3168 static const struct phy_reg phy_reg_init[] = {
daf9df6d 3169 { 0x1f, 0x0002 },
3170 { 0x05, 0x669a },
5b538df9 3171 { 0x1f, 0x0005 },
daf9df6d 3172 { 0x05, 0x8330 },
3173 { 0x06, 0x669a },
3174
3175 { 0x1f, 0x0002 }
3176 };
3177 int val;
3178
4da19633 3179 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 3180
4da19633 3181 val = rtl_readphy(tp, 0x0d);
daf9df6d 3182 if ((val & 0x00ff) != 0x006c) {
b6bc7650 3183 static const u32 set[] = {
daf9df6d 3184 0x0065, 0x0066, 0x0067, 0x0068,
3185 0x0069, 0x006a, 0x006b, 0x006c
3186 };
3187 int i;
3188
4da19633 3189 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 3190
3191 val &= 0xff00;
3192 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 3193 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 3194 }
3195 } else {
350f7596 3196 static const struct phy_reg phy_reg_init[] = {
daf9df6d 3197 { 0x1f, 0x0002 },
3198 { 0x05, 0x2642 },
5b538df9 3199 { 0x1f, 0x0005 },
daf9df6d 3200 { 0x05, 0x8330 },
3201 { 0x06, 0x2642 }
5b538df9
FR		 3202 };
3203
4da19633 3204 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 3205 }
3206
bca03d5f 3207 /* Fine tune PLL performance */
4da19633 3208 rtl_writephy(tp, 0x1f, 0x0002);
76564428
CHL		 3209 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3210 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 3211
bca03d5f 3212 /* Switching regulator Slew rate */
4da19633 3213 rtl_writephy(tp, 0x1f, 0x0002);
3214 rtl_patchphy(tp, 0x0f, 0x0017);
daf9df6d 3215
4da19633 3216 rtl_writephy(tp, 0x1f, 0x0005);
3217 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 3218
3219 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
bca03d5f 3220
4da19633 3221 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 3222}
3223
4da19633 3224static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 3225{
350f7596 3226 static const struct phy_reg phy_reg_init[] = {
daf9df6d 3227 { 0x1f, 0x0002 },
3228 { 0x10, 0x0008 },
3229 { 0x0d, 0x006c },
3230
3231 { 0x1f, 0x0000 },
3232 { 0x0d, 0xf880 },
3233
3234 { 0x1f, 0x0001 },
3235 { 0x17, 0x0cc0 },
3236
3237 { 0x1f, 0x0001 },
3238 { 0x0b, 0xa4d8 },
3239 { 0x09, 0x281c },
3240 { 0x07, 0x2883 },
3241 { 0x0a, 0x6b35 },
3242 { 0x1d, 0x3da4 },
3243 { 0x1c, 0xeffd },
3244 { 0x14, 0x7f52 },
3245 { 0x18, 0x7fc6 },
3246 { 0x08, 0x0601 },
3247 { 0x06, 0x4063 },
3248 { 0x10, 0xf074 },
3249 { 0x1f, 0x0003 },
3250 { 0x13, 0x0789 },
3251 { 0x12, 0xf4bd },
3252 { 0x1a, 0x04fd },
3253 { 0x14, 0x84b0 },
3254 { 0x1f, 0x0000 },
3255 { 0x00, 0x9200 },
3256
3257 { 0x1f, 0x0005 },
3258 { 0x01, 0x0340 },
3259 { 0x1f, 0x0001 },
3260 { 0x04, 0x4000 },
3261 { 0x03, 0x1d21 },
3262 { 0x02, 0x0c32 },
3263 { 0x01, 0x0200 },
3264 { 0x00, 0x5554 },
3265 { 0x04, 0x4800 },
3266 { 0x04, 0x4000 },
3267 { 0x04, 0xf000 },
3268 { 0x03, 0xdf01 },
3269 { 0x02, 0xdf20 },
3270 { 0x01, 0x101a },
3271 { 0x00, 0xa0ff },
3272 { 0x04, 0xf800 },
3273 { 0x04, 0xf000 },
3274 { 0x1f, 0x0000 },
3275
3276 { 0x1f, 0x0007 },
3277 { 0x1e, 0x0023 },
3278 { 0x16, 0x0000 },
3279 { 0x1f, 0x0000 }
3280 };
3281
4da19633 3282 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 3283}
3284
e6de30d6 3285static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3286{
3287 static const struct phy_reg phy_reg_init[] = {
3288 { 0x1f, 0x0001 },
3289 { 0x17, 0x0cc0 },
3290
3291 { 0x1f, 0x0007 },
3292 { 0x1e, 0x002d },
3293 { 0x18, 0x0040 },
3294 { 0x1f, 0x0000 }
3295 };
3296
3297 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3298 rtl_patchphy(tp, 0x0d, 1 << 5);
3299}
3300
70090424 3301static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
01dc7fec 3302{
3303 static const struct phy_reg phy_reg_init[] = {
3304 /* Enable Delay cap */
3305 { 0x1f, 0x0005 },
3306 { 0x05, 0x8b80 },
3307 { 0x06, 0xc896 },
3308 { 0x1f, 0x0000 },
3309
3310 /* Channel estimation fine tune */
3311 { 0x1f, 0x0001 },
3312 { 0x0b, 0x6c20 },
3313 { 0x07, 0x2872 },
3314 { 0x1c, 0xefff },
3315 { 0x1f, 0x0003 },
3316 { 0x14, 0x6420 },
3317 { 0x1f, 0x0000 },
3318
3319 /* Update PFM & 10M TX idle timer */
3320 { 0x1f, 0x0007 },
3321 { 0x1e, 0x002f },
3322 { 0x15, 0x1919 },
3323 { 0x1f, 0x0000 },
3324
3325 { 0x1f, 0x0007 },
3326 { 0x1e, 0x00ac },
3327 { 0x18, 0x0006 },
3328 { 0x1f, 0x0000 }
3329 };
3330
15ecd039
FR		 3331 rtl_apply_firmware(tp);
3332
01dc7fec 3333 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3334
3335 /* DCO enable for 10M IDLE Power */
3336 rtl_writephy(tp, 0x1f, 0x0007);
3337 rtl_writephy(tp, 0x1e, 0x0023);
76564428 3338 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
01dc7fec 3339 rtl_writephy(tp, 0x1f, 0x0000);
3340
3341 /* For impedance matching */
3342 rtl_writephy(tp, 0x1f, 0x0002);
76564428 3343 rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
cecb5fd7 3344 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3345
3346 /* PHY auto speed down */
3347 rtl_writephy(tp, 0x1f, 0x0007);
3348 rtl_writephy(tp, 0x1e, 0x002d);
76564428 3349 rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
01dc7fec 3350 rtl_writephy(tp, 0x1f, 0x0000);
76564428 3351 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
01dc7fec 3352
3353 rtl_writephy(tp, 0x1f, 0x0005);
3354 rtl_writephy(tp, 0x05, 0x8b86);
76564428 3355 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
01dc7fec 3356 rtl_writephy(tp, 0x1f, 0x0000);
3357
3358 rtl_writephy(tp, 0x1f, 0x0005);
3359 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3360 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
01dc7fec 3361 rtl_writephy(tp, 0x1f, 0x0007);
3362 rtl_writephy(tp, 0x1e, 0x0020);
76564428 3363 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
01dc7fec 3364 rtl_writephy(tp, 0x1f, 0x0006);
3365 rtl_writephy(tp, 0x00, 0x5a00);
3366 rtl_writephy(tp, 0x1f, 0x0000);
3367 rtl_writephy(tp, 0x0d, 0x0007);
3368 rtl_writephy(tp, 0x0e, 0x003c);
3369 rtl_writephy(tp, 0x0d, 0x4007);
3370 rtl_writephy(tp, 0x0e, 0x0000);
3371 rtl_writephy(tp, 0x0d, 0x0000);
3372}
3373
9ecb9aab 3374static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3375{
3376 const u16 w[] = {
3377 addr[0] | (addr[1] << 8),
3378 addr[2] | (addr[3] << 8),
3379 addr[4] | (addr[5] << 8)
3380 };
3381 const struct exgmac_reg e[] = {
3382 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3383 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3384 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3385 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3386 };
3387
3388 rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3389}
3390
70090424
HW		 3391static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3392{
3393 static const struct phy_reg phy_reg_init[] = {
3394 /* Enable Delay cap */
3395 { 0x1f, 0x0004 },
3396 { 0x1f, 0x0007 },
3397 { 0x1e, 0x00ac },
3398 { 0x18, 0x0006 },
3399 { 0x1f, 0x0002 },
3400 { 0x1f, 0x0000 },
3401 { 0x1f, 0x0000 },
3402
3403 /* Channel estimation fine tune */
3404 { 0x1f, 0x0003 },
3405 { 0x09, 0xa20f },
3406 { 0x1f, 0x0000 },
3407 { 0x1f, 0x0000 },
3408
3409 /* Green Setting */
3410 { 0x1f, 0x0005 },
3411 { 0x05, 0x8b5b },
3412 { 0x06, 0x9222 },
3413 { 0x05, 0x8b6d },
3414 { 0x06, 0x8000 },
3415 { 0x05, 0x8b76 },
3416 { 0x06, 0x8000 },
3417 { 0x1f, 0x0000 }
3418 };
3419
3420 rtl_apply_firmware(tp);
3421
3422 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3423
3424 /* For 4-corner performance improve */
3425 rtl_writephy(tp, 0x1f, 0x0005);
3426 rtl_writephy(tp, 0x05, 0x8b80);
76564428 3427 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
70090424
HW		 3428 rtl_writephy(tp, 0x1f, 0x0000);
3429
3430 /* PHY auto speed down */
3431 rtl_writephy(tp, 0x1f, 0x0004);
3432 rtl_writephy(tp, 0x1f, 0x0007);
3433 rtl_writephy(tp, 0x1e, 0x002d);
76564428 3434 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
70090424
HW		 3435 rtl_writephy(tp, 0x1f, 0x0002);
3436 rtl_writephy(tp, 0x1f, 0x0000);
76564428 3437 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
70090424
HW		 3438
3439 /* improve 10M EEE waveform */
3440 rtl_writephy(tp, 0x1f, 0x0005);
3441 rtl_writephy(tp, 0x05, 0x8b86);
76564428 3442 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
70090424
HW		 3443 rtl_writephy(tp, 0x1f, 0x0000);
3444
3445 /* Improve 2-pair detection performance */
3446 rtl_writephy(tp, 0x1f, 0x0005);
3447 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3448 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
70090424
HW		 3449 rtl_writephy(tp, 0x1f, 0x0000);
3450
3451 /* EEE setting */
706123d0 3452 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003, ERIAR_EXGMAC);
70090424
HW		 3453 rtl_writephy(tp, 0x1f, 0x0005);
3454 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3455 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
70090424
HW		 3456 rtl_writephy(tp, 0x1f, 0x0004);
3457 rtl_writephy(tp, 0x1f, 0x0007);
3458 rtl_writephy(tp, 0x1e, 0x0020);
76564428 3459 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0100);
70090424
HW		 3460 rtl_writephy(tp, 0x1f, 0x0002);
3461 rtl_writephy(tp, 0x1f, 0x0000);
3462 rtl_writephy(tp, 0x0d, 0x0007);
3463 rtl_writephy(tp, 0x0e, 0x003c);
3464 rtl_writephy(tp, 0x0d, 0x4007);
3465 rtl_writephy(tp, 0x0e, 0x0000);
3466 rtl_writephy(tp, 0x0d, 0x0000);
3467
3468 /* Green feature */
3469 rtl_writephy(tp, 0x1f, 0x0003);
76564428
CHL		 3470 rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3471 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
70090424 3472 rtl_writephy(tp, 0x1f, 0x0000);
e0c07557 3473
9ecb9aab 3474 /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3475 rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
70090424
HW		 3476}
3477
5f886e08
HW		 3478static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3479{
3480 /* For 4-corner performance improve */
3481 rtl_writephy(tp, 0x1f, 0x0005);
3482 rtl_writephy(tp, 0x05, 0x8b80);
76564428 3483 rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
5f886e08
HW		 3484 rtl_writephy(tp, 0x1f, 0x0000);
3485
3486 /* PHY auto speed down */
3487 rtl_writephy(tp, 0x1f, 0x0007);
3488 rtl_writephy(tp, 0x1e, 0x002d);
76564428 3489 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
5f886e08 3490 rtl_writephy(tp, 0x1f, 0x0000);
76564428 3491 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
5f886e08
HW		 3492
3493 /* Improve 10M EEE waveform */
3494 rtl_writephy(tp, 0x1f, 0x0005);
3495 rtl_writephy(tp, 0x05, 0x8b86);
76564428 3496 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
5f886e08
HW		 3497 rtl_writephy(tp, 0x1f, 0x0000);
3498}
3499
c2218925
HW		 3500static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3501{
3502 static const struct phy_reg phy_reg_init[] = {
3503 /* Channel estimation fine tune */
3504 { 0x1f, 0x0003 },
3505 { 0x09, 0xa20f },
3506 { 0x1f, 0x0000 },
3507
3508 /* Modify green table for giga & fnet */
3509 { 0x1f, 0x0005 },
3510 { 0x05, 0x8b55 },
3511 { 0x06, 0x0000 },
3512 { 0x05, 0x8b5e },
3513 { 0x06, 0x0000 },
3514 { 0x05, 0x8b67 },
3515 { 0x06, 0x0000 },
3516 { 0x05, 0x8b70 },
3517 { 0x06, 0x0000 },
3518 { 0x1f, 0x0000 },
3519 { 0x1f, 0x0007 },
3520 { 0x1e, 0x0078 },
3521 { 0x17, 0x0000 },
3522 { 0x19, 0x00fb },
3523 { 0x1f, 0x0000 },
3524
3525 /* Modify green table for 10M */
3526 { 0x1f, 0x0005 },
3527 { 0x05, 0x8b79 },
3528 { 0x06, 0xaa00 },
3529 { 0x1f, 0x0000 },
3530
3531 /* Disable hiimpedance detection (RTCT) */
3532 { 0x1f, 0x0003 },
3533 { 0x01, 0x328a },
3534 { 0x1f, 0x0000 }
3535 };
3536
3537 rtl_apply_firmware(tp);
3538
3539 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3540
5f886e08 3541 rtl8168f_hw_phy_config(tp);
c2218925
HW		 3542
3543 /* Improve 2-pair detection performance */
3544 rtl_writephy(tp, 0x1f, 0x0005);
3545 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3546 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
c2218925
HW		 3547 rtl_writephy(tp, 0x1f, 0x0000);
3548}
3549
3550static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3551{
3552 rtl_apply_firmware(tp);
3553
5f886e08 3554 rtl8168f_hw_phy_config(tp);
c2218925
HW		 3555}
3556
b3d7b2f2
HW		 3557static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3558{
b3d7b2f2
HW		 3559 static const struct phy_reg phy_reg_init[] = {
3560 /* Channel estimation fine tune */
3561 { 0x1f, 0x0003 },
3562 { 0x09, 0xa20f },
3563 { 0x1f, 0x0000 },
3564
3565 /* Modify green table for giga & fnet */
3566 { 0x1f, 0x0005 },
3567 { 0x05, 0x8b55 },
3568 { 0x06, 0x0000 },
3569 { 0x05, 0x8b5e },
3570 { 0x06, 0x0000 },
3571 { 0x05, 0x8b67 },
3572 { 0x06, 0x0000 },
3573 { 0x05, 0x8b70 },
3574 { 0x06, 0x0000 },
3575 { 0x1f, 0x0000 },
3576 { 0x1f, 0x0007 },
3577 { 0x1e, 0x0078 },
3578 { 0x17, 0x0000 },
3579 { 0x19, 0x00aa },
3580 { 0x1f, 0x0000 },
3581
3582 /* Modify green table for 10M */
3583 { 0x1f, 0x0005 },
3584 { 0x05, 0x8b79 },
3585 { 0x06, 0xaa00 },
3586 { 0x1f, 0x0000 },
3587
3588 /* Disable hiimpedance detection (RTCT) */
3589 { 0x1f, 0x0003 },
3590 { 0x01, 0x328a },
3591 { 0x1f, 0x0000 }
3592 };
3593
3594
3595 rtl_apply_firmware(tp);
3596
3597 rtl8168f_hw_phy_config(tp);
3598
3599 /* Improve 2-pair detection performance */
3600 rtl_writephy(tp, 0x1f, 0x0005);
3601 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3602 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
b3d7b2f2
HW		 3603 rtl_writephy(tp, 0x1f, 0x0000);
3604
3605 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3606
3607 /* Modify green table for giga */
3608 rtl_writephy(tp, 0x1f, 0x0005);
3609 rtl_writephy(tp, 0x05, 0x8b54);
76564428 3610 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
b3d7b2f2 3611 rtl_writephy(tp, 0x05, 0x8b5d);
76564428 3612 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
b3d7b2f2 3613 rtl_writephy(tp, 0x05, 0x8a7c);
76564428 3614 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
b3d7b2f2 3615 rtl_writephy(tp, 0x05, 0x8a7f);
76564428 3616 rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
b3d7b2f2 3617 rtl_writephy(tp, 0x05, 0x8a82);
76564428 3618 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
b3d7b2f2 3619 rtl_writephy(tp, 0x05, 0x8a85);
76564428 3620 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
b3d7b2f2 3621 rtl_writephy(tp, 0x05, 0x8a88);
76564428 3622 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
b3d7b2f2
HW		 3623 rtl_writephy(tp, 0x1f, 0x0000);
3624
3625 /* uc same-seed solution */
3626 rtl_writephy(tp, 0x1f, 0x0005);
3627 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3628 rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
b3d7b2f2
HW		 3629 rtl_writephy(tp, 0x1f, 0x0000);
3630
3631 /* eee setting */
706123d0 3632 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
b3d7b2f2
HW		 3633 rtl_writephy(tp, 0x1f, 0x0005);
3634 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3635 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
b3d7b2f2
HW		 3636 rtl_writephy(tp, 0x1f, 0x0004);
3637 rtl_writephy(tp, 0x1f, 0x0007);
3638 rtl_writephy(tp, 0x1e, 0x0020);
76564428 3639 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0100);
b3d7b2f2
HW		 3640 rtl_writephy(tp, 0x1f, 0x0000);
3641 rtl_writephy(tp, 0x0d, 0x0007);
3642 rtl_writephy(tp, 0x0e, 0x003c);
3643 rtl_writephy(tp, 0x0d, 0x4007);
3644 rtl_writephy(tp, 0x0e, 0x0000);
3645 rtl_writephy(tp, 0x0d, 0x0000);
3646
3647 /* Green feature */
3648 rtl_writephy(tp, 0x1f, 0x0003);
76564428
CHL		 3649 rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3650 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
b3d7b2f2
HW		 3651 rtl_writephy(tp, 0x1f, 0x0000);
3652}
3653
c558386b
HW		 3654static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3655{
c558386b
HW		 3656 rtl_apply_firmware(tp);
3657
41f44d13 3658 rtl_writephy(tp, 0x1f, 0x0a46);
3659 if (rtl_readphy(tp, 0x10) & 0x0100) {
3660 rtl_writephy(tp, 0x1f, 0x0bcc);
76564428 3661 rtl_w0w1_phy(tp, 0x12, 0x0000, 0x8000);
41f44d13 3662 } else {
3663 rtl_writephy(tp, 0x1f, 0x0bcc);
76564428 3664 rtl_w0w1_phy(tp, 0x12, 0x8000, 0x0000);
41f44d13 3665 }
c558386b 3666
41f44d13 3667 rtl_writephy(tp, 0x1f, 0x0a46);
3668 if (rtl_readphy(tp, 0x13) & 0x0100) {
3669 rtl_writephy(tp, 0x1f, 0x0c41);
76564428 3670 rtl_w0w1_phy(tp, 0x15, 0x0002, 0x0000);
41f44d13 3671 } else {
fe7524c0 3672 rtl_writephy(tp, 0x1f, 0x0c41);
76564428 3673 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0002);
41f44d13 3674 }
c558386b 3675
41f44d13 3676 /* Enable PHY auto speed down */
3677 rtl_writephy(tp, 0x1f, 0x0a44);
76564428 3678 rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
c558386b 3679
fe7524c0 3680 rtl_writephy(tp, 0x1f, 0x0bcc);
76564428 3681 rtl_w0w1_phy(tp, 0x14, 0x0100, 0x0000);
fe7524c0 3682 rtl_writephy(tp, 0x1f, 0x0a44);
76564428 3683 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
fe7524c0 3684 rtl_writephy(tp, 0x1f, 0x0a43);
3685 rtl_writephy(tp, 0x13, 0x8084);
76564428
CHL		 3686 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3687 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
fe7524c0 3688
41f44d13 3689 /* EEE auto-fallback function */
3690 rtl_writephy(tp, 0x1f, 0x0a4b);
76564428 3691 rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
c558386b 3692
41f44d13 3693 /* Enable UC LPF tune function */
3694 rtl_writephy(tp, 0x1f, 0x0a43);
3695 rtl_writephy(tp, 0x13, 0x8012);
76564428 3696 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
41f44d13 3697
3698 rtl_writephy(tp, 0x1f, 0x0c42);
76564428 3699 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
41f44d13 3700
fe7524c0 3701 /* Improve SWR Efficiency */
3702 rtl_writephy(tp, 0x1f, 0x0bcd);
3703 rtl_writephy(tp, 0x14, 0x5065);
3704 rtl_writephy(tp, 0x14, 0xd065);
3705 rtl_writephy(tp, 0x1f, 0x0bc8);
3706 rtl_writephy(tp, 0x11, 0x5655);
3707 rtl_writephy(tp, 0x1f, 0x0bcd);
3708 rtl_writephy(tp, 0x14, 0x1065);
3709 rtl_writephy(tp, 0x14, 0x9065);
3710 rtl_writephy(tp, 0x14, 0x1065);
3711
1bac1072
DC		 3712 /* Check ALDPS bit, disable it if enabled */
3713 rtl_writephy(tp, 0x1f, 0x0a43);
3714 if (rtl_readphy(tp, 0x10) & 0x0004)
76564428 3715 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
1bac1072 3716
41f44d13 3717 rtl_writephy(tp, 0x1f, 0x0000);
c558386b
HW		 3718}
3719
57538c4a 3720static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3721{
3722 rtl_apply_firmware(tp);
3723}
3724
6e1d0b89
CHL		 3725static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3726{
3727 u16 dout_tapbin;
3728 u32 data;
3729
3730 rtl_apply_firmware(tp);
3731
3732 /* CHN EST parameters adjust - giga master */
3733 rtl_writephy(tp, 0x1f, 0x0a43);
3734 rtl_writephy(tp, 0x13, 0x809b);
76564428 3735 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800);
6e1d0b89 3736 rtl_writephy(tp, 0x13, 0x80a2);
76564428 3737 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00);
6e1d0b89 3738 rtl_writephy(tp, 0x13, 0x80a4);
76564428 3739 rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00);
6e1d0b89 3740 rtl_writephy(tp, 0x13, 0x809c);
76564428 3741 rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00);
6e1d0b89
CHL		 3742 rtl_writephy(tp, 0x1f, 0x0000);
3743
3744 /* CHN EST parameters adjust - giga slave */
3745 rtl_writephy(tp, 0x1f, 0x0a43);
3746 rtl_writephy(tp, 0x13, 0x80ad);
76564428 3747 rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800);
6e1d0b89 3748 rtl_writephy(tp, 0x13, 0x80b4);
76564428 3749 rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00);
6e1d0b89 3750 rtl_writephy(tp, 0x13, 0x80ac);
76564428 3751 rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00);
6e1d0b89
CHL		 3752 rtl_writephy(tp, 0x1f, 0x0000);
3753
3754 /* CHN EST parameters adjust - fnet */
3755 rtl_writephy(tp, 0x1f, 0x0a43);
3756 rtl_writephy(tp, 0x13, 0x808e);
76564428 3757 rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00);
6e1d0b89 3758 rtl_writephy(tp, 0x13, 0x8090);
76564428 3759 rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00);
6e1d0b89 3760 rtl_writephy(tp, 0x13, 0x8092);
76564428 3761 rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00);
6e1d0b89
CHL		 3762 rtl_writephy(tp, 0x1f, 0x0000);
3763
3764 /* enable R-tune & PGA-retune function */
3765 dout_tapbin = 0;
3766 rtl_writephy(tp, 0x1f, 0x0a46);
3767 data = rtl_readphy(tp, 0x13);
3768 data &= 3;
3769 data <<= 2;
3770 dout_tapbin |= data;
3771 data = rtl_readphy(tp, 0x12);
3772 data &= 0xc000;
3773 data >>= 14;
3774 dout_tapbin |= data;
3775 dout_tapbin = ~(dout_tapbin^0x08);
3776 dout_tapbin <<= 12;
3777 dout_tapbin &= 0xf000;
3778 rtl_writephy(tp, 0x1f, 0x0a43);
3779 rtl_writephy(tp, 0x13, 0x827a);
76564428 3780 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
6e1d0b89 3781 rtl_writephy(tp, 0x13, 0x827b);
76564428 3782 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
6e1d0b89 3783 rtl_writephy(tp, 0x13, 0x827c);
76564428 3784 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
6e1d0b89 3785 rtl_writephy(tp, 0x13, 0x827d);
76564428 3786 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
6e1d0b89
CHL		 3787
3788 rtl_writephy(tp, 0x1f, 0x0a43);
3789 rtl_writephy(tp, 0x13, 0x0811);
76564428 3790 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
6e1d0b89 3791 rtl_writephy(tp, 0x1f, 0x0a42);
76564428 3792 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
6e1d0b89
CHL		 3793 rtl_writephy(tp, 0x1f, 0x0000);
3794
3795 /* enable GPHY 10M */
3796 rtl_writephy(tp, 0x1f, 0x0a44);
76564428 3797 rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
6e1d0b89
CHL		 3798 rtl_writephy(tp, 0x1f, 0x0000);
3799
3800 /* SAR ADC performance */
3801 rtl_writephy(tp, 0x1f, 0x0bca);
76564428 3802 rtl_w0w1_phy(tp, 0x17, 0x4000, 0x3000);
6e1d0b89
CHL		 3803 rtl_writephy(tp, 0x1f, 0x0000);
3804
3805 rtl_writephy(tp, 0x1f, 0x0a43);
3806 rtl_writephy(tp, 0x13, 0x803f);
76564428 3807 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 3808 rtl_writephy(tp, 0x13, 0x8047);
76564428 3809 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 3810 rtl_writephy(tp, 0x13, 0x804f);
76564428 3811 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 3812 rtl_writephy(tp, 0x13, 0x8057);
76564428 3813 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 3814 rtl_writephy(tp, 0x13, 0x805f);
76564428 3815 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 3816 rtl_writephy(tp, 0x13, 0x8067);
76564428 3817 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 3818 rtl_writephy(tp, 0x13, 0x806f);
76564428 3819 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89
CHL		 3820 rtl_writephy(tp, 0x1f, 0x0000);
3821
3822 /* disable phy pfm mode */
3823 rtl_writephy(tp, 0x1f, 0x0a44);
76564428 3824 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0080);
6e1d0b89
CHL		 3825 rtl_writephy(tp, 0x1f, 0x0000);
3826
3827 /* Check ALDPS bit, disable it if enabled */
3828 rtl_writephy(tp, 0x1f, 0x0a43);
3829 if (rtl_readphy(tp, 0x10) & 0x0004)
76564428 3830 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
6e1d0b89
CHL		 3831
3832 rtl_writephy(tp, 0x1f, 0x0000);
3833}
3834
3835static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
3836{
3837 u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
3838 u16 rlen;
3839 u32 data;
3840
3841 rtl_apply_firmware(tp);
3842
3843 /* CHIN EST parameter update */
3844 rtl_writephy(tp, 0x1f, 0x0a43);
3845 rtl_writephy(tp, 0x13, 0x808a);
76564428 3846 rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f);
6e1d0b89
CHL		 3847 rtl_writephy(tp, 0x1f, 0x0000);
3848
3849 /* enable R-tune & PGA-retune function */
3850 rtl_writephy(tp, 0x1f, 0x0a43);
3851 rtl_writephy(tp, 0x13, 0x0811);
76564428 3852 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
6e1d0b89 3853 rtl_writephy(tp, 0x1f, 0x0a42);
76564428 3854 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
6e1d0b89
CHL		 3855 rtl_writephy(tp, 0x1f, 0x0000);
3856
3857 /* enable GPHY 10M */
3858 rtl_writephy(tp, 0x1f, 0x0a44);
76564428 3859 rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
6e1d0b89
CHL		 3860 rtl_writephy(tp, 0x1f, 0x0000);
3861
3862 r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
3863 data = r8168_mac_ocp_read(tp, 0xdd02);
3864 ioffset_p3 = ((data & 0x80)>>7);
3865 ioffset_p3 <<= 3;
3866
3867 data = r8168_mac_ocp_read(tp, 0xdd00);
3868 ioffset_p3 |= ((data & (0xe000))>>13);
3869 ioffset_p2 = ((data & (0x1e00))>>9);
3870 ioffset_p1 = ((data & (0x01e0))>>5);
3871 ioffset_p0 = ((data & 0x0010)>>4);
3872 ioffset_p0 <<= 3;
3873 ioffset_p0 |= (data & (0x07));
3874 data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
3875
05b9687b
CHL		 3876 if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
3877 (ioffset_p1 != 0x0f) || (ioffset_p0 == 0x0f)) {
6e1d0b89
CHL		 3878 rtl_writephy(tp, 0x1f, 0x0bcf);
3879 rtl_writephy(tp, 0x16, data);
3880 rtl_writephy(tp, 0x1f, 0x0000);
3881 }
3882
3883 /* Modify rlen (TX LPF corner frequency) level */
3884 rtl_writephy(tp, 0x1f, 0x0bcd);
3885 data = rtl_readphy(tp, 0x16);
3886 data &= 0x000f;
3887 rlen = 0;
3888 if (data > 3)
3889 rlen = data - 3;
3890 data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
3891 rtl_writephy(tp, 0x17, data);
3892 rtl_writephy(tp, 0x1f, 0x0bcd);
3893 rtl_writephy(tp, 0x1f, 0x0000);
3894
3895 /* disable phy pfm mode */
3896 rtl_writephy(tp, 0x1f, 0x0a44);
76564428 3897 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0080);
6e1d0b89
CHL		 3898 rtl_writephy(tp, 0x1f, 0x0000);
3899
3900 /* Check ALDPS bit, disable it if enabled */
3901 rtl_writephy(tp, 0x1f, 0x0a43);
3902 if (rtl_readphy(tp, 0x10) & 0x0004)
76564428 3903 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
6e1d0b89
CHL		 3904
3905 rtl_writephy(tp, 0x1f, 0x0000);
3906}
3907
935e2218
CHL		 3908static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
3909{
3910 /* Enable PHY auto speed down */
3911 rtl_writephy(tp, 0x1f, 0x0a44);
3912 rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3913 rtl_writephy(tp, 0x1f, 0x0000);
3914
3915 /* patch 10M & ALDPS */
3916 rtl_writephy(tp, 0x1f, 0x0bcc);
3917 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
3918 rtl_writephy(tp, 0x1f, 0x0a44);
3919 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3920 rtl_writephy(tp, 0x1f, 0x0a43);
3921 rtl_writephy(tp, 0x13, 0x8084);
3922 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3923 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3924 rtl_writephy(tp, 0x1f, 0x0000);
3925
3926 /* Enable EEE auto-fallback function */
3927 rtl_writephy(tp, 0x1f, 0x0a4b);
3928 rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3929 rtl_writephy(tp, 0x1f, 0x0000);
3930
3931 /* Enable UC LPF tune function */
3932 rtl_writephy(tp, 0x1f, 0x0a43);
3933 rtl_writephy(tp, 0x13, 0x8012);
3934 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3935 rtl_writephy(tp, 0x1f, 0x0000);
3936
3937 /* set rg_sel_sdm_rate */
3938 rtl_writephy(tp, 0x1f, 0x0c42);
3939 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3940 rtl_writephy(tp, 0x1f, 0x0000);
3941
3942 /* Check ALDPS bit, disable it if enabled */
3943 rtl_writephy(tp, 0x1f, 0x0a43);
3944 if (rtl_readphy(tp, 0x10) & 0x0004)
3945 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3946
3947 rtl_writephy(tp, 0x1f, 0x0000);
3948}
3949
3950static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
3951{
3952 /* patch 10M & ALDPS */
3953 rtl_writephy(tp, 0x1f, 0x0bcc);
3954 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
3955 rtl_writephy(tp, 0x1f, 0x0a44);
3956 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3957 rtl_writephy(tp, 0x1f, 0x0a43);
3958 rtl_writephy(tp, 0x13, 0x8084);
3959 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3960 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3961 rtl_writephy(tp, 0x1f, 0x0000);
3962
3963 /* Enable UC LPF tune function */
3964 rtl_writephy(tp, 0x1f, 0x0a43);
3965 rtl_writephy(tp, 0x13, 0x8012);
3966 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3967 rtl_writephy(tp, 0x1f, 0x0000);
3968
3969 /* Set rg_sel_sdm_rate */
3970 rtl_writephy(tp, 0x1f, 0x0c42);
3971 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3972 rtl_writephy(tp, 0x1f, 0x0000);
3973
3974 /* Channel estimation parameters */
3975 rtl_writephy(tp, 0x1f, 0x0a43);
3976 rtl_writephy(tp, 0x13, 0x80f3);
3977 rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff);
3978 rtl_writephy(tp, 0x13, 0x80f0);
3979 rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff);
3980 rtl_writephy(tp, 0x13, 0x80ef);
3981 rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff);
3982 rtl_writephy(tp, 0x13, 0x80f6);
3983 rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff);
3984 rtl_writephy(tp, 0x13, 0x80ec);
3985 rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff);
3986 rtl_writephy(tp, 0x13, 0x80ed);
3987 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3988 rtl_writephy(tp, 0x13, 0x80f2);
3989 rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff);
3990 rtl_writephy(tp, 0x13, 0x80f4);
3991 rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff);
3992 rtl_writephy(tp, 0x1f, 0x0a43);
3993 rtl_writephy(tp, 0x13, 0x8110);
3994 rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff);
3995 rtl_writephy(tp, 0x13, 0x810f);
3996 rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff);
3997 rtl_writephy(tp, 0x13, 0x8111);
3998 rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff);
3999 rtl_writephy(tp, 0x13, 0x8113);
4000 rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff);
4001 rtl_writephy(tp, 0x13, 0x8115);
4002 rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff);
4003 rtl_writephy(tp, 0x13, 0x810e);
4004 rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff);
4005 rtl_writephy(tp, 0x13, 0x810c);
4006 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
4007 rtl_writephy(tp, 0x13, 0x810b);
4008 rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff);
4009 rtl_writephy(tp, 0x1f, 0x0a43);
4010 rtl_writephy(tp, 0x13, 0x80d1);
4011 rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff);
4012 rtl_writephy(tp, 0x13, 0x80cd);
4013 rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff);
4014 rtl_writephy(tp, 0x13, 0x80d3);
4015 rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff);
4016 rtl_writephy(tp, 0x13, 0x80d5);
4017 rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff);
4018 rtl_writephy(tp, 0x13, 0x80d7);
4019 rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff);
4020
4021 /* Force PWM-mode */
4022 rtl_writephy(tp, 0x1f, 0x0bcd);
4023 rtl_writephy(tp, 0x14, 0x5065);
4024 rtl_writephy(tp, 0x14, 0xd065);
4025 rtl_writephy(tp, 0x1f, 0x0bc8);
4026 rtl_writephy(tp, 0x12, 0x00ed);
4027 rtl_writephy(tp, 0x1f, 0x0bcd);
4028 rtl_writephy(tp, 0x14, 0x1065);
4029 rtl_writephy(tp, 0x14, 0x9065);
4030 rtl_writephy(tp, 0x14, 0x1065);
4031 rtl_writephy(tp, 0x1f, 0x0000);
4032
4033 /* Check ALDPS bit, disable it if enabled */
4034 rtl_writephy(tp, 0x1f, 0x0a43);
4035 if (rtl_readphy(tp, 0x10) & 0x0004)
4036 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
4037
4038 rtl_writephy(tp, 0x1f, 0x0000);
4039}
4040
4da19633 4041static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2857ffb7 4042{
350f7596 4043 static const struct phy_reg phy_reg_init[] = {
2857ffb7
FR		 4044 { 0x1f, 0x0003 },
4045 { 0x08, 0x441d },
4046 { 0x01, 0x9100 },
4047 { 0x1f, 0x0000 }
4048 };
4049
4da19633 4050 rtl_writephy(tp, 0x1f, 0x0000);
4051 rtl_patchphy(tp, 0x11, 1 << 12);
4052 rtl_patchphy(tp, 0x19, 1 << 13);
4053 rtl_patchphy(tp, 0x10, 1 << 15);
2857ffb7 4054
4da19633 4055 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2857ffb7
FR		 4056}
4057
5a5e4443
HW		 4058static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
4059{
4060 static const struct phy_reg phy_reg_init[] = {
4061 { 0x1f, 0x0005 },
4062 { 0x1a, 0x0000 },
4063 { 0x1f, 0x0000 },
4064
4065 { 0x1f, 0x0004 },
4066 { 0x1c, 0x0000 },
4067 { 0x1f, 0x0000 },
4068
4069 { 0x1f, 0x0001 },
4070 { 0x15, 0x7701 },
4071 { 0x1f, 0x0000 }
4072 };
4073
4074 /* Disable ALDPS before ram code */
eef63cc1
FR		 4075 rtl_writephy(tp, 0x1f, 0x0000);
4076 rtl_writephy(tp, 0x18, 0x0310);
4077 msleep(100);
5a5e4443 4078
953a12cc 4079 rtl_apply_firmware(tp);
5a5e4443
HW		 4080
4081 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4082}
4083
7e18dca1
HW		 4084static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
4085{
7e18dca1 4086 /* Disable ALDPS before setting firmware */
eef63cc1
FR		 4087 rtl_writephy(tp, 0x1f, 0x0000);
4088 rtl_writephy(tp, 0x18, 0x0310);
4089 msleep(20);
7e18dca1
HW		 4090
4091 rtl_apply_firmware(tp);
4092
4093 /* EEE setting */
fdf6fc06 4094 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
7e18dca1
HW		 4095 rtl_writephy(tp, 0x1f, 0x0004);
4096 rtl_writephy(tp, 0x10, 0x401f);
4097 rtl_writephy(tp, 0x19, 0x7030);
4098 rtl_writephy(tp, 0x1f, 0x0000);
4099}
4100
5598bfe5
HW		 4101static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
4102{
5598bfe5
HW		 4103 static const struct phy_reg phy_reg_init[] = {
4104 { 0x1f, 0x0004 },
4105 { 0x10, 0xc07f },
4106 { 0x19, 0x7030 },
4107 { 0x1f, 0x0000 }
4108 };
4109
4110 /* Disable ALDPS before ram code */
eef63cc1
FR		 4111 rtl_writephy(tp, 0x1f, 0x0000);
4112 rtl_writephy(tp, 0x18, 0x0310);
4113 msleep(100);
5598bfe5
HW		 4114
4115 rtl_apply_firmware(tp);
4116
fdf6fc06 4117 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5598bfe5
HW		 4118 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4119
fdf6fc06 4120 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5598bfe5
HW		 4121}
4122
5615d9f1
FR		 4123static void rtl_hw_phy_config(struct net_device *dev)
4124{
4125 struct rtl8169_private *tp = netdev_priv(dev);
5615d9f1
FR		 4126
4127 rtl8169_print_mac_version(tp);
4128
4129 switch (tp->mac_version) {
4130 case RTL_GIGA_MAC_VER_01:
4131 break;
4132 case RTL_GIGA_MAC_VER_02:
4133 case RTL_GIGA_MAC_VER_03:
4da19633 4134 rtl8169s_hw_phy_config(tp);
5615d9f1
FR		 4135 break;
4136 case RTL_GIGA_MAC_VER_04:
4da19633 4137 rtl8169sb_hw_phy_config(tp);
5615d9f1 4138 break;
2e955856 4139 case RTL_GIGA_MAC_VER_05:
4da19633 4140 rtl8169scd_hw_phy_config(tp);
2e955856 4141 break;
8c7006aa 4142 case RTL_GIGA_MAC_VER_06:
4da19633 4143 rtl8169sce_hw_phy_config(tp);
8c7006aa 4144 break;
2857ffb7
FR		 4145 case RTL_GIGA_MAC_VER_07:
4146 case RTL_GIGA_MAC_VER_08:
4147 case RTL_GIGA_MAC_VER_09:
4da19633 4148 rtl8102e_hw_phy_config(tp);
2857ffb7 4149 break;
236b8082 4150 case RTL_GIGA_MAC_VER_11:
4da19633 4151 rtl8168bb_hw_phy_config(tp);
236b8082
FR		 4152 break;
4153 case RTL_GIGA_MAC_VER_12:
4da19633 4154 rtl8168bef_hw_phy_config(tp);
236b8082
FR		 4155 break;
4156 case RTL_GIGA_MAC_VER_17:
4da19633 4157 rtl8168bef_hw_phy_config(tp);
236b8082 4158 break;
867763c1 4159 case RTL_GIGA_MAC_VER_18:
4da19633 4160 rtl8168cp_1_hw_phy_config(tp);
867763c1
FR		 4161 break;
4162 case RTL_GIGA_MAC_VER_19:
4da19633 4163 rtl8168c_1_hw_phy_config(tp);
867763c1 4164 break;
7da97ec9 4165 case RTL_GIGA_MAC_VER_20:
4da19633 4166 rtl8168c_2_hw_phy_config(tp);
7da97ec9 4167 break;
197ff761 4168 case RTL_GIGA_MAC_VER_21:
4da19633 4169 rtl8168c_3_hw_phy_config(tp);
197ff761 4170 break;
6fb07058 4171 case RTL_GIGA_MAC_VER_22:
4da19633 4172 rtl8168c_4_hw_phy_config(tp);
6fb07058 4173 break;
ef3386f0 4174 case RTL_GIGA_MAC_VER_23:
7f3e3d3a 4175 case RTL_GIGA_MAC_VER_24:
4da19633 4176 rtl8168cp_2_hw_phy_config(tp);
ef3386f0 4177 break;
5b538df9 4178 case RTL_GIGA_MAC_VER_25:
bca03d5f 4179 rtl8168d_1_hw_phy_config(tp);
daf9df6d 4180 break;
4181 case RTL_GIGA_MAC_VER_26:
bca03d5f 4182 rtl8168d_2_hw_phy_config(tp);
daf9df6d 4183 break;
4184 case RTL_GIGA_MAC_VER_27:
4da19633 4185 rtl8168d_3_hw_phy_config(tp);
5b538df9 4186 break;
e6de30d6 4187 case RTL_GIGA_MAC_VER_28:
4188 rtl8168d_4_hw_phy_config(tp);
4189 break;
5a5e4443
HW		 4190 case RTL_GIGA_MAC_VER_29:
4191 case RTL_GIGA_MAC_VER_30:
4192 rtl8105e_hw_phy_config(tp);
4193 break;
cecb5fd7
FR		 4194 case RTL_GIGA_MAC_VER_31:
4195 /* None. */
4196 break;
01dc7fec 4197 case RTL_GIGA_MAC_VER_32:
01dc7fec 4198 case RTL_GIGA_MAC_VER_33:
70090424
HW		 4199 rtl8168e_1_hw_phy_config(tp);
4200 break;
4201 case RTL_GIGA_MAC_VER_34:
4202 rtl8168e_2_hw_phy_config(tp);
01dc7fec 4203 break;
c2218925
HW		 4204 case RTL_GIGA_MAC_VER_35:
4205 rtl8168f_1_hw_phy_config(tp);
4206 break;
4207 case RTL_GIGA_MAC_VER_36:
4208 rtl8168f_2_hw_phy_config(tp);
4209 break;
ef3386f0 4210
7e18dca1
HW		 4211 case RTL_GIGA_MAC_VER_37:
4212 rtl8402_hw_phy_config(tp);
4213 break;
4214
b3d7b2f2
HW		 4215 case RTL_GIGA_MAC_VER_38:
4216 rtl8411_hw_phy_config(tp);
4217 break;
4218
5598bfe5
HW		 4219 case RTL_GIGA_MAC_VER_39:
4220 rtl8106e_hw_phy_config(tp);
4221 break;
4222
c558386b
HW		 4223 case RTL_GIGA_MAC_VER_40:
4224 rtl8168g_1_hw_phy_config(tp);
4225 break;
57538c4a 4226 case RTL_GIGA_MAC_VER_42:
58152cd4 4227 case RTL_GIGA_MAC_VER_43:
45dd95c4 4228 case RTL_GIGA_MAC_VER_44:
57538c4a 4229 rtl8168g_2_hw_phy_config(tp);
4230 break;
6e1d0b89
CHL		 4231 case RTL_GIGA_MAC_VER_45:
4232 case RTL_GIGA_MAC_VER_47:
4233 rtl8168h_1_hw_phy_config(tp);
4234 break;
4235 case RTL_GIGA_MAC_VER_46:
4236 case RTL_GIGA_MAC_VER_48:
4237 rtl8168h_2_hw_phy_config(tp);
4238 break;
c558386b 4239
935e2218
CHL		 4240 case RTL_GIGA_MAC_VER_49:
4241 rtl8168ep_1_hw_phy_config(tp);
4242 break;
4243 case RTL_GIGA_MAC_VER_50:
4244 case RTL_GIGA_MAC_VER_51:
4245 rtl8168ep_2_hw_phy_config(tp);
4246 break;
4247
c558386b 4248 case RTL_GIGA_MAC_VER_41:
5615d9f1
FR		 4249 default:
4250 break;
4251 }
4252}
4253
da78dbff 4254static void rtl_phy_work(struct rtl8169_private *tp)
1da177e4 4255{
1da177e4
LT		 4256 struct timer_list *timer = &tp->timer;
4257 void __iomem *ioaddr = tp->mmio_addr;
4258 unsigned long timeout = RTL8169_PHY_TIMEOUT;
4259
bcf0bf90 4260 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1da177e4 4261
4da19633 4262 if (tp->phy_reset_pending(tp)) {
5b0384f4 4263 /*
1da177e4
LT		 4264 * A busy loop could burn quite a few cycles on nowadays CPU.
4265 * Let's delay the execution of the timer for a few ticks.
4266 */
4267 timeout = HZ/10;
4268 goto out_mod_timer;
4269 }
4270
4271 if (tp->link_ok(ioaddr))
da78dbff 4272 return;
1da177e4 4273
9bb8eeb5 4274 netif_dbg(tp, link, tp->dev, "PHY reset until link up\n");
1da177e4 4275
4da19633 4276 tp->phy_reset_enable(tp);
1da177e4
LT		 4277
4278out_mod_timer:
4279 mod_timer(timer, jiffies + timeout);
da78dbff
FR		 4280}
4281
4282static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
4283{
da78dbff
FR		 4284 if (!test_and_set_bit(flag, tp->wk.flags))
4285 schedule_work(&tp->wk.work);
da78dbff
FR		 4286}
4287
4288static void rtl8169_phy_timer(unsigned long __opaque)
4289{
4290 struct net_device *dev = (struct net_device *)__opaque;
4291 struct rtl8169_private *tp = netdev_priv(dev);
4292
98ddf986 4293 rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
1da177e4
LT		 4294}
4295
1da177e4
LT		 4296static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
4297 void __iomem *ioaddr)
4298{
4299 iounmap(ioaddr);
4300 pci_release_regions(pdev);
87aeec76 4301 pci_clear_mwi(pdev);
1da177e4
LT		 4302 pci_disable_device(pdev);
4303 free_netdev(dev);
4304}
4305
ffc46952
FR		 4306DECLARE_RTL_COND(rtl_phy_reset_cond)
4307{
4308 return tp->phy_reset_pending(tp);
4309}
4310
bf793295
FR		 4311static void rtl8169_phy_reset(struct net_device *dev,
4312 struct rtl8169_private *tp)
4313{
4da19633 4314 tp->phy_reset_enable(tp);
ffc46952 4315 rtl_msleep_loop_wait_low(tp, &rtl_phy_reset_cond, 1, 100);
bf793295
FR		 4316}
4317
2544bfc0
FR		 4318static bool rtl_tbi_enabled(struct rtl8169_private *tp)
4319{
4320 void __iomem *ioaddr = tp->mmio_addr;
4321
4322 return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
4323 (RTL_R8(PHYstatus) & TBI_Enable);
4324}
4325
4ff96fa6
FR		 4326static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
4327{
4328 void __iomem *ioaddr = tp->mmio_addr;
4ff96fa6 4329
5615d9f1 4330 rtl_hw_phy_config(dev);
4ff96fa6 4331
77332894
MS		 4332 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
4333 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4334 RTL_W8(0x82, 0x01);
4335 }
4ff96fa6 4336
6dccd16b
FR		 4337 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
4338
4339 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
4340 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 4341
bcf0bf90 4342 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4ff96fa6
FR		 4343 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4344 RTL_W8(0x82, 0x01);
4345 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
4da19633 4346 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4ff96fa6
FR		 4347 }
4348
bf793295
FR		 4349 rtl8169_phy_reset(dev, tp);
4350
54405cde 4351 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
cecb5fd7
FR		 4352 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4353 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
4354 (tp->mii.supports_gmii ?
4355 ADVERTISED_1000baseT_Half |
4356 ADVERTISED_1000baseT_Full : 0));
4ff96fa6 4357
2544bfc0 4358 if (rtl_tbi_enabled(tp))
bf82c189 4359 netif_info(tp, link, dev, "TBI auto-negotiating\n");
4ff96fa6
FR		 4360}
4361
773d2021
FR		 4362static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
4363{
4364 void __iomem *ioaddr = tp->mmio_addr;
773d2021 4365
da78dbff 4366 rtl_lock_work(tp);
773d2021
FR		 4367
4368 RTL_W8(Cfg9346, Cfg9346_Unlock);
908ba2bf 4369
9ecb9aab 4370 RTL_W32(MAC4, addr[4] | addr[5] << 8);
908ba2bf 4371 RTL_R32(MAC4);
4372
9ecb9aab 4373 RTL_W32(MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
908ba2bf 4374 RTL_R32(MAC0);
4375
9ecb9aab 4376 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4377 rtl_rar_exgmac_set(tp, addr);
c28aa385 4378
773d2021
FR		 4379 RTL_W8(Cfg9346, Cfg9346_Lock);
4380
da78dbff 4381 rtl_unlock_work(tp);
773d2021
FR		 4382}
4383
4384static int rtl_set_mac_address(struct net_device *dev, void *p)
4385{
4386 struct rtl8169_private *tp = netdev_priv(dev);
4387 struct sockaddr *addr = p;
4388
4389 if (!is_valid_ether_addr(addr->sa_data))
4390 return -EADDRNOTAVAIL;
4391
4392 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
4393
4394 rtl_rar_set(tp, dev->dev_addr);
4395
4396 return 0;
4397}
4398
5f787a1a
FR		 4399static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4400{
4401 struct rtl8169_private *tp = netdev_priv(dev);
4402 struct mii_ioctl_data *data = if_mii(ifr);
4403
8b4ab28d
FR		 4404 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
4405}
5f787a1a 4406
cecb5fd7
FR		 4407static int rtl_xmii_ioctl(struct rtl8169_private *tp,
4408 struct mii_ioctl_data *data, int cmd)
8b4ab28d 4409{
5f787a1a
FR		 4410 switch (cmd) {
4411 case SIOCGMIIPHY:
4412 data->phy_id = 32; /* Internal PHY */
4413 return 0;
4414
4415 case SIOCGMIIREG:
4da19633 4416 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
5f787a1a
FR		 4417 return 0;
4418
4419 case SIOCSMIIREG:
4da19633 4420 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
5f787a1a
FR		 4421 return 0;
4422 }
4423 return -EOPNOTSUPP;
4424}
4425
8b4ab28d
FR		 4426static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
4427{
4428 return -EOPNOTSUPP;
4429}
4430
fbac58fc
FR		 4431static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
4432{
4433 if (tp->features & RTL_FEATURE_MSI) {
4434 pci_disable_msi(pdev);
4435 tp->features &= ~RTL_FEATURE_MSI;
4436 }
4437}
4438
baf63293 4439static void rtl_init_mdio_ops(struct rtl8169_private *tp)
c0e45c1c 4440{
4441 struct mdio_ops *ops = &tp->mdio_ops;
4442
4443 switch (tp->mac_version) {
4444 case RTL_GIGA_MAC_VER_27:
4445 ops->write = r8168dp_1_mdio_write;
4446 ops->read = r8168dp_1_mdio_read;
4447 break;
e6de30d6 4448 case RTL_GIGA_MAC_VER_28:
4804b3b3 4449 case RTL_GIGA_MAC_VER_31:
e6de30d6 4450 ops->write = r8168dp_2_mdio_write;
4451 ops->read = r8168dp_2_mdio_read;
4452 break;
c558386b
HW		 4453 case RTL_GIGA_MAC_VER_40:
4454 case RTL_GIGA_MAC_VER_41:
57538c4a 4455 case RTL_GIGA_MAC_VER_42:
58152cd4 4456 case RTL_GIGA_MAC_VER_43:
45dd95c4 4457 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 4458 case RTL_GIGA_MAC_VER_45:
4459 case RTL_GIGA_MAC_VER_46:
4460 case RTL_GIGA_MAC_VER_47:
4461 case RTL_GIGA_MAC_VER_48:
935e2218
CHL		 4462 case RTL_GIGA_MAC_VER_49:
4463 case RTL_GIGA_MAC_VER_50:
4464 case RTL_GIGA_MAC_VER_51:
c558386b
HW		 4465 ops->write = r8168g_mdio_write;
4466 ops->read = r8168g_mdio_read;
4467 break;
c0e45c1c 4468 default:
4469 ops->write = r8169_mdio_write;
4470 ops->read = r8169_mdio_read;
4471 break;
4472 }
4473}
4474
e2409d83 4475static void rtl_speed_down(struct rtl8169_private *tp)
4476{
4477 u32 adv;
4478 int lpa;
4479
4480 rtl_writephy(tp, 0x1f, 0x0000);
4481 lpa = rtl_readphy(tp, MII_LPA);
4482
4483 if (lpa & (LPA_10HALF | LPA_10FULL))
4484 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full;
4485 else if (lpa & (LPA_100HALF | LPA_100FULL))
4486 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4487 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
4488 else
4489 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4490 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
4491 (tp->mii.supports_gmii ?
4492 ADVERTISED_1000baseT_Half |
4493 ADVERTISED_1000baseT_Full : 0);
4494
4495 rtl8169_set_speed(tp->dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
4496 adv);
4497}
4498
649b3b8c 4499static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
4500{
4501 void __iomem *ioaddr = tp->mmio_addr;
4502
4503 switch (tp->mac_version) {
b00e69de
CB		 4504 case RTL_GIGA_MAC_VER_25:
4505 case RTL_GIGA_MAC_VER_26:
649b3b8c 4506 case RTL_GIGA_MAC_VER_29:
4507 case RTL_GIGA_MAC_VER_30:
4508 case RTL_GIGA_MAC_VER_32:
4509 case RTL_GIGA_MAC_VER_33:
4510 case RTL_GIGA_MAC_VER_34:
7e18dca1 4511 case RTL_GIGA_MAC_VER_37:
b3d7b2f2 4512 case RTL_GIGA_MAC_VER_38:
5598bfe5 4513 case RTL_GIGA_MAC_VER_39:
c558386b
HW		 4514 case RTL_GIGA_MAC_VER_40:
4515 case RTL_GIGA_MAC_VER_41:
57538c4a 4516 case RTL_GIGA_MAC_VER_42:
58152cd4 4517 case RTL_GIGA_MAC_VER_43:
45dd95c4 4518 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 4519 case RTL_GIGA_MAC_VER_45:
4520 case RTL_GIGA_MAC_VER_46:
4521 case RTL_GIGA_MAC_VER_47:
4522 case RTL_GIGA_MAC_VER_48:
935e2218
CHL		 4523 case RTL_GIGA_MAC_VER_49:
4524 case RTL_GIGA_MAC_VER_50:
4525 case RTL_GIGA_MAC_VER_51:
649b3b8c 4526 RTL_W32(RxConfig, RTL_R32(RxConfig) |
4527 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
4528 break;
4529 default:
4530 break;
4531 }
4532}
4533
4534static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
4535{
4536 if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
4537 return false;
4538
e2409d83 4539 rtl_speed_down(tp);
649b3b8c 4540 rtl_wol_suspend_quirk(tp);
4541
4542 return true;
4543}
4544
065c27c1 4545static void r810x_phy_power_down(struct rtl8169_private *tp)
4546{
4547 rtl_writephy(tp, 0x1f, 0x0000);
4548 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
4549}
4550
4551static void r810x_phy_power_up(struct rtl8169_private *tp)
4552{
4553 rtl_writephy(tp, 0x1f, 0x0000);
4554 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
4555}
4556
4557static void r810x_pll_power_down(struct rtl8169_private *tp)
4558{
0004299a
HW		 4559 void __iomem *ioaddr = tp->mmio_addr;
4560
649b3b8c 4561 if (rtl_wol_pll_power_down(tp))
065c27c1 4562 return;
065c27c1 4563
4564 r810x_phy_power_down(tp);
0004299a
HW		 4565
4566 switch (tp->mac_version) {
4567 case RTL_GIGA_MAC_VER_07:
4568 case RTL_GIGA_MAC_VER_08:
4569 case RTL_GIGA_MAC_VER_09:
4570 case RTL_GIGA_MAC_VER_10:
4571 case RTL_GIGA_MAC_VER_13:
4572 case RTL_GIGA_MAC_VER_16:
4573 break;
4574 default:
4575 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4576 break;
4577 }
065c27c1 4578}
4579
4580static void r810x_pll_power_up(struct rtl8169_private *tp)
4581{
0004299a
HW		 4582 void __iomem *ioaddr = tp->mmio_addr;
4583
065c27c1 4584 r810x_phy_power_up(tp);
0004299a
HW		 4585
4586 switch (tp->mac_version) {
4587 case RTL_GIGA_MAC_VER_07:
4588 case RTL_GIGA_MAC_VER_08:
4589 case RTL_GIGA_MAC_VER_09:
4590 case RTL_GIGA_MAC_VER_10:
4591 case RTL_GIGA_MAC_VER_13:
4592 case RTL_GIGA_MAC_VER_16:
4593 break;
6e1d0b89
CHL		 4594 case RTL_GIGA_MAC_VER_47:
4595 case RTL_GIGA_MAC_VER_48:
05b9687b 4596 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
6e1d0b89 4597 break;
0004299a
HW		 4598 default:
4599 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
4600 break;
4601 }
065c27c1 4602}
4603
4604static void r8168_phy_power_up(struct rtl8169_private *tp)
4605{
4606 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 4607 switch (tp->mac_version) {
4608 case RTL_GIGA_MAC_VER_11:
4609 case RTL_GIGA_MAC_VER_12:
4610 case RTL_GIGA_MAC_VER_17:
4611 case RTL_GIGA_MAC_VER_18:
4612 case RTL_GIGA_MAC_VER_19:
4613 case RTL_GIGA_MAC_VER_20:
4614 case RTL_GIGA_MAC_VER_21:
4615 case RTL_GIGA_MAC_VER_22:
4616 case RTL_GIGA_MAC_VER_23:
4617 case RTL_GIGA_MAC_VER_24:
4618 case RTL_GIGA_MAC_VER_25:
4619 case RTL_GIGA_MAC_VER_26:
4620 case RTL_GIGA_MAC_VER_27:
4621 case RTL_GIGA_MAC_VER_28:
4622 case RTL_GIGA_MAC_VER_31:
4623 rtl_writephy(tp, 0x0e, 0x0000);
4624 break;
4625 default:
4626 break;
4627 }
065c27c1 4628 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
4629}
4630
4631static void r8168_phy_power_down(struct rtl8169_private *tp)
4632{
4633 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 4634 switch (tp->mac_version) {
4635 case RTL_GIGA_MAC_VER_32:
4636 case RTL_GIGA_MAC_VER_33:
beb330a4 4637 case RTL_GIGA_MAC_VER_40:
4638 case RTL_GIGA_MAC_VER_41:
01dc7fec 4639 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
4640 break;
4641
4642 case RTL_GIGA_MAC_VER_11:
4643 case RTL_GIGA_MAC_VER_12:
4644 case RTL_GIGA_MAC_VER_17:
4645 case RTL_GIGA_MAC_VER_18:
4646 case RTL_GIGA_MAC_VER_19:
4647 case RTL_GIGA_MAC_VER_20:
4648 case RTL_GIGA_MAC_VER_21:
4649 case RTL_GIGA_MAC_VER_22:
4650 case RTL_GIGA_MAC_VER_23:
4651 case RTL_GIGA_MAC_VER_24:
4652 case RTL_GIGA_MAC_VER_25:
4653 case RTL_GIGA_MAC_VER_26:
4654 case RTL_GIGA_MAC_VER_27:
4655 case RTL_GIGA_MAC_VER_28:
4656 case RTL_GIGA_MAC_VER_31:
4657 rtl_writephy(tp, 0x0e, 0x0200);
4658 default:
4659 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
4660 break;
4661 }
065c27c1 4662}
4663
4664static void r8168_pll_power_down(struct rtl8169_private *tp)
4665{
4666 void __iomem *ioaddr = tp->mmio_addr;
4667
cecb5fd7
FR		 4668 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4669 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
935e2218
CHL		 4670 tp->mac_version == RTL_GIGA_MAC_VER_31 ||
4671 tp->mac_version == RTL_GIGA_MAC_VER_49 ||
4672 tp->mac_version == RTL_GIGA_MAC_VER_50 ||
4673 tp->mac_version == RTL_GIGA_MAC_VER_51) &&
2f8c040c 4674 r8168_check_dash(tp)) {
065c27c1 4675 return;
5d2e1957 4676 }
065c27c1 4677
cecb5fd7
FR		 4678 if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
4679 tp->mac_version == RTL_GIGA_MAC_VER_24) &&
065c27c1 4680 (RTL_R16(CPlusCmd) & ASF)) {
4681 return;
4682 }
4683
01dc7fec 4684 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4685 tp->mac_version == RTL_GIGA_MAC_VER_33)
fdf6fc06 4686 rtl_ephy_write(tp, 0x19, 0xff64);
01dc7fec 4687
649b3b8c 4688 if (rtl_wol_pll_power_down(tp))
065c27c1 4689 return;
065c27c1 4690
4691 r8168_phy_power_down(tp);
4692
4693 switch (tp->mac_version) {
4694 case RTL_GIGA_MAC_VER_25:
4695 case RTL_GIGA_MAC_VER_26:
5d2e1957
HW		 4696 case RTL_GIGA_MAC_VER_27:
4697 case RTL_GIGA_MAC_VER_28:
4804b3b3 4698 case RTL_GIGA_MAC_VER_31:
01dc7fec 4699 case RTL_GIGA_MAC_VER_32:
4700 case RTL_GIGA_MAC_VER_33:
42fde737 4701 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 4702 case RTL_GIGA_MAC_VER_45:
4703 case RTL_GIGA_MAC_VER_46:
935e2218
CHL		 4704 case RTL_GIGA_MAC_VER_50:
4705 case RTL_GIGA_MAC_VER_51:
065c27c1 4706 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4707 break;
beb330a4 4708 case RTL_GIGA_MAC_VER_40:
4709 case RTL_GIGA_MAC_VER_41:
935e2218 4710 case RTL_GIGA_MAC_VER_49:
706123d0 4711 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000,
beb330a4 4712 0xfc000000, ERIAR_EXGMAC);
b8e5e6ad 4713 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
beb330a4 4714 break;
065c27c1 4715 }
4716}
4717
4718static void r8168_pll_power_up(struct rtl8169_private *tp)
4719{
4720 void __iomem *ioaddr = tp->mmio_addr;
4721
065c27c1 4722 switch (tp->mac_version) {
4723 case RTL_GIGA_MAC_VER_25:
4724 case RTL_GIGA_MAC_VER_26:
5d2e1957
HW		 4725 case RTL_GIGA_MAC_VER_27:
4726 case RTL_GIGA_MAC_VER_28:
4804b3b3 4727 case RTL_GIGA_MAC_VER_31:
01dc7fec 4728 case RTL_GIGA_MAC_VER_32:
4729 case RTL_GIGA_MAC_VER_33:
065c27c1 4730 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
4731 break;
42fde737 4732 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 4733 case RTL_GIGA_MAC_VER_45:
4734 case RTL_GIGA_MAC_VER_46:
935e2218
CHL		 4735 case RTL_GIGA_MAC_VER_50:
4736 case RTL_GIGA_MAC_VER_51:
05b9687b 4737 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
6e1d0b89 4738 break;
beb330a4 4739 case RTL_GIGA_MAC_VER_40:
4740 case RTL_GIGA_MAC_VER_41:
935e2218 4741 case RTL_GIGA_MAC_VER_49:
b8e5e6ad 4742 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
706123d0 4743 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000,
beb330a4 4744 0x00000000, ERIAR_EXGMAC);
4745 break;
065c27c1 4746 }
4747
4748 r8168_phy_power_up(tp);
4749}
4750
d58d46b5
FR		 4751static void rtl_generic_op(struct rtl8169_private *tp,
4752 void (*op)(struct rtl8169_private *))
065c27c1 4753{
4754 if (op)
4755 op(tp);
4756}
4757
4758static void rtl_pll_power_down(struct rtl8169_private *tp)
4759{
d58d46b5 4760 rtl_generic_op(tp, tp->pll_power_ops.down);
065c27c1 4761}
4762
4763static void rtl_pll_power_up(struct rtl8169_private *tp)
4764{
d58d46b5 4765 rtl_generic_op(tp, tp->pll_power_ops.up);
065c27c1 4766}
4767
baf63293 4768static void rtl_init_pll_power_ops(struct rtl8169_private *tp)
065c27c1 4769{
4770 struct pll_power_ops *ops = &tp->pll_power_ops;
4771
4772 switch (tp->mac_version) {
4773 case RTL_GIGA_MAC_VER_07:
4774 case RTL_GIGA_MAC_VER_08:
4775 case RTL_GIGA_MAC_VER_09:
4776 case RTL_GIGA_MAC_VER_10:
4777 case RTL_GIGA_MAC_VER_16:
5a5e4443
HW		 4778 case RTL_GIGA_MAC_VER_29:
4779 case RTL_GIGA_MAC_VER_30:
7e18dca1 4780 case RTL_GIGA_MAC_VER_37:
5598bfe5 4781 case RTL_GIGA_MAC_VER_39:
58152cd4 4782 case RTL_GIGA_MAC_VER_43:
6e1d0b89
CHL		 4783 case RTL_GIGA_MAC_VER_47:
4784 case RTL_GIGA_MAC_VER_48:
065c27c1 4785 ops->down = r810x_pll_power_down;
4786 ops->up = r810x_pll_power_up;
4787 break;
4788
4789 case RTL_GIGA_MAC_VER_11:
4790 case RTL_GIGA_MAC_VER_12:
4791 case RTL_GIGA_MAC_VER_17:
4792 case RTL_GIGA_MAC_VER_18:
4793 case RTL_GIGA_MAC_VER_19:
4794 case RTL_GIGA_MAC_VER_20:
4795 case RTL_GIGA_MAC_VER_21:
4796 case RTL_GIGA_MAC_VER_22:
4797 case RTL_GIGA_MAC_VER_23:
4798 case RTL_GIGA_MAC_VER_24:
4799 case RTL_GIGA_MAC_VER_25:
4800 case RTL_GIGA_MAC_VER_26:
4801 case RTL_GIGA_MAC_VER_27:
e6de30d6 4802 case RTL_GIGA_MAC_VER_28:
4804b3b3 4803 case RTL_GIGA_MAC_VER_31:
01dc7fec 4804 case RTL_GIGA_MAC_VER_32:
4805 case RTL_GIGA_MAC_VER_33:
70090424 4806 case RTL_GIGA_MAC_VER_34:
c2218925
HW		 4807 case RTL_GIGA_MAC_VER_35:
4808 case RTL_GIGA_MAC_VER_36:
b3d7b2f2 4809 case RTL_GIGA_MAC_VER_38:
c558386b
HW		 4810 case RTL_GIGA_MAC_VER_40:
4811 case RTL_GIGA_MAC_VER_41:
57538c4a 4812 case RTL_GIGA_MAC_VER_42:
45dd95c4 4813 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 4814 case RTL_GIGA_MAC_VER_45:
4815 case RTL_GIGA_MAC_VER_46:
935e2218
CHL		 4816 case RTL_GIGA_MAC_VER_49:
4817 case RTL_GIGA_MAC_VER_50:
4818 case RTL_GIGA_MAC_VER_51:
065c27c1 4819 ops->down = r8168_pll_power_down;
4820 ops->up = r8168_pll_power_up;
4821 break;
4822
4823 default:
4824 ops->down = NULL;
4825 ops->up = NULL;
4826 break;
4827 }
4828}
4829
e542a226
HW		 4830static void rtl_init_rxcfg(struct rtl8169_private *tp)
4831{
4832 void __iomem *ioaddr = tp->mmio_addr;
4833
4834 switch (tp->mac_version) {
4835 case RTL_GIGA_MAC_VER_01:
4836 case RTL_GIGA_MAC_VER_02:
4837 case RTL_GIGA_MAC_VER_03:
4838 case RTL_GIGA_MAC_VER_04:
4839 case RTL_GIGA_MAC_VER_05:
4840 case RTL_GIGA_MAC_VER_06:
4841 case RTL_GIGA_MAC_VER_10:
4842 case RTL_GIGA_MAC_VER_11:
4843 case RTL_GIGA_MAC_VER_12:
4844 case RTL_GIGA_MAC_VER_13:
4845 case RTL_GIGA_MAC_VER_14:
4846 case RTL_GIGA_MAC_VER_15:
4847 case RTL_GIGA_MAC_VER_16:
4848 case RTL_GIGA_MAC_VER_17:
4849 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
4850 break;
4851 case RTL_GIGA_MAC_VER_18:
4852 case RTL_GIGA_MAC_VER_19:
4853 case RTL_GIGA_MAC_VER_20:
4854 case RTL_GIGA_MAC_VER_21:
4855 case RTL_GIGA_MAC_VER_22:
4856 case RTL_GIGA_MAC_VER_23:
4857 case RTL_GIGA_MAC_VER_24:
eb2dc35d 4858 case RTL_GIGA_MAC_VER_34:
3ced8c95 4859 case RTL_GIGA_MAC_VER_35:
e542a226
HW		 4860 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
4861 break;
beb330a4 4862 case RTL_GIGA_MAC_VER_40:
7a9810e7
MD		 4863 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
4864 break;
beb330a4 4865 case RTL_GIGA_MAC_VER_41:
57538c4a 4866 case RTL_GIGA_MAC_VER_42:
58152cd4 4867 case RTL_GIGA_MAC_VER_43:
45dd95c4 4868 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 4869 case RTL_GIGA_MAC_VER_45:
4870 case RTL_GIGA_MAC_VER_46:
4871 case RTL_GIGA_MAC_VER_47:
4872 case RTL_GIGA_MAC_VER_48:
935e2218
CHL		 4873 case RTL_GIGA_MAC_VER_49:
4874 case RTL_GIGA_MAC_VER_50:
4875 case RTL_GIGA_MAC_VER_51:
beb330a4 4876 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST | RX_EARLY_OFF);
4877 break;
e542a226
HW		 4878 default:
4879 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
4880 break;
4881 }
4882}
4883
92fc43b4
HW		 4884static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4885{
9fba0812 4886 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
92fc43b4
HW		 4887}
4888
d58d46b5
FR		 4889static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4890{
9c5028e9 4891 void __iomem *ioaddr = tp->mmio_addr;
4892
4893 RTL_W8(Cfg9346, Cfg9346_Unlock);
d58d46b5 4894 rtl_generic_op(tp, tp->jumbo_ops.enable);
9c5028e9 4895 RTL_W8(Cfg9346, Cfg9346_Lock);
d58d46b5
FR		 4896}
4897
4898static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4899{
9c5028e9 4900 void __iomem *ioaddr = tp->mmio_addr;
4901
4902 RTL_W8(Cfg9346, Cfg9346_Unlock);
d58d46b5 4903 rtl_generic_op(tp, tp->jumbo_ops.disable);
9c5028e9 4904 RTL_W8(Cfg9346, Cfg9346_Lock);
d58d46b5
FR		 4905}
4906
4907static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
4908{
4909 void __iomem *ioaddr = tp->mmio_addr;
4910
4911 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4912 RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
4913 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
4914}
4915
4916static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
4917{
4918 void __iomem *ioaddr = tp->mmio_addr;
4919
4920 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4921 RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
4922 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
4923}
4924
4925static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
4926{
4927 void __iomem *ioaddr = tp->mmio_addr;
4928
4929 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4930}
4931
4932static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
4933{
4934 void __iomem *ioaddr = tp->mmio_addr;
4935
4936 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4937}
4938
4939static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
4940{
4941 void __iomem *ioaddr = tp->mmio_addr;
d58d46b5
FR		 4942
4943 RTL_W8(MaxTxPacketSize, 0x3f);
4944 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4945 RTL_W8(Config4, RTL_R8(Config4) | 0x01);
4512ff9f 4946 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
d58d46b5
FR		 4947}
4948
4949static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
4950{
4951 void __iomem *ioaddr = tp->mmio_addr;
d58d46b5
FR		 4952
4953 RTL_W8(MaxTxPacketSize, 0x0c);
4954 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4955 RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
4512ff9f 4956 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
d58d46b5
FR		 4957}
4958
4959static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
4960{
4961 rtl_tx_performance_tweak(tp->pci_dev,
4962 (0x2 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4963}
4964
4965static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
4966{
4967 rtl_tx_performance_tweak(tp->pci_dev,
4968 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4969}
4970
4971static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
4972{
4973 void __iomem *ioaddr = tp->mmio_addr;
4974
4975 r8168b_0_hw_jumbo_enable(tp);
4976
4977 RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
4978}
4979
4980static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
4981{
4982 void __iomem *ioaddr = tp->mmio_addr;
4983
4984 r8168b_0_hw_jumbo_disable(tp);
4985
4986 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
4987}
4988
baf63293 4989static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
d58d46b5
FR		 4990{
4991 struct jumbo_ops *ops = &tp->jumbo_ops;
4992
4993 switch (tp->mac_version) {
4994 case RTL_GIGA_MAC_VER_11:
4995 ops->disable = r8168b_0_hw_jumbo_disable;
4996 ops->enable = r8168b_0_hw_jumbo_enable;
4997 break;
4998 case RTL_GIGA_MAC_VER_12:
4999 case RTL_GIGA_MAC_VER_17:
5000 ops->disable = r8168b_1_hw_jumbo_disable;
5001 ops->enable = r8168b_1_hw_jumbo_enable;
5002 break;
5003 case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
5004 case RTL_GIGA_MAC_VER_19:
5005 case RTL_GIGA_MAC_VER_20:
5006 case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
5007 case RTL_GIGA_MAC_VER_22:
5008 case RTL_GIGA_MAC_VER_23:
5009 case RTL_GIGA_MAC_VER_24:
5010 case RTL_GIGA_MAC_VER_25:
5011 case RTL_GIGA_MAC_VER_26:
5012 ops->disable = r8168c_hw_jumbo_disable;
5013 ops->enable = r8168c_hw_jumbo_enable;
5014 break;
5015 case RTL_GIGA_MAC_VER_27:
5016 case RTL_GIGA_MAC_VER_28:
5017 ops->disable = r8168dp_hw_jumbo_disable;
5018 ops->enable = r8168dp_hw_jumbo_enable;
5019 break;
5020 case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
5021 case RTL_GIGA_MAC_VER_32:
5022 case RTL_GIGA_MAC_VER_33:
5023 case RTL_GIGA_MAC_VER_34:
5024 ops->disable = r8168e_hw_jumbo_disable;
5025 ops->enable = r8168e_hw_jumbo_enable;
5026 break;
5027
5028 /*
5029 * No action needed for jumbo frames with 8169.
5030 * No jumbo for 810x at all.
5031 */
c558386b
HW		 5032 case RTL_GIGA_MAC_VER_40:
5033 case RTL_GIGA_MAC_VER_41:
57538c4a 5034 case RTL_GIGA_MAC_VER_42:
58152cd4 5035 case RTL_GIGA_MAC_VER_43:
45dd95c4 5036 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 5037 case RTL_GIGA_MAC_VER_45:
5038 case RTL_GIGA_MAC_VER_46:
5039 case RTL_GIGA_MAC_VER_47:
5040 case RTL_GIGA_MAC_VER_48:
935e2218
CHL		 5041 case RTL_GIGA_MAC_VER_49:
5042 case RTL_GIGA_MAC_VER_50:
5043 case RTL_GIGA_MAC_VER_51:
d58d46b5
FR		 5044 default:
5045 ops->disable = NULL;
5046 ops->enable = NULL;
5047 break;
5048 }
5049}
5050
ffc46952
FR		 5051DECLARE_RTL_COND(rtl_chipcmd_cond)
5052{
5053 void __iomem *ioaddr = tp->mmio_addr;
5054
5055 return RTL_R8(ChipCmd) & CmdReset;
5056}
5057
6f43adc8
FR		 5058static void rtl_hw_reset(struct rtl8169_private *tp)
5059{
5060 void __iomem *ioaddr = tp->mmio_addr;
6f43adc8 5061
6f43adc8
FR		 5062 RTL_W8(ChipCmd, CmdReset);
5063
ffc46952 5064 rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
1e918876
FW		 5065
5066 netdev_reset_queue(tp->dev);
6f43adc8
FR		 5067}
5068
b6ffd97f 5069static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
953a12cc 5070{
b6ffd97f
FR		 5071 struct rtl_fw *rtl_fw;
5072 const char *name;
5073 int rc = -ENOMEM;
953a12cc 5074
b6ffd97f
FR		 5075 name = rtl_lookup_firmware_name(tp);
5076 if (!name)
5077 goto out_no_firmware;
953a12cc 5078
b6ffd97f
FR		 5079 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
5080 if (!rtl_fw)
5081 goto err_warn;
31bd204f 5082
b6ffd97f
FR		 5083 rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
5084 if (rc < 0)
5085 goto err_free;
5086
fd112f2e
FR		 5087 rc = rtl_check_firmware(tp, rtl_fw);
5088 if (rc < 0)
5089 goto err_release_firmware;
5090
b6ffd97f
FR		 5091 tp->rtl_fw = rtl_fw;
5092out:
5093 return;
5094
fd112f2e
FR		 5095err_release_firmware:
5096 release_firmware(rtl_fw->fw);
b6ffd97f
FR		 5097err_free:
5098 kfree(rtl_fw);
5099err_warn:
5100 netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
5101 name, rc);
5102out_no_firmware:
5103 tp->rtl_fw = NULL;
5104 goto out;
5105}
5106
5107static void rtl_request_firmware(struct rtl8169_private *tp)
5108{
5109 if (IS_ERR(tp->rtl_fw))
5110 rtl_request_uncached_firmware(tp);
953a12cc
FR		 5111}
5112
92fc43b4
HW		 5113static void rtl_rx_close(struct rtl8169_private *tp)
5114{
5115 void __iomem *ioaddr = tp->mmio_addr;
92fc43b4 5116
1687b566 5117 RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
92fc43b4
HW		 5118}
5119
ffc46952
FR		 5120DECLARE_RTL_COND(rtl_npq_cond)
5121{
5122 void __iomem *ioaddr = tp->mmio_addr;
5123
5124 return RTL_R8(TxPoll) & NPQ;
5125}
5126
5127DECLARE_RTL_COND(rtl_txcfg_empty_cond)
5128{
5129 void __iomem *ioaddr = tp->mmio_addr;
5130
5131 return RTL_R32(TxConfig) & TXCFG_EMPTY;
5132}
5133
e6de30d6 5134static void rtl8169_hw_reset(struct rtl8169_private *tp)
1da177e4 5135{
e6de30d6 5136 void __iomem *ioaddr = tp->mmio_addr;
5137
1da177e4 5138 /* Disable interrupts */
811fd301 5139 rtl8169_irq_mask_and_ack(tp);
1da177e4 5140
92fc43b4
HW		 5141 rtl_rx_close(tp);
5142
5d2e1957 5143 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4804b3b3 5144 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
5145 tp->mac_version == RTL_GIGA_MAC_VER_31) {
ffc46952 5146 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
c2218925 5147 } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
6e1d0b89
CHL		 5148 tp->mac_version == RTL_GIGA_MAC_VER_35 ||
5149 tp->mac_version == RTL_GIGA_MAC_VER_36 ||
5150 tp->mac_version == RTL_GIGA_MAC_VER_37 ||
5151 tp->mac_version == RTL_GIGA_MAC_VER_38 ||
5152 tp->mac_version == RTL_GIGA_MAC_VER_40 ||
5153 tp->mac_version == RTL_GIGA_MAC_VER_41 ||
5154 tp->mac_version == RTL_GIGA_MAC_VER_42 ||
5155 tp->mac_version == RTL_GIGA_MAC_VER_43 ||
5156 tp->mac_version == RTL_GIGA_MAC_VER_44 ||
5157 tp->mac_version == RTL_GIGA_MAC_VER_45 ||
5158 tp->mac_version == RTL_GIGA_MAC_VER_46 ||
5159 tp->mac_version == RTL_GIGA_MAC_VER_47 ||
935e2218
CHL		 5160 tp->mac_version == RTL_GIGA_MAC_VER_48 ||
5161 tp->mac_version == RTL_GIGA_MAC_VER_49 ||
5162 tp->mac_version == RTL_GIGA_MAC_VER_50 ||
5163 tp->mac_version == RTL_GIGA_MAC_VER_51) {
c2b0c1e7 5164 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
ffc46952 5165 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
92fc43b4
HW		 5166 } else {
5167 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
5168 udelay(100);
e6de30d6 5169 }
5170
92fc43b4 5171 rtl_hw_reset(tp);
1da177e4
LT		 5172}
5173
7f796d83 5174static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
9cb427b6
FR		 5175{
5176 void __iomem *ioaddr = tp->mmio_addr;
9cb427b6
FR		 5177
5178 /* Set DMA burst size and Interframe Gap Time */
5179 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
5180 (InterFrameGap << TxInterFrameGapShift));
5181}
5182
07ce4064 5183static void rtl_hw_start(struct net_device *dev)
1da177e4
LT		 5184{
5185 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 5186
07ce4064
FR		 5187 tp->hw_start(dev);
5188
da78dbff 5189 rtl_irq_enable_all(tp);
07ce4064
FR		 5190}
5191
7f796d83
FR		 5192static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
5193 void __iomem *ioaddr)
5194{
5195 /*
5196 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
5197 * register to be written before TxDescAddrLow to work.
5198 * Switching from MMIO to I/O access fixes the issue as well.
5199 */
5200 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
284901a9 5201 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
7f796d83 5202 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
284901a9 5203 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
7f796d83
FR		 5204}
5205
5206static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
5207{
5208 u16 cmd;
5209
5210 cmd = RTL_R16(CPlusCmd);
5211 RTL_W16(CPlusCmd, cmd);
5212 return cmd;
5213}
5214
fdd7b4c3 5215static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
7f796d83
FR		 5216{
5217 /* Low hurts. Let's disable the filtering. */
207d6e87 5218 RTL_W16(RxMaxSize, rx_buf_sz + 1);
7f796d83
FR		 5219}
5220
6dccd16b
FR		 5221static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
5222{
3744100e 5223 static const struct rtl_cfg2_info {
6dccd16b
FR		 5224 u32 mac_version;
5225 u32 clk;
5226 u32 val;
5227 } cfg2_info [] = {
5228 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
5229 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
5230 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
5231 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3744100e
FR		 5232 };
5233 const struct rtl_cfg2_info *p = cfg2_info;
6dccd16b
FR		 5234 unsigned int i;
5235 u32 clk;
5236
5237 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
cadf1855 5238 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
6dccd16b
FR		 5239 if ((p->mac_version == mac_version) && (p->clk == clk)) {
5240 RTL_W32(0x7c, p->val);
5241 break;
5242 }
5243 }
5244}
5245
e6b763ea
FR		 5246static void rtl_set_rx_mode(struct net_device *dev)
5247{
5248 struct rtl8169_private *tp = netdev_priv(dev);
5249 void __iomem *ioaddr = tp->mmio_addr;
5250 u32 mc_filter[2]; /* Multicast hash filter */
5251 int rx_mode;
5252 u32 tmp = 0;
5253
5254 if (dev->flags & IFF_PROMISC) {
5255 /* Unconditionally log net taps. */
5256 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
5257 rx_mode =
5258 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
5259 AcceptAllPhys;
5260 mc_filter[1] = mc_filter[0] = 0xffffffff;
5261 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
5262 (dev->flags & IFF_ALLMULTI)) {
5263 /* Too many to filter perfectly -- accept all multicasts. */
5264 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
5265 mc_filter[1] = mc_filter[0] = 0xffffffff;
5266 } else {
5267 struct netdev_hw_addr *ha;
5268
5269 rx_mode = AcceptBroadcast | AcceptMyPhys;
5270 mc_filter[1] = mc_filter[0] = 0;
5271 netdev_for_each_mc_addr(ha, dev) {
5272 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
5273 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
5274 rx_mode |= AcceptMulticast;
5275 }
5276 }
5277
5278 if (dev->features & NETIF_F_RXALL)
5279 rx_mode |= (AcceptErr | AcceptRunt);
5280
5281 tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
5282
5283 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
5284 u32 data = mc_filter[0];
5285
5286 mc_filter[0] = swab32(mc_filter[1]);
5287 mc_filter[1] = swab32(data);
5288 }
5289
0481776b
NW		 5290 if (tp->mac_version == RTL_GIGA_MAC_VER_35)
5291 mc_filter[1] = mc_filter[0] = 0xffffffff;
5292
e6b763ea
FR		 5293 RTL_W32(MAR0 + 4, mc_filter[1]);
5294 RTL_W32(MAR0 + 0, mc_filter[0]);
5295
5296 RTL_W32(RxConfig, tmp);
5297}
5298
07ce4064
FR		 5299static void rtl_hw_start_8169(struct net_device *dev)
5300{
5301 struct rtl8169_private *tp = netdev_priv(dev);
5302 void __iomem *ioaddr = tp->mmio_addr;
5303 struct pci_dev *pdev = tp->pci_dev;
07ce4064 5304
9cb427b6
FR		 5305 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
5306 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
5307 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
5308 }
5309
1da177e4 5310 RTL_W8(Cfg9346, Cfg9346_Unlock);
cecb5fd7
FR		 5311 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
5312 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5313 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
5314 tp->mac_version == RTL_GIGA_MAC_VER_04)
9cb427b6
FR		 5315 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5316
e542a226
HW		 5317 rtl_init_rxcfg(tp);
5318
f0298f81 5319 RTL_W8(EarlyTxThres, NoEarlyTx);
1da177e4 5320
6f0333b8 5321 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
1da177e4 5322
cecb5fd7
FR		 5323 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
5324 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5325 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
5326 tp->mac_version == RTL_GIGA_MAC_VER_04)
c946b304 5327 rtl_set_rx_tx_config_registers(tp);
1da177e4 5328
7f796d83 5329 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1da177e4 5330
cecb5fd7
FR		 5331 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5332 tp->mac_version == RTL_GIGA_MAC_VER_03) {
05b9687b 5333 dprintk("Set MAC Reg C+CR Offset 0xe0. "
1da177e4 5334 "Bit-3 and bit-14 MUST be 1\n");
bcf0bf90 5335 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 5336 }
5337
bcf0bf90
FR		 5338 RTL_W16(CPlusCmd, tp->cp_cmd);
5339
6dccd16b
FR		 5340 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
5341
1da177e4
LT		 5342 /*
5343 * Undocumented corner. Supposedly:
5344 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
5345 */
5346 RTL_W16(IntrMitigate, 0x0000);
5347
7f796d83 5348 rtl_set_rx_tx_desc_registers(tp, ioaddr);
9cb427b6 5349
cecb5fd7
FR		 5350 if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
5351 tp->mac_version != RTL_GIGA_MAC_VER_02 &&
5352 tp->mac_version != RTL_GIGA_MAC_VER_03 &&
5353 tp->mac_version != RTL_GIGA_MAC_VER_04) {
c946b304
FR		 5354 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5355 rtl_set_rx_tx_config_registers(tp);
5356 }
5357
1da177e4 5358 RTL_W8(Cfg9346, Cfg9346_Lock);
b518fa8e
FR		 5359
5360 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
5361 RTL_R8(IntrMask);
1da177e4
LT		 5362
5363 RTL_W32(RxMissed, 0);
5364
07ce4064 5365 rtl_set_rx_mode(dev);
1da177e4
LT		 5366
5367 /* no early-rx interrupts */
05b9687b 5368 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
07ce4064 5369}
1da177e4 5370
beb1fe18
HW		 5371static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
5372{
5373 if (tp->csi_ops.write)
52989f0e 5374 tp->csi_ops.write(tp, addr, value);
beb1fe18
HW		 5375}
5376
5377static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
5378{
52989f0e 5379 return tp->csi_ops.read ? tp->csi_ops.read(tp, addr) : ~0;
beb1fe18
HW		 5380}
5381
5382static void rtl_csi_access_enable(struct rtl8169_private *tp, u32 bits)
dacf8154
FR		 5383{
5384 u32 csi;
5385
beb1fe18
HW		 5386 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
5387 rtl_csi_write(tp, 0x070c, csi | bits);
5388}
5389
5390static void rtl_csi_access_enable_1(struct rtl8169_private *tp)
5391{
5392 rtl_csi_access_enable(tp, 0x17000000);
650e8d5d 5393}
5394
beb1fe18 5395static void rtl_csi_access_enable_2(struct rtl8169_private *tp)
e6de30d6 5396{
beb1fe18 5397 rtl_csi_access_enable(tp, 0x27000000);
e6de30d6 5398}
5399
ffc46952
FR		 5400DECLARE_RTL_COND(rtl_csiar_cond)
5401{
5402 void __iomem *ioaddr = tp->mmio_addr;
5403
5404 return RTL_R32(CSIAR) & CSIAR_FLAG;
5405}
5406
52989f0e 5407static void r8169_csi_write(struct rtl8169_private *tp, int addr, int value)
650e8d5d 5408{
52989f0e 5409 void __iomem *ioaddr = tp->mmio_addr;
beb1fe18
HW		 5410
5411 RTL_W32(CSIDR, value);
5412 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5413 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5414
ffc46952 5415 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
beb1fe18
HW		 5416}
5417
52989f0e 5418static u32 r8169_csi_read(struct rtl8169_private *tp, int addr)
beb1fe18 5419{
52989f0e 5420 void __iomem *ioaddr = tp->mmio_addr;
beb1fe18
HW		 5421
5422 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
5423 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5424
ffc46952
FR		 5425 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5426 RTL_R32(CSIDR) : ~0;
beb1fe18
HW		 5427}
5428
52989f0e 5429static void r8402_csi_write(struct rtl8169_private *tp, int addr, int value)
7e18dca1 5430{
52989f0e 5431 void __iomem *ioaddr = tp->mmio_addr;
7e18dca1
HW		 5432
5433 RTL_W32(CSIDR, value);
5434 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5435 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
5436 CSIAR_FUNC_NIC);
5437
ffc46952 5438 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
7e18dca1
HW		 5439}
5440
52989f0e 5441static u32 r8402_csi_read(struct rtl8169_private *tp, int addr)
7e18dca1 5442{
52989f0e 5443 void __iomem *ioaddr = tp->mmio_addr;
7e18dca1
HW		 5444
5445 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC |
5446 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5447
ffc46952
FR		 5448 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5449 RTL_R32(CSIDR) : ~0;
7e18dca1
HW		 5450}
5451
45dd95c4 5452static void r8411_csi_write(struct rtl8169_private *tp, int addr, int value)
5453{
5454 void __iomem *ioaddr = tp->mmio_addr;
5455
5456 RTL_W32(CSIDR, value);
5457 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5458 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
5459 CSIAR_FUNC_NIC2);
5460
5461 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
5462}
5463
5464static u32 r8411_csi_read(struct rtl8169_private *tp, int addr)
5465{
5466 void __iomem *ioaddr = tp->mmio_addr;
5467
5468 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC2 |
5469 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5470
5471 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5472 RTL_R32(CSIDR) : ~0;
5473}
5474
baf63293 5475static void rtl_init_csi_ops(struct rtl8169_private *tp)
beb1fe18
HW		 5476{
5477 struct csi_ops *ops = &tp->csi_ops;
5478
5479 switch (tp->mac_version) {
5480 case RTL_GIGA_MAC_VER_01:
5481 case RTL_GIGA_MAC_VER_02:
5482 case RTL_GIGA_MAC_VER_03:
5483 case RTL_GIGA_MAC_VER_04:
5484 case RTL_GIGA_MAC_VER_05:
5485 case RTL_GIGA_MAC_VER_06:
5486 case RTL_GIGA_MAC_VER_10:
5487 case RTL_GIGA_MAC_VER_11:
5488 case RTL_GIGA_MAC_VER_12:
5489 case RTL_GIGA_MAC_VER_13:
5490 case RTL_GIGA_MAC_VER_14:
5491 case RTL_GIGA_MAC_VER_15:
5492 case RTL_GIGA_MAC_VER_16:
5493 case RTL_GIGA_MAC_VER_17:
5494 ops->write = NULL;
5495 ops->read = NULL;
5496 break;
5497
7e18dca1 5498 case RTL_GIGA_MAC_VER_37:
b3d7b2f2 5499 case RTL_GIGA_MAC_VER_38:
7e18dca1
HW		 5500 ops->write = r8402_csi_write;
5501 ops->read = r8402_csi_read;
5502 break;
5503
45dd95c4 5504 case RTL_GIGA_MAC_VER_44:
5505 ops->write = r8411_csi_write;
5506 ops->read = r8411_csi_read;
5507 break;
5508
beb1fe18
HW		 5509 default:
5510 ops->write = r8169_csi_write;
5511 ops->read = r8169_csi_read;
5512 break;
5513 }
dacf8154
FR		 5514}
5515
5516struct ephy_info {
5517 unsigned int offset;
5518 u16 mask;
5519 u16 bits;
5520};
5521
fdf6fc06
FR		 5522static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
5523 int len)
dacf8154
FR		 5524{
5525 u16 w;
5526
5527 while (len-- > 0) {
fdf6fc06
FR		 5528 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
5529 rtl_ephy_write(tp, e->offset, w);
dacf8154
FR		 5530 e++;
5531 }
5532}
5533
b726e493
FR		 5534static void rtl_disable_clock_request(struct pci_dev *pdev)
5535{
7d7903b2
JL		 5536 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL,
5537 PCI_EXP_LNKCTL_CLKREQ_EN);
b726e493
FR		 5538}
5539
e6de30d6 5540static void rtl_enable_clock_request(struct pci_dev *pdev)
5541{
7d7903b2
JL		 5542 pcie_capability_set_word(pdev, PCI_EXP_LNKCTL,
5543 PCI_EXP_LNKCTL_CLKREQ_EN);
e6de30d6 5544}
5545
b51ecea8 5546static void rtl_pcie_state_l2l3_enable(struct rtl8169_private *tp, bool enable)
5547{
5548 void __iomem *ioaddr = tp->mmio_addr;
5549 u8 data;
5550
5551 data = RTL_R8(Config3);
5552
5553 if (enable)
5554 data |= Rdy_to_L23;
5555 else
5556 data &= ~Rdy_to_L23;
5557
5558 RTL_W8(Config3, data);
5559}
5560
b726e493
FR		 5561#define R8168_CPCMD_QUIRK_MASK (\
5562 EnableBist | \
5563 Mac_dbgo_oe | \
5564 Force_half_dup | \
5565 Force_rxflow_en | \
5566 Force_txflow_en | \
5567 Cxpl_dbg_sel | \
5568 ASF | \
5569 PktCntrDisable | \
5570 Mac_dbgo_sel)
5571
beb1fe18 5572static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
219a1e9d 5573{
beb1fe18
HW		 5574 void __iomem *ioaddr = tp->mmio_addr;
5575 struct pci_dev *pdev = tp->pci_dev;
5576
b726e493
FR		 5577 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5578
5579 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5580
faf1e785 5581 if (tp->dev->mtu <= ETH_DATA_LEN) {
5582 rtl_tx_performance_tweak(pdev, (0x5 << MAX_READ_REQUEST_SHIFT) |
5583 PCI_EXP_DEVCTL_NOSNOOP_EN);
5584 }
219a1e9d
FR		 5585}
5586
beb1fe18 5587static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
219a1e9d 5588{
beb1fe18
HW		 5589 void __iomem *ioaddr = tp->mmio_addr;
5590
5591 rtl_hw_start_8168bb(tp);
b726e493 5592
f0298f81 5593 RTL_W8(MaxTxPacketSize, TxPacketMax);
b726e493
FR		 5594
5595 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
219a1e9d
FR		 5596}
5597
beb1fe18 5598static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
219a1e9d 5599{
beb1fe18
HW		 5600 void __iomem *ioaddr = tp->mmio_addr;
5601 struct pci_dev *pdev = tp->pci_dev;
5602
b726e493
FR		 5603 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
5604
5605 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5606
faf1e785 5607 if (tp->dev->mtu <= ETH_DATA_LEN)
5608 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
b726e493
FR		 5609
5610 rtl_disable_clock_request(pdev);
5611
5612 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
219a1e9d
FR		 5613}
5614
beb1fe18 5615static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
219a1e9d 5616{
350f7596 5617 static const struct ephy_info e_info_8168cp[] = {
b726e493
FR		 5618 { 0x01, 0, 0x0001 },
5619 { 0x02, 0x0800, 0x1000 },
5620 { 0x03, 0, 0x0042 },
5621 { 0x06, 0x0080, 0x0000 },
5622 { 0x07, 0, 0x2000 }
5623 };
5624
beb1fe18 5625 rtl_csi_access_enable_2(tp);
b726e493 5626
fdf6fc06 5627 rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
b726e493 5628
beb1fe18 5629 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 5630}
5631
beb1fe18 5632static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
ef3386f0 5633{
beb1fe18
HW		 5634 void __iomem *ioaddr = tp->mmio_addr;
5635 struct pci_dev *pdev = tp->pci_dev;
5636
5637 rtl_csi_access_enable_2(tp);
ef3386f0
FR		 5638
5639 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5640
faf1e785 5641 if (tp->dev->mtu <= ETH_DATA_LEN)
5642 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
ef3386f0
FR		 5643
5644 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5645}
5646
beb1fe18 5647static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
7f3e3d3a 5648{
beb1fe18
HW		 5649 void __iomem *ioaddr = tp->mmio_addr;
5650 struct pci_dev *pdev = tp->pci_dev;
5651
5652 rtl_csi_access_enable_2(tp);
7f3e3d3a
FR		 5653
5654 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5655
5656 /* Magic. */
5657 RTL_W8(DBG_REG, 0x20);
5658
f0298f81 5659 RTL_W8(MaxTxPacketSize, TxPacketMax);
7f3e3d3a 5660
faf1e785 5661 if (tp->dev->mtu <= ETH_DATA_LEN)
5662 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
7f3e3d3a
FR		 5663
5664 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5665}
5666
beb1fe18 5667static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
219a1e9d 5668{
beb1fe18 5669 void __iomem *ioaddr = tp->mmio_addr;
350f7596 5670 static const struct ephy_info e_info_8168c_1[] = {
b726e493
FR		 5671 { 0x02, 0x0800, 0x1000 },
5672 { 0x03, 0, 0x0002 },
5673 { 0x06, 0x0080, 0x0000 }
5674 };
5675
beb1fe18 5676 rtl_csi_access_enable_2(tp);
b726e493
FR		 5677
5678 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
5679
fdf6fc06 5680 rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
b726e493 5681
beb1fe18 5682 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 5683}
5684
beb1fe18 5685static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
219a1e9d 5686{
350f7596 5687 static const struct ephy_info e_info_8168c_2[] = {
b726e493
FR		 5688 { 0x01, 0, 0x0001 },
5689 { 0x03, 0x0400, 0x0220 }
5690 };
5691
beb1fe18 5692 rtl_csi_access_enable_2(tp);
b726e493 5693
fdf6fc06 5694 rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
b726e493 5695
beb1fe18 5696 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 5697}
5698
beb1fe18 5699static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
197ff761 5700{
beb1fe18 5701 rtl_hw_start_8168c_2(tp);
197ff761
FR		 5702}
5703
beb1fe18 5704static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
6fb07058 5705{
beb1fe18 5706 rtl_csi_access_enable_2(tp);
6fb07058 5707
beb1fe18 5708 __rtl_hw_start_8168cp(tp);
6fb07058
FR		 5709}
5710
beb1fe18 5711static void rtl_hw_start_8168d(struct rtl8169_private *tp)
5b538df9 5712{
beb1fe18
HW		 5713 void __iomem *ioaddr = tp->mmio_addr;
5714 struct pci_dev *pdev = tp->pci_dev;
5715
5716 rtl_csi_access_enable_2(tp);
5b538df9
FR		 5717
5718 rtl_disable_clock_request(pdev);
5719
f0298f81 5720 RTL_W8(MaxTxPacketSize, TxPacketMax);
5b538df9 5721
faf1e785 5722 if (tp->dev->mtu <= ETH_DATA_LEN)
5723 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5b538df9
FR		 5724
5725 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5726}
5727
beb1fe18 5728static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
4804b3b3 5729{
beb1fe18
HW		 5730 void __iomem *ioaddr = tp->mmio_addr;
5731 struct pci_dev *pdev = tp->pci_dev;
5732
5733 rtl_csi_access_enable_1(tp);
4804b3b3 5734
faf1e785 5735 if (tp->dev->mtu <= ETH_DATA_LEN)
5736 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4804b3b3 5737
5738 RTL_W8(MaxTxPacketSize, TxPacketMax);
5739
5740 rtl_disable_clock_request(pdev);
5741}
5742
beb1fe18 5743static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
e6de30d6 5744{
beb1fe18
HW		 5745 void __iomem *ioaddr = tp->mmio_addr;
5746 struct pci_dev *pdev = tp->pci_dev;
e6de30d6 5747 static const struct ephy_info e_info_8168d_4[] = {
5748 { 0x0b, ~0, 0x48 },
5749 { 0x19, 0x20, 0x50 },
5750 { 0x0c, ~0, 0x20 }
5751 };
5752 int i;
5753
beb1fe18 5754 rtl_csi_access_enable_1(tp);
e6de30d6 5755
5756 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5757
5758 RTL_W8(MaxTxPacketSize, TxPacketMax);
5759
5760 for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
5761 const struct ephy_info *e = e_info_8168d_4 + i;
5762 u16 w;
5763
fdf6fc06
FR		 5764 w = rtl_ephy_read(tp, e->offset);
5765 rtl_ephy_write(tp, 0x03, (w & e->mask) | e->bits);
e6de30d6 5766 }
5767
5768 rtl_enable_clock_request(pdev);
5769}
5770
beb1fe18 5771static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
01dc7fec 5772{
beb1fe18
HW		 5773 void __iomem *ioaddr = tp->mmio_addr;
5774 struct pci_dev *pdev = tp->pci_dev;
70090424 5775 static const struct ephy_info e_info_8168e_1[] = {
01dc7fec 5776 { 0x00, 0x0200, 0x0100 },
5777 { 0x00, 0x0000, 0x0004 },
5778 { 0x06, 0x0002, 0x0001 },
5779 { 0x06, 0x0000, 0x0030 },
5780 { 0x07, 0x0000, 0x2000 },
5781 { 0x00, 0x0000, 0x0020 },
5782 { 0x03, 0x5800, 0x2000 },
5783 { 0x03, 0x0000, 0x0001 },
5784 { 0x01, 0x0800, 0x1000 },
5785 { 0x07, 0x0000, 0x4000 },
5786 { 0x1e, 0x0000, 0x2000 },
5787 { 0x19, 0xffff, 0xfe6c },
5788 { 0x0a, 0x0000, 0x0040 }
5789 };
5790
beb1fe18 5791 rtl_csi_access_enable_2(tp);
01dc7fec 5792
fdf6fc06 5793 rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
01dc7fec 5794
faf1e785 5795 if (tp->dev->mtu <= ETH_DATA_LEN)
5796 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
01dc7fec 5797
5798 RTL_W8(MaxTxPacketSize, TxPacketMax);
5799
5800 rtl_disable_clock_request(pdev);
5801
5802 /* Reset tx FIFO pointer */
cecb5fd7
FR		 5803 RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
5804 RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
01dc7fec 5805
cecb5fd7 5806 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
01dc7fec 5807}
5808
beb1fe18 5809static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
70090424 5810{
beb1fe18
HW		 5811 void __iomem *ioaddr = tp->mmio_addr;
5812 struct pci_dev *pdev = tp->pci_dev;
70090424
HW		 5813 static const struct ephy_info e_info_8168e_2[] = {
5814 { 0x09, 0x0000, 0x0080 },
5815 { 0x19, 0x0000, 0x0224 }
5816 };
5817
beb1fe18 5818 rtl_csi_access_enable_1(tp);
70090424 5819
fdf6fc06 5820 rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
70090424 5821
faf1e785 5822 if (tp->dev->mtu <= ETH_DATA_LEN)
5823 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
70090424 5824
fdf6fc06
FR		 5825 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5826 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5827 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5828 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5829 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5830 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
706123d0
CHL		 5831 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5832 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
70090424 5833
3090bd9a 5834 RTL_W8(MaxTxPacketSize, EarlySize);
70090424 5835
4521e1a9
FR		 5836 rtl_disable_clock_request(pdev);
5837
70090424
HW		 5838 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5839 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5840
5841 /* Adjust EEE LED frequency */
5842 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5843
5844 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5845 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4521e1a9 5846 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
70090424
HW		 5847}
5848
5f886e08 5849static void rtl_hw_start_8168f(struct rtl8169_private *tp)
c2218925 5850{
beb1fe18
HW		 5851 void __iomem *ioaddr = tp->mmio_addr;
5852 struct pci_dev *pdev = tp->pci_dev;
c2218925 5853
5f886e08 5854 rtl_csi_access_enable_2(tp);
c2218925
HW		 5855
5856 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5857
fdf6fc06
FR		 5858 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5859 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5860 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5861 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
706123d0
CHL		 5862 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5863 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5864 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5865 rtl_w0w1_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
fdf6fc06
FR		 5866 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5867 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
c2218925
HW		 5868
5869 RTL_W8(MaxTxPacketSize, EarlySize);
5870
4521e1a9
FR		 5871 rtl_disable_clock_request(pdev);
5872
c2218925
HW		 5873 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5874 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
c2218925 5875 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4521e1a9
FR		 5876 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
5877 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
c2218925
HW		 5878}
5879
5f886e08
HW		 5880static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
5881{
5882 void __iomem *ioaddr = tp->mmio_addr;
5883 static const struct ephy_info e_info_8168f_1[] = {
5884 { 0x06, 0x00c0, 0x0020 },
5885 { 0x08, 0x0001, 0x0002 },
5886 { 0x09, 0x0000, 0x0080 },
5887 { 0x19, 0x0000, 0x0224 }
5888 };
5889
5890 rtl_hw_start_8168f(tp);
5891
fdf6fc06 5892 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5f886e08 5893
706123d0 5894 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5f886e08
HW		 5895
5896 /* Adjust EEE LED frequency */
5897 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5898}
5899
b3d7b2f2
HW		 5900static void rtl_hw_start_8411(struct rtl8169_private *tp)
5901{
b3d7b2f2
HW		 5902 static const struct ephy_info e_info_8168f_1[] = {
5903 { 0x06, 0x00c0, 0x0020 },
5904 { 0x0f, 0xffff, 0x5200 },
5905 { 0x1e, 0x0000, 0x4000 },
5906 { 0x19, 0x0000, 0x0224 }
5907 };
5908
5909 rtl_hw_start_8168f(tp);
b51ecea8 5910 rtl_pcie_state_l2l3_enable(tp, false);
b3d7b2f2 5911
fdf6fc06 5912 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
b3d7b2f2 5913
706123d0 5914 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
b3d7b2f2
HW		 5915}
5916
c558386b
HW		 5917static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
5918{
5919 void __iomem *ioaddr = tp->mmio_addr;
5920 struct pci_dev *pdev = tp->pci_dev;
5921
beb330a4 5922 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5923
c558386b
HW		 5924 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
5925 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5926 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5927 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5928
5929 rtl_csi_access_enable_1(tp);
5930
5931 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5932
706123d0
CHL		 5933 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5934 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
beb330a4 5935 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC);
c558386b 5936
4521e1a9 5937 RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
c558386b
HW		 5938 RTL_W8(MaxTxPacketSize, EarlySize);
5939
5940 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5941 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5942
5943 /* Adjust EEE LED frequency */
5944 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5945
706123d0
CHL		 5946 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
5947 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
b51ecea8 5948
5949 rtl_pcie_state_l2l3_enable(tp, false);
c558386b
HW		 5950}
5951
57538c4a 5952static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
5953{
5954 void __iomem *ioaddr = tp->mmio_addr;
5955 static const struct ephy_info e_info_8168g_2[] = {
5956 { 0x00, 0x0000, 0x0008 },
5957 { 0x0c, 0x3df0, 0x0200 },
5958 { 0x19, 0xffff, 0xfc00 },
5959 { 0x1e, 0xffff, 0x20eb }
5960 };
5961
5962 rtl_hw_start_8168g_1(tp);
5963
5964 /* disable aspm and clock request before access ephy */
5965 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
5966 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
5967 rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2));
5968}
5969
45dd95c4 5970static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
5971{
5972 void __iomem *ioaddr = tp->mmio_addr;
5973 static const struct ephy_info e_info_8411_2[] = {
5974 { 0x00, 0x0000, 0x0008 },
5975 { 0x0c, 0x3df0, 0x0200 },
5976 { 0x0f, 0xffff, 0x5200 },
5977 { 0x19, 0x0020, 0x0000 },
5978 { 0x1e, 0x0000, 0x2000 }
5979 };
5980
5981 rtl_hw_start_8168g_1(tp);
5982
5983 /* disable aspm and clock request before access ephy */
5984 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
5985 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
5986 rtl_ephy_init(tp, e_info_8411_2, ARRAY_SIZE(e_info_8411_2));
5987}
5988
6e1d0b89
CHL		 5989static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
5990{
5991 void __iomem *ioaddr = tp->mmio_addr;
5992 struct pci_dev *pdev = tp->pci_dev;
5993 u16 rg_saw_cnt;
5994 u32 data;
5995 static const struct ephy_info e_info_8168h_1[] = {
5996 { 0x1e, 0x0800, 0x0001 },
5997 { 0x1d, 0x0000, 0x0800 },
5998 { 0x05, 0xffff, 0x2089 },
5999 { 0x06, 0xffff, 0x5881 },
6000 { 0x04, 0xffff, 0x154a },
6001 { 0x01, 0xffff, 0x068b }
6002 };
6003
6004 /* disable aspm and clock request before access ephy */
6005 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6006 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6007 rtl_ephy_init(tp, e_info_8168h_1, ARRAY_SIZE(e_info_8168h_1));
6008
6009 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6010
6011 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
6012 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
6013 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
6014 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
6015
6016 rtl_csi_access_enable_1(tp);
6017
6018 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6019
706123d0
CHL		 6020 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6021 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6e1d0b89 6022
706123d0 6023 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_1111, 0x0010, 0x00, ERIAR_EXGMAC);
6e1d0b89 6024
706123d0 6025 rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f00, 0x00, ERIAR_EXGMAC);
6e1d0b89
CHL		 6026
6027 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
6028
6e1d0b89
CHL		 6029 RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
6030 RTL_W8(MaxTxPacketSize, EarlySize);
6031
6032 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6033 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6034
6035 /* Adjust EEE LED frequency */
6036 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
6037
6038 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
6039 RTL_W8(DLLPR, RTL_R8(MISC_1) & ~PFM_D3COLD_EN);
6040
6041 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~TX_10M_PS_EN);
6042
706123d0 6043 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
6e1d0b89
CHL		 6044
6045 rtl_pcie_state_l2l3_enable(tp, false);
6046
6047 rtl_writephy(tp, 0x1f, 0x0c42);
6048 rg_saw_cnt = rtl_readphy(tp, 0x13);
6049 rtl_writephy(tp, 0x1f, 0x0000);
6050 if (rg_saw_cnt > 0) {
6051 u16 sw_cnt_1ms_ini;
6052
6053 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
6054 sw_cnt_1ms_ini &= 0x0fff;
6055 data = r8168_mac_ocp_read(tp, 0xd412);
6056 data &= 0x0fff;
6057 data |= sw_cnt_1ms_ini;
6058 r8168_mac_ocp_write(tp, 0xd412, data);
6059 }
6060
6061 data = r8168_mac_ocp_read(tp, 0xe056);
6062 data &= 0xf0;
6063 data |= 0x07;
6064 r8168_mac_ocp_write(tp, 0xe056, data);
6065
6066 data = r8168_mac_ocp_read(tp, 0xe052);
6067 data &= 0x8008;
6068 data |= 0x6000;
6069 r8168_mac_ocp_write(tp, 0xe052, data);
6070
6071 data = r8168_mac_ocp_read(tp, 0xe0d6);
6072 data &= 0x01ff;
6073 data |= 0x017f;
6074 r8168_mac_ocp_write(tp, 0xe0d6, data);
6075
6076 data = r8168_mac_ocp_read(tp, 0xd420);
6077 data &= 0x0fff;
6078 data |= 0x047f;
6079 r8168_mac_ocp_write(tp, 0xd420, data);
6080
6081 r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
6082 r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
6083 r8168_mac_ocp_write(tp, 0xc094, 0x0000);
6084 r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
6085}
6086
935e2218
CHL		 6087static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
6088{
6089 void __iomem *ioaddr = tp->mmio_addr;
6090 struct pci_dev *pdev = tp->pci_dev;
6091
6092 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6093
6094 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
6095 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x2f, ERIAR_EXGMAC);
6096 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x5f, ERIAR_EXGMAC);
6097 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
6098
6099 rtl_csi_access_enable_1(tp);
6100
6101 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6102
6103 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6104 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6105
6106 rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f80, 0x00, ERIAR_EXGMAC);
6107
6108 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
6109
935e2218
CHL		 6110 RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
6111 RTL_W8(MaxTxPacketSize, EarlySize);
6112
6113 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6114 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6115
6116 /* Adjust EEE LED frequency */
6117 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
6118
6119 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
6120
6121 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~TX_10M_PS_EN);
6122
6123 rtl_pcie_state_l2l3_enable(tp, false);
6124}
6125
6126static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
6127{
6128 void __iomem *ioaddr = tp->mmio_addr;
6129 static const struct ephy_info e_info_8168ep_1[] = {
6130 { 0x00, 0xffff, 0x10ab },
6131 { 0x06, 0xffff, 0xf030 },
6132 { 0x08, 0xffff, 0x2006 },
6133 { 0x0d, 0xffff, 0x1666 },
6134 { 0x0c, 0x3ff0, 0x0000 }
6135 };
6136
6137 /* disable aspm and clock request before access ephy */
6138 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6139 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6140 rtl_ephy_init(tp, e_info_8168ep_1, ARRAY_SIZE(e_info_8168ep_1));
6141
6142 rtl_hw_start_8168ep(tp);
6143}
6144
6145static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
6146{
6147 void __iomem *ioaddr = tp->mmio_addr;
6148 static const struct ephy_info e_info_8168ep_2[] = {
6149 { 0x00, 0xffff, 0x10a3 },
6150 { 0x19, 0xffff, 0xfc00 },
6151 { 0x1e, 0xffff, 0x20ea }
6152 };
6153
6154 /* disable aspm and clock request before access ephy */
6155 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6156 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6157 rtl_ephy_init(tp, e_info_8168ep_2, ARRAY_SIZE(e_info_8168ep_2));
6158
6159 rtl_hw_start_8168ep(tp);
6160
6161 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
6162 RTL_W8(DLLPR, RTL_R8(MISC_1) & ~PFM_D3COLD_EN);
6163}
6164
6165static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
6166{
6167 void __iomem *ioaddr = tp->mmio_addr;
6168 u32 data;
6169 static const struct ephy_info e_info_8168ep_3[] = {
6170 { 0x00, 0xffff, 0x10a3 },
6171 { 0x19, 0xffff, 0x7c00 },
6172 { 0x1e, 0xffff, 0x20eb },
6173 { 0x0d, 0xffff, 0x1666 }
6174 };
6175
6176 /* disable aspm and clock request before access ephy */
6177 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6178 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6179 rtl_ephy_init(tp, e_info_8168ep_3, ARRAY_SIZE(e_info_8168ep_3));
6180
6181 rtl_hw_start_8168ep(tp);
6182
6183 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
6184 RTL_W8(DLLPR, RTL_R8(MISC_1) & ~PFM_D3COLD_EN);
6185
6186 data = r8168_mac_ocp_read(tp, 0xd3e2);
6187 data &= 0xf000;
6188 data |= 0x0271;
6189 r8168_mac_ocp_write(tp, 0xd3e2, data);
6190
6191 data = r8168_mac_ocp_read(tp, 0xd3e4);
6192 data &= 0xff00;
6193 r8168_mac_ocp_write(tp, 0xd3e4, data);
6194
6195 data = r8168_mac_ocp_read(tp, 0xe860);
6196 data |= 0x0080;
6197 r8168_mac_ocp_write(tp, 0xe860, data);
6198}
6199
07ce4064
FR		 6200static void rtl_hw_start_8168(struct net_device *dev)
6201{
2dd99530
FR		 6202 struct rtl8169_private *tp = netdev_priv(dev);
6203 void __iomem *ioaddr = tp->mmio_addr;
6204
6205 RTL_W8(Cfg9346, Cfg9346_Unlock);
6206
f0298f81 6207 RTL_W8(MaxTxPacketSize, TxPacketMax);
2dd99530 6208
6f0333b8 6209 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
2dd99530 6210
0e485150 6211 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2dd99530
FR		 6212
6213 RTL_W16(CPlusCmd, tp->cp_cmd);
6214
0e485150 6215 RTL_W16(IntrMitigate, 0x5151);
2dd99530 6216
0e485150 6217 /* Work around for RxFIFO overflow. */
811fd301 6218 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
da78dbff
FR		 6219 tp->event_slow |= RxFIFOOver | PCSTimeout;
6220 tp->event_slow &= ~RxOverflow;
0e485150
FR		 6221 }
6222
6223 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2dd99530 6224
1a964649 6225 rtl_set_rx_tx_config_registers(tp);
2dd99530
FR		 6226
6227 RTL_R8(IntrMask);
6228
219a1e9d
FR		 6229 switch (tp->mac_version) {
6230 case RTL_GIGA_MAC_VER_11:
beb1fe18 6231 rtl_hw_start_8168bb(tp);
4804b3b3 6232 break;
219a1e9d
FR		 6233
6234 case RTL_GIGA_MAC_VER_12:
6235 case RTL_GIGA_MAC_VER_17:
beb1fe18 6236 rtl_hw_start_8168bef(tp);
4804b3b3 6237 break;
219a1e9d
FR		 6238
6239 case RTL_GIGA_MAC_VER_18:
beb1fe18 6240 rtl_hw_start_8168cp_1(tp);
4804b3b3 6241 break;
219a1e9d
FR		 6242
6243 case RTL_GIGA_MAC_VER_19:
beb1fe18 6244 rtl_hw_start_8168c_1(tp);
4804b3b3 6245 break;
219a1e9d
FR		 6246
6247 case RTL_GIGA_MAC_VER_20:
beb1fe18 6248 rtl_hw_start_8168c_2(tp);
4804b3b3 6249 break;
219a1e9d 6250
197ff761 6251 case RTL_GIGA_MAC_VER_21:
beb1fe18 6252 rtl_hw_start_8168c_3(tp);
4804b3b3 6253 break;
197ff761 6254
6fb07058 6255 case RTL_GIGA_MAC_VER_22:
beb1fe18 6256 rtl_hw_start_8168c_4(tp);
4804b3b3 6257 break;
6fb07058 6258
ef3386f0 6259 case RTL_GIGA_MAC_VER_23:
beb1fe18 6260 rtl_hw_start_8168cp_2(tp);
4804b3b3 6261 break;
ef3386f0 6262
7f3e3d3a 6263 case RTL_GIGA_MAC_VER_24:
beb1fe18 6264 rtl_hw_start_8168cp_3(tp);
4804b3b3 6265 break;
7f3e3d3a 6266
5b538df9 6267 case RTL_GIGA_MAC_VER_25:
daf9df6d 6268 case RTL_GIGA_MAC_VER_26:
6269 case RTL_GIGA_MAC_VER_27:
beb1fe18 6270 rtl_hw_start_8168d(tp);
4804b3b3 6271 break;
5b538df9 6272
e6de30d6 6273 case RTL_GIGA_MAC_VER_28:
beb1fe18 6274 rtl_hw_start_8168d_4(tp);
4804b3b3 6275 break;
cecb5fd7 6276
4804b3b3 6277 case RTL_GIGA_MAC_VER_31:
beb1fe18 6278 rtl_hw_start_8168dp(tp);
4804b3b3 6279 break;
6280
01dc7fec 6281 case RTL_GIGA_MAC_VER_32:
6282 case RTL_GIGA_MAC_VER_33:
beb1fe18 6283 rtl_hw_start_8168e_1(tp);
70090424
HW		 6284 break;
6285 case RTL_GIGA_MAC_VER_34:
beb1fe18 6286 rtl_hw_start_8168e_2(tp);
01dc7fec 6287 break;
e6de30d6 6288
c2218925
HW		 6289 case RTL_GIGA_MAC_VER_35:
6290 case RTL_GIGA_MAC_VER_36:
beb1fe18 6291 rtl_hw_start_8168f_1(tp);
c2218925
HW		 6292 break;
6293
b3d7b2f2
HW		 6294 case RTL_GIGA_MAC_VER_38:
6295 rtl_hw_start_8411(tp);
6296 break;
6297
c558386b
HW		 6298 case RTL_GIGA_MAC_VER_40:
6299 case RTL_GIGA_MAC_VER_41:
6300 rtl_hw_start_8168g_1(tp);
6301 break;
57538c4a 6302 case RTL_GIGA_MAC_VER_42:
6303 rtl_hw_start_8168g_2(tp);
6304 break;
c558386b 6305
45dd95c4 6306 case RTL_GIGA_MAC_VER_44:
6307 rtl_hw_start_8411_2(tp);
6308 break;
6309
6e1d0b89
CHL		 6310 case RTL_GIGA_MAC_VER_45:
6311 case RTL_GIGA_MAC_VER_46:
6312 rtl_hw_start_8168h_1(tp);
6313 break;
6314
935e2218
CHL		 6315 case RTL_GIGA_MAC_VER_49:
6316 rtl_hw_start_8168ep_1(tp);
6317 break;
6318
6319 case RTL_GIGA_MAC_VER_50:
6320 rtl_hw_start_8168ep_2(tp);
6321 break;
6322
6323 case RTL_GIGA_MAC_VER_51:
6324 rtl_hw_start_8168ep_3(tp);
6325 break;
6326
219a1e9d
FR		 6327 default:
6328 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
6329 dev->name, tp->mac_version);
4804b3b3 6330 break;
219a1e9d 6331 }
2dd99530 6332
1a964649 6333 RTL_W8(Cfg9346, Cfg9346_Lock);
6334
0e485150
FR		 6335 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
6336
1a964649 6337 rtl_set_rx_mode(dev);
b8363901 6338
05b9687b 6339 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
07ce4064 6340}
1da177e4 6341
2857ffb7
FR		 6342#define R810X_CPCMD_QUIRK_MASK (\
6343 EnableBist | \
6344 Mac_dbgo_oe | \
6345 Force_half_dup | \
5edcc537 6346 Force_rxflow_en | \
2857ffb7
FR		 6347 Force_txflow_en | \
6348 Cxpl_dbg_sel | \
6349 ASF | \
6350 PktCntrDisable | \
d24e9aaf 6351 Mac_dbgo_sel)
2857ffb7 6352
beb1fe18 6353static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
2857ffb7 6354{
beb1fe18
HW		 6355 void __iomem *ioaddr = tp->mmio_addr;
6356 struct pci_dev *pdev = tp->pci_dev;
350f7596 6357 static const struct ephy_info e_info_8102e_1[] = {
2857ffb7
FR		 6358 { 0x01, 0, 0x6e65 },
6359 { 0x02, 0, 0x091f },
6360 { 0x03, 0, 0xc2f9 },
6361 { 0x06, 0, 0xafb5 },
6362 { 0x07, 0, 0x0e00 },
6363 { 0x19, 0, 0xec80 },
6364 { 0x01, 0, 0x2e65 },
6365 { 0x01, 0, 0x6e65 }
6366 };
6367 u8 cfg1;
6368
beb1fe18 6369 rtl_csi_access_enable_2(tp);
2857ffb7
FR		 6370
6371 RTL_W8(DBG_REG, FIX_NAK_1);
6372
6373 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6374
6375 RTL_W8(Config1,
6376 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
6377 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
6378
6379 cfg1 = RTL_R8(Config1);
6380 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
6381 RTL_W8(Config1, cfg1 & ~LEDS0);
6382
fdf6fc06 6383 rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
2857ffb7
FR		 6384}
6385
beb1fe18 6386static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
2857ffb7 6387{
beb1fe18
HW		 6388 void __iomem *ioaddr = tp->mmio_addr;
6389 struct pci_dev *pdev = tp->pci_dev;
6390
6391 rtl_csi_access_enable_2(tp);
2857ffb7
FR		 6392
6393 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6394
6395 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
6396 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2857ffb7
FR		 6397}
6398
beb1fe18 6399static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
2857ffb7 6400{
beb1fe18 6401 rtl_hw_start_8102e_2(tp);
2857ffb7 6402
fdf6fc06 6403 rtl_ephy_write(tp, 0x03, 0xc2f9);
2857ffb7
FR		 6404}
6405
beb1fe18 6406static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5a5e4443 6407{
beb1fe18 6408 void __iomem *ioaddr = tp->mmio_addr;
5a5e4443
HW		 6409 static const struct ephy_info e_info_8105e_1[] = {
6410 { 0x07, 0, 0x4000 },
6411 { 0x19, 0, 0x0200 },
6412 { 0x19, 0, 0x0020 },
6413 { 0x1e, 0, 0x2000 },
6414 { 0x03, 0, 0x0001 },
6415 { 0x19, 0, 0x0100 },
6416 { 0x19, 0, 0x0004 },
6417 { 0x0a, 0, 0x0020 }
6418 };
6419
cecb5fd7 6420 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5a5e4443
HW		 6421 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
6422
cecb5fd7 6423 /* Disable Early Tally Counter */
5a5e4443
HW		 6424 RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
6425
6426 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
4f6b00e5 6427 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5a5e4443 6428
fdf6fc06 6429 rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
b51ecea8 6430
6431 rtl_pcie_state_l2l3_enable(tp, false);
5a5e4443
HW		 6432}
6433
beb1fe18 6434static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5a5e4443 6435{
beb1fe18 6436 rtl_hw_start_8105e_1(tp);
fdf6fc06 6437 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5a5e4443
HW		 6438}
6439
7e18dca1
HW		 6440static void rtl_hw_start_8402(struct rtl8169_private *tp)
6441{
6442 void __iomem *ioaddr = tp->mmio_addr;
6443 static const struct ephy_info e_info_8402[] = {
6444 { 0x19, 0xffff, 0xff64 },
6445 { 0x1e, 0, 0x4000 }
6446 };
6447
6448 rtl_csi_access_enable_2(tp);
6449
6450 /* Force LAN exit from ASPM if Rx/Tx are not idle */
6451 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
6452
6453 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6454 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
6455
fdf6fc06 6456 rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
7e18dca1
HW		 6457
6458 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
6459
fdf6fc06
FR		 6460 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
6461 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
706123d0
CHL		 6462 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6463 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
fdf6fc06
FR		 6464 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6465 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
706123d0 6466 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
b51ecea8 6467
6468 rtl_pcie_state_l2l3_enable(tp, false);
7e18dca1
HW		 6469}
6470
5598bfe5
HW		 6471static void rtl_hw_start_8106(struct rtl8169_private *tp)
6472{
6473 void __iomem *ioaddr = tp->mmio_addr;
6474
6475 /* Force LAN exit from ASPM if Rx/Tx are not idle */
6476 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
6477
4521e1a9 6478 RTL_W32(MISC, (RTL_R32(MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
5598bfe5
HW		 6479 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
6480 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
b51ecea8 6481
6482 rtl_pcie_state_l2l3_enable(tp, false);
5598bfe5
HW		 6483}
6484
07ce4064
FR		 6485static void rtl_hw_start_8101(struct net_device *dev)
6486{
cdf1a608
FR		 6487 struct rtl8169_private *tp = netdev_priv(dev);
6488 void __iomem *ioaddr = tp->mmio_addr;
6489 struct pci_dev *pdev = tp->pci_dev;
6490
da78dbff
FR		 6491 if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
6492 tp->event_slow &= ~RxFIFOOver;
811fd301 6493
cecb5fd7 6494 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
7d7903b2 6495 tp->mac_version == RTL_GIGA_MAC_VER_16)
8200bc72
BH		 6496 pcie_capability_set_word(pdev, PCI_EXP_DEVCTL,
6497 PCI_EXP_DEVCTL_NOSNOOP_EN);
cdf1a608 6498
d24e9aaf
HW		 6499 RTL_W8(Cfg9346, Cfg9346_Unlock);
6500
1a964649 6501 RTL_W8(MaxTxPacketSize, TxPacketMax);
6502
6503 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
6504
6505 tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
6506 RTL_W16(CPlusCmd, tp->cp_cmd);
6507
6508 rtl_set_rx_tx_desc_registers(tp, ioaddr);
6509
6510 rtl_set_rx_tx_config_registers(tp);
6511
2857ffb7
FR		 6512 switch (tp->mac_version) {
6513 case RTL_GIGA_MAC_VER_07:
beb1fe18 6514 rtl_hw_start_8102e_1(tp);
2857ffb7
FR		 6515 break;
6516
6517 case RTL_GIGA_MAC_VER_08:
beb1fe18 6518 rtl_hw_start_8102e_3(tp);
2857ffb7
FR		 6519 break;
6520
6521 case RTL_GIGA_MAC_VER_09:
beb1fe18 6522 rtl_hw_start_8102e_2(tp);
2857ffb7 6523 break;
5a5e4443
HW		 6524
6525 case RTL_GIGA_MAC_VER_29:
beb1fe18 6526 rtl_hw_start_8105e_1(tp);
5a5e4443
HW		 6527 break;
6528 case RTL_GIGA_MAC_VER_30:
beb1fe18 6529 rtl_hw_start_8105e_2(tp);
5a5e4443 6530 break;
7e18dca1
HW		 6531
6532 case RTL_GIGA_MAC_VER_37:
6533 rtl_hw_start_8402(tp);
6534 break;
5598bfe5
HW		 6535
6536 case RTL_GIGA_MAC_VER_39:
6537 rtl_hw_start_8106(tp);
6538 break;
58152cd4 6539 case RTL_GIGA_MAC_VER_43:
6540 rtl_hw_start_8168g_2(tp);
6541 break;
6e1d0b89
CHL		 6542 case RTL_GIGA_MAC_VER_47:
6543 case RTL_GIGA_MAC_VER_48:
6544 rtl_hw_start_8168h_1(tp);
6545 break;
cdf1a608
FR		 6546 }
6547
d24e9aaf 6548 RTL_W8(Cfg9346, Cfg9346_Lock);
cdf1a608 6549
cdf1a608
FR		 6550 RTL_W16(IntrMitigate, 0x0000);
6551
cdf1a608 6552 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
cdf1a608 6553
cdf1a608
FR		 6554 rtl_set_rx_mode(dev);
6555
1a964649 6556 RTL_R8(IntrMask);
6557
cdf1a608 6558 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
1da177e4
LT		 6559}
6560
6561static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
6562{
d58d46b5
FR		 6563 struct rtl8169_private *tp = netdev_priv(dev);
6564
6565 if (new_mtu < ETH_ZLEN ||
6566 new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max)
1da177e4
LT		 6567 return -EINVAL;
6568
d58d46b5
FR		 6569 if (new_mtu > ETH_DATA_LEN)
6570 rtl_hw_jumbo_enable(tp);
6571 else
6572 rtl_hw_jumbo_disable(tp);
6573
1da177e4 6574 dev->mtu = new_mtu;
350fb32a
MM		 6575 netdev_update_features(dev);
6576
323bb685 6577 return 0;
1da177e4
LT		 6578}
6579
6580static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
6581{
95e0918d 6582 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
1da177e4
LT		 6583 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
6584}
6585
6f0333b8
ED		 6586static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
6587 void **data_buff, struct RxDesc *desc)
1da177e4 6588{
48addcc9 6589 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
231aee63 6590 DMA_FROM_DEVICE);
48addcc9 6591
6f0333b8
ED		 6592 kfree(*data_buff);
6593 *data_buff = NULL;
1da177e4
LT		 6594 rtl8169_make_unusable_by_asic(desc);
6595}
6596
6597static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
6598{
6599 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
6600
6601 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
6602}
6603
6604static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
6605 u32 rx_buf_sz)
6606{
6607 desc->addr = cpu_to_le64(mapping);
6608 wmb();
6609 rtl8169_mark_to_asic(desc, rx_buf_sz);
6610}
6611
6f0333b8
ED		 6612static inline void *rtl8169_align(void *data)
6613{
6614 return (void *)ALIGN((long)data, 16);
6615}
6616
0ecbe1ca
SG		 6617static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
6618 struct RxDesc *desc)
1da177e4 6619{
6f0333b8 6620 void *data;
1da177e4 6621 dma_addr_t mapping;
48addcc9 6622 struct device *d = &tp->pci_dev->dev;
0ecbe1ca 6623 struct net_device *dev = tp->dev;
6f0333b8 6624 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
1da177e4 6625
6f0333b8
ED		 6626 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
6627 if (!data)
6628 return NULL;
e9f63f30 6629
6f0333b8
ED		 6630 if (rtl8169_align(data) != data) {
6631 kfree(data);
6632 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
6633 if (!data)
6634 return NULL;
6635 }
3eafe507 6636
48addcc9 6637 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
231aee63 6638 DMA_FROM_DEVICE);
d827d86b
SG		 6639 if (unlikely(dma_mapping_error(d, mapping))) {
6640 if (net_ratelimit())
6641 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
3eafe507 6642 goto err_out;
d827d86b 6643 }
1da177e4
LT		 6644
6645 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
6f0333b8 6646 return data;
3eafe507
SG		 6647
6648err_out:
6649 kfree(data);
6650 return NULL;
1da177e4
LT		 6651}
6652
6653static void rtl8169_rx_clear(struct rtl8169_private *tp)
6654{
07d3f51f 6655 unsigned int i;
1da177e4
LT		 6656
6657 for (i = 0; i < NUM_RX_DESC; i++) {
6f0333b8
ED		 6658 if (tp->Rx_databuff[i]) {
6659 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
1da177e4
LT		 6660 tp->RxDescArray + i);
6661 }
6662 }
6663}
6664
0ecbe1ca 6665static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
1da177e4 6666{
0ecbe1ca
SG		 6667 desc->opts1 |= cpu_to_le32(RingEnd);
6668}
5b0384f4 6669
0ecbe1ca
SG		 6670static int rtl8169_rx_fill(struct rtl8169_private *tp)
6671{
6672 unsigned int i;
1da177e4 6673
0ecbe1ca
SG		 6674 for (i = 0; i < NUM_RX_DESC; i++) {
6675 void *data;
4ae47c2d 6676
6f0333b8 6677 if (tp->Rx_databuff[i])
1da177e4 6678 continue;
bcf0bf90 6679
0ecbe1ca 6680 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
6f0333b8
ED		 6681 if (!data) {
6682 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
0ecbe1ca 6683 goto err_out;
6f0333b8
ED		 6684 }
6685 tp->Rx_databuff[i] = data;
1da177e4 6686 }
1da177e4 6687
0ecbe1ca
SG		 6688 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
6689 return 0;
6690
6691err_out:
6692 rtl8169_rx_clear(tp);
6693 return -ENOMEM;
1da177e4
LT		 6694}
6695
1da177e4
LT		 6696static int rtl8169_init_ring(struct net_device *dev)
6697{
6698 struct rtl8169_private *tp = netdev_priv(dev);
6699
6700 rtl8169_init_ring_indexes(tp);
6701
6702 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
6f0333b8 6703 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
1da177e4 6704
0ecbe1ca 6705 return rtl8169_rx_fill(tp);
1da177e4
LT		 6706}
6707
48addcc9 6708static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
1da177e4
LT		 6709 struct TxDesc *desc)
6710{
6711 unsigned int len = tx_skb->len;
6712
48addcc9
SG		 6713 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
6714
1da177e4
LT		 6715 desc->opts1 = 0x00;
6716 desc->opts2 = 0x00;
6717 desc->addr = 0x00;
6718 tx_skb->len = 0;
6719}
6720
3eafe507
SG		 6721static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
6722 unsigned int n)
1da177e4
LT		 6723{
6724 unsigned int i;
6725
3eafe507
SG		 6726 for (i = 0; i < n; i++) {
6727 unsigned int entry = (start + i) % NUM_TX_DESC;
1da177e4
LT		 6728 struct ring_info *tx_skb = tp->tx_skb + entry;
6729 unsigned int len = tx_skb->len;
6730
6731 if (len) {
6732 struct sk_buff *skb = tx_skb->skb;
6733
48addcc9 6734 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
1da177e4
LT		 6735 tp->TxDescArray + entry);
6736 if (skb) {
cac4b22f 6737 tp->dev->stats.tx_dropped++;
989c9ba1 6738 dev_kfree_skb_any(skb);
1da177e4
LT		 6739 tx_skb->skb = NULL;
6740 }
1da177e4
LT		 6741 }
6742 }
3eafe507
SG		 6743}
6744
6745static void rtl8169_tx_clear(struct rtl8169_private *tp)
6746{
6747 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
1da177e4
LT		 6748 tp->cur_tx = tp->dirty_tx = 0;
6749}
6750
4422bcd4 6751static void rtl_reset_work(struct rtl8169_private *tp)
1da177e4 6752{
c4028958 6753 struct net_device *dev = tp->dev;
56de414c 6754 int i;
1da177e4 6755
da78dbff
FR		 6756 napi_disable(&tp->napi);
6757 netif_stop_queue(dev);
6758 synchronize_sched();
1da177e4 6759
c7c2c39b 6760 rtl8169_hw_reset(tp);
6761
56de414c
FR		 6762 for (i = 0; i < NUM_RX_DESC; i++)
6763 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
6764
1da177e4 6765 rtl8169_tx_clear(tp);
c7c2c39b 6766 rtl8169_init_ring_indexes(tp);
1da177e4 6767
da78dbff 6768 napi_enable(&tp->napi);
56de414c
FR		 6769 rtl_hw_start(dev);
6770 netif_wake_queue(dev);
6771 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1da177e4
LT		 6772}
6773
6774static void rtl8169_tx_timeout(struct net_device *dev)
6775{
da78dbff
FR		 6776 struct rtl8169_private *tp = netdev_priv(dev);
6777
6778 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
1da177e4
LT		 6779}
6780
6781static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2b7b4318 6782 u32 *opts)
1da177e4
LT		 6783{
6784 struct skb_shared_info *info = skb_shinfo(skb);
6785 unsigned int cur_frag, entry;
6e1d0b89 6786 struct TxDesc *uninitialized_var(txd);
48addcc9 6787 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 6788
6789 entry = tp->cur_tx;
6790 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
9e903e08 6791 const skb_frag_t *frag = info->frags + cur_frag;
1da177e4
LT		 6792 dma_addr_t mapping;
6793 u32 status, len;
6794 void *addr;
6795
6796 entry = (entry + 1) % NUM_TX_DESC;
6797
6798 txd = tp->TxDescArray + entry;
9e903e08 6799 len = skb_frag_size(frag);
929f6189 6800 addr = skb_frag_address(frag);
48addcc9 6801 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
d827d86b
SG		 6802 if (unlikely(dma_mapping_error(d, mapping))) {
6803 if (net_ratelimit())
6804 netif_err(tp, drv, tp->dev,
6805 "Failed to map TX fragments DMA!\n");
3eafe507 6806 goto err_out;
d827d86b 6807 }
1da177e4 6808
cecb5fd7 6809 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318
FR		 6810 status = opts[0] | len |
6811 (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 6812
6813 txd->opts1 = cpu_to_le32(status);
2b7b4318 6814 txd->opts2 = cpu_to_le32(opts[1]);
1da177e4
LT		 6815 txd->addr = cpu_to_le64(mapping);
6816
6817 tp->tx_skb[entry].len = len;
6818 }
6819
6820 if (cur_frag) {
6821 tp->tx_skb[entry].skb = skb;
6822 txd->opts1 |= cpu_to_le32(LastFrag);
6823 }
6824
6825 return cur_frag;
3eafe507
SG		 6826
6827err_out:
6828 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
6829 return -EIO;
1da177e4
LT		 6830}
6831
b423e9ae 6832static bool rtl_skb_pad(struct sk_buff *skb)
6833{
6834 if (skb_padto(skb, ETH_ZLEN))
6835 return false;
6836 skb_put(skb, ETH_ZLEN - skb->len);
6837 return true;
6838}
6839
6840static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
6841{
6842 return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
6843}
6844
e974604b 6845static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
6846 struct net_device *dev);
6847/* r8169_csum_workaround()
6848 * The hw limites the value the transport offset. When the offset is out of the
6849 * range, calculate the checksum by sw.
6850 */
6851static void r8169_csum_workaround(struct rtl8169_private *tp,
6852 struct sk_buff *skb)
6853{
6854 if (skb_shinfo(skb)->gso_size) {
6855 netdev_features_t features = tp->dev->features;
6856 struct sk_buff *segs, *nskb;
6857
6858 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
6859 segs = skb_gso_segment(skb, features);
6860 if (IS_ERR(segs) || !segs)
6861 goto drop;
6862
6863 do {
6864 nskb = segs;
6865 segs = segs->next;
6866 nskb->next = NULL;
6867 rtl8169_start_xmit(nskb, tp->dev);
6868 } while (segs);
6869
6870 dev_kfree_skb(skb);
6871 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6872 if (skb_checksum_help(skb) < 0)
6873 goto drop;
6874
6875 rtl8169_start_xmit(skb, tp->dev);
6876 } else {
6877 struct net_device_stats *stats;
6878
6879drop:
6880 stats = &tp->dev->stats;
6881 stats->tx_dropped++;
6882 dev_kfree_skb(skb);
6883 }
6884}
6885
6886/* msdn_giant_send_check()
6887 * According to the document of microsoft, the TCP Pseudo Header excludes the
6888 * packet length for IPv6 TCP large packets.
6889 */
6890static int msdn_giant_send_check(struct sk_buff *skb)
6891{
6892 const struct ipv6hdr *ipv6h;
6893 struct tcphdr *th;
6894 int ret;
6895
6896 ret = skb_cow_head(skb, 0);
6897 if (ret)
6898 return ret;
6899
6900 ipv6h = ipv6_hdr(skb);
6901 th = tcp_hdr(skb);
6902
6903 th->check = 0;
6904 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
6905
6906 return ret;
6907}
6908
6909static inline __be16 get_protocol(struct sk_buff *skb)
6910{
6911 __be16 protocol;
6912
6913 if (skb->protocol == htons(ETH_P_8021Q))
6914 protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
6915 else
6916 protocol = skb->protocol;
6917
6918 return protocol;
6919}
6920
5888d3fc 6921static bool rtl8169_tso_csum_v1(struct rtl8169_private *tp,
6922 struct sk_buff *skb, u32 *opts)
1da177e4 6923{
350fb32a
MM		 6924 u32 mss = skb_shinfo(skb)->gso_size;
6925
2b7b4318
FR		 6926 if (mss) {
6927 opts[0] |= TD_LSO;
5888d3fc 6928 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
6929 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6930 const struct iphdr *ip = ip_hdr(skb);
6931
6932 if (ip->protocol == IPPROTO_TCP)
6933 opts[0] |= TD0_IP_CS | TD0_TCP_CS;
6934 else if (ip->protocol == IPPROTO_UDP)
6935 opts[0] |= TD0_IP_CS | TD0_UDP_CS;
6936 else
6937 WARN_ON_ONCE(1);
6938 }
6939
6940 return true;
6941}
6942
6943static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
6944 struct sk_buff *skb, u32 *opts)
6945{
bdfa4ed6 6946 u32 transport_offset = (u32)skb_transport_offset(skb);
5888d3fc 6947 u32 mss = skb_shinfo(skb)->gso_size;
6948
6949 if (mss) {
e974604b 6950 if (transport_offset > GTTCPHO_MAX) {
6951 netif_warn(tp, tx_err, tp->dev,
6952 "Invalid transport offset 0x%x for TSO\n",
6953 transport_offset);
6954 return false;
6955 }
6956
6957 switch (get_protocol(skb)) {
6958 case htons(ETH_P_IP):
6959 opts[0] |= TD1_GTSENV4;
6960 break;
6961
6962 case htons(ETH_P_IPV6):
6963 if (msdn_giant_send_check(skb))
6964 return false;
6965
6966 opts[0] |= TD1_GTSENV6;
6967 break;
6968
6969 default:
6970 WARN_ON_ONCE(1);
6971 break;
6972 }
6973
bdfa4ed6 6974 opts[0] |= transport_offset << GTTCPHO_SHIFT;
5888d3fc 6975 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
2b7b4318 6976 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
e974604b 6977 u8 ip_protocol;
1da177e4 6978
b423e9ae 6979 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
6980 return skb_checksum_help(skb) == 0 && rtl_skb_pad(skb);
6981
e974604b 6982 if (transport_offset > TCPHO_MAX) {
6983 netif_warn(tp, tx_err, tp->dev,
6984 "Invalid transport offset 0x%x\n",
6985 transport_offset);
6986 return false;
6987 }
6988
6989 switch (get_protocol(skb)) {
6990 case htons(ETH_P_IP):
6991 opts[1] |= TD1_IPv4_CS;
6992 ip_protocol = ip_hdr(skb)->protocol;
6993 break;
6994
6995 case htons(ETH_P_IPV6):
6996 opts[1] |= TD1_IPv6_CS;
6997 ip_protocol = ipv6_hdr(skb)->nexthdr;
6998 break;
6999
7000 default:
7001 ip_protocol = IPPROTO_RAW;
7002 break;
7003 }
7004
7005 if (ip_protocol == IPPROTO_TCP)
7006 opts[1] |= TD1_TCP_CS;
7007 else if (ip_protocol == IPPROTO_UDP)
7008 opts[1] |= TD1_UDP_CS;
2b7b4318
FR		 7009 else
7010 WARN_ON_ONCE(1);
e974604b 7011
7012 opts[1] |= transport_offset << TCPHO_SHIFT;
b423e9ae 7013 } else {
7014 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
7015 return rtl_skb_pad(skb);
1da177e4 7016 }
5888d3fc 7017
b423e9ae 7018 return true;
1da177e4
LT		 7019}
7020
61357325
SH		 7021static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
7022 struct net_device *dev)
1da177e4
LT		 7023{
7024 struct rtl8169_private *tp = netdev_priv(dev);
3eafe507 7025 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
1da177e4
LT		 7026 struct TxDesc *txd = tp->TxDescArray + entry;
7027 void __iomem *ioaddr = tp->mmio_addr;
48addcc9 7028 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 7029 dma_addr_t mapping;
7030 u32 status, len;
2b7b4318 7031 u32 opts[2];
3eafe507 7032 int frags;
5b0384f4 7033
477206a0 7034 if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
bf82c189 7035 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
3eafe507 7036 goto err_stop_0;
1da177e4
LT		 7037 }
7038
7039 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
3eafe507
SG		 7040 goto err_stop_0;
7041
b423e9ae 7042 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
7043 opts[0] = DescOwn;
7044
e974604b 7045 if (!tp->tso_csum(tp, skb, opts)) {
7046 r8169_csum_workaround(tp, skb);
7047 return NETDEV_TX_OK;
7048 }
b423e9ae 7049
3eafe507 7050 len = skb_headlen(skb);
48addcc9 7051 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
d827d86b
SG		 7052 if (unlikely(dma_mapping_error(d, mapping))) {
7053 if (net_ratelimit())
7054 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
3eafe507 7055 goto err_dma_0;
d827d86b 7056 }
3eafe507
SG		 7057
7058 tp->tx_skb[entry].len = len;
7059 txd->addr = cpu_to_le64(mapping);
1da177e4 7060
2b7b4318 7061 frags = rtl8169_xmit_frags(tp, skb, opts);
3eafe507
SG		 7062 if (frags < 0)
7063 goto err_dma_1;
7064 else if (frags)
2b7b4318 7065 opts[0] |= FirstFrag;
3eafe507 7066 else {
2b7b4318 7067 opts[0] |= FirstFrag | LastFrag;
1da177e4
LT		 7068 tp->tx_skb[entry].skb = skb;
7069 }
7070
2b7b4318
FR		 7071 txd->opts2 = cpu_to_le32(opts[1]);
7072
1e918876
FW		 7073 netdev_sent_queue(dev, skb->len);
7074
5047fb5d
RC		 7075 skb_tx_timestamp(skb);
7076
1da177e4
LT		 7077 wmb();
7078
cecb5fd7 7079 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318 7080 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 7081 txd->opts1 = cpu_to_le32(status);
7082
1da177e4
LT		 7083 tp->cur_tx += frags + 1;
7084
4c020a96 7085 wmb();
1da177e4 7086
cecb5fd7 7087 RTL_W8(TxPoll, NPQ);
1da177e4 7088
da78dbff
FR		 7089 mmiowb();
7090
477206a0 7091 if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
ae1f23fb
FR		 7092 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
7093 * not miss a ring update when it notices a stopped queue.
7094 */
7095 smp_wmb();
1da177e4 7096 netif_stop_queue(dev);
ae1f23fb
FR		 7097 /* Sync with rtl_tx:
7098 * - publish queue status and cur_tx ring index (write barrier)
7099 * - refresh dirty_tx ring index (read barrier).
7100 * May the current thread have a pessimistic view of the ring
7101 * status and forget to wake up queue, a racing rtl_tx thread
7102 * can't.
7103 */
1e874e04 7104 smp_mb();
477206a0 7105 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
1da177e4
LT		 7106 netif_wake_queue(dev);
7107 }
7108
61357325 7109 return NETDEV_TX_OK;
1da177e4 7110
3eafe507 7111err_dma_1:
48addcc9 7112 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
3eafe507 7113err_dma_0:
989c9ba1 7114 dev_kfree_skb_any(skb);
3eafe507
SG		 7115 dev->stats.tx_dropped++;
7116 return NETDEV_TX_OK;
7117
7118err_stop_0:
1da177e4 7119 netif_stop_queue(dev);
cebf8cc7 7120 dev->stats.tx_dropped++;
61357325 7121 return NETDEV_TX_BUSY;
1da177e4
LT		 7122}
7123
7124static void rtl8169_pcierr_interrupt(struct net_device *dev)
7125{
7126 struct rtl8169_private *tp = netdev_priv(dev);
7127 struct pci_dev *pdev = tp->pci_dev;
1da177e4
LT		 7128 u16 pci_status, pci_cmd;
7129
7130 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
7131 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
7132
bf82c189
JP		 7133 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
7134 pci_cmd, pci_status);
1da177e4
LT		 7135
7136 /*
7137 * The recovery sequence below admits a very elaborated explanation:
7138 * - it seems to work;
d03902b8
FR		 7139 * - I did not see what else could be done;
7140 * - it makes iop3xx happy.
1da177e4
LT		 7141 *
7142 * Feel free to adjust to your needs.
7143 */
a27993f3 7144 if (pdev->broken_parity_status)
d03902b8
FR		 7145 pci_cmd &= ~PCI_COMMAND_PARITY;
7146 else
7147 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
7148
7149 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 7150
7151 pci_write_config_word(pdev, PCI_STATUS,
7152 pci_status & (PCI_STATUS_DETECTED_PARITY |
7153 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
7154 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
7155
7156 /* The infamous DAC f*ckup only happens at boot time */
9fba0812 7157 if ((tp->cp_cmd & PCIDAC) && !tp->cur_rx) {
e6de30d6 7158 void __iomem *ioaddr = tp->mmio_addr;
7159
bf82c189 7160 netif_info(tp, intr, dev, "disabling PCI DAC\n");
1da177e4
LT		 7161 tp->cp_cmd &= ~PCIDAC;
7162 RTL_W16(CPlusCmd, tp->cp_cmd);
7163 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 7164 }
7165
e6de30d6 7166 rtl8169_hw_reset(tp);
d03902b8 7167
98ddf986 7168 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
1da177e4
LT		 7169}
7170
da78dbff 7171static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
1da177e4
LT		 7172{
7173 unsigned int dirty_tx, tx_left;
1e918876 7174 unsigned int bytes_compl = 0, pkts_compl = 0;
1da177e4 7175
1da177e4
LT		 7176 dirty_tx = tp->dirty_tx;
7177 smp_rmb();
7178 tx_left = tp->cur_tx - dirty_tx;
7179
7180 while (tx_left > 0) {
7181 unsigned int entry = dirty_tx % NUM_TX_DESC;
7182 struct ring_info *tx_skb = tp->tx_skb + entry;
1da177e4
LT		 7183 u32 status;
7184
7185 rmb();
7186 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
7187 if (status & DescOwn)
7188 break;
7189
48addcc9
SG		 7190 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
7191 tp->TxDescArray + entry);
1da177e4 7192 if (status & LastFrag) {
1e918876
FW		 7193 pkts_compl++;
7194 bytes_compl += tx_skb->skb->len;
989c9ba1 7195 dev_kfree_skb_any(tx_skb->skb);
1da177e4
LT		 7196 tx_skb->skb = NULL;
7197 }
7198 dirty_tx++;
7199 tx_left--;
7200 }
7201
7202 if (tp->dirty_tx != dirty_tx) {
1e918876
FW		 7203 netdev_completed_queue(tp->dev, pkts_compl, bytes_compl);
7204
7205 u64_stats_update_begin(&tp->tx_stats.syncp);
7206 tp->tx_stats.packets += pkts_compl;
7207 tp->tx_stats.bytes += bytes_compl;
7208 u64_stats_update_end(&tp->tx_stats.syncp);
7209
1da177e4 7210 tp->dirty_tx = dirty_tx;
ae1f23fb
FR		 7211 /* Sync with rtl8169_start_xmit:
7212 * - publish dirty_tx ring index (write barrier)
7213 * - refresh cur_tx ring index and queue status (read barrier)
7214 * May the current thread miss the stopped queue condition,
7215 * a racing xmit thread can only have a right view of the
7216 * ring status.
7217 */
1e874e04 7218 smp_mb();
1da177e4 7219 if (netif_queue_stopped(dev) &&
477206a0 7220 TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
1da177e4
LT		 7221 netif_wake_queue(dev);
7222 }
d78ae2dc
FR		 7223 /*
7224 * 8168 hack: TxPoll requests are lost when the Tx packets are
7225 * too close. Let's kick an extra TxPoll request when a burst
7226 * of start_xmit activity is detected (if it is not detected,
7227 * it is slow enough). -- FR
7228 */
da78dbff
FR		 7229 if (tp->cur_tx != dirty_tx) {
7230 void __iomem *ioaddr = tp->mmio_addr;
7231
d78ae2dc 7232 RTL_W8(TxPoll, NPQ);
da78dbff 7233 }
1da177e4
LT		 7234 }
7235}
7236
126fa4b9
FR		 7237static inline int rtl8169_fragmented_frame(u32 status)
7238{
7239 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
7240}
7241
adea1ac7 7242static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
1da177e4 7243{
1da177e4
LT		 7244 u32 status = opts1 & RxProtoMask;
7245
7246 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
d5d3ebe3 7247 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
1da177e4
LT		 7248 skb->ip_summed = CHECKSUM_UNNECESSARY;
7249 else
bc8acf2c 7250 skb_checksum_none_assert(skb);
1da177e4
LT		 7251}
7252
6f0333b8
ED		 7253static struct sk_buff *rtl8169_try_rx_copy(void *data,
7254 struct rtl8169_private *tp,
7255 int pkt_size,
7256 dma_addr_t addr)
1da177e4 7257{
b449655f 7258 struct sk_buff *skb;
48addcc9 7259 struct device *d = &tp->pci_dev->dev;
b449655f 7260
6f0333b8 7261 data = rtl8169_align(data);
48addcc9 7262 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6f0333b8
ED		 7263 prefetch(data);
7264 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
7265 if (skb)
7266 memcpy(skb->data, data, pkt_size);
48addcc9
SG		 7267 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
7268
6f0333b8 7269 return skb;
1da177e4
LT		 7270}
7271
da78dbff 7272static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
1da177e4
LT		 7273{
7274 unsigned int cur_rx, rx_left;
6f0333b8 7275 unsigned int count;
1da177e4 7276
1da177e4 7277 cur_rx = tp->cur_rx;
1da177e4 7278
9fba0812 7279 for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
1da177e4 7280 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 7281 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 7282 u32 status;
7283
7284 rmb();
e03f33af 7285 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
1da177e4
LT		 7286
7287 if (status & DescOwn)
7288 break;
4dcb7d33 7289 if (unlikely(status & RxRES)) {
bf82c189
JP		 7290 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
7291 status);
cebf8cc7 7292 dev->stats.rx_errors++;
1da177e4 7293 if (status & (RxRWT | RxRUNT))
cebf8cc7 7294 dev->stats.rx_length_errors++;
1da177e4 7295 if (status & RxCRC)
cebf8cc7 7296 dev->stats.rx_crc_errors++;
9dccf611 7297 if (status & RxFOVF) {
da78dbff 7298 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
cebf8cc7 7299 dev->stats.rx_fifo_errors++;
9dccf611 7300 }
6bbe021d
BG		 7301 if ((status & (RxRUNT | RxCRC)) &&
7302 !(status & (RxRWT | RxFOVF)) &&
7303 (dev->features & NETIF_F_RXALL))
7304 goto process_pkt;
1da177e4 7305 } else {
6f0333b8 7306 struct sk_buff *skb;
6bbe021d
BG		 7307 dma_addr_t addr;
7308 int pkt_size;
7309
7310process_pkt:
7311 addr = le64_to_cpu(desc->addr);
79d0c1d2
BG		 7312 if (likely(!(dev->features & NETIF_F_RXFCS)))
7313 pkt_size = (status & 0x00003fff) - 4;
7314 else
7315 pkt_size = status & 0x00003fff;
1da177e4 7316
126fa4b9
FR		 7317 /*
7318 * The driver does not support incoming fragmented
7319 * frames. They are seen as a symptom of over-mtu
7320 * sized frames.
7321 */
7322 if (unlikely(rtl8169_fragmented_frame(status))) {
cebf8cc7
FR		 7323 dev->stats.rx_dropped++;
7324 dev->stats.rx_length_errors++;
ce11ff5e 7325 goto release_descriptor;
126fa4b9
FR		 7326 }
7327
6f0333b8
ED		 7328 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
7329 tp, pkt_size, addr);
6f0333b8
ED		 7330 if (!skb) {
7331 dev->stats.rx_dropped++;
ce11ff5e 7332 goto release_descriptor;
1da177e4
LT		 7333 }
7334
adea1ac7 7335 rtl8169_rx_csum(skb, status);
1da177e4
LT		 7336 skb_put(skb, pkt_size);
7337 skb->protocol = eth_type_trans(skb, dev);
7338
7a8fc77b
FR		 7339 rtl8169_rx_vlan_tag(desc, skb);
7340
56de414c 7341 napi_gro_receive(&tp->napi, skb);
1da177e4 7342
8027aa24
JW		 7343 u64_stats_update_begin(&tp->rx_stats.syncp);
7344 tp->rx_stats.packets++;
7345 tp->rx_stats.bytes += pkt_size;
7346 u64_stats_update_end(&tp->rx_stats.syncp);
1da177e4 7347 }
ce11ff5e 7348release_descriptor:
7349 desc->opts2 = 0;
7350 wmb();
7351 rtl8169_mark_to_asic(desc, rx_buf_sz);
1da177e4
LT		 7352 }
7353
7354 count = cur_rx - tp->cur_rx;
7355 tp->cur_rx = cur_rx;
7356
1da177e4
LT		 7357 return count;
7358}
7359
07d3f51f 7360static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 7361{
07d3f51f 7362 struct net_device *dev = dev_instance;
1da177e4 7363 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 7364 int handled = 0;
9085cdfa 7365 u16 status;
1da177e4 7366
9085cdfa 7367 status = rtl_get_events(tp);
da78dbff
FR		 7368 if (status && status != 0xffff) {
7369 status &= RTL_EVENT_NAPI | tp->event_slow;
7370 if (status) {
7371 handled = 1;
1da177e4 7372
da78dbff
FR		 7373 rtl_irq_disable(tp);
7374 napi_schedule(&tp->napi);
f11a377b 7375 }
da78dbff
FR		 7376 }
7377 return IRQ_RETVAL(handled);
7378}
1da177e4 7379
da78dbff
FR		 7380/*
7381 * Workqueue context.
7382 */
7383static void rtl_slow_event_work(struct rtl8169_private *tp)
7384{
7385 struct net_device *dev = tp->dev;
7386 u16 status;
7387
7388 status = rtl_get_events(tp) & tp->event_slow;
7389 rtl_ack_events(tp, status);
1da177e4 7390
da78dbff
FR		 7391 if (unlikely(status & RxFIFOOver)) {
7392 switch (tp->mac_version) {
7393 /* Work around for rx fifo overflow */
7394 case RTL_GIGA_MAC_VER_11:
7395 netif_stop_queue(dev);
934714d0
FR		 7396 /* XXX - Hack alert. See rtl_task(). */
7397 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
da78dbff 7398 default:
f11a377b
DD		 7399 break;
7400 }
da78dbff 7401 }
1da177e4 7402
da78dbff
FR		 7403 if (unlikely(status & SYSErr))
7404 rtl8169_pcierr_interrupt(dev);
0e485150 7405
da78dbff
FR		 7406 if (status & LinkChg)
7407 __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true);
1da177e4 7408
7dbb4918 7409 rtl_irq_enable_all(tp);
1da177e4
LT		 7410}
7411
4422bcd4
FR		 7412static void rtl_task(struct work_struct *work)
7413{
da78dbff
FR		 7414 static const struct {
7415 int bitnr;
7416 void (*action)(struct rtl8169_private *);
7417 } rtl_work[] = {
934714d0 7418 /* XXX - keep rtl_slow_event_work() as first element. */
da78dbff
FR		 7419 { RTL_FLAG_TASK_SLOW_PENDING, rtl_slow_event_work },
7420 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work },
7421 { RTL_FLAG_TASK_PHY_PENDING, rtl_phy_work }
7422 };
4422bcd4
FR		 7423 struct rtl8169_private *tp =
7424 container_of(work, struct rtl8169_private, wk.work);
da78dbff
FR		 7425 struct net_device *dev = tp->dev;
7426 int i;
7427
7428 rtl_lock_work(tp);
7429
6c4a70c5
FR		 7430 if (!netif_running(dev) ||
7431 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
da78dbff
FR		 7432 goto out_unlock;
7433
7434 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
7435 bool pending;
7436
da78dbff 7437 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
da78dbff
FR		 7438 if (pending)
7439 rtl_work[i].action(tp);
7440 }
4422bcd4 7441
da78dbff
FR		 7442out_unlock:
7443 rtl_unlock_work(tp);
4422bcd4
FR		 7444}
7445
bea3348e 7446static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 7447{
bea3348e
SH		 7448 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
7449 struct net_device *dev = tp->dev;
da78dbff
FR		 7450 u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
7451 int work_done= 0;
7452 u16 status;
7453
7454 status = rtl_get_events(tp);
7455 rtl_ack_events(tp, status & ~tp->event_slow);
7456
7457 if (status & RTL_EVENT_NAPI_RX)
7458 work_done = rtl_rx(dev, tp, (u32) budget);
7459
7460 if (status & RTL_EVENT_NAPI_TX)
7461 rtl_tx(dev, tp);
1da177e4 7462
da78dbff
FR		 7463 if (status & tp->event_slow) {
7464 enable_mask &= ~tp->event_slow;
7465
7466 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
7467 }
1da177e4 7468
bea3348e 7469 if (work_done < budget) {
288379f0 7470 napi_complete(napi);
f11a377b 7471
da78dbff
FR		 7472 rtl_irq_enable(tp, enable_mask);
7473 mmiowb();
1da177e4
LT		 7474 }
7475
bea3348e 7476 return work_done;
1da177e4 7477}
1da177e4 7478
523a6094
FR		 7479static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
7480{
7481 struct rtl8169_private *tp = netdev_priv(dev);
7482
7483 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
7484 return;
7485
7486 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
7487 RTL_W32(RxMissed, 0);
7488}
7489
1da177e4
LT		 7490static void rtl8169_down(struct net_device *dev)
7491{
7492 struct rtl8169_private *tp = netdev_priv(dev);
7493 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 7494
4876cc1e 7495 del_timer_sync(&tp->timer);
1da177e4 7496
93dd79e8 7497 napi_disable(&tp->napi);
da78dbff 7498 netif_stop_queue(dev);
1da177e4 7499
92fc43b4 7500 rtl8169_hw_reset(tp);
323bb685
SG		 7501 /*
7502 * At this point device interrupts can not be enabled in any function,
209e5ac8
FR		 7503 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
7504 * and napi is disabled (rtl8169_poll).
323bb685 7505 */
523a6094 7506 rtl8169_rx_missed(dev, ioaddr);
1da177e4 7507
1da177e4 7508 /* Give a racing hard_start_xmit a few cycles to complete. */
da78dbff 7509 synchronize_sched();
1da177e4 7510
1da177e4
LT		 7511 rtl8169_tx_clear(tp);
7512
7513 rtl8169_rx_clear(tp);
065c27c1 7514
7515 rtl_pll_power_down(tp);
1da177e4
LT		 7516}
7517
7518static int rtl8169_close(struct net_device *dev)
7519{
7520 struct rtl8169_private *tp = netdev_priv(dev);
7521 struct pci_dev *pdev = tp->pci_dev;
7522
e1759441
RW		 7523 pm_runtime_get_sync(&pdev->dev);
7524
cecb5fd7 7525 /* Update counters before going down */
355423d0
IV		 7526 rtl8169_update_counters(dev);
7527
da78dbff 7528 rtl_lock_work(tp);
6c4a70c5 7529 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
da78dbff 7530
1da177e4 7531 rtl8169_down(dev);
da78dbff 7532 rtl_unlock_work(tp);
1da177e4 7533
4ea72445
L		 7534 cancel_work_sync(&tp->wk.work);
7535
92a7c4e7 7536 free_irq(pdev->irq, dev);
1da177e4 7537
82553bb6
SG		 7538 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
7539 tp->RxPhyAddr);
7540 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
7541 tp->TxPhyAddr);
1da177e4
LT		 7542 tp->TxDescArray = NULL;
7543 tp->RxDescArray = NULL;
7544
e1759441
RW		 7545 pm_runtime_put_sync(&pdev->dev);
7546
1da177e4
LT		 7547 return 0;
7548}
7549
dc1c00ce
FR		 7550#ifdef CONFIG_NET_POLL_CONTROLLER
7551static void rtl8169_netpoll(struct net_device *dev)
7552{
7553 struct rtl8169_private *tp = netdev_priv(dev);
7554
7555 rtl8169_interrupt(tp->pci_dev->irq, dev);
7556}
7557#endif
7558
df43ac78
FR		 7559static int rtl_open(struct net_device *dev)
7560{
7561 struct rtl8169_private *tp = netdev_priv(dev);
7562 void __iomem *ioaddr = tp->mmio_addr;
7563 struct pci_dev *pdev = tp->pci_dev;
7564 int retval = -ENOMEM;
7565
7566 pm_runtime_get_sync(&pdev->dev);
7567
7568 /*
e75d6606 7569 * Rx and Tx descriptors needs 256 bytes alignment.
df43ac78
FR		 7570 * dma_alloc_coherent provides more.
7571 */
7572 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
7573 &tp->TxPhyAddr, GFP_KERNEL);
7574 if (!tp->TxDescArray)
7575 goto err_pm_runtime_put;
7576
7577 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
7578 &tp->RxPhyAddr, GFP_KERNEL);
7579 if (!tp->RxDescArray)
7580 goto err_free_tx_0;
7581
7582 retval = rtl8169_init_ring(dev);
7583 if (retval < 0)
7584 goto err_free_rx_1;
7585
7586 INIT_WORK(&tp->wk.work, rtl_task);
7587
7588 smp_mb();
7589
7590 rtl_request_firmware(tp);
7591
92a7c4e7 7592 retval = request_irq(pdev->irq, rtl8169_interrupt,
df43ac78
FR		 7593 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
7594 dev->name, dev);
7595 if (retval < 0)
7596 goto err_release_fw_2;
7597
7598 rtl_lock_work(tp);
7599
7600 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7601
7602 napi_enable(&tp->napi);
7603
7604 rtl8169_init_phy(dev, tp);
7605
7606 __rtl8169_set_features(dev, dev->features);
7607
7608 rtl_pll_power_up(tp);
7609
7610 rtl_hw_start(dev);
7611
7612 netif_start_queue(dev);
7613
7614 rtl_unlock_work(tp);
7615
7616 tp->saved_wolopts = 0;
7617 pm_runtime_put_noidle(&pdev->dev);
7618
7619 rtl8169_check_link_status(dev, tp, ioaddr);
7620out:
7621 return retval;
7622
7623err_release_fw_2:
7624 rtl_release_firmware(tp);
7625 rtl8169_rx_clear(tp);
7626err_free_rx_1:
7627 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
7628 tp->RxPhyAddr);
7629 tp->RxDescArray = NULL;
7630err_free_tx_0:
7631 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
7632 tp->TxPhyAddr);
7633 tp->TxDescArray = NULL;
7634err_pm_runtime_put:
7635 pm_runtime_put_noidle(&pdev->dev);
7636 goto out;
7637}
7638
8027aa24
JW		 7639static struct rtnl_link_stats64 *
7640rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
1da177e4
LT		 7641{
7642 struct rtl8169_private *tp = netdev_priv(dev);
7643 void __iomem *ioaddr = tp->mmio_addr;
8027aa24 7644 unsigned int start;
1da177e4 7645
da78dbff 7646 if (netif_running(dev))
523a6094 7647 rtl8169_rx_missed(dev, ioaddr);
5b0384f4 7648
8027aa24 7649 do {
57a7744e 7650 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
8027aa24
JW		 7651 stats->rx_packets = tp->rx_stats.packets;
7652 stats->rx_bytes = tp->rx_stats.bytes;
57a7744e 7653 } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
8027aa24
JW		 7654
7655
7656 do {
57a7744e 7657 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
8027aa24
JW		 7658 stats->tx_packets = tp->tx_stats.packets;
7659 stats->tx_bytes = tp->tx_stats.bytes;
57a7744e 7660 } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
8027aa24
JW		 7661
7662 stats->rx_dropped = dev->stats.rx_dropped;
7663 stats->tx_dropped = dev->stats.tx_dropped;
7664 stats->rx_length_errors = dev->stats.rx_length_errors;
7665 stats->rx_errors = dev->stats.rx_errors;
7666 stats->rx_crc_errors = dev->stats.rx_crc_errors;
7667 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
7668 stats->rx_missed_errors = dev->stats.rx_missed_errors;
7669
7670 return stats;
1da177e4
LT		 7671}
7672
861ab440 7673static void rtl8169_net_suspend(struct net_device *dev)
5d06a99f 7674{
065c27c1 7675 struct rtl8169_private *tp = netdev_priv(dev);
7676
5d06a99f 7677 if (!netif_running(dev))
861ab440 7678 return;
5d06a99f
FR		 7679
7680 netif_device_detach(dev);
7681 netif_stop_queue(dev);
da78dbff
FR		 7682
7683 rtl_lock_work(tp);
7684 napi_disable(&tp->napi);
6c4a70c5 7685 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
da78dbff
FR		 7686 rtl_unlock_work(tp);
7687
7688 rtl_pll_power_down(tp);
861ab440
RW		 7689}
7690
7691#ifdef CONFIG_PM
7692
7693static int rtl8169_suspend(struct device *device)
7694{
7695 struct pci_dev *pdev = to_pci_dev(device);
7696 struct net_device *dev = pci_get_drvdata(pdev);
5d06a99f 7697
861ab440 7698 rtl8169_net_suspend(dev);
1371fa6d 7699
5d06a99f
FR		 7700 return 0;
7701}
7702
e1759441
RW		 7703static void __rtl8169_resume(struct net_device *dev)
7704{
065c27c1 7705 struct rtl8169_private *tp = netdev_priv(dev);
7706
e1759441 7707 netif_device_attach(dev);
065c27c1 7708
7709 rtl_pll_power_up(tp);
7710
cff4c162
AS		 7711 rtl_lock_work(tp);
7712 napi_enable(&tp->napi);
6c4a70c5 7713 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
cff4c162 7714 rtl_unlock_work(tp);
da78dbff 7715
98ddf986 7716 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
e1759441
RW		 7717}
7718
861ab440 7719static int rtl8169_resume(struct device *device)
5d06a99f 7720{
861ab440 7721 struct pci_dev *pdev = to_pci_dev(device);
5d06a99f 7722 struct net_device *dev = pci_get_drvdata(pdev);
fccec10b
SG		 7723 struct rtl8169_private *tp = netdev_priv(dev);
7724
7725 rtl8169_init_phy(dev, tp);
5d06a99f 7726
e1759441
RW		 7727 if (netif_running(dev))
7728 __rtl8169_resume(dev);
5d06a99f 7729
e1759441
RW		 7730 return 0;
7731}
7732
7733static int rtl8169_runtime_suspend(struct device *device)
7734{
7735 struct pci_dev *pdev = to_pci_dev(device);
7736 struct net_device *dev = pci_get_drvdata(pdev);
7737 struct rtl8169_private *tp = netdev_priv(dev);
7738
7739 if (!tp->TxDescArray)
7740 return 0;
7741
da78dbff 7742 rtl_lock_work(tp);
e1759441
RW		 7743 tp->saved_wolopts = __rtl8169_get_wol(tp);
7744 __rtl8169_set_wol(tp, WAKE_ANY);
da78dbff 7745 rtl_unlock_work(tp);
e1759441
RW		 7746
7747 rtl8169_net_suspend(dev);
7748
7749 return 0;
7750}
7751
7752static int rtl8169_runtime_resume(struct device *device)
7753{
7754 struct pci_dev *pdev = to_pci_dev(device);
7755 struct net_device *dev = pci_get_drvdata(pdev);
7756 struct rtl8169_private *tp = netdev_priv(dev);
7757
7758 if (!tp->TxDescArray)
7759 return 0;
7760
da78dbff 7761 rtl_lock_work(tp);
e1759441
RW		 7762 __rtl8169_set_wol(tp, tp->saved_wolopts);
7763 tp->saved_wolopts = 0;
da78dbff 7764 rtl_unlock_work(tp);
e1759441 7765
fccec10b
SG		 7766 rtl8169_init_phy(dev, tp);
7767
e1759441 7768 __rtl8169_resume(dev);
5d06a99f 7769
5d06a99f
FR		 7770 return 0;
7771}
7772
e1759441
RW		 7773static int rtl8169_runtime_idle(struct device *device)
7774{
7775 struct pci_dev *pdev = to_pci_dev(device);
7776 struct net_device *dev = pci_get_drvdata(pdev);
7777 struct rtl8169_private *tp = netdev_priv(dev);
7778
e4fbce74 7779 return tp->TxDescArray ? -EBUSY : 0;
e1759441
RW		 7780}
7781
47145210 7782static const struct dev_pm_ops rtl8169_pm_ops = {
cecb5fd7
FR		 7783 .suspend = rtl8169_suspend,
7784 .resume = rtl8169_resume,
7785 .freeze = rtl8169_suspend,
7786 .thaw = rtl8169_resume,
7787 .poweroff = rtl8169_suspend,
7788 .restore = rtl8169_resume,
7789 .runtime_suspend = rtl8169_runtime_suspend,
7790 .runtime_resume = rtl8169_runtime_resume,
7791 .runtime_idle = rtl8169_runtime_idle,
861ab440
RW		 7792};
7793
7794#define RTL8169_PM_OPS (&rtl8169_pm_ops)
7795
7796#else /* !CONFIG_PM */
7797
7798#define RTL8169_PM_OPS NULL
7799
7800#endif /* !CONFIG_PM */
7801
649b3b8c 7802static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
7803{
7804 void __iomem *ioaddr = tp->mmio_addr;
7805
7806 /* WoL fails with 8168b when the receiver is disabled. */
7807 switch (tp->mac_version) {
7808 case RTL_GIGA_MAC_VER_11:
7809 case RTL_GIGA_MAC_VER_12:
7810 case RTL_GIGA_MAC_VER_17:
7811 pci_clear_master(tp->pci_dev);
7812
7813 RTL_W8(ChipCmd, CmdRxEnb);
7814 /* PCI commit */
7815 RTL_R8(ChipCmd);
7816 break;
7817 default:
7818 break;
7819 }
7820}
7821
1765f95d
FR		 7822static void rtl_shutdown(struct pci_dev *pdev)
7823{
861ab440 7824 struct net_device *dev = pci_get_drvdata(pdev);
4bb3f522 7825 struct rtl8169_private *tp = netdev_priv(dev);
2a15cd2f 7826 struct device *d = &pdev->dev;
7827
7828 pm_runtime_get_sync(d);
861ab440
RW		 7829
7830 rtl8169_net_suspend(dev);
1765f95d 7831
cecb5fd7 7832 /* Restore original MAC address */
cc098dc7
IV		 7833 rtl_rar_set(tp, dev->perm_addr);
7834
92fc43b4 7835 rtl8169_hw_reset(tp);
4bb3f522 7836
861ab440 7837 if (system_state == SYSTEM_POWER_OFF) {
649b3b8c 7838 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
7839 rtl_wol_suspend_quirk(tp);
7840 rtl_wol_shutdown_quirk(tp);
ca52efd5 7841 }
7842
861ab440
RW		 7843 pci_wake_from_d3(pdev, true);
7844 pci_set_power_state(pdev, PCI_D3hot);
7845 }
2a15cd2f 7846
7847 pm_runtime_put_noidle(d);
861ab440 7848}
5d06a99f 7849
baf63293 7850static void rtl_remove_one(struct pci_dev *pdev)
e27566ed
FR		 7851{
7852 struct net_device *dev = pci_get_drvdata(pdev);
7853 struct rtl8169_private *tp = netdev_priv(dev);
7854
ee7a1beb
CHL		 7855 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
7856 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
935e2218
CHL		 7857 tp->mac_version == RTL_GIGA_MAC_VER_31 ||
7858 tp->mac_version == RTL_GIGA_MAC_VER_49 ||
7859 tp->mac_version == RTL_GIGA_MAC_VER_50 ||
7860 tp->mac_version == RTL_GIGA_MAC_VER_51) &&
ee7a1beb 7861 r8168_check_dash(tp)) {
e27566ed
FR		 7862 rtl8168_driver_stop(tp);
7863 }
7864
ad1be8d3
DN		 7865 netif_napi_del(&tp->napi);
7866
e27566ed
FR		 7867 unregister_netdev(dev);
7868
7869 rtl_release_firmware(tp);
7870
7871 if (pci_dev_run_wake(pdev))
7872 pm_runtime_get_noresume(&pdev->dev);
7873
7874 /* restore original MAC address */
7875 rtl_rar_set(tp, dev->perm_addr);
7876
7877 rtl_disable_msi(pdev, tp);
7878 rtl8169_release_board(pdev, dev, tp->mmio_addr);
e27566ed
FR		 7879}
7880
fa9c385e 7881static const struct net_device_ops rtl_netdev_ops = {
df43ac78 7882 .ndo_open = rtl_open,
fa9c385e
FR		 7883 .ndo_stop = rtl8169_close,
7884 .ndo_get_stats64 = rtl8169_get_stats64,
7885 .ndo_start_xmit = rtl8169_start_xmit,
7886 .ndo_tx_timeout = rtl8169_tx_timeout,
7887 .ndo_validate_addr = eth_validate_addr,
7888 .ndo_change_mtu = rtl8169_change_mtu,
7889 .ndo_fix_features = rtl8169_fix_features,
7890 .ndo_set_features = rtl8169_set_features,
7891 .ndo_set_mac_address = rtl_set_mac_address,
7892 .ndo_do_ioctl = rtl8169_ioctl,
7893 .ndo_set_rx_mode = rtl_set_rx_mode,
7894#ifdef CONFIG_NET_POLL_CONTROLLER
7895 .ndo_poll_controller = rtl8169_netpoll,
7896#endif
7897
7898};
7899
31fa8b18
FR		 7900static const struct rtl_cfg_info {
7901 void (*hw_start)(struct net_device *);
7902 unsigned int region;
7903 unsigned int align;
7904 u16 event_slow;
7905 unsigned features;
7906 u8 default_ver;
7907} rtl_cfg_infos [] = {
7908 [RTL_CFG_0] = {
7909 .hw_start = rtl_hw_start_8169,
7910 .region = 1,
7911 .align = 0,
7912 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
7913 .features = RTL_FEATURE_GMII,
7914 .default_ver = RTL_GIGA_MAC_VER_01,
7915 },
7916 [RTL_CFG_1] = {
7917 .hw_start = rtl_hw_start_8168,
7918 .region = 2,
7919 .align = 8,
7920 .event_slow = SYSErr | LinkChg | RxOverflow,
7921 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
7922 .default_ver = RTL_GIGA_MAC_VER_11,
7923 },
7924 [RTL_CFG_2] = {
7925 .hw_start = rtl_hw_start_8101,
7926 .region = 2,
7927 .align = 8,
7928 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
7929 PCSTimeout,
7930 .features = RTL_FEATURE_MSI,
7931 .default_ver = RTL_GIGA_MAC_VER_13,
7932 }
7933};
7934
7935/* Cfg9346_Unlock assumed. */
7936static unsigned rtl_try_msi(struct rtl8169_private *tp,
7937 const struct rtl_cfg_info *cfg)
7938{
7939 void __iomem *ioaddr = tp->mmio_addr;
7940 unsigned msi = 0;
7941 u8 cfg2;
7942
7943 cfg2 = RTL_R8(Config2) & ~MSIEnable;
7944 if (cfg->features & RTL_FEATURE_MSI) {
7945 if (pci_enable_msi(tp->pci_dev)) {
7946 netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
7947 } else {
7948 cfg2 |= MSIEnable;
7949 msi = RTL_FEATURE_MSI;
7950 }
7951 }
7952 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
7953 RTL_W8(Config2, cfg2);
7954 return msi;
7955}
7956
c558386b
HW		 7957DECLARE_RTL_COND(rtl_link_list_ready_cond)
7958{
7959 void __iomem *ioaddr = tp->mmio_addr;
7960
7961 return RTL_R8(MCU) & LINK_LIST_RDY;
7962}
7963
7964DECLARE_RTL_COND(rtl_rxtx_empty_cond)
7965{
7966 void __iomem *ioaddr = tp->mmio_addr;
7967
7968 return (RTL_R8(MCU) & RXTX_EMPTY) == RXTX_EMPTY;
7969}
7970
baf63293 7971static void rtl_hw_init_8168g(struct rtl8169_private *tp)
c558386b
HW		 7972{
7973 void __iomem *ioaddr = tp->mmio_addr;
7974 u32 data;
7975
7976 tp->ocp_base = OCP_STD_PHY_BASE;
7977
7978 RTL_W32(MISC, RTL_R32(MISC) | RXDV_GATED_EN);
7979
7980 if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
7981 return;
7982
7983 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
7984 return;
7985
7986 RTL_W8(ChipCmd, RTL_R8(ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
7987 msleep(1);
7988 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
7989
5f8bcce9 7990 data = r8168_mac_ocp_read(tp, 0xe8de);
c558386b
HW		 7991 data &= ~(1 << 14);
7992 r8168_mac_ocp_write(tp, 0xe8de, data);
7993
7994 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
7995 return;
7996
5f8bcce9 7997 data = r8168_mac_ocp_read(tp, 0xe8de);
c558386b
HW		 7998 data |= (1 << 15);
7999 r8168_mac_ocp_write(tp, 0xe8de, data);
8000
8001 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
8002 return;
8003}
8004
baf63293 8005static void rtl_hw_initialize(struct rtl8169_private *tp)
c558386b
HW		 8006{
8007 switch (tp->mac_version) {
8008 case RTL_GIGA_MAC_VER_40:
8009 case RTL_GIGA_MAC_VER_41:
57538c4a 8010 case RTL_GIGA_MAC_VER_42:
58152cd4 8011 case RTL_GIGA_MAC_VER_43:
45dd95c4 8012 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 8013 case RTL_GIGA_MAC_VER_45:
8014 case RTL_GIGA_MAC_VER_46:
8015 case RTL_GIGA_MAC_VER_47:
8016 case RTL_GIGA_MAC_VER_48:
935e2218
CHL		 8017 case RTL_GIGA_MAC_VER_49:
8018 case RTL_GIGA_MAC_VER_50:
8019 case RTL_GIGA_MAC_VER_51:
c558386b
HW		 8020 rtl_hw_init_8168g(tp);
8021 break;
8022
8023 default:
8024 break;
8025 }
8026}
8027
929a031d 8028static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3b6cf25d
FR		 8029{
8030 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
8031 const unsigned int region = cfg->region;
8032 struct rtl8169_private *tp;
8033 struct mii_if_info *mii;
8034 struct net_device *dev;
8035 void __iomem *ioaddr;
8036 int chipset, i;
8037 int rc;
8038
8039 if (netif_msg_drv(&debug)) {
8040 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
8041 MODULENAME, RTL8169_VERSION);
8042 }
8043
8044 dev = alloc_etherdev(sizeof (*tp));
8045 if (!dev) {
8046 rc = -ENOMEM;
8047 goto out;
8048 }
8049
8050 SET_NETDEV_DEV(dev, &pdev->dev);
fa9c385e 8051 dev->netdev_ops = &rtl_netdev_ops;
3b6cf25d
FR		 8052 tp = netdev_priv(dev);
8053 tp->dev = dev;
8054 tp->pci_dev = pdev;
8055 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
8056
8057 mii = &tp->mii;
8058 mii->dev = dev;
8059 mii->mdio_read = rtl_mdio_read;
8060 mii->mdio_write = rtl_mdio_write;
8061 mii->phy_id_mask = 0x1f;
8062 mii->reg_num_mask = 0x1f;
8063 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
8064
8065 /* disable ASPM completely as that cause random device stop working
8066 * problems as well as full system hangs for some PCIe devices users */
8067 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
8068 PCIE_LINK_STATE_CLKPM);
8069
8070 /* enable device (incl. PCI PM wakeup and hotplug setup) */
8071 rc = pci_enable_device(pdev);
8072 if (rc < 0) {
8073 netif_err(tp, probe, dev, "enable failure\n");
8074 goto err_out_free_dev_1;
8075 }
8076
8077 if (pci_set_mwi(pdev) < 0)
8078 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
8079
8080 /* make sure PCI base addr 1 is MMIO */
8081 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
8082 netif_err(tp, probe, dev,
8083 "region #%d not an MMIO resource, aborting\n",
8084 region);
8085 rc = -ENODEV;
8086 goto err_out_mwi_2;
8087 }
8088
8089 /* check for weird/broken PCI region reporting */
8090 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
8091 netif_err(tp, probe, dev,
8092 "Invalid PCI region size(s), aborting\n");
8093 rc = -ENODEV;
8094 goto err_out_mwi_2;
8095 }
8096
8097 rc = pci_request_regions(pdev, MODULENAME);
8098 if (rc < 0) {
8099 netif_err(tp, probe, dev, "could not request regions\n");
8100 goto err_out_mwi_2;
8101 }
8102
929a031d 8103 tp->cp_cmd = 0;
3b6cf25d
FR		 8104
8105 if ((sizeof(dma_addr_t) > 4) &&
8106 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
8107 tp->cp_cmd |= PCIDAC;
8108 dev->features |= NETIF_F_HIGHDMA;
8109 } else {
8110 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
8111 if (rc < 0) {
8112 netif_err(tp, probe, dev, "DMA configuration failed\n");
8113 goto err_out_free_res_3;
8114 }
8115 }
8116
8117 /* ioremap MMIO region */
8118 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
8119 if (!ioaddr) {
8120 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
8121 rc = -EIO;
8122 goto err_out_free_res_3;
8123 }
8124 tp->mmio_addr = ioaddr;
8125
8126 if (!pci_is_pcie(pdev))
8127 netif_info(tp, probe, dev, "not PCI Express\n");
8128
8129 /* Identify chip attached to board */
8130 rtl8169_get_mac_version(tp, dev, cfg->default_ver);
8131
8132 rtl_init_rxcfg(tp);
8133
8134 rtl_irq_disable(tp);
8135
c558386b
HW		 8136 rtl_hw_initialize(tp);
8137
3b6cf25d
FR		 8138 rtl_hw_reset(tp);
8139
8140 rtl_ack_events(tp, 0xffff);
8141
8142 pci_set_master(pdev);
8143
3b6cf25d
FR		 8144 rtl_init_mdio_ops(tp);
8145 rtl_init_pll_power_ops(tp);
8146 rtl_init_jumbo_ops(tp);
beb1fe18 8147 rtl_init_csi_ops(tp);
3b6cf25d
FR		 8148
8149 rtl8169_print_mac_version(tp);
8150
8151 chipset = tp->mac_version;
8152 tp->txd_version = rtl_chip_infos[chipset].txd_version;
8153
8154 RTL_W8(Cfg9346, Cfg9346_Unlock);
8155 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
8f9d5138 8156 RTL_W8(Config5, RTL_R8(Config5) & (BWF | MWF | UWF | LanWake | PMEStatus));
6e1d0b89 8157 switch (tp->mac_version) {
ac85bcdb
CHL		 8158 case RTL_GIGA_MAC_VER_34:
8159 case RTL_GIGA_MAC_VER_35:
8160 case RTL_GIGA_MAC_VER_36:
8161 case RTL_GIGA_MAC_VER_37:
8162 case RTL_GIGA_MAC_VER_38:
8163 case RTL_GIGA_MAC_VER_40:
8164 case RTL_GIGA_MAC_VER_41:
8165 case RTL_GIGA_MAC_VER_42:
8166 case RTL_GIGA_MAC_VER_43:
8167 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 8168 case RTL_GIGA_MAC_VER_45:
8169 case RTL_GIGA_MAC_VER_46:
ac85bcdb
CHL		 8170 case RTL_GIGA_MAC_VER_47:
8171 case RTL_GIGA_MAC_VER_48:
935e2218
CHL		 8172 case RTL_GIGA_MAC_VER_49:
8173 case RTL_GIGA_MAC_VER_50:
8174 case RTL_GIGA_MAC_VER_51:
6e1d0b89
CHL		 8175 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
8176 tp->features |= RTL_FEATURE_WOL;
8177 if ((RTL_R8(Config3) & LinkUp) != 0)
8178 tp->features |= RTL_FEATURE_WOL;
8179 break;
8180 default:
8181 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
8182 tp->features |= RTL_FEATURE_WOL;
8183 break;
8184 }
3b6cf25d
FR		 8185 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
8186 tp->features |= RTL_FEATURE_WOL;
8187 tp->features |= rtl_try_msi(tp, cfg);
8188 RTL_W8(Cfg9346, Cfg9346_Lock);
8189
8190 if (rtl_tbi_enabled(tp)) {
8191 tp->set_speed = rtl8169_set_speed_tbi;
8192 tp->get_settings = rtl8169_gset_tbi;
8193 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
8194 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
8195 tp->link_ok = rtl8169_tbi_link_ok;
8196 tp->do_ioctl = rtl_tbi_ioctl;
8197 } else {
8198 tp->set_speed = rtl8169_set_speed_xmii;
8199 tp->get_settings = rtl8169_gset_xmii;
8200 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
8201 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
8202 tp->link_ok = rtl8169_xmii_link_ok;
8203 tp->do_ioctl = rtl_xmii_ioctl;
8204 }
8205
8206 mutex_init(&tp->wk.mutex);
340fea3d
KM		 8207 u64_stats_init(&tp->rx_stats.syncp);
8208 u64_stats_init(&tp->tx_stats.syncp);
3b6cf25d
FR		 8209
8210 /* Get MAC address */
89cceb27
CHL		 8211 if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
8212 tp->mac_version == RTL_GIGA_MAC_VER_36 ||
8213 tp->mac_version == RTL_GIGA_MAC_VER_37 ||
8214 tp->mac_version == RTL_GIGA_MAC_VER_38 ||
8215 tp->mac_version == RTL_GIGA_MAC_VER_40 ||
8216 tp->mac_version == RTL_GIGA_MAC_VER_41 ||
8217 tp->mac_version == RTL_GIGA_MAC_VER_42 ||
8218 tp->mac_version == RTL_GIGA_MAC_VER_43 ||
8219 tp->mac_version == RTL_GIGA_MAC_VER_44 ||
8220 tp->mac_version == RTL_GIGA_MAC_VER_45 ||
6e1d0b89
CHL		 8221 tp->mac_version == RTL_GIGA_MAC_VER_46 ||
8222 tp->mac_version == RTL_GIGA_MAC_VER_47 ||
935e2218
CHL		 8223 tp->mac_version == RTL_GIGA_MAC_VER_48 ||
8224 tp->mac_version == RTL_GIGA_MAC_VER_49 ||
8225 tp->mac_version == RTL_GIGA_MAC_VER_50 ||
8226 tp->mac_version == RTL_GIGA_MAC_VER_51) {
6e1d0b89
CHL		 8227 u16 mac_addr[3];
8228
05b9687b
CHL		 8229 *(u32 *)&mac_addr[0] = rtl_eri_read(tp, 0xe0, ERIAR_EXGMAC);
8230 *(u16 *)&mac_addr[2] = rtl_eri_read(tp, 0xe4, ERIAR_EXGMAC);
6e1d0b89
CHL		 8231
8232 if (is_valid_ether_addr((u8 *)mac_addr))
8233 rtl_rar_set(tp, (u8 *)mac_addr);
8234 }
3b6cf25d
FR		 8235 for (i = 0; i < ETH_ALEN; i++)
8236 dev->dev_addr[i] = RTL_R8(MAC0 + i);
3b6cf25d 8237
7ad24ea4 8238 dev->ethtool_ops = &rtl8169_ethtool_ops;
3b6cf25d 8239 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3b6cf25d
FR		 8240
8241 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
8242
8243 /* don't enable SG, IP_CSUM and TSO by default - it might not work
8244 * properly for all devices */
8245 dev->features |= NETIF_F_RXCSUM |
f646968f 8246 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
3b6cf25d
FR		 8247
8248 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
f646968f
PM		 8249 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
8250 NETIF_F_HW_VLAN_CTAG_RX;
3b6cf25d
FR		 8251 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
8252 NETIF_F_HIGHDMA;
8253
929a031d 8254 tp->cp_cmd |= RxChkSum | RxVlan;
8255
8256 /*
8257 * Pretend we are using VLANs; This bypasses a nasty bug where
8258 * Interrupts stop flowing on high load on 8110SCd controllers.
8259 */
3b6cf25d 8260 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
929a031d 8261 /* Disallow toggling */
f646968f 8262 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3b6cf25d 8263
5888d3fc 8264 if (tp->txd_version == RTL_TD_0)
8265 tp->tso_csum = rtl8169_tso_csum_v1;
e974604b 8266 else if (tp->txd_version == RTL_TD_1) {
5888d3fc 8267 tp->tso_csum = rtl8169_tso_csum_v2;
e974604b 8268 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
8269 } else
5888d3fc 8270 WARN_ON_ONCE(1);
8271
3b6cf25d
FR		 8272 dev->hw_features |= NETIF_F_RXALL;
8273 dev->hw_features |= NETIF_F_RXFCS;
8274
8275 tp->hw_start = cfg->hw_start;
8276 tp->event_slow = cfg->event_slow;
8277
8278 tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
8279 ~(RxBOVF | RxFOVF) : ~0;
8280
8281 init_timer(&tp->timer);
8282 tp->timer.data = (unsigned long) dev;
8283 tp->timer.function = rtl8169_phy_timer;
8284
8285 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
8286
8287 rc = register_netdev(dev);
8288 if (rc < 0)
8289 goto err_out_msi_4;
8290
8291 pci_set_drvdata(pdev, dev);
8292
92a7c4e7
FR		 8293 netif_info(tp, probe, dev, "%s at 0x%p, %pM, XID %08x IRQ %d\n",
8294 rtl_chip_infos[chipset].name, ioaddr, dev->dev_addr,
8295 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), pdev->irq);
3b6cf25d
FR		 8296 if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
8297 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
8298 "tx checksumming: %s]\n",
8299 rtl_chip_infos[chipset].jumbo_max,
8300 rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
8301 }
8302
ee7a1beb
CHL		 8303 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
8304 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
935e2218
CHL		 8305 tp->mac_version == RTL_GIGA_MAC_VER_31 ||
8306 tp->mac_version == RTL_GIGA_MAC_VER_49 ||
8307 tp->mac_version == RTL_GIGA_MAC_VER_50 ||
8308 tp->mac_version == RTL_GIGA_MAC_VER_51) &&
ee7a1beb 8309 r8168_check_dash(tp)) {
3b6cf25d
FR		 8310 rtl8168_driver_start(tp);
8311 }
8312
8313 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
8314
8315 if (pci_dev_run_wake(pdev))
8316 pm_runtime_put_noidle(&pdev->dev);
8317
8318 netif_carrier_off(dev);
8319
8320out:
8321 return rc;
8322
8323err_out_msi_4:
ad1be8d3 8324 netif_napi_del(&tp->napi);
3b6cf25d
FR		 8325 rtl_disable_msi(pdev, tp);
8326 iounmap(ioaddr);
8327err_out_free_res_3:
8328 pci_release_regions(pdev);
8329err_out_mwi_2:
8330 pci_clear_mwi(pdev);
8331 pci_disable_device(pdev);
8332err_out_free_dev_1:
8333 free_netdev(dev);
8334 goto out;
8335}
8336
1da177e4
LT		 8337static struct pci_driver rtl8169_pci_driver = {
8338 .name = MODULENAME,
8339 .id_table = rtl8169_pci_tbl,
3b6cf25d 8340 .probe = rtl_init_one,
baf63293 8341 .remove = rtl_remove_one,
1765f95d 8342 .shutdown = rtl_shutdown,
861ab440 8343 .driver.pm = RTL8169_PM_OPS,
1da177e4
LT		 8344};
8345
3eeb7da9 8346module_pci_driver(rtl8169_pci_driver);
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