]>
Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
07d3f51f FR |
2 | * r8169.c: RealTek 8169/8168/8101 ethernet driver. |
3 | * | |
4 | * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw> | |
5 | * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com> | |
6 | * Copyright (c) a lot of people too. Please respect their work. | |
7 | * | |
8 | * See MAINTAINERS file for support contact information. | |
1da177e4 LT |
9 | */ |
10 | ||
11 | #include <linux/module.h> | |
12 | #include <linux/moduleparam.h> | |
13 | #include <linux/pci.h> | |
14 | #include <linux/netdevice.h> | |
15 | #include <linux/etherdevice.h> | |
16 | #include <linux/delay.h> | |
17 | #include <linux/ethtool.h> | |
18 | #include <linux/mii.h> | |
19 | #include <linux/if_vlan.h> | |
20 | #include <linux/crc32.h> | |
21 | #include <linux/in.h> | |
22 | #include <linux/ip.h> | |
23 | #include <linux/tcp.h> | |
a6b7a407 | 24 | #include <linux/interrupt.h> |
1da177e4 | 25 | #include <linux/dma-mapping.h> |
e1759441 | 26 | #include <linux/pm_runtime.h> |
bca03d5f | 27 | #include <linux/firmware.h> |
ba04c7c9 | 28 | #include <linux/pci-aspm.h> |
70c71606 | 29 | #include <linux/prefetch.h> |
e974604b | 30 | #include <linux/ipv6.h> |
31 | #include <net/ip6_checksum.h> | |
1da177e4 LT |
32 | |
33 | #include <asm/io.h> | |
34 | #include <asm/irq.h> | |
35 | ||
865c652d | 36 | #define RTL8169_VERSION "2.3LK-NAPI" |
1da177e4 LT |
37 | #define MODULENAME "r8169" |
38 | #define PFX MODULENAME ": " | |
39 | ||
bca03d5f | 40 | #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw" |
41 | #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw" | |
01dc7fec | 42 | #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw" |
43 | #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw" | |
70090424 | 44 | #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw" |
c2218925 HW |
45 | #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw" |
46 | #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw" | |
5a5e4443 | 47 | #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw" |
7e18dca1 | 48 | #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw" |
b3d7b2f2 | 49 | #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw" |
45dd95c4 | 50 | #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw" |
5598bfe5 | 51 | #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw" |
58152cd4 | 52 | #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw" |
beb330a4 | 53 | #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw" |
57538c4a | 54 | #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw" |
6e1d0b89 CHL |
55 | #define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw" |
56 | #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw" | |
57 | #define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw" | |
58 | #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw" | |
bca03d5f | 59 | |
1da177e4 LT |
60 | #ifdef RTL8169_DEBUG |
61 | #define assert(expr) \ | |
5b0384f4 FR |
62 | if (!(expr)) { \ |
63 | printk( "Assertion failed! %s,%s,%s,line=%d\n", \ | |
b39d66a8 | 64 | #expr,__FILE__,__func__,__LINE__); \ |
5b0384f4 | 65 | } |
06fa7358 JP |
66 | #define dprintk(fmt, args...) \ |
67 | do { printk(KERN_DEBUG PFX fmt, ## args); } while (0) | |
1da177e4 LT |
68 | #else |
69 | #define assert(expr) do {} while (0) | |
70 | #define dprintk(fmt, args...) do {} while (0) | |
71 | #endif /* RTL8169_DEBUG */ | |
72 | ||
b57b7e5a | 73 | #define R8169_MSG_DEFAULT \ |
f0e837d9 | 74 | (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN) |
b57b7e5a | 75 | |
477206a0 JD |
76 | #define TX_SLOTS_AVAIL(tp) \ |
77 | (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx) | |
78 | ||
79 | /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */ | |
80 | #define TX_FRAGS_READY_FOR(tp,nr_frags) \ | |
81 | (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1)) | |
1da177e4 | 82 | |
1da177e4 LT |
83 | /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). |
84 | The RTL chips use a 64 element hash table based on the Ethernet CRC. */ | |
f71e1309 | 85 | static const int multicast_filter_limit = 32; |
1da177e4 | 86 | |
9c14ceaf | 87 | #define MAX_READ_REQUEST_SHIFT 12 |
aee77e4a | 88 | #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */ |
1da177e4 LT |
89 | #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ |
90 | ||
91 | #define R8169_REGS_SIZE 256 | |
92 | #define R8169_NAPI_WEIGHT 64 | |
93 | #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */ | |
9fba0812 | 94 | #define NUM_RX_DESC 256U /* Number of Rx descriptor registers */ |
1da177e4 LT |
95 | #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc)) |
96 | #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc)) | |
97 | ||
98 | #define RTL8169_TX_TIMEOUT (6*HZ) | |
99 | #define RTL8169_PHY_TIMEOUT (10*HZ) | |
100 | ||
101 | /* write/read MMIO register */ | |
102 | #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg)) | |
103 | #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg)) | |
104 | #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg)) | |
105 | #define RTL_R8(reg) readb (ioaddr + (reg)) | |
106 | #define RTL_R16(reg) readw (ioaddr + (reg)) | |
06f555f3 | 107 | #define RTL_R32(reg) readl (ioaddr + (reg)) |
1da177e4 LT |
108 | |
109 | enum mac_version { | |
85bffe6c FR |
110 | RTL_GIGA_MAC_VER_01 = 0, |
111 | RTL_GIGA_MAC_VER_02, | |
112 | RTL_GIGA_MAC_VER_03, | |
113 | RTL_GIGA_MAC_VER_04, | |
114 | RTL_GIGA_MAC_VER_05, | |
115 | RTL_GIGA_MAC_VER_06, | |
116 | RTL_GIGA_MAC_VER_07, | |
117 | RTL_GIGA_MAC_VER_08, | |
118 | RTL_GIGA_MAC_VER_09, | |
119 | RTL_GIGA_MAC_VER_10, | |
120 | RTL_GIGA_MAC_VER_11, | |
121 | RTL_GIGA_MAC_VER_12, | |
122 | RTL_GIGA_MAC_VER_13, | |
123 | RTL_GIGA_MAC_VER_14, | |
124 | RTL_GIGA_MAC_VER_15, | |
125 | RTL_GIGA_MAC_VER_16, | |
126 | RTL_GIGA_MAC_VER_17, | |
127 | RTL_GIGA_MAC_VER_18, | |
128 | RTL_GIGA_MAC_VER_19, | |
129 | RTL_GIGA_MAC_VER_20, | |
130 | RTL_GIGA_MAC_VER_21, | |
131 | RTL_GIGA_MAC_VER_22, | |
132 | RTL_GIGA_MAC_VER_23, | |
133 | RTL_GIGA_MAC_VER_24, | |
134 | RTL_GIGA_MAC_VER_25, | |
135 | RTL_GIGA_MAC_VER_26, | |
136 | RTL_GIGA_MAC_VER_27, | |
137 | RTL_GIGA_MAC_VER_28, | |
138 | RTL_GIGA_MAC_VER_29, | |
139 | RTL_GIGA_MAC_VER_30, | |
140 | RTL_GIGA_MAC_VER_31, | |
141 | RTL_GIGA_MAC_VER_32, | |
142 | RTL_GIGA_MAC_VER_33, | |
70090424 | 143 | RTL_GIGA_MAC_VER_34, |
c2218925 HW |
144 | RTL_GIGA_MAC_VER_35, |
145 | RTL_GIGA_MAC_VER_36, | |
7e18dca1 | 146 | RTL_GIGA_MAC_VER_37, |
b3d7b2f2 | 147 | RTL_GIGA_MAC_VER_38, |
5598bfe5 | 148 | RTL_GIGA_MAC_VER_39, |
c558386b HW |
149 | RTL_GIGA_MAC_VER_40, |
150 | RTL_GIGA_MAC_VER_41, | |
57538c4a | 151 | RTL_GIGA_MAC_VER_42, |
58152cd4 | 152 | RTL_GIGA_MAC_VER_43, |
45dd95c4 | 153 | RTL_GIGA_MAC_VER_44, |
6e1d0b89 CHL |
154 | RTL_GIGA_MAC_VER_45, |
155 | RTL_GIGA_MAC_VER_46, | |
156 | RTL_GIGA_MAC_VER_47, | |
157 | RTL_GIGA_MAC_VER_48, | |
935e2218 CHL |
158 | RTL_GIGA_MAC_VER_49, |
159 | RTL_GIGA_MAC_VER_50, | |
160 | RTL_GIGA_MAC_VER_51, | |
85bffe6c | 161 | RTL_GIGA_MAC_NONE = 0xff, |
1da177e4 LT |
162 | }; |
163 | ||
2b7b4318 FR |
164 | enum rtl_tx_desc_version { |
165 | RTL_TD_0 = 0, | |
166 | RTL_TD_1 = 1, | |
167 | }; | |
168 | ||
d58d46b5 FR |
169 | #define JUMBO_1K ETH_DATA_LEN |
170 | #define JUMBO_4K (4*1024 - ETH_HLEN - 2) | |
171 | #define JUMBO_6K (6*1024 - ETH_HLEN - 2) | |
172 | #define JUMBO_7K (7*1024 - ETH_HLEN - 2) | |
173 | #define JUMBO_9K (9*1024 - ETH_HLEN - 2) | |
174 | ||
175 | #define _R(NAME,TD,FW,SZ,B) { \ | |
176 | .name = NAME, \ | |
177 | .txd_version = TD, \ | |
178 | .fw_name = FW, \ | |
179 | .jumbo_max = SZ, \ | |
180 | .jumbo_tx_csum = B \ | |
181 | } | |
1da177e4 | 182 | |
3c6bee1d | 183 | static const struct { |
1da177e4 | 184 | const char *name; |
2b7b4318 | 185 | enum rtl_tx_desc_version txd_version; |
953a12cc | 186 | const char *fw_name; |
d58d46b5 FR |
187 | u16 jumbo_max; |
188 | bool jumbo_tx_csum; | |
85bffe6c FR |
189 | } rtl_chip_infos[] = { |
190 | /* PCI devices. */ | |
191 | [RTL_GIGA_MAC_VER_01] = | |
d58d46b5 | 192 | _R("RTL8169", RTL_TD_0, NULL, JUMBO_7K, true), |
85bffe6c | 193 | [RTL_GIGA_MAC_VER_02] = |
d58d46b5 | 194 | _R("RTL8169s", RTL_TD_0, NULL, JUMBO_7K, true), |
85bffe6c | 195 | [RTL_GIGA_MAC_VER_03] = |
d58d46b5 | 196 | _R("RTL8110s", RTL_TD_0, NULL, JUMBO_7K, true), |
85bffe6c | 197 | [RTL_GIGA_MAC_VER_04] = |
d58d46b5 | 198 | _R("RTL8169sb/8110sb", RTL_TD_0, NULL, JUMBO_7K, true), |
85bffe6c | 199 | [RTL_GIGA_MAC_VER_05] = |
d58d46b5 | 200 | _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true), |
85bffe6c | 201 | [RTL_GIGA_MAC_VER_06] = |
d58d46b5 | 202 | _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true), |
85bffe6c FR |
203 | /* PCI-E devices. */ |
204 | [RTL_GIGA_MAC_VER_07] = | |
d58d46b5 | 205 | _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true), |
85bffe6c | 206 | [RTL_GIGA_MAC_VER_08] = |
d58d46b5 | 207 | _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true), |
85bffe6c | 208 | [RTL_GIGA_MAC_VER_09] = |
d58d46b5 | 209 | _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true), |
85bffe6c | 210 | [RTL_GIGA_MAC_VER_10] = |
d58d46b5 | 211 | _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true), |
85bffe6c | 212 | [RTL_GIGA_MAC_VER_11] = |
d58d46b5 | 213 | _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false), |
85bffe6c | 214 | [RTL_GIGA_MAC_VER_12] = |
d58d46b5 | 215 | _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false), |
85bffe6c | 216 | [RTL_GIGA_MAC_VER_13] = |
d58d46b5 | 217 | _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true), |
85bffe6c | 218 | [RTL_GIGA_MAC_VER_14] = |
d58d46b5 | 219 | _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true), |
85bffe6c | 220 | [RTL_GIGA_MAC_VER_15] = |
d58d46b5 | 221 | _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true), |
85bffe6c | 222 | [RTL_GIGA_MAC_VER_16] = |
d58d46b5 | 223 | _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true), |
85bffe6c | 224 | [RTL_GIGA_MAC_VER_17] = |
f75761b6 | 225 | _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false), |
85bffe6c | 226 | [RTL_GIGA_MAC_VER_18] = |
d58d46b5 | 227 | _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false), |
85bffe6c | 228 | [RTL_GIGA_MAC_VER_19] = |
d58d46b5 | 229 | _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false), |
85bffe6c | 230 | [RTL_GIGA_MAC_VER_20] = |
d58d46b5 | 231 | _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false), |
85bffe6c | 232 | [RTL_GIGA_MAC_VER_21] = |
d58d46b5 | 233 | _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false), |
85bffe6c | 234 | [RTL_GIGA_MAC_VER_22] = |
d58d46b5 | 235 | _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false), |
85bffe6c | 236 | [RTL_GIGA_MAC_VER_23] = |
d58d46b5 | 237 | _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false), |
85bffe6c | 238 | [RTL_GIGA_MAC_VER_24] = |
d58d46b5 | 239 | _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false), |
85bffe6c | 240 | [RTL_GIGA_MAC_VER_25] = |
d58d46b5 FR |
241 | _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1, |
242 | JUMBO_9K, false), | |
85bffe6c | 243 | [RTL_GIGA_MAC_VER_26] = |
d58d46b5 FR |
244 | _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2, |
245 | JUMBO_9K, false), | |
85bffe6c | 246 | [RTL_GIGA_MAC_VER_27] = |
d58d46b5 | 247 | _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false), |
85bffe6c | 248 | [RTL_GIGA_MAC_VER_28] = |
d58d46b5 | 249 | _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false), |
85bffe6c | 250 | [RTL_GIGA_MAC_VER_29] = |
d58d46b5 FR |
251 | _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1, |
252 | JUMBO_1K, true), | |
85bffe6c | 253 | [RTL_GIGA_MAC_VER_30] = |
d58d46b5 FR |
254 | _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1, |
255 | JUMBO_1K, true), | |
85bffe6c | 256 | [RTL_GIGA_MAC_VER_31] = |
d58d46b5 | 257 | _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false), |
85bffe6c | 258 | [RTL_GIGA_MAC_VER_32] = |
d58d46b5 FR |
259 | _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1, |
260 | JUMBO_9K, false), | |
85bffe6c | 261 | [RTL_GIGA_MAC_VER_33] = |
d58d46b5 FR |
262 | _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2, |
263 | JUMBO_9K, false), | |
70090424 | 264 | [RTL_GIGA_MAC_VER_34] = |
d58d46b5 FR |
265 | _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3, |
266 | JUMBO_9K, false), | |
c2218925 | 267 | [RTL_GIGA_MAC_VER_35] = |
d58d46b5 FR |
268 | _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_1, |
269 | JUMBO_9K, false), | |
c2218925 | 270 | [RTL_GIGA_MAC_VER_36] = |
d58d46b5 FR |
271 | _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_2, |
272 | JUMBO_9K, false), | |
7e18dca1 HW |
273 | [RTL_GIGA_MAC_VER_37] = |
274 | _R("RTL8402", RTL_TD_1, FIRMWARE_8402_1, | |
275 | JUMBO_1K, true), | |
b3d7b2f2 HW |
276 | [RTL_GIGA_MAC_VER_38] = |
277 | _R("RTL8411", RTL_TD_1, FIRMWARE_8411_1, | |
278 | JUMBO_9K, false), | |
5598bfe5 HW |
279 | [RTL_GIGA_MAC_VER_39] = |
280 | _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_1, | |
281 | JUMBO_1K, true), | |
c558386b | 282 | [RTL_GIGA_MAC_VER_40] = |
beb330a4 | 283 | _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_2, |
c558386b HW |
284 | JUMBO_9K, false), |
285 | [RTL_GIGA_MAC_VER_41] = | |
286 | _R("RTL8168g/8111g", RTL_TD_1, NULL, JUMBO_9K, false), | |
57538c4a | 287 | [RTL_GIGA_MAC_VER_42] = |
288 | _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_3, | |
289 | JUMBO_9K, false), | |
58152cd4 | 290 | [RTL_GIGA_MAC_VER_43] = |
291 | _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_2, | |
292 | JUMBO_1K, true), | |
45dd95c4 | 293 | [RTL_GIGA_MAC_VER_44] = |
294 | _R("RTL8411", RTL_TD_1, FIRMWARE_8411_2, | |
295 | JUMBO_9K, false), | |
6e1d0b89 CHL |
296 | [RTL_GIGA_MAC_VER_45] = |
297 | _R("RTL8168h/8111h", RTL_TD_1, FIRMWARE_8168H_1, | |
298 | JUMBO_9K, false), | |
299 | [RTL_GIGA_MAC_VER_46] = | |
300 | _R("RTL8168h/8111h", RTL_TD_1, FIRMWARE_8168H_2, | |
301 | JUMBO_9K, false), | |
302 | [RTL_GIGA_MAC_VER_47] = | |
303 | _R("RTL8107e", RTL_TD_1, FIRMWARE_8107E_1, | |
304 | JUMBO_1K, false), | |
305 | [RTL_GIGA_MAC_VER_48] = | |
306 | _R("RTL8107e", RTL_TD_1, FIRMWARE_8107E_2, | |
307 | JUMBO_1K, false), | |
935e2218 CHL |
308 | [RTL_GIGA_MAC_VER_49] = |
309 | _R("RTL8168ep/8111ep", RTL_TD_1, NULL, | |
310 | JUMBO_9K, false), | |
311 | [RTL_GIGA_MAC_VER_50] = | |
312 | _R("RTL8168ep/8111ep", RTL_TD_1, NULL, | |
313 | JUMBO_9K, false), | |
314 | [RTL_GIGA_MAC_VER_51] = | |
315 | _R("RTL8168ep/8111ep", RTL_TD_1, NULL, | |
316 | JUMBO_9K, false), | |
953a12cc | 317 | }; |
85bffe6c | 318 | #undef _R |
953a12cc | 319 | |
bcf0bf90 FR |
320 | enum cfg_version { |
321 | RTL_CFG_0 = 0x00, | |
322 | RTL_CFG_1, | |
323 | RTL_CFG_2 | |
324 | }; | |
325 | ||
9baa3c34 | 326 | static const struct pci_device_id rtl8169_pci_tbl[] = { |
bcf0bf90 | 327 | { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 }, |
d2eed8cf | 328 | { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 }, |
d81bf551 | 329 | { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 }, |
07ce4064 | 330 | { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 }, |
bcf0bf90 | 331 | { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 }, |
2a35cfa5 FR |
332 | { PCI_VENDOR_ID_DLINK, 0x4300, |
333 | PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0, RTL_CFG_1 }, | |
bcf0bf90 | 334 | { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 }, |
93a3aa25 | 335 | { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 }, |
bc1660b5 | 336 | { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 }, |
bcf0bf90 FR |
337 | { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 }, |
338 | { PCI_VENDOR_ID_LINKSYS, 0x1032, | |
339 | PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 }, | |
11d2e282 CM |
340 | { 0x0001, 0x8168, |
341 | PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 }, | |
1da177e4 LT |
342 | {0,}, |
343 | }; | |
344 | ||
345 | MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl); | |
346 | ||
6f0333b8 | 347 | static int rx_buf_sz = 16383; |
4300e8c7 | 348 | static int use_dac; |
b57b7e5a SH |
349 | static struct { |
350 | u32 msg_enable; | |
351 | } debug = { -1 }; | |
1da177e4 | 352 | |
07d3f51f FR |
353 | enum rtl_registers { |
354 | MAC0 = 0, /* Ethernet hardware address. */ | |
773d2021 | 355 | MAC4 = 4, |
07d3f51f FR |
356 | MAR0 = 8, /* Multicast filter. */ |
357 | CounterAddrLow = 0x10, | |
358 | CounterAddrHigh = 0x14, | |
359 | TxDescStartAddrLow = 0x20, | |
360 | TxDescStartAddrHigh = 0x24, | |
361 | TxHDescStartAddrLow = 0x28, | |
362 | TxHDescStartAddrHigh = 0x2c, | |
363 | FLASH = 0x30, | |
364 | ERSR = 0x36, | |
365 | ChipCmd = 0x37, | |
366 | TxPoll = 0x38, | |
367 | IntrMask = 0x3c, | |
368 | IntrStatus = 0x3e, | |
4f6b00e5 | 369 | |
07d3f51f | 370 | TxConfig = 0x40, |
4f6b00e5 HW |
371 | #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */ |
372 | #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */ | |
2b7b4318 | 373 | |
4f6b00e5 HW |
374 | RxConfig = 0x44, |
375 | #define RX128_INT_EN (1 << 15) /* 8111c and later */ | |
376 | #define RX_MULTI_EN (1 << 14) /* 8111c only */ | |
377 | #define RXCFG_FIFO_SHIFT 13 | |
378 | /* No threshold before first PCI xfer */ | |
379 | #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT) | |
beb330a4 | 380 | #define RX_EARLY_OFF (1 << 11) |
4f6b00e5 HW |
381 | #define RXCFG_DMA_SHIFT 8 |
382 | /* Unlimited maximum PCI burst. */ | |
383 | #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT) | |
2b7b4318 | 384 | |
07d3f51f FR |
385 | RxMissed = 0x4c, |
386 | Cfg9346 = 0x50, | |
387 | Config0 = 0x51, | |
388 | Config1 = 0x52, | |
389 | Config2 = 0x53, | |
d387b427 FR |
390 | #define PME_SIGNAL (1 << 5) /* 8168c and later */ |
391 | ||
07d3f51f FR |
392 | Config3 = 0x54, |
393 | Config4 = 0x55, | |
394 | Config5 = 0x56, | |
395 | MultiIntr = 0x5c, | |
396 | PHYAR = 0x60, | |
07d3f51f FR |
397 | PHYstatus = 0x6c, |
398 | RxMaxSize = 0xda, | |
399 | CPlusCmd = 0xe0, | |
400 | IntrMitigate = 0xe2, | |
401 | RxDescAddrLow = 0xe4, | |
402 | RxDescAddrHigh = 0xe8, | |
f0298f81 | 403 | EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */ |
404 | ||
405 | #define NoEarlyTx 0x3f /* Max value : no early transmit. */ | |
406 | ||
407 | MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */ | |
408 | ||
409 | #define TxPacketMax (8064 >> 7) | |
3090bd9a | 410 | #define EarlySize 0x27 |
f0298f81 | 411 | |
07d3f51f FR |
412 | FuncEvent = 0xf0, |
413 | FuncEventMask = 0xf4, | |
414 | FuncPresetState = 0xf8, | |
935e2218 CHL |
415 | IBCR0 = 0xf8, |
416 | IBCR2 = 0xf9, | |
417 | IBIMR0 = 0xfa, | |
418 | IBISR0 = 0xfb, | |
07d3f51f | 419 | FuncForceEvent = 0xfc, |
1da177e4 LT |
420 | }; |
421 | ||
f162a5d1 FR |
422 | enum rtl8110_registers { |
423 | TBICSR = 0x64, | |
424 | TBI_ANAR = 0x68, | |
425 | TBI_LPAR = 0x6a, | |
426 | }; | |
427 | ||
428 | enum rtl8168_8101_registers { | |
429 | CSIDR = 0x64, | |
430 | CSIAR = 0x68, | |
431 | #define CSIAR_FLAG 0x80000000 | |
432 | #define CSIAR_WRITE_CMD 0x80000000 | |
433 | #define CSIAR_BYTE_ENABLE 0x0f | |
434 | #define CSIAR_BYTE_ENABLE_SHIFT 12 | |
435 | #define CSIAR_ADDR_MASK 0x0fff | |
7e18dca1 HW |
436 | #define CSIAR_FUNC_CARD 0x00000000 |
437 | #define CSIAR_FUNC_SDIO 0x00010000 | |
438 | #define CSIAR_FUNC_NIC 0x00020000 | |
45dd95c4 | 439 | #define CSIAR_FUNC_NIC2 0x00010000 |
065c27c1 | 440 | PMCH = 0x6f, |
f162a5d1 FR |
441 | EPHYAR = 0x80, |
442 | #define EPHYAR_FLAG 0x80000000 | |
443 | #define EPHYAR_WRITE_CMD 0x80000000 | |
444 | #define EPHYAR_REG_MASK 0x1f | |
445 | #define EPHYAR_REG_SHIFT 16 | |
446 | #define EPHYAR_DATA_MASK 0xffff | |
5a5e4443 | 447 | DLLPR = 0xd0, |
4f6b00e5 | 448 | #define PFM_EN (1 << 6) |
6e1d0b89 | 449 | #define TX_10M_PS_EN (1 << 7) |
f162a5d1 FR |
450 | DBG_REG = 0xd1, |
451 | #define FIX_NAK_1 (1 << 4) | |
452 | #define FIX_NAK_2 (1 << 3) | |
5a5e4443 HW |
453 | TWSI = 0xd2, |
454 | MCU = 0xd3, | |
4f6b00e5 | 455 | #define NOW_IS_OOB (1 << 7) |
c558386b HW |
456 | #define TX_EMPTY (1 << 5) |
457 | #define RX_EMPTY (1 << 4) | |
458 | #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY) | |
5a5e4443 HW |
459 | #define EN_NDP (1 << 3) |
460 | #define EN_OOB_RESET (1 << 2) | |
c558386b | 461 | #define LINK_LIST_RDY (1 << 1) |
daf9df6d | 462 | EFUSEAR = 0xdc, |
463 | #define EFUSEAR_FLAG 0x80000000 | |
464 | #define EFUSEAR_WRITE_CMD 0x80000000 | |
465 | #define EFUSEAR_READ_CMD 0x00000000 | |
466 | #define EFUSEAR_REG_MASK 0x03ff | |
467 | #define EFUSEAR_REG_SHIFT 8 | |
468 | #define EFUSEAR_DATA_MASK 0xff | |
6e1d0b89 CHL |
469 | MISC_1 = 0xf2, |
470 | #define PFM_D3COLD_EN (1 << 6) | |
f162a5d1 FR |
471 | }; |
472 | ||
c0e45c1c | 473 | enum rtl8168_registers { |
4f6b00e5 HW |
474 | LED_FREQ = 0x1a, |
475 | EEE_LED = 0x1b, | |
b646d900 | 476 | ERIDR = 0x70, |
477 | ERIAR = 0x74, | |
478 | #define ERIAR_FLAG 0x80000000 | |
479 | #define ERIAR_WRITE_CMD 0x80000000 | |
480 | #define ERIAR_READ_CMD 0x00000000 | |
481 | #define ERIAR_ADDR_BYTE_ALIGN 4 | |
b646d900 | 482 | #define ERIAR_TYPE_SHIFT 16 |
4f6b00e5 HW |
483 | #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT) |
484 | #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT) | |
485 | #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT) | |
935e2218 | 486 | #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT) |
4f6b00e5 HW |
487 | #define ERIAR_MASK_SHIFT 12 |
488 | #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT) | |
489 | #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT) | |
6e1d0b89 | 490 | #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT) |
c558386b | 491 | #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT) |
4f6b00e5 | 492 | #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT) |
c0e45c1c | 493 | EPHY_RXER_NUM = 0x7c, |
494 | OCPDR = 0xb0, /* OCP GPHY access */ | |
495 | #define OCPDR_WRITE_CMD 0x80000000 | |
496 | #define OCPDR_READ_CMD 0x00000000 | |
497 | #define OCPDR_REG_MASK 0x7f | |
498 | #define OCPDR_GPHY_REG_SHIFT 16 | |
499 | #define OCPDR_DATA_MASK 0xffff | |
500 | OCPAR = 0xb4, | |
501 | #define OCPAR_FLAG 0x80000000 | |
502 | #define OCPAR_GPHY_WRITE_CMD 0x8000f060 | |
503 | #define OCPAR_GPHY_READ_CMD 0x0000f060 | |
c558386b | 504 | GPHY_OCP = 0xb8, |
01dc7fec | 505 | RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */ |
506 | MISC = 0xf0, /* 8168e only. */ | |
cecb5fd7 | 507 | #define TXPLA_RST (1 << 29) |
5598bfe5 | 508 | #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */ |
4f6b00e5 | 509 | #define PWM_EN (1 << 22) |
c558386b | 510 | #define RXDV_GATED_EN (1 << 19) |
5598bfe5 | 511 | #define EARLY_TALLY_EN (1 << 16) |
c0e45c1c | 512 | }; |
513 | ||
07d3f51f | 514 | enum rtl_register_content { |
1da177e4 | 515 | /* InterruptStatusBits */ |
07d3f51f FR |
516 | SYSErr = 0x8000, |
517 | PCSTimeout = 0x4000, | |
518 | SWInt = 0x0100, | |
519 | TxDescUnavail = 0x0080, | |
520 | RxFIFOOver = 0x0040, | |
521 | LinkChg = 0x0020, | |
522 | RxOverflow = 0x0010, | |
523 | TxErr = 0x0008, | |
524 | TxOK = 0x0004, | |
525 | RxErr = 0x0002, | |
526 | RxOK = 0x0001, | |
1da177e4 LT |
527 | |
528 | /* RxStatusDesc */ | |
e03f33af | 529 | RxBOVF = (1 << 24), |
9dccf611 FR |
530 | RxFOVF = (1 << 23), |
531 | RxRWT = (1 << 22), | |
532 | RxRES = (1 << 21), | |
533 | RxRUNT = (1 << 20), | |
534 | RxCRC = (1 << 19), | |
1da177e4 LT |
535 | |
536 | /* ChipCmdBits */ | |
4f6b00e5 | 537 | StopReq = 0x80, |
07d3f51f FR |
538 | CmdReset = 0x10, |
539 | CmdRxEnb = 0x08, | |
540 | CmdTxEnb = 0x04, | |
541 | RxBufEmpty = 0x01, | |
1da177e4 | 542 | |
275391a4 FR |
543 | /* TXPoll register p.5 */ |
544 | HPQ = 0x80, /* Poll cmd on the high prio queue */ | |
545 | NPQ = 0x40, /* Poll cmd on the low prio queue */ | |
546 | FSWInt = 0x01, /* Forced software interrupt */ | |
547 | ||
1da177e4 | 548 | /* Cfg9346Bits */ |
07d3f51f FR |
549 | Cfg9346_Lock = 0x00, |
550 | Cfg9346_Unlock = 0xc0, | |
1da177e4 LT |
551 | |
552 | /* rx_mode_bits */ | |
07d3f51f FR |
553 | AcceptErr = 0x20, |
554 | AcceptRunt = 0x10, | |
555 | AcceptBroadcast = 0x08, | |
556 | AcceptMulticast = 0x04, | |
557 | AcceptMyPhys = 0x02, | |
558 | AcceptAllPhys = 0x01, | |
1687b566 | 559 | #define RX_CONFIG_ACCEPT_MASK 0x3f |
1da177e4 | 560 | |
1da177e4 LT |
561 | /* TxConfigBits */ |
562 | TxInterFrameGapShift = 24, | |
563 | TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ | |
564 | ||
5d06a99f | 565 | /* Config1 register p.24 */ |
f162a5d1 FR |
566 | LEDS1 = (1 << 7), |
567 | LEDS0 = (1 << 6), | |
f162a5d1 FR |
568 | Speed_down = (1 << 4), |
569 | MEMMAP = (1 << 3), | |
570 | IOMAP = (1 << 2), | |
571 | VPD = (1 << 1), | |
5d06a99f FR |
572 | PMEnable = (1 << 0), /* Power Management Enable */ |
573 | ||
6dccd16b | 574 | /* Config2 register p. 25 */ |
57538c4a | 575 | ClkReqEn = (1 << 7), /* Clock Request Enable */ |
2ca6cf06 | 576 | MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */ |
6dccd16b FR |
577 | PCI_Clock_66MHz = 0x01, |
578 | PCI_Clock_33MHz = 0x00, | |
579 | ||
61a4dcc2 FR |
580 | /* Config3 register p.25 */ |
581 | MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */ | |
582 | LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */ | |
d58d46b5 | 583 | Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */ |
b51ecea8 | 584 | Rdy_to_L23 = (1 << 1), /* L23 Enable */ |
f162a5d1 | 585 | Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */ |
61a4dcc2 | 586 | |
d58d46b5 FR |
587 | /* Config4 register */ |
588 | Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */ | |
589 | ||
5d06a99f | 590 | /* Config5 register p.27 */ |
61a4dcc2 FR |
591 | BWF = (1 << 6), /* Accept Broadcast wakeup frame */ |
592 | MWF = (1 << 5), /* Accept Multicast wakeup frame */ | |
593 | UWF = (1 << 4), /* Accept Unicast wakeup frame */ | |
cecb5fd7 | 594 | Spi_en = (1 << 3), |
61a4dcc2 | 595 | LanWake = (1 << 1), /* LanWake enable/disable */ |
5d06a99f | 596 | PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */ |
57538c4a | 597 | ASPM_en = (1 << 0), /* ASPM enable */ |
5d06a99f | 598 | |
1da177e4 LT |
599 | /* TBICSR p.28 */ |
600 | TBIReset = 0x80000000, | |
601 | TBILoopback = 0x40000000, | |
602 | TBINwEnable = 0x20000000, | |
603 | TBINwRestart = 0x10000000, | |
604 | TBILinkOk = 0x02000000, | |
605 | TBINwComplete = 0x01000000, | |
606 | ||
607 | /* CPlusCmd p.31 */ | |
f162a5d1 FR |
608 | EnableBist = (1 << 15), // 8168 8101 |
609 | Mac_dbgo_oe = (1 << 14), // 8168 8101 | |
610 | Normal_mode = (1 << 13), // unused | |
611 | Force_half_dup = (1 << 12), // 8168 8101 | |
612 | Force_rxflow_en = (1 << 11), // 8168 8101 | |
613 | Force_txflow_en = (1 << 10), // 8168 8101 | |
614 | Cxpl_dbg_sel = (1 << 9), // 8168 8101 | |
615 | ASF = (1 << 8), // 8168 8101 | |
616 | PktCntrDisable = (1 << 7), // 8168 8101 | |
617 | Mac_dbgo_sel = 0x001c, // 8168 | |
1da177e4 LT |
618 | RxVlan = (1 << 6), |
619 | RxChkSum = (1 << 5), | |
620 | PCIDAC = (1 << 4), | |
621 | PCIMulRW = (1 << 3), | |
0e485150 FR |
622 | INTT_0 = 0x0000, // 8168 |
623 | INTT_1 = 0x0001, // 8168 | |
624 | INTT_2 = 0x0002, // 8168 | |
625 | INTT_3 = 0x0003, // 8168 | |
1da177e4 LT |
626 | |
627 | /* rtl8169_PHYstatus */ | |
07d3f51f FR |
628 | TBI_Enable = 0x80, |
629 | TxFlowCtrl = 0x40, | |
630 | RxFlowCtrl = 0x20, | |
631 | _1000bpsF = 0x10, | |
632 | _100bps = 0x08, | |
633 | _10bps = 0x04, | |
634 | LinkStatus = 0x02, | |
635 | FullDup = 0x01, | |
1da177e4 | 636 | |
1da177e4 | 637 | /* _TBICSRBit */ |
07d3f51f | 638 | TBILinkOK = 0x02000000, |
d4a3a0fc SH |
639 | |
640 | /* DumpCounterCommand */ | |
07d3f51f | 641 | CounterDump = 0x8, |
6e1d0b89 CHL |
642 | |
643 | /* magic enable v2 */ | |
644 | MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */ | |
1da177e4 LT |
645 | }; |
646 | ||
2b7b4318 FR |
647 | enum rtl_desc_bit { |
648 | /* First doubleword. */ | |
1da177e4 LT |
649 | DescOwn = (1 << 31), /* Descriptor is owned by NIC */ |
650 | RingEnd = (1 << 30), /* End of descriptor ring */ | |
651 | FirstFrag = (1 << 29), /* First segment of a packet */ | |
652 | LastFrag = (1 << 28), /* Final segment of a packet */ | |
2b7b4318 FR |
653 | }; |
654 | ||
655 | /* Generic case. */ | |
656 | enum rtl_tx_desc_bit { | |
657 | /* First doubleword. */ | |
658 | TD_LSO = (1 << 27), /* Large Send Offload */ | |
659 | #define TD_MSS_MAX 0x07ffu /* MSS value */ | |
1da177e4 | 660 | |
2b7b4318 FR |
661 | /* Second doubleword. */ |
662 | TxVlanTag = (1 << 17), /* Add VLAN tag */ | |
663 | }; | |
664 | ||
665 | /* 8169, 8168b and 810x except 8102e. */ | |
666 | enum rtl_tx_desc_bit_0 { | |
667 | /* First doubleword. */ | |
668 | #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */ | |
669 | TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */ | |
670 | TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */ | |
671 | TD0_IP_CS = (1 << 18), /* Calculate IP checksum */ | |
672 | }; | |
673 | ||
674 | /* 8102e, 8168c and beyond. */ | |
675 | enum rtl_tx_desc_bit_1 { | |
bdfa4ed6 | 676 | /* First doubleword. */ |
677 | TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */ | |
e974604b | 678 | TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */ |
bdfa4ed6 | 679 | #define GTTCPHO_SHIFT 18 |
e974604b | 680 | #define GTTCPHO_MAX 0x7fU |
bdfa4ed6 | 681 | |
2b7b4318 | 682 | /* Second doubleword. */ |
e974604b | 683 | #define TCPHO_SHIFT 18 |
684 | #define TCPHO_MAX 0x3ffU | |
2b7b4318 | 685 | #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */ |
e974604b | 686 | TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */ |
687 | TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */ | |
2b7b4318 FR |
688 | TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */ |
689 | TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */ | |
690 | }; | |
1da177e4 | 691 | |
2b7b4318 | 692 | enum rtl_rx_desc_bit { |
1da177e4 LT |
693 | /* Rx private */ |
694 | PID1 = (1 << 18), /* Protocol ID bit 1/2 */ | |
695 | PID0 = (1 << 17), /* Protocol ID bit 2/2 */ | |
696 | ||
697 | #define RxProtoUDP (PID1) | |
698 | #define RxProtoTCP (PID0) | |
699 | #define RxProtoIP (PID1 | PID0) | |
700 | #define RxProtoMask RxProtoIP | |
701 | ||
702 | IPFail = (1 << 16), /* IP checksum failed */ | |
703 | UDPFail = (1 << 15), /* UDP/IP checksum failed */ | |
704 | TCPFail = (1 << 14), /* TCP/IP checksum failed */ | |
705 | RxVlanTag = (1 << 16), /* VLAN tag available */ | |
706 | }; | |
707 | ||
708 | #define RsvdMask 0x3fffc000 | |
709 | ||
710 | struct TxDesc { | |
6cccd6e7 REB |
711 | __le32 opts1; |
712 | __le32 opts2; | |
713 | __le64 addr; | |
1da177e4 LT |
714 | }; |
715 | ||
716 | struct RxDesc { | |
6cccd6e7 REB |
717 | __le32 opts1; |
718 | __le32 opts2; | |
719 | __le64 addr; | |
1da177e4 LT |
720 | }; |
721 | ||
722 | struct ring_info { | |
723 | struct sk_buff *skb; | |
724 | u32 len; | |
725 | u8 __pad[sizeof(void *) - sizeof(u32)]; | |
726 | }; | |
727 | ||
f23e7fda | 728 | enum features { |
ccdffb9a FR |
729 | RTL_FEATURE_WOL = (1 << 0), |
730 | RTL_FEATURE_MSI = (1 << 1), | |
731 | RTL_FEATURE_GMII = (1 << 2), | |
f23e7fda FR |
732 | }; |
733 | ||
355423d0 IV |
734 | struct rtl8169_counters { |
735 | __le64 tx_packets; | |
736 | __le64 rx_packets; | |
737 | __le64 tx_errors; | |
738 | __le32 rx_errors; | |
739 | __le16 rx_missed; | |
740 | __le16 align_errors; | |
741 | __le32 tx_one_collision; | |
742 | __le32 tx_multi_collision; | |
743 | __le64 rx_unicast; | |
744 | __le64 rx_broadcast; | |
745 | __le32 rx_multicast; | |
746 | __le16 tx_aborted; | |
747 | __le16 tx_underun; | |
748 | }; | |
749 | ||
da78dbff | 750 | enum rtl_flag { |
6c4a70c5 | 751 | RTL_FLAG_TASK_ENABLED, |
da78dbff FR |
752 | RTL_FLAG_TASK_SLOW_PENDING, |
753 | RTL_FLAG_TASK_RESET_PENDING, | |
754 | RTL_FLAG_TASK_PHY_PENDING, | |
755 | RTL_FLAG_MAX | |
756 | }; | |
757 | ||
8027aa24 JW |
758 | struct rtl8169_stats { |
759 | u64 packets; | |
760 | u64 bytes; | |
761 | struct u64_stats_sync syncp; | |
762 | }; | |
763 | ||
1da177e4 LT |
764 | struct rtl8169_private { |
765 | void __iomem *mmio_addr; /* memory map physical address */ | |
cecb5fd7 | 766 | struct pci_dev *pci_dev; |
c4028958 | 767 | struct net_device *dev; |
bea3348e | 768 | struct napi_struct napi; |
b57b7e5a | 769 | u32 msg_enable; |
2b7b4318 FR |
770 | u16 txd_version; |
771 | u16 mac_version; | |
1da177e4 LT |
772 | u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ |
773 | u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ | |
1da177e4 | 774 | u32 dirty_tx; |
8027aa24 JW |
775 | struct rtl8169_stats rx_stats; |
776 | struct rtl8169_stats tx_stats; | |
1da177e4 LT |
777 | struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */ |
778 | struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */ | |
779 | dma_addr_t TxPhyAddr; | |
780 | dma_addr_t RxPhyAddr; | |
6f0333b8 | 781 | void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */ |
1da177e4 | 782 | struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */ |
1da177e4 LT |
783 | struct timer_list timer; |
784 | u16 cp_cmd; | |
da78dbff FR |
785 | |
786 | u16 event_slow; | |
c0e45c1c | 787 | |
788 | struct mdio_ops { | |
24192210 FR |
789 | void (*write)(struct rtl8169_private *, int, int); |
790 | int (*read)(struct rtl8169_private *, int); | |
c0e45c1c | 791 | } mdio_ops; |
792 | ||
065c27c1 | 793 | struct pll_power_ops { |
794 | void (*down)(struct rtl8169_private *); | |
795 | void (*up)(struct rtl8169_private *); | |
796 | } pll_power_ops; | |
797 | ||
d58d46b5 FR |
798 | struct jumbo_ops { |
799 | void (*enable)(struct rtl8169_private *); | |
800 | void (*disable)(struct rtl8169_private *); | |
801 | } jumbo_ops; | |
802 | ||
beb1fe18 | 803 | struct csi_ops { |
52989f0e FR |
804 | void (*write)(struct rtl8169_private *, int, int); |
805 | u32 (*read)(struct rtl8169_private *, int); | |
beb1fe18 HW |
806 | } csi_ops; |
807 | ||
54405cde | 808 | int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv); |
ccdffb9a | 809 | int (*get_settings)(struct net_device *, struct ethtool_cmd *); |
4da19633 | 810 | void (*phy_reset_enable)(struct rtl8169_private *tp); |
07ce4064 | 811 | void (*hw_start)(struct net_device *); |
4da19633 | 812 | unsigned int (*phy_reset_pending)(struct rtl8169_private *tp); |
1da177e4 | 813 | unsigned int (*link_ok)(void __iomem *); |
8b4ab28d | 814 | int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd); |
5888d3fc | 815 | bool (*tso_csum)(struct rtl8169_private *, struct sk_buff *, u32 *); |
4422bcd4 FR |
816 | |
817 | struct { | |
da78dbff FR |
818 | DECLARE_BITMAP(flags, RTL_FLAG_MAX); |
819 | struct mutex mutex; | |
4422bcd4 FR |
820 | struct work_struct work; |
821 | } wk; | |
822 | ||
f23e7fda | 823 | unsigned features; |
ccdffb9a FR |
824 | |
825 | struct mii_if_info mii; | |
355423d0 | 826 | struct rtl8169_counters counters; |
e1759441 | 827 | u32 saved_wolopts; |
e03f33af | 828 | u32 opts1_mask; |
f1e02ed1 | 829 | |
b6ffd97f FR |
830 | struct rtl_fw { |
831 | const struct firmware *fw; | |
1c361efb FR |
832 | |
833 | #define RTL_VER_SIZE 32 | |
834 | ||
835 | char version[RTL_VER_SIZE]; | |
836 | ||
837 | struct rtl_fw_phy_action { | |
838 | __le32 *code; | |
839 | size_t size; | |
840 | } phy_action; | |
b6ffd97f | 841 | } *rtl_fw; |
497888cf | 842 | #define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN) |
c558386b HW |
843 | |
844 | u32 ocp_base; | |
1da177e4 LT |
845 | }; |
846 | ||
979b6c13 | 847 | MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>"); |
1da177e4 | 848 | MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver"); |
1da177e4 | 849 | module_param(use_dac, int, 0); |
4300e8c7 | 850 | MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot."); |
b57b7e5a SH |
851 | module_param_named(debug, debug.msg_enable, int, 0); |
852 | MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)"); | |
1da177e4 LT |
853 | MODULE_LICENSE("GPL"); |
854 | MODULE_VERSION(RTL8169_VERSION); | |
bca03d5f | 855 | MODULE_FIRMWARE(FIRMWARE_8168D_1); |
856 | MODULE_FIRMWARE(FIRMWARE_8168D_2); | |
01dc7fec | 857 | MODULE_FIRMWARE(FIRMWARE_8168E_1); |
858 | MODULE_FIRMWARE(FIRMWARE_8168E_2); | |
bbb8af75 | 859 | MODULE_FIRMWARE(FIRMWARE_8168E_3); |
5a5e4443 | 860 | MODULE_FIRMWARE(FIRMWARE_8105E_1); |
c2218925 HW |
861 | MODULE_FIRMWARE(FIRMWARE_8168F_1); |
862 | MODULE_FIRMWARE(FIRMWARE_8168F_2); | |
7e18dca1 | 863 | MODULE_FIRMWARE(FIRMWARE_8402_1); |
b3d7b2f2 | 864 | MODULE_FIRMWARE(FIRMWARE_8411_1); |
45dd95c4 | 865 | MODULE_FIRMWARE(FIRMWARE_8411_2); |
5598bfe5 | 866 | MODULE_FIRMWARE(FIRMWARE_8106E_1); |
58152cd4 | 867 | MODULE_FIRMWARE(FIRMWARE_8106E_2); |
beb330a4 | 868 | MODULE_FIRMWARE(FIRMWARE_8168G_2); |
57538c4a | 869 | MODULE_FIRMWARE(FIRMWARE_8168G_3); |
6e1d0b89 CHL |
870 | MODULE_FIRMWARE(FIRMWARE_8168H_1); |
871 | MODULE_FIRMWARE(FIRMWARE_8168H_2); | |
a3bf5c42 FR |
872 | MODULE_FIRMWARE(FIRMWARE_8107E_1); |
873 | MODULE_FIRMWARE(FIRMWARE_8107E_2); | |
1da177e4 | 874 | |
da78dbff FR |
875 | static void rtl_lock_work(struct rtl8169_private *tp) |
876 | { | |
877 | mutex_lock(&tp->wk.mutex); | |
878 | } | |
879 | ||
880 | static void rtl_unlock_work(struct rtl8169_private *tp) | |
881 | { | |
882 | mutex_unlock(&tp->wk.mutex); | |
883 | } | |
884 | ||
d58d46b5 FR |
885 | static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force) |
886 | { | |
7d7903b2 JL |
887 | pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL, |
888 | PCI_EXP_DEVCTL_READRQ, force); | |
d58d46b5 FR |
889 | } |
890 | ||
ffc46952 FR |
891 | struct rtl_cond { |
892 | bool (*check)(struct rtl8169_private *); | |
893 | const char *msg; | |
894 | }; | |
895 | ||
896 | static void rtl_udelay(unsigned int d) | |
897 | { | |
898 | udelay(d); | |
899 | } | |
900 | ||
901 | static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c, | |
902 | void (*delay)(unsigned int), unsigned int d, int n, | |
903 | bool high) | |
904 | { | |
905 | int i; | |
906 | ||
907 | for (i = 0; i < n; i++) { | |
908 | delay(d); | |
909 | if (c->check(tp) == high) | |
910 | return true; | |
911 | } | |
82e316ef FR |
912 | netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n", |
913 | c->msg, !high, n, d); | |
ffc46952 FR |
914 | return false; |
915 | } | |
916 | ||
917 | static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp, | |
918 | const struct rtl_cond *c, | |
919 | unsigned int d, int n) | |
920 | { | |
921 | return rtl_loop_wait(tp, c, rtl_udelay, d, n, true); | |
922 | } | |
923 | ||
924 | static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp, | |
925 | const struct rtl_cond *c, | |
926 | unsigned int d, int n) | |
927 | { | |
928 | return rtl_loop_wait(tp, c, rtl_udelay, d, n, false); | |
929 | } | |
930 | ||
931 | static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp, | |
932 | const struct rtl_cond *c, | |
933 | unsigned int d, int n) | |
934 | { | |
935 | return rtl_loop_wait(tp, c, msleep, d, n, true); | |
936 | } | |
937 | ||
938 | static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp, | |
939 | const struct rtl_cond *c, | |
940 | unsigned int d, int n) | |
941 | { | |
942 | return rtl_loop_wait(tp, c, msleep, d, n, false); | |
943 | } | |
944 | ||
945 | #define DECLARE_RTL_COND(name) \ | |
946 | static bool name ## _check(struct rtl8169_private *); \ | |
947 | \ | |
948 | static const struct rtl_cond name = { \ | |
949 | .check = name ## _check, \ | |
950 | .msg = #name \ | |
951 | }; \ | |
952 | \ | |
953 | static bool name ## _check(struct rtl8169_private *tp) | |
954 | ||
c558386b HW |
955 | static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg) |
956 | { | |
957 | if (reg & 0xffff0001) { | |
958 | netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg); | |
959 | return true; | |
960 | } | |
961 | return false; | |
962 | } | |
963 | ||
964 | DECLARE_RTL_COND(rtl_ocp_gphy_cond) | |
965 | { | |
966 | void __iomem *ioaddr = tp->mmio_addr; | |
967 | ||
968 | return RTL_R32(GPHY_OCP) & OCPAR_FLAG; | |
969 | } | |
970 | ||
971 | static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) | |
972 | { | |
973 | void __iomem *ioaddr = tp->mmio_addr; | |
974 | ||
975 | if (rtl_ocp_reg_failure(tp, reg)) | |
976 | return; | |
977 | ||
978 | RTL_W32(GPHY_OCP, OCPAR_FLAG | (reg << 15) | data); | |
979 | ||
980 | rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10); | |
981 | } | |
982 | ||
983 | static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg) | |
984 | { | |
985 | void __iomem *ioaddr = tp->mmio_addr; | |
986 | ||
987 | if (rtl_ocp_reg_failure(tp, reg)) | |
988 | return 0; | |
989 | ||
990 | RTL_W32(GPHY_OCP, reg << 15); | |
991 | ||
992 | return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ? | |
993 | (RTL_R32(GPHY_OCP) & 0xffff) : ~0; | |
994 | } | |
995 | ||
c558386b HW |
996 | static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) |
997 | { | |
998 | void __iomem *ioaddr = tp->mmio_addr; | |
999 | ||
1000 | if (rtl_ocp_reg_failure(tp, reg)) | |
1001 | return; | |
1002 | ||
1003 | RTL_W32(OCPDR, OCPAR_FLAG | (reg << 15) | data); | |
c558386b HW |
1004 | } |
1005 | ||
1006 | static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg) | |
1007 | { | |
1008 | void __iomem *ioaddr = tp->mmio_addr; | |
1009 | ||
1010 | if (rtl_ocp_reg_failure(tp, reg)) | |
1011 | return 0; | |
1012 | ||
1013 | RTL_W32(OCPDR, reg << 15); | |
1014 | ||
3a83ad12 | 1015 | return RTL_R32(OCPDR); |
c558386b HW |
1016 | } |
1017 | ||
1018 | #define OCP_STD_PHY_BASE 0xa400 | |
1019 | ||
1020 | static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value) | |
1021 | { | |
1022 | if (reg == 0x1f) { | |
1023 | tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE; | |
1024 | return; | |
1025 | } | |
1026 | ||
1027 | if (tp->ocp_base != OCP_STD_PHY_BASE) | |
1028 | reg -= 0x10; | |
1029 | ||
1030 | r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value); | |
1031 | } | |
1032 | ||
1033 | static int r8168g_mdio_read(struct rtl8169_private *tp, int reg) | |
1034 | { | |
1035 | if (tp->ocp_base != OCP_STD_PHY_BASE) | |
1036 | reg -= 0x10; | |
1037 | ||
1038 | return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2); | |
1039 | } | |
1040 | ||
eee3786f | 1041 | static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value) |
1042 | { | |
1043 | if (reg == 0x1f) { | |
1044 | tp->ocp_base = value << 4; | |
1045 | return; | |
1046 | } | |
1047 | ||
1048 | r8168_mac_ocp_write(tp, tp->ocp_base + reg, value); | |
1049 | } | |
1050 | ||
1051 | static int mac_mcu_read(struct rtl8169_private *tp, int reg) | |
1052 | { | |
1053 | return r8168_mac_ocp_read(tp, tp->ocp_base + reg); | |
1054 | } | |
1055 | ||
ffc46952 FR |
1056 | DECLARE_RTL_COND(rtl_phyar_cond) |
1057 | { | |
1058 | void __iomem *ioaddr = tp->mmio_addr; | |
1059 | ||
1060 | return RTL_R32(PHYAR) & 0x80000000; | |
1061 | } | |
1062 | ||
24192210 | 1063 | static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value) |
1da177e4 | 1064 | { |
24192210 | 1065 | void __iomem *ioaddr = tp->mmio_addr; |
1da177e4 | 1066 | |
24192210 | 1067 | RTL_W32(PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff)); |
1da177e4 | 1068 | |
ffc46952 | 1069 | rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20); |
024a07ba | 1070 | /* |
81a95f04 TT |
1071 | * According to hardware specs a 20us delay is required after write |
1072 | * complete indication, but before sending next command. | |
024a07ba | 1073 | */ |
81a95f04 | 1074 | udelay(20); |
1da177e4 LT |
1075 | } |
1076 | ||
24192210 | 1077 | static int r8169_mdio_read(struct rtl8169_private *tp, int reg) |
1da177e4 | 1078 | { |
24192210 | 1079 | void __iomem *ioaddr = tp->mmio_addr; |
ffc46952 | 1080 | int value; |
1da177e4 | 1081 | |
24192210 | 1082 | RTL_W32(PHYAR, 0x0 | (reg & 0x1f) << 16); |
1da177e4 | 1083 | |
ffc46952 FR |
1084 | value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ? |
1085 | RTL_R32(PHYAR) & 0xffff : ~0; | |
1086 | ||
81a95f04 TT |
1087 | /* |
1088 | * According to hardware specs a 20us delay is required after read | |
1089 | * complete indication, but before sending next command. | |
1090 | */ | |
1091 | udelay(20); | |
1092 | ||
1da177e4 LT |
1093 | return value; |
1094 | } | |
1095 | ||
935e2218 CHL |
1096 | DECLARE_RTL_COND(rtl_ocpar_cond) |
1097 | { | |
1098 | void __iomem *ioaddr = tp->mmio_addr; | |
1099 | ||
1100 | return RTL_R32(OCPAR) & OCPAR_FLAG; | |
1101 | } | |
1102 | ||
24192210 | 1103 | static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data) |
c0e45c1c | 1104 | { |
24192210 | 1105 | void __iomem *ioaddr = tp->mmio_addr; |
c0e45c1c | 1106 | |
24192210 | 1107 | RTL_W32(OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT)); |
c0e45c1c | 1108 | RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD); |
1109 | RTL_W32(EPHY_RXER_NUM, 0); | |
1110 | ||
ffc46952 | 1111 | rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100); |
c0e45c1c | 1112 | } |
1113 | ||
24192210 | 1114 | static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value) |
c0e45c1c | 1115 | { |
24192210 FR |
1116 | r8168dp_1_mdio_access(tp, reg, |
1117 | OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK)); | |
c0e45c1c | 1118 | } |
1119 | ||
24192210 | 1120 | static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg) |
c0e45c1c | 1121 | { |
24192210 | 1122 | void __iomem *ioaddr = tp->mmio_addr; |
c0e45c1c | 1123 | |
24192210 | 1124 | r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD); |
c0e45c1c | 1125 | |
1126 | mdelay(1); | |
1127 | RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD); | |
1128 | RTL_W32(EPHY_RXER_NUM, 0); | |
1129 | ||
ffc46952 FR |
1130 | return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ? |
1131 | RTL_R32(OCPDR) & OCPDR_DATA_MASK : ~0; | |
c0e45c1c | 1132 | } |
1133 | ||
e6de30d6 | 1134 | #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000 |
1135 | ||
1136 | static void r8168dp_2_mdio_start(void __iomem *ioaddr) | |
1137 | { | |
1138 | RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT); | |
1139 | } | |
1140 | ||
1141 | static void r8168dp_2_mdio_stop(void __iomem *ioaddr) | |
1142 | { | |
1143 | RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT); | |
1144 | } | |
1145 | ||
24192210 | 1146 | static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value) |
e6de30d6 | 1147 | { |
24192210 FR |
1148 | void __iomem *ioaddr = tp->mmio_addr; |
1149 | ||
e6de30d6 | 1150 | r8168dp_2_mdio_start(ioaddr); |
1151 | ||
24192210 | 1152 | r8169_mdio_write(tp, reg, value); |
e6de30d6 | 1153 | |
1154 | r8168dp_2_mdio_stop(ioaddr); | |
1155 | } | |
1156 | ||
24192210 | 1157 | static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg) |
e6de30d6 | 1158 | { |
24192210 | 1159 | void __iomem *ioaddr = tp->mmio_addr; |
e6de30d6 | 1160 | int value; |
1161 | ||
1162 | r8168dp_2_mdio_start(ioaddr); | |
1163 | ||
24192210 | 1164 | value = r8169_mdio_read(tp, reg); |
e6de30d6 | 1165 | |
1166 | r8168dp_2_mdio_stop(ioaddr); | |
1167 | ||
1168 | return value; | |
1169 | } | |
1170 | ||
4da19633 | 1171 | static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val) |
dacf8154 | 1172 | { |
24192210 | 1173 | tp->mdio_ops.write(tp, location, val); |
dacf8154 FR |
1174 | } |
1175 | ||
4da19633 | 1176 | static int rtl_readphy(struct rtl8169_private *tp, int location) |
1177 | { | |
24192210 | 1178 | return tp->mdio_ops.read(tp, location); |
4da19633 | 1179 | } |
1180 | ||
1181 | static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value) | |
1182 | { | |
1183 | rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value); | |
1184 | } | |
1185 | ||
76564428 | 1186 | static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m) |
daf9df6d | 1187 | { |
1188 | int val; | |
1189 | ||
4da19633 | 1190 | val = rtl_readphy(tp, reg_addr); |
76564428 | 1191 | rtl_writephy(tp, reg_addr, (val & ~m) | p); |
daf9df6d | 1192 | } |
1193 | ||
ccdffb9a FR |
1194 | static void rtl_mdio_write(struct net_device *dev, int phy_id, int location, |
1195 | int val) | |
1196 | { | |
1197 | struct rtl8169_private *tp = netdev_priv(dev); | |
ccdffb9a | 1198 | |
4da19633 | 1199 | rtl_writephy(tp, location, val); |
ccdffb9a FR |
1200 | } |
1201 | ||
1202 | static int rtl_mdio_read(struct net_device *dev, int phy_id, int location) | |
1203 | { | |
1204 | struct rtl8169_private *tp = netdev_priv(dev); | |
ccdffb9a | 1205 | |
4da19633 | 1206 | return rtl_readphy(tp, location); |
ccdffb9a FR |
1207 | } |
1208 | ||
ffc46952 FR |
1209 | DECLARE_RTL_COND(rtl_ephyar_cond) |
1210 | { | |
1211 | void __iomem *ioaddr = tp->mmio_addr; | |
1212 | ||
1213 | return RTL_R32(EPHYAR) & EPHYAR_FLAG; | |
1214 | } | |
1215 | ||
fdf6fc06 | 1216 | static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value) |
dacf8154 | 1217 | { |
fdf6fc06 | 1218 | void __iomem *ioaddr = tp->mmio_addr; |
dacf8154 FR |
1219 | |
1220 | RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) | | |
1221 | (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); | |
1222 | ||
ffc46952 FR |
1223 | rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100); |
1224 | ||
1225 | udelay(10); | |
dacf8154 FR |
1226 | } |
1227 | ||
fdf6fc06 | 1228 | static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr) |
dacf8154 | 1229 | { |
fdf6fc06 | 1230 | void __iomem *ioaddr = tp->mmio_addr; |
dacf8154 FR |
1231 | |
1232 | RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); | |
1233 | ||
ffc46952 FR |
1234 | return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ? |
1235 | RTL_R32(EPHYAR) & EPHYAR_DATA_MASK : ~0; | |
dacf8154 FR |
1236 | } |
1237 | ||
935e2218 CHL |
1238 | DECLARE_RTL_COND(rtl_eriar_cond) |
1239 | { | |
1240 | void __iomem *ioaddr = tp->mmio_addr; | |
1241 | ||
1242 | return RTL_R32(ERIAR) & ERIAR_FLAG; | |
1243 | } | |
1244 | ||
fdf6fc06 FR |
1245 | static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, |
1246 | u32 val, int type) | |
133ac40a | 1247 | { |
fdf6fc06 | 1248 | void __iomem *ioaddr = tp->mmio_addr; |
133ac40a HW |
1249 | |
1250 | BUG_ON((addr & 3) || (mask == 0)); | |
1251 | RTL_W32(ERIDR, val); | |
1252 | RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr); | |
1253 | ||
ffc46952 | 1254 | rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100); |
133ac40a HW |
1255 | } |
1256 | ||
fdf6fc06 | 1257 | static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type) |
133ac40a | 1258 | { |
fdf6fc06 | 1259 | void __iomem *ioaddr = tp->mmio_addr; |
133ac40a HW |
1260 | |
1261 | RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr); | |
1262 | ||
ffc46952 FR |
1263 | return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ? |
1264 | RTL_R32(ERIDR) : ~0; | |
133ac40a HW |
1265 | } |
1266 | ||
706123d0 | 1267 | static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p, |
fdf6fc06 | 1268 | u32 m, int type) |
133ac40a HW |
1269 | { |
1270 | u32 val; | |
1271 | ||
fdf6fc06 FR |
1272 | val = rtl_eri_read(tp, addr, type); |
1273 | rtl_eri_write(tp, addr, mask, (val & ~m) | p, type); | |
133ac40a HW |
1274 | } |
1275 | ||
935e2218 CHL |
1276 | static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg) |
1277 | { | |
1278 | void __iomem *ioaddr = tp->mmio_addr; | |
1279 | ||
1280 | RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); | |
1281 | return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ? | |
1282 | RTL_R32(OCPDR) : ~0; | |
1283 | } | |
1284 | ||
1285 | static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg) | |
1286 | { | |
1287 | return rtl_eri_read(tp, reg, ERIAR_OOB); | |
1288 | } | |
1289 | ||
1290 | static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg) | |
1291 | { | |
1292 | switch (tp->mac_version) { | |
1293 | case RTL_GIGA_MAC_VER_27: | |
1294 | case RTL_GIGA_MAC_VER_28: | |
1295 | case RTL_GIGA_MAC_VER_31: | |
1296 | return r8168dp_ocp_read(tp, mask, reg); | |
1297 | case RTL_GIGA_MAC_VER_49: | |
1298 | case RTL_GIGA_MAC_VER_50: | |
1299 | case RTL_GIGA_MAC_VER_51: | |
1300 | return r8168ep_ocp_read(tp, mask, reg); | |
1301 | default: | |
1302 | BUG(); | |
1303 | return ~0; | |
1304 | } | |
1305 | } | |
1306 | ||
1307 | static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, | |
1308 | u32 data) | |
1309 | { | |
1310 | void __iomem *ioaddr = tp->mmio_addr; | |
1311 | ||
1312 | RTL_W32(OCPDR, data); | |
1313 | RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); | |
1314 | rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20); | |
1315 | } | |
1316 | ||
1317 | static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, | |
1318 | u32 data) | |
1319 | { | |
1320 | rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT, | |
1321 | data, ERIAR_OOB); | |
1322 | } | |
1323 | ||
1324 | static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data) | |
1325 | { | |
1326 | switch (tp->mac_version) { | |
1327 | case RTL_GIGA_MAC_VER_27: | |
1328 | case RTL_GIGA_MAC_VER_28: | |
1329 | case RTL_GIGA_MAC_VER_31: | |
1330 | r8168dp_ocp_write(tp, mask, reg, data); | |
1331 | break; | |
1332 | case RTL_GIGA_MAC_VER_49: | |
1333 | case RTL_GIGA_MAC_VER_50: | |
1334 | case RTL_GIGA_MAC_VER_51: | |
1335 | r8168ep_ocp_write(tp, mask, reg, data); | |
1336 | break; | |
1337 | default: | |
1338 | BUG(); | |
1339 | break; | |
1340 | } | |
1341 | } | |
1342 | ||
2a9b4d96 CHL |
1343 | static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd) |
1344 | { | |
1345 | rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd, ERIAR_EXGMAC); | |
1346 | ||
1347 | ocp_write(tp, 0x1, 0x30, 0x00000001); | |
1348 | } | |
1349 | ||
1350 | #define OOB_CMD_RESET 0x00 | |
1351 | #define OOB_CMD_DRIVER_START 0x05 | |
1352 | #define OOB_CMD_DRIVER_STOP 0x06 | |
1353 | ||
1354 | static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp) | |
1355 | { | |
1356 | return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10; | |
1357 | } | |
1358 | ||
1359 | DECLARE_RTL_COND(rtl_ocp_read_cond) | |
1360 | { | |
1361 | u16 reg; | |
1362 | ||
1363 | reg = rtl8168_get_ocp_reg(tp); | |
1364 | ||
1365 | return ocp_read(tp, 0x0f, reg) & 0x00000800; | |
1366 | } | |
1367 | ||
935e2218 | 1368 | DECLARE_RTL_COND(rtl_ep_ocp_read_cond) |
2a9b4d96 | 1369 | { |
935e2218 CHL |
1370 | return ocp_read(tp, 0x0f, 0x124) & 0x00000001; |
1371 | } | |
1372 | ||
1373 | DECLARE_RTL_COND(rtl_ocp_tx_cond) | |
1374 | { | |
1375 | void __iomem *ioaddr = tp->mmio_addr; | |
1376 | ||
1377 | return RTL_R8(IBISR0) & 0x02; | |
1378 | } | |
2a9b4d96 | 1379 | |
003609da CHL |
1380 | static void rtl8168ep_stop_cmac(struct rtl8169_private *tp) |
1381 | { | |
1382 | void __iomem *ioaddr = tp->mmio_addr; | |
1383 | ||
1384 | RTL_W8(IBCR2, RTL_R8(IBCR2) & ~0x01); | |
1385 | rtl_msleep_loop_wait_low(tp, &rtl_ocp_tx_cond, 50, 2000); | |
1386 | RTL_W8(IBISR0, RTL_R8(IBISR0) | 0x20); | |
1387 | RTL_W8(IBCR0, RTL_R8(IBCR0) & ~0x01); | |
1388 | } | |
1389 | ||
935e2218 CHL |
1390 | static void rtl8168dp_driver_start(struct rtl8169_private *tp) |
1391 | { | |
1392 | rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START); | |
2a9b4d96 CHL |
1393 | rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10); |
1394 | } | |
1395 | ||
935e2218 | 1396 | static void rtl8168ep_driver_start(struct rtl8169_private *tp) |
2a9b4d96 | 1397 | { |
935e2218 CHL |
1398 | ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START); |
1399 | ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01); | |
1400 | rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10); | |
1401 | } | |
1402 | ||
1403 | static void rtl8168_driver_start(struct rtl8169_private *tp) | |
1404 | { | |
1405 | switch (tp->mac_version) { | |
1406 | case RTL_GIGA_MAC_VER_27: | |
1407 | case RTL_GIGA_MAC_VER_28: | |
1408 | case RTL_GIGA_MAC_VER_31: | |
1409 | rtl8168dp_driver_start(tp); | |
1410 | break; | |
1411 | case RTL_GIGA_MAC_VER_49: | |
1412 | case RTL_GIGA_MAC_VER_50: | |
1413 | case RTL_GIGA_MAC_VER_51: | |
1414 | rtl8168ep_driver_start(tp); | |
1415 | break; | |
1416 | default: | |
1417 | BUG(); | |
1418 | break; | |
1419 | } | |
1420 | } | |
2a9b4d96 | 1421 | |
935e2218 CHL |
1422 | static void rtl8168dp_driver_stop(struct rtl8169_private *tp) |
1423 | { | |
1424 | rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP); | |
2a9b4d96 CHL |
1425 | rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10); |
1426 | } | |
1427 | ||
935e2218 CHL |
1428 | static void rtl8168ep_driver_stop(struct rtl8169_private *tp) |
1429 | { | |
003609da | 1430 | rtl8168ep_stop_cmac(tp); |
935e2218 CHL |
1431 | ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP); |
1432 | ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01); | |
1433 | rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10); | |
1434 | } | |
1435 | ||
1436 | static void rtl8168_driver_stop(struct rtl8169_private *tp) | |
1437 | { | |
1438 | switch (tp->mac_version) { | |
1439 | case RTL_GIGA_MAC_VER_27: | |
1440 | case RTL_GIGA_MAC_VER_28: | |
1441 | case RTL_GIGA_MAC_VER_31: | |
1442 | rtl8168dp_driver_stop(tp); | |
1443 | break; | |
1444 | case RTL_GIGA_MAC_VER_49: | |
1445 | case RTL_GIGA_MAC_VER_50: | |
1446 | case RTL_GIGA_MAC_VER_51: | |
1447 | rtl8168ep_driver_stop(tp); | |
1448 | break; | |
1449 | default: | |
1450 | BUG(); | |
1451 | break; | |
1452 | } | |
1453 | } | |
1454 | ||
1455 | static int r8168dp_check_dash(struct rtl8169_private *tp) | |
2a9b4d96 CHL |
1456 | { |
1457 | u16 reg = rtl8168_get_ocp_reg(tp); | |
1458 | ||
1459 | return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0; | |
1460 | } | |
1461 | ||
935e2218 CHL |
1462 | static int r8168ep_check_dash(struct rtl8169_private *tp) |
1463 | { | |
1464 | return (ocp_read(tp, 0x0f, 0x128) & 0x00000001) ? 1 : 0; | |
1465 | } | |
1466 | ||
1467 | static int r8168_check_dash(struct rtl8169_private *tp) | |
1468 | { | |
1469 | switch (tp->mac_version) { | |
1470 | case RTL_GIGA_MAC_VER_27: | |
1471 | case RTL_GIGA_MAC_VER_28: | |
1472 | case RTL_GIGA_MAC_VER_31: | |
1473 | return r8168dp_check_dash(tp); | |
1474 | case RTL_GIGA_MAC_VER_49: | |
1475 | case RTL_GIGA_MAC_VER_50: | |
1476 | case RTL_GIGA_MAC_VER_51: | |
1477 | return r8168ep_check_dash(tp); | |
1478 | default: | |
1479 | return 0; | |
1480 | } | |
1481 | } | |
1482 | ||
c28aa385 | 1483 | struct exgmac_reg { |
1484 | u16 addr; | |
1485 | u16 mask; | |
1486 | u32 val; | |
1487 | }; | |
1488 | ||
fdf6fc06 | 1489 | static void rtl_write_exgmac_batch(struct rtl8169_private *tp, |
c28aa385 | 1490 | const struct exgmac_reg *r, int len) |
1491 | { | |
1492 | while (len-- > 0) { | |
fdf6fc06 | 1493 | rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC); |
c28aa385 | 1494 | r++; |
1495 | } | |
1496 | } | |
1497 | ||
ffc46952 FR |
1498 | DECLARE_RTL_COND(rtl_efusear_cond) |
1499 | { | |
1500 | void __iomem *ioaddr = tp->mmio_addr; | |
1501 | ||
1502 | return RTL_R32(EFUSEAR) & EFUSEAR_FLAG; | |
1503 | } | |
1504 | ||
fdf6fc06 | 1505 | static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr) |
daf9df6d | 1506 | { |
fdf6fc06 | 1507 | void __iomem *ioaddr = tp->mmio_addr; |
daf9df6d | 1508 | |
1509 | RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT); | |
1510 | ||
ffc46952 FR |
1511 | return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ? |
1512 | RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK : ~0; | |
daf9df6d | 1513 | } |
1514 | ||
9085cdfa FR |
1515 | static u16 rtl_get_events(struct rtl8169_private *tp) |
1516 | { | |
1517 | void __iomem *ioaddr = tp->mmio_addr; | |
1518 | ||
1519 | return RTL_R16(IntrStatus); | |
1520 | } | |
1521 | ||
1522 | static void rtl_ack_events(struct rtl8169_private *tp, u16 bits) | |
1523 | { | |
1524 | void __iomem *ioaddr = tp->mmio_addr; | |
1525 | ||
1526 | RTL_W16(IntrStatus, bits); | |
1527 | mmiowb(); | |
1528 | } | |
1529 | ||
1530 | static void rtl_irq_disable(struct rtl8169_private *tp) | |
1531 | { | |
1532 | void __iomem *ioaddr = tp->mmio_addr; | |
1533 | ||
1534 | RTL_W16(IntrMask, 0); | |
1535 | mmiowb(); | |
1536 | } | |
1537 | ||
3e990ff5 FR |
1538 | static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits) |
1539 | { | |
1540 | void __iomem *ioaddr = tp->mmio_addr; | |
1541 | ||
1542 | RTL_W16(IntrMask, bits); | |
1543 | } | |
1544 | ||
da78dbff FR |
1545 | #define RTL_EVENT_NAPI_RX (RxOK | RxErr) |
1546 | #define RTL_EVENT_NAPI_TX (TxOK | TxErr) | |
1547 | #define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX) | |
1548 | ||
1549 | static void rtl_irq_enable_all(struct rtl8169_private *tp) | |
1550 | { | |
1551 | rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow); | |
1552 | } | |
1553 | ||
811fd301 | 1554 | static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp) |
1da177e4 | 1555 | { |
811fd301 | 1556 | void __iomem *ioaddr = tp->mmio_addr; |
1da177e4 | 1557 | |
9085cdfa | 1558 | rtl_irq_disable(tp); |
da78dbff | 1559 | rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow); |
811fd301 | 1560 | RTL_R8(ChipCmd); |
1da177e4 LT |
1561 | } |
1562 | ||
4da19633 | 1563 | static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp) |
1da177e4 | 1564 | { |
4da19633 | 1565 | void __iomem *ioaddr = tp->mmio_addr; |
1566 | ||
1da177e4 LT |
1567 | return RTL_R32(TBICSR) & TBIReset; |
1568 | } | |
1569 | ||
4da19633 | 1570 | static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp) |
1da177e4 | 1571 | { |
4da19633 | 1572 | return rtl_readphy(tp, MII_BMCR) & BMCR_RESET; |
1da177e4 LT |
1573 | } |
1574 | ||
1575 | static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr) | |
1576 | { | |
1577 | return RTL_R32(TBICSR) & TBILinkOk; | |
1578 | } | |
1579 | ||
1580 | static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr) | |
1581 | { | |
1582 | return RTL_R8(PHYstatus) & LinkStatus; | |
1583 | } | |
1584 | ||
4da19633 | 1585 | static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp) |
1da177e4 | 1586 | { |
4da19633 | 1587 | void __iomem *ioaddr = tp->mmio_addr; |
1588 | ||
1da177e4 LT |
1589 | RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset); |
1590 | } | |
1591 | ||
4da19633 | 1592 | static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp) |
1da177e4 LT |
1593 | { |
1594 | unsigned int val; | |
1595 | ||
4da19633 | 1596 | val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET; |
1597 | rtl_writephy(tp, MII_BMCR, val & 0xffff); | |
1da177e4 LT |
1598 | } |
1599 | ||
70090424 HW |
1600 | static void rtl_link_chg_patch(struct rtl8169_private *tp) |
1601 | { | |
1602 | void __iomem *ioaddr = tp->mmio_addr; | |
1603 | struct net_device *dev = tp->dev; | |
1604 | ||
1605 | if (!netif_running(dev)) | |
1606 | return; | |
1607 | ||
b3d7b2f2 HW |
1608 | if (tp->mac_version == RTL_GIGA_MAC_VER_34 || |
1609 | tp->mac_version == RTL_GIGA_MAC_VER_38) { | |
70090424 | 1610 | if (RTL_R8(PHYstatus) & _1000bpsF) { |
fdf6fc06 FR |
1611 | rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011, |
1612 | ERIAR_EXGMAC); | |
1613 | rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005, | |
1614 | ERIAR_EXGMAC); | |
70090424 | 1615 | } else if (RTL_R8(PHYstatus) & _100bps) { |
fdf6fc06 FR |
1616 | rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f, |
1617 | ERIAR_EXGMAC); | |
1618 | rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005, | |
1619 | ERIAR_EXGMAC); | |
70090424 | 1620 | } else { |
fdf6fc06 FR |
1621 | rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f, |
1622 | ERIAR_EXGMAC); | |
1623 | rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f, | |
1624 | ERIAR_EXGMAC); | |
70090424 HW |
1625 | } |
1626 | /* Reset packet filter */ | |
706123d0 | 1627 | rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, |
70090424 | 1628 | ERIAR_EXGMAC); |
706123d0 | 1629 | rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, |
70090424 | 1630 | ERIAR_EXGMAC); |
c2218925 HW |
1631 | } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 || |
1632 | tp->mac_version == RTL_GIGA_MAC_VER_36) { | |
1633 | if (RTL_R8(PHYstatus) & _1000bpsF) { | |
fdf6fc06 FR |
1634 | rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011, |
1635 | ERIAR_EXGMAC); | |
1636 | rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005, | |
1637 | ERIAR_EXGMAC); | |
c2218925 | 1638 | } else { |
fdf6fc06 FR |
1639 | rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f, |
1640 | ERIAR_EXGMAC); | |
1641 | rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f, | |
1642 | ERIAR_EXGMAC); | |
c2218925 | 1643 | } |
7e18dca1 HW |
1644 | } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) { |
1645 | if (RTL_R8(PHYstatus) & _10bps) { | |
fdf6fc06 FR |
1646 | rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02, |
1647 | ERIAR_EXGMAC); | |
1648 | rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060, | |
1649 | ERIAR_EXGMAC); | |
7e18dca1 | 1650 | } else { |
fdf6fc06 FR |
1651 | rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, |
1652 | ERIAR_EXGMAC); | |
7e18dca1 | 1653 | } |
70090424 HW |
1654 | } |
1655 | } | |
1656 | ||
e4fbce74 | 1657 | static void __rtl8169_check_link_status(struct net_device *dev, |
cecb5fd7 FR |
1658 | struct rtl8169_private *tp, |
1659 | void __iomem *ioaddr, bool pm) | |
1da177e4 | 1660 | { |
1da177e4 | 1661 | if (tp->link_ok(ioaddr)) { |
70090424 | 1662 | rtl_link_chg_patch(tp); |
e1759441 | 1663 | /* This is to cancel a scheduled suspend if there's one. */ |
e4fbce74 RW |
1664 | if (pm) |
1665 | pm_request_resume(&tp->pci_dev->dev); | |
1da177e4 | 1666 | netif_carrier_on(dev); |
1519e57f FR |
1667 | if (net_ratelimit()) |
1668 | netif_info(tp, ifup, dev, "link up\n"); | |
b57b7e5a | 1669 | } else { |
1da177e4 | 1670 | netif_carrier_off(dev); |
bf82c189 | 1671 | netif_info(tp, ifdown, dev, "link down\n"); |
e4fbce74 | 1672 | if (pm) |
10953db8 | 1673 | pm_schedule_suspend(&tp->pci_dev->dev, 5000); |
b57b7e5a | 1674 | } |
1da177e4 LT |
1675 | } |
1676 | ||
e4fbce74 RW |
1677 | static void rtl8169_check_link_status(struct net_device *dev, |
1678 | struct rtl8169_private *tp, | |
1679 | void __iomem *ioaddr) | |
1680 | { | |
1681 | __rtl8169_check_link_status(dev, tp, ioaddr, false); | |
1682 | } | |
1683 | ||
e1759441 RW |
1684 | #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) |
1685 | ||
1686 | static u32 __rtl8169_get_wol(struct rtl8169_private *tp) | |
61a4dcc2 | 1687 | { |
61a4dcc2 FR |
1688 | void __iomem *ioaddr = tp->mmio_addr; |
1689 | u8 options; | |
e1759441 | 1690 | u32 wolopts = 0; |
61a4dcc2 FR |
1691 | |
1692 | options = RTL_R8(Config1); | |
1693 | if (!(options & PMEnable)) | |
e1759441 | 1694 | return 0; |
61a4dcc2 FR |
1695 | |
1696 | options = RTL_R8(Config3); | |
1697 | if (options & LinkUp) | |
e1759441 | 1698 | wolopts |= WAKE_PHY; |
6e1d0b89 | 1699 | switch (tp->mac_version) { |
ac85bcdb CHL |
1700 | case RTL_GIGA_MAC_VER_34: |
1701 | case RTL_GIGA_MAC_VER_35: | |
1702 | case RTL_GIGA_MAC_VER_36: | |
1703 | case RTL_GIGA_MAC_VER_37: | |
1704 | case RTL_GIGA_MAC_VER_38: | |
1705 | case RTL_GIGA_MAC_VER_40: | |
1706 | case RTL_GIGA_MAC_VER_41: | |
1707 | case RTL_GIGA_MAC_VER_42: | |
1708 | case RTL_GIGA_MAC_VER_43: | |
1709 | case RTL_GIGA_MAC_VER_44: | |
6e1d0b89 CHL |
1710 | case RTL_GIGA_MAC_VER_45: |
1711 | case RTL_GIGA_MAC_VER_46: | |
ac85bcdb CHL |
1712 | case RTL_GIGA_MAC_VER_47: |
1713 | case RTL_GIGA_MAC_VER_48: | |
935e2218 CHL |
1714 | case RTL_GIGA_MAC_VER_49: |
1715 | case RTL_GIGA_MAC_VER_50: | |
1716 | case RTL_GIGA_MAC_VER_51: | |
6e1d0b89 CHL |
1717 | if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2) |
1718 | wolopts |= WAKE_MAGIC; | |
1719 | break; | |
1720 | default: | |
1721 | if (options & MagicPacket) | |
1722 | wolopts |= WAKE_MAGIC; | |
1723 | break; | |
1724 | } | |
61a4dcc2 FR |
1725 | |
1726 | options = RTL_R8(Config5); | |
1727 | if (options & UWF) | |
e1759441 | 1728 | wolopts |= WAKE_UCAST; |
61a4dcc2 | 1729 | if (options & BWF) |
e1759441 | 1730 | wolopts |= WAKE_BCAST; |
61a4dcc2 | 1731 | if (options & MWF) |
e1759441 | 1732 | wolopts |= WAKE_MCAST; |
61a4dcc2 | 1733 | |
e1759441 | 1734 | return wolopts; |
61a4dcc2 FR |
1735 | } |
1736 | ||
e1759441 | 1737 | static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) |
61a4dcc2 FR |
1738 | { |
1739 | struct rtl8169_private *tp = netdev_priv(dev); | |
e1759441 | 1740 | |
da78dbff | 1741 | rtl_lock_work(tp); |
e1759441 RW |
1742 | |
1743 | wol->supported = WAKE_ANY; | |
1744 | wol->wolopts = __rtl8169_get_wol(tp); | |
1745 | ||
da78dbff | 1746 | rtl_unlock_work(tp); |
e1759441 RW |
1747 | } |
1748 | ||
1749 | static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts) | |
1750 | { | |
61a4dcc2 | 1751 | void __iomem *ioaddr = tp->mmio_addr; |
6e1d0b89 | 1752 | unsigned int i, tmp; |
350f7596 | 1753 | static const struct { |
61a4dcc2 FR |
1754 | u32 opt; |
1755 | u16 reg; | |
1756 | u8 mask; | |
1757 | } cfg[] = { | |
61a4dcc2 | 1758 | { WAKE_PHY, Config3, LinkUp }, |
61a4dcc2 FR |
1759 | { WAKE_UCAST, Config5, UWF }, |
1760 | { WAKE_BCAST, Config5, BWF }, | |
1761 | { WAKE_MCAST, Config5, MWF }, | |
6e1d0b89 CHL |
1762 | { WAKE_ANY, Config5, LanWake }, |
1763 | { WAKE_MAGIC, Config3, MagicPacket } | |
61a4dcc2 | 1764 | }; |
851e6022 | 1765 | u8 options; |
61a4dcc2 | 1766 | |
61a4dcc2 FR |
1767 | RTL_W8(Cfg9346, Cfg9346_Unlock); |
1768 | ||
6e1d0b89 | 1769 | switch (tp->mac_version) { |
ac85bcdb CHL |
1770 | case RTL_GIGA_MAC_VER_34: |
1771 | case RTL_GIGA_MAC_VER_35: | |
1772 | case RTL_GIGA_MAC_VER_36: | |
1773 | case RTL_GIGA_MAC_VER_37: | |
1774 | case RTL_GIGA_MAC_VER_38: | |
1775 | case RTL_GIGA_MAC_VER_40: | |
1776 | case RTL_GIGA_MAC_VER_41: | |
1777 | case RTL_GIGA_MAC_VER_42: | |
1778 | case RTL_GIGA_MAC_VER_43: | |
1779 | case RTL_GIGA_MAC_VER_44: | |
6e1d0b89 CHL |
1780 | case RTL_GIGA_MAC_VER_45: |
1781 | case RTL_GIGA_MAC_VER_46: | |
ac85bcdb CHL |
1782 | case RTL_GIGA_MAC_VER_47: |
1783 | case RTL_GIGA_MAC_VER_48: | |
935e2218 CHL |
1784 | case RTL_GIGA_MAC_VER_49: |
1785 | case RTL_GIGA_MAC_VER_50: | |
1786 | case RTL_GIGA_MAC_VER_51: | |
6e1d0b89 CHL |
1787 | tmp = ARRAY_SIZE(cfg) - 1; |
1788 | if (wolopts & WAKE_MAGIC) | |
706123d0 | 1789 | rtl_w0w1_eri(tp, |
6e1d0b89 CHL |
1790 | 0x0dc, |
1791 | ERIAR_MASK_0100, | |
1792 | MagicPacket_v2, | |
1793 | 0x0000, | |
1794 | ERIAR_EXGMAC); | |
1795 | else | |
706123d0 | 1796 | rtl_w0w1_eri(tp, |
6e1d0b89 CHL |
1797 | 0x0dc, |
1798 | ERIAR_MASK_0100, | |
1799 | 0x0000, | |
1800 | MagicPacket_v2, | |
1801 | ERIAR_EXGMAC); | |
1802 | break; | |
1803 | default: | |
1804 | tmp = ARRAY_SIZE(cfg); | |
1805 | break; | |
1806 | } | |
1807 | ||
1808 | for (i = 0; i < tmp; i++) { | |
851e6022 | 1809 | options = RTL_R8(cfg[i].reg) & ~cfg[i].mask; |
e1759441 | 1810 | if (wolopts & cfg[i].opt) |
61a4dcc2 FR |
1811 | options |= cfg[i].mask; |
1812 | RTL_W8(cfg[i].reg, options); | |
1813 | } | |
1814 | ||
851e6022 FR |
1815 | switch (tp->mac_version) { |
1816 | case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17: | |
1817 | options = RTL_R8(Config1) & ~PMEnable; | |
1818 | if (wolopts) | |
1819 | options |= PMEnable; | |
1820 | RTL_W8(Config1, options); | |
1821 | break; | |
1822 | default: | |
d387b427 FR |
1823 | options = RTL_R8(Config2) & ~PME_SIGNAL; |
1824 | if (wolopts) | |
1825 | options |= PME_SIGNAL; | |
1826 | RTL_W8(Config2, options); | |
851e6022 FR |
1827 | break; |
1828 | } | |
1829 | ||
61a4dcc2 | 1830 | RTL_W8(Cfg9346, Cfg9346_Lock); |
e1759441 RW |
1831 | } |
1832 | ||
1833 | static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
1834 | { | |
1835 | struct rtl8169_private *tp = netdev_priv(dev); | |
1836 | ||
da78dbff | 1837 | rtl_lock_work(tp); |
61a4dcc2 | 1838 | |
f23e7fda FR |
1839 | if (wol->wolopts) |
1840 | tp->features |= RTL_FEATURE_WOL; | |
1841 | else | |
1842 | tp->features &= ~RTL_FEATURE_WOL; | |
e1759441 | 1843 | __rtl8169_set_wol(tp, wol->wolopts); |
da78dbff FR |
1844 | |
1845 | rtl_unlock_work(tp); | |
61a4dcc2 | 1846 | |
ea80907f | 1847 | device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts); |
1848 | ||
61a4dcc2 FR |
1849 | return 0; |
1850 | } | |
1851 | ||
31bd204f FR |
1852 | static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp) |
1853 | { | |
85bffe6c | 1854 | return rtl_chip_infos[tp->mac_version].fw_name; |
31bd204f FR |
1855 | } |
1856 | ||
1da177e4 LT |
1857 | static void rtl8169_get_drvinfo(struct net_device *dev, |
1858 | struct ethtool_drvinfo *info) | |
1859 | { | |
1860 | struct rtl8169_private *tp = netdev_priv(dev); | |
b6ffd97f | 1861 | struct rtl_fw *rtl_fw = tp->rtl_fw; |
1da177e4 | 1862 | |
68aad78c RJ |
1863 | strlcpy(info->driver, MODULENAME, sizeof(info->driver)); |
1864 | strlcpy(info->version, RTL8169_VERSION, sizeof(info->version)); | |
1865 | strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info)); | |
1c361efb | 1866 | BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version)); |
8ac72d16 RJ |
1867 | if (!IS_ERR_OR_NULL(rtl_fw)) |
1868 | strlcpy(info->fw_version, rtl_fw->version, | |
1869 | sizeof(info->fw_version)); | |
1da177e4 LT |
1870 | } |
1871 | ||
1872 | static int rtl8169_get_regs_len(struct net_device *dev) | |
1873 | { | |
1874 | return R8169_REGS_SIZE; | |
1875 | } | |
1876 | ||
1877 | static int rtl8169_set_speed_tbi(struct net_device *dev, | |
54405cde | 1878 | u8 autoneg, u16 speed, u8 duplex, u32 ignored) |
1da177e4 LT |
1879 | { |
1880 | struct rtl8169_private *tp = netdev_priv(dev); | |
1881 | void __iomem *ioaddr = tp->mmio_addr; | |
1882 | int ret = 0; | |
1883 | u32 reg; | |
1884 | ||
1885 | reg = RTL_R32(TBICSR); | |
1886 | if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) && | |
1887 | (duplex == DUPLEX_FULL)) { | |
1888 | RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart)); | |
1889 | } else if (autoneg == AUTONEG_ENABLE) | |
1890 | RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart); | |
1891 | else { | |
bf82c189 JP |
1892 | netif_warn(tp, link, dev, |
1893 | "incorrect speed setting refused in TBI mode\n"); | |
1da177e4 LT |
1894 | ret = -EOPNOTSUPP; |
1895 | } | |
1896 | ||
1897 | return ret; | |
1898 | } | |
1899 | ||
1900 | static int rtl8169_set_speed_xmii(struct net_device *dev, | |
54405cde | 1901 | u8 autoneg, u16 speed, u8 duplex, u32 adv) |
1da177e4 LT |
1902 | { |
1903 | struct rtl8169_private *tp = netdev_priv(dev); | |
3577aa1b | 1904 | int giga_ctrl, bmcr; |
54405cde | 1905 | int rc = -EINVAL; |
1da177e4 | 1906 | |
716b50a3 | 1907 | rtl_writephy(tp, 0x1f, 0x0000); |
1da177e4 LT |
1908 | |
1909 | if (autoneg == AUTONEG_ENABLE) { | |
3577aa1b | 1910 | int auto_nego; |
1911 | ||
4da19633 | 1912 | auto_nego = rtl_readphy(tp, MII_ADVERTISE); |
54405cde ON |
1913 | auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL | |
1914 | ADVERTISE_100HALF | ADVERTISE_100FULL); | |
1915 | ||
1916 | if (adv & ADVERTISED_10baseT_Half) | |
1917 | auto_nego |= ADVERTISE_10HALF; | |
1918 | if (adv & ADVERTISED_10baseT_Full) | |
1919 | auto_nego |= ADVERTISE_10FULL; | |
1920 | if (adv & ADVERTISED_100baseT_Half) | |
1921 | auto_nego |= ADVERTISE_100HALF; | |
1922 | if (adv & ADVERTISED_100baseT_Full) | |
1923 | auto_nego |= ADVERTISE_100FULL; | |
1924 | ||
3577aa1b | 1925 | auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; |
1da177e4 | 1926 | |
4da19633 | 1927 | giga_ctrl = rtl_readphy(tp, MII_CTRL1000); |
3577aa1b | 1928 | giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF); |
bcf0bf90 | 1929 | |
3577aa1b | 1930 | /* The 8100e/8101e/8102e do Fast Ethernet only. */ |
826e6cbd | 1931 | if (tp->mii.supports_gmii) { |
54405cde ON |
1932 | if (adv & ADVERTISED_1000baseT_Half) |
1933 | giga_ctrl |= ADVERTISE_1000HALF; | |
1934 | if (adv & ADVERTISED_1000baseT_Full) | |
1935 | giga_ctrl |= ADVERTISE_1000FULL; | |
1936 | } else if (adv & (ADVERTISED_1000baseT_Half | | |
1937 | ADVERTISED_1000baseT_Full)) { | |
bf82c189 JP |
1938 | netif_info(tp, link, dev, |
1939 | "PHY does not support 1000Mbps\n"); | |
54405cde | 1940 | goto out; |
bcf0bf90 | 1941 | } |
1da177e4 | 1942 | |
3577aa1b | 1943 | bmcr = BMCR_ANENABLE | BMCR_ANRESTART; |
1944 | ||
4da19633 | 1945 | rtl_writephy(tp, MII_ADVERTISE, auto_nego); |
1946 | rtl_writephy(tp, MII_CTRL1000, giga_ctrl); | |
3577aa1b | 1947 | } else { |
1948 | giga_ctrl = 0; | |
1949 | ||
1950 | if (speed == SPEED_10) | |
1951 | bmcr = 0; | |
1952 | else if (speed == SPEED_100) | |
1953 | bmcr = BMCR_SPEED100; | |
1954 | else | |
54405cde | 1955 | goto out; |
3577aa1b | 1956 | |
1957 | if (duplex == DUPLEX_FULL) | |
1958 | bmcr |= BMCR_FULLDPLX; | |
2584fbc3 RS |
1959 | } |
1960 | ||
4da19633 | 1961 | rtl_writephy(tp, MII_BMCR, bmcr); |
3577aa1b | 1962 | |
cecb5fd7 FR |
1963 | if (tp->mac_version == RTL_GIGA_MAC_VER_02 || |
1964 | tp->mac_version == RTL_GIGA_MAC_VER_03) { | |
3577aa1b | 1965 | if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) { |
4da19633 | 1966 | rtl_writephy(tp, 0x17, 0x2138); |
1967 | rtl_writephy(tp, 0x0e, 0x0260); | |
3577aa1b | 1968 | } else { |
4da19633 | 1969 | rtl_writephy(tp, 0x17, 0x2108); |
1970 | rtl_writephy(tp, 0x0e, 0x0000); | |
3577aa1b | 1971 | } |
1972 | } | |
1973 | ||
54405cde ON |
1974 | rc = 0; |
1975 | out: | |
1976 | return rc; | |
1da177e4 LT |
1977 | } |
1978 | ||
1979 | static int rtl8169_set_speed(struct net_device *dev, | |
54405cde | 1980 | u8 autoneg, u16 speed, u8 duplex, u32 advertising) |
1da177e4 LT |
1981 | { |
1982 | struct rtl8169_private *tp = netdev_priv(dev); | |
1983 | int ret; | |
1984 | ||
54405cde | 1985 | ret = tp->set_speed(dev, autoneg, speed, duplex, advertising); |
4876cc1e FR |
1986 | if (ret < 0) |
1987 | goto out; | |
1da177e4 | 1988 | |
4876cc1e FR |
1989 | if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) && |
1990 | (advertising & ADVERTISED_1000baseT_Full)) { | |
1da177e4 | 1991 | mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT); |
4876cc1e FR |
1992 | } |
1993 | out: | |
1da177e4 LT |
1994 | return ret; |
1995 | } | |
1996 | ||
1997 | static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
1998 | { | |
1999 | struct rtl8169_private *tp = netdev_priv(dev); | |
1da177e4 LT |
2000 | int ret; |
2001 | ||
4876cc1e FR |
2002 | del_timer_sync(&tp->timer); |
2003 | ||
da78dbff | 2004 | rtl_lock_work(tp); |
cecb5fd7 | 2005 | ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd), |
25db0338 | 2006 | cmd->duplex, cmd->advertising); |
da78dbff | 2007 | rtl_unlock_work(tp); |
5b0384f4 | 2008 | |
1da177e4 LT |
2009 | return ret; |
2010 | } | |
2011 | ||
c8f44aff MM |
2012 | static netdev_features_t rtl8169_fix_features(struct net_device *dev, |
2013 | netdev_features_t features) | |
1da177e4 | 2014 | { |
d58d46b5 FR |
2015 | struct rtl8169_private *tp = netdev_priv(dev); |
2016 | ||
2b7b4318 | 2017 | if (dev->mtu > TD_MSS_MAX) |
350fb32a | 2018 | features &= ~NETIF_F_ALL_TSO; |
1da177e4 | 2019 | |
d58d46b5 FR |
2020 | if (dev->mtu > JUMBO_1K && |
2021 | !rtl_chip_infos[tp->mac_version].jumbo_tx_csum) | |
2022 | features &= ~NETIF_F_IP_CSUM; | |
2023 | ||
350fb32a | 2024 | return features; |
1da177e4 LT |
2025 | } |
2026 | ||
da78dbff FR |
2027 | static void __rtl8169_set_features(struct net_device *dev, |
2028 | netdev_features_t features) | |
1da177e4 LT |
2029 | { |
2030 | struct rtl8169_private *tp = netdev_priv(dev); | |
da78dbff | 2031 | void __iomem *ioaddr = tp->mmio_addr; |
929a031d | 2032 | u32 rx_config; |
1da177e4 | 2033 | |
929a031d | 2034 | rx_config = RTL_R32(RxConfig); |
2035 | if (features & NETIF_F_RXALL) | |
2036 | rx_config |= (AcceptErr | AcceptRunt); | |
2037 | else | |
2038 | rx_config &= ~(AcceptErr | AcceptRunt); | |
1da177e4 | 2039 | |
929a031d | 2040 | RTL_W32(RxConfig, rx_config); |
350fb32a | 2041 | |
929a031d | 2042 | if (features & NETIF_F_RXCSUM) |
2043 | tp->cp_cmd |= RxChkSum; | |
2044 | else | |
2045 | tp->cp_cmd &= ~RxChkSum; | |
6bbe021d | 2046 | |
929a031d | 2047 | if (features & NETIF_F_HW_VLAN_CTAG_RX) |
2048 | tp->cp_cmd |= RxVlan; | |
2049 | else | |
2050 | tp->cp_cmd &= ~RxVlan; | |
2051 | ||
2052 | tp->cp_cmd |= RTL_R16(CPlusCmd) & ~(RxVlan | RxChkSum); | |
2053 | ||
2054 | RTL_W16(CPlusCmd, tp->cp_cmd); | |
2055 | RTL_R16(CPlusCmd); | |
da78dbff | 2056 | } |
1da177e4 | 2057 | |
da78dbff FR |
2058 | static int rtl8169_set_features(struct net_device *dev, |
2059 | netdev_features_t features) | |
2060 | { | |
2061 | struct rtl8169_private *tp = netdev_priv(dev); | |
2062 | ||
929a031d | 2063 | features &= NETIF_F_RXALL | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX; |
2064 | ||
da78dbff | 2065 | rtl_lock_work(tp); |
85911d71 | 2066 | if (features ^ dev->features) |
929a031d | 2067 | __rtl8169_set_features(dev, features); |
da78dbff | 2068 | rtl_unlock_work(tp); |
1da177e4 LT |
2069 | |
2070 | return 0; | |
2071 | } | |
2072 | ||
da78dbff | 2073 | |
810f4893 | 2074 | static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb) |
1da177e4 | 2075 | { |
eab6d18d | 2076 | return (vlan_tx_tag_present(skb)) ? |
1da177e4 LT |
2077 | TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00; |
2078 | } | |
2079 | ||
7a8fc77b | 2080 | static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb) |
1da177e4 LT |
2081 | { |
2082 | u32 opts2 = le32_to_cpu(desc->opts2); | |
1da177e4 | 2083 | |
7a8fc77b | 2084 | if (opts2 & RxVlanTag) |
86a9bad3 | 2085 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff)); |
1da177e4 LT |
2086 | } |
2087 | ||
ccdffb9a | 2088 | static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd) |
1da177e4 LT |
2089 | { |
2090 | struct rtl8169_private *tp = netdev_priv(dev); | |
2091 | void __iomem *ioaddr = tp->mmio_addr; | |
2092 | u32 status; | |
2093 | ||
2094 | cmd->supported = | |
2095 | SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE; | |
2096 | cmd->port = PORT_FIBRE; | |
2097 | cmd->transceiver = XCVR_INTERNAL; | |
2098 | ||
2099 | status = RTL_R32(TBICSR); | |
2100 | cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0; | |
2101 | cmd->autoneg = !!(status & TBINwEnable); | |
2102 | ||
70739497 | 2103 | ethtool_cmd_speed_set(cmd, SPEED_1000); |
1da177e4 | 2104 | cmd->duplex = DUPLEX_FULL; /* Always set */ |
ccdffb9a FR |
2105 | |
2106 | return 0; | |
1da177e4 LT |
2107 | } |
2108 | ||
ccdffb9a | 2109 | static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd) |
1da177e4 LT |
2110 | { |
2111 | struct rtl8169_private *tp = netdev_priv(dev); | |
ccdffb9a FR |
2112 | |
2113 | return mii_ethtool_gset(&tp->mii, cmd); | |
1da177e4 LT |
2114 | } |
2115 | ||
2116 | static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
2117 | { | |
2118 | struct rtl8169_private *tp = netdev_priv(dev); | |
ccdffb9a | 2119 | int rc; |
1da177e4 | 2120 | |
da78dbff | 2121 | rtl_lock_work(tp); |
ccdffb9a | 2122 | rc = tp->get_settings(dev, cmd); |
da78dbff | 2123 | rtl_unlock_work(tp); |
1da177e4 | 2124 | |
ccdffb9a | 2125 | return rc; |
1da177e4 LT |
2126 | } |
2127 | ||
2128 | static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs, | |
2129 | void *p) | |
2130 | { | |
5b0384f4 | 2131 | struct rtl8169_private *tp = netdev_priv(dev); |
15edae91 PW |
2132 | u32 __iomem *data = tp->mmio_addr; |
2133 | u32 *dw = p; | |
2134 | int i; | |
1da177e4 | 2135 | |
da78dbff | 2136 | rtl_lock_work(tp); |
15edae91 PW |
2137 | for (i = 0; i < R8169_REGS_SIZE; i += 4) |
2138 | memcpy_fromio(dw++, data++, 4); | |
da78dbff | 2139 | rtl_unlock_work(tp); |
1da177e4 LT |
2140 | } |
2141 | ||
b57b7e5a SH |
2142 | static u32 rtl8169_get_msglevel(struct net_device *dev) |
2143 | { | |
2144 | struct rtl8169_private *tp = netdev_priv(dev); | |
2145 | ||
2146 | return tp->msg_enable; | |
2147 | } | |
2148 | ||
2149 | static void rtl8169_set_msglevel(struct net_device *dev, u32 value) | |
2150 | { | |
2151 | struct rtl8169_private *tp = netdev_priv(dev); | |
2152 | ||
2153 | tp->msg_enable = value; | |
2154 | } | |
2155 | ||
d4a3a0fc SH |
2156 | static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = { |
2157 | "tx_packets", | |
2158 | "rx_packets", | |
2159 | "tx_errors", | |
2160 | "rx_errors", | |
2161 | "rx_missed", | |
2162 | "align_errors", | |
2163 | "tx_single_collisions", | |
2164 | "tx_multi_collisions", | |
2165 | "unicast", | |
2166 | "broadcast", | |
2167 | "multicast", | |
2168 | "tx_aborted", | |
2169 | "tx_underrun", | |
2170 | }; | |
2171 | ||
b9f2c044 | 2172 | static int rtl8169_get_sset_count(struct net_device *dev, int sset) |
d4a3a0fc | 2173 | { |
b9f2c044 JG |
2174 | switch (sset) { |
2175 | case ETH_SS_STATS: | |
2176 | return ARRAY_SIZE(rtl8169_gstrings); | |
2177 | default: | |
2178 | return -EOPNOTSUPP; | |
2179 | } | |
d4a3a0fc SH |
2180 | } |
2181 | ||
ffc46952 FR |
2182 | DECLARE_RTL_COND(rtl_counters_cond) |
2183 | { | |
2184 | void __iomem *ioaddr = tp->mmio_addr; | |
2185 | ||
2186 | return RTL_R32(CounterAddrLow) & CounterDump; | |
2187 | } | |
2188 | ||
355423d0 | 2189 | static void rtl8169_update_counters(struct net_device *dev) |
d4a3a0fc SH |
2190 | { |
2191 | struct rtl8169_private *tp = netdev_priv(dev); | |
2192 | void __iomem *ioaddr = tp->mmio_addr; | |
cecb5fd7 | 2193 | struct device *d = &tp->pci_dev->dev; |
d4a3a0fc SH |
2194 | struct rtl8169_counters *counters; |
2195 | dma_addr_t paddr; | |
2196 | u32 cmd; | |
2197 | ||
355423d0 IV |
2198 | /* |
2199 | * Some chips are unable to dump tally counters when the receiver | |
2200 | * is disabled. | |
2201 | */ | |
2202 | if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0) | |
2203 | return; | |
d4a3a0fc | 2204 | |
48addcc9 | 2205 | counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL); |
d4a3a0fc SH |
2206 | if (!counters) |
2207 | return; | |
2208 | ||
2209 | RTL_W32(CounterAddrHigh, (u64)paddr >> 32); | |
284901a9 | 2210 | cmd = (u64)paddr & DMA_BIT_MASK(32); |
d4a3a0fc SH |
2211 | RTL_W32(CounterAddrLow, cmd); |
2212 | RTL_W32(CounterAddrLow, cmd | CounterDump); | |
2213 | ||
ffc46952 FR |
2214 | if (rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000)) |
2215 | memcpy(&tp->counters, counters, sizeof(*counters)); | |
d4a3a0fc SH |
2216 | |
2217 | RTL_W32(CounterAddrLow, 0); | |
2218 | RTL_W32(CounterAddrHigh, 0); | |
2219 | ||
48addcc9 | 2220 | dma_free_coherent(d, sizeof(*counters), counters, paddr); |
d4a3a0fc SH |
2221 | } |
2222 | ||
355423d0 IV |
2223 | static void rtl8169_get_ethtool_stats(struct net_device *dev, |
2224 | struct ethtool_stats *stats, u64 *data) | |
2225 | { | |
2226 | struct rtl8169_private *tp = netdev_priv(dev); | |
2227 | ||
2228 | ASSERT_RTNL(); | |
2229 | ||
2230 | rtl8169_update_counters(dev); | |
2231 | ||
2232 | data[0] = le64_to_cpu(tp->counters.tx_packets); | |
2233 | data[1] = le64_to_cpu(tp->counters.rx_packets); | |
2234 | data[2] = le64_to_cpu(tp->counters.tx_errors); | |
2235 | data[3] = le32_to_cpu(tp->counters.rx_errors); | |
2236 | data[4] = le16_to_cpu(tp->counters.rx_missed); | |
2237 | data[5] = le16_to_cpu(tp->counters.align_errors); | |
2238 | data[6] = le32_to_cpu(tp->counters.tx_one_collision); | |
2239 | data[7] = le32_to_cpu(tp->counters.tx_multi_collision); | |
2240 | data[8] = le64_to_cpu(tp->counters.rx_unicast); | |
2241 | data[9] = le64_to_cpu(tp->counters.rx_broadcast); | |
2242 | data[10] = le32_to_cpu(tp->counters.rx_multicast); | |
2243 | data[11] = le16_to_cpu(tp->counters.tx_aborted); | |
2244 | data[12] = le16_to_cpu(tp->counters.tx_underun); | |
2245 | } | |
2246 | ||
d4a3a0fc SH |
2247 | static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data) |
2248 | { | |
2249 | switch(stringset) { | |
2250 | case ETH_SS_STATS: | |
2251 | memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings)); | |
2252 | break; | |
2253 | } | |
2254 | } | |
2255 | ||
7282d491 | 2256 | static const struct ethtool_ops rtl8169_ethtool_ops = { |
1da177e4 LT |
2257 | .get_drvinfo = rtl8169_get_drvinfo, |
2258 | .get_regs_len = rtl8169_get_regs_len, | |
2259 | .get_link = ethtool_op_get_link, | |
2260 | .get_settings = rtl8169_get_settings, | |
2261 | .set_settings = rtl8169_set_settings, | |
b57b7e5a SH |
2262 | .get_msglevel = rtl8169_get_msglevel, |
2263 | .set_msglevel = rtl8169_set_msglevel, | |
1da177e4 | 2264 | .get_regs = rtl8169_get_regs, |
61a4dcc2 FR |
2265 | .get_wol = rtl8169_get_wol, |
2266 | .set_wol = rtl8169_set_wol, | |
d4a3a0fc | 2267 | .get_strings = rtl8169_get_strings, |
b9f2c044 | 2268 | .get_sset_count = rtl8169_get_sset_count, |
d4a3a0fc | 2269 | .get_ethtool_stats = rtl8169_get_ethtool_stats, |
e1593bb1 | 2270 | .get_ts_info = ethtool_op_get_ts_info, |
1da177e4 LT |
2271 | }; |
2272 | ||
07d3f51f | 2273 | static void rtl8169_get_mac_version(struct rtl8169_private *tp, |
5d320a20 | 2274 | struct net_device *dev, u8 default_version) |
1da177e4 | 2275 | { |
5d320a20 | 2276 | void __iomem *ioaddr = tp->mmio_addr; |
0e485150 FR |
2277 | /* |
2278 | * The driver currently handles the 8168Bf and the 8168Be identically | |
2279 | * but they can be identified more specifically through the test below | |
2280 | * if needed: | |
2281 | * | |
2282 | * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be | |
0127215c FR |
2283 | * |
2284 | * Same thing for the 8101Eb and the 8101Ec: | |
2285 | * | |
2286 | * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec | |
0e485150 | 2287 | */ |
3744100e | 2288 | static const struct rtl_mac_info { |
1da177e4 | 2289 | u32 mask; |
e3cf0cc0 | 2290 | u32 val; |
1da177e4 LT |
2291 | int mac_version; |
2292 | } mac_info[] = { | |
935e2218 CHL |
2293 | /* 8168EP family. */ |
2294 | { 0x7cf00000, 0x50200000, RTL_GIGA_MAC_VER_51 }, | |
2295 | { 0x7cf00000, 0x50100000, RTL_GIGA_MAC_VER_50 }, | |
2296 | { 0x7cf00000, 0x50000000, RTL_GIGA_MAC_VER_49 }, | |
2297 | ||
6e1d0b89 CHL |
2298 | /* 8168H family. */ |
2299 | { 0x7cf00000, 0x54100000, RTL_GIGA_MAC_VER_46 }, | |
2300 | { 0x7cf00000, 0x54000000, RTL_GIGA_MAC_VER_45 }, | |
2301 | ||
c558386b | 2302 | /* 8168G family. */ |
45dd95c4 | 2303 | { 0x7cf00000, 0x5c800000, RTL_GIGA_MAC_VER_44 }, |
57538c4a | 2304 | { 0x7cf00000, 0x50900000, RTL_GIGA_MAC_VER_42 }, |
c558386b HW |
2305 | { 0x7cf00000, 0x4c100000, RTL_GIGA_MAC_VER_41 }, |
2306 | { 0x7cf00000, 0x4c000000, RTL_GIGA_MAC_VER_40 }, | |
2307 | ||
c2218925 | 2308 | /* 8168F family. */ |
b3d7b2f2 | 2309 | { 0x7c800000, 0x48800000, RTL_GIGA_MAC_VER_38 }, |
c2218925 HW |
2310 | { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36 }, |
2311 | { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35 }, | |
2312 | ||
01dc7fec | 2313 | /* 8168E family. */ |
70090424 | 2314 | { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 }, |
01dc7fec | 2315 | { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 }, |
2316 | { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 }, | |
2317 | { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 }, | |
2318 | ||
5b538df9 | 2319 | /* 8168D family. */ |
daf9df6d | 2320 | { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 }, |
2321 | { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 }, | |
daf9df6d | 2322 | { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 }, |
5b538df9 | 2323 | |
e6de30d6 | 2324 | /* 8168DP family. */ |
2325 | { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 }, | |
2326 | { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 }, | |
4804b3b3 | 2327 | { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 }, |
e6de30d6 | 2328 | |
ef808d50 | 2329 | /* 8168C family. */ |
17c99297 | 2330 | { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 }, |
ef3386f0 | 2331 | { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 }, |
ef808d50 | 2332 | { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 }, |
7f3e3d3a | 2333 | { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 }, |
e3cf0cc0 FR |
2334 | { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 }, |
2335 | { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 }, | |
197ff761 | 2336 | { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 }, |
6fb07058 | 2337 | { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 }, |
ef808d50 | 2338 | { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 }, |
e3cf0cc0 FR |
2339 | |
2340 | /* 8168B family. */ | |
2341 | { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 }, | |
2342 | { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 }, | |
2343 | { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 }, | |
2344 | { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 }, | |
2345 | ||
2346 | /* 8101 family. */ | |
5598bfe5 HW |
2347 | { 0x7cf00000, 0x44900000, RTL_GIGA_MAC_VER_39 }, |
2348 | { 0x7c800000, 0x44800000, RTL_GIGA_MAC_VER_39 }, | |
7e18dca1 | 2349 | { 0x7c800000, 0x44000000, RTL_GIGA_MAC_VER_37 }, |
36a0e6c2 | 2350 | { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 }, |
5a5e4443 HW |
2351 | { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 }, |
2352 | { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 }, | |
2353 | { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 }, | |
2857ffb7 FR |
2354 | { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 }, |
2355 | { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 }, | |
2356 | { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 }, | |
2357 | { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 }, | |
2358 | { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 }, | |
2359 | { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 }, | |
e3cf0cc0 | 2360 | { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 }, |
2857ffb7 | 2361 | { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 }, |
e3cf0cc0 | 2362 | { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 }, |
2857ffb7 FR |
2363 | { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 }, |
2364 | { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 }, | |
e3cf0cc0 FR |
2365 | { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 }, |
2366 | /* FIXME: where did these entries come from ? -- FR */ | |
2367 | { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 }, | |
2368 | { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 }, | |
2369 | ||
2370 | /* 8110 family. */ | |
2371 | { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 }, | |
2372 | { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 }, | |
2373 | { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 }, | |
2374 | { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 }, | |
2375 | { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 }, | |
2376 | { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 }, | |
2377 | ||
f21b75e9 JD |
2378 | /* Catch-all */ |
2379 | { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE } | |
3744100e FR |
2380 | }; |
2381 | const struct rtl_mac_info *p = mac_info; | |
1da177e4 LT |
2382 | u32 reg; |
2383 | ||
e3cf0cc0 FR |
2384 | reg = RTL_R32(TxConfig); |
2385 | while ((reg & p->mask) != p->val) | |
1da177e4 LT |
2386 | p++; |
2387 | tp->mac_version = p->mac_version; | |
5d320a20 FR |
2388 | |
2389 | if (tp->mac_version == RTL_GIGA_MAC_NONE) { | |
2390 | netif_notice(tp, probe, dev, | |
2391 | "unknown MAC, using family default\n"); | |
2392 | tp->mac_version = default_version; | |
58152cd4 | 2393 | } else if (tp->mac_version == RTL_GIGA_MAC_VER_42) { |
2394 | tp->mac_version = tp->mii.supports_gmii ? | |
2395 | RTL_GIGA_MAC_VER_42 : | |
2396 | RTL_GIGA_MAC_VER_43; | |
6e1d0b89 CHL |
2397 | } else if (tp->mac_version == RTL_GIGA_MAC_VER_45) { |
2398 | tp->mac_version = tp->mii.supports_gmii ? | |
2399 | RTL_GIGA_MAC_VER_45 : | |
2400 | RTL_GIGA_MAC_VER_47; | |
2401 | } else if (tp->mac_version == RTL_GIGA_MAC_VER_46) { | |
2402 | tp->mac_version = tp->mii.supports_gmii ? | |
2403 | RTL_GIGA_MAC_VER_46 : | |
2404 | RTL_GIGA_MAC_VER_48; | |
5d320a20 | 2405 | } |
1da177e4 LT |
2406 | } |
2407 | ||
2408 | static void rtl8169_print_mac_version(struct rtl8169_private *tp) | |
2409 | { | |
bcf0bf90 | 2410 | dprintk("mac_version = 0x%02x\n", tp->mac_version); |
1da177e4 LT |
2411 | } |
2412 | ||
867763c1 FR |
2413 | struct phy_reg { |
2414 | u16 reg; | |
2415 | u16 val; | |
2416 | }; | |
2417 | ||
4da19633 | 2418 | static void rtl_writephy_batch(struct rtl8169_private *tp, |
2419 | const struct phy_reg *regs, int len) | |
867763c1 FR |
2420 | { |
2421 | while (len-- > 0) { | |
4da19633 | 2422 | rtl_writephy(tp, regs->reg, regs->val); |
867763c1 FR |
2423 | regs++; |
2424 | } | |
2425 | } | |
2426 | ||
bca03d5f | 2427 | #define PHY_READ 0x00000000 |
2428 | #define PHY_DATA_OR 0x10000000 | |
2429 | #define PHY_DATA_AND 0x20000000 | |
2430 | #define PHY_BJMPN 0x30000000 | |
eee3786f | 2431 | #define PHY_MDIO_CHG 0x40000000 |
bca03d5f | 2432 | #define PHY_CLEAR_READCOUNT 0x70000000 |
2433 | #define PHY_WRITE 0x80000000 | |
2434 | #define PHY_READCOUNT_EQ_SKIP 0x90000000 | |
2435 | #define PHY_COMP_EQ_SKIPN 0xa0000000 | |
2436 | #define PHY_COMP_NEQ_SKIPN 0xb0000000 | |
2437 | #define PHY_WRITE_PREVIOUS 0xc0000000 | |
2438 | #define PHY_SKIPN 0xd0000000 | |
2439 | #define PHY_DELAY_MS 0xe0000000 | |
bca03d5f | 2440 | |
960aee6c HW |
2441 | struct fw_info { |
2442 | u32 magic; | |
2443 | char version[RTL_VER_SIZE]; | |
2444 | __le32 fw_start; | |
2445 | __le32 fw_len; | |
2446 | u8 chksum; | |
2447 | } __packed; | |
2448 | ||
1c361efb FR |
2449 | #define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code)) |
2450 | ||
2451 | static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw) | |
bca03d5f | 2452 | { |
b6ffd97f | 2453 | const struct firmware *fw = rtl_fw->fw; |
960aee6c | 2454 | struct fw_info *fw_info = (struct fw_info *)fw->data; |
1c361efb FR |
2455 | struct rtl_fw_phy_action *pa = &rtl_fw->phy_action; |
2456 | char *version = rtl_fw->version; | |
2457 | bool rc = false; | |
2458 | ||
2459 | if (fw->size < FW_OPCODE_SIZE) | |
2460 | goto out; | |
960aee6c HW |
2461 | |
2462 | if (!fw_info->magic) { | |
2463 | size_t i, size, start; | |
2464 | u8 checksum = 0; | |
2465 | ||
2466 | if (fw->size < sizeof(*fw_info)) | |
2467 | goto out; | |
2468 | ||
2469 | for (i = 0; i < fw->size; i++) | |
2470 | checksum += fw->data[i]; | |
2471 | if (checksum != 0) | |
2472 | goto out; | |
2473 | ||
2474 | start = le32_to_cpu(fw_info->fw_start); | |
2475 | if (start > fw->size) | |
2476 | goto out; | |
2477 | ||
2478 | size = le32_to_cpu(fw_info->fw_len); | |
2479 | if (size > (fw->size - start) / FW_OPCODE_SIZE) | |
2480 | goto out; | |
2481 | ||
2482 | memcpy(version, fw_info->version, RTL_VER_SIZE); | |
2483 | ||
2484 | pa->code = (__le32 *)(fw->data + start); | |
2485 | pa->size = size; | |
2486 | } else { | |
1c361efb FR |
2487 | if (fw->size % FW_OPCODE_SIZE) |
2488 | goto out; | |
2489 | ||
2490 | strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE); | |
2491 | ||
2492 | pa->code = (__le32 *)fw->data; | |
2493 | pa->size = fw->size / FW_OPCODE_SIZE; | |
2494 | } | |
2495 | version[RTL_VER_SIZE - 1] = 0; | |
2496 | ||
2497 | rc = true; | |
2498 | out: | |
2499 | return rc; | |
2500 | } | |
2501 | ||
fd112f2e FR |
2502 | static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev, |
2503 | struct rtl_fw_phy_action *pa) | |
1c361efb | 2504 | { |
fd112f2e | 2505 | bool rc = false; |
1c361efb | 2506 | size_t index; |
bca03d5f | 2507 | |
1c361efb FR |
2508 | for (index = 0; index < pa->size; index++) { |
2509 | u32 action = le32_to_cpu(pa->code[index]); | |
42b82dc1 | 2510 | u32 regno = (action & 0x0fff0000) >> 16; |
bca03d5f | 2511 | |
42b82dc1 | 2512 | switch(action & 0xf0000000) { |
2513 | case PHY_READ: | |
2514 | case PHY_DATA_OR: | |
2515 | case PHY_DATA_AND: | |
eee3786f | 2516 | case PHY_MDIO_CHG: |
42b82dc1 | 2517 | case PHY_CLEAR_READCOUNT: |
2518 | case PHY_WRITE: | |
2519 | case PHY_WRITE_PREVIOUS: | |
2520 | case PHY_DELAY_MS: | |
2521 | break; | |
2522 | ||
2523 | case PHY_BJMPN: | |
2524 | if (regno > index) { | |
fd112f2e | 2525 | netif_err(tp, ifup, tp->dev, |
cecb5fd7 | 2526 | "Out of range of firmware\n"); |
fd112f2e | 2527 | goto out; |
42b82dc1 | 2528 | } |
2529 | break; | |
2530 | case PHY_READCOUNT_EQ_SKIP: | |
1c361efb | 2531 | if (index + 2 >= pa->size) { |
fd112f2e | 2532 | netif_err(tp, ifup, tp->dev, |
cecb5fd7 | 2533 | "Out of range of firmware\n"); |
fd112f2e | 2534 | goto out; |
42b82dc1 | 2535 | } |
2536 | break; | |
2537 | case PHY_COMP_EQ_SKIPN: | |
2538 | case PHY_COMP_NEQ_SKIPN: | |
2539 | case PHY_SKIPN: | |
1c361efb | 2540 | if (index + 1 + regno >= pa->size) { |
fd112f2e | 2541 | netif_err(tp, ifup, tp->dev, |
cecb5fd7 | 2542 | "Out of range of firmware\n"); |
fd112f2e | 2543 | goto out; |
42b82dc1 | 2544 | } |
bca03d5f | 2545 | break; |
2546 | ||
42b82dc1 | 2547 | default: |
fd112f2e | 2548 | netif_err(tp, ifup, tp->dev, |
42b82dc1 | 2549 | "Invalid action 0x%08x\n", action); |
fd112f2e | 2550 | goto out; |
bca03d5f | 2551 | } |
2552 | } | |
fd112f2e FR |
2553 | rc = true; |
2554 | out: | |
2555 | return rc; | |
2556 | } | |
bca03d5f | 2557 | |
fd112f2e FR |
2558 | static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw) |
2559 | { | |
2560 | struct net_device *dev = tp->dev; | |
2561 | int rc = -EINVAL; | |
2562 | ||
2563 | if (!rtl_fw_format_ok(tp, rtl_fw)) { | |
2564 | netif_err(tp, ifup, dev, "invalid firwmare\n"); | |
2565 | goto out; | |
2566 | } | |
2567 | ||
2568 | if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action)) | |
2569 | rc = 0; | |
2570 | out: | |
2571 | return rc; | |
2572 | } | |
2573 | ||
2574 | static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw) | |
2575 | { | |
2576 | struct rtl_fw_phy_action *pa = &rtl_fw->phy_action; | |
eee3786f | 2577 | struct mdio_ops org, *ops = &tp->mdio_ops; |
fd112f2e FR |
2578 | u32 predata, count; |
2579 | size_t index; | |
2580 | ||
2581 | predata = count = 0; | |
eee3786f | 2582 | org.write = ops->write; |
2583 | org.read = ops->read; | |
42b82dc1 | 2584 | |
1c361efb FR |
2585 | for (index = 0; index < pa->size; ) { |
2586 | u32 action = le32_to_cpu(pa->code[index]); | |
bca03d5f | 2587 | u32 data = action & 0x0000ffff; |
42b82dc1 | 2588 | u32 regno = (action & 0x0fff0000) >> 16; |
2589 | ||
2590 | if (!action) | |
2591 | break; | |
bca03d5f | 2592 | |
2593 | switch(action & 0xf0000000) { | |
42b82dc1 | 2594 | case PHY_READ: |
2595 | predata = rtl_readphy(tp, regno); | |
2596 | count++; | |
2597 | index++; | |
2598 | break; | |
2599 | case PHY_DATA_OR: | |
2600 | predata |= data; | |
2601 | index++; | |
2602 | break; | |
2603 | case PHY_DATA_AND: | |
2604 | predata &= data; | |
2605 | index++; | |
2606 | break; | |
2607 | case PHY_BJMPN: | |
2608 | index -= regno; | |
2609 | break; | |
eee3786f | 2610 | case PHY_MDIO_CHG: |
2611 | if (data == 0) { | |
2612 | ops->write = org.write; | |
2613 | ops->read = org.read; | |
2614 | } else if (data == 1) { | |
2615 | ops->write = mac_mcu_write; | |
2616 | ops->read = mac_mcu_read; | |
2617 | } | |
2618 | ||
42b82dc1 | 2619 | index++; |
2620 | break; | |
2621 | case PHY_CLEAR_READCOUNT: | |
2622 | count = 0; | |
2623 | index++; | |
2624 | break; | |
bca03d5f | 2625 | case PHY_WRITE: |
42b82dc1 | 2626 | rtl_writephy(tp, regno, data); |
2627 | index++; | |
2628 | break; | |
2629 | case PHY_READCOUNT_EQ_SKIP: | |
cecb5fd7 | 2630 | index += (count == data) ? 2 : 1; |
bca03d5f | 2631 | break; |
42b82dc1 | 2632 | case PHY_COMP_EQ_SKIPN: |
2633 | if (predata == data) | |
2634 | index += regno; | |
2635 | index++; | |
2636 | break; | |
2637 | case PHY_COMP_NEQ_SKIPN: | |
2638 | if (predata != data) | |
2639 | index += regno; | |
2640 | index++; | |
2641 | break; | |
2642 | case PHY_WRITE_PREVIOUS: | |
2643 | rtl_writephy(tp, regno, predata); | |
2644 | index++; | |
2645 | break; | |
2646 | case PHY_SKIPN: | |
2647 | index += regno + 1; | |
2648 | break; | |
2649 | case PHY_DELAY_MS: | |
2650 | mdelay(data); | |
2651 | index++; | |
2652 | break; | |
2653 | ||
bca03d5f | 2654 | default: |
2655 | BUG(); | |
2656 | } | |
2657 | } | |
eee3786f | 2658 | |
2659 | ops->write = org.write; | |
2660 | ops->read = org.read; | |
bca03d5f | 2661 | } |
2662 | ||
f1e02ed1 | 2663 | static void rtl_release_firmware(struct rtl8169_private *tp) |
2664 | { | |
b6ffd97f FR |
2665 | if (!IS_ERR_OR_NULL(tp->rtl_fw)) { |
2666 | release_firmware(tp->rtl_fw->fw); | |
2667 | kfree(tp->rtl_fw); | |
2668 | } | |
2669 | tp->rtl_fw = RTL_FIRMWARE_UNKNOWN; | |
f1e02ed1 | 2670 | } |
2671 | ||
953a12cc | 2672 | static void rtl_apply_firmware(struct rtl8169_private *tp) |
f1e02ed1 | 2673 | { |
b6ffd97f | 2674 | struct rtl_fw *rtl_fw = tp->rtl_fw; |
f1e02ed1 | 2675 | |
2676 | /* TODO: release firmware once rtl_phy_write_fw signals failures. */ | |
eef63cc1 | 2677 | if (!IS_ERR_OR_NULL(rtl_fw)) |
b6ffd97f | 2678 | rtl_phy_write_fw(tp, rtl_fw); |
953a12cc FR |
2679 | } |
2680 | ||
2681 | static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val) | |
2682 | { | |
2683 | if (rtl_readphy(tp, reg) != val) | |
2684 | netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n"); | |
2685 | else | |
2686 | rtl_apply_firmware(tp); | |
f1e02ed1 | 2687 | } |
2688 | ||
4da19633 | 2689 | static void rtl8169s_hw_phy_config(struct rtl8169_private *tp) |
1da177e4 | 2690 | { |
350f7596 | 2691 | static const struct phy_reg phy_reg_init[] = { |
0b9b571d | 2692 | { 0x1f, 0x0001 }, |
2693 | { 0x06, 0x006e }, | |
2694 | { 0x08, 0x0708 }, | |
2695 | { 0x15, 0x4000 }, | |
2696 | { 0x18, 0x65c7 }, | |
1da177e4 | 2697 | |
0b9b571d | 2698 | { 0x1f, 0x0001 }, |
2699 | { 0x03, 0x00a1 }, | |
2700 | { 0x02, 0x0008 }, | |
2701 | { 0x01, 0x0120 }, | |
2702 | { 0x00, 0x1000 }, | |
2703 | { 0x04, 0x0800 }, | |
2704 | { 0x04, 0x0000 }, | |
1da177e4 | 2705 | |
0b9b571d | 2706 | { 0x03, 0xff41 }, |
2707 | { 0x02, 0xdf60 }, | |
2708 | { 0x01, 0x0140 }, | |
2709 | { 0x00, 0x0077 }, | |
2710 | { 0x04, 0x7800 }, | |
2711 | { 0x04, 0x7000 }, | |
2712 | ||
2713 | { 0x03, 0x802f }, | |
2714 | { 0x02, 0x4f02 }, | |
2715 | { 0x01, 0x0409 }, | |
2716 | { 0x00, 0xf0f9 }, | |
2717 | { 0x04, 0x9800 }, | |
2718 | { 0x04, 0x9000 }, | |
2719 | ||
2720 | { 0x03, 0xdf01 }, | |
2721 | { 0x02, 0xdf20 }, | |
2722 | { 0x01, 0xff95 }, | |
2723 | { 0x00, 0xba00 }, | |
2724 | { 0x04, 0xa800 }, | |
2725 | { 0x04, 0xa000 }, | |
2726 | ||
2727 | { 0x03, 0xff41 }, | |
2728 | { 0x02, 0xdf20 }, | |
2729 | { 0x01, 0x0140 }, | |
2730 | { 0x00, 0x00bb }, | |
2731 | { 0x04, 0xb800 }, | |
2732 | { 0x04, 0xb000 }, | |
2733 | ||
2734 | { 0x03, 0xdf41 }, | |
2735 | { 0x02, 0xdc60 }, | |
2736 | { 0x01, 0x6340 }, | |
2737 | { 0x00, 0x007d }, | |
2738 | { 0x04, 0xd800 }, | |
2739 | { 0x04, 0xd000 }, | |
2740 | ||
2741 | { 0x03, 0xdf01 }, | |
2742 | { 0x02, 0xdf20 }, | |
2743 | { 0x01, 0x100a }, | |
2744 | { 0x00, 0xa0ff }, | |
2745 | { 0x04, 0xf800 }, | |
2746 | { 0x04, 0xf000 }, | |
2747 | ||
2748 | { 0x1f, 0x0000 }, | |
2749 | { 0x0b, 0x0000 }, | |
2750 | { 0x00, 0x9200 } | |
2751 | }; | |
1da177e4 | 2752 | |
4da19633 | 2753 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
1da177e4 LT |
2754 | } |
2755 | ||
4da19633 | 2756 | static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp) |
5615d9f1 | 2757 | { |
350f7596 | 2758 | static const struct phy_reg phy_reg_init[] = { |
a441d7b6 FR |
2759 | { 0x1f, 0x0002 }, |
2760 | { 0x01, 0x90d0 }, | |
2761 | { 0x1f, 0x0000 } | |
2762 | }; | |
2763 | ||
4da19633 | 2764 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
5615d9f1 FR |
2765 | } |
2766 | ||
4da19633 | 2767 | static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp) |
2e955856 | 2768 | { |
2769 | struct pci_dev *pdev = tp->pci_dev; | |
2e955856 | 2770 | |
ccbae55e SS |
2771 | if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) || |
2772 | (pdev->subsystem_device != 0xe000)) | |
2e955856 | 2773 | return; |
2774 | ||
4da19633 | 2775 | rtl_writephy(tp, 0x1f, 0x0001); |
2776 | rtl_writephy(tp, 0x10, 0xf01b); | |
2777 | rtl_writephy(tp, 0x1f, 0x0000); | |
2e955856 | 2778 | } |
2779 | ||
4da19633 | 2780 | static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp) |
2e955856 | 2781 | { |
350f7596 | 2782 | static const struct phy_reg phy_reg_init[] = { |
2e955856 | 2783 | { 0x1f, 0x0001 }, |
2784 | { 0x04, 0x0000 }, | |
2785 | { 0x03, 0x00a1 }, | |
2786 | { 0x02, 0x0008 }, | |
2787 | { 0x01, 0x0120 }, | |
2788 | { 0x00, 0x1000 }, | |
2789 | { 0x04, 0x0800 }, | |
2790 | { 0x04, 0x9000 }, | |
2791 | { 0x03, 0x802f }, | |
2792 | { 0x02, 0x4f02 }, | |
2793 | { 0x01, 0x0409 }, | |
2794 | { 0x00, 0xf099 }, | |
2795 | { 0x04, 0x9800 }, | |
2796 | { 0x04, 0xa000 }, | |
2797 | { 0x03, 0xdf01 }, | |
2798 | { 0x02, 0xdf20 }, | |
2799 | { 0x01, 0xff95 }, | |
2800 | { 0x00, 0xba00 }, | |
2801 | { 0x04, 0xa800 }, | |
2802 | { 0x04, 0xf000 }, | |
2803 | { 0x03, 0xdf01 }, | |
2804 | { 0x02, 0xdf20 }, | |
2805 | { 0x01, 0x101a }, | |
2806 | { 0x00, 0xa0ff }, | |
2807 | { 0x04, 0xf800 }, | |
2808 | { 0x04, 0x0000 }, | |
2809 | { 0x1f, 0x0000 }, | |
2810 | ||
2811 | { 0x1f, 0x0001 }, | |
2812 | { 0x10, 0xf41b }, | |
2813 | { 0x14, 0xfb54 }, | |
2814 | { 0x18, 0xf5c7 }, | |
2815 | { 0x1f, 0x0000 }, | |
2816 | ||
2817 | { 0x1f, 0x0001 }, | |
2818 | { 0x17, 0x0cc0 }, | |
2819 | { 0x1f, 0x0000 } | |
2820 | }; | |
2821 | ||
4da19633 | 2822 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
2e955856 | 2823 | |
4da19633 | 2824 | rtl8169scd_hw_phy_config_quirk(tp); |
2e955856 | 2825 | } |
2826 | ||
4da19633 | 2827 | static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp) |
8c7006aa | 2828 | { |
350f7596 | 2829 | static const struct phy_reg phy_reg_init[] = { |
8c7006aa | 2830 | { 0x1f, 0x0001 }, |
2831 | { 0x04, 0x0000 }, | |
2832 | { 0x03, 0x00a1 }, | |
2833 | { 0x02, 0x0008 }, | |
2834 | { 0x01, 0x0120 }, | |
2835 | { 0x00, 0x1000 }, | |
2836 | { 0x04, 0x0800 }, | |
2837 | { 0x04, 0x9000 }, | |
2838 | { 0x03, 0x802f }, | |
2839 | { 0x02, 0x4f02 }, | |
2840 | { 0x01, 0x0409 }, | |
2841 | { 0x00, 0xf099 }, | |
2842 | { 0x04, 0x9800 }, | |
2843 | { 0x04, 0xa000 }, | |
2844 | { 0x03, 0xdf01 }, | |
2845 | { 0x02, 0xdf20 }, | |
2846 | { 0x01, 0xff95 }, | |
2847 | { 0x00, 0xba00 }, | |
2848 | { 0x04, 0xa800 }, | |
2849 | { 0x04, 0xf000 }, | |
2850 | { 0x03, 0xdf01 }, | |
2851 | { 0x02, 0xdf20 }, | |
2852 | { 0x01, 0x101a }, | |
2853 | { 0x00, 0xa0ff }, | |
2854 | { 0x04, 0xf800 }, | |
2855 | { 0x04, 0x0000 }, | |
2856 | { 0x1f, 0x0000 }, | |
2857 | ||
2858 | { 0x1f, 0x0001 }, | |
2859 | { 0x0b, 0x8480 }, | |
2860 | { 0x1f, 0x0000 }, | |
2861 | ||
2862 | { 0x1f, 0x0001 }, | |
2863 | { 0x18, 0x67c7 }, | |
2864 | { 0x04, 0x2000 }, | |
2865 | { 0x03, 0x002f }, | |
2866 | { 0x02, 0x4360 }, | |
2867 | { 0x01, 0x0109 }, | |
2868 | { 0x00, 0x3022 }, | |
2869 | { 0x04, 0x2800 }, | |
2870 | { 0x1f, 0x0000 }, | |
2871 | ||
2872 | { 0x1f, 0x0001 }, | |
2873 | { 0x17, 0x0cc0 }, | |
2874 | { 0x1f, 0x0000 } | |
2875 | }; | |
2876 | ||
4da19633 | 2877 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
8c7006aa | 2878 | } |
2879 | ||
4da19633 | 2880 | static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp) |
236b8082 | 2881 | { |
350f7596 | 2882 | static const struct phy_reg phy_reg_init[] = { |
236b8082 FR |
2883 | { 0x10, 0xf41b }, |
2884 | { 0x1f, 0x0000 } | |
2885 | }; | |
2886 | ||
4da19633 | 2887 | rtl_writephy(tp, 0x1f, 0x0001); |
2888 | rtl_patchphy(tp, 0x16, 1 << 0); | |
236b8082 | 2889 | |
4da19633 | 2890 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
236b8082 FR |
2891 | } |
2892 | ||
4da19633 | 2893 | static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp) |
236b8082 | 2894 | { |
350f7596 | 2895 | static const struct phy_reg phy_reg_init[] = { |
236b8082 FR |
2896 | { 0x1f, 0x0001 }, |
2897 | { 0x10, 0xf41b }, | |
2898 | { 0x1f, 0x0000 } | |
2899 | }; | |
2900 | ||
4da19633 | 2901 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
236b8082 FR |
2902 | } |
2903 | ||
4da19633 | 2904 | static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp) |
867763c1 | 2905 | { |
350f7596 | 2906 | static const struct phy_reg phy_reg_init[] = { |
867763c1 FR |
2907 | { 0x1f, 0x0000 }, |
2908 | { 0x1d, 0x0f00 }, | |
2909 | { 0x1f, 0x0002 }, | |
2910 | { 0x0c, 0x1ec8 }, | |
2911 | { 0x1f, 0x0000 } | |
2912 | }; | |
2913 | ||
4da19633 | 2914 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
867763c1 FR |
2915 | } |
2916 | ||
4da19633 | 2917 | static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp) |
ef3386f0 | 2918 | { |
350f7596 | 2919 | static const struct phy_reg phy_reg_init[] = { |
ef3386f0 FR |
2920 | { 0x1f, 0x0001 }, |
2921 | { 0x1d, 0x3d98 }, | |
2922 | { 0x1f, 0x0000 } | |
2923 | }; | |
2924 | ||
4da19633 | 2925 | rtl_writephy(tp, 0x1f, 0x0000); |
2926 | rtl_patchphy(tp, 0x14, 1 << 5); | |
2927 | rtl_patchphy(tp, 0x0d, 1 << 5); | |
ef3386f0 | 2928 | |
4da19633 | 2929 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
ef3386f0 FR |
2930 | } |
2931 | ||
4da19633 | 2932 | static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp) |
867763c1 | 2933 | { |
350f7596 | 2934 | static const struct phy_reg phy_reg_init[] = { |
a3f80671 FR |
2935 | { 0x1f, 0x0001 }, |
2936 | { 0x12, 0x2300 }, | |
867763c1 FR |
2937 | { 0x1f, 0x0002 }, |
2938 | { 0x00, 0x88d4 }, | |
2939 | { 0x01, 0x82b1 }, | |
2940 | { 0x03, 0x7002 }, | |
2941 | { 0x08, 0x9e30 }, | |
2942 | { 0x09, 0x01f0 }, | |
2943 | { 0x0a, 0x5500 }, | |
2944 | { 0x0c, 0x00c8 }, | |
2945 | { 0x1f, 0x0003 }, | |
2946 | { 0x12, 0xc096 }, | |
2947 | { 0x16, 0x000a }, | |
f50d4275 FR |
2948 | { 0x1f, 0x0000 }, |
2949 | { 0x1f, 0x0000 }, | |
2950 | { 0x09, 0x2000 }, | |
2951 | { 0x09, 0x0000 } | |
867763c1 FR |
2952 | }; |
2953 | ||
4da19633 | 2954 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
f50d4275 | 2955 | |
4da19633 | 2956 | rtl_patchphy(tp, 0x14, 1 << 5); |
2957 | rtl_patchphy(tp, 0x0d, 1 << 5); | |
2958 | rtl_writephy(tp, 0x1f, 0x0000); | |
867763c1 FR |
2959 | } |
2960 | ||
4da19633 | 2961 | static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp) |
7da97ec9 | 2962 | { |
350f7596 | 2963 | static const struct phy_reg phy_reg_init[] = { |
f50d4275 | 2964 | { 0x1f, 0x0001 }, |
7da97ec9 | 2965 | { 0x12, 0x2300 }, |
f50d4275 FR |
2966 | { 0x03, 0x802f }, |
2967 | { 0x02, 0x4f02 }, | |
2968 | { 0x01, 0x0409 }, | |
2969 | { 0x00, 0xf099 }, | |
2970 | { 0x04, 0x9800 }, | |
2971 | { 0x04, 0x9000 }, | |
2972 | { 0x1d, 0x3d98 }, | |
7da97ec9 FR |
2973 | { 0x1f, 0x0002 }, |
2974 | { 0x0c, 0x7eb8 }, | |
f50d4275 FR |
2975 | { 0x06, 0x0761 }, |
2976 | { 0x1f, 0x0003 }, | |
2977 | { 0x16, 0x0f0a }, | |
7da97ec9 FR |
2978 | { 0x1f, 0x0000 } |
2979 | }; | |
2980 | ||
4da19633 | 2981 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
f50d4275 | 2982 | |
4da19633 | 2983 | rtl_patchphy(tp, 0x16, 1 << 0); |
2984 | rtl_patchphy(tp, 0x14, 1 << 5); | |
2985 | rtl_patchphy(tp, 0x0d, 1 << 5); | |
2986 | rtl_writephy(tp, 0x1f, 0x0000); | |
7da97ec9 FR |
2987 | } |
2988 | ||
4da19633 | 2989 | static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp) |
197ff761 | 2990 | { |
350f7596 | 2991 | static const struct phy_reg phy_reg_init[] = { |
197ff761 FR |
2992 | { 0x1f, 0x0001 }, |
2993 | { 0x12, 0x2300 }, | |
2994 | { 0x1d, 0x3d98 }, | |
2995 | { 0x1f, 0x0002 }, | |
2996 | { 0x0c, 0x7eb8 }, | |
2997 | { 0x06, 0x5461 }, | |
2998 | { 0x1f, 0x0003 }, | |
2999 | { 0x16, 0x0f0a }, | |
3000 | { 0x1f, 0x0000 } | |
3001 | }; | |
3002 | ||
4da19633 | 3003 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
197ff761 | 3004 | |
4da19633 | 3005 | rtl_patchphy(tp, 0x16, 1 << 0); |
3006 | rtl_patchphy(tp, 0x14, 1 << 5); | |
3007 | rtl_patchphy(tp, 0x0d, 1 << 5); | |
3008 | rtl_writephy(tp, 0x1f, 0x0000); | |
197ff761 FR |
3009 | } |
3010 | ||
4da19633 | 3011 | static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp) |
6fb07058 | 3012 | { |
4da19633 | 3013 | rtl8168c_3_hw_phy_config(tp); |
6fb07058 FR |
3014 | } |
3015 | ||
bca03d5f | 3016 | static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp) |
5b538df9 | 3017 | { |
350f7596 | 3018 | static const struct phy_reg phy_reg_init_0[] = { |
bca03d5f | 3019 | /* Channel Estimation */ |
5b538df9 | 3020 | { 0x1f, 0x0001 }, |
daf9df6d | 3021 | { 0x06, 0x4064 }, |
3022 | { 0x07, 0x2863 }, | |
3023 | { 0x08, 0x059c }, | |
3024 | { 0x09, 0x26b4 }, | |
3025 | { 0x0a, 0x6a19 }, | |
3026 | { 0x0b, 0xdcc8 }, | |
3027 | { 0x10, 0xf06d }, | |
3028 | { 0x14, 0x7f68 }, | |
3029 | { 0x18, 0x7fd9 }, | |
3030 | { 0x1c, 0xf0ff }, | |
3031 | { 0x1d, 0x3d9c }, | |
5b538df9 | 3032 | { 0x1f, 0x0003 }, |
daf9df6d | 3033 | { 0x12, 0xf49f }, |
3034 | { 0x13, 0x070b }, | |
3035 | { 0x1a, 0x05ad }, | |
bca03d5f | 3036 | { 0x14, 0x94c0 }, |
3037 | ||
3038 | /* | |
3039 | * Tx Error Issue | |
cecb5fd7 | 3040 | * Enhance line driver power |
bca03d5f | 3041 | */ |
5b538df9 | 3042 | { 0x1f, 0x0002 }, |
daf9df6d | 3043 | { 0x06, 0x5561 }, |
3044 | { 0x1f, 0x0005 }, | |
3045 | { 0x05, 0x8332 }, | |
bca03d5f | 3046 | { 0x06, 0x5561 }, |
3047 | ||
3048 | /* | |
3049 | * Can not link to 1Gbps with bad cable | |
3050 | * Decrease SNR threshold form 21.07dB to 19.04dB | |
3051 | */ | |
3052 | { 0x1f, 0x0001 }, | |
3053 | { 0x17, 0x0cc0 }, | |
daf9df6d | 3054 | |
5b538df9 | 3055 | { 0x1f, 0x0000 }, |
bca03d5f | 3056 | { 0x0d, 0xf880 } |
daf9df6d | 3057 | }; |
3058 | ||
4da19633 | 3059 | rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0)); |
daf9df6d | 3060 | |
bca03d5f | 3061 | /* |
3062 | * Rx Error Issue | |
3063 | * Fine Tune Switching regulator parameter | |
3064 | */ | |
4da19633 | 3065 | rtl_writephy(tp, 0x1f, 0x0002); |
76564428 CHL |
3066 | rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef); |
3067 | rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00); | |
daf9df6d | 3068 | |
fdf6fc06 | 3069 | if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) { |
350f7596 | 3070 | static const struct phy_reg phy_reg_init[] = { |
daf9df6d | 3071 | { 0x1f, 0x0002 }, |
3072 | { 0x05, 0x669a }, | |
3073 | { 0x1f, 0x0005 }, | |
3074 | { 0x05, 0x8330 }, | |
3075 | { 0x06, 0x669a }, | |
3076 | { 0x1f, 0x0002 } | |
3077 | }; | |
3078 | int val; | |
3079 | ||
4da19633 | 3080 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
daf9df6d | 3081 | |
4da19633 | 3082 | val = rtl_readphy(tp, 0x0d); |
daf9df6d | 3083 | |
3084 | if ((val & 0x00ff) != 0x006c) { | |
350f7596 | 3085 | static const u32 set[] = { |
daf9df6d | 3086 | 0x0065, 0x0066, 0x0067, 0x0068, |
3087 | 0x0069, 0x006a, 0x006b, 0x006c | |
3088 | }; | |
3089 | int i; | |
3090 | ||
4da19633 | 3091 | rtl_writephy(tp, 0x1f, 0x0002); |
daf9df6d | 3092 | |
3093 | val &= 0xff00; | |
3094 | for (i = 0; i < ARRAY_SIZE(set); i++) | |
4da19633 | 3095 | rtl_writephy(tp, 0x0d, val | set[i]); |
daf9df6d | 3096 | } |
3097 | } else { | |
350f7596 | 3098 | static const struct phy_reg phy_reg_init[] = { |
daf9df6d | 3099 | { 0x1f, 0x0002 }, |
3100 | { 0x05, 0x6662 }, | |
3101 | { 0x1f, 0x0005 }, | |
3102 | { 0x05, 0x8330 }, | |
3103 | { 0x06, 0x6662 } | |
3104 | }; | |
3105 | ||
4da19633 | 3106 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
daf9df6d | 3107 | } |
3108 | ||
bca03d5f | 3109 | /* RSET couple improve */ |
4da19633 | 3110 | rtl_writephy(tp, 0x1f, 0x0002); |
3111 | rtl_patchphy(tp, 0x0d, 0x0300); | |
3112 | rtl_patchphy(tp, 0x0f, 0x0010); | |
daf9df6d | 3113 | |
bca03d5f | 3114 | /* Fine tune PLL performance */ |
4da19633 | 3115 | rtl_writephy(tp, 0x1f, 0x0002); |
76564428 CHL |
3116 | rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600); |
3117 | rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000); | |
daf9df6d | 3118 | |
4da19633 | 3119 | rtl_writephy(tp, 0x1f, 0x0005); |
3120 | rtl_writephy(tp, 0x05, 0x001b); | |
953a12cc FR |
3121 | |
3122 | rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00); | |
bca03d5f | 3123 | |
4da19633 | 3124 | rtl_writephy(tp, 0x1f, 0x0000); |
daf9df6d | 3125 | } |
3126 | ||
bca03d5f | 3127 | static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp) |
daf9df6d | 3128 | { |
350f7596 | 3129 | static const struct phy_reg phy_reg_init_0[] = { |
bca03d5f | 3130 | /* Channel Estimation */ |
daf9df6d | 3131 | { 0x1f, 0x0001 }, |
3132 | { 0x06, 0x4064 }, | |
3133 | { 0x07, 0x2863 }, | |
3134 | { 0x08, 0x059c }, | |
3135 | { 0x09, 0x26b4 }, | |
3136 | { 0x0a, 0x6a19 }, | |
3137 | { 0x0b, 0xdcc8 }, | |
3138 | { 0x10, 0xf06d }, | |
3139 | { 0x14, 0x7f68 }, | |
3140 | { 0x18, 0x7fd9 }, | |
3141 | { 0x1c, 0xf0ff }, | |
3142 | { 0x1d, 0x3d9c }, | |
3143 | { 0x1f, 0x0003 }, | |
3144 | { 0x12, 0xf49f }, | |
3145 | { 0x13, 0x070b }, | |
3146 | { 0x1a, 0x05ad }, | |
3147 | { 0x14, 0x94c0 }, | |
3148 | ||
bca03d5f | 3149 | /* |
3150 | * Tx Error Issue | |
cecb5fd7 | 3151 | * Enhance line driver power |
bca03d5f | 3152 | */ |
daf9df6d | 3153 | { 0x1f, 0x0002 }, |
3154 | { 0x06, 0x5561 }, | |
3155 | { 0x1f, 0x0005 }, | |
3156 | { 0x05, 0x8332 }, | |
bca03d5f | 3157 | { 0x06, 0x5561 }, |
3158 | ||
3159 | /* | |
3160 | * Can not link to 1Gbps with bad cable | |
3161 | * Decrease SNR threshold form 21.07dB to 19.04dB | |
3162 | */ | |
3163 | { 0x1f, 0x0001 }, | |
3164 | { 0x17, 0x0cc0 }, | |
daf9df6d | 3165 | |
3166 | { 0x1f, 0x0000 }, | |
bca03d5f | 3167 | { 0x0d, 0xf880 } |
5b538df9 FR |
3168 | }; |
3169 | ||
4da19633 | 3170 | rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0)); |
5b538df9 | 3171 | |
fdf6fc06 | 3172 | if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) { |
350f7596 | 3173 | static const struct phy_reg phy_reg_init[] = { |
daf9df6d | 3174 | { 0x1f, 0x0002 }, |
3175 | { 0x05, 0x669a }, | |
5b538df9 | 3176 | { 0x1f, 0x0005 }, |
daf9df6d | 3177 | { 0x05, 0x8330 }, |
3178 | { 0x06, 0x669a }, | |
3179 | ||
3180 | { 0x1f, 0x0002 } | |
3181 | }; | |
3182 | int val; | |
3183 | ||
4da19633 | 3184 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
daf9df6d | 3185 | |
4da19633 | 3186 | val = rtl_readphy(tp, 0x0d); |
daf9df6d | 3187 | if ((val & 0x00ff) != 0x006c) { |
b6bc7650 | 3188 | static const u32 set[] = { |
daf9df6d | 3189 | 0x0065, 0x0066, 0x0067, 0x0068, |
3190 | 0x0069, 0x006a, 0x006b, 0x006c | |
3191 | }; | |
3192 | int i; | |
3193 | ||
4da19633 | 3194 | rtl_writephy(tp, 0x1f, 0x0002); |
daf9df6d | 3195 | |
3196 | val &= 0xff00; | |
3197 | for (i = 0; i < ARRAY_SIZE(set); i++) | |
4da19633 | 3198 | rtl_writephy(tp, 0x0d, val | set[i]); |
daf9df6d | 3199 | } |
3200 | } else { | |
350f7596 | 3201 | static const struct phy_reg phy_reg_init[] = { |
daf9df6d | 3202 | { 0x1f, 0x0002 }, |
3203 | { 0x05, 0x2642 }, | |
5b538df9 | 3204 | { 0x1f, 0x0005 }, |
daf9df6d | 3205 | { 0x05, 0x8330 }, |
3206 | { 0x06, 0x2642 } | |
5b538df9 FR |
3207 | }; |
3208 | ||
4da19633 | 3209 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
5b538df9 FR |
3210 | } |
3211 | ||
bca03d5f | 3212 | /* Fine tune PLL performance */ |
4da19633 | 3213 | rtl_writephy(tp, 0x1f, 0x0002); |
76564428 CHL |
3214 | rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600); |
3215 | rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000); | |
daf9df6d | 3216 | |
bca03d5f | 3217 | /* Switching regulator Slew rate */ |
4da19633 | 3218 | rtl_writephy(tp, 0x1f, 0x0002); |
3219 | rtl_patchphy(tp, 0x0f, 0x0017); | |
daf9df6d | 3220 | |
4da19633 | 3221 | rtl_writephy(tp, 0x1f, 0x0005); |
3222 | rtl_writephy(tp, 0x05, 0x001b); | |
953a12cc FR |
3223 | |
3224 | rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300); | |
bca03d5f | 3225 | |
4da19633 | 3226 | rtl_writephy(tp, 0x1f, 0x0000); |
daf9df6d | 3227 | } |
3228 | ||
4da19633 | 3229 | static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp) |
daf9df6d | 3230 | { |
350f7596 | 3231 | static const struct phy_reg phy_reg_init[] = { |
daf9df6d | 3232 | { 0x1f, 0x0002 }, |
3233 | { 0x10, 0x0008 }, | |
3234 | { 0x0d, 0x006c }, | |
3235 | ||
3236 | { 0x1f, 0x0000 }, | |
3237 | { 0x0d, 0xf880 }, | |
3238 | ||
3239 | { 0x1f, 0x0001 }, | |
3240 | { 0x17, 0x0cc0 }, | |
3241 | ||
3242 | { 0x1f, 0x0001 }, | |
3243 | { 0x0b, 0xa4d8 }, | |
3244 | { 0x09, 0x281c }, | |
3245 | { 0x07, 0x2883 }, | |
3246 | { 0x0a, 0x6b35 }, | |
3247 | { 0x1d, 0x3da4 }, | |
3248 | { 0x1c, 0xeffd }, | |
3249 | { 0x14, 0x7f52 }, | |
3250 | { 0x18, 0x7fc6 }, | |
3251 | { 0x08, 0x0601 }, | |
3252 | { 0x06, 0x4063 }, | |
3253 | { 0x10, 0xf074 }, | |
3254 | { 0x1f, 0x0003 }, | |
3255 | { 0x13, 0x0789 }, | |
3256 | { 0x12, 0xf4bd }, | |
3257 | { 0x1a, 0x04fd }, | |
3258 | { 0x14, 0x84b0 }, | |
3259 | { 0x1f, 0x0000 }, | |
3260 | { 0x00, 0x9200 }, | |
3261 | ||
3262 | { 0x1f, 0x0005 }, | |
3263 | { 0x01, 0x0340 }, | |
3264 | { 0x1f, 0x0001 }, | |
3265 | { 0x04, 0x4000 }, | |
3266 | { 0x03, 0x1d21 }, | |
3267 | { 0x02, 0x0c32 }, | |
3268 | { 0x01, 0x0200 }, | |
3269 | { 0x00, 0x5554 }, | |
3270 | { 0x04, 0x4800 }, | |
3271 | { 0x04, 0x4000 }, | |
3272 | { 0x04, 0xf000 }, | |
3273 | { 0x03, 0xdf01 }, | |
3274 | { 0x02, 0xdf20 }, | |
3275 | { 0x01, 0x101a }, | |
3276 | { 0x00, 0xa0ff }, | |
3277 | { 0x04, 0xf800 }, | |
3278 | { 0x04, 0xf000 }, | |
3279 | { 0x1f, 0x0000 }, | |
3280 | ||
3281 | { 0x1f, 0x0007 }, | |
3282 | { 0x1e, 0x0023 }, | |
3283 | { 0x16, 0x0000 }, | |
3284 | { 0x1f, 0x0000 } | |
3285 | }; | |
3286 | ||
4da19633 | 3287 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
5b538df9 FR |
3288 | } |
3289 | ||
e6de30d6 | 3290 | static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp) |
3291 | { | |
3292 | static const struct phy_reg phy_reg_init[] = { | |
3293 | { 0x1f, 0x0001 }, | |
3294 | { 0x17, 0x0cc0 }, | |
3295 | ||
3296 | { 0x1f, 0x0007 }, | |
3297 | { 0x1e, 0x002d }, | |
3298 | { 0x18, 0x0040 }, | |
3299 | { 0x1f, 0x0000 } | |
3300 | }; | |
3301 | ||
3302 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); | |
3303 | rtl_patchphy(tp, 0x0d, 1 << 5); | |
3304 | } | |
3305 | ||
70090424 | 3306 | static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp) |
01dc7fec | 3307 | { |
3308 | static const struct phy_reg phy_reg_init[] = { | |
3309 | /* Enable Delay cap */ | |
3310 | { 0x1f, 0x0005 }, | |
3311 | { 0x05, 0x8b80 }, | |
3312 | { 0x06, 0xc896 }, | |
3313 | { 0x1f, 0x0000 }, | |
3314 | ||
3315 | /* Channel estimation fine tune */ | |
3316 | { 0x1f, 0x0001 }, | |
3317 | { 0x0b, 0x6c20 }, | |
3318 | { 0x07, 0x2872 }, | |
3319 | { 0x1c, 0xefff }, | |
3320 | { 0x1f, 0x0003 }, | |
3321 | { 0x14, 0x6420 }, | |
3322 | { 0x1f, 0x0000 }, | |
3323 | ||
3324 | /* Update PFM & 10M TX idle timer */ | |
3325 | { 0x1f, 0x0007 }, | |
3326 | { 0x1e, 0x002f }, | |
3327 | { 0x15, 0x1919 }, | |
3328 | { 0x1f, 0x0000 }, | |
3329 | ||
3330 | { 0x1f, 0x0007 }, | |
3331 | { 0x1e, 0x00ac }, | |
3332 | { 0x18, 0x0006 }, | |
3333 | { 0x1f, 0x0000 } | |
3334 | }; | |
3335 | ||
15ecd039 FR |
3336 | rtl_apply_firmware(tp); |
3337 | ||
01dc7fec | 3338 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
3339 | ||
3340 | /* DCO enable for 10M IDLE Power */ | |
3341 | rtl_writephy(tp, 0x1f, 0x0007); | |
3342 | rtl_writephy(tp, 0x1e, 0x0023); | |
76564428 | 3343 | rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000); |
01dc7fec | 3344 | rtl_writephy(tp, 0x1f, 0x0000); |
3345 | ||
3346 | /* For impedance matching */ | |
3347 | rtl_writephy(tp, 0x1f, 0x0002); | |
76564428 | 3348 | rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00); |
cecb5fd7 | 3349 | rtl_writephy(tp, 0x1f, 0x0000); |
01dc7fec | 3350 | |
3351 | /* PHY auto speed down */ | |
3352 | rtl_writephy(tp, 0x1f, 0x0007); | |
3353 | rtl_writephy(tp, 0x1e, 0x002d); | |
76564428 | 3354 | rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000); |
01dc7fec | 3355 | rtl_writephy(tp, 0x1f, 0x0000); |
76564428 | 3356 | rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000); |
01dc7fec | 3357 | |
3358 | rtl_writephy(tp, 0x1f, 0x0005); | |
3359 | rtl_writephy(tp, 0x05, 0x8b86); | |
76564428 | 3360 | rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000); |
01dc7fec | 3361 | rtl_writephy(tp, 0x1f, 0x0000); |
3362 | ||
3363 | rtl_writephy(tp, 0x1f, 0x0005); | |
3364 | rtl_writephy(tp, 0x05, 0x8b85); | |
76564428 | 3365 | rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000); |
01dc7fec | 3366 | rtl_writephy(tp, 0x1f, 0x0007); |
3367 | rtl_writephy(tp, 0x1e, 0x0020); | |
76564428 | 3368 | rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100); |
01dc7fec | 3369 | rtl_writephy(tp, 0x1f, 0x0006); |
3370 | rtl_writephy(tp, 0x00, 0x5a00); | |
3371 | rtl_writephy(tp, 0x1f, 0x0000); | |
3372 | rtl_writephy(tp, 0x0d, 0x0007); | |
3373 | rtl_writephy(tp, 0x0e, 0x003c); | |
3374 | rtl_writephy(tp, 0x0d, 0x4007); | |
3375 | rtl_writephy(tp, 0x0e, 0x0000); | |
3376 | rtl_writephy(tp, 0x0d, 0x0000); | |
3377 | } | |
3378 | ||
9ecb9aab | 3379 | static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr) |
3380 | { | |
3381 | const u16 w[] = { | |
3382 | addr[0] | (addr[1] << 8), | |
3383 | addr[2] | (addr[3] << 8), | |
3384 | addr[4] | (addr[5] << 8) | |
3385 | }; | |
3386 | const struct exgmac_reg e[] = { | |
3387 | { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) }, | |
3388 | { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] }, | |
3389 | { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 }, | |
3390 | { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) } | |
3391 | }; | |
3392 | ||
3393 | rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e)); | |
3394 | } | |
3395 | ||
70090424 HW |
3396 | static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp) |
3397 | { | |
3398 | static const struct phy_reg phy_reg_init[] = { | |
3399 | /* Enable Delay cap */ | |
3400 | { 0x1f, 0x0004 }, | |
3401 | { 0x1f, 0x0007 }, | |
3402 | { 0x1e, 0x00ac }, | |
3403 | { 0x18, 0x0006 }, | |
3404 | { 0x1f, 0x0002 }, | |
3405 | { 0x1f, 0x0000 }, | |
3406 | { 0x1f, 0x0000 }, | |
3407 | ||
3408 | /* Channel estimation fine tune */ | |
3409 | { 0x1f, 0x0003 }, | |
3410 | { 0x09, 0xa20f }, | |
3411 | { 0x1f, 0x0000 }, | |
3412 | { 0x1f, 0x0000 }, | |
3413 | ||
3414 | /* Green Setting */ | |
3415 | { 0x1f, 0x0005 }, | |
3416 | { 0x05, 0x8b5b }, | |
3417 | { 0x06, 0x9222 }, | |
3418 | { 0x05, 0x8b6d }, | |
3419 | { 0x06, 0x8000 }, | |
3420 | { 0x05, 0x8b76 }, | |
3421 | { 0x06, 0x8000 }, | |
3422 | { 0x1f, 0x0000 } | |
3423 | }; | |
3424 | ||
3425 | rtl_apply_firmware(tp); | |
3426 | ||
3427 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); | |
3428 | ||
3429 | /* For 4-corner performance improve */ | |
3430 | rtl_writephy(tp, 0x1f, 0x0005); | |
3431 | rtl_writephy(tp, 0x05, 0x8b80); | |
76564428 | 3432 | rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000); |
70090424 HW |
3433 | rtl_writephy(tp, 0x1f, 0x0000); |
3434 | ||
3435 | /* PHY auto speed down */ | |
3436 | rtl_writephy(tp, 0x1f, 0x0004); | |
3437 | rtl_writephy(tp, 0x1f, 0x0007); | |
3438 | rtl_writephy(tp, 0x1e, 0x002d); | |
76564428 | 3439 | rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000); |
70090424 HW |
3440 | rtl_writephy(tp, 0x1f, 0x0002); |
3441 | rtl_writephy(tp, 0x1f, 0x0000); | |
76564428 | 3442 | rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000); |
70090424 HW |
3443 | |
3444 | /* improve 10M EEE waveform */ | |
3445 | rtl_writephy(tp, 0x1f, 0x0005); | |
3446 | rtl_writephy(tp, 0x05, 0x8b86); | |
76564428 | 3447 | rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000); |
70090424 HW |
3448 | rtl_writephy(tp, 0x1f, 0x0000); |
3449 | ||
3450 | /* Improve 2-pair detection performance */ | |
3451 | rtl_writephy(tp, 0x1f, 0x0005); | |
3452 | rtl_writephy(tp, 0x05, 0x8b85); | |
76564428 | 3453 | rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000); |
70090424 HW |
3454 | rtl_writephy(tp, 0x1f, 0x0000); |
3455 | ||
3456 | /* EEE setting */ | |
706123d0 | 3457 | rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003, ERIAR_EXGMAC); |
70090424 HW |
3458 | rtl_writephy(tp, 0x1f, 0x0005); |
3459 | rtl_writephy(tp, 0x05, 0x8b85); | |
76564428 | 3460 | rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000); |
70090424 HW |
3461 | rtl_writephy(tp, 0x1f, 0x0004); |
3462 | rtl_writephy(tp, 0x1f, 0x0007); | |
3463 | rtl_writephy(tp, 0x1e, 0x0020); | |
76564428 | 3464 | rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0100); |
70090424 HW |
3465 | rtl_writephy(tp, 0x1f, 0x0002); |
3466 | rtl_writephy(tp, 0x1f, 0x0000); | |
3467 | rtl_writephy(tp, 0x0d, 0x0007); | |
3468 | rtl_writephy(tp, 0x0e, 0x003c); | |
3469 | rtl_writephy(tp, 0x0d, 0x4007); | |
3470 | rtl_writephy(tp, 0x0e, 0x0000); | |
3471 | rtl_writephy(tp, 0x0d, 0x0000); | |
3472 | ||
3473 | /* Green feature */ | |
3474 | rtl_writephy(tp, 0x1f, 0x0003); | |
76564428 CHL |
3475 | rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001); |
3476 | rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400); | |
70090424 | 3477 | rtl_writephy(tp, 0x1f, 0x0000); |
e0c07557 | 3478 | |
9ecb9aab | 3479 | /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */ |
3480 | rtl_rar_exgmac_set(tp, tp->dev->dev_addr); | |
70090424 HW |
3481 | } |
3482 | ||
5f886e08 HW |
3483 | static void rtl8168f_hw_phy_config(struct rtl8169_private *tp) |
3484 | { | |
3485 | /* For 4-corner performance improve */ | |
3486 | rtl_writephy(tp, 0x1f, 0x0005); | |
3487 | rtl_writephy(tp, 0x05, 0x8b80); | |
76564428 | 3488 | rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000); |
5f886e08 HW |
3489 | rtl_writephy(tp, 0x1f, 0x0000); |
3490 | ||
3491 | /* PHY auto speed down */ | |
3492 | rtl_writephy(tp, 0x1f, 0x0007); | |
3493 | rtl_writephy(tp, 0x1e, 0x002d); | |
76564428 | 3494 | rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000); |
5f886e08 | 3495 | rtl_writephy(tp, 0x1f, 0x0000); |
76564428 | 3496 | rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000); |
5f886e08 HW |
3497 | |
3498 | /* Improve 10M EEE waveform */ | |
3499 | rtl_writephy(tp, 0x1f, 0x0005); | |
3500 | rtl_writephy(tp, 0x05, 0x8b86); | |
76564428 | 3501 | rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000); |
5f886e08 HW |
3502 | rtl_writephy(tp, 0x1f, 0x0000); |
3503 | } | |
3504 | ||
c2218925 HW |
3505 | static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp) |
3506 | { | |
3507 | static const struct phy_reg phy_reg_init[] = { | |
3508 | /* Channel estimation fine tune */ | |
3509 | { 0x1f, 0x0003 }, | |
3510 | { 0x09, 0xa20f }, | |
3511 | { 0x1f, 0x0000 }, | |
3512 | ||
3513 | /* Modify green table for giga & fnet */ | |
3514 | { 0x1f, 0x0005 }, | |
3515 | { 0x05, 0x8b55 }, | |
3516 | { 0x06, 0x0000 }, | |
3517 | { 0x05, 0x8b5e }, | |
3518 | { 0x06, 0x0000 }, | |
3519 | { 0x05, 0x8b67 }, | |
3520 | { 0x06, 0x0000 }, | |
3521 | { 0x05, 0x8b70 }, | |
3522 | { 0x06, 0x0000 }, | |
3523 | { 0x1f, 0x0000 }, | |
3524 | { 0x1f, 0x0007 }, | |
3525 | { 0x1e, 0x0078 }, | |
3526 | { 0x17, 0x0000 }, | |
3527 | { 0x19, 0x00fb }, | |
3528 | { 0x1f, 0x0000 }, | |
3529 | ||
3530 | /* Modify green table for 10M */ | |
3531 | { 0x1f, 0x0005 }, | |
3532 | { 0x05, 0x8b79 }, | |
3533 | { 0x06, 0xaa00 }, | |
3534 | { 0x1f, 0x0000 }, | |
3535 | ||
3536 | /* Disable hiimpedance detection (RTCT) */ | |
3537 | { 0x1f, 0x0003 }, | |
3538 | { 0x01, 0x328a }, | |
3539 | { 0x1f, 0x0000 } | |
3540 | }; | |
3541 | ||
3542 | rtl_apply_firmware(tp); | |
3543 | ||
3544 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); | |
3545 | ||
5f886e08 | 3546 | rtl8168f_hw_phy_config(tp); |
c2218925 HW |
3547 | |
3548 | /* Improve 2-pair detection performance */ | |
3549 | rtl_writephy(tp, 0x1f, 0x0005); | |
3550 | rtl_writephy(tp, 0x05, 0x8b85); | |
76564428 | 3551 | rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000); |
c2218925 HW |
3552 | rtl_writephy(tp, 0x1f, 0x0000); |
3553 | } | |
3554 | ||
3555 | static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp) | |
3556 | { | |
3557 | rtl_apply_firmware(tp); | |
3558 | ||
5f886e08 | 3559 | rtl8168f_hw_phy_config(tp); |
c2218925 HW |
3560 | } |
3561 | ||
b3d7b2f2 HW |
3562 | static void rtl8411_hw_phy_config(struct rtl8169_private *tp) |
3563 | { | |
b3d7b2f2 HW |
3564 | static const struct phy_reg phy_reg_init[] = { |
3565 | /* Channel estimation fine tune */ | |
3566 | { 0x1f, 0x0003 }, | |
3567 | { 0x09, 0xa20f }, | |
3568 | { 0x1f, 0x0000 }, | |
3569 | ||
3570 | /* Modify green table for giga & fnet */ | |
3571 | { 0x1f, 0x0005 }, | |
3572 | { 0x05, 0x8b55 }, | |
3573 | { 0x06, 0x0000 }, | |
3574 | { 0x05, 0x8b5e }, | |
3575 | { 0x06, 0x0000 }, | |
3576 | { 0x05, 0x8b67 }, | |
3577 | { 0x06, 0x0000 }, | |
3578 | { 0x05, 0x8b70 }, | |
3579 | { 0x06, 0x0000 }, | |
3580 | { 0x1f, 0x0000 }, | |
3581 | { 0x1f, 0x0007 }, | |
3582 | { 0x1e, 0x0078 }, | |
3583 | { 0x17, 0x0000 }, | |
3584 | { 0x19, 0x00aa }, | |
3585 | { 0x1f, 0x0000 }, | |
3586 | ||
3587 | /* Modify green table for 10M */ | |
3588 | { 0x1f, 0x0005 }, | |
3589 | { 0x05, 0x8b79 }, | |
3590 | { 0x06, 0xaa00 }, | |
3591 | { 0x1f, 0x0000 }, | |
3592 | ||
3593 | /* Disable hiimpedance detection (RTCT) */ | |
3594 | { 0x1f, 0x0003 }, | |
3595 | { 0x01, 0x328a }, | |
3596 | { 0x1f, 0x0000 } | |
3597 | }; | |
3598 | ||
3599 | ||
3600 | rtl_apply_firmware(tp); | |
3601 | ||
3602 | rtl8168f_hw_phy_config(tp); | |
3603 | ||
3604 | /* Improve 2-pair detection performance */ | |
3605 | rtl_writephy(tp, 0x1f, 0x0005); | |
3606 | rtl_writephy(tp, 0x05, 0x8b85); | |
76564428 | 3607 | rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000); |
b3d7b2f2 HW |
3608 | rtl_writephy(tp, 0x1f, 0x0000); |
3609 | ||
3610 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); | |
3611 | ||
3612 | /* Modify green table for giga */ | |
3613 | rtl_writephy(tp, 0x1f, 0x0005); | |
3614 | rtl_writephy(tp, 0x05, 0x8b54); | |
76564428 | 3615 | rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800); |
b3d7b2f2 | 3616 | rtl_writephy(tp, 0x05, 0x8b5d); |
76564428 | 3617 | rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800); |
b3d7b2f2 | 3618 | rtl_writephy(tp, 0x05, 0x8a7c); |
76564428 | 3619 | rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100); |
b3d7b2f2 | 3620 | rtl_writephy(tp, 0x05, 0x8a7f); |
76564428 | 3621 | rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000); |
b3d7b2f2 | 3622 | rtl_writephy(tp, 0x05, 0x8a82); |
76564428 | 3623 | rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100); |
b3d7b2f2 | 3624 | rtl_writephy(tp, 0x05, 0x8a85); |
76564428 | 3625 | rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100); |
b3d7b2f2 | 3626 | rtl_writephy(tp, 0x05, 0x8a88); |
76564428 | 3627 | rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100); |
b3d7b2f2 HW |
3628 | rtl_writephy(tp, 0x1f, 0x0000); |
3629 | ||
3630 | /* uc same-seed solution */ | |
3631 | rtl_writephy(tp, 0x1f, 0x0005); | |
3632 | rtl_writephy(tp, 0x05, 0x8b85); | |
76564428 | 3633 | rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000); |
b3d7b2f2 HW |
3634 | rtl_writephy(tp, 0x1f, 0x0000); |
3635 | ||
3636 | /* eee setting */ | |
706123d0 | 3637 | rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC); |
b3d7b2f2 HW |
3638 | rtl_writephy(tp, 0x1f, 0x0005); |
3639 | rtl_writephy(tp, 0x05, 0x8b85); | |
76564428 | 3640 | rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000); |
b3d7b2f2 HW |
3641 | rtl_writephy(tp, 0x1f, 0x0004); |
3642 | rtl_writephy(tp, 0x1f, 0x0007); | |
3643 | rtl_writephy(tp, 0x1e, 0x0020); | |
76564428 | 3644 | rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0100); |
b3d7b2f2 HW |
3645 | rtl_writephy(tp, 0x1f, 0x0000); |
3646 | rtl_writephy(tp, 0x0d, 0x0007); | |
3647 | rtl_writephy(tp, 0x0e, 0x003c); | |
3648 | rtl_writephy(tp, 0x0d, 0x4007); | |
3649 | rtl_writephy(tp, 0x0e, 0x0000); | |
3650 | rtl_writephy(tp, 0x0d, 0x0000); | |
3651 | ||
3652 | /* Green feature */ | |
3653 | rtl_writephy(tp, 0x1f, 0x0003); | |
76564428 CHL |
3654 | rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001); |
3655 | rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400); | |
b3d7b2f2 HW |
3656 | rtl_writephy(tp, 0x1f, 0x0000); |
3657 | } | |
3658 | ||
c558386b HW |
3659 | static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp) |
3660 | { | |
c558386b HW |
3661 | rtl_apply_firmware(tp); |
3662 | ||
41f44d13 | 3663 | rtl_writephy(tp, 0x1f, 0x0a46); |
3664 | if (rtl_readphy(tp, 0x10) & 0x0100) { | |
3665 | rtl_writephy(tp, 0x1f, 0x0bcc); | |
76564428 | 3666 | rtl_w0w1_phy(tp, 0x12, 0x0000, 0x8000); |
41f44d13 | 3667 | } else { |
3668 | rtl_writephy(tp, 0x1f, 0x0bcc); | |
76564428 | 3669 | rtl_w0w1_phy(tp, 0x12, 0x8000, 0x0000); |
41f44d13 | 3670 | } |
c558386b | 3671 | |
41f44d13 | 3672 | rtl_writephy(tp, 0x1f, 0x0a46); |
3673 | if (rtl_readphy(tp, 0x13) & 0x0100) { | |
3674 | rtl_writephy(tp, 0x1f, 0x0c41); | |
76564428 | 3675 | rtl_w0w1_phy(tp, 0x15, 0x0002, 0x0000); |
41f44d13 | 3676 | } else { |
fe7524c0 | 3677 | rtl_writephy(tp, 0x1f, 0x0c41); |
76564428 | 3678 | rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0002); |
41f44d13 | 3679 | } |
c558386b | 3680 | |
41f44d13 | 3681 | /* Enable PHY auto speed down */ |
3682 | rtl_writephy(tp, 0x1f, 0x0a44); | |
76564428 | 3683 | rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000); |
c558386b | 3684 | |
fe7524c0 | 3685 | rtl_writephy(tp, 0x1f, 0x0bcc); |
76564428 | 3686 | rtl_w0w1_phy(tp, 0x14, 0x0100, 0x0000); |
fe7524c0 | 3687 | rtl_writephy(tp, 0x1f, 0x0a44); |
76564428 | 3688 | rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000); |
fe7524c0 | 3689 | rtl_writephy(tp, 0x1f, 0x0a43); |
3690 | rtl_writephy(tp, 0x13, 0x8084); | |
76564428 CHL |
3691 | rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000); |
3692 | rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000); | |
fe7524c0 | 3693 | |
41f44d13 | 3694 | /* EEE auto-fallback function */ |
3695 | rtl_writephy(tp, 0x1f, 0x0a4b); | |
76564428 | 3696 | rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000); |
c558386b | 3697 | |
41f44d13 | 3698 | /* Enable UC LPF tune function */ |
3699 | rtl_writephy(tp, 0x1f, 0x0a43); | |
3700 | rtl_writephy(tp, 0x13, 0x8012); | |
76564428 | 3701 | rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000); |
41f44d13 | 3702 | |
3703 | rtl_writephy(tp, 0x1f, 0x0c42); | |
76564428 | 3704 | rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000); |
41f44d13 | 3705 | |
fe7524c0 | 3706 | /* Improve SWR Efficiency */ |
3707 | rtl_writephy(tp, 0x1f, 0x0bcd); | |
3708 | rtl_writephy(tp, 0x14, 0x5065); | |
3709 | rtl_writephy(tp, 0x14, 0xd065); | |
3710 | rtl_writephy(tp, 0x1f, 0x0bc8); | |
3711 | rtl_writephy(tp, 0x11, 0x5655); | |
3712 | rtl_writephy(tp, 0x1f, 0x0bcd); | |
3713 | rtl_writephy(tp, 0x14, 0x1065); | |
3714 | rtl_writephy(tp, 0x14, 0x9065); | |
3715 | rtl_writephy(tp, 0x14, 0x1065); | |
3716 | ||
1bac1072 DC |
3717 | /* Check ALDPS bit, disable it if enabled */ |
3718 | rtl_writephy(tp, 0x1f, 0x0a43); | |
3719 | if (rtl_readphy(tp, 0x10) & 0x0004) | |
76564428 | 3720 | rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004); |
1bac1072 | 3721 | |
41f44d13 | 3722 | rtl_writephy(tp, 0x1f, 0x0000); |
c558386b HW |
3723 | } |
3724 | ||
57538c4a | 3725 | static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp) |
3726 | { | |
3727 | rtl_apply_firmware(tp); | |
3728 | } | |
3729 | ||
6e1d0b89 CHL |
3730 | static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp) |
3731 | { | |
3732 | u16 dout_tapbin; | |
3733 | u32 data; | |
3734 | ||
3735 | rtl_apply_firmware(tp); | |
3736 | ||
3737 | /* CHN EST parameters adjust - giga master */ | |
3738 | rtl_writephy(tp, 0x1f, 0x0a43); | |
3739 | rtl_writephy(tp, 0x13, 0x809b); | |
76564428 | 3740 | rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800); |
6e1d0b89 | 3741 | rtl_writephy(tp, 0x13, 0x80a2); |
76564428 | 3742 | rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00); |
6e1d0b89 | 3743 | rtl_writephy(tp, 0x13, 0x80a4); |
76564428 | 3744 | rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00); |
6e1d0b89 | 3745 | rtl_writephy(tp, 0x13, 0x809c); |
76564428 | 3746 | rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00); |
6e1d0b89 CHL |
3747 | rtl_writephy(tp, 0x1f, 0x0000); |
3748 | ||
3749 | /* CHN EST parameters adjust - giga slave */ | |
3750 | rtl_writephy(tp, 0x1f, 0x0a43); | |
3751 | rtl_writephy(tp, 0x13, 0x80ad); | |
76564428 | 3752 | rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800); |
6e1d0b89 | 3753 | rtl_writephy(tp, 0x13, 0x80b4); |
76564428 | 3754 | rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00); |
6e1d0b89 | 3755 | rtl_writephy(tp, 0x13, 0x80ac); |
76564428 | 3756 | rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00); |
6e1d0b89 CHL |
3757 | rtl_writephy(tp, 0x1f, 0x0000); |
3758 | ||
3759 | /* CHN EST parameters adjust - fnet */ | |
3760 | rtl_writephy(tp, 0x1f, 0x0a43); | |
3761 | rtl_writephy(tp, 0x13, 0x808e); | |
76564428 | 3762 | rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00); |
6e1d0b89 | 3763 | rtl_writephy(tp, 0x13, 0x8090); |
76564428 | 3764 | rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00); |
6e1d0b89 | 3765 | rtl_writephy(tp, 0x13, 0x8092); |
76564428 | 3766 | rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00); |
6e1d0b89 CHL |
3767 | rtl_writephy(tp, 0x1f, 0x0000); |
3768 | ||
3769 | /* enable R-tune & PGA-retune function */ | |
3770 | dout_tapbin = 0; | |
3771 | rtl_writephy(tp, 0x1f, 0x0a46); | |
3772 | data = rtl_readphy(tp, 0x13); | |
3773 | data &= 3; | |
3774 | data <<= 2; | |
3775 | dout_tapbin |= data; | |
3776 | data = rtl_readphy(tp, 0x12); | |
3777 | data &= 0xc000; | |
3778 | data >>= 14; | |
3779 | dout_tapbin |= data; | |
3780 | dout_tapbin = ~(dout_tapbin^0x08); | |
3781 | dout_tapbin <<= 12; | |
3782 | dout_tapbin &= 0xf000; | |
3783 | rtl_writephy(tp, 0x1f, 0x0a43); | |
3784 | rtl_writephy(tp, 0x13, 0x827a); | |
76564428 | 3785 | rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000); |
6e1d0b89 | 3786 | rtl_writephy(tp, 0x13, 0x827b); |
76564428 | 3787 | rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000); |
6e1d0b89 | 3788 | rtl_writephy(tp, 0x13, 0x827c); |
76564428 | 3789 | rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000); |
6e1d0b89 | 3790 | rtl_writephy(tp, 0x13, 0x827d); |
76564428 | 3791 | rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000); |
6e1d0b89 CHL |
3792 | |
3793 | rtl_writephy(tp, 0x1f, 0x0a43); | |
3794 | rtl_writephy(tp, 0x13, 0x0811); | |
76564428 | 3795 | rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000); |
6e1d0b89 | 3796 | rtl_writephy(tp, 0x1f, 0x0a42); |
76564428 | 3797 | rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000); |
6e1d0b89 CHL |
3798 | rtl_writephy(tp, 0x1f, 0x0000); |
3799 | ||
3800 | /* enable GPHY 10M */ | |
3801 | rtl_writephy(tp, 0x1f, 0x0a44); | |
76564428 | 3802 | rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000); |
6e1d0b89 CHL |
3803 | rtl_writephy(tp, 0x1f, 0x0000); |
3804 | ||
3805 | /* SAR ADC performance */ | |
3806 | rtl_writephy(tp, 0x1f, 0x0bca); | |
76564428 | 3807 | rtl_w0w1_phy(tp, 0x17, 0x4000, 0x3000); |
6e1d0b89 CHL |
3808 | rtl_writephy(tp, 0x1f, 0x0000); |
3809 | ||
3810 | rtl_writephy(tp, 0x1f, 0x0a43); | |
3811 | rtl_writephy(tp, 0x13, 0x803f); | |
76564428 | 3812 | rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000); |
6e1d0b89 | 3813 | rtl_writephy(tp, 0x13, 0x8047); |
76564428 | 3814 | rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000); |
6e1d0b89 | 3815 | rtl_writephy(tp, 0x13, 0x804f); |
76564428 | 3816 | rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000); |
6e1d0b89 | 3817 | rtl_writephy(tp, 0x13, 0x8057); |
76564428 | 3818 | rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000); |
6e1d0b89 | 3819 | rtl_writephy(tp, 0x13, 0x805f); |
76564428 | 3820 | rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000); |
6e1d0b89 | 3821 | rtl_writephy(tp, 0x13, 0x8067); |
76564428 | 3822 | rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000); |
6e1d0b89 | 3823 | rtl_writephy(tp, 0x13, 0x806f); |
76564428 | 3824 | rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000); |
6e1d0b89 CHL |
3825 | rtl_writephy(tp, 0x1f, 0x0000); |
3826 | ||
3827 | /* disable phy pfm mode */ | |
3828 | rtl_writephy(tp, 0x1f, 0x0a44); | |
76564428 | 3829 | rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0080); |
6e1d0b89 CHL |
3830 | rtl_writephy(tp, 0x1f, 0x0000); |
3831 | ||
3832 | /* Check ALDPS bit, disable it if enabled */ | |
3833 | rtl_writephy(tp, 0x1f, 0x0a43); | |
3834 | if (rtl_readphy(tp, 0x10) & 0x0004) | |
76564428 | 3835 | rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004); |
6e1d0b89 CHL |
3836 | |
3837 | rtl_writephy(tp, 0x1f, 0x0000); | |
3838 | } | |
3839 | ||
3840 | static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp) | |
3841 | { | |
3842 | u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0; | |
3843 | u16 rlen; | |
3844 | u32 data; | |
3845 | ||
3846 | rtl_apply_firmware(tp); | |
3847 | ||
3848 | /* CHIN EST parameter update */ | |
3849 | rtl_writephy(tp, 0x1f, 0x0a43); | |
3850 | rtl_writephy(tp, 0x13, 0x808a); | |
76564428 | 3851 | rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f); |
6e1d0b89 CHL |
3852 | rtl_writephy(tp, 0x1f, 0x0000); |
3853 | ||
3854 | /* enable R-tune & PGA-retune function */ | |
3855 | rtl_writephy(tp, 0x1f, 0x0a43); | |
3856 | rtl_writephy(tp, 0x13, 0x0811); | |
76564428 | 3857 | rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000); |
6e1d0b89 | 3858 | rtl_writephy(tp, 0x1f, 0x0a42); |
76564428 | 3859 | rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000); |
6e1d0b89 CHL |
3860 | rtl_writephy(tp, 0x1f, 0x0000); |
3861 | ||
3862 | /* enable GPHY 10M */ | |
3863 | rtl_writephy(tp, 0x1f, 0x0a44); | |
76564428 | 3864 | rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000); |
6e1d0b89 CHL |
3865 | rtl_writephy(tp, 0x1f, 0x0000); |
3866 | ||
3867 | r8168_mac_ocp_write(tp, 0xdd02, 0x807d); | |
3868 | data = r8168_mac_ocp_read(tp, 0xdd02); | |
3869 | ioffset_p3 = ((data & 0x80)>>7); | |
3870 | ioffset_p3 <<= 3; | |
3871 | ||
3872 | data = r8168_mac_ocp_read(tp, 0xdd00); | |
3873 | ioffset_p3 |= ((data & (0xe000))>>13); | |
3874 | ioffset_p2 = ((data & (0x1e00))>>9); | |
3875 | ioffset_p1 = ((data & (0x01e0))>>5); | |
3876 | ioffset_p0 = ((data & 0x0010)>>4); | |
3877 | ioffset_p0 <<= 3; | |
3878 | ioffset_p0 |= (data & (0x07)); | |
3879 | data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0); | |
3880 | ||
05b9687b CHL |
3881 | if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) || |
3882 | (ioffset_p1 != 0x0f) || (ioffset_p0 == 0x0f)) { | |
6e1d0b89 CHL |
3883 | rtl_writephy(tp, 0x1f, 0x0bcf); |
3884 | rtl_writephy(tp, 0x16, data); | |
3885 | rtl_writephy(tp, 0x1f, 0x0000); | |
3886 | } | |
3887 | ||
3888 | /* Modify rlen (TX LPF corner frequency) level */ | |
3889 | rtl_writephy(tp, 0x1f, 0x0bcd); | |
3890 | data = rtl_readphy(tp, 0x16); | |
3891 | data &= 0x000f; | |
3892 | rlen = 0; | |
3893 | if (data > 3) | |
3894 | rlen = data - 3; | |
3895 | data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12); | |
3896 | rtl_writephy(tp, 0x17, data); | |
3897 | rtl_writephy(tp, 0x1f, 0x0bcd); | |
3898 | rtl_writephy(tp, 0x1f, 0x0000); | |
3899 | ||
3900 | /* disable phy pfm mode */ | |
3901 | rtl_writephy(tp, 0x1f, 0x0a44); | |
76564428 | 3902 | rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0080); |
6e1d0b89 CHL |
3903 | rtl_writephy(tp, 0x1f, 0x0000); |
3904 | ||
3905 | /* Check ALDPS bit, disable it if enabled */ | |
3906 | rtl_writephy(tp, 0x1f, 0x0a43); | |
3907 | if (rtl_readphy(tp, 0x10) & 0x0004) | |
76564428 | 3908 | rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004); |
6e1d0b89 CHL |
3909 | |
3910 | rtl_writephy(tp, 0x1f, 0x0000); | |
3911 | } | |
3912 | ||
935e2218 CHL |
3913 | static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp) |
3914 | { | |
3915 | /* Enable PHY auto speed down */ | |
3916 | rtl_writephy(tp, 0x1f, 0x0a44); | |
3917 | rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000); | |
3918 | rtl_writephy(tp, 0x1f, 0x0000); | |
3919 | ||
3920 | /* patch 10M & ALDPS */ | |
3921 | rtl_writephy(tp, 0x1f, 0x0bcc); | |
3922 | rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100); | |
3923 | rtl_writephy(tp, 0x1f, 0x0a44); | |
3924 | rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000); | |
3925 | rtl_writephy(tp, 0x1f, 0x0a43); | |
3926 | rtl_writephy(tp, 0x13, 0x8084); | |
3927 | rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000); | |
3928 | rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000); | |
3929 | rtl_writephy(tp, 0x1f, 0x0000); | |
3930 | ||
3931 | /* Enable EEE auto-fallback function */ | |
3932 | rtl_writephy(tp, 0x1f, 0x0a4b); | |
3933 | rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000); | |
3934 | rtl_writephy(tp, 0x1f, 0x0000); | |
3935 | ||
3936 | /* Enable UC LPF tune function */ | |
3937 | rtl_writephy(tp, 0x1f, 0x0a43); | |
3938 | rtl_writephy(tp, 0x13, 0x8012); | |
3939 | rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000); | |
3940 | rtl_writephy(tp, 0x1f, 0x0000); | |
3941 | ||
3942 | /* set rg_sel_sdm_rate */ | |
3943 | rtl_writephy(tp, 0x1f, 0x0c42); | |
3944 | rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000); | |
3945 | rtl_writephy(tp, 0x1f, 0x0000); | |
3946 | ||
3947 | /* Check ALDPS bit, disable it if enabled */ | |
3948 | rtl_writephy(tp, 0x1f, 0x0a43); | |
3949 | if (rtl_readphy(tp, 0x10) & 0x0004) | |
3950 | rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004); | |
3951 | ||
3952 | rtl_writephy(tp, 0x1f, 0x0000); | |
3953 | } | |
3954 | ||
3955 | static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp) | |
3956 | { | |
3957 | /* patch 10M & ALDPS */ | |
3958 | rtl_writephy(tp, 0x1f, 0x0bcc); | |
3959 | rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100); | |
3960 | rtl_writephy(tp, 0x1f, 0x0a44); | |
3961 | rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000); | |
3962 | rtl_writephy(tp, 0x1f, 0x0a43); | |
3963 | rtl_writephy(tp, 0x13, 0x8084); | |
3964 | rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000); | |
3965 | rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000); | |
3966 | rtl_writephy(tp, 0x1f, 0x0000); | |
3967 | ||
3968 | /* Enable UC LPF tune function */ | |
3969 | rtl_writephy(tp, 0x1f, 0x0a43); | |
3970 | rtl_writephy(tp, 0x13, 0x8012); | |
3971 | rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000); | |
3972 | rtl_writephy(tp, 0x1f, 0x0000); | |
3973 | ||
3974 | /* Set rg_sel_sdm_rate */ | |
3975 | rtl_writephy(tp, 0x1f, 0x0c42); | |
3976 | rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000); | |
3977 | rtl_writephy(tp, 0x1f, 0x0000); | |
3978 | ||
3979 | /* Channel estimation parameters */ | |
3980 | rtl_writephy(tp, 0x1f, 0x0a43); | |
3981 | rtl_writephy(tp, 0x13, 0x80f3); | |
3982 | rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff); | |
3983 | rtl_writephy(tp, 0x13, 0x80f0); | |
3984 | rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff); | |
3985 | rtl_writephy(tp, 0x13, 0x80ef); | |
3986 | rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff); | |
3987 | rtl_writephy(tp, 0x13, 0x80f6); | |
3988 | rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff); | |
3989 | rtl_writephy(tp, 0x13, 0x80ec); | |
3990 | rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff); | |
3991 | rtl_writephy(tp, 0x13, 0x80ed); | |
3992 | rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff); | |
3993 | rtl_writephy(tp, 0x13, 0x80f2); | |
3994 | rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff); | |
3995 | rtl_writephy(tp, 0x13, 0x80f4); | |
3996 | rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff); | |
3997 | rtl_writephy(tp, 0x1f, 0x0a43); | |
3998 | rtl_writephy(tp, 0x13, 0x8110); | |
3999 | rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff); | |
4000 | rtl_writephy(tp, 0x13, 0x810f); | |
4001 | rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff); | |
4002 | rtl_writephy(tp, 0x13, 0x8111); | |
4003 | rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff); | |
4004 | rtl_writephy(tp, 0x13, 0x8113); | |
4005 | rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff); | |
4006 | rtl_writephy(tp, 0x13, 0x8115); | |
4007 | rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff); | |
4008 | rtl_writephy(tp, 0x13, 0x810e); | |
4009 | rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff); | |
4010 | rtl_writephy(tp, 0x13, 0x810c); | |
4011 | rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff); | |
4012 | rtl_writephy(tp, 0x13, 0x810b); | |
4013 | rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff); | |
4014 | rtl_writephy(tp, 0x1f, 0x0a43); | |
4015 | rtl_writephy(tp, 0x13, 0x80d1); | |
4016 | rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff); | |
4017 | rtl_writephy(tp, 0x13, 0x80cd); | |
4018 | rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff); | |
4019 | rtl_writephy(tp, 0x13, 0x80d3); | |
4020 | rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff); | |
4021 | rtl_writephy(tp, 0x13, 0x80d5); | |
4022 | rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff); | |
4023 | rtl_writephy(tp, 0x13, 0x80d7); | |
4024 | rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff); | |
4025 | ||
4026 | /* Force PWM-mode */ | |
4027 | rtl_writephy(tp, 0x1f, 0x0bcd); | |
4028 | rtl_writephy(tp, 0x14, 0x5065); | |
4029 | rtl_writephy(tp, 0x14, 0xd065); | |
4030 | rtl_writephy(tp, 0x1f, 0x0bc8); | |
4031 | rtl_writephy(tp, 0x12, 0x00ed); | |
4032 | rtl_writephy(tp, 0x1f, 0x0bcd); | |
4033 | rtl_writephy(tp, 0x14, 0x1065); | |
4034 | rtl_writephy(tp, 0x14, 0x9065); | |
4035 | rtl_writephy(tp, 0x14, 0x1065); | |
4036 | rtl_writephy(tp, 0x1f, 0x0000); | |
4037 | ||
4038 | /* Check ALDPS bit, disable it if enabled */ | |
4039 | rtl_writephy(tp, 0x1f, 0x0a43); | |
4040 | if (rtl_readphy(tp, 0x10) & 0x0004) | |
4041 | rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004); | |
4042 | ||
4043 | rtl_writephy(tp, 0x1f, 0x0000); | |
4044 | } | |
4045 | ||
4da19633 | 4046 | static void rtl8102e_hw_phy_config(struct rtl8169_private *tp) |
2857ffb7 | 4047 | { |
350f7596 | 4048 | static const struct phy_reg phy_reg_init[] = { |
2857ffb7 FR |
4049 | { 0x1f, 0x0003 }, |
4050 | { 0x08, 0x441d }, | |
4051 | { 0x01, 0x9100 }, | |
4052 | { 0x1f, 0x0000 } | |
4053 | }; | |
4054 | ||
4da19633 | 4055 | rtl_writephy(tp, 0x1f, 0x0000); |
4056 | rtl_patchphy(tp, 0x11, 1 << 12); | |
4057 | rtl_patchphy(tp, 0x19, 1 << 13); | |
4058 | rtl_patchphy(tp, 0x10, 1 << 15); | |
2857ffb7 | 4059 | |
4da19633 | 4060 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
2857ffb7 FR |
4061 | } |
4062 | ||
5a5e4443 HW |
4063 | static void rtl8105e_hw_phy_config(struct rtl8169_private *tp) |
4064 | { | |
4065 | static const struct phy_reg phy_reg_init[] = { | |
4066 | { 0x1f, 0x0005 }, | |
4067 | { 0x1a, 0x0000 }, | |
4068 | { 0x1f, 0x0000 }, | |
4069 | ||
4070 | { 0x1f, 0x0004 }, | |
4071 | { 0x1c, 0x0000 }, | |
4072 | { 0x1f, 0x0000 }, | |
4073 | ||
4074 | { 0x1f, 0x0001 }, | |
4075 | { 0x15, 0x7701 }, | |
4076 | { 0x1f, 0x0000 } | |
4077 | }; | |
4078 | ||
4079 | /* Disable ALDPS before ram code */ | |
eef63cc1 FR |
4080 | rtl_writephy(tp, 0x1f, 0x0000); |
4081 | rtl_writephy(tp, 0x18, 0x0310); | |
4082 | msleep(100); | |
5a5e4443 | 4083 | |
953a12cc | 4084 | rtl_apply_firmware(tp); |
5a5e4443 HW |
4085 | |
4086 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); | |
4087 | } | |
4088 | ||
7e18dca1 HW |
4089 | static void rtl8402_hw_phy_config(struct rtl8169_private *tp) |
4090 | { | |
7e18dca1 | 4091 | /* Disable ALDPS before setting firmware */ |
eef63cc1 FR |
4092 | rtl_writephy(tp, 0x1f, 0x0000); |
4093 | rtl_writephy(tp, 0x18, 0x0310); | |
4094 | msleep(20); | |
7e18dca1 HW |
4095 | |
4096 | rtl_apply_firmware(tp); | |
4097 | ||
4098 | /* EEE setting */ | |
fdf6fc06 | 4099 | rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); |
7e18dca1 HW |
4100 | rtl_writephy(tp, 0x1f, 0x0004); |
4101 | rtl_writephy(tp, 0x10, 0x401f); | |
4102 | rtl_writephy(tp, 0x19, 0x7030); | |
4103 | rtl_writephy(tp, 0x1f, 0x0000); | |
4104 | } | |
4105 | ||
5598bfe5 HW |
4106 | static void rtl8106e_hw_phy_config(struct rtl8169_private *tp) |
4107 | { | |
5598bfe5 HW |
4108 | static const struct phy_reg phy_reg_init[] = { |
4109 | { 0x1f, 0x0004 }, | |
4110 | { 0x10, 0xc07f }, | |
4111 | { 0x19, 0x7030 }, | |
4112 | { 0x1f, 0x0000 } | |
4113 | }; | |
4114 | ||
4115 | /* Disable ALDPS before ram code */ | |
eef63cc1 FR |
4116 | rtl_writephy(tp, 0x1f, 0x0000); |
4117 | rtl_writephy(tp, 0x18, 0x0310); | |
4118 | msleep(100); | |
5598bfe5 HW |
4119 | |
4120 | rtl_apply_firmware(tp); | |
4121 | ||
fdf6fc06 | 4122 | rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); |
5598bfe5 HW |
4123 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
4124 | ||
fdf6fc06 | 4125 | rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); |
5598bfe5 HW |
4126 | } |
4127 | ||
5615d9f1 FR |
4128 | static void rtl_hw_phy_config(struct net_device *dev) |
4129 | { | |
4130 | struct rtl8169_private *tp = netdev_priv(dev); | |
5615d9f1 FR |
4131 | |
4132 | rtl8169_print_mac_version(tp); | |
4133 | ||
4134 | switch (tp->mac_version) { | |
4135 | case RTL_GIGA_MAC_VER_01: | |
4136 | break; | |
4137 | case RTL_GIGA_MAC_VER_02: | |
4138 | case RTL_GIGA_MAC_VER_03: | |
4da19633 | 4139 | rtl8169s_hw_phy_config(tp); |
5615d9f1 FR |
4140 | break; |
4141 | case RTL_GIGA_MAC_VER_04: | |
4da19633 | 4142 | rtl8169sb_hw_phy_config(tp); |
5615d9f1 | 4143 | break; |
2e955856 | 4144 | case RTL_GIGA_MAC_VER_05: |
4da19633 | 4145 | rtl8169scd_hw_phy_config(tp); |
2e955856 | 4146 | break; |
8c7006aa | 4147 | case RTL_GIGA_MAC_VER_06: |
4da19633 | 4148 | rtl8169sce_hw_phy_config(tp); |
8c7006aa | 4149 | break; |
2857ffb7 FR |
4150 | case RTL_GIGA_MAC_VER_07: |
4151 | case RTL_GIGA_MAC_VER_08: | |
4152 | case RTL_GIGA_MAC_VER_09: | |
4da19633 | 4153 | rtl8102e_hw_phy_config(tp); |
2857ffb7 | 4154 | break; |
236b8082 | 4155 | case RTL_GIGA_MAC_VER_11: |
4da19633 | 4156 | rtl8168bb_hw_phy_config(tp); |
236b8082 FR |
4157 | break; |
4158 | case RTL_GIGA_MAC_VER_12: | |
4da19633 | 4159 | rtl8168bef_hw_phy_config(tp); |
236b8082 FR |
4160 | break; |
4161 | case RTL_GIGA_MAC_VER_17: | |
4da19633 | 4162 | rtl8168bef_hw_phy_config(tp); |
236b8082 | 4163 | break; |
867763c1 | 4164 | case RTL_GIGA_MAC_VER_18: |
4da19633 | 4165 | rtl8168cp_1_hw_phy_config(tp); |
867763c1 FR |
4166 | break; |
4167 | case RTL_GIGA_MAC_VER_19: | |
4da19633 | 4168 | rtl8168c_1_hw_phy_config(tp); |
867763c1 | 4169 | break; |
7da97ec9 | 4170 | case RTL_GIGA_MAC_VER_20: |
4da19633 | 4171 | rtl8168c_2_hw_phy_config(tp); |
7da97ec9 | 4172 | break; |
197ff761 | 4173 | case RTL_GIGA_MAC_VER_21: |
4da19633 | 4174 | rtl8168c_3_hw_phy_config(tp); |
197ff761 | 4175 | break; |
6fb07058 | 4176 | case RTL_GIGA_MAC_VER_22: |
4da19633 | 4177 | rtl8168c_4_hw_phy_config(tp); |
6fb07058 | 4178 | break; |
ef3386f0 | 4179 | case RTL_GIGA_MAC_VER_23: |
7f3e3d3a | 4180 | case RTL_GIGA_MAC_VER_24: |
4da19633 | 4181 | rtl8168cp_2_hw_phy_config(tp); |
ef3386f0 | 4182 | break; |
5b538df9 | 4183 | case RTL_GIGA_MAC_VER_25: |
bca03d5f | 4184 | rtl8168d_1_hw_phy_config(tp); |
daf9df6d | 4185 | break; |
4186 | case RTL_GIGA_MAC_VER_26: | |
bca03d5f | 4187 | rtl8168d_2_hw_phy_config(tp); |
daf9df6d | 4188 | break; |
4189 | case RTL_GIGA_MAC_VER_27: | |
4da19633 | 4190 | rtl8168d_3_hw_phy_config(tp); |
5b538df9 | 4191 | break; |
e6de30d6 | 4192 | case RTL_GIGA_MAC_VER_28: |
4193 | rtl8168d_4_hw_phy_config(tp); | |
4194 | break; | |
5a5e4443 HW |
4195 | case RTL_GIGA_MAC_VER_29: |
4196 | case RTL_GIGA_MAC_VER_30: | |
4197 | rtl8105e_hw_phy_config(tp); | |
4198 | break; | |
cecb5fd7 FR |
4199 | case RTL_GIGA_MAC_VER_31: |
4200 | /* None. */ | |
4201 | break; | |
01dc7fec | 4202 | case RTL_GIGA_MAC_VER_32: |
01dc7fec | 4203 | case RTL_GIGA_MAC_VER_33: |
70090424 HW |
4204 | rtl8168e_1_hw_phy_config(tp); |
4205 | break; | |
4206 | case RTL_GIGA_MAC_VER_34: | |
4207 | rtl8168e_2_hw_phy_config(tp); | |
01dc7fec | 4208 | break; |
c2218925 HW |
4209 | case RTL_GIGA_MAC_VER_35: |
4210 | rtl8168f_1_hw_phy_config(tp); | |
4211 | break; | |
4212 | case RTL_GIGA_MAC_VER_36: | |
4213 | rtl8168f_2_hw_phy_config(tp); | |
4214 | break; | |
ef3386f0 | 4215 | |
7e18dca1 HW |
4216 | case RTL_GIGA_MAC_VER_37: |
4217 | rtl8402_hw_phy_config(tp); | |
4218 | break; | |
4219 | ||
b3d7b2f2 HW |
4220 | case RTL_GIGA_MAC_VER_38: |
4221 | rtl8411_hw_phy_config(tp); | |
4222 | break; | |
4223 | ||
5598bfe5 HW |
4224 | case RTL_GIGA_MAC_VER_39: |
4225 | rtl8106e_hw_phy_config(tp); | |
4226 | break; | |
4227 | ||
c558386b HW |
4228 | case RTL_GIGA_MAC_VER_40: |
4229 | rtl8168g_1_hw_phy_config(tp); | |
4230 | break; | |
57538c4a | 4231 | case RTL_GIGA_MAC_VER_42: |
58152cd4 | 4232 | case RTL_GIGA_MAC_VER_43: |
45dd95c4 | 4233 | case RTL_GIGA_MAC_VER_44: |
57538c4a | 4234 | rtl8168g_2_hw_phy_config(tp); |
4235 | break; | |
6e1d0b89 CHL |
4236 | case RTL_GIGA_MAC_VER_45: |
4237 | case RTL_GIGA_MAC_VER_47: | |
4238 | rtl8168h_1_hw_phy_config(tp); | |
4239 | break; | |
4240 | case RTL_GIGA_MAC_VER_46: | |
4241 | case RTL_GIGA_MAC_VER_48: | |
4242 | rtl8168h_2_hw_phy_config(tp); | |
4243 | break; | |
c558386b | 4244 | |
935e2218 CHL |
4245 | case RTL_GIGA_MAC_VER_49: |
4246 | rtl8168ep_1_hw_phy_config(tp); | |
4247 | break; | |
4248 | case RTL_GIGA_MAC_VER_50: | |
4249 | case RTL_GIGA_MAC_VER_51: | |
4250 | rtl8168ep_2_hw_phy_config(tp); | |
4251 | break; | |
4252 | ||
c558386b | 4253 | case RTL_GIGA_MAC_VER_41: |
5615d9f1 FR |
4254 | default: |
4255 | break; | |
4256 | } | |
4257 | } | |
4258 | ||
da78dbff | 4259 | static void rtl_phy_work(struct rtl8169_private *tp) |
1da177e4 | 4260 | { |
1da177e4 LT |
4261 | struct timer_list *timer = &tp->timer; |
4262 | void __iomem *ioaddr = tp->mmio_addr; | |
4263 | unsigned long timeout = RTL8169_PHY_TIMEOUT; | |
4264 | ||
bcf0bf90 | 4265 | assert(tp->mac_version > RTL_GIGA_MAC_VER_01); |
1da177e4 | 4266 | |
4da19633 | 4267 | if (tp->phy_reset_pending(tp)) { |
5b0384f4 | 4268 | /* |
1da177e4 LT |
4269 | * A busy loop could burn quite a few cycles on nowadays CPU. |
4270 | * Let's delay the execution of the timer for a few ticks. | |
4271 | */ | |
4272 | timeout = HZ/10; | |
4273 | goto out_mod_timer; | |
4274 | } | |
4275 | ||
4276 | if (tp->link_ok(ioaddr)) | |
da78dbff | 4277 | return; |
1da177e4 | 4278 | |
9bb8eeb5 | 4279 | netif_dbg(tp, link, tp->dev, "PHY reset until link up\n"); |
1da177e4 | 4280 | |
4da19633 | 4281 | tp->phy_reset_enable(tp); |
1da177e4 LT |
4282 | |
4283 | out_mod_timer: | |
4284 | mod_timer(timer, jiffies + timeout); | |
da78dbff FR |
4285 | } |
4286 | ||
4287 | static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag) | |
4288 | { | |
da78dbff FR |
4289 | if (!test_and_set_bit(flag, tp->wk.flags)) |
4290 | schedule_work(&tp->wk.work); | |
da78dbff FR |
4291 | } |
4292 | ||
4293 | static void rtl8169_phy_timer(unsigned long __opaque) | |
4294 | { | |
4295 | struct net_device *dev = (struct net_device *)__opaque; | |
4296 | struct rtl8169_private *tp = netdev_priv(dev); | |
4297 | ||
98ddf986 | 4298 | rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING); |
1da177e4 LT |
4299 | } |
4300 | ||
1da177e4 LT |
4301 | static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev, |
4302 | void __iomem *ioaddr) | |
4303 | { | |
4304 | iounmap(ioaddr); | |
4305 | pci_release_regions(pdev); | |
87aeec76 | 4306 | pci_clear_mwi(pdev); |
1da177e4 LT |
4307 | pci_disable_device(pdev); |
4308 | free_netdev(dev); | |
4309 | } | |
4310 | ||
ffc46952 FR |
4311 | DECLARE_RTL_COND(rtl_phy_reset_cond) |
4312 | { | |
4313 | return tp->phy_reset_pending(tp); | |
4314 | } | |
4315 | ||
bf793295 FR |
4316 | static void rtl8169_phy_reset(struct net_device *dev, |
4317 | struct rtl8169_private *tp) | |
4318 | { | |
4da19633 | 4319 | tp->phy_reset_enable(tp); |
ffc46952 | 4320 | rtl_msleep_loop_wait_low(tp, &rtl_phy_reset_cond, 1, 100); |
bf793295 FR |
4321 | } |
4322 | ||
2544bfc0 FR |
4323 | static bool rtl_tbi_enabled(struct rtl8169_private *tp) |
4324 | { | |
4325 | void __iomem *ioaddr = tp->mmio_addr; | |
4326 | ||
4327 | return (tp->mac_version == RTL_GIGA_MAC_VER_01) && | |
4328 | (RTL_R8(PHYstatus) & TBI_Enable); | |
4329 | } | |
4330 | ||
4ff96fa6 FR |
4331 | static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp) |
4332 | { | |
4333 | void __iomem *ioaddr = tp->mmio_addr; | |
4ff96fa6 | 4334 | |
5615d9f1 | 4335 | rtl_hw_phy_config(dev); |
4ff96fa6 | 4336 | |
77332894 MS |
4337 | if (tp->mac_version <= RTL_GIGA_MAC_VER_06) { |
4338 | dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n"); | |
4339 | RTL_W8(0x82, 0x01); | |
4340 | } | |
4ff96fa6 | 4341 | |
6dccd16b FR |
4342 | pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); |
4343 | ||
4344 | if (tp->mac_version <= RTL_GIGA_MAC_VER_06) | |
4345 | pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); | |
4ff96fa6 | 4346 | |
bcf0bf90 | 4347 | if (tp->mac_version == RTL_GIGA_MAC_VER_02) { |
4ff96fa6 FR |
4348 | dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n"); |
4349 | RTL_W8(0x82, 0x01); | |
4350 | dprintk("Set PHY Reg 0x0bh = 0x00h\n"); | |
4da19633 | 4351 | rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0 |
4ff96fa6 FR |
4352 | } |
4353 | ||
bf793295 FR |
4354 | rtl8169_phy_reset(dev, tp); |
4355 | ||
54405cde | 4356 | rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL, |
cecb5fd7 FR |
4357 | ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | |
4358 | ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | | |
4359 | (tp->mii.supports_gmii ? | |
4360 | ADVERTISED_1000baseT_Half | | |
4361 | ADVERTISED_1000baseT_Full : 0)); | |
4ff96fa6 | 4362 | |
2544bfc0 | 4363 | if (rtl_tbi_enabled(tp)) |
bf82c189 | 4364 | netif_info(tp, link, dev, "TBI auto-negotiating\n"); |
4ff96fa6 FR |
4365 | } |
4366 | ||
773d2021 FR |
4367 | static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr) |
4368 | { | |
4369 | void __iomem *ioaddr = tp->mmio_addr; | |
773d2021 | 4370 | |
da78dbff | 4371 | rtl_lock_work(tp); |
773d2021 FR |
4372 | |
4373 | RTL_W8(Cfg9346, Cfg9346_Unlock); | |
908ba2bf | 4374 | |
9ecb9aab | 4375 | RTL_W32(MAC4, addr[4] | addr[5] << 8); |
908ba2bf | 4376 | RTL_R32(MAC4); |
4377 | ||
9ecb9aab | 4378 | RTL_W32(MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24); |
908ba2bf | 4379 | RTL_R32(MAC0); |
4380 | ||
9ecb9aab | 4381 | if (tp->mac_version == RTL_GIGA_MAC_VER_34) |
4382 | rtl_rar_exgmac_set(tp, addr); | |
c28aa385 | 4383 | |
773d2021 FR |
4384 | RTL_W8(Cfg9346, Cfg9346_Lock); |
4385 | ||
da78dbff | 4386 | rtl_unlock_work(tp); |
773d2021 FR |
4387 | } |
4388 | ||
4389 | static int rtl_set_mac_address(struct net_device *dev, void *p) | |
4390 | { | |
4391 | struct rtl8169_private *tp = netdev_priv(dev); | |
4392 | struct sockaddr *addr = p; | |
4393 | ||
4394 | if (!is_valid_ether_addr(addr->sa_data)) | |
4395 | return -EADDRNOTAVAIL; | |
4396 | ||
4397 | memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); | |
4398 | ||
4399 | rtl_rar_set(tp, dev->dev_addr); | |
4400 | ||
4401 | return 0; | |
4402 | } | |
4403 | ||
5f787a1a FR |
4404 | static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
4405 | { | |
4406 | struct rtl8169_private *tp = netdev_priv(dev); | |
4407 | struct mii_ioctl_data *data = if_mii(ifr); | |
4408 | ||
8b4ab28d FR |
4409 | return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV; |
4410 | } | |
5f787a1a | 4411 | |
cecb5fd7 FR |
4412 | static int rtl_xmii_ioctl(struct rtl8169_private *tp, |
4413 | struct mii_ioctl_data *data, int cmd) | |
8b4ab28d | 4414 | { |
5f787a1a FR |
4415 | switch (cmd) { |
4416 | case SIOCGMIIPHY: | |
4417 | data->phy_id = 32; /* Internal PHY */ | |
4418 | return 0; | |
4419 | ||
4420 | case SIOCGMIIREG: | |
4da19633 | 4421 | data->val_out = rtl_readphy(tp, data->reg_num & 0x1f); |
5f787a1a FR |
4422 | return 0; |
4423 | ||
4424 | case SIOCSMIIREG: | |
4da19633 | 4425 | rtl_writephy(tp, data->reg_num & 0x1f, data->val_in); |
5f787a1a FR |
4426 | return 0; |
4427 | } | |
4428 | return -EOPNOTSUPP; | |
4429 | } | |
4430 | ||
8b4ab28d FR |
4431 | static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd) |
4432 | { | |
4433 | return -EOPNOTSUPP; | |
4434 | } | |
4435 | ||
fbac58fc FR |
4436 | static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp) |
4437 | { | |
4438 | if (tp->features & RTL_FEATURE_MSI) { | |
4439 | pci_disable_msi(pdev); | |
4440 | tp->features &= ~RTL_FEATURE_MSI; | |
4441 | } | |
4442 | } | |
4443 | ||
baf63293 | 4444 | static void rtl_init_mdio_ops(struct rtl8169_private *tp) |
c0e45c1c | 4445 | { |
4446 | struct mdio_ops *ops = &tp->mdio_ops; | |
4447 | ||
4448 | switch (tp->mac_version) { | |
4449 | case RTL_GIGA_MAC_VER_27: | |
4450 | ops->write = r8168dp_1_mdio_write; | |
4451 | ops->read = r8168dp_1_mdio_read; | |
4452 | break; | |
e6de30d6 | 4453 | case RTL_GIGA_MAC_VER_28: |
4804b3b3 | 4454 | case RTL_GIGA_MAC_VER_31: |
e6de30d6 | 4455 | ops->write = r8168dp_2_mdio_write; |
4456 | ops->read = r8168dp_2_mdio_read; | |
4457 | break; | |
c558386b HW |
4458 | case RTL_GIGA_MAC_VER_40: |
4459 | case RTL_GIGA_MAC_VER_41: | |
57538c4a | 4460 | case RTL_GIGA_MAC_VER_42: |
58152cd4 | 4461 | case RTL_GIGA_MAC_VER_43: |
45dd95c4 | 4462 | case RTL_GIGA_MAC_VER_44: |
6e1d0b89 CHL |
4463 | case RTL_GIGA_MAC_VER_45: |
4464 | case RTL_GIGA_MAC_VER_46: | |
4465 | case RTL_GIGA_MAC_VER_47: | |
4466 | case RTL_GIGA_MAC_VER_48: | |
935e2218 CHL |
4467 | case RTL_GIGA_MAC_VER_49: |
4468 | case RTL_GIGA_MAC_VER_50: | |
4469 | case RTL_GIGA_MAC_VER_51: | |
c558386b HW |
4470 | ops->write = r8168g_mdio_write; |
4471 | ops->read = r8168g_mdio_read; | |
4472 | break; | |
c0e45c1c | 4473 | default: |
4474 | ops->write = r8169_mdio_write; | |
4475 | ops->read = r8169_mdio_read; | |
4476 | break; | |
4477 | } | |
4478 | } | |
4479 | ||
e2409d83 | 4480 | static void rtl_speed_down(struct rtl8169_private *tp) |
4481 | { | |
4482 | u32 adv; | |
4483 | int lpa; | |
4484 | ||
4485 | rtl_writephy(tp, 0x1f, 0x0000); | |
4486 | lpa = rtl_readphy(tp, MII_LPA); | |
4487 | ||
4488 | if (lpa & (LPA_10HALF | LPA_10FULL)) | |
4489 | adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full; | |
4490 | else if (lpa & (LPA_100HALF | LPA_100FULL)) | |
4491 | adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | | |
4492 | ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full; | |
4493 | else | |
4494 | adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | | |
4495 | ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | | |
4496 | (tp->mii.supports_gmii ? | |
4497 | ADVERTISED_1000baseT_Half | | |
4498 | ADVERTISED_1000baseT_Full : 0); | |
4499 | ||
4500 | rtl8169_set_speed(tp->dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL, | |
4501 | adv); | |
4502 | } | |
4503 | ||
649b3b8c | 4504 | static void rtl_wol_suspend_quirk(struct rtl8169_private *tp) |
4505 | { | |
4506 | void __iomem *ioaddr = tp->mmio_addr; | |
4507 | ||
4508 | switch (tp->mac_version) { | |
b00e69de CB |
4509 | case RTL_GIGA_MAC_VER_25: |
4510 | case RTL_GIGA_MAC_VER_26: | |
649b3b8c | 4511 | case RTL_GIGA_MAC_VER_29: |
4512 | case RTL_GIGA_MAC_VER_30: | |
4513 | case RTL_GIGA_MAC_VER_32: | |
4514 | case RTL_GIGA_MAC_VER_33: | |
4515 | case RTL_GIGA_MAC_VER_34: | |
7e18dca1 | 4516 | case RTL_GIGA_MAC_VER_37: |
b3d7b2f2 | 4517 | case RTL_GIGA_MAC_VER_38: |
5598bfe5 | 4518 | case RTL_GIGA_MAC_VER_39: |
c558386b HW |
4519 | case RTL_GIGA_MAC_VER_40: |
4520 | case RTL_GIGA_MAC_VER_41: | |
57538c4a | 4521 | case RTL_GIGA_MAC_VER_42: |
58152cd4 | 4522 | case RTL_GIGA_MAC_VER_43: |
45dd95c4 | 4523 | case RTL_GIGA_MAC_VER_44: |
6e1d0b89 CHL |
4524 | case RTL_GIGA_MAC_VER_45: |
4525 | case RTL_GIGA_MAC_VER_46: | |
4526 | case RTL_GIGA_MAC_VER_47: | |
4527 | case RTL_GIGA_MAC_VER_48: | |
935e2218 CHL |
4528 | case RTL_GIGA_MAC_VER_49: |
4529 | case RTL_GIGA_MAC_VER_50: | |
4530 | case RTL_GIGA_MAC_VER_51: | |
649b3b8c | 4531 | RTL_W32(RxConfig, RTL_R32(RxConfig) | |
4532 | AcceptBroadcast | AcceptMulticast | AcceptMyPhys); | |
4533 | break; | |
4534 | default: | |
4535 | break; | |
4536 | } | |
4537 | } | |
4538 | ||
4539 | static bool rtl_wol_pll_power_down(struct rtl8169_private *tp) | |
4540 | { | |
4541 | if (!(__rtl8169_get_wol(tp) & WAKE_ANY)) | |
4542 | return false; | |
4543 | ||
e2409d83 | 4544 | rtl_speed_down(tp); |
649b3b8c | 4545 | rtl_wol_suspend_quirk(tp); |
4546 | ||
4547 | return true; | |
4548 | } | |
4549 | ||
065c27c1 | 4550 | static void r810x_phy_power_down(struct rtl8169_private *tp) |
4551 | { | |
4552 | rtl_writephy(tp, 0x1f, 0x0000); | |
4553 | rtl_writephy(tp, MII_BMCR, BMCR_PDOWN); | |
4554 | } | |
4555 | ||
4556 | static void r810x_phy_power_up(struct rtl8169_private *tp) | |
4557 | { | |
4558 | rtl_writephy(tp, 0x1f, 0x0000); | |
4559 | rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE); | |
4560 | } | |
4561 | ||
4562 | static void r810x_pll_power_down(struct rtl8169_private *tp) | |
4563 | { | |
0004299a HW |
4564 | void __iomem *ioaddr = tp->mmio_addr; |
4565 | ||
649b3b8c | 4566 | if (rtl_wol_pll_power_down(tp)) |
065c27c1 | 4567 | return; |
065c27c1 | 4568 | |
4569 | r810x_phy_power_down(tp); | |
0004299a HW |
4570 | |
4571 | switch (tp->mac_version) { | |
4572 | case RTL_GIGA_MAC_VER_07: | |
4573 | case RTL_GIGA_MAC_VER_08: | |
4574 | case RTL_GIGA_MAC_VER_09: | |
4575 | case RTL_GIGA_MAC_VER_10: | |
4576 | case RTL_GIGA_MAC_VER_13: | |
4577 | case RTL_GIGA_MAC_VER_16: | |
4578 | break; | |
4579 | default: | |
4580 | RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80); | |
4581 | break; | |
4582 | } | |
065c27c1 | 4583 | } |
4584 | ||
4585 | static void r810x_pll_power_up(struct rtl8169_private *tp) | |
4586 | { | |
0004299a HW |
4587 | void __iomem *ioaddr = tp->mmio_addr; |
4588 | ||
065c27c1 | 4589 | r810x_phy_power_up(tp); |
0004299a HW |
4590 | |
4591 | switch (tp->mac_version) { | |
4592 | case RTL_GIGA_MAC_VER_07: | |
4593 | case RTL_GIGA_MAC_VER_08: | |
4594 | case RTL_GIGA_MAC_VER_09: | |
4595 | case RTL_GIGA_MAC_VER_10: | |
4596 | case RTL_GIGA_MAC_VER_13: | |
4597 | case RTL_GIGA_MAC_VER_16: | |
4598 | break; | |
6e1d0b89 CHL |
4599 | case RTL_GIGA_MAC_VER_47: |
4600 | case RTL_GIGA_MAC_VER_48: | |
05b9687b | 4601 | RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0); |
6e1d0b89 | 4602 | break; |
0004299a HW |
4603 | default: |
4604 | RTL_W8(PMCH, RTL_R8(PMCH) | 0x80); | |
4605 | break; | |
4606 | } | |
065c27c1 | 4607 | } |
4608 | ||
4609 | static void r8168_phy_power_up(struct rtl8169_private *tp) | |
4610 | { | |
4611 | rtl_writephy(tp, 0x1f, 0x0000); | |
01dc7fec | 4612 | switch (tp->mac_version) { |
4613 | case RTL_GIGA_MAC_VER_11: | |
4614 | case RTL_GIGA_MAC_VER_12: | |
4615 | case RTL_GIGA_MAC_VER_17: | |
4616 | case RTL_GIGA_MAC_VER_18: | |
4617 | case RTL_GIGA_MAC_VER_19: | |
4618 | case RTL_GIGA_MAC_VER_20: | |
4619 | case RTL_GIGA_MAC_VER_21: | |
4620 | case RTL_GIGA_MAC_VER_22: | |
4621 | case RTL_GIGA_MAC_VER_23: | |
4622 | case RTL_GIGA_MAC_VER_24: | |
4623 | case RTL_GIGA_MAC_VER_25: | |
4624 | case RTL_GIGA_MAC_VER_26: | |
4625 | case RTL_GIGA_MAC_VER_27: | |
4626 | case RTL_GIGA_MAC_VER_28: | |
4627 | case RTL_GIGA_MAC_VER_31: | |
4628 | rtl_writephy(tp, 0x0e, 0x0000); | |
4629 | break; | |
4630 | default: | |
4631 | break; | |
4632 | } | |
065c27c1 | 4633 | rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE); |
4634 | } | |
4635 | ||
4636 | static void r8168_phy_power_down(struct rtl8169_private *tp) | |
4637 | { | |
4638 | rtl_writephy(tp, 0x1f, 0x0000); | |
01dc7fec | 4639 | switch (tp->mac_version) { |
4640 | case RTL_GIGA_MAC_VER_32: | |
4641 | case RTL_GIGA_MAC_VER_33: | |
beb330a4 | 4642 | case RTL_GIGA_MAC_VER_40: |
4643 | case RTL_GIGA_MAC_VER_41: | |
01dc7fec | 4644 | rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN); |
4645 | break; | |
4646 | ||
4647 | case RTL_GIGA_MAC_VER_11: | |
4648 | case RTL_GIGA_MAC_VER_12: | |
4649 | case RTL_GIGA_MAC_VER_17: | |
4650 | case RTL_GIGA_MAC_VER_18: | |
4651 | case RTL_GIGA_MAC_VER_19: | |
4652 | case RTL_GIGA_MAC_VER_20: | |
4653 | case RTL_GIGA_MAC_VER_21: | |
4654 | case RTL_GIGA_MAC_VER_22: | |
4655 | case RTL_GIGA_MAC_VER_23: | |
4656 | case RTL_GIGA_MAC_VER_24: | |
4657 | case RTL_GIGA_MAC_VER_25: | |
4658 | case RTL_GIGA_MAC_VER_26: | |
4659 | case RTL_GIGA_MAC_VER_27: | |
4660 | case RTL_GIGA_MAC_VER_28: | |
4661 | case RTL_GIGA_MAC_VER_31: | |
4662 | rtl_writephy(tp, 0x0e, 0x0200); | |
4663 | default: | |
4664 | rtl_writephy(tp, MII_BMCR, BMCR_PDOWN); | |
4665 | break; | |
4666 | } | |
065c27c1 | 4667 | } |
4668 | ||
4669 | static void r8168_pll_power_down(struct rtl8169_private *tp) | |
4670 | { | |
4671 | void __iomem *ioaddr = tp->mmio_addr; | |
4672 | ||
cecb5fd7 FR |
4673 | if ((tp->mac_version == RTL_GIGA_MAC_VER_27 || |
4674 | tp->mac_version == RTL_GIGA_MAC_VER_28 || | |
935e2218 CHL |
4675 | tp->mac_version == RTL_GIGA_MAC_VER_31 || |
4676 | tp->mac_version == RTL_GIGA_MAC_VER_49 || | |
4677 | tp->mac_version == RTL_GIGA_MAC_VER_50 || | |
4678 | tp->mac_version == RTL_GIGA_MAC_VER_51) && | |
2f8c040c | 4679 | r8168_check_dash(tp)) { |
065c27c1 | 4680 | return; |
5d2e1957 | 4681 | } |
065c27c1 | 4682 | |
cecb5fd7 FR |
4683 | if ((tp->mac_version == RTL_GIGA_MAC_VER_23 || |
4684 | tp->mac_version == RTL_GIGA_MAC_VER_24) && | |
065c27c1 | 4685 | (RTL_R16(CPlusCmd) & ASF)) { |
4686 | return; | |
4687 | } | |
4688 | ||
01dc7fec | 4689 | if (tp->mac_version == RTL_GIGA_MAC_VER_32 || |
4690 | tp->mac_version == RTL_GIGA_MAC_VER_33) | |
fdf6fc06 | 4691 | rtl_ephy_write(tp, 0x19, 0xff64); |
01dc7fec | 4692 | |
649b3b8c | 4693 | if (rtl_wol_pll_power_down(tp)) |
065c27c1 | 4694 | return; |
065c27c1 | 4695 | |
4696 | r8168_phy_power_down(tp); | |
4697 | ||
4698 | switch (tp->mac_version) { | |
4699 | case RTL_GIGA_MAC_VER_25: | |
4700 | case RTL_GIGA_MAC_VER_26: | |
5d2e1957 HW |
4701 | case RTL_GIGA_MAC_VER_27: |
4702 | case RTL_GIGA_MAC_VER_28: | |
4804b3b3 | 4703 | case RTL_GIGA_MAC_VER_31: |
01dc7fec | 4704 | case RTL_GIGA_MAC_VER_32: |
4705 | case RTL_GIGA_MAC_VER_33: | |
42fde737 | 4706 | case RTL_GIGA_MAC_VER_44: |
6e1d0b89 CHL |
4707 | case RTL_GIGA_MAC_VER_45: |
4708 | case RTL_GIGA_MAC_VER_46: | |
935e2218 CHL |
4709 | case RTL_GIGA_MAC_VER_50: |
4710 | case RTL_GIGA_MAC_VER_51: | |
065c27c1 | 4711 | RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80); |
4712 | break; | |
beb330a4 | 4713 | case RTL_GIGA_MAC_VER_40: |
4714 | case RTL_GIGA_MAC_VER_41: | |
935e2218 | 4715 | case RTL_GIGA_MAC_VER_49: |
706123d0 | 4716 | rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000, |
beb330a4 | 4717 | 0xfc000000, ERIAR_EXGMAC); |
b8e5e6ad | 4718 | RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80); |
beb330a4 | 4719 | break; |
065c27c1 | 4720 | } |
4721 | } | |
4722 | ||
4723 | static void r8168_pll_power_up(struct rtl8169_private *tp) | |
4724 | { | |
4725 | void __iomem *ioaddr = tp->mmio_addr; | |
4726 | ||
065c27c1 | 4727 | switch (tp->mac_version) { |
4728 | case RTL_GIGA_MAC_VER_25: | |
4729 | case RTL_GIGA_MAC_VER_26: | |
5d2e1957 HW |
4730 | case RTL_GIGA_MAC_VER_27: |
4731 | case RTL_GIGA_MAC_VER_28: | |
4804b3b3 | 4732 | case RTL_GIGA_MAC_VER_31: |
01dc7fec | 4733 | case RTL_GIGA_MAC_VER_32: |
4734 | case RTL_GIGA_MAC_VER_33: | |
065c27c1 | 4735 | RTL_W8(PMCH, RTL_R8(PMCH) | 0x80); |
4736 | break; | |
42fde737 | 4737 | case RTL_GIGA_MAC_VER_44: |
6e1d0b89 CHL |
4738 | case RTL_GIGA_MAC_VER_45: |
4739 | case RTL_GIGA_MAC_VER_46: | |
935e2218 CHL |
4740 | case RTL_GIGA_MAC_VER_50: |
4741 | case RTL_GIGA_MAC_VER_51: | |
05b9687b | 4742 | RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0); |
6e1d0b89 | 4743 | break; |
beb330a4 | 4744 | case RTL_GIGA_MAC_VER_40: |
4745 | case RTL_GIGA_MAC_VER_41: | |
935e2218 | 4746 | case RTL_GIGA_MAC_VER_49: |
b8e5e6ad | 4747 | RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0); |
706123d0 | 4748 | rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000, |
beb330a4 | 4749 | 0x00000000, ERIAR_EXGMAC); |
4750 | break; | |
065c27c1 | 4751 | } |
4752 | ||
4753 | r8168_phy_power_up(tp); | |
4754 | } | |
4755 | ||
d58d46b5 FR |
4756 | static void rtl_generic_op(struct rtl8169_private *tp, |
4757 | void (*op)(struct rtl8169_private *)) | |
065c27c1 | 4758 | { |
4759 | if (op) | |
4760 | op(tp); | |
4761 | } | |
4762 | ||
4763 | static void rtl_pll_power_down(struct rtl8169_private *tp) | |
4764 | { | |
d58d46b5 | 4765 | rtl_generic_op(tp, tp->pll_power_ops.down); |
065c27c1 | 4766 | } |
4767 | ||
4768 | static void rtl_pll_power_up(struct rtl8169_private *tp) | |
4769 | { | |
d58d46b5 | 4770 | rtl_generic_op(tp, tp->pll_power_ops.up); |
065c27c1 | 4771 | } |
4772 | ||
baf63293 | 4773 | static void rtl_init_pll_power_ops(struct rtl8169_private *tp) |
065c27c1 | 4774 | { |
4775 | struct pll_power_ops *ops = &tp->pll_power_ops; | |
4776 | ||
4777 | switch (tp->mac_version) { | |
4778 | case RTL_GIGA_MAC_VER_07: | |
4779 | case RTL_GIGA_MAC_VER_08: | |
4780 | case RTL_GIGA_MAC_VER_09: | |
4781 | case RTL_GIGA_MAC_VER_10: | |
4782 | case RTL_GIGA_MAC_VER_16: | |
5a5e4443 HW |
4783 | case RTL_GIGA_MAC_VER_29: |
4784 | case RTL_GIGA_MAC_VER_30: | |
7e18dca1 | 4785 | case RTL_GIGA_MAC_VER_37: |
5598bfe5 | 4786 | case RTL_GIGA_MAC_VER_39: |
58152cd4 | 4787 | case RTL_GIGA_MAC_VER_43: |
6e1d0b89 CHL |
4788 | case RTL_GIGA_MAC_VER_47: |
4789 | case RTL_GIGA_MAC_VER_48: | |
065c27c1 | 4790 | ops->down = r810x_pll_power_down; |
4791 | ops->up = r810x_pll_power_up; | |
4792 | break; | |
4793 | ||
4794 | case RTL_GIGA_MAC_VER_11: | |
4795 | case RTL_GIGA_MAC_VER_12: | |
4796 | case RTL_GIGA_MAC_VER_17: | |
4797 | case RTL_GIGA_MAC_VER_18: | |
4798 | case RTL_GIGA_MAC_VER_19: | |
4799 | case RTL_GIGA_MAC_VER_20: | |
4800 | case RTL_GIGA_MAC_VER_21: | |
4801 | case RTL_GIGA_MAC_VER_22: | |
4802 | case RTL_GIGA_MAC_VER_23: | |
4803 | case RTL_GIGA_MAC_VER_24: | |
4804 | case RTL_GIGA_MAC_VER_25: | |
4805 | case RTL_GIGA_MAC_VER_26: | |
4806 | case RTL_GIGA_MAC_VER_27: | |
e6de30d6 | 4807 | case RTL_GIGA_MAC_VER_28: |
4804b3b3 | 4808 | case RTL_GIGA_MAC_VER_31: |
01dc7fec | 4809 | case RTL_GIGA_MAC_VER_32: |
4810 | case RTL_GIGA_MAC_VER_33: | |
70090424 | 4811 | case RTL_GIGA_MAC_VER_34: |
c2218925 HW |
4812 | case RTL_GIGA_MAC_VER_35: |
4813 | case RTL_GIGA_MAC_VER_36: | |
b3d7b2f2 | 4814 | case RTL_GIGA_MAC_VER_38: |
c558386b HW |
4815 | case RTL_GIGA_MAC_VER_40: |
4816 | case RTL_GIGA_MAC_VER_41: | |
57538c4a | 4817 | case RTL_GIGA_MAC_VER_42: |
45dd95c4 | 4818 | case RTL_GIGA_MAC_VER_44: |
6e1d0b89 CHL |
4819 | case RTL_GIGA_MAC_VER_45: |
4820 | case RTL_GIGA_MAC_VER_46: | |
935e2218 CHL |
4821 | case RTL_GIGA_MAC_VER_49: |
4822 | case RTL_GIGA_MAC_VER_50: | |
4823 | case RTL_GIGA_MAC_VER_51: | |
065c27c1 | 4824 | ops->down = r8168_pll_power_down; |
4825 | ops->up = r8168_pll_power_up; | |
4826 | break; | |
4827 | ||
4828 | default: | |
4829 | ops->down = NULL; | |
4830 | ops->up = NULL; | |
4831 | break; | |
4832 | } | |
4833 | } | |
4834 | ||
e542a226 HW |
4835 | static void rtl_init_rxcfg(struct rtl8169_private *tp) |
4836 | { | |
4837 | void __iomem *ioaddr = tp->mmio_addr; | |
4838 | ||
4839 | switch (tp->mac_version) { | |
4840 | case RTL_GIGA_MAC_VER_01: | |
4841 | case RTL_GIGA_MAC_VER_02: | |
4842 | case RTL_GIGA_MAC_VER_03: | |
4843 | case RTL_GIGA_MAC_VER_04: | |
4844 | case RTL_GIGA_MAC_VER_05: | |
4845 | case RTL_GIGA_MAC_VER_06: | |
4846 | case RTL_GIGA_MAC_VER_10: | |
4847 | case RTL_GIGA_MAC_VER_11: | |
4848 | case RTL_GIGA_MAC_VER_12: | |
4849 | case RTL_GIGA_MAC_VER_13: | |
4850 | case RTL_GIGA_MAC_VER_14: | |
4851 | case RTL_GIGA_MAC_VER_15: | |
4852 | case RTL_GIGA_MAC_VER_16: | |
4853 | case RTL_GIGA_MAC_VER_17: | |
4854 | RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST); | |
4855 | break; | |
4856 | case RTL_GIGA_MAC_VER_18: | |
4857 | case RTL_GIGA_MAC_VER_19: | |
4858 | case RTL_GIGA_MAC_VER_20: | |
4859 | case RTL_GIGA_MAC_VER_21: | |
4860 | case RTL_GIGA_MAC_VER_22: | |
4861 | case RTL_GIGA_MAC_VER_23: | |
4862 | case RTL_GIGA_MAC_VER_24: | |
eb2dc35d | 4863 | case RTL_GIGA_MAC_VER_34: |
3ced8c95 | 4864 | case RTL_GIGA_MAC_VER_35: |
e542a226 HW |
4865 | RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST); |
4866 | break; | |
beb330a4 | 4867 | case RTL_GIGA_MAC_VER_40: |
7a9810e7 MD |
4868 | RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF); |
4869 | break; | |
beb330a4 | 4870 | case RTL_GIGA_MAC_VER_41: |
57538c4a | 4871 | case RTL_GIGA_MAC_VER_42: |
58152cd4 | 4872 | case RTL_GIGA_MAC_VER_43: |
45dd95c4 | 4873 | case RTL_GIGA_MAC_VER_44: |
6e1d0b89 CHL |
4874 | case RTL_GIGA_MAC_VER_45: |
4875 | case RTL_GIGA_MAC_VER_46: | |
4876 | case RTL_GIGA_MAC_VER_47: | |
4877 | case RTL_GIGA_MAC_VER_48: | |
935e2218 CHL |
4878 | case RTL_GIGA_MAC_VER_49: |
4879 | case RTL_GIGA_MAC_VER_50: | |
4880 | case RTL_GIGA_MAC_VER_51: | |
beb330a4 | 4881 | RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST | RX_EARLY_OFF); |
4882 | break; | |
e542a226 HW |
4883 | default: |
4884 | RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST); | |
4885 | break; | |
4886 | } | |
4887 | } | |
4888 | ||
92fc43b4 HW |
4889 | static void rtl8169_init_ring_indexes(struct rtl8169_private *tp) |
4890 | { | |
9fba0812 | 4891 | tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0; |
92fc43b4 HW |
4892 | } |
4893 | ||
d58d46b5 FR |
4894 | static void rtl_hw_jumbo_enable(struct rtl8169_private *tp) |
4895 | { | |
9c5028e9 | 4896 | void __iomem *ioaddr = tp->mmio_addr; |
4897 | ||
4898 | RTL_W8(Cfg9346, Cfg9346_Unlock); | |
d58d46b5 | 4899 | rtl_generic_op(tp, tp->jumbo_ops.enable); |
9c5028e9 | 4900 | RTL_W8(Cfg9346, Cfg9346_Lock); |
d58d46b5 FR |
4901 | } |
4902 | ||
4903 | static void rtl_hw_jumbo_disable(struct rtl8169_private *tp) | |
4904 | { | |
9c5028e9 | 4905 | void __iomem *ioaddr = tp->mmio_addr; |
4906 | ||
4907 | RTL_W8(Cfg9346, Cfg9346_Unlock); | |
d58d46b5 | 4908 | rtl_generic_op(tp, tp->jumbo_ops.disable); |
9c5028e9 | 4909 | RTL_W8(Cfg9346, Cfg9346_Lock); |
d58d46b5 FR |
4910 | } |
4911 | ||
4912 | static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp) | |
4913 | { | |
4914 | void __iomem *ioaddr = tp->mmio_addr; | |
4915 | ||
4916 | RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0); | |
4917 | RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1); | |
4918 | rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT); | |
4919 | } | |
4920 | ||
4921 | static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp) | |
4922 | { | |
4923 | void __iomem *ioaddr = tp->mmio_addr; | |
4924 | ||
4925 | RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0); | |
4926 | RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1); | |
4927 | rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
4928 | } | |
4929 | ||
4930 | static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp) | |
4931 | { | |
4932 | void __iomem *ioaddr = tp->mmio_addr; | |
4933 | ||
4934 | RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0); | |
4935 | } | |
4936 | ||
4937 | static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp) | |
4938 | { | |
4939 | void __iomem *ioaddr = tp->mmio_addr; | |
4940 | ||
4941 | RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0); | |
4942 | } | |
4943 | ||
4944 | static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp) | |
4945 | { | |
4946 | void __iomem *ioaddr = tp->mmio_addr; | |
d58d46b5 FR |
4947 | |
4948 | RTL_W8(MaxTxPacketSize, 0x3f); | |
4949 | RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0); | |
4950 | RTL_W8(Config4, RTL_R8(Config4) | 0x01); | |
4512ff9f | 4951 | rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT); |
d58d46b5 FR |
4952 | } |
4953 | ||
4954 | static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp) | |
4955 | { | |
4956 | void __iomem *ioaddr = tp->mmio_addr; | |
d58d46b5 FR |
4957 | |
4958 | RTL_W8(MaxTxPacketSize, 0x0c); | |
4959 | RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0); | |
4960 | RTL_W8(Config4, RTL_R8(Config4) & ~0x01); | |
4512ff9f | 4961 | rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT); |
d58d46b5 FR |
4962 | } |
4963 | ||
4964 | static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp) | |
4965 | { | |
4966 | rtl_tx_performance_tweak(tp->pci_dev, | |
4967 | (0x2 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN); | |
4968 | } | |
4969 | ||
4970 | static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp) | |
4971 | { | |
4972 | rtl_tx_performance_tweak(tp->pci_dev, | |
4973 | (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN); | |
4974 | } | |
4975 | ||
4976 | static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp) | |
4977 | { | |
4978 | void __iomem *ioaddr = tp->mmio_addr; | |
4979 | ||
4980 | r8168b_0_hw_jumbo_enable(tp); | |
4981 | ||
4982 | RTL_W8(Config4, RTL_R8(Config4) | (1 << 0)); | |
4983 | } | |
4984 | ||
4985 | static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp) | |
4986 | { | |
4987 | void __iomem *ioaddr = tp->mmio_addr; | |
4988 | ||
4989 | r8168b_0_hw_jumbo_disable(tp); | |
4990 | ||
4991 | RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0)); | |
4992 | } | |
4993 | ||
baf63293 | 4994 | static void rtl_init_jumbo_ops(struct rtl8169_private *tp) |
d58d46b5 FR |
4995 | { |
4996 | struct jumbo_ops *ops = &tp->jumbo_ops; | |
4997 | ||
4998 | switch (tp->mac_version) { | |
4999 | case RTL_GIGA_MAC_VER_11: | |
5000 | ops->disable = r8168b_0_hw_jumbo_disable; | |
5001 | ops->enable = r8168b_0_hw_jumbo_enable; | |
5002 | break; | |
5003 | case RTL_GIGA_MAC_VER_12: | |
5004 | case RTL_GIGA_MAC_VER_17: | |
5005 | ops->disable = r8168b_1_hw_jumbo_disable; | |
5006 | ops->enable = r8168b_1_hw_jumbo_enable; | |
5007 | break; | |
5008 | case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */ | |
5009 | case RTL_GIGA_MAC_VER_19: | |
5010 | case RTL_GIGA_MAC_VER_20: | |
5011 | case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */ | |
5012 | case RTL_GIGA_MAC_VER_22: | |
5013 | case RTL_GIGA_MAC_VER_23: | |
5014 | case RTL_GIGA_MAC_VER_24: | |
5015 | case RTL_GIGA_MAC_VER_25: | |
5016 | case RTL_GIGA_MAC_VER_26: | |
5017 | ops->disable = r8168c_hw_jumbo_disable; | |
5018 | ops->enable = r8168c_hw_jumbo_enable; | |
5019 | break; | |
5020 | case RTL_GIGA_MAC_VER_27: | |
5021 | case RTL_GIGA_MAC_VER_28: | |
5022 | ops->disable = r8168dp_hw_jumbo_disable; | |
5023 | ops->enable = r8168dp_hw_jumbo_enable; | |
5024 | break; | |
5025 | case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */ | |
5026 | case RTL_GIGA_MAC_VER_32: | |
5027 | case RTL_GIGA_MAC_VER_33: | |
5028 | case RTL_GIGA_MAC_VER_34: | |
5029 | ops->disable = r8168e_hw_jumbo_disable; | |
5030 | ops->enable = r8168e_hw_jumbo_enable; | |
5031 | break; | |
5032 | ||
5033 | /* | |
5034 | * No action needed for jumbo frames with 8169. | |
5035 | * No jumbo for 810x at all. | |
5036 | */ | |
c558386b HW |
5037 | case RTL_GIGA_MAC_VER_40: |
5038 | case RTL_GIGA_MAC_VER_41: | |
57538c4a | 5039 | case RTL_GIGA_MAC_VER_42: |
58152cd4 | 5040 | case RTL_GIGA_MAC_VER_43: |
45dd95c4 | 5041 | case RTL_GIGA_MAC_VER_44: |
6e1d0b89 CHL |
5042 | case RTL_GIGA_MAC_VER_45: |
5043 | case RTL_GIGA_MAC_VER_46: | |
5044 | case RTL_GIGA_MAC_VER_47: | |
5045 | case RTL_GIGA_MAC_VER_48: | |
935e2218 CHL |
5046 | case RTL_GIGA_MAC_VER_49: |
5047 | case RTL_GIGA_MAC_VER_50: | |
5048 | case RTL_GIGA_MAC_VER_51: | |
d58d46b5 FR |
5049 | default: |
5050 | ops->disable = NULL; | |
5051 | ops->enable = NULL; | |
5052 | break; | |
5053 | } | |
5054 | } | |
5055 | ||
ffc46952 FR |
5056 | DECLARE_RTL_COND(rtl_chipcmd_cond) |
5057 | { | |
5058 | void __iomem *ioaddr = tp->mmio_addr; | |
5059 | ||
5060 | return RTL_R8(ChipCmd) & CmdReset; | |
5061 | } | |
5062 | ||
6f43adc8 FR |
5063 | static void rtl_hw_reset(struct rtl8169_private *tp) |
5064 | { | |
5065 | void __iomem *ioaddr = tp->mmio_addr; | |
6f43adc8 | 5066 | |
6f43adc8 FR |
5067 | RTL_W8(ChipCmd, CmdReset); |
5068 | ||
ffc46952 | 5069 | rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100); |
1e918876 FW |
5070 | |
5071 | netdev_reset_queue(tp->dev); | |
6f43adc8 FR |
5072 | } |
5073 | ||
b6ffd97f | 5074 | static void rtl_request_uncached_firmware(struct rtl8169_private *tp) |
953a12cc | 5075 | { |
b6ffd97f FR |
5076 | struct rtl_fw *rtl_fw; |
5077 | const char *name; | |
5078 | int rc = -ENOMEM; | |
953a12cc | 5079 | |
b6ffd97f FR |
5080 | name = rtl_lookup_firmware_name(tp); |
5081 | if (!name) | |
5082 | goto out_no_firmware; | |
953a12cc | 5083 | |
b6ffd97f FR |
5084 | rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL); |
5085 | if (!rtl_fw) | |
5086 | goto err_warn; | |
31bd204f | 5087 | |
b6ffd97f FR |
5088 | rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev); |
5089 | if (rc < 0) | |
5090 | goto err_free; | |
5091 | ||
fd112f2e FR |
5092 | rc = rtl_check_firmware(tp, rtl_fw); |
5093 | if (rc < 0) | |
5094 | goto err_release_firmware; | |
5095 | ||
b6ffd97f FR |
5096 | tp->rtl_fw = rtl_fw; |
5097 | out: | |
5098 | return; | |
5099 | ||
fd112f2e FR |
5100 | err_release_firmware: |
5101 | release_firmware(rtl_fw->fw); | |
b6ffd97f FR |
5102 | err_free: |
5103 | kfree(rtl_fw); | |
5104 | err_warn: | |
5105 | netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n", | |
5106 | name, rc); | |
5107 | out_no_firmware: | |
5108 | tp->rtl_fw = NULL; | |
5109 | goto out; | |
5110 | } | |
5111 | ||
5112 | static void rtl_request_firmware(struct rtl8169_private *tp) | |
5113 | { | |
5114 | if (IS_ERR(tp->rtl_fw)) | |
5115 | rtl_request_uncached_firmware(tp); | |
953a12cc FR |
5116 | } |
5117 | ||
92fc43b4 HW |
5118 | static void rtl_rx_close(struct rtl8169_private *tp) |
5119 | { | |
5120 | void __iomem *ioaddr = tp->mmio_addr; | |
92fc43b4 | 5121 | |
1687b566 | 5122 | RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK); |
92fc43b4 HW |
5123 | } |
5124 | ||
ffc46952 FR |
5125 | DECLARE_RTL_COND(rtl_npq_cond) |
5126 | { | |
5127 | void __iomem *ioaddr = tp->mmio_addr; | |
5128 | ||
5129 | return RTL_R8(TxPoll) & NPQ; | |
5130 | } | |
5131 | ||
5132 | DECLARE_RTL_COND(rtl_txcfg_empty_cond) | |
5133 | { | |
5134 | void __iomem *ioaddr = tp->mmio_addr; | |
5135 | ||
5136 | return RTL_R32(TxConfig) & TXCFG_EMPTY; | |
5137 | } | |
5138 | ||
e6de30d6 | 5139 | static void rtl8169_hw_reset(struct rtl8169_private *tp) |
1da177e4 | 5140 | { |
e6de30d6 | 5141 | void __iomem *ioaddr = tp->mmio_addr; |
5142 | ||
1da177e4 | 5143 | /* Disable interrupts */ |
811fd301 | 5144 | rtl8169_irq_mask_and_ack(tp); |
1da177e4 | 5145 | |
92fc43b4 HW |
5146 | rtl_rx_close(tp); |
5147 | ||
5d2e1957 | 5148 | if (tp->mac_version == RTL_GIGA_MAC_VER_27 || |
4804b3b3 | 5149 | tp->mac_version == RTL_GIGA_MAC_VER_28 || |
5150 | tp->mac_version == RTL_GIGA_MAC_VER_31) { | |
ffc46952 | 5151 | rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42); |
c2218925 | 5152 | } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 || |
6e1d0b89 CHL |
5153 | tp->mac_version == RTL_GIGA_MAC_VER_35 || |
5154 | tp->mac_version == RTL_GIGA_MAC_VER_36 || | |
5155 | tp->mac_version == RTL_GIGA_MAC_VER_37 || | |
5156 | tp->mac_version == RTL_GIGA_MAC_VER_38 || | |
5157 | tp->mac_version == RTL_GIGA_MAC_VER_40 || | |
5158 | tp->mac_version == RTL_GIGA_MAC_VER_41 || | |
5159 | tp->mac_version == RTL_GIGA_MAC_VER_42 || | |
5160 | tp->mac_version == RTL_GIGA_MAC_VER_43 || | |
5161 | tp->mac_version == RTL_GIGA_MAC_VER_44 || | |
5162 | tp->mac_version == RTL_GIGA_MAC_VER_45 || | |
5163 | tp->mac_version == RTL_GIGA_MAC_VER_46 || | |
5164 | tp->mac_version == RTL_GIGA_MAC_VER_47 || | |
935e2218 CHL |
5165 | tp->mac_version == RTL_GIGA_MAC_VER_48 || |
5166 | tp->mac_version == RTL_GIGA_MAC_VER_49 || | |
5167 | tp->mac_version == RTL_GIGA_MAC_VER_50 || | |
5168 | tp->mac_version == RTL_GIGA_MAC_VER_51) { | |
c2b0c1e7 | 5169 | RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq); |
ffc46952 | 5170 | rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666); |
92fc43b4 HW |
5171 | } else { |
5172 | RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq); | |
5173 | udelay(100); | |
e6de30d6 | 5174 | } |
5175 | ||
92fc43b4 | 5176 | rtl_hw_reset(tp); |
1da177e4 LT |
5177 | } |
5178 | ||
7f796d83 | 5179 | static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp) |
9cb427b6 FR |
5180 | { |
5181 | void __iomem *ioaddr = tp->mmio_addr; | |
9cb427b6 FR |
5182 | |
5183 | /* Set DMA burst size and Interframe Gap Time */ | |
5184 | RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) | | |
5185 | (InterFrameGap << TxInterFrameGapShift)); | |
5186 | } | |
5187 | ||
07ce4064 | 5188 | static void rtl_hw_start(struct net_device *dev) |
1da177e4 LT |
5189 | { |
5190 | struct rtl8169_private *tp = netdev_priv(dev); | |
1da177e4 | 5191 | |
07ce4064 FR |
5192 | tp->hw_start(dev); |
5193 | ||
da78dbff | 5194 | rtl_irq_enable_all(tp); |
07ce4064 FR |
5195 | } |
5196 | ||
7f796d83 FR |
5197 | static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp, |
5198 | void __iomem *ioaddr) | |
5199 | { | |
5200 | /* | |
5201 | * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh | |
5202 | * register to be written before TxDescAddrLow to work. | |
5203 | * Switching from MMIO to I/O access fixes the issue as well. | |
5204 | */ | |
5205 | RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32); | |
284901a9 | 5206 | RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32)); |
7f796d83 | 5207 | RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32); |
284901a9 | 5208 | RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32)); |
7f796d83 FR |
5209 | } |
5210 | ||
5211 | static u16 rtl_rw_cpluscmd(void __iomem *ioaddr) | |
5212 | { | |
5213 | u16 cmd; | |
5214 | ||
5215 | cmd = RTL_R16(CPlusCmd); | |
5216 | RTL_W16(CPlusCmd, cmd); | |
5217 | return cmd; | |
5218 | } | |
5219 | ||
fdd7b4c3 | 5220 | static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz) |
7f796d83 FR |
5221 | { |
5222 | /* Low hurts. Let's disable the filtering. */ | |
207d6e87 | 5223 | RTL_W16(RxMaxSize, rx_buf_sz + 1); |
7f796d83 FR |
5224 | } |
5225 | ||
6dccd16b FR |
5226 | static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version) |
5227 | { | |
3744100e | 5228 | static const struct rtl_cfg2_info { |
6dccd16b FR |
5229 | u32 mac_version; |
5230 | u32 clk; | |
5231 | u32 val; | |
5232 | } cfg2_info [] = { | |
5233 | { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd | |
5234 | { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff }, | |
5235 | { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe | |
5236 | { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff } | |
3744100e FR |
5237 | }; |
5238 | const struct rtl_cfg2_info *p = cfg2_info; | |
6dccd16b FR |
5239 | unsigned int i; |
5240 | u32 clk; | |
5241 | ||
5242 | clk = RTL_R8(Config2) & PCI_Clock_66MHz; | |
cadf1855 | 5243 | for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) { |
6dccd16b FR |
5244 | if ((p->mac_version == mac_version) && (p->clk == clk)) { |
5245 | RTL_W32(0x7c, p->val); | |
5246 | break; | |
5247 | } | |
5248 | } | |
5249 | } | |
5250 | ||
e6b763ea FR |
5251 | static void rtl_set_rx_mode(struct net_device *dev) |
5252 | { | |
5253 | struct rtl8169_private *tp = netdev_priv(dev); | |
5254 | void __iomem *ioaddr = tp->mmio_addr; | |
5255 | u32 mc_filter[2]; /* Multicast hash filter */ | |
5256 | int rx_mode; | |
5257 | u32 tmp = 0; | |
5258 | ||
5259 | if (dev->flags & IFF_PROMISC) { | |
5260 | /* Unconditionally log net taps. */ | |
5261 | netif_notice(tp, link, dev, "Promiscuous mode enabled\n"); | |
5262 | rx_mode = | |
5263 | AcceptBroadcast | AcceptMulticast | AcceptMyPhys | | |
5264 | AcceptAllPhys; | |
5265 | mc_filter[1] = mc_filter[0] = 0xffffffff; | |
5266 | } else if ((netdev_mc_count(dev) > multicast_filter_limit) || | |
5267 | (dev->flags & IFF_ALLMULTI)) { | |
5268 | /* Too many to filter perfectly -- accept all multicasts. */ | |
5269 | rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys; | |
5270 | mc_filter[1] = mc_filter[0] = 0xffffffff; | |
5271 | } else { | |
5272 | struct netdev_hw_addr *ha; | |
5273 | ||
5274 | rx_mode = AcceptBroadcast | AcceptMyPhys; | |
5275 | mc_filter[1] = mc_filter[0] = 0; | |
5276 | netdev_for_each_mc_addr(ha, dev) { | |
5277 | int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; | |
5278 | mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); | |
5279 | rx_mode |= AcceptMulticast; | |
5280 | } | |
5281 | } | |
5282 | ||
5283 | if (dev->features & NETIF_F_RXALL) | |
5284 | rx_mode |= (AcceptErr | AcceptRunt); | |
5285 | ||
5286 | tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode; | |
5287 | ||
5288 | if (tp->mac_version > RTL_GIGA_MAC_VER_06) { | |
5289 | u32 data = mc_filter[0]; | |
5290 | ||
5291 | mc_filter[0] = swab32(mc_filter[1]); | |
5292 | mc_filter[1] = swab32(data); | |
5293 | } | |
5294 | ||
0481776b NW |
5295 | if (tp->mac_version == RTL_GIGA_MAC_VER_35) |
5296 | mc_filter[1] = mc_filter[0] = 0xffffffff; | |
5297 | ||
e6b763ea FR |
5298 | RTL_W32(MAR0 + 4, mc_filter[1]); |
5299 | RTL_W32(MAR0 + 0, mc_filter[0]); | |
5300 | ||
5301 | RTL_W32(RxConfig, tmp); | |
5302 | } | |
5303 | ||
07ce4064 FR |
5304 | static void rtl_hw_start_8169(struct net_device *dev) |
5305 | { | |
5306 | struct rtl8169_private *tp = netdev_priv(dev); | |
5307 | void __iomem *ioaddr = tp->mmio_addr; | |
5308 | struct pci_dev *pdev = tp->pci_dev; | |
07ce4064 | 5309 | |
9cb427b6 FR |
5310 | if (tp->mac_version == RTL_GIGA_MAC_VER_05) { |
5311 | RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW); | |
5312 | pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08); | |
5313 | } | |
5314 | ||
1da177e4 | 5315 | RTL_W8(Cfg9346, Cfg9346_Unlock); |
cecb5fd7 FR |
5316 | if (tp->mac_version == RTL_GIGA_MAC_VER_01 || |
5317 | tp->mac_version == RTL_GIGA_MAC_VER_02 || | |
5318 | tp->mac_version == RTL_GIGA_MAC_VER_03 || | |
5319 | tp->mac_version == RTL_GIGA_MAC_VER_04) | |
9cb427b6 FR |
5320 | RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); |
5321 | ||
e542a226 HW |
5322 | rtl_init_rxcfg(tp); |
5323 | ||
f0298f81 | 5324 | RTL_W8(EarlyTxThres, NoEarlyTx); |
1da177e4 | 5325 | |
6f0333b8 | 5326 | rtl_set_rx_max_size(ioaddr, rx_buf_sz); |
1da177e4 | 5327 | |
cecb5fd7 FR |
5328 | if (tp->mac_version == RTL_GIGA_MAC_VER_01 || |
5329 | tp->mac_version == RTL_GIGA_MAC_VER_02 || | |
5330 | tp->mac_version == RTL_GIGA_MAC_VER_03 || | |
5331 | tp->mac_version == RTL_GIGA_MAC_VER_04) | |
c946b304 | 5332 | rtl_set_rx_tx_config_registers(tp); |
1da177e4 | 5333 | |
7f796d83 | 5334 | tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW; |
1da177e4 | 5335 | |
cecb5fd7 FR |
5336 | if (tp->mac_version == RTL_GIGA_MAC_VER_02 || |
5337 | tp->mac_version == RTL_GIGA_MAC_VER_03) { | |
05b9687b | 5338 | dprintk("Set MAC Reg C+CR Offset 0xe0. " |
1da177e4 | 5339 | "Bit-3 and bit-14 MUST be 1\n"); |
bcf0bf90 | 5340 | tp->cp_cmd |= (1 << 14); |
1da177e4 LT |
5341 | } |
5342 | ||
bcf0bf90 FR |
5343 | RTL_W16(CPlusCmd, tp->cp_cmd); |
5344 | ||
6dccd16b FR |
5345 | rtl8169_set_magic_reg(ioaddr, tp->mac_version); |
5346 | ||
1da177e4 LT |
5347 | /* |
5348 | * Undocumented corner. Supposedly: | |
5349 | * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets | |
5350 | */ | |
5351 | RTL_W16(IntrMitigate, 0x0000); | |
5352 | ||
7f796d83 | 5353 | rtl_set_rx_tx_desc_registers(tp, ioaddr); |
9cb427b6 | 5354 | |
cecb5fd7 FR |
5355 | if (tp->mac_version != RTL_GIGA_MAC_VER_01 && |
5356 | tp->mac_version != RTL_GIGA_MAC_VER_02 && | |
5357 | tp->mac_version != RTL_GIGA_MAC_VER_03 && | |
5358 | tp->mac_version != RTL_GIGA_MAC_VER_04) { | |
c946b304 FR |
5359 | RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); |
5360 | rtl_set_rx_tx_config_registers(tp); | |
5361 | } | |
5362 | ||
1da177e4 | 5363 | RTL_W8(Cfg9346, Cfg9346_Lock); |
b518fa8e FR |
5364 | |
5365 | /* Initially a 10 us delay. Turned it into a PCI commit. - FR */ | |
5366 | RTL_R8(IntrMask); | |
1da177e4 LT |
5367 | |
5368 | RTL_W32(RxMissed, 0); | |
5369 | ||
07ce4064 | 5370 | rtl_set_rx_mode(dev); |
1da177e4 LT |
5371 | |
5372 | /* no early-rx interrupts */ | |
05b9687b | 5373 | RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000); |
07ce4064 | 5374 | } |
1da177e4 | 5375 | |
beb1fe18 HW |
5376 | static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value) |
5377 | { | |
5378 | if (tp->csi_ops.write) | |
52989f0e | 5379 | tp->csi_ops.write(tp, addr, value); |
beb1fe18 HW |
5380 | } |
5381 | ||
5382 | static u32 rtl_csi_read(struct rtl8169_private *tp, int addr) | |
5383 | { | |
52989f0e | 5384 | return tp->csi_ops.read ? tp->csi_ops.read(tp, addr) : ~0; |
beb1fe18 HW |
5385 | } |
5386 | ||
5387 | static void rtl_csi_access_enable(struct rtl8169_private *tp, u32 bits) | |
dacf8154 FR |
5388 | { |
5389 | u32 csi; | |
5390 | ||
beb1fe18 HW |
5391 | csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff; |
5392 | rtl_csi_write(tp, 0x070c, csi | bits); | |
5393 | } | |
5394 | ||
5395 | static void rtl_csi_access_enable_1(struct rtl8169_private *tp) | |
5396 | { | |
5397 | rtl_csi_access_enable(tp, 0x17000000); | |
650e8d5d | 5398 | } |
5399 | ||
beb1fe18 | 5400 | static void rtl_csi_access_enable_2(struct rtl8169_private *tp) |
e6de30d6 | 5401 | { |
beb1fe18 | 5402 | rtl_csi_access_enable(tp, 0x27000000); |
e6de30d6 | 5403 | } |
5404 | ||
ffc46952 FR |
5405 | DECLARE_RTL_COND(rtl_csiar_cond) |
5406 | { | |
5407 | void __iomem *ioaddr = tp->mmio_addr; | |
5408 | ||
5409 | return RTL_R32(CSIAR) & CSIAR_FLAG; | |
5410 | } | |
5411 | ||
52989f0e | 5412 | static void r8169_csi_write(struct rtl8169_private *tp, int addr, int value) |
650e8d5d | 5413 | { |
52989f0e | 5414 | void __iomem *ioaddr = tp->mmio_addr; |
beb1fe18 HW |
5415 | |
5416 | RTL_W32(CSIDR, value); | |
5417 | RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | | |
5418 | CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT); | |
5419 | ||
ffc46952 | 5420 | rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100); |
beb1fe18 HW |
5421 | } |
5422 | ||
52989f0e | 5423 | static u32 r8169_csi_read(struct rtl8169_private *tp, int addr) |
beb1fe18 | 5424 | { |
52989f0e | 5425 | void __iomem *ioaddr = tp->mmio_addr; |
beb1fe18 HW |
5426 | |
5427 | RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | | |
5428 | CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT); | |
5429 | ||
ffc46952 FR |
5430 | return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ? |
5431 | RTL_R32(CSIDR) : ~0; | |
beb1fe18 HW |
5432 | } |
5433 | ||
52989f0e | 5434 | static void r8402_csi_write(struct rtl8169_private *tp, int addr, int value) |
7e18dca1 | 5435 | { |
52989f0e | 5436 | void __iomem *ioaddr = tp->mmio_addr; |
7e18dca1 HW |
5437 | |
5438 | RTL_W32(CSIDR, value); | |
5439 | RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | | |
5440 | CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT | | |
5441 | CSIAR_FUNC_NIC); | |
5442 | ||
ffc46952 | 5443 | rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100); |
7e18dca1 HW |
5444 | } |
5445 | ||
52989f0e | 5446 | static u32 r8402_csi_read(struct rtl8169_private *tp, int addr) |
7e18dca1 | 5447 | { |
52989f0e | 5448 | void __iomem *ioaddr = tp->mmio_addr; |
7e18dca1 HW |
5449 | |
5450 | RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC | | |
5451 | CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT); | |
5452 | ||
ffc46952 FR |
5453 | return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ? |
5454 | RTL_R32(CSIDR) : ~0; | |
7e18dca1 HW |
5455 | } |
5456 | ||
45dd95c4 | 5457 | static void r8411_csi_write(struct rtl8169_private *tp, int addr, int value) |
5458 | { | |
5459 | void __iomem *ioaddr = tp->mmio_addr; | |
5460 | ||
5461 | RTL_W32(CSIDR, value); | |
5462 | RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | | |
5463 | CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT | | |
5464 | CSIAR_FUNC_NIC2); | |
5465 | ||
5466 | rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100); | |
5467 | } | |
5468 | ||
5469 | static u32 r8411_csi_read(struct rtl8169_private *tp, int addr) | |
5470 | { | |
5471 | void __iomem *ioaddr = tp->mmio_addr; | |
5472 | ||
5473 | RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC2 | | |
5474 | CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT); | |
5475 | ||
5476 | return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ? | |
5477 | RTL_R32(CSIDR) : ~0; | |
5478 | } | |
5479 | ||
baf63293 | 5480 | static void rtl_init_csi_ops(struct rtl8169_private *tp) |
beb1fe18 HW |
5481 | { |
5482 | struct csi_ops *ops = &tp->csi_ops; | |
5483 | ||
5484 | switch (tp->mac_version) { | |
5485 | case RTL_GIGA_MAC_VER_01: | |
5486 | case RTL_GIGA_MAC_VER_02: | |
5487 | case RTL_GIGA_MAC_VER_03: | |
5488 | case RTL_GIGA_MAC_VER_04: | |
5489 | case RTL_GIGA_MAC_VER_05: | |
5490 | case RTL_GIGA_MAC_VER_06: | |
5491 | case RTL_GIGA_MAC_VER_10: | |
5492 | case RTL_GIGA_MAC_VER_11: | |
5493 | case RTL_GIGA_MAC_VER_12: | |
5494 | case RTL_GIGA_MAC_VER_13: | |
5495 | case RTL_GIGA_MAC_VER_14: | |
5496 | case RTL_GIGA_MAC_VER_15: | |
5497 | case RTL_GIGA_MAC_VER_16: | |
5498 | case RTL_GIGA_MAC_VER_17: | |
5499 | ops->write = NULL; | |
5500 | ops->read = NULL; | |
5501 | break; | |
5502 | ||
7e18dca1 | 5503 | case RTL_GIGA_MAC_VER_37: |
b3d7b2f2 | 5504 | case RTL_GIGA_MAC_VER_38: |
7e18dca1 HW |
5505 | ops->write = r8402_csi_write; |
5506 | ops->read = r8402_csi_read; | |
5507 | break; | |
5508 | ||
45dd95c4 | 5509 | case RTL_GIGA_MAC_VER_44: |
5510 | ops->write = r8411_csi_write; | |
5511 | ops->read = r8411_csi_read; | |
5512 | break; | |
5513 | ||
beb1fe18 HW |
5514 | default: |
5515 | ops->write = r8169_csi_write; | |
5516 | ops->read = r8169_csi_read; | |
5517 | break; | |
5518 | } | |
dacf8154 FR |
5519 | } |
5520 | ||
5521 | struct ephy_info { | |
5522 | unsigned int offset; | |
5523 | u16 mask; | |
5524 | u16 bits; | |
5525 | }; | |
5526 | ||
fdf6fc06 FR |
5527 | static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e, |
5528 | int len) | |
dacf8154 FR |
5529 | { |
5530 | u16 w; | |
5531 | ||
5532 | while (len-- > 0) { | |
fdf6fc06 FR |
5533 | w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits; |
5534 | rtl_ephy_write(tp, e->offset, w); | |
dacf8154 FR |
5535 | e++; |
5536 | } | |
5537 | } | |
5538 | ||
b726e493 FR |
5539 | static void rtl_disable_clock_request(struct pci_dev *pdev) |
5540 | { | |
7d7903b2 JL |
5541 | pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL, |
5542 | PCI_EXP_LNKCTL_CLKREQ_EN); | |
b726e493 FR |
5543 | } |
5544 | ||
e6de30d6 | 5545 | static void rtl_enable_clock_request(struct pci_dev *pdev) |
5546 | { | |
7d7903b2 JL |
5547 | pcie_capability_set_word(pdev, PCI_EXP_LNKCTL, |
5548 | PCI_EXP_LNKCTL_CLKREQ_EN); | |
e6de30d6 | 5549 | } |
5550 | ||
b51ecea8 | 5551 | static void rtl_pcie_state_l2l3_enable(struct rtl8169_private *tp, bool enable) |
5552 | { | |
5553 | void __iomem *ioaddr = tp->mmio_addr; | |
5554 | u8 data; | |
5555 | ||
5556 | data = RTL_R8(Config3); | |
5557 | ||
5558 | if (enable) | |
5559 | data |= Rdy_to_L23; | |
5560 | else | |
5561 | data &= ~Rdy_to_L23; | |
5562 | ||
5563 | RTL_W8(Config3, data); | |
5564 | } | |
5565 | ||
b726e493 FR |
5566 | #define R8168_CPCMD_QUIRK_MASK (\ |
5567 | EnableBist | \ | |
5568 | Mac_dbgo_oe | \ | |
5569 | Force_half_dup | \ | |
5570 | Force_rxflow_en | \ | |
5571 | Force_txflow_en | \ | |
5572 | Cxpl_dbg_sel | \ | |
5573 | ASF | \ | |
5574 | PktCntrDisable | \ | |
5575 | Mac_dbgo_sel) | |
5576 | ||
beb1fe18 | 5577 | static void rtl_hw_start_8168bb(struct rtl8169_private *tp) |
219a1e9d | 5578 | { |
beb1fe18 HW |
5579 | void __iomem *ioaddr = tp->mmio_addr; |
5580 | struct pci_dev *pdev = tp->pci_dev; | |
5581 | ||
b726e493 FR |
5582 | RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); |
5583 | ||
5584 | RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); | |
5585 | ||
faf1e785 | 5586 | if (tp->dev->mtu <= ETH_DATA_LEN) { |
5587 | rtl_tx_performance_tweak(pdev, (0x5 << MAX_READ_REQUEST_SHIFT) | | |
5588 | PCI_EXP_DEVCTL_NOSNOOP_EN); | |
5589 | } | |
219a1e9d FR |
5590 | } |
5591 | ||
beb1fe18 | 5592 | static void rtl_hw_start_8168bef(struct rtl8169_private *tp) |
219a1e9d | 5593 | { |
beb1fe18 HW |
5594 | void __iomem *ioaddr = tp->mmio_addr; |
5595 | ||
5596 | rtl_hw_start_8168bb(tp); | |
b726e493 | 5597 | |
f0298f81 | 5598 | RTL_W8(MaxTxPacketSize, TxPacketMax); |
b726e493 FR |
5599 | |
5600 | RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0)); | |
219a1e9d FR |
5601 | } |
5602 | ||
beb1fe18 | 5603 | static void __rtl_hw_start_8168cp(struct rtl8169_private *tp) |
219a1e9d | 5604 | { |
beb1fe18 HW |
5605 | void __iomem *ioaddr = tp->mmio_addr; |
5606 | struct pci_dev *pdev = tp->pci_dev; | |
5607 | ||
b726e493 FR |
5608 | RTL_W8(Config1, RTL_R8(Config1) | Speed_down); |
5609 | ||
5610 | RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); | |
5611 | ||
faf1e785 | 5612 | if (tp->dev->mtu <= ETH_DATA_LEN) |
5613 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
b726e493 FR |
5614 | |
5615 | rtl_disable_clock_request(pdev); | |
5616 | ||
5617 | RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); | |
219a1e9d FR |
5618 | } |
5619 | ||
beb1fe18 | 5620 | static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp) |
219a1e9d | 5621 | { |
350f7596 | 5622 | static const struct ephy_info e_info_8168cp[] = { |
b726e493 FR |
5623 | { 0x01, 0, 0x0001 }, |
5624 | { 0x02, 0x0800, 0x1000 }, | |
5625 | { 0x03, 0, 0x0042 }, | |
5626 | { 0x06, 0x0080, 0x0000 }, | |
5627 | { 0x07, 0, 0x2000 } | |
5628 | }; | |
5629 | ||
beb1fe18 | 5630 | rtl_csi_access_enable_2(tp); |
b726e493 | 5631 | |
fdf6fc06 | 5632 | rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp)); |
b726e493 | 5633 | |
beb1fe18 | 5634 | __rtl_hw_start_8168cp(tp); |
219a1e9d FR |
5635 | } |
5636 | ||
beb1fe18 | 5637 | static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp) |
ef3386f0 | 5638 | { |
beb1fe18 HW |
5639 | void __iomem *ioaddr = tp->mmio_addr; |
5640 | struct pci_dev *pdev = tp->pci_dev; | |
5641 | ||
5642 | rtl_csi_access_enable_2(tp); | |
ef3386f0 FR |
5643 | |
5644 | RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); | |
5645 | ||
faf1e785 | 5646 | if (tp->dev->mtu <= ETH_DATA_LEN) |
5647 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
ef3386f0 FR |
5648 | |
5649 | RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); | |
5650 | } | |
5651 | ||
beb1fe18 | 5652 | static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp) |
7f3e3d3a | 5653 | { |
beb1fe18 HW |
5654 | void __iomem *ioaddr = tp->mmio_addr; |
5655 | struct pci_dev *pdev = tp->pci_dev; | |
5656 | ||
5657 | rtl_csi_access_enable_2(tp); | |
7f3e3d3a FR |
5658 | |
5659 | RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); | |
5660 | ||
5661 | /* Magic. */ | |
5662 | RTL_W8(DBG_REG, 0x20); | |
5663 | ||
f0298f81 | 5664 | RTL_W8(MaxTxPacketSize, TxPacketMax); |
7f3e3d3a | 5665 | |
faf1e785 | 5666 | if (tp->dev->mtu <= ETH_DATA_LEN) |
5667 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
7f3e3d3a FR |
5668 | |
5669 | RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); | |
5670 | } | |
5671 | ||
beb1fe18 | 5672 | static void rtl_hw_start_8168c_1(struct rtl8169_private *tp) |
219a1e9d | 5673 | { |
beb1fe18 | 5674 | void __iomem *ioaddr = tp->mmio_addr; |
350f7596 | 5675 | static const struct ephy_info e_info_8168c_1[] = { |
b726e493 FR |
5676 | { 0x02, 0x0800, 0x1000 }, |
5677 | { 0x03, 0, 0x0002 }, | |
5678 | { 0x06, 0x0080, 0x0000 } | |
5679 | }; | |
5680 | ||
beb1fe18 | 5681 | rtl_csi_access_enable_2(tp); |
b726e493 FR |
5682 | |
5683 | RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2); | |
5684 | ||
fdf6fc06 | 5685 | rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1)); |
b726e493 | 5686 | |
beb1fe18 | 5687 | __rtl_hw_start_8168cp(tp); |
219a1e9d FR |
5688 | } |
5689 | ||
beb1fe18 | 5690 | static void rtl_hw_start_8168c_2(struct rtl8169_private *tp) |
219a1e9d | 5691 | { |
350f7596 | 5692 | static const struct ephy_info e_info_8168c_2[] = { |
b726e493 FR |
5693 | { 0x01, 0, 0x0001 }, |
5694 | { 0x03, 0x0400, 0x0220 } | |
5695 | }; | |
5696 | ||
beb1fe18 | 5697 | rtl_csi_access_enable_2(tp); |
b726e493 | 5698 | |
fdf6fc06 | 5699 | rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2)); |
b726e493 | 5700 | |
beb1fe18 | 5701 | __rtl_hw_start_8168cp(tp); |
219a1e9d FR |
5702 | } |
5703 | ||
beb1fe18 | 5704 | static void rtl_hw_start_8168c_3(struct rtl8169_private *tp) |
197ff761 | 5705 | { |
beb1fe18 | 5706 | rtl_hw_start_8168c_2(tp); |
197ff761 FR |
5707 | } |
5708 | ||
beb1fe18 | 5709 | static void rtl_hw_start_8168c_4(struct rtl8169_private *tp) |
6fb07058 | 5710 | { |
beb1fe18 | 5711 | rtl_csi_access_enable_2(tp); |
6fb07058 | 5712 | |
beb1fe18 | 5713 | __rtl_hw_start_8168cp(tp); |
6fb07058 FR |
5714 | } |
5715 | ||
beb1fe18 | 5716 | static void rtl_hw_start_8168d(struct rtl8169_private *tp) |
5b538df9 | 5717 | { |
beb1fe18 HW |
5718 | void __iomem *ioaddr = tp->mmio_addr; |
5719 | struct pci_dev *pdev = tp->pci_dev; | |
5720 | ||
5721 | rtl_csi_access_enable_2(tp); | |
5b538df9 FR |
5722 | |
5723 | rtl_disable_clock_request(pdev); | |
5724 | ||
f0298f81 | 5725 | RTL_W8(MaxTxPacketSize, TxPacketMax); |
5b538df9 | 5726 | |
faf1e785 | 5727 | if (tp->dev->mtu <= ETH_DATA_LEN) |
5728 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
5b538df9 FR |
5729 | |
5730 | RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); | |
5731 | } | |
5732 | ||
beb1fe18 | 5733 | static void rtl_hw_start_8168dp(struct rtl8169_private *tp) |
4804b3b3 | 5734 | { |
beb1fe18 HW |
5735 | void __iomem *ioaddr = tp->mmio_addr; |
5736 | struct pci_dev *pdev = tp->pci_dev; | |
5737 | ||
5738 | rtl_csi_access_enable_1(tp); | |
4804b3b3 | 5739 | |
faf1e785 | 5740 | if (tp->dev->mtu <= ETH_DATA_LEN) |
5741 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
4804b3b3 | 5742 | |
5743 | RTL_W8(MaxTxPacketSize, TxPacketMax); | |
5744 | ||
5745 | rtl_disable_clock_request(pdev); | |
5746 | } | |
5747 | ||
beb1fe18 | 5748 | static void rtl_hw_start_8168d_4(struct rtl8169_private *tp) |
e6de30d6 | 5749 | { |
beb1fe18 HW |
5750 | void __iomem *ioaddr = tp->mmio_addr; |
5751 | struct pci_dev *pdev = tp->pci_dev; | |
e6de30d6 | 5752 | static const struct ephy_info e_info_8168d_4[] = { |
5753 | { 0x0b, ~0, 0x48 }, | |
5754 | { 0x19, 0x20, 0x50 }, | |
5755 | { 0x0c, ~0, 0x20 } | |
5756 | }; | |
5757 | int i; | |
5758 | ||
beb1fe18 | 5759 | rtl_csi_access_enable_1(tp); |
e6de30d6 | 5760 | |
5761 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
5762 | ||
5763 | RTL_W8(MaxTxPacketSize, TxPacketMax); | |
5764 | ||
5765 | for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) { | |
5766 | const struct ephy_info *e = e_info_8168d_4 + i; | |
5767 | u16 w; | |
5768 | ||
fdf6fc06 FR |
5769 | w = rtl_ephy_read(tp, e->offset); |
5770 | rtl_ephy_write(tp, 0x03, (w & e->mask) | e->bits); | |
e6de30d6 | 5771 | } |
5772 | ||
5773 | rtl_enable_clock_request(pdev); | |
5774 | } | |
5775 | ||
beb1fe18 | 5776 | static void rtl_hw_start_8168e_1(struct rtl8169_private *tp) |
01dc7fec | 5777 | { |
beb1fe18 HW |
5778 | void __iomem *ioaddr = tp->mmio_addr; |
5779 | struct pci_dev *pdev = tp->pci_dev; | |
70090424 | 5780 | static const struct ephy_info e_info_8168e_1[] = { |
01dc7fec | 5781 | { 0x00, 0x0200, 0x0100 }, |
5782 | { 0x00, 0x0000, 0x0004 }, | |
5783 | { 0x06, 0x0002, 0x0001 }, | |
5784 | { 0x06, 0x0000, 0x0030 }, | |
5785 | { 0x07, 0x0000, 0x2000 }, | |
5786 | { 0x00, 0x0000, 0x0020 }, | |
5787 | { 0x03, 0x5800, 0x2000 }, | |
5788 | { 0x03, 0x0000, 0x0001 }, | |
5789 | { 0x01, 0x0800, 0x1000 }, | |
5790 | { 0x07, 0x0000, 0x4000 }, | |
5791 | { 0x1e, 0x0000, 0x2000 }, | |
5792 | { 0x19, 0xffff, 0xfe6c }, | |
5793 | { 0x0a, 0x0000, 0x0040 } | |
5794 | }; | |
5795 | ||
beb1fe18 | 5796 | rtl_csi_access_enable_2(tp); |
01dc7fec | 5797 | |
fdf6fc06 | 5798 | rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1)); |
01dc7fec | 5799 | |
faf1e785 | 5800 | if (tp->dev->mtu <= ETH_DATA_LEN) |
5801 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
01dc7fec | 5802 | |
5803 | RTL_W8(MaxTxPacketSize, TxPacketMax); | |
5804 | ||
5805 | rtl_disable_clock_request(pdev); | |
5806 | ||
5807 | /* Reset tx FIFO pointer */ | |
cecb5fd7 FR |
5808 | RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST); |
5809 | RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST); | |
01dc7fec | 5810 | |
cecb5fd7 | 5811 | RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en); |
01dc7fec | 5812 | } |
5813 | ||
beb1fe18 | 5814 | static void rtl_hw_start_8168e_2(struct rtl8169_private *tp) |
70090424 | 5815 | { |
beb1fe18 HW |
5816 | void __iomem *ioaddr = tp->mmio_addr; |
5817 | struct pci_dev *pdev = tp->pci_dev; | |
70090424 HW |
5818 | static const struct ephy_info e_info_8168e_2[] = { |
5819 | { 0x09, 0x0000, 0x0080 }, | |
5820 | { 0x19, 0x0000, 0x0224 } | |
5821 | }; | |
5822 | ||
beb1fe18 | 5823 | rtl_csi_access_enable_1(tp); |
70090424 | 5824 | |
fdf6fc06 | 5825 | rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2)); |
70090424 | 5826 | |
faf1e785 | 5827 | if (tp->dev->mtu <= ETH_DATA_LEN) |
5828 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
70090424 | 5829 | |
fdf6fc06 FR |
5830 | rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); |
5831 | rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); | |
5832 | rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC); | |
5833 | rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC); | |
5834 | rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC); | |
5835 | rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC); | |
706123d0 CHL |
5836 | rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC); |
5837 | rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC); | |
70090424 | 5838 | |
3090bd9a | 5839 | RTL_W8(MaxTxPacketSize, EarlySize); |
70090424 | 5840 | |
4521e1a9 FR |
5841 | rtl_disable_clock_request(pdev); |
5842 | ||
70090424 HW |
5843 | RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO); |
5844 | RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB); | |
5845 | ||
5846 | /* Adjust EEE LED frequency */ | |
5847 | RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07); | |
5848 | ||
5849 | RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN); | |
5850 | RTL_W32(MISC, RTL_R32(MISC) | PWM_EN); | |
4521e1a9 | 5851 | RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en); |
70090424 HW |
5852 | } |
5853 | ||
5f886e08 | 5854 | static void rtl_hw_start_8168f(struct rtl8169_private *tp) |
c2218925 | 5855 | { |
beb1fe18 HW |
5856 | void __iomem *ioaddr = tp->mmio_addr; |
5857 | struct pci_dev *pdev = tp->pci_dev; | |
c2218925 | 5858 | |
5f886e08 | 5859 | rtl_csi_access_enable_2(tp); |
c2218925 HW |
5860 | |
5861 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
5862 | ||
fdf6fc06 FR |
5863 | rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); |
5864 | rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); | |
5865 | rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC); | |
5866 | rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC); | |
706123d0 CHL |
5867 | rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC); |
5868 | rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC); | |
5869 | rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC); | |
5870 | rtl_w0w1_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC); | |
fdf6fc06 FR |
5871 | rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC); |
5872 | rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC); | |
c2218925 HW |
5873 | |
5874 | RTL_W8(MaxTxPacketSize, EarlySize); | |
5875 | ||
4521e1a9 FR |
5876 | rtl_disable_clock_request(pdev); |
5877 | ||
c2218925 HW |
5878 | RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO); |
5879 | RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB); | |
c2218925 | 5880 | RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN); |
4521e1a9 FR |
5881 | RTL_W32(MISC, RTL_R32(MISC) | PWM_EN); |
5882 | RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en); | |
c2218925 HW |
5883 | } |
5884 | ||
5f886e08 HW |
5885 | static void rtl_hw_start_8168f_1(struct rtl8169_private *tp) |
5886 | { | |
5887 | void __iomem *ioaddr = tp->mmio_addr; | |
5888 | static const struct ephy_info e_info_8168f_1[] = { | |
5889 | { 0x06, 0x00c0, 0x0020 }, | |
5890 | { 0x08, 0x0001, 0x0002 }, | |
5891 | { 0x09, 0x0000, 0x0080 }, | |
5892 | { 0x19, 0x0000, 0x0224 } | |
5893 | }; | |
5894 | ||
5895 | rtl_hw_start_8168f(tp); | |
5896 | ||
fdf6fc06 | 5897 | rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1)); |
5f886e08 | 5898 | |
706123d0 | 5899 | rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC); |
5f886e08 HW |
5900 | |
5901 | /* Adjust EEE LED frequency */ | |
5902 | RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07); | |
5903 | } | |
5904 | ||
b3d7b2f2 HW |
5905 | static void rtl_hw_start_8411(struct rtl8169_private *tp) |
5906 | { | |
b3d7b2f2 HW |
5907 | static const struct ephy_info e_info_8168f_1[] = { |
5908 | { 0x06, 0x00c0, 0x0020 }, | |
5909 | { 0x0f, 0xffff, 0x5200 }, | |
5910 | { 0x1e, 0x0000, 0x4000 }, | |
5911 | { 0x19, 0x0000, 0x0224 } | |
5912 | }; | |
5913 | ||
5914 | rtl_hw_start_8168f(tp); | |
b51ecea8 | 5915 | rtl_pcie_state_l2l3_enable(tp, false); |
b3d7b2f2 | 5916 | |
fdf6fc06 | 5917 | rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1)); |
b3d7b2f2 | 5918 | |
706123d0 | 5919 | rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC); |
b3d7b2f2 HW |
5920 | } |
5921 | ||
5fbea337 | 5922 | static void rtl_hw_start_8168g(struct rtl8169_private *tp) |
c558386b HW |
5923 | { |
5924 | void __iomem *ioaddr = tp->mmio_addr; | |
5925 | struct pci_dev *pdev = tp->pci_dev; | |
5926 | ||
beb330a4 | 5927 | RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO); |
5928 | ||
c558386b HW |
5929 | rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC); |
5930 | rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC); | |
5931 | rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC); | |
5932 | rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC); | |
5933 | ||
5934 | rtl_csi_access_enable_1(tp); | |
5935 | ||
5936 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
5937 | ||
706123d0 CHL |
5938 | rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC); |
5939 | rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC); | |
beb330a4 | 5940 | rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC); |
c558386b | 5941 | |
4521e1a9 | 5942 | RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN); |
c558386b HW |
5943 | RTL_W8(MaxTxPacketSize, EarlySize); |
5944 | ||
5945 | rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); | |
5946 | rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); | |
5947 | ||
5948 | /* Adjust EEE LED frequency */ | |
5949 | RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07); | |
5950 | ||
706123d0 CHL |
5951 | rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC); |
5952 | rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC); | |
b51ecea8 | 5953 | |
5954 | rtl_pcie_state_l2l3_enable(tp, false); | |
c558386b HW |
5955 | } |
5956 | ||
5fbea337 CHL |
5957 | static void rtl_hw_start_8168g_1(struct rtl8169_private *tp) |
5958 | { | |
5959 | void __iomem *ioaddr = tp->mmio_addr; | |
5960 | static const struct ephy_info e_info_8168g_1[] = { | |
5961 | { 0x00, 0x0000, 0x0008 }, | |
5962 | { 0x0c, 0x37d0, 0x0820 }, | |
5963 | { 0x1e, 0x0000, 0x0001 }, | |
5964 | { 0x19, 0x8000, 0x0000 } | |
5965 | }; | |
5966 | ||
5967 | rtl_hw_start_8168g(tp); | |
5968 | ||
5969 | /* disable aspm and clock request before access ephy */ | |
5970 | RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn); | |
5971 | RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en); | |
5972 | rtl_ephy_init(tp, e_info_8168g_1, ARRAY_SIZE(e_info_8168g_1)); | |
5973 | } | |
5974 | ||
57538c4a | 5975 | static void rtl_hw_start_8168g_2(struct rtl8169_private *tp) |
5976 | { | |
5977 | void __iomem *ioaddr = tp->mmio_addr; | |
5978 | static const struct ephy_info e_info_8168g_2[] = { | |
5979 | { 0x00, 0x0000, 0x0008 }, | |
5980 | { 0x0c, 0x3df0, 0x0200 }, | |
5981 | { 0x19, 0xffff, 0xfc00 }, | |
5982 | { 0x1e, 0xffff, 0x20eb } | |
5983 | }; | |
5984 | ||
5fbea337 | 5985 | rtl_hw_start_8168g(tp); |
57538c4a | 5986 | |
5987 | /* disable aspm and clock request before access ephy */ | |
5988 | RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn); | |
5989 | RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en); | |
5990 | rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2)); | |
5991 | } | |
5992 | ||
45dd95c4 | 5993 | static void rtl_hw_start_8411_2(struct rtl8169_private *tp) |
5994 | { | |
5995 | void __iomem *ioaddr = tp->mmio_addr; | |
5996 | static const struct ephy_info e_info_8411_2[] = { | |
5997 | { 0x00, 0x0000, 0x0008 }, | |
5998 | { 0x0c, 0x3df0, 0x0200 }, | |
5999 | { 0x0f, 0xffff, 0x5200 }, | |
6000 | { 0x19, 0x0020, 0x0000 }, | |
6001 | { 0x1e, 0x0000, 0x2000 } | |
6002 | }; | |
6003 | ||
5fbea337 | 6004 | rtl_hw_start_8168g(tp); |
45dd95c4 | 6005 | |
6006 | /* disable aspm and clock request before access ephy */ | |
6007 | RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn); | |
6008 | RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en); | |
6009 | rtl_ephy_init(tp, e_info_8411_2, ARRAY_SIZE(e_info_8411_2)); | |
6010 | } | |
6011 | ||
6e1d0b89 CHL |
6012 | static void rtl_hw_start_8168h_1(struct rtl8169_private *tp) |
6013 | { | |
6014 | void __iomem *ioaddr = tp->mmio_addr; | |
6015 | struct pci_dev *pdev = tp->pci_dev; | |
6016 | u16 rg_saw_cnt; | |
6017 | u32 data; | |
6018 | static const struct ephy_info e_info_8168h_1[] = { | |
6019 | { 0x1e, 0x0800, 0x0001 }, | |
6020 | { 0x1d, 0x0000, 0x0800 }, | |
6021 | { 0x05, 0xffff, 0x2089 }, | |
6022 | { 0x06, 0xffff, 0x5881 }, | |
6023 | { 0x04, 0xffff, 0x154a }, | |
6024 | { 0x01, 0xffff, 0x068b } | |
6025 | }; | |
6026 | ||
6027 | /* disable aspm and clock request before access ephy */ | |
6028 | RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn); | |
6029 | RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en); | |
6030 | rtl_ephy_init(tp, e_info_8168h_1, ARRAY_SIZE(e_info_8168h_1)); | |
6031 | ||
6032 | RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO); | |
6033 | ||
6034 | rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC); | |
6035 | rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC); | |
6036 | rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC); | |
6037 | rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC); | |
6038 | ||
6039 | rtl_csi_access_enable_1(tp); | |
6040 | ||
6041 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
6042 | ||
706123d0 CHL |
6043 | rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC); |
6044 | rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC); | |
6e1d0b89 | 6045 | |
706123d0 | 6046 | rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_1111, 0x0010, 0x00, ERIAR_EXGMAC); |
6e1d0b89 | 6047 | |
706123d0 | 6048 | rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f00, 0x00, ERIAR_EXGMAC); |
6e1d0b89 CHL |
6049 | |
6050 | rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC); | |
6051 | ||
6e1d0b89 CHL |
6052 | RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN); |
6053 | RTL_W8(MaxTxPacketSize, EarlySize); | |
6054 | ||
6055 | rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); | |
6056 | rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); | |
6057 | ||
6058 | /* Adjust EEE LED frequency */ | |
6059 | RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07); | |
6060 | ||
6061 | RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN); | |
6062 | RTL_W8(DLLPR, RTL_R8(MISC_1) & ~PFM_D3COLD_EN); | |
6063 | ||
6064 | RTL_W8(DLLPR, RTL_R8(DLLPR) & ~TX_10M_PS_EN); | |
6065 | ||
706123d0 | 6066 | rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC); |
6e1d0b89 CHL |
6067 | |
6068 | rtl_pcie_state_l2l3_enable(tp, false); | |
6069 | ||
6070 | rtl_writephy(tp, 0x1f, 0x0c42); | |
6071 | rg_saw_cnt = rtl_readphy(tp, 0x13); | |
6072 | rtl_writephy(tp, 0x1f, 0x0000); | |
6073 | if (rg_saw_cnt > 0) { | |
6074 | u16 sw_cnt_1ms_ini; | |
6075 | ||
6076 | sw_cnt_1ms_ini = 16000000/rg_saw_cnt; | |
6077 | sw_cnt_1ms_ini &= 0x0fff; | |
6078 | data = r8168_mac_ocp_read(tp, 0xd412); | |
6079 | data &= 0x0fff; | |
6080 | data |= sw_cnt_1ms_ini; | |
6081 | r8168_mac_ocp_write(tp, 0xd412, data); | |
6082 | } | |
6083 | ||
6084 | data = r8168_mac_ocp_read(tp, 0xe056); | |
6085 | data &= 0xf0; | |
6086 | data |= 0x07; | |
6087 | r8168_mac_ocp_write(tp, 0xe056, data); | |
6088 | ||
6089 | data = r8168_mac_ocp_read(tp, 0xe052); | |
6090 | data &= 0x8008; | |
6091 | data |= 0x6000; | |
6092 | r8168_mac_ocp_write(tp, 0xe052, data); | |
6093 | ||
6094 | data = r8168_mac_ocp_read(tp, 0xe0d6); | |
6095 | data &= 0x01ff; | |
6096 | data |= 0x017f; | |
6097 | r8168_mac_ocp_write(tp, 0xe0d6, data); | |
6098 | ||
6099 | data = r8168_mac_ocp_read(tp, 0xd420); | |
6100 | data &= 0x0fff; | |
6101 | data |= 0x047f; | |
6102 | r8168_mac_ocp_write(tp, 0xd420, data); | |
6103 | ||
6104 | r8168_mac_ocp_write(tp, 0xe63e, 0x0001); | |
6105 | r8168_mac_ocp_write(tp, 0xe63e, 0x0000); | |
6106 | r8168_mac_ocp_write(tp, 0xc094, 0x0000); | |
6107 | r8168_mac_ocp_write(tp, 0xc09e, 0x0000); | |
6108 | } | |
6109 | ||
935e2218 CHL |
6110 | static void rtl_hw_start_8168ep(struct rtl8169_private *tp) |
6111 | { | |
6112 | void __iomem *ioaddr = tp->mmio_addr; | |
6113 | struct pci_dev *pdev = tp->pci_dev; | |
6114 | ||
003609da CHL |
6115 | rtl8168ep_stop_cmac(tp); |
6116 | ||
935e2218 CHL |
6117 | RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO); |
6118 | ||
6119 | rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC); | |
6120 | rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x2f, ERIAR_EXGMAC); | |
6121 | rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x5f, ERIAR_EXGMAC); | |
6122 | rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC); | |
6123 | ||
6124 | rtl_csi_access_enable_1(tp); | |
6125 | ||
6126 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
6127 | ||
6128 | rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC); | |
6129 | rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC); | |
6130 | ||
6131 | rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f80, 0x00, ERIAR_EXGMAC); | |
6132 | ||
6133 | rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC); | |
6134 | ||
935e2218 CHL |
6135 | RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN); |
6136 | RTL_W8(MaxTxPacketSize, EarlySize); | |
6137 | ||
6138 | rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); | |
6139 | rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); | |
6140 | ||
6141 | /* Adjust EEE LED frequency */ | |
6142 | RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07); | |
6143 | ||
6144 | rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC); | |
6145 | ||
6146 | RTL_W8(DLLPR, RTL_R8(DLLPR) & ~TX_10M_PS_EN); | |
6147 | ||
6148 | rtl_pcie_state_l2l3_enable(tp, false); | |
6149 | } | |
6150 | ||
6151 | static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp) | |
6152 | { | |
6153 | void __iomem *ioaddr = tp->mmio_addr; | |
6154 | static const struct ephy_info e_info_8168ep_1[] = { | |
6155 | { 0x00, 0xffff, 0x10ab }, | |
6156 | { 0x06, 0xffff, 0xf030 }, | |
6157 | { 0x08, 0xffff, 0x2006 }, | |
6158 | { 0x0d, 0xffff, 0x1666 }, | |
6159 | { 0x0c, 0x3ff0, 0x0000 } | |
6160 | }; | |
6161 | ||
6162 | /* disable aspm and clock request before access ephy */ | |
6163 | RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn); | |
6164 | RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en); | |
6165 | rtl_ephy_init(tp, e_info_8168ep_1, ARRAY_SIZE(e_info_8168ep_1)); | |
6166 | ||
6167 | rtl_hw_start_8168ep(tp); | |
6168 | } | |
6169 | ||
6170 | static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp) | |
6171 | { | |
6172 | void __iomem *ioaddr = tp->mmio_addr; | |
6173 | static const struct ephy_info e_info_8168ep_2[] = { | |
6174 | { 0x00, 0xffff, 0x10a3 }, | |
6175 | { 0x19, 0xffff, 0xfc00 }, | |
6176 | { 0x1e, 0xffff, 0x20ea } | |
6177 | }; | |
6178 | ||
6179 | /* disable aspm and clock request before access ephy */ | |
6180 | RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn); | |
6181 | RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en); | |
6182 | rtl_ephy_init(tp, e_info_8168ep_2, ARRAY_SIZE(e_info_8168ep_2)); | |
6183 | ||
6184 | rtl_hw_start_8168ep(tp); | |
6185 | ||
6186 | RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN); | |
6187 | RTL_W8(DLLPR, RTL_R8(MISC_1) & ~PFM_D3COLD_EN); | |
6188 | } | |
6189 | ||
6190 | static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp) | |
6191 | { | |
6192 | void __iomem *ioaddr = tp->mmio_addr; | |
6193 | u32 data; | |
6194 | static const struct ephy_info e_info_8168ep_3[] = { | |
6195 | { 0x00, 0xffff, 0x10a3 }, | |
6196 | { 0x19, 0xffff, 0x7c00 }, | |
6197 | { 0x1e, 0xffff, 0x20eb }, | |
6198 | { 0x0d, 0xffff, 0x1666 } | |
6199 | }; | |
6200 | ||
6201 | /* disable aspm and clock request before access ephy */ | |
6202 | RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn); | |
6203 | RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en); | |
6204 | rtl_ephy_init(tp, e_info_8168ep_3, ARRAY_SIZE(e_info_8168ep_3)); | |
6205 | ||
6206 | rtl_hw_start_8168ep(tp); | |
6207 | ||
6208 | RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN); | |
6209 | RTL_W8(DLLPR, RTL_R8(MISC_1) & ~PFM_D3COLD_EN); | |
6210 | ||
6211 | data = r8168_mac_ocp_read(tp, 0xd3e2); | |
6212 | data &= 0xf000; | |
6213 | data |= 0x0271; | |
6214 | r8168_mac_ocp_write(tp, 0xd3e2, data); | |
6215 | ||
6216 | data = r8168_mac_ocp_read(tp, 0xd3e4); | |
6217 | data &= 0xff00; | |
6218 | r8168_mac_ocp_write(tp, 0xd3e4, data); | |
6219 | ||
6220 | data = r8168_mac_ocp_read(tp, 0xe860); | |
6221 | data |= 0x0080; | |
6222 | r8168_mac_ocp_write(tp, 0xe860, data); | |
6223 | } | |
6224 | ||
07ce4064 FR |
6225 | static void rtl_hw_start_8168(struct net_device *dev) |
6226 | { | |
2dd99530 FR |
6227 | struct rtl8169_private *tp = netdev_priv(dev); |
6228 | void __iomem *ioaddr = tp->mmio_addr; | |
6229 | ||
6230 | RTL_W8(Cfg9346, Cfg9346_Unlock); | |
6231 | ||
f0298f81 | 6232 | RTL_W8(MaxTxPacketSize, TxPacketMax); |
2dd99530 | 6233 | |
6f0333b8 | 6234 | rtl_set_rx_max_size(ioaddr, rx_buf_sz); |
2dd99530 | 6235 | |
0e485150 | 6236 | tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1; |
2dd99530 FR |
6237 | |
6238 | RTL_W16(CPlusCmd, tp->cp_cmd); | |
6239 | ||
0e485150 | 6240 | RTL_W16(IntrMitigate, 0x5151); |
2dd99530 | 6241 | |
0e485150 | 6242 | /* Work around for RxFIFO overflow. */ |
811fd301 | 6243 | if (tp->mac_version == RTL_GIGA_MAC_VER_11) { |
da78dbff FR |
6244 | tp->event_slow |= RxFIFOOver | PCSTimeout; |
6245 | tp->event_slow &= ~RxOverflow; | |
0e485150 FR |
6246 | } |
6247 | ||
6248 | rtl_set_rx_tx_desc_registers(tp, ioaddr); | |
2dd99530 | 6249 | |
1a964649 | 6250 | rtl_set_rx_tx_config_registers(tp); |
2dd99530 FR |
6251 | |
6252 | RTL_R8(IntrMask); | |
6253 | ||
219a1e9d FR |
6254 | switch (tp->mac_version) { |
6255 | case RTL_GIGA_MAC_VER_11: | |
beb1fe18 | 6256 | rtl_hw_start_8168bb(tp); |
4804b3b3 | 6257 | break; |
219a1e9d FR |
6258 | |
6259 | case RTL_GIGA_MAC_VER_12: | |
6260 | case RTL_GIGA_MAC_VER_17: | |
beb1fe18 | 6261 | rtl_hw_start_8168bef(tp); |
4804b3b3 | 6262 | break; |
219a1e9d FR |
6263 | |
6264 | case RTL_GIGA_MAC_VER_18: | |
beb1fe18 | 6265 | rtl_hw_start_8168cp_1(tp); |
4804b3b3 | 6266 | break; |
219a1e9d FR |
6267 | |
6268 | case RTL_GIGA_MAC_VER_19: | |
beb1fe18 | 6269 | rtl_hw_start_8168c_1(tp); |
4804b3b3 | 6270 | break; |
219a1e9d FR |
6271 | |
6272 | case RTL_GIGA_MAC_VER_20: | |
beb1fe18 | 6273 | rtl_hw_start_8168c_2(tp); |
4804b3b3 | 6274 | break; |
219a1e9d | 6275 | |
197ff761 | 6276 | case RTL_GIGA_MAC_VER_21: |
beb1fe18 | 6277 | rtl_hw_start_8168c_3(tp); |
4804b3b3 | 6278 | break; |
197ff761 | 6279 | |
6fb07058 | 6280 | case RTL_GIGA_MAC_VER_22: |
beb1fe18 | 6281 | rtl_hw_start_8168c_4(tp); |
4804b3b3 | 6282 | break; |
6fb07058 | 6283 | |
ef3386f0 | 6284 | case RTL_GIGA_MAC_VER_23: |
beb1fe18 | 6285 | rtl_hw_start_8168cp_2(tp); |
4804b3b3 | 6286 | break; |
ef3386f0 | 6287 | |
7f3e3d3a | 6288 | case RTL_GIGA_MAC_VER_24: |
beb1fe18 | 6289 | rtl_hw_start_8168cp_3(tp); |
4804b3b3 | 6290 | break; |
7f3e3d3a | 6291 | |
5b538df9 | 6292 | case RTL_GIGA_MAC_VER_25: |
daf9df6d | 6293 | case RTL_GIGA_MAC_VER_26: |
6294 | case RTL_GIGA_MAC_VER_27: | |
beb1fe18 | 6295 | rtl_hw_start_8168d(tp); |
4804b3b3 | 6296 | break; |
5b538df9 | 6297 | |
e6de30d6 | 6298 | case RTL_GIGA_MAC_VER_28: |
beb1fe18 | 6299 | rtl_hw_start_8168d_4(tp); |
4804b3b3 | 6300 | break; |
cecb5fd7 | 6301 | |
4804b3b3 | 6302 | case RTL_GIGA_MAC_VER_31: |
beb1fe18 | 6303 | rtl_hw_start_8168dp(tp); |
4804b3b3 | 6304 | break; |
6305 | ||
01dc7fec | 6306 | case RTL_GIGA_MAC_VER_32: |
6307 | case RTL_GIGA_MAC_VER_33: | |
beb1fe18 | 6308 | rtl_hw_start_8168e_1(tp); |
70090424 HW |
6309 | break; |
6310 | case RTL_GIGA_MAC_VER_34: | |
beb1fe18 | 6311 | rtl_hw_start_8168e_2(tp); |
01dc7fec | 6312 | break; |
e6de30d6 | 6313 | |
c2218925 HW |
6314 | case RTL_GIGA_MAC_VER_35: |
6315 | case RTL_GIGA_MAC_VER_36: | |
beb1fe18 | 6316 | rtl_hw_start_8168f_1(tp); |
c2218925 HW |
6317 | break; |
6318 | ||
b3d7b2f2 HW |
6319 | case RTL_GIGA_MAC_VER_38: |
6320 | rtl_hw_start_8411(tp); | |
6321 | break; | |
6322 | ||
c558386b HW |
6323 | case RTL_GIGA_MAC_VER_40: |
6324 | case RTL_GIGA_MAC_VER_41: | |
6325 | rtl_hw_start_8168g_1(tp); | |
6326 | break; | |
57538c4a | 6327 | case RTL_GIGA_MAC_VER_42: |
6328 | rtl_hw_start_8168g_2(tp); | |
6329 | break; | |
c558386b | 6330 | |
45dd95c4 | 6331 | case RTL_GIGA_MAC_VER_44: |
6332 | rtl_hw_start_8411_2(tp); | |
6333 | break; | |
6334 | ||
6e1d0b89 CHL |
6335 | case RTL_GIGA_MAC_VER_45: |
6336 | case RTL_GIGA_MAC_VER_46: | |
6337 | rtl_hw_start_8168h_1(tp); | |
6338 | break; | |
6339 | ||
935e2218 CHL |
6340 | case RTL_GIGA_MAC_VER_49: |
6341 | rtl_hw_start_8168ep_1(tp); | |
6342 | break; | |
6343 | ||
6344 | case RTL_GIGA_MAC_VER_50: | |
6345 | rtl_hw_start_8168ep_2(tp); | |
6346 | break; | |
6347 | ||
6348 | case RTL_GIGA_MAC_VER_51: | |
6349 | rtl_hw_start_8168ep_3(tp); | |
6350 | break; | |
6351 | ||
219a1e9d FR |
6352 | default: |
6353 | printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n", | |
6354 | dev->name, tp->mac_version); | |
4804b3b3 | 6355 | break; |
219a1e9d | 6356 | } |
2dd99530 | 6357 | |
1a964649 | 6358 | RTL_W8(Cfg9346, Cfg9346_Lock); |
6359 | ||
0e485150 FR |
6360 | RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); |
6361 | ||
1a964649 | 6362 | rtl_set_rx_mode(dev); |
b8363901 | 6363 | |
05b9687b | 6364 | RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000); |
07ce4064 | 6365 | } |
1da177e4 | 6366 | |
2857ffb7 FR |
6367 | #define R810X_CPCMD_QUIRK_MASK (\ |
6368 | EnableBist | \ | |
6369 | Mac_dbgo_oe | \ | |
6370 | Force_half_dup | \ | |
5edcc537 | 6371 | Force_rxflow_en | \ |
2857ffb7 FR |
6372 | Force_txflow_en | \ |
6373 | Cxpl_dbg_sel | \ | |
6374 | ASF | \ | |
6375 | PktCntrDisable | \ | |
d24e9aaf | 6376 | Mac_dbgo_sel) |
2857ffb7 | 6377 | |
beb1fe18 | 6378 | static void rtl_hw_start_8102e_1(struct rtl8169_private *tp) |
2857ffb7 | 6379 | { |
beb1fe18 HW |
6380 | void __iomem *ioaddr = tp->mmio_addr; |
6381 | struct pci_dev *pdev = tp->pci_dev; | |
350f7596 | 6382 | static const struct ephy_info e_info_8102e_1[] = { |
2857ffb7 FR |
6383 | { 0x01, 0, 0x6e65 }, |
6384 | { 0x02, 0, 0x091f }, | |
6385 | { 0x03, 0, 0xc2f9 }, | |
6386 | { 0x06, 0, 0xafb5 }, | |
6387 | { 0x07, 0, 0x0e00 }, | |
6388 | { 0x19, 0, 0xec80 }, | |
6389 | { 0x01, 0, 0x2e65 }, | |
6390 | { 0x01, 0, 0x6e65 } | |
6391 | }; | |
6392 | u8 cfg1; | |
6393 | ||
beb1fe18 | 6394 | rtl_csi_access_enable_2(tp); |
2857ffb7 FR |
6395 | |
6396 | RTL_W8(DBG_REG, FIX_NAK_1); | |
6397 | ||
6398 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
6399 | ||
6400 | RTL_W8(Config1, | |
6401 | LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable); | |
6402 | RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); | |
6403 | ||
6404 | cfg1 = RTL_R8(Config1); | |
6405 | if ((cfg1 & LEDS0) && (cfg1 & LEDS1)) | |
6406 | RTL_W8(Config1, cfg1 & ~LEDS0); | |
6407 | ||
fdf6fc06 | 6408 | rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1)); |
2857ffb7 FR |
6409 | } |
6410 | ||
beb1fe18 | 6411 | static void rtl_hw_start_8102e_2(struct rtl8169_private *tp) |
2857ffb7 | 6412 | { |
beb1fe18 HW |
6413 | void __iomem *ioaddr = tp->mmio_addr; |
6414 | struct pci_dev *pdev = tp->pci_dev; | |
6415 | ||
6416 | rtl_csi_access_enable_2(tp); | |
2857ffb7 FR |
6417 | |
6418 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
6419 | ||
6420 | RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable); | |
6421 | RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); | |
2857ffb7 FR |
6422 | } |
6423 | ||
beb1fe18 | 6424 | static void rtl_hw_start_8102e_3(struct rtl8169_private *tp) |
2857ffb7 | 6425 | { |
beb1fe18 | 6426 | rtl_hw_start_8102e_2(tp); |
2857ffb7 | 6427 | |
fdf6fc06 | 6428 | rtl_ephy_write(tp, 0x03, 0xc2f9); |
2857ffb7 FR |
6429 | } |
6430 | ||
beb1fe18 | 6431 | static void rtl_hw_start_8105e_1(struct rtl8169_private *tp) |
5a5e4443 | 6432 | { |
beb1fe18 | 6433 | void __iomem *ioaddr = tp->mmio_addr; |
5a5e4443 HW |
6434 | static const struct ephy_info e_info_8105e_1[] = { |
6435 | { 0x07, 0, 0x4000 }, | |
6436 | { 0x19, 0, 0x0200 }, | |
6437 | { 0x19, 0, 0x0020 }, | |
6438 | { 0x1e, 0, 0x2000 }, | |
6439 | { 0x03, 0, 0x0001 }, | |
6440 | { 0x19, 0, 0x0100 }, | |
6441 | { 0x19, 0, 0x0004 }, | |
6442 | { 0x0a, 0, 0x0020 } | |
6443 | }; | |
6444 | ||
cecb5fd7 | 6445 | /* Force LAN exit from ASPM if Rx/Tx are not idle */ |
5a5e4443 HW |
6446 | RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800); |
6447 | ||
cecb5fd7 | 6448 | /* Disable Early Tally Counter */ |
5a5e4443 HW |
6449 | RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000); |
6450 | ||
6451 | RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET); | |
4f6b00e5 | 6452 | RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN); |
5a5e4443 | 6453 | |
fdf6fc06 | 6454 | rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1)); |
b51ecea8 | 6455 | |
6456 | rtl_pcie_state_l2l3_enable(tp, false); | |
5a5e4443 HW |
6457 | } |
6458 | ||
beb1fe18 | 6459 | static void rtl_hw_start_8105e_2(struct rtl8169_private *tp) |
5a5e4443 | 6460 | { |
beb1fe18 | 6461 | rtl_hw_start_8105e_1(tp); |
fdf6fc06 | 6462 | rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000); |
5a5e4443 HW |
6463 | } |
6464 | ||
7e18dca1 HW |
6465 | static void rtl_hw_start_8402(struct rtl8169_private *tp) |
6466 | { | |
6467 | void __iomem *ioaddr = tp->mmio_addr; | |
6468 | static const struct ephy_info e_info_8402[] = { | |
6469 | { 0x19, 0xffff, 0xff64 }, | |
6470 | { 0x1e, 0, 0x4000 } | |
6471 | }; | |
6472 | ||
6473 | rtl_csi_access_enable_2(tp); | |
6474 | ||
6475 | /* Force LAN exit from ASPM if Rx/Tx are not idle */ | |
6476 | RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800); | |
6477 | ||
6478 | RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO); | |
6479 | RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB); | |
6480 | ||
fdf6fc06 | 6481 | rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402)); |
7e18dca1 HW |
6482 | |
6483 | rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
6484 | ||
fdf6fc06 FR |
6485 | rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC); |
6486 | rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC); | |
706123d0 CHL |
6487 | rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC); |
6488 | rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC); | |
fdf6fc06 FR |
6489 | rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); |
6490 | rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); | |
706123d0 | 6491 | rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC); |
b51ecea8 | 6492 | |
6493 | rtl_pcie_state_l2l3_enable(tp, false); | |
7e18dca1 HW |
6494 | } |
6495 | ||
5598bfe5 HW |
6496 | static void rtl_hw_start_8106(struct rtl8169_private *tp) |
6497 | { | |
6498 | void __iomem *ioaddr = tp->mmio_addr; | |
6499 | ||
6500 | /* Force LAN exit from ASPM if Rx/Tx are not idle */ | |
6501 | RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800); | |
6502 | ||
4521e1a9 | 6503 | RTL_W32(MISC, (RTL_R32(MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN); |
5598bfe5 HW |
6504 | RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET); |
6505 | RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN); | |
b51ecea8 | 6506 | |
6507 | rtl_pcie_state_l2l3_enable(tp, false); | |
5598bfe5 HW |
6508 | } |
6509 | ||
07ce4064 FR |
6510 | static void rtl_hw_start_8101(struct net_device *dev) |
6511 | { | |
cdf1a608 FR |
6512 | struct rtl8169_private *tp = netdev_priv(dev); |
6513 | void __iomem *ioaddr = tp->mmio_addr; | |
6514 | struct pci_dev *pdev = tp->pci_dev; | |
6515 | ||
da78dbff FR |
6516 | if (tp->mac_version >= RTL_GIGA_MAC_VER_30) |
6517 | tp->event_slow &= ~RxFIFOOver; | |
811fd301 | 6518 | |
cecb5fd7 | 6519 | if (tp->mac_version == RTL_GIGA_MAC_VER_13 || |
7d7903b2 | 6520 | tp->mac_version == RTL_GIGA_MAC_VER_16) |
8200bc72 BH |
6521 | pcie_capability_set_word(pdev, PCI_EXP_DEVCTL, |
6522 | PCI_EXP_DEVCTL_NOSNOOP_EN); | |
cdf1a608 | 6523 | |
d24e9aaf HW |
6524 | RTL_W8(Cfg9346, Cfg9346_Unlock); |
6525 | ||
1a964649 | 6526 | RTL_W8(MaxTxPacketSize, TxPacketMax); |
6527 | ||
6528 | rtl_set_rx_max_size(ioaddr, rx_buf_sz); | |
6529 | ||
6530 | tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK; | |
6531 | RTL_W16(CPlusCmd, tp->cp_cmd); | |
6532 | ||
6533 | rtl_set_rx_tx_desc_registers(tp, ioaddr); | |
6534 | ||
6535 | rtl_set_rx_tx_config_registers(tp); | |
6536 | ||
2857ffb7 FR |
6537 | switch (tp->mac_version) { |
6538 | case RTL_GIGA_MAC_VER_07: | |
beb1fe18 | 6539 | rtl_hw_start_8102e_1(tp); |
2857ffb7 FR |
6540 | break; |
6541 | ||
6542 | case RTL_GIGA_MAC_VER_08: | |
beb1fe18 | 6543 | rtl_hw_start_8102e_3(tp); |
2857ffb7 FR |
6544 | break; |
6545 | ||
6546 | case RTL_GIGA_MAC_VER_09: | |
beb1fe18 | 6547 | rtl_hw_start_8102e_2(tp); |
2857ffb7 | 6548 | break; |
5a5e4443 HW |
6549 | |
6550 | case RTL_GIGA_MAC_VER_29: | |
beb1fe18 | 6551 | rtl_hw_start_8105e_1(tp); |
5a5e4443 HW |
6552 | break; |
6553 | case RTL_GIGA_MAC_VER_30: | |
beb1fe18 | 6554 | rtl_hw_start_8105e_2(tp); |
5a5e4443 | 6555 | break; |
7e18dca1 HW |
6556 | |
6557 | case RTL_GIGA_MAC_VER_37: | |
6558 | rtl_hw_start_8402(tp); | |
6559 | break; | |
5598bfe5 HW |
6560 | |
6561 | case RTL_GIGA_MAC_VER_39: | |
6562 | rtl_hw_start_8106(tp); | |
6563 | break; | |
58152cd4 | 6564 | case RTL_GIGA_MAC_VER_43: |
6565 | rtl_hw_start_8168g_2(tp); | |
6566 | break; | |
6e1d0b89 CHL |
6567 | case RTL_GIGA_MAC_VER_47: |
6568 | case RTL_GIGA_MAC_VER_48: | |
6569 | rtl_hw_start_8168h_1(tp); | |
6570 | break; | |
cdf1a608 FR |
6571 | } |
6572 | ||
d24e9aaf | 6573 | RTL_W8(Cfg9346, Cfg9346_Lock); |
cdf1a608 | 6574 | |
cdf1a608 FR |
6575 | RTL_W16(IntrMitigate, 0x0000); |
6576 | ||
cdf1a608 | 6577 | RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); |
cdf1a608 | 6578 | |
cdf1a608 FR |
6579 | rtl_set_rx_mode(dev); |
6580 | ||
1a964649 | 6581 | RTL_R8(IntrMask); |
6582 | ||
cdf1a608 | 6583 | RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000); |
1da177e4 LT |
6584 | } |
6585 | ||
6586 | static int rtl8169_change_mtu(struct net_device *dev, int new_mtu) | |
6587 | { | |
d58d46b5 FR |
6588 | struct rtl8169_private *tp = netdev_priv(dev); |
6589 | ||
6590 | if (new_mtu < ETH_ZLEN || | |
6591 | new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max) | |
1da177e4 LT |
6592 | return -EINVAL; |
6593 | ||
d58d46b5 FR |
6594 | if (new_mtu > ETH_DATA_LEN) |
6595 | rtl_hw_jumbo_enable(tp); | |
6596 | else | |
6597 | rtl_hw_jumbo_disable(tp); | |
6598 | ||
1da177e4 | 6599 | dev->mtu = new_mtu; |
350fb32a MM |
6600 | netdev_update_features(dev); |
6601 | ||
323bb685 | 6602 | return 0; |
1da177e4 LT |
6603 | } |
6604 | ||
6605 | static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc) | |
6606 | { | |
95e0918d | 6607 | desc->addr = cpu_to_le64(0x0badbadbadbadbadull); |
1da177e4 LT |
6608 | desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask); |
6609 | } | |
6610 | ||
6f0333b8 ED |
6611 | static void rtl8169_free_rx_databuff(struct rtl8169_private *tp, |
6612 | void **data_buff, struct RxDesc *desc) | |
1da177e4 | 6613 | { |
48addcc9 | 6614 | dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz, |
231aee63 | 6615 | DMA_FROM_DEVICE); |
48addcc9 | 6616 | |
6f0333b8 ED |
6617 | kfree(*data_buff); |
6618 | *data_buff = NULL; | |
1da177e4 LT |
6619 | rtl8169_make_unusable_by_asic(desc); |
6620 | } | |
6621 | ||
6622 | static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz) | |
6623 | { | |
6624 | u32 eor = le32_to_cpu(desc->opts1) & RingEnd; | |
6625 | ||
a0750138 AD |
6626 | /* Force memory writes to complete before releasing descriptor */ |
6627 | dma_wmb(); | |
6628 | ||
1da177e4 LT |
6629 | desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz); |
6630 | } | |
6631 | ||
6632 | static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping, | |
6633 | u32 rx_buf_sz) | |
6634 | { | |
6635 | desc->addr = cpu_to_le64(mapping); | |
1da177e4 LT |
6636 | rtl8169_mark_to_asic(desc, rx_buf_sz); |
6637 | } | |
6638 | ||
6f0333b8 ED |
6639 | static inline void *rtl8169_align(void *data) |
6640 | { | |
6641 | return (void *)ALIGN((long)data, 16); | |
6642 | } | |
6643 | ||
0ecbe1ca SG |
6644 | static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp, |
6645 | struct RxDesc *desc) | |
1da177e4 | 6646 | { |
6f0333b8 | 6647 | void *data; |
1da177e4 | 6648 | dma_addr_t mapping; |
48addcc9 | 6649 | struct device *d = &tp->pci_dev->dev; |
0ecbe1ca | 6650 | struct net_device *dev = tp->dev; |
6f0333b8 | 6651 | int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1; |
1da177e4 | 6652 | |
6f0333b8 ED |
6653 | data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node); |
6654 | if (!data) | |
6655 | return NULL; | |
e9f63f30 | 6656 | |
6f0333b8 ED |
6657 | if (rtl8169_align(data) != data) { |
6658 | kfree(data); | |
6659 | data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node); | |
6660 | if (!data) | |
6661 | return NULL; | |
6662 | } | |
3eafe507 | 6663 | |
48addcc9 | 6664 | mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz, |
231aee63 | 6665 | DMA_FROM_DEVICE); |
d827d86b SG |
6666 | if (unlikely(dma_mapping_error(d, mapping))) { |
6667 | if (net_ratelimit()) | |
6668 | netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n"); | |
3eafe507 | 6669 | goto err_out; |
d827d86b | 6670 | } |
1da177e4 LT |
6671 | |
6672 | rtl8169_map_to_asic(desc, mapping, rx_buf_sz); | |
6f0333b8 | 6673 | return data; |
3eafe507 SG |
6674 | |
6675 | err_out: | |
6676 | kfree(data); | |
6677 | return NULL; | |
1da177e4 LT |
6678 | } |
6679 | ||
6680 | static void rtl8169_rx_clear(struct rtl8169_private *tp) | |
6681 | { | |
07d3f51f | 6682 | unsigned int i; |
1da177e4 LT |
6683 | |
6684 | for (i = 0; i < NUM_RX_DESC; i++) { | |
6f0333b8 ED |
6685 | if (tp->Rx_databuff[i]) { |
6686 | rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i, | |
1da177e4 LT |
6687 | tp->RxDescArray + i); |
6688 | } | |
6689 | } | |
6690 | } | |
6691 | ||
0ecbe1ca | 6692 | static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc) |
1da177e4 | 6693 | { |
0ecbe1ca SG |
6694 | desc->opts1 |= cpu_to_le32(RingEnd); |
6695 | } | |
5b0384f4 | 6696 | |
0ecbe1ca SG |
6697 | static int rtl8169_rx_fill(struct rtl8169_private *tp) |
6698 | { | |
6699 | unsigned int i; | |
1da177e4 | 6700 | |
0ecbe1ca SG |
6701 | for (i = 0; i < NUM_RX_DESC; i++) { |
6702 | void *data; | |
4ae47c2d | 6703 | |
6f0333b8 | 6704 | if (tp->Rx_databuff[i]) |
1da177e4 | 6705 | continue; |
bcf0bf90 | 6706 | |
0ecbe1ca | 6707 | data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i); |
6f0333b8 ED |
6708 | if (!data) { |
6709 | rtl8169_make_unusable_by_asic(tp->RxDescArray + i); | |
0ecbe1ca | 6710 | goto err_out; |
6f0333b8 ED |
6711 | } |
6712 | tp->Rx_databuff[i] = data; | |
1da177e4 | 6713 | } |
1da177e4 | 6714 | |
0ecbe1ca SG |
6715 | rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1); |
6716 | return 0; | |
6717 | ||
6718 | err_out: | |
6719 | rtl8169_rx_clear(tp); | |
6720 | return -ENOMEM; | |
1da177e4 LT |
6721 | } |
6722 | ||
1da177e4 LT |
6723 | static int rtl8169_init_ring(struct net_device *dev) |
6724 | { | |
6725 | struct rtl8169_private *tp = netdev_priv(dev); | |
6726 | ||
6727 | rtl8169_init_ring_indexes(tp); | |
6728 | ||
6729 | memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info)); | |
6f0333b8 | 6730 | memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *)); |
1da177e4 | 6731 | |
0ecbe1ca | 6732 | return rtl8169_rx_fill(tp); |
1da177e4 LT |
6733 | } |
6734 | ||
48addcc9 | 6735 | static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb, |
1da177e4 LT |
6736 | struct TxDesc *desc) |
6737 | { | |
6738 | unsigned int len = tx_skb->len; | |
6739 | ||
48addcc9 SG |
6740 | dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE); |
6741 | ||
1da177e4 LT |
6742 | desc->opts1 = 0x00; |
6743 | desc->opts2 = 0x00; | |
6744 | desc->addr = 0x00; | |
6745 | tx_skb->len = 0; | |
6746 | } | |
6747 | ||
3eafe507 SG |
6748 | static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start, |
6749 | unsigned int n) | |
1da177e4 LT |
6750 | { |
6751 | unsigned int i; | |
6752 | ||
3eafe507 SG |
6753 | for (i = 0; i < n; i++) { |
6754 | unsigned int entry = (start + i) % NUM_TX_DESC; | |
1da177e4 LT |
6755 | struct ring_info *tx_skb = tp->tx_skb + entry; |
6756 | unsigned int len = tx_skb->len; | |
6757 | ||
6758 | if (len) { | |
6759 | struct sk_buff *skb = tx_skb->skb; | |
6760 | ||
48addcc9 | 6761 | rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb, |
1da177e4 LT |
6762 | tp->TxDescArray + entry); |
6763 | if (skb) { | |
cac4b22f | 6764 | tp->dev->stats.tx_dropped++; |
989c9ba1 | 6765 | dev_kfree_skb_any(skb); |
1da177e4 LT |
6766 | tx_skb->skb = NULL; |
6767 | } | |
1da177e4 LT |
6768 | } |
6769 | } | |
3eafe507 SG |
6770 | } |
6771 | ||
6772 | static void rtl8169_tx_clear(struct rtl8169_private *tp) | |
6773 | { | |
6774 | rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC); | |
1da177e4 LT |
6775 | tp->cur_tx = tp->dirty_tx = 0; |
6776 | } | |
6777 | ||
4422bcd4 | 6778 | static void rtl_reset_work(struct rtl8169_private *tp) |
1da177e4 | 6779 | { |
c4028958 | 6780 | struct net_device *dev = tp->dev; |
56de414c | 6781 | int i; |
1da177e4 | 6782 | |
da78dbff FR |
6783 | napi_disable(&tp->napi); |
6784 | netif_stop_queue(dev); | |
6785 | synchronize_sched(); | |
1da177e4 | 6786 | |
c7c2c39b | 6787 | rtl8169_hw_reset(tp); |
6788 | ||
56de414c FR |
6789 | for (i = 0; i < NUM_RX_DESC; i++) |
6790 | rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz); | |
6791 | ||
1da177e4 | 6792 | rtl8169_tx_clear(tp); |
c7c2c39b | 6793 | rtl8169_init_ring_indexes(tp); |
1da177e4 | 6794 | |
da78dbff | 6795 | napi_enable(&tp->napi); |
56de414c FR |
6796 | rtl_hw_start(dev); |
6797 | netif_wake_queue(dev); | |
6798 | rtl8169_check_link_status(dev, tp, tp->mmio_addr); | |
1da177e4 LT |
6799 | } |
6800 | ||
6801 | static void rtl8169_tx_timeout(struct net_device *dev) | |
6802 | { | |
da78dbff FR |
6803 | struct rtl8169_private *tp = netdev_priv(dev); |
6804 | ||
6805 | rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); | |
1da177e4 LT |
6806 | } |
6807 | ||
6808 | static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb, | |
2b7b4318 | 6809 | u32 *opts) |
1da177e4 LT |
6810 | { |
6811 | struct skb_shared_info *info = skb_shinfo(skb); | |
6812 | unsigned int cur_frag, entry; | |
6e1d0b89 | 6813 | struct TxDesc *uninitialized_var(txd); |
48addcc9 | 6814 | struct device *d = &tp->pci_dev->dev; |
1da177e4 LT |
6815 | |
6816 | entry = tp->cur_tx; | |
6817 | for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) { | |
9e903e08 | 6818 | const skb_frag_t *frag = info->frags + cur_frag; |
1da177e4 LT |
6819 | dma_addr_t mapping; |
6820 | u32 status, len; | |
6821 | void *addr; | |
6822 | ||
6823 | entry = (entry + 1) % NUM_TX_DESC; | |
6824 | ||
6825 | txd = tp->TxDescArray + entry; | |
9e903e08 | 6826 | len = skb_frag_size(frag); |
929f6189 | 6827 | addr = skb_frag_address(frag); |
48addcc9 | 6828 | mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE); |
d827d86b SG |
6829 | if (unlikely(dma_mapping_error(d, mapping))) { |
6830 | if (net_ratelimit()) | |
6831 | netif_err(tp, drv, tp->dev, | |
6832 | "Failed to map TX fragments DMA!\n"); | |
3eafe507 | 6833 | goto err_out; |
d827d86b | 6834 | } |
1da177e4 | 6835 | |
cecb5fd7 | 6836 | /* Anti gcc 2.95.3 bugware (sic) */ |
2b7b4318 FR |
6837 | status = opts[0] | len | |
6838 | (RingEnd * !((entry + 1) % NUM_TX_DESC)); | |
1da177e4 LT |
6839 | |
6840 | txd->opts1 = cpu_to_le32(status); | |
2b7b4318 | 6841 | txd->opts2 = cpu_to_le32(opts[1]); |
1da177e4 LT |
6842 | txd->addr = cpu_to_le64(mapping); |
6843 | ||
6844 | tp->tx_skb[entry].len = len; | |
6845 | } | |
6846 | ||
6847 | if (cur_frag) { | |
6848 | tp->tx_skb[entry].skb = skb; | |
6849 | txd->opts1 |= cpu_to_le32(LastFrag); | |
6850 | } | |
6851 | ||
6852 | return cur_frag; | |
3eafe507 SG |
6853 | |
6854 | err_out: | |
6855 | rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag); | |
6856 | return -EIO; | |
1da177e4 LT |
6857 | } |
6858 | ||
b423e9ae | 6859 | static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb) |
6860 | { | |
6861 | return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34; | |
6862 | } | |
6863 | ||
e974604b | 6864 | static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb, |
6865 | struct net_device *dev); | |
6866 | /* r8169_csum_workaround() | |
6867 | * The hw limites the value the transport offset. When the offset is out of the | |
6868 | * range, calculate the checksum by sw. | |
6869 | */ | |
6870 | static void r8169_csum_workaround(struct rtl8169_private *tp, | |
6871 | struct sk_buff *skb) | |
6872 | { | |
6873 | if (skb_shinfo(skb)->gso_size) { | |
6874 | netdev_features_t features = tp->dev->features; | |
6875 | struct sk_buff *segs, *nskb; | |
6876 | ||
6877 | features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6); | |
6878 | segs = skb_gso_segment(skb, features); | |
6879 | if (IS_ERR(segs) || !segs) | |
6880 | goto drop; | |
6881 | ||
6882 | do { | |
6883 | nskb = segs; | |
6884 | segs = segs->next; | |
6885 | nskb->next = NULL; | |
6886 | rtl8169_start_xmit(nskb, tp->dev); | |
6887 | } while (segs); | |
6888 | ||
6889 | dev_kfree_skb(skb); | |
6890 | } else if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
6891 | if (skb_checksum_help(skb) < 0) | |
6892 | goto drop; | |
6893 | ||
6894 | rtl8169_start_xmit(skb, tp->dev); | |
6895 | } else { | |
6896 | struct net_device_stats *stats; | |
6897 | ||
6898 | drop: | |
6899 | stats = &tp->dev->stats; | |
6900 | stats->tx_dropped++; | |
6901 | dev_kfree_skb(skb); | |
6902 | } | |
6903 | } | |
6904 | ||
6905 | /* msdn_giant_send_check() | |
6906 | * According to the document of microsoft, the TCP Pseudo Header excludes the | |
6907 | * packet length for IPv6 TCP large packets. | |
6908 | */ | |
6909 | static int msdn_giant_send_check(struct sk_buff *skb) | |
6910 | { | |
6911 | const struct ipv6hdr *ipv6h; | |
6912 | struct tcphdr *th; | |
6913 | int ret; | |
6914 | ||
6915 | ret = skb_cow_head(skb, 0); | |
6916 | if (ret) | |
6917 | return ret; | |
6918 | ||
6919 | ipv6h = ipv6_hdr(skb); | |
6920 | th = tcp_hdr(skb); | |
6921 | ||
6922 | th->check = 0; | |
6923 | th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0); | |
6924 | ||
6925 | return ret; | |
6926 | } | |
6927 | ||
6928 | static inline __be16 get_protocol(struct sk_buff *skb) | |
6929 | { | |
6930 | __be16 protocol; | |
6931 | ||
6932 | if (skb->protocol == htons(ETH_P_8021Q)) | |
6933 | protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto; | |
6934 | else | |
6935 | protocol = skb->protocol; | |
6936 | ||
6937 | return protocol; | |
6938 | } | |
6939 | ||
5888d3fc | 6940 | static bool rtl8169_tso_csum_v1(struct rtl8169_private *tp, |
6941 | struct sk_buff *skb, u32 *opts) | |
1da177e4 | 6942 | { |
350fb32a MM |
6943 | u32 mss = skb_shinfo(skb)->gso_size; |
6944 | ||
2b7b4318 FR |
6945 | if (mss) { |
6946 | opts[0] |= TD_LSO; | |
5888d3fc | 6947 | opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT; |
6948 | } else if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
6949 | const struct iphdr *ip = ip_hdr(skb); | |
6950 | ||
6951 | if (ip->protocol == IPPROTO_TCP) | |
6952 | opts[0] |= TD0_IP_CS | TD0_TCP_CS; | |
6953 | else if (ip->protocol == IPPROTO_UDP) | |
6954 | opts[0] |= TD0_IP_CS | TD0_UDP_CS; | |
6955 | else | |
6956 | WARN_ON_ONCE(1); | |
6957 | } | |
6958 | ||
6959 | return true; | |
6960 | } | |
6961 | ||
6962 | static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp, | |
6963 | struct sk_buff *skb, u32 *opts) | |
6964 | { | |
bdfa4ed6 | 6965 | u32 transport_offset = (u32)skb_transport_offset(skb); |
5888d3fc | 6966 | u32 mss = skb_shinfo(skb)->gso_size; |
6967 | ||
6968 | if (mss) { | |
e974604b | 6969 | if (transport_offset > GTTCPHO_MAX) { |
6970 | netif_warn(tp, tx_err, tp->dev, | |
6971 | "Invalid transport offset 0x%x for TSO\n", | |
6972 | transport_offset); | |
6973 | return false; | |
6974 | } | |
6975 | ||
6976 | switch (get_protocol(skb)) { | |
6977 | case htons(ETH_P_IP): | |
6978 | opts[0] |= TD1_GTSENV4; | |
6979 | break; | |
6980 | ||
6981 | case htons(ETH_P_IPV6): | |
6982 | if (msdn_giant_send_check(skb)) | |
6983 | return false; | |
6984 | ||
6985 | opts[0] |= TD1_GTSENV6; | |
6986 | break; | |
6987 | ||
6988 | default: | |
6989 | WARN_ON_ONCE(1); | |
6990 | break; | |
6991 | } | |
6992 | ||
bdfa4ed6 | 6993 | opts[0] |= transport_offset << GTTCPHO_SHIFT; |
5888d3fc | 6994 | opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT; |
2b7b4318 | 6995 | } else if (skb->ip_summed == CHECKSUM_PARTIAL) { |
e974604b | 6996 | u8 ip_protocol; |
1da177e4 | 6997 | |
b423e9ae | 6998 | if (unlikely(rtl_test_hw_pad_bug(tp, skb))) |
207c5f44 | 6999 | return !(skb_checksum_help(skb) || eth_skb_pad(skb)); |
b423e9ae | 7000 | |
e974604b | 7001 | if (transport_offset > TCPHO_MAX) { |
7002 | netif_warn(tp, tx_err, tp->dev, | |
7003 | "Invalid transport offset 0x%x\n", | |
7004 | transport_offset); | |
7005 | return false; | |
7006 | } | |
7007 | ||
7008 | switch (get_protocol(skb)) { | |
7009 | case htons(ETH_P_IP): | |
7010 | opts[1] |= TD1_IPv4_CS; | |
7011 | ip_protocol = ip_hdr(skb)->protocol; | |
7012 | break; | |
7013 | ||
7014 | case htons(ETH_P_IPV6): | |
7015 | opts[1] |= TD1_IPv6_CS; | |
7016 | ip_protocol = ipv6_hdr(skb)->nexthdr; | |
7017 | break; | |
7018 | ||
7019 | default: | |
7020 | ip_protocol = IPPROTO_RAW; | |
7021 | break; | |
7022 | } | |
7023 | ||
7024 | if (ip_protocol == IPPROTO_TCP) | |
7025 | opts[1] |= TD1_TCP_CS; | |
7026 | else if (ip_protocol == IPPROTO_UDP) | |
7027 | opts[1] |= TD1_UDP_CS; | |
2b7b4318 FR |
7028 | else |
7029 | WARN_ON_ONCE(1); | |
e974604b | 7030 | |
7031 | opts[1] |= transport_offset << TCPHO_SHIFT; | |
b423e9ae | 7032 | } else { |
7033 | if (unlikely(rtl_test_hw_pad_bug(tp, skb))) | |
207c5f44 | 7034 | return !eth_skb_pad(skb); |
1da177e4 | 7035 | } |
5888d3fc | 7036 | |
b423e9ae | 7037 | return true; |
1da177e4 LT |
7038 | } |
7039 | ||
61357325 SH |
7040 | static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb, |
7041 | struct net_device *dev) | |
1da177e4 LT |
7042 | { |
7043 | struct rtl8169_private *tp = netdev_priv(dev); | |
3eafe507 | 7044 | unsigned int entry = tp->cur_tx % NUM_TX_DESC; |
1da177e4 LT |
7045 | struct TxDesc *txd = tp->TxDescArray + entry; |
7046 | void __iomem *ioaddr = tp->mmio_addr; | |
48addcc9 | 7047 | struct device *d = &tp->pci_dev->dev; |
1da177e4 LT |
7048 | dma_addr_t mapping; |
7049 | u32 status, len; | |
2b7b4318 | 7050 | u32 opts[2]; |
3eafe507 | 7051 | int frags; |
0bec3b70 | 7052 | bool stop_queue; |
5b0384f4 | 7053 | |
477206a0 | 7054 | if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) { |
bf82c189 | 7055 | netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n"); |
3eafe507 | 7056 | goto err_stop_0; |
1da177e4 LT |
7057 | } |
7058 | ||
7059 | if (unlikely(le32_to_cpu(txd->opts1) & DescOwn)) | |
3eafe507 SG |
7060 | goto err_stop_0; |
7061 | ||
b423e9ae | 7062 | opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb)); |
7063 | opts[0] = DescOwn; | |
7064 | ||
e974604b | 7065 | if (!tp->tso_csum(tp, skb, opts)) { |
7066 | r8169_csum_workaround(tp, skb); | |
7067 | return NETDEV_TX_OK; | |
7068 | } | |
b423e9ae | 7069 | |
3eafe507 | 7070 | len = skb_headlen(skb); |
48addcc9 | 7071 | mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE); |
d827d86b SG |
7072 | if (unlikely(dma_mapping_error(d, mapping))) { |
7073 | if (net_ratelimit()) | |
7074 | netif_err(tp, drv, dev, "Failed to map TX DMA!\n"); | |
3eafe507 | 7075 | goto err_dma_0; |
d827d86b | 7076 | } |
3eafe507 SG |
7077 | |
7078 | tp->tx_skb[entry].len = len; | |
7079 | txd->addr = cpu_to_le64(mapping); | |
1da177e4 | 7080 | |
2b7b4318 | 7081 | frags = rtl8169_xmit_frags(tp, skb, opts); |
3eafe507 SG |
7082 | if (frags < 0) |
7083 | goto err_dma_1; | |
7084 | else if (frags) | |
2b7b4318 | 7085 | opts[0] |= FirstFrag; |
3eafe507 | 7086 | else { |
2b7b4318 | 7087 | opts[0] |= FirstFrag | LastFrag; |
1da177e4 LT |
7088 | tp->tx_skb[entry].skb = skb; |
7089 | } | |
7090 | ||
2b7b4318 FR |
7091 | txd->opts2 = cpu_to_le32(opts[1]); |
7092 | ||
1e918876 FW |
7093 | netdev_sent_queue(dev, skb->len); |
7094 | ||
5047fb5d RC |
7095 | skb_tx_timestamp(skb); |
7096 | ||
a0750138 AD |
7097 | /* Force memory writes to complete before releasing descriptor */ |
7098 | dma_wmb(); | |
1da177e4 | 7099 | |
cecb5fd7 | 7100 | /* Anti gcc 2.95.3 bugware (sic) */ |
2b7b4318 | 7101 | status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC)); |
1da177e4 LT |
7102 | txd->opts1 = cpu_to_le32(status); |
7103 | ||
a0750138 | 7104 | /* Force all memory writes to complete before notifying device */ |
4c020a96 | 7105 | wmb(); |
1da177e4 | 7106 | |
a0750138 AD |
7107 | tp->cur_tx += frags + 1; |
7108 | ||
0bec3b70 | 7109 | stop_queue = !TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS); |
1da177e4 | 7110 | |
0bec3b70 FW |
7111 | if (!skb->xmit_more || stop_queue || |
7112 | netif_xmit_stopped(netdev_get_tx_queue(dev, 0))) { | |
7113 | RTL_W8(TxPoll, NPQ); | |
7114 | ||
7115 | mmiowb(); | |
7116 | } | |
da78dbff | 7117 | |
0bec3b70 | 7118 | if (stop_queue) { |
ae1f23fb FR |
7119 | /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must |
7120 | * not miss a ring update when it notices a stopped queue. | |
7121 | */ | |
7122 | smp_wmb(); | |
1da177e4 | 7123 | netif_stop_queue(dev); |
ae1f23fb FR |
7124 | /* Sync with rtl_tx: |
7125 | * - publish queue status and cur_tx ring index (write barrier) | |
7126 | * - refresh dirty_tx ring index (read barrier). | |
7127 | * May the current thread have a pessimistic view of the ring | |
7128 | * status and forget to wake up queue, a racing rtl_tx thread | |
7129 | * can't. | |
7130 | */ | |
1e874e04 | 7131 | smp_mb(); |
477206a0 | 7132 | if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) |
1da177e4 LT |
7133 | netif_wake_queue(dev); |
7134 | } | |
7135 | ||
61357325 | 7136 | return NETDEV_TX_OK; |
1da177e4 | 7137 | |
3eafe507 | 7138 | err_dma_1: |
48addcc9 | 7139 | rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd); |
3eafe507 | 7140 | err_dma_0: |
989c9ba1 | 7141 | dev_kfree_skb_any(skb); |
3eafe507 SG |
7142 | dev->stats.tx_dropped++; |
7143 | return NETDEV_TX_OK; | |
7144 | ||
7145 | err_stop_0: | |
1da177e4 | 7146 | netif_stop_queue(dev); |
cebf8cc7 | 7147 | dev->stats.tx_dropped++; |
61357325 | 7148 | return NETDEV_TX_BUSY; |
1da177e4 LT |
7149 | } |
7150 | ||
7151 | static void rtl8169_pcierr_interrupt(struct net_device *dev) | |
7152 | { | |
7153 | struct rtl8169_private *tp = netdev_priv(dev); | |
7154 | struct pci_dev *pdev = tp->pci_dev; | |
1da177e4 LT |
7155 | u16 pci_status, pci_cmd; |
7156 | ||
7157 | pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); | |
7158 | pci_read_config_word(pdev, PCI_STATUS, &pci_status); | |
7159 | ||
bf82c189 JP |
7160 | netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n", |
7161 | pci_cmd, pci_status); | |
1da177e4 LT |
7162 | |
7163 | /* | |
7164 | * The recovery sequence below admits a very elaborated explanation: | |
7165 | * - it seems to work; | |
d03902b8 FR |
7166 | * - I did not see what else could be done; |
7167 | * - it makes iop3xx happy. | |
1da177e4 LT |
7168 | * |
7169 | * Feel free to adjust to your needs. | |
7170 | */ | |
a27993f3 | 7171 | if (pdev->broken_parity_status) |
d03902b8 FR |
7172 | pci_cmd &= ~PCI_COMMAND_PARITY; |
7173 | else | |
7174 | pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY; | |
7175 | ||
7176 | pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); | |
1da177e4 LT |
7177 | |
7178 | pci_write_config_word(pdev, PCI_STATUS, | |
7179 | pci_status & (PCI_STATUS_DETECTED_PARITY | | |
7180 | PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT | | |
7181 | PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT)); | |
7182 | ||
7183 | /* The infamous DAC f*ckup only happens at boot time */ | |
9fba0812 | 7184 | if ((tp->cp_cmd & PCIDAC) && !tp->cur_rx) { |
e6de30d6 | 7185 | void __iomem *ioaddr = tp->mmio_addr; |
7186 | ||
bf82c189 | 7187 | netif_info(tp, intr, dev, "disabling PCI DAC\n"); |
1da177e4 LT |
7188 | tp->cp_cmd &= ~PCIDAC; |
7189 | RTL_W16(CPlusCmd, tp->cp_cmd); | |
7190 | dev->features &= ~NETIF_F_HIGHDMA; | |
1da177e4 LT |
7191 | } |
7192 | ||
e6de30d6 | 7193 | rtl8169_hw_reset(tp); |
d03902b8 | 7194 | |
98ddf986 | 7195 | rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); |
1da177e4 LT |
7196 | } |
7197 | ||
da78dbff | 7198 | static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp) |
1da177e4 LT |
7199 | { |
7200 | unsigned int dirty_tx, tx_left; | |
1e918876 | 7201 | unsigned int bytes_compl = 0, pkts_compl = 0; |
1da177e4 | 7202 | |
1da177e4 LT |
7203 | dirty_tx = tp->dirty_tx; |
7204 | smp_rmb(); | |
7205 | tx_left = tp->cur_tx - dirty_tx; | |
7206 | ||
7207 | while (tx_left > 0) { | |
7208 | unsigned int entry = dirty_tx % NUM_TX_DESC; | |
7209 | struct ring_info *tx_skb = tp->tx_skb + entry; | |
1da177e4 LT |
7210 | u32 status; |
7211 | ||
1da177e4 LT |
7212 | status = le32_to_cpu(tp->TxDescArray[entry].opts1); |
7213 | if (status & DescOwn) | |
7214 | break; | |
7215 | ||
a0750138 AD |
7216 | /* This barrier is needed to keep us from reading |
7217 | * any other fields out of the Tx descriptor until | |
7218 | * we know the status of DescOwn | |
7219 | */ | |
7220 | dma_rmb(); | |
7221 | ||
48addcc9 SG |
7222 | rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb, |
7223 | tp->TxDescArray + entry); | |
1da177e4 | 7224 | if (status & LastFrag) { |
1e918876 FW |
7225 | pkts_compl++; |
7226 | bytes_compl += tx_skb->skb->len; | |
989c9ba1 | 7227 | dev_kfree_skb_any(tx_skb->skb); |
1da177e4 LT |
7228 | tx_skb->skb = NULL; |
7229 | } | |
7230 | dirty_tx++; | |
7231 | tx_left--; | |
7232 | } | |
7233 | ||
7234 | if (tp->dirty_tx != dirty_tx) { | |
1e918876 FW |
7235 | netdev_completed_queue(tp->dev, pkts_compl, bytes_compl); |
7236 | ||
7237 | u64_stats_update_begin(&tp->tx_stats.syncp); | |
7238 | tp->tx_stats.packets += pkts_compl; | |
7239 | tp->tx_stats.bytes += bytes_compl; | |
7240 | u64_stats_update_end(&tp->tx_stats.syncp); | |
7241 | ||
1da177e4 | 7242 | tp->dirty_tx = dirty_tx; |
ae1f23fb FR |
7243 | /* Sync with rtl8169_start_xmit: |
7244 | * - publish dirty_tx ring index (write barrier) | |
7245 | * - refresh cur_tx ring index and queue status (read barrier) | |
7246 | * May the current thread miss the stopped queue condition, | |
7247 | * a racing xmit thread can only have a right view of the | |
7248 | * ring status. | |
7249 | */ | |
1e874e04 | 7250 | smp_mb(); |
1da177e4 | 7251 | if (netif_queue_stopped(dev) && |
477206a0 | 7252 | TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) { |
1da177e4 LT |
7253 | netif_wake_queue(dev); |
7254 | } | |
d78ae2dc FR |
7255 | /* |
7256 | * 8168 hack: TxPoll requests are lost when the Tx packets are | |
7257 | * too close. Let's kick an extra TxPoll request when a burst | |
7258 | * of start_xmit activity is detected (if it is not detected, | |
7259 | * it is slow enough). -- FR | |
7260 | */ | |
da78dbff FR |
7261 | if (tp->cur_tx != dirty_tx) { |
7262 | void __iomem *ioaddr = tp->mmio_addr; | |
7263 | ||
d78ae2dc | 7264 | RTL_W8(TxPoll, NPQ); |
da78dbff | 7265 | } |
1da177e4 LT |
7266 | } |
7267 | } | |
7268 | ||
126fa4b9 FR |
7269 | static inline int rtl8169_fragmented_frame(u32 status) |
7270 | { | |
7271 | return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag); | |
7272 | } | |
7273 | ||
adea1ac7 | 7274 | static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1) |
1da177e4 | 7275 | { |
1da177e4 LT |
7276 | u32 status = opts1 & RxProtoMask; |
7277 | ||
7278 | if (((status == RxProtoTCP) && !(opts1 & TCPFail)) || | |
d5d3ebe3 | 7279 | ((status == RxProtoUDP) && !(opts1 & UDPFail))) |
1da177e4 LT |
7280 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
7281 | else | |
bc8acf2c | 7282 | skb_checksum_none_assert(skb); |
1da177e4 LT |
7283 | } |
7284 | ||
6f0333b8 ED |
7285 | static struct sk_buff *rtl8169_try_rx_copy(void *data, |
7286 | struct rtl8169_private *tp, | |
7287 | int pkt_size, | |
7288 | dma_addr_t addr) | |
1da177e4 | 7289 | { |
b449655f | 7290 | struct sk_buff *skb; |
48addcc9 | 7291 | struct device *d = &tp->pci_dev->dev; |
b449655f | 7292 | |
6f0333b8 | 7293 | data = rtl8169_align(data); |
48addcc9 | 7294 | dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE); |
6f0333b8 | 7295 | prefetch(data); |
e2338f86 | 7296 | skb = napi_alloc_skb(&tp->napi, pkt_size); |
6f0333b8 ED |
7297 | if (skb) |
7298 | memcpy(skb->data, data, pkt_size); | |
48addcc9 SG |
7299 | dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE); |
7300 | ||
6f0333b8 | 7301 | return skb; |
1da177e4 LT |
7302 | } |
7303 | ||
da78dbff | 7304 | static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget) |
1da177e4 LT |
7305 | { |
7306 | unsigned int cur_rx, rx_left; | |
6f0333b8 | 7307 | unsigned int count; |
1da177e4 | 7308 | |
1da177e4 | 7309 | cur_rx = tp->cur_rx; |
1da177e4 | 7310 | |
9fba0812 | 7311 | for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) { |
1da177e4 | 7312 | unsigned int entry = cur_rx % NUM_RX_DESC; |
126fa4b9 | 7313 | struct RxDesc *desc = tp->RxDescArray + entry; |
1da177e4 LT |
7314 | u32 status; |
7315 | ||
e03f33af | 7316 | status = le32_to_cpu(desc->opts1) & tp->opts1_mask; |
1da177e4 LT |
7317 | if (status & DescOwn) |
7318 | break; | |
a0750138 AD |
7319 | |
7320 | /* This barrier is needed to keep us from reading | |
7321 | * any other fields out of the Rx descriptor until | |
7322 | * we know the status of DescOwn | |
7323 | */ | |
7324 | dma_rmb(); | |
7325 | ||
4dcb7d33 | 7326 | if (unlikely(status & RxRES)) { |
bf82c189 JP |
7327 | netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n", |
7328 | status); | |
cebf8cc7 | 7329 | dev->stats.rx_errors++; |
1da177e4 | 7330 | if (status & (RxRWT | RxRUNT)) |
cebf8cc7 | 7331 | dev->stats.rx_length_errors++; |
1da177e4 | 7332 | if (status & RxCRC) |
cebf8cc7 | 7333 | dev->stats.rx_crc_errors++; |
9dccf611 | 7334 | if (status & RxFOVF) { |
da78dbff | 7335 | rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); |
cebf8cc7 | 7336 | dev->stats.rx_fifo_errors++; |
9dccf611 | 7337 | } |
6bbe021d BG |
7338 | if ((status & (RxRUNT | RxCRC)) && |
7339 | !(status & (RxRWT | RxFOVF)) && | |
7340 | (dev->features & NETIF_F_RXALL)) | |
7341 | goto process_pkt; | |
1da177e4 | 7342 | } else { |
6f0333b8 | 7343 | struct sk_buff *skb; |
6bbe021d BG |
7344 | dma_addr_t addr; |
7345 | int pkt_size; | |
7346 | ||
7347 | process_pkt: | |
7348 | addr = le64_to_cpu(desc->addr); | |
79d0c1d2 BG |
7349 | if (likely(!(dev->features & NETIF_F_RXFCS))) |
7350 | pkt_size = (status & 0x00003fff) - 4; | |
7351 | else | |
7352 | pkt_size = status & 0x00003fff; | |
1da177e4 | 7353 | |
126fa4b9 FR |
7354 | /* |
7355 | * The driver does not support incoming fragmented | |
7356 | * frames. They are seen as a symptom of over-mtu | |
7357 | * sized frames. | |
7358 | */ | |
7359 | if (unlikely(rtl8169_fragmented_frame(status))) { | |
cebf8cc7 FR |
7360 | dev->stats.rx_dropped++; |
7361 | dev->stats.rx_length_errors++; | |
ce11ff5e | 7362 | goto release_descriptor; |
126fa4b9 FR |
7363 | } |
7364 | ||
6f0333b8 ED |
7365 | skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry], |
7366 | tp, pkt_size, addr); | |
6f0333b8 ED |
7367 | if (!skb) { |
7368 | dev->stats.rx_dropped++; | |
ce11ff5e | 7369 | goto release_descriptor; |
1da177e4 LT |
7370 | } |
7371 | ||
adea1ac7 | 7372 | rtl8169_rx_csum(skb, status); |
1da177e4 LT |
7373 | skb_put(skb, pkt_size); |
7374 | skb->protocol = eth_type_trans(skb, dev); | |
7375 | ||
7a8fc77b FR |
7376 | rtl8169_rx_vlan_tag(desc, skb); |
7377 | ||
56de414c | 7378 | napi_gro_receive(&tp->napi, skb); |
1da177e4 | 7379 | |
8027aa24 JW |
7380 | u64_stats_update_begin(&tp->rx_stats.syncp); |
7381 | tp->rx_stats.packets++; | |
7382 | tp->rx_stats.bytes += pkt_size; | |
7383 | u64_stats_update_end(&tp->rx_stats.syncp); | |
1da177e4 | 7384 | } |
ce11ff5e | 7385 | release_descriptor: |
7386 | desc->opts2 = 0; | |
ce11ff5e | 7387 | rtl8169_mark_to_asic(desc, rx_buf_sz); |
1da177e4 LT |
7388 | } |
7389 | ||
7390 | count = cur_rx - tp->cur_rx; | |
7391 | tp->cur_rx = cur_rx; | |
7392 | ||
1da177e4 LT |
7393 | return count; |
7394 | } | |
7395 | ||
07d3f51f | 7396 | static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance) |
1da177e4 | 7397 | { |
07d3f51f | 7398 | struct net_device *dev = dev_instance; |
1da177e4 | 7399 | struct rtl8169_private *tp = netdev_priv(dev); |
1da177e4 | 7400 | int handled = 0; |
9085cdfa | 7401 | u16 status; |
1da177e4 | 7402 | |
9085cdfa | 7403 | status = rtl_get_events(tp); |
da78dbff FR |
7404 | if (status && status != 0xffff) { |
7405 | status &= RTL_EVENT_NAPI | tp->event_slow; | |
7406 | if (status) { | |
7407 | handled = 1; | |
1da177e4 | 7408 | |
da78dbff FR |
7409 | rtl_irq_disable(tp); |
7410 | napi_schedule(&tp->napi); | |
f11a377b | 7411 | } |
da78dbff FR |
7412 | } |
7413 | return IRQ_RETVAL(handled); | |
7414 | } | |
1da177e4 | 7415 | |
da78dbff FR |
7416 | /* |
7417 | * Workqueue context. | |
7418 | */ | |
7419 | static void rtl_slow_event_work(struct rtl8169_private *tp) | |
7420 | { | |
7421 | struct net_device *dev = tp->dev; | |
7422 | u16 status; | |
7423 | ||
7424 | status = rtl_get_events(tp) & tp->event_slow; | |
7425 | rtl_ack_events(tp, status); | |
1da177e4 | 7426 | |
da78dbff FR |
7427 | if (unlikely(status & RxFIFOOver)) { |
7428 | switch (tp->mac_version) { | |
7429 | /* Work around for rx fifo overflow */ | |
7430 | case RTL_GIGA_MAC_VER_11: | |
7431 | netif_stop_queue(dev); | |
934714d0 FR |
7432 | /* XXX - Hack alert. See rtl_task(). */ |
7433 | set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags); | |
da78dbff | 7434 | default: |
f11a377b DD |
7435 | break; |
7436 | } | |
da78dbff | 7437 | } |
1da177e4 | 7438 | |
da78dbff FR |
7439 | if (unlikely(status & SYSErr)) |
7440 | rtl8169_pcierr_interrupt(dev); | |
0e485150 | 7441 | |
da78dbff FR |
7442 | if (status & LinkChg) |
7443 | __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true); | |
1da177e4 | 7444 | |
7dbb4918 | 7445 | rtl_irq_enable_all(tp); |
1da177e4 LT |
7446 | } |
7447 | ||
4422bcd4 FR |
7448 | static void rtl_task(struct work_struct *work) |
7449 | { | |
da78dbff FR |
7450 | static const struct { |
7451 | int bitnr; | |
7452 | void (*action)(struct rtl8169_private *); | |
7453 | } rtl_work[] = { | |
934714d0 | 7454 | /* XXX - keep rtl_slow_event_work() as first element. */ |
da78dbff FR |
7455 | { RTL_FLAG_TASK_SLOW_PENDING, rtl_slow_event_work }, |
7456 | { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work }, | |
7457 | { RTL_FLAG_TASK_PHY_PENDING, rtl_phy_work } | |
7458 | }; | |
4422bcd4 FR |
7459 | struct rtl8169_private *tp = |
7460 | container_of(work, struct rtl8169_private, wk.work); | |
da78dbff FR |
7461 | struct net_device *dev = tp->dev; |
7462 | int i; | |
7463 | ||
7464 | rtl_lock_work(tp); | |
7465 | ||
6c4a70c5 FR |
7466 | if (!netif_running(dev) || |
7467 | !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags)) | |
da78dbff FR |
7468 | goto out_unlock; |
7469 | ||
7470 | for (i = 0; i < ARRAY_SIZE(rtl_work); i++) { | |
7471 | bool pending; | |
7472 | ||
da78dbff | 7473 | pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags); |
da78dbff FR |
7474 | if (pending) |
7475 | rtl_work[i].action(tp); | |
7476 | } | |
4422bcd4 | 7477 | |
da78dbff FR |
7478 | out_unlock: |
7479 | rtl_unlock_work(tp); | |
4422bcd4 FR |
7480 | } |
7481 | ||
bea3348e | 7482 | static int rtl8169_poll(struct napi_struct *napi, int budget) |
1da177e4 | 7483 | { |
bea3348e SH |
7484 | struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi); |
7485 | struct net_device *dev = tp->dev; | |
da78dbff FR |
7486 | u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow; |
7487 | int work_done= 0; | |
7488 | u16 status; | |
7489 | ||
7490 | status = rtl_get_events(tp); | |
7491 | rtl_ack_events(tp, status & ~tp->event_slow); | |
7492 | ||
7493 | if (status & RTL_EVENT_NAPI_RX) | |
7494 | work_done = rtl_rx(dev, tp, (u32) budget); | |
7495 | ||
7496 | if (status & RTL_EVENT_NAPI_TX) | |
7497 | rtl_tx(dev, tp); | |
1da177e4 | 7498 | |
da78dbff FR |
7499 | if (status & tp->event_slow) { |
7500 | enable_mask &= ~tp->event_slow; | |
7501 | ||
7502 | rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING); | |
7503 | } | |
1da177e4 | 7504 | |
bea3348e | 7505 | if (work_done < budget) { |
288379f0 | 7506 | napi_complete(napi); |
f11a377b | 7507 | |
da78dbff FR |
7508 | rtl_irq_enable(tp, enable_mask); |
7509 | mmiowb(); | |
1da177e4 LT |
7510 | } |
7511 | ||
bea3348e | 7512 | return work_done; |
1da177e4 | 7513 | } |
1da177e4 | 7514 | |
523a6094 FR |
7515 | static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr) |
7516 | { | |
7517 | struct rtl8169_private *tp = netdev_priv(dev); | |
7518 | ||
7519 | if (tp->mac_version > RTL_GIGA_MAC_VER_06) | |
7520 | return; | |
7521 | ||
7522 | dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff); | |
7523 | RTL_W32(RxMissed, 0); | |
7524 | } | |
7525 | ||
1da177e4 LT |
7526 | static void rtl8169_down(struct net_device *dev) |
7527 | { | |
7528 | struct rtl8169_private *tp = netdev_priv(dev); | |
7529 | void __iomem *ioaddr = tp->mmio_addr; | |
1da177e4 | 7530 | |
4876cc1e | 7531 | del_timer_sync(&tp->timer); |
1da177e4 | 7532 | |
93dd79e8 | 7533 | napi_disable(&tp->napi); |
da78dbff | 7534 | netif_stop_queue(dev); |
1da177e4 | 7535 | |
92fc43b4 | 7536 | rtl8169_hw_reset(tp); |
323bb685 SG |
7537 | /* |
7538 | * At this point device interrupts can not be enabled in any function, | |
209e5ac8 FR |
7539 | * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task) |
7540 | * and napi is disabled (rtl8169_poll). | |
323bb685 | 7541 | */ |
523a6094 | 7542 | rtl8169_rx_missed(dev, ioaddr); |
1da177e4 | 7543 | |
1da177e4 | 7544 | /* Give a racing hard_start_xmit a few cycles to complete. */ |
da78dbff | 7545 | synchronize_sched(); |
1da177e4 | 7546 | |
1da177e4 LT |
7547 | rtl8169_tx_clear(tp); |
7548 | ||
7549 | rtl8169_rx_clear(tp); | |
065c27c1 | 7550 | |
7551 | rtl_pll_power_down(tp); | |
1da177e4 LT |
7552 | } |
7553 | ||
7554 | static int rtl8169_close(struct net_device *dev) | |
7555 | { | |
7556 | struct rtl8169_private *tp = netdev_priv(dev); | |
7557 | struct pci_dev *pdev = tp->pci_dev; | |
7558 | ||
e1759441 RW |
7559 | pm_runtime_get_sync(&pdev->dev); |
7560 | ||
cecb5fd7 | 7561 | /* Update counters before going down */ |
355423d0 IV |
7562 | rtl8169_update_counters(dev); |
7563 | ||
da78dbff | 7564 | rtl_lock_work(tp); |
6c4a70c5 | 7565 | clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags); |
da78dbff | 7566 | |
1da177e4 | 7567 | rtl8169_down(dev); |
da78dbff | 7568 | rtl_unlock_work(tp); |
1da177e4 | 7569 | |
4ea72445 L |
7570 | cancel_work_sync(&tp->wk.work); |
7571 | ||
92a7c4e7 | 7572 | free_irq(pdev->irq, dev); |
1da177e4 | 7573 | |
82553bb6 SG |
7574 | dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, |
7575 | tp->RxPhyAddr); | |
7576 | dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, | |
7577 | tp->TxPhyAddr); | |
1da177e4 LT |
7578 | tp->TxDescArray = NULL; |
7579 | tp->RxDescArray = NULL; | |
7580 | ||
e1759441 RW |
7581 | pm_runtime_put_sync(&pdev->dev); |
7582 | ||
1da177e4 LT |
7583 | return 0; |
7584 | } | |
7585 | ||
dc1c00ce FR |
7586 | #ifdef CONFIG_NET_POLL_CONTROLLER |
7587 | static void rtl8169_netpoll(struct net_device *dev) | |
7588 | { | |
7589 | struct rtl8169_private *tp = netdev_priv(dev); | |
7590 | ||
7591 | rtl8169_interrupt(tp->pci_dev->irq, dev); | |
7592 | } | |
7593 | #endif | |
7594 | ||
df43ac78 FR |
7595 | static int rtl_open(struct net_device *dev) |
7596 | { | |
7597 | struct rtl8169_private *tp = netdev_priv(dev); | |
7598 | void __iomem *ioaddr = tp->mmio_addr; | |
7599 | struct pci_dev *pdev = tp->pci_dev; | |
7600 | int retval = -ENOMEM; | |
7601 | ||
7602 | pm_runtime_get_sync(&pdev->dev); | |
7603 | ||
7604 | /* | |
e75d6606 | 7605 | * Rx and Tx descriptors needs 256 bytes alignment. |
df43ac78 FR |
7606 | * dma_alloc_coherent provides more. |
7607 | */ | |
7608 | tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES, | |
7609 | &tp->TxPhyAddr, GFP_KERNEL); | |
7610 | if (!tp->TxDescArray) | |
7611 | goto err_pm_runtime_put; | |
7612 | ||
7613 | tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES, | |
7614 | &tp->RxPhyAddr, GFP_KERNEL); | |
7615 | if (!tp->RxDescArray) | |
7616 | goto err_free_tx_0; | |
7617 | ||
7618 | retval = rtl8169_init_ring(dev); | |
7619 | if (retval < 0) | |
7620 | goto err_free_rx_1; | |
7621 | ||
7622 | INIT_WORK(&tp->wk.work, rtl_task); | |
7623 | ||
7624 | smp_mb(); | |
7625 | ||
7626 | rtl_request_firmware(tp); | |
7627 | ||
92a7c4e7 | 7628 | retval = request_irq(pdev->irq, rtl8169_interrupt, |
df43ac78 FR |
7629 | (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED, |
7630 | dev->name, dev); | |
7631 | if (retval < 0) | |
7632 | goto err_release_fw_2; | |
7633 | ||
7634 | rtl_lock_work(tp); | |
7635 | ||
7636 | set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags); | |
7637 | ||
7638 | napi_enable(&tp->napi); | |
7639 | ||
7640 | rtl8169_init_phy(dev, tp); | |
7641 | ||
7642 | __rtl8169_set_features(dev, dev->features); | |
7643 | ||
7644 | rtl_pll_power_up(tp); | |
7645 | ||
7646 | rtl_hw_start(dev); | |
7647 | ||
7648 | netif_start_queue(dev); | |
7649 | ||
7650 | rtl_unlock_work(tp); | |
7651 | ||
7652 | tp->saved_wolopts = 0; | |
7653 | pm_runtime_put_noidle(&pdev->dev); | |
7654 | ||
7655 | rtl8169_check_link_status(dev, tp, ioaddr); | |
7656 | out: | |
7657 | return retval; | |
7658 | ||
7659 | err_release_fw_2: | |
7660 | rtl_release_firmware(tp); | |
7661 | rtl8169_rx_clear(tp); | |
7662 | err_free_rx_1: | |
7663 | dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, | |
7664 | tp->RxPhyAddr); | |
7665 | tp->RxDescArray = NULL; | |
7666 | err_free_tx_0: | |
7667 | dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, | |
7668 | tp->TxPhyAddr); | |
7669 | tp->TxDescArray = NULL; | |
7670 | err_pm_runtime_put: | |
7671 | pm_runtime_put_noidle(&pdev->dev); | |
7672 | goto out; | |
7673 | } | |
7674 | ||
8027aa24 JW |
7675 | static struct rtnl_link_stats64 * |
7676 | rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) | |
1da177e4 LT |
7677 | { |
7678 | struct rtl8169_private *tp = netdev_priv(dev); | |
7679 | void __iomem *ioaddr = tp->mmio_addr; | |
8027aa24 | 7680 | unsigned int start; |
1da177e4 | 7681 | |
da78dbff | 7682 | if (netif_running(dev)) |
523a6094 | 7683 | rtl8169_rx_missed(dev, ioaddr); |
5b0384f4 | 7684 | |
8027aa24 | 7685 | do { |
57a7744e | 7686 | start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp); |
8027aa24 JW |
7687 | stats->rx_packets = tp->rx_stats.packets; |
7688 | stats->rx_bytes = tp->rx_stats.bytes; | |
57a7744e | 7689 | } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start)); |
8027aa24 JW |
7690 | |
7691 | ||
7692 | do { | |
57a7744e | 7693 | start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp); |
8027aa24 JW |
7694 | stats->tx_packets = tp->tx_stats.packets; |
7695 | stats->tx_bytes = tp->tx_stats.bytes; | |
57a7744e | 7696 | } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start)); |
8027aa24 JW |
7697 | |
7698 | stats->rx_dropped = dev->stats.rx_dropped; | |
7699 | stats->tx_dropped = dev->stats.tx_dropped; | |
7700 | stats->rx_length_errors = dev->stats.rx_length_errors; | |
7701 | stats->rx_errors = dev->stats.rx_errors; | |
7702 | stats->rx_crc_errors = dev->stats.rx_crc_errors; | |
7703 | stats->rx_fifo_errors = dev->stats.rx_fifo_errors; | |
7704 | stats->rx_missed_errors = dev->stats.rx_missed_errors; | |
7705 | ||
7706 | return stats; | |
1da177e4 LT |
7707 | } |
7708 | ||
861ab440 | 7709 | static void rtl8169_net_suspend(struct net_device *dev) |
5d06a99f | 7710 | { |
065c27c1 | 7711 | struct rtl8169_private *tp = netdev_priv(dev); |
7712 | ||
5d06a99f | 7713 | if (!netif_running(dev)) |
861ab440 | 7714 | return; |
5d06a99f FR |
7715 | |
7716 | netif_device_detach(dev); | |
7717 | netif_stop_queue(dev); | |
da78dbff FR |
7718 | |
7719 | rtl_lock_work(tp); | |
7720 | napi_disable(&tp->napi); | |
6c4a70c5 | 7721 | clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags); |
da78dbff FR |
7722 | rtl_unlock_work(tp); |
7723 | ||
7724 | rtl_pll_power_down(tp); | |
861ab440 RW |
7725 | } |
7726 | ||
7727 | #ifdef CONFIG_PM | |
7728 | ||
7729 | static int rtl8169_suspend(struct device *device) | |
7730 | { | |
7731 | struct pci_dev *pdev = to_pci_dev(device); | |
7732 | struct net_device *dev = pci_get_drvdata(pdev); | |
5d06a99f | 7733 | |
861ab440 | 7734 | rtl8169_net_suspend(dev); |
1371fa6d | 7735 | |
5d06a99f FR |
7736 | return 0; |
7737 | } | |
7738 | ||
e1759441 RW |
7739 | static void __rtl8169_resume(struct net_device *dev) |
7740 | { | |
065c27c1 | 7741 | struct rtl8169_private *tp = netdev_priv(dev); |
7742 | ||
e1759441 | 7743 | netif_device_attach(dev); |
065c27c1 | 7744 | |
7745 | rtl_pll_power_up(tp); | |
7746 | ||
cff4c162 AS |
7747 | rtl_lock_work(tp); |
7748 | napi_enable(&tp->napi); | |
6c4a70c5 | 7749 | set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags); |
cff4c162 | 7750 | rtl_unlock_work(tp); |
da78dbff | 7751 | |
98ddf986 | 7752 | rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); |
e1759441 RW |
7753 | } |
7754 | ||
861ab440 | 7755 | static int rtl8169_resume(struct device *device) |
5d06a99f | 7756 | { |
861ab440 | 7757 | struct pci_dev *pdev = to_pci_dev(device); |
5d06a99f | 7758 | struct net_device *dev = pci_get_drvdata(pdev); |
fccec10b SG |
7759 | struct rtl8169_private *tp = netdev_priv(dev); |
7760 | ||
7761 | rtl8169_init_phy(dev, tp); | |
5d06a99f | 7762 | |
e1759441 RW |
7763 | if (netif_running(dev)) |
7764 | __rtl8169_resume(dev); | |
5d06a99f | 7765 | |
e1759441 RW |
7766 | return 0; |
7767 | } | |
7768 | ||
7769 | static int rtl8169_runtime_suspend(struct device *device) | |
7770 | { | |
7771 | struct pci_dev *pdev = to_pci_dev(device); | |
7772 | struct net_device *dev = pci_get_drvdata(pdev); | |
7773 | struct rtl8169_private *tp = netdev_priv(dev); | |
7774 | ||
7775 | if (!tp->TxDescArray) | |
7776 | return 0; | |
7777 | ||
da78dbff | 7778 | rtl_lock_work(tp); |
e1759441 RW |
7779 | tp->saved_wolopts = __rtl8169_get_wol(tp); |
7780 | __rtl8169_set_wol(tp, WAKE_ANY); | |
da78dbff | 7781 | rtl_unlock_work(tp); |
e1759441 RW |
7782 | |
7783 | rtl8169_net_suspend(dev); | |
7784 | ||
7785 | return 0; | |
7786 | } | |
7787 | ||
7788 | static int rtl8169_runtime_resume(struct device *device) | |
7789 | { | |
7790 | struct pci_dev *pdev = to_pci_dev(device); | |
7791 | struct net_device *dev = pci_get_drvdata(pdev); | |
7792 | struct rtl8169_private *tp = netdev_priv(dev); | |
7793 | ||
7794 | if (!tp->TxDescArray) | |
7795 | return 0; | |
7796 | ||
da78dbff | 7797 | rtl_lock_work(tp); |
e1759441 RW |
7798 | __rtl8169_set_wol(tp, tp->saved_wolopts); |
7799 | tp->saved_wolopts = 0; | |
da78dbff | 7800 | rtl_unlock_work(tp); |
e1759441 | 7801 | |
fccec10b SG |
7802 | rtl8169_init_phy(dev, tp); |
7803 | ||
e1759441 | 7804 | __rtl8169_resume(dev); |
5d06a99f | 7805 | |
5d06a99f FR |
7806 | return 0; |
7807 | } | |
7808 | ||
e1759441 RW |
7809 | static int rtl8169_runtime_idle(struct device *device) |
7810 | { | |
7811 | struct pci_dev *pdev = to_pci_dev(device); | |
7812 | struct net_device *dev = pci_get_drvdata(pdev); | |
7813 | struct rtl8169_private *tp = netdev_priv(dev); | |
7814 | ||
e4fbce74 | 7815 | return tp->TxDescArray ? -EBUSY : 0; |
e1759441 RW |
7816 | } |
7817 | ||
47145210 | 7818 | static const struct dev_pm_ops rtl8169_pm_ops = { |
cecb5fd7 FR |
7819 | .suspend = rtl8169_suspend, |
7820 | .resume = rtl8169_resume, | |
7821 | .freeze = rtl8169_suspend, | |
7822 | .thaw = rtl8169_resume, | |
7823 | .poweroff = rtl8169_suspend, | |
7824 | .restore = rtl8169_resume, | |
7825 | .runtime_suspend = rtl8169_runtime_suspend, | |
7826 | .runtime_resume = rtl8169_runtime_resume, | |
7827 | .runtime_idle = rtl8169_runtime_idle, | |
861ab440 RW |
7828 | }; |
7829 | ||
7830 | #define RTL8169_PM_OPS (&rtl8169_pm_ops) | |
7831 | ||
7832 | #else /* !CONFIG_PM */ | |
7833 | ||
7834 | #define RTL8169_PM_OPS NULL | |
7835 | ||
7836 | #endif /* !CONFIG_PM */ | |
7837 | ||
649b3b8c | 7838 | static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp) |
7839 | { | |
7840 | void __iomem *ioaddr = tp->mmio_addr; | |
7841 | ||
7842 | /* WoL fails with 8168b when the receiver is disabled. */ | |
7843 | switch (tp->mac_version) { | |
7844 | case RTL_GIGA_MAC_VER_11: | |
7845 | case RTL_GIGA_MAC_VER_12: | |
7846 | case RTL_GIGA_MAC_VER_17: | |
7847 | pci_clear_master(tp->pci_dev); | |
7848 | ||
7849 | RTL_W8(ChipCmd, CmdRxEnb); | |
7850 | /* PCI commit */ | |
7851 | RTL_R8(ChipCmd); | |
7852 | break; | |
7853 | default: | |
7854 | break; | |
7855 | } | |
7856 | } | |
7857 | ||
1765f95d FR |
7858 | static void rtl_shutdown(struct pci_dev *pdev) |
7859 | { | |
861ab440 | 7860 | struct net_device *dev = pci_get_drvdata(pdev); |
4bb3f522 | 7861 | struct rtl8169_private *tp = netdev_priv(dev); |
2a15cd2f | 7862 | struct device *d = &pdev->dev; |
7863 | ||
7864 | pm_runtime_get_sync(d); | |
861ab440 RW |
7865 | |
7866 | rtl8169_net_suspend(dev); | |
1765f95d | 7867 | |
cecb5fd7 | 7868 | /* Restore original MAC address */ |
cc098dc7 IV |
7869 | rtl_rar_set(tp, dev->perm_addr); |
7870 | ||
92fc43b4 | 7871 | rtl8169_hw_reset(tp); |
4bb3f522 | 7872 | |
861ab440 | 7873 | if (system_state == SYSTEM_POWER_OFF) { |
649b3b8c | 7874 | if (__rtl8169_get_wol(tp) & WAKE_ANY) { |
7875 | rtl_wol_suspend_quirk(tp); | |
7876 | rtl_wol_shutdown_quirk(tp); | |
ca52efd5 | 7877 | } |
7878 | ||
861ab440 RW |
7879 | pci_wake_from_d3(pdev, true); |
7880 | pci_set_power_state(pdev, PCI_D3hot); | |
7881 | } | |
2a15cd2f | 7882 | |
7883 | pm_runtime_put_noidle(d); | |
861ab440 | 7884 | } |
5d06a99f | 7885 | |
baf63293 | 7886 | static void rtl_remove_one(struct pci_dev *pdev) |
e27566ed FR |
7887 | { |
7888 | struct net_device *dev = pci_get_drvdata(pdev); | |
7889 | struct rtl8169_private *tp = netdev_priv(dev); | |
7890 | ||
ee7a1beb CHL |
7891 | if ((tp->mac_version == RTL_GIGA_MAC_VER_27 || |
7892 | tp->mac_version == RTL_GIGA_MAC_VER_28 || | |
935e2218 CHL |
7893 | tp->mac_version == RTL_GIGA_MAC_VER_31 || |
7894 | tp->mac_version == RTL_GIGA_MAC_VER_49 || | |
7895 | tp->mac_version == RTL_GIGA_MAC_VER_50 || | |
7896 | tp->mac_version == RTL_GIGA_MAC_VER_51) && | |
ee7a1beb | 7897 | r8168_check_dash(tp)) { |
e27566ed FR |
7898 | rtl8168_driver_stop(tp); |
7899 | } | |
7900 | ||
ad1be8d3 DN |
7901 | netif_napi_del(&tp->napi); |
7902 | ||
e27566ed FR |
7903 | unregister_netdev(dev); |
7904 | ||
7905 | rtl_release_firmware(tp); | |
7906 | ||
7907 | if (pci_dev_run_wake(pdev)) | |
7908 | pm_runtime_get_noresume(&pdev->dev); | |
7909 | ||
7910 | /* restore original MAC address */ | |
7911 | rtl_rar_set(tp, dev->perm_addr); | |
7912 | ||
7913 | rtl_disable_msi(pdev, tp); | |
7914 | rtl8169_release_board(pdev, dev, tp->mmio_addr); | |
e27566ed FR |
7915 | } |
7916 | ||
fa9c385e | 7917 | static const struct net_device_ops rtl_netdev_ops = { |
df43ac78 | 7918 | .ndo_open = rtl_open, |
fa9c385e FR |
7919 | .ndo_stop = rtl8169_close, |
7920 | .ndo_get_stats64 = rtl8169_get_stats64, | |
7921 | .ndo_start_xmit = rtl8169_start_xmit, | |
7922 | .ndo_tx_timeout = rtl8169_tx_timeout, | |
7923 | .ndo_validate_addr = eth_validate_addr, | |
7924 | .ndo_change_mtu = rtl8169_change_mtu, | |
7925 | .ndo_fix_features = rtl8169_fix_features, | |
7926 | .ndo_set_features = rtl8169_set_features, | |
7927 | .ndo_set_mac_address = rtl_set_mac_address, | |
7928 | .ndo_do_ioctl = rtl8169_ioctl, | |
7929 | .ndo_set_rx_mode = rtl_set_rx_mode, | |
7930 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
7931 | .ndo_poll_controller = rtl8169_netpoll, | |
7932 | #endif | |
7933 | ||
7934 | }; | |
7935 | ||
31fa8b18 FR |
7936 | static const struct rtl_cfg_info { |
7937 | void (*hw_start)(struct net_device *); | |
7938 | unsigned int region; | |
7939 | unsigned int align; | |
7940 | u16 event_slow; | |
7941 | unsigned features; | |
7942 | u8 default_ver; | |
7943 | } rtl_cfg_infos [] = { | |
7944 | [RTL_CFG_0] = { | |
7945 | .hw_start = rtl_hw_start_8169, | |
7946 | .region = 1, | |
7947 | .align = 0, | |
7948 | .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver, | |
7949 | .features = RTL_FEATURE_GMII, | |
7950 | .default_ver = RTL_GIGA_MAC_VER_01, | |
7951 | }, | |
7952 | [RTL_CFG_1] = { | |
7953 | .hw_start = rtl_hw_start_8168, | |
7954 | .region = 2, | |
7955 | .align = 8, | |
7956 | .event_slow = SYSErr | LinkChg | RxOverflow, | |
7957 | .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI, | |
7958 | .default_ver = RTL_GIGA_MAC_VER_11, | |
7959 | }, | |
7960 | [RTL_CFG_2] = { | |
7961 | .hw_start = rtl_hw_start_8101, | |
7962 | .region = 2, | |
7963 | .align = 8, | |
7964 | .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver | | |
7965 | PCSTimeout, | |
7966 | .features = RTL_FEATURE_MSI, | |
7967 | .default_ver = RTL_GIGA_MAC_VER_13, | |
7968 | } | |
7969 | }; | |
7970 | ||
7971 | /* Cfg9346_Unlock assumed. */ | |
7972 | static unsigned rtl_try_msi(struct rtl8169_private *tp, | |
7973 | const struct rtl_cfg_info *cfg) | |
7974 | { | |
7975 | void __iomem *ioaddr = tp->mmio_addr; | |
7976 | unsigned msi = 0; | |
7977 | u8 cfg2; | |
7978 | ||
7979 | cfg2 = RTL_R8(Config2) & ~MSIEnable; | |
7980 | if (cfg->features & RTL_FEATURE_MSI) { | |
7981 | if (pci_enable_msi(tp->pci_dev)) { | |
7982 | netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n"); | |
7983 | } else { | |
7984 | cfg2 |= MSIEnable; | |
7985 | msi = RTL_FEATURE_MSI; | |
7986 | } | |
7987 | } | |
7988 | if (tp->mac_version <= RTL_GIGA_MAC_VER_06) | |
7989 | RTL_W8(Config2, cfg2); | |
7990 | return msi; | |
7991 | } | |
7992 | ||
c558386b HW |
7993 | DECLARE_RTL_COND(rtl_link_list_ready_cond) |
7994 | { | |
7995 | void __iomem *ioaddr = tp->mmio_addr; | |
7996 | ||
7997 | return RTL_R8(MCU) & LINK_LIST_RDY; | |
7998 | } | |
7999 | ||
8000 | DECLARE_RTL_COND(rtl_rxtx_empty_cond) | |
8001 | { | |
8002 | void __iomem *ioaddr = tp->mmio_addr; | |
8003 | ||
8004 | return (RTL_R8(MCU) & RXTX_EMPTY) == RXTX_EMPTY; | |
8005 | } | |
8006 | ||
baf63293 | 8007 | static void rtl_hw_init_8168g(struct rtl8169_private *tp) |
c558386b HW |
8008 | { |
8009 | void __iomem *ioaddr = tp->mmio_addr; | |
8010 | u32 data; | |
8011 | ||
8012 | tp->ocp_base = OCP_STD_PHY_BASE; | |
8013 | ||
8014 | RTL_W32(MISC, RTL_R32(MISC) | RXDV_GATED_EN); | |
8015 | ||
8016 | if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42)) | |
8017 | return; | |
8018 | ||
8019 | if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42)) | |
8020 | return; | |
8021 | ||
8022 | RTL_W8(ChipCmd, RTL_R8(ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); | |
8023 | msleep(1); | |
8024 | RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB); | |
8025 | ||
5f8bcce9 | 8026 | data = r8168_mac_ocp_read(tp, 0xe8de); |
c558386b HW |
8027 | data &= ~(1 << 14); |
8028 | r8168_mac_ocp_write(tp, 0xe8de, data); | |
8029 | ||
8030 | if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42)) | |
8031 | return; | |
8032 | ||
5f8bcce9 | 8033 | data = r8168_mac_ocp_read(tp, 0xe8de); |
c558386b HW |
8034 | data |= (1 << 15); |
8035 | r8168_mac_ocp_write(tp, 0xe8de, data); | |
8036 | ||
8037 | if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42)) | |
8038 | return; | |
8039 | } | |
8040 | ||
003609da CHL |
8041 | static void rtl_hw_init_8168ep(struct rtl8169_private *tp) |
8042 | { | |
8043 | rtl8168ep_stop_cmac(tp); | |
8044 | rtl_hw_init_8168g(tp); | |
8045 | } | |
8046 | ||
baf63293 | 8047 | static void rtl_hw_initialize(struct rtl8169_private *tp) |
c558386b HW |
8048 | { |
8049 | switch (tp->mac_version) { | |
8050 | case RTL_GIGA_MAC_VER_40: | |
8051 | case RTL_GIGA_MAC_VER_41: | |
57538c4a | 8052 | case RTL_GIGA_MAC_VER_42: |
58152cd4 | 8053 | case RTL_GIGA_MAC_VER_43: |
45dd95c4 | 8054 | case RTL_GIGA_MAC_VER_44: |
6e1d0b89 CHL |
8055 | case RTL_GIGA_MAC_VER_45: |
8056 | case RTL_GIGA_MAC_VER_46: | |
8057 | case RTL_GIGA_MAC_VER_47: | |
8058 | case RTL_GIGA_MAC_VER_48: | |
003609da CHL |
8059 | rtl_hw_init_8168g(tp); |
8060 | break; | |
935e2218 CHL |
8061 | case RTL_GIGA_MAC_VER_49: |
8062 | case RTL_GIGA_MAC_VER_50: | |
8063 | case RTL_GIGA_MAC_VER_51: | |
003609da | 8064 | rtl_hw_init_8168ep(tp); |
c558386b | 8065 | break; |
c558386b HW |
8066 | default: |
8067 | break; | |
8068 | } | |
8069 | } | |
8070 | ||
929a031d | 8071 | static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
3b6cf25d FR |
8072 | { |
8073 | const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data; | |
8074 | const unsigned int region = cfg->region; | |
8075 | struct rtl8169_private *tp; | |
8076 | struct mii_if_info *mii; | |
8077 | struct net_device *dev; | |
8078 | void __iomem *ioaddr; | |
8079 | int chipset, i; | |
8080 | int rc; | |
8081 | ||
8082 | if (netif_msg_drv(&debug)) { | |
8083 | printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n", | |
8084 | MODULENAME, RTL8169_VERSION); | |
8085 | } | |
8086 | ||
8087 | dev = alloc_etherdev(sizeof (*tp)); | |
8088 | if (!dev) { | |
8089 | rc = -ENOMEM; | |
8090 | goto out; | |
8091 | } | |
8092 | ||
8093 | SET_NETDEV_DEV(dev, &pdev->dev); | |
fa9c385e | 8094 | dev->netdev_ops = &rtl_netdev_ops; |
3b6cf25d FR |
8095 | tp = netdev_priv(dev); |
8096 | tp->dev = dev; | |
8097 | tp->pci_dev = pdev; | |
8098 | tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT); | |
8099 | ||
8100 | mii = &tp->mii; | |
8101 | mii->dev = dev; | |
8102 | mii->mdio_read = rtl_mdio_read; | |
8103 | mii->mdio_write = rtl_mdio_write; | |
8104 | mii->phy_id_mask = 0x1f; | |
8105 | mii->reg_num_mask = 0x1f; | |
8106 | mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII); | |
8107 | ||
8108 | /* disable ASPM completely as that cause random device stop working | |
8109 | * problems as well as full system hangs for some PCIe devices users */ | |
8110 | pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 | | |
8111 | PCIE_LINK_STATE_CLKPM); | |
8112 | ||
8113 | /* enable device (incl. PCI PM wakeup and hotplug setup) */ | |
8114 | rc = pci_enable_device(pdev); | |
8115 | if (rc < 0) { | |
8116 | netif_err(tp, probe, dev, "enable failure\n"); | |
8117 | goto err_out_free_dev_1; | |
8118 | } | |
8119 | ||
8120 | if (pci_set_mwi(pdev) < 0) | |
8121 | netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n"); | |
8122 | ||
8123 | /* make sure PCI base addr 1 is MMIO */ | |
8124 | if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) { | |
8125 | netif_err(tp, probe, dev, | |
8126 | "region #%d not an MMIO resource, aborting\n", | |
8127 | region); | |
8128 | rc = -ENODEV; | |
8129 | goto err_out_mwi_2; | |
8130 | } | |
8131 | ||
8132 | /* check for weird/broken PCI region reporting */ | |
8133 | if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) { | |
8134 | netif_err(tp, probe, dev, | |
8135 | "Invalid PCI region size(s), aborting\n"); | |
8136 | rc = -ENODEV; | |
8137 | goto err_out_mwi_2; | |
8138 | } | |
8139 | ||
8140 | rc = pci_request_regions(pdev, MODULENAME); | |
8141 | if (rc < 0) { | |
8142 | netif_err(tp, probe, dev, "could not request regions\n"); | |
8143 | goto err_out_mwi_2; | |
8144 | } | |
8145 | ||
929a031d | 8146 | tp->cp_cmd = 0; |
3b6cf25d FR |
8147 | |
8148 | if ((sizeof(dma_addr_t) > 4) && | |
8149 | !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) { | |
8150 | tp->cp_cmd |= PCIDAC; | |
8151 | dev->features |= NETIF_F_HIGHDMA; | |
8152 | } else { | |
8153 | rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); | |
8154 | if (rc < 0) { | |
8155 | netif_err(tp, probe, dev, "DMA configuration failed\n"); | |
8156 | goto err_out_free_res_3; | |
8157 | } | |
8158 | } | |
8159 | ||
8160 | /* ioremap MMIO region */ | |
8161 | ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE); | |
8162 | if (!ioaddr) { | |
8163 | netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n"); | |
8164 | rc = -EIO; | |
8165 | goto err_out_free_res_3; | |
8166 | } | |
8167 | tp->mmio_addr = ioaddr; | |
8168 | ||
8169 | if (!pci_is_pcie(pdev)) | |
8170 | netif_info(tp, probe, dev, "not PCI Express\n"); | |
8171 | ||
8172 | /* Identify chip attached to board */ | |
8173 | rtl8169_get_mac_version(tp, dev, cfg->default_ver); | |
8174 | ||
8175 | rtl_init_rxcfg(tp); | |
8176 | ||
8177 | rtl_irq_disable(tp); | |
8178 | ||
c558386b HW |
8179 | rtl_hw_initialize(tp); |
8180 | ||
3b6cf25d FR |
8181 | rtl_hw_reset(tp); |
8182 | ||
8183 | rtl_ack_events(tp, 0xffff); | |
8184 | ||
8185 | pci_set_master(pdev); | |
8186 | ||
3b6cf25d FR |
8187 | rtl_init_mdio_ops(tp); |
8188 | rtl_init_pll_power_ops(tp); | |
8189 | rtl_init_jumbo_ops(tp); | |
beb1fe18 | 8190 | rtl_init_csi_ops(tp); |
3b6cf25d FR |
8191 | |
8192 | rtl8169_print_mac_version(tp); | |
8193 | ||
8194 | chipset = tp->mac_version; | |
8195 | tp->txd_version = rtl_chip_infos[chipset].txd_version; | |
8196 | ||
8197 | RTL_W8(Cfg9346, Cfg9346_Unlock); | |
8198 | RTL_W8(Config1, RTL_R8(Config1) | PMEnable); | |
8f9d5138 | 8199 | RTL_W8(Config5, RTL_R8(Config5) & (BWF | MWF | UWF | LanWake | PMEStatus)); |
6e1d0b89 | 8200 | switch (tp->mac_version) { |
ac85bcdb CHL |
8201 | case RTL_GIGA_MAC_VER_34: |
8202 | case RTL_GIGA_MAC_VER_35: | |
8203 | case RTL_GIGA_MAC_VER_36: | |
8204 | case RTL_GIGA_MAC_VER_37: | |
8205 | case RTL_GIGA_MAC_VER_38: | |
8206 | case RTL_GIGA_MAC_VER_40: | |
8207 | case RTL_GIGA_MAC_VER_41: | |
8208 | case RTL_GIGA_MAC_VER_42: | |
8209 | case RTL_GIGA_MAC_VER_43: | |
8210 | case RTL_GIGA_MAC_VER_44: | |
6e1d0b89 CHL |
8211 | case RTL_GIGA_MAC_VER_45: |
8212 | case RTL_GIGA_MAC_VER_46: | |
ac85bcdb CHL |
8213 | case RTL_GIGA_MAC_VER_47: |
8214 | case RTL_GIGA_MAC_VER_48: | |
935e2218 CHL |
8215 | case RTL_GIGA_MAC_VER_49: |
8216 | case RTL_GIGA_MAC_VER_50: | |
8217 | case RTL_GIGA_MAC_VER_51: | |
6e1d0b89 CHL |
8218 | if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2) |
8219 | tp->features |= RTL_FEATURE_WOL; | |
8220 | if ((RTL_R8(Config3) & LinkUp) != 0) | |
8221 | tp->features |= RTL_FEATURE_WOL; | |
8222 | break; | |
8223 | default: | |
8224 | if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0) | |
8225 | tp->features |= RTL_FEATURE_WOL; | |
8226 | break; | |
8227 | } | |
3b6cf25d FR |
8228 | if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0) |
8229 | tp->features |= RTL_FEATURE_WOL; | |
8230 | tp->features |= rtl_try_msi(tp, cfg); | |
8231 | RTL_W8(Cfg9346, Cfg9346_Lock); | |
8232 | ||
8233 | if (rtl_tbi_enabled(tp)) { | |
8234 | tp->set_speed = rtl8169_set_speed_tbi; | |
8235 | tp->get_settings = rtl8169_gset_tbi; | |
8236 | tp->phy_reset_enable = rtl8169_tbi_reset_enable; | |
8237 | tp->phy_reset_pending = rtl8169_tbi_reset_pending; | |
8238 | tp->link_ok = rtl8169_tbi_link_ok; | |
8239 | tp->do_ioctl = rtl_tbi_ioctl; | |
8240 | } else { | |
8241 | tp->set_speed = rtl8169_set_speed_xmii; | |
8242 | tp->get_settings = rtl8169_gset_xmii; | |
8243 | tp->phy_reset_enable = rtl8169_xmii_reset_enable; | |
8244 | tp->phy_reset_pending = rtl8169_xmii_reset_pending; | |
8245 | tp->link_ok = rtl8169_xmii_link_ok; | |
8246 | tp->do_ioctl = rtl_xmii_ioctl; | |
8247 | } | |
8248 | ||
8249 | mutex_init(&tp->wk.mutex); | |
340fea3d KM |
8250 | u64_stats_init(&tp->rx_stats.syncp); |
8251 | u64_stats_init(&tp->tx_stats.syncp); | |
3b6cf25d FR |
8252 | |
8253 | /* Get MAC address */ | |
89cceb27 CHL |
8254 | if (tp->mac_version == RTL_GIGA_MAC_VER_35 || |
8255 | tp->mac_version == RTL_GIGA_MAC_VER_36 || | |
8256 | tp->mac_version == RTL_GIGA_MAC_VER_37 || | |
8257 | tp->mac_version == RTL_GIGA_MAC_VER_38 || | |
8258 | tp->mac_version == RTL_GIGA_MAC_VER_40 || | |
8259 | tp->mac_version == RTL_GIGA_MAC_VER_41 || | |
8260 | tp->mac_version == RTL_GIGA_MAC_VER_42 || | |
8261 | tp->mac_version == RTL_GIGA_MAC_VER_43 || | |
8262 | tp->mac_version == RTL_GIGA_MAC_VER_44 || | |
8263 | tp->mac_version == RTL_GIGA_MAC_VER_45 || | |
6e1d0b89 CHL |
8264 | tp->mac_version == RTL_GIGA_MAC_VER_46 || |
8265 | tp->mac_version == RTL_GIGA_MAC_VER_47 || | |
935e2218 CHL |
8266 | tp->mac_version == RTL_GIGA_MAC_VER_48 || |
8267 | tp->mac_version == RTL_GIGA_MAC_VER_49 || | |
8268 | tp->mac_version == RTL_GIGA_MAC_VER_50 || | |
8269 | tp->mac_version == RTL_GIGA_MAC_VER_51) { | |
6e1d0b89 CHL |
8270 | u16 mac_addr[3]; |
8271 | ||
05b9687b CHL |
8272 | *(u32 *)&mac_addr[0] = rtl_eri_read(tp, 0xe0, ERIAR_EXGMAC); |
8273 | *(u16 *)&mac_addr[2] = rtl_eri_read(tp, 0xe4, ERIAR_EXGMAC); | |
6e1d0b89 CHL |
8274 | |
8275 | if (is_valid_ether_addr((u8 *)mac_addr)) | |
8276 | rtl_rar_set(tp, (u8 *)mac_addr); | |
8277 | } | |
3b6cf25d FR |
8278 | for (i = 0; i < ETH_ALEN; i++) |
8279 | dev->dev_addr[i] = RTL_R8(MAC0 + i); | |
3b6cf25d | 8280 | |
7ad24ea4 | 8281 | dev->ethtool_ops = &rtl8169_ethtool_ops; |
3b6cf25d | 8282 | dev->watchdog_timeo = RTL8169_TX_TIMEOUT; |
3b6cf25d FR |
8283 | |
8284 | netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT); | |
8285 | ||
8286 | /* don't enable SG, IP_CSUM and TSO by default - it might not work | |
8287 | * properly for all devices */ | |
8288 | dev->features |= NETIF_F_RXCSUM | | |
f646968f | 8289 | NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX; |
3b6cf25d FR |
8290 | |
8291 | dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | | |
f646968f PM |
8292 | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX | |
8293 | NETIF_F_HW_VLAN_CTAG_RX; | |
3b6cf25d FR |
8294 | dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | |
8295 | NETIF_F_HIGHDMA; | |
8296 | ||
929a031d | 8297 | tp->cp_cmd |= RxChkSum | RxVlan; |
8298 | ||
8299 | /* | |
8300 | * Pretend we are using VLANs; This bypasses a nasty bug where | |
8301 | * Interrupts stop flowing on high load on 8110SCd controllers. | |
8302 | */ | |
3b6cf25d | 8303 | if (tp->mac_version == RTL_GIGA_MAC_VER_05) |
929a031d | 8304 | /* Disallow toggling */ |
f646968f | 8305 | dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX; |
3b6cf25d | 8306 | |
5888d3fc | 8307 | if (tp->txd_version == RTL_TD_0) |
8308 | tp->tso_csum = rtl8169_tso_csum_v1; | |
e974604b | 8309 | else if (tp->txd_version == RTL_TD_1) { |
5888d3fc | 8310 | tp->tso_csum = rtl8169_tso_csum_v2; |
e974604b | 8311 | dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6; |
8312 | } else | |
5888d3fc | 8313 | WARN_ON_ONCE(1); |
8314 | ||
3b6cf25d FR |
8315 | dev->hw_features |= NETIF_F_RXALL; |
8316 | dev->hw_features |= NETIF_F_RXFCS; | |
8317 | ||
8318 | tp->hw_start = cfg->hw_start; | |
8319 | tp->event_slow = cfg->event_slow; | |
8320 | ||
8321 | tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ? | |
8322 | ~(RxBOVF | RxFOVF) : ~0; | |
8323 | ||
8324 | init_timer(&tp->timer); | |
8325 | tp->timer.data = (unsigned long) dev; | |
8326 | tp->timer.function = rtl8169_phy_timer; | |
8327 | ||
8328 | tp->rtl_fw = RTL_FIRMWARE_UNKNOWN; | |
8329 | ||
8330 | rc = register_netdev(dev); | |
8331 | if (rc < 0) | |
8332 | goto err_out_msi_4; | |
8333 | ||
8334 | pci_set_drvdata(pdev, dev); | |
8335 | ||
92a7c4e7 FR |
8336 | netif_info(tp, probe, dev, "%s at 0x%p, %pM, XID %08x IRQ %d\n", |
8337 | rtl_chip_infos[chipset].name, ioaddr, dev->dev_addr, | |
8338 | (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), pdev->irq); | |
3b6cf25d FR |
8339 | if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) { |
8340 | netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, " | |
8341 | "tx checksumming: %s]\n", | |
8342 | rtl_chip_infos[chipset].jumbo_max, | |
8343 | rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko"); | |
8344 | } | |
8345 | ||
ee7a1beb CHL |
8346 | if ((tp->mac_version == RTL_GIGA_MAC_VER_27 || |
8347 | tp->mac_version == RTL_GIGA_MAC_VER_28 || | |
935e2218 CHL |
8348 | tp->mac_version == RTL_GIGA_MAC_VER_31 || |
8349 | tp->mac_version == RTL_GIGA_MAC_VER_49 || | |
8350 | tp->mac_version == RTL_GIGA_MAC_VER_50 || | |
8351 | tp->mac_version == RTL_GIGA_MAC_VER_51) && | |
ee7a1beb | 8352 | r8168_check_dash(tp)) { |
3b6cf25d FR |
8353 | rtl8168_driver_start(tp); |
8354 | } | |
8355 | ||
8356 | device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL); | |
8357 | ||
8358 | if (pci_dev_run_wake(pdev)) | |
8359 | pm_runtime_put_noidle(&pdev->dev); | |
8360 | ||
8361 | netif_carrier_off(dev); | |
8362 | ||
8363 | out: | |
8364 | return rc; | |
8365 | ||
8366 | err_out_msi_4: | |
ad1be8d3 | 8367 | netif_napi_del(&tp->napi); |
3b6cf25d FR |
8368 | rtl_disable_msi(pdev, tp); |
8369 | iounmap(ioaddr); | |
8370 | err_out_free_res_3: | |
8371 | pci_release_regions(pdev); | |
8372 | err_out_mwi_2: | |
8373 | pci_clear_mwi(pdev); | |
8374 | pci_disable_device(pdev); | |
8375 | err_out_free_dev_1: | |
8376 | free_netdev(dev); | |
8377 | goto out; | |
8378 | } | |
8379 | ||
1da177e4 LT |
8380 | static struct pci_driver rtl8169_pci_driver = { |
8381 | .name = MODULENAME, | |
8382 | .id_table = rtl8169_pci_tbl, | |
3b6cf25d | 8383 | .probe = rtl_init_one, |
baf63293 | 8384 | .remove = rtl_remove_one, |
1765f95d | 8385 | .shutdown = rtl_shutdown, |
861ab440 | 8386 | .driver.pm = RTL8169_PM_OPS, |
1da177e4 LT |
8387 | }; |
8388 | ||
3eeb7da9 | 8389 | module_pci_driver(rtl8169_pci_driver); |