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Commit | Line | Data |
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1da177e4 | 1 | /* |
07d3f51f FR |
2 | * r8169.c: RealTek 8169/8168/8101 ethernet driver. |
3 | * | |
4 | * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw> | |
5 | * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com> | |
6 | * Copyright (c) a lot of people too. Please respect their work. | |
7 | * | |
8 | * See MAINTAINERS file for support contact information. | |
1da177e4 LT |
9 | */ |
10 | ||
11 | #include <linux/module.h> | |
12 | #include <linux/moduleparam.h> | |
13 | #include <linux/pci.h> | |
14 | #include <linux/netdevice.h> | |
15 | #include <linux/etherdevice.h> | |
16 | #include <linux/delay.h> | |
17 | #include <linux/ethtool.h> | |
18 | #include <linux/mii.h> | |
19 | #include <linux/if_vlan.h> | |
20 | #include <linux/crc32.h> | |
21 | #include <linux/in.h> | |
22 | #include <linux/ip.h> | |
23 | #include <linux/tcp.h> | |
24 | #include <linux/init.h> | |
a6b7a407 | 25 | #include <linux/interrupt.h> |
1da177e4 | 26 | #include <linux/dma-mapping.h> |
e1759441 | 27 | #include <linux/pm_runtime.h> |
bca03d5f | 28 | #include <linux/firmware.h> |
ba04c7c9 | 29 | #include <linux/pci-aspm.h> |
70c71606 | 30 | #include <linux/prefetch.h> |
1da177e4 | 31 | |
99f252b0 | 32 | #include <asm/system.h> |
1da177e4 LT |
33 | #include <asm/io.h> |
34 | #include <asm/irq.h> | |
35 | ||
865c652d | 36 | #define RTL8169_VERSION "2.3LK-NAPI" |
1da177e4 LT |
37 | #define MODULENAME "r8169" |
38 | #define PFX MODULENAME ": " | |
39 | ||
bca03d5f | 40 | #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw" |
41 | #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw" | |
01dc7fec | 42 | #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw" |
43 | #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw" | |
70090424 | 44 | #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw" |
c2218925 HW |
45 | #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw" |
46 | #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw" | |
5a5e4443 | 47 | #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw" |
bca03d5f | 48 | |
1da177e4 LT |
49 | #ifdef RTL8169_DEBUG |
50 | #define assert(expr) \ | |
5b0384f4 FR |
51 | if (!(expr)) { \ |
52 | printk( "Assertion failed! %s,%s,%s,line=%d\n", \ | |
b39d66a8 | 53 | #expr,__FILE__,__func__,__LINE__); \ |
5b0384f4 | 54 | } |
06fa7358 JP |
55 | #define dprintk(fmt, args...) \ |
56 | do { printk(KERN_DEBUG PFX fmt, ## args); } while (0) | |
1da177e4 LT |
57 | #else |
58 | #define assert(expr) do {} while (0) | |
59 | #define dprintk(fmt, args...) do {} while (0) | |
60 | #endif /* RTL8169_DEBUG */ | |
61 | ||
b57b7e5a | 62 | #define R8169_MSG_DEFAULT \ |
f0e837d9 | 63 | (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN) |
b57b7e5a | 64 | |
1da177e4 LT |
65 | #define TX_BUFFS_AVAIL(tp) \ |
66 | (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1) | |
67 | ||
1da177e4 LT |
68 | /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). |
69 | The RTL chips use a 64 element hash table based on the Ethernet CRC. */ | |
f71e1309 | 70 | static const int multicast_filter_limit = 32; |
1da177e4 LT |
71 | |
72 | /* MAC address length */ | |
73 | #define MAC_ADDR_LEN 6 | |
74 | ||
9c14ceaf | 75 | #define MAX_READ_REQUEST_SHIFT 12 |
1da177e4 | 76 | #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ |
1da177e4 LT |
77 | #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */ |
78 | #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ | |
79 | ||
80 | #define R8169_REGS_SIZE 256 | |
81 | #define R8169_NAPI_WEIGHT 64 | |
82 | #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */ | |
83 | #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */ | |
84 | #define RX_BUF_SIZE 1536 /* Rx Buffer size */ | |
85 | #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc)) | |
86 | #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc)) | |
87 | ||
88 | #define RTL8169_TX_TIMEOUT (6*HZ) | |
89 | #define RTL8169_PHY_TIMEOUT (10*HZ) | |
90 | ||
ea8dbdd1 | 91 | #define RTL_EEPROM_SIG cpu_to_le32(0x8129) |
92 | #define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff) | |
e1564ec9 FR |
93 | #define RTL_EEPROM_SIG_ADDR 0x0000 |
94 | ||
1da177e4 LT |
95 | /* write/read MMIO register */ |
96 | #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg)) | |
97 | #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg)) | |
98 | #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg)) | |
99 | #define RTL_R8(reg) readb (ioaddr + (reg)) | |
100 | #define RTL_R16(reg) readw (ioaddr + (reg)) | |
06f555f3 | 101 | #define RTL_R32(reg) readl (ioaddr + (reg)) |
1da177e4 LT |
102 | |
103 | enum mac_version { | |
85bffe6c FR |
104 | RTL_GIGA_MAC_VER_01 = 0, |
105 | RTL_GIGA_MAC_VER_02, | |
106 | RTL_GIGA_MAC_VER_03, | |
107 | RTL_GIGA_MAC_VER_04, | |
108 | RTL_GIGA_MAC_VER_05, | |
109 | RTL_GIGA_MAC_VER_06, | |
110 | RTL_GIGA_MAC_VER_07, | |
111 | RTL_GIGA_MAC_VER_08, | |
112 | RTL_GIGA_MAC_VER_09, | |
113 | RTL_GIGA_MAC_VER_10, | |
114 | RTL_GIGA_MAC_VER_11, | |
115 | RTL_GIGA_MAC_VER_12, | |
116 | RTL_GIGA_MAC_VER_13, | |
117 | RTL_GIGA_MAC_VER_14, | |
118 | RTL_GIGA_MAC_VER_15, | |
119 | RTL_GIGA_MAC_VER_16, | |
120 | RTL_GIGA_MAC_VER_17, | |
121 | RTL_GIGA_MAC_VER_18, | |
122 | RTL_GIGA_MAC_VER_19, | |
123 | RTL_GIGA_MAC_VER_20, | |
124 | RTL_GIGA_MAC_VER_21, | |
125 | RTL_GIGA_MAC_VER_22, | |
126 | RTL_GIGA_MAC_VER_23, | |
127 | RTL_GIGA_MAC_VER_24, | |
128 | RTL_GIGA_MAC_VER_25, | |
129 | RTL_GIGA_MAC_VER_26, | |
130 | RTL_GIGA_MAC_VER_27, | |
131 | RTL_GIGA_MAC_VER_28, | |
132 | RTL_GIGA_MAC_VER_29, | |
133 | RTL_GIGA_MAC_VER_30, | |
134 | RTL_GIGA_MAC_VER_31, | |
135 | RTL_GIGA_MAC_VER_32, | |
136 | RTL_GIGA_MAC_VER_33, | |
70090424 | 137 | RTL_GIGA_MAC_VER_34, |
c2218925 HW |
138 | RTL_GIGA_MAC_VER_35, |
139 | RTL_GIGA_MAC_VER_36, | |
85bffe6c | 140 | RTL_GIGA_MAC_NONE = 0xff, |
1da177e4 LT |
141 | }; |
142 | ||
2b7b4318 FR |
143 | enum rtl_tx_desc_version { |
144 | RTL_TD_0 = 0, | |
145 | RTL_TD_1 = 1, | |
146 | }; | |
147 | ||
d58d46b5 FR |
148 | #define JUMBO_1K ETH_DATA_LEN |
149 | #define JUMBO_4K (4*1024 - ETH_HLEN - 2) | |
150 | #define JUMBO_6K (6*1024 - ETH_HLEN - 2) | |
151 | #define JUMBO_7K (7*1024 - ETH_HLEN - 2) | |
152 | #define JUMBO_9K (9*1024 - ETH_HLEN - 2) | |
153 | ||
154 | #define _R(NAME,TD,FW,SZ,B) { \ | |
155 | .name = NAME, \ | |
156 | .txd_version = TD, \ | |
157 | .fw_name = FW, \ | |
158 | .jumbo_max = SZ, \ | |
159 | .jumbo_tx_csum = B \ | |
160 | } | |
1da177e4 | 161 | |
3c6bee1d | 162 | static const struct { |
1da177e4 | 163 | const char *name; |
2b7b4318 | 164 | enum rtl_tx_desc_version txd_version; |
953a12cc | 165 | const char *fw_name; |
d58d46b5 FR |
166 | u16 jumbo_max; |
167 | bool jumbo_tx_csum; | |
85bffe6c FR |
168 | } rtl_chip_infos[] = { |
169 | /* PCI devices. */ | |
170 | [RTL_GIGA_MAC_VER_01] = | |
d58d46b5 | 171 | _R("RTL8169", RTL_TD_0, NULL, JUMBO_7K, true), |
85bffe6c | 172 | [RTL_GIGA_MAC_VER_02] = |
d58d46b5 | 173 | _R("RTL8169s", RTL_TD_0, NULL, JUMBO_7K, true), |
85bffe6c | 174 | [RTL_GIGA_MAC_VER_03] = |
d58d46b5 | 175 | _R("RTL8110s", RTL_TD_0, NULL, JUMBO_7K, true), |
85bffe6c | 176 | [RTL_GIGA_MAC_VER_04] = |
d58d46b5 | 177 | _R("RTL8169sb/8110sb", RTL_TD_0, NULL, JUMBO_7K, true), |
85bffe6c | 178 | [RTL_GIGA_MAC_VER_05] = |
d58d46b5 | 179 | _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true), |
85bffe6c | 180 | [RTL_GIGA_MAC_VER_06] = |
d58d46b5 | 181 | _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true), |
85bffe6c FR |
182 | /* PCI-E devices. */ |
183 | [RTL_GIGA_MAC_VER_07] = | |
d58d46b5 | 184 | _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true), |
85bffe6c | 185 | [RTL_GIGA_MAC_VER_08] = |
d58d46b5 | 186 | _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true), |
85bffe6c | 187 | [RTL_GIGA_MAC_VER_09] = |
d58d46b5 | 188 | _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true), |
85bffe6c | 189 | [RTL_GIGA_MAC_VER_10] = |
d58d46b5 | 190 | _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true), |
85bffe6c | 191 | [RTL_GIGA_MAC_VER_11] = |
d58d46b5 | 192 | _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false), |
85bffe6c | 193 | [RTL_GIGA_MAC_VER_12] = |
d58d46b5 | 194 | _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false), |
85bffe6c | 195 | [RTL_GIGA_MAC_VER_13] = |
d58d46b5 | 196 | _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true), |
85bffe6c | 197 | [RTL_GIGA_MAC_VER_14] = |
d58d46b5 | 198 | _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true), |
85bffe6c | 199 | [RTL_GIGA_MAC_VER_15] = |
d58d46b5 | 200 | _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true), |
85bffe6c | 201 | [RTL_GIGA_MAC_VER_16] = |
d58d46b5 | 202 | _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true), |
85bffe6c | 203 | [RTL_GIGA_MAC_VER_17] = |
d58d46b5 | 204 | _R("RTL8168b/8111b", RTL_TD_1, NULL, JUMBO_4K, false), |
85bffe6c | 205 | [RTL_GIGA_MAC_VER_18] = |
d58d46b5 | 206 | _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false), |
85bffe6c | 207 | [RTL_GIGA_MAC_VER_19] = |
d58d46b5 | 208 | _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false), |
85bffe6c | 209 | [RTL_GIGA_MAC_VER_20] = |
d58d46b5 | 210 | _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false), |
85bffe6c | 211 | [RTL_GIGA_MAC_VER_21] = |
d58d46b5 | 212 | _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false), |
85bffe6c | 213 | [RTL_GIGA_MAC_VER_22] = |
d58d46b5 | 214 | _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false), |
85bffe6c | 215 | [RTL_GIGA_MAC_VER_23] = |
d58d46b5 | 216 | _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false), |
85bffe6c | 217 | [RTL_GIGA_MAC_VER_24] = |
d58d46b5 | 218 | _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false), |
85bffe6c | 219 | [RTL_GIGA_MAC_VER_25] = |
d58d46b5 FR |
220 | _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1, |
221 | JUMBO_9K, false), | |
85bffe6c | 222 | [RTL_GIGA_MAC_VER_26] = |
d58d46b5 FR |
223 | _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2, |
224 | JUMBO_9K, false), | |
85bffe6c | 225 | [RTL_GIGA_MAC_VER_27] = |
d58d46b5 | 226 | _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false), |
85bffe6c | 227 | [RTL_GIGA_MAC_VER_28] = |
d58d46b5 | 228 | _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false), |
85bffe6c | 229 | [RTL_GIGA_MAC_VER_29] = |
d58d46b5 FR |
230 | _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1, |
231 | JUMBO_1K, true), | |
85bffe6c | 232 | [RTL_GIGA_MAC_VER_30] = |
d58d46b5 FR |
233 | _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1, |
234 | JUMBO_1K, true), | |
85bffe6c | 235 | [RTL_GIGA_MAC_VER_31] = |
d58d46b5 | 236 | _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false), |
85bffe6c | 237 | [RTL_GIGA_MAC_VER_32] = |
d58d46b5 FR |
238 | _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1, |
239 | JUMBO_9K, false), | |
85bffe6c | 240 | [RTL_GIGA_MAC_VER_33] = |
d58d46b5 FR |
241 | _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2, |
242 | JUMBO_9K, false), | |
70090424 | 243 | [RTL_GIGA_MAC_VER_34] = |
d58d46b5 FR |
244 | _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3, |
245 | JUMBO_9K, false), | |
c2218925 | 246 | [RTL_GIGA_MAC_VER_35] = |
d58d46b5 FR |
247 | _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_1, |
248 | JUMBO_9K, false), | |
c2218925 | 249 | [RTL_GIGA_MAC_VER_36] = |
d58d46b5 FR |
250 | _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_2, |
251 | JUMBO_9K, false), | |
953a12cc | 252 | }; |
85bffe6c | 253 | #undef _R |
953a12cc | 254 | |
bcf0bf90 FR |
255 | enum cfg_version { |
256 | RTL_CFG_0 = 0x00, | |
257 | RTL_CFG_1, | |
258 | RTL_CFG_2 | |
259 | }; | |
260 | ||
07ce4064 FR |
261 | static void rtl_hw_start_8169(struct net_device *); |
262 | static void rtl_hw_start_8168(struct net_device *); | |
263 | static void rtl_hw_start_8101(struct net_device *); | |
264 | ||
a3aa1884 | 265 | static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = { |
bcf0bf90 | 266 | { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 }, |
d2eed8cf | 267 | { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 }, |
d81bf551 | 268 | { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 }, |
07ce4064 | 269 | { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 }, |
bcf0bf90 FR |
270 | { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 }, |
271 | { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 }, | |
93a3aa25 | 272 | { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 }, |
bc1660b5 | 273 | { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 }, |
bcf0bf90 FR |
274 | { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 }, |
275 | { PCI_VENDOR_ID_LINKSYS, 0x1032, | |
276 | PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 }, | |
11d2e282 CM |
277 | { 0x0001, 0x8168, |
278 | PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 }, | |
1da177e4 LT |
279 | {0,}, |
280 | }; | |
281 | ||
282 | MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl); | |
283 | ||
6f0333b8 | 284 | static int rx_buf_sz = 16383; |
4300e8c7 | 285 | static int use_dac; |
b57b7e5a SH |
286 | static struct { |
287 | u32 msg_enable; | |
288 | } debug = { -1 }; | |
1da177e4 | 289 | |
07d3f51f FR |
290 | enum rtl_registers { |
291 | MAC0 = 0, /* Ethernet hardware address. */ | |
773d2021 | 292 | MAC4 = 4, |
07d3f51f FR |
293 | MAR0 = 8, /* Multicast filter. */ |
294 | CounterAddrLow = 0x10, | |
295 | CounterAddrHigh = 0x14, | |
296 | TxDescStartAddrLow = 0x20, | |
297 | TxDescStartAddrHigh = 0x24, | |
298 | TxHDescStartAddrLow = 0x28, | |
299 | TxHDescStartAddrHigh = 0x2c, | |
300 | FLASH = 0x30, | |
301 | ERSR = 0x36, | |
302 | ChipCmd = 0x37, | |
303 | TxPoll = 0x38, | |
304 | IntrMask = 0x3c, | |
305 | IntrStatus = 0x3e, | |
4f6b00e5 | 306 | |
07d3f51f | 307 | TxConfig = 0x40, |
4f6b00e5 HW |
308 | #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */ |
309 | #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */ | |
2b7b4318 | 310 | |
4f6b00e5 HW |
311 | RxConfig = 0x44, |
312 | #define RX128_INT_EN (1 << 15) /* 8111c and later */ | |
313 | #define RX_MULTI_EN (1 << 14) /* 8111c only */ | |
314 | #define RXCFG_FIFO_SHIFT 13 | |
315 | /* No threshold before first PCI xfer */ | |
316 | #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT) | |
317 | #define RXCFG_DMA_SHIFT 8 | |
318 | /* Unlimited maximum PCI burst. */ | |
319 | #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT) | |
2b7b4318 | 320 | |
07d3f51f FR |
321 | RxMissed = 0x4c, |
322 | Cfg9346 = 0x50, | |
323 | Config0 = 0x51, | |
324 | Config1 = 0x52, | |
325 | Config2 = 0x53, | |
326 | Config3 = 0x54, | |
327 | Config4 = 0x55, | |
328 | Config5 = 0x56, | |
329 | MultiIntr = 0x5c, | |
330 | PHYAR = 0x60, | |
07d3f51f FR |
331 | PHYstatus = 0x6c, |
332 | RxMaxSize = 0xda, | |
333 | CPlusCmd = 0xe0, | |
334 | IntrMitigate = 0xe2, | |
335 | RxDescAddrLow = 0xe4, | |
336 | RxDescAddrHigh = 0xe8, | |
f0298f81 | 337 | EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */ |
338 | ||
339 | #define NoEarlyTx 0x3f /* Max value : no early transmit. */ | |
340 | ||
341 | MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */ | |
342 | ||
343 | #define TxPacketMax (8064 >> 7) | |
3090bd9a | 344 | #define EarlySize 0x27 |
f0298f81 | 345 | |
07d3f51f FR |
346 | FuncEvent = 0xf0, |
347 | FuncEventMask = 0xf4, | |
348 | FuncPresetState = 0xf8, | |
349 | FuncForceEvent = 0xfc, | |
1da177e4 LT |
350 | }; |
351 | ||
f162a5d1 FR |
352 | enum rtl8110_registers { |
353 | TBICSR = 0x64, | |
354 | TBI_ANAR = 0x68, | |
355 | TBI_LPAR = 0x6a, | |
356 | }; | |
357 | ||
358 | enum rtl8168_8101_registers { | |
359 | CSIDR = 0x64, | |
360 | CSIAR = 0x68, | |
361 | #define CSIAR_FLAG 0x80000000 | |
362 | #define CSIAR_WRITE_CMD 0x80000000 | |
363 | #define CSIAR_BYTE_ENABLE 0x0f | |
364 | #define CSIAR_BYTE_ENABLE_SHIFT 12 | |
365 | #define CSIAR_ADDR_MASK 0x0fff | |
065c27c1 | 366 | PMCH = 0x6f, |
f162a5d1 FR |
367 | EPHYAR = 0x80, |
368 | #define EPHYAR_FLAG 0x80000000 | |
369 | #define EPHYAR_WRITE_CMD 0x80000000 | |
370 | #define EPHYAR_REG_MASK 0x1f | |
371 | #define EPHYAR_REG_SHIFT 16 | |
372 | #define EPHYAR_DATA_MASK 0xffff | |
5a5e4443 | 373 | DLLPR = 0xd0, |
4f6b00e5 | 374 | #define PFM_EN (1 << 6) |
f162a5d1 FR |
375 | DBG_REG = 0xd1, |
376 | #define FIX_NAK_1 (1 << 4) | |
377 | #define FIX_NAK_2 (1 << 3) | |
5a5e4443 HW |
378 | TWSI = 0xd2, |
379 | MCU = 0xd3, | |
4f6b00e5 | 380 | #define NOW_IS_OOB (1 << 7) |
5a5e4443 HW |
381 | #define EN_NDP (1 << 3) |
382 | #define EN_OOB_RESET (1 << 2) | |
daf9df6d | 383 | EFUSEAR = 0xdc, |
384 | #define EFUSEAR_FLAG 0x80000000 | |
385 | #define EFUSEAR_WRITE_CMD 0x80000000 | |
386 | #define EFUSEAR_READ_CMD 0x00000000 | |
387 | #define EFUSEAR_REG_MASK 0x03ff | |
388 | #define EFUSEAR_REG_SHIFT 8 | |
389 | #define EFUSEAR_DATA_MASK 0xff | |
f162a5d1 FR |
390 | }; |
391 | ||
c0e45c1c | 392 | enum rtl8168_registers { |
4f6b00e5 HW |
393 | LED_FREQ = 0x1a, |
394 | EEE_LED = 0x1b, | |
b646d900 | 395 | ERIDR = 0x70, |
396 | ERIAR = 0x74, | |
397 | #define ERIAR_FLAG 0x80000000 | |
398 | #define ERIAR_WRITE_CMD 0x80000000 | |
399 | #define ERIAR_READ_CMD 0x00000000 | |
400 | #define ERIAR_ADDR_BYTE_ALIGN 4 | |
b646d900 | 401 | #define ERIAR_TYPE_SHIFT 16 |
4f6b00e5 HW |
402 | #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT) |
403 | #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT) | |
404 | #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT) | |
405 | #define ERIAR_MASK_SHIFT 12 | |
406 | #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT) | |
407 | #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT) | |
408 | #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT) | |
c0e45c1c | 409 | EPHY_RXER_NUM = 0x7c, |
410 | OCPDR = 0xb0, /* OCP GPHY access */ | |
411 | #define OCPDR_WRITE_CMD 0x80000000 | |
412 | #define OCPDR_READ_CMD 0x00000000 | |
413 | #define OCPDR_REG_MASK 0x7f | |
414 | #define OCPDR_GPHY_REG_SHIFT 16 | |
415 | #define OCPDR_DATA_MASK 0xffff | |
416 | OCPAR = 0xb4, | |
417 | #define OCPAR_FLAG 0x80000000 | |
418 | #define OCPAR_GPHY_WRITE_CMD 0x8000f060 | |
419 | #define OCPAR_GPHY_READ_CMD 0x0000f060 | |
01dc7fec | 420 | RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */ |
421 | MISC = 0xf0, /* 8168e only. */ | |
cecb5fd7 | 422 | #define TXPLA_RST (1 << 29) |
4f6b00e5 | 423 | #define PWM_EN (1 << 22) |
c0e45c1c | 424 | }; |
425 | ||
07d3f51f | 426 | enum rtl_register_content { |
1da177e4 | 427 | /* InterruptStatusBits */ |
07d3f51f FR |
428 | SYSErr = 0x8000, |
429 | PCSTimeout = 0x4000, | |
430 | SWInt = 0x0100, | |
431 | TxDescUnavail = 0x0080, | |
432 | RxFIFOOver = 0x0040, | |
433 | LinkChg = 0x0020, | |
434 | RxOverflow = 0x0010, | |
435 | TxErr = 0x0008, | |
436 | TxOK = 0x0004, | |
437 | RxErr = 0x0002, | |
438 | RxOK = 0x0001, | |
1da177e4 LT |
439 | |
440 | /* RxStatusDesc */ | |
e03f33af | 441 | RxBOVF = (1 << 24), |
9dccf611 FR |
442 | RxFOVF = (1 << 23), |
443 | RxRWT = (1 << 22), | |
444 | RxRES = (1 << 21), | |
445 | RxRUNT = (1 << 20), | |
446 | RxCRC = (1 << 19), | |
1da177e4 LT |
447 | |
448 | /* ChipCmdBits */ | |
4f6b00e5 | 449 | StopReq = 0x80, |
07d3f51f FR |
450 | CmdReset = 0x10, |
451 | CmdRxEnb = 0x08, | |
452 | CmdTxEnb = 0x04, | |
453 | RxBufEmpty = 0x01, | |
1da177e4 | 454 | |
275391a4 FR |
455 | /* TXPoll register p.5 */ |
456 | HPQ = 0x80, /* Poll cmd on the high prio queue */ | |
457 | NPQ = 0x40, /* Poll cmd on the low prio queue */ | |
458 | FSWInt = 0x01, /* Forced software interrupt */ | |
459 | ||
1da177e4 | 460 | /* Cfg9346Bits */ |
07d3f51f FR |
461 | Cfg9346_Lock = 0x00, |
462 | Cfg9346_Unlock = 0xc0, | |
1da177e4 LT |
463 | |
464 | /* rx_mode_bits */ | |
07d3f51f FR |
465 | AcceptErr = 0x20, |
466 | AcceptRunt = 0x10, | |
467 | AcceptBroadcast = 0x08, | |
468 | AcceptMulticast = 0x04, | |
469 | AcceptMyPhys = 0x02, | |
470 | AcceptAllPhys = 0x01, | |
1687b566 | 471 | #define RX_CONFIG_ACCEPT_MASK 0x3f |
1da177e4 | 472 | |
1da177e4 LT |
473 | /* TxConfigBits */ |
474 | TxInterFrameGapShift = 24, | |
475 | TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ | |
476 | ||
5d06a99f | 477 | /* Config1 register p.24 */ |
f162a5d1 FR |
478 | LEDS1 = (1 << 7), |
479 | LEDS0 = (1 << 6), | |
fbac58fc | 480 | MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */ |
f162a5d1 FR |
481 | Speed_down = (1 << 4), |
482 | MEMMAP = (1 << 3), | |
483 | IOMAP = (1 << 2), | |
484 | VPD = (1 << 1), | |
5d06a99f FR |
485 | PMEnable = (1 << 0), /* Power Management Enable */ |
486 | ||
6dccd16b FR |
487 | /* Config2 register p. 25 */ |
488 | PCI_Clock_66MHz = 0x01, | |
489 | PCI_Clock_33MHz = 0x00, | |
490 | ||
61a4dcc2 FR |
491 | /* Config3 register p.25 */ |
492 | MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */ | |
493 | LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */ | |
d58d46b5 | 494 | Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */ |
f162a5d1 | 495 | Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */ |
61a4dcc2 | 496 | |
d58d46b5 FR |
497 | /* Config4 register */ |
498 | Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */ | |
499 | ||
5d06a99f | 500 | /* Config5 register p.27 */ |
61a4dcc2 FR |
501 | BWF = (1 << 6), /* Accept Broadcast wakeup frame */ |
502 | MWF = (1 << 5), /* Accept Multicast wakeup frame */ | |
503 | UWF = (1 << 4), /* Accept Unicast wakeup frame */ | |
cecb5fd7 | 504 | Spi_en = (1 << 3), |
61a4dcc2 | 505 | LanWake = (1 << 1), /* LanWake enable/disable */ |
5d06a99f FR |
506 | PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */ |
507 | ||
1da177e4 LT |
508 | /* TBICSR p.28 */ |
509 | TBIReset = 0x80000000, | |
510 | TBILoopback = 0x40000000, | |
511 | TBINwEnable = 0x20000000, | |
512 | TBINwRestart = 0x10000000, | |
513 | TBILinkOk = 0x02000000, | |
514 | TBINwComplete = 0x01000000, | |
515 | ||
516 | /* CPlusCmd p.31 */ | |
f162a5d1 FR |
517 | EnableBist = (1 << 15), // 8168 8101 |
518 | Mac_dbgo_oe = (1 << 14), // 8168 8101 | |
519 | Normal_mode = (1 << 13), // unused | |
520 | Force_half_dup = (1 << 12), // 8168 8101 | |
521 | Force_rxflow_en = (1 << 11), // 8168 8101 | |
522 | Force_txflow_en = (1 << 10), // 8168 8101 | |
523 | Cxpl_dbg_sel = (1 << 9), // 8168 8101 | |
524 | ASF = (1 << 8), // 8168 8101 | |
525 | PktCntrDisable = (1 << 7), // 8168 8101 | |
526 | Mac_dbgo_sel = 0x001c, // 8168 | |
1da177e4 LT |
527 | RxVlan = (1 << 6), |
528 | RxChkSum = (1 << 5), | |
529 | PCIDAC = (1 << 4), | |
530 | PCIMulRW = (1 << 3), | |
0e485150 FR |
531 | INTT_0 = 0x0000, // 8168 |
532 | INTT_1 = 0x0001, // 8168 | |
533 | INTT_2 = 0x0002, // 8168 | |
534 | INTT_3 = 0x0003, // 8168 | |
1da177e4 LT |
535 | |
536 | /* rtl8169_PHYstatus */ | |
07d3f51f FR |
537 | TBI_Enable = 0x80, |
538 | TxFlowCtrl = 0x40, | |
539 | RxFlowCtrl = 0x20, | |
540 | _1000bpsF = 0x10, | |
541 | _100bps = 0x08, | |
542 | _10bps = 0x04, | |
543 | LinkStatus = 0x02, | |
544 | FullDup = 0x01, | |
1da177e4 | 545 | |
1da177e4 | 546 | /* _TBICSRBit */ |
07d3f51f | 547 | TBILinkOK = 0x02000000, |
d4a3a0fc SH |
548 | |
549 | /* DumpCounterCommand */ | |
07d3f51f | 550 | CounterDump = 0x8, |
1da177e4 LT |
551 | }; |
552 | ||
2b7b4318 FR |
553 | enum rtl_desc_bit { |
554 | /* First doubleword. */ | |
1da177e4 LT |
555 | DescOwn = (1 << 31), /* Descriptor is owned by NIC */ |
556 | RingEnd = (1 << 30), /* End of descriptor ring */ | |
557 | FirstFrag = (1 << 29), /* First segment of a packet */ | |
558 | LastFrag = (1 << 28), /* Final segment of a packet */ | |
2b7b4318 FR |
559 | }; |
560 | ||
561 | /* Generic case. */ | |
562 | enum rtl_tx_desc_bit { | |
563 | /* First doubleword. */ | |
564 | TD_LSO = (1 << 27), /* Large Send Offload */ | |
565 | #define TD_MSS_MAX 0x07ffu /* MSS value */ | |
1da177e4 | 566 | |
2b7b4318 FR |
567 | /* Second doubleword. */ |
568 | TxVlanTag = (1 << 17), /* Add VLAN tag */ | |
569 | }; | |
570 | ||
571 | /* 8169, 8168b and 810x except 8102e. */ | |
572 | enum rtl_tx_desc_bit_0 { | |
573 | /* First doubleword. */ | |
574 | #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */ | |
575 | TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */ | |
576 | TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */ | |
577 | TD0_IP_CS = (1 << 18), /* Calculate IP checksum */ | |
578 | }; | |
579 | ||
580 | /* 8102e, 8168c and beyond. */ | |
581 | enum rtl_tx_desc_bit_1 { | |
582 | /* Second doubleword. */ | |
583 | #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */ | |
584 | TD1_IP_CS = (1 << 29), /* Calculate IP checksum */ | |
585 | TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */ | |
586 | TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */ | |
587 | }; | |
1da177e4 | 588 | |
2b7b4318 FR |
589 | static const struct rtl_tx_desc_info { |
590 | struct { | |
591 | u32 udp; | |
592 | u32 tcp; | |
593 | } checksum; | |
594 | u16 mss_shift; | |
595 | u16 opts_offset; | |
596 | } tx_desc_info [] = { | |
597 | [RTL_TD_0] = { | |
598 | .checksum = { | |
599 | .udp = TD0_IP_CS | TD0_UDP_CS, | |
600 | .tcp = TD0_IP_CS | TD0_TCP_CS | |
601 | }, | |
602 | .mss_shift = TD0_MSS_SHIFT, | |
603 | .opts_offset = 0 | |
604 | }, | |
605 | [RTL_TD_1] = { | |
606 | .checksum = { | |
607 | .udp = TD1_IP_CS | TD1_UDP_CS, | |
608 | .tcp = TD1_IP_CS | TD1_TCP_CS | |
609 | }, | |
610 | .mss_shift = TD1_MSS_SHIFT, | |
611 | .opts_offset = 1 | |
612 | } | |
613 | }; | |
614 | ||
615 | enum rtl_rx_desc_bit { | |
1da177e4 LT |
616 | /* Rx private */ |
617 | PID1 = (1 << 18), /* Protocol ID bit 1/2 */ | |
618 | PID0 = (1 << 17), /* Protocol ID bit 2/2 */ | |
619 | ||
620 | #define RxProtoUDP (PID1) | |
621 | #define RxProtoTCP (PID0) | |
622 | #define RxProtoIP (PID1 | PID0) | |
623 | #define RxProtoMask RxProtoIP | |
624 | ||
625 | IPFail = (1 << 16), /* IP checksum failed */ | |
626 | UDPFail = (1 << 15), /* UDP/IP checksum failed */ | |
627 | TCPFail = (1 << 14), /* TCP/IP checksum failed */ | |
628 | RxVlanTag = (1 << 16), /* VLAN tag available */ | |
629 | }; | |
630 | ||
631 | #define RsvdMask 0x3fffc000 | |
632 | ||
633 | struct TxDesc { | |
6cccd6e7 REB |
634 | __le32 opts1; |
635 | __le32 opts2; | |
636 | __le64 addr; | |
1da177e4 LT |
637 | }; |
638 | ||
639 | struct RxDesc { | |
6cccd6e7 REB |
640 | __le32 opts1; |
641 | __le32 opts2; | |
642 | __le64 addr; | |
1da177e4 LT |
643 | }; |
644 | ||
645 | struct ring_info { | |
646 | struct sk_buff *skb; | |
647 | u32 len; | |
648 | u8 __pad[sizeof(void *) - sizeof(u32)]; | |
649 | }; | |
650 | ||
f23e7fda | 651 | enum features { |
ccdffb9a FR |
652 | RTL_FEATURE_WOL = (1 << 0), |
653 | RTL_FEATURE_MSI = (1 << 1), | |
654 | RTL_FEATURE_GMII = (1 << 2), | |
f23e7fda FR |
655 | }; |
656 | ||
355423d0 IV |
657 | struct rtl8169_counters { |
658 | __le64 tx_packets; | |
659 | __le64 rx_packets; | |
660 | __le64 tx_errors; | |
661 | __le32 rx_errors; | |
662 | __le16 rx_missed; | |
663 | __le16 align_errors; | |
664 | __le32 tx_one_collision; | |
665 | __le32 tx_multi_collision; | |
666 | __le64 rx_unicast; | |
667 | __le64 rx_broadcast; | |
668 | __le32 rx_multicast; | |
669 | __le16 tx_aborted; | |
670 | __le16 tx_underun; | |
671 | }; | |
672 | ||
1da177e4 LT |
673 | struct rtl8169_private { |
674 | void __iomem *mmio_addr; /* memory map physical address */ | |
cecb5fd7 | 675 | struct pci_dev *pci_dev; |
c4028958 | 676 | struct net_device *dev; |
bea3348e | 677 | struct napi_struct napi; |
cecb5fd7 | 678 | spinlock_t lock; |
b57b7e5a | 679 | u32 msg_enable; |
2b7b4318 FR |
680 | u16 txd_version; |
681 | u16 mac_version; | |
1da177e4 LT |
682 | u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ |
683 | u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ | |
684 | u32 dirty_rx; | |
685 | u32 dirty_tx; | |
686 | struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */ | |
687 | struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */ | |
688 | dma_addr_t TxPhyAddr; | |
689 | dma_addr_t RxPhyAddr; | |
6f0333b8 | 690 | void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */ |
1da177e4 | 691 | struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */ |
1da177e4 LT |
692 | struct timer_list timer; |
693 | u16 cp_cmd; | |
0e485150 FR |
694 | u16 intr_event; |
695 | u16 napi_event; | |
1da177e4 | 696 | u16 intr_mask; |
c0e45c1c | 697 | |
698 | struct mdio_ops { | |
699 | void (*write)(void __iomem *, int, int); | |
700 | int (*read)(void __iomem *, int); | |
701 | } mdio_ops; | |
702 | ||
065c27c1 | 703 | struct pll_power_ops { |
704 | void (*down)(struct rtl8169_private *); | |
705 | void (*up)(struct rtl8169_private *); | |
706 | } pll_power_ops; | |
707 | ||
d58d46b5 FR |
708 | struct jumbo_ops { |
709 | void (*enable)(struct rtl8169_private *); | |
710 | void (*disable)(struct rtl8169_private *); | |
711 | } jumbo_ops; | |
712 | ||
54405cde | 713 | int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv); |
ccdffb9a | 714 | int (*get_settings)(struct net_device *, struct ethtool_cmd *); |
4da19633 | 715 | void (*phy_reset_enable)(struct rtl8169_private *tp); |
07ce4064 | 716 | void (*hw_start)(struct net_device *); |
4da19633 | 717 | unsigned int (*phy_reset_pending)(struct rtl8169_private *tp); |
1da177e4 | 718 | unsigned int (*link_ok)(void __iomem *); |
8b4ab28d | 719 | int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd); |
c4028958 | 720 | struct delayed_work task; |
f23e7fda | 721 | unsigned features; |
ccdffb9a FR |
722 | |
723 | struct mii_if_info mii; | |
355423d0 | 724 | struct rtl8169_counters counters; |
e1759441 | 725 | u32 saved_wolopts; |
e03f33af | 726 | u32 opts1_mask; |
f1e02ed1 | 727 | |
b6ffd97f FR |
728 | struct rtl_fw { |
729 | const struct firmware *fw; | |
1c361efb FR |
730 | |
731 | #define RTL_VER_SIZE 32 | |
732 | ||
733 | char version[RTL_VER_SIZE]; | |
734 | ||
735 | struct rtl_fw_phy_action { | |
736 | __le32 *code; | |
737 | size_t size; | |
738 | } phy_action; | |
b6ffd97f | 739 | } *rtl_fw; |
497888cf | 740 | #define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN) |
1da177e4 LT |
741 | }; |
742 | ||
979b6c13 | 743 | MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>"); |
1da177e4 | 744 | MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver"); |
1da177e4 | 745 | module_param(use_dac, int, 0); |
4300e8c7 | 746 | MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot."); |
b57b7e5a SH |
747 | module_param_named(debug, debug.msg_enable, int, 0); |
748 | MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)"); | |
1da177e4 LT |
749 | MODULE_LICENSE("GPL"); |
750 | MODULE_VERSION(RTL8169_VERSION); | |
bca03d5f | 751 | MODULE_FIRMWARE(FIRMWARE_8168D_1); |
752 | MODULE_FIRMWARE(FIRMWARE_8168D_2); | |
01dc7fec | 753 | MODULE_FIRMWARE(FIRMWARE_8168E_1); |
754 | MODULE_FIRMWARE(FIRMWARE_8168E_2); | |
bbb8af75 | 755 | MODULE_FIRMWARE(FIRMWARE_8168E_3); |
5a5e4443 | 756 | MODULE_FIRMWARE(FIRMWARE_8105E_1); |
c2218925 HW |
757 | MODULE_FIRMWARE(FIRMWARE_8168F_1); |
758 | MODULE_FIRMWARE(FIRMWARE_8168F_2); | |
1da177e4 LT |
759 | |
760 | static int rtl8169_open(struct net_device *dev); | |
61357325 SH |
761 | static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb, |
762 | struct net_device *dev); | |
7d12e780 | 763 | static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance); |
1da177e4 | 764 | static int rtl8169_init_ring(struct net_device *dev); |
07ce4064 | 765 | static void rtl_hw_start(struct net_device *dev); |
1da177e4 | 766 | static int rtl8169_close(struct net_device *dev); |
07ce4064 | 767 | static void rtl_set_rx_mode(struct net_device *dev); |
1da177e4 | 768 | static void rtl8169_tx_timeout(struct net_device *dev); |
4dcb7d33 | 769 | static struct net_device_stats *rtl8169_get_stats(struct net_device *dev); |
1da177e4 | 770 | static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *, |
bea3348e | 771 | void __iomem *, u32 budget); |
4dcb7d33 | 772 | static int rtl8169_change_mtu(struct net_device *dev, int new_mtu); |
1da177e4 | 773 | static void rtl8169_down(struct net_device *dev); |
99f252b0 | 774 | static void rtl8169_rx_clear(struct rtl8169_private *tp); |
bea3348e | 775 | static int rtl8169_poll(struct napi_struct *napi, int budget); |
1da177e4 | 776 | |
d58d46b5 FR |
777 | static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force) |
778 | { | |
779 | int cap = pci_pcie_cap(pdev); | |
780 | ||
781 | if (cap) { | |
782 | u16 ctl; | |
783 | ||
784 | pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl); | |
785 | ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force; | |
786 | pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl); | |
787 | } | |
788 | } | |
789 | ||
b646d900 | 790 | static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg) |
791 | { | |
792 | void __iomem *ioaddr = tp->mmio_addr; | |
793 | int i; | |
794 | ||
795 | RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); | |
796 | for (i = 0; i < 20; i++) { | |
797 | udelay(100); | |
798 | if (RTL_R32(OCPAR) & OCPAR_FLAG) | |
799 | break; | |
800 | } | |
801 | return RTL_R32(OCPDR); | |
802 | } | |
803 | ||
804 | static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data) | |
805 | { | |
806 | void __iomem *ioaddr = tp->mmio_addr; | |
807 | int i; | |
808 | ||
809 | RTL_W32(OCPDR, data); | |
810 | RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); | |
811 | for (i = 0; i < 20; i++) { | |
812 | udelay(100); | |
813 | if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0) | |
814 | break; | |
815 | } | |
816 | } | |
817 | ||
fac5b3ca | 818 | static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd) |
b646d900 | 819 | { |
fac5b3ca | 820 | void __iomem *ioaddr = tp->mmio_addr; |
b646d900 | 821 | int i; |
822 | ||
823 | RTL_W8(ERIDR, cmd); | |
824 | RTL_W32(ERIAR, 0x800010e8); | |
825 | msleep(2); | |
826 | for (i = 0; i < 5; i++) { | |
827 | udelay(100); | |
1e4e82ba | 828 | if (!(RTL_R32(ERIAR) & ERIAR_FLAG)) |
b646d900 | 829 | break; |
830 | } | |
831 | ||
fac5b3ca | 832 | ocp_write(tp, 0x1, 0x30, 0x00000001); |
b646d900 | 833 | } |
834 | ||
835 | #define OOB_CMD_RESET 0x00 | |
836 | #define OOB_CMD_DRIVER_START 0x05 | |
837 | #define OOB_CMD_DRIVER_STOP 0x06 | |
838 | ||
cecb5fd7 FR |
839 | static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp) |
840 | { | |
841 | return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10; | |
842 | } | |
843 | ||
b646d900 | 844 | static void rtl8168_driver_start(struct rtl8169_private *tp) |
845 | { | |
cecb5fd7 | 846 | u16 reg; |
b646d900 | 847 | int i; |
848 | ||
849 | rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START); | |
850 | ||
cecb5fd7 | 851 | reg = rtl8168_get_ocp_reg(tp); |
4804b3b3 | 852 | |
b646d900 | 853 | for (i = 0; i < 10; i++) { |
854 | msleep(10); | |
4804b3b3 | 855 | if (ocp_read(tp, 0x0f, reg) & 0x00000800) |
b646d900 | 856 | break; |
857 | } | |
858 | } | |
859 | ||
860 | static void rtl8168_driver_stop(struct rtl8169_private *tp) | |
861 | { | |
cecb5fd7 | 862 | u16 reg; |
b646d900 | 863 | int i; |
864 | ||
865 | rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP); | |
866 | ||
cecb5fd7 | 867 | reg = rtl8168_get_ocp_reg(tp); |
4804b3b3 | 868 | |
b646d900 | 869 | for (i = 0; i < 10; i++) { |
870 | msleep(10); | |
4804b3b3 | 871 | if ((ocp_read(tp, 0x0f, reg) & 0x00000800) == 0) |
b646d900 | 872 | break; |
873 | } | |
874 | } | |
875 | ||
4804b3b3 | 876 | static int r8168dp_check_dash(struct rtl8169_private *tp) |
877 | { | |
cecb5fd7 | 878 | u16 reg = rtl8168_get_ocp_reg(tp); |
4804b3b3 | 879 | |
cecb5fd7 | 880 | return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0; |
4804b3b3 | 881 | } |
b646d900 | 882 | |
4da19633 | 883 | static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value) |
1da177e4 LT |
884 | { |
885 | int i; | |
886 | ||
a6baf3af | 887 | RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff)); |
1da177e4 | 888 | |
2371408c | 889 | for (i = 20; i > 0; i--) { |
07d3f51f FR |
890 | /* |
891 | * Check if the RTL8169 has completed writing to the specified | |
892 | * MII register. | |
893 | */ | |
5b0384f4 | 894 | if (!(RTL_R32(PHYAR) & 0x80000000)) |
1da177e4 | 895 | break; |
2371408c | 896 | udelay(25); |
1da177e4 | 897 | } |
024a07ba | 898 | /* |
81a95f04 TT |
899 | * According to hardware specs a 20us delay is required after write |
900 | * complete indication, but before sending next command. | |
024a07ba | 901 | */ |
81a95f04 | 902 | udelay(20); |
1da177e4 LT |
903 | } |
904 | ||
4da19633 | 905 | static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr) |
1da177e4 LT |
906 | { |
907 | int i, value = -1; | |
908 | ||
a6baf3af | 909 | RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16); |
1da177e4 | 910 | |
2371408c | 911 | for (i = 20; i > 0; i--) { |
07d3f51f FR |
912 | /* |
913 | * Check if the RTL8169 has completed retrieving data from | |
914 | * the specified MII register. | |
915 | */ | |
1da177e4 | 916 | if (RTL_R32(PHYAR) & 0x80000000) { |
a6baf3af | 917 | value = RTL_R32(PHYAR) & 0xffff; |
1da177e4 LT |
918 | break; |
919 | } | |
2371408c | 920 | udelay(25); |
1da177e4 | 921 | } |
81a95f04 TT |
922 | /* |
923 | * According to hardware specs a 20us delay is required after read | |
924 | * complete indication, but before sending next command. | |
925 | */ | |
926 | udelay(20); | |
927 | ||
1da177e4 LT |
928 | return value; |
929 | } | |
930 | ||
c0e45c1c | 931 | static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data) |
932 | { | |
933 | int i; | |
934 | ||
935 | RTL_W32(OCPDR, data | | |
936 | ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT)); | |
937 | RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD); | |
938 | RTL_W32(EPHY_RXER_NUM, 0); | |
939 | ||
940 | for (i = 0; i < 100; i++) { | |
941 | mdelay(1); | |
942 | if (!(RTL_R32(OCPAR) & OCPAR_FLAG)) | |
943 | break; | |
944 | } | |
945 | } | |
946 | ||
947 | static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value) | |
948 | { | |
949 | r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD | | |
950 | (value & OCPDR_DATA_MASK)); | |
951 | } | |
952 | ||
953 | static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr) | |
954 | { | |
955 | int i; | |
956 | ||
957 | r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD); | |
958 | ||
959 | mdelay(1); | |
960 | RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD); | |
961 | RTL_W32(EPHY_RXER_NUM, 0); | |
962 | ||
963 | for (i = 0; i < 100; i++) { | |
964 | mdelay(1); | |
965 | if (RTL_R32(OCPAR) & OCPAR_FLAG) | |
966 | break; | |
967 | } | |
968 | ||
969 | return RTL_R32(OCPDR) & OCPDR_DATA_MASK; | |
970 | } | |
971 | ||
e6de30d6 | 972 | #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000 |
973 | ||
974 | static void r8168dp_2_mdio_start(void __iomem *ioaddr) | |
975 | { | |
976 | RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT); | |
977 | } | |
978 | ||
979 | static void r8168dp_2_mdio_stop(void __iomem *ioaddr) | |
980 | { | |
981 | RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT); | |
982 | } | |
983 | ||
984 | static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value) | |
985 | { | |
986 | r8168dp_2_mdio_start(ioaddr); | |
987 | ||
988 | r8169_mdio_write(ioaddr, reg_addr, value); | |
989 | ||
990 | r8168dp_2_mdio_stop(ioaddr); | |
991 | } | |
992 | ||
993 | static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr) | |
994 | { | |
995 | int value; | |
996 | ||
997 | r8168dp_2_mdio_start(ioaddr); | |
998 | ||
999 | value = r8169_mdio_read(ioaddr, reg_addr); | |
1000 | ||
1001 | r8168dp_2_mdio_stop(ioaddr); | |
1002 | ||
1003 | return value; | |
1004 | } | |
1005 | ||
4da19633 | 1006 | static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val) |
dacf8154 | 1007 | { |
c0e45c1c | 1008 | tp->mdio_ops.write(tp->mmio_addr, location, val); |
dacf8154 FR |
1009 | } |
1010 | ||
4da19633 | 1011 | static int rtl_readphy(struct rtl8169_private *tp, int location) |
1012 | { | |
c0e45c1c | 1013 | return tp->mdio_ops.read(tp->mmio_addr, location); |
4da19633 | 1014 | } |
1015 | ||
1016 | static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value) | |
1017 | { | |
1018 | rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value); | |
1019 | } | |
1020 | ||
1021 | static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m) | |
daf9df6d | 1022 | { |
1023 | int val; | |
1024 | ||
4da19633 | 1025 | val = rtl_readphy(tp, reg_addr); |
1026 | rtl_writephy(tp, reg_addr, (val | p) & ~m); | |
daf9df6d | 1027 | } |
1028 | ||
ccdffb9a FR |
1029 | static void rtl_mdio_write(struct net_device *dev, int phy_id, int location, |
1030 | int val) | |
1031 | { | |
1032 | struct rtl8169_private *tp = netdev_priv(dev); | |
ccdffb9a | 1033 | |
4da19633 | 1034 | rtl_writephy(tp, location, val); |
ccdffb9a FR |
1035 | } |
1036 | ||
1037 | static int rtl_mdio_read(struct net_device *dev, int phy_id, int location) | |
1038 | { | |
1039 | struct rtl8169_private *tp = netdev_priv(dev); | |
ccdffb9a | 1040 | |
4da19633 | 1041 | return rtl_readphy(tp, location); |
ccdffb9a FR |
1042 | } |
1043 | ||
dacf8154 FR |
1044 | static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value) |
1045 | { | |
1046 | unsigned int i; | |
1047 | ||
1048 | RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) | | |
1049 | (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); | |
1050 | ||
1051 | for (i = 0; i < 100; i++) { | |
1052 | if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG)) | |
1053 | break; | |
1054 | udelay(10); | |
1055 | } | |
1056 | } | |
1057 | ||
1058 | static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr) | |
1059 | { | |
1060 | u16 value = 0xffff; | |
1061 | unsigned int i; | |
1062 | ||
1063 | RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); | |
1064 | ||
1065 | for (i = 0; i < 100; i++) { | |
1066 | if (RTL_R32(EPHYAR) & EPHYAR_FLAG) { | |
1067 | value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK; | |
1068 | break; | |
1069 | } | |
1070 | udelay(10); | |
1071 | } | |
1072 | ||
1073 | return value; | |
1074 | } | |
1075 | ||
1076 | static void rtl_csi_write(void __iomem *ioaddr, int addr, int value) | |
1077 | { | |
1078 | unsigned int i; | |
1079 | ||
1080 | RTL_W32(CSIDR, value); | |
1081 | RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | | |
1082 | CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT); | |
1083 | ||
1084 | for (i = 0; i < 100; i++) { | |
1085 | if (!(RTL_R32(CSIAR) & CSIAR_FLAG)) | |
1086 | break; | |
1087 | udelay(10); | |
1088 | } | |
1089 | } | |
1090 | ||
1091 | static u32 rtl_csi_read(void __iomem *ioaddr, int addr) | |
1092 | { | |
1093 | u32 value = ~0x00; | |
1094 | unsigned int i; | |
1095 | ||
1096 | RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | | |
1097 | CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT); | |
1098 | ||
1099 | for (i = 0; i < 100; i++) { | |
1100 | if (RTL_R32(CSIAR) & CSIAR_FLAG) { | |
1101 | value = RTL_R32(CSIDR); | |
1102 | break; | |
1103 | } | |
1104 | udelay(10); | |
1105 | } | |
1106 | ||
1107 | return value; | |
1108 | } | |
1109 | ||
133ac40a HW |
1110 | static |
1111 | void rtl_eri_write(void __iomem *ioaddr, int addr, u32 mask, u32 val, int type) | |
1112 | { | |
1113 | unsigned int i; | |
1114 | ||
1115 | BUG_ON((addr & 3) || (mask == 0)); | |
1116 | RTL_W32(ERIDR, val); | |
1117 | RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr); | |
1118 | ||
1119 | for (i = 0; i < 100; i++) { | |
1120 | if (!(RTL_R32(ERIAR) & ERIAR_FLAG)) | |
1121 | break; | |
1122 | udelay(100); | |
1123 | } | |
1124 | } | |
1125 | ||
1126 | static u32 rtl_eri_read(void __iomem *ioaddr, int addr, int type) | |
1127 | { | |
1128 | u32 value = ~0x00; | |
1129 | unsigned int i; | |
1130 | ||
1131 | RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr); | |
1132 | ||
1133 | for (i = 0; i < 100; i++) { | |
1134 | if (RTL_R32(ERIAR) & ERIAR_FLAG) { | |
1135 | value = RTL_R32(ERIDR); | |
1136 | break; | |
1137 | } | |
1138 | udelay(100); | |
1139 | } | |
1140 | ||
1141 | return value; | |
1142 | } | |
1143 | ||
1144 | static void | |
1145 | rtl_w1w0_eri(void __iomem *ioaddr, int addr, u32 mask, u32 p, u32 m, int type) | |
1146 | { | |
1147 | u32 val; | |
1148 | ||
1149 | val = rtl_eri_read(ioaddr, addr, type); | |
1150 | rtl_eri_write(ioaddr, addr, mask, (val & ~m) | p, type); | |
1151 | } | |
1152 | ||
c28aa385 | 1153 | struct exgmac_reg { |
1154 | u16 addr; | |
1155 | u16 mask; | |
1156 | u32 val; | |
1157 | }; | |
1158 | ||
1159 | static void rtl_write_exgmac_batch(void __iomem *ioaddr, | |
1160 | const struct exgmac_reg *r, int len) | |
1161 | { | |
1162 | while (len-- > 0) { | |
1163 | rtl_eri_write(ioaddr, r->addr, r->mask, r->val, ERIAR_EXGMAC); | |
1164 | r++; | |
1165 | } | |
1166 | } | |
1167 | ||
daf9df6d | 1168 | static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr) |
1169 | { | |
1170 | u8 value = 0xff; | |
1171 | unsigned int i; | |
1172 | ||
1173 | RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT); | |
1174 | ||
1175 | for (i = 0; i < 300; i++) { | |
1176 | if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) { | |
1177 | value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK; | |
1178 | break; | |
1179 | } | |
1180 | udelay(100); | |
1181 | } | |
1182 | ||
1183 | return value; | |
1184 | } | |
1185 | ||
1da177e4 LT |
1186 | static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr) |
1187 | { | |
1188 | RTL_W16(IntrMask, 0x0000); | |
1189 | ||
1190 | RTL_W16(IntrStatus, 0xffff); | |
1191 | } | |
1192 | ||
4da19633 | 1193 | static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp) |
1da177e4 | 1194 | { |
4da19633 | 1195 | void __iomem *ioaddr = tp->mmio_addr; |
1196 | ||
1da177e4 LT |
1197 | return RTL_R32(TBICSR) & TBIReset; |
1198 | } | |
1199 | ||
4da19633 | 1200 | static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp) |
1da177e4 | 1201 | { |
4da19633 | 1202 | return rtl_readphy(tp, MII_BMCR) & BMCR_RESET; |
1da177e4 LT |
1203 | } |
1204 | ||
1205 | static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr) | |
1206 | { | |
1207 | return RTL_R32(TBICSR) & TBILinkOk; | |
1208 | } | |
1209 | ||
1210 | static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr) | |
1211 | { | |
1212 | return RTL_R8(PHYstatus) & LinkStatus; | |
1213 | } | |
1214 | ||
4da19633 | 1215 | static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp) |
1da177e4 | 1216 | { |
4da19633 | 1217 | void __iomem *ioaddr = tp->mmio_addr; |
1218 | ||
1da177e4 LT |
1219 | RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset); |
1220 | } | |
1221 | ||
4da19633 | 1222 | static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp) |
1da177e4 LT |
1223 | { |
1224 | unsigned int val; | |
1225 | ||
4da19633 | 1226 | val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET; |
1227 | rtl_writephy(tp, MII_BMCR, val & 0xffff); | |
1da177e4 LT |
1228 | } |
1229 | ||
70090424 HW |
1230 | static void rtl_link_chg_patch(struct rtl8169_private *tp) |
1231 | { | |
1232 | void __iomem *ioaddr = tp->mmio_addr; | |
1233 | struct net_device *dev = tp->dev; | |
1234 | ||
1235 | if (!netif_running(dev)) | |
1236 | return; | |
1237 | ||
1238 | if (tp->mac_version == RTL_GIGA_MAC_VER_34) { | |
1239 | if (RTL_R8(PHYstatus) & _1000bpsF) { | |
1240 | rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111, | |
1241 | 0x00000011, ERIAR_EXGMAC); | |
1242 | rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111, | |
1243 | 0x00000005, ERIAR_EXGMAC); | |
1244 | } else if (RTL_R8(PHYstatus) & _100bps) { | |
1245 | rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111, | |
1246 | 0x0000001f, ERIAR_EXGMAC); | |
1247 | rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111, | |
1248 | 0x00000005, ERIAR_EXGMAC); | |
1249 | } else { | |
1250 | rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111, | |
1251 | 0x0000001f, ERIAR_EXGMAC); | |
1252 | rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111, | |
1253 | 0x0000003f, ERIAR_EXGMAC); | |
1254 | } | |
1255 | /* Reset packet filter */ | |
1256 | rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, | |
1257 | ERIAR_EXGMAC); | |
1258 | rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, | |
1259 | ERIAR_EXGMAC); | |
c2218925 HW |
1260 | } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 || |
1261 | tp->mac_version == RTL_GIGA_MAC_VER_36) { | |
1262 | if (RTL_R8(PHYstatus) & _1000bpsF) { | |
1263 | rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111, | |
1264 | 0x00000011, ERIAR_EXGMAC); | |
1265 | rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111, | |
1266 | 0x00000005, ERIAR_EXGMAC); | |
1267 | } else { | |
1268 | rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111, | |
1269 | 0x0000001f, ERIAR_EXGMAC); | |
1270 | rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111, | |
1271 | 0x0000003f, ERIAR_EXGMAC); | |
1272 | } | |
70090424 HW |
1273 | } |
1274 | } | |
1275 | ||
e4fbce74 | 1276 | static void __rtl8169_check_link_status(struct net_device *dev, |
cecb5fd7 FR |
1277 | struct rtl8169_private *tp, |
1278 | void __iomem *ioaddr, bool pm) | |
1da177e4 LT |
1279 | { |
1280 | unsigned long flags; | |
1281 | ||
1282 | spin_lock_irqsave(&tp->lock, flags); | |
1283 | if (tp->link_ok(ioaddr)) { | |
70090424 | 1284 | rtl_link_chg_patch(tp); |
e1759441 | 1285 | /* This is to cancel a scheduled suspend if there's one. */ |
e4fbce74 RW |
1286 | if (pm) |
1287 | pm_request_resume(&tp->pci_dev->dev); | |
1da177e4 | 1288 | netif_carrier_on(dev); |
1519e57f FR |
1289 | if (net_ratelimit()) |
1290 | netif_info(tp, ifup, dev, "link up\n"); | |
b57b7e5a | 1291 | } else { |
1da177e4 | 1292 | netif_carrier_off(dev); |
bf82c189 | 1293 | netif_info(tp, ifdown, dev, "link down\n"); |
e4fbce74 RW |
1294 | if (pm) |
1295 | pm_schedule_suspend(&tp->pci_dev->dev, 100); | |
b57b7e5a | 1296 | } |
1da177e4 LT |
1297 | spin_unlock_irqrestore(&tp->lock, flags); |
1298 | } | |
1299 | ||
e4fbce74 RW |
1300 | static void rtl8169_check_link_status(struct net_device *dev, |
1301 | struct rtl8169_private *tp, | |
1302 | void __iomem *ioaddr) | |
1303 | { | |
1304 | __rtl8169_check_link_status(dev, tp, ioaddr, false); | |
1305 | } | |
1306 | ||
e1759441 RW |
1307 | #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) |
1308 | ||
1309 | static u32 __rtl8169_get_wol(struct rtl8169_private *tp) | |
61a4dcc2 | 1310 | { |
61a4dcc2 FR |
1311 | void __iomem *ioaddr = tp->mmio_addr; |
1312 | u8 options; | |
e1759441 | 1313 | u32 wolopts = 0; |
61a4dcc2 FR |
1314 | |
1315 | options = RTL_R8(Config1); | |
1316 | if (!(options & PMEnable)) | |
e1759441 | 1317 | return 0; |
61a4dcc2 FR |
1318 | |
1319 | options = RTL_R8(Config3); | |
1320 | if (options & LinkUp) | |
e1759441 | 1321 | wolopts |= WAKE_PHY; |
61a4dcc2 | 1322 | if (options & MagicPacket) |
e1759441 | 1323 | wolopts |= WAKE_MAGIC; |
61a4dcc2 FR |
1324 | |
1325 | options = RTL_R8(Config5); | |
1326 | if (options & UWF) | |
e1759441 | 1327 | wolopts |= WAKE_UCAST; |
61a4dcc2 | 1328 | if (options & BWF) |
e1759441 | 1329 | wolopts |= WAKE_BCAST; |
61a4dcc2 | 1330 | if (options & MWF) |
e1759441 | 1331 | wolopts |= WAKE_MCAST; |
61a4dcc2 | 1332 | |
e1759441 | 1333 | return wolopts; |
61a4dcc2 FR |
1334 | } |
1335 | ||
e1759441 | 1336 | static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) |
61a4dcc2 FR |
1337 | { |
1338 | struct rtl8169_private *tp = netdev_priv(dev); | |
e1759441 RW |
1339 | |
1340 | spin_lock_irq(&tp->lock); | |
1341 | ||
1342 | wol->supported = WAKE_ANY; | |
1343 | wol->wolopts = __rtl8169_get_wol(tp); | |
1344 | ||
1345 | spin_unlock_irq(&tp->lock); | |
1346 | } | |
1347 | ||
1348 | static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts) | |
1349 | { | |
61a4dcc2 | 1350 | void __iomem *ioaddr = tp->mmio_addr; |
07d3f51f | 1351 | unsigned int i; |
350f7596 | 1352 | static const struct { |
61a4dcc2 FR |
1353 | u32 opt; |
1354 | u16 reg; | |
1355 | u8 mask; | |
1356 | } cfg[] = { | |
1357 | { WAKE_ANY, Config1, PMEnable }, | |
1358 | { WAKE_PHY, Config3, LinkUp }, | |
1359 | { WAKE_MAGIC, Config3, MagicPacket }, | |
1360 | { WAKE_UCAST, Config5, UWF }, | |
1361 | { WAKE_BCAST, Config5, BWF }, | |
1362 | { WAKE_MCAST, Config5, MWF }, | |
1363 | { WAKE_ANY, Config5, LanWake } | |
1364 | }; | |
1365 | ||
61a4dcc2 FR |
1366 | RTL_W8(Cfg9346, Cfg9346_Unlock); |
1367 | ||
1368 | for (i = 0; i < ARRAY_SIZE(cfg); i++) { | |
1369 | u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask; | |
e1759441 | 1370 | if (wolopts & cfg[i].opt) |
61a4dcc2 FR |
1371 | options |= cfg[i].mask; |
1372 | RTL_W8(cfg[i].reg, options); | |
1373 | } | |
1374 | ||
1375 | RTL_W8(Cfg9346, Cfg9346_Lock); | |
e1759441 RW |
1376 | } |
1377 | ||
1378 | static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
1379 | { | |
1380 | struct rtl8169_private *tp = netdev_priv(dev); | |
1381 | ||
1382 | spin_lock_irq(&tp->lock); | |
61a4dcc2 | 1383 | |
f23e7fda FR |
1384 | if (wol->wolopts) |
1385 | tp->features |= RTL_FEATURE_WOL; | |
1386 | else | |
1387 | tp->features &= ~RTL_FEATURE_WOL; | |
e1759441 | 1388 | __rtl8169_set_wol(tp, wol->wolopts); |
61a4dcc2 FR |
1389 | spin_unlock_irq(&tp->lock); |
1390 | ||
ea80907f | 1391 | device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts); |
1392 | ||
61a4dcc2 FR |
1393 | return 0; |
1394 | } | |
1395 | ||
31bd204f FR |
1396 | static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp) |
1397 | { | |
85bffe6c | 1398 | return rtl_chip_infos[tp->mac_version].fw_name; |
31bd204f FR |
1399 | } |
1400 | ||
1da177e4 LT |
1401 | static void rtl8169_get_drvinfo(struct net_device *dev, |
1402 | struct ethtool_drvinfo *info) | |
1403 | { | |
1404 | struct rtl8169_private *tp = netdev_priv(dev); | |
b6ffd97f | 1405 | struct rtl_fw *rtl_fw = tp->rtl_fw; |
1da177e4 LT |
1406 | |
1407 | strcpy(info->driver, MODULENAME); | |
1408 | strcpy(info->version, RTL8169_VERSION); | |
1409 | strcpy(info->bus_info, pci_name(tp->pci_dev)); | |
1c361efb FR |
1410 | BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version)); |
1411 | strcpy(info->fw_version, IS_ERR_OR_NULL(rtl_fw) ? "N/A" : | |
1412 | rtl_fw->version); | |
1da177e4 LT |
1413 | } |
1414 | ||
1415 | static int rtl8169_get_regs_len(struct net_device *dev) | |
1416 | { | |
1417 | return R8169_REGS_SIZE; | |
1418 | } | |
1419 | ||
1420 | static int rtl8169_set_speed_tbi(struct net_device *dev, | |
54405cde | 1421 | u8 autoneg, u16 speed, u8 duplex, u32 ignored) |
1da177e4 LT |
1422 | { |
1423 | struct rtl8169_private *tp = netdev_priv(dev); | |
1424 | void __iomem *ioaddr = tp->mmio_addr; | |
1425 | int ret = 0; | |
1426 | u32 reg; | |
1427 | ||
1428 | reg = RTL_R32(TBICSR); | |
1429 | if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) && | |
1430 | (duplex == DUPLEX_FULL)) { | |
1431 | RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart)); | |
1432 | } else if (autoneg == AUTONEG_ENABLE) | |
1433 | RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart); | |
1434 | else { | |
bf82c189 JP |
1435 | netif_warn(tp, link, dev, |
1436 | "incorrect speed setting refused in TBI mode\n"); | |
1da177e4 LT |
1437 | ret = -EOPNOTSUPP; |
1438 | } | |
1439 | ||
1440 | return ret; | |
1441 | } | |
1442 | ||
1443 | static int rtl8169_set_speed_xmii(struct net_device *dev, | |
54405cde | 1444 | u8 autoneg, u16 speed, u8 duplex, u32 adv) |
1da177e4 LT |
1445 | { |
1446 | struct rtl8169_private *tp = netdev_priv(dev); | |
3577aa1b | 1447 | int giga_ctrl, bmcr; |
54405cde | 1448 | int rc = -EINVAL; |
1da177e4 | 1449 | |
716b50a3 | 1450 | rtl_writephy(tp, 0x1f, 0x0000); |
1da177e4 LT |
1451 | |
1452 | if (autoneg == AUTONEG_ENABLE) { | |
3577aa1b | 1453 | int auto_nego; |
1454 | ||
4da19633 | 1455 | auto_nego = rtl_readphy(tp, MII_ADVERTISE); |
54405cde ON |
1456 | auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL | |
1457 | ADVERTISE_100HALF | ADVERTISE_100FULL); | |
1458 | ||
1459 | if (adv & ADVERTISED_10baseT_Half) | |
1460 | auto_nego |= ADVERTISE_10HALF; | |
1461 | if (adv & ADVERTISED_10baseT_Full) | |
1462 | auto_nego |= ADVERTISE_10FULL; | |
1463 | if (adv & ADVERTISED_100baseT_Half) | |
1464 | auto_nego |= ADVERTISE_100HALF; | |
1465 | if (adv & ADVERTISED_100baseT_Full) | |
1466 | auto_nego |= ADVERTISE_100FULL; | |
1467 | ||
3577aa1b | 1468 | auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; |
1da177e4 | 1469 | |
4da19633 | 1470 | giga_ctrl = rtl_readphy(tp, MII_CTRL1000); |
3577aa1b | 1471 | giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF); |
bcf0bf90 | 1472 | |
3577aa1b | 1473 | /* The 8100e/8101e/8102e do Fast Ethernet only. */ |
826e6cbd | 1474 | if (tp->mii.supports_gmii) { |
54405cde ON |
1475 | if (adv & ADVERTISED_1000baseT_Half) |
1476 | giga_ctrl |= ADVERTISE_1000HALF; | |
1477 | if (adv & ADVERTISED_1000baseT_Full) | |
1478 | giga_ctrl |= ADVERTISE_1000FULL; | |
1479 | } else if (adv & (ADVERTISED_1000baseT_Half | | |
1480 | ADVERTISED_1000baseT_Full)) { | |
bf82c189 JP |
1481 | netif_info(tp, link, dev, |
1482 | "PHY does not support 1000Mbps\n"); | |
54405cde | 1483 | goto out; |
bcf0bf90 | 1484 | } |
1da177e4 | 1485 | |
3577aa1b | 1486 | bmcr = BMCR_ANENABLE | BMCR_ANRESTART; |
1487 | ||
4da19633 | 1488 | rtl_writephy(tp, MII_ADVERTISE, auto_nego); |
1489 | rtl_writephy(tp, MII_CTRL1000, giga_ctrl); | |
3577aa1b | 1490 | } else { |
1491 | giga_ctrl = 0; | |
1492 | ||
1493 | if (speed == SPEED_10) | |
1494 | bmcr = 0; | |
1495 | else if (speed == SPEED_100) | |
1496 | bmcr = BMCR_SPEED100; | |
1497 | else | |
54405cde | 1498 | goto out; |
3577aa1b | 1499 | |
1500 | if (duplex == DUPLEX_FULL) | |
1501 | bmcr |= BMCR_FULLDPLX; | |
2584fbc3 RS |
1502 | } |
1503 | ||
4da19633 | 1504 | rtl_writephy(tp, MII_BMCR, bmcr); |
3577aa1b | 1505 | |
cecb5fd7 FR |
1506 | if (tp->mac_version == RTL_GIGA_MAC_VER_02 || |
1507 | tp->mac_version == RTL_GIGA_MAC_VER_03) { | |
3577aa1b | 1508 | if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) { |
4da19633 | 1509 | rtl_writephy(tp, 0x17, 0x2138); |
1510 | rtl_writephy(tp, 0x0e, 0x0260); | |
3577aa1b | 1511 | } else { |
4da19633 | 1512 | rtl_writephy(tp, 0x17, 0x2108); |
1513 | rtl_writephy(tp, 0x0e, 0x0000); | |
3577aa1b | 1514 | } |
1515 | } | |
1516 | ||
54405cde ON |
1517 | rc = 0; |
1518 | out: | |
1519 | return rc; | |
1da177e4 LT |
1520 | } |
1521 | ||
1522 | static int rtl8169_set_speed(struct net_device *dev, | |
54405cde | 1523 | u8 autoneg, u16 speed, u8 duplex, u32 advertising) |
1da177e4 LT |
1524 | { |
1525 | struct rtl8169_private *tp = netdev_priv(dev); | |
1526 | int ret; | |
1527 | ||
54405cde | 1528 | ret = tp->set_speed(dev, autoneg, speed, duplex, advertising); |
4876cc1e FR |
1529 | if (ret < 0) |
1530 | goto out; | |
1da177e4 | 1531 | |
4876cc1e FR |
1532 | if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) && |
1533 | (advertising & ADVERTISED_1000baseT_Full)) { | |
1da177e4 | 1534 | mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT); |
4876cc1e FR |
1535 | } |
1536 | out: | |
1da177e4 LT |
1537 | return ret; |
1538 | } | |
1539 | ||
1540 | static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
1541 | { | |
1542 | struct rtl8169_private *tp = netdev_priv(dev); | |
1543 | unsigned long flags; | |
1544 | int ret; | |
1545 | ||
4876cc1e FR |
1546 | del_timer_sync(&tp->timer); |
1547 | ||
1da177e4 | 1548 | spin_lock_irqsave(&tp->lock, flags); |
cecb5fd7 | 1549 | ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd), |
25db0338 | 1550 | cmd->duplex, cmd->advertising); |
1da177e4 | 1551 | spin_unlock_irqrestore(&tp->lock, flags); |
5b0384f4 | 1552 | |
1da177e4 LT |
1553 | return ret; |
1554 | } | |
1555 | ||
350fb32a | 1556 | static u32 rtl8169_fix_features(struct net_device *dev, u32 features) |
1da177e4 | 1557 | { |
d58d46b5 FR |
1558 | struct rtl8169_private *tp = netdev_priv(dev); |
1559 | ||
2b7b4318 | 1560 | if (dev->mtu > TD_MSS_MAX) |
350fb32a | 1561 | features &= ~NETIF_F_ALL_TSO; |
1da177e4 | 1562 | |
d58d46b5 FR |
1563 | if (dev->mtu > JUMBO_1K && |
1564 | !rtl_chip_infos[tp->mac_version].jumbo_tx_csum) | |
1565 | features &= ~NETIF_F_IP_CSUM; | |
1566 | ||
350fb32a | 1567 | return features; |
1da177e4 LT |
1568 | } |
1569 | ||
350fb32a | 1570 | static int rtl8169_set_features(struct net_device *dev, u32 features) |
1da177e4 LT |
1571 | { |
1572 | struct rtl8169_private *tp = netdev_priv(dev); | |
1573 | void __iomem *ioaddr = tp->mmio_addr; | |
1574 | unsigned long flags; | |
1575 | ||
1576 | spin_lock_irqsave(&tp->lock, flags); | |
1577 | ||
350fb32a | 1578 | if (features & NETIF_F_RXCSUM) |
1da177e4 LT |
1579 | tp->cp_cmd |= RxChkSum; |
1580 | else | |
1581 | tp->cp_cmd &= ~RxChkSum; | |
1582 | ||
350fb32a MM |
1583 | if (dev->features & NETIF_F_HW_VLAN_RX) |
1584 | tp->cp_cmd |= RxVlan; | |
1585 | else | |
1586 | tp->cp_cmd &= ~RxVlan; | |
1587 | ||
1da177e4 LT |
1588 | RTL_W16(CPlusCmd, tp->cp_cmd); |
1589 | RTL_R16(CPlusCmd); | |
1590 | ||
1591 | spin_unlock_irqrestore(&tp->lock, flags); | |
1592 | ||
1593 | return 0; | |
1594 | } | |
1595 | ||
1da177e4 LT |
1596 | static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp, |
1597 | struct sk_buff *skb) | |
1598 | { | |
eab6d18d | 1599 | return (vlan_tx_tag_present(skb)) ? |
1da177e4 LT |
1600 | TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00; |
1601 | } | |
1602 | ||
7a8fc77b | 1603 | static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb) |
1da177e4 LT |
1604 | { |
1605 | u32 opts2 = le32_to_cpu(desc->opts2); | |
1da177e4 | 1606 | |
7a8fc77b FR |
1607 | if (opts2 & RxVlanTag) |
1608 | __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff)); | |
2edae08e | 1609 | |
1da177e4 | 1610 | desc->opts2 = 0; |
1da177e4 LT |
1611 | } |
1612 | ||
ccdffb9a | 1613 | static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd) |
1da177e4 LT |
1614 | { |
1615 | struct rtl8169_private *tp = netdev_priv(dev); | |
1616 | void __iomem *ioaddr = tp->mmio_addr; | |
1617 | u32 status; | |
1618 | ||
1619 | cmd->supported = | |
1620 | SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE; | |
1621 | cmd->port = PORT_FIBRE; | |
1622 | cmd->transceiver = XCVR_INTERNAL; | |
1623 | ||
1624 | status = RTL_R32(TBICSR); | |
1625 | cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0; | |
1626 | cmd->autoneg = !!(status & TBINwEnable); | |
1627 | ||
70739497 | 1628 | ethtool_cmd_speed_set(cmd, SPEED_1000); |
1da177e4 | 1629 | cmd->duplex = DUPLEX_FULL; /* Always set */ |
ccdffb9a FR |
1630 | |
1631 | return 0; | |
1da177e4 LT |
1632 | } |
1633 | ||
ccdffb9a | 1634 | static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd) |
1da177e4 LT |
1635 | { |
1636 | struct rtl8169_private *tp = netdev_priv(dev); | |
ccdffb9a FR |
1637 | |
1638 | return mii_ethtool_gset(&tp->mii, cmd); | |
1da177e4 LT |
1639 | } |
1640 | ||
1641 | static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
1642 | { | |
1643 | struct rtl8169_private *tp = netdev_priv(dev); | |
1644 | unsigned long flags; | |
ccdffb9a | 1645 | int rc; |
1da177e4 LT |
1646 | |
1647 | spin_lock_irqsave(&tp->lock, flags); | |
1648 | ||
ccdffb9a | 1649 | rc = tp->get_settings(dev, cmd); |
1da177e4 LT |
1650 | |
1651 | spin_unlock_irqrestore(&tp->lock, flags); | |
ccdffb9a | 1652 | return rc; |
1da177e4 LT |
1653 | } |
1654 | ||
1655 | static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs, | |
1656 | void *p) | |
1657 | { | |
5b0384f4 FR |
1658 | struct rtl8169_private *tp = netdev_priv(dev); |
1659 | unsigned long flags; | |
1da177e4 | 1660 | |
5b0384f4 FR |
1661 | if (regs->len > R8169_REGS_SIZE) |
1662 | regs->len = R8169_REGS_SIZE; | |
1da177e4 | 1663 | |
5b0384f4 FR |
1664 | spin_lock_irqsave(&tp->lock, flags); |
1665 | memcpy_fromio(p, tp->mmio_addr, regs->len); | |
1666 | spin_unlock_irqrestore(&tp->lock, flags); | |
1da177e4 LT |
1667 | } |
1668 | ||
b57b7e5a SH |
1669 | static u32 rtl8169_get_msglevel(struct net_device *dev) |
1670 | { | |
1671 | struct rtl8169_private *tp = netdev_priv(dev); | |
1672 | ||
1673 | return tp->msg_enable; | |
1674 | } | |
1675 | ||
1676 | static void rtl8169_set_msglevel(struct net_device *dev, u32 value) | |
1677 | { | |
1678 | struct rtl8169_private *tp = netdev_priv(dev); | |
1679 | ||
1680 | tp->msg_enable = value; | |
1681 | } | |
1682 | ||
d4a3a0fc SH |
1683 | static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = { |
1684 | "tx_packets", | |
1685 | "rx_packets", | |
1686 | "tx_errors", | |
1687 | "rx_errors", | |
1688 | "rx_missed", | |
1689 | "align_errors", | |
1690 | "tx_single_collisions", | |
1691 | "tx_multi_collisions", | |
1692 | "unicast", | |
1693 | "broadcast", | |
1694 | "multicast", | |
1695 | "tx_aborted", | |
1696 | "tx_underrun", | |
1697 | }; | |
1698 | ||
b9f2c044 | 1699 | static int rtl8169_get_sset_count(struct net_device *dev, int sset) |
d4a3a0fc | 1700 | { |
b9f2c044 JG |
1701 | switch (sset) { |
1702 | case ETH_SS_STATS: | |
1703 | return ARRAY_SIZE(rtl8169_gstrings); | |
1704 | default: | |
1705 | return -EOPNOTSUPP; | |
1706 | } | |
d4a3a0fc SH |
1707 | } |
1708 | ||
355423d0 | 1709 | static void rtl8169_update_counters(struct net_device *dev) |
d4a3a0fc SH |
1710 | { |
1711 | struct rtl8169_private *tp = netdev_priv(dev); | |
1712 | void __iomem *ioaddr = tp->mmio_addr; | |
cecb5fd7 | 1713 | struct device *d = &tp->pci_dev->dev; |
d4a3a0fc SH |
1714 | struct rtl8169_counters *counters; |
1715 | dma_addr_t paddr; | |
1716 | u32 cmd; | |
355423d0 | 1717 | int wait = 1000; |
d4a3a0fc | 1718 | |
355423d0 IV |
1719 | /* |
1720 | * Some chips are unable to dump tally counters when the receiver | |
1721 | * is disabled. | |
1722 | */ | |
1723 | if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0) | |
1724 | return; | |
d4a3a0fc | 1725 | |
48addcc9 | 1726 | counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL); |
d4a3a0fc SH |
1727 | if (!counters) |
1728 | return; | |
1729 | ||
1730 | RTL_W32(CounterAddrHigh, (u64)paddr >> 32); | |
284901a9 | 1731 | cmd = (u64)paddr & DMA_BIT_MASK(32); |
d4a3a0fc SH |
1732 | RTL_W32(CounterAddrLow, cmd); |
1733 | RTL_W32(CounterAddrLow, cmd | CounterDump); | |
1734 | ||
355423d0 IV |
1735 | while (wait--) { |
1736 | if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) { | |
355423d0 | 1737 | memcpy(&tp->counters, counters, sizeof(*counters)); |
d4a3a0fc | 1738 | break; |
355423d0 IV |
1739 | } |
1740 | udelay(10); | |
d4a3a0fc SH |
1741 | } |
1742 | ||
1743 | RTL_W32(CounterAddrLow, 0); | |
1744 | RTL_W32(CounterAddrHigh, 0); | |
1745 | ||
48addcc9 | 1746 | dma_free_coherent(d, sizeof(*counters), counters, paddr); |
d4a3a0fc SH |
1747 | } |
1748 | ||
355423d0 IV |
1749 | static void rtl8169_get_ethtool_stats(struct net_device *dev, |
1750 | struct ethtool_stats *stats, u64 *data) | |
1751 | { | |
1752 | struct rtl8169_private *tp = netdev_priv(dev); | |
1753 | ||
1754 | ASSERT_RTNL(); | |
1755 | ||
1756 | rtl8169_update_counters(dev); | |
1757 | ||
1758 | data[0] = le64_to_cpu(tp->counters.tx_packets); | |
1759 | data[1] = le64_to_cpu(tp->counters.rx_packets); | |
1760 | data[2] = le64_to_cpu(tp->counters.tx_errors); | |
1761 | data[3] = le32_to_cpu(tp->counters.rx_errors); | |
1762 | data[4] = le16_to_cpu(tp->counters.rx_missed); | |
1763 | data[5] = le16_to_cpu(tp->counters.align_errors); | |
1764 | data[6] = le32_to_cpu(tp->counters.tx_one_collision); | |
1765 | data[7] = le32_to_cpu(tp->counters.tx_multi_collision); | |
1766 | data[8] = le64_to_cpu(tp->counters.rx_unicast); | |
1767 | data[9] = le64_to_cpu(tp->counters.rx_broadcast); | |
1768 | data[10] = le32_to_cpu(tp->counters.rx_multicast); | |
1769 | data[11] = le16_to_cpu(tp->counters.tx_aborted); | |
1770 | data[12] = le16_to_cpu(tp->counters.tx_underun); | |
1771 | } | |
1772 | ||
d4a3a0fc SH |
1773 | static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data) |
1774 | { | |
1775 | switch(stringset) { | |
1776 | case ETH_SS_STATS: | |
1777 | memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings)); | |
1778 | break; | |
1779 | } | |
1780 | } | |
1781 | ||
7282d491 | 1782 | static const struct ethtool_ops rtl8169_ethtool_ops = { |
1da177e4 LT |
1783 | .get_drvinfo = rtl8169_get_drvinfo, |
1784 | .get_regs_len = rtl8169_get_regs_len, | |
1785 | .get_link = ethtool_op_get_link, | |
1786 | .get_settings = rtl8169_get_settings, | |
1787 | .set_settings = rtl8169_set_settings, | |
b57b7e5a SH |
1788 | .get_msglevel = rtl8169_get_msglevel, |
1789 | .set_msglevel = rtl8169_set_msglevel, | |
1da177e4 | 1790 | .get_regs = rtl8169_get_regs, |
61a4dcc2 FR |
1791 | .get_wol = rtl8169_get_wol, |
1792 | .set_wol = rtl8169_set_wol, | |
d4a3a0fc | 1793 | .get_strings = rtl8169_get_strings, |
b9f2c044 | 1794 | .get_sset_count = rtl8169_get_sset_count, |
d4a3a0fc | 1795 | .get_ethtool_stats = rtl8169_get_ethtool_stats, |
1da177e4 LT |
1796 | }; |
1797 | ||
07d3f51f | 1798 | static void rtl8169_get_mac_version(struct rtl8169_private *tp, |
5d320a20 | 1799 | struct net_device *dev, u8 default_version) |
1da177e4 | 1800 | { |
5d320a20 | 1801 | void __iomem *ioaddr = tp->mmio_addr; |
0e485150 FR |
1802 | /* |
1803 | * The driver currently handles the 8168Bf and the 8168Be identically | |
1804 | * but they can be identified more specifically through the test below | |
1805 | * if needed: | |
1806 | * | |
1807 | * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be | |
0127215c FR |
1808 | * |
1809 | * Same thing for the 8101Eb and the 8101Ec: | |
1810 | * | |
1811 | * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec | |
0e485150 | 1812 | */ |
3744100e | 1813 | static const struct rtl_mac_info { |
1da177e4 | 1814 | u32 mask; |
e3cf0cc0 | 1815 | u32 val; |
1da177e4 LT |
1816 | int mac_version; |
1817 | } mac_info[] = { | |
c2218925 HW |
1818 | /* 8168F family. */ |
1819 | { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36 }, | |
1820 | { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35 }, | |
1821 | ||
01dc7fec | 1822 | /* 8168E family. */ |
70090424 | 1823 | { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 }, |
01dc7fec | 1824 | { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 }, |
1825 | { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 }, | |
1826 | { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 }, | |
1827 | ||
5b538df9 | 1828 | /* 8168D family. */ |
daf9df6d | 1829 | { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 }, |
1830 | { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 }, | |
daf9df6d | 1831 | { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 }, |
5b538df9 | 1832 | |
e6de30d6 | 1833 | /* 8168DP family. */ |
1834 | { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 }, | |
1835 | { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 }, | |
4804b3b3 | 1836 | { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 }, |
e6de30d6 | 1837 | |
ef808d50 | 1838 | /* 8168C family. */ |
17c99297 | 1839 | { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 }, |
ef3386f0 | 1840 | { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 }, |
ef808d50 | 1841 | { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 }, |
7f3e3d3a | 1842 | { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 }, |
e3cf0cc0 FR |
1843 | { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 }, |
1844 | { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 }, | |
197ff761 | 1845 | { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 }, |
6fb07058 | 1846 | { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 }, |
ef808d50 | 1847 | { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 }, |
e3cf0cc0 FR |
1848 | |
1849 | /* 8168B family. */ | |
1850 | { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 }, | |
1851 | { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 }, | |
1852 | { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 }, | |
1853 | { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 }, | |
1854 | ||
1855 | /* 8101 family. */ | |
36a0e6c2 | 1856 | { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 }, |
5a5e4443 HW |
1857 | { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 }, |
1858 | { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 }, | |
1859 | { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 }, | |
2857ffb7 FR |
1860 | { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 }, |
1861 | { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 }, | |
1862 | { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 }, | |
1863 | { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 }, | |
1864 | { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 }, | |
1865 | { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 }, | |
e3cf0cc0 | 1866 | { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 }, |
2857ffb7 | 1867 | { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 }, |
e3cf0cc0 | 1868 | { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 }, |
2857ffb7 FR |
1869 | { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 }, |
1870 | { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 }, | |
e3cf0cc0 FR |
1871 | { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 }, |
1872 | /* FIXME: where did these entries come from ? -- FR */ | |
1873 | { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 }, | |
1874 | { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 }, | |
1875 | ||
1876 | /* 8110 family. */ | |
1877 | { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 }, | |
1878 | { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 }, | |
1879 | { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 }, | |
1880 | { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 }, | |
1881 | { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 }, | |
1882 | { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 }, | |
1883 | ||
f21b75e9 JD |
1884 | /* Catch-all */ |
1885 | { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE } | |
3744100e FR |
1886 | }; |
1887 | const struct rtl_mac_info *p = mac_info; | |
1da177e4 LT |
1888 | u32 reg; |
1889 | ||
e3cf0cc0 FR |
1890 | reg = RTL_R32(TxConfig); |
1891 | while ((reg & p->mask) != p->val) | |
1da177e4 LT |
1892 | p++; |
1893 | tp->mac_version = p->mac_version; | |
5d320a20 FR |
1894 | |
1895 | if (tp->mac_version == RTL_GIGA_MAC_NONE) { | |
1896 | netif_notice(tp, probe, dev, | |
1897 | "unknown MAC, using family default\n"); | |
1898 | tp->mac_version = default_version; | |
1899 | } | |
1da177e4 LT |
1900 | } |
1901 | ||
1902 | static void rtl8169_print_mac_version(struct rtl8169_private *tp) | |
1903 | { | |
bcf0bf90 | 1904 | dprintk("mac_version = 0x%02x\n", tp->mac_version); |
1da177e4 LT |
1905 | } |
1906 | ||
867763c1 FR |
1907 | struct phy_reg { |
1908 | u16 reg; | |
1909 | u16 val; | |
1910 | }; | |
1911 | ||
4da19633 | 1912 | static void rtl_writephy_batch(struct rtl8169_private *tp, |
1913 | const struct phy_reg *regs, int len) | |
867763c1 FR |
1914 | { |
1915 | while (len-- > 0) { | |
4da19633 | 1916 | rtl_writephy(tp, regs->reg, regs->val); |
867763c1 FR |
1917 | regs++; |
1918 | } | |
1919 | } | |
1920 | ||
bca03d5f | 1921 | #define PHY_READ 0x00000000 |
1922 | #define PHY_DATA_OR 0x10000000 | |
1923 | #define PHY_DATA_AND 0x20000000 | |
1924 | #define PHY_BJMPN 0x30000000 | |
1925 | #define PHY_READ_EFUSE 0x40000000 | |
1926 | #define PHY_READ_MAC_BYTE 0x50000000 | |
1927 | #define PHY_WRITE_MAC_BYTE 0x60000000 | |
1928 | #define PHY_CLEAR_READCOUNT 0x70000000 | |
1929 | #define PHY_WRITE 0x80000000 | |
1930 | #define PHY_READCOUNT_EQ_SKIP 0x90000000 | |
1931 | #define PHY_COMP_EQ_SKIPN 0xa0000000 | |
1932 | #define PHY_COMP_NEQ_SKIPN 0xb0000000 | |
1933 | #define PHY_WRITE_PREVIOUS 0xc0000000 | |
1934 | #define PHY_SKIPN 0xd0000000 | |
1935 | #define PHY_DELAY_MS 0xe0000000 | |
1936 | #define PHY_WRITE_ERI_WORD 0xf0000000 | |
1937 | ||
960aee6c HW |
1938 | struct fw_info { |
1939 | u32 magic; | |
1940 | char version[RTL_VER_SIZE]; | |
1941 | __le32 fw_start; | |
1942 | __le32 fw_len; | |
1943 | u8 chksum; | |
1944 | } __packed; | |
1945 | ||
1c361efb FR |
1946 | #define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code)) |
1947 | ||
1948 | static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw) | |
bca03d5f | 1949 | { |
b6ffd97f | 1950 | const struct firmware *fw = rtl_fw->fw; |
960aee6c | 1951 | struct fw_info *fw_info = (struct fw_info *)fw->data; |
1c361efb FR |
1952 | struct rtl_fw_phy_action *pa = &rtl_fw->phy_action; |
1953 | char *version = rtl_fw->version; | |
1954 | bool rc = false; | |
1955 | ||
1956 | if (fw->size < FW_OPCODE_SIZE) | |
1957 | goto out; | |
960aee6c HW |
1958 | |
1959 | if (!fw_info->magic) { | |
1960 | size_t i, size, start; | |
1961 | u8 checksum = 0; | |
1962 | ||
1963 | if (fw->size < sizeof(*fw_info)) | |
1964 | goto out; | |
1965 | ||
1966 | for (i = 0; i < fw->size; i++) | |
1967 | checksum += fw->data[i]; | |
1968 | if (checksum != 0) | |
1969 | goto out; | |
1970 | ||
1971 | start = le32_to_cpu(fw_info->fw_start); | |
1972 | if (start > fw->size) | |
1973 | goto out; | |
1974 | ||
1975 | size = le32_to_cpu(fw_info->fw_len); | |
1976 | if (size > (fw->size - start) / FW_OPCODE_SIZE) | |
1977 | goto out; | |
1978 | ||
1979 | memcpy(version, fw_info->version, RTL_VER_SIZE); | |
1980 | ||
1981 | pa->code = (__le32 *)(fw->data + start); | |
1982 | pa->size = size; | |
1983 | } else { | |
1c361efb FR |
1984 | if (fw->size % FW_OPCODE_SIZE) |
1985 | goto out; | |
1986 | ||
1987 | strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE); | |
1988 | ||
1989 | pa->code = (__le32 *)fw->data; | |
1990 | pa->size = fw->size / FW_OPCODE_SIZE; | |
1991 | } | |
1992 | version[RTL_VER_SIZE - 1] = 0; | |
1993 | ||
1994 | rc = true; | |
1995 | out: | |
1996 | return rc; | |
1997 | } | |
1998 | ||
fd112f2e FR |
1999 | static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev, |
2000 | struct rtl_fw_phy_action *pa) | |
1c361efb | 2001 | { |
fd112f2e | 2002 | bool rc = false; |
1c361efb | 2003 | size_t index; |
bca03d5f | 2004 | |
1c361efb FR |
2005 | for (index = 0; index < pa->size; index++) { |
2006 | u32 action = le32_to_cpu(pa->code[index]); | |
42b82dc1 | 2007 | u32 regno = (action & 0x0fff0000) >> 16; |
bca03d5f | 2008 | |
42b82dc1 | 2009 | switch(action & 0xf0000000) { |
2010 | case PHY_READ: | |
2011 | case PHY_DATA_OR: | |
2012 | case PHY_DATA_AND: | |
2013 | case PHY_READ_EFUSE: | |
2014 | case PHY_CLEAR_READCOUNT: | |
2015 | case PHY_WRITE: | |
2016 | case PHY_WRITE_PREVIOUS: | |
2017 | case PHY_DELAY_MS: | |
2018 | break; | |
2019 | ||
2020 | case PHY_BJMPN: | |
2021 | if (regno > index) { | |
fd112f2e | 2022 | netif_err(tp, ifup, tp->dev, |
cecb5fd7 | 2023 | "Out of range of firmware\n"); |
fd112f2e | 2024 | goto out; |
42b82dc1 | 2025 | } |
2026 | break; | |
2027 | case PHY_READCOUNT_EQ_SKIP: | |
1c361efb | 2028 | if (index + 2 >= pa->size) { |
fd112f2e | 2029 | netif_err(tp, ifup, tp->dev, |
cecb5fd7 | 2030 | "Out of range of firmware\n"); |
fd112f2e | 2031 | goto out; |
42b82dc1 | 2032 | } |
2033 | break; | |
2034 | case PHY_COMP_EQ_SKIPN: | |
2035 | case PHY_COMP_NEQ_SKIPN: | |
2036 | case PHY_SKIPN: | |
1c361efb | 2037 | if (index + 1 + regno >= pa->size) { |
fd112f2e | 2038 | netif_err(tp, ifup, tp->dev, |
cecb5fd7 | 2039 | "Out of range of firmware\n"); |
fd112f2e | 2040 | goto out; |
42b82dc1 | 2041 | } |
bca03d5f | 2042 | break; |
2043 | ||
42b82dc1 | 2044 | case PHY_READ_MAC_BYTE: |
2045 | case PHY_WRITE_MAC_BYTE: | |
2046 | case PHY_WRITE_ERI_WORD: | |
2047 | default: | |
fd112f2e | 2048 | netif_err(tp, ifup, tp->dev, |
42b82dc1 | 2049 | "Invalid action 0x%08x\n", action); |
fd112f2e | 2050 | goto out; |
bca03d5f | 2051 | } |
2052 | } | |
fd112f2e FR |
2053 | rc = true; |
2054 | out: | |
2055 | return rc; | |
2056 | } | |
bca03d5f | 2057 | |
fd112f2e FR |
2058 | static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw) |
2059 | { | |
2060 | struct net_device *dev = tp->dev; | |
2061 | int rc = -EINVAL; | |
2062 | ||
2063 | if (!rtl_fw_format_ok(tp, rtl_fw)) { | |
2064 | netif_err(tp, ifup, dev, "invalid firwmare\n"); | |
2065 | goto out; | |
2066 | } | |
2067 | ||
2068 | if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action)) | |
2069 | rc = 0; | |
2070 | out: | |
2071 | return rc; | |
2072 | } | |
2073 | ||
2074 | static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw) | |
2075 | { | |
2076 | struct rtl_fw_phy_action *pa = &rtl_fw->phy_action; | |
2077 | u32 predata, count; | |
2078 | size_t index; | |
2079 | ||
2080 | predata = count = 0; | |
42b82dc1 | 2081 | |
1c361efb FR |
2082 | for (index = 0; index < pa->size; ) { |
2083 | u32 action = le32_to_cpu(pa->code[index]); | |
bca03d5f | 2084 | u32 data = action & 0x0000ffff; |
42b82dc1 | 2085 | u32 regno = (action & 0x0fff0000) >> 16; |
2086 | ||
2087 | if (!action) | |
2088 | break; | |
bca03d5f | 2089 | |
2090 | switch(action & 0xf0000000) { | |
42b82dc1 | 2091 | case PHY_READ: |
2092 | predata = rtl_readphy(tp, regno); | |
2093 | count++; | |
2094 | index++; | |
2095 | break; | |
2096 | case PHY_DATA_OR: | |
2097 | predata |= data; | |
2098 | index++; | |
2099 | break; | |
2100 | case PHY_DATA_AND: | |
2101 | predata &= data; | |
2102 | index++; | |
2103 | break; | |
2104 | case PHY_BJMPN: | |
2105 | index -= regno; | |
2106 | break; | |
2107 | case PHY_READ_EFUSE: | |
2108 | predata = rtl8168d_efuse_read(tp->mmio_addr, regno); | |
2109 | index++; | |
2110 | break; | |
2111 | case PHY_CLEAR_READCOUNT: | |
2112 | count = 0; | |
2113 | index++; | |
2114 | break; | |
bca03d5f | 2115 | case PHY_WRITE: |
42b82dc1 | 2116 | rtl_writephy(tp, regno, data); |
2117 | index++; | |
2118 | break; | |
2119 | case PHY_READCOUNT_EQ_SKIP: | |
cecb5fd7 | 2120 | index += (count == data) ? 2 : 1; |
bca03d5f | 2121 | break; |
42b82dc1 | 2122 | case PHY_COMP_EQ_SKIPN: |
2123 | if (predata == data) | |
2124 | index += regno; | |
2125 | index++; | |
2126 | break; | |
2127 | case PHY_COMP_NEQ_SKIPN: | |
2128 | if (predata != data) | |
2129 | index += regno; | |
2130 | index++; | |
2131 | break; | |
2132 | case PHY_WRITE_PREVIOUS: | |
2133 | rtl_writephy(tp, regno, predata); | |
2134 | index++; | |
2135 | break; | |
2136 | case PHY_SKIPN: | |
2137 | index += regno + 1; | |
2138 | break; | |
2139 | case PHY_DELAY_MS: | |
2140 | mdelay(data); | |
2141 | index++; | |
2142 | break; | |
2143 | ||
2144 | case PHY_READ_MAC_BYTE: | |
2145 | case PHY_WRITE_MAC_BYTE: | |
2146 | case PHY_WRITE_ERI_WORD: | |
bca03d5f | 2147 | default: |
2148 | BUG(); | |
2149 | } | |
2150 | } | |
2151 | } | |
2152 | ||
f1e02ed1 | 2153 | static void rtl_release_firmware(struct rtl8169_private *tp) |
2154 | { | |
b6ffd97f FR |
2155 | if (!IS_ERR_OR_NULL(tp->rtl_fw)) { |
2156 | release_firmware(tp->rtl_fw->fw); | |
2157 | kfree(tp->rtl_fw); | |
2158 | } | |
2159 | tp->rtl_fw = RTL_FIRMWARE_UNKNOWN; | |
f1e02ed1 | 2160 | } |
2161 | ||
953a12cc | 2162 | static void rtl_apply_firmware(struct rtl8169_private *tp) |
f1e02ed1 | 2163 | { |
b6ffd97f | 2164 | struct rtl_fw *rtl_fw = tp->rtl_fw; |
f1e02ed1 | 2165 | |
2166 | /* TODO: release firmware once rtl_phy_write_fw signals failures. */ | |
b6ffd97f FR |
2167 | if (!IS_ERR_OR_NULL(rtl_fw)) |
2168 | rtl_phy_write_fw(tp, rtl_fw); | |
953a12cc FR |
2169 | } |
2170 | ||
2171 | static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val) | |
2172 | { | |
2173 | if (rtl_readphy(tp, reg) != val) | |
2174 | netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n"); | |
2175 | else | |
2176 | rtl_apply_firmware(tp); | |
f1e02ed1 | 2177 | } |
2178 | ||
4da19633 | 2179 | static void rtl8169s_hw_phy_config(struct rtl8169_private *tp) |
1da177e4 | 2180 | { |
350f7596 | 2181 | static const struct phy_reg phy_reg_init[] = { |
0b9b571d | 2182 | { 0x1f, 0x0001 }, |
2183 | { 0x06, 0x006e }, | |
2184 | { 0x08, 0x0708 }, | |
2185 | { 0x15, 0x4000 }, | |
2186 | { 0x18, 0x65c7 }, | |
1da177e4 | 2187 | |
0b9b571d | 2188 | { 0x1f, 0x0001 }, |
2189 | { 0x03, 0x00a1 }, | |
2190 | { 0x02, 0x0008 }, | |
2191 | { 0x01, 0x0120 }, | |
2192 | { 0x00, 0x1000 }, | |
2193 | { 0x04, 0x0800 }, | |
2194 | { 0x04, 0x0000 }, | |
1da177e4 | 2195 | |
0b9b571d | 2196 | { 0x03, 0xff41 }, |
2197 | { 0x02, 0xdf60 }, | |
2198 | { 0x01, 0x0140 }, | |
2199 | { 0x00, 0x0077 }, | |
2200 | { 0x04, 0x7800 }, | |
2201 | { 0x04, 0x7000 }, | |
2202 | ||
2203 | { 0x03, 0x802f }, | |
2204 | { 0x02, 0x4f02 }, | |
2205 | { 0x01, 0x0409 }, | |
2206 | { 0x00, 0xf0f9 }, | |
2207 | { 0x04, 0x9800 }, | |
2208 | { 0x04, 0x9000 }, | |
2209 | ||
2210 | { 0x03, 0xdf01 }, | |
2211 | { 0x02, 0xdf20 }, | |
2212 | { 0x01, 0xff95 }, | |
2213 | { 0x00, 0xba00 }, | |
2214 | { 0x04, 0xa800 }, | |
2215 | { 0x04, 0xa000 }, | |
2216 | ||
2217 | { 0x03, 0xff41 }, | |
2218 | { 0x02, 0xdf20 }, | |
2219 | { 0x01, 0x0140 }, | |
2220 | { 0x00, 0x00bb }, | |
2221 | { 0x04, 0xb800 }, | |
2222 | { 0x04, 0xb000 }, | |
2223 | ||
2224 | { 0x03, 0xdf41 }, | |
2225 | { 0x02, 0xdc60 }, | |
2226 | { 0x01, 0x6340 }, | |
2227 | { 0x00, 0x007d }, | |
2228 | { 0x04, 0xd800 }, | |
2229 | { 0x04, 0xd000 }, | |
2230 | ||
2231 | { 0x03, 0xdf01 }, | |
2232 | { 0x02, 0xdf20 }, | |
2233 | { 0x01, 0x100a }, | |
2234 | { 0x00, 0xa0ff }, | |
2235 | { 0x04, 0xf800 }, | |
2236 | { 0x04, 0xf000 }, | |
2237 | ||
2238 | { 0x1f, 0x0000 }, | |
2239 | { 0x0b, 0x0000 }, | |
2240 | { 0x00, 0x9200 } | |
2241 | }; | |
1da177e4 | 2242 | |
4da19633 | 2243 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
1da177e4 LT |
2244 | } |
2245 | ||
4da19633 | 2246 | static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp) |
5615d9f1 | 2247 | { |
350f7596 | 2248 | static const struct phy_reg phy_reg_init[] = { |
a441d7b6 FR |
2249 | { 0x1f, 0x0002 }, |
2250 | { 0x01, 0x90d0 }, | |
2251 | { 0x1f, 0x0000 } | |
2252 | }; | |
2253 | ||
4da19633 | 2254 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
5615d9f1 FR |
2255 | } |
2256 | ||
4da19633 | 2257 | static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp) |
2e955856 | 2258 | { |
2259 | struct pci_dev *pdev = tp->pci_dev; | |
2e955856 | 2260 | |
ccbae55e SS |
2261 | if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) || |
2262 | (pdev->subsystem_device != 0xe000)) | |
2e955856 | 2263 | return; |
2264 | ||
4da19633 | 2265 | rtl_writephy(tp, 0x1f, 0x0001); |
2266 | rtl_writephy(tp, 0x10, 0xf01b); | |
2267 | rtl_writephy(tp, 0x1f, 0x0000); | |
2e955856 | 2268 | } |
2269 | ||
4da19633 | 2270 | static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp) |
2e955856 | 2271 | { |
350f7596 | 2272 | static const struct phy_reg phy_reg_init[] = { |
2e955856 | 2273 | { 0x1f, 0x0001 }, |
2274 | { 0x04, 0x0000 }, | |
2275 | { 0x03, 0x00a1 }, | |
2276 | { 0x02, 0x0008 }, | |
2277 | { 0x01, 0x0120 }, | |
2278 | { 0x00, 0x1000 }, | |
2279 | { 0x04, 0x0800 }, | |
2280 | { 0x04, 0x9000 }, | |
2281 | { 0x03, 0x802f }, | |
2282 | { 0x02, 0x4f02 }, | |
2283 | { 0x01, 0x0409 }, | |
2284 | { 0x00, 0xf099 }, | |
2285 | { 0x04, 0x9800 }, | |
2286 | { 0x04, 0xa000 }, | |
2287 | { 0x03, 0xdf01 }, | |
2288 | { 0x02, 0xdf20 }, | |
2289 | { 0x01, 0xff95 }, | |
2290 | { 0x00, 0xba00 }, | |
2291 | { 0x04, 0xa800 }, | |
2292 | { 0x04, 0xf000 }, | |
2293 | { 0x03, 0xdf01 }, | |
2294 | { 0x02, 0xdf20 }, | |
2295 | { 0x01, 0x101a }, | |
2296 | { 0x00, 0xa0ff }, | |
2297 | { 0x04, 0xf800 }, | |
2298 | { 0x04, 0x0000 }, | |
2299 | { 0x1f, 0x0000 }, | |
2300 | ||
2301 | { 0x1f, 0x0001 }, | |
2302 | { 0x10, 0xf41b }, | |
2303 | { 0x14, 0xfb54 }, | |
2304 | { 0x18, 0xf5c7 }, | |
2305 | { 0x1f, 0x0000 }, | |
2306 | ||
2307 | { 0x1f, 0x0001 }, | |
2308 | { 0x17, 0x0cc0 }, | |
2309 | { 0x1f, 0x0000 } | |
2310 | }; | |
2311 | ||
4da19633 | 2312 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
2e955856 | 2313 | |
4da19633 | 2314 | rtl8169scd_hw_phy_config_quirk(tp); |
2e955856 | 2315 | } |
2316 | ||
4da19633 | 2317 | static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp) |
8c7006aa | 2318 | { |
350f7596 | 2319 | static const struct phy_reg phy_reg_init[] = { |
8c7006aa | 2320 | { 0x1f, 0x0001 }, |
2321 | { 0x04, 0x0000 }, | |
2322 | { 0x03, 0x00a1 }, | |
2323 | { 0x02, 0x0008 }, | |
2324 | { 0x01, 0x0120 }, | |
2325 | { 0x00, 0x1000 }, | |
2326 | { 0x04, 0x0800 }, | |
2327 | { 0x04, 0x9000 }, | |
2328 | { 0x03, 0x802f }, | |
2329 | { 0x02, 0x4f02 }, | |
2330 | { 0x01, 0x0409 }, | |
2331 | { 0x00, 0xf099 }, | |
2332 | { 0x04, 0x9800 }, | |
2333 | { 0x04, 0xa000 }, | |
2334 | { 0x03, 0xdf01 }, | |
2335 | { 0x02, 0xdf20 }, | |
2336 | { 0x01, 0xff95 }, | |
2337 | { 0x00, 0xba00 }, | |
2338 | { 0x04, 0xa800 }, | |
2339 | { 0x04, 0xf000 }, | |
2340 | { 0x03, 0xdf01 }, | |
2341 | { 0x02, 0xdf20 }, | |
2342 | { 0x01, 0x101a }, | |
2343 | { 0x00, 0xa0ff }, | |
2344 | { 0x04, 0xf800 }, | |
2345 | { 0x04, 0x0000 }, | |
2346 | { 0x1f, 0x0000 }, | |
2347 | ||
2348 | { 0x1f, 0x0001 }, | |
2349 | { 0x0b, 0x8480 }, | |
2350 | { 0x1f, 0x0000 }, | |
2351 | ||
2352 | { 0x1f, 0x0001 }, | |
2353 | { 0x18, 0x67c7 }, | |
2354 | { 0x04, 0x2000 }, | |
2355 | { 0x03, 0x002f }, | |
2356 | { 0x02, 0x4360 }, | |
2357 | { 0x01, 0x0109 }, | |
2358 | { 0x00, 0x3022 }, | |
2359 | { 0x04, 0x2800 }, | |
2360 | { 0x1f, 0x0000 }, | |
2361 | ||
2362 | { 0x1f, 0x0001 }, | |
2363 | { 0x17, 0x0cc0 }, | |
2364 | { 0x1f, 0x0000 } | |
2365 | }; | |
2366 | ||
4da19633 | 2367 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
8c7006aa | 2368 | } |
2369 | ||
4da19633 | 2370 | static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp) |
236b8082 | 2371 | { |
350f7596 | 2372 | static const struct phy_reg phy_reg_init[] = { |
236b8082 FR |
2373 | { 0x10, 0xf41b }, |
2374 | { 0x1f, 0x0000 } | |
2375 | }; | |
2376 | ||
4da19633 | 2377 | rtl_writephy(tp, 0x1f, 0x0001); |
2378 | rtl_patchphy(tp, 0x16, 1 << 0); | |
236b8082 | 2379 | |
4da19633 | 2380 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
236b8082 FR |
2381 | } |
2382 | ||
4da19633 | 2383 | static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp) |
236b8082 | 2384 | { |
350f7596 | 2385 | static const struct phy_reg phy_reg_init[] = { |
236b8082 FR |
2386 | { 0x1f, 0x0001 }, |
2387 | { 0x10, 0xf41b }, | |
2388 | { 0x1f, 0x0000 } | |
2389 | }; | |
2390 | ||
4da19633 | 2391 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
236b8082 FR |
2392 | } |
2393 | ||
4da19633 | 2394 | static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp) |
867763c1 | 2395 | { |
350f7596 | 2396 | static const struct phy_reg phy_reg_init[] = { |
867763c1 FR |
2397 | { 0x1f, 0x0000 }, |
2398 | { 0x1d, 0x0f00 }, | |
2399 | { 0x1f, 0x0002 }, | |
2400 | { 0x0c, 0x1ec8 }, | |
2401 | { 0x1f, 0x0000 } | |
2402 | }; | |
2403 | ||
4da19633 | 2404 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
867763c1 FR |
2405 | } |
2406 | ||
4da19633 | 2407 | static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp) |
ef3386f0 | 2408 | { |
350f7596 | 2409 | static const struct phy_reg phy_reg_init[] = { |
ef3386f0 FR |
2410 | { 0x1f, 0x0001 }, |
2411 | { 0x1d, 0x3d98 }, | |
2412 | { 0x1f, 0x0000 } | |
2413 | }; | |
2414 | ||
4da19633 | 2415 | rtl_writephy(tp, 0x1f, 0x0000); |
2416 | rtl_patchphy(tp, 0x14, 1 << 5); | |
2417 | rtl_patchphy(tp, 0x0d, 1 << 5); | |
ef3386f0 | 2418 | |
4da19633 | 2419 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
ef3386f0 FR |
2420 | } |
2421 | ||
4da19633 | 2422 | static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp) |
867763c1 | 2423 | { |
350f7596 | 2424 | static const struct phy_reg phy_reg_init[] = { |
a3f80671 FR |
2425 | { 0x1f, 0x0001 }, |
2426 | { 0x12, 0x2300 }, | |
867763c1 FR |
2427 | { 0x1f, 0x0002 }, |
2428 | { 0x00, 0x88d4 }, | |
2429 | { 0x01, 0x82b1 }, | |
2430 | { 0x03, 0x7002 }, | |
2431 | { 0x08, 0x9e30 }, | |
2432 | { 0x09, 0x01f0 }, | |
2433 | { 0x0a, 0x5500 }, | |
2434 | { 0x0c, 0x00c8 }, | |
2435 | { 0x1f, 0x0003 }, | |
2436 | { 0x12, 0xc096 }, | |
2437 | { 0x16, 0x000a }, | |
f50d4275 FR |
2438 | { 0x1f, 0x0000 }, |
2439 | { 0x1f, 0x0000 }, | |
2440 | { 0x09, 0x2000 }, | |
2441 | { 0x09, 0x0000 } | |
867763c1 FR |
2442 | }; |
2443 | ||
4da19633 | 2444 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
f50d4275 | 2445 | |
4da19633 | 2446 | rtl_patchphy(tp, 0x14, 1 << 5); |
2447 | rtl_patchphy(tp, 0x0d, 1 << 5); | |
2448 | rtl_writephy(tp, 0x1f, 0x0000); | |
867763c1 FR |
2449 | } |
2450 | ||
4da19633 | 2451 | static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp) |
7da97ec9 | 2452 | { |
350f7596 | 2453 | static const struct phy_reg phy_reg_init[] = { |
f50d4275 | 2454 | { 0x1f, 0x0001 }, |
7da97ec9 | 2455 | { 0x12, 0x2300 }, |
f50d4275 FR |
2456 | { 0x03, 0x802f }, |
2457 | { 0x02, 0x4f02 }, | |
2458 | { 0x01, 0x0409 }, | |
2459 | { 0x00, 0xf099 }, | |
2460 | { 0x04, 0x9800 }, | |
2461 | { 0x04, 0x9000 }, | |
2462 | { 0x1d, 0x3d98 }, | |
7da97ec9 FR |
2463 | { 0x1f, 0x0002 }, |
2464 | { 0x0c, 0x7eb8 }, | |
f50d4275 FR |
2465 | { 0x06, 0x0761 }, |
2466 | { 0x1f, 0x0003 }, | |
2467 | { 0x16, 0x0f0a }, | |
7da97ec9 FR |
2468 | { 0x1f, 0x0000 } |
2469 | }; | |
2470 | ||
4da19633 | 2471 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
f50d4275 | 2472 | |
4da19633 | 2473 | rtl_patchphy(tp, 0x16, 1 << 0); |
2474 | rtl_patchphy(tp, 0x14, 1 << 5); | |
2475 | rtl_patchphy(tp, 0x0d, 1 << 5); | |
2476 | rtl_writephy(tp, 0x1f, 0x0000); | |
7da97ec9 FR |
2477 | } |
2478 | ||
4da19633 | 2479 | static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp) |
197ff761 | 2480 | { |
350f7596 | 2481 | static const struct phy_reg phy_reg_init[] = { |
197ff761 FR |
2482 | { 0x1f, 0x0001 }, |
2483 | { 0x12, 0x2300 }, | |
2484 | { 0x1d, 0x3d98 }, | |
2485 | { 0x1f, 0x0002 }, | |
2486 | { 0x0c, 0x7eb8 }, | |
2487 | { 0x06, 0x5461 }, | |
2488 | { 0x1f, 0x0003 }, | |
2489 | { 0x16, 0x0f0a }, | |
2490 | { 0x1f, 0x0000 } | |
2491 | }; | |
2492 | ||
4da19633 | 2493 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
197ff761 | 2494 | |
4da19633 | 2495 | rtl_patchphy(tp, 0x16, 1 << 0); |
2496 | rtl_patchphy(tp, 0x14, 1 << 5); | |
2497 | rtl_patchphy(tp, 0x0d, 1 << 5); | |
2498 | rtl_writephy(tp, 0x1f, 0x0000); | |
197ff761 FR |
2499 | } |
2500 | ||
4da19633 | 2501 | static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp) |
6fb07058 | 2502 | { |
4da19633 | 2503 | rtl8168c_3_hw_phy_config(tp); |
6fb07058 FR |
2504 | } |
2505 | ||
bca03d5f | 2506 | static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp) |
5b538df9 | 2507 | { |
350f7596 | 2508 | static const struct phy_reg phy_reg_init_0[] = { |
bca03d5f | 2509 | /* Channel Estimation */ |
5b538df9 | 2510 | { 0x1f, 0x0001 }, |
daf9df6d | 2511 | { 0x06, 0x4064 }, |
2512 | { 0x07, 0x2863 }, | |
2513 | { 0x08, 0x059c }, | |
2514 | { 0x09, 0x26b4 }, | |
2515 | { 0x0a, 0x6a19 }, | |
2516 | { 0x0b, 0xdcc8 }, | |
2517 | { 0x10, 0xf06d }, | |
2518 | { 0x14, 0x7f68 }, | |
2519 | { 0x18, 0x7fd9 }, | |
2520 | { 0x1c, 0xf0ff }, | |
2521 | { 0x1d, 0x3d9c }, | |
5b538df9 | 2522 | { 0x1f, 0x0003 }, |
daf9df6d | 2523 | { 0x12, 0xf49f }, |
2524 | { 0x13, 0x070b }, | |
2525 | { 0x1a, 0x05ad }, | |
bca03d5f | 2526 | { 0x14, 0x94c0 }, |
2527 | ||
2528 | /* | |
2529 | * Tx Error Issue | |
cecb5fd7 | 2530 | * Enhance line driver power |
bca03d5f | 2531 | */ |
5b538df9 | 2532 | { 0x1f, 0x0002 }, |
daf9df6d | 2533 | { 0x06, 0x5561 }, |
2534 | { 0x1f, 0x0005 }, | |
2535 | { 0x05, 0x8332 }, | |
bca03d5f | 2536 | { 0x06, 0x5561 }, |
2537 | ||
2538 | /* | |
2539 | * Can not link to 1Gbps with bad cable | |
2540 | * Decrease SNR threshold form 21.07dB to 19.04dB | |
2541 | */ | |
2542 | { 0x1f, 0x0001 }, | |
2543 | { 0x17, 0x0cc0 }, | |
daf9df6d | 2544 | |
5b538df9 | 2545 | { 0x1f, 0x0000 }, |
bca03d5f | 2546 | { 0x0d, 0xf880 } |
daf9df6d | 2547 | }; |
bca03d5f | 2548 | void __iomem *ioaddr = tp->mmio_addr; |
daf9df6d | 2549 | |
4da19633 | 2550 | rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0)); |
daf9df6d | 2551 | |
bca03d5f | 2552 | /* |
2553 | * Rx Error Issue | |
2554 | * Fine Tune Switching regulator parameter | |
2555 | */ | |
4da19633 | 2556 | rtl_writephy(tp, 0x1f, 0x0002); |
2557 | rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef); | |
2558 | rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00); | |
daf9df6d | 2559 | |
daf9df6d | 2560 | if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) { |
350f7596 | 2561 | static const struct phy_reg phy_reg_init[] = { |
daf9df6d | 2562 | { 0x1f, 0x0002 }, |
2563 | { 0x05, 0x669a }, | |
2564 | { 0x1f, 0x0005 }, | |
2565 | { 0x05, 0x8330 }, | |
2566 | { 0x06, 0x669a }, | |
2567 | { 0x1f, 0x0002 } | |
2568 | }; | |
2569 | int val; | |
2570 | ||
4da19633 | 2571 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
daf9df6d | 2572 | |
4da19633 | 2573 | val = rtl_readphy(tp, 0x0d); |
daf9df6d | 2574 | |
2575 | if ((val & 0x00ff) != 0x006c) { | |
350f7596 | 2576 | static const u32 set[] = { |
daf9df6d | 2577 | 0x0065, 0x0066, 0x0067, 0x0068, |
2578 | 0x0069, 0x006a, 0x006b, 0x006c | |
2579 | }; | |
2580 | int i; | |
2581 | ||
4da19633 | 2582 | rtl_writephy(tp, 0x1f, 0x0002); |
daf9df6d | 2583 | |
2584 | val &= 0xff00; | |
2585 | for (i = 0; i < ARRAY_SIZE(set); i++) | |
4da19633 | 2586 | rtl_writephy(tp, 0x0d, val | set[i]); |
daf9df6d | 2587 | } |
2588 | } else { | |
350f7596 | 2589 | static const struct phy_reg phy_reg_init[] = { |
daf9df6d | 2590 | { 0x1f, 0x0002 }, |
2591 | { 0x05, 0x6662 }, | |
2592 | { 0x1f, 0x0005 }, | |
2593 | { 0x05, 0x8330 }, | |
2594 | { 0x06, 0x6662 } | |
2595 | }; | |
2596 | ||
4da19633 | 2597 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
daf9df6d | 2598 | } |
2599 | ||
bca03d5f | 2600 | /* RSET couple improve */ |
4da19633 | 2601 | rtl_writephy(tp, 0x1f, 0x0002); |
2602 | rtl_patchphy(tp, 0x0d, 0x0300); | |
2603 | rtl_patchphy(tp, 0x0f, 0x0010); | |
daf9df6d | 2604 | |
bca03d5f | 2605 | /* Fine tune PLL performance */ |
4da19633 | 2606 | rtl_writephy(tp, 0x1f, 0x0002); |
2607 | rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600); | |
2608 | rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000); | |
daf9df6d | 2609 | |
4da19633 | 2610 | rtl_writephy(tp, 0x1f, 0x0005); |
2611 | rtl_writephy(tp, 0x05, 0x001b); | |
953a12cc FR |
2612 | |
2613 | rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00); | |
bca03d5f | 2614 | |
4da19633 | 2615 | rtl_writephy(tp, 0x1f, 0x0000); |
daf9df6d | 2616 | } |
2617 | ||
bca03d5f | 2618 | static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp) |
daf9df6d | 2619 | { |
350f7596 | 2620 | static const struct phy_reg phy_reg_init_0[] = { |
bca03d5f | 2621 | /* Channel Estimation */ |
daf9df6d | 2622 | { 0x1f, 0x0001 }, |
2623 | { 0x06, 0x4064 }, | |
2624 | { 0x07, 0x2863 }, | |
2625 | { 0x08, 0x059c }, | |
2626 | { 0x09, 0x26b4 }, | |
2627 | { 0x0a, 0x6a19 }, | |
2628 | { 0x0b, 0xdcc8 }, | |
2629 | { 0x10, 0xf06d }, | |
2630 | { 0x14, 0x7f68 }, | |
2631 | { 0x18, 0x7fd9 }, | |
2632 | { 0x1c, 0xf0ff }, | |
2633 | { 0x1d, 0x3d9c }, | |
2634 | { 0x1f, 0x0003 }, | |
2635 | { 0x12, 0xf49f }, | |
2636 | { 0x13, 0x070b }, | |
2637 | { 0x1a, 0x05ad }, | |
2638 | { 0x14, 0x94c0 }, | |
2639 | ||
bca03d5f | 2640 | /* |
2641 | * Tx Error Issue | |
cecb5fd7 | 2642 | * Enhance line driver power |
bca03d5f | 2643 | */ |
daf9df6d | 2644 | { 0x1f, 0x0002 }, |
2645 | { 0x06, 0x5561 }, | |
2646 | { 0x1f, 0x0005 }, | |
2647 | { 0x05, 0x8332 }, | |
bca03d5f | 2648 | { 0x06, 0x5561 }, |
2649 | ||
2650 | /* | |
2651 | * Can not link to 1Gbps with bad cable | |
2652 | * Decrease SNR threshold form 21.07dB to 19.04dB | |
2653 | */ | |
2654 | { 0x1f, 0x0001 }, | |
2655 | { 0x17, 0x0cc0 }, | |
daf9df6d | 2656 | |
2657 | { 0x1f, 0x0000 }, | |
bca03d5f | 2658 | { 0x0d, 0xf880 } |
5b538df9 | 2659 | }; |
bca03d5f | 2660 | void __iomem *ioaddr = tp->mmio_addr; |
5b538df9 | 2661 | |
4da19633 | 2662 | rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0)); |
5b538df9 | 2663 | |
daf9df6d | 2664 | if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) { |
350f7596 | 2665 | static const struct phy_reg phy_reg_init[] = { |
daf9df6d | 2666 | { 0x1f, 0x0002 }, |
2667 | { 0x05, 0x669a }, | |
5b538df9 | 2668 | { 0x1f, 0x0005 }, |
daf9df6d | 2669 | { 0x05, 0x8330 }, |
2670 | { 0x06, 0x669a }, | |
2671 | ||
2672 | { 0x1f, 0x0002 } | |
2673 | }; | |
2674 | int val; | |
2675 | ||
4da19633 | 2676 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
daf9df6d | 2677 | |
4da19633 | 2678 | val = rtl_readphy(tp, 0x0d); |
daf9df6d | 2679 | if ((val & 0x00ff) != 0x006c) { |
b6bc7650 | 2680 | static const u32 set[] = { |
daf9df6d | 2681 | 0x0065, 0x0066, 0x0067, 0x0068, |
2682 | 0x0069, 0x006a, 0x006b, 0x006c | |
2683 | }; | |
2684 | int i; | |
2685 | ||
4da19633 | 2686 | rtl_writephy(tp, 0x1f, 0x0002); |
daf9df6d | 2687 | |
2688 | val &= 0xff00; | |
2689 | for (i = 0; i < ARRAY_SIZE(set); i++) | |
4da19633 | 2690 | rtl_writephy(tp, 0x0d, val | set[i]); |
daf9df6d | 2691 | } |
2692 | } else { | |
350f7596 | 2693 | static const struct phy_reg phy_reg_init[] = { |
daf9df6d | 2694 | { 0x1f, 0x0002 }, |
2695 | { 0x05, 0x2642 }, | |
5b538df9 | 2696 | { 0x1f, 0x0005 }, |
daf9df6d | 2697 | { 0x05, 0x8330 }, |
2698 | { 0x06, 0x2642 } | |
5b538df9 FR |
2699 | }; |
2700 | ||
4da19633 | 2701 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
5b538df9 FR |
2702 | } |
2703 | ||
bca03d5f | 2704 | /* Fine tune PLL performance */ |
4da19633 | 2705 | rtl_writephy(tp, 0x1f, 0x0002); |
2706 | rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600); | |
2707 | rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000); | |
daf9df6d | 2708 | |
bca03d5f | 2709 | /* Switching regulator Slew rate */ |
4da19633 | 2710 | rtl_writephy(tp, 0x1f, 0x0002); |
2711 | rtl_patchphy(tp, 0x0f, 0x0017); | |
daf9df6d | 2712 | |
4da19633 | 2713 | rtl_writephy(tp, 0x1f, 0x0005); |
2714 | rtl_writephy(tp, 0x05, 0x001b); | |
953a12cc FR |
2715 | |
2716 | rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300); | |
bca03d5f | 2717 | |
4da19633 | 2718 | rtl_writephy(tp, 0x1f, 0x0000); |
daf9df6d | 2719 | } |
2720 | ||
4da19633 | 2721 | static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp) |
daf9df6d | 2722 | { |
350f7596 | 2723 | static const struct phy_reg phy_reg_init[] = { |
daf9df6d | 2724 | { 0x1f, 0x0002 }, |
2725 | { 0x10, 0x0008 }, | |
2726 | { 0x0d, 0x006c }, | |
2727 | ||
2728 | { 0x1f, 0x0000 }, | |
2729 | { 0x0d, 0xf880 }, | |
2730 | ||
2731 | { 0x1f, 0x0001 }, | |
2732 | { 0x17, 0x0cc0 }, | |
2733 | ||
2734 | { 0x1f, 0x0001 }, | |
2735 | { 0x0b, 0xa4d8 }, | |
2736 | { 0x09, 0x281c }, | |
2737 | { 0x07, 0x2883 }, | |
2738 | { 0x0a, 0x6b35 }, | |
2739 | { 0x1d, 0x3da4 }, | |
2740 | { 0x1c, 0xeffd }, | |
2741 | { 0x14, 0x7f52 }, | |
2742 | { 0x18, 0x7fc6 }, | |
2743 | { 0x08, 0x0601 }, | |
2744 | { 0x06, 0x4063 }, | |
2745 | { 0x10, 0xf074 }, | |
2746 | { 0x1f, 0x0003 }, | |
2747 | { 0x13, 0x0789 }, | |
2748 | { 0x12, 0xf4bd }, | |
2749 | { 0x1a, 0x04fd }, | |
2750 | { 0x14, 0x84b0 }, | |
2751 | { 0x1f, 0x0000 }, | |
2752 | { 0x00, 0x9200 }, | |
2753 | ||
2754 | { 0x1f, 0x0005 }, | |
2755 | { 0x01, 0x0340 }, | |
2756 | { 0x1f, 0x0001 }, | |
2757 | { 0x04, 0x4000 }, | |
2758 | { 0x03, 0x1d21 }, | |
2759 | { 0x02, 0x0c32 }, | |
2760 | { 0x01, 0x0200 }, | |
2761 | { 0x00, 0x5554 }, | |
2762 | { 0x04, 0x4800 }, | |
2763 | { 0x04, 0x4000 }, | |
2764 | { 0x04, 0xf000 }, | |
2765 | { 0x03, 0xdf01 }, | |
2766 | { 0x02, 0xdf20 }, | |
2767 | { 0x01, 0x101a }, | |
2768 | { 0x00, 0xa0ff }, | |
2769 | { 0x04, 0xf800 }, | |
2770 | { 0x04, 0xf000 }, | |
2771 | { 0x1f, 0x0000 }, | |
2772 | ||
2773 | { 0x1f, 0x0007 }, | |
2774 | { 0x1e, 0x0023 }, | |
2775 | { 0x16, 0x0000 }, | |
2776 | { 0x1f, 0x0000 } | |
2777 | }; | |
2778 | ||
4da19633 | 2779 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
5b538df9 FR |
2780 | } |
2781 | ||
e6de30d6 | 2782 | static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp) |
2783 | { | |
2784 | static const struct phy_reg phy_reg_init[] = { | |
2785 | { 0x1f, 0x0001 }, | |
2786 | { 0x17, 0x0cc0 }, | |
2787 | ||
2788 | { 0x1f, 0x0007 }, | |
2789 | { 0x1e, 0x002d }, | |
2790 | { 0x18, 0x0040 }, | |
2791 | { 0x1f, 0x0000 } | |
2792 | }; | |
2793 | ||
2794 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); | |
2795 | rtl_patchphy(tp, 0x0d, 1 << 5); | |
2796 | } | |
2797 | ||
70090424 | 2798 | static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp) |
01dc7fec | 2799 | { |
2800 | static const struct phy_reg phy_reg_init[] = { | |
2801 | /* Enable Delay cap */ | |
2802 | { 0x1f, 0x0005 }, | |
2803 | { 0x05, 0x8b80 }, | |
2804 | { 0x06, 0xc896 }, | |
2805 | { 0x1f, 0x0000 }, | |
2806 | ||
2807 | /* Channel estimation fine tune */ | |
2808 | { 0x1f, 0x0001 }, | |
2809 | { 0x0b, 0x6c20 }, | |
2810 | { 0x07, 0x2872 }, | |
2811 | { 0x1c, 0xefff }, | |
2812 | { 0x1f, 0x0003 }, | |
2813 | { 0x14, 0x6420 }, | |
2814 | { 0x1f, 0x0000 }, | |
2815 | ||
2816 | /* Update PFM & 10M TX idle timer */ | |
2817 | { 0x1f, 0x0007 }, | |
2818 | { 0x1e, 0x002f }, | |
2819 | { 0x15, 0x1919 }, | |
2820 | { 0x1f, 0x0000 }, | |
2821 | ||
2822 | { 0x1f, 0x0007 }, | |
2823 | { 0x1e, 0x00ac }, | |
2824 | { 0x18, 0x0006 }, | |
2825 | { 0x1f, 0x0000 } | |
2826 | }; | |
2827 | ||
15ecd039 FR |
2828 | rtl_apply_firmware(tp); |
2829 | ||
01dc7fec | 2830 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
2831 | ||
2832 | /* DCO enable for 10M IDLE Power */ | |
2833 | rtl_writephy(tp, 0x1f, 0x0007); | |
2834 | rtl_writephy(tp, 0x1e, 0x0023); | |
2835 | rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000); | |
2836 | rtl_writephy(tp, 0x1f, 0x0000); | |
2837 | ||
2838 | /* For impedance matching */ | |
2839 | rtl_writephy(tp, 0x1f, 0x0002); | |
2840 | rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00); | |
cecb5fd7 | 2841 | rtl_writephy(tp, 0x1f, 0x0000); |
01dc7fec | 2842 | |
2843 | /* PHY auto speed down */ | |
2844 | rtl_writephy(tp, 0x1f, 0x0007); | |
2845 | rtl_writephy(tp, 0x1e, 0x002d); | |
2846 | rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000); | |
2847 | rtl_writephy(tp, 0x1f, 0x0000); | |
2848 | rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000); | |
2849 | ||
2850 | rtl_writephy(tp, 0x1f, 0x0005); | |
2851 | rtl_writephy(tp, 0x05, 0x8b86); | |
2852 | rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000); | |
2853 | rtl_writephy(tp, 0x1f, 0x0000); | |
2854 | ||
2855 | rtl_writephy(tp, 0x1f, 0x0005); | |
2856 | rtl_writephy(tp, 0x05, 0x8b85); | |
2857 | rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000); | |
2858 | rtl_writephy(tp, 0x1f, 0x0007); | |
2859 | rtl_writephy(tp, 0x1e, 0x0020); | |
2860 | rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100); | |
2861 | rtl_writephy(tp, 0x1f, 0x0006); | |
2862 | rtl_writephy(tp, 0x00, 0x5a00); | |
2863 | rtl_writephy(tp, 0x1f, 0x0000); | |
2864 | rtl_writephy(tp, 0x0d, 0x0007); | |
2865 | rtl_writephy(tp, 0x0e, 0x003c); | |
2866 | rtl_writephy(tp, 0x0d, 0x4007); | |
2867 | rtl_writephy(tp, 0x0e, 0x0000); | |
2868 | rtl_writephy(tp, 0x0d, 0x0000); | |
2869 | } | |
2870 | ||
70090424 HW |
2871 | static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp) |
2872 | { | |
2873 | static const struct phy_reg phy_reg_init[] = { | |
2874 | /* Enable Delay cap */ | |
2875 | { 0x1f, 0x0004 }, | |
2876 | { 0x1f, 0x0007 }, | |
2877 | { 0x1e, 0x00ac }, | |
2878 | { 0x18, 0x0006 }, | |
2879 | { 0x1f, 0x0002 }, | |
2880 | { 0x1f, 0x0000 }, | |
2881 | { 0x1f, 0x0000 }, | |
2882 | ||
2883 | /* Channel estimation fine tune */ | |
2884 | { 0x1f, 0x0003 }, | |
2885 | { 0x09, 0xa20f }, | |
2886 | { 0x1f, 0x0000 }, | |
2887 | { 0x1f, 0x0000 }, | |
2888 | ||
2889 | /* Green Setting */ | |
2890 | { 0x1f, 0x0005 }, | |
2891 | { 0x05, 0x8b5b }, | |
2892 | { 0x06, 0x9222 }, | |
2893 | { 0x05, 0x8b6d }, | |
2894 | { 0x06, 0x8000 }, | |
2895 | { 0x05, 0x8b76 }, | |
2896 | { 0x06, 0x8000 }, | |
2897 | { 0x1f, 0x0000 } | |
2898 | }; | |
2899 | ||
2900 | rtl_apply_firmware(tp); | |
2901 | ||
2902 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); | |
2903 | ||
2904 | /* For 4-corner performance improve */ | |
2905 | rtl_writephy(tp, 0x1f, 0x0005); | |
2906 | rtl_writephy(tp, 0x05, 0x8b80); | |
2907 | rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000); | |
2908 | rtl_writephy(tp, 0x1f, 0x0000); | |
2909 | ||
2910 | /* PHY auto speed down */ | |
2911 | rtl_writephy(tp, 0x1f, 0x0004); | |
2912 | rtl_writephy(tp, 0x1f, 0x0007); | |
2913 | rtl_writephy(tp, 0x1e, 0x002d); | |
2914 | rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000); | |
2915 | rtl_writephy(tp, 0x1f, 0x0002); | |
2916 | rtl_writephy(tp, 0x1f, 0x0000); | |
2917 | rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000); | |
2918 | ||
2919 | /* improve 10M EEE waveform */ | |
2920 | rtl_writephy(tp, 0x1f, 0x0005); | |
2921 | rtl_writephy(tp, 0x05, 0x8b86); | |
2922 | rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000); | |
2923 | rtl_writephy(tp, 0x1f, 0x0000); | |
2924 | ||
2925 | /* Improve 2-pair detection performance */ | |
2926 | rtl_writephy(tp, 0x1f, 0x0005); | |
2927 | rtl_writephy(tp, 0x05, 0x8b85); | |
2928 | rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000); | |
2929 | rtl_writephy(tp, 0x1f, 0x0000); | |
2930 | ||
2931 | /* EEE setting */ | |
2932 | rtl_w1w0_eri(tp->mmio_addr, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003, | |
2933 | ERIAR_EXGMAC); | |
2934 | rtl_writephy(tp, 0x1f, 0x0005); | |
2935 | rtl_writephy(tp, 0x05, 0x8b85); | |
2936 | rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000); | |
2937 | rtl_writephy(tp, 0x1f, 0x0004); | |
2938 | rtl_writephy(tp, 0x1f, 0x0007); | |
2939 | rtl_writephy(tp, 0x1e, 0x0020); | |
2940 | rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100); | |
2941 | rtl_writephy(tp, 0x1f, 0x0002); | |
2942 | rtl_writephy(tp, 0x1f, 0x0000); | |
2943 | rtl_writephy(tp, 0x0d, 0x0007); | |
2944 | rtl_writephy(tp, 0x0e, 0x003c); | |
2945 | rtl_writephy(tp, 0x0d, 0x4007); | |
2946 | rtl_writephy(tp, 0x0e, 0x0000); | |
2947 | rtl_writephy(tp, 0x0d, 0x0000); | |
2948 | ||
2949 | /* Green feature */ | |
2950 | rtl_writephy(tp, 0x1f, 0x0003); | |
2951 | rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001); | |
2952 | rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400); | |
2953 | rtl_writephy(tp, 0x1f, 0x0000); | |
2954 | } | |
2955 | ||
c2218925 HW |
2956 | static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp) |
2957 | { | |
2958 | static const struct phy_reg phy_reg_init[] = { | |
2959 | /* Channel estimation fine tune */ | |
2960 | { 0x1f, 0x0003 }, | |
2961 | { 0x09, 0xa20f }, | |
2962 | { 0x1f, 0x0000 }, | |
2963 | ||
2964 | /* Modify green table for giga & fnet */ | |
2965 | { 0x1f, 0x0005 }, | |
2966 | { 0x05, 0x8b55 }, | |
2967 | { 0x06, 0x0000 }, | |
2968 | { 0x05, 0x8b5e }, | |
2969 | { 0x06, 0x0000 }, | |
2970 | { 0x05, 0x8b67 }, | |
2971 | { 0x06, 0x0000 }, | |
2972 | { 0x05, 0x8b70 }, | |
2973 | { 0x06, 0x0000 }, | |
2974 | { 0x1f, 0x0000 }, | |
2975 | { 0x1f, 0x0007 }, | |
2976 | { 0x1e, 0x0078 }, | |
2977 | { 0x17, 0x0000 }, | |
2978 | { 0x19, 0x00fb }, | |
2979 | { 0x1f, 0x0000 }, | |
2980 | ||
2981 | /* Modify green table for 10M */ | |
2982 | { 0x1f, 0x0005 }, | |
2983 | { 0x05, 0x8b79 }, | |
2984 | { 0x06, 0xaa00 }, | |
2985 | { 0x1f, 0x0000 }, | |
2986 | ||
2987 | /* Disable hiimpedance detection (RTCT) */ | |
2988 | { 0x1f, 0x0003 }, | |
2989 | { 0x01, 0x328a }, | |
2990 | { 0x1f, 0x0000 } | |
2991 | }; | |
2992 | ||
2993 | rtl_apply_firmware(tp); | |
2994 | ||
2995 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); | |
2996 | ||
2997 | /* For 4-corner performance improve */ | |
2998 | rtl_writephy(tp, 0x1f, 0x0005); | |
2999 | rtl_writephy(tp, 0x05, 0x8b80); | |
3000 | rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000); | |
3001 | rtl_writephy(tp, 0x1f, 0x0000); | |
3002 | ||
3003 | /* PHY auto speed down */ | |
3004 | rtl_writephy(tp, 0x1f, 0x0007); | |
3005 | rtl_writephy(tp, 0x1e, 0x002d); | |
3006 | rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000); | |
3007 | rtl_writephy(tp, 0x1f, 0x0000); | |
3008 | rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000); | |
3009 | ||
3010 | /* Improve 10M EEE waveform */ | |
3011 | rtl_writephy(tp, 0x1f, 0x0005); | |
3012 | rtl_writephy(tp, 0x05, 0x8b86); | |
3013 | rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000); | |
3014 | rtl_writephy(tp, 0x1f, 0x0000); | |
3015 | ||
3016 | /* Improve 2-pair detection performance */ | |
3017 | rtl_writephy(tp, 0x1f, 0x0005); | |
3018 | rtl_writephy(tp, 0x05, 0x8b85); | |
3019 | rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000); | |
3020 | rtl_writephy(tp, 0x1f, 0x0000); | |
3021 | } | |
3022 | ||
3023 | static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp) | |
3024 | { | |
3025 | rtl_apply_firmware(tp); | |
3026 | ||
3027 | /* For 4-corner performance improve */ | |
3028 | rtl_writephy(tp, 0x1f, 0x0005); | |
3029 | rtl_writephy(tp, 0x05, 0x8b80); | |
3030 | rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000); | |
3031 | rtl_writephy(tp, 0x1f, 0x0000); | |
3032 | ||
3033 | /* PHY auto speed down */ | |
3034 | rtl_writephy(tp, 0x1f, 0x0007); | |
3035 | rtl_writephy(tp, 0x1e, 0x002d); | |
3036 | rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000); | |
3037 | rtl_writephy(tp, 0x1f, 0x0000); | |
3038 | rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000); | |
3039 | ||
3040 | /* Improve 10M EEE waveform */ | |
3041 | rtl_writephy(tp, 0x1f, 0x0005); | |
3042 | rtl_writephy(tp, 0x05, 0x8b86); | |
3043 | rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000); | |
3044 | rtl_writephy(tp, 0x1f, 0x0000); | |
3045 | } | |
3046 | ||
4da19633 | 3047 | static void rtl8102e_hw_phy_config(struct rtl8169_private *tp) |
2857ffb7 | 3048 | { |
350f7596 | 3049 | static const struct phy_reg phy_reg_init[] = { |
2857ffb7 FR |
3050 | { 0x1f, 0x0003 }, |
3051 | { 0x08, 0x441d }, | |
3052 | { 0x01, 0x9100 }, | |
3053 | { 0x1f, 0x0000 } | |
3054 | }; | |
3055 | ||
4da19633 | 3056 | rtl_writephy(tp, 0x1f, 0x0000); |
3057 | rtl_patchphy(tp, 0x11, 1 << 12); | |
3058 | rtl_patchphy(tp, 0x19, 1 << 13); | |
3059 | rtl_patchphy(tp, 0x10, 1 << 15); | |
2857ffb7 | 3060 | |
4da19633 | 3061 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
2857ffb7 FR |
3062 | } |
3063 | ||
5a5e4443 HW |
3064 | static void rtl8105e_hw_phy_config(struct rtl8169_private *tp) |
3065 | { | |
3066 | static const struct phy_reg phy_reg_init[] = { | |
3067 | { 0x1f, 0x0005 }, | |
3068 | { 0x1a, 0x0000 }, | |
3069 | { 0x1f, 0x0000 }, | |
3070 | ||
3071 | { 0x1f, 0x0004 }, | |
3072 | { 0x1c, 0x0000 }, | |
3073 | { 0x1f, 0x0000 }, | |
3074 | ||
3075 | { 0x1f, 0x0001 }, | |
3076 | { 0x15, 0x7701 }, | |
3077 | { 0x1f, 0x0000 } | |
3078 | }; | |
3079 | ||
3080 | /* Disable ALDPS before ram code */ | |
3081 | rtl_writephy(tp, 0x1f, 0x0000); | |
3082 | rtl_writephy(tp, 0x18, 0x0310); | |
3083 | msleep(100); | |
3084 | ||
953a12cc | 3085 | rtl_apply_firmware(tp); |
5a5e4443 HW |
3086 | |
3087 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); | |
3088 | } | |
3089 | ||
5615d9f1 FR |
3090 | static void rtl_hw_phy_config(struct net_device *dev) |
3091 | { | |
3092 | struct rtl8169_private *tp = netdev_priv(dev); | |
5615d9f1 FR |
3093 | |
3094 | rtl8169_print_mac_version(tp); | |
3095 | ||
3096 | switch (tp->mac_version) { | |
3097 | case RTL_GIGA_MAC_VER_01: | |
3098 | break; | |
3099 | case RTL_GIGA_MAC_VER_02: | |
3100 | case RTL_GIGA_MAC_VER_03: | |
4da19633 | 3101 | rtl8169s_hw_phy_config(tp); |
5615d9f1 FR |
3102 | break; |
3103 | case RTL_GIGA_MAC_VER_04: | |
4da19633 | 3104 | rtl8169sb_hw_phy_config(tp); |
5615d9f1 | 3105 | break; |
2e955856 | 3106 | case RTL_GIGA_MAC_VER_05: |
4da19633 | 3107 | rtl8169scd_hw_phy_config(tp); |
2e955856 | 3108 | break; |
8c7006aa | 3109 | case RTL_GIGA_MAC_VER_06: |
4da19633 | 3110 | rtl8169sce_hw_phy_config(tp); |
8c7006aa | 3111 | break; |
2857ffb7 FR |
3112 | case RTL_GIGA_MAC_VER_07: |
3113 | case RTL_GIGA_MAC_VER_08: | |
3114 | case RTL_GIGA_MAC_VER_09: | |
4da19633 | 3115 | rtl8102e_hw_phy_config(tp); |
2857ffb7 | 3116 | break; |
236b8082 | 3117 | case RTL_GIGA_MAC_VER_11: |
4da19633 | 3118 | rtl8168bb_hw_phy_config(tp); |
236b8082 FR |
3119 | break; |
3120 | case RTL_GIGA_MAC_VER_12: | |
4da19633 | 3121 | rtl8168bef_hw_phy_config(tp); |
236b8082 FR |
3122 | break; |
3123 | case RTL_GIGA_MAC_VER_17: | |
4da19633 | 3124 | rtl8168bef_hw_phy_config(tp); |
236b8082 | 3125 | break; |
867763c1 | 3126 | case RTL_GIGA_MAC_VER_18: |
4da19633 | 3127 | rtl8168cp_1_hw_phy_config(tp); |
867763c1 FR |
3128 | break; |
3129 | case RTL_GIGA_MAC_VER_19: | |
4da19633 | 3130 | rtl8168c_1_hw_phy_config(tp); |
867763c1 | 3131 | break; |
7da97ec9 | 3132 | case RTL_GIGA_MAC_VER_20: |
4da19633 | 3133 | rtl8168c_2_hw_phy_config(tp); |
7da97ec9 | 3134 | break; |
197ff761 | 3135 | case RTL_GIGA_MAC_VER_21: |
4da19633 | 3136 | rtl8168c_3_hw_phy_config(tp); |
197ff761 | 3137 | break; |
6fb07058 | 3138 | case RTL_GIGA_MAC_VER_22: |
4da19633 | 3139 | rtl8168c_4_hw_phy_config(tp); |
6fb07058 | 3140 | break; |
ef3386f0 | 3141 | case RTL_GIGA_MAC_VER_23: |
7f3e3d3a | 3142 | case RTL_GIGA_MAC_VER_24: |
4da19633 | 3143 | rtl8168cp_2_hw_phy_config(tp); |
ef3386f0 | 3144 | break; |
5b538df9 | 3145 | case RTL_GIGA_MAC_VER_25: |
bca03d5f | 3146 | rtl8168d_1_hw_phy_config(tp); |
daf9df6d | 3147 | break; |
3148 | case RTL_GIGA_MAC_VER_26: | |
bca03d5f | 3149 | rtl8168d_2_hw_phy_config(tp); |
daf9df6d | 3150 | break; |
3151 | case RTL_GIGA_MAC_VER_27: | |
4da19633 | 3152 | rtl8168d_3_hw_phy_config(tp); |
5b538df9 | 3153 | break; |
e6de30d6 | 3154 | case RTL_GIGA_MAC_VER_28: |
3155 | rtl8168d_4_hw_phy_config(tp); | |
3156 | break; | |
5a5e4443 HW |
3157 | case RTL_GIGA_MAC_VER_29: |
3158 | case RTL_GIGA_MAC_VER_30: | |
3159 | rtl8105e_hw_phy_config(tp); | |
3160 | break; | |
cecb5fd7 FR |
3161 | case RTL_GIGA_MAC_VER_31: |
3162 | /* None. */ | |
3163 | break; | |
01dc7fec | 3164 | case RTL_GIGA_MAC_VER_32: |
01dc7fec | 3165 | case RTL_GIGA_MAC_VER_33: |
70090424 HW |
3166 | rtl8168e_1_hw_phy_config(tp); |
3167 | break; | |
3168 | case RTL_GIGA_MAC_VER_34: | |
3169 | rtl8168e_2_hw_phy_config(tp); | |
01dc7fec | 3170 | break; |
c2218925 HW |
3171 | case RTL_GIGA_MAC_VER_35: |
3172 | rtl8168f_1_hw_phy_config(tp); | |
3173 | break; | |
3174 | case RTL_GIGA_MAC_VER_36: | |
3175 | rtl8168f_2_hw_phy_config(tp); | |
3176 | break; | |
ef3386f0 | 3177 | |
5615d9f1 FR |
3178 | default: |
3179 | break; | |
3180 | } | |
3181 | } | |
3182 | ||
1da177e4 LT |
3183 | static void rtl8169_phy_timer(unsigned long __opaque) |
3184 | { | |
3185 | struct net_device *dev = (struct net_device *)__opaque; | |
3186 | struct rtl8169_private *tp = netdev_priv(dev); | |
3187 | struct timer_list *timer = &tp->timer; | |
3188 | void __iomem *ioaddr = tp->mmio_addr; | |
3189 | unsigned long timeout = RTL8169_PHY_TIMEOUT; | |
3190 | ||
bcf0bf90 | 3191 | assert(tp->mac_version > RTL_GIGA_MAC_VER_01); |
1da177e4 | 3192 | |
1da177e4 LT |
3193 | spin_lock_irq(&tp->lock); |
3194 | ||
4da19633 | 3195 | if (tp->phy_reset_pending(tp)) { |
5b0384f4 | 3196 | /* |
1da177e4 LT |
3197 | * A busy loop could burn quite a few cycles on nowadays CPU. |
3198 | * Let's delay the execution of the timer for a few ticks. | |
3199 | */ | |
3200 | timeout = HZ/10; | |
3201 | goto out_mod_timer; | |
3202 | } | |
3203 | ||
3204 | if (tp->link_ok(ioaddr)) | |
3205 | goto out_unlock; | |
3206 | ||
bf82c189 | 3207 | netif_warn(tp, link, dev, "PHY reset until link up\n"); |
1da177e4 | 3208 | |
4da19633 | 3209 | tp->phy_reset_enable(tp); |
1da177e4 LT |
3210 | |
3211 | out_mod_timer: | |
3212 | mod_timer(timer, jiffies + timeout); | |
3213 | out_unlock: | |
3214 | spin_unlock_irq(&tp->lock); | |
3215 | } | |
3216 | ||
1da177e4 LT |
3217 | #ifdef CONFIG_NET_POLL_CONTROLLER |
3218 | /* | |
3219 | * Polling 'interrupt' - used by things like netconsole to send skbs | |
3220 | * without having to re-enable interrupts. It's not called while | |
3221 | * the interrupt routine is executing. | |
3222 | */ | |
3223 | static void rtl8169_netpoll(struct net_device *dev) | |
3224 | { | |
3225 | struct rtl8169_private *tp = netdev_priv(dev); | |
3226 | struct pci_dev *pdev = tp->pci_dev; | |
3227 | ||
3228 | disable_irq(pdev->irq); | |
7d12e780 | 3229 | rtl8169_interrupt(pdev->irq, dev); |
1da177e4 LT |
3230 | enable_irq(pdev->irq); |
3231 | } | |
3232 | #endif | |
3233 | ||
3234 | static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev, | |
3235 | void __iomem *ioaddr) | |
3236 | { | |
3237 | iounmap(ioaddr); | |
3238 | pci_release_regions(pdev); | |
87aeec76 | 3239 | pci_clear_mwi(pdev); |
1da177e4 LT |
3240 | pci_disable_device(pdev); |
3241 | free_netdev(dev); | |
3242 | } | |
3243 | ||
bf793295 FR |
3244 | static void rtl8169_phy_reset(struct net_device *dev, |
3245 | struct rtl8169_private *tp) | |
3246 | { | |
07d3f51f | 3247 | unsigned int i; |
bf793295 | 3248 | |
4da19633 | 3249 | tp->phy_reset_enable(tp); |
bf793295 | 3250 | for (i = 0; i < 100; i++) { |
4da19633 | 3251 | if (!tp->phy_reset_pending(tp)) |
bf793295 FR |
3252 | return; |
3253 | msleep(1); | |
3254 | } | |
bf82c189 | 3255 | netif_err(tp, link, dev, "PHY reset failed\n"); |
bf793295 FR |
3256 | } |
3257 | ||
2544bfc0 FR |
3258 | static bool rtl_tbi_enabled(struct rtl8169_private *tp) |
3259 | { | |
3260 | void __iomem *ioaddr = tp->mmio_addr; | |
3261 | ||
3262 | return (tp->mac_version == RTL_GIGA_MAC_VER_01) && | |
3263 | (RTL_R8(PHYstatus) & TBI_Enable); | |
3264 | } | |
3265 | ||
4ff96fa6 FR |
3266 | static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp) |
3267 | { | |
3268 | void __iomem *ioaddr = tp->mmio_addr; | |
4ff96fa6 | 3269 | |
5615d9f1 | 3270 | rtl_hw_phy_config(dev); |
4ff96fa6 | 3271 | |
77332894 MS |
3272 | if (tp->mac_version <= RTL_GIGA_MAC_VER_06) { |
3273 | dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n"); | |
3274 | RTL_W8(0x82, 0x01); | |
3275 | } | |
4ff96fa6 | 3276 | |
6dccd16b FR |
3277 | pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); |
3278 | ||
3279 | if (tp->mac_version <= RTL_GIGA_MAC_VER_06) | |
3280 | pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); | |
4ff96fa6 | 3281 | |
bcf0bf90 | 3282 | if (tp->mac_version == RTL_GIGA_MAC_VER_02) { |
4ff96fa6 FR |
3283 | dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n"); |
3284 | RTL_W8(0x82, 0x01); | |
3285 | dprintk("Set PHY Reg 0x0bh = 0x00h\n"); | |
4da19633 | 3286 | rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0 |
4ff96fa6 FR |
3287 | } |
3288 | ||
bf793295 FR |
3289 | rtl8169_phy_reset(dev, tp); |
3290 | ||
54405cde | 3291 | rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL, |
cecb5fd7 FR |
3292 | ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | |
3293 | ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | | |
3294 | (tp->mii.supports_gmii ? | |
3295 | ADVERTISED_1000baseT_Half | | |
3296 | ADVERTISED_1000baseT_Full : 0)); | |
4ff96fa6 | 3297 | |
2544bfc0 | 3298 | if (rtl_tbi_enabled(tp)) |
bf82c189 | 3299 | netif_info(tp, link, dev, "TBI auto-negotiating\n"); |
4ff96fa6 FR |
3300 | } |
3301 | ||
773d2021 FR |
3302 | static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr) |
3303 | { | |
3304 | void __iomem *ioaddr = tp->mmio_addr; | |
3305 | u32 high; | |
3306 | u32 low; | |
3307 | ||
3308 | low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24); | |
3309 | high = addr[4] | (addr[5] << 8); | |
3310 | ||
3311 | spin_lock_irq(&tp->lock); | |
3312 | ||
3313 | RTL_W8(Cfg9346, Cfg9346_Unlock); | |
908ba2bf | 3314 | |
773d2021 | 3315 | RTL_W32(MAC4, high); |
908ba2bf | 3316 | RTL_R32(MAC4); |
3317 | ||
78f1cd02 | 3318 | RTL_W32(MAC0, low); |
908ba2bf | 3319 | RTL_R32(MAC0); |
3320 | ||
c28aa385 | 3321 | if (tp->mac_version == RTL_GIGA_MAC_VER_34) { |
3322 | const struct exgmac_reg e[] = { | |
3323 | { .addr = 0xe0, ERIAR_MASK_1111, .val = low }, | |
3324 | { .addr = 0xe4, ERIAR_MASK_1111, .val = high }, | |
3325 | { .addr = 0xf0, ERIAR_MASK_1111, .val = low << 16 }, | |
3326 | { .addr = 0xf4, ERIAR_MASK_1111, .val = high << 16 | | |
3327 | low >> 16 }, | |
3328 | }; | |
3329 | ||
3330 | rtl_write_exgmac_batch(ioaddr, e, ARRAY_SIZE(e)); | |
3331 | } | |
3332 | ||
773d2021 FR |
3333 | RTL_W8(Cfg9346, Cfg9346_Lock); |
3334 | ||
3335 | spin_unlock_irq(&tp->lock); | |
3336 | } | |
3337 | ||
3338 | static int rtl_set_mac_address(struct net_device *dev, void *p) | |
3339 | { | |
3340 | struct rtl8169_private *tp = netdev_priv(dev); | |
3341 | struct sockaddr *addr = p; | |
3342 | ||
3343 | if (!is_valid_ether_addr(addr->sa_data)) | |
3344 | return -EADDRNOTAVAIL; | |
3345 | ||
3346 | memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); | |
3347 | ||
3348 | rtl_rar_set(tp, dev->dev_addr); | |
3349 | ||
3350 | return 0; | |
3351 | } | |
3352 | ||
5f787a1a FR |
3353 | static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
3354 | { | |
3355 | struct rtl8169_private *tp = netdev_priv(dev); | |
3356 | struct mii_ioctl_data *data = if_mii(ifr); | |
3357 | ||
8b4ab28d FR |
3358 | return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV; |
3359 | } | |
5f787a1a | 3360 | |
cecb5fd7 FR |
3361 | static int rtl_xmii_ioctl(struct rtl8169_private *tp, |
3362 | struct mii_ioctl_data *data, int cmd) | |
8b4ab28d | 3363 | { |
5f787a1a FR |
3364 | switch (cmd) { |
3365 | case SIOCGMIIPHY: | |
3366 | data->phy_id = 32; /* Internal PHY */ | |
3367 | return 0; | |
3368 | ||
3369 | case SIOCGMIIREG: | |
4da19633 | 3370 | data->val_out = rtl_readphy(tp, data->reg_num & 0x1f); |
5f787a1a FR |
3371 | return 0; |
3372 | ||
3373 | case SIOCSMIIREG: | |
4da19633 | 3374 | rtl_writephy(tp, data->reg_num & 0x1f, data->val_in); |
5f787a1a FR |
3375 | return 0; |
3376 | } | |
3377 | return -EOPNOTSUPP; | |
3378 | } | |
3379 | ||
8b4ab28d FR |
3380 | static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd) |
3381 | { | |
3382 | return -EOPNOTSUPP; | |
3383 | } | |
3384 | ||
0e485150 FR |
3385 | static const struct rtl_cfg_info { |
3386 | void (*hw_start)(struct net_device *); | |
3387 | unsigned int region; | |
3388 | unsigned int align; | |
3389 | u16 intr_event; | |
3390 | u16 napi_event; | |
ccdffb9a | 3391 | unsigned features; |
f21b75e9 | 3392 | u8 default_ver; |
0e485150 FR |
3393 | } rtl_cfg_infos [] = { |
3394 | [RTL_CFG_0] = { | |
3395 | .hw_start = rtl_hw_start_8169, | |
3396 | .region = 1, | |
e9f63f30 | 3397 | .align = 0, |
0e485150 FR |
3398 | .intr_event = SYSErr | LinkChg | RxOverflow | |
3399 | RxFIFOOver | TxErr | TxOK | RxOK | RxErr, | |
fbac58fc | 3400 | .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow, |
f21b75e9 JD |
3401 | .features = RTL_FEATURE_GMII, |
3402 | .default_ver = RTL_GIGA_MAC_VER_01, | |
0e485150 FR |
3403 | }, |
3404 | [RTL_CFG_1] = { | |
3405 | .hw_start = rtl_hw_start_8168, | |
3406 | .region = 2, | |
3407 | .align = 8, | |
53f57357 | 3408 | .intr_event = SYSErr | LinkChg | RxOverflow | |
0e485150 | 3409 | TxErr | TxOK | RxOK | RxErr, |
fbac58fc | 3410 | .napi_event = TxErr | TxOK | RxOK | RxOverflow, |
f21b75e9 JD |
3411 | .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI, |
3412 | .default_ver = RTL_GIGA_MAC_VER_11, | |
0e485150 FR |
3413 | }, |
3414 | [RTL_CFG_2] = { | |
3415 | .hw_start = rtl_hw_start_8101, | |
3416 | .region = 2, | |
3417 | .align = 8, | |
3418 | .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout | | |
3419 | RxFIFOOver | TxErr | TxOK | RxOK | RxErr, | |
fbac58fc | 3420 | .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow, |
f21b75e9 JD |
3421 | .features = RTL_FEATURE_MSI, |
3422 | .default_ver = RTL_GIGA_MAC_VER_13, | |
0e485150 FR |
3423 | } |
3424 | }; | |
3425 | ||
fbac58fc FR |
3426 | /* Cfg9346_Unlock assumed. */ |
3427 | static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr, | |
3428 | const struct rtl_cfg_info *cfg) | |
3429 | { | |
3430 | unsigned msi = 0; | |
3431 | u8 cfg2; | |
3432 | ||
3433 | cfg2 = RTL_R8(Config2) & ~MSIEnable; | |
ccdffb9a | 3434 | if (cfg->features & RTL_FEATURE_MSI) { |
fbac58fc FR |
3435 | if (pci_enable_msi(pdev)) { |
3436 | dev_info(&pdev->dev, "no MSI. Back to INTx.\n"); | |
3437 | } else { | |
3438 | cfg2 |= MSIEnable; | |
3439 | msi = RTL_FEATURE_MSI; | |
3440 | } | |
3441 | } | |
3442 | RTL_W8(Config2, cfg2); | |
3443 | return msi; | |
3444 | } | |
3445 | ||
3446 | static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp) | |
3447 | { | |
3448 | if (tp->features & RTL_FEATURE_MSI) { | |
3449 | pci_disable_msi(pdev); | |
3450 | tp->features &= ~RTL_FEATURE_MSI; | |
3451 | } | |
3452 | } | |
3453 | ||
8b4ab28d FR |
3454 | static const struct net_device_ops rtl8169_netdev_ops = { |
3455 | .ndo_open = rtl8169_open, | |
3456 | .ndo_stop = rtl8169_close, | |
3457 | .ndo_get_stats = rtl8169_get_stats, | |
00829823 | 3458 | .ndo_start_xmit = rtl8169_start_xmit, |
8b4ab28d FR |
3459 | .ndo_tx_timeout = rtl8169_tx_timeout, |
3460 | .ndo_validate_addr = eth_validate_addr, | |
3461 | .ndo_change_mtu = rtl8169_change_mtu, | |
350fb32a MM |
3462 | .ndo_fix_features = rtl8169_fix_features, |
3463 | .ndo_set_features = rtl8169_set_features, | |
8b4ab28d FR |
3464 | .ndo_set_mac_address = rtl_set_mac_address, |
3465 | .ndo_do_ioctl = rtl8169_ioctl, | |
afc4b13d | 3466 | .ndo_set_rx_mode = rtl_set_rx_mode, |
8b4ab28d FR |
3467 | #ifdef CONFIG_NET_POLL_CONTROLLER |
3468 | .ndo_poll_controller = rtl8169_netpoll, | |
3469 | #endif | |
3470 | ||
3471 | }; | |
3472 | ||
c0e45c1c | 3473 | static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp) |
3474 | { | |
3475 | struct mdio_ops *ops = &tp->mdio_ops; | |
3476 | ||
3477 | switch (tp->mac_version) { | |
3478 | case RTL_GIGA_MAC_VER_27: | |
3479 | ops->write = r8168dp_1_mdio_write; | |
3480 | ops->read = r8168dp_1_mdio_read; | |
3481 | break; | |
e6de30d6 | 3482 | case RTL_GIGA_MAC_VER_28: |
4804b3b3 | 3483 | case RTL_GIGA_MAC_VER_31: |
e6de30d6 | 3484 | ops->write = r8168dp_2_mdio_write; |
3485 | ops->read = r8168dp_2_mdio_read; | |
3486 | break; | |
c0e45c1c | 3487 | default: |
3488 | ops->write = r8169_mdio_write; | |
3489 | ops->read = r8169_mdio_read; | |
3490 | break; | |
3491 | } | |
3492 | } | |
3493 | ||
065c27c1 | 3494 | static void r810x_phy_power_down(struct rtl8169_private *tp) |
3495 | { | |
3496 | rtl_writephy(tp, 0x1f, 0x0000); | |
3497 | rtl_writephy(tp, MII_BMCR, BMCR_PDOWN); | |
3498 | } | |
3499 | ||
3500 | static void r810x_phy_power_up(struct rtl8169_private *tp) | |
3501 | { | |
3502 | rtl_writephy(tp, 0x1f, 0x0000); | |
3503 | rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE); | |
3504 | } | |
3505 | ||
3506 | static void r810x_pll_power_down(struct rtl8169_private *tp) | |
3507 | { | |
10663389 HW |
3508 | void __iomem *ioaddr = tp->mmio_addr; |
3509 | ||
065c27c1 | 3510 | if (__rtl8169_get_wol(tp) & WAKE_ANY) { |
3511 | rtl_writephy(tp, 0x1f, 0x0000); | |
3512 | rtl_writephy(tp, MII_BMCR, 0x0000); | |
10663389 HW |
3513 | |
3514 | if (tp->mac_version == RTL_GIGA_MAC_VER_29 || | |
3515 | tp->mac_version == RTL_GIGA_MAC_VER_30) | |
3516 | RTL_W32(RxConfig, RTL_R32(RxConfig) | AcceptBroadcast | | |
3517 | AcceptMulticast | AcceptMyPhys); | |
065c27c1 | 3518 | return; |
3519 | } | |
3520 | ||
3521 | r810x_phy_power_down(tp); | |
3522 | } | |
3523 | ||
3524 | static void r810x_pll_power_up(struct rtl8169_private *tp) | |
3525 | { | |
3526 | r810x_phy_power_up(tp); | |
3527 | } | |
3528 | ||
3529 | static void r8168_phy_power_up(struct rtl8169_private *tp) | |
3530 | { | |
3531 | rtl_writephy(tp, 0x1f, 0x0000); | |
01dc7fec | 3532 | switch (tp->mac_version) { |
3533 | case RTL_GIGA_MAC_VER_11: | |
3534 | case RTL_GIGA_MAC_VER_12: | |
3535 | case RTL_GIGA_MAC_VER_17: | |
3536 | case RTL_GIGA_MAC_VER_18: | |
3537 | case RTL_GIGA_MAC_VER_19: | |
3538 | case RTL_GIGA_MAC_VER_20: | |
3539 | case RTL_GIGA_MAC_VER_21: | |
3540 | case RTL_GIGA_MAC_VER_22: | |
3541 | case RTL_GIGA_MAC_VER_23: | |
3542 | case RTL_GIGA_MAC_VER_24: | |
3543 | case RTL_GIGA_MAC_VER_25: | |
3544 | case RTL_GIGA_MAC_VER_26: | |
3545 | case RTL_GIGA_MAC_VER_27: | |
3546 | case RTL_GIGA_MAC_VER_28: | |
3547 | case RTL_GIGA_MAC_VER_31: | |
3548 | rtl_writephy(tp, 0x0e, 0x0000); | |
3549 | break; | |
3550 | default: | |
3551 | break; | |
3552 | } | |
065c27c1 | 3553 | rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE); |
3554 | } | |
3555 | ||
3556 | static void r8168_phy_power_down(struct rtl8169_private *tp) | |
3557 | { | |
3558 | rtl_writephy(tp, 0x1f, 0x0000); | |
01dc7fec | 3559 | switch (tp->mac_version) { |
3560 | case RTL_GIGA_MAC_VER_32: | |
3561 | case RTL_GIGA_MAC_VER_33: | |
3562 | rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN); | |
3563 | break; | |
3564 | ||
3565 | case RTL_GIGA_MAC_VER_11: | |
3566 | case RTL_GIGA_MAC_VER_12: | |
3567 | case RTL_GIGA_MAC_VER_17: | |
3568 | case RTL_GIGA_MAC_VER_18: | |
3569 | case RTL_GIGA_MAC_VER_19: | |
3570 | case RTL_GIGA_MAC_VER_20: | |
3571 | case RTL_GIGA_MAC_VER_21: | |
3572 | case RTL_GIGA_MAC_VER_22: | |
3573 | case RTL_GIGA_MAC_VER_23: | |
3574 | case RTL_GIGA_MAC_VER_24: | |
3575 | case RTL_GIGA_MAC_VER_25: | |
3576 | case RTL_GIGA_MAC_VER_26: | |
3577 | case RTL_GIGA_MAC_VER_27: | |
3578 | case RTL_GIGA_MAC_VER_28: | |
3579 | case RTL_GIGA_MAC_VER_31: | |
3580 | rtl_writephy(tp, 0x0e, 0x0200); | |
3581 | default: | |
3582 | rtl_writephy(tp, MII_BMCR, BMCR_PDOWN); | |
3583 | break; | |
3584 | } | |
065c27c1 | 3585 | } |
3586 | ||
3587 | static void r8168_pll_power_down(struct rtl8169_private *tp) | |
3588 | { | |
3589 | void __iomem *ioaddr = tp->mmio_addr; | |
3590 | ||
cecb5fd7 FR |
3591 | if ((tp->mac_version == RTL_GIGA_MAC_VER_27 || |
3592 | tp->mac_version == RTL_GIGA_MAC_VER_28 || | |
3593 | tp->mac_version == RTL_GIGA_MAC_VER_31) && | |
4804b3b3 | 3594 | r8168dp_check_dash(tp)) { |
065c27c1 | 3595 | return; |
5d2e1957 | 3596 | } |
065c27c1 | 3597 | |
cecb5fd7 FR |
3598 | if ((tp->mac_version == RTL_GIGA_MAC_VER_23 || |
3599 | tp->mac_version == RTL_GIGA_MAC_VER_24) && | |
065c27c1 | 3600 | (RTL_R16(CPlusCmd) & ASF)) { |
3601 | return; | |
3602 | } | |
3603 | ||
01dc7fec | 3604 | if (tp->mac_version == RTL_GIGA_MAC_VER_32 || |
3605 | tp->mac_version == RTL_GIGA_MAC_VER_33) | |
3606 | rtl_ephy_write(ioaddr, 0x19, 0xff64); | |
3607 | ||
065c27c1 | 3608 | if (__rtl8169_get_wol(tp) & WAKE_ANY) { |
3609 | rtl_writephy(tp, 0x1f, 0x0000); | |
3610 | rtl_writephy(tp, MII_BMCR, 0x0000); | |
3611 | ||
d4ed95d7 | 3612 | if (tp->mac_version == RTL_GIGA_MAC_VER_32 || |
10663389 HW |
3613 | tp->mac_version == RTL_GIGA_MAC_VER_33 || |
3614 | tp->mac_version == RTL_GIGA_MAC_VER_34) | |
d4ed95d7 HW |
3615 | RTL_W32(RxConfig, RTL_R32(RxConfig) | AcceptBroadcast | |
3616 | AcceptMulticast | AcceptMyPhys); | |
065c27c1 | 3617 | return; |
3618 | } | |
3619 | ||
3620 | r8168_phy_power_down(tp); | |
3621 | ||
3622 | switch (tp->mac_version) { | |
3623 | case RTL_GIGA_MAC_VER_25: | |
3624 | case RTL_GIGA_MAC_VER_26: | |
5d2e1957 HW |
3625 | case RTL_GIGA_MAC_VER_27: |
3626 | case RTL_GIGA_MAC_VER_28: | |
4804b3b3 | 3627 | case RTL_GIGA_MAC_VER_31: |
01dc7fec | 3628 | case RTL_GIGA_MAC_VER_32: |
3629 | case RTL_GIGA_MAC_VER_33: | |
065c27c1 | 3630 | RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80); |
3631 | break; | |
3632 | } | |
3633 | } | |
3634 | ||
3635 | static void r8168_pll_power_up(struct rtl8169_private *tp) | |
3636 | { | |
3637 | void __iomem *ioaddr = tp->mmio_addr; | |
3638 | ||
cecb5fd7 FR |
3639 | if ((tp->mac_version == RTL_GIGA_MAC_VER_27 || |
3640 | tp->mac_version == RTL_GIGA_MAC_VER_28 || | |
3641 | tp->mac_version == RTL_GIGA_MAC_VER_31) && | |
4804b3b3 | 3642 | r8168dp_check_dash(tp)) { |
065c27c1 | 3643 | return; |
5d2e1957 | 3644 | } |
065c27c1 | 3645 | |
3646 | switch (tp->mac_version) { | |
3647 | case RTL_GIGA_MAC_VER_25: | |
3648 | case RTL_GIGA_MAC_VER_26: | |
5d2e1957 HW |
3649 | case RTL_GIGA_MAC_VER_27: |
3650 | case RTL_GIGA_MAC_VER_28: | |
4804b3b3 | 3651 | case RTL_GIGA_MAC_VER_31: |
01dc7fec | 3652 | case RTL_GIGA_MAC_VER_32: |
3653 | case RTL_GIGA_MAC_VER_33: | |
065c27c1 | 3654 | RTL_W8(PMCH, RTL_R8(PMCH) | 0x80); |
3655 | break; | |
3656 | } | |
3657 | ||
3658 | r8168_phy_power_up(tp); | |
3659 | } | |
3660 | ||
d58d46b5 FR |
3661 | static void rtl_generic_op(struct rtl8169_private *tp, |
3662 | void (*op)(struct rtl8169_private *)) | |
065c27c1 | 3663 | { |
3664 | if (op) | |
3665 | op(tp); | |
3666 | } | |
3667 | ||
3668 | static void rtl_pll_power_down(struct rtl8169_private *tp) | |
3669 | { | |
d58d46b5 | 3670 | rtl_generic_op(tp, tp->pll_power_ops.down); |
065c27c1 | 3671 | } |
3672 | ||
3673 | static void rtl_pll_power_up(struct rtl8169_private *tp) | |
3674 | { | |
d58d46b5 | 3675 | rtl_generic_op(tp, tp->pll_power_ops.up); |
065c27c1 | 3676 | } |
3677 | ||
3678 | static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp) | |
3679 | { | |
3680 | struct pll_power_ops *ops = &tp->pll_power_ops; | |
3681 | ||
3682 | switch (tp->mac_version) { | |
3683 | case RTL_GIGA_MAC_VER_07: | |
3684 | case RTL_GIGA_MAC_VER_08: | |
3685 | case RTL_GIGA_MAC_VER_09: | |
3686 | case RTL_GIGA_MAC_VER_10: | |
3687 | case RTL_GIGA_MAC_VER_16: | |
5a5e4443 HW |
3688 | case RTL_GIGA_MAC_VER_29: |
3689 | case RTL_GIGA_MAC_VER_30: | |
065c27c1 | 3690 | ops->down = r810x_pll_power_down; |
3691 | ops->up = r810x_pll_power_up; | |
3692 | break; | |
3693 | ||
3694 | case RTL_GIGA_MAC_VER_11: | |
3695 | case RTL_GIGA_MAC_VER_12: | |
3696 | case RTL_GIGA_MAC_VER_17: | |
3697 | case RTL_GIGA_MAC_VER_18: | |
3698 | case RTL_GIGA_MAC_VER_19: | |
3699 | case RTL_GIGA_MAC_VER_20: | |
3700 | case RTL_GIGA_MAC_VER_21: | |
3701 | case RTL_GIGA_MAC_VER_22: | |
3702 | case RTL_GIGA_MAC_VER_23: | |
3703 | case RTL_GIGA_MAC_VER_24: | |
3704 | case RTL_GIGA_MAC_VER_25: | |
3705 | case RTL_GIGA_MAC_VER_26: | |
3706 | case RTL_GIGA_MAC_VER_27: | |
e6de30d6 | 3707 | case RTL_GIGA_MAC_VER_28: |
4804b3b3 | 3708 | case RTL_GIGA_MAC_VER_31: |
01dc7fec | 3709 | case RTL_GIGA_MAC_VER_32: |
3710 | case RTL_GIGA_MAC_VER_33: | |
70090424 | 3711 | case RTL_GIGA_MAC_VER_34: |
c2218925 HW |
3712 | case RTL_GIGA_MAC_VER_35: |
3713 | case RTL_GIGA_MAC_VER_36: | |
065c27c1 | 3714 | ops->down = r8168_pll_power_down; |
3715 | ops->up = r8168_pll_power_up; | |
3716 | break; | |
3717 | ||
3718 | default: | |
3719 | ops->down = NULL; | |
3720 | ops->up = NULL; | |
3721 | break; | |
3722 | } | |
3723 | } | |
3724 | ||
e542a226 HW |
3725 | static void rtl_init_rxcfg(struct rtl8169_private *tp) |
3726 | { | |
3727 | void __iomem *ioaddr = tp->mmio_addr; | |
3728 | ||
3729 | switch (tp->mac_version) { | |
3730 | case RTL_GIGA_MAC_VER_01: | |
3731 | case RTL_GIGA_MAC_VER_02: | |
3732 | case RTL_GIGA_MAC_VER_03: | |
3733 | case RTL_GIGA_MAC_VER_04: | |
3734 | case RTL_GIGA_MAC_VER_05: | |
3735 | case RTL_GIGA_MAC_VER_06: | |
3736 | case RTL_GIGA_MAC_VER_10: | |
3737 | case RTL_GIGA_MAC_VER_11: | |
3738 | case RTL_GIGA_MAC_VER_12: | |
3739 | case RTL_GIGA_MAC_VER_13: | |
3740 | case RTL_GIGA_MAC_VER_14: | |
3741 | case RTL_GIGA_MAC_VER_15: | |
3742 | case RTL_GIGA_MAC_VER_16: | |
3743 | case RTL_GIGA_MAC_VER_17: | |
3744 | RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST); | |
3745 | break; | |
3746 | case RTL_GIGA_MAC_VER_18: | |
3747 | case RTL_GIGA_MAC_VER_19: | |
3748 | case RTL_GIGA_MAC_VER_20: | |
3749 | case RTL_GIGA_MAC_VER_21: | |
3750 | case RTL_GIGA_MAC_VER_22: | |
3751 | case RTL_GIGA_MAC_VER_23: | |
3752 | case RTL_GIGA_MAC_VER_24: | |
3753 | RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST); | |
3754 | break; | |
3755 | default: | |
3756 | RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST); | |
3757 | break; | |
3758 | } | |
3759 | } | |
3760 | ||
92fc43b4 HW |
3761 | static void rtl8169_init_ring_indexes(struct rtl8169_private *tp) |
3762 | { | |
3763 | tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0; | |
3764 | } | |
3765 | ||
d58d46b5 FR |
3766 | static void rtl_hw_jumbo_enable(struct rtl8169_private *tp) |
3767 | { | |
3768 | rtl_generic_op(tp, tp->jumbo_ops.enable); | |
3769 | } | |
3770 | ||
3771 | static void rtl_hw_jumbo_disable(struct rtl8169_private *tp) | |
3772 | { | |
3773 | rtl_generic_op(tp, tp->jumbo_ops.disable); | |
3774 | } | |
3775 | ||
3776 | static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp) | |
3777 | { | |
3778 | void __iomem *ioaddr = tp->mmio_addr; | |
3779 | ||
3780 | RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0); | |
3781 | RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1); | |
3782 | rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT); | |
3783 | } | |
3784 | ||
3785 | static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp) | |
3786 | { | |
3787 | void __iomem *ioaddr = tp->mmio_addr; | |
3788 | ||
3789 | RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0); | |
3790 | RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1); | |
3791 | rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
3792 | } | |
3793 | ||
3794 | static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp) | |
3795 | { | |
3796 | void __iomem *ioaddr = tp->mmio_addr; | |
3797 | ||
3798 | RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0); | |
3799 | } | |
3800 | ||
3801 | static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp) | |
3802 | { | |
3803 | void __iomem *ioaddr = tp->mmio_addr; | |
3804 | ||
3805 | RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0); | |
3806 | } | |
3807 | ||
3808 | static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp) | |
3809 | { | |
3810 | void __iomem *ioaddr = tp->mmio_addr; | |
3811 | struct pci_dev *pdev = tp->pci_dev; | |
3812 | ||
3813 | RTL_W8(MaxTxPacketSize, 0x3f); | |
3814 | RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0); | |
3815 | RTL_W8(Config4, RTL_R8(Config4) | 0x01); | |
3816 | pci_write_config_byte(pdev, 0x79, 0x20); | |
3817 | } | |
3818 | ||
3819 | static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp) | |
3820 | { | |
3821 | void __iomem *ioaddr = tp->mmio_addr; | |
3822 | struct pci_dev *pdev = tp->pci_dev; | |
3823 | ||
3824 | RTL_W8(MaxTxPacketSize, 0x0c); | |
3825 | RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0); | |
3826 | RTL_W8(Config4, RTL_R8(Config4) & ~0x01); | |
3827 | pci_write_config_byte(pdev, 0x79, 0x50); | |
3828 | } | |
3829 | ||
3830 | static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp) | |
3831 | { | |
3832 | rtl_tx_performance_tweak(tp->pci_dev, | |
3833 | (0x2 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN); | |
3834 | } | |
3835 | ||
3836 | static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp) | |
3837 | { | |
3838 | rtl_tx_performance_tweak(tp->pci_dev, | |
3839 | (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN); | |
3840 | } | |
3841 | ||
3842 | static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp) | |
3843 | { | |
3844 | void __iomem *ioaddr = tp->mmio_addr; | |
3845 | ||
3846 | r8168b_0_hw_jumbo_enable(tp); | |
3847 | ||
3848 | RTL_W8(Config4, RTL_R8(Config4) | (1 << 0)); | |
3849 | } | |
3850 | ||
3851 | static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp) | |
3852 | { | |
3853 | void __iomem *ioaddr = tp->mmio_addr; | |
3854 | ||
3855 | r8168b_0_hw_jumbo_disable(tp); | |
3856 | ||
3857 | RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0)); | |
3858 | } | |
3859 | ||
3860 | static void __devinit rtl_init_jumbo_ops(struct rtl8169_private *tp) | |
3861 | { | |
3862 | struct jumbo_ops *ops = &tp->jumbo_ops; | |
3863 | ||
3864 | switch (tp->mac_version) { | |
3865 | case RTL_GIGA_MAC_VER_11: | |
3866 | ops->disable = r8168b_0_hw_jumbo_disable; | |
3867 | ops->enable = r8168b_0_hw_jumbo_enable; | |
3868 | break; | |
3869 | case RTL_GIGA_MAC_VER_12: | |
3870 | case RTL_GIGA_MAC_VER_17: | |
3871 | ops->disable = r8168b_1_hw_jumbo_disable; | |
3872 | ops->enable = r8168b_1_hw_jumbo_enable; | |
3873 | break; | |
3874 | case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */ | |
3875 | case RTL_GIGA_MAC_VER_19: | |
3876 | case RTL_GIGA_MAC_VER_20: | |
3877 | case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */ | |
3878 | case RTL_GIGA_MAC_VER_22: | |
3879 | case RTL_GIGA_MAC_VER_23: | |
3880 | case RTL_GIGA_MAC_VER_24: | |
3881 | case RTL_GIGA_MAC_VER_25: | |
3882 | case RTL_GIGA_MAC_VER_26: | |
3883 | ops->disable = r8168c_hw_jumbo_disable; | |
3884 | ops->enable = r8168c_hw_jumbo_enable; | |
3885 | break; | |
3886 | case RTL_GIGA_MAC_VER_27: | |
3887 | case RTL_GIGA_MAC_VER_28: | |
3888 | ops->disable = r8168dp_hw_jumbo_disable; | |
3889 | ops->enable = r8168dp_hw_jumbo_enable; | |
3890 | break; | |
3891 | case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */ | |
3892 | case RTL_GIGA_MAC_VER_32: | |
3893 | case RTL_GIGA_MAC_VER_33: | |
3894 | case RTL_GIGA_MAC_VER_34: | |
3895 | ops->disable = r8168e_hw_jumbo_disable; | |
3896 | ops->enable = r8168e_hw_jumbo_enable; | |
3897 | break; | |
3898 | ||
3899 | /* | |
3900 | * No action needed for jumbo frames with 8169. | |
3901 | * No jumbo for 810x at all. | |
3902 | */ | |
3903 | default: | |
3904 | ops->disable = NULL; | |
3905 | ops->enable = NULL; | |
3906 | break; | |
3907 | } | |
3908 | } | |
3909 | ||
6f43adc8 FR |
3910 | static void rtl_hw_reset(struct rtl8169_private *tp) |
3911 | { | |
3912 | void __iomem *ioaddr = tp->mmio_addr; | |
3913 | int i; | |
3914 | ||
3915 | /* Soft reset the chip. */ | |
3916 | RTL_W8(ChipCmd, CmdReset); | |
3917 | ||
3918 | /* Check that the chip has finished the reset. */ | |
3919 | for (i = 0; i < 100; i++) { | |
3920 | if ((RTL_R8(ChipCmd) & CmdReset) == 0) | |
3921 | break; | |
92fc43b4 | 3922 | udelay(100); |
6f43adc8 | 3923 | } |
92fc43b4 HW |
3924 | |
3925 | rtl8169_init_ring_indexes(tp); | |
6f43adc8 FR |
3926 | } |
3927 | ||
1da177e4 | 3928 | static int __devinit |
4ff96fa6 | 3929 | rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
1da177e4 | 3930 | { |
0e485150 FR |
3931 | const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data; |
3932 | const unsigned int region = cfg->region; | |
1da177e4 | 3933 | struct rtl8169_private *tp; |
ccdffb9a | 3934 | struct mii_if_info *mii; |
4ff96fa6 FR |
3935 | struct net_device *dev; |
3936 | void __iomem *ioaddr; | |
2b7b4318 | 3937 | int chipset, i; |
07d3f51f | 3938 | int rc; |
1da177e4 | 3939 | |
4ff96fa6 FR |
3940 | if (netif_msg_drv(&debug)) { |
3941 | printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n", | |
3942 | MODULENAME, RTL8169_VERSION); | |
3943 | } | |
1da177e4 | 3944 | |
1da177e4 | 3945 | dev = alloc_etherdev(sizeof (*tp)); |
4ff96fa6 | 3946 | if (!dev) { |
b57b7e5a | 3947 | if (netif_msg_drv(&debug)) |
9b91cf9d | 3948 | dev_err(&pdev->dev, "unable to alloc new ethernet\n"); |
4ff96fa6 FR |
3949 | rc = -ENOMEM; |
3950 | goto out; | |
1da177e4 LT |
3951 | } |
3952 | ||
1da177e4 | 3953 | SET_NETDEV_DEV(dev, &pdev->dev); |
8b4ab28d | 3954 | dev->netdev_ops = &rtl8169_netdev_ops; |
1da177e4 | 3955 | tp = netdev_priv(dev); |
c4028958 | 3956 | tp->dev = dev; |
21e197f2 | 3957 | tp->pci_dev = pdev; |
b57b7e5a | 3958 | tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT); |
1da177e4 | 3959 | |
ccdffb9a FR |
3960 | mii = &tp->mii; |
3961 | mii->dev = dev; | |
3962 | mii->mdio_read = rtl_mdio_read; | |
3963 | mii->mdio_write = rtl_mdio_write; | |
3964 | mii->phy_id_mask = 0x1f; | |
3965 | mii->reg_num_mask = 0x1f; | |
3966 | mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII); | |
3967 | ||
ba04c7c9 SG |
3968 | /* disable ASPM completely as that cause random device stop working |
3969 | * problems as well as full system hangs for some PCIe devices users */ | |
3970 | pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 | | |
3971 | PCIE_LINK_STATE_CLKPM); | |
3972 | ||
1da177e4 LT |
3973 | /* enable device (incl. PCI PM wakeup and hotplug setup) */ |
3974 | rc = pci_enable_device(pdev); | |
b57b7e5a | 3975 | if (rc < 0) { |
bf82c189 | 3976 | netif_err(tp, probe, dev, "enable failure\n"); |
4ff96fa6 | 3977 | goto err_out_free_dev_1; |
1da177e4 LT |
3978 | } |
3979 | ||
87aeec76 | 3980 | if (pci_set_mwi(pdev) < 0) |
3981 | netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n"); | |
1da177e4 | 3982 | |
1da177e4 | 3983 | /* make sure PCI base addr 1 is MMIO */ |
bcf0bf90 | 3984 | if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) { |
bf82c189 JP |
3985 | netif_err(tp, probe, dev, |
3986 | "region #%d not an MMIO resource, aborting\n", | |
3987 | region); | |
1da177e4 | 3988 | rc = -ENODEV; |
87aeec76 | 3989 | goto err_out_mwi_2; |
1da177e4 | 3990 | } |
4ff96fa6 | 3991 | |
1da177e4 | 3992 | /* check for weird/broken PCI region reporting */ |
bcf0bf90 | 3993 | if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) { |
bf82c189 JP |
3994 | netif_err(tp, probe, dev, |
3995 | "Invalid PCI region size(s), aborting\n"); | |
1da177e4 | 3996 | rc = -ENODEV; |
87aeec76 | 3997 | goto err_out_mwi_2; |
1da177e4 LT |
3998 | } |
3999 | ||
4000 | rc = pci_request_regions(pdev, MODULENAME); | |
b57b7e5a | 4001 | if (rc < 0) { |
bf82c189 | 4002 | netif_err(tp, probe, dev, "could not request regions\n"); |
87aeec76 | 4003 | goto err_out_mwi_2; |
1da177e4 LT |
4004 | } |
4005 | ||
d24e9aaf | 4006 | tp->cp_cmd = RxChkSum; |
1da177e4 LT |
4007 | |
4008 | if ((sizeof(dma_addr_t) > 4) && | |
4300e8c7 | 4009 | !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) { |
1da177e4 LT |
4010 | tp->cp_cmd |= PCIDAC; |
4011 | dev->features |= NETIF_F_HIGHDMA; | |
4012 | } else { | |
284901a9 | 4013 | rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
1da177e4 | 4014 | if (rc < 0) { |
bf82c189 | 4015 | netif_err(tp, probe, dev, "DMA configuration failed\n"); |
87aeec76 | 4016 | goto err_out_free_res_3; |
1da177e4 LT |
4017 | } |
4018 | } | |
4019 | ||
1da177e4 | 4020 | /* ioremap MMIO region */ |
bcf0bf90 | 4021 | ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE); |
4ff96fa6 | 4022 | if (!ioaddr) { |
bf82c189 | 4023 | netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n"); |
1da177e4 | 4024 | rc = -EIO; |
87aeec76 | 4025 | goto err_out_free_res_3; |
1da177e4 | 4026 | } |
6f43adc8 | 4027 | tp->mmio_addr = ioaddr; |
1da177e4 | 4028 | |
e44daade JM |
4029 | if (!pci_is_pcie(pdev)) |
4030 | netif_info(tp, probe, dev, "not PCI Express\n"); | |
4300e8c7 | 4031 | |
e542a226 HW |
4032 | /* Identify chip attached to board */ |
4033 | rtl8169_get_mac_version(tp, dev, cfg->default_ver); | |
4034 | ||
4035 | rtl_init_rxcfg(tp); | |
4036 | ||
d78ad8cb | 4037 | RTL_W16(IntrMask, 0x0000); |
1da177e4 | 4038 | |
6f43adc8 | 4039 | rtl_hw_reset(tp); |
1da177e4 | 4040 | |
d78ad8cb KW |
4041 | RTL_W16(IntrStatus, 0xffff); |
4042 | ||
ca52efd5 | 4043 | pci_set_master(pdev); |
4044 | ||
7a8fc77b FR |
4045 | /* |
4046 | * Pretend we are using VLANs; This bypasses a nasty bug where | |
4047 | * Interrupts stop flowing on high load on 8110SCd controllers. | |
4048 | */ | |
4049 | if (tp->mac_version == RTL_GIGA_MAC_VER_05) | |
4050 | tp->cp_cmd |= RxVlan; | |
4051 | ||
c0e45c1c | 4052 | rtl_init_mdio_ops(tp); |
065c27c1 | 4053 | rtl_init_pll_power_ops(tp); |
d58d46b5 | 4054 | rtl_init_jumbo_ops(tp); |
c0e45c1c | 4055 | |
1da177e4 | 4056 | rtl8169_print_mac_version(tp); |
1da177e4 | 4057 | |
85bffe6c FR |
4058 | chipset = tp->mac_version; |
4059 | tp->txd_version = rtl_chip_infos[chipset].txd_version; | |
1da177e4 | 4060 | |
5d06a99f FR |
4061 | RTL_W8(Cfg9346, Cfg9346_Unlock); |
4062 | RTL_W8(Config1, RTL_R8(Config1) | PMEnable); | |
4063 | RTL_W8(Config5, RTL_R8(Config5) & PMEStatus); | |
20037fa4 BP |
4064 | if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0) |
4065 | tp->features |= RTL_FEATURE_WOL; | |
4066 | if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0) | |
4067 | tp->features |= RTL_FEATURE_WOL; | |
fbac58fc | 4068 | tp->features |= rtl_try_msi(pdev, ioaddr, cfg); |
5d06a99f FR |
4069 | RTL_W8(Cfg9346, Cfg9346_Lock); |
4070 | ||
2544bfc0 | 4071 | if (rtl_tbi_enabled(tp)) { |
1da177e4 LT |
4072 | tp->set_speed = rtl8169_set_speed_tbi; |
4073 | tp->get_settings = rtl8169_gset_tbi; | |
4074 | tp->phy_reset_enable = rtl8169_tbi_reset_enable; | |
4075 | tp->phy_reset_pending = rtl8169_tbi_reset_pending; | |
4076 | tp->link_ok = rtl8169_tbi_link_ok; | |
8b4ab28d | 4077 | tp->do_ioctl = rtl_tbi_ioctl; |
1da177e4 LT |
4078 | } else { |
4079 | tp->set_speed = rtl8169_set_speed_xmii; | |
4080 | tp->get_settings = rtl8169_gset_xmii; | |
4081 | tp->phy_reset_enable = rtl8169_xmii_reset_enable; | |
4082 | tp->phy_reset_pending = rtl8169_xmii_reset_pending; | |
4083 | tp->link_ok = rtl8169_xmii_link_ok; | |
8b4ab28d | 4084 | tp->do_ioctl = rtl_xmii_ioctl; |
1da177e4 LT |
4085 | } |
4086 | ||
df58ef51 FR |
4087 | spin_lock_init(&tp->lock); |
4088 | ||
7bf6bf48 | 4089 | /* Get MAC address */ |
1da177e4 LT |
4090 | for (i = 0; i < MAC_ADDR_LEN; i++) |
4091 | dev->dev_addr[i] = RTL_R8(MAC0 + i); | |
6d6525b7 | 4092 | memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); |
1da177e4 | 4093 | |
1da177e4 | 4094 | SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops); |
1da177e4 LT |
4095 | dev->watchdog_timeo = RTL8169_TX_TIMEOUT; |
4096 | dev->irq = pdev->irq; | |
4097 | dev->base_addr = (unsigned long) ioaddr; | |
1da177e4 | 4098 | |
bea3348e | 4099 | netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT); |
1da177e4 | 4100 | |
350fb32a MM |
4101 | /* don't enable SG, IP_CSUM and TSO by default - it might not work |
4102 | * properly for all devices */ | |
4103 | dev->features |= NETIF_F_RXCSUM | | |
4104 | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; | |
4105 | ||
4106 | dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | | |
4107 | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; | |
4108 | dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | | |
4109 | NETIF_F_HIGHDMA; | |
4110 | ||
4111 | if (tp->mac_version == RTL_GIGA_MAC_VER_05) | |
4112 | /* 8110SCd requires hardware Rx VLAN - disallow toggling */ | |
4113 | dev->hw_features &= ~NETIF_F_HW_VLAN_RX; | |
1da177e4 LT |
4114 | |
4115 | tp->intr_mask = 0xffff; | |
0e485150 FR |
4116 | tp->hw_start = cfg->hw_start; |
4117 | tp->intr_event = cfg->intr_event; | |
4118 | tp->napi_event = cfg->napi_event; | |
1da177e4 | 4119 | |
e03f33af FR |
4120 | tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ? |
4121 | ~(RxBOVF | RxFOVF) : ~0; | |
4122 | ||
2efa53f3 FR |
4123 | init_timer(&tp->timer); |
4124 | tp->timer.data = (unsigned long) dev; | |
4125 | tp->timer.function = rtl8169_phy_timer; | |
4126 | ||
b6ffd97f | 4127 | tp->rtl_fw = RTL_FIRMWARE_UNKNOWN; |
953a12cc | 4128 | |
1da177e4 | 4129 | rc = register_netdev(dev); |
4ff96fa6 | 4130 | if (rc < 0) |
87aeec76 | 4131 | goto err_out_msi_4; |
1da177e4 LT |
4132 | |
4133 | pci_set_drvdata(pdev, dev); | |
4134 | ||
bf82c189 | 4135 | netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n", |
85bffe6c | 4136 | rtl_chip_infos[chipset].name, dev->base_addr, dev->dev_addr, |
bf82c189 | 4137 | (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq); |
d58d46b5 FR |
4138 | if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) { |
4139 | netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, " | |
4140 | "tx checksumming: %s]\n", | |
4141 | rtl_chip_infos[chipset].jumbo_max, | |
4142 | rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko"); | |
4143 | } | |
1da177e4 | 4144 | |
cecb5fd7 FR |
4145 | if (tp->mac_version == RTL_GIGA_MAC_VER_27 || |
4146 | tp->mac_version == RTL_GIGA_MAC_VER_28 || | |
4147 | tp->mac_version == RTL_GIGA_MAC_VER_31) { | |
b646d900 | 4148 | rtl8168_driver_start(tp); |
e6de30d6 | 4149 | } |
b646d900 | 4150 | |
8b76ab39 | 4151 | device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL); |
1da177e4 | 4152 | |
f3ec4f87 AS |
4153 | if (pci_dev_run_wake(pdev)) |
4154 | pm_runtime_put_noidle(&pdev->dev); | |
e1759441 | 4155 | |
0d672e9f IV |
4156 | netif_carrier_off(dev); |
4157 | ||
4ff96fa6 FR |
4158 | out: |
4159 | return rc; | |
1da177e4 | 4160 | |
87aeec76 | 4161 | err_out_msi_4: |
fbac58fc | 4162 | rtl_disable_msi(pdev, tp); |
4ff96fa6 | 4163 | iounmap(ioaddr); |
87aeec76 | 4164 | err_out_free_res_3: |
4ff96fa6 | 4165 | pci_release_regions(pdev); |
87aeec76 | 4166 | err_out_mwi_2: |
4ff96fa6 | 4167 | pci_clear_mwi(pdev); |
4ff96fa6 FR |
4168 | pci_disable_device(pdev); |
4169 | err_out_free_dev_1: | |
4170 | free_netdev(dev); | |
4171 | goto out; | |
1da177e4 LT |
4172 | } |
4173 | ||
07d3f51f | 4174 | static void __devexit rtl8169_remove_one(struct pci_dev *pdev) |
1da177e4 LT |
4175 | { |
4176 | struct net_device *dev = pci_get_drvdata(pdev); | |
4177 | struct rtl8169_private *tp = netdev_priv(dev); | |
4178 | ||
cecb5fd7 FR |
4179 | if (tp->mac_version == RTL_GIGA_MAC_VER_27 || |
4180 | tp->mac_version == RTL_GIGA_MAC_VER_28 || | |
4181 | tp->mac_version == RTL_GIGA_MAC_VER_31) { | |
b646d900 | 4182 | rtl8168_driver_stop(tp); |
e6de30d6 | 4183 | } |
b646d900 | 4184 | |
23f333a2 | 4185 | cancel_delayed_work_sync(&tp->task); |
eb2a021c | 4186 | |
1da177e4 | 4187 | unregister_netdev(dev); |
cc098dc7 | 4188 | |
953a12cc FR |
4189 | rtl_release_firmware(tp); |
4190 | ||
f3ec4f87 AS |
4191 | if (pci_dev_run_wake(pdev)) |
4192 | pm_runtime_get_noresume(&pdev->dev); | |
e1759441 | 4193 | |
cc098dc7 IV |
4194 | /* restore original MAC address */ |
4195 | rtl_rar_set(tp, dev->perm_addr); | |
4196 | ||
fbac58fc | 4197 | rtl_disable_msi(pdev, tp); |
1da177e4 LT |
4198 | rtl8169_release_board(pdev, dev, tp->mmio_addr); |
4199 | pci_set_drvdata(pdev, NULL); | |
4200 | } | |
4201 | ||
b6ffd97f | 4202 | static void rtl_request_uncached_firmware(struct rtl8169_private *tp) |
953a12cc | 4203 | { |
b6ffd97f FR |
4204 | struct rtl_fw *rtl_fw; |
4205 | const char *name; | |
4206 | int rc = -ENOMEM; | |
953a12cc | 4207 | |
b6ffd97f FR |
4208 | name = rtl_lookup_firmware_name(tp); |
4209 | if (!name) | |
4210 | goto out_no_firmware; | |
953a12cc | 4211 | |
b6ffd97f FR |
4212 | rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL); |
4213 | if (!rtl_fw) | |
4214 | goto err_warn; | |
31bd204f | 4215 | |
b6ffd97f FR |
4216 | rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev); |
4217 | if (rc < 0) | |
4218 | goto err_free; | |
4219 | ||
fd112f2e FR |
4220 | rc = rtl_check_firmware(tp, rtl_fw); |
4221 | if (rc < 0) | |
4222 | goto err_release_firmware; | |
4223 | ||
b6ffd97f FR |
4224 | tp->rtl_fw = rtl_fw; |
4225 | out: | |
4226 | return; | |
4227 | ||
fd112f2e FR |
4228 | err_release_firmware: |
4229 | release_firmware(rtl_fw->fw); | |
b6ffd97f FR |
4230 | err_free: |
4231 | kfree(rtl_fw); | |
4232 | err_warn: | |
4233 | netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n", | |
4234 | name, rc); | |
4235 | out_no_firmware: | |
4236 | tp->rtl_fw = NULL; | |
4237 | goto out; | |
4238 | } | |
4239 | ||
4240 | static void rtl_request_firmware(struct rtl8169_private *tp) | |
4241 | { | |
4242 | if (IS_ERR(tp->rtl_fw)) | |
4243 | rtl_request_uncached_firmware(tp); | |
953a12cc FR |
4244 | } |
4245 | ||
1da177e4 LT |
4246 | static int rtl8169_open(struct net_device *dev) |
4247 | { | |
4248 | struct rtl8169_private *tp = netdev_priv(dev); | |
eee3a96c | 4249 | void __iomem *ioaddr = tp->mmio_addr; |
1da177e4 | 4250 | struct pci_dev *pdev = tp->pci_dev; |
99f252b0 | 4251 | int retval = -ENOMEM; |
1da177e4 | 4252 | |
e1759441 | 4253 | pm_runtime_get_sync(&pdev->dev); |
1da177e4 | 4254 | |
1da177e4 LT |
4255 | /* |
4256 | * Rx and Tx desscriptors needs 256 bytes alignment. | |
82553bb6 | 4257 | * dma_alloc_coherent provides more. |
1da177e4 | 4258 | */ |
82553bb6 SG |
4259 | tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES, |
4260 | &tp->TxPhyAddr, GFP_KERNEL); | |
1da177e4 | 4261 | if (!tp->TxDescArray) |
e1759441 | 4262 | goto err_pm_runtime_put; |
1da177e4 | 4263 | |
82553bb6 SG |
4264 | tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES, |
4265 | &tp->RxPhyAddr, GFP_KERNEL); | |
1da177e4 | 4266 | if (!tp->RxDescArray) |
99f252b0 | 4267 | goto err_free_tx_0; |
1da177e4 LT |
4268 | |
4269 | retval = rtl8169_init_ring(dev); | |
4270 | if (retval < 0) | |
99f252b0 | 4271 | goto err_free_rx_1; |
1da177e4 | 4272 | |
c4028958 | 4273 | INIT_DELAYED_WORK(&tp->task, NULL); |
1da177e4 | 4274 | |
99f252b0 FR |
4275 | smp_mb(); |
4276 | ||
953a12cc FR |
4277 | rtl_request_firmware(tp); |
4278 | ||
fbac58fc FR |
4279 | retval = request_irq(dev->irq, rtl8169_interrupt, |
4280 | (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED, | |
99f252b0 FR |
4281 | dev->name, dev); |
4282 | if (retval < 0) | |
953a12cc | 4283 | goto err_release_fw_2; |
99f252b0 | 4284 | |
bea3348e | 4285 | napi_enable(&tp->napi); |
bea3348e | 4286 | |
eee3a96c | 4287 | rtl8169_init_phy(dev, tp); |
4288 | ||
350fb32a | 4289 | rtl8169_set_features(dev, dev->features); |
eee3a96c | 4290 | |
065c27c1 | 4291 | rtl_pll_power_up(tp); |
4292 | ||
07ce4064 | 4293 | rtl_hw_start(dev); |
1da177e4 | 4294 | |
e1759441 RW |
4295 | tp->saved_wolopts = 0; |
4296 | pm_runtime_put_noidle(&pdev->dev); | |
4297 | ||
eee3a96c | 4298 | rtl8169_check_link_status(dev, tp, ioaddr); |
1da177e4 LT |
4299 | out: |
4300 | return retval; | |
4301 | ||
953a12cc FR |
4302 | err_release_fw_2: |
4303 | rtl_release_firmware(tp); | |
99f252b0 FR |
4304 | rtl8169_rx_clear(tp); |
4305 | err_free_rx_1: | |
82553bb6 SG |
4306 | dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, |
4307 | tp->RxPhyAddr); | |
e1759441 | 4308 | tp->RxDescArray = NULL; |
99f252b0 | 4309 | err_free_tx_0: |
82553bb6 SG |
4310 | dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, |
4311 | tp->TxPhyAddr); | |
e1759441 RW |
4312 | tp->TxDescArray = NULL; |
4313 | err_pm_runtime_put: | |
4314 | pm_runtime_put_noidle(&pdev->dev); | |
1da177e4 LT |
4315 | goto out; |
4316 | } | |
4317 | ||
92fc43b4 HW |
4318 | static void rtl_rx_close(struct rtl8169_private *tp) |
4319 | { | |
4320 | void __iomem *ioaddr = tp->mmio_addr; | |
92fc43b4 | 4321 | |
1687b566 | 4322 | RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK); |
92fc43b4 HW |
4323 | } |
4324 | ||
e6de30d6 | 4325 | static void rtl8169_hw_reset(struct rtl8169_private *tp) |
1da177e4 | 4326 | { |
e6de30d6 | 4327 | void __iomem *ioaddr = tp->mmio_addr; |
4328 | ||
1da177e4 LT |
4329 | /* Disable interrupts */ |
4330 | rtl8169_irq_mask_and_ack(ioaddr); | |
4331 | ||
92fc43b4 HW |
4332 | rtl_rx_close(tp); |
4333 | ||
5d2e1957 | 4334 | if (tp->mac_version == RTL_GIGA_MAC_VER_27 || |
4804b3b3 | 4335 | tp->mac_version == RTL_GIGA_MAC_VER_28 || |
4336 | tp->mac_version == RTL_GIGA_MAC_VER_31) { | |
e6de30d6 | 4337 | while (RTL_R8(TxPoll) & NPQ) |
4338 | udelay(20); | |
c2218925 HW |
4339 | } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 || |
4340 | tp->mac_version == RTL_GIGA_MAC_VER_35 || | |
4341 | tp->mac_version == RTL_GIGA_MAC_VER_36) { | |
c2b0c1e7 | 4342 | RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq); |
70090424 HW |
4343 | while (!(RTL_R32(TxConfig) & TXCFG_EMPTY)) |
4344 | udelay(100); | |
92fc43b4 HW |
4345 | } else { |
4346 | RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq); | |
4347 | udelay(100); | |
e6de30d6 | 4348 | } |
4349 | ||
92fc43b4 | 4350 | rtl_hw_reset(tp); |
1da177e4 LT |
4351 | } |
4352 | ||
7f796d83 | 4353 | static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp) |
9cb427b6 FR |
4354 | { |
4355 | void __iomem *ioaddr = tp->mmio_addr; | |
9cb427b6 FR |
4356 | |
4357 | /* Set DMA burst size and Interframe Gap Time */ | |
4358 | RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) | | |
4359 | (InterFrameGap << TxInterFrameGapShift)); | |
4360 | } | |
4361 | ||
07ce4064 | 4362 | static void rtl_hw_start(struct net_device *dev) |
1da177e4 LT |
4363 | { |
4364 | struct rtl8169_private *tp = netdev_priv(dev); | |
1da177e4 | 4365 | |
07ce4064 FR |
4366 | tp->hw_start(dev); |
4367 | ||
07ce4064 FR |
4368 | netif_start_queue(dev); |
4369 | } | |
4370 | ||
7f796d83 FR |
4371 | static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp, |
4372 | void __iomem *ioaddr) | |
4373 | { | |
4374 | /* | |
4375 | * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh | |
4376 | * register to be written before TxDescAddrLow to work. | |
4377 | * Switching from MMIO to I/O access fixes the issue as well. | |
4378 | */ | |
4379 | RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32); | |
284901a9 | 4380 | RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32)); |
7f796d83 | 4381 | RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32); |
284901a9 | 4382 | RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32)); |
7f796d83 FR |
4383 | } |
4384 | ||
4385 | static u16 rtl_rw_cpluscmd(void __iomem *ioaddr) | |
4386 | { | |
4387 | u16 cmd; | |
4388 | ||
4389 | cmd = RTL_R16(CPlusCmd); | |
4390 | RTL_W16(CPlusCmd, cmd); | |
4391 | return cmd; | |
4392 | } | |
4393 | ||
fdd7b4c3 | 4394 | static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz) |
7f796d83 FR |
4395 | { |
4396 | /* Low hurts. Let's disable the filtering. */ | |
207d6e87 | 4397 | RTL_W16(RxMaxSize, rx_buf_sz + 1); |
7f796d83 FR |
4398 | } |
4399 | ||
6dccd16b FR |
4400 | static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version) |
4401 | { | |
3744100e | 4402 | static const struct rtl_cfg2_info { |
6dccd16b FR |
4403 | u32 mac_version; |
4404 | u32 clk; | |
4405 | u32 val; | |
4406 | } cfg2_info [] = { | |
4407 | { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd | |
4408 | { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff }, | |
4409 | { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe | |
4410 | { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff } | |
3744100e FR |
4411 | }; |
4412 | const struct rtl_cfg2_info *p = cfg2_info; | |
6dccd16b FR |
4413 | unsigned int i; |
4414 | u32 clk; | |
4415 | ||
4416 | clk = RTL_R8(Config2) & PCI_Clock_66MHz; | |
cadf1855 | 4417 | for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) { |
6dccd16b FR |
4418 | if ((p->mac_version == mac_version) && (p->clk == clk)) { |
4419 | RTL_W32(0x7c, p->val); | |
4420 | break; | |
4421 | } | |
4422 | } | |
4423 | } | |
4424 | ||
07ce4064 FR |
4425 | static void rtl_hw_start_8169(struct net_device *dev) |
4426 | { | |
4427 | struct rtl8169_private *tp = netdev_priv(dev); | |
4428 | void __iomem *ioaddr = tp->mmio_addr; | |
4429 | struct pci_dev *pdev = tp->pci_dev; | |
07ce4064 | 4430 | |
9cb427b6 FR |
4431 | if (tp->mac_version == RTL_GIGA_MAC_VER_05) { |
4432 | RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW); | |
4433 | pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08); | |
4434 | } | |
4435 | ||
1da177e4 | 4436 | RTL_W8(Cfg9346, Cfg9346_Unlock); |
cecb5fd7 FR |
4437 | if (tp->mac_version == RTL_GIGA_MAC_VER_01 || |
4438 | tp->mac_version == RTL_GIGA_MAC_VER_02 || | |
4439 | tp->mac_version == RTL_GIGA_MAC_VER_03 || | |
4440 | tp->mac_version == RTL_GIGA_MAC_VER_04) | |
9cb427b6 FR |
4441 | RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); |
4442 | ||
e542a226 HW |
4443 | rtl_init_rxcfg(tp); |
4444 | ||
f0298f81 | 4445 | RTL_W8(EarlyTxThres, NoEarlyTx); |
1da177e4 | 4446 | |
6f0333b8 | 4447 | rtl_set_rx_max_size(ioaddr, rx_buf_sz); |
1da177e4 | 4448 | |
cecb5fd7 FR |
4449 | if (tp->mac_version == RTL_GIGA_MAC_VER_01 || |
4450 | tp->mac_version == RTL_GIGA_MAC_VER_02 || | |
4451 | tp->mac_version == RTL_GIGA_MAC_VER_03 || | |
4452 | tp->mac_version == RTL_GIGA_MAC_VER_04) | |
c946b304 | 4453 | rtl_set_rx_tx_config_registers(tp); |
1da177e4 | 4454 | |
7f796d83 | 4455 | tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW; |
1da177e4 | 4456 | |
cecb5fd7 FR |
4457 | if (tp->mac_version == RTL_GIGA_MAC_VER_02 || |
4458 | tp->mac_version == RTL_GIGA_MAC_VER_03) { | |
06fa7358 | 4459 | dprintk("Set MAC Reg C+CR Offset 0xE0. " |
1da177e4 | 4460 | "Bit-3 and bit-14 MUST be 1\n"); |
bcf0bf90 | 4461 | tp->cp_cmd |= (1 << 14); |
1da177e4 LT |
4462 | } |
4463 | ||
bcf0bf90 FR |
4464 | RTL_W16(CPlusCmd, tp->cp_cmd); |
4465 | ||
6dccd16b FR |
4466 | rtl8169_set_magic_reg(ioaddr, tp->mac_version); |
4467 | ||
1da177e4 LT |
4468 | /* |
4469 | * Undocumented corner. Supposedly: | |
4470 | * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets | |
4471 | */ | |
4472 | RTL_W16(IntrMitigate, 0x0000); | |
4473 | ||
7f796d83 | 4474 | rtl_set_rx_tx_desc_registers(tp, ioaddr); |
9cb427b6 | 4475 | |
cecb5fd7 FR |
4476 | if (tp->mac_version != RTL_GIGA_MAC_VER_01 && |
4477 | tp->mac_version != RTL_GIGA_MAC_VER_02 && | |
4478 | tp->mac_version != RTL_GIGA_MAC_VER_03 && | |
4479 | tp->mac_version != RTL_GIGA_MAC_VER_04) { | |
c946b304 FR |
4480 | RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); |
4481 | rtl_set_rx_tx_config_registers(tp); | |
4482 | } | |
4483 | ||
1da177e4 | 4484 | RTL_W8(Cfg9346, Cfg9346_Lock); |
b518fa8e FR |
4485 | |
4486 | /* Initially a 10 us delay. Turned it into a PCI commit. - FR */ | |
4487 | RTL_R8(IntrMask); | |
1da177e4 LT |
4488 | |
4489 | RTL_W32(RxMissed, 0); | |
4490 | ||
07ce4064 | 4491 | rtl_set_rx_mode(dev); |
1da177e4 LT |
4492 | |
4493 | /* no early-rx interrupts */ | |
4494 | RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000); | |
6dccd16b FR |
4495 | |
4496 | /* Enable all known interrupts by setting the interrupt mask. */ | |
0e485150 | 4497 | RTL_W16(IntrMask, tp->intr_event); |
07ce4064 | 4498 | } |
1da177e4 | 4499 | |
650e8d5d | 4500 | static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits) |
dacf8154 FR |
4501 | { |
4502 | u32 csi; | |
4503 | ||
4504 | csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff; | |
650e8d5d | 4505 | rtl_csi_write(ioaddr, 0x070c, csi | bits); |
4506 | } | |
4507 | ||
e6de30d6 | 4508 | static void rtl_csi_access_enable_1(void __iomem *ioaddr) |
4509 | { | |
4510 | rtl_csi_access_enable(ioaddr, 0x17000000); | |
4511 | } | |
4512 | ||
650e8d5d | 4513 | static void rtl_csi_access_enable_2(void __iomem *ioaddr) |
4514 | { | |
4515 | rtl_csi_access_enable(ioaddr, 0x27000000); | |
dacf8154 FR |
4516 | } |
4517 | ||
4518 | struct ephy_info { | |
4519 | unsigned int offset; | |
4520 | u16 mask; | |
4521 | u16 bits; | |
4522 | }; | |
4523 | ||
350f7596 | 4524 | static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len) |
dacf8154 FR |
4525 | { |
4526 | u16 w; | |
4527 | ||
4528 | while (len-- > 0) { | |
4529 | w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits; | |
4530 | rtl_ephy_write(ioaddr, e->offset, w); | |
4531 | e++; | |
4532 | } | |
4533 | } | |
4534 | ||
b726e493 FR |
4535 | static void rtl_disable_clock_request(struct pci_dev *pdev) |
4536 | { | |
e44daade | 4537 | int cap = pci_pcie_cap(pdev); |
b726e493 FR |
4538 | |
4539 | if (cap) { | |
4540 | u16 ctl; | |
4541 | ||
4542 | pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl); | |
4543 | ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN; | |
4544 | pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl); | |
4545 | } | |
4546 | } | |
4547 | ||
e6de30d6 | 4548 | static void rtl_enable_clock_request(struct pci_dev *pdev) |
4549 | { | |
e44daade | 4550 | int cap = pci_pcie_cap(pdev); |
e6de30d6 | 4551 | |
4552 | if (cap) { | |
4553 | u16 ctl; | |
4554 | ||
4555 | pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl); | |
4556 | ctl |= PCI_EXP_LNKCTL_CLKREQ_EN; | |
4557 | pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl); | |
4558 | } | |
4559 | } | |
4560 | ||
b726e493 FR |
4561 | #define R8168_CPCMD_QUIRK_MASK (\ |
4562 | EnableBist | \ | |
4563 | Mac_dbgo_oe | \ | |
4564 | Force_half_dup | \ | |
4565 | Force_rxflow_en | \ | |
4566 | Force_txflow_en | \ | |
4567 | Cxpl_dbg_sel | \ | |
4568 | ASF | \ | |
4569 | PktCntrDisable | \ | |
4570 | Mac_dbgo_sel) | |
4571 | ||
219a1e9d FR |
4572 | static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev) |
4573 | { | |
b726e493 FR |
4574 | RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); |
4575 | ||
4576 | RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); | |
4577 | ||
2e68ae44 FR |
4578 | rtl_tx_performance_tweak(pdev, |
4579 | (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN); | |
219a1e9d FR |
4580 | } |
4581 | ||
4582 | static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev) | |
4583 | { | |
4584 | rtl_hw_start_8168bb(ioaddr, pdev); | |
b726e493 | 4585 | |
f0298f81 | 4586 | RTL_W8(MaxTxPacketSize, TxPacketMax); |
b726e493 FR |
4587 | |
4588 | RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0)); | |
219a1e9d FR |
4589 | } |
4590 | ||
4591 | static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev) | |
4592 | { | |
b726e493 FR |
4593 | RTL_W8(Config1, RTL_R8(Config1) | Speed_down); |
4594 | ||
4595 | RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); | |
4596 | ||
219a1e9d | 4597 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); |
b726e493 FR |
4598 | |
4599 | rtl_disable_clock_request(pdev); | |
4600 | ||
4601 | RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); | |
219a1e9d FR |
4602 | } |
4603 | ||
ef3386f0 | 4604 | static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev) |
219a1e9d | 4605 | { |
350f7596 | 4606 | static const struct ephy_info e_info_8168cp[] = { |
b726e493 FR |
4607 | { 0x01, 0, 0x0001 }, |
4608 | { 0x02, 0x0800, 0x1000 }, | |
4609 | { 0x03, 0, 0x0042 }, | |
4610 | { 0x06, 0x0080, 0x0000 }, | |
4611 | { 0x07, 0, 0x2000 } | |
4612 | }; | |
4613 | ||
650e8d5d | 4614 | rtl_csi_access_enable_2(ioaddr); |
b726e493 FR |
4615 | |
4616 | rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp)); | |
4617 | ||
219a1e9d FR |
4618 | __rtl_hw_start_8168cp(ioaddr, pdev); |
4619 | } | |
4620 | ||
ef3386f0 FR |
4621 | static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev) |
4622 | { | |
650e8d5d | 4623 | rtl_csi_access_enable_2(ioaddr); |
ef3386f0 FR |
4624 | |
4625 | RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); | |
4626 | ||
4627 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
4628 | ||
4629 | RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); | |
4630 | } | |
4631 | ||
7f3e3d3a FR |
4632 | static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev) |
4633 | { | |
650e8d5d | 4634 | rtl_csi_access_enable_2(ioaddr); |
7f3e3d3a FR |
4635 | |
4636 | RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); | |
4637 | ||
4638 | /* Magic. */ | |
4639 | RTL_W8(DBG_REG, 0x20); | |
4640 | ||
f0298f81 | 4641 | RTL_W8(MaxTxPacketSize, TxPacketMax); |
7f3e3d3a FR |
4642 | |
4643 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
4644 | ||
4645 | RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); | |
4646 | } | |
4647 | ||
219a1e9d FR |
4648 | static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev) |
4649 | { | |
350f7596 | 4650 | static const struct ephy_info e_info_8168c_1[] = { |
b726e493 FR |
4651 | { 0x02, 0x0800, 0x1000 }, |
4652 | { 0x03, 0, 0x0002 }, | |
4653 | { 0x06, 0x0080, 0x0000 } | |
4654 | }; | |
4655 | ||
650e8d5d | 4656 | rtl_csi_access_enable_2(ioaddr); |
b726e493 FR |
4657 | |
4658 | RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2); | |
4659 | ||
4660 | rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1)); | |
4661 | ||
219a1e9d FR |
4662 | __rtl_hw_start_8168cp(ioaddr, pdev); |
4663 | } | |
4664 | ||
4665 | static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev) | |
4666 | { | |
350f7596 | 4667 | static const struct ephy_info e_info_8168c_2[] = { |
b726e493 FR |
4668 | { 0x01, 0, 0x0001 }, |
4669 | { 0x03, 0x0400, 0x0220 } | |
4670 | }; | |
4671 | ||
650e8d5d | 4672 | rtl_csi_access_enable_2(ioaddr); |
b726e493 FR |
4673 | |
4674 | rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2)); | |
4675 | ||
219a1e9d FR |
4676 | __rtl_hw_start_8168cp(ioaddr, pdev); |
4677 | } | |
4678 | ||
197ff761 FR |
4679 | static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev) |
4680 | { | |
4681 | rtl_hw_start_8168c_2(ioaddr, pdev); | |
4682 | } | |
4683 | ||
6fb07058 FR |
4684 | static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev) |
4685 | { | |
650e8d5d | 4686 | rtl_csi_access_enable_2(ioaddr); |
6fb07058 FR |
4687 | |
4688 | __rtl_hw_start_8168cp(ioaddr, pdev); | |
4689 | } | |
4690 | ||
5b538df9 FR |
4691 | static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev) |
4692 | { | |
650e8d5d | 4693 | rtl_csi_access_enable_2(ioaddr); |
5b538df9 FR |
4694 | |
4695 | rtl_disable_clock_request(pdev); | |
4696 | ||
f0298f81 | 4697 | RTL_W8(MaxTxPacketSize, TxPacketMax); |
5b538df9 FR |
4698 | |
4699 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
4700 | ||
4701 | RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); | |
4702 | } | |
4703 | ||
4804b3b3 | 4704 | static void rtl_hw_start_8168dp(void __iomem *ioaddr, struct pci_dev *pdev) |
4705 | { | |
4706 | rtl_csi_access_enable_1(ioaddr); | |
4707 | ||
4708 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
4709 | ||
4710 | RTL_W8(MaxTxPacketSize, TxPacketMax); | |
4711 | ||
4712 | rtl_disable_clock_request(pdev); | |
4713 | } | |
4714 | ||
e6de30d6 | 4715 | static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev) |
4716 | { | |
4717 | static const struct ephy_info e_info_8168d_4[] = { | |
4718 | { 0x0b, ~0, 0x48 }, | |
4719 | { 0x19, 0x20, 0x50 }, | |
4720 | { 0x0c, ~0, 0x20 } | |
4721 | }; | |
4722 | int i; | |
4723 | ||
4724 | rtl_csi_access_enable_1(ioaddr); | |
4725 | ||
4726 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
4727 | ||
4728 | RTL_W8(MaxTxPacketSize, TxPacketMax); | |
4729 | ||
4730 | for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) { | |
4731 | const struct ephy_info *e = e_info_8168d_4 + i; | |
4732 | u16 w; | |
4733 | ||
4734 | w = rtl_ephy_read(ioaddr, e->offset); | |
4735 | rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits); | |
4736 | } | |
4737 | ||
4738 | rtl_enable_clock_request(pdev); | |
4739 | } | |
4740 | ||
70090424 | 4741 | static void rtl_hw_start_8168e_1(void __iomem *ioaddr, struct pci_dev *pdev) |
01dc7fec | 4742 | { |
70090424 | 4743 | static const struct ephy_info e_info_8168e_1[] = { |
01dc7fec | 4744 | { 0x00, 0x0200, 0x0100 }, |
4745 | { 0x00, 0x0000, 0x0004 }, | |
4746 | { 0x06, 0x0002, 0x0001 }, | |
4747 | { 0x06, 0x0000, 0x0030 }, | |
4748 | { 0x07, 0x0000, 0x2000 }, | |
4749 | { 0x00, 0x0000, 0x0020 }, | |
4750 | { 0x03, 0x5800, 0x2000 }, | |
4751 | { 0x03, 0x0000, 0x0001 }, | |
4752 | { 0x01, 0x0800, 0x1000 }, | |
4753 | { 0x07, 0x0000, 0x4000 }, | |
4754 | { 0x1e, 0x0000, 0x2000 }, | |
4755 | { 0x19, 0xffff, 0xfe6c }, | |
4756 | { 0x0a, 0x0000, 0x0040 } | |
4757 | }; | |
4758 | ||
4759 | rtl_csi_access_enable_2(ioaddr); | |
4760 | ||
70090424 | 4761 | rtl_ephy_init(ioaddr, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1)); |
01dc7fec | 4762 | |
4763 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
4764 | ||
4765 | RTL_W8(MaxTxPacketSize, TxPacketMax); | |
4766 | ||
4767 | rtl_disable_clock_request(pdev); | |
4768 | ||
4769 | /* Reset tx FIFO pointer */ | |
cecb5fd7 FR |
4770 | RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST); |
4771 | RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST); | |
01dc7fec | 4772 | |
cecb5fd7 | 4773 | RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en); |
01dc7fec | 4774 | } |
4775 | ||
70090424 HW |
4776 | static void rtl_hw_start_8168e_2(void __iomem *ioaddr, struct pci_dev *pdev) |
4777 | { | |
4778 | static const struct ephy_info e_info_8168e_2[] = { | |
4779 | { 0x09, 0x0000, 0x0080 }, | |
4780 | { 0x19, 0x0000, 0x0224 } | |
4781 | }; | |
4782 | ||
4783 | rtl_csi_access_enable_1(ioaddr); | |
4784 | ||
4785 | rtl_ephy_init(ioaddr, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2)); | |
4786 | ||
4787 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
4788 | ||
4789 | rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); | |
4790 | rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); | |
4791 | rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC); | |
4792 | rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC); | |
4793 | rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC); | |
4794 | rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC); | |
4795 | rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC); | |
4796 | rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, | |
4797 | ERIAR_EXGMAC); | |
4798 | ||
3090bd9a | 4799 | RTL_W8(MaxTxPacketSize, EarlySize); |
70090424 HW |
4800 | |
4801 | rtl_disable_clock_request(pdev); | |
4802 | ||
4803 | RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO); | |
4804 | RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB); | |
4805 | ||
4806 | /* Adjust EEE LED frequency */ | |
4807 | RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07); | |
4808 | ||
4809 | RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN); | |
4810 | RTL_W32(MISC, RTL_R32(MISC) | PWM_EN); | |
4811 | RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en); | |
4812 | } | |
4813 | ||
c2218925 HW |
4814 | static void rtl_hw_start_8168f_1(void __iomem *ioaddr, struct pci_dev *pdev) |
4815 | { | |
4816 | static const struct ephy_info e_info_8168f_1[] = { | |
4817 | { 0x06, 0x00c0, 0x0020 }, | |
4818 | { 0x08, 0x0001, 0x0002 }, | |
4819 | { 0x09, 0x0000, 0x0080 }, | |
4820 | { 0x19, 0x0000, 0x0224 } | |
4821 | }; | |
4822 | ||
4823 | rtl_csi_access_enable_1(ioaddr); | |
4824 | ||
4825 | rtl_ephy_init(ioaddr, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1)); | |
4826 | ||
4827 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
4828 | ||
4829 | rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); | |
4830 | rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); | |
4831 | rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC); | |
4832 | rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC); | |
4833 | rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC); | |
4834 | rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC); | |
4835 | rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC); | |
4836 | rtl_w1w0_eri(ioaddr, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC); | |
4837 | rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC); | |
4838 | rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC); | |
4839 | rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, | |
4840 | ERIAR_EXGMAC); | |
4841 | ||
4842 | RTL_W8(MaxTxPacketSize, EarlySize); | |
4843 | ||
4844 | rtl_disable_clock_request(pdev); | |
4845 | ||
4846 | RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO); | |
4847 | RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB); | |
4848 | ||
4849 | /* Adjust EEE LED frequency */ | |
4850 | RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07); | |
4851 | ||
4852 | RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN); | |
4853 | RTL_W32(MISC, RTL_R32(MISC) | PWM_EN); | |
4854 | RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en); | |
4855 | } | |
4856 | ||
07ce4064 FR |
4857 | static void rtl_hw_start_8168(struct net_device *dev) |
4858 | { | |
2dd99530 FR |
4859 | struct rtl8169_private *tp = netdev_priv(dev); |
4860 | void __iomem *ioaddr = tp->mmio_addr; | |
0e485150 | 4861 | struct pci_dev *pdev = tp->pci_dev; |
2dd99530 FR |
4862 | |
4863 | RTL_W8(Cfg9346, Cfg9346_Unlock); | |
4864 | ||
f0298f81 | 4865 | RTL_W8(MaxTxPacketSize, TxPacketMax); |
2dd99530 | 4866 | |
6f0333b8 | 4867 | rtl_set_rx_max_size(ioaddr, rx_buf_sz); |
2dd99530 | 4868 | |
0e485150 | 4869 | tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1; |
2dd99530 FR |
4870 | |
4871 | RTL_W16(CPlusCmd, tp->cp_cmd); | |
4872 | ||
0e485150 | 4873 | RTL_W16(IntrMitigate, 0x5151); |
2dd99530 | 4874 | |
0e485150 | 4875 | /* Work around for RxFIFO overflow. */ |
b5ba6d12 IV |
4876 | if (tp->mac_version == RTL_GIGA_MAC_VER_11 || |
4877 | tp->mac_version == RTL_GIGA_MAC_VER_22) { | |
0e485150 FR |
4878 | tp->intr_event |= RxFIFOOver | PCSTimeout; |
4879 | tp->intr_event &= ~RxOverflow; | |
4880 | } | |
4881 | ||
4882 | rtl_set_rx_tx_desc_registers(tp, ioaddr); | |
2dd99530 | 4883 | |
b8363901 FR |
4884 | rtl_set_rx_mode(dev); |
4885 | ||
4886 | RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) | | |
4887 | (InterFrameGap << TxInterFrameGapShift)); | |
2dd99530 FR |
4888 | |
4889 | RTL_R8(IntrMask); | |
4890 | ||
219a1e9d FR |
4891 | switch (tp->mac_version) { |
4892 | case RTL_GIGA_MAC_VER_11: | |
4893 | rtl_hw_start_8168bb(ioaddr, pdev); | |
4804b3b3 | 4894 | break; |
219a1e9d FR |
4895 | |
4896 | case RTL_GIGA_MAC_VER_12: | |
4897 | case RTL_GIGA_MAC_VER_17: | |
4898 | rtl_hw_start_8168bef(ioaddr, pdev); | |
4804b3b3 | 4899 | break; |
219a1e9d FR |
4900 | |
4901 | case RTL_GIGA_MAC_VER_18: | |
ef3386f0 | 4902 | rtl_hw_start_8168cp_1(ioaddr, pdev); |
4804b3b3 | 4903 | break; |
219a1e9d FR |
4904 | |
4905 | case RTL_GIGA_MAC_VER_19: | |
4906 | rtl_hw_start_8168c_1(ioaddr, pdev); | |
4804b3b3 | 4907 | break; |
219a1e9d FR |
4908 | |
4909 | case RTL_GIGA_MAC_VER_20: | |
4910 | rtl_hw_start_8168c_2(ioaddr, pdev); | |
4804b3b3 | 4911 | break; |
219a1e9d | 4912 | |
197ff761 FR |
4913 | case RTL_GIGA_MAC_VER_21: |
4914 | rtl_hw_start_8168c_3(ioaddr, pdev); | |
4804b3b3 | 4915 | break; |
197ff761 | 4916 | |
6fb07058 FR |
4917 | case RTL_GIGA_MAC_VER_22: |
4918 | rtl_hw_start_8168c_4(ioaddr, pdev); | |
4804b3b3 | 4919 | break; |
6fb07058 | 4920 | |
ef3386f0 FR |
4921 | case RTL_GIGA_MAC_VER_23: |
4922 | rtl_hw_start_8168cp_2(ioaddr, pdev); | |
4804b3b3 | 4923 | break; |
ef3386f0 | 4924 | |
7f3e3d3a FR |
4925 | case RTL_GIGA_MAC_VER_24: |
4926 | rtl_hw_start_8168cp_3(ioaddr, pdev); | |
4804b3b3 | 4927 | break; |
7f3e3d3a | 4928 | |
5b538df9 | 4929 | case RTL_GIGA_MAC_VER_25: |
daf9df6d | 4930 | case RTL_GIGA_MAC_VER_26: |
4931 | case RTL_GIGA_MAC_VER_27: | |
5b538df9 | 4932 | rtl_hw_start_8168d(ioaddr, pdev); |
4804b3b3 | 4933 | break; |
5b538df9 | 4934 | |
e6de30d6 | 4935 | case RTL_GIGA_MAC_VER_28: |
4936 | rtl_hw_start_8168d_4(ioaddr, pdev); | |
4804b3b3 | 4937 | break; |
cecb5fd7 | 4938 | |
4804b3b3 | 4939 | case RTL_GIGA_MAC_VER_31: |
4940 | rtl_hw_start_8168dp(ioaddr, pdev); | |
4941 | break; | |
4942 | ||
01dc7fec | 4943 | case RTL_GIGA_MAC_VER_32: |
4944 | case RTL_GIGA_MAC_VER_33: | |
70090424 HW |
4945 | rtl_hw_start_8168e_1(ioaddr, pdev); |
4946 | break; | |
4947 | case RTL_GIGA_MAC_VER_34: | |
4948 | rtl_hw_start_8168e_2(ioaddr, pdev); | |
01dc7fec | 4949 | break; |
e6de30d6 | 4950 | |
c2218925 HW |
4951 | case RTL_GIGA_MAC_VER_35: |
4952 | case RTL_GIGA_MAC_VER_36: | |
4953 | rtl_hw_start_8168f_1(ioaddr, pdev); | |
4954 | break; | |
4955 | ||
219a1e9d FR |
4956 | default: |
4957 | printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n", | |
4958 | dev->name, tp->mac_version); | |
4804b3b3 | 4959 | break; |
219a1e9d | 4960 | } |
2dd99530 | 4961 | |
0e485150 FR |
4962 | RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); |
4963 | ||
b8363901 FR |
4964 | RTL_W8(Cfg9346, Cfg9346_Lock); |
4965 | ||
2dd99530 | 4966 | RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000); |
6dccd16b | 4967 | |
0e485150 | 4968 | RTL_W16(IntrMask, tp->intr_event); |
07ce4064 | 4969 | } |
1da177e4 | 4970 | |
2857ffb7 FR |
4971 | #define R810X_CPCMD_QUIRK_MASK (\ |
4972 | EnableBist | \ | |
4973 | Mac_dbgo_oe | \ | |
4974 | Force_half_dup | \ | |
5edcc537 | 4975 | Force_rxflow_en | \ |
2857ffb7 FR |
4976 | Force_txflow_en | \ |
4977 | Cxpl_dbg_sel | \ | |
4978 | ASF | \ | |
4979 | PktCntrDisable | \ | |
d24e9aaf | 4980 | Mac_dbgo_sel) |
2857ffb7 FR |
4981 | |
4982 | static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev) | |
4983 | { | |
350f7596 | 4984 | static const struct ephy_info e_info_8102e_1[] = { |
2857ffb7 FR |
4985 | { 0x01, 0, 0x6e65 }, |
4986 | { 0x02, 0, 0x091f }, | |
4987 | { 0x03, 0, 0xc2f9 }, | |
4988 | { 0x06, 0, 0xafb5 }, | |
4989 | { 0x07, 0, 0x0e00 }, | |
4990 | { 0x19, 0, 0xec80 }, | |
4991 | { 0x01, 0, 0x2e65 }, | |
4992 | { 0x01, 0, 0x6e65 } | |
4993 | }; | |
4994 | u8 cfg1; | |
4995 | ||
650e8d5d | 4996 | rtl_csi_access_enable_2(ioaddr); |
2857ffb7 FR |
4997 | |
4998 | RTL_W8(DBG_REG, FIX_NAK_1); | |
4999 | ||
5000 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
5001 | ||
5002 | RTL_W8(Config1, | |
5003 | LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable); | |
5004 | RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); | |
5005 | ||
5006 | cfg1 = RTL_R8(Config1); | |
5007 | if ((cfg1 & LEDS0) && (cfg1 & LEDS1)) | |
5008 | RTL_W8(Config1, cfg1 & ~LEDS0); | |
5009 | ||
2857ffb7 FR |
5010 | rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1)); |
5011 | } | |
5012 | ||
5013 | static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev) | |
5014 | { | |
650e8d5d | 5015 | rtl_csi_access_enable_2(ioaddr); |
2857ffb7 FR |
5016 | |
5017 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
5018 | ||
5019 | RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable); | |
5020 | RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); | |
2857ffb7 FR |
5021 | } |
5022 | ||
5023 | static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev) | |
5024 | { | |
5025 | rtl_hw_start_8102e_2(ioaddr, pdev); | |
5026 | ||
5027 | rtl_ephy_write(ioaddr, 0x03, 0xc2f9); | |
5028 | } | |
5029 | ||
5a5e4443 HW |
5030 | static void rtl_hw_start_8105e_1(void __iomem *ioaddr, struct pci_dev *pdev) |
5031 | { | |
5032 | static const struct ephy_info e_info_8105e_1[] = { | |
5033 | { 0x07, 0, 0x4000 }, | |
5034 | { 0x19, 0, 0x0200 }, | |
5035 | { 0x19, 0, 0x0020 }, | |
5036 | { 0x1e, 0, 0x2000 }, | |
5037 | { 0x03, 0, 0x0001 }, | |
5038 | { 0x19, 0, 0x0100 }, | |
5039 | { 0x19, 0, 0x0004 }, | |
5040 | { 0x0a, 0, 0x0020 } | |
5041 | }; | |
5042 | ||
cecb5fd7 | 5043 | /* Force LAN exit from ASPM if Rx/Tx are not idle */ |
5a5e4443 HW |
5044 | RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800); |
5045 | ||
cecb5fd7 | 5046 | /* Disable Early Tally Counter */ |
5a5e4443 HW |
5047 | RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000); |
5048 | ||
5049 | RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET); | |
4f6b00e5 | 5050 | RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN); |
5a5e4443 HW |
5051 | |
5052 | rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1)); | |
5053 | } | |
5054 | ||
5055 | static void rtl_hw_start_8105e_2(void __iomem *ioaddr, struct pci_dev *pdev) | |
5056 | { | |
5057 | rtl_hw_start_8105e_1(ioaddr, pdev); | |
5058 | rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000); | |
5059 | } | |
5060 | ||
07ce4064 FR |
5061 | static void rtl_hw_start_8101(struct net_device *dev) |
5062 | { | |
cdf1a608 FR |
5063 | struct rtl8169_private *tp = netdev_priv(dev); |
5064 | void __iomem *ioaddr = tp->mmio_addr; | |
5065 | struct pci_dev *pdev = tp->pci_dev; | |
5066 | ||
cecb5fd7 FR |
5067 | if (tp->mac_version == RTL_GIGA_MAC_VER_13 || |
5068 | tp->mac_version == RTL_GIGA_MAC_VER_16) { | |
e44daade | 5069 | int cap = pci_pcie_cap(pdev); |
9c14ceaf FR |
5070 | |
5071 | if (cap) { | |
5072 | pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, | |
5073 | PCI_EXP_DEVCTL_NOSNOOP_EN); | |
5074 | } | |
cdf1a608 FR |
5075 | } |
5076 | ||
d24e9aaf HW |
5077 | RTL_W8(Cfg9346, Cfg9346_Unlock); |
5078 | ||
2857ffb7 FR |
5079 | switch (tp->mac_version) { |
5080 | case RTL_GIGA_MAC_VER_07: | |
5081 | rtl_hw_start_8102e_1(ioaddr, pdev); | |
5082 | break; | |
5083 | ||
5084 | case RTL_GIGA_MAC_VER_08: | |
5085 | rtl_hw_start_8102e_3(ioaddr, pdev); | |
5086 | break; | |
5087 | ||
5088 | case RTL_GIGA_MAC_VER_09: | |
5089 | rtl_hw_start_8102e_2(ioaddr, pdev); | |
5090 | break; | |
5a5e4443 HW |
5091 | |
5092 | case RTL_GIGA_MAC_VER_29: | |
5093 | rtl_hw_start_8105e_1(ioaddr, pdev); | |
5094 | break; | |
5095 | case RTL_GIGA_MAC_VER_30: | |
5096 | rtl_hw_start_8105e_2(ioaddr, pdev); | |
5097 | break; | |
cdf1a608 FR |
5098 | } |
5099 | ||
d24e9aaf | 5100 | RTL_W8(Cfg9346, Cfg9346_Lock); |
cdf1a608 | 5101 | |
f0298f81 | 5102 | RTL_W8(MaxTxPacketSize, TxPacketMax); |
cdf1a608 | 5103 | |
6f0333b8 | 5104 | rtl_set_rx_max_size(ioaddr, rx_buf_sz); |
cdf1a608 | 5105 | |
d24e9aaf | 5106 | tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK; |
cdf1a608 FR |
5107 | RTL_W16(CPlusCmd, tp->cp_cmd); |
5108 | ||
5109 | RTL_W16(IntrMitigate, 0x0000); | |
5110 | ||
5111 | rtl_set_rx_tx_desc_registers(tp, ioaddr); | |
5112 | ||
5113 | RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); | |
5114 | rtl_set_rx_tx_config_registers(tp); | |
5115 | ||
cdf1a608 FR |
5116 | RTL_R8(IntrMask); |
5117 | ||
cdf1a608 FR |
5118 | rtl_set_rx_mode(dev); |
5119 | ||
5120 | RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000); | |
6dccd16b | 5121 | |
0e485150 | 5122 | RTL_W16(IntrMask, tp->intr_event); |
1da177e4 LT |
5123 | } |
5124 | ||
5125 | static int rtl8169_change_mtu(struct net_device *dev, int new_mtu) | |
5126 | { | |
d58d46b5 FR |
5127 | struct rtl8169_private *tp = netdev_priv(dev); |
5128 | ||
5129 | if (new_mtu < ETH_ZLEN || | |
5130 | new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max) | |
1da177e4 LT |
5131 | return -EINVAL; |
5132 | ||
d58d46b5 FR |
5133 | if (new_mtu > ETH_DATA_LEN) |
5134 | rtl_hw_jumbo_enable(tp); | |
5135 | else | |
5136 | rtl_hw_jumbo_disable(tp); | |
5137 | ||
1da177e4 | 5138 | dev->mtu = new_mtu; |
350fb32a MM |
5139 | netdev_update_features(dev); |
5140 | ||
323bb685 | 5141 | return 0; |
1da177e4 LT |
5142 | } |
5143 | ||
5144 | static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc) | |
5145 | { | |
95e0918d | 5146 | desc->addr = cpu_to_le64(0x0badbadbadbadbadull); |
1da177e4 LT |
5147 | desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask); |
5148 | } | |
5149 | ||
6f0333b8 ED |
5150 | static void rtl8169_free_rx_databuff(struct rtl8169_private *tp, |
5151 | void **data_buff, struct RxDesc *desc) | |
1da177e4 | 5152 | { |
48addcc9 | 5153 | dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz, |
231aee63 | 5154 | DMA_FROM_DEVICE); |
48addcc9 | 5155 | |
6f0333b8 ED |
5156 | kfree(*data_buff); |
5157 | *data_buff = NULL; | |
1da177e4 LT |
5158 | rtl8169_make_unusable_by_asic(desc); |
5159 | } | |
5160 | ||
5161 | static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz) | |
5162 | { | |
5163 | u32 eor = le32_to_cpu(desc->opts1) & RingEnd; | |
5164 | ||
5165 | desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz); | |
5166 | } | |
5167 | ||
5168 | static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping, | |
5169 | u32 rx_buf_sz) | |
5170 | { | |
5171 | desc->addr = cpu_to_le64(mapping); | |
5172 | wmb(); | |
5173 | rtl8169_mark_to_asic(desc, rx_buf_sz); | |
5174 | } | |
5175 | ||
6f0333b8 ED |
5176 | static inline void *rtl8169_align(void *data) |
5177 | { | |
5178 | return (void *)ALIGN((long)data, 16); | |
5179 | } | |
5180 | ||
0ecbe1ca SG |
5181 | static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp, |
5182 | struct RxDesc *desc) | |
1da177e4 | 5183 | { |
6f0333b8 | 5184 | void *data; |
1da177e4 | 5185 | dma_addr_t mapping; |
48addcc9 | 5186 | struct device *d = &tp->pci_dev->dev; |
0ecbe1ca | 5187 | struct net_device *dev = tp->dev; |
6f0333b8 | 5188 | int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1; |
1da177e4 | 5189 | |
6f0333b8 ED |
5190 | data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node); |
5191 | if (!data) | |
5192 | return NULL; | |
e9f63f30 | 5193 | |
6f0333b8 ED |
5194 | if (rtl8169_align(data) != data) { |
5195 | kfree(data); | |
5196 | data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node); | |
5197 | if (!data) | |
5198 | return NULL; | |
5199 | } | |
3eafe507 | 5200 | |
48addcc9 | 5201 | mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz, |
231aee63 | 5202 | DMA_FROM_DEVICE); |
d827d86b SG |
5203 | if (unlikely(dma_mapping_error(d, mapping))) { |
5204 | if (net_ratelimit()) | |
5205 | netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n"); | |
3eafe507 | 5206 | goto err_out; |
d827d86b | 5207 | } |
1da177e4 LT |
5208 | |
5209 | rtl8169_map_to_asic(desc, mapping, rx_buf_sz); | |
6f0333b8 | 5210 | return data; |
3eafe507 SG |
5211 | |
5212 | err_out: | |
5213 | kfree(data); | |
5214 | return NULL; | |
1da177e4 LT |
5215 | } |
5216 | ||
5217 | static void rtl8169_rx_clear(struct rtl8169_private *tp) | |
5218 | { | |
07d3f51f | 5219 | unsigned int i; |
1da177e4 LT |
5220 | |
5221 | for (i = 0; i < NUM_RX_DESC; i++) { | |
6f0333b8 ED |
5222 | if (tp->Rx_databuff[i]) { |
5223 | rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i, | |
1da177e4 LT |
5224 | tp->RxDescArray + i); |
5225 | } | |
5226 | } | |
5227 | } | |
5228 | ||
0ecbe1ca | 5229 | static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc) |
1da177e4 | 5230 | { |
0ecbe1ca SG |
5231 | desc->opts1 |= cpu_to_le32(RingEnd); |
5232 | } | |
5b0384f4 | 5233 | |
0ecbe1ca SG |
5234 | static int rtl8169_rx_fill(struct rtl8169_private *tp) |
5235 | { | |
5236 | unsigned int i; | |
1da177e4 | 5237 | |
0ecbe1ca SG |
5238 | for (i = 0; i < NUM_RX_DESC; i++) { |
5239 | void *data; | |
4ae47c2d | 5240 | |
6f0333b8 | 5241 | if (tp->Rx_databuff[i]) |
1da177e4 | 5242 | continue; |
bcf0bf90 | 5243 | |
0ecbe1ca | 5244 | data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i); |
6f0333b8 ED |
5245 | if (!data) { |
5246 | rtl8169_make_unusable_by_asic(tp->RxDescArray + i); | |
0ecbe1ca | 5247 | goto err_out; |
6f0333b8 ED |
5248 | } |
5249 | tp->Rx_databuff[i] = data; | |
1da177e4 | 5250 | } |
1da177e4 | 5251 | |
0ecbe1ca SG |
5252 | rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1); |
5253 | return 0; | |
5254 | ||
5255 | err_out: | |
5256 | rtl8169_rx_clear(tp); | |
5257 | return -ENOMEM; | |
1da177e4 LT |
5258 | } |
5259 | ||
1da177e4 LT |
5260 | static int rtl8169_init_ring(struct net_device *dev) |
5261 | { | |
5262 | struct rtl8169_private *tp = netdev_priv(dev); | |
5263 | ||
5264 | rtl8169_init_ring_indexes(tp); | |
5265 | ||
5266 | memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info)); | |
6f0333b8 | 5267 | memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *)); |
1da177e4 | 5268 | |
0ecbe1ca | 5269 | return rtl8169_rx_fill(tp); |
1da177e4 LT |
5270 | } |
5271 | ||
48addcc9 | 5272 | static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb, |
1da177e4 LT |
5273 | struct TxDesc *desc) |
5274 | { | |
5275 | unsigned int len = tx_skb->len; | |
5276 | ||
48addcc9 SG |
5277 | dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE); |
5278 | ||
1da177e4 LT |
5279 | desc->opts1 = 0x00; |
5280 | desc->opts2 = 0x00; | |
5281 | desc->addr = 0x00; | |
5282 | tx_skb->len = 0; | |
5283 | } | |
5284 | ||
3eafe507 SG |
5285 | static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start, |
5286 | unsigned int n) | |
1da177e4 LT |
5287 | { |
5288 | unsigned int i; | |
5289 | ||
3eafe507 SG |
5290 | for (i = 0; i < n; i++) { |
5291 | unsigned int entry = (start + i) % NUM_TX_DESC; | |
1da177e4 LT |
5292 | struct ring_info *tx_skb = tp->tx_skb + entry; |
5293 | unsigned int len = tx_skb->len; | |
5294 | ||
5295 | if (len) { | |
5296 | struct sk_buff *skb = tx_skb->skb; | |
5297 | ||
48addcc9 | 5298 | rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb, |
1da177e4 LT |
5299 | tp->TxDescArray + entry); |
5300 | if (skb) { | |
cac4b22f | 5301 | tp->dev->stats.tx_dropped++; |
1da177e4 LT |
5302 | dev_kfree_skb(skb); |
5303 | tx_skb->skb = NULL; | |
5304 | } | |
1da177e4 LT |
5305 | } |
5306 | } | |
3eafe507 SG |
5307 | } |
5308 | ||
5309 | static void rtl8169_tx_clear(struct rtl8169_private *tp) | |
5310 | { | |
5311 | rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC); | |
1da177e4 LT |
5312 | tp->cur_tx = tp->dirty_tx = 0; |
5313 | } | |
5314 | ||
c4028958 | 5315 | static void rtl8169_schedule_work(struct net_device *dev, work_func_t task) |
1da177e4 LT |
5316 | { |
5317 | struct rtl8169_private *tp = netdev_priv(dev); | |
5318 | ||
c4028958 | 5319 | PREPARE_DELAYED_WORK(&tp->task, task); |
1da177e4 LT |
5320 | schedule_delayed_work(&tp->task, 4); |
5321 | } | |
5322 | ||
5323 | static void rtl8169_wait_for_quiescence(struct net_device *dev) | |
5324 | { | |
5325 | struct rtl8169_private *tp = netdev_priv(dev); | |
5326 | void __iomem *ioaddr = tp->mmio_addr; | |
5327 | ||
5328 | synchronize_irq(dev->irq); | |
5329 | ||
5330 | /* Wait for any pending NAPI task to complete */ | |
bea3348e | 5331 | napi_disable(&tp->napi); |
1da177e4 LT |
5332 | |
5333 | rtl8169_irq_mask_and_ack(ioaddr); | |
5334 | ||
d1d08d12 DM |
5335 | tp->intr_mask = 0xffff; |
5336 | RTL_W16(IntrMask, tp->intr_event); | |
bea3348e | 5337 | napi_enable(&tp->napi); |
1da177e4 LT |
5338 | } |
5339 | ||
c4028958 | 5340 | static void rtl8169_reinit_task(struct work_struct *work) |
1da177e4 | 5341 | { |
c4028958 DH |
5342 | struct rtl8169_private *tp = |
5343 | container_of(work, struct rtl8169_private, task.work); | |
5344 | struct net_device *dev = tp->dev; | |
1da177e4 LT |
5345 | int ret; |
5346 | ||
eb2a021c FR |
5347 | rtnl_lock(); |
5348 | ||
5349 | if (!netif_running(dev)) | |
5350 | goto out_unlock; | |
5351 | ||
5352 | rtl8169_wait_for_quiescence(dev); | |
5353 | rtl8169_close(dev); | |
1da177e4 LT |
5354 | |
5355 | ret = rtl8169_open(dev); | |
5356 | if (unlikely(ret < 0)) { | |
bf82c189 JP |
5357 | if (net_ratelimit()) |
5358 | netif_err(tp, drv, dev, | |
5359 | "reinit failure (status = %d). Rescheduling\n", | |
5360 | ret); | |
1da177e4 LT |
5361 | rtl8169_schedule_work(dev, rtl8169_reinit_task); |
5362 | } | |
eb2a021c FR |
5363 | |
5364 | out_unlock: | |
5365 | rtnl_unlock(); | |
1da177e4 LT |
5366 | } |
5367 | ||
c4028958 | 5368 | static void rtl8169_reset_task(struct work_struct *work) |
1da177e4 | 5369 | { |
c4028958 DH |
5370 | struct rtl8169_private *tp = |
5371 | container_of(work, struct rtl8169_private, task.work); | |
5372 | struct net_device *dev = tp->dev; | |
56de414c | 5373 | int i; |
1da177e4 | 5374 | |
eb2a021c FR |
5375 | rtnl_lock(); |
5376 | ||
1da177e4 | 5377 | if (!netif_running(dev)) |
eb2a021c | 5378 | goto out_unlock; |
1da177e4 LT |
5379 | |
5380 | rtl8169_wait_for_quiescence(dev); | |
5381 | ||
56de414c FR |
5382 | for (i = 0; i < NUM_RX_DESC; i++) |
5383 | rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz); | |
5384 | ||
1da177e4 LT |
5385 | rtl8169_tx_clear(tp); |
5386 | ||
92fc43b4 | 5387 | rtl8169_hw_reset(tp); |
56de414c FR |
5388 | rtl_hw_start(dev); |
5389 | netif_wake_queue(dev); | |
5390 | rtl8169_check_link_status(dev, tp, tp->mmio_addr); | |
eb2a021c FR |
5391 | |
5392 | out_unlock: | |
5393 | rtnl_unlock(); | |
1da177e4 LT |
5394 | } |
5395 | ||
5396 | static void rtl8169_tx_timeout(struct net_device *dev) | |
5397 | { | |
5398 | struct rtl8169_private *tp = netdev_priv(dev); | |
5399 | ||
e6de30d6 | 5400 | rtl8169_hw_reset(tp); |
1da177e4 LT |
5401 | |
5402 | /* Let's wait a bit while any (async) irq lands on */ | |
5403 | rtl8169_schedule_work(dev, rtl8169_reset_task); | |
5404 | } | |
5405 | ||
5406 | static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb, | |
2b7b4318 | 5407 | u32 *opts) |
1da177e4 LT |
5408 | { |
5409 | struct skb_shared_info *info = skb_shinfo(skb); | |
5410 | unsigned int cur_frag, entry; | |
a6343afb | 5411 | struct TxDesc * uninitialized_var(txd); |
48addcc9 | 5412 | struct device *d = &tp->pci_dev->dev; |
1da177e4 LT |
5413 | |
5414 | entry = tp->cur_tx; | |
5415 | for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) { | |
5416 | skb_frag_t *frag = info->frags + cur_frag; | |
5417 | dma_addr_t mapping; | |
5418 | u32 status, len; | |
5419 | void *addr; | |
5420 | ||
5421 | entry = (entry + 1) % NUM_TX_DESC; | |
5422 | ||
5423 | txd = tp->TxDescArray + entry; | |
5424 | len = frag->size; | |
929f6189 | 5425 | addr = skb_frag_address(frag); |
48addcc9 | 5426 | mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE); |
d827d86b SG |
5427 | if (unlikely(dma_mapping_error(d, mapping))) { |
5428 | if (net_ratelimit()) | |
5429 | netif_err(tp, drv, tp->dev, | |
5430 | "Failed to map TX fragments DMA!\n"); | |
3eafe507 | 5431 | goto err_out; |
d827d86b | 5432 | } |
1da177e4 | 5433 | |
cecb5fd7 | 5434 | /* Anti gcc 2.95.3 bugware (sic) */ |
2b7b4318 FR |
5435 | status = opts[0] | len | |
5436 | (RingEnd * !((entry + 1) % NUM_TX_DESC)); | |
1da177e4 LT |
5437 | |
5438 | txd->opts1 = cpu_to_le32(status); | |
2b7b4318 | 5439 | txd->opts2 = cpu_to_le32(opts[1]); |
1da177e4 LT |
5440 | txd->addr = cpu_to_le64(mapping); |
5441 | ||
5442 | tp->tx_skb[entry].len = len; | |
5443 | } | |
5444 | ||
5445 | if (cur_frag) { | |
5446 | tp->tx_skb[entry].skb = skb; | |
5447 | txd->opts1 |= cpu_to_le32(LastFrag); | |
5448 | } | |
5449 | ||
5450 | return cur_frag; | |
3eafe507 SG |
5451 | |
5452 | err_out: | |
5453 | rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag); | |
5454 | return -EIO; | |
1da177e4 LT |
5455 | } |
5456 | ||
2b7b4318 FR |
5457 | static inline void rtl8169_tso_csum(struct rtl8169_private *tp, |
5458 | struct sk_buff *skb, u32 *opts) | |
1da177e4 | 5459 | { |
2b7b4318 | 5460 | const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version; |
350fb32a | 5461 | u32 mss = skb_shinfo(skb)->gso_size; |
2b7b4318 | 5462 | int offset = info->opts_offset; |
350fb32a | 5463 | |
2b7b4318 FR |
5464 | if (mss) { |
5465 | opts[0] |= TD_LSO; | |
5466 | opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift; | |
5467 | } else if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
eddc9ec5 | 5468 | const struct iphdr *ip = ip_hdr(skb); |
1da177e4 LT |
5469 | |
5470 | if (ip->protocol == IPPROTO_TCP) | |
2b7b4318 | 5471 | opts[offset] |= info->checksum.tcp; |
1da177e4 | 5472 | else if (ip->protocol == IPPROTO_UDP) |
2b7b4318 FR |
5473 | opts[offset] |= info->checksum.udp; |
5474 | else | |
5475 | WARN_ON_ONCE(1); | |
1da177e4 | 5476 | } |
1da177e4 LT |
5477 | } |
5478 | ||
61357325 SH |
5479 | static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb, |
5480 | struct net_device *dev) | |
1da177e4 LT |
5481 | { |
5482 | struct rtl8169_private *tp = netdev_priv(dev); | |
3eafe507 | 5483 | unsigned int entry = tp->cur_tx % NUM_TX_DESC; |
1da177e4 LT |
5484 | struct TxDesc *txd = tp->TxDescArray + entry; |
5485 | void __iomem *ioaddr = tp->mmio_addr; | |
48addcc9 | 5486 | struct device *d = &tp->pci_dev->dev; |
1da177e4 LT |
5487 | dma_addr_t mapping; |
5488 | u32 status, len; | |
2b7b4318 | 5489 | u32 opts[2]; |
3eafe507 | 5490 | int frags; |
5b0384f4 | 5491 | |
1da177e4 | 5492 | if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) { |
bf82c189 | 5493 | netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n"); |
3eafe507 | 5494 | goto err_stop_0; |
1da177e4 LT |
5495 | } |
5496 | ||
5497 | if (unlikely(le32_to_cpu(txd->opts1) & DescOwn)) | |
3eafe507 SG |
5498 | goto err_stop_0; |
5499 | ||
5500 | len = skb_headlen(skb); | |
48addcc9 | 5501 | mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE); |
d827d86b SG |
5502 | if (unlikely(dma_mapping_error(d, mapping))) { |
5503 | if (net_ratelimit()) | |
5504 | netif_err(tp, drv, dev, "Failed to map TX DMA!\n"); | |
3eafe507 | 5505 | goto err_dma_0; |
d827d86b | 5506 | } |
3eafe507 SG |
5507 | |
5508 | tp->tx_skb[entry].len = len; | |
5509 | txd->addr = cpu_to_le64(mapping); | |
1da177e4 | 5510 | |
2b7b4318 FR |
5511 | opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb)); |
5512 | opts[0] = DescOwn; | |
1da177e4 | 5513 | |
2b7b4318 FR |
5514 | rtl8169_tso_csum(tp, skb, opts); |
5515 | ||
5516 | frags = rtl8169_xmit_frags(tp, skb, opts); | |
3eafe507 SG |
5517 | if (frags < 0) |
5518 | goto err_dma_1; | |
5519 | else if (frags) | |
2b7b4318 | 5520 | opts[0] |= FirstFrag; |
3eafe507 | 5521 | else { |
2b7b4318 | 5522 | opts[0] |= FirstFrag | LastFrag; |
1da177e4 LT |
5523 | tp->tx_skb[entry].skb = skb; |
5524 | } | |
5525 | ||
2b7b4318 FR |
5526 | txd->opts2 = cpu_to_le32(opts[1]); |
5527 | ||
1da177e4 LT |
5528 | wmb(); |
5529 | ||
cecb5fd7 | 5530 | /* Anti gcc 2.95.3 bugware (sic) */ |
2b7b4318 | 5531 | status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC)); |
1da177e4 LT |
5532 | txd->opts1 = cpu_to_le32(status); |
5533 | ||
1da177e4 LT |
5534 | tp->cur_tx += frags + 1; |
5535 | ||
4c020a96 | 5536 | wmb(); |
1da177e4 | 5537 | |
cecb5fd7 | 5538 | RTL_W8(TxPoll, NPQ); |
1da177e4 LT |
5539 | |
5540 | if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) { | |
5541 | netif_stop_queue(dev); | |
5542 | smp_rmb(); | |
5543 | if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS) | |
5544 | netif_wake_queue(dev); | |
5545 | } | |
5546 | ||
61357325 | 5547 | return NETDEV_TX_OK; |
1da177e4 | 5548 | |
3eafe507 | 5549 | err_dma_1: |
48addcc9 | 5550 | rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd); |
3eafe507 SG |
5551 | err_dma_0: |
5552 | dev_kfree_skb(skb); | |
5553 | dev->stats.tx_dropped++; | |
5554 | return NETDEV_TX_OK; | |
5555 | ||
5556 | err_stop_0: | |
1da177e4 | 5557 | netif_stop_queue(dev); |
cebf8cc7 | 5558 | dev->stats.tx_dropped++; |
61357325 | 5559 | return NETDEV_TX_BUSY; |
1da177e4 LT |
5560 | } |
5561 | ||
5562 | static void rtl8169_pcierr_interrupt(struct net_device *dev) | |
5563 | { | |
5564 | struct rtl8169_private *tp = netdev_priv(dev); | |
5565 | struct pci_dev *pdev = tp->pci_dev; | |
1da177e4 LT |
5566 | u16 pci_status, pci_cmd; |
5567 | ||
5568 | pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); | |
5569 | pci_read_config_word(pdev, PCI_STATUS, &pci_status); | |
5570 | ||
bf82c189 JP |
5571 | netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n", |
5572 | pci_cmd, pci_status); | |
1da177e4 LT |
5573 | |
5574 | /* | |
5575 | * The recovery sequence below admits a very elaborated explanation: | |
5576 | * - it seems to work; | |
d03902b8 FR |
5577 | * - I did not see what else could be done; |
5578 | * - it makes iop3xx happy. | |
1da177e4 LT |
5579 | * |
5580 | * Feel free to adjust to your needs. | |
5581 | */ | |
a27993f3 | 5582 | if (pdev->broken_parity_status) |
d03902b8 FR |
5583 | pci_cmd &= ~PCI_COMMAND_PARITY; |
5584 | else | |
5585 | pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY; | |
5586 | ||
5587 | pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); | |
1da177e4 LT |
5588 | |
5589 | pci_write_config_word(pdev, PCI_STATUS, | |
5590 | pci_status & (PCI_STATUS_DETECTED_PARITY | | |
5591 | PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT | | |
5592 | PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT)); | |
5593 | ||
5594 | /* The infamous DAC f*ckup only happens at boot time */ | |
5595 | if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) { | |
e6de30d6 | 5596 | void __iomem *ioaddr = tp->mmio_addr; |
5597 | ||
bf82c189 | 5598 | netif_info(tp, intr, dev, "disabling PCI DAC\n"); |
1da177e4 LT |
5599 | tp->cp_cmd &= ~PCIDAC; |
5600 | RTL_W16(CPlusCmd, tp->cp_cmd); | |
5601 | dev->features &= ~NETIF_F_HIGHDMA; | |
1da177e4 LT |
5602 | } |
5603 | ||
e6de30d6 | 5604 | rtl8169_hw_reset(tp); |
d03902b8 FR |
5605 | |
5606 | rtl8169_schedule_work(dev, rtl8169_reinit_task); | |
1da177e4 LT |
5607 | } |
5608 | ||
07d3f51f FR |
5609 | static void rtl8169_tx_interrupt(struct net_device *dev, |
5610 | struct rtl8169_private *tp, | |
5611 | void __iomem *ioaddr) | |
1da177e4 LT |
5612 | { |
5613 | unsigned int dirty_tx, tx_left; | |
5614 | ||
1da177e4 LT |
5615 | dirty_tx = tp->dirty_tx; |
5616 | smp_rmb(); | |
5617 | tx_left = tp->cur_tx - dirty_tx; | |
5618 | ||
5619 | while (tx_left > 0) { | |
5620 | unsigned int entry = dirty_tx % NUM_TX_DESC; | |
5621 | struct ring_info *tx_skb = tp->tx_skb + entry; | |
1da177e4 LT |
5622 | u32 status; |
5623 | ||
5624 | rmb(); | |
5625 | status = le32_to_cpu(tp->TxDescArray[entry].opts1); | |
5626 | if (status & DescOwn) | |
5627 | break; | |
5628 | ||
48addcc9 SG |
5629 | rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb, |
5630 | tp->TxDescArray + entry); | |
1da177e4 | 5631 | if (status & LastFrag) { |
cac4b22f SG |
5632 | dev->stats.tx_packets++; |
5633 | dev->stats.tx_bytes += tx_skb->skb->len; | |
87433bfc | 5634 | dev_kfree_skb(tx_skb->skb); |
1da177e4 LT |
5635 | tx_skb->skb = NULL; |
5636 | } | |
5637 | dirty_tx++; | |
5638 | tx_left--; | |
5639 | } | |
5640 | ||
5641 | if (tp->dirty_tx != dirty_tx) { | |
5642 | tp->dirty_tx = dirty_tx; | |
5643 | smp_wmb(); | |
5644 | if (netif_queue_stopped(dev) && | |
5645 | (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) { | |
5646 | netif_wake_queue(dev); | |
5647 | } | |
d78ae2dc FR |
5648 | /* |
5649 | * 8168 hack: TxPoll requests are lost when the Tx packets are | |
5650 | * too close. Let's kick an extra TxPoll request when a burst | |
5651 | * of start_xmit activity is detected (if it is not detected, | |
5652 | * it is slow enough). -- FR | |
5653 | */ | |
5654 | smp_rmb(); | |
5655 | if (tp->cur_tx != dirty_tx) | |
5656 | RTL_W8(TxPoll, NPQ); | |
1da177e4 LT |
5657 | } |
5658 | } | |
5659 | ||
126fa4b9 FR |
5660 | static inline int rtl8169_fragmented_frame(u32 status) |
5661 | { | |
5662 | return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag); | |
5663 | } | |
5664 | ||
adea1ac7 | 5665 | static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1) |
1da177e4 | 5666 | { |
1da177e4 LT |
5667 | u32 status = opts1 & RxProtoMask; |
5668 | ||
5669 | if (((status == RxProtoTCP) && !(opts1 & TCPFail)) || | |
d5d3ebe3 | 5670 | ((status == RxProtoUDP) && !(opts1 & UDPFail))) |
1da177e4 LT |
5671 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
5672 | else | |
bc8acf2c | 5673 | skb_checksum_none_assert(skb); |
1da177e4 LT |
5674 | } |
5675 | ||
6f0333b8 ED |
5676 | static struct sk_buff *rtl8169_try_rx_copy(void *data, |
5677 | struct rtl8169_private *tp, | |
5678 | int pkt_size, | |
5679 | dma_addr_t addr) | |
1da177e4 | 5680 | { |
b449655f | 5681 | struct sk_buff *skb; |
48addcc9 | 5682 | struct device *d = &tp->pci_dev->dev; |
b449655f | 5683 | |
6f0333b8 | 5684 | data = rtl8169_align(data); |
48addcc9 | 5685 | dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE); |
6f0333b8 ED |
5686 | prefetch(data); |
5687 | skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size); | |
5688 | if (skb) | |
5689 | memcpy(skb->data, data, pkt_size); | |
48addcc9 SG |
5690 | dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE); |
5691 | ||
6f0333b8 | 5692 | return skb; |
1da177e4 LT |
5693 | } |
5694 | ||
07d3f51f FR |
5695 | static int rtl8169_rx_interrupt(struct net_device *dev, |
5696 | struct rtl8169_private *tp, | |
bea3348e | 5697 | void __iomem *ioaddr, u32 budget) |
1da177e4 LT |
5698 | { |
5699 | unsigned int cur_rx, rx_left; | |
6f0333b8 | 5700 | unsigned int count; |
1da177e4 | 5701 | |
1da177e4 LT |
5702 | cur_rx = tp->cur_rx; |
5703 | rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx; | |
865c652d | 5704 | rx_left = min(rx_left, budget); |
1da177e4 | 5705 | |
4dcb7d33 | 5706 | for (; rx_left > 0; rx_left--, cur_rx++) { |
1da177e4 | 5707 | unsigned int entry = cur_rx % NUM_RX_DESC; |
126fa4b9 | 5708 | struct RxDesc *desc = tp->RxDescArray + entry; |
1da177e4 LT |
5709 | u32 status; |
5710 | ||
5711 | rmb(); | |
e03f33af | 5712 | status = le32_to_cpu(desc->opts1) & tp->opts1_mask; |
1da177e4 LT |
5713 | |
5714 | if (status & DescOwn) | |
5715 | break; | |
4dcb7d33 | 5716 | if (unlikely(status & RxRES)) { |
bf82c189 JP |
5717 | netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n", |
5718 | status); | |
cebf8cc7 | 5719 | dev->stats.rx_errors++; |
1da177e4 | 5720 | if (status & (RxRWT | RxRUNT)) |
cebf8cc7 | 5721 | dev->stats.rx_length_errors++; |
1da177e4 | 5722 | if (status & RxCRC) |
cebf8cc7 | 5723 | dev->stats.rx_crc_errors++; |
9dccf611 FR |
5724 | if (status & RxFOVF) { |
5725 | rtl8169_schedule_work(dev, rtl8169_reset_task); | |
cebf8cc7 | 5726 | dev->stats.rx_fifo_errors++; |
9dccf611 | 5727 | } |
6f0333b8 | 5728 | rtl8169_mark_to_asic(desc, rx_buf_sz); |
1da177e4 | 5729 | } else { |
6f0333b8 | 5730 | struct sk_buff *skb; |
b449655f | 5731 | dma_addr_t addr = le64_to_cpu(desc->addr); |
deb9d93c | 5732 | int pkt_size = (status & 0x00003fff) - 4; |
1da177e4 | 5733 | |
126fa4b9 FR |
5734 | /* |
5735 | * The driver does not support incoming fragmented | |
5736 | * frames. They are seen as a symptom of over-mtu | |
5737 | * sized frames. | |
5738 | */ | |
5739 | if (unlikely(rtl8169_fragmented_frame(status))) { | |
cebf8cc7 FR |
5740 | dev->stats.rx_dropped++; |
5741 | dev->stats.rx_length_errors++; | |
6f0333b8 | 5742 | rtl8169_mark_to_asic(desc, rx_buf_sz); |
4dcb7d33 | 5743 | continue; |
126fa4b9 FR |
5744 | } |
5745 | ||
6f0333b8 ED |
5746 | skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry], |
5747 | tp, pkt_size, addr); | |
5748 | rtl8169_mark_to_asic(desc, rx_buf_sz); | |
5749 | if (!skb) { | |
5750 | dev->stats.rx_dropped++; | |
5751 | continue; | |
1da177e4 LT |
5752 | } |
5753 | ||
adea1ac7 | 5754 | rtl8169_rx_csum(skb, status); |
1da177e4 LT |
5755 | skb_put(skb, pkt_size); |
5756 | skb->protocol = eth_type_trans(skb, dev); | |
5757 | ||
7a8fc77b FR |
5758 | rtl8169_rx_vlan_tag(desc, skb); |
5759 | ||
56de414c | 5760 | napi_gro_receive(&tp->napi, skb); |
1da177e4 | 5761 | |
cebf8cc7 FR |
5762 | dev->stats.rx_bytes += pkt_size; |
5763 | dev->stats.rx_packets++; | |
1da177e4 | 5764 | } |
6dccd16b FR |
5765 | |
5766 | /* Work around for AMD plateform. */ | |
95e0918d | 5767 | if ((desc->opts2 & cpu_to_le32(0xfffe000)) && |
6dccd16b FR |
5768 | (tp->mac_version == RTL_GIGA_MAC_VER_05)) { |
5769 | desc->opts2 = 0; | |
5770 | cur_rx++; | |
5771 | } | |
1da177e4 LT |
5772 | } |
5773 | ||
5774 | count = cur_rx - tp->cur_rx; | |
5775 | tp->cur_rx = cur_rx; | |
5776 | ||
6f0333b8 | 5777 | tp->dirty_rx += count; |
1da177e4 LT |
5778 | |
5779 | return count; | |
5780 | } | |
5781 | ||
07d3f51f | 5782 | static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance) |
1da177e4 | 5783 | { |
07d3f51f | 5784 | struct net_device *dev = dev_instance; |
1da177e4 | 5785 | struct rtl8169_private *tp = netdev_priv(dev); |
1da177e4 | 5786 | void __iomem *ioaddr = tp->mmio_addr; |
1da177e4 | 5787 | int handled = 0; |
865c652d | 5788 | int status; |
1da177e4 | 5789 | |
f11a377b DD |
5790 | /* loop handling interrupts until we have no new ones or |
5791 | * we hit a invalid/hotplug case. | |
5792 | */ | |
865c652d | 5793 | status = RTL_R16(IntrStatus); |
f11a377b DD |
5794 | while (status && status != 0xffff) { |
5795 | handled = 1; | |
1da177e4 | 5796 | |
f11a377b DD |
5797 | /* Handle all of the error cases first. These will reset |
5798 | * the chip, so just exit the loop. | |
5799 | */ | |
5800 | if (unlikely(!netif_running(dev))) { | |
92fc43b4 | 5801 | rtl8169_hw_reset(tp); |
f11a377b DD |
5802 | break; |
5803 | } | |
1da177e4 | 5804 | |
1519e57f FR |
5805 | if (unlikely(status & RxFIFOOver)) { |
5806 | switch (tp->mac_version) { | |
5807 | /* Work around for rx fifo overflow */ | |
5808 | case RTL_GIGA_MAC_VER_11: | |
5809 | case RTL_GIGA_MAC_VER_22: | |
5810 | case RTL_GIGA_MAC_VER_26: | |
5811 | netif_stop_queue(dev); | |
5812 | rtl8169_tx_timeout(dev); | |
5813 | goto done; | |
f60ac8e7 FR |
5814 | /* Testers needed. */ |
5815 | case RTL_GIGA_MAC_VER_17: | |
5816 | case RTL_GIGA_MAC_VER_19: | |
5817 | case RTL_GIGA_MAC_VER_20: | |
5818 | case RTL_GIGA_MAC_VER_21: | |
5819 | case RTL_GIGA_MAC_VER_23: | |
5820 | case RTL_GIGA_MAC_VER_24: | |
5821 | case RTL_GIGA_MAC_VER_27: | |
5822 | case RTL_GIGA_MAC_VER_28: | |
4804b3b3 | 5823 | case RTL_GIGA_MAC_VER_31: |
1519e57f FR |
5824 | /* Experimental science. Pktgen proof. */ |
5825 | case RTL_GIGA_MAC_VER_12: | |
5826 | case RTL_GIGA_MAC_VER_25: | |
5827 | if (status == RxFIFOOver) | |
5828 | goto done; | |
5829 | break; | |
5830 | default: | |
5831 | break; | |
5832 | } | |
f11a377b | 5833 | } |
1da177e4 | 5834 | |
f11a377b DD |
5835 | if (unlikely(status & SYSErr)) { |
5836 | rtl8169_pcierr_interrupt(dev); | |
5837 | break; | |
5838 | } | |
1da177e4 | 5839 | |
f11a377b | 5840 | if (status & LinkChg) |
e4fbce74 | 5841 | __rtl8169_check_link_status(dev, tp, ioaddr, true); |
0e485150 | 5842 | |
f11a377b DD |
5843 | /* We need to see the lastest version of tp->intr_mask to |
5844 | * avoid ignoring an MSI interrupt and having to wait for | |
5845 | * another event which may never come. | |
5846 | */ | |
5847 | smp_rmb(); | |
5848 | if (status & tp->intr_mask & tp->napi_event) { | |
5849 | RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event); | |
5850 | tp->intr_mask = ~tp->napi_event; | |
5851 | ||
5852 | if (likely(napi_schedule_prep(&tp->napi))) | |
5853 | __napi_schedule(&tp->napi); | |
bf82c189 JP |
5854 | else |
5855 | netif_info(tp, intr, dev, | |
5856 | "interrupt %04x in poll\n", status); | |
f11a377b | 5857 | } |
1da177e4 | 5858 | |
f11a377b DD |
5859 | /* We only get a new MSI interrupt when all active irq |
5860 | * sources on the chip have been acknowledged. So, ack | |
5861 | * everything we've seen and check if new sources have become | |
5862 | * active to avoid blocking all interrupts from the chip. | |
5863 | */ | |
5864 | RTL_W16(IntrStatus, | |
5865 | (status & RxFIFOOver) ? (status | RxOverflow) : status); | |
5866 | status = RTL_R16(IntrStatus); | |
865c652d | 5867 | } |
1519e57f | 5868 | done: |
1da177e4 LT |
5869 | return IRQ_RETVAL(handled); |
5870 | } | |
5871 | ||
bea3348e | 5872 | static int rtl8169_poll(struct napi_struct *napi, int budget) |
1da177e4 | 5873 | { |
bea3348e SH |
5874 | struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi); |
5875 | struct net_device *dev = tp->dev; | |
1da177e4 | 5876 | void __iomem *ioaddr = tp->mmio_addr; |
bea3348e | 5877 | int work_done; |
1da177e4 | 5878 | |
bea3348e | 5879 | work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget); |
1da177e4 LT |
5880 | rtl8169_tx_interrupt(dev, tp, ioaddr); |
5881 | ||
bea3348e | 5882 | if (work_done < budget) { |
288379f0 | 5883 | napi_complete(napi); |
f11a377b DD |
5884 | |
5885 | /* We need for force the visibility of tp->intr_mask | |
5886 | * for other CPUs, as we can loose an MSI interrupt | |
5887 | * and potentially wait for a retransmit timeout if we don't. | |
5888 | * The posted write to IntrMask is safe, as it will | |
5889 | * eventually make it to the chip and we won't loose anything | |
5890 | * until it does. | |
1da177e4 | 5891 | */ |
f11a377b | 5892 | tp->intr_mask = 0xffff; |
4c020a96 | 5893 | wmb(); |
0e485150 | 5894 | RTL_W16(IntrMask, tp->intr_event); |
1da177e4 LT |
5895 | } |
5896 | ||
bea3348e | 5897 | return work_done; |
1da177e4 | 5898 | } |
1da177e4 | 5899 | |
523a6094 FR |
5900 | static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr) |
5901 | { | |
5902 | struct rtl8169_private *tp = netdev_priv(dev); | |
5903 | ||
5904 | if (tp->mac_version > RTL_GIGA_MAC_VER_06) | |
5905 | return; | |
5906 | ||
5907 | dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff); | |
5908 | RTL_W32(RxMissed, 0); | |
5909 | } | |
5910 | ||
1da177e4 LT |
5911 | static void rtl8169_down(struct net_device *dev) |
5912 | { | |
5913 | struct rtl8169_private *tp = netdev_priv(dev); | |
5914 | void __iomem *ioaddr = tp->mmio_addr; | |
1da177e4 | 5915 | |
4876cc1e | 5916 | del_timer_sync(&tp->timer); |
1da177e4 LT |
5917 | |
5918 | netif_stop_queue(dev); | |
5919 | ||
93dd79e8 | 5920 | napi_disable(&tp->napi); |
93dd79e8 | 5921 | |
1da177e4 LT |
5922 | spin_lock_irq(&tp->lock); |
5923 | ||
92fc43b4 | 5924 | rtl8169_hw_reset(tp); |
323bb685 SG |
5925 | /* |
5926 | * At this point device interrupts can not be enabled in any function, | |
5927 | * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task, | |
5928 | * rtl8169_reinit_task) and napi is disabled (rtl8169_poll). | |
5929 | */ | |
523a6094 | 5930 | rtl8169_rx_missed(dev, ioaddr); |
1da177e4 LT |
5931 | |
5932 | spin_unlock_irq(&tp->lock); | |
5933 | ||
5934 | synchronize_irq(dev->irq); | |
5935 | ||
1da177e4 | 5936 | /* Give a racing hard_start_xmit a few cycles to complete. */ |
fbd568a3 | 5937 | synchronize_sched(); /* FIXME: should this be synchronize_irq()? */ |
1da177e4 | 5938 | |
1da177e4 LT |
5939 | rtl8169_tx_clear(tp); |
5940 | ||
5941 | rtl8169_rx_clear(tp); | |
065c27c1 | 5942 | |
5943 | rtl_pll_power_down(tp); | |
1da177e4 LT |
5944 | } |
5945 | ||
5946 | static int rtl8169_close(struct net_device *dev) | |
5947 | { | |
5948 | struct rtl8169_private *tp = netdev_priv(dev); | |
5949 | struct pci_dev *pdev = tp->pci_dev; | |
5950 | ||
e1759441 RW |
5951 | pm_runtime_get_sync(&pdev->dev); |
5952 | ||
cecb5fd7 | 5953 | /* Update counters before going down */ |
355423d0 IV |
5954 | rtl8169_update_counters(dev); |
5955 | ||
1da177e4 LT |
5956 | rtl8169_down(dev); |
5957 | ||
5958 | free_irq(dev->irq, dev); | |
5959 | ||
82553bb6 SG |
5960 | dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, |
5961 | tp->RxPhyAddr); | |
5962 | dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, | |
5963 | tp->TxPhyAddr); | |
1da177e4 LT |
5964 | tp->TxDescArray = NULL; |
5965 | tp->RxDescArray = NULL; | |
5966 | ||
e1759441 RW |
5967 | pm_runtime_put_sync(&pdev->dev); |
5968 | ||
1da177e4 LT |
5969 | return 0; |
5970 | } | |
5971 | ||
07ce4064 | 5972 | static void rtl_set_rx_mode(struct net_device *dev) |
1da177e4 LT |
5973 | { |
5974 | struct rtl8169_private *tp = netdev_priv(dev); | |
5975 | void __iomem *ioaddr = tp->mmio_addr; | |
5976 | unsigned long flags; | |
5977 | u32 mc_filter[2]; /* Multicast hash filter */ | |
07d3f51f | 5978 | int rx_mode; |
1da177e4 LT |
5979 | u32 tmp = 0; |
5980 | ||
5981 | if (dev->flags & IFF_PROMISC) { | |
5982 | /* Unconditionally log net taps. */ | |
bf82c189 | 5983 | netif_notice(tp, link, dev, "Promiscuous mode enabled\n"); |
1da177e4 LT |
5984 | rx_mode = |
5985 | AcceptBroadcast | AcceptMulticast | AcceptMyPhys | | |
5986 | AcceptAllPhys; | |
5987 | mc_filter[1] = mc_filter[0] = 0xffffffff; | |
4cd24eaf | 5988 | } else if ((netdev_mc_count(dev) > multicast_filter_limit) || |
8e95a202 | 5989 | (dev->flags & IFF_ALLMULTI)) { |
1da177e4 LT |
5990 | /* Too many to filter perfectly -- accept all multicasts. */ |
5991 | rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys; | |
5992 | mc_filter[1] = mc_filter[0] = 0xffffffff; | |
5993 | } else { | |
22bedad3 | 5994 | struct netdev_hw_addr *ha; |
07d3f51f | 5995 | |
1da177e4 LT |
5996 | rx_mode = AcceptBroadcast | AcceptMyPhys; |
5997 | mc_filter[1] = mc_filter[0] = 0; | |
22bedad3 JP |
5998 | netdev_for_each_mc_addr(ha, dev) { |
5999 | int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; | |
1da177e4 LT |
6000 | mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); |
6001 | rx_mode |= AcceptMulticast; | |
6002 | } | |
6003 | } | |
6004 | ||
6005 | spin_lock_irqsave(&tp->lock, flags); | |
6006 | ||
1687b566 | 6007 | tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode; |
1da177e4 | 6008 | |
f887cce8 | 6009 | if (tp->mac_version > RTL_GIGA_MAC_VER_06) { |
1087f4f4 FR |
6010 | u32 data = mc_filter[0]; |
6011 | ||
6012 | mc_filter[0] = swab32(mc_filter[1]); | |
6013 | mc_filter[1] = swab32(data); | |
bcf0bf90 FR |
6014 | } |
6015 | ||
1da177e4 | 6016 | RTL_W32(MAR0 + 4, mc_filter[1]); |
78f1cd02 | 6017 | RTL_W32(MAR0 + 0, mc_filter[0]); |
1da177e4 | 6018 | |
57a9f236 FR |
6019 | RTL_W32(RxConfig, tmp); |
6020 | ||
1da177e4 LT |
6021 | spin_unlock_irqrestore(&tp->lock, flags); |
6022 | } | |
6023 | ||
6024 | /** | |
6025 | * rtl8169_get_stats - Get rtl8169 read/write statistics | |
6026 | * @dev: The Ethernet Device to get statistics for | |
6027 | * | |
6028 | * Get TX/RX statistics for rtl8169 | |
6029 | */ | |
6030 | static struct net_device_stats *rtl8169_get_stats(struct net_device *dev) | |
6031 | { | |
6032 | struct rtl8169_private *tp = netdev_priv(dev); | |
6033 | void __iomem *ioaddr = tp->mmio_addr; | |
6034 | unsigned long flags; | |
6035 | ||
6036 | if (netif_running(dev)) { | |
6037 | spin_lock_irqsave(&tp->lock, flags); | |
523a6094 | 6038 | rtl8169_rx_missed(dev, ioaddr); |
1da177e4 LT |
6039 | spin_unlock_irqrestore(&tp->lock, flags); |
6040 | } | |
5b0384f4 | 6041 | |
cebf8cc7 | 6042 | return &dev->stats; |
1da177e4 LT |
6043 | } |
6044 | ||
861ab440 | 6045 | static void rtl8169_net_suspend(struct net_device *dev) |
5d06a99f | 6046 | { |
065c27c1 | 6047 | struct rtl8169_private *tp = netdev_priv(dev); |
6048 | ||
5d06a99f | 6049 | if (!netif_running(dev)) |
861ab440 | 6050 | return; |
5d06a99f | 6051 | |
065c27c1 | 6052 | rtl_pll_power_down(tp); |
6053 | ||
5d06a99f FR |
6054 | netif_device_detach(dev); |
6055 | netif_stop_queue(dev); | |
861ab440 RW |
6056 | } |
6057 | ||
6058 | #ifdef CONFIG_PM | |
6059 | ||
6060 | static int rtl8169_suspend(struct device *device) | |
6061 | { | |
6062 | struct pci_dev *pdev = to_pci_dev(device); | |
6063 | struct net_device *dev = pci_get_drvdata(pdev); | |
5d06a99f | 6064 | |
861ab440 | 6065 | rtl8169_net_suspend(dev); |
1371fa6d | 6066 | |
5d06a99f FR |
6067 | return 0; |
6068 | } | |
6069 | ||
e1759441 RW |
6070 | static void __rtl8169_resume(struct net_device *dev) |
6071 | { | |
065c27c1 | 6072 | struct rtl8169_private *tp = netdev_priv(dev); |
6073 | ||
e1759441 | 6074 | netif_device_attach(dev); |
065c27c1 | 6075 | |
6076 | rtl_pll_power_up(tp); | |
6077 | ||
e1759441 RW |
6078 | rtl8169_schedule_work(dev, rtl8169_reset_task); |
6079 | } | |
6080 | ||
861ab440 | 6081 | static int rtl8169_resume(struct device *device) |
5d06a99f | 6082 | { |
861ab440 | 6083 | struct pci_dev *pdev = to_pci_dev(device); |
5d06a99f | 6084 | struct net_device *dev = pci_get_drvdata(pdev); |
fccec10b SG |
6085 | struct rtl8169_private *tp = netdev_priv(dev); |
6086 | ||
6087 | rtl8169_init_phy(dev, tp); | |
5d06a99f | 6088 | |
e1759441 RW |
6089 | if (netif_running(dev)) |
6090 | __rtl8169_resume(dev); | |
5d06a99f | 6091 | |
e1759441 RW |
6092 | return 0; |
6093 | } | |
6094 | ||
6095 | static int rtl8169_runtime_suspend(struct device *device) | |
6096 | { | |
6097 | struct pci_dev *pdev = to_pci_dev(device); | |
6098 | struct net_device *dev = pci_get_drvdata(pdev); | |
6099 | struct rtl8169_private *tp = netdev_priv(dev); | |
6100 | ||
6101 | if (!tp->TxDescArray) | |
6102 | return 0; | |
6103 | ||
6104 | spin_lock_irq(&tp->lock); | |
6105 | tp->saved_wolopts = __rtl8169_get_wol(tp); | |
6106 | __rtl8169_set_wol(tp, WAKE_ANY); | |
6107 | spin_unlock_irq(&tp->lock); | |
6108 | ||
6109 | rtl8169_net_suspend(dev); | |
6110 | ||
6111 | return 0; | |
6112 | } | |
6113 | ||
6114 | static int rtl8169_runtime_resume(struct device *device) | |
6115 | { | |
6116 | struct pci_dev *pdev = to_pci_dev(device); | |
6117 | struct net_device *dev = pci_get_drvdata(pdev); | |
6118 | struct rtl8169_private *tp = netdev_priv(dev); | |
6119 | ||
6120 | if (!tp->TxDescArray) | |
6121 | return 0; | |
6122 | ||
6123 | spin_lock_irq(&tp->lock); | |
6124 | __rtl8169_set_wol(tp, tp->saved_wolopts); | |
6125 | tp->saved_wolopts = 0; | |
6126 | spin_unlock_irq(&tp->lock); | |
6127 | ||
fccec10b SG |
6128 | rtl8169_init_phy(dev, tp); |
6129 | ||
e1759441 | 6130 | __rtl8169_resume(dev); |
5d06a99f | 6131 | |
5d06a99f FR |
6132 | return 0; |
6133 | } | |
6134 | ||
e1759441 RW |
6135 | static int rtl8169_runtime_idle(struct device *device) |
6136 | { | |
6137 | struct pci_dev *pdev = to_pci_dev(device); | |
6138 | struct net_device *dev = pci_get_drvdata(pdev); | |
6139 | struct rtl8169_private *tp = netdev_priv(dev); | |
6140 | ||
e4fbce74 | 6141 | return tp->TxDescArray ? -EBUSY : 0; |
e1759441 RW |
6142 | } |
6143 | ||
47145210 | 6144 | static const struct dev_pm_ops rtl8169_pm_ops = { |
cecb5fd7 FR |
6145 | .suspend = rtl8169_suspend, |
6146 | .resume = rtl8169_resume, | |
6147 | .freeze = rtl8169_suspend, | |
6148 | .thaw = rtl8169_resume, | |
6149 | .poweroff = rtl8169_suspend, | |
6150 | .restore = rtl8169_resume, | |
6151 | .runtime_suspend = rtl8169_runtime_suspend, | |
6152 | .runtime_resume = rtl8169_runtime_resume, | |
6153 | .runtime_idle = rtl8169_runtime_idle, | |
861ab440 RW |
6154 | }; |
6155 | ||
6156 | #define RTL8169_PM_OPS (&rtl8169_pm_ops) | |
6157 | ||
6158 | #else /* !CONFIG_PM */ | |
6159 | ||
6160 | #define RTL8169_PM_OPS NULL | |
6161 | ||
6162 | #endif /* !CONFIG_PM */ | |
6163 | ||
1765f95d FR |
6164 | static void rtl_shutdown(struct pci_dev *pdev) |
6165 | { | |
861ab440 | 6166 | struct net_device *dev = pci_get_drvdata(pdev); |
4bb3f522 | 6167 | struct rtl8169_private *tp = netdev_priv(dev); |
6168 | void __iomem *ioaddr = tp->mmio_addr; | |
861ab440 RW |
6169 | |
6170 | rtl8169_net_suspend(dev); | |
1765f95d | 6171 | |
cecb5fd7 | 6172 | /* Restore original MAC address */ |
cc098dc7 IV |
6173 | rtl_rar_set(tp, dev->perm_addr); |
6174 | ||
4bb3f522 | 6175 | spin_lock_irq(&tp->lock); |
6176 | ||
92fc43b4 | 6177 | rtl8169_hw_reset(tp); |
4bb3f522 | 6178 | |
6179 | spin_unlock_irq(&tp->lock); | |
6180 | ||
861ab440 | 6181 | if (system_state == SYSTEM_POWER_OFF) { |
aaa89c08 HW |
6182 | /* WoL fails with 8168b when the receiver is disabled. */ |
6183 | if ((tp->mac_version == RTL_GIGA_MAC_VER_11 || | |
6184 | tp->mac_version == RTL_GIGA_MAC_VER_12 || | |
6185 | tp->mac_version == RTL_GIGA_MAC_VER_17) && | |
6186 | (tp->features & RTL_FEATURE_WOL)) { | |
ca52efd5 | 6187 | pci_clear_master(pdev); |
6188 | ||
6189 | RTL_W8(ChipCmd, CmdRxEnb); | |
6190 | /* PCI commit */ | |
6191 | RTL_R8(ChipCmd); | |
6192 | } | |
6193 | ||
861ab440 RW |
6194 | pci_wake_from_d3(pdev, true); |
6195 | pci_set_power_state(pdev, PCI_D3hot); | |
6196 | } | |
6197 | } | |
5d06a99f | 6198 | |
1da177e4 LT |
6199 | static struct pci_driver rtl8169_pci_driver = { |
6200 | .name = MODULENAME, | |
6201 | .id_table = rtl8169_pci_tbl, | |
6202 | .probe = rtl8169_init_one, | |
6203 | .remove = __devexit_p(rtl8169_remove_one), | |
1765f95d | 6204 | .shutdown = rtl_shutdown, |
861ab440 | 6205 | .driver.pm = RTL8169_PM_OPS, |
1da177e4 LT |
6206 | }; |
6207 | ||
07d3f51f | 6208 | static int __init rtl8169_init_module(void) |
1da177e4 | 6209 | { |
29917620 | 6210 | return pci_register_driver(&rtl8169_pci_driver); |
1da177e4 LT |
6211 | } |
6212 | ||
07d3f51f | 6213 | static void __exit rtl8169_cleanup_module(void) |
1da177e4 LT |
6214 | { |
6215 | pci_unregister_driver(&rtl8169_pci_driver); | |
6216 | } | |
6217 | ||
6218 | module_init(rtl8169_init_module); | |
6219 | module_exit(rtl8169_cleanup_module); |