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r8169: move the driver removal method to the end of the driver file.
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / realtek / r8169.c
CommitLineData
1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
18#include <linux/mii.h>
19#include <linux/if_vlan.h>
20#include <linux/crc32.h>
21#include <linux/in.h>
22#include <linux/ip.h>
23#include <linux/tcp.h>
24#include <linux/init.h>
a6b7a407 25#include <linux/interrupt.h>
1da177e4 26#include <linux/dma-mapping.h>
e1759441 27#include <linux/pm_runtime.h>
bca03d5f 28#include <linux/firmware.h>
ba04c7c9 29#include <linux/pci-aspm.h>
70c71606 30#include <linux/prefetch.h>
1da177e4 31
99f252b0 32#include <asm/system.h>
1da177e4
LT		 33#include <asm/io.h>
34#include <asm/irq.h>
35
865c652d 36#define RTL8169_VERSION "2.3LK-NAPI"
1da177e4
LT		 37#define MODULENAME "r8169"
38#define PFX MODULENAME ": "
39
bca03d5f 40#define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
41#define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
01dc7fec 42#define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
43#define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
70090424 44#define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
c2218925
HW		 45#define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
46#define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
5a5e4443 47#define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
bca03d5f 48
1da177e4
LT		 49#ifdef RTL8169_DEBUG
50#define assert(expr) \
5b0384f4
FR		 51 if (!(expr)) { \
52 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
b39d66a8 53 #expr,__FILE__,__func__,__LINE__); \
5b0384f4 54 }
06fa7358
JP		 55#define dprintk(fmt, args...) \
56 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
1da177e4
LT		 57#else
58#define assert(expr) do {} while (0)
59#define dprintk(fmt, args...) do {} while (0)
60#endif /* RTL8169_DEBUG */
61
b57b7e5a 62#define R8169_MSG_DEFAULT \
f0e837d9 63 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 64
1da177e4
LT		 65#define TX_BUFFS_AVAIL(tp) \
66 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
67
1da177e4
LT		 68/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
69 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 70static const int multicast_filter_limit = 32;
1da177e4 71
9c14ceaf 72#define MAX_READ_REQUEST_SHIFT 12
1da177e4 73#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
1da177e4
LT		 74#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
75#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
76
77#define R8169_REGS_SIZE 256
78#define R8169_NAPI_WEIGHT 64
79#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
80#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
81#define RX_BUF_SIZE 1536 /* Rx Buffer size */
82#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
83#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
84
85#define RTL8169_TX_TIMEOUT (6*HZ)
86#define RTL8169_PHY_TIMEOUT (10*HZ)
87
ea8dbdd1 88#define RTL_EEPROM_SIG cpu_to_le32(0x8129)
89#define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
e1564ec9
FR		 90#define RTL_EEPROM_SIG_ADDR 0x0000
91
1da177e4
LT		 92/* write/read MMIO register */
93#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
94#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
95#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
96#define RTL_R8(reg) readb (ioaddr + (reg))
97#define RTL_R16(reg) readw (ioaddr + (reg))
06f555f3 98#define RTL_R32(reg) readl (ioaddr + (reg))
1da177e4
LT		 99
100enum mac_version {
85bffe6c
FR		 101 RTL_GIGA_MAC_VER_01 = 0,
102 RTL_GIGA_MAC_VER_02,
103 RTL_GIGA_MAC_VER_03,
104 RTL_GIGA_MAC_VER_04,
105 RTL_GIGA_MAC_VER_05,
106 RTL_GIGA_MAC_VER_06,
107 RTL_GIGA_MAC_VER_07,
108 RTL_GIGA_MAC_VER_08,
109 RTL_GIGA_MAC_VER_09,
110 RTL_GIGA_MAC_VER_10,
111 RTL_GIGA_MAC_VER_11,
112 RTL_GIGA_MAC_VER_12,
113 RTL_GIGA_MAC_VER_13,
114 RTL_GIGA_MAC_VER_14,
115 RTL_GIGA_MAC_VER_15,
116 RTL_GIGA_MAC_VER_16,
117 RTL_GIGA_MAC_VER_17,
118 RTL_GIGA_MAC_VER_18,
119 RTL_GIGA_MAC_VER_19,
120 RTL_GIGA_MAC_VER_20,
121 RTL_GIGA_MAC_VER_21,
122 RTL_GIGA_MAC_VER_22,
123 RTL_GIGA_MAC_VER_23,
124 RTL_GIGA_MAC_VER_24,
125 RTL_GIGA_MAC_VER_25,
126 RTL_GIGA_MAC_VER_26,
127 RTL_GIGA_MAC_VER_27,
128 RTL_GIGA_MAC_VER_28,
129 RTL_GIGA_MAC_VER_29,
130 RTL_GIGA_MAC_VER_30,
131 RTL_GIGA_MAC_VER_31,
132 RTL_GIGA_MAC_VER_32,
133 RTL_GIGA_MAC_VER_33,
70090424 134 RTL_GIGA_MAC_VER_34,
c2218925
HW		 135 RTL_GIGA_MAC_VER_35,
136 RTL_GIGA_MAC_VER_36,
85bffe6c 137 RTL_GIGA_MAC_NONE = 0xff,
1da177e4
LT		 138};
139
2b7b4318
FR		 140enum rtl_tx_desc_version {
141 RTL_TD_0 = 0,
142 RTL_TD_1 = 1,
143};
144
d58d46b5
FR		 145#define JUMBO_1K ETH_DATA_LEN
146#define JUMBO_4K (4*1024 - ETH_HLEN - 2)
147#define JUMBO_6K (6*1024 - ETH_HLEN - 2)
148#define JUMBO_7K (7*1024 - ETH_HLEN - 2)
149#define JUMBO_9K (9*1024 - ETH_HLEN - 2)
150
151#define _R(NAME,TD,FW,SZ,B) { \
152 .name = NAME, \
153 .txd_version = TD, \
154 .fw_name = FW, \
155 .jumbo_max = SZ, \
156 .jumbo_tx_csum = B \
157}
1da177e4 158
3c6bee1d 159static const struct {
1da177e4 160 const char *name;
2b7b4318 161 enum rtl_tx_desc_version txd_version;
953a12cc 162 const char *fw_name;
d58d46b5
FR		 163 u16 jumbo_max;
164 bool jumbo_tx_csum;
85bffe6c
FR		 165} rtl_chip_infos[] = {
166 /* PCI devices. */
167 [RTL_GIGA_MAC_VER_01] =
d58d46b5 168 _R("RTL8169", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 169 [RTL_GIGA_MAC_VER_02] =
d58d46b5 170 _R("RTL8169s", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 171 [RTL_GIGA_MAC_VER_03] =
d58d46b5 172 _R("RTL8110s", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 173 [RTL_GIGA_MAC_VER_04] =
d58d46b5 174 _R("RTL8169sb/8110sb", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 175 [RTL_GIGA_MAC_VER_05] =
d58d46b5 176 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 177 [RTL_GIGA_MAC_VER_06] =
d58d46b5 178 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c
FR		 179 /* PCI-E devices. */
180 [RTL_GIGA_MAC_VER_07] =
d58d46b5 181 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
85bffe6c 182 [RTL_GIGA_MAC_VER_08] =
d58d46b5 183 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
85bffe6c 184 [RTL_GIGA_MAC_VER_09] =
d58d46b5 185 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
85bffe6c 186 [RTL_GIGA_MAC_VER_10] =
d58d46b5 187 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 188 [RTL_GIGA_MAC_VER_11] =
d58d46b5 189 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
85bffe6c 190 [RTL_GIGA_MAC_VER_12] =
d58d46b5 191 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
85bffe6c 192 [RTL_GIGA_MAC_VER_13] =
d58d46b5 193 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 194 [RTL_GIGA_MAC_VER_14] =
d58d46b5 195 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 196 [RTL_GIGA_MAC_VER_15] =
d58d46b5 197 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 198 [RTL_GIGA_MAC_VER_16] =
d58d46b5 199 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 200 [RTL_GIGA_MAC_VER_17] =
d58d46b5 201 _R("RTL8168b/8111b", RTL_TD_1, NULL, JUMBO_4K, false),
85bffe6c 202 [RTL_GIGA_MAC_VER_18] =
d58d46b5 203 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 204 [RTL_GIGA_MAC_VER_19] =
d58d46b5 205 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 206 [RTL_GIGA_MAC_VER_20] =
d58d46b5 207 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 208 [RTL_GIGA_MAC_VER_21] =
d58d46b5 209 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 210 [RTL_GIGA_MAC_VER_22] =
d58d46b5 211 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 212 [RTL_GIGA_MAC_VER_23] =
d58d46b5 213 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 214 [RTL_GIGA_MAC_VER_24] =
d58d46b5 215 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 216 [RTL_GIGA_MAC_VER_25] =
d58d46b5
FR		 217 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1,
218 JUMBO_9K, false),
85bffe6c 219 [RTL_GIGA_MAC_VER_26] =
d58d46b5
FR		 220 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2,
221 JUMBO_9K, false),
85bffe6c 222 [RTL_GIGA_MAC_VER_27] =
d58d46b5 223 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
85bffe6c 224 [RTL_GIGA_MAC_VER_28] =
d58d46b5 225 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
85bffe6c 226 [RTL_GIGA_MAC_VER_29] =
d58d46b5
FR		 227 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
228 JUMBO_1K, true),
85bffe6c 229 [RTL_GIGA_MAC_VER_30] =
d58d46b5
FR		 230 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
231 JUMBO_1K, true),
85bffe6c 232 [RTL_GIGA_MAC_VER_31] =
d58d46b5 233 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
85bffe6c 234 [RTL_GIGA_MAC_VER_32] =
d58d46b5
FR		 235 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1,
236 JUMBO_9K, false),
85bffe6c 237 [RTL_GIGA_MAC_VER_33] =
d58d46b5
FR		 238 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2,
239 JUMBO_9K, false),
70090424 240 [RTL_GIGA_MAC_VER_34] =
d58d46b5
FR		 241 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
242 JUMBO_9K, false),
c2218925 243 [RTL_GIGA_MAC_VER_35] =
d58d46b5
FR		 244 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_1,
245 JUMBO_9K, false),
c2218925 246 [RTL_GIGA_MAC_VER_36] =
d58d46b5
FR		 247 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_2,
248 JUMBO_9K, false),
953a12cc 249};
85bffe6c 250#undef _R
953a12cc 251
bcf0bf90
FR		 252enum cfg_version {
253 RTL_CFG_0 = 0x00,
254 RTL_CFG_1,
255 RTL_CFG_2
256};
257
07ce4064
FR		 258static void rtl_hw_start_8169(struct net_device *);
259static void rtl_hw_start_8168(struct net_device *);
260static void rtl_hw_start_8101(struct net_device *);
261
a3aa1884 262static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
bcf0bf90 263 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 264 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
d81bf551 265 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 266 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90
FR		 267 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
268 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
93a3aa25 269 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 },
bc1660b5 270 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 271 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
272 { PCI_VENDOR_ID_LINKSYS, 0x1032,
273 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
11d2e282
CM		 274 { 0x0001, 0x8168,
275 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
1da177e4
LT		 276 {0,},
277};
278
279MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
280
6f0333b8 281static int rx_buf_sz = 16383;
4300e8c7 282static int use_dac;
b57b7e5a
SH		 283static struct {
284 u32 msg_enable;
285} debug = { -1 };
1da177e4 286
07d3f51f
FR		 287enum rtl_registers {
288 MAC0 = 0, /* Ethernet hardware address. */
773d2021 289 MAC4 = 4,
07d3f51f
FR		 290 MAR0 = 8, /* Multicast filter. */
291 CounterAddrLow = 0x10,
292 CounterAddrHigh = 0x14,
293 TxDescStartAddrLow = 0x20,
294 TxDescStartAddrHigh = 0x24,
295 TxHDescStartAddrLow = 0x28,
296 TxHDescStartAddrHigh = 0x2c,
297 FLASH = 0x30,
298 ERSR = 0x36,
299 ChipCmd = 0x37,
300 TxPoll = 0x38,
301 IntrMask = 0x3c,
302 IntrStatus = 0x3e,
4f6b00e5 303
07d3f51f 304 TxConfig = 0x40,
4f6b00e5
HW		 305#define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
306#define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
2b7b4318 307
4f6b00e5
HW		 308 RxConfig = 0x44,
309#define RX128_INT_EN (1 << 15) /* 8111c and later */
310#define RX_MULTI_EN (1 << 14) /* 8111c only */
311#define RXCFG_FIFO_SHIFT 13
312 /* No threshold before first PCI xfer */
313#define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
314#define RXCFG_DMA_SHIFT 8
315 /* Unlimited maximum PCI burst. */
316#define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
2b7b4318 317
07d3f51f
FR		 318 RxMissed = 0x4c,
319 Cfg9346 = 0x50,
320 Config0 = 0x51,
321 Config1 = 0x52,
322 Config2 = 0x53,
323 Config3 = 0x54,
324 Config4 = 0x55,
325 Config5 = 0x56,
326 MultiIntr = 0x5c,
327 PHYAR = 0x60,
07d3f51f
FR		 328 PHYstatus = 0x6c,
329 RxMaxSize = 0xda,
330 CPlusCmd = 0xe0,
331 IntrMitigate = 0xe2,
332 RxDescAddrLow = 0xe4,
333 RxDescAddrHigh = 0xe8,
f0298f81 334 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
335
336#define NoEarlyTx 0x3f /* Max value : no early transmit. */
337
338 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
339
340#define TxPacketMax (8064 >> 7)
3090bd9a 341#define EarlySize 0x27
f0298f81 342
07d3f51f
FR		 343 FuncEvent = 0xf0,
344 FuncEventMask = 0xf4,
345 FuncPresetState = 0xf8,
346 FuncForceEvent = 0xfc,
1da177e4
LT		 347};
348
f162a5d1
FR		 349enum rtl8110_registers {
350 TBICSR = 0x64,
351 TBI_ANAR = 0x68,
352 TBI_LPAR = 0x6a,
353};
354
355enum rtl8168_8101_registers {
356 CSIDR = 0x64,
357 CSIAR = 0x68,
358#define CSIAR_FLAG 0x80000000
359#define CSIAR_WRITE_CMD 0x80000000
360#define CSIAR_BYTE_ENABLE 0x0f
361#define CSIAR_BYTE_ENABLE_SHIFT 12
362#define CSIAR_ADDR_MASK 0x0fff
065c27c1 363 PMCH = 0x6f,
f162a5d1
FR		 364 EPHYAR = 0x80,
365#define EPHYAR_FLAG 0x80000000
366#define EPHYAR_WRITE_CMD 0x80000000
367#define EPHYAR_REG_MASK 0x1f
368#define EPHYAR_REG_SHIFT 16
369#define EPHYAR_DATA_MASK 0xffff
5a5e4443 370 DLLPR = 0xd0,
4f6b00e5 371#define PFM_EN (1 << 6)
f162a5d1
FR		 372 DBG_REG = 0xd1,
373#define FIX_NAK_1 (1 << 4)
374#define FIX_NAK_2 (1 << 3)
5a5e4443
HW		 375 TWSI = 0xd2,
376 MCU = 0xd3,
4f6b00e5 377#define NOW_IS_OOB (1 << 7)
5a5e4443
HW		 378#define EN_NDP (1 << 3)
379#define EN_OOB_RESET (1 << 2)
daf9df6d 380 EFUSEAR = 0xdc,
381#define EFUSEAR_FLAG 0x80000000
382#define EFUSEAR_WRITE_CMD 0x80000000
383#define EFUSEAR_READ_CMD 0x00000000
384#define EFUSEAR_REG_MASK 0x03ff
385#define EFUSEAR_REG_SHIFT 8
386#define EFUSEAR_DATA_MASK 0xff
f162a5d1
FR		 387};
388
c0e45c1c 389enum rtl8168_registers {
4f6b00e5
HW		 390 LED_FREQ = 0x1a,
391 EEE_LED = 0x1b,
b646d900 392 ERIDR = 0x70,
393 ERIAR = 0x74,
394#define ERIAR_FLAG 0x80000000
395#define ERIAR_WRITE_CMD 0x80000000
396#define ERIAR_READ_CMD 0x00000000
397#define ERIAR_ADDR_BYTE_ALIGN 4
b646d900 398#define ERIAR_TYPE_SHIFT 16
4f6b00e5
HW		 399#define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
400#define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
401#define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
402#define ERIAR_MASK_SHIFT 12
403#define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
404#define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
405#define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
c0e45c1c 406 EPHY_RXER_NUM = 0x7c,
407 OCPDR = 0xb0, /* OCP GPHY access */
408#define OCPDR_WRITE_CMD 0x80000000
409#define OCPDR_READ_CMD 0x00000000
410#define OCPDR_REG_MASK 0x7f
411#define OCPDR_GPHY_REG_SHIFT 16
412#define OCPDR_DATA_MASK 0xffff
413 OCPAR = 0xb4,
414#define OCPAR_FLAG 0x80000000
415#define OCPAR_GPHY_WRITE_CMD 0x8000f060
416#define OCPAR_GPHY_READ_CMD 0x0000f060
01dc7fec 417 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
418 MISC = 0xf0, /* 8168e only. */
cecb5fd7 419#define TXPLA_RST (1 << 29)
4f6b00e5 420#define PWM_EN (1 << 22)
c0e45c1c 421};
422
07d3f51f 423enum rtl_register_content {
1da177e4 424 /* InterruptStatusBits */
07d3f51f
FR		 425 SYSErr = 0x8000,
426 PCSTimeout = 0x4000,
427 SWInt = 0x0100,
428 TxDescUnavail = 0x0080,
429 RxFIFOOver = 0x0040,
430 LinkChg = 0x0020,
431 RxOverflow = 0x0010,
432 TxErr = 0x0008,
433 TxOK = 0x0004,
434 RxErr = 0x0002,
435 RxOK = 0x0001,
1da177e4
LT		 436
437 /* RxStatusDesc */
e03f33af 438 RxBOVF = (1 << 24),
9dccf611
FR		 439 RxFOVF = (1 << 23),
440 RxRWT = (1 << 22),
441 RxRES = (1 << 21),
442 RxRUNT = (1 << 20),
443 RxCRC = (1 << 19),
1da177e4
LT		 444
445 /* ChipCmdBits */
4f6b00e5 446 StopReq = 0x80,
07d3f51f
FR		 447 CmdReset = 0x10,
448 CmdRxEnb = 0x08,
449 CmdTxEnb = 0x04,
450 RxBufEmpty = 0x01,
1da177e4 451
275391a4
FR		 452 /* TXPoll register p.5 */
453 HPQ = 0x80, /* Poll cmd on the high prio queue */
454 NPQ = 0x40, /* Poll cmd on the low prio queue */
455 FSWInt = 0x01, /* Forced software interrupt */
456
1da177e4 457 /* Cfg9346Bits */
07d3f51f
FR		 458 Cfg9346_Lock = 0x00,
459 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 460
461 /* rx_mode_bits */
07d3f51f
FR		 462 AcceptErr = 0x20,
463 AcceptRunt = 0x10,
464 AcceptBroadcast = 0x08,
465 AcceptMulticast = 0x04,
466 AcceptMyPhys = 0x02,
467 AcceptAllPhys = 0x01,
1687b566 468#define RX_CONFIG_ACCEPT_MASK 0x3f
1da177e4 469
1da177e4
LT		 470 /* TxConfigBits */
471 TxInterFrameGapShift = 24,
472 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
473
5d06a99f 474 /* Config1 register p.24 */
f162a5d1
FR		 475 LEDS1 = (1 << 7),
476 LEDS0 = (1 << 6),
f162a5d1
FR		 477 Speed_down = (1 << 4),
478 MEMMAP = (1 << 3),
479 IOMAP = (1 << 2),
480 VPD = (1 << 1),
5d06a99f
FR		 481 PMEnable = (1 << 0), /* Power Management Enable */
482
6dccd16b 483 /* Config2 register p. 25 */
2ca6cf06 484 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
6dccd16b
FR		 485 PCI_Clock_66MHz = 0x01,
486 PCI_Clock_33MHz = 0x00,
487
61a4dcc2
FR		 488 /* Config3 register p.25 */
489 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
490 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
d58d46b5 491 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
f162a5d1 492 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
61a4dcc2 493
d58d46b5
FR		 494 /* Config4 register */
495 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
496
5d06a99f 497 /* Config5 register p.27 */
61a4dcc2
FR		 498 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
499 MWF = (1 << 5), /* Accept Multicast wakeup frame */
500 UWF = (1 << 4), /* Accept Unicast wakeup frame */
cecb5fd7 501 Spi_en = (1 << 3),
61a4dcc2 502 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f
FR		 503 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
504
1da177e4
LT		 505 /* TBICSR p.28 */
506 TBIReset = 0x80000000,
507 TBILoopback = 0x40000000,
508 TBINwEnable = 0x20000000,
509 TBINwRestart = 0x10000000,
510 TBILinkOk = 0x02000000,
511 TBINwComplete = 0x01000000,
512
513 /* CPlusCmd p.31 */
f162a5d1
FR		 514 EnableBist = (1 << 15), // 8168 8101
515 Mac_dbgo_oe = (1 << 14), // 8168 8101
516 Normal_mode = (1 << 13), // unused
517 Force_half_dup = (1 << 12), // 8168 8101
518 Force_rxflow_en = (1 << 11), // 8168 8101
519 Force_txflow_en = (1 << 10), // 8168 8101
520 Cxpl_dbg_sel = (1 << 9), // 8168 8101
521 ASF = (1 << 8), // 8168 8101
522 PktCntrDisable = (1 << 7), // 8168 8101
523 Mac_dbgo_sel = 0x001c, // 8168
1da177e4
LT		 524 RxVlan = (1 << 6),
525 RxChkSum = (1 << 5),
526 PCIDAC = (1 << 4),
527 PCIMulRW = (1 << 3),
0e485150
FR		 528 INTT_0 = 0x0000, // 8168
529 INTT_1 = 0x0001, // 8168
530 INTT_2 = 0x0002, // 8168
531 INTT_3 = 0x0003, // 8168
1da177e4
LT		 532
533 /* rtl8169_PHYstatus */
07d3f51f
FR		 534 TBI_Enable = 0x80,
535 TxFlowCtrl = 0x40,
536 RxFlowCtrl = 0x20,
537 _1000bpsF = 0x10,
538 _100bps = 0x08,
539 _10bps = 0x04,
540 LinkStatus = 0x02,
541 FullDup = 0x01,
1da177e4 542
1da177e4 543 /* _TBICSRBit */
07d3f51f 544 TBILinkOK = 0x02000000,
d4a3a0fc
SH		 545
546 /* DumpCounterCommand */
07d3f51f 547 CounterDump = 0x8,
1da177e4
LT		 548};
549
2b7b4318
FR		 550enum rtl_desc_bit {
551 /* First doubleword. */
1da177e4
LT		 552 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
553 RingEnd = (1 << 30), /* End of descriptor ring */
554 FirstFrag = (1 << 29), /* First segment of a packet */
555 LastFrag = (1 << 28), /* Final segment of a packet */
2b7b4318
FR		 556};
557
558/* Generic case. */
559enum rtl_tx_desc_bit {
560 /* First doubleword. */
561 TD_LSO = (1 << 27), /* Large Send Offload */
562#define TD_MSS_MAX 0x07ffu /* MSS value */
1da177e4 563
2b7b4318
FR		 564 /* Second doubleword. */
565 TxVlanTag = (1 << 17), /* Add VLAN tag */
566};
567
568/* 8169, 8168b and 810x except 8102e. */
569enum rtl_tx_desc_bit_0 {
570 /* First doubleword. */
571#define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
572 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
573 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
574 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
575};
576
577/* 8102e, 8168c and beyond. */
578enum rtl_tx_desc_bit_1 {
579 /* Second doubleword. */
580#define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
581 TD1_IP_CS = (1 << 29), /* Calculate IP checksum */
582 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
583 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
584};
1da177e4 585
2b7b4318
FR		 586static const struct rtl_tx_desc_info {
587 struct {
588 u32 udp;
589 u32 tcp;
590 } checksum;
591 u16 mss_shift;
592 u16 opts_offset;
593} tx_desc_info [] = {
594 [RTL_TD_0] = {
595 .checksum = {
596 .udp = TD0_IP_CS | TD0_UDP_CS,
597 .tcp = TD0_IP_CS | TD0_TCP_CS
598 },
599 .mss_shift = TD0_MSS_SHIFT,
600 .opts_offset = 0
601 },
602 [RTL_TD_1] = {
603 .checksum = {
604 .udp = TD1_IP_CS | TD1_UDP_CS,
605 .tcp = TD1_IP_CS | TD1_TCP_CS
606 },
607 .mss_shift = TD1_MSS_SHIFT,
608 .opts_offset = 1
609 }
610};
611
612enum rtl_rx_desc_bit {
1da177e4
LT		 613 /* Rx private */
614 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
615 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
616
617#define RxProtoUDP (PID1)
618#define RxProtoTCP (PID0)
619#define RxProtoIP (PID1 | PID0)
620#define RxProtoMask RxProtoIP
621
622 IPFail = (1 << 16), /* IP checksum failed */
623 UDPFail = (1 << 15), /* UDP/IP checksum failed */
624 TCPFail = (1 << 14), /* TCP/IP checksum failed */
625 RxVlanTag = (1 << 16), /* VLAN tag available */
626};
627
628#define RsvdMask 0x3fffc000
629
630struct TxDesc {
6cccd6e7
REB		 631 __le32 opts1;
632 __le32 opts2;
633 __le64 addr;
1da177e4
LT		 634};
635
636struct RxDesc {
6cccd6e7
REB		 637 __le32 opts1;
638 __le32 opts2;
639 __le64 addr;
1da177e4
LT		 640};
641
642struct ring_info {
643 struct sk_buff *skb;
644 u32 len;
645 u8 __pad[sizeof(void *) - sizeof(u32)];
646};
647
f23e7fda 648enum features {
ccdffb9a
FR		 649 RTL_FEATURE_WOL = (1 << 0),
650 RTL_FEATURE_MSI = (1 << 1),
651 RTL_FEATURE_GMII = (1 << 2),
f23e7fda
FR		 652};
653
355423d0
IV		 654struct rtl8169_counters {
655 __le64 tx_packets;
656 __le64 rx_packets;
657 __le64 tx_errors;
658 __le32 rx_errors;
659 __le16 rx_missed;
660 __le16 align_errors;
661 __le32 tx_one_collision;
662 __le32 tx_multi_collision;
663 __le64 rx_unicast;
664 __le64 rx_broadcast;
665 __le32 rx_multicast;
666 __le16 tx_aborted;
667 __le16 tx_underun;
668};
669
da78dbff 670enum rtl_flag {
6c4a70c5 671 RTL_FLAG_TASK_ENABLED,
da78dbff
FR		 672 RTL_FLAG_TASK_SLOW_PENDING,
673 RTL_FLAG_TASK_RESET_PENDING,
674 RTL_FLAG_TASK_PHY_PENDING,
675 RTL_FLAG_MAX
676};
677
8027aa24
JW		 678struct rtl8169_stats {
679 u64 packets;
680 u64 bytes;
681 struct u64_stats_sync syncp;
682};
683
1da177e4
LT		 684struct rtl8169_private {
685 void __iomem *mmio_addr; /* memory map physical address */
cecb5fd7 686 struct pci_dev *pci_dev;
c4028958 687 struct net_device *dev;
bea3348e 688 struct napi_struct napi;
b57b7e5a 689 u32 msg_enable;
2b7b4318
FR		 690 u16 txd_version;
691 u16 mac_version;
1da177e4
LT		 692 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
693 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
694 u32 dirty_rx;
695 u32 dirty_tx;
8027aa24
JW		 696 struct rtl8169_stats rx_stats;
697 struct rtl8169_stats tx_stats;
1da177e4
LT		 698 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
699 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
700 dma_addr_t TxPhyAddr;
701 dma_addr_t RxPhyAddr;
6f0333b8 702 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
1da177e4 703 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
1da177e4
LT		 704 struct timer_list timer;
705 u16 cp_cmd;
da78dbff
FR		 706
707 u16 event_slow;
c0e45c1c 708
709 struct mdio_ops {
710 void (*write)(void __iomem *, int, int);
711 int (*read)(void __iomem *, int);
712 } mdio_ops;
713
065c27c1 714 struct pll_power_ops {
715 void (*down)(struct rtl8169_private *);
716 void (*up)(struct rtl8169_private *);
717 } pll_power_ops;
718
d58d46b5
FR		 719 struct jumbo_ops {
720 void (*enable)(struct rtl8169_private *);
721 void (*disable)(struct rtl8169_private *);
722 } jumbo_ops;
723
54405cde 724 int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
ccdffb9a 725 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
4da19633 726 void (*phy_reset_enable)(struct rtl8169_private *tp);
07ce4064 727 void (*hw_start)(struct net_device *);
4da19633 728 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
1da177e4 729 unsigned int (*link_ok)(void __iomem *);
8b4ab28d 730 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
4422bcd4
FR		 731
732 struct {
da78dbff
FR		 733 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
734 struct mutex mutex;
4422bcd4
FR		 735 struct work_struct work;
736 } wk;
737
f23e7fda 738 unsigned features;
ccdffb9a
FR		 739
740 struct mii_if_info mii;
355423d0 741 struct rtl8169_counters counters;
e1759441 742 u32 saved_wolopts;
e03f33af 743 u32 opts1_mask;
f1e02ed1 744
b6ffd97f
FR		 745 struct rtl_fw {
746 const struct firmware *fw;
1c361efb
FR		 747
748#define RTL_VER_SIZE 32
749
750 char version[RTL_VER_SIZE];
751
752 struct rtl_fw_phy_action {
753 __le32 *code;
754 size_t size;
755 } phy_action;
b6ffd97f 756 } *rtl_fw;
497888cf 757#define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
1da177e4
LT		 758};
759
979b6c13 760MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 761MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 762module_param(use_dac, int, 0);
4300e8c7 763MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 764module_param_named(debug, debug.msg_enable, int, 0);
765MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 766MODULE_LICENSE("GPL");
767MODULE_VERSION(RTL8169_VERSION);
bca03d5f 768MODULE_FIRMWARE(FIRMWARE_8168D_1);
769MODULE_FIRMWARE(FIRMWARE_8168D_2);
01dc7fec 770MODULE_FIRMWARE(FIRMWARE_8168E_1);
771MODULE_FIRMWARE(FIRMWARE_8168E_2);
bbb8af75 772MODULE_FIRMWARE(FIRMWARE_8168E_3);
5a5e4443 773MODULE_FIRMWARE(FIRMWARE_8105E_1);
c2218925
HW		 774MODULE_FIRMWARE(FIRMWARE_8168F_1);
775MODULE_FIRMWARE(FIRMWARE_8168F_2);
1da177e4
LT		 776
777static int rtl8169_open(struct net_device *dev);
61357325
SH		 778static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
779 struct net_device *dev);
7d12e780 780static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
1da177e4 781static int rtl8169_init_ring(struct net_device *dev);
07ce4064 782static void rtl_hw_start(struct net_device *dev);
1da177e4 783static int rtl8169_close(struct net_device *dev);
07ce4064 784static void rtl_set_rx_mode(struct net_device *dev);
1da177e4 785static void rtl8169_tx_timeout(struct net_device *dev);
8027aa24
JW		 786static struct rtnl_link_stats64 *rtl8169_get_stats64(struct net_device *dev,
787 struct rtnl_link_stats64
788 *stats);
4dcb7d33 789static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
99f252b0 790static void rtl8169_rx_clear(struct rtl8169_private *tp);
bea3348e 791static int rtl8169_poll(struct napi_struct *napi, int budget);
1da177e4 792
da78dbff
FR		 793static void rtl_lock_work(struct rtl8169_private *tp)
794{
795 mutex_lock(&tp->wk.mutex);
796}
797
798static void rtl_unlock_work(struct rtl8169_private *tp)
799{
800 mutex_unlock(&tp->wk.mutex);
801}
802
d58d46b5
FR		 803static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
804{
805 int cap = pci_pcie_cap(pdev);
806
807 if (cap) {
808 u16 ctl;
809
810 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
811 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
812 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
813 }
814}
815
b646d900 816static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
817{
818 void __iomem *ioaddr = tp->mmio_addr;
819 int i;
820
821 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
822 for (i = 0; i < 20; i++) {
823 udelay(100);
824 if (RTL_R32(OCPAR) & OCPAR_FLAG)
825 break;
826 }
827 return RTL_R32(OCPDR);
828}
829
830static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
831{
832 void __iomem *ioaddr = tp->mmio_addr;
833 int i;
834
835 RTL_W32(OCPDR, data);
836 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
837 for (i = 0; i < 20; i++) {
838 udelay(100);
839 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
840 break;
841 }
842}
843
fac5b3ca 844static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
b646d900 845{
fac5b3ca 846 void __iomem *ioaddr = tp->mmio_addr;
b646d900 847 int i;
848
849 RTL_W8(ERIDR, cmd);
850 RTL_W32(ERIAR, 0x800010e8);
851 msleep(2);
852 for (i = 0; i < 5; i++) {
853 udelay(100);
1e4e82ba 854 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
b646d900 855 break;
856 }
857
fac5b3ca 858 ocp_write(tp, 0x1, 0x30, 0x00000001);
b646d900 859}
860
861#define OOB_CMD_RESET 0x00
862#define OOB_CMD_DRIVER_START 0x05
863#define OOB_CMD_DRIVER_STOP 0x06
864
cecb5fd7
FR		 865static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
866{
867 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
868}
869
b646d900 870static void rtl8168_driver_start(struct rtl8169_private *tp)
871{
cecb5fd7 872 u16 reg;
b646d900 873 int i;
874
875 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
876
cecb5fd7 877 reg = rtl8168_get_ocp_reg(tp);
4804b3b3 878
b646d900 879 for (i = 0; i < 10; i++) {
880 msleep(10);
4804b3b3 881 if (ocp_read(tp, 0x0f, reg) & 0x00000800)
b646d900 882 break;
883 }
884}
885
886static void rtl8168_driver_stop(struct rtl8169_private *tp)
887{
cecb5fd7 888 u16 reg;
b646d900 889 int i;
890
891 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
892
cecb5fd7 893 reg = rtl8168_get_ocp_reg(tp);
4804b3b3 894
b646d900 895 for (i = 0; i < 10; i++) {
896 msleep(10);
4804b3b3 897 if ((ocp_read(tp, 0x0f, reg) & 0x00000800) == 0)
b646d900 898 break;
899 }
900}
901
4804b3b3 902static int r8168dp_check_dash(struct rtl8169_private *tp)
903{
cecb5fd7 904 u16 reg = rtl8168_get_ocp_reg(tp);
4804b3b3 905
cecb5fd7 906 return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
4804b3b3 907}
b646d900 908
4da19633 909static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
1da177e4
LT		 910{
911 int i;
912
a6baf3af 913 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
1da177e4 914
2371408c 915 for (i = 20; i > 0; i--) {
07d3f51f
FR		 916 /*
917 * Check if the RTL8169 has completed writing to the specified
918 * MII register.
919 */
5b0384f4 920 if (!(RTL_R32(PHYAR) & 0x80000000))
1da177e4 921 break;
2371408c 922 udelay(25);
1da177e4 923 }
024a07ba 924 /*
81a95f04
TT		 925 * According to hardware specs a 20us delay is required after write
926 * complete indication, but before sending next command.
024a07ba 927 */
81a95f04 928 udelay(20);
1da177e4
LT		 929}
930
4da19633 931static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
1da177e4
LT		 932{
933 int i, value = -1;
934
a6baf3af 935 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
1da177e4 936
2371408c 937 for (i = 20; i > 0; i--) {
07d3f51f
FR		 938 /*
939 * Check if the RTL8169 has completed retrieving data from
940 * the specified MII register.
941 */
1da177e4 942 if (RTL_R32(PHYAR) & 0x80000000) {
a6baf3af 943 value = RTL_R32(PHYAR) & 0xffff;
1da177e4
LT		 944 break;
945 }
2371408c 946 udelay(25);
1da177e4 947 }
81a95f04
TT		 948 /*
949 * According to hardware specs a 20us delay is required after read
950 * complete indication, but before sending next command.
951 */
952 udelay(20);
953
1da177e4
LT		 954 return value;
955}
956
c0e45c1c 957static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
958{
959 int i;
960
961 RTL_W32(OCPDR, data |
962 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
963 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
964 RTL_W32(EPHY_RXER_NUM, 0);
965
966 for (i = 0; i < 100; i++) {
967 mdelay(1);
968 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
969 break;
970 }
971}
972
973static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
974{
975 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
976 (value & OCPDR_DATA_MASK));
977}
978
979static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
980{
981 int i;
982
983 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
984
985 mdelay(1);
986 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
987 RTL_W32(EPHY_RXER_NUM, 0);
988
989 for (i = 0; i < 100; i++) {
990 mdelay(1);
991 if (RTL_R32(OCPAR) & OCPAR_FLAG)
992 break;
993 }
994
995 return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
996}
997
e6de30d6 998#define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
999
1000static void r8168dp_2_mdio_start(void __iomem *ioaddr)
1001{
1002 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1003}
1004
1005static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
1006{
1007 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1008}
1009
1010static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
1011{
1012 r8168dp_2_mdio_start(ioaddr);
1013
1014 r8169_mdio_write(ioaddr, reg_addr, value);
1015
1016 r8168dp_2_mdio_stop(ioaddr);
1017}
1018
1019static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
1020{
1021 int value;
1022
1023 r8168dp_2_mdio_start(ioaddr);
1024
1025 value = r8169_mdio_read(ioaddr, reg_addr);
1026
1027 r8168dp_2_mdio_stop(ioaddr);
1028
1029 return value;
1030}
1031
4da19633 1032static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
dacf8154 1033{
c0e45c1c 1034 tp->mdio_ops.write(tp->mmio_addr, location, val);
dacf8154
FR		 1035}
1036
4da19633 1037static int rtl_readphy(struct rtl8169_private *tp, int location)
1038{
c0e45c1c 1039 return tp->mdio_ops.read(tp->mmio_addr, location);
4da19633 1040}
1041
1042static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1043{
1044 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1045}
1046
1047static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
daf9df6d 1048{
1049 int val;
1050
4da19633 1051 val = rtl_readphy(tp, reg_addr);
1052 rtl_writephy(tp, reg_addr, (val | p) & ~m);
daf9df6d 1053}
1054
ccdffb9a
FR		 1055static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1056 int val)
1057{
1058 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 1059
4da19633 1060 rtl_writephy(tp, location, val);
ccdffb9a
FR		 1061}
1062
1063static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1064{
1065 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 1066
4da19633 1067 return rtl_readphy(tp, location);
ccdffb9a
FR		 1068}
1069
dacf8154
FR		 1070static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
1071{
1072 unsigned int i;
1073
1074 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1075 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1076
1077 for (i = 0; i < 100; i++) {
1078 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
1079 break;
1080 udelay(10);
1081 }
1082}
1083
1084static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
1085{
1086 u16 value = 0xffff;
1087 unsigned int i;
1088
1089 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1090
1091 for (i = 0; i < 100; i++) {
1092 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
1093 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
1094 break;
1095 }
1096 udelay(10);
1097 }
1098
1099 return value;
1100}
1101
1102static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
1103{
1104 unsigned int i;
1105
1106 RTL_W32(CSIDR, value);
1107 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
1108 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1109
1110 for (i = 0; i < 100; i++) {
1111 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
1112 break;
1113 udelay(10);
1114 }
1115}
1116
1117static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
1118{
1119 u32 value = ~0x00;
1120 unsigned int i;
1121
1122 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
1123 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1124
1125 for (i = 0; i < 100; i++) {
1126 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
1127 value = RTL_R32(CSIDR);
1128 break;
1129 }
1130 udelay(10);
1131 }
1132
1133 return value;
1134}
1135
133ac40a
HW		 1136static
1137void rtl_eri_write(void __iomem *ioaddr, int addr, u32 mask, u32 val, int type)
1138{
1139 unsigned int i;
1140
1141 BUG_ON((addr & 3) || (mask == 0));
1142 RTL_W32(ERIDR, val);
1143 RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1144
1145 for (i = 0; i < 100; i++) {
1146 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
1147 break;
1148 udelay(100);
1149 }
1150}
1151
1152static u32 rtl_eri_read(void __iomem *ioaddr, int addr, int type)
1153{
1154 u32 value = ~0x00;
1155 unsigned int i;
1156
1157 RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1158
1159 for (i = 0; i < 100; i++) {
1160 if (RTL_R32(ERIAR) & ERIAR_FLAG) {
1161 value = RTL_R32(ERIDR);
1162 break;
1163 }
1164 udelay(100);
1165 }
1166
1167 return value;
1168}
1169
1170static void
1171rtl_w1w0_eri(void __iomem *ioaddr, int addr, u32 mask, u32 p, u32 m, int type)
1172{
1173 u32 val;
1174
1175 val = rtl_eri_read(ioaddr, addr, type);
1176 rtl_eri_write(ioaddr, addr, mask, (val & ~m) | p, type);
1177}
1178
c28aa385 1179struct exgmac_reg {
1180 u16 addr;
1181 u16 mask;
1182 u32 val;
1183};
1184
1185static void rtl_write_exgmac_batch(void __iomem *ioaddr,
1186 const struct exgmac_reg *r, int len)
1187{
1188 while (len-- > 0) {
1189 rtl_eri_write(ioaddr, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1190 r++;
1191 }
1192}
1193
daf9df6d 1194static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
1195{
1196 u8 value = 0xff;
1197 unsigned int i;
1198
1199 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1200
1201 for (i = 0; i < 300; i++) {
1202 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
1203 value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
1204 break;
1205 }
1206 udelay(100);
1207 }
1208
1209 return value;
1210}
1211
9085cdfa
FR		 1212static u16 rtl_get_events(struct rtl8169_private *tp)
1213{
1214 void __iomem *ioaddr = tp->mmio_addr;
1215
1216 return RTL_R16(IntrStatus);
1217}
1218
1219static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1220{
1221 void __iomem *ioaddr = tp->mmio_addr;
1222
1223 RTL_W16(IntrStatus, bits);
1224 mmiowb();
1225}
1226
1227static void rtl_irq_disable(struct rtl8169_private *tp)
1228{
1229 void __iomem *ioaddr = tp->mmio_addr;
1230
1231 RTL_W16(IntrMask, 0);
1232 mmiowb();
1233}
1234
3e990ff5
FR		 1235static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1236{
1237 void __iomem *ioaddr = tp->mmio_addr;
1238
1239 RTL_W16(IntrMask, bits);
1240}
1241
da78dbff
FR		 1242#define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1243#define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1244#define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1245
1246static void rtl_irq_enable_all(struct rtl8169_private *tp)
1247{
1248 rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1249}
1250
811fd301 1251static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1da177e4 1252{
811fd301 1253 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 1254
9085cdfa 1255 rtl_irq_disable(tp);
da78dbff 1256 rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
811fd301 1257 RTL_R8(ChipCmd);
1da177e4
LT		 1258}
1259
4da19633 1260static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1da177e4 1261{
4da19633 1262 void __iomem *ioaddr = tp->mmio_addr;
1263
1da177e4
LT		 1264 return RTL_R32(TBICSR) & TBIReset;
1265}
1266
4da19633 1267static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1da177e4 1268{
4da19633 1269 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1da177e4
LT		 1270}
1271
1272static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1273{
1274 return RTL_R32(TBICSR) & TBILinkOk;
1275}
1276
1277static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1278{
1279 return RTL_R8(PHYstatus) & LinkStatus;
1280}
1281
4da19633 1282static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1da177e4 1283{
4da19633 1284 void __iomem *ioaddr = tp->mmio_addr;
1285
1da177e4
LT		 1286 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1287}
1288
4da19633 1289static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1da177e4
LT		 1290{
1291 unsigned int val;
1292
4da19633 1293 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1294 rtl_writephy(tp, MII_BMCR, val & 0xffff);
1da177e4
LT		 1295}
1296
70090424
HW		 1297static void rtl_link_chg_patch(struct rtl8169_private *tp)
1298{
1299 void __iomem *ioaddr = tp->mmio_addr;
1300 struct net_device *dev = tp->dev;
1301
1302 if (!netif_running(dev))
1303 return;
1304
1305 if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
1306 if (RTL_R8(PHYstatus) & _1000bpsF) {
1307 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1308 0x00000011, ERIAR_EXGMAC);
1309 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1310 0x00000005, ERIAR_EXGMAC);
1311 } else if (RTL_R8(PHYstatus) & _100bps) {
1312 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1313 0x0000001f, ERIAR_EXGMAC);
1314 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1315 0x00000005, ERIAR_EXGMAC);
1316 } else {
1317 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1318 0x0000001f, ERIAR_EXGMAC);
1319 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1320 0x0000003f, ERIAR_EXGMAC);
1321 }
1322 /* Reset packet filter */
1323 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1324 ERIAR_EXGMAC);
1325 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1326 ERIAR_EXGMAC);
c2218925
HW		 1327 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1328 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1329 if (RTL_R8(PHYstatus) & _1000bpsF) {
1330 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1331 0x00000011, ERIAR_EXGMAC);
1332 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1333 0x00000005, ERIAR_EXGMAC);
1334 } else {
1335 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1336 0x0000001f, ERIAR_EXGMAC);
1337 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1338 0x0000003f, ERIAR_EXGMAC);
1339 }
70090424
HW		 1340 }
1341}
1342
e4fbce74 1343static void __rtl8169_check_link_status(struct net_device *dev,
cecb5fd7
FR		 1344 struct rtl8169_private *tp,
1345 void __iomem *ioaddr, bool pm)
1da177e4 1346{
1da177e4 1347 if (tp->link_ok(ioaddr)) {
70090424 1348 rtl_link_chg_patch(tp);
e1759441 1349 /* This is to cancel a scheduled suspend if there's one. */
e4fbce74
RW		 1350 if (pm)
1351 pm_request_resume(&tp->pci_dev->dev);
1da177e4 1352 netif_carrier_on(dev);
1519e57f
FR		 1353 if (net_ratelimit())
1354 netif_info(tp, ifup, dev, "link up\n");
b57b7e5a 1355 } else {
1da177e4 1356 netif_carrier_off(dev);
bf82c189 1357 netif_info(tp, ifdown, dev, "link down\n");
e4fbce74 1358 if (pm)
10953db8 1359 pm_schedule_suspend(&tp->pci_dev->dev, 5000);
b57b7e5a 1360 }
1da177e4
LT		 1361}
1362
e4fbce74
RW		 1363static void rtl8169_check_link_status(struct net_device *dev,
1364 struct rtl8169_private *tp,
1365 void __iomem *ioaddr)
1366{
1367 __rtl8169_check_link_status(dev, tp, ioaddr, false);
1368}
1369
e1759441
RW		 1370#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1371
1372static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
61a4dcc2 1373{
61a4dcc2
FR		 1374 void __iomem *ioaddr = tp->mmio_addr;
1375 u8 options;
e1759441 1376 u32 wolopts = 0;
61a4dcc2
FR		 1377
1378 options = RTL_R8(Config1);
1379 if (!(options & PMEnable))
e1759441 1380 return 0;
61a4dcc2
FR		 1381
1382 options = RTL_R8(Config3);
1383 if (options & LinkUp)
e1759441 1384 wolopts |= WAKE_PHY;
61a4dcc2 1385 if (options & MagicPacket)
e1759441 1386 wolopts |= WAKE_MAGIC;
61a4dcc2
FR		 1387
1388 options = RTL_R8(Config5);
1389 if (options & UWF)
e1759441 1390 wolopts |= WAKE_UCAST;
61a4dcc2 1391 if (options & BWF)
e1759441 1392 wolopts |= WAKE_BCAST;
61a4dcc2 1393 if (options & MWF)
e1759441 1394 wolopts |= WAKE_MCAST;
61a4dcc2 1395
e1759441 1396 return wolopts;
61a4dcc2
FR		 1397}
1398
e1759441 1399static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
61a4dcc2
FR		 1400{
1401 struct rtl8169_private *tp = netdev_priv(dev);
e1759441 1402
da78dbff 1403 rtl_lock_work(tp);
e1759441
RW		 1404
1405 wol->supported = WAKE_ANY;
1406 wol->wolopts = __rtl8169_get_wol(tp);
1407
da78dbff 1408 rtl_unlock_work(tp);
e1759441
RW		 1409}
1410
1411static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1412{
61a4dcc2 1413 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 1414 unsigned int i;
350f7596 1415 static const struct {
61a4dcc2
FR		 1416 u32 opt;
1417 u16 reg;
1418 u8 mask;
1419 } cfg[] = {
1420 { WAKE_ANY, Config1, PMEnable },
1421 { WAKE_PHY, Config3, LinkUp },
1422 { WAKE_MAGIC, Config3, MagicPacket },
1423 { WAKE_UCAST, Config5, UWF },
1424 { WAKE_BCAST, Config5, BWF },
1425 { WAKE_MCAST, Config5, MWF },
1426 { WAKE_ANY, Config5, LanWake }
1427 };
1428
61a4dcc2
FR		 1429 RTL_W8(Cfg9346, Cfg9346_Unlock);
1430
1431 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1432 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
e1759441 1433 if (wolopts & cfg[i].opt)
61a4dcc2
FR		 1434 options |= cfg[i].mask;
1435 RTL_W8(cfg[i].reg, options);
1436 }
1437
1438 RTL_W8(Cfg9346, Cfg9346_Lock);
e1759441
RW		 1439}
1440
1441static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1442{
1443 struct rtl8169_private *tp = netdev_priv(dev);
1444
da78dbff 1445 rtl_lock_work(tp);
61a4dcc2 1446
f23e7fda
FR		 1447 if (wol->wolopts)
1448 tp->features |= RTL_FEATURE_WOL;
1449 else
1450 tp->features &= ~RTL_FEATURE_WOL;
e1759441 1451 __rtl8169_set_wol(tp, wol->wolopts);
da78dbff
FR		 1452
1453 rtl_unlock_work(tp);
61a4dcc2 1454
ea80907f 1455 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1456
61a4dcc2
FR		 1457 return 0;
1458}
1459
31bd204f
FR		 1460static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1461{
85bffe6c 1462 return rtl_chip_infos[tp->mac_version].fw_name;
31bd204f
FR		 1463}
1464
1da177e4
LT		 1465static void rtl8169_get_drvinfo(struct net_device *dev,
1466 struct ethtool_drvinfo *info)
1467{
1468 struct rtl8169_private *tp = netdev_priv(dev);
b6ffd97f 1469 struct rtl_fw *rtl_fw = tp->rtl_fw;
1da177e4 1470
68aad78c
RJ		 1471 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1472 strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1473 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1c361efb 1474 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
8ac72d16
RJ		 1475 if (!IS_ERR_OR_NULL(rtl_fw))
1476 strlcpy(info->fw_version, rtl_fw->version,
1477 sizeof(info->fw_version));
1da177e4
LT		 1478}
1479
1480static int rtl8169_get_regs_len(struct net_device *dev)
1481{
1482 return R8169_REGS_SIZE;
1483}
1484
1485static int rtl8169_set_speed_tbi(struct net_device *dev,
54405cde 1486 u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1da177e4
LT		 1487{
1488 struct rtl8169_private *tp = netdev_priv(dev);
1489 void __iomem *ioaddr = tp->mmio_addr;
1490 int ret = 0;
1491 u32 reg;
1492
1493 reg = RTL_R32(TBICSR);
1494 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1495 (duplex == DUPLEX_FULL)) {
1496 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1497 } else if (autoneg == AUTONEG_ENABLE)
1498 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1499 else {
bf82c189
JP		 1500 netif_warn(tp, link, dev,
1501 "incorrect speed setting refused in TBI mode\n");
1da177e4
LT		 1502 ret = -EOPNOTSUPP;
1503 }
1504
1505 return ret;
1506}
1507
1508static int rtl8169_set_speed_xmii(struct net_device *dev,
54405cde 1509 u8 autoneg, u16 speed, u8 duplex, u32 adv)
1da177e4
LT		 1510{
1511 struct rtl8169_private *tp = netdev_priv(dev);
3577aa1b 1512 int giga_ctrl, bmcr;
54405cde 1513 int rc = -EINVAL;
1da177e4 1514
716b50a3 1515 rtl_writephy(tp, 0x1f, 0x0000);
1da177e4
LT		 1516
1517 if (autoneg == AUTONEG_ENABLE) {
3577aa1b 1518 int auto_nego;
1519
4da19633 1520 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
54405cde
ON		 1521 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1522 ADVERTISE_100HALF | ADVERTISE_100FULL);
1523
1524 if (adv & ADVERTISED_10baseT_Half)
1525 auto_nego |= ADVERTISE_10HALF;
1526 if (adv & ADVERTISED_10baseT_Full)
1527 auto_nego |= ADVERTISE_10FULL;
1528 if (adv & ADVERTISED_100baseT_Half)
1529 auto_nego |= ADVERTISE_100HALF;
1530 if (adv & ADVERTISED_100baseT_Full)
1531 auto_nego |= ADVERTISE_100FULL;
1532
3577aa1b 1533 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1da177e4 1534
4da19633 1535 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
3577aa1b 1536 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
bcf0bf90 1537
3577aa1b 1538 /* The 8100e/8101e/8102e do Fast Ethernet only. */
826e6cbd 1539 if (tp->mii.supports_gmii) {
54405cde
ON		 1540 if (adv & ADVERTISED_1000baseT_Half)
1541 giga_ctrl |= ADVERTISE_1000HALF;
1542 if (adv & ADVERTISED_1000baseT_Full)
1543 giga_ctrl |= ADVERTISE_1000FULL;
1544 } else if (adv & (ADVERTISED_1000baseT_Half |
1545 ADVERTISED_1000baseT_Full)) {
bf82c189
JP		 1546 netif_info(tp, link, dev,
1547 "PHY does not support 1000Mbps\n");
54405cde 1548 goto out;
bcf0bf90 1549 }
1da177e4 1550
3577aa1b 1551 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1552
4da19633 1553 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1554 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
3577aa1b 1555 } else {
1556 giga_ctrl = 0;
1557
1558 if (speed == SPEED_10)
1559 bmcr = 0;
1560 else if (speed == SPEED_100)
1561 bmcr = BMCR_SPEED100;
1562 else
54405cde 1563 goto out;
3577aa1b 1564
1565 if (duplex == DUPLEX_FULL)
1566 bmcr |= BMCR_FULLDPLX;
2584fbc3
RS		 1567 }
1568
4da19633 1569 rtl_writephy(tp, MII_BMCR, bmcr);
3577aa1b 1570
cecb5fd7
FR		 1571 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1572 tp->mac_version == RTL_GIGA_MAC_VER_03) {
3577aa1b 1573 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
4da19633 1574 rtl_writephy(tp, 0x17, 0x2138);
1575 rtl_writephy(tp, 0x0e, 0x0260);
3577aa1b 1576 } else {
4da19633 1577 rtl_writephy(tp, 0x17, 0x2108);
1578 rtl_writephy(tp, 0x0e, 0x0000);
3577aa1b 1579 }
1580 }
1581
54405cde
ON		 1582 rc = 0;
1583out:
1584 return rc;
1da177e4
LT		 1585}
1586
1587static int rtl8169_set_speed(struct net_device *dev,
54405cde 1588 u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1da177e4
LT		 1589{
1590 struct rtl8169_private *tp = netdev_priv(dev);
1591 int ret;
1592
54405cde 1593 ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
4876cc1e
FR		 1594 if (ret < 0)
1595 goto out;
1da177e4 1596
4876cc1e
FR		 1597 if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1598 (advertising & ADVERTISED_1000baseT_Full)) {
1da177e4 1599 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
4876cc1e
FR		 1600 }
1601out:
1da177e4
LT		 1602 return ret;
1603}
1604
1605static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1606{
1607 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4
LT		 1608 int ret;
1609
4876cc1e
FR		 1610 del_timer_sync(&tp->timer);
1611
da78dbff 1612 rtl_lock_work(tp);
cecb5fd7 1613 ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
25db0338 1614 cmd->duplex, cmd->advertising);
da78dbff 1615 rtl_unlock_work(tp);
5b0384f4 1616
1da177e4
LT		 1617 return ret;
1618}
1619
c8f44aff
MM		 1620static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1621 netdev_features_t features)
1da177e4 1622{
d58d46b5
FR		 1623 struct rtl8169_private *tp = netdev_priv(dev);
1624
2b7b4318 1625 if (dev->mtu > TD_MSS_MAX)
350fb32a 1626 features &= ~NETIF_F_ALL_TSO;
1da177e4 1627
d58d46b5
FR		 1628 if (dev->mtu > JUMBO_1K &&
1629 !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
1630 features &= ~NETIF_F_IP_CSUM;
1631
350fb32a 1632 return features;
1da177e4
LT		 1633}
1634
da78dbff
FR		 1635static void __rtl8169_set_features(struct net_device *dev,
1636 netdev_features_t features)
1da177e4
LT		 1637{
1638 struct rtl8169_private *tp = netdev_priv(dev);
6bbe021d 1639 netdev_features_t changed = features ^ dev->features;
da78dbff 1640 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 1641
6bbe021d
BG		 1642 if (!(changed & (NETIF_F_RXALL | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX)))
1643 return;
1da177e4 1644
6bbe021d
BG		 1645 if (changed & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX)) {
1646 if (features & NETIF_F_RXCSUM)
1647 tp->cp_cmd |= RxChkSum;
1648 else
1649 tp->cp_cmd &= ~RxChkSum;
350fb32a 1650
6bbe021d
BG		 1651 if (dev->features & NETIF_F_HW_VLAN_RX)
1652 tp->cp_cmd |= RxVlan;
1653 else
1654 tp->cp_cmd &= ~RxVlan;
1655
1656 RTL_W16(CPlusCmd, tp->cp_cmd);
1657 RTL_R16(CPlusCmd);
1658 }
1659 if (changed & NETIF_F_RXALL) {
1660 int tmp = (RTL_R32(RxConfig) & ~(AcceptErr | AcceptRunt));
1661 if (features & NETIF_F_RXALL)
1662 tmp |= (AcceptErr | AcceptRunt);
1663 RTL_W32(RxConfig, tmp);
1664 }
da78dbff 1665}
1da177e4 1666
da78dbff
FR		 1667static int rtl8169_set_features(struct net_device *dev,
1668 netdev_features_t features)
1669{
1670 struct rtl8169_private *tp = netdev_priv(dev);
1671
1672 rtl_lock_work(tp);
1673 __rtl8169_set_features(dev, features);
1674 rtl_unlock_work(tp);
1da177e4
LT		 1675
1676 return 0;
1677}
1678
da78dbff 1679
1da177e4
LT		 1680static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1681 struct sk_buff *skb)
1682{
eab6d18d 1683 return (vlan_tx_tag_present(skb)) ?
1da177e4
LT		 1684 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1685}
1686
7a8fc77b 1687static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1da177e4
LT		 1688{
1689 u32 opts2 = le32_to_cpu(desc->opts2);
1da177e4 1690
7a8fc77b
FR		 1691 if (opts2 & RxVlanTag)
1692 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
2edae08e 1693
1da177e4 1694 desc->opts2 = 0;
1da177e4
LT		 1695}
1696
ccdffb9a 1697static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1698{
1699 struct rtl8169_private *tp = netdev_priv(dev);
1700 void __iomem *ioaddr = tp->mmio_addr;
1701 u32 status;
1702
1703 cmd->supported =
1704 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1705 cmd->port = PORT_FIBRE;
1706 cmd->transceiver = XCVR_INTERNAL;
1707
1708 status = RTL_R32(TBICSR);
1709 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1710 cmd->autoneg = !!(status & TBINwEnable);
1711
70739497 1712 ethtool_cmd_speed_set(cmd, SPEED_1000);
1da177e4 1713 cmd->duplex = DUPLEX_FULL; /* Always set */
ccdffb9a
FR		 1714
1715 return 0;
1da177e4
LT		 1716}
1717
ccdffb9a 1718static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1719{
1720 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a
FR		 1721
1722 return mii_ethtool_gset(&tp->mii, cmd);
1da177e4
LT		 1723}
1724
1725static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1726{
1727 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 1728 int rc;
1da177e4 1729
da78dbff 1730 rtl_lock_work(tp);
ccdffb9a 1731 rc = tp->get_settings(dev, cmd);
da78dbff 1732 rtl_unlock_work(tp);
1da177e4 1733
ccdffb9a 1734 return rc;
1da177e4
LT		 1735}
1736
1737static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1738 void *p)
1739{
5b0384f4 1740 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 1741
5b0384f4
FR		 1742 if (regs->len > R8169_REGS_SIZE)
1743 regs->len = R8169_REGS_SIZE;
1da177e4 1744
da78dbff 1745 rtl_lock_work(tp);
5b0384f4 1746 memcpy_fromio(p, tp->mmio_addr, regs->len);
da78dbff 1747 rtl_unlock_work(tp);
1da177e4
LT		 1748}
1749
b57b7e5a
SH		 1750static u32 rtl8169_get_msglevel(struct net_device *dev)
1751{
1752 struct rtl8169_private *tp = netdev_priv(dev);
1753
1754 return tp->msg_enable;
1755}
1756
1757static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1758{
1759 struct rtl8169_private *tp = netdev_priv(dev);
1760
1761 tp->msg_enable = value;
1762}
1763
d4a3a0fc
SH		 1764static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1765 "tx_packets",
1766 "rx_packets",
1767 "tx_errors",
1768 "rx_errors",
1769 "rx_missed",
1770 "align_errors",
1771 "tx_single_collisions",
1772 "tx_multi_collisions",
1773 "unicast",
1774 "broadcast",
1775 "multicast",
1776 "tx_aborted",
1777 "tx_underrun",
1778};
1779
b9f2c044 1780static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 1781{
b9f2c044
JG		 1782 switch (sset) {
1783 case ETH_SS_STATS:
1784 return ARRAY_SIZE(rtl8169_gstrings);
1785 default:
1786 return -EOPNOTSUPP;
1787 }
d4a3a0fc
SH		 1788}
1789
355423d0 1790static void rtl8169_update_counters(struct net_device *dev)
d4a3a0fc
SH		 1791{
1792 struct rtl8169_private *tp = netdev_priv(dev);
1793 void __iomem *ioaddr = tp->mmio_addr;
cecb5fd7 1794 struct device *d = &tp->pci_dev->dev;
d4a3a0fc
SH		 1795 struct rtl8169_counters *counters;
1796 dma_addr_t paddr;
1797 u32 cmd;
355423d0 1798 int wait = 1000;
d4a3a0fc 1799
355423d0
IV		 1800 /*
1801 * Some chips are unable to dump tally counters when the receiver
1802 * is disabled.
1803 */
1804 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1805 return;
d4a3a0fc 1806
48addcc9 1807 counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
d4a3a0fc
SH		 1808 if (!counters)
1809 return;
1810
1811 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
284901a9 1812 cmd = (u64)paddr & DMA_BIT_MASK(32);
d4a3a0fc
SH		 1813 RTL_W32(CounterAddrLow, cmd);
1814 RTL_W32(CounterAddrLow, cmd | CounterDump);
1815
355423d0
IV		 1816 while (wait--) {
1817 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
355423d0 1818 memcpy(&tp->counters, counters, sizeof(*counters));
d4a3a0fc 1819 break;
355423d0
IV		 1820 }
1821 udelay(10);
d4a3a0fc
SH		 1822 }
1823
1824 RTL_W32(CounterAddrLow, 0);
1825 RTL_W32(CounterAddrHigh, 0);
1826
48addcc9 1827 dma_free_coherent(d, sizeof(*counters), counters, paddr);
d4a3a0fc
SH		 1828}
1829
355423d0
IV		 1830static void rtl8169_get_ethtool_stats(struct net_device *dev,
1831 struct ethtool_stats *stats, u64 *data)
1832{
1833 struct rtl8169_private *tp = netdev_priv(dev);
1834
1835 ASSERT_RTNL();
1836
1837 rtl8169_update_counters(dev);
1838
1839 data[0] = le64_to_cpu(tp->counters.tx_packets);
1840 data[1] = le64_to_cpu(tp->counters.rx_packets);
1841 data[2] = le64_to_cpu(tp->counters.tx_errors);
1842 data[3] = le32_to_cpu(tp->counters.rx_errors);
1843 data[4] = le16_to_cpu(tp->counters.rx_missed);
1844 data[5] = le16_to_cpu(tp->counters.align_errors);
1845 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1846 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1847 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1848 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1849 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1850 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1851 data[12] = le16_to_cpu(tp->counters.tx_underun);
1852}
1853
d4a3a0fc
SH		 1854static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1855{
1856 switch(stringset) {
1857 case ETH_SS_STATS:
1858 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1859 break;
1860 }
1861}
1862
7282d491 1863static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 1864 .get_drvinfo = rtl8169_get_drvinfo,
1865 .get_regs_len = rtl8169_get_regs_len,
1866 .get_link = ethtool_op_get_link,
1867 .get_settings = rtl8169_get_settings,
1868 .set_settings = rtl8169_set_settings,
b57b7e5a
SH		 1869 .get_msglevel = rtl8169_get_msglevel,
1870 .set_msglevel = rtl8169_set_msglevel,
1da177e4 1871 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 1872 .get_wol = rtl8169_get_wol,
1873 .set_wol = rtl8169_set_wol,
d4a3a0fc 1874 .get_strings = rtl8169_get_strings,
b9f2c044 1875 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 1876 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1da177e4
LT		 1877};
1878
07d3f51f 1879static void rtl8169_get_mac_version(struct rtl8169_private *tp,
5d320a20 1880 struct net_device *dev, u8 default_version)
1da177e4 1881{
5d320a20 1882 void __iomem *ioaddr = tp->mmio_addr;
0e485150
FR		 1883 /*
1884 * The driver currently handles the 8168Bf and the 8168Be identically
1885 * but they can be identified more specifically through the test below
1886 * if needed:
1887 *
1888 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 1889 *
1890 * Same thing for the 8101Eb and the 8101Ec:
1891 *
1892 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 1893 */
3744100e 1894 static const struct rtl_mac_info {
1da177e4 1895 u32 mask;
e3cf0cc0 1896 u32 val;
1da177e4
LT		 1897 int mac_version;
1898 } mac_info[] = {
c2218925
HW		 1899 /* 8168F family. */
1900 { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36 },
1901 { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35 },
1902
01dc7fec 1903 /* 8168E family. */
70090424 1904 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 },
01dc7fec 1905 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 },
1906 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
1907 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
1908
5b538df9 1909 /* 8168D family. */
daf9df6d 1910 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
1911 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
daf9df6d 1912 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
5b538df9 1913
e6de30d6 1914 /* 8168DP family. */
1915 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
1916 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
4804b3b3 1917 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
e6de30d6 1918
ef808d50 1919 /* 8168C family. */
17c99297 1920 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
ef3386f0 1921 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
ef808d50 1922 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
7f3e3d3a 1923 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
e3cf0cc0
FR		 1924 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1925 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
197ff761 1926 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
6fb07058 1927 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
ef808d50 1928 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
e3cf0cc0
FR		 1929
1930 /* 8168B family. */
1931 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1932 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1933 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1934 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1935
1936 /* 8101 family. */
36a0e6c2 1937 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 },
5a5e4443
HW		 1938 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 },
1939 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
1940 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
2857ffb7
FR		 1941 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1942 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1943 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
1944 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
1945 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
1946 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
e3cf0cc0 1947 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2857ffb7 1948 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
e3cf0cc0 1949 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2857ffb7
FR		 1950 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
1951 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
e3cf0cc0
FR		 1952 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1953 /* FIXME: where did these entries come from ? -- FR */
1954 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1955 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1956
1957 /* 8110 family. */
1958 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1959 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1960 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1961 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1962 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1963 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1964
f21b75e9
JD		 1965 /* Catch-all */
1966 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
3744100e
FR		 1967 };
1968 const struct rtl_mac_info *p = mac_info;
1da177e4
LT		 1969 u32 reg;
1970
e3cf0cc0
FR		 1971 reg = RTL_R32(TxConfig);
1972 while ((reg & p->mask) != p->val)
1da177e4
LT		 1973 p++;
1974 tp->mac_version = p->mac_version;
5d320a20
FR		 1975
1976 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
1977 netif_notice(tp, probe, dev,
1978 "unknown MAC, using family default\n");
1979 tp->mac_version = default_version;
1980 }
1da177e4
LT		 1981}
1982
1983static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1984{
bcf0bf90 1985 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 1986}
1987
867763c1
FR		 1988struct phy_reg {
1989 u16 reg;
1990 u16 val;
1991};
1992
4da19633 1993static void rtl_writephy_batch(struct rtl8169_private *tp,
1994 const struct phy_reg *regs, int len)
867763c1
FR		 1995{
1996 while (len-- > 0) {
4da19633 1997 rtl_writephy(tp, regs->reg, regs->val);
867763c1
FR		 1998 regs++;
1999 }
2000}
2001
bca03d5f 2002#define PHY_READ 0x00000000
2003#define PHY_DATA_OR 0x10000000
2004#define PHY_DATA_AND 0x20000000
2005#define PHY_BJMPN 0x30000000
2006#define PHY_READ_EFUSE 0x40000000
2007#define PHY_READ_MAC_BYTE 0x50000000
2008#define PHY_WRITE_MAC_BYTE 0x60000000
2009#define PHY_CLEAR_READCOUNT 0x70000000
2010#define PHY_WRITE 0x80000000
2011#define PHY_READCOUNT_EQ_SKIP 0x90000000
2012#define PHY_COMP_EQ_SKIPN 0xa0000000
2013#define PHY_COMP_NEQ_SKIPN 0xb0000000
2014#define PHY_WRITE_PREVIOUS 0xc0000000
2015#define PHY_SKIPN 0xd0000000
2016#define PHY_DELAY_MS 0xe0000000
2017#define PHY_WRITE_ERI_WORD 0xf0000000
2018
960aee6c
HW		 2019struct fw_info {
2020 u32 magic;
2021 char version[RTL_VER_SIZE];
2022 __le32 fw_start;
2023 __le32 fw_len;
2024 u8 chksum;
2025} __packed;
2026
1c361efb
FR		 2027#define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2028
2029static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
bca03d5f 2030{
b6ffd97f 2031 const struct firmware *fw = rtl_fw->fw;
960aee6c 2032 struct fw_info *fw_info = (struct fw_info *)fw->data;
1c361efb
FR		 2033 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2034 char *version = rtl_fw->version;
2035 bool rc = false;
2036
2037 if (fw->size < FW_OPCODE_SIZE)
2038 goto out;
960aee6c
HW		 2039
2040 if (!fw_info->magic) {
2041 size_t i, size, start;
2042 u8 checksum = 0;
2043
2044 if (fw->size < sizeof(*fw_info))
2045 goto out;
2046
2047 for (i = 0; i < fw->size; i++)
2048 checksum += fw->data[i];
2049 if (checksum != 0)
2050 goto out;
2051
2052 start = le32_to_cpu(fw_info->fw_start);
2053 if (start > fw->size)
2054 goto out;
2055
2056 size = le32_to_cpu(fw_info->fw_len);
2057 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2058 goto out;
2059
2060 memcpy(version, fw_info->version, RTL_VER_SIZE);
2061
2062 pa->code = (__le32 *)(fw->data + start);
2063 pa->size = size;
2064 } else {
1c361efb
FR		 2065 if (fw->size % FW_OPCODE_SIZE)
2066 goto out;
2067
2068 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2069
2070 pa->code = (__le32 *)fw->data;
2071 pa->size = fw->size / FW_OPCODE_SIZE;
2072 }
2073 version[RTL_VER_SIZE - 1] = 0;
2074
2075 rc = true;
2076out:
2077 return rc;
2078}
2079
fd112f2e
FR		 2080static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2081 struct rtl_fw_phy_action *pa)
1c361efb 2082{
fd112f2e 2083 bool rc = false;
1c361efb 2084 size_t index;
bca03d5f 2085
1c361efb
FR		 2086 for (index = 0; index < pa->size; index++) {
2087 u32 action = le32_to_cpu(pa->code[index]);
42b82dc1 2088 u32 regno = (action & 0x0fff0000) >> 16;
bca03d5f 2089
42b82dc1 2090 switch(action & 0xf0000000) {
2091 case PHY_READ:
2092 case PHY_DATA_OR:
2093 case PHY_DATA_AND:
2094 case PHY_READ_EFUSE:
2095 case PHY_CLEAR_READCOUNT:
2096 case PHY_WRITE:
2097 case PHY_WRITE_PREVIOUS:
2098 case PHY_DELAY_MS:
2099 break;
2100
2101 case PHY_BJMPN:
2102 if (regno > index) {
fd112f2e 2103 netif_err(tp, ifup, tp->dev,
cecb5fd7 2104 "Out of range of firmware\n");
fd112f2e 2105 goto out;
42b82dc1 2106 }
2107 break;
2108 case PHY_READCOUNT_EQ_SKIP:
1c361efb 2109 if (index + 2 >= pa->size) {
fd112f2e 2110 netif_err(tp, ifup, tp->dev,
cecb5fd7 2111 "Out of range of firmware\n");
fd112f2e 2112 goto out;
42b82dc1 2113 }
2114 break;
2115 case PHY_COMP_EQ_SKIPN:
2116 case PHY_COMP_NEQ_SKIPN:
2117 case PHY_SKIPN:
1c361efb 2118 if (index + 1 + regno >= pa->size) {
fd112f2e 2119 netif_err(tp, ifup, tp->dev,
cecb5fd7 2120 "Out of range of firmware\n");
fd112f2e 2121 goto out;
42b82dc1 2122 }
bca03d5f 2123 break;
2124
42b82dc1 2125 case PHY_READ_MAC_BYTE:
2126 case PHY_WRITE_MAC_BYTE:
2127 case PHY_WRITE_ERI_WORD:
2128 default:
fd112f2e 2129 netif_err(tp, ifup, tp->dev,
42b82dc1 2130 "Invalid action 0x%08x\n", action);
fd112f2e 2131 goto out;
bca03d5f 2132 }
2133 }
fd112f2e
FR		 2134 rc = true;
2135out:
2136 return rc;
2137}
bca03d5f 2138
fd112f2e
FR		 2139static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2140{
2141 struct net_device *dev = tp->dev;
2142 int rc = -EINVAL;
2143
2144 if (!rtl_fw_format_ok(tp, rtl_fw)) {
2145 netif_err(tp, ifup, dev, "invalid firwmare\n");
2146 goto out;
2147 }
2148
2149 if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2150 rc = 0;
2151out:
2152 return rc;
2153}
2154
2155static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2156{
2157 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2158 u32 predata, count;
2159 size_t index;
2160
2161 predata = count = 0;
42b82dc1 2162
1c361efb
FR		 2163 for (index = 0; index < pa->size; ) {
2164 u32 action = le32_to_cpu(pa->code[index]);
bca03d5f 2165 u32 data = action & 0x0000ffff;
42b82dc1 2166 u32 regno = (action & 0x0fff0000) >> 16;
2167
2168 if (!action)
2169 break;
bca03d5f 2170
2171 switch(action & 0xf0000000) {
42b82dc1 2172 case PHY_READ:
2173 predata = rtl_readphy(tp, regno);
2174 count++;
2175 index++;
2176 break;
2177 case PHY_DATA_OR:
2178 predata |= data;
2179 index++;
2180 break;
2181 case PHY_DATA_AND:
2182 predata &= data;
2183 index++;
2184 break;
2185 case PHY_BJMPN:
2186 index -= regno;
2187 break;
2188 case PHY_READ_EFUSE:
2189 predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
2190 index++;
2191 break;
2192 case PHY_CLEAR_READCOUNT:
2193 count = 0;
2194 index++;
2195 break;
bca03d5f 2196 case PHY_WRITE:
42b82dc1 2197 rtl_writephy(tp, regno, data);
2198 index++;
2199 break;
2200 case PHY_READCOUNT_EQ_SKIP:
cecb5fd7 2201 index += (count == data) ? 2 : 1;
bca03d5f 2202 break;
42b82dc1 2203 case PHY_COMP_EQ_SKIPN:
2204 if (predata == data)
2205 index += regno;
2206 index++;
2207 break;
2208 case PHY_COMP_NEQ_SKIPN:
2209 if (predata != data)
2210 index += regno;
2211 index++;
2212 break;
2213 case PHY_WRITE_PREVIOUS:
2214 rtl_writephy(tp, regno, predata);
2215 index++;
2216 break;
2217 case PHY_SKIPN:
2218 index += regno + 1;
2219 break;
2220 case PHY_DELAY_MS:
2221 mdelay(data);
2222 index++;
2223 break;
2224
2225 case PHY_READ_MAC_BYTE:
2226 case PHY_WRITE_MAC_BYTE:
2227 case PHY_WRITE_ERI_WORD:
bca03d5f 2228 default:
2229 BUG();
2230 }
2231 }
2232}
2233
f1e02ed1 2234static void rtl_release_firmware(struct rtl8169_private *tp)
2235{
b6ffd97f
FR		 2236 if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2237 release_firmware(tp->rtl_fw->fw);
2238 kfree(tp->rtl_fw);
2239 }
2240 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
f1e02ed1 2241}
2242
953a12cc 2243static void rtl_apply_firmware(struct rtl8169_private *tp)
f1e02ed1 2244{
b6ffd97f 2245 struct rtl_fw *rtl_fw = tp->rtl_fw;
f1e02ed1 2246
2247 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
b6ffd97f
FR		 2248 if (!IS_ERR_OR_NULL(rtl_fw))
2249 rtl_phy_write_fw(tp, rtl_fw);
953a12cc
FR		 2250}
2251
2252static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2253{
2254 if (rtl_readphy(tp, reg) != val)
2255 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2256 else
2257 rtl_apply_firmware(tp);
f1e02ed1 2258}
2259
4da19633 2260static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1da177e4 2261{
350f7596 2262 static const struct phy_reg phy_reg_init[] = {
0b9b571d 2263 { 0x1f, 0x0001 },
2264 { 0x06, 0x006e },
2265 { 0x08, 0x0708 },
2266 { 0x15, 0x4000 },
2267 { 0x18, 0x65c7 },
1da177e4 2268
0b9b571d 2269 { 0x1f, 0x0001 },
2270 { 0x03, 0x00a1 },
2271 { 0x02, 0x0008 },
2272 { 0x01, 0x0120 },
2273 { 0x00, 0x1000 },
2274 { 0x04, 0x0800 },
2275 { 0x04, 0x0000 },
1da177e4 2276
0b9b571d 2277 { 0x03, 0xff41 },
2278 { 0x02, 0xdf60 },
2279 { 0x01, 0x0140 },
2280 { 0x00, 0x0077 },
2281 { 0x04, 0x7800 },
2282 { 0x04, 0x7000 },
2283
2284 { 0x03, 0x802f },
2285 { 0x02, 0x4f02 },
2286 { 0x01, 0x0409 },
2287 { 0x00, 0xf0f9 },
2288 { 0x04, 0x9800 },
2289 { 0x04, 0x9000 },
2290
2291 { 0x03, 0xdf01 },
2292 { 0x02, 0xdf20 },
2293 { 0x01, 0xff95 },
2294 { 0x00, 0xba00 },
2295 { 0x04, 0xa800 },
2296 { 0x04, 0xa000 },
2297
2298 { 0x03, 0xff41 },
2299 { 0x02, 0xdf20 },
2300 { 0x01, 0x0140 },
2301 { 0x00, 0x00bb },
2302 { 0x04, 0xb800 },
2303 { 0x04, 0xb000 },
2304
2305 { 0x03, 0xdf41 },
2306 { 0x02, 0xdc60 },
2307 { 0x01, 0x6340 },
2308 { 0x00, 0x007d },
2309 { 0x04, 0xd800 },
2310 { 0x04, 0xd000 },
2311
2312 { 0x03, 0xdf01 },
2313 { 0x02, 0xdf20 },
2314 { 0x01, 0x100a },
2315 { 0x00, 0xa0ff },
2316 { 0x04, 0xf800 },
2317 { 0x04, 0xf000 },
2318
2319 { 0x1f, 0x0000 },
2320 { 0x0b, 0x0000 },
2321 { 0x00, 0x9200 }
2322 };
1da177e4 2323
4da19633 2324 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1da177e4
LT		 2325}
2326
4da19633 2327static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
5615d9f1 2328{
350f7596 2329 static const struct phy_reg phy_reg_init[] = {
a441d7b6
FR		 2330 { 0x1f, 0x0002 },
2331 { 0x01, 0x90d0 },
2332 { 0x1f, 0x0000 }
2333 };
2334
4da19633 2335 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5615d9f1
FR		 2336}
2337
4da19633 2338static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2e955856 2339{
2340 struct pci_dev *pdev = tp->pci_dev;
2e955856 2341
ccbae55e
SS		 2342 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2343 (pdev->subsystem_device != 0xe000))
2e955856 2344 return;
2345
4da19633 2346 rtl_writephy(tp, 0x1f, 0x0001);
2347 rtl_writephy(tp, 0x10, 0xf01b);
2348 rtl_writephy(tp, 0x1f, 0x0000);
2e955856 2349}
2350
4da19633 2351static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2e955856 2352{
350f7596 2353 static const struct phy_reg phy_reg_init[] = {
2e955856 2354 { 0x1f, 0x0001 },
2355 { 0x04, 0x0000 },
2356 { 0x03, 0x00a1 },
2357 { 0x02, 0x0008 },
2358 { 0x01, 0x0120 },
2359 { 0x00, 0x1000 },
2360 { 0x04, 0x0800 },
2361 { 0x04, 0x9000 },
2362 { 0x03, 0x802f },
2363 { 0x02, 0x4f02 },
2364 { 0x01, 0x0409 },
2365 { 0x00, 0xf099 },
2366 { 0x04, 0x9800 },
2367 { 0x04, 0xa000 },
2368 { 0x03, 0xdf01 },
2369 { 0x02, 0xdf20 },
2370 { 0x01, 0xff95 },
2371 { 0x00, 0xba00 },
2372 { 0x04, 0xa800 },
2373 { 0x04, 0xf000 },
2374 { 0x03, 0xdf01 },
2375 { 0x02, 0xdf20 },
2376 { 0x01, 0x101a },
2377 { 0x00, 0xa0ff },
2378 { 0x04, 0xf800 },
2379 { 0x04, 0x0000 },
2380 { 0x1f, 0x0000 },
2381
2382 { 0x1f, 0x0001 },
2383 { 0x10, 0xf41b },
2384 { 0x14, 0xfb54 },
2385 { 0x18, 0xf5c7 },
2386 { 0x1f, 0x0000 },
2387
2388 { 0x1f, 0x0001 },
2389 { 0x17, 0x0cc0 },
2390 { 0x1f, 0x0000 }
2391 };
2392
4da19633 2393 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2e955856 2394
4da19633 2395 rtl8169scd_hw_phy_config_quirk(tp);
2e955856 2396}
2397
4da19633 2398static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
8c7006aa 2399{
350f7596 2400 static const struct phy_reg phy_reg_init[] = {
8c7006aa 2401 { 0x1f, 0x0001 },
2402 { 0x04, 0x0000 },
2403 { 0x03, 0x00a1 },
2404 { 0x02, 0x0008 },
2405 { 0x01, 0x0120 },
2406 { 0x00, 0x1000 },
2407 { 0x04, 0x0800 },
2408 { 0x04, 0x9000 },
2409 { 0x03, 0x802f },
2410 { 0x02, 0x4f02 },
2411 { 0x01, 0x0409 },
2412 { 0x00, 0xf099 },
2413 { 0x04, 0x9800 },
2414 { 0x04, 0xa000 },
2415 { 0x03, 0xdf01 },
2416 { 0x02, 0xdf20 },
2417 { 0x01, 0xff95 },
2418 { 0x00, 0xba00 },
2419 { 0x04, 0xa800 },
2420 { 0x04, 0xf000 },
2421 { 0x03, 0xdf01 },
2422 { 0x02, 0xdf20 },
2423 { 0x01, 0x101a },
2424 { 0x00, 0xa0ff },
2425 { 0x04, 0xf800 },
2426 { 0x04, 0x0000 },
2427 { 0x1f, 0x0000 },
2428
2429 { 0x1f, 0x0001 },
2430 { 0x0b, 0x8480 },
2431 { 0x1f, 0x0000 },
2432
2433 { 0x1f, 0x0001 },
2434 { 0x18, 0x67c7 },
2435 { 0x04, 0x2000 },
2436 { 0x03, 0x002f },
2437 { 0x02, 0x4360 },
2438 { 0x01, 0x0109 },
2439 { 0x00, 0x3022 },
2440 { 0x04, 0x2800 },
2441 { 0x1f, 0x0000 },
2442
2443 { 0x1f, 0x0001 },
2444 { 0x17, 0x0cc0 },
2445 { 0x1f, 0x0000 }
2446 };
2447
4da19633 2448 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
8c7006aa 2449}
2450
4da19633 2451static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
236b8082 2452{
350f7596 2453 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2454 { 0x10, 0xf41b },
2455 { 0x1f, 0x0000 }
2456 };
2457
4da19633 2458 rtl_writephy(tp, 0x1f, 0x0001);
2459 rtl_patchphy(tp, 0x16, 1 << 0);
236b8082 2460
4da19633 2461 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2462}
2463
4da19633 2464static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
236b8082 2465{
350f7596 2466 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2467 { 0x1f, 0x0001 },
2468 { 0x10, 0xf41b },
2469 { 0x1f, 0x0000 }
2470 };
2471
4da19633 2472 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2473}
2474
4da19633 2475static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2476{
350f7596 2477 static const struct phy_reg phy_reg_init[] = {
867763c1
FR		 2478 { 0x1f, 0x0000 },
2479 { 0x1d, 0x0f00 },
2480 { 0x1f, 0x0002 },
2481 { 0x0c, 0x1ec8 },
2482 { 0x1f, 0x0000 }
2483 };
2484
4da19633 2485 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
867763c1
FR		 2486}
2487
4da19633 2488static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
ef3386f0 2489{
350f7596 2490 static const struct phy_reg phy_reg_init[] = {
ef3386f0
FR		 2491 { 0x1f, 0x0001 },
2492 { 0x1d, 0x3d98 },
2493 { 0x1f, 0x0000 }
2494 };
2495
4da19633 2496 rtl_writephy(tp, 0x1f, 0x0000);
2497 rtl_patchphy(tp, 0x14, 1 << 5);
2498 rtl_patchphy(tp, 0x0d, 1 << 5);
ef3386f0 2499
4da19633 2500 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
ef3386f0
FR		 2501}
2502
4da19633 2503static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2504{
350f7596 2505 static const struct phy_reg phy_reg_init[] = {
a3f80671
FR		 2506 { 0x1f, 0x0001 },
2507 { 0x12, 0x2300 },
867763c1
FR		 2508 { 0x1f, 0x0002 },
2509 { 0x00, 0x88d4 },
2510 { 0x01, 0x82b1 },
2511 { 0x03, 0x7002 },
2512 { 0x08, 0x9e30 },
2513 { 0x09, 0x01f0 },
2514 { 0x0a, 0x5500 },
2515 { 0x0c, 0x00c8 },
2516 { 0x1f, 0x0003 },
2517 { 0x12, 0xc096 },
2518 { 0x16, 0x000a },
f50d4275
FR		 2519 { 0x1f, 0x0000 },
2520 { 0x1f, 0x0000 },
2521 { 0x09, 0x2000 },
2522 { 0x09, 0x0000 }
867763c1
FR		 2523 };
2524
4da19633 2525 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2526
4da19633 2527 rtl_patchphy(tp, 0x14, 1 << 5);
2528 rtl_patchphy(tp, 0x0d, 1 << 5);
2529 rtl_writephy(tp, 0x1f, 0x0000);
867763c1
FR		 2530}
2531
4da19633 2532static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
7da97ec9 2533{
350f7596 2534 static const struct phy_reg phy_reg_init[] = {
f50d4275 2535 { 0x1f, 0x0001 },
7da97ec9 2536 { 0x12, 0x2300 },
f50d4275
FR		 2537 { 0x03, 0x802f },
2538 { 0x02, 0x4f02 },
2539 { 0x01, 0x0409 },
2540 { 0x00, 0xf099 },
2541 { 0x04, 0x9800 },
2542 { 0x04, 0x9000 },
2543 { 0x1d, 0x3d98 },
7da97ec9
FR		 2544 { 0x1f, 0x0002 },
2545 { 0x0c, 0x7eb8 },
f50d4275
FR		 2546 { 0x06, 0x0761 },
2547 { 0x1f, 0x0003 },
2548 { 0x16, 0x0f0a },
7da97ec9
FR		 2549 { 0x1f, 0x0000 }
2550 };
2551
4da19633 2552 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2553
4da19633 2554 rtl_patchphy(tp, 0x16, 1 << 0);
2555 rtl_patchphy(tp, 0x14, 1 << 5);
2556 rtl_patchphy(tp, 0x0d, 1 << 5);
2557 rtl_writephy(tp, 0x1f, 0x0000);
7da97ec9
FR		 2558}
2559
4da19633 2560static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
197ff761 2561{
350f7596 2562 static const struct phy_reg phy_reg_init[] = {
197ff761
FR		 2563 { 0x1f, 0x0001 },
2564 { 0x12, 0x2300 },
2565 { 0x1d, 0x3d98 },
2566 { 0x1f, 0x0002 },
2567 { 0x0c, 0x7eb8 },
2568 { 0x06, 0x5461 },
2569 { 0x1f, 0x0003 },
2570 { 0x16, 0x0f0a },
2571 { 0x1f, 0x0000 }
2572 };
2573
4da19633 2574 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
197ff761 2575
4da19633 2576 rtl_patchphy(tp, 0x16, 1 << 0);
2577 rtl_patchphy(tp, 0x14, 1 << 5);
2578 rtl_patchphy(tp, 0x0d, 1 << 5);
2579 rtl_writephy(tp, 0x1f, 0x0000);
197ff761
FR		 2580}
2581
4da19633 2582static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
6fb07058 2583{
4da19633 2584 rtl8168c_3_hw_phy_config(tp);
6fb07058
FR		 2585}
2586
bca03d5f 2587static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
5b538df9 2588{
350f7596 2589 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2590 /* Channel Estimation */
5b538df9 2591 { 0x1f, 0x0001 },
daf9df6d 2592 { 0x06, 0x4064 },
2593 { 0x07, 0x2863 },
2594 { 0x08, 0x059c },
2595 { 0x09, 0x26b4 },
2596 { 0x0a, 0x6a19 },
2597 { 0x0b, 0xdcc8 },
2598 { 0x10, 0xf06d },
2599 { 0x14, 0x7f68 },
2600 { 0x18, 0x7fd9 },
2601 { 0x1c, 0xf0ff },
2602 { 0x1d, 0x3d9c },
5b538df9 2603 { 0x1f, 0x0003 },
daf9df6d 2604 { 0x12, 0xf49f },
2605 { 0x13, 0x070b },
2606 { 0x1a, 0x05ad },
bca03d5f 2607 { 0x14, 0x94c0 },
2608
2609 /*
2610 * Tx Error Issue
cecb5fd7 2611 * Enhance line driver power
bca03d5f 2612 */
5b538df9 2613 { 0x1f, 0x0002 },
daf9df6d 2614 { 0x06, 0x5561 },
2615 { 0x1f, 0x0005 },
2616 { 0x05, 0x8332 },
bca03d5f 2617 { 0x06, 0x5561 },
2618
2619 /*
2620 * Can not link to 1Gbps with bad cable
2621 * Decrease SNR threshold form 21.07dB to 19.04dB
2622 */
2623 { 0x1f, 0x0001 },
2624 { 0x17, 0x0cc0 },
daf9df6d 2625
5b538df9 2626 { 0x1f, 0x0000 },
bca03d5f 2627 { 0x0d, 0xf880 }
daf9df6d 2628 };
bca03d5f 2629 void __iomem *ioaddr = tp->mmio_addr;
daf9df6d 2630
4da19633 2631 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
daf9df6d 2632
bca03d5f 2633 /*
2634 * Rx Error Issue
2635 * Fine Tune Switching regulator parameter
2636 */
4da19633 2637 rtl_writephy(tp, 0x1f, 0x0002);
2638 rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2639 rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
daf9df6d 2640
daf9df6d 2641 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
350f7596 2642 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2643 { 0x1f, 0x0002 },
2644 { 0x05, 0x669a },
2645 { 0x1f, 0x0005 },
2646 { 0x05, 0x8330 },
2647 { 0x06, 0x669a },
2648 { 0x1f, 0x0002 }
2649 };
2650 int val;
2651
4da19633 2652 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2653
4da19633 2654 val = rtl_readphy(tp, 0x0d);
daf9df6d 2655
2656 if ((val & 0x00ff) != 0x006c) {
350f7596 2657 static const u32 set[] = {
daf9df6d 2658 0x0065, 0x0066, 0x0067, 0x0068,
2659 0x0069, 0x006a, 0x006b, 0x006c
2660 };
2661 int i;
2662
4da19633 2663 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2664
2665 val &= 0xff00;
2666 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2667 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2668 }
2669 } else {
350f7596 2670 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2671 { 0x1f, 0x0002 },
2672 { 0x05, 0x6662 },
2673 { 0x1f, 0x0005 },
2674 { 0x05, 0x8330 },
2675 { 0x06, 0x6662 }
2676 };
2677
4da19633 2678 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2679 }
2680
bca03d5f 2681 /* RSET couple improve */
4da19633 2682 rtl_writephy(tp, 0x1f, 0x0002);
2683 rtl_patchphy(tp, 0x0d, 0x0300);
2684 rtl_patchphy(tp, 0x0f, 0x0010);
daf9df6d 2685
bca03d5f 2686 /* Fine tune PLL performance */
4da19633 2687 rtl_writephy(tp, 0x1f, 0x0002);
2688 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2689 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2690
4da19633 2691 rtl_writephy(tp, 0x1f, 0x0005);
2692 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 2693
2694 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
bca03d5f 2695
4da19633 2696 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2697}
2698
bca03d5f 2699static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2700{
350f7596 2701 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2702 /* Channel Estimation */
daf9df6d 2703 { 0x1f, 0x0001 },
2704 { 0x06, 0x4064 },
2705 { 0x07, 0x2863 },
2706 { 0x08, 0x059c },
2707 { 0x09, 0x26b4 },
2708 { 0x0a, 0x6a19 },
2709 { 0x0b, 0xdcc8 },
2710 { 0x10, 0xf06d },
2711 { 0x14, 0x7f68 },
2712 { 0x18, 0x7fd9 },
2713 { 0x1c, 0xf0ff },
2714 { 0x1d, 0x3d9c },
2715 { 0x1f, 0x0003 },
2716 { 0x12, 0xf49f },
2717 { 0x13, 0x070b },
2718 { 0x1a, 0x05ad },
2719 { 0x14, 0x94c0 },
2720
bca03d5f 2721 /*
2722 * Tx Error Issue
cecb5fd7 2723 * Enhance line driver power
bca03d5f 2724 */
daf9df6d 2725 { 0x1f, 0x0002 },
2726 { 0x06, 0x5561 },
2727 { 0x1f, 0x0005 },
2728 { 0x05, 0x8332 },
bca03d5f 2729 { 0x06, 0x5561 },
2730
2731 /*
2732 * Can not link to 1Gbps with bad cable
2733 * Decrease SNR threshold form 21.07dB to 19.04dB
2734 */
2735 { 0x1f, 0x0001 },
2736 { 0x17, 0x0cc0 },
daf9df6d 2737
2738 { 0x1f, 0x0000 },
bca03d5f 2739 { 0x0d, 0xf880 }
5b538df9 2740 };
bca03d5f 2741 void __iomem *ioaddr = tp->mmio_addr;
5b538df9 2742
4da19633 2743 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
5b538df9 2744
daf9df6d 2745 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
350f7596 2746 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2747 { 0x1f, 0x0002 },
2748 { 0x05, 0x669a },
5b538df9 2749 { 0x1f, 0x0005 },
daf9df6d 2750 { 0x05, 0x8330 },
2751 { 0x06, 0x669a },
2752
2753 { 0x1f, 0x0002 }
2754 };
2755 int val;
2756
4da19633 2757 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2758
4da19633 2759 val = rtl_readphy(tp, 0x0d);
daf9df6d 2760 if ((val & 0x00ff) != 0x006c) {
b6bc7650 2761 static const u32 set[] = {
daf9df6d 2762 0x0065, 0x0066, 0x0067, 0x0068,
2763 0x0069, 0x006a, 0x006b, 0x006c
2764 };
2765 int i;
2766
4da19633 2767 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2768
2769 val &= 0xff00;
2770 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2771 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2772 }
2773 } else {
350f7596 2774 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2775 { 0x1f, 0x0002 },
2776 { 0x05, 0x2642 },
5b538df9 2777 { 0x1f, 0x0005 },
daf9df6d 2778 { 0x05, 0x8330 },
2779 { 0x06, 0x2642 }
5b538df9
FR		 2780 };
2781
4da19633 2782 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2783 }
2784
bca03d5f 2785 /* Fine tune PLL performance */
4da19633 2786 rtl_writephy(tp, 0x1f, 0x0002);
2787 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2788 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2789
bca03d5f 2790 /* Switching regulator Slew rate */
4da19633 2791 rtl_writephy(tp, 0x1f, 0x0002);
2792 rtl_patchphy(tp, 0x0f, 0x0017);
daf9df6d 2793
4da19633 2794 rtl_writephy(tp, 0x1f, 0x0005);
2795 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 2796
2797 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
bca03d5f 2798
4da19633 2799 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2800}
2801
4da19633 2802static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2803{
350f7596 2804 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2805 { 0x1f, 0x0002 },
2806 { 0x10, 0x0008 },
2807 { 0x0d, 0x006c },
2808
2809 { 0x1f, 0x0000 },
2810 { 0x0d, 0xf880 },
2811
2812 { 0x1f, 0x0001 },
2813 { 0x17, 0x0cc0 },
2814
2815 { 0x1f, 0x0001 },
2816 { 0x0b, 0xa4d8 },
2817 { 0x09, 0x281c },
2818 { 0x07, 0x2883 },
2819 { 0x0a, 0x6b35 },
2820 { 0x1d, 0x3da4 },
2821 { 0x1c, 0xeffd },
2822 { 0x14, 0x7f52 },
2823 { 0x18, 0x7fc6 },
2824 { 0x08, 0x0601 },
2825 { 0x06, 0x4063 },
2826 { 0x10, 0xf074 },
2827 { 0x1f, 0x0003 },
2828 { 0x13, 0x0789 },
2829 { 0x12, 0xf4bd },
2830 { 0x1a, 0x04fd },
2831 { 0x14, 0x84b0 },
2832 { 0x1f, 0x0000 },
2833 { 0x00, 0x9200 },
2834
2835 { 0x1f, 0x0005 },
2836 { 0x01, 0x0340 },
2837 { 0x1f, 0x0001 },
2838 { 0x04, 0x4000 },
2839 { 0x03, 0x1d21 },
2840 { 0x02, 0x0c32 },
2841 { 0x01, 0x0200 },
2842 { 0x00, 0x5554 },
2843 { 0x04, 0x4800 },
2844 { 0x04, 0x4000 },
2845 { 0x04, 0xf000 },
2846 { 0x03, 0xdf01 },
2847 { 0x02, 0xdf20 },
2848 { 0x01, 0x101a },
2849 { 0x00, 0xa0ff },
2850 { 0x04, 0xf800 },
2851 { 0x04, 0xf000 },
2852 { 0x1f, 0x0000 },
2853
2854 { 0x1f, 0x0007 },
2855 { 0x1e, 0x0023 },
2856 { 0x16, 0x0000 },
2857 { 0x1f, 0x0000 }
2858 };
2859
4da19633 2860 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2861}
2862
e6de30d6 2863static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2864{
2865 static const struct phy_reg phy_reg_init[] = {
2866 { 0x1f, 0x0001 },
2867 { 0x17, 0x0cc0 },
2868
2869 { 0x1f, 0x0007 },
2870 { 0x1e, 0x002d },
2871 { 0x18, 0x0040 },
2872 { 0x1f, 0x0000 }
2873 };
2874
2875 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2876 rtl_patchphy(tp, 0x0d, 1 << 5);
2877}
2878
70090424 2879static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
01dc7fec 2880{
2881 static const struct phy_reg phy_reg_init[] = {
2882 /* Enable Delay cap */
2883 { 0x1f, 0x0005 },
2884 { 0x05, 0x8b80 },
2885 { 0x06, 0xc896 },
2886 { 0x1f, 0x0000 },
2887
2888 /* Channel estimation fine tune */
2889 { 0x1f, 0x0001 },
2890 { 0x0b, 0x6c20 },
2891 { 0x07, 0x2872 },
2892 { 0x1c, 0xefff },
2893 { 0x1f, 0x0003 },
2894 { 0x14, 0x6420 },
2895 { 0x1f, 0x0000 },
2896
2897 /* Update PFM & 10M TX idle timer */
2898 { 0x1f, 0x0007 },
2899 { 0x1e, 0x002f },
2900 { 0x15, 0x1919 },
2901 { 0x1f, 0x0000 },
2902
2903 { 0x1f, 0x0007 },
2904 { 0x1e, 0x00ac },
2905 { 0x18, 0x0006 },
2906 { 0x1f, 0x0000 }
2907 };
2908
15ecd039
FR		 2909 rtl_apply_firmware(tp);
2910
01dc7fec 2911 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2912
2913 /* DCO enable for 10M IDLE Power */
2914 rtl_writephy(tp, 0x1f, 0x0007);
2915 rtl_writephy(tp, 0x1e, 0x0023);
2916 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2917 rtl_writephy(tp, 0x1f, 0x0000);
2918
2919 /* For impedance matching */
2920 rtl_writephy(tp, 0x1f, 0x0002);
2921 rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
cecb5fd7 2922 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 2923
2924 /* PHY auto speed down */
2925 rtl_writephy(tp, 0x1f, 0x0007);
2926 rtl_writephy(tp, 0x1e, 0x002d);
2927 rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
2928 rtl_writephy(tp, 0x1f, 0x0000);
2929 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2930
2931 rtl_writephy(tp, 0x1f, 0x0005);
2932 rtl_writephy(tp, 0x05, 0x8b86);
2933 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2934 rtl_writephy(tp, 0x1f, 0x0000);
2935
2936 rtl_writephy(tp, 0x1f, 0x0005);
2937 rtl_writephy(tp, 0x05, 0x8b85);
2938 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2939 rtl_writephy(tp, 0x1f, 0x0007);
2940 rtl_writephy(tp, 0x1e, 0x0020);
2941 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
2942 rtl_writephy(tp, 0x1f, 0x0006);
2943 rtl_writephy(tp, 0x00, 0x5a00);
2944 rtl_writephy(tp, 0x1f, 0x0000);
2945 rtl_writephy(tp, 0x0d, 0x0007);
2946 rtl_writephy(tp, 0x0e, 0x003c);
2947 rtl_writephy(tp, 0x0d, 0x4007);
2948 rtl_writephy(tp, 0x0e, 0x0000);
2949 rtl_writephy(tp, 0x0d, 0x0000);
2950}
2951
70090424
HW		 2952static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
2953{
2954 static const struct phy_reg phy_reg_init[] = {
2955 /* Enable Delay cap */
2956 { 0x1f, 0x0004 },
2957 { 0x1f, 0x0007 },
2958 { 0x1e, 0x00ac },
2959 { 0x18, 0x0006 },
2960 { 0x1f, 0x0002 },
2961 { 0x1f, 0x0000 },
2962 { 0x1f, 0x0000 },
2963
2964 /* Channel estimation fine tune */
2965 { 0x1f, 0x0003 },
2966 { 0x09, 0xa20f },
2967 { 0x1f, 0x0000 },
2968 { 0x1f, 0x0000 },
2969
2970 /* Green Setting */
2971 { 0x1f, 0x0005 },
2972 { 0x05, 0x8b5b },
2973 { 0x06, 0x9222 },
2974 { 0x05, 0x8b6d },
2975 { 0x06, 0x8000 },
2976 { 0x05, 0x8b76 },
2977 { 0x06, 0x8000 },
2978 { 0x1f, 0x0000 }
2979 };
2980
2981 rtl_apply_firmware(tp);
2982
2983 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2984
2985 /* For 4-corner performance improve */
2986 rtl_writephy(tp, 0x1f, 0x0005);
2987 rtl_writephy(tp, 0x05, 0x8b80);
2988 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2989 rtl_writephy(tp, 0x1f, 0x0000);
2990
2991 /* PHY auto speed down */
2992 rtl_writephy(tp, 0x1f, 0x0004);
2993 rtl_writephy(tp, 0x1f, 0x0007);
2994 rtl_writephy(tp, 0x1e, 0x002d);
2995 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
2996 rtl_writephy(tp, 0x1f, 0x0002);
2997 rtl_writephy(tp, 0x1f, 0x0000);
2998 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2999
3000 /* improve 10M EEE waveform */
3001 rtl_writephy(tp, 0x1f, 0x0005);
3002 rtl_writephy(tp, 0x05, 0x8b86);
3003 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3004 rtl_writephy(tp, 0x1f, 0x0000);
3005
3006 /* Improve 2-pair detection performance */
3007 rtl_writephy(tp, 0x1f, 0x0005);
3008 rtl_writephy(tp, 0x05, 0x8b85);
3009 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3010 rtl_writephy(tp, 0x1f, 0x0000);
3011
3012 /* EEE setting */
3013 rtl_w1w0_eri(tp->mmio_addr, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003,
3014 ERIAR_EXGMAC);
3015 rtl_writephy(tp, 0x1f, 0x0005);
3016 rtl_writephy(tp, 0x05, 0x8b85);
3017 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3018 rtl_writephy(tp, 0x1f, 0x0004);
3019 rtl_writephy(tp, 0x1f, 0x0007);
3020 rtl_writephy(tp, 0x1e, 0x0020);
1b23a3e3 3021 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
70090424
HW		 3022 rtl_writephy(tp, 0x1f, 0x0002);
3023 rtl_writephy(tp, 0x1f, 0x0000);
3024 rtl_writephy(tp, 0x0d, 0x0007);
3025 rtl_writephy(tp, 0x0e, 0x003c);
3026 rtl_writephy(tp, 0x0d, 0x4007);
3027 rtl_writephy(tp, 0x0e, 0x0000);
3028 rtl_writephy(tp, 0x0d, 0x0000);
3029
3030 /* Green feature */
3031 rtl_writephy(tp, 0x1f, 0x0003);
3032 rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
3033 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
3034 rtl_writephy(tp, 0x1f, 0x0000);
3035}
3036
c2218925
HW		 3037static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3038{
3039 static const struct phy_reg phy_reg_init[] = {
3040 /* Channel estimation fine tune */
3041 { 0x1f, 0x0003 },
3042 { 0x09, 0xa20f },
3043 { 0x1f, 0x0000 },
3044
3045 /* Modify green table for giga & fnet */
3046 { 0x1f, 0x0005 },
3047 { 0x05, 0x8b55 },
3048 { 0x06, 0x0000 },
3049 { 0x05, 0x8b5e },
3050 { 0x06, 0x0000 },
3051 { 0x05, 0x8b67 },
3052 { 0x06, 0x0000 },
3053 { 0x05, 0x8b70 },
3054 { 0x06, 0x0000 },
3055 { 0x1f, 0x0000 },
3056 { 0x1f, 0x0007 },
3057 { 0x1e, 0x0078 },
3058 { 0x17, 0x0000 },
3059 { 0x19, 0x00fb },
3060 { 0x1f, 0x0000 },
3061
3062 /* Modify green table for 10M */
3063 { 0x1f, 0x0005 },
3064 { 0x05, 0x8b79 },
3065 { 0x06, 0xaa00 },
3066 { 0x1f, 0x0000 },
3067
3068 /* Disable hiimpedance detection (RTCT) */
3069 { 0x1f, 0x0003 },
3070 { 0x01, 0x328a },
3071 { 0x1f, 0x0000 }
3072 };
3073
3074 rtl_apply_firmware(tp);
3075
3076 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3077
3078 /* For 4-corner performance improve */
3079 rtl_writephy(tp, 0x1f, 0x0005);
3080 rtl_writephy(tp, 0x05, 0x8b80);
3081 rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
3082 rtl_writephy(tp, 0x1f, 0x0000);
3083
3084 /* PHY auto speed down */
3085 rtl_writephy(tp, 0x1f, 0x0007);
3086 rtl_writephy(tp, 0x1e, 0x002d);
3087 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3088 rtl_writephy(tp, 0x1f, 0x0000);
3089 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3090
3091 /* Improve 10M EEE waveform */
3092 rtl_writephy(tp, 0x1f, 0x0005);
3093 rtl_writephy(tp, 0x05, 0x8b86);
3094 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3095 rtl_writephy(tp, 0x1f, 0x0000);
3096
3097 /* Improve 2-pair detection performance */
3098 rtl_writephy(tp, 0x1f, 0x0005);
3099 rtl_writephy(tp, 0x05, 0x8b85);
3100 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3101 rtl_writephy(tp, 0x1f, 0x0000);
3102}
3103
3104static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3105{
3106 rtl_apply_firmware(tp);
3107
3108 /* For 4-corner performance improve */
3109 rtl_writephy(tp, 0x1f, 0x0005);
3110 rtl_writephy(tp, 0x05, 0x8b80);
3111 rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
3112 rtl_writephy(tp, 0x1f, 0x0000);
3113
3114 /* PHY auto speed down */
3115 rtl_writephy(tp, 0x1f, 0x0007);
3116 rtl_writephy(tp, 0x1e, 0x002d);
3117 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3118 rtl_writephy(tp, 0x1f, 0x0000);
3119 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3120
3121 /* Improve 10M EEE waveform */
3122 rtl_writephy(tp, 0x1f, 0x0005);
3123 rtl_writephy(tp, 0x05, 0x8b86);
3124 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3125 rtl_writephy(tp, 0x1f, 0x0000);
3126}
3127
4da19633 3128static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2857ffb7 3129{
350f7596 3130 static const struct phy_reg phy_reg_init[] = {
2857ffb7
FR		 3131 { 0x1f, 0x0003 },
3132 { 0x08, 0x441d },
3133 { 0x01, 0x9100 },
3134 { 0x1f, 0x0000 }
3135 };
3136
4da19633 3137 rtl_writephy(tp, 0x1f, 0x0000);
3138 rtl_patchphy(tp, 0x11, 1 << 12);
3139 rtl_patchphy(tp, 0x19, 1 << 13);
3140 rtl_patchphy(tp, 0x10, 1 << 15);
2857ffb7 3141
4da19633 3142 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2857ffb7
FR		 3143}
3144
5a5e4443
HW		 3145static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3146{
3147 static const struct phy_reg phy_reg_init[] = {
3148 { 0x1f, 0x0005 },
3149 { 0x1a, 0x0000 },
3150 { 0x1f, 0x0000 },
3151
3152 { 0x1f, 0x0004 },
3153 { 0x1c, 0x0000 },
3154 { 0x1f, 0x0000 },
3155
3156 { 0x1f, 0x0001 },
3157 { 0x15, 0x7701 },
3158 { 0x1f, 0x0000 }
3159 };
3160
3161 /* Disable ALDPS before ram code */
3162 rtl_writephy(tp, 0x1f, 0x0000);
3163 rtl_writephy(tp, 0x18, 0x0310);
3164 msleep(100);
3165
953a12cc 3166 rtl_apply_firmware(tp);
5a5e4443
HW		 3167
3168 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3169}
3170
5615d9f1
FR		 3171static void rtl_hw_phy_config(struct net_device *dev)
3172{
3173 struct rtl8169_private *tp = netdev_priv(dev);
5615d9f1
FR		 3174
3175 rtl8169_print_mac_version(tp);
3176
3177 switch (tp->mac_version) {
3178 case RTL_GIGA_MAC_VER_01:
3179 break;
3180 case RTL_GIGA_MAC_VER_02:
3181 case RTL_GIGA_MAC_VER_03:
4da19633 3182 rtl8169s_hw_phy_config(tp);
5615d9f1
FR		 3183 break;
3184 case RTL_GIGA_MAC_VER_04:
4da19633 3185 rtl8169sb_hw_phy_config(tp);
5615d9f1 3186 break;
2e955856 3187 case RTL_GIGA_MAC_VER_05:
4da19633 3188 rtl8169scd_hw_phy_config(tp);
2e955856 3189 break;
8c7006aa 3190 case RTL_GIGA_MAC_VER_06:
4da19633 3191 rtl8169sce_hw_phy_config(tp);
8c7006aa 3192 break;
2857ffb7
FR		 3193 case RTL_GIGA_MAC_VER_07:
3194 case RTL_GIGA_MAC_VER_08:
3195 case RTL_GIGA_MAC_VER_09:
4da19633 3196 rtl8102e_hw_phy_config(tp);
2857ffb7 3197 break;
236b8082 3198 case RTL_GIGA_MAC_VER_11:
4da19633 3199 rtl8168bb_hw_phy_config(tp);
236b8082
FR		 3200 break;
3201 case RTL_GIGA_MAC_VER_12:
4da19633 3202 rtl8168bef_hw_phy_config(tp);
236b8082
FR		 3203 break;
3204 case RTL_GIGA_MAC_VER_17:
4da19633 3205 rtl8168bef_hw_phy_config(tp);
236b8082 3206 break;
867763c1 3207 case RTL_GIGA_MAC_VER_18:
4da19633 3208 rtl8168cp_1_hw_phy_config(tp);
867763c1
FR		 3209 break;
3210 case RTL_GIGA_MAC_VER_19:
4da19633 3211 rtl8168c_1_hw_phy_config(tp);
867763c1 3212 break;
7da97ec9 3213 case RTL_GIGA_MAC_VER_20:
4da19633 3214 rtl8168c_2_hw_phy_config(tp);
7da97ec9 3215 break;
197ff761 3216 case RTL_GIGA_MAC_VER_21:
4da19633 3217 rtl8168c_3_hw_phy_config(tp);
197ff761 3218 break;
6fb07058 3219 case RTL_GIGA_MAC_VER_22:
4da19633 3220 rtl8168c_4_hw_phy_config(tp);
6fb07058 3221 break;
ef3386f0 3222 case RTL_GIGA_MAC_VER_23:
7f3e3d3a 3223 case RTL_GIGA_MAC_VER_24:
4da19633 3224 rtl8168cp_2_hw_phy_config(tp);
ef3386f0 3225 break;
5b538df9 3226 case RTL_GIGA_MAC_VER_25:
bca03d5f 3227 rtl8168d_1_hw_phy_config(tp);
daf9df6d 3228 break;
3229 case RTL_GIGA_MAC_VER_26:
bca03d5f 3230 rtl8168d_2_hw_phy_config(tp);
daf9df6d 3231 break;
3232 case RTL_GIGA_MAC_VER_27:
4da19633 3233 rtl8168d_3_hw_phy_config(tp);
5b538df9 3234 break;
e6de30d6 3235 case RTL_GIGA_MAC_VER_28:
3236 rtl8168d_4_hw_phy_config(tp);
3237 break;
5a5e4443
HW		 3238 case RTL_GIGA_MAC_VER_29:
3239 case RTL_GIGA_MAC_VER_30:
3240 rtl8105e_hw_phy_config(tp);
3241 break;
cecb5fd7
FR		 3242 case RTL_GIGA_MAC_VER_31:
3243 /* None. */
3244 break;
01dc7fec 3245 case RTL_GIGA_MAC_VER_32:
01dc7fec 3246 case RTL_GIGA_MAC_VER_33:
70090424
HW		 3247 rtl8168e_1_hw_phy_config(tp);
3248 break;
3249 case RTL_GIGA_MAC_VER_34:
3250 rtl8168e_2_hw_phy_config(tp);
01dc7fec 3251 break;
c2218925
HW		 3252 case RTL_GIGA_MAC_VER_35:
3253 rtl8168f_1_hw_phy_config(tp);
3254 break;
3255 case RTL_GIGA_MAC_VER_36:
3256 rtl8168f_2_hw_phy_config(tp);
3257 break;
ef3386f0 3258
5615d9f1
FR		 3259 default:
3260 break;
3261 }
3262}
3263
da78dbff 3264static void rtl_phy_work(struct rtl8169_private *tp)
1da177e4 3265{
1da177e4
LT		 3266 struct timer_list *timer = &tp->timer;
3267 void __iomem *ioaddr = tp->mmio_addr;
3268 unsigned long timeout = RTL8169_PHY_TIMEOUT;
3269
bcf0bf90 3270 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1da177e4 3271
4da19633 3272 if (tp->phy_reset_pending(tp)) {
5b0384f4 3273 /*
1da177e4
LT		 3274 * A busy loop could burn quite a few cycles on nowadays CPU.
3275 * Let's delay the execution of the timer for a few ticks.
3276 */
3277 timeout = HZ/10;
3278 goto out_mod_timer;
3279 }
3280
3281 if (tp->link_ok(ioaddr))
da78dbff 3282 return;
1da177e4 3283
da78dbff 3284 netif_warn(tp, link, tp->dev, "PHY reset until link up\n");
1da177e4 3285
4da19633 3286 tp->phy_reset_enable(tp);
1da177e4
LT		 3287
3288out_mod_timer:
3289 mod_timer(timer, jiffies + timeout);
da78dbff
FR		 3290}
3291
3292static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
3293{
da78dbff
FR		 3294 if (!test_and_set_bit(flag, tp->wk.flags))
3295 schedule_work(&tp->wk.work);
da78dbff
FR		 3296}
3297
3298static void rtl8169_phy_timer(unsigned long __opaque)
3299{
3300 struct net_device *dev = (struct net_device *)__opaque;
3301 struct rtl8169_private *tp = netdev_priv(dev);
3302
98ddf986 3303 rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
1da177e4
LT		 3304}
3305
1da177e4 3306#ifdef CONFIG_NET_POLL_CONTROLLER
1da177e4
LT		 3307static void rtl8169_netpoll(struct net_device *dev)
3308{
3309 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 3310
da78dbff 3311 rtl8169_interrupt(tp->pci_dev->irq, dev);
1da177e4
LT		 3312}
3313#endif
3314
3315static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
3316 void __iomem *ioaddr)
3317{
3318 iounmap(ioaddr);
3319 pci_release_regions(pdev);
87aeec76 3320 pci_clear_mwi(pdev);
1da177e4
LT		 3321 pci_disable_device(pdev);
3322 free_netdev(dev);
3323}
3324
bf793295
FR		 3325static void rtl8169_phy_reset(struct net_device *dev,
3326 struct rtl8169_private *tp)
3327{
07d3f51f 3328 unsigned int i;
bf793295 3329
4da19633 3330 tp->phy_reset_enable(tp);
bf793295 3331 for (i = 0; i < 100; i++) {
4da19633 3332 if (!tp->phy_reset_pending(tp))
bf793295
FR		 3333 return;
3334 msleep(1);
3335 }
bf82c189 3336 netif_err(tp, link, dev, "PHY reset failed\n");
bf793295
FR		 3337}
3338
2544bfc0
FR		 3339static bool rtl_tbi_enabled(struct rtl8169_private *tp)
3340{
3341 void __iomem *ioaddr = tp->mmio_addr;
3342
3343 return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
3344 (RTL_R8(PHYstatus) & TBI_Enable);
3345}
3346
4ff96fa6
FR		 3347static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3348{
3349 void __iomem *ioaddr = tp->mmio_addr;
4ff96fa6 3350
5615d9f1 3351 rtl_hw_phy_config(dev);
4ff96fa6 3352
77332894
MS		 3353 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3354 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3355 RTL_W8(0x82, 0x01);
3356 }
4ff96fa6 3357
6dccd16b
FR		 3358 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3359
3360 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3361 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 3362
bcf0bf90 3363 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4ff96fa6
FR		 3364 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3365 RTL_W8(0x82, 0x01);
3366 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
4da19633 3367 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4ff96fa6
FR		 3368 }
3369
bf793295
FR		 3370 rtl8169_phy_reset(dev, tp);
3371
54405cde 3372 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
cecb5fd7
FR		 3373 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3374 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
3375 (tp->mii.supports_gmii ?
3376 ADVERTISED_1000baseT_Half |
3377 ADVERTISED_1000baseT_Full : 0));
4ff96fa6 3378
2544bfc0 3379 if (rtl_tbi_enabled(tp))
bf82c189 3380 netif_info(tp, link, dev, "TBI auto-negotiating\n");
4ff96fa6
FR		 3381}
3382
773d2021
FR		 3383static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3384{
3385 void __iomem *ioaddr = tp->mmio_addr;
3386 u32 high;
3387 u32 low;
3388
3389 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
3390 high = addr[4] | (addr[5] << 8);
3391
da78dbff 3392 rtl_lock_work(tp);
773d2021
FR		 3393
3394 RTL_W8(Cfg9346, Cfg9346_Unlock);
908ba2bf 3395
773d2021 3396 RTL_W32(MAC4, high);
908ba2bf 3397 RTL_R32(MAC4);
3398
78f1cd02 3399 RTL_W32(MAC0, low);
908ba2bf 3400 RTL_R32(MAC0);
3401
c28aa385 3402 if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
3403 const struct exgmac_reg e[] = {
3404 { .addr = 0xe0, ERIAR_MASK_1111, .val = low },
3405 { .addr = 0xe4, ERIAR_MASK_1111, .val = high },
3406 { .addr = 0xf0, ERIAR_MASK_1111, .val = low << 16 },
3407 { .addr = 0xf4, ERIAR_MASK_1111, .val = high << 16 |
3408 low >> 16 },
3409 };
3410
3411 rtl_write_exgmac_batch(ioaddr, e, ARRAY_SIZE(e));
3412 }
3413
773d2021
FR		 3414 RTL_W8(Cfg9346, Cfg9346_Lock);
3415
da78dbff 3416 rtl_unlock_work(tp);
773d2021
FR		 3417}
3418
3419static int rtl_set_mac_address(struct net_device *dev, void *p)
3420{
3421 struct rtl8169_private *tp = netdev_priv(dev);
3422 struct sockaddr *addr = p;
3423
3424 if (!is_valid_ether_addr(addr->sa_data))
3425 return -EADDRNOTAVAIL;
3426
3427 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3428
3429 rtl_rar_set(tp, dev->dev_addr);
3430
3431 return 0;
3432}
3433
5f787a1a
FR		 3434static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3435{
3436 struct rtl8169_private *tp = netdev_priv(dev);
3437 struct mii_ioctl_data *data = if_mii(ifr);
3438
8b4ab28d
FR		 3439 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
3440}
5f787a1a 3441
cecb5fd7
FR		 3442static int rtl_xmii_ioctl(struct rtl8169_private *tp,
3443 struct mii_ioctl_data *data, int cmd)
8b4ab28d 3444{
5f787a1a
FR		 3445 switch (cmd) {
3446 case SIOCGMIIPHY:
3447 data->phy_id = 32; /* Internal PHY */
3448 return 0;
3449
3450 case SIOCGMIIREG:
4da19633 3451 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
5f787a1a
FR		 3452 return 0;
3453
3454 case SIOCSMIIREG:
4da19633 3455 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
5f787a1a
FR		 3456 return 0;
3457 }
3458 return -EOPNOTSUPP;
3459}
3460
8b4ab28d
FR		 3461static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
3462{
3463 return -EOPNOTSUPP;
3464}
3465
0e485150
FR		 3466static const struct rtl_cfg_info {
3467 void (*hw_start)(struct net_device *);
3468 unsigned int region;
3469 unsigned int align;
da78dbff 3470 u16 event_slow;
ccdffb9a 3471 unsigned features;
f21b75e9 3472 u8 default_ver;
0e485150
FR		 3473} rtl_cfg_infos [] = {
3474 [RTL_CFG_0] = {
3475 .hw_start = rtl_hw_start_8169,
3476 .region = 1,
e9f63f30 3477 .align = 0,
da78dbff 3478 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
f21b75e9
JD		 3479 .features = RTL_FEATURE_GMII,
3480 .default_ver = RTL_GIGA_MAC_VER_01,
0e485150
FR		 3481 },
3482 [RTL_CFG_1] = {
3483 .hw_start = rtl_hw_start_8168,
3484 .region = 2,
3485 .align = 8,
da78dbff 3486 .event_slow = SYSErr | LinkChg | RxOverflow,
f21b75e9
JD		 3487 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
3488 .default_ver = RTL_GIGA_MAC_VER_11,
0e485150
FR		 3489 },
3490 [RTL_CFG_2] = {
3491 .hw_start = rtl_hw_start_8101,
3492 .region = 2,
3493 .align = 8,
da78dbff
FR		 3494 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
3495 PCSTimeout,
f21b75e9
JD		 3496 .features = RTL_FEATURE_MSI,
3497 .default_ver = RTL_GIGA_MAC_VER_13,
0e485150
FR		 3498 }
3499};
3500
fbac58fc 3501/* Cfg9346_Unlock assumed. */
2ca6cf06 3502static unsigned rtl_try_msi(struct rtl8169_private *tp,
fbac58fc
FR		 3503 const struct rtl_cfg_info *cfg)
3504{
2ca6cf06 3505 void __iomem *ioaddr = tp->mmio_addr;
fbac58fc
FR		 3506 unsigned msi = 0;
3507 u8 cfg2;
3508
3509 cfg2 = RTL_R8(Config2) & ~MSIEnable;
ccdffb9a 3510 if (cfg->features & RTL_FEATURE_MSI) {
2ca6cf06 3511 if (pci_enable_msi(tp->pci_dev)) {
3512 netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
fbac58fc
FR		 3513 } else {
3514 cfg2 |= MSIEnable;
3515 msi = RTL_FEATURE_MSI;
3516 }
3517 }
2ca6cf06 3518 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3519 RTL_W8(Config2, cfg2);
fbac58fc
FR		 3520 return msi;
3521}
3522
3523static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
3524{
3525 if (tp->features & RTL_FEATURE_MSI) {
3526 pci_disable_msi(pdev);
3527 tp->features &= ~RTL_FEATURE_MSI;
3528 }
3529}
3530
8b4ab28d
FR		 3531static const struct net_device_ops rtl8169_netdev_ops = {
3532 .ndo_open = rtl8169_open,
3533 .ndo_stop = rtl8169_close,
8027aa24 3534 .ndo_get_stats64 = rtl8169_get_stats64,
00829823 3535 .ndo_start_xmit = rtl8169_start_xmit,
8b4ab28d
FR		 3536 .ndo_tx_timeout = rtl8169_tx_timeout,
3537 .ndo_validate_addr = eth_validate_addr,
3538 .ndo_change_mtu = rtl8169_change_mtu,
350fb32a
MM		 3539 .ndo_fix_features = rtl8169_fix_features,
3540 .ndo_set_features = rtl8169_set_features,
8b4ab28d
FR		 3541 .ndo_set_mac_address = rtl_set_mac_address,
3542 .ndo_do_ioctl = rtl8169_ioctl,
afc4b13d 3543 .ndo_set_rx_mode = rtl_set_rx_mode,
8b4ab28d
FR		 3544#ifdef CONFIG_NET_POLL_CONTROLLER
3545 .ndo_poll_controller = rtl8169_netpoll,
3546#endif
3547
3548};
3549
c0e45c1c 3550static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
3551{
3552 struct mdio_ops *ops = &tp->mdio_ops;
3553
3554 switch (tp->mac_version) {
3555 case RTL_GIGA_MAC_VER_27:
3556 ops->write = r8168dp_1_mdio_write;
3557 ops->read = r8168dp_1_mdio_read;
3558 break;
e6de30d6 3559 case RTL_GIGA_MAC_VER_28:
4804b3b3 3560 case RTL_GIGA_MAC_VER_31:
e6de30d6 3561 ops->write = r8168dp_2_mdio_write;
3562 ops->read = r8168dp_2_mdio_read;
3563 break;
c0e45c1c 3564 default:
3565 ops->write = r8169_mdio_write;
3566 ops->read = r8169_mdio_read;
3567 break;
3568 }
3569}
3570
649b3b8c 3571static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
3572{
3573 void __iomem *ioaddr = tp->mmio_addr;
3574
3575 switch (tp->mac_version) {
3576 case RTL_GIGA_MAC_VER_29:
3577 case RTL_GIGA_MAC_VER_30:
3578 case RTL_GIGA_MAC_VER_32:
3579 case RTL_GIGA_MAC_VER_33:
3580 case RTL_GIGA_MAC_VER_34:
3581 RTL_W32(RxConfig, RTL_R32(RxConfig) |
3582 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3583 break;
3584 default:
3585 break;
3586 }
3587}
3588
3589static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
3590{
3591 if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
3592 return false;
3593
3594 rtl_writephy(tp, 0x1f, 0x0000);
3595 rtl_writephy(tp, MII_BMCR, 0x0000);
3596
3597 rtl_wol_suspend_quirk(tp);
3598
3599 return true;
3600}
3601
065c27c1 3602static void r810x_phy_power_down(struct rtl8169_private *tp)
3603{
3604 rtl_writephy(tp, 0x1f, 0x0000);
3605 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3606}
3607
3608static void r810x_phy_power_up(struct rtl8169_private *tp)
3609{
3610 rtl_writephy(tp, 0x1f, 0x0000);
3611 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3612}
3613
3614static void r810x_pll_power_down(struct rtl8169_private *tp)
3615{
649b3b8c 3616 if (rtl_wol_pll_power_down(tp))
065c27c1 3617 return;
065c27c1 3618
3619 r810x_phy_power_down(tp);
3620}
3621
3622static void r810x_pll_power_up(struct rtl8169_private *tp)
3623{
3624 r810x_phy_power_up(tp);
3625}
3626
3627static void r8168_phy_power_up(struct rtl8169_private *tp)
3628{
3629 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3630 switch (tp->mac_version) {
3631 case RTL_GIGA_MAC_VER_11:
3632 case RTL_GIGA_MAC_VER_12:
3633 case RTL_GIGA_MAC_VER_17:
3634 case RTL_GIGA_MAC_VER_18:
3635 case RTL_GIGA_MAC_VER_19:
3636 case RTL_GIGA_MAC_VER_20:
3637 case RTL_GIGA_MAC_VER_21:
3638 case RTL_GIGA_MAC_VER_22:
3639 case RTL_GIGA_MAC_VER_23:
3640 case RTL_GIGA_MAC_VER_24:
3641 case RTL_GIGA_MAC_VER_25:
3642 case RTL_GIGA_MAC_VER_26:
3643 case RTL_GIGA_MAC_VER_27:
3644 case RTL_GIGA_MAC_VER_28:
3645 case RTL_GIGA_MAC_VER_31:
3646 rtl_writephy(tp, 0x0e, 0x0000);
3647 break;
3648 default:
3649 break;
3650 }
065c27c1 3651 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3652}
3653
3654static void r8168_phy_power_down(struct rtl8169_private *tp)
3655{
3656 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3657 switch (tp->mac_version) {
3658 case RTL_GIGA_MAC_VER_32:
3659 case RTL_GIGA_MAC_VER_33:
3660 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
3661 break;
3662
3663 case RTL_GIGA_MAC_VER_11:
3664 case RTL_GIGA_MAC_VER_12:
3665 case RTL_GIGA_MAC_VER_17:
3666 case RTL_GIGA_MAC_VER_18:
3667 case RTL_GIGA_MAC_VER_19:
3668 case RTL_GIGA_MAC_VER_20:
3669 case RTL_GIGA_MAC_VER_21:
3670 case RTL_GIGA_MAC_VER_22:
3671 case RTL_GIGA_MAC_VER_23:
3672 case RTL_GIGA_MAC_VER_24:
3673 case RTL_GIGA_MAC_VER_25:
3674 case RTL_GIGA_MAC_VER_26:
3675 case RTL_GIGA_MAC_VER_27:
3676 case RTL_GIGA_MAC_VER_28:
3677 case RTL_GIGA_MAC_VER_31:
3678 rtl_writephy(tp, 0x0e, 0x0200);
3679 default:
3680 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3681 break;
3682 }
065c27c1 3683}
3684
3685static void r8168_pll_power_down(struct rtl8169_private *tp)
3686{
3687 void __iomem *ioaddr = tp->mmio_addr;
3688
cecb5fd7
FR		 3689 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3690 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3691 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
4804b3b3 3692 r8168dp_check_dash(tp)) {
065c27c1 3693 return;
5d2e1957 3694 }
065c27c1 3695
cecb5fd7
FR		 3696 if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
3697 tp->mac_version == RTL_GIGA_MAC_VER_24) &&
065c27c1 3698 (RTL_R16(CPlusCmd) & ASF)) {
3699 return;
3700 }
3701
01dc7fec 3702 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3703 tp->mac_version == RTL_GIGA_MAC_VER_33)
3704 rtl_ephy_write(ioaddr, 0x19, 0xff64);
3705
649b3b8c 3706 if (rtl_wol_pll_power_down(tp))
065c27c1 3707 return;
065c27c1 3708
3709 r8168_phy_power_down(tp);
3710
3711 switch (tp->mac_version) {
3712 case RTL_GIGA_MAC_VER_25:
3713 case RTL_GIGA_MAC_VER_26:
5d2e1957
HW		 3714 case RTL_GIGA_MAC_VER_27:
3715 case RTL_GIGA_MAC_VER_28:
4804b3b3 3716 case RTL_GIGA_MAC_VER_31:
01dc7fec 3717 case RTL_GIGA_MAC_VER_32:
3718 case RTL_GIGA_MAC_VER_33:
065c27c1 3719 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3720 break;
3721 }
3722}
3723
3724static void r8168_pll_power_up(struct rtl8169_private *tp)
3725{
3726 void __iomem *ioaddr = tp->mmio_addr;
3727
cecb5fd7
FR		 3728 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3729 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3730 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
4804b3b3 3731 r8168dp_check_dash(tp)) {
065c27c1 3732 return;
5d2e1957 3733 }
065c27c1 3734
3735 switch (tp->mac_version) {
3736 case RTL_GIGA_MAC_VER_25:
3737 case RTL_GIGA_MAC_VER_26:
5d2e1957
HW		 3738 case RTL_GIGA_MAC_VER_27:
3739 case RTL_GIGA_MAC_VER_28:
4804b3b3 3740 case RTL_GIGA_MAC_VER_31:
01dc7fec 3741 case RTL_GIGA_MAC_VER_32:
3742 case RTL_GIGA_MAC_VER_33:
065c27c1 3743 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3744 break;
3745 }
3746
3747 r8168_phy_power_up(tp);
3748}
3749
d58d46b5
FR		 3750static void rtl_generic_op(struct rtl8169_private *tp,
3751 void (*op)(struct rtl8169_private *))
065c27c1 3752{
3753 if (op)
3754 op(tp);
3755}
3756
3757static void rtl_pll_power_down(struct rtl8169_private *tp)
3758{
d58d46b5 3759 rtl_generic_op(tp, tp->pll_power_ops.down);
065c27c1 3760}
3761
3762static void rtl_pll_power_up(struct rtl8169_private *tp)
3763{
d58d46b5 3764 rtl_generic_op(tp, tp->pll_power_ops.up);
065c27c1 3765}
3766
3767static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
3768{
3769 struct pll_power_ops *ops = &tp->pll_power_ops;
3770
3771 switch (tp->mac_version) {
3772 case RTL_GIGA_MAC_VER_07:
3773 case RTL_GIGA_MAC_VER_08:
3774 case RTL_GIGA_MAC_VER_09:
3775 case RTL_GIGA_MAC_VER_10:
3776 case RTL_GIGA_MAC_VER_16:
5a5e4443
HW		 3777 case RTL_GIGA_MAC_VER_29:
3778 case RTL_GIGA_MAC_VER_30:
065c27c1 3779 ops->down = r810x_pll_power_down;
3780 ops->up = r810x_pll_power_up;
3781 break;
3782
3783 case RTL_GIGA_MAC_VER_11:
3784 case RTL_GIGA_MAC_VER_12:
3785 case RTL_GIGA_MAC_VER_17:
3786 case RTL_GIGA_MAC_VER_18:
3787 case RTL_GIGA_MAC_VER_19:
3788 case RTL_GIGA_MAC_VER_20:
3789 case RTL_GIGA_MAC_VER_21:
3790 case RTL_GIGA_MAC_VER_22:
3791 case RTL_GIGA_MAC_VER_23:
3792 case RTL_GIGA_MAC_VER_24:
3793 case RTL_GIGA_MAC_VER_25:
3794 case RTL_GIGA_MAC_VER_26:
3795 case RTL_GIGA_MAC_VER_27:
e6de30d6 3796 case RTL_GIGA_MAC_VER_28:
4804b3b3 3797 case RTL_GIGA_MAC_VER_31:
01dc7fec 3798 case RTL_GIGA_MAC_VER_32:
3799 case RTL_GIGA_MAC_VER_33:
70090424 3800 case RTL_GIGA_MAC_VER_34:
c2218925
HW		 3801 case RTL_GIGA_MAC_VER_35:
3802 case RTL_GIGA_MAC_VER_36:
065c27c1 3803 ops->down = r8168_pll_power_down;
3804 ops->up = r8168_pll_power_up;
3805 break;
3806
3807 default:
3808 ops->down = NULL;
3809 ops->up = NULL;
3810 break;
3811 }
3812}
3813
e542a226
HW		 3814static void rtl_init_rxcfg(struct rtl8169_private *tp)
3815{
3816 void __iomem *ioaddr = tp->mmio_addr;
3817
3818 switch (tp->mac_version) {
3819 case RTL_GIGA_MAC_VER_01:
3820 case RTL_GIGA_MAC_VER_02:
3821 case RTL_GIGA_MAC_VER_03:
3822 case RTL_GIGA_MAC_VER_04:
3823 case RTL_GIGA_MAC_VER_05:
3824 case RTL_GIGA_MAC_VER_06:
3825 case RTL_GIGA_MAC_VER_10:
3826 case RTL_GIGA_MAC_VER_11:
3827 case RTL_GIGA_MAC_VER_12:
3828 case RTL_GIGA_MAC_VER_13:
3829 case RTL_GIGA_MAC_VER_14:
3830 case RTL_GIGA_MAC_VER_15:
3831 case RTL_GIGA_MAC_VER_16:
3832 case RTL_GIGA_MAC_VER_17:
3833 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
3834 break;
3835 case RTL_GIGA_MAC_VER_18:
3836 case RTL_GIGA_MAC_VER_19:
3837 case RTL_GIGA_MAC_VER_20:
3838 case RTL_GIGA_MAC_VER_21:
3839 case RTL_GIGA_MAC_VER_22:
3840 case RTL_GIGA_MAC_VER_23:
3841 case RTL_GIGA_MAC_VER_24:
3842 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
3843 break;
3844 default:
3845 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
3846 break;
3847 }
3848}
3849
92fc43b4
HW		 3850static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
3851{
3852 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
3853}
3854
d58d46b5
FR		 3855static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
3856{
9c5028e9 3857 void __iomem *ioaddr = tp->mmio_addr;
3858
3859 RTL_W8(Cfg9346, Cfg9346_Unlock);
d58d46b5 3860 rtl_generic_op(tp, tp->jumbo_ops.enable);
9c5028e9 3861 RTL_W8(Cfg9346, Cfg9346_Lock);
d58d46b5
FR		 3862}
3863
3864static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
3865{
9c5028e9 3866 void __iomem *ioaddr = tp->mmio_addr;
3867
3868 RTL_W8(Cfg9346, Cfg9346_Unlock);
d58d46b5 3869 rtl_generic_op(tp, tp->jumbo_ops.disable);
9c5028e9 3870 RTL_W8(Cfg9346, Cfg9346_Lock);
d58d46b5
FR		 3871}
3872
3873static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
3874{
3875 void __iomem *ioaddr = tp->mmio_addr;
3876
3877 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3878 RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
3879 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
3880}
3881
3882static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
3883{
3884 void __iomem *ioaddr = tp->mmio_addr;
3885
3886 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3887 RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
3888 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
3889}
3890
3891static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
3892{
3893 void __iomem *ioaddr = tp->mmio_addr;
3894
3895 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3896}
3897
3898static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
3899{
3900 void __iomem *ioaddr = tp->mmio_addr;
3901
3902 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3903}
3904
3905static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
3906{
3907 void __iomem *ioaddr = tp->mmio_addr;
d58d46b5
FR		 3908
3909 RTL_W8(MaxTxPacketSize, 0x3f);
3910 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3911 RTL_W8(Config4, RTL_R8(Config4) | 0x01);
4512ff9f 3912 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
d58d46b5
FR		 3913}
3914
3915static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
3916{
3917 void __iomem *ioaddr = tp->mmio_addr;
d58d46b5
FR		 3918
3919 RTL_W8(MaxTxPacketSize, 0x0c);
3920 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3921 RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
4512ff9f 3922 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
d58d46b5
FR		 3923}
3924
3925static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
3926{
3927 rtl_tx_performance_tweak(tp->pci_dev,
3928 (0x2 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3929}
3930
3931static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
3932{
3933 rtl_tx_performance_tweak(tp->pci_dev,
3934 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3935}
3936
3937static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
3938{
3939 void __iomem *ioaddr = tp->mmio_addr;
3940
3941 r8168b_0_hw_jumbo_enable(tp);
3942
3943 RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
3944}
3945
3946static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
3947{
3948 void __iomem *ioaddr = tp->mmio_addr;
3949
3950 r8168b_0_hw_jumbo_disable(tp);
3951
3952 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
3953}
3954
3955static void __devinit rtl_init_jumbo_ops(struct rtl8169_private *tp)
3956{
3957 struct jumbo_ops *ops = &tp->jumbo_ops;
3958
3959 switch (tp->mac_version) {
3960 case RTL_GIGA_MAC_VER_11:
3961 ops->disable = r8168b_0_hw_jumbo_disable;
3962 ops->enable = r8168b_0_hw_jumbo_enable;
3963 break;
3964 case RTL_GIGA_MAC_VER_12:
3965 case RTL_GIGA_MAC_VER_17:
3966 ops->disable = r8168b_1_hw_jumbo_disable;
3967 ops->enable = r8168b_1_hw_jumbo_enable;
3968 break;
3969 case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
3970 case RTL_GIGA_MAC_VER_19:
3971 case RTL_GIGA_MAC_VER_20:
3972 case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
3973 case RTL_GIGA_MAC_VER_22:
3974 case RTL_GIGA_MAC_VER_23:
3975 case RTL_GIGA_MAC_VER_24:
3976 case RTL_GIGA_MAC_VER_25:
3977 case RTL_GIGA_MAC_VER_26:
3978 ops->disable = r8168c_hw_jumbo_disable;
3979 ops->enable = r8168c_hw_jumbo_enable;
3980 break;
3981 case RTL_GIGA_MAC_VER_27:
3982 case RTL_GIGA_MAC_VER_28:
3983 ops->disable = r8168dp_hw_jumbo_disable;
3984 ops->enable = r8168dp_hw_jumbo_enable;
3985 break;
3986 case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
3987 case RTL_GIGA_MAC_VER_32:
3988 case RTL_GIGA_MAC_VER_33:
3989 case RTL_GIGA_MAC_VER_34:
3990 ops->disable = r8168e_hw_jumbo_disable;
3991 ops->enable = r8168e_hw_jumbo_enable;
3992 break;
3993
3994 /*
3995 * No action needed for jumbo frames with 8169.
3996 * No jumbo for 810x at all.
3997 */
3998 default:
3999 ops->disable = NULL;
4000 ops->enable = NULL;
4001 break;
4002 }
4003}
4004
6f43adc8
FR		 4005static void rtl_hw_reset(struct rtl8169_private *tp)
4006{
4007 void __iomem *ioaddr = tp->mmio_addr;
4008 int i;
4009
4010 /* Soft reset the chip. */
4011 RTL_W8(ChipCmd, CmdReset);
4012
4013 /* Check that the chip has finished the reset. */
4014 for (i = 0; i < 100; i++) {
4015 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
4016 break;
92fc43b4 4017 udelay(100);
6f43adc8
FR		 4018 }
4019}
4020
1da177e4 4021static int __devinit
4ff96fa6 4022rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 4023{
0e485150
FR		 4024 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
4025 const unsigned int region = cfg->region;
1da177e4 4026 struct rtl8169_private *tp;
ccdffb9a 4027 struct mii_if_info *mii;
4ff96fa6
FR		 4028 struct net_device *dev;
4029 void __iomem *ioaddr;
2b7b4318 4030 int chipset, i;
07d3f51f 4031 int rc;
1da177e4 4032
4ff96fa6
FR		 4033 if (netif_msg_drv(&debug)) {
4034 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
4035 MODULENAME, RTL8169_VERSION);
4036 }
1da177e4 4037
1da177e4 4038 dev = alloc_etherdev(sizeof (*tp));
4ff96fa6 4039 if (!dev) {
4ff96fa6
FR		 4040 rc = -ENOMEM;
4041 goto out;
1da177e4
LT		 4042 }
4043
1da177e4 4044 SET_NETDEV_DEV(dev, &pdev->dev);
8b4ab28d 4045 dev->netdev_ops = &rtl8169_netdev_ops;
1da177e4 4046 tp = netdev_priv(dev);
c4028958 4047 tp->dev = dev;
21e197f2 4048 tp->pci_dev = pdev;
b57b7e5a 4049 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1da177e4 4050
ccdffb9a
FR		 4051 mii = &tp->mii;
4052 mii->dev = dev;
4053 mii->mdio_read = rtl_mdio_read;
4054 mii->mdio_write = rtl_mdio_write;
4055 mii->phy_id_mask = 0x1f;
4056 mii->reg_num_mask = 0x1f;
4057 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
4058
ba04c7c9
SG		 4059 /* disable ASPM completely as that cause random device stop working
4060 * problems as well as full system hangs for some PCIe devices users */
4061 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
4062 PCIE_LINK_STATE_CLKPM);
4063
1da177e4
LT		 4064 /* enable device (incl. PCI PM wakeup and hotplug setup) */
4065 rc = pci_enable_device(pdev);
b57b7e5a 4066 if (rc < 0) {
bf82c189 4067 netif_err(tp, probe, dev, "enable failure\n");
4ff96fa6 4068 goto err_out_free_dev_1;
1da177e4
LT		 4069 }
4070
87aeec76 4071 if (pci_set_mwi(pdev) < 0)
4072 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
1da177e4 4073
1da177e4 4074 /* make sure PCI base addr 1 is MMIO */
bcf0bf90 4075 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
bf82c189
JP		 4076 netif_err(tp, probe, dev,
4077 "region #%d not an MMIO resource, aborting\n",
4078 region);
1da177e4 4079 rc = -ENODEV;
87aeec76 4080 goto err_out_mwi_2;
1da177e4 4081 }
4ff96fa6 4082
1da177e4 4083 /* check for weird/broken PCI region reporting */
bcf0bf90 4084 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
bf82c189
JP		 4085 netif_err(tp, probe, dev,
4086 "Invalid PCI region size(s), aborting\n");
1da177e4 4087 rc = -ENODEV;
87aeec76 4088 goto err_out_mwi_2;
1da177e4
LT		 4089 }
4090
4091 rc = pci_request_regions(pdev, MODULENAME);
b57b7e5a 4092 if (rc < 0) {
bf82c189 4093 netif_err(tp, probe, dev, "could not request regions\n");
87aeec76 4094 goto err_out_mwi_2;
1da177e4
LT		 4095 }
4096
d24e9aaf 4097 tp->cp_cmd = RxChkSum;
1da177e4
LT		 4098
4099 if ((sizeof(dma_addr_t) > 4) &&
4300e8c7 4100 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
1da177e4
LT		 4101 tp->cp_cmd |= PCIDAC;
4102 dev->features |= NETIF_F_HIGHDMA;
4103 } else {
284901a9 4104 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 4105 if (rc < 0) {
bf82c189 4106 netif_err(tp, probe, dev, "DMA configuration failed\n");
87aeec76 4107 goto err_out_free_res_3;
1da177e4
LT		 4108 }
4109 }
4110
1da177e4 4111 /* ioremap MMIO region */
bcf0bf90 4112 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
4ff96fa6 4113 if (!ioaddr) {
bf82c189 4114 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
1da177e4 4115 rc = -EIO;
87aeec76 4116 goto err_out_free_res_3;
1da177e4 4117 }
6f43adc8 4118 tp->mmio_addr = ioaddr;
1da177e4 4119
e44daade
JM		 4120 if (!pci_is_pcie(pdev))
4121 netif_info(tp, probe, dev, "not PCI Express\n");
4300e8c7 4122
e542a226
HW		 4123 /* Identify chip attached to board */
4124 rtl8169_get_mac_version(tp, dev, cfg->default_ver);
4125
4126 rtl_init_rxcfg(tp);
4127
9085cdfa 4128 rtl_irq_disable(tp);
1da177e4 4129
6f43adc8 4130 rtl_hw_reset(tp);
1da177e4 4131
9085cdfa 4132 rtl_ack_events(tp, 0xffff);
d78ad8cb 4133
ca52efd5 4134 pci_set_master(pdev);
4135
7a8fc77b
FR		 4136 /*
4137 * Pretend we are using VLANs; This bypasses a nasty bug where
4138 * Interrupts stop flowing on high load on 8110SCd controllers.
4139 */
4140 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4141 tp->cp_cmd |= RxVlan;
4142
c0e45c1c 4143 rtl_init_mdio_ops(tp);
065c27c1 4144 rtl_init_pll_power_ops(tp);
d58d46b5 4145 rtl_init_jumbo_ops(tp);
c0e45c1c 4146
1da177e4 4147 rtl8169_print_mac_version(tp);
1da177e4 4148
85bffe6c
FR		 4149 chipset = tp->mac_version;
4150 tp->txd_version = rtl_chip_infos[chipset].txd_version;
1da177e4 4151
5d06a99f
FR		 4152 RTL_W8(Cfg9346, Cfg9346_Unlock);
4153 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
4154 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
20037fa4
BP		 4155 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
4156 tp->features |= RTL_FEATURE_WOL;
4157 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
4158 tp->features |= RTL_FEATURE_WOL;
2ca6cf06 4159 tp->features |= rtl_try_msi(tp, cfg);
5d06a99f
FR		 4160 RTL_W8(Cfg9346, Cfg9346_Lock);
4161
2544bfc0 4162 if (rtl_tbi_enabled(tp)) {
1da177e4
LT		 4163 tp->set_speed = rtl8169_set_speed_tbi;
4164 tp->get_settings = rtl8169_gset_tbi;
4165 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
4166 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
4167 tp->link_ok = rtl8169_tbi_link_ok;
8b4ab28d 4168 tp->do_ioctl = rtl_tbi_ioctl;
1da177e4
LT		 4169 } else {
4170 tp->set_speed = rtl8169_set_speed_xmii;
4171 tp->get_settings = rtl8169_gset_xmii;
4172 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
4173 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
4174 tp->link_ok = rtl8169_xmii_link_ok;
8b4ab28d 4175 tp->do_ioctl = rtl_xmii_ioctl;
1da177e4
LT		 4176 }
4177
da78dbff 4178 mutex_init(&tp->wk.mutex);
df58ef51 4179
7bf6bf48 4180 /* Get MAC address */
6a3c910c 4181 for (i = 0; i < ETH_ALEN; i++)
1da177e4 4182 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6d6525b7 4183 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4 4184
1da177e4 4185 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1da177e4
LT		 4186 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
4187 dev->irq = pdev->irq;
4188 dev->base_addr = (unsigned long) ioaddr;
1da177e4 4189
bea3348e 4190 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
1da177e4 4191
350fb32a
MM		 4192 /* don't enable SG, IP_CSUM and TSO by default - it might not work
4193 * properly for all devices */
4194 dev->features |= NETIF_F_RXCSUM |
4195 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
4196
4197 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
4198 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
4199 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
4200 NETIF_F_HIGHDMA;
4201
4202 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4203 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
4204 dev->hw_features &= ~NETIF_F_HW_VLAN_RX;
1da177e4 4205
6bbe021d 4206 dev->hw_features |= NETIF_F_RXALL;
79d0c1d2 4207 dev->hw_features |= NETIF_F_RXFCS;
6bbe021d 4208
0e485150 4209 tp->hw_start = cfg->hw_start;
da78dbff 4210 tp->event_slow = cfg->event_slow;
1da177e4 4211
e03f33af
FR		 4212 tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
4213 ~(RxBOVF | RxFOVF) : ~0;
4214
2efa53f3
FR		 4215 init_timer(&tp->timer);
4216 tp->timer.data = (unsigned long) dev;
4217 tp->timer.function = rtl8169_phy_timer;
4218
b6ffd97f 4219 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
953a12cc 4220
1da177e4 4221 rc = register_netdev(dev);
4ff96fa6 4222 if (rc < 0)
87aeec76 4223 goto err_out_msi_4;
1da177e4
LT		 4224
4225 pci_set_drvdata(pdev, dev);
4226
bf82c189 4227 netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
85bffe6c 4228 rtl_chip_infos[chipset].name, dev->base_addr, dev->dev_addr,
bf82c189 4229 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
d58d46b5
FR		 4230 if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
4231 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
4232 "tx checksumming: %s]\n",
4233 rtl_chip_infos[chipset].jumbo_max,
4234 rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
4235 }
1da177e4 4236
cecb5fd7
FR		 4237 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4238 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4239 tp->mac_version == RTL_GIGA_MAC_VER_31) {
b646d900 4240 rtl8168_driver_start(tp);
e6de30d6 4241 }
b646d900 4242
8b76ab39 4243 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
1da177e4 4244
f3ec4f87
AS		 4245 if (pci_dev_run_wake(pdev))
4246 pm_runtime_put_noidle(&pdev->dev);
e1759441 4247
0d672e9f
IV		 4248 netif_carrier_off(dev);
4249
4ff96fa6
FR		 4250out:
4251 return rc;
1da177e4 4252
87aeec76 4253err_out_msi_4:
fbac58fc 4254 rtl_disable_msi(pdev, tp);
4ff96fa6 4255 iounmap(ioaddr);
87aeec76 4256err_out_free_res_3:
4ff96fa6 4257 pci_release_regions(pdev);
87aeec76 4258err_out_mwi_2:
4ff96fa6 4259 pci_clear_mwi(pdev);
4ff96fa6
FR		 4260 pci_disable_device(pdev);
4261err_out_free_dev_1:
4262 free_netdev(dev);
4263 goto out;
1da177e4
LT		 4264}
4265
b6ffd97f 4266static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
953a12cc 4267{
b6ffd97f
FR		 4268 struct rtl_fw *rtl_fw;
4269 const char *name;
4270 int rc = -ENOMEM;
953a12cc 4271
b6ffd97f
FR		 4272 name = rtl_lookup_firmware_name(tp);
4273 if (!name)
4274 goto out_no_firmware;
953a12cc 4275
b6ffd97f
FR		 4276 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4277 if (!rtl_fw)
4278 goto err_warn;
31bd204f 4279
b6ffd97f
FR		 4280 rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
4281 if (rc < 0)
4282 goto err_free;
4283
fd112f2e
FR		 4284 rc = rtl_check_firmware(tp, rtl_fw);
4285 if (rc < 0)
4286 goto err_release_firmware;
4287
b6ffd97f
FR		 4288 tp->rtl_fw = rtl_fw;
4289out:
4290 return;
4291
fd112f2e
FR		 4292err_release_firmware:
4293 release_firmware(rtl_fw->fw);
b6ffd97f
FR		 4294err_free:
4295 kfree(rtl_fw);
4296err_warn:
4297 netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
4298 name, rc);
4299out_no_firmware:
4300 tp->rtl_fw = NULL;
4301 goto out;
4302}
4303
4304static void rtl_request_firmware(struct rtl8169_private *tp)
4305{
4306 if (IS_ERR(tp->rtl_fw))
4307 rtl_request_uncached_firmware(tp);
953a12cc
FR		 4308}
4309
4422bcd4
FR		 4310static void rtl_task(struct work_struct *);
4311
1da177e4
LT		 4312static int rtl8169_open(struct net_device *dev)
4313{
4314 struct rtl8169_private *tp = netdev_priv(dev);
eee3a96c 4315 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 4316 struct pci_dev *pdev = tp->pci_dev;
99f252b0 4317 int retval = -ENOMEM;
1da177e4 4318
e1759441 4319 pm_runtime_get_sync(&pdev->dev);
1da177e4 4320
1da177e4
LT		 4321 /*
4322 * Rx and Tx desscriptors needs 256 bytes alignment.
82553bb6 4323 * dma_alloc_coherent provides more.
1da177e4 4324 */
82553bb6
SG		 4325 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
4326 &tp->TxPhyAddr, GFP_KERNEL);
1da177e4 4327 if (!tp->TxDescArray)
e1759441 4328 goto err_pm_runtime_put;
1da177e4 4329
82553bb6
SG		 4330 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
4331 &tp->RxPhyAddr, GFP_KERNEL);
1da177e4 4332 if (!tp->RxDescArray)
99f252b0 4333 goto err_free_tx_0;
1da177e4
LT		 4334
4335 retval = rtl8169_init_ring(dev);
4336 if (retval < 0)
99f252b0 4337 goto err_free_rx_1;
1da177e4 4338
4422bcd4 4339 INIT_WORK(&tp->wk.work, rtl_task);
1da177e4 4340
99f252b0
FR		 4341 smp_mb();
4342
953a12cc
FR		 4343 rtl_request_firmware(tp);
4344
fbac58fc
FR		 4345 retval = request_irq(dev->irq, rtl8169_interrupt,
4346 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
99f252b0
FR		 4347 dev->name, dev);
4348 if (retval < 0)
953a12cc 4349 goto err_release_fw_2;
99f252b0 4350
da78dbff
FR		 4351 rtl_lock_work(tp);
4352
6c4a70c5 4353 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
da78dbff 4354
bea3348e 4355 napi_enable(&tp->napi);
bea3348e 4356
eee3a96c 4357 rtl8169_init_phy(dev, tp);
4358
da78dbff 4359 __rtl8169_set_features(dev, dev->features);
eee3a96c 4360
065c27c1 4361 rtl_pll_power_up(tp);
4362
07ce4064 4363 rtl_hw_start(dev);
1da177e4 4364
da78dbff
FR		 4365 netif_start_queue(dev);
4366
4367 rtl_unlock_work(tp);
4368
e1759441
RW		 4369 tp->saved_wolopts = 0;
4370 pm_runtime_put_noidle(&pdev->dev);
4371
eee3a96c 4372 rtl8169_check_link_status(dev, tp, ioaddr);
1da177e4
LT		 4373out:
4374 return retval;
4375
953a12cc
FR		 4376err_release_fw_2:
4377 rtl_release_firmware(tp);
99f252b0
FR		 4378 rtl8169_rx_clear(tp);
4379err_free_rx_1:
82553bb6
SG		 4380 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4381 tp->RxPhyAddr);
e1759441 4382 tp->RxDescArray = NULL;
99f252b0 4383err_free_tx_0:
82553bb6
SG		 4384 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4385 tp->TxPhyAddr);
e1759441
RW		 4386 tp->TxDescArray = NULL;
4387err_pm_runtime_put:
4388 pm_runtime_put_noidle(&pdev->dev);
1da177e4
LT		 4389 goto out;
4390}
4391
92fc43b4
HW		 4392static void rtl_rx_close(struct rtl8169_private *tp)
4393{
4394 void __iomem *ioaddr = tp->mmio_addr;
92fc43b4 4395
1687b566 4396 RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
92fc43b4
HW		 4397}
4398
e6de30d6 4399static void rtl8169_hw_reset(struct rtl8169_private *tp)
1da177e4 4400{
e6de30d6 4401 void __iomem *ioaddr = tp->mmio_addr;
4402
1da177e4 4403 /* Disable interrupts */
811fd301 4404 rtl8169_irq_mask_and_ack(tp);
1da177e4 4405
92fc43b4
HW		 4406 rtl_rx_close(tp);
4407
5d2e1957 4408 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4804b3b3 4409 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4410 tp->mac_version == RTL_GIGA_MAC_VER_31) {
e6de30d6 4411 while (RTL_R8(TxPoll) & NPQ)
4412 udelay(20);
c2218925
HW		 4413 } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
4414 tp->mac_version == RTL_GIGA_MAC_VER_35 ||
4415 tp->mac_version == RTL_GIGA_MAC_VER_36) {
c2b0c1e7 4416 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
70090424
HW		 4417 while (!(RTL_R32(TxConfig) & TXCFG_EMPTY))
4418 udelay(100);
92fc43b4
HW		 4419 } else {
4420 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4421 udelay(100);
e6de30d6 4422 }
4423
92fc43b4 4424 rtl_hw_reset(tp);
1da177e4
LT		 4425}
4426
7f796d83 4427static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
9cb427b6
FR		 4428{
4429 void __iomem *ioaddr = tp->mmio_addr;
9cb427b6
FR		 4430
4431 /* Set DMA burst size and Interframe Gap Time */
4432 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4433 (InterFrameGap << TxInterFrameGapShift));
4434}
4435
07ce4064 4436static void rtl_hw_start(struct net_device *dev)
1da177e4
LT		 4437{
4438 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 4439
07ce4064
FR		 4440 tp->hw_start(dev);
4441
da78dbff 4442 rtl_irq_enable_all(tp);
07ce4064
FR		 4443}
4444
7f796d83
FR		 4445static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
4446 void __iomem *ioaddr)
4447{
4448 /*
4449 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4450 * register to be written before TxDescAddrLow to work.
4451 * Switching from MMIO to I/O access fixes the issue as well.
4452 */
4453 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
284901a9 4454 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
7f796d83 4455 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
284901a9 4456 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
7f796d83
FR		 4457}
4458
4459static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
4460{
4461 u16 cmd;
4462
4463 cmd = RTL_R16(CPlusCmd);
4464 RTL_W16(CPlusCmd, cmd);
4465 return cmd;
4466}
4467
fdd7b4c3 4468static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
7f796d83
FR		 4469{
4470 /* Low hurts. Let's disable the filtering. */
207d6e87 4471 RTL_W16(RxMaxSize, rx_buf_sz + 1);
7f796d83
FR		 4472}
4473
6dccd16b
FR		 4474static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
4475{
3744100e 4476 static const struct rtl_cfg2_info {
6dccd16b
FR		 4477 u32 mac_version;
4478 u32 clk;
4479 u32 val;
4480 } cfg2_info [] = {
4481 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
4482 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
4483 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
4484 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3744100e
FR		 4485 };
4486 const struct rtl_cfg2_info *p = cfg2_info;
6dccd16b
FR		 4487 unsigned int i;
4488 u32 clk;
4489
4490 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
cadf1855 4491 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
6dccd16b
FR		 4492 if ((p->mac_version == mac_version) && (p->clk == clk)) {
4493 RTL_W32(0x7c, p->val);
4494 break;
4495 }
4496 }
4497}
4498
07ce4064
FR		 4499static void rtl_hw_start_8169(struct net_device *dev)
4500{
4501 struct rtl8169_private *tp = netdev_priv(dev);
4502 void __iomem *ioaddr = tp->mmio_addr;
4503 struct pci_dev *pdev = tp->pci_dev;
07ce4064 4504
9cb427b6
FR		 4505 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
4506 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
4507 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
4508 }
4509
1da177e4 4510 RTL_W8(Cfg9346, Cfg9346_Unlock);
cecb5fd7
FR		 4511 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4512 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4513 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4514 tp->mac_version == RTL_GIGA_MAC_VER_04)
9cb427b6
FR		 4515 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4516
e542a226
HW		 4517 rtl_init_rxcfg(tp);
4518
f0298f81 4519 RTL_W8(EarlyTxThres, NoEarlyTx);
1da177e4 4520
6f0333b8 4521 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
1da177e4 4522
cecb5fd7
FR		 4523 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4524 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4525 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4526 tp->mac_version == RTL_GIGA_MAC_VER_04)
c946b304 4527 rtl_set_rx_tx_config_registers(tp);
1da177e4 4528
7f796d83 4529 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1da177e4 4530
cecb5fd7
FR		 4531 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4532 tp->mac_version == RTL_GIGA_MAC_VER_03) {
06fa7358 4533 dprintk("Set MAC Reg C+CR Offset 0xE0. "
1da177e4 4534 "Bit-3 and bit-14 MUST be 1\n");
bcf0bf90 4535 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 4536 }
4537
bcf0bf90
FR		 4538 RTL_W16(CPlusCmd, tp->cp_cmd);
4539
6dccd16b
FR		 4540 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
4541
1da177e4
LT		 4542 /*
4543 * Undocumented corner. Supposedly:
4544 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4545 */
4546 RTL_W16(IntrMitigate, 0x0000);
4547
7f796d83 4548 rtl_set_rx_tx_desc_registers(tp, ioaddr);
9cb427b6 4549
cecb5fd7
FR		 4550 if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
4551 tp->mac_version != RTL_GIGA_MAC_VER_02 &&
4552 tp->mac_version != RTL_GIGA_MAC_VER_03 &&
4553 tp->mac_version != RTL_GIGA_MAC_VER_04) {
c946b304
FR		 4554 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4555 rtl_set_rx_tx_config_registers(tp);
4556 }
4557
1da177e4 4558 RTL_W8(Cfg9346, Cfg9346_Lock);
b518fa8e
FR		 4559
4560 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4561 RTL_R8(IntrMask);
1da177e4
LT		 4562
4563 RTL_W32(RxMissed, 0);
4564
07ce4064 4565 rtl_set_rx_mode(dev);
1da177e4
LT		 4566
4567 /* no early-rx interrupts */
4568 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
07ce4064 4569}
1da177e4 4570
650e8d5d 4571static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits)
dacf8154
FR		 4572{
4573 u32 csi;
4574
4575 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
650e8d5d 4576 rtl_csi_write(ioaddr, 0x070c, csi | bits);
4577}
4578
e6de30d6 4579static void rtl_csi_access_enable_1(void __iomem *ioaddr)
4580{
4581 rtl_csi_access_enable(ioaddr, 0x17000000);
4582}
4583
650e8d5d 4584static void rtl_csi_access_enable_2(void __iomem *ioaddr)
4585{
4586 rtl_csi_access_enable(ioaddr, 0x27000000);
dacf8154
FR		 4587}
4588
4589struct ephy_info {
4590 unsigned int offset;
4591 u16 mask;
4592 u16 bits;
4593};
4594
350f7596 4595static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
dacf8154
FR		 4596{
4597 u16 w;
4598
4599 while (len-- > 0) {
4600 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
4601 rtl_ephy_write(ioaddr, e->offset, w);
4602 e++;
4603 }
4604}
4605
b726e493
FR		 4606static void rtl_disable_clock_request(struct pci_dev *pdev)
4607{
e44daade 4608 int cap = pci_pcie_cap(pdev);
b726e493
FR		 4609
4610 if (cap) {
4611 u16 ctl;
4612
4613 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4614 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
4615 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4616 }
4617}
4618
e6de30d6 4619static void rtl_enable_clock_request(struct pci_dev *pdev)
4620{
e44daade 4621 int cap = pci_pcie_cap(pdev);
e6de30d6 4622
4623 if (cap) {
4624 u16 ctl;
4625
4626 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4627 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
4628 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4629 }
4630}
4631
b726e493
FR		 4632#define R8168_CPCMD_QUIRK_MASK (\
4633 EnableBist | \
4634 Mac_dbgo_oe | \
4635 Force_half_dup | \
4636 Force_rxflow_en | \
4637 Force_txflow_en | \
4638 Cxpl_dbg_sel | \
4639 ASF | \
4640 PktCntrDisable | \
4641 Mac_dbgo_sel)
4642
219a1e9d
FR		 4643static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
4644{
b726e493
FR		 4645 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4646
4647 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4648
2e68ae44
FR		 4649 rtl_tx_performance_tweak(pdev,
4650 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
219a1e9d
FR		 4651}
4652
4653static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
4654{
4655 rtl_hw_start_8168bb(ioaddr, pdev);
b726e493 4656
f0298f81 4657 RTL_W8(MaxTxPacketSize, TxPacketMax);
b726e493
FR		 4658
4659 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
219a1e9d
FR		 4660}
4661
4662static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
4663{
b726e493
FR		 4664 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
4665
4666 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4667
219a1e9d 4668 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
b726e493
FR		 4669
4670 rtl_disable_clock_request(pdev);
4671
4672 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
219a1e9d
FR		 4673}
4674
ef3386f0 4675static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
219a1e9d 4676{
350f7596 4677 static const struct ephy_info e_info_8168cp[] = {
b726e493
FR		 4678 { 0x01, 0, 0x0001 },
4679 { 0x02, 0x0800, 0x1000 },
4680 { 0x03, 0, 0x0042 },
4681 { 0x06, 0x0080, 0x0000 },
4682 { 0x07, 0, 0x2000 }
4683 };
4684
650e8d5d 4685 rtl_csi_access_enable_2(ioaddr);
b726e493
FR		 4686
4687 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
4688
219a1e9d
FR		 4689 __rtl_hw_start_8168cp(ioaddr, pdev);
4690}
4691
ef3386f0
FR		 4692static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
4693{
650e8d5d 4694 rtl_csi_access_enable_2(ioaddr);
ef3386f0
FR		 4695
4696 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4697
4698 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4699
4700 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4701}
4702
7f3e3d3a
FR		 4703static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
4704{
650e8d5d 4705 rtl_csi_access_enable_2(ioaddr);
7f3e3d3a
FR		 4706
4707 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4708
4709 /* Magic. */
4710 RTL_W8(DBG_REG, 0x20);
4711
f0298f81 4712 RTL_W8(MaxTxPacketSize, TxPacketMax);
7f3e3d3a
FR		 4713
4714 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4715
4716 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4717}
4718
219a1e9d
FR		 4719static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
4720{
350f7596 4721 static const struct ephy_info e_info_8168c_1[] = {
b726e493
FR		 4722 { 0x02, 0x0800, 0x1000 },
4723 { 0x03, 0, 0x0002 },
4724 { 0x06, 0x0080, 0x0000 }
4725 };
4726
650e8d5d 4727 rtl_csi_access_enable_2(ioaddr);
b726e493
FR		 4728
4729 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4730
4731 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
4732
219a1e9d
FR		 4733 __rtl_hw_start_8168cp(ioaddr, pdev);
4734}
4735
4736static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
4737{
350f7596 4738 static const struct ephy_info e_info_8168c_2[] = {
b726e493
FR		 4739 { 0x01, 0, 0x0001 },
4740 { 0x03, 0x0400, 0x0220 }
4741 };
4742
650e8d5d 4743 rtl_csi_access_enable_2(ioaddr);
b726e493
FR		 4744
4745 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
4746
219a1e9d
FR		 4747 __rtl_hw_start_8168cp(ioaddr, pdev);
4748}
4749
197ff761
FR		 4750static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
4751{
4752 rtl_hw_start_8168c_2(ioaddr, pdev);
4753}
4754
6fb07058
FR		 4755static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
4756{
650e8d5d 4757 rtl_csi_access_enable_2(ioaddr);
6fb07058
FR		 4758
4759 __rtl_hw_start_8168cp(ioaddr, pdev);
4760}
4761
5b538df9
FR		 4762static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
4763{
650e8d5d 4764 rtl_csi_access_enable_2(ioaddr);
5b538df9
FR		 4765
4766 rtl_disable_clock_request(pdev);
4767
f0298f81 4768 RTL_W8(MaxTxPacketSize, TxPacketMax);
5b538df9
FR		 4769
4770 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4771
4772 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4773}
4774
4804b3b3 4775static void rtl_hw_start_8168dp(void __iomem *ioaddr, struct pci_dev *pdev)
4776{
4777 rtl_csi_access_enable_1(ioaddr);
4778
4779 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4780
4781 RTL_W8(MaxTxPacketSize, TxPacketMax);
4782
4783 rtl_disable_clock_request(pdev);
4784}
4785
e6de30d6 4786static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
4787{
4788 static const struct ephy_info e_info_8168d_4[] = {
4789 { 0x0b, ~0, 0x48 },
4790 { 0x19, 0x20, 0x50 },
4791 { 0x0c, ~0, 0x20 }
4792 };
4793 int i;
4794
4795 rtl_csi_access_enable_1(ioaddr);
4796
4797 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4798
4799 RTL_W8(MaxTxPacketSize, TxPacketMax);
4800
4801 for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
4802 const struct ephy_info *e = e_info_8168d_4 + i;
4803 u16 w;
4804
4805 w = rtl_ephy_read(ioaddr, e->offset);
4806 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
4807 }
4808
4809 rtl_enable_clock_request(pdev);
4810}
4811
70090424 4812static void rtl_hw_start_8168e_1(void __iomem *ioaddr, struct pci_dev *pdev)
01dc7fec 4813{
70090424 4814 static const struct ephy_info e_info_8168e_1[] = {
01dc7fec 4815 { 0x00, 0x0200, 0x0100 },
4816 { 0x00, 0x0000, 0x0004 },
4817 { 0x06, 0x0002, 0x0001 },
4818 { 0x06, 0x0000, 0x0030 },
4819 { 0x07, 0x0000, 0x2000 },
4820 { 0x00, 0x0000, 0x0020 },
4821 { 0x03, 0x5800, 0x2000 },
4822 { 0x03, 0x0000, 0x0001 },
4823 { 0x01, 0x0800, 0x1000 },
4824 { 0x07, 0x0000, 0x4000 },
4825 { 0x1e, 0x0000, 0x2000 },
4826 { 0x19, 0xffff, 0xfe6c },
4827 { 0x0a, 0x0000, 0x0040 }
4828 };
4829
4830 rtl_csi_access_enable_2(ioaddr);
4831
70090424 4832 rtl_ephy_init(ioaddr, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
01dc7fec 4833
4834 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4835
4836 RTL_W8(MaxTxPacketSize, TxPacketMax);
4837
4838 rtl_disable_clock_request(pdev);
4839
4840 /* Reset tx FIFO pointer */
cecb5fd7
FR		 4841 RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
4842 RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
01dc7fec 4843
cecb5fd7 4844 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
01dc7fec 4845}
4846
70090424
HW		 4847static void rtl_hw_start_8168e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4848{
4849 static const struct ephy_info e_info_8168e_2[] = {
4850 { 0x09, 0x0000, 0x0080 },
4851 { 0x19, 0x0000, 0x0224 }
4852 };
4853
4854 rtl_csi_access_enable_1(ioaddr);
4855
4856 rtl_ephy_init(ioaddr, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
4857
4858 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4859
4860 rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4861 rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4862 rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
4863 rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
4864 rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
4865 rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
4866 rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4867 rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00,
4868 ERIAR_EXGMAC);
4869
3090bd9a 4870 RTL_W8(MaxTxPacketSize, EarlySize);
70090424
HW		 4871
4872 rtl_disable_clock_request(pdev);
4873
4874 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
4875 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
4876
4877 /* Adjust EEE LED frequency */
4878 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
4879
4880 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4881 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4882 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4883}
4884
c2218925
HW		 4885static void rtl_hw_start_8168f_1(void __iomem *ioaddr, struct pci_dev *pdev)
4886{
4887 static const struct ephy_info e_info_8168f_1[] = {
4888 { 0x06, 0x00c0, 0x0020 },
4889 { 0x08, 0x0001, 0x0002 },
4890 { 0x09, 0x0000, 0x0080 },
4891 { 0x19, 0x0000, 0x0224 }
4892 };
4893
4894 rtl_csi_access_enable_1(ioaddr);
4895
4896 rtl_ephy_init(ioaddr, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
4897
4898 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4899
4900 rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4901 rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4902 rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
4903 rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
4904 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
4905 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
4906 rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4907 rtl_w1w0_eri(ioaddr, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4908 rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
4909 rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
4910 rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00,
4911 ERIAR_EXGMAC);
4912
4913 RTL_W8(MaxTxPacketSize, EarlySize);
4914
4915 rtl_disable_clock_request(pdev);
4916
4917 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
4918 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
4919
4920 /* Adjust EEE LED frequency */
4921 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
4922
4923 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4924 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4925 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4926}
4927
07ce4064
FR		 4928static void rtl_hw_start_8168(struct net_device *dev)
4929{
2dd99530
FR		 4930 struct rtl8169_private *tp = netdev_priv(dev);
4931 void __iomem *ioaddr = tp->mmio_addr;
0e485150 4932 struct pci_dev *pdev = tp->pci_dev;
2dd99530
FR		 4933
4934 RTL_W8(Cfg9346, Cfg9346_Unlock);
4935
f0298f81 4936 RTL_W8(MaxTxPacketSize, TxPacketMax);
2dd99530 4937
6f0333b8 4938 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
2dd99530 4939
0e485150 4940 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2dd99530
FR		 4941
4942 RTL_W16(CPlusCmd, tp->cp_cmd);
4943
0e485150 4944 RTL_W16(IntrMitigate, 0x5151);
2dd99530 4945
0e485150 4946 /* Work around for RxFIFO overflow. */
811fd301 4947 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
da78dbff
FR		 4948 tp->event_slow |= RxFIFOOver | PCSTimeout;
4949 tp->event_slow &= ~RxOverflow;
0e485150
FR		 4950 }
4951
4952 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2dd99530 4953
b8363901
FR		 4954 rtl_set_rx_mode(dev);
4955
4956 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4957 (InterFrameGap << TxInterFrameGapShift));
2dd99530
FR		 4958
4959 RTL_R8(IntrMask);
4960
219a1e9d
FR		 4961 switch (tp->mac_version) {
4962 case RTL_GIGA_MAC_VER_11:
4963 rtl_hw_start_8168bb(ioaddr, pdev);
4804b3b3 4964 break;
219a1e9d
FR		 4965
4966 case RTL_GIGA_MAC_VER_12:
4967 case RTL_GIGA_MAC_VER_17:
4968 rtl_hw_start_8168bef(ioaddr, pdev);
4804b3b3 4969 break;
219a1e9d
FR		 4970
4971 case RTL_GIGA_MAC_VER_18:
ef3386f0 4972 rtl_hw_start_8168cp_1(ioaddr, pdev);
4804b3b3 4973 break;
219a1e9d
FR		 4974
4975 case RTL_GIGA_MAC_VER_19:
4976 rtl_hw_start_8168c_1(ioaddr, pdev);
4804b3b3 4977 break;
219a1e9d
FR		 4978
4979 case RTL_GIGA_MAC_VER_20:
4980 rtl_hw_start_8168c_2(ioaddr, pdev);
4804b3b3 4981 break;
219a1e9d 4982
197ff761
FR		 4983 case RTL_GIGA_MAC_VER_21:
4984 rtl_hw_start_8168c_3(ioaddr, pdev);
4804b3b3 4985 break;
197ff761 4986
6fb07058
FR		 4987 case RTL_GIGA_MAC_VER_22:
4988 rtl_hw_start_8168c_4(ioaddr, pdev);
4804b3b3 4989 break;
6fb07058 4990
ef3386f0
FR		 4991 case RTL_GIGA_MAC_VER_23:
4992 rtl_hw_start_8168cp_2(ioaddr, pdev);
4804b3b3 4993 break;
ef3386f0 4994
7f3e3d3a
FR		 4995 case RTL_GIGA_MAC_VER_24:
4996 rtl_hw_start_8168cp_3(ioaddr, pdev);
4804b3b3 4997 break;
7f3e3d3a 4998
5b538df9 4999 case RTL_GIGA_MAC_VER_25:
daf9df6d 5000 case RTL_GIGA_MAC_VER_26:
5001 case RTL_GIGA_MAC_VER_27:
5b538df9 5002 rtl_hw_start_8168d(ioaddr, pdev);
4804b3b3 5003 break;
5b538df9 5004
e6de30d6 5005 case RTL_GIGA_MAC_VER_28:
5006 rtl_hw_start_8168d_4(ioaddr, pdev);
4804b3b3 5007 break;
cecb5fd7 5008
4804b3b3 5009 case RTL_GIGA_MAC_VER_31:
5010 rtl_hw_start_8168dp(ioaddr, pdev);
5011 break;
5012
01dc7fec 5013 case RTL_GIGA_MAC_VER_32:
5014 case RTL_GIGA_MAC_VER_33:
70090424
HW		 5015 rtl_hw_start_8168e_1(ioaddr, pdev);
5016 break;
5017 case RTL_GIGA_MAC_VER_34:
5018 rtl_hw_start_8168e_2(ioaddr, pdev);
01dc7fec 5019 break;
e6de30d6 5020
c2218925
HW		 5021 case RTL_GIGA_MAC_VER_35:
5022 case RTL_GIGA_MAC_VER_36:
5023 rtl_hw_start_8168f_1(ioaddr, pdev);
5024 break;
5025
219a1e9d
FR		 5026 default:
5027 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
5028 dev->name, tp->mac_version);
4804b3b3 5029 break;
219a1e9d 5030 }
2dd99530 5031
0e485150
FR		 5032 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5033
b8363901
FR		 5034 RTL_W8(Cfg9346, Cfg9346_Lock);
5035
2dd99530 5036 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
07ce4064 5037}
1da177e4 5038
2857ffb7
FR		 5039#define R810X_CPCMD_QUIRK_MASK (\
5040 EnableBist | \
5041 Mac_dbgo_oe | \
5042 Force_half_dup | \
5edcc537 5043 Force_rxflow_en | \
2857ffb7
FR		 5044 Force_txflow_en | \
5045 Cxpl_dbg_sel | \
5046 ASF | \
5047 PktCntrDisable | \
d24e9aaf 5048 Mac_dbgo_sel)
2857ffb7
FR		 5049
5050static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
5051{
350f7596 5052 static const struct ephy_info e_info_8102e_1[] = {
2857ffb7
FR		 5053 { 0x01, 0, 0x6e65 },
5054 { 0x02, 0, 0x091f },
5055 { 0x03, 0, 0xc2f9 },
5056 { 0x06, 0, 0xafb5 },
5057 { 0x07, 0, 0x0e00 },
5058 { 0x19, 0, 0xec80 },
5059 { 0x01, 0, 0x2e65 },
5060 { 0x01, 0, 0x6e65 }
5061 };
5062 u8 cfg1;
5063
650e8d5d 5064 rtl_csi_access_enable_2(ioaddr);
2857ffb7
FR		 5065
5066 RTL_W8(DBG_REG, FIX_NAK_1);
5067
5068 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5069
5070 RTL_W8(Config1,
5071 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
5072 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5073
5074 cfg1 = RTL_R8(Config1);
5075 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
5076 RTL_W8(Config1, cfg1 & ~LEDS0);
5077
2857ffb7
FR		 5078 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
5079}
5080
5081static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
5082{
650e8d5d 5083 rtl_csi_access_enable_2(ioaddr);
2857ffb7
FR		 5084
5085 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5086
5087 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
5088 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2857ffb7
FR		 5089}
5090
5091static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
5092{
5093 rtl_hw_start_8102e_2(ioaddr, pdev);
5094
5095 rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
5096}
5097
5a5e4443
HW		 5098static void rtl_hw_start_8105e_1(void __iomem *ioaddr, struct pci_dev *pdev)
5099{
5100 static const struct ephy_info e_info_8105e_1[] = {
5101 { 0x07, 0, 0x4000 },
5102 { 0x19, 0, 0x0200 },
5103 { 0x19, 0, 0x0020 },
5104 { 0x1e, 0, 0x2000 },
5105 { 0x03, 0, 0x0001 },
5106 { 0x19, 0, 0x0100 },
5107 { 0x19, 0, 0x0004 },
5108 { 0x0a, 0, 0x0020 }
5109 };
5110
cecb5fd7 5111 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5a5e4443
HW		 5112 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5113
cecb5fd7 5114 /* Disable Early Tally Counter */
5a5e4443
HW		 5115 RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
5116
5117 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
4f6b00e5 5118 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5a5e4443
HW		 5119
5120 rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
5121}
5122
5123static void rtl_hw_start_8105e_2(void __iomem *ioaddr, struct pci_dev *pdev)
5124{
5125 rtl_hw_start_8105e_1(ioaddr, pdev);
5126 rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000);
5127}
5128
07ce4064
FR		 5129static void rtl_hw_start_8101(struct net_device *dev)
5130{
cdf1a608
FR		 5131 struct rtl8169_private *tp = netdev_priv(dev);
5132 void __iomem *ioaddr = tp->mmio_addr;
5133 struct pci_dev *pdev = tp->pci_dev;
5134
da78dbff
FR		 5135 if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
5136 tp->event_slow &= ~RxFIFOOver;
811fd301 5137
cecb5fd7
FR		 5138 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
5139 tp->mac_version == RTL_GIGA_MAC_VER_16) {
e44daade 5140 int cap = pci_pcie_cap(pdev);
9c14ceaf
FR		 5141
5142 if (cap) {
5143 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
5144 PCI_EXP_DEVCTL_NOSNOOP_EN);
5145 }
cdf1a608
FR		 5146 }
5147
d24e9aaf
HW		 5148 RTL_W8(Cfg9346, Cfg9346_Unlock);
5149
2857ffb7
FR		 5150 switch (tp->mac_version) {
5151 case RTL_GIGA_MAC_VER_07:
5152 rtl_hw_start_8102e_1(ioaddr, pdev);
5153 break;
5154
5155 case RTL_GIGA_MAC_VER_08:
5156 rtl_hw_start_8102e_3(ioaddr, pdev);
5157 break;
5158
5159 case RTL_GIGA_MAC_VER_09:
5160 rtl_hw_start_8102e_2(ioaddr, pdev);
5161 break;
5a5e4443
HW		 5162
5163 case RTL_GIGA_MAC_VER_29:
5164 rtl_hw_start_8105e_1(ioaddr, pdev);
5165 break;
5166 case RTL_GIGA_MAC_VER_30:
5167 rtl_hw_start_8105e_2(ioaddr, pdev);
5168 break;
cdf1a608
FR		 5169 }
5170
d24e9aaf 5171 RTL_W8(Cfg9346, Cfg9346_Lock);
cdf1a608 5172
f0298f81 5173 RTL_W8(MaxTxPacketSize, TxPacketMax);
cdf1a608 5174
6f0333b8 5175 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
cdf1a608 5176
d24e9aaf 5177 tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
cdf1a608
FR		 5178 RTL_W16(CPlusCmd, tp->cp_cmd);
5179
5180 RTL_W16(IntrMitigate, 0x0000);
5181
5182 rtl_set_rx_tx_desc_registers(tp, ioaddr);
5183
5184 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5185 rtl_set_rx_tx_config_registers(tp);
5186
cdf1a608
FR		 5187 RTL_R8(IntrMask);
5188
cdf1a608
FR		 5189 rtl_set_rx_mode(dev);
5190
5191 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
1da177e4
LT		 5192}
5193
5194static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5195{
d58d46b5
FR		 5196 struct rtl8169_private *tp = netdev_priv(dev);
5197
5198 if (new_mtu < ETH_ZLEN ||
5199 new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max)
1da177e4
LT		 5200 return -EINVAL;
5201
d58d46b5
FR		 5202 if (new_mtu > ETH_DATA_LEN)
5203 rtl_hw_jumbo_enable(tp);
5204 else
5205 rtl_hw_jumbo_disable(tp);
5206
1da177e4 5207 dev->mtu = new_mtu;
350fb32a
MM		 5208 netdev_update_features(dev);
5209
323bb685 5210 return 0;
1da177e4
LT		 5211}
5212
5213static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5214{
95e0918d 5215 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
1da177e4
LT		 5216 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5217}
5218
6f0333b8
ED		 5219static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
5220 void **data_buff, struct RxDesc *desc)
1da177e4 5221{
48addcc9 5222 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
231aee63 5223 DMA_FROM_DEVICE);
48addcc9 5224
6f0333b8
ED		 5225 kfree(*data_buff);
5226 *data_buff = NULL;
1da177e4
LT		 5227 rtl8169_make_unusable_by_asic(desc);
5228}
5229
5230static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
5231{
5232 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5233
5234 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
5235}
5236
5237static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
5238 u32 rx_buf_sz)
5239{
5240 desc->addr = cpu_to_le64(mapping);
5241 wmb();
5242 rtl8169_mark_to_asic(desc, rx_buf_sz);
5243}
5244
6f0333b8
ED		 5245static inline void *rtl8169_align(void *data)
5246{
5247 return (void *)ALIGN((long)data, 16);
5248}
5249
0ecbe1ca
SG		 5250static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5251 struct RxDesc *desc)
1da177e4 5252{
6f0333b8 5253 void *data;
1da177e4 5254 dma_addr_t mapping;
48addcc9 5255 struct device *d = &tp->pci_dev->dev;
0ecbe1ca 5256 struct net_device *dev = tp->dev;
6f0333b8 5257 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
1da177e4 5258
6f0333b8
ED		 5259 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
5260 if (!data)
5261 return NULL;
e9f63f30 5262
6f0333b8
ED		 5263 if (rtl8169_align(data) != data) {
5264 kfree(data);
5265 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
5266 if (!data)
5267 return NULL;
5268 }
3eafe507 5269
48addcc9 5270 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
231aee63 5271 DMA_FROM_DEVICE);
d827d86b
SG		 5272 if (unlikely(dma_mapping_error(d, mapping))) {
5273 if (net_ratelimit())
5274 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
3eafe507 5275 goto err_out;
d827d86b 5276 }
1da177e4
LT		 5277
5278 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
6f0333b8 5279 return data;
3eafe507
SG		 5280
5281err_out:
5282 kfree(data);
5283 return NULL;
1da177e4
LT		 5284}
5285
5286static void rtl8169_rx_clear(struct rtl8169_private *tp)
5287{
07d3f51f 5288 unsigned int i;
1da177e4
LT		 5289
5290 for (i = 0; i < NUM_RX_DESC; i++) {
6f0333b8
ED		 5291 if (tp->Rx_databuff[i]) {
5292 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
1da177e4
LT		 5293 tp->RxDescArray + i);
5294 }
5295 }
5296}
5297
0ecbe1ca 5298static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
1da177e4 5299{
0ecbe1ca
SG		 5300 desc->opts1 |= cpu_to_le32(RingEnd);
5301}
5b0384f4 5302
0ecbe1ca
SG		 5303static int rtl8169_rx_fill(struct rtl8169_private *tp)
5304{
5305 unsigned int i;
1da177e4 5306
0ecbe1ca
SG		 5307 for (i = 0; i < NUM_RX_DESC; i++) {
5308 void *data;
4ae47c2d 5309
6f0333b8 5310 if (tp->Rx_databuff[i])
1da177e4 5311 continue;
bcf0bf90 5312
0ecbe1ca 5313 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
6f0333b8
ED		 5314 if (!data) {
5315 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
0ecbe1ca 5316 goto err_out;
6f0333b8
ED		 5317 }
5318 tp->Rx_databuff[i] = data;
1da177e4 5319 }
1da177e4 5320
0ecbe1ca
SG		 5321 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5322 return 0;
5323
5324err_out:
5325 rtl8169_rx_clear(tp);
5326 return -ENOMEM;
1da177e4
LT		 5327}
5328
1da177e4
LT		 5329static int rtl8169_init_ring(struct net_device *dev)
5330{
5331 struct rtl8169_private *tp = netdev_priv(dev);
5332
5333 rtl8169_init_ring_indexes(tp);
5334
5335 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
6f0333b8 5336 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
1da177e4 5337
0ecbe1ca 5338 return rtl8169_rx_fill(tp);
1da177e4
LT		 5339}
5340
48addcc9 5341static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
1da177e4
LT		 5342 struct TxDesc *desc)
5343{
5344 unsigned int len = tx_skb->len;
5345
48addcc9
SG		 5346 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5347
1da177e4
LT		 5348 desc->opts1 = 0x00;
5349 desc->opts2 = 0x00;
5350 desc->addr = 0x00;
5351 tx_skb->len = 0;
5352}
5353
3eafe507
SG		 5354static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5355 unsigned int n)
1da177e4
LT		 5356{
5357 unsigned int i;
5358
3eafe507
SG		 5359 for (i = 0; i < n; i++) {
5360 unsigned int entry = (start + i) % NUM_TX_DESC;
1da177e4
LT		 5361 struct ring_info *tx_skb = tp->tx_skb + entry;
5362 unsigned int len = tx_skb->len;
5363
5364 if (len) {
5365 struct sk_buff *skb = tx_skb->skb;
5366
48addcc9 5367 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
1da177e4
LT		 5368 tp->TxDescArray + entry);
5369 if (skb) {
cac4b22f 5370 tp->dev->stats.tx_dropped++;
1da177e4
LT		 5371 dev_kfree_skb(skb);
5372 tx_skb->skb = NULL;
5373 }
1da177e4
LT		 5374 }
5375 }
3eafe507
SG		 5376}
5377
5378static void rtl8169_tx_clear(struct rtl8169_private *tp)
5379{
5380 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
1da177e4 5381 tp->cur_tx = tp->dirty_tx = 0;
036dafa2 5382 netdev_reset_queue(tp->dev);
1da177e4
LT		 5383}
5384
4422bcd4 5385static void rtl_reset_work(struct rtl8169_private *tp)
1da177e4 5386{
c4028958 5387 struct net_device *dev = tp->dev;
56de414c 5388 int i;
1da177e4 5389
da78dbff
FR		 5390 napi_disable(&tp->napi);
5391 netif_stop_queue(dev);
5392 synchronize_sched();
1da177e4 5393
c7c2c39b 5394 rtl8169_hw_reset(tp);
5395
56de414c
FR		 5396 for (i = 0; i < NUM_RX_DESC; i++)
5397 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
5398
1da177e4 5399 rtl8169_tx_clear(tp);
c7c2c39b 5400 rtl8169_init_ring_indexes(tp);
1da177e4 5401
da78dbff 5402 napi_enable(&tp->napi);
56de414c
FR		 5403 rtl_hw_start(dev);
5404 netif_wake_queue(dev);
5405 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1da177e4
LT		 5406}
5407
5408static void rtl8169_tx_timeout(struct net_device *dev)
5409{
da78dbff
FR		 5410 struct rtl8169_private *tp = netdev_priv(dev);
5411
5412 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
1da177e4
LT		 5413}
5414
5415static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2b7b4318 5416 u32 *opts)
1da177e4
LT		 5417{
5418 struct skb_shared_info *info = skb_shinfo(skb);
5419 unsigned int cur_frag, entry;
a6343afb 5420 struct TxDesc * uninitialized_var(txd);
48addcc9 5421 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 5422
5423 entry = tp->cur_tx;
5424 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
9e903e08 5425 const skb_frag_t *frag = info->frags + cur_frag;
1da177e4
LT		 5426 dma_addr_t mapping;
5427 u32 status, len;
5428 void *addr;
5429
5430 entry = (entry + 1) % NUM_TX_DESC;
5431
5432 txd = tp->TxDescArray + entry;
9e903e08 5433 len = skb_frag_size(frag);
929f6189 5434 addr = skb_frag_address(frag);
48addcc9 5435 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
d827d86b
SG		 5436 if (unlikely(dma_mapping_error(d, mapping))) {
5437 if (net_ratelimit())
5438 netif_err(tp, drv, tp->dev,
5439 "Failed to map TX fragments DMA!\n");
3eafe507 5440 goto err_out;
d827d86b 5441 }
1da177e4 5442
cecb5fd7 5443 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318
FR		 5444 status = opts[0] | len |
5445 (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 5446
5447 txd->opts1 = cpu_to_le32(status);
2b7b4318 5448 txd->opts2 = cpu_to_le32(opts[1]);
1da177e4
LT		 5449 txd->addr = cpu_to_le64(mapping);
5450
5451 tp->tx_skb[entry].len = len;
5452 }
5453
5454 if (cur_frag) {
5455 tp->tx_skb[entry].skb = skb;
5456 txd->opts1 |= cpu_to_le32(LastFrag);
5457 }
5458
5459 return cur_frag;
3eafe507
SG		 5460
5461err_out:
5462 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5463 return -EIO;
1da177e4
LT		 5464}
5465
2b7b4318
FR		 5466static inline void rtl8169_tso_csum(struct rtl8169_private *tp,
5467 struct sk_buff *skb, u32 *opts)
1da177e4 5468{
2b7b4318 5469 const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
350fb32a 5470 u32 mss = skb_shinfo(skb)->gso_size;
2b7b4318 5471 int offset = info->opts_offset;
350fb32a 5472
2b7b4318
FR		 5473 if (mss) {
5474 opts[0] |= TD_LSO;
5475 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
5476 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
eddc9ec5 5477 const struct iphdr *ip = ip_hdr(skb);
1da177e4
LT		 5478
5479 if (ip->protocol == IPPROTO_TCP)
2b7b4318 5480 opts[offset] |= info->checksum.tcp;
1da177e4 5481 else if (ip->protocol == IPPROTO_UDP)
2b7b4318
FR		 5482 opts[offset] |= info->checksum.udp;
5483 else
5484 WARN_ON_ONCE(1);
1da177e4 5485 }
1da177e4
LT		 5486}
5487
61357325
SH		 5488static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5489 struct net_device *dev)
1da177e4
LT		 5490{
5491 struct rtl8169_private *tp = netdev_priv(dev);
3eafe507 5492 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
1da177e4
LT		 5493 struct TxDesc *txd = tp->TxDescArray + entry;
5494 void __iomem *ioaddr = tp->mmio_addr;
48addcc9 5495 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 5496 dma_addr_t mapping;
5497 u32 status, len;
2b7b4318 5498 u32 opts[2];
3eafe507 5499 int frags;
5b0384f4 5500
1da177e4 5501 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
bf82c189 5502 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
3eafe507 5503 goto err_stop_0;
1da177e4
LT		 5504 }
5505
5506 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
3eafe507
SG		 5507 goto err_stop_0;
5508
5509 len = skb_headlen(skb);
48addcc9 5510 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
d827d86b
SG		 5511 if (unlikely(dma_mapping_error(d, mapping))) {
5512 if (net_ratelimit())
5513 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
3eafe507 5514 goto err_dma_0;
d827d86b 5515 }
3eafe507
SG		 5516
5517 tp->tx_skb[entry].len = len;
5518 txd->addr = cpu_to_le64(mapping);
1da177e4 5519
2b7b4318
FR		 5520 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
5521 opts[0] = DescOwn;
1da177e4 5522
2b7b4318
FR		 5523 rtl8169_tso_csum(tp, skb, opts);
5524
5525 frags = rtl8169_xmit_frags(tp, skb, opts);
3eafe507
SG		 5526 if (frags < 0)
5527 goto err_dma_1;
5528 else if (frags)
2b7b4318 5529 opts[0] |= FirstFrag;
3eafe507 5530 else {
2b7b4318 5531 opts[0] |= FirstFrag | LastFrag;
1da177e4
LT		 5532 tp->tx_skb[entry].skb = skb;
5533 }
5534
2b7b4318
FR		 5535 txd->opts2 = cpu_to_le32(opts[1]);
5536
036dafa2
IM		 5537 netdev_sent_queue(dev, skb->len);
5538
1da177e4
LT		 5539 wmb();
5540
cecb5fd7 5541 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318 5542 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 5543 txd->opts1 = cpu_to_le32(status);
5544
1da177e4
LT		 5545 tp->cur_tx += frags + 1;
5546
4c020a96 5547 wmb();
1da177e4 5548
cecb5fd7 5549 RTL_W8(TxPoll, NPQ);
1da177e4 5550
da78dbff
FR		 5551 mmiowb();
5552
1da177e4 5553 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
ae1f23fb
FR		 5554 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
5555 * not miss a ring update when it notices a stopped queue.
5556 */
5557 smp_wmb();
1da177e4 5558 netif_stop_queue(dev);
ae1f23fb
FR		 5559 /* Sync with rtl_tx:
5560 * - publish queue status and cur_tx ring index (write barrier)
5561 * - refresh dirty_tx ring index (read barrier).
5562 * May the current thread have a pessimistic view of the ring
5563 * status and forget to wake up queue, a racing rtl_tx thread
5564 * can't.
5565 */
1e874e04 5566 smp_mb();
1da177e4
LT		 5567 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
5568 netif_wake_queue(dev);
5569 }
5570
61357325 5571 return NETDEV_TX_OK;
1da177e4 5572
3eafe507 5573err_dma_1:
48addcc9 5574 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
3eafe507
SG		 5575err_dma_0:
5576 dev_kfree_skb(skb);
5577 dev->stats.tx_dropped++;
5578 return NETDEV_TX_OK;
5579
5580err_stop_0:
1da177e4 5581 netif_stop_queue(dev);
cebf8cc7 5582 dev->stats.tx_dropped++;
61357325 5583 return NETDEV_TX_BUSY;
1da177e4
LT		 5584}
5585
5586static void rtl8169_pcierr_interrupt(struct net_device *dev)
5587{
5588 struct rtl8169_private *tp = netdev_priv(dev);
5589 struct pci_dev *pdev = tp->pci_dev;
1da177e4
LT		 5590 u16 pci_status, pci_cmd;
5591
5592 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
5593 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
5594
bf82c189
JP		 5595 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
5596 pci_cmd, pci_status);
1da177e4
LT		 5597
5598 /*
5599 * The recovery sequence below admits a very elaborated explanation:
5600 * - it seems to work;
d03902b8
FR		 5601 * - I did not see what else could be done;
5602 * - it makes iop3xx happy.
1da177e4
LT		 5603 *
5604 * Feel free to adjust to your needs.
5605 */
a27993f3 5606 if (pdev->broken_parity_status)
d03902b8
FR		 5607 pci_cmd &= ~PCI_COMMAND_PARITY;
5608 else
5609 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
5610
5611 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 5612
5613 pci_write_config_word(pdev, PCI_STATUS,
5614 pci_status & (PCI_STATUS_DETECTED_PARITY |
5615 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
5616 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
5617
5618 /* The infamous DAC f*ckup only happens at boot time */
5619 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
e6de30d6 5620 void __iomem *ioaddr = tp->mmio_addr;
5621
bf82c189 5622 netif_info(tp, intr, dev, "disabling PCI DAC\n");
1da177e4
LT		 5623 tp->cp_cmd &= ~PCIDAC;
5624 RTL_W16(CPlusCmd, tp->cp_cmd);
5625 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 5626 }
5627
e6de30d6 5628 rtl8169_hw_reset(tp);
d03902b8 5629
98ddf986 5630 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
1da177e4
LT		 5631}
5632
036dafa2
IM		 5633struct rtl_txc {
5634 int packets;
5635 int bytes;
5636};
5637
da78dbff 5638static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
1da177e4 5639{
036dafa2 5640 struct rtl8169_stats *tx_stats = &tp->tx_stats;
1da177e4 5641 unsigned int dirty_tx, tx_left;
036dafa2 5642 struct rtl_txc txc = { 0, 0 };
1da177e4 5643
1da177e4
LT		 5644 dirty_tx = tp->dirty_tx;
5645 smp_rmb();
5646 tx_left = tp->cur_tx - dirty_tx;
5647
5648 while (tx_left > 0) {
5649 unsigned int entry = dirty_tx % NUM_TX_DESC;
5650 struct ring_info *tx_skb = tp->tx_skb + entry;
1da177e4
LT		 5651 u32 status;
5652
5653 rmb();
5654 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
5655 if (status & DescOwn)
5656 break;
5657
48addcc9
SG		 5658 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5659 tp->TxDescArray + entry);
1da177e4 5660 if (status & LastFrag) {
036dafa2
IM		 5661 struct sk_buff *skb = tx_skb->skb;
5662
5663 txc.packets++;
5664 txc.bytes += skb->len;
5665 dev_kfree_skb(skb);
1da177e4
LT		 5666 tx_skb->skb = NULL;
5667 }
5668 dirty_tx++;
5669 tx_left--;
5670 }
5671
036dafa2
IM		 5672 u64_stats_update_begin(&tx_stats->syncp);
5673 tx_stats->packets += txc.packets;
5674 tx_stats->bytes += txc.bytes;
5675 u64_stats_update_end(&tx_stats->syncp);
5676
5677 netdev_completed_queue(dev, txc.packets, txc.bytes);
5678
1da177e4
LT		 5679 if (tp->dirty_tx != dirty_tx) {
5680 tp->dirty_tx = dirty_tx;
ae1f23fb
FR		 5681 /* Sync with rtl8169_start_xmit:
5682 * - publish dirty_tx ring index (write barrier)
5683 * - refresh cur_tx ring index and queue status (read barrier)
5684 * May the current thread miss the stopped queue condition,
5685 * a racing xmit thread can only have a right view of the
5686 * ring status.
5687 */
1e874e04 5688 smp_mb();
1da177e4
LT		 5689 if (netif_queue_stopped(dev) &&
5690 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
5691 netif_wake_queue(dev);
5692 }
d78ae2dc
FR		 5693 /*
5694 * 8168 hack: TxPoll requests are lost when the Tx packets are
5695 * too close. Let's kick an extra TxPoll request when a burst
5696 * of start_xmit activity is detected (if it is not detected,
5697 * it is slow enough). -- FR
5698 */
da78dbff
FR		 5699 if (tp->cur_tx != dirty_tx) {
5700 void __iomem *ioaddr = tp->mmio_addr;
5701
d78ae2dc 5702 RTL_W8(TxPoll, NPQ);
da78dbff 5703 }
1da177e4
LT		 5704 }
5705}
5706
126fa4b9
FR		 5707static inline int rtl8169_fragmented_frame(u32 status)
5708{
5709 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
5710}
5711
adea1ac7 5712static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
1da177e4 5713{
1da177e4
LT		 5714 u32 status = opts1 & RxProtoMask;
5715
5716 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
d5d3ebe3 5717 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
1da177e4
LT		 5718 skb->ip_summed = CHECKSUM_UNNECESSARY;
5719 else
bc8acf2c 5720 skb_checksum_none_assert(skb);
1da177e4
LT		 5721}
5722
6f0333b8
ED		 5723static struct sk_buff *rtl8169_try_rx_copy(void *data,
5724 struct rtl8169_private *tp,
5725 int pkt_size,
5726 dma_addr_t addr)
1da177e4 5727{
b449655f 5728 struct sk_buff *skb;
48addcc9 5729 struct device *d = &tp->pci_dev->dev;
b449655f 5730
6f0333b8 5731 data = rtl8169_align(data);
48addcc9 5732 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6f0333b8
ED		 5733 prefetch(data);
5734 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
5735 if (skb)
5736 memcpy(skb->data, data, pkt_size);
48addcc9
SG		 5737 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
5738
6f0333b8 5739 return skb;
1da177e4
LT		 5740}
5741
da78dbff 5742static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
1da177e4
LT		 5743{
5744 unsigned int cur_rx, rx_left;
6f0333b8 5745 unsigned int count;
1da177e4 5746
1da177e4
LT		 5747 cur_rx = tp->cur_rx;
5748 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
865c652d 5749 rx_left = min(rx_left, budget);
1da177e4 5750
4dcb7d33 5751 for (; rx_left > 0; rx_left--, cur_rx++) {
1da177e4 5752 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 5753 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 5754 u32 status;
5755
5756 rmb();
e03f33af 5757 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
1da177e4
LT		 5758
5759 if (status & DescOwn)
5760 break;
4dcb7d33 5761 if (unlikely(status & RxRES)) {
bf82c189
JP		 5762 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
5763 status);
cebf8cc7 5764 dev->stats.rx_errors++;
1da177e4 5765 if (status & (RxRWT | RxRUNT))
cebf8cc7 5766 dev->stats.rx_length_errors++;
1da177e4 5767 if (status & RxCRC)
cebf8cc7 5768 dev->stats.rx_crc_errors++;
9dccf611 5769 if (status & RxFOVF) {
da78dbff 5770 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
cebf8cc7 5771 dev->stats.rx_fifo_errors++;
9dccf611 5772 }
6bbe021d
BG		 5773 if ((status & (RxRUNT | RxCRC)) &&
5774 !(status & (RxRWT | RxFOVF)) &&
5775 (dev->features & NETIF_F_RXALL))
5776 goto process_pkt;
5777
6f0333b8 5778 rtl8169_mark_to_asic(desc, rx_buf_sz);
1da177e4 5779 } else {
6f0333b8 5780 struct sk_buff *skb;
6bbe021d
BG		 5781 dma_addr_t addr;
5782 int pkt_size;
5783
5784process_pkt:
5785 addr = le64_to_cpu(desc->addr);
79d0c1d2
BG		 5786 if (likely(!(dev->features & NETIF_F_RXFCS)))
5787 pkt_size = (status & 0x00003fff) - 4;
5788 else
5789 pkt_size = status & 0x00003fff;
1da177e4 5790
126fa4b9
FR		 5791 /*
5792 * The driver does not support incoming fragmented
5793 * frames. They are seen as a symptom of over-mtu
5794 * sized frames.
5795 */
5796 if (unlikely(rtl8169_fragmented_frame(status))) {
cebf8cc7
FR		 5797 dev->stats.rx_dropped++;
5798 dev->stats.rx_length_errors++;
6f0333b8 5799 rtl8169_mark_to_asic(desc, rx_buf_sz);
4dcb7d33 5800 continue;
126fa4b9
FR		 5801 }
5802
6f0333b8
ED		 5803 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
5804 tp, pkt_size, addr);
5805 rtl8169_mark_to_asic(desc, rx_buf_sz);
5806 if (!skb) {
5807 dev->stats.rx_dropped++;
5808 continue;
1da177e4
LT		 5809 }
5810
adea1ac7 5811 rtl8169_rx_csum(skb, status);
1da177e4
LT		 5812 skb_put(skb, pkt_size);
5813 skb->protocol = eth_type_trans(skb, dev);
5814
7a8fc77b
FR		 5815 rtl8169_rx_vlan_tag(desc, skb);
5816
56de414c 5817 napi_gro_receive(&tp->napi, skb);
1da177e4 5818
8027aa24
JW		 5819 u64_stats_update_begin(&tp->rx_stats.syncp);
5820 tp->rx_stats.packets++;
5821 tp->rx_stats.bytes += pkt_size;
5822 u64_stats_update_end(&tp->rx_stats.syncp);
1da177e4 5823 }
6dccd16b
FR		 5824
5825 /* Work around for AMD plateform. */
95e0918d 5826 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
6dccd16b
FR		 5827 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
5828 desc->opts2 = 0;
5829 cur_rx++;
5830 }
1da177e4
LT		 5831 }
5832
5833 count = cur_rx - tp->cur_rx;
5834 tp->cur_rx = cur_rx;
5835
6f0333b8 5836 tp->dirty_rx += count;
1da177e4
LT		 5837
5838 return count;
5839}
5840
07d3f51f 5841static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 5842{
07d3f51f 5843 struct net_device *dev = dev_instance;
1da177e4 5844 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 5845 int handled = 0;
9085cdfa 5846 u16 status;
1da177e4 5847
9085cdfa 5848 status = rtl_get_events(tp);
da78dbff
FR		 5849 if (status && status != 0xffff) {
5850 status &= RTL_EVENT_NAPI | tp->event_slow;
5851 if (status) {
5852 handled = 1;
1da177e4 5853
da78dbff
FR		 5854 rtl_irq_disable(tp);
5855 napi_schedule(&tp->napi);
f11a377b 5856 }
da78dbff
FR		 5857 }
5858 return IRQ_RETVAL(handled);
5859}
1da177e4 5860
da78dbff
FR		 5861/*
5862 * Workqueue context.
5863 */
5864static void rtl_slow_event_work(struct rtl8169_private *tp)
5865{
5866 struct net_device *dev = tp->dev;
5867 u16 status;
5868
5869 status = rtl_get_events(tp) & tp->event_slow;
5870 rtl_ack_events(tp, status);
1da177e4 5871
da78dbff
FR		 5872 if (unlikely(status & RxFIFOOver)) {
5873 switch (tp->mac_version) {
5874 /* Work around for rx fifo overflow */
5875 case RTL_GIGA_MAC_VER_11:
5876 netif_stop_queue(dev);
934714d0
FR		 5877 /* XXX - Hack alert. See rtl_task(). */
5878 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
da78dbff 5879 default:
f11a377b
DD		 5880 break;
5881 }
da78dbff 5882 }
1da177e4 5883
da78dbff
FR		 5884 if (unlikely(status & SYSErr))
5885 rtl8169_pcierr_interrupt(dev);
0e485150 5886
da78dbff
FR		 5887 if (status & LinkChg)
5888 __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true);
1da177e4 5889
da78dbff
FR		 5890 napi_disable(&tp->napi);
5891 rtl_irq_disable(tp);
5892
5893 napi_enable(&tp->napi);
5894 napi_schedule(&tp->napi);
1da177e4
LT		 5895}
5896
4422bcd4
FR		 5897static void rtl_task(struct work_struct *work)
5898{
da78dbff
FR		 5899 static const struct {
5900 int bitnr;
5901 void (*action)(struct rtl8169_private *);
5902 } rtl_work[] = {
934714d0 5903 /* XXX - keep rtl_slow_event_work() as first element. */
da78dbff
FR		 5904 { RTL_FLAG_TASK_SLOW_PENDING, rtl_slow_event_work },
5905 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work },
5906 { RTL_FLAG_TASK_PHY_PENDING, rtl_phy_work }
5907 };
4422bcd4
FR		 5908 struct rtl8169_private *tp =
5909 container_of(work, struct rtl8169_private, wk.work);
da78dbff
FR		 5910 struct net_device *dev = tp->dev;
5911 int i;
5912
5913 rtl_lock_work(tp);
5914
6c4a70c5
FR		 5915 if (!netif_running(dev) ||
5916 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
da78dbff
FR		 5917 goto out_unlock;
5918
5919 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
5920 bool pending;
5921
da78dbff 5922 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
da78dbff
FR		 5923 if (pending)
5924 rtl_work[i].action(tp);
5925 }
4422bcd4 5926
da78dbff
FR		 5927out_unlock:
5928 rtl_unlock_work(tp);
4422bcd4
FR		 5929}
5930
bea3348e 5931static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 5932{
bea3348e
SH		 5933 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
5934 struct net_device *dev = tp->dev;
da78dbff
FR		 5935 u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
5936 int work_done= 0;
5937 u16 status;
5938
5939 status = rtl_get_events(tp);
5940 rtl_ack_events(tp, status & ~tp->event_slow);
5941
5942 if (status & RTL_EVENT_NAPI_RX)
5943 work_done = rtl_rx(dev, tp, (u32) budget);
5944
5945 if (status & RTL_EVENT_NAPI_TX)
5946 rtl_tx(dev, tp);
1da177e4 5947
da78dbff
FR		 5948 if (status & tp->event_slow) {
5949 enable_mask &= ~tp->event_slow;
5950
5951 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
5952 }
1da177e4 5953
bea3348e 5954 if (work_done < budget) {
288379f0 5955 napi_complete(napi);
f11a377b 5956
da78dbff
FR		 5957 rtl_irq_enable(tp, enable_mask);
5958 mmiowb();
1da177e4
LT		 5959 }
5960
bea3348e 5961 return work_done;
1da177e4 5962}
1da177e4 5963
523a6094
FR		 5964static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
5965{
5966 struct rtl8169_private *tp = netdev_priv(dev);
5967
5968 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
5969 return;
5970
5971 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
5972 RTL_W32(RxMissed, 0);
5973}
5974
1da177e4
LT		 5975static void rtl8169_down(struct net_device *dev)
5976{
5977 struct rtl8169_private *tp = netdev_priv(dev);
5978 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 5979
4876cc1e 5980 del_timer_sync(&tp->timer);
1da177e4 5981
93dd79e8 5982 napi_disable(&tp->napi);
da78dbff 5983 netif_stop_queue(dev);
1da177e4 5984
92fc43b4 5985 rtl8169_hw_reset(tp);
323bb685
SG		 5986 /*
5987 * At this point device interrupts can not be enabled in any function,
209e5ac8
FR		 5988 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
5989 * and napi is disabled (rtl8169_poll).
323bb685 5990 */
523a6094 5991 rtl8169_rx_missed(dev, ioaddr);
1da177e4 5992
1da177e4 5993 /* Give a racing hard_start_xmit a few cycles to complete. */
da78dbff 5994 synchronize_sched();
1da177e4 5995
1da177e4
LT		 5996 rtl8169_tx_clear(tp);
5997
5998 rtl8169_rx_clear(tp);
065c27c1 5999
6000 rtl_pll_power_down(tp);
1da177e4
LT		 6001}
6002
6003static int rtl8169_close(struct net_device *dev)
6004{
6005 struct rtl8169_private *tp = netdev_priv(dev);
6006 struct pci_dev *pdev = tp->pci_dev;
6007
e1759441
RW		 6008 pm_runtime_get_sync(&pdev->dev);
6009
cecb5fd7 6010 /* Update counters before going down */
355423d0
IV		 6011 rtl8169_update_counters(dev);
6012
da78dbff 6013 rtl_lock_work(tp);
6c4a70c5 6014 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
da78dbff 6015
1da177e4 6016 rtl8169_down(dev);
da78dbff 6017 rtl_unlock_work(tp);
1da177e4
LT		 6018
6019 free_irq(dev->irq, dev);
6020
82553bb6
SG		 6021 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6022 tp->RxPhyAddr);
6023 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6024 tp->TxPhyAddr);
1da177e4
LT		 6025 tp->TxDescArray = NULL;
6026 tp->RxDescArray = NULL;
6027
e1759441
RW		 6028 pm_runtime_put_sync(&pdev->dev);
6029
1da177e4
LT		 6030 return 0;
6031}
6032
07ce4064 6033static void rtl_set_rx_mode(struct net_device *dev)
1da177e4
LT		 6034{
6035 struct rtl8169_private *tp = netdev_priv(dev);
6036 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 6037 u32 mc_filter[2]; /* Multicast hash filter */
07d3f51f 6038 int rx_mode;
1da177e4
LT		 6039 u32 tmp = 0;
6040
6041 if (dev->flags & IFF_PROMISC) {
6042 /* Unconditionally log net taps. */
bf82c189 6043 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
1da177e4
LT		 6044 rx_mode =
6045 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
6046 AcceptAllPhys;
6047 mc_filter[1] = mc_filter[0] = 0xffffffff;
4cd24eaf 6048 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
8e95a202 6049 (dev->flags & IFF_ALLMULTI)) {
1da177e4
LT		 6050 /* Too many to filter perfectly -- accept all multicasts. */
6051 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
6052 mc_filter[1] = mc_filter[0] = 0xffffffff;
6053 } else {
22bedad3 6054 struct netdev_hw_addr *ha;
07d3f51f 6055
1da177e4
LT		 6056 rx_mode = AcceptBroadcast | AcceptMyPhys;
6057 mc_filter[1] = mc_filter[0] = 0;
22bedad3
JP		 6058 netdev_for_each_mc_addr(ha, dev) {
6059 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
1da177e4
LT		 6060 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
6061 rx_mode |= AcceptMulticast;
6062 }
6063 }
6064
6bbe021d
BG		 6065 if (dev->features & NETIF_F_RXALL)
6066 rx_mode |= (AcceptErr | AcceptRunt);
6067
1687b566 6068 tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
1da177e4 6069
f887cce8 6070 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
1087f4f4
FR		 6071 u32 data = mc_filter[0];
6072
6073 mc_filter[0] = swab32(mc_filter[1]);
6074 mc_filter[1] = swab32(data);
bcf0bf90
FR		 6075 }
6076
1da177e4 6077 RTL_W32(MAR0 + 4, mc_filter[1]);
78f1cd02 6078 RTL_W32(MAR0 + 0, mc_filter[0]);
1da177e4 6079
57a9f236 6080 RTL_W32(RxConfig, tmp);
1da177e4
LT		 6081}
6082
8027aa24
JW		 6083static struct rtnl_link_stats64 *
6084rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
1da177e4
LT		 6085{
6086 struct rtl8169_private *tp = netdev_priv(dev);
6087 void __iomem *ioaddr = tp->mmio_addr;
8027aa24 6088 unsigned int start;
1da177e4 6089
da78dbff 6090 if (netif_running(dev))
523a6094 6091 rtl8169_rx_missed(dev, ioaddr);
5b0384f4 6092
8027aa24
JW		 6093 do {
6094 start = u64_stats_fetch_begin_bh(&tp->rx_stats.syncp);
6095 stats->rx_packets = tp->rx_stats.packets;
6096 stats->rx_bytes = tp->rx_stats.bytes;
6097 } while (u64_stats_fetch_retry_bh(&tp->rx_stats.syncp, start));
6098
6099
6100 do {
6101 start = u64_stats_fetch_begin_bh(&tp->tx_stats.syncp);
6102 stats->tx_packets = tp->tx_stats.packets;
6103 stats->tx_bytes = tp->tx_stats.bytes;
6104 } while (u64_stats_fetch_retry_bh(&tp->tx_stats.syncp, start));
6105
6106 stats->rx_dropped = dev->stats.rx_dropped;
6107 stats->tx_dropped = dev->stats.tx_dropped;
6108 stats->rx_length_errors = dev->stats.rx_length_errors;
6109 stats->rx_errors = dev->stats.rx_errors;
6110 stats->rx_crc_errors = dev->stats.rx_crc_errors;
6111 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
6112 stats->rx_missed_errors = dev->stats.rx_missed_errors;
6113
6114 return stats;
1da177e4
LT		 6115}
6116
861ab440 6117static void rtl8169_net_suspend(struct net_device *dev)
5d06a99f 6118{
065c27c1 6119 struct rtl8169_private *tp = netdev_priv(dev);
6120
5d06a99f 6121 if (!netif_running(dev))
861ab440 6122 return;
5d06a99f
FR		 6123
6124 netif_device_detach(dev);
6125 netif_stop_queue(dev);
da78dbff
FR		 6126
6127 rtl_lock_work(tp);
6128 napi_disable(&tp->napi);
6c4a70c5 6129 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
da78dbff
FR		 6130 rtl_unlock_work(tp);
6131
6132 rtl_pll_power_down(tp);
861ab440
RW		 6133}
6134
6135#ifdef CONFIG_PM
6136
6137static int rtl8169_suspend(struct device *device)
6138{
6139 struct pci_dev *pdev = to_pci_dev(device);
6140 struct net_device *dev = pci_get_drvdata(pdev);
5d06a99f 6141
861ab440 6142 rtl8169_net_suspend(dev);
1371fa6d 6143
5d06a99f
FR		 6144 return 0;
6145}
6146
e1759441
RW		 6147static void __rtl8169_resume(struct net_device *dev)
6148{
065c27c1 6149 struct rtl8169_private *tp = netdev_priv(dev);
6150
e1759441 6151 netif_device_attach(dev);
065c27c1 6152
6153 rtl_pll_power_up(tp);
6154
6c4a70c5 6155 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
da78dbff 6156
98ddf986 6157 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
e1759441
RW		 6158}
6159
861ab440 6160static int rtl8169_resume(struct device *device)
5d06a99f 6161{
861ab440 6162 struct pci_dev *pdev = to_pci_dev(device);
5d06a99f 6163 struct net_device *dev = pci_get_drvdata(pdev);
fccec10b
SG		 6164 struct rtl8169_private *tp = netdev_priv(dev);
6165
6166 rtl8169_init_phy(dev, tp);
5d06a99f 6167
e1759441
RW		 6168 if (netif_running(dev))
6169 __rtl8169_resume(dev);
5d06a99f 6170
e1759441
RW		 6171 return 0;
6172}
6173
6174static int rtl8169_runtime_suspend(struct device *device)
6175{
6176 struct pci_dev *pdev = to_pci_dev(device);
6177 struct net_device *dev = pci_get_drvdata(pdev);
6178 struct rtl8169_private *tp = netdev_priv(dev);
6179
6180 if (!tp->TxDescArray)
6181 return 0;
6182
da78dbff 6183 rtl_lock_work(tp);
e1759441
RW		 6184 tp->saved_wolopts = __rtl8169_get_wol(tp);
6185 __rtl8169_set_wol(tp, WAKE_ANY);
da78dbff 6186 rtl_unlock_work(tp);
e1759441
RW		 6187
6188 rtl8169_net_suspend(dev);
6189
6190 return 0;
6191}
6192
6193static int rtl8169_runtime_resume(struct device *device)
6194{
6195 struct pci_dev *pdev = to_pci_dev(device);
6196 struct net_device *dev = pci_get_drvdata(pdev);
6197 struct rtl8169_private *tp = netdev_priv(dev);
6198
6199 if (!tp->TxDescArray)
6200 return 0;
6201
da78dbff 6202 rtl_lock_work(tp);
e1759441
RW		 6203 __rtl8169_set_wol(tp, tp->saved_wolopts);
6204 tp->saved_wolopts = 0;
da78dbff 6205 rtl_unlock_work(tp);
e1759441 6206
fccec10b
SG		 6207 rtl8169_init_phy(dev, tp);
6208
e1759441 6209 __rtl8169_resume(dev);
5d06a99f 6210
5d06a99f
FR		 6211 return 0;
6212}
6213
e1759441
RW		 6214static int rtl8169_runtime_idle(struct device *device)
6215{
6216 struct pci_dev *pdev = to_pci_dev(device);
6217 struct net_device *dev = pci_get_drvdata(pdev);
6218 struct rtl8169_private *tp = netdev_priv(dev);
6219
e4fbce74 6220 return tp->TxDescArray ? -EBUSY : 0;
e1759441
RW		 6221}
6222
47145210 6223static const struct dev_pm_ops rtl8169_pm_ops = {
cecb5fd7
FR		 6224 .suspend = rtl8169_suspend,
6225 .resume = rtl8169_resume,
6226 .freeze = rtl8169_suspend,
6227 .thaw = rtl8169_resume,
6228 .poweroff = rtl8169_suspend,
6229 .restore = rtl8169_resume,
6230 .runtime_suspend = rtl8169_runtime_suspend,
6231 .runtime_resume = rtl8169_runtime_resume,
6232 .runtime_idle = rtl8169_runtime_idle,
861ab440
RW		 6233};
6234
6235#define RTL8169_PM_OPS (&rtl8169_pm_ops)
6236
6237#else /* !CONFIG_PM */
6238
6239#define RTL8169_PM_OPS NULL
6240
6241#endif /* !CONFIG_PM */
6242
649b3b8c 6243static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
6244{
6245 void __iomem *ioaddr = tp->mmio_addr;
6246
6247 /* WoL fails with 8168b when the receiver is disabled. */
6248 switch (tp->mac_version) {
6249 case RTL_GIGA_MAC_VER_11:
6250 case RTL_GIGA_MAC_VER_12:
6251 case RTL_GIGA_MAC_VER_17:
6252 pci_clear_master(tp->pci_dev);
6253
6254 RTL_W8(ChipCmd, CmdRxEnb);
6255 /* PCI commit */
6256 RTL_R8(ChipCmd);
6257 break;
6258 default:
6259 break;
6260 }
6261}
6262
1765f95d
FR		 6263static void rtl_shutdown(struct pci_dev *pdev)
6264{
861ab440 6265 struct net_device *dev = pci_get_drvdata(pdev);
4bb3f522 6266 struct rtl8169_private *tp = netdev_priv(dev);
2a15cd2f 6267 struct device *d = &pdev->dev;
6268
6269 pm_runtime_get_sync(d);
861ab440
RW		 6270
6271 rtl8169_net_suspend(dev);
1765f95d 6272
cecb5fd7 6273 /* Restore original MAC address */
cc098dc7
IV		 6274 rtl_rar_set(tp, dev->perm_addr);
6275
92fc43b4 6276 rtl8169_hw_reset(tp);
4bb3f522 6277
861ab440 6278 if (system_state == SYSTEM_POWER_OFF) {
649b3b8c 6279 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
6280 rtl_wol_suspend_quirk(tp);
6281 rtl_wol_shutdown_quirk(tp);
ca52efd5 6282 }
6283
861ab440
RW		 6284 pci_wake_from_d3(pdev, true);
6285 pci_set_power_state(pdev, PCI_D3hot);
6286 }
2a15cd2f 6287
6288 pm_runtime_put_noidle(d);
861ab440 6289}
5d06a99f 6290
e27566ed
FR		 6291static void __devexit rtl_remove_one(struct pci_dev *pdev)
6292{
6293 struct net_device *dev = pci_get_drvdata(pdev);
6294 struct rtl8169_private *tp = netdev_priv(dev);
6295
6296 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
6297 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
6298 tp->mac_version == RTL_GIGA_MAC_VER_31) {
6299 rtl8168_driver_stop(tp);
6300 }
6301
6302 cancel_work_sync(&tp->wk.work);
6303
6304 unregister_netdev(dev);
6305
6306 rtl_release_firmware(tp);
6307
6308 if (pci_dev_run_wake(pdev))
6309 pm_runtime_get_noresume(&pdev->dev);
6310
6311 /* restore original MAC address */
6312 rtl_rar_set(tp, dev->perm_addr);
6313
6314 rtl_disable_msi(pdev, tp);
6315 rtl8169_release_board(pdev, dev, tp->mmio_addr);
6316 pci_set_drvdata(pdev, NULL);
6317}
6318
1da177e4
LT		 6319static struct pci_driver rtl8169_pci_driver = {
6320 .name = MODULENAME,
6321 .id_table = rtl8169_pci_tbl,
6322 .probe = rtl8169_init_one,
e27566ed 6323 .remove = __devexit_p(rtl_remove_one),
1765f95d 6324 .shutdown = rtl_shutdown,
861ab440 6325 .driver.pm = RTL8169_PM_OPS,
1da177e4
LT		 6326};
6327
07d3f51f 6328static int __init rtl8169_init_module(void)
1da177e4 6329{
29917620 6330 return pci_register_driver(&rtl8169_pci_driver);
1da177e4
LT		 6331}
6332
07d3f51f 6333static void __exit rtl8169_cleanup_module(void)
1da177e4
LT		 6334{
6335 pci_unregister_driver(&rtl8169_pci_driver);
6336}
6337
6338module_init(rtl8169_init_module);
6339module_exit(rtl8169_cleanup_module);
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