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hippi: fix printk format in rrunner.c
[mirror_ubuntu-zesty-kernel.git] / drivers / net / ethernet / realtek / r8169.c
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1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
18#include <linux/mii.h>
19#include <linux/if_vlan.h>
20#include <linux/crc32.h>
21#include <linux/in.h>
22#include <linux/ip.h>
23#include <linux/tcp.h>
24#include <linux/init.h>
a6b7a407 25#include <linux/interrupt.h>
1da177e4 26#include <linux/dma-mapping.h>
e1759441 27#include <linux/pm_runtime.h>
bca03d5f 28#include <linux/firmware.h>
ba04c7c9 29#include <linux/pci-aspm.h>
70c71606 30#include <linux/prefetch.h>
1da177e4
LT		 31
32#include <asm/io.h>
33#include <asm/irq.h>
34
865c652d 35#define RTL8169_VERSION "2.3LK-NAPI"
1da177e4
LT		 36#define MODULENAME "r8169"
37#define PFX MODULENAME ": "
38
bca03d5f 39#define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
40#define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
01dc7fec 41#define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
42#define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
70090424 43#define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
c2218925
HW		 44#define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
45#define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
5a5e4443 46#define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
bca03d5f 47
1da177e4
LT		 48#ifdef RTL8169_DEBUG
49#define assert(expr) \
5b0384f4
FR		 50 if (!(expr)) { \
51 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
b39d66a8 52 #expr,__FILE__,__func__,__LINE__); \
5b0384f4 53 }
06fa7358
JP		 54#define dprintk(fmt, args...) \
55 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
1da177e4
LT		 56#else
57#define assert(expr) do {} while (0)
58#define dprintk(fmt, args...) do {} while (0)
59#endif /* RTL8169_DEBUG */
60
b57b7e5a 61#define R8169_MSG_DEFAULT \
f0e837d9 62 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 63
1da177e4
LT		 64#define TX_BUFFS_AVAIL(tp) \
65 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
66
1da177e4
LT		 67/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
68 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 69static const int multicast_filter_limit = 32;
1da177e4 70
9c14ceaf 71#define MAX_READ_REQUEST_SHIFT 12
1da177e4 72#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
1da177e4
LT		 73#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
74#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
75
76#define R8169_REGS_SIZE 256
77#define R8169_NAPI_WEIGHT 64
78#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
79#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
80#define RX_BUF_SIZE 1536 /* Rx Buffer size */
81#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
82#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
83
84#define RTL8169_TX_TIMEOUT (6*HZ)
85#define RTL8169_PHY_TIMEOUT (10*HZ)
86
ea8dbdd1 87#define RTL_EEPROM_SIG cpu_to_le32(0x8129)
88#define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
e1564ec9
FR		 89#define RTL_EEPROM_SIG_ADDR 0x0000
90
1da177e4
LT		 91/* write/read MMIO register */
92#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
93#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
94#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
95#define RTL_R8(reg) readb (ioaddr + (reg))
96#define RTL_R16(reg) readw (ioaddr + (reg))
06f555f3 97#define RTL_R32(reg) readl (ioaddr + (reg))
1da177e4
LT		 98
99enum mac_version {
85bffe6c
FR		 100 RTL_GIGA_MAC_VER_01 = 0,
101 RTL_GIGA_MAC_VER_02,
102 RTL_GIGA_MAC_VER_03,
103 RTL_GIGA_MAC_VER_04,
104 RTL_GIGA_MAC_VER_05,
105 RTL_GIGA_MAC_VER_06,
106 RTL_GIGA_MAC_VER_07,
107 RTL_GIGA_MAC_VER_08,
108 RTL_GIGA_MAC_VER_09,
109 RTL_GIGA_MAC_VER_10,
110 RTL_GIGA_MAC_VER_11,
111 RTL_GIGA_MAC_VER_12,
112 RTL_GIGA_MAC_VER_13,
113 RTL_GIGA_MAC_VER_14,
114 RTL_GIGA_MAC_VER_15,
115 RTL_GIGA_MAC_VER_16,
116 RTL_GIGA_MAC_VER_17,
117 RTL_GIGA_MAC_VER_18,
118 RTL_GIGA_MAC_VER_19,
119 RTL_GIGA_MAC_VER_20,
120 RTL_GIGA_MAC_VER_21,
121 RTL_GIGA_MAC_VER_22,
122 RTL_GIGA_MAC_VER_23,
123 RTL_GIGA_MAC_VER_24,
124 RTL_GIGA_MAC_VER_25,
125 RTL_GIGA_MAC_VER_26,
126 RTL_GIGA_MAC_VER_27,
127 RTL_GIGA_MAC_VER_28,
128 RTL_GIGA_MAC_VER_29,
129 RTL_GIGA_MAC_VER_30,
130 RTL_GIGA_MAC_VER_31,
131 RTL_GIGA_MAC_VER_32,
132 RTL_GIGA_MAC_VER_33,
70090424 133 RTL_GIGA_MAC_VER_34,
c2218925
HW		 134 RTL_GIGA_MAC_VER_35,
135 RTL_GIGA_MAC_VER_36,
85bffe6c 136 RTL_GIGA_MAC_NONE = 0xff,
1da177e4
LT		 137};
138
2b7b4318
FR		 139enum rtl_tx_desc_version {
140 RTL_TD_0 = 0,
141 RTL_TD_1 = 1,
142};
143
d58d46b5
FR		 144#define JUMBO_1K ETH_DATA_LEN
145#define JUMBO_4K (4*1024 - ETH_HLEN - 2)
146#define JUMBO_6K (6*1024 - ETH_HLEN - 2)
147#define JUMBO_7K (7*1024 - ETH_HLEN - 2)
148#define JUMBO_9K (9*1024 - ETH_HLEN - 2)
149
150#define _R(NAME,TD,FW,SZ,B) { \
151 .name = NAME, \
152 .txd_version = TD, \
153 .fw_name = FW, \
154 .jumbo_max = SZ, \
155 .jumbo_tx_csum = B \
156}
1da177e4 157
3c6bee1d 158static const struct {
1da177e4 159 const char *name;
2b7b4318 160 enum rtl_tx_desc_version txd_version;
953a12cc 161 const char *fw_name;
d58d46b5
FR		 162 u16 jumbo_max;
163 bool jumbo_tx_csum;
85bffe6c
FR		 164} rtl_chip_infos[] = {
165 /* PCI devices. */
166 [RTL_GIGA_MAC_VER_01] =
d58d46b5 167 _R("RTL8169", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 168 [RTL_GIGA_MAC_VER_02] =
d58d46b5 169 _R("RTL8169s", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 170 [RTL_GIGA_MAC_VER_03] =
d58d46b5 171 _R("RTL8110s", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 172 [RTL_GIGA_MAC_VER_04] =
d58d46b5 173 _R("RTL8169sb/8110sb", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 174 [RTL_GIGA_MAC_VER_05] =
d58d46b5 175 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 176 [RTL_GIGA_MAC_VER_06] =
d58d46b5 177 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c
FR		 178 /* PCI-E devices. */
179 [RTL_GIGA_MAC_VER_07] =
d58d46b5 180 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
85bffe6c 181 [RTL_GIGA_MAC_VER_08] =
d58d46b5 182 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
85bffe6c 183 [RTL_GIGA_MAC_VER_09] =
d58d46b5 184 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
85bffe6c 185 [RTL_GIGA_MAC_VER_10] =
d58d46b5 186 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 187 [RTL_GIGA_MAC_VER_11] =
d58d46b5 188 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
85bffe6c 189 [RTL_GIGA_MAC_VER_12] =
d58d46b5 190 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
85bffe6c 191 [RTL_GIGA_MAC_VER_13] =
d58d46b5 192 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 193 [RTL_GIGA_MAC_VER_14] =
d58d46b5 194 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 195 [RTL_GIGA_MAC_VER_15] =
d58d46b5 196 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 197 [RTL_GIGA_MAC_VER_16] =
d58d46b5 198 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 199 [RTL_GIGA_MAC_VER_17] =
d58d46b5 200 _R("RTL8168b/8111b", RTL_TD_1, NULL, JUMBO_4K, false),
85bffe6c 201 [RTL_GIGA_MAC_VER_18] =
d58d46b5 202 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 203 [RTL_GIGA_MAC_VER_19] =
d58d46b5 204 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 205 [RTL_GIGA_MAC_VER_20] =
d58d46b5 206 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 207 [RTL_GIGA_MAC_VER_21] =
d58d46b5 208 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 209 [RTL_GIGA_MAC_VER_22] =
d58d46b5 210 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 211 [RTL_GIGA_MAC_VER_23] =
d58d46b5 212 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 213 [RTL_GIGA_MAC_VER_24] =
d58d46b5 214 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 215 [RTL_GIGA_MAC_VER_25] =
d58d46b5
FR		 216 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1,
217 JUMBO_9K, false),
85bffe6c 218 [RTL_GIGA_MAC_VER_26] =
d58d46b5
FR		 219 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2,
220 JUMBO_9K, false),
85bffe6c 221 [RTL_GIGA_MAC_VER_27] =
d58d46b5 222 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
85bffe6c 223 [RTL_GIGA_MAC_VER_28] =
d58d46b5 224 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
85bffe6c 225 [RTL_GIGA_MAC_VER_29] =
d58d46b5
FR		 226 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
227 JUMBO_1K, true),
85bffe6c 228 [RTL_GIGA_MAC_VER_30] =
d58d46b5
FR		 229 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
230 JUMBO_1K, true),
85bffe6c 231 [RTL_GIGA_MAC_VER_31] =
d58d46b5 232 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
85bffe6c 233 [RTL_GIGA_MAC_VER_32] =
d58d46b5
FR		 234 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1,
235 JUMBO_9K, false),
85bffe6c 236 [RTL_GIGA_MAC_VER_33] =
d58d46b5
FR		 237 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2,
238 JUMBO_9K, false),
70090424 239 [RTL_GIGA_MAC_VER_34] =
d58d46b5
FR		 240 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
241 JUMBO_9K, false),
c2218925 242 [RTL_GIGA_MAC_VER_35] =
d58d46b5
FR		 243 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_1,
244 JUMBO_9K, false),
c2218925 245 [RTL_GIGA_MAC_VER_36] =
d58d46b5
FR		 246 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_2,
247 JUMBO_9K, false),
953a12cc 248};
85bffe6c 249#undef _R
953a12cc 250
bcf0bf90
FR		 251enum cfg_version {
252 RTL_CFG_0 = 0x00,
253 RTL_CFG_1,
254 RTL_CFG_2
255};
256
a3aa1884 257static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
bcf0bf90 258 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 259 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
d81bf551 260 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 261 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90
FR		 262 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
263 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
93a3aa25 264 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 },
bc1660b5 265 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 266 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
267 { PCI_VENDOR_ID_LINKSYS, 0x1032,
268 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
11d2e282
CM		 269 { 0x0001, 0x8168,
270 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
1da177e4
LT		 271 {0,},
272};
273
274MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
275
6f0333b8 276static int rx_buf_sz = 16383;
4300e8c7 277static int use_dac;
b57b7e5a
SH		 278static struct {
279 u32 msg_enable;
280} debug = { -1 };
1da177e4 281
07d3f51f
FR		 282enum rtl_registers {
283 MAC0 = 0, /* Ethernet hardware address. */
773d2021 284 MAC4 = 4,
07d3f51f
FR		 285 MAR0 = 8, /* Multicast filter. */
286 CounterAddrLow = 0x10,
287 CounterAddrHigh = 0x14,
288 TxDescStartAddrLow = 0x20,
289 TxDescStartAddrHigh = 0x24,
290 TxHDescStartAddrLow = 0x28,
291 TxHDescStartAddrHigh = 0x2c,
292 FLASH = 0x30,
293 ERSR = 0x36,
294 ChipCmd = 0x37,
295 TxPoll = 0x38,
296 IntrMask = 0x3c,
297 IntrStatus = 0x3e,
4f6b00e5 298
07d3f51f 299 TxConfig = 0x40,
4f6b00e5
HW		 300#define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
301#define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
2b7b4318 302
4f6b00e5
HW		 303 RxConfig = 0x44,
304#define RX128_INT_EN (1 << 15) /* 8111c and later */
305#define RX_MULTI_EN (1 << 14) /* 8111c only */
306#define RXCFG_FIFO_SHIFT 13
307 /* No threshold before first PCI xfer */
308#define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
309#define RXCFG_DMA_SHIFT 8
310 /* Unlimited maximum PCI burst. */
311#define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
2b7b4318 312
07d3f51f
FR		 313 RxMissed = 0x4c,
314 Cfg9346 = 0x50,
315 Config0 = 0x51,
316 Config1 = 0x52,
317 Config2 = 0x53,
318 Config3 = 0x54,
319 Config4 = 0x55,
320 Config5 = 0x56,
321 MultiIntr = 0x5c,
322 PHYAR = 0x60,
07d3f51f
FR		 323 PHYstatus = 0x6c,
324 RxMaxSize = 0xda,
325 CPlusCmd = 0xe0,
326 IntrMitigate = 0xe2,
327 RxDescAddrLow = 0xe4,
328 RxDescAddrHigh = 0xe8,
f0298f81 329 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
330
331#define NoEarlyTx 0x3f /* Max value : no early transmit. */
332
333 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
334
335#define TxPacketMax (8064 >> 7)
3090bd9a 336#define EarlySize 0x27
f0298f81 337
07d3f51f
FR		 338 FuncEvent = 0xf0,
339 FuncEventMask = 0xf4,
340 FuncPresetState = 0xf8,
341 FuncForceEvent = 0xfc,
1da177e4
LT		 342};
343
f162a5d1
FR		 344enum rtl8110_registers {
345 TBICSR = 0x64,
346 TBI_ANAR = 0x68,
347 TBI_LPAR = 0x6a,
348};
349
350enum rtl8168_8101_registers {
351 CSIDR = 0x64,
352 CSIAR = 0x68,
353#define CSIAR_FLAG 0x80000000
354#define CSIAR_WRITE_CMD 0x80000000
355#define CSIAR_BYTE_ENABLE 0x0f
356#define CSIAR_BYTE_ENABLE_SHIFT 12
357#define CSIAR_ADDR_MASK 0x0fff
065c27c1 358 PMCH = 0x6f,
f162a5d1
FR		 359 EPHYAR = 0x80,
360#define EPHYAR_FLAG 0x80000000
361#define EPHYAR_WRITE_CMD 0x80000000
362#define EPHYAR_REG_MASK 0x1f
363#define EPHYAR_REG_SHIFT 16
364#define EPHYAR_DATA_MASK 0xffff
5a5e4443 365 DLLPR = 0xd0,
4f6b00e5 366#define PFM_EN (1 << 6)
f162a5d1
FR		 367 DBG_REG = 0xd1,
368#define FIX_NAK_1 (1 << 4)
369#define FIX_NAK_2 (1 << 3)
5a5e4443
HW		 370 TWSI = 0xd2,
371 MCU = 0xd3,
4f6b00e5 372#define NOW_IS_OOB (1 << 7)
5a5e4443
HW		 373#define EN_NDP (1 << 3)
374#define EN_OOB_RESET (1 << 2)
daf9df6d 375 EFUSEAR = 0xdc,
376#define EFUSEAR_FLAG 0x80000000
377#define EFUSEAR_WRITE_CMD 0x80000000
378#define EFUSEAR_READ_CMD 0x00000000
379#define EFUSEAR_REG_MASK 0x03ff
380#define EFUSEAR_REG_SHIFT 8
381#define EFUSEAR_DATA_MASK 0xff
f162a5d1
FR		 382};
383
c0e45c1c 384enum rtl8168_registers {
4f6b00e5
HW		 385 LED_FREQ = 0x1a,
386 EEE_LED = 0x1b,
b646d900 387 ERIDR = 0x70,
388 ERIAR = 0x74,
389#define ERIAR_FLAG 0x80000000
390#define ERIAR_WRITE_CMD 0x80000000
391#define ERIAR_READ_CMD 0x00000000
392#define ERIAR_ADDR_BYTE_ALIGN 4
b646d900 393#define ERIAR_TYPE_SHIFT 16
4f6b00e5
HW		 394#define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
395#define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
396#define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
397#define ERIAR_MASK_SHIFT 12
398#define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
399#define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
400#define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
c0e45c1c 401 EPHY_RXER_NUM = 0x7c,
402 OCPDR = 0xb0, /* OCP GPHY access */
403#define OCPDR_WRITE_CMD 0x80000000
404#define OCPDR_READ_CMD 0x00000000
405#define OCPDR_REG_MASK 0x7f
406#define OCPDR_GPHY_REG_SHIFT 16
407#define OCPDR_DATA_MASK 0xffff
408 OCPAR = 0xb4,
409#define OCPAR_FLAG 0x80000000
410#define OCPAR_GPHY_WRITE_CMD 0x8000f060
411#define OCPAR_GPHY_READ_CMD 0x0000f060
01dc7fec 412 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
413 MISC = 0xf0, /* 8168e only. */
cecb5fd7 414#define TXPLA_RST (1 << 29)
4f6b00e5 415#define PWM_EN (1 << 22)
c0e45c1c 416};
417
07d3f51f 418enum rtl_register_content {
1da177e4 419 /* InterruptStatusBits */
07d3f51f
FR		 420 SYSErr = 0x8000,
421 PCSTimeout = 0x4000,
422 SWInt = 0x0100,
423 TxDescUnavail = 0x0080,
424 RxFIFOOver = 0x0040,
425 LinkChg = 0x0020,
426 RxOverflow = 0x0010,
427 TxErr = 0x0008,
428 TxOK = 0x0004,
429 RxErr = 0x0002,
430 RxOK = 0x0001,
1da177e4
LT		 431
432 /* RxStatusDesc */
e03f33af 433 RxBOVF = (1 << 24),
9dccf611
FR		 434 RxFOVF = (1 << 23),
435 RxRWT = (1 << 22),
436 RxRES = (1 << 21),
437 RxRUNT = (1 << 20),
438 RxCRC = (1 << 19),
1da177e4
LT		 439
440 /* ChipCmdBits */
4f6b00e5 441 StopReq = 0x80,
07d3f51f
FR		 442 CmdReset = 0x10,
443 CmdRxEnb = 0x08,
444 CmdTxEnb = 0x04,
445 RxBufEmpty = 0x01,
1da177e4 446
275391a4
FR		 447 /* TXPoll register p.5 */
448 HPQ = 0x80, /* Poll cmd on the high prio queue */
449 NPQ = 0x40, /* Poll cmd on the low prio queue */
450 FSWInt = 0x01, /* Forced software interrupt */
451
1da177e4 452 /* Cfg9346Bits */
07d3f51f
FR		 453 Cfg9346_Lock = 0x00,
454 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 455
456 /* rx_mode_bits */
07d3f51f
FR		 457 AcceptErr = 0x20,
458 AcceptRunt = 0x10,
459 AcceptBroadcast = 0x08,
460 AcceptMulticast = 0x04,
461 AcceptMyPhys = 0x02,
462 AcceptAllPhys = 0x01,
1687b566 463#define RX_CONFIG_ACCEPT_MASK 0x3f
1da177e4 464
1da177e4
LT		 465 /* TxConfigBits */
466 TxInterFrameGapShift = 24,
467 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
468
5d06a99f 469 /* Config1 register p.24 */
f162a5d1
FR		 470 LEDS1 = (1 << 7),
471 LEDS0 = (1 << 6),
f162a5d1
FR		 472 Speed_down = (1 << 4),
473 MEMMAP = (1 << 3),
474 IOMAP = (1 << 2),
475 VPD = (1 << 1),
5d06a99f
FR		 476 PMEnable = (1 << 0), /* Power Management Enable */
477
6dccd16b 478 /* Config2 register p. 25 */
2ca6cf06 479 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
6dccd16b
FR		 480 PCI_Clock_66MHz = 0x01,
481 PCI_Clock_33MHz = 0x00,
482
61a4dcc2
FR		 483 /* Config3 register p.25 */
484 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
485 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
d58d46b5 486 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
f162a5d1 487 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
61a4dcc2 488
d58d46b5
FR		 489 /* Config4 register */
490 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
491
5d06a99f 492 /* Config5 register p.27 */
61a4dcc2
FR		 493 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
494 MWF = (1 << 5), /* Accept Multicast wakeup frame */
495 UWF = (1 << 4), /* Accept Unicast wakeup frame */
cecb5fd7 496 Spi_en = (1 << 3),
61a4dcc2 497 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f
FR		 498 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
499
1da177e4
LT		 500 /* TBICSR p.28 */
501 TBIReset = 0x80000000,
502 TBILoopback = 0x40000000,
503 TBINwEnable = 0x20000000,
504 TBINwRestart = 0x10000000,
505 TBILinkOk = 0x02000000,
506 TBINwComplete = 0x01000000,
507
508 /* CPlusCmd p.31 */
f162a5d1
FR		 509 EnableBist = (1 << 15), // 8168 8101
510 Mac_dbgo_oe = (1 << 14), // 8168 8101
511 Normal_mode = (1 << 13), // unused
512 Force_half_dup = (1 << 12), // 8168 8101
513 Force_rxflow_en = (1 << 11), // 8168 8101
514 Force_txflow_en = (1 << 10), // 8168 8101
515 Cxpl_dbg_sel = (1 << 9), // 8168 8101
516 ASF = (1 << 8), // 8168 8101
517 PktCntrDisable = (1 << 7), // 8168 8101
518 Mac_dbgo_sel = 0x001c, // 8168
1da177e4
LT		 519 RxVlan = (1 << 6),
520 RxChkSum = (1 << 5),
521 PCIDAC = (1 << 4),
522 PCIMulRW = (1 << 3),
0e485150
FR		 523 INTT_0 = 0x0000, // 8168
524 INTT_1 = 0x0001, // 8168
525 INTT_2 = 0x0002, // 8168
526 INTT_3 = 0x0003, // 8168
1da177e4
LT		 527
528 /* rtl8169_PHYstatus */
07d3f51f
FR		 529 TBI_Enable = 0x80,
530 TxFlowCtrl = 0x40,
531 RxFlowCtrl = 0x20,
532 _1000bpsF = 0x10,
533 _100bps = 0x08,
534 _10bps = 0x04,
535 LinkStatus = 0x02,
536 FullDup = 0x01,
1da177e4 537
1da177e4 538 /* _TBICSRBit */
07d3f51f 539 TBILinkOK = 0x02000000,
d4a3a0fc
SH		 540
541 /* DumpCounterCommand */
07d3f51f 542 CounterDump = 0x8,
1da177e4
LT		 543};
544
2b7b4318
FR		 545enum rtl_desc_bit {
546 /* First doubleword. */
1da177e4
LT		 547 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
548 RingEnd = (1 << 30), /* End of descriptor ring */
549 FirstFrag = (1 << 29), /* First segment of a packet */
550 LastFrag = (1 << 28), /* Final segment of a packet */
2b7b4318
FR		 551};
552
553/* Generic case. */
554enum rtl_tx_desc_bit {
555 /* First doubleword. */
556 TD_LSO = (1 << 27), /* Large Send Offload */
557#define TD_MSS_MAX 0x07ffu /* MSS value */
1da177e4 558
2b7b4318
FR		 559 /* Second doubleword. */
560 TxVlanTag = (1 << 17), /* Add VLAN tag */
561};
562
563/* 8169, 8168b and 810x except 8102e. */
564enum rtl_tx_desc_bit_0 {
565 /* First doubleword. */
566#define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
567 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
568 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
569 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
570};
571
572/* 8102e, 8168c and beyond. */
573enum rtl_tx_desc_bit_1 {
574 /* Second doubleword. */
575#define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
576 TD1_IP_CS = (1 << 29), /* Calculate IP checksum */
577 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
578 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
579};
1da177e4 580
2b7b4318
FR		 581static const struct rtl_tx_desc_info {
582 struct {
583 u32 udp;
584 u32 tcp;
585 } checksum;
586 u16 mss_shift;
587 u16 opts_offset;
588} tx_desc_info [] = {
589 [RTL_TD_0] = {
590 .checksum = {
591 .udp = TD0_IP_CS | TD0_UDP_CS,
592 .tcp = TD0_IP_CS | TD0_TCP_CS
593 },
594 .mss_shift = TD0_MSS_SHIFT,
595 .opts_offset = 0
596 },
597 [RTL_TD_1] = {
598 .checksum = {
599 .udp = TD1_IP_CS | TD1_UDP_CS,
600 .tcp = TD1_IP_CS | TD1_TCP_CS
601 },
602 .mss_shift = TD1_MSS_SHIFT,
603 .opts_offset = 1
604 }
605};
606
607enum rtl_rx_desc_bit {
1da177e4
LT		 608 /* Rx private */
609 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
610 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
611
612#define RxProtoUDP (PID1)
613#define RxProtoTCP (PID0)
614#define RxProtoIP (PID1 | PID0)
615#define RxProtoMask RxProtoIP
616
617 IPFail = (1 << 16), /* IP checksum failed */
618 UDPFail = (1 << 15), /* UDP/IP checksum failed */
619 TCPFail = (1 << 14), /* TCP/IP checksum failed */
620 RxVlanTag = (1 << 16), /* VLAN tag available */
621};
622
623#define RsvdMask 0x3fffc000
624
625struct TxDesc {
6cccd6e7
REB		 626 __le32 opts1;
627 __le32 opts2;
628 __le64 addr;
1da177e4
LT		 629};
630
631struct RxDesc {
6cccd6e7
REB		 632 __le32 opts1;
633 __le32 opts2;
634 __le64 addr;
1da177e4
LT		 635};
636
637struct ring_info {
638 struct sk_buff *skb;
639 u32 len;
640 u8 __pad[sizeof(void *) - sizeof(u32)];
641};
642
f23e7fda 643enum features {
ccdffb9a
FR		 644 RTL_FEATURE_WOL = (1 << 0),
645 RTL_FEATURE_MSI = (1 << 1),
646 RTL_FEATURE_GMII = (1 << 2),
f23e7fda
FR		 647};
648
355423d0
IV		 649struct rtl8169_counters {
650 __le64 tx_packets;
651 __le64 rx_packets;
652 __le64 tx_errors;
653 __le32 rx_errors;
654 __le16 rx_missed;
655 __le16 align_errors;
656 __le32 tx_one_collision;
657 __le32 tx_multi_collision;
658 __le64 rx_unicast;
659 __le64 rx_broadcast;
660 __le32 rx_multicast;
661 __le16 tx_aborted;
662 __le16 tx_underun;
663};
664
da78dbff 665enum rtl_flag {
6c4a70c5 666 RTL_FLAG_TASK_ENABLED,
da78dbff
FR		 667 RTL_FLAG_TASK_SLOW_PENDING,
668 RTL_FLAG_TASK_RESET_PENDING,
669 RTL_FLAG_TASK_PHY_PENDING,
670 RTL_FLAG_MAX
671};
672
8027aa24
JW		 673struct rtl8169_stats {
674 u64 packets;
675 u64 bytes;
676 struct u64_stats_sync syncp;
677};
678
1da177e4
LT		 679struct rtl8169_private {
680 void __iomem *mmio_addr; /* memory map physical address */
cecb5fd7 681 struct pci_dev *pci_dev;
c4028958 682 struct net_device *dev;
bea3348e 683 struct napi_struct napi;
b57b7e5a 684 u32 msg_enable;
2b7b4318
FR		 685 u16 txd_version;
686 u16 mac_version;
1da177e4
LT		 687 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
688 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
689 u32 dirty_rx;
690 u32 dirty_tx;
8027aa24
JW		 691 struct rtl8169_stats rx_stats;
692 struct rtl8169_stats tx_stats;
1da177e4
LT		 693 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
694 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
695 dma_addr_t TxPhyAddr;
696 dma_addr_t RxPhyAddr;
6f0333b8 697 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
1da177e4 698 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
1da177e4
LT		 699 struct timer_list timer;
700 u16 cp_cmd;
da78dbff
FR		 701
702 u16 event_slow;
c0e45c1c 703
704 struct mdio_ops {
705 void (*write)(void __iomem *, int, int);
706 int (*read)(void __iomem *, int);
707 } mdio_ops;
708
065c27c1 709 struct pll_power_ops {
710 void (*down)(struct rtl8169_private *);
711 void (*up)(struct rtl8169_private *);
712 } pll_power_ops;
713
d58d46b5
FR		 714 struct jumbo_ops {
715 void (*enable)(struct rtl8169_private *);
716 void (*disable)(struct rtl8169_private *);
717 } jumbo_ops;
718
54405cde 719 int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
ccdffb9a 720 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
4da19633 721 void (*phy_reset_enable)(struct rtl8169_private *tp);
07ce4064 722 void (*hw_start)(struct net_device *);
4da19633 723 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
1da177e4 724 unsigned int (*link_ok)(void __iomem *);
8b4ab28d 725 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
4422bcd4
FR		 726
727 struct {
da78dbff
FR		 728 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
729 struct mutex mutex;
4422bcd4
FR		 730 struct work_struct work;
731 } wk;
732
f23e7fda 733 unsigned features;
ccdffb9a
FR		 734
735 struct mii_if_info mii;
355423d0 736 struct rtl8169_counters counters;
e1759441 737 u32 saved_wolopts;
e03f33af 738 u32 opts1_mask;
f1e02ed1 739
b6ffd97f
FR		 740 struct rtl_fw {
741 const struct firmware *fw;
1c361efb
FR		 742
743#define RTL_VER_SIZE 32
744
745 char version[RTL_VER_SIZE];
746
747 struct rtl_fw_phy_action {
748 __le32 *code;
749 size_t size;
750 } phy_action;
b6ffd97f 751 } *rtl_fw;
497888cf 752#define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
1da177e4
LT		 753};
754
979b6c13 755MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 756MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 757module_param(use_dac, int, 0);
4300e8c7 758MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 759module_param_named(debug, debug.msg_enable, int, 0);
760MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 761MODULE_LICENSE("GPL");
762MODULE_VERSION(RTL8169_VERSION);
bca03d5f 763MODULE_FIRMWARE(FIRMWARE_8168D_1);
764MODULE_FIRMWARE(FIRMWARE_8168D_2);
01dc7fec 765MODULE_FIRMWARE(FIRMWARE_8168E_1);
766MODULE_FIRMWARE(FIRMWARE_8168E_2);
bbb8af75 767MODULE_FIRMWARE(FIRMWARE_8168E_3);
5a5e4443 768MODULE_FIRMWARE(FIRMWARE_8105E_1);
c2218925
HW		 769MODULE_FIRMWARE(FIRMWARE_8168F_1);
770MODULE_FIRMWARE(FIRMWARE_8168F_2);
1da177e4 771
da78dbff
FR		 772static void rtl_lock_work(struct rtl8169_private *tp)
773{
774 mutex_lock(&tp->wk.mutex);
775}
776
777static void rtl_unlock_work(struct rtl8169_private *tp)
778{
779 mutex_unlock(&tp->wk.mutex);
780}
781
d58d46b5
FR		 782static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
783{
784 int cap = pci_pcie_cap(pdev);
785
786 if (cap) {
787 u16 ctl;
788
789 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
790 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
791 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
792 }
793}
794
b646d900 795static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
796{
797 void __iomem *ioaddr = tp->mmio_addr;
798 int i;
799
800 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
801 for (i = 0; i < 20; i++) {
802 udelay(100);
803 if (RTL_R32(OCPAR) & OCPAR_FLAG)
804 break;
805 }
806 return RTL_R32(OCPDR);
807}
808
809static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
810{
811 void __iomem *ioaddr = tp->mmio_addr;
812 int i;
813
814 RTL_W32(OCPDR, data);
815 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
816 for (i = 0; i < 20; i++) {
817 udelay(100);
818 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
819 break;
820 }
821}
822
fac5b3ca 823static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
b646d900 824{
fac5b3ca 825 void __iomem *ioaddr = tp->mmio_addr;
b646d900 826 int i;
827
828 RTL_W8(ERIDR, cmd);
829 RTL_W32(ERIAR, 0x800010e8);
830 msleep(2);
831 for (i = 0; i < 5; i++) {
832 udelay(100);
1e4e82ba 833 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
b646d900 834 break;
835 }
836
fac5b3ca 837 ocp_write(tp, 0x1, 0x30, 0x00000001);
b646d900 838}
839
840#define OOB_CMD_RESET 0x00
841#define OOB_CMD_DRIVER_START 0x05
842#define OOB_CMD_DRIVER_STOP 0x06
843
cecb5fd7
FR		 844static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
845{
846 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
847}
848
b646d900 849static void rtl8168_driver_start(struct rtl8169_private *tp)
850{
cecb5fd7 851 u16 reg;
b646d900 852 int i;
853
854 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
855
cecb5fd7 856 reg = rtl8168_get_ocp_reg(tp);
4804b3b3 857
b646d900 858 for (i = 0; i < 10; i++) {
859 msleep(10);
4804b3b3 860 if (ocp_read(tp, 0x0f, reg) & 0x00000800)
b646d900 861 break;
862 }
863}
864
865static void rtl8168_driver_stop(struct rtl8169_private *tp)
866{
cecb5fd7 867 u16 reg;
b646d900 868 int i;
869
870 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
871
cecb5fd7 872 reg = rtl8168_get_ocp_reg(tp);
4804b3b3 873
b646d900 874 for (i = 0; i < 10; i++) {
875 msleep(10);
4804b3b3 876 if ((ocp_read(tp, 0x0f, reg) & 0x00000800) == 0)
b646d900 877 break;
878 }
879}
880
4804b3b3 881static int r8168dp_check_dash(struct rtl8169_private *tp)
882{
cecb5fd7 883 u16 reg = rtl8168_get_ocp_reg(tp);
4804b3b3 884
cecb5fd7 885 return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
4804b3b3 886}
b646d900 887
4da19633 888static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
1da177e4
LT		 889{
890 int i;
891
a6baf3af 892 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
1da177e4 893
2371408c 894 for (i = 20; i > 0; i--) {
07d3f51f
FR		 895 /*
896 * Check if the RTL8169 has completed writing to the specified
897 * MII register.
898 */
5b0384f4 899 if (!(RTL_R32(PHYAR) & 0x80000000))
1da177e4 900 break;
2371408c 901 udelay(25);
1da177e4 902 }
024a07ba 903 /*
81a95f04
TT		 904 * According to hardware specs a 20us delay is required after write
905 * complete indication, but before sending next command.
024a07ba 906 */
81a95f04 907 udelay(20);
1da177e4
LT		 908}
909
4da19633 910static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
1da177e4
LT		 911{
912 int i, value = -1;
913
a6baf3af 914 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
1da177e4 915
2371408c 916 for (i = 20; i > 0; i--) {
07d3f51f
FR		 917 /*
918 * Check if the RTL8169 has completed retrieving data from
919 * the specified MII register.
920 */
1da177e4 921 if (RTL_R32(PHYAR) & 0x80000000) {
a6baf3af 922 value = RTL_R32(PHYAR) & 0xffff;
1da177e4
LT		 923 break;
924 }
2371408c 925 udelay(25);
1da177e4 926 }
81a95f04
TT		 927 /*
928 * According to hardware specs a 20us delay is required after read
929 * complete indication, but before sending next command.
930 */
931 udelay(20);
932
1da177e4
LT		 933 return value;
934}
935
c0e45c1c 936static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
937{
938 int i;
939
940 RTL_W32(OCPDR, data |
941 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
942 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
943 RTL_W32(EPHY_RXER_NUM, 0);
944
945 for (i = 0; i < 100; i++) {
946 mdelay(1);
947 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
948 break;
949 }
950}
951
952static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
953{
954 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
955 (value & OCPDR_DATA_MASK));
956}
957
958static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
959{
960 int i;
961
962 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
963
964 mdelay(1);
965 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
966 RTL_W32(EPHY_RXER_NUM, 0);
967
968 for (i = 0; i < 100; i++) {
969 mdelay(1);
970 if (RTL_R32(OCPAR) & OCPAR_FLAG)
971 break;
972 }
973
974 return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
975}
976
e6de30d6 977#define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
978
979static void r8168dp_2_mdio_start(void __iomem *ioaddr)
980{
981 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
982}
983
984static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
985{
986 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
987}
988
989static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
990{
991 r8168dp_2_mdio_start(ioaddr);
992
993 r8169_mdio_write(ioaddr, reg_addr, value);
994
995 r8168dp_2_mdio_stop(ioaddr);
996}
997
998static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
999{
1000 int value;
1001
1002 r8168dp_2_mdio_start(ioaddr);
1003
1004 value = r8169_mdio_read(ioaddr, reg_addr);
1005
1006 r8168dp_2_mdio_stop(ioaddr);
1007
1008 return value;
1009}
1010
4da19633 1011static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
dacf8154 1012{
c0e45c1c 1013 tp->mdio_ops.write(tp->mmio_addr, location, val);
dacf8154
FR		 1014}
1015
4da19633 1016static int rtl_readphy(struct rtl8169_private *tp, int location)
1017{
c0e45c1c 1018 return tp->mdio_ops.read(tp->mmio_addr, location);
4da19633 1019}
1020
1021static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1022{
1023 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1024}
1025
1026static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
daf9df6d 1027{
1028 int val;
1029
4da19633 1030 val = rtl_readphy(tp, reg_addr);
1031 rtl_writephy(tp, reg_addr, (val | p) & ~m);
daf9df6d 1032}
1033
ccdffb9a
FR		 1034static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1035 int val)
1036{
1037 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 1038
4da19633 1039 rtl_writephy(tp, location, val);
ccdffb9a
FR		 1040}
1041
1042static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1043{
1044 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 1045
4da19633 1046 return rtl_readphy(tp, location);
ccdffb9a
FR		 1047}
1048
dacf8154
FR		 1049static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
1050{
1051 unsigned int i;
1052
1053 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1054 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1055
1056 for (i = 0; i < 100; i++) {
1057 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
1058 break;
1059 udelay(10);
1060 }
1061}
1062
1063static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
1064{
1065 u16 value = 0xffff;
1066 unsigned int i;
1067
1068 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1069
1070 for (i = 0; i < 100; i++) {
1071 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
1072 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
1073 break;
1074 }
1075 udelay(10);
1076 }
1077
1078 return value;
1079}
1080
1081static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
1082{
1083 unsigned int i;
1084
1085 RTL_W32(CSIDR, value);
1086 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
1087 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1088
1089 for (i = 0; i < 100; i++) {
1090 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
1091 break;
1092 udelay(10);
1093 }
1094}
1095
1096static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
1097{
1098 u32 value = ~0x00;
1099 unsigned int i;
1100
1101 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
1102 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1103
1104 for (i = 0; i < 100; i++) {
1105 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
1106 value = RTL_R32(CSIDR);
1107 break;
1108 }
1109 udelay(10);
1110 }
1111
1112 return value;
1113}
1114
133ac40a
HW		 1115static
1116void rtl_eri_write(void __iomem *ioaddr, int addr, u32 mask, u32 val, int type)
1117{
1118 unsigned int i;
1119
1120 BUG_ON((addr & 3) || (mask == 0));
1121 RTL_W32(ERIDR, val);
1122 RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1123
1124 for (i = 0; i < 100; i++) {
1125 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
1126 break;
1127 udelay(100);
1128 }
1129}
1130
1131static u32 rtl_eri_read(void __iomem *ioaddr, int addr, int type)
1132{
1133 u32 value = ~0x00;
1134 unsigned int i;
1135
1136 RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1137
1138 for (i = 0; i < 100; i++) {
1139 if (RTL_R32(ERIAR) & ERIAR_FLAG) {
1140 value = RTL_R32(ERIDR);
1141 break;
1142 }
1143 udelay(100);
1144 }
1145
1146 return value;
1147}
1148
1149static void
1150rtl_w1w0_eri(void __iomem *ioaddr, int addr, u32 mask, u32 p, u32 m, int type)
1151{
1152 u32 val;
1153
1154 val = rtl_eri_read(ioaddr, addr, type);
1155 rtl_eri_write(ioaddr, addr, mask, (val & ~m) | p, type);
1156}
1157
c28aa385 1158struct exgmac_reg {
1159 u16 addr;
1160 u16 mask;
1161 u32 val;
1162};
1163
1164static void rtl_write_exgmac_batch(void __iomem *ioaddr,
1165 const struct exgmac_reg *r, int len)
1166{
1167 while (len-- > 0) {
1168 rtl_eri_write(ioaddr, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1169 r++;
1170 }
1171}
1172
daf9df6d 1173static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
1174{
1175 u8 value = 0xff;
1176 unsigned int i;
1177
1178 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1179
1180 for (i = 0; i < 300; i++) {
1181 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
1182 value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
1183 break;
1184 }
1185 udelay(100);
1186 }
1187
1188 return value;
1189}
1190
9085cdfa
FR		 1191static u16 rtl_get_events(struct rtl8169_private *tp)
1192{
1193 void __iomem *ioaddr = tp->mmio_addr;
1194
1195 return RTL_R16(IntrStatus);
1196}
1197
1198static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1199{
1200 void __iomem *ioaddr = tp->mmio_addr;
1201
1202 RTL_W16(IntrStatus, bits);
1203 mmiowb();
1204}
1205
1206static void rtl_irq_disable(struct rtl8169_private *tp)
1207{
1208 void __iomem *ioaddr = tp->mmio_addr;
1209
1210 RTL_W16(IntrMask, 0);
1211 mmiowb();
1212}
1213
3e990ff5
FR		 1214static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1215{
1216 void __iomem *ioaddr = tp->mmio_addr;
1217
1218 RTL_W16(IntrMask, bits);
1219}
1220
da78dbff
FR		 1221#define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1222#define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1223#define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1224
1225static void rtl_irq_enable_all(struct rtl8169_private *tp)
1226{
1227 rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1228}
1229
811fd301 1230static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1da177e4 1231{
811fd301 1232 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 1233
9085cdfa 1234 rtl_irq_disable(tp);
da78dbff 1235 rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
811fd301 1236 RTL_R8(ChipCmd);
1da177e4
LT		 1237}
1238
4da19633 1239static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1da177e4 1240{
4da19633 1241 void __iomem *ioaddr = tp->mmio_addr;
1242
1da177e4
LT		 1243 return RTL_R32(TBICSR) & TBIReset;
1244}
1245
4da19633 1246static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1da177e4 1247{
4da19633 1248 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1da177e4
LT		 1249}
1250
1251static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1252{
1253 return RTL_R32(TBICSR) & TBILinkOk;
1254}
1255
1256static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1257{
1258 return RTL_R8(PHYstatus) & LinkStatus;
1259}
1260
4da19633 1261static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1da177e4 1262{
4da19633 1263 void __iomem *ioaddr = tp->mmio_addr;
1264
1da177e4
LT		 1265 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1266}
1267
4da19633 1268static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1da177e4
LT		 1269{
1270 unsigned int val;
1271
4da19633 1272 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1273 rtl_writephy(tp, MII_BMCR, val & 0xffff);
1da177e4
LT		 1274}
1275
70090424
HW		 1276static void rtl_link_chg_patch(struct rtl8169_private *tp)
1277{
1278 void __iomem *ioaddr = tp->mmio_addr;
1279 struct net_device *dev = tp->dev;
1280
1281 if (!netif_running(dev))
1282 return;
1283
1284 if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
1285 if (RTL_R8(PHYstatus) & _1000bpsF) {
1286 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1287 0x00000011, ERIAR_EXGMAC);
1288 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1289 0x00000005, ERIAR_EXGMAC);
1290 } else if (RTL_R8(PHYstatus) & _100bps) {
1291 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1292 0x0000001f, ERIAR_EXGMAC);
1293 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1294 0x00000005, ERIAR_EXGMAC);
1295 } else {
1296 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1297 0x0000001f, ERIAR_EXGMAC);
1298 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1299 0x0000003f, ERIAR_EXGMAC);
1300 }
1301 /* Reset packet filter */
1302 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1303 ERIAR_EXGMAC);
1304 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1305 ERIAR_EXGMAC);
c2218925
HW		 1306 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1307 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1308 if (RTL_R8(PHYstatus) & _1000bpsF) {
1309 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1310 0x00000011, ERIAR_EXGMAC);
1311 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1312 0x00000005, ERIAR_EXGMAC);
1313 } else {
1314 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1315 0x0000001f, ERIAR_EXGMAC);
1316 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1317 0x0000003f, ERIAR_EXGMAC);
1318 }
70090424
HW		 1319 }
1320}
1321
e4fbce74 1322static void __rtl8169_check_link_status(struct net_device *dev,
cecb5fd7
FR		 1323 struct rtl8169_private *tp,
1324 void __iomem *ioaddr, bool pm)
1da177e4 1325{
1da177e4 1326 if (tp->link_ok(ioaddr)) {
70090424 1327 rtl_link_chg_patch(tp);
e1759441 1328 /* This is to cancel a scheduled suspend if there's one. */
e4fbce74
RW		 1329 if (pm)
1330 pm_request_resume(&tp->pci_dev->dev);
1da177e4 1331 netif_carrier_on(dev);
1519e57f
FR		 1332 if (net_ratelimit())
1333 netif_info(tp, ifup, dev, "link up\n");
b57b7e5a 1334 } else {
1da177e4 1335 netif_carrier_off(dev);
bf82c189 1336 netif_info(tp, ifdown, dev, "link down\n");
e4fbce74 1337 if (pm)
10953db8 1338 pm_schedule_suspend(&tp->pci_dev->dev, 5000);
b57b7e5a 1339 }
1da177e4
LT		 1340}
1341
e4fbce74
RW		 1342static void rtl8169_check_link_status(struct net_device *dev,
1343 struct rtl8169_private *tp,
1344 void __iomem *ioaddr)
1345{
1346 __rtl8169_check_link_status(dev, tp, ioaddr, false);
1347}
1348
e1759441
RW		 1349#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1350
1351static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
61a4dcc2 1352{
61a4dcc2
FR		 1353 void __iomem *ioaddr = tp->mmio_addr;
1354 u8 options;
e1759441 1355 u32 wolopts = 0;
61a4dcc2
FR		 1356
1357 options = RTL_R8(Config1);
1358 if (!(options & PMEnable))
e1759441 1359 return 0;
61a4dcc2
FR		 1360
1361 options = RTL_R8(Config3);
1362 if (options & LinkUp)
e1759441 1363 wolopts |= WAKE_PHY;
61a4dcc2 1364 if (options & MagicPacket)
e1759441 1365 wolopts |= WAKE_MAGIC;
61a4dcc2
FR		 1366
1367 options = RTL_R8(Config5);
1368 if (options & UWF)
e1759441 1369 wolopts |= WAKE_UCAST;
61a4dcc2 1370 if (options & BWF)
e1759441 1371 wolopts |= WAKE_BCAST;
61a4dcc2 1372 if (options & MWF)
e1759441 1373 wolopts |= WAKE_MCAST;
61a4dcc2 1374
e1759441 1375 return wolopts;
61a4dcc2
FR		 1376}
1377
e1759441 1378static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
61a4dcc2
FR		 1379{
1380 struct rtl8169_private *tp = netdev_priv(dev);
e1759441 1381
da78dbff 1382 rtl_lock_work(tp);
e1759441
RW		 1383
1384 wol->supported = WAKE_ANY;
1385 wol->wolopts = __rtl8169_get_wol(tp);
1386
da78dbff 1387 rtl_unlock_work(tp);
e1759441
RW		 1388}
1389
1390static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1391{
61a4dcc2 1392 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 1393 unsigned int i;
350f7596 1394 static const struct {
61a4dcc2
FR		 1395 u32 opt;
1396 u16 reg;
1397 u8 mask;
1398 } cfg[] = {
1399 { WAKE_ANY, Config1, PMEnable },
1400 { WAKE_PHY, Config3, LinkUp },
1401 { WAKE_MAGIC, Config3, MagicPacket },
1402 { WAKE_UCAST, Config5, UWF },
1403 { WAKE_BCAST, Config5, BWF },
1404 { WAKE_MCAST, Config5, MWF },
1405 { WAKE_ANY, Config5, LanWake }
1406 };
1407
61a4dcc2
FR		 1408 RTL_W8(Cfg9346, Cfg9346_Unlock);
1409
1410 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1411 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
e1759441 1412 if (wolopts & cfg[i].opt)
61a4dcc2
FR		 1413 options |= cfg[i].mask;
1414 RTL_W8(cfg[i].reg, options);
1415 }
1416
1417 RTL_W8(Cfg9346, Cfg9346_Lock);
e1759441
RW		 1418}
1419
1420static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1421{
1422 struct rtl8169_private *tp = netdev_priv(dev);
1423
da78dbff 1424 rtl_lock_work(tp);
61a4dcc2 1425
f23e7fda
FR		 1426 if (wol->wolopts)
1427 tp->features |= RTL_FEATURE_WOL;
1428 else
1429 tp->features &= ~RTL_FEATURE_WOL;
e1759441 1430 __rtl8169_set_wol(tp, wol->wolopts);
da78dbff
FR		 1431
1432 rtl_unlock_work(tp);
61a4dcc2 1433
ea80907f 1434 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1435
61a4dcc2
FR		 1436 return 0;
1437}
1438
31bd204f
FR		 1439static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1440{
85bffe6c 1441 return rtl_chip_infos[tp->mac_version].fw_name;
31bd204f
FR		 1442}
1443
1da177e4
LT		 1444static void rtl8169_get_drvinfo(struct net_device *dev,
1445 struct ethtool_drvinfo *info)
1446{
1447 struct rtl8169_private *tp = netdev_priv(dev);
b6ffd97f 1448 struct rtl_fw *rtl_fw = tp->rtl_fw;
1da177e4 1449
68aad78c
RJ		 1450 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1451 strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1452 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1c361efb 1453 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
8ac72d16
RJ		 1454 if (!IS_ERR_OR_NULL(rtl_fw))
1455 strlcpy(info->fw_version, rtl_fw->version,
1456 sizeof(info->fw_version));
1da177e4
LT		 1457}
1458
1459static int rtl8169_get_regs_len(struct net_device *dev)
1460{
1461 return R8169_REGS_SIZE;
1462}
1463
1464static int rtl8169_set_speed_tbi(struct net_device *dev,
54405cde 1465 u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1da177e4
LT		 1466{
1467 struct rtl8169_private *tp = netdev_priv(dev);
1468 void __iomem *ioaddr = tp->mmio_addr;
1469 int ret = 0;
1470 u32 reg;
1471
1472 reg = RTL_R32(TBICSR);
1473 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1474 (duplex == DUPLEX_FULL)) {
1475 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1476 } else if (autoneg == AUTONEG_ENABLE)
1477 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1478 else {
bf82c189
JP		 1479 netif_warn(tp, link, dev,
1480 "incorrect speed setting refused in TBI mode\n");
1da177e4
LT		 1481 ret = -EOPNOTSUPP;
1482 }
1483
1484 return ret;
1485}
1486
1487static int rtl8169_set_speed_xmii(struct net_device *dev,
54405cde 1488 u8 autoneg, u16 speed, u8 duplex, u32 adv)
1da177e4
LT		 1489{
1490 struct rtl8169_private *tp = netdev_priv(dev);
3577aa1b 1491 int giga_ctrl, bmcr;
54405cde 1492 int rc = -EINVAL;
1da177e4 1493
716b50a3 1494 rtl_writephy(tp, 0x1f, 0x0000);
1da177e4
LT		 1495
1496 if (autoneg == AUTONEG_ENABLE) {
3577aa1b 1497 int auto_nego;
1498
4da19633 1499 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
54405cde
ON		 1500 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1501 ADVERTISE_100HALF | ADVERTISE_100FULL);
1502
1503 if (adv & ADVERTISED_10baseT_Half)
1504 auto_nego |= ADVERTISE_10HALF;
1505 if (adv & ADVERTISED_10baseT_Full)
1506 auto_nego |= ADVERTISE_10FULL;
1507 if (adv & ADVERTISED_100baseT_Half)
1508 auto_nego |= ADVERTISE_100HALF;
1509 if (adv & ADVERTISED_100baseT_Full)
1510 auto_nego |= ADVERTISE_100FULL;
1511
3577aa1b 1512 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1da177e4 1513
4da19633 1514 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
3577aa1b 1515 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
bcf0bf90 1516
3577aa1b 1517 /* The 8100e/8101e/8102e do Fast Ethernet only. */
826e6cbd 1518 if (tp->mii.supports_gmii) {
54405cde
ON		 1519 if (adv & ADVERTISED_1000baseT_Half)
1520 giga_ctrl |= ADVERTISE_1000HALF;
1521 if (adv & ADVERTISED_1000baseT_Full)
1522 giga_ctrl |= ADVERTISE_1000FULL;
1523 } else if (adv & (ADVERTISED_1000baseT_Half |
1524 ADVERTISED_1000baseT_Full)) {
bf82c189
JP		 1525 netif_info(tp, link, dev,
1526 "PHY does not support 1000Mbps\n");
54405cde 1527 goto out;
bcf0bf90 1528 }
1da177e4 1529
3577aa1b 1530 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1531
4da19633 1532 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1533 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
3577aa1b 1534 } else {
1535 giga_ctrl = 0;
1536
1537 if (speed == SPEED_10)
1538 bmcr = 0;
1539 else if (speed == SPEED_100)
1540 bmcr = BMCR_SPEED100;
1541 else
54405cde 1542 goto out;
3577aa1b 1543
1544 if (duplex == DUPLEX_FULL)
1545 bmcr |= BMCR_FULLDPLX;
2584fbc3
RS		 1546 }
1547
4da19633 1548 rtl_writephy(tp, MII_BMCR, bmcr);
3577aa1b 1549
cecb5fd7
FR		 1550 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1551 tp->mac_version == RTL_GIGA_MAC_VER_03) {
3577aa1b 1552 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
4da19633 1553 rtl_writephy(tp, 0x17, 0x2138);
1554 rtl_writephy(tp, 0x0e, 0x0260);
3577aa1b 1555 } else {
4da19633 1556 rtl_writephy(tp, 0x17, 0x2108);
1557 rtl_writephy(tp, 0x0e, 0x0000);
3577aa1b 1558 }
1559 }
1560
54405cde
ON		 1561 rc = 0;
1562out:
1563 return rc;
1da177e4
LT		 1564}
1565
1566static int rtl8169_set_speed(struct net_device *dev,
54405cde 1567 u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1da177e4
LT		 1568{
1569 struct rtl8169_private *tp = netdev_priv(dev);
1570 int ret;
1571
54405cde 1572 ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
4876cc1e
FR		 1573 if (ret < 0)
1574 goto out;
1da177e4 1575
4876cc1e
FR		 1576 if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1577 (advertising & ADVERTISED_1000baseT_Full)) {
1da177e4 1578 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
4876cc1e
FR		 1579 }
1580out:
1da177e4
LT		 1581 return ret;
1582}
1583
1584static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1585{
1586 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4
LT		 1587 int ret;
1588
4876cc1e
FR		 1589 del_timer_sync(&tp->timer);
1590
da78dbff 1591 rtl_lock_work(tp);
cecb5fd7 1592 ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
25db0338 1593 cmd->duplex, cmd->advertising);
da78dbff 1594 rtl_unlock_work(tp);
5b0384f4 1595
1da177e4
LT		 1596 return ret;
1597}
1598
c8f44aff
MM		 1599static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1600 netdev_features_t features)
1da177e4 1601{
d58d46b5
FR		 1602 struct rtl8169_private *tp = netdev_priv(dev);
1603
2b7b4318 1604 if (dev->mtu > TD_MSS_MAX)
350fb32a 1605 features &= ~NETIF_F_ALL_TSO;
1da177e4 1606
d58d46b5
FR		 1607 if (dev->mtu > JUMBO_1K &&
1608 !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
1609 features &= ~NETIF_F_IP_CSUM;
1610
350fb32a 1611 return features;
1da177e4
LT		 1612}
1613
da78dbff
FR		 1614static void __rtl8169_set_features(struct net_device *dev,
1615 netdev_features_t features)
1da177e4
LT		 1616{
1617 struct rtl8169_private *tp = netdev_priv(dev);
6bbe021d 1618 netdev_features_t changed = features ^ dev->features;
da78dbff 1619 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 1620
6bbe021d
BG		 1621 if (!(changed & (NETIF_F_RXALL | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX)))
1622 return;
1da177e4 1623
6bbe021d
BG		 1624 if (changed & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX)) {
1625 if (features & NETIF_F_RXCSUM)
1626 tp->cp_cmd |= RxChkSum;
1627 else
1628 tp->cp_cmd &= ~RxChkSum;
350fb32a 1629
6bbe021d
BG		 1630 if (dev->features & NETIF_F_HW_VLAN_RX)
1631 tp->cp_cmd |= RxVlan;
1632 else
1633 tp->cp_cmd &= ~RxVlan;
1634
1635 RTL_W16(CPlusCmd, tp->cp_cmd);
1636 RTL_R16(CPlusCmd);
1637 }
1638 if (changed & NETIF_F_RXALL) {
1639 int tmp = (RTL_R32(RxConfig) & ~(AcceptErr | AcceptRunt));
1640 if (features & NETIF_F_RXALL)
1641 tmp |= (AcceptErr | AcceptRunt);
1642 RTL_W32(RxConfig, tmp);
1643 }
da78dbff 1644}
1da177e4 1645
da78dbff
FR		 1646static int rtl8169_set_features(struct net_device *dev,
1647 netdev_features_t features)
1648{
1649 struct rtl8169_private *tp = netdev_priv(dev);
1650
1651 rtl_lock_work(tp);
1652 __rtl8169_set_features(dev, features);
1653 rtl_unlock_work(tp);
1da177e4
LT		 1654
1655 return 0;
1656}
1657
da78dbff 1658
1da177e4
LT		 1659static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1660 struct sk_buff *skb)
1661{
eab6d18d 1662 return (vlan_tx_tag_present(skb)) ?
1da177e4
LT		 1663 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1664}
1665
7a8fc77b 1666static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1da177e4
LT		 1667{
1668 u32 opts2 = le32_to_cpu(desc->opts2);
1da177e4 1669
7a8fc77b
FR		 1670 if (opts2 & RxVlanTag)
1671 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
2edae08e 1672
1da177e4 1673 desc->opts2 = 0;
1da177e4
LT		 1674}
1675
ccdffb9a 1676static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1677{
1678 struct rtl8169_private *tp = netdev_priv(dev);
1679 void __iomem *ioaddr = tp->mmio_addr;
1680 u32 status;
1681
1682 cmd->supported =
1683 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1684 cmd->port = PORT_FIBRE;
1685 cmd->transceiver = XCVR_INTERNAL;
1686
1687 status = RTL_R32(TBICSR);
1688 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1689 cmd->autoneg = !!(status & TBINwEnable);
1690
70739497 1691 ethtool_cmd_speed_set(cmd, SPEED_1000);
1da177e4 1692 cmd->duplex = DUPLEX_FULL; /* Always set */
ccdffb9a
FR		 1693
1694 return 0;
1da177e4
LT		 1695}
1696
ccdffb9a 1697static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1698{
1699 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a
FR		 1700
1701 return mii_ethtool_gset(&tp->mii, cmd);
1da177e4
LT		 1702}
1703
1704static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1705{
1706 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 1707 int rc;
1da177e4 1708
da78dbff 1709 rtl_lock_work(tp);
ccdffb9a 1710 rc = tp->get_settings(dev, cmd);
da78dbff 1711 rtl_unlock_work(tp);
1da177e4 1712
ccdffb9a 1713 return rc;
1da177e4
LT		 1714}
1715
1716static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1717 void *p)
1718{
5b0384f4 1719 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 1720
5b0384f4
FR		 1721 if (regs->len > R8169_REGS_SIZE)
1722 regs->len = R8169_REGS_SIZE;
1da177e4 1723
da78dbff 1724 rtl_lock_work(tp);
5b0384f4 1725 memcpy_fromio(p, tp->mmio_addr, regs->len);
da78dbff 1726 rtl_unlock_work(tp);
1da177e4
LT		 1727}
1728
b57b7e5a
SH		 1729static u32 rtl8169_get_msglevel(struct net_device *dev)
1730{
1731 struct rtl8169_private *tp = netdev_priv(dev);
1732
1733 return tp->msg_enable;
1734}
1735
1736static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1737{
1738 struct rtl8169_private *tp = netdev_priv(dev);
1739
1740 tp->msg_enable = value;
1741}
1742
d4a3a0fc
SH		 1743static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1744 "tx_packets",
1745 "rx_packets",
1746 "tx_errors",
1747 "rx_errors",
1748 "rx_missed",
1749 "align_errors",
1750 "tx_single_collisions",
1751 "tx_multi_collisions",
1752 "unicast",
1753 "broadcast",
1754 "multicast",
1755 "tx_aborted",
1756 "tx_underrun",
1757};
1758
b9f2c044 1759static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 1760{
b9f2c044
JG		 1761 switch (sset) {
1762 case ETH_SS_STATS:
1763 return ARRAY_SIZE(rtl8169_gstrings);
1764 default:
1765 return -EOPNOTSUPP;
1766 }
d4a3a0fc
SH		 1767}
1768
355423d0 1769static void rtl8169_update_counters(struct net_device *dev)
d4a3a0fc
SH		 1770{
1771 struct rtl8169_private *tp = netdev_priv(dev);
1772 void __iomem *ioaddr = tp->mmio_addr;
cecb5fd7 1773 struct device *d = &tp->pci_dev->dev;
d4a3a0fc
SH		 1774 struct rtl8169_counters *counters;
1775 dma_addr_t paddr;
1776 u32 cmd;
355423d0 1777 int wait = 1000;
d4a3a0fc 1778
355423d0
IV		 1779 /*
1780 * Some chips are unable to dump tally counters when the receiver
1781 * is disabled.
1782 */
1783 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1784 return;
d4a3a0fc 1785
48addcc9 1786 counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
d4a3a0fc
SH		 1787 if (!counters)
1788 return;
1789
1790 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
284901a9 1791 cmd = (u64)paddr & DMA_BIT_MASK(32);
d4a3a0fc
SH		 1792 RTL_W32(CounterAddrLow, cmd);
1793 RTL_W32(CounterAddrLow, cmd | CounterDump);
1794
355423d0
IV		 1795 while (wait--) {
1796 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
355423d0 1797 memcpy(&tp->counters, counters, sizeof(*counters));
d4a3a0fc 1798 break;
355423d0
IV		 1799 }
1800 udelay(10);
d4a3a0fc
SH		 1801 }
1802
1803 RTL_W32(CounterAddrLow, 0);
1804 RTL_W32(CounterAddrHigh, 0);
1805
48addcc9 1806 dma_free_coherent(d, sizeof(*counters), counters, paddr);
d4a3a0fc
SH		 1807}
1808
355423d0
IV		 1809static void rtl8169_get_ethtool_stats(struct net_device *dev,
1810 struct ethtool_stats *stats, u64 *data)
1811{
1812 struct rtl8169_private *tp = netdev_priv(dev);
1813
1814 ASSERT_RTNL();
1815
1816 rtl8169_update_counters(dev);
1817
1818 data[0] = le64_to_cpu(tp->counters.tx_packets);
1819 data[1] = le64_to_cpu(tp->counters.rx_packets);
1820 data[2] = le64_to_cpu(tp->counters.tx_errors);
1821 data[3] = le32_to_cpu(tp->counters.rx_errors);
1822 data[4] = le16_to_cpu(tp->counters.rx_missed);
1823 data[5] = le16_to_cpu(tp->counters.align_errors);
1824 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1825 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1826 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1827 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1828 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1829 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1830 data[12] = le16_to_cpu(tp->counters.tx_underun);
1831}
1832
d4a3a0fc
SH		 1833static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1834{
1835 switch(stringset) {
1836 case ETH_SS_STATS:
1837 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1838 break;
1839 }
1840}
1841
7282d491 1842static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 1843 .get_drvinfo = rtl8169_get_drvinfo,
1844 .get_regs_len = rtl8169_get_regs_len,
1845 .get_link = ethtool_op_get_link,
1846 .get_settings = rtl8169_get_settings,
1847 .set_settings = rtl8169_set_settings,
b57b7e5a
SH		 1848 .get_msglevel = rtl8169_get_msglevel,
1849 .set_msglevel = rtl8169_set_msglevel,
1da177e4 1850 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 1851 .get_wol = rtl8169_get_wol,
1852 .set_wol = rtl8169_set_wol,
d4a3a0fc 1853 .get_strings = rtl8169_get_strings,
b9f2c044 1854 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 1855 .get_ethtool_stats = rtl8169_get_ethtool_stats,
e1593bb1 1856 .get_ts_info = ethtool_op_get_ts_info,
1da177e4
LT		 1857};
1858
07d3f51f 1859static void rtl8169_get_mac_version(struct rtl8169_private *tp,
5d320a20 1860 struct net_device *dev, u8 default_version)
1da177e4 1861{
5d320a20 1862 void __iomem *ioaddr = tp->mmio_addr;
0e485150
FR		 1863 /*
1864 * The driver currently handles the 8168Bf and the 8168Be identically
1865 * but they can be identified more specifically through the test below
1866 * if needed:
1867 *
1868 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 1869 *
1870 * Same thing for the 8101Eb and the 8101Ec:
1871 *
1872 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 1873 */
3744100e 1874 static const struct rtl_mac_info {
1da177e4 1875 u32 mask;
e3cf0cc0 1876 u32 val;
1da177e4
LT		 1877 int mac_version;
1878 } mac_info[] = {
c2218925
HW		 1879 /* 8168F family. */
1880 { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36 },
1881 { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35 },
1882
01dc7fec 1883 /* 8168E family. */
70090424 1884 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 },
01dc7fec 1885 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 },
1886 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
1887 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
1888
5b538df9 1889 /* 8168D family. */
daf9df6d 1890 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
1891 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
daf9df6d 1892 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
5b538df9 1893
e6de30d6 1894 /* 8168DP family. */
1895 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
1896 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
4804b3b3 1897 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
e6de30d6 1898
ef808d50 1899 /* 8168C family. */
17c99297 1900 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
ef3386f0 1901 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
ef808d50 1902 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
7f3e3d3a 1903 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
e3cf0cc0
FR		 1904 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1905 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
197ff761 1906 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
6fb07058 1907 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
ef808d50 1908 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
e3cf0cc0
FR		 1909
1910 /* 8168B family. */
1911 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1912 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1913 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1914 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1915
1916 /* 8101 family. */
36a0e6c2 1917 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 },
5a5e4443
HW		 1918 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 },
1919 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
1920 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
2857ffb7
FR		 1921 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1922 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1923 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
1924 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
1925 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
1926 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
e3cf0cc0 1927 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2857ffb7 1928 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
e3cf0cc0 1929 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2857ffb7
FR		 1930 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
1931 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
e3cf0cc0
FR		 1932 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1933 /* FIXME: where did these entries come from ? -- FR */
1934 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1935 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1936
1937 /* 8110 family. */
1938 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1939 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1940 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1941 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1942 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1943 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1944
f21b75e9
JD		 1945 /* Catch-all */
1946 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
3744100e
FR		 1947 };
1948 const struct rtl_mac_info *p = mac_info;
1da177e4
LT		 1949 u32 reg;
1950
e3cf0cc0
FR		 1951 reg = RTL_R32(TxConfig);
1952 while ((reg & p->mask) != p->val)
1da177e4
LT		 1953 p++;
1954 tp->mac_version = p->mac_version;
5d320a20
FR		 1955
1956 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
1957 netif_notice(tp, probe, dev,
1958 "unknown MAC, using family default\n");
1959 tp->mac_version = default_version;
1960 }
1da177e4
LT		 1961}
1962
1963static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1964{
bcf0bf90 1965 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 1966}
1967
867763c1
FR		 1968struct phy_reg {
1969 u16 reg;
1970 u16 val;
1971};
1972
4da19633 1973static void rtl_writephy_batch(struct rtl8169_private *tp,
1974 const struct phy_reg *regs, int len)
867763c1
FR		 1975{
1976 while (len-- > 0) {
4da19633 1977 rtl_writephy(tp, regs->reg, regs->val);
867763c1
FR		 1978 regs++;
1979 }
1980}
1981
bca03d5f 1982#define PHY_READ 0x00000000
1983#define PHY_DATA_OR 0x10000000
1984#define PHY_DATA_AND 0x20000000
1985#define PHY_BJMPN 0x30000000
1986#define PHY_READ_EFUSE 0x40000000
1987#define PHY_READ_MAC_BYTE 0x50000000
1988#define PHY_WRITE_MAC_BYTE 0x60000000
1989#define PHY_CLEAR_READCOUNT 0x70000000
1990#define PHY_WRITE 0x80000000
1991#define PHY_READCOUNT_EQ_SKIP 0x90000000
1992#define PHY_COMP_EQ_SKIPN 0xa0000000
1993#define PHY_COMP_NEQ_SKIPN 0xb0000000
1994#define PHY_WRITE_PREVIOUS 0xc0000000
1995#define PHY_SKIPN 0xd0000000
1996#define PHY_DELAY_MS 0xe0000000
1997#define PHY_WRITE_ERI_WORD 0xf0000000
1998
960aee6c
HW		 1999struct fw_info {
2000 u32 magic;
2001 char version[RTL_VER_SIZE];
2002 __le32 fw_start;
2003 __le32 fw_len;
2004 u8 chksum;
2005} __packed;
2006
1c361efb
FR		 2007#define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2008
2009static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
bca03d5f 2010{
b6ffd97f 2011 const struct firmware *fw = rtl_fw->fw;
960aee6c 2012 struct fw_info *fw_info = (struct fw_info *)fw->data;
1c361efb
FR		 2013 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2014 char *version = rtl_fw->version;
2015 bool rc = false;
2016
2017 if (fw->size < FW_OPCODE_SIZE)
2018 goto out;
960aee6c
HW		 2019
2020 if (!fw_info->magic) {
2021 size_t i, size, start;
2022 u8 checksum = 0;
2023
2024 if (fw->size < sizeof(*fw_info))
2025 goto out;
2026
2027 for (i = 0; i < fw->size; i++)
2028 checksum += fw->data[i];
2029 if (checksum != 0)
2030 goto out;
2031
2032 start = le32_to_cpu(fw_info->fw_start);
2033 if (start > fw->size)
2034 goto out;
2035
2036 size = le32_to_cpu(fw_info->fw_len);
2037 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2038 goto out;
2039
2040 memcpy(version, fw_info->version, RTL_VER_SIZE);
2041
2042 pa->code = (__le32 *)(fw->data + start);
2043 pa->size = size;
2044 } else {
1c361efb
FR		 2045 if (fw->size % FW_OPCODE_SIZE)
2046 goto out;
2047
2048 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2049
2050 pa->code = (__le32 *)fw->data;
2051 pa->size = fw->size / FW_OPCODE_SIZE;
2052 }
2053 version[RTL_VER_SIZE - 1] = 0;
2054
2055 rc = true;
2056out:
2057 return rc;
2058}
2059
fd112f2e
FR		 2060static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2061 struct rtl_fw_phy_action *pa)
1c361efb 2062{
fd112f2e 2063 bool rc = false;
1c361efb 2064 size_t index;
bca03d5f 2065
1c361efb
FR		 2066 for (index = 0; index < pa->size; index++) {
2067 u32 action = le32_to_cpu(pa->code[index]);
42b82dc1 2068 u32 regno = (action & 0x0fff0000) >> 16;
bca03d5f 2069
42b82dc1 2070 switch(action & 0xf0000000) {
2071 case PHY_READ:
2072 case PHY_DATA_OR:
2073 case PHY_DATA_AND:
2074 case PHY_READ_EFUSE:
2075 case PHY_CLEAR_READCOUNT:
2076 case PHY_WRITE:
2077 case PHY_WRITE_PREVIOUS:
2078 case PHY_DELAY_MS:
2079 break;
2080
2081 case PHY_BJMPN:
2082 if (regno > index) {
fd112f2e 2083 netif_err(tp, ifup, tp->dev,
cecb5fd7 2084 "Out of range of firmware\n");
fd112f2e 2085 goto out;
42b82dc1 2086 }
2087 break;
2088 case PHY_READCOUNT_EQ_SKIP:
1c361efb 2089 if (index + 2 >= pa->size) {
fd112f2e 2090 netif_err(tp, ifup, tp->dev,
cecb5fd7 2091 "Out of range of firmware\n");
fd112f2e 2092 goto out;
42b82dc1 2093 }
2094 break;
2095 case PHY_COMP_EQ_SKIPN:
2096 case PHY_COMP_NEQ_SKIPN:
2097 case PHY_SKIPN:
1c361efb 2098 if (index + 1 + regno >= pa->size) {
fd112f2e 2099 netif_err(tp, ifup, tp->dev,
cecb5fd7 2100 "Out of range of firmware\n");
fd112f2e 2101 goto out;
42b82dc1 2102 }
bca03d5f 2103 break;
2104
42b82dc1 2105 case PHY_READ_MAC_BYTE:
2106 case PHY_WRITE_MAC_BYTE:
2107 case PHY_WRITE_ERI_WORD:
2108 default:
fd112f2e 2109 netif_err(tp, ifup, tp->dev,
42b82dc1 2110 "Invalid action 0x%08x\n", action);
fd112f2e 2111 goto out;
bca03d5f 2112 }
2113 }
fd112f2e
FR		 2114 rc = true;
2115out:
2116 return rc;
2117}
bca03d5f 2118
fd112f2e
FR		 2119static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2120{
2121 struct net_device *dev = tp->dev;
2122 int rc = -EINVAL;
2123
2124 if (!rtl_fw_format_ok(tp, rtl_fw)) {
2125 netif_err(tp, ifup, dev, "invalid firwmare\n");
2126 goto out;
2127 }
2128
2129 if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2130 rc = 0;
2131out:
2132 return rc;
2133}
2134
2135static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2136{
2137 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2138 u32 predata, count;
2139 size_t index;
2140
2141 predata = count = 0;
42b82dc1 2142
1c361efb
FR		 2143 for (index = 0; index < pa->size; ) {
2144 u32 action = le32_to_cpu(pa->code[index]);
bca03d5f 2145 u32 data = action & 0x0000ffff;
42b82dc1 2146 u32 regno = (action & 0x0fff0000) >> 16;
2147
2148 if (!action)
2149 break;
bca03d5f 2150
2151 switch(action & 0xf0000000) {
42b82dc1 2152 case PHY_READ:
2153 predata = rtl_readphy(tp, regno);
2154 count++;
2155 index++;
2156 break;
2157 case PHY_DATA_OR:
2158 predata |= data;
2159 index++;
2160 break;
2161 case PHY_DATA_AND:
2162 predata &= data;
2163 index++;
2164 break;
2165 case PHY_BJMPN:
2166 index -= regno;
2167 break;
2168 case PHY_READ_EFUSE:
2169 predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
2170 index++;
2171 break;
2172 case PHY_CLEAR_READCOUNT:
2173 count = 0;
2174 index++;
2175 break;
bca03d5f 2176 case PHY_WRITE:
42b82dc1 2177 rtl_writephy(tp, regno, data);
2178 index++;
2179 break;
2180 case PHY_READCOUNT_EQ_SKIP:
cecb5fd7 2181 index += (count == data) ? 2 : 1;
bca03d5f 2182 break;
42b82dc1 2183 case PHY_COMP_EQ_SKIPN:
2184 if (predata == data)
2185 index += regno;
2186 index++;
2187 break;
2188 case PHY_COMP_NEQ_SKIPN:
2189 if (predata != data)
2190 index += regno;
2191 index++;
2192 break;
2193 case PHY_WRITE_PREVIOUS:
2194 rtl_writephy(tp, regno, predata);
2195 index++;
2196 break;
2197 case PHY_SKIPN:
2198 index += regno + 1;
2199 break;
2200 case PHY_DELAY_MS:
2201 mdelay(data);
2202 index++;
2203 break;
2204
2205 case PHY_READ_MAC_BYTE:
2206 case PHY_WRITE_MAC_BYTE:
2207 case PHY_WRITE_ERI_WORD:
bca03d5f 2208 default:
2209 BUG();
2210 }
2211 }
2212}
2213
f1e02ed1 2214static void rtl_release_firmware(struct rtl8169_private *tp)
2215{
b6ffd97f
FR		 2216 if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2217 release_firmware(tp->rtl_fw->fw);
2218 kfree(tp->rtl_fw);
2219 }
2220 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
f1e02ed1 2221}
2222
953a12cc 2223static void rtl_apply_firmware(struct rtl8169_private *tp)
f1e02ed1 2224{
b6ffd97f 2225 struct rtl_fw *rtl_fw = tp->rtl_fw;
f1e02ed1 2226
2227 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
b6ffd97f
FR		 2228 if (!IS_ERR_OR_NULL(rtl_fw))
2229 rtl_phy_write_fw(tp, rtl_fw);
953a12cc
FR		 2230}
2231
2232static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2233{
2234 if (rtl_readphy(tp, reg) != val)
2235 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2236 else
2237 rtl_apply_firmware(tp);
f1e02ed1 2238}
2239
4da19633 2240static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1da177e4 2241{
350f7596 2242 static const struct phy_reg phy_reg_init[] = {
0b9b571d 2243 { 0x1f, 0x0001 },
2244 { 0x06, 0x006e },
2245 { 0x08, 0x0708 },
2246 { 0x15, 0x4000 },
2247 { 0x18, 0x65c7 },
1da177e4 2248
0b9b571d 2249 { 0x1f, 0x0001 },
2250 { 0x03, 0x00a1 },
2251 { 0x02, 0x0008 },
2252 { 0x01, 0x0120 },
2253 { 0x00, 0x1000 },
2254 { 0x04, 0x0800 },
2255 { 0x04, 0x0000 },
1da177e4 2256
0b9b571d 2257 { 0x03, 0xff41 },
2258 { 0x02, 0xdf60 },
2259 { 0x01, 0x0140 },
2260 { 0x00, 0x0077 },
2261 { 0x04, 0x7800 },
2262 { 0x04, 0x7000 },
2263
2264 { 0x03, 0x802f },
2265 { 0x02, 0x4f02 },
2266 { 0x01, 0x0409 },
2267 { 0x00, 0xf0f9 },
2268 { 0x04, 0x9800 },
2269 { 0x04, 0x9000 },
2270
2271 { 0x03, 0xdf01 },
2272 { 0x02, 0xdf20 },
2273 { 0x01, 0xff95 },
2274 { 0x00, 0xba00 },
2275 { 0x04, 0xa800 },
2276 { 0x04, 0xa000 },
2277
2278 { 0x03, 0xff41 },
2279 { 0x02, 0xdf20 },
2280 { 0x01, 0x0140 },
2281 { 0x00, 0x00bb },
2282 { 0x04, 0xb800 },
2283 { 0x04, 0xb000 },
2284
2285 { 0x03, 0xdf41 },
2286 { 0x02, 0xdc60 },
2287 { 0x01, 0x6340 },
2288 { 0x00, 0x007d },
2289 { 0x04, 0xd800 },
2290 { 0x04, 0xd000 },
2291
2292 { 0x03, 0xdf01 },
2293 { 0x02, 0xdf20 },
2294 { 0x01, 0x100a },
2295 { 0x00, 0xa0ff },
2296 { 0x04, 0xf800 },
2297 { 0x04, 0xf000 },
2298
2299 { 0x1f, 0x0000 },
2300 { 0x0b, 0x0000 },
2301 { 0x00, 0x9200 }
2302 };
1da177e4 2303
4da19633 2304 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1da177e4
LT		 2305}
2306
4da19633 2307static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
5615d9f1 2308{
350f7596 2309 static const struct phy_reg phy_reg_init[] = {
a441d7b6
FR		 2310 { 0x1f, 0x0002 },
2311 { 0x01, 0x90d0 },
2312 { 0x1f, 0x0000 }
2313 };
2314
4da19633 2315 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5615d9f1
FR		 2316}
2317
4da19633 2318static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2e955856 2319{
2320 struct pci_dev *pdev = tp->pci_dev;
2e955856 2321
ccbae55e
SS		 2322 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2323 (pdev->subsystem_device != 0xe000))
2e955856 2324 return;
2325
4da19633 2326 rtl_writephy(tp, 0x1f, 0x0001);
2327 rtl_writephy(tp, 0x10, 0xf01b);
2328 rtl_writephy(tp, 0x1f, 0x0000);
2e955856 2329}
2330
4da19633 2331static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2e955856 2332{
350f7596 2333 static const struct phy_reg phy_reg_init[] = {
2e955856 2334 { 0x1f, 0x0001 },
2335 { 0x04, 0x0000 },
2336 { 0x03, 0x00a1 },
2337 { 0x02, 0x0008 },
2338 { 0x01, 0x0120 },
2339 { 0x00, 0x1000 },
2340 { 0x04, 0x0800 },
2341 { 0x04, 0x9000 },
2342 { 0x03, 0x802f },
2343 { 0x02, 0x4f02 },
2344 { 0x01, 0x0409 },
2345 { 0x00, 0xf099 },
2346 { 0x04, 0x9800 },
2347 { 0x04, 0xa000 },
2348 { 0x03, 0xdf01 },
2349 { 0x02, 0xdf20 },
2350 { 0x01, 0xff95 },
2351 { 0x00, 0xba00 },
2352 { 0x04, 0xa800 },
2353 { 0x04, 0xf000 },
2354 { 0x03, 0xdf01 },
2355 { 0x02, 0xdf20 },
2356 { 0x01, 0x101a },
2357 { 0x00, 0xa0ff },
2358 { 0x04, 0xf800 },
2359 { 0x04, 0x0000 },
2360 { 0x1f, 0x0000 },
2361
2362 { 0x1f, 0x0001 },
2363 { 0x10, 0xf41b },
2364 { 0x14, 0xfb54 },
2365 { 0x18, 0xf5c7 },
2366 { 0x1f, 0x0000 },
2367
2368 { 0x1f, 0x0001 },
2369 { 0x17, 0x0cc0 },
2370 { 0x1f, 0x0000 }
2371 };
2372
4da19633 2373 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2e955856 2374
4da19633 2375 rtl8169scd_hw_phy_config_quirk(tp);
2e955856 2376}
2377
4da19633 2378static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
8c7006aa 2379{
350f7596 2380 static const struct phy_reg phy_reg_init[] = {
8c7006aa 2381 { 0x1f, 0x0001 },
2382 { 0x04, 0x0000 },
2383 { 0x03, 0x00a1 },
2384 { 0x02, 0x0008 },
2385 { 0x01, 0x0120 },
2386 { 0x00, 0x1000 },
2387 { 0x04, 0x0800 },
2388 { 0x04, 0x9000 },
2389 { 0x03, 0x802f },
2390 { 0x02, 0x4f02 },
2391 { 0x01, 0x0409 },
2392 { 0x00, 0xf099 },
2393 { 0x04, 0x9800 },
2394 { 0x04, 0xa000 },
2395 { 0x03, 0xdf01 },
2396 { 0x02, 0xdf20 },
2397 { 0x01, 0xff95 },
2398 { 0x00, 0xba00 },
2399 { 0x04, 0xa800 },
2400 { 0x04, 0xf000 },
2401 { 0x03, 0xdf01 },
2402 { 0x02, 0xdf20 },
2403 { 0x01, 0x101a },
2404 { 0x00, 0xa0ff },
2405 { 0x04, 0xf800 },
2406 { 0x04, 0x0000 },
2407 { 0x1f, 0x0000 },
2408
2409 { 0x1f, 0x0001 },
2410 { 0x0b, 0x8480 },
2411 { 0x1f, 0x0000 },
2412
2413 { 0x1f, 0x0001 },
2414 { 0x18, 0x67c7 },
2415 { 0x04, 0x2000 },
2416 { 0x03, 0x002f },
2417 { 0x02, 0x4360 },
2418 { 0x01, 0x0109 },
2419 { 0x00, 0x3022 },
2420 { 0x04, 0x2800 },
2421 { 0x1f, 0x0000 },
2422
2423 { 0x1f, 0x0001 },
2424 { 0x17, 0x0cc0 },
2425 { 0x1f, 0x0000 }
2426 };
2427
4da19633 2428 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
8c7006aa 2429}
2430
4da19633 2431static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
236b8082 2432{
350f7596 2433 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2434 { 0x10, 0xf41b },
2435 { 0x1f, 0x0000 }
2436 };
2437
4da19633 2438 rtl_writephy(tp, 0x1f, 0x0001);
2439 rtl_patchphy(tp, 0x16, 1 << 0);
236b8082 2440
4da19633 2441 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2442}
2443
4da19633 2444static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
236b8082 2445{
350f7596 2446 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2447 { 0x1f, 0x0001 },
2448 { 0x10, 0xf41b },
2449 { 0x1f, 0x0000 }
2450 };
2451
4da19633 2452 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2453}
2454
4da19633 2455static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2456{
350f7596 2457 static const struct phy_reg phy_reg_init[] = {
867763c1
FR		 2458 { 0x1f, 0x0000 },
2459 { 0x1d, 0x0f00 },
2460 { 0x1f, 0x0002 },
2461 { 0x0c, 0x1ec8 },
2462 { 0x1f, 0x0000 }
2463 };
2464
4da19633 2465 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
867763c1
FR		 2466}
2467
4da19633 2468static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
ef3386f0 2469{
350f7596 2470 static const struct phy_reg phy_reg_init[] = {
ef3386f0
FR		 2471 { 0x1f, 0x0001 },
2472 { 0x1d, 0x3d98 },
2473 { 0x1f, 0x0000 }
2474 };
2475
4da19633 2476 rtl_writephy(tp, 0x1f, 0x0000);
2477 rtl_patchphy(tp, 0x14, 1 << 5);
2478 rtl_patchphy(tp, 0x0d, 1 << 5);
ef3386f0 2479
4da19633 2480 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
ef3386f0
FR		 2481}
2482
4da19633 2483static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2484{
350f7596 2485 static const struct phy_reg phy_reg_init[] = {
a3f80671
FR		 2486 { 0x1f, 0x0001 },
2487 { 0x12, 0x2300 },
867763c1
FR		 2488 { 0x1f, 0x0002 },
2489 { 0x00, 0x88d4 },
2490 { 0x01, 0x82b1 },
2491 { 0x03, 0x7002 },
2492 { 0x08, 0x9e30 },
2493 { 0x09, 0x01f0 },
2494 { 0x0a, 0x5500 },
2495 { 0x0c, 0x00c8 },
2496 { 0x1f, 0x0003 },
2497 { 0x12, 0xc096 },
2498 { 0x16, 0x000a },
f50d4275
FR		 2499 { 0x1f, 0x0000 },
2500 { 0x1f, 0x0000 },
2501 { 0x09, 0x2000 },
2502 { 0x09, 0x0000 }
867763c1
FR		 2503 };
2504
4da19633 2505 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2506
4da19633 2507 rtl_patchphy(tp, 0x14, 1 << 5);
2508 rtl_patchphy(tp, 0x0d, 1 << 5);
2509 rtl_writephy(tp, 0x1f, 0x0000);
867763c1
FR		 2510}
2511
4da19633 2512static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
7da97ec9 2513{
350f7596 2514 static const struct phy_reg phy_reg_init[] = {
f50d4275 2515 { 0x1f, 0x0001 },
7da97ec9 2516 { 0x12, 0x2300 },
f50d4275
FR		 2517 { 0x03, 0x802f },
2518 { 0x02, 0x4f02 },
2519 { 0x01, 0x0409 },
2520 { 0x00, 0xf099 },
2521 { 0x04, 0x9800 },
2522 { 0x04, 0x9000 },
2523 { 0x1d, 0x3d98 },
7da97ec9
FR		 2524 { 0x1f, 0x0002 },
2525 { 0x0c, 0x7eb8 },
f50d4275
FR		 2526 { 0x06, 0x0761 },
2527 { 0x1f, 0x0003 },
2528 { 0x16, 0x0f0a },
7da97ec9
FR		 2529 { 0x1f, 0x0000 }
2530 };
2531
4da19633 2532 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2533
4da19633 2534 rtl_patchphy(tp, 0x16, 1 << 0);
2535 rtl_patchphy(tp, 0x14, 1 << 5);
2536 rtl_patchphy(tp, 0x0d, 1 << 5);
2537 rtl_writephy(tp, 0x1f, 0x0000);
7da97ec9
FR		 2538}
2539
4da19633 2540static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
197ff761 2541{
350f7596 2542 static const struct phy_reg phy_reg_init[] = {
197ff761
FR		 2543 { 0x1f, 0x0001 },
2544 { 0x12, 0x2300 },
2545 { 0x1d, 0x3d98 },
2546 { 0x1f, 0x0002 },
2547 { 0x0c, 0x7eb8 },
2548 { 0x06, 0x5461 },
2549 { 0x1f, 0x0003 },
2550 { 0x16, 0x0f0a },
2551 { 0x1f, 0x0000 }
2552 };
2553
4da19633 2554 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
197ff761 2555
4da19633 2556 rtl_patchphy(tp, 0x16, 1 << 0);
2557 rtl_patchphy(tp, 0x14, 1 << 5);
2558 rtl_patchphy(tp, 0x0d, 1 << 5);
2559 rtl_writephy(tp, 0x1f, 0x0000);
197ff761
FR		 2560}
2561
4da19633 2562static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
6fb07058 2563{
4da19633 2564 rtl8168c_3_hw_phy_config(tp);
6fb07058
FR		 2565}
2566
bca03d5f 2567static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
5b538df9 2568{
350f7596 2569 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2570 /* Channel Estimation */
5b538df9 2571 { 0x1f, 0x0001 },
daf9df6d 2572 { 0x06, 0x4064 },
2573 { 0x07, 0x2863 },
2574 { 0x08, 0x059c },
2575 { 0x09, 0x26b4 },
2576 { 0x0a, 0x6a19 },
2577 { 0x0b, 0xdcc8 },
2578 { 0x10, 0xf06d },
2579 { 0x14, 0x7f68 },
2580 { 0x18, 0x7fd9 },
2581 { 0x1c, 0xf0ff },
2582 { 0x1d, 0x3d9c },
5b538df9 2583 { 0x1f, 0x0003 },
daf9df6d 2584 { 0x12, 0xf49f },
2585 { 0x13, 0x070b },
2586 { 0x1a, 0x05ad },
bca03d5f 2587 { 0x14, 0x94c0 },
2588
2589 /*
2590 * Tx Error Issue
cecb5fd7 2591 * Enhance line driver power
bca03d5f 2592 */
5b538df9 2593 { 0x1f, 0x0002 },
daf9df6d 2594 { 0x06, 0x5561 },
2595 { 0x1f, 0x0005 },
2596 { 0x05, 0x8332 },
bca03d5f 2597 { 0x06, 0x5561 },
2598
2599 /*
2600 * Can not link to 1Gbps with bad cable
2601 * Decrease SNR threshold form 21.07dB to 19.04dB
2602 */
2603 { 0x1f, 0x0001 },
2604 { 0x17, 0x0cc0 },
daf9df6d 2605
5b538df9 2606 { 0x1f, 0x0000 },
bca03d5f 2607 { 0x0d, 0xf880 }
daf9df6d 2608 };
bca03d5f 2609 void __iomem *ioaddr = tp->mmio_addr;
daf9df6d 2610
4da19633 2611 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
daf9df6d 2612
bca03d5f 2613 /*
2614 * Rx Error Issue
2615 * Fine Tune Switching regulator parameter
2616 */
4da19633 2617 rtl_writephy(tp, 0x1f, 0x0002);
2618 rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2619 rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
daf9df6d 2620
daf9df6d 2621 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
350f7596 2622 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2623 { 0x1f, 0x0002 },
2624 { 0x05, 0x669a },
2625 { 0x1f, 0x0005 },
2626 { 0x05, 0x8330 },
2627 { 0x06, 0x669a },
2628 { 0x1f, 0x0002 }
2629 };
2630 int val;
2631
4da19633 2632 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2633
4da19633 2634 val = rtl_readphy(tp, 0x0d);
daf9df6d 2635
2636 if ((val & 0x00ff) != 0x006c) {
350f7596 2637 static const u32 set[] = {
daf9df6d 2638 0x0065, 0x0066, 0x0067, 0x0068,
2639 0x0069, 0x006a, 0x006b, 0x006c
2640 };
2641 int i;
2642
4da19633 2643 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2644
2645 val &= 0xff00;
2646 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2647 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2648 }
2649 } else {
350f7596 2650 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2651 { 0x1f, 0x0002 },
2652 { 0x05, 0x6662 },
2653 { 0x1f, 0x0005 },
2654 { 0x05, 0x8330 },
2655 { 0x06, 0x6662 }
2656 };
2657
4da19633 2658 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2659 }
2660
bca03d5f 2661 /* RSET couple improve */
4da19633 2662 rtl_writephy(tp, 0x1f, 0x0002);
2663 rtl_patchphy(tp, 0x0d, 0x0300);
2664 rtl_patchphy(tp, 0x0f, 0x0010);
daf9df6d 2665
bca03d5f 2666 /* Fine tune PLL performance */
4da19633 2667 rtl_writephy(tp, 0x1f, 0x0002);
2668 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2669 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2670
4da19633 2671 rtl_writephy(tp, 0x1f, 0x0005);
2672 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 2673
2674 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
bca03d5f 2675
4da19633 2676 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2677}
2678
bca03d5f 2679static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2680{
350f7596 2681 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2682 /* Channel Estimation */
daf9df6d 2683 { 0x1f, 0x0001 },
2684 { 0x06, 0x4064 },
2685 { 0x07, 0x2863 },
2686 { 0x08, 0x059c },
2687 { 0x09, 0x26b4 },
2688 { 0x0a, 0x6a19 },
2689 { 0x0b, 0xdcc8 },
2690 { 0x10, 0xf06d },
2691 { 0x14, 0x7f68 },
2692 { 0x18, 0x7fd9 },
2693 { 0x1c, 0xf0ff },
2694 { 0x1d, 0x3d9c },
2695 { 0x1f, 0x0003 },
2696 { 0x12, 0xf49f },
2697 { 0x13, 0x070b },
2698 { 0x1a, 0x05ad },
2699 { 0x14, 0x94c0 },
2700
bca03d5f 2701 /*
2702 * Tx Error Issue
cecb5fd7 2703 * Enhance line driver power
bca03d5f 2704 */
daf9df6d 2705 { 0x1f, 0x0002 },
2706 { 0x06, 0x5561 },
2707 { 0x1f, 0x0005 },
2708 { 0x05, 0x8332 },
bca03d5f 2709 { 0x06, 0x5561 },
2710
2711 /*
2712 * Can not link to 1Gbps with bad cable
2713 * Decrease SNR threshold form 21.07dB to 19.04dB
2714 */
2715 { 0x1f, 0x0001 },
2716 { 0x17, 0x0cc0 },
daf9df6d 2717
2718 { 0x1f, 0x0000 },
bca03d5f 2719 { 0x0d, 0xf880 }
5b538df9 2720 };
bca03d5f 2721 void __iomem *ioaddr = tp->mmio_addr;
5b538df9 2722
4da19633 2723 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
5b538df9 2724
daf9df6d 2725 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
350f7596 2726 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2727 { 0x1f, 0x0002 },
2728 { 0x05, 0x669a },
5b538df9 2729 { 0x1f, 0x0005 },
daf9df6d 2730 { 0x05, 0x8330 },
2731 { 0x06, 0x669a },
2732
2733 { 0x1f, 0x0002 }
2734 };
2735 int val;
2736
4da19633 2737 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2738
4da19633 2739 val = rtl_readphy(tp, 0x0d);
daf9df6d 2740 if ((val & 0x00ff) != 0x006c) {
b6bc7650 2741 static const u32 set[] = {
daf9df6d 2742 0x0065, 0x0066, 0x0067, 0x0068,
2743 0x0069, 0x006a, 0x006b, 0x006c
2744 };
2745 int i;
2746
4da19633 2747 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2748
2749 val &= 0xff00;
2750 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2751 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2752 }
2753 } else {
350f7596 2754 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2755 { 0x1f, 0x0002 },
2756 { 0x05, 0x2642 },
5b538df9 2757 { 0x1f, 0x0005 },
daf9df6d 2758 { 0x05, 0x8330 },
2759 { 0x06, 0x2642 }
5b538df9
FR		 2760 };
2761
4da19633 2762 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2763 }
2764
bca03d5f 2765 /* Fine tune PLL performance */
4da19633 2766 rtl_writephy(tp, 0x1f, 0x0002);
2767 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2768 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2769
bca03d5f 2770 /* Switching regulator Slew rate */
4da19633 2771 rtl_writephy(tp, 0x1f, 0x0002);
2772 rtl_patchphy(tp, 0x0f, 0x0017);
daf9df6d 2773
4da19633 2774 rtl_writephy(tp, 0x1f, 0x0005);
2775 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 2776
2777 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
bca03d5f 2778
4da19633 2779 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2780}
2781
4da19633 2782static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2783{
350f7596 2784 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2785 { 0x1f, 0x0002 },
2786 { 0x10, 0x0008 },
2787 { 0x0d, 0x006c },
2788
2789 { 0x1f, 0x0000 },
2790 { 0x0d, 0xf880 },
2791
2792 { 0x1f, 0x0001 },
2793 { 0x17, 0x0cc0 },
2794
2795 { 0x1f, 0x0001 },
2796 { 0x0b, 0xa4d8 },
2797 { 0x09, 0x281c },
2798 { 0x07, 0x2883 },
2799 { 0x0a, 0x6b35 },
2800 { 0x1d, 0x3da4 },
2801 { 0x1c, 0xeffd },
2802 { 0x14, 0x7f52 },
2803 { 0x18, 0x7fc6 },
2804 { 0x08, 0x0601 },
2805 { 0x06, 0x4063 },
2806 { 0x10, 0xf074 },
2807 { 0x1f, 0x0003 },
2808 { 0x13, 0x0789 },
2809 { 0x12, 0xf4bd },
2810 { 0x1a, 0x04fd },
2811 { 0x14, 0x84b0 },
2812 { 0x1f, 0x0000 },
2813 { 0x00, 0x9200 },
2814
2815 { 0x1f, 0x0005 },
2816 { 0x01, 0x0340 },
2817 { 0x1f, 0x0001 },
2818 { 0x04, 0x4000 },
2819 { 0x03, 0x1d21 },
2820 { 0x02, 0x0c32 },
2821 { 0x01, 0x0200 },
2822 { 0x00, 0x5554 },
2823 { 0x04, 0x4800 },
2824 { 0x04, 0x4000 },
2825 { 0x04, 0xf000 },
2826 { 0x03, 0xdf01 },
2827 { 0x02, 0xdf20 },
2828 { 0x01, 0x101a },
2829 { 0x00, 0xa0ff },
2830 { 0x04, 0xf800 },
2831 { 0x04, 0xf000 },
2832 { 0x1f, 0x0000 },
2833
2834 { 0x1f, 0x0007 },
2835 { 0x1e, 0x0023 },
2836 { 0x16, 0x0000 },
2837 { 0x1f, 0x0000 }
2838 };
2839
4da19633 2840 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2841}
2842
e6de30d6 2843static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2844{
2845 static const struct phy_reg phy_reg_init[] = {
2846 { 0x1f, 0x0001 },
2847 { 0x17, 0x0cc0 },
2848
2849 { 0x1f, 0x0007 },
2850 { 0x1e, 0x002d },
2851 { 0x18, 0x0040 },
2852 { 0x1f, 0x0000 }
2853 };
2854
2855 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2856 rtl_patchphy(tp, 0x0d, 1 << 5);
2857}
2858
70090424 2859static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
01dc7fec 2860{
2861 static const struct phy_reg phy_reg_init[] = {
2862 /* Enable Delay cap */
2863 { 0x1f, 0x0005 },
2864 { 0x05, 0x8b80 },
2865 { 0x06, 0xc896 },
2866 { 0x1f, 0x0000 },
2867
2868 /* Channel estimation fine tune */
2869 { 0x1f, 0x0001 },
2870 { 0x0b, 0x6c20 },
2871 { 0x07, 0x2872 },
2872 { 0x1c, 0xefff },
2873 { 0x1f, 0x0003 },
2874 { 0x14, 0x6420 },
2875 { 0x1f, 0x0000 },
2876
2877 /* Update PFM & 10M TX idle timer */
2878 { 0x1f, 0x0007 },
2879 { 0x1e, 0x002f },
2880 { 0x15, 0x1919 },
2881 { 0x1f, 0x0000 },
2882
2883 { 0x1f, 0x0007 },
2884 { 0x1e, 0x00ac },
2885 { 0x18, 0x0006 },
2886 { 0x1f, 0x0000 }
2887 };
2888
15ecd039
FR		 2889 rtl_apply_firmware(tp);
2890
01dc7fec 2891 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2892
2893 /* DCO enable for 10M IDLE Power */
2894 rtl_writephy(tp, 0x1f, 0x0007);
2895 rtl_writephy(tp, 0x1e, 0x0023);
2896 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2897 rtl_writephy(tp, 0x1f, 0x0000);
2898
2899 /* For impedance matching */
2900 rtl_writephy(tp, 0x1f, 0x0002);
2901 rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
cecb5fd7 2902 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 2903
2904 /* PHY auto speed down */
2905 rtl_writephy(tp, 0x1f, 0x0007);
2906 rtl_writephy(tp, 0x1e, 0x002d);
2907 rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
2908 rtl_writephy(tp, 0x1f, 0x0000);
2909 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2910
2911 rtl_writephy(tp, 0x1f, 0x0005);
2912 rtl_writephy(tp, 0x05, 0x8b86);
2913 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2914 rtl_writephy(tp, 0x1f, 0x0000);
2915
2916 rtl_writephy(tp, 0x1f, 0x0005);
2917 rtl_writephy(tp, 0x05, 0x8b85);
2918 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2919 rtl_writephy(tp, 0x1f, 0x0007);
2920 rtl_writephy(tp, 0x1e, 0x0020);
2921 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
2922 rtl_writephy(tp, 0x1f, 0x0006);
2923 rtl_writephy(tp, 0x00, 0x5a00);
2924 rtl_writephy(tp, 0x1f, 0x0000);
2925 rtl_writephy(tp, 0x0d, 0x0007);
2926 rtl_writephy(tp, 0x0e, 0x003c);
2927 rtl_writephy(tp, 0x0d, 0x4007);
2928 rtl_writephy(tp, 0x0e, 0x0000);
2929 rtl_writephy(tp, 0x0d, 0x0000);
2930}
2931
70090424
HW		 2932static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
2933{
2934 static const struct phy_reg phy_reg_init[] = {
2935 /* Enable Delay cap */
2936 { 0x1f, 0x0004 },
2937 { 0x1f, 0x0007 },
2938 { 0x1e, 0x00ac },
2939 { 0x18, 0x0006 },
2940 { 0x1f, 0x0002 },
2941 { 0x1f, 0x0000 },
2942 { 0x1f, 0x0000 },
2943
2944 /* Channel estimation fine tune */
2945 { 0x1f, 0x0003 },
2946 { 0x09, 0xa20f },
2947 { 0x1f, 0x0000 },
2948 { 0x1f, 0x0000 },
2949
2950 /* Green Setting */
2951 { 0x1f, 0x0005 },
2952 { 0x05, 0x8b5b },
2953 { 0x06, 0x9222 },
2954 { 0x05, 0x8b6d },
2955 { 0x06, 0x8000 },
2956 { 0x05, 0x8b76 },
2957 { 0x06, 0x8000 },
2958 { 0x1f, 0x0000 }
2959 };
2960
2961 rtl_apply_firmware(tp);
2962
2963 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2964
2965 /* For 4-corner performance improve */
2966 rtl_writephy(tp, 0x1f, 0x0005);
2967 rtl_writephy(tp, 0x05, 0x8b80);
2968 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2969 rtl_writephy(tp, 0x1f, 0x0000);
2970
2971 /* PHY auto speed down */
2972 rtl_writephy(tp, 0x1f, 0x0004);
2973 rtl_writephy(tp, 0x1f, 0x0007);
2974 rtl_writephy(tp, 0x1e, 0x002d);
2975 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
2976 rtl_writephy(tp, 0x1f, 0x0002);
2977 rtl_writephy(tp, 0x1f, 0x0000);
2978 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2979
2980 /* improve 10M EEE waveform */
2981 rtl_writephy(tp, 0x1f, 0x0005);
2982 rtl_writephy(tp, 0x05, 0x8b86);
2983 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2984 rtl_writephy(tp, 0x1f, 0x0000);
2985
2986 /* Improve 2-pair detection performance */
2987 rtl_writephy(tp, 0x1f, 0x0005);
2988 rtl_writephy(tp, 0x05, 0x8b85);
2989 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
2990 rtl_writephy(tp, 0x1f, 0x0000);
2991
2992 /* EEE setting */
2993 rtl_w1w0_eri(tp->mmio_addr, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003,
2994 ERIAR_EXGMAC);
2995 rtl_writephy(tp, 0x1f, 0x0005);
2996 rtl_writephy(tp, 0x05, 0x8b85);
2997 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2998 rtl_writephy(tp, 0x1f, 0x0004);
2999 rtl_writephy(tp, 0x1f, 0x0007);
3000 rtl_writephy(tp, 0x1e, 0x0020);
1b23a3e3 3001 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
70090424
HW		 3002 rtl_writephy(tp, 0x1f, 0x0002);
3003 rtl_writephy(tp, 0x1f, 0x0000);
3004 rtl_writephy(tp, 0x0d, 0x0007);
3005 rtl_writephy(tp, 0x0e, 0x003c);
3006 rtl_writephy(tp, 0x0d, 0x4007);
3007 rtl_writephy(tp, 0x0e, 0x0000);
3008 rtl_writephy(tp, 0x0d, 0x0000);
3009
3010 /* Green feature */
3011 rtl_writephy(tp, 0x1f, 0x0003);
3012 rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
3013 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
3014 rtl_writephy(tp, 0x1f, 0x0000);
3015}
3016
c2218925
HW		 3017static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3018{
3019 static const struct phy_reg phy_reg_init[] = {
3020 /* Channel estimation fine tune */
3021 { 0x1f, 0x0003 },
3022 { 0x09, 0xa20f },
3023 { 0x1f, 0x0000 },
3024
3025 /* Modify green table for giga & fnet */
3026 { 0x1f, 0x0005 },
3027 { 0x05, 0x8b55 },
3028 { 0x06, 0x0000 },
3029 { 0x05, 0x8b5e },
3030 { 0x06, 0x0000 },
3031 { 0x05, 0x8b67 },
3032 { 0x06, 0x0000 },
3033 { 0x05, 0x8b70 },
3034 { 0x06, 0x0000 },
3035 { 0x1f, 0x0000 },
3036 { 0x1f, 0x0007 },
3037 { 0x1e, 0x0078 },
3038 { 0x17, 0x0000 },
3039 { 0x19, 0x00fb },
3040 { 0x1f, 0x0000 },
3041
3042 /* Modify green table for 10M */
3043 { 0x1f, 0x0005 },
3044 { 0x05, 0x8b79 },
3045 { 0x06, 0xaa00 },
3046 { 0x1f, 0x0000 },
3047
3048 /* Disable hiimpedance detection (RTCT) */
3049 { 0x1f, 0x0003 },
3050 { 0x01, 0x328a },
3051 { 0x1f, 0x0000 }
3052 };
3053
3054 rtl_apply_firmware(tp);
3055
3056 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3057
3058 /* For 4-corner performance improve */
3059 rtl_writephy(tp, 0x1f, 0x0005);
3060 rtl_writephy(tp, 0x05, 0x8b80);
3061 rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
3062 rtl_writephy(tp, 0x1f, 0x0000);
3063
3064 /* PHY auto speed down */
3065 rtl_writephy(tp, 0x1f, 0x0007);
3066 rtl_writephy(tp, 0x1e, 0x002d);
3067 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3068 rtl_writephy(tp, 0x1f, 0x0000);
3069 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3070
3071 /* Improve 10M EEE waveform */
3072 rtl_writephy(tp, 0x1f, 0x0005);
3073 rtl_writephy(tp, 0x05, 0x8b86);
3074 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3075 rtl_writephy(tp, 0x1f, 0x0000);
3076
3077 /* Improve 2-pair detection performance */
3078 rtl_writephy(tp, 0x1f, 0x0005);
3079 rtl_writephy(tp, 0x05, 0x8b85);
3080 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3081 rtl_writephy(tp, 0x1f, 0x0000);
3082}
3083
3084static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3085{
3086 rtl_apply_firmware(tp);
3087
3088 /* For 4-corner performance improve */
3089 rtl_writephy(tp, 0x1f, 0x0005);
3090 rtl_writephy(tp, 0x05, 0x8b80);
3091 rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
3092 rtl_writephy(tp, 0x1f, 0x0000);
3093
3094 /* PHY auto speed down */
3095 rtl_writephy(tp, 0x1f, 0x0007);
3096 rtl_writephy(tp, 0x1e, 0x002d);
3097 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3098 rtl_writephy(tp, 0x1f, 0x0000);
3099 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3100
3101 /* Improve 10M EEE waveform */
3102 rtl_writephy(tp, 0x1f, 0x0005);
3103 rtl_writephy(tp, 0x05, 0x8b86);
3104 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3105 rtl_writephy(tp, 0x1f, 0x0000);
3106}
3107
4da19633 3108static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2857ffb7 3109{
350f7596 3110 static const struct phy_reg phy_reg_init[] = {
2857ffb7
FR		 3111 { 0x1f, 0x0003 },
3112 { 0x08, 0x441d },
3113 { 0x01, 0x9100 },
3114 { 0x1f, 0x0000 }
3115 };
3116
4da19633 3117 rtl_writephy(tp, 0x1f, 0x0000);
3118 rtl_patchphy(tp, 0x11, 1 << 12);
3119 rtl_patchphy(tp, 0x19, 1 << 13);
3120 rtl_patchphy(tp, 0x10, 1 << 15);
2857ffb7 3121
4da19633 3122 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2857ffb7
FR		 3123}
3124
5a5e4443
HW		 3125static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3126{
3127 static const struct phy_reg phy_reg_init[] = {
3128 { 0x1f, 0x0005 },
3129 { 0x1a, 0x0000 },
3130 { 0x1f, 0x0000 },
3131
3132 { 0x1f, 0x0004 },
3133 { 0x1c, 0x0000 },
3134 { 0x1f, 0x0000 },
3135
3136 { 0x1f, 0x0001 },
3137 { 0x15, 0x7701 },
3138 { 0x1f, 0x0000 }
3139 };
3140
3141 /* Disable ALDPS before ram code */
3142 rtl_writephy(tp, 0x1f, 0x0000);
3143 rtl_writephy(tp, 0x18, 0x0310);
3144 msleep(100);
3145
953a12cc 3146 rtl_apply_firmware(tp);
5a5e4443
HW		 3147
3148 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3149}
3150
5615d9f1
FR		 3151static void rtl_hw_phy_config(struct net_device *dev)
3152{
3153 struct rtl8169_private *tp = netdev_priv(dev);
5615d9f1
FR		 3154
3155 rtl8169_print_mac_version(tp);
3156
3157 switch (tp->mac_version) {
3158 case RTL_GIGA_MAC_VER_01:
3159 break;
3160 case RTL_GIGA_MAC_VER_02:
3161 case RTL_GIGA_MAC_VER_03:
4da19633 3162 rtl8169s_hw_phy_config(tp);
5615d9f1
FR		 3163 break;
3164 case RTL_GIGA_MAC_VER_04:
4da19633 3165 rtl8169sb_hw_phy_config(tp);
5615d9f1 3166 break;
2e955856 3167 case RTL_GIGA_MAC_VER_05:
4da19633 3168 rtl8169scd_hw_phy_config(tp);
2e955856 3169 break;
8c7006aa 3170 case RTL_GIGA_MAC_VER_06:
4da19633 3171 rtl8169sce_hw_phy_config(tp);
8c7006aa 3172 break;
2857ffb7
FR		 3173 case RTL_GIGA_MAC_VER_07:
3174 case RTL_GIGA_MAC_VER_08:
3175 case RTL_GIGA_MAC_VER_09:
4da19633 3176 rtl8102e_hw_phy_config(tp);
2857ffb7 3177 break;
236b8082 3178 case RTL_GIGA_MAC_VER_11:
4da19633 3179 rtl8168bb_hw_phy_config(tp);
236b8082
FR		 3180 break;
3181 case RTL_GIGA_MAC_VER_12:
4da19633 3182 rtl8168bef_hw_phy_config(tp);
236b8082
FR		 3183 break;
3184 case RTL_GIGA_MAC_VER_17:
4da19633 3185 rtl8168bef_hw_phy_config(tp);
236b8082 3186 break;
867763c1 3187 case RTL_GIGA_MAC_VER_18:
4da19633 3188 rtl8168cp_1_hw_phy_config(tp);
867763c1
FR		 3189 break;
3190 case RTL_GIGA_MAC_VER_19:
4da19633 3191 rtl8168c_1_hw_phy_config(tp);
867763c1 3192 break;
7da97ec9 3193 case RTL_GIGA_MAC_VER_20:
4da19633 3194 rtl8168c_2_hw_phy_config(tp);
7da97ec9 3195 break;
197ff761 3196 case RTL_GIGA_MAC_VER_21:
4da19633 3197 rtl8168c_3_hw_phy_config(tp);
197ff761 3198 break;
6fb07058 3199 case RTL_GIGA_MAC_VER_22:
4da19633 3200 rtl8168c_4_hw_phy_config(tp);
6fb07058 3201 break;
ef3386f0 3202 case RTL_GIGA_MAC_VER_23:
7f3e3d3a 3203 case RTL_GIGA_MAC_VER_24:
4da19633 3204 rtl8168cp_2_hw_phy_config(tp);
ef3386f0 3205 break;
5b538df9 3206 case RTL_GIGA_MAC_VER_25:
bca03d5f 3207 rtl8168d_1_hw_phy_config(tp);
daf9df6d 3208 break;
3209 case RTL_GIGA_MAC_VER_26:
bca03d5f 3210 rtl8168d_2_hw_phy_config(tp);
daf9df6d 3211 break;
3212 case RTL_GIGA_MAC_VER_27:
4da19633 3213 rtl8168d_3_hw_phy_config(tp);
5b538df9 3214 break;
e6de30d6 3215 case RTL_GIGA_MAC_VER_28:
3216 rtl8168d_4_hw_phy_config(tp);
3217 break;
5a5e4443
HW		 3218 case RTL_GIGA_MAC_VER_29:
3219 case RTL_GIGA_MAC_VER_30:
3220 rtl8105e_hw_phy_config(tp);
3221 break;
cecb5fd7
FR		 3222 case RTL_GIGA_MAC_VER_31:
3223 /* None. */
3224 break;
01dc7fec 3225 case RTL_GIGA_MAC_VER_32:
01dc7fec 3226 case RTL_GIGA_MAC_VER_33:
70090424
HW		 3227 rtl8168e_1_hw_phy_config(tp);
3228 break;
3229 case RTL_GIGA_MAC_VER_34:
3230 rtl8168e_2_hw_phy_config(tp);
01dc7fec 3231 break;
c2218925
HW		 3232 case RTL_GIGA_MAC_VER_35:
3233 rtl8168f_1_hw_phy_config(tp);
3234 break;
3235 case RTL_GIGA_MAC_VER_36:
3236 rtl8168f_2_hw_phy_config(tp);
3237 break;
ef3386f0 3238
5615d9f1
FR		 3239 default:
3240 break;
3241 }
3242}
3243
da78dbff 3244static void rtl_phy_work(struct rtl8169_private *tp)
1da177e4 3245{
1da177e4
LT		 3246 struct timer_list *timer = &tp->timer;
3247 void __iomem *ioaddr = tp->mmio_addr;
3248 unsigned long timeout = RTL8169_PHY_TIMEOUT;
3249
bcf0bf90 3250 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1da177e4 3251
4da19633 3252 if (tp->phy_reset_pending(tp)) {
5b0384f4 3253 /*
1da177e4
LT		 3254 * A busy loop could burn quite a few cycles on nowadays CPU.
3255 * Let's delay the execution of the timer for a few ticks.
3256 */
3257 timeout = HZ/10;
3258 goto out_mod_timer;
3259 }
3260
3261 if (tp->link_ok(ioaddr))
da78dbff 3262 return;
1da177e4 3263
da78dbff 3264 netif_warn(tp, link, tp->dev, "PHY reset until link up\n");
1da177e4 3265
4da19633 3266 tp->phy_reset_enable(tp);
1da177e4
LT		 3267
3268out_mod_timer:
3269 mod_timer(timer, jiffies + timeout);
da78dbff
FR		 3270}
3271
3272static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
3273{
da78dbff
FR		 3274 if (!test_and_set_bit(flag, tp->wk.flags))
3275 schedule_work(&tp->wk.work);
da78dbff
FR		 3276}
3277
3278static void rtl8169_phy_timer(unsigned long __opaque)
3279{
3280 struct net_device *dev = (struct net_device *)__opaque;
3281 struct rtl8169_private *tp = netdev_priv(dev);
3282
98ddf986 3283 rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
1da177e4
LT		 3284}
3285
1da177e4
LT		 3286static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
3287 void __iomem *ioaddr)
3288{
3289 iounmap(ioaddr);
3290 pci_release_regions(pdev);
87aeec76 3291 pci_clear_mwi(pdev);
1da177e4
LT		 3292 pci_disable_device(pdev);
3293 free_netdev(dev);
3294}
3295
bf793295
FR		 3296static void rtl8169_phy_reset(struct net_device *dev,
3297 struct rtl8169_private *tp)
3298{
07d3f51f 3299 unsigned int i;
bf793295 3300
4da19633 3301 tp->phy_reset_enable(tp);
bf793295 3302 for (i = 0; i < 100; i++) {
4da19633 3303 if (!tp->phy_reset_pending(tp))
bf793295
FR		 3304 return;
3305 msleep(1);
3306 }
bf82c189 3307 netif_err(tp, link, dev, "PHY reset failed\n");
bf793295
FR		 3308}
3309
2544bfc0
FR		 3310static bool rtl_tbi_enabled(struct rtl8169_private *tp)
3311{
3312 void __iomem *ioaddr = tp->mmio_addr;
3313
3314 return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
3315 (RTL_R8(PHYstatus) & TBI_Enable);
3316}
3317
4ff96fa6
FR		 3318static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3319{
3320 void __iomem *ioaddr = tp->mmio_addr;
4ff96fa6 3321
5615d9f1 3322 rtl_hw_phy_config(dev);
4ff96fa6 3323
77332894
MS		 3324 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3325 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3326 RTL_W8(0x82, 0x01);
3327 }
4ff96fa6 3328
6dccd16b
FR		 3329 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3330
3331 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3332 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 3333
bcf0bf90 3334 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4ff96fa6
FR		 3335 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3336 RTL_W8(0x82, 0x01);
3337 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
4da19633 3338 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4ff96fa6
FR		 3339 }
3340
bf793295
FR		 3341 rtl8169_phy_reset(dev, tp);
3342
54405cde 3343 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
cecb5fd7
FR		 3344 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3345 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
3346 (tp->mii.supports_gmii ?
3347 ADVERTISED_1000baseT_Half |
3348 ADVERTISED_1000baseT_Full : 0));
4ff96fa6 3349
2544bfc0 3350 if (rtl_tbi_enabled(tp))
bf82c189 3351 netif_info(tp, link, dev, "TBI auto-negotiating\n");
4ff96fa6
FR		 3352}
3353
773d2021
FR		 3354static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3355{
3356 void __iomem *ioaddr = tp->mmio_addr;
3357 u32 high;
3358 u32 low;
3359
3360 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
3361 high = addr[4] | (addr[5] << 8);
3362
da78dbff 3363 rtl_lock_work(tp);
773d2021
FR		 3364
3365 RTL_W8(Cfg9346, Cfg9346_Unlock);
908ba2bf 3366
773d2021 3367 RTL_W32(MAC4, high);
908ba2bf 3368 RTL_R32(MAC4);
3369
78f1cd02 3370 RTL_W32(MAC0, low);
908ba2bf 3371 RTL_R32(MAC0);
3372
c28aa385 3373 if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
3374 const struct exgmac_reg e[] = {
3375 { .addr = 0xe0, ERIAR_MASK_1111, .val = low },
3376 { .addr = 0xe4, ERIAR_MASK_1111, .val = high },
3377 { .addr = 0xf0, ERIAR_MASK_1111, .val = low << 16 },
3378 { .addr = 0xf4, ERIAR_MASK_1111, .val = high << 16 |
3379 low >> 16 },
3380 };
3381
3382 rtl_write_exgmac_batch(ioaddr, e, ARRAY_SIZE(e));
3383 }
3384
773d2021
FR		 3385 RTL_W8(Cfg9346, Cfg9346_Lock);
3386
da78dbff 3387 rtl_unlock_work(tp);
773d2021
FR		 3388}
3389
3390static int rtl_set_mac_address(struct net_device *dev, void *p)
3391{
3392 struct rtl8169_private *tp = netdev_priv(dev);
3393 struct sockaddr *addr = p;
3394
3395 if (!is_valid_ether_addr(addr->sa_data))
3396 return -EADDRNOTAVAIL;
3397
3398 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3399
3400 rtl_rar_set(tp, dev->dev_addr);
3401
3402 return 0;
3403}
3404
5f787a1a
FR		 3405static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3406{
3407 struct rtl8169_private *tp = netdev_priv(dev);
3408 struct mii_ioctl_data *data = if_mii(ifr);
3409
8b4ab28d
FR		 3410 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
3411}
5f787a1a 3412
cecb5fd7
FR		 3413static int rtl_xmii_ioctl(struct rtl8169_private *tp,
3414 struct mii_ioctl_data *data, int cmd)
8b4ab28d 3415{
5f787a1a
FR		 3416 switch (cmd) {
3417 case SIOCGMIIPHY:
3418 data->phy_id = 32; /* Internal PHY */
3419 return 0;
3420
3421 case SIOCGMIIREG:
4da19633 3422 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
5f787a1a
FR		 3423 return 0;
3424
3425 case SIOCSMIIREG:
4da19633 3426 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
5f787a1a
FR		 3427 return 0;
3428 }
3429 return -EOPNOTSUPP;
3430}
3431
8b4ab28d
FR		 3432static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
3433{
3434 return -EOPNOTSUPP;
3435}
3436
fbac58fc
FR		 3437static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
3438{
3439 if (tp->features & RTL_FEATURE_MSI) {
3440 pci_disable_msi(pdev);
3441 tp->features &= ~RTL_FEATURE_MSI;
3442 }
3443}
3444
c0e45c1c 3445static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
3446{
3447 struct mdio_ops *ops = &tp->mdio_ops;
3448
3449 switch (tp->mac_version) {
3450 case RTL_GIGA_MAC_VER_27:
3451 ops->write = r8168dp_1_mdio_write;
3452 ops->read = r8168dp_1_mdio_read;
3453 break;
e6de30d6 3454 case RTL_GIGA_MAC_VER_28:
4804b3b3 3455 case RTL_GIGA_MAC_VER_31:
e6de30d6 3456 ops->write = r8168dp_2_mdio_write;
3457 ops->read = r8168dp_2_mdio_read;
3458 break;
c0e45c1c 3459 default:
3460 ops->write = r8169_mdio_write;
3461 ops->read = r8169_mdio_read;
3462 break;
3463 }
3464}
3465
649b3b8c 3466static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
3467{
3468 void __iomem *ioaddr = tp->mmio_addr;
3469
3470 switch (tp->mac_version) {
3471 case RTL_GIGA_MAC_VER_29:
3472 case RTL_GIGA_MAC_VER_30:
3473 case RTL_GIGA_MAC_VER_32:
3474 case RTL_GIGA_MAC_VER_33:
3475 case RTL_GIGA_MAC_VER_34:
3476 RTL_W32(RxConfig, RTL_R32(RxConfig) |
3477 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3478 break;
3479 default:
3480 break;
3481 }
3482}
3483
3484static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
3485{
3486 if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
3487 return false;
3488
3489 rtl_writephy(tp, 0x1f, 0x0000);
3490 rtl_writephy(tp, MII_BMCR, 0x0000);
3491
3492 rtl_wol_suspend_quirk(tp);
3493
3494 return true;
3495}
3496
065c27c1 3497static void r810x_phy_power_down(struct rtl8169_private *tp)
3498{
3499 rtl_writephy(tp, 0x1f, 0x0000);
3500 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3501}
3502
3503static void r810x_phy_power_up(struct rtl8169_private *tp)
3504{
3505 rtl_writephy(tp, 0x1f, 0x0000);
3506 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3507}
3508
3509static void r810x_pll_power_down(struct rtl8169_private *tp)
3510{
649b3b8c 3511 if (rtl_wol_pll_power_down(tp))
065c27c1 3512 return;
065c27c1 3513
3514 r810x_phy_power_down(tp);
3515}
3516
3517static void r810x_pll_power_up(struct rtl8169_private *tp)
3518{
3519 r810x_phy_power_up(tp);
3520}
3521
3522static void r8168_phy_power_up(struct rtl8169_private *tp)
3523{
3524 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3525 switch (tp->mac_version) {
3526 case RTL_GIGA_MAC_VER_11:
3527 case RTL_GIGA_MAC_VER_12:
3528 case RTL_GIGA_MAC_VER_17:
3529 case RTL_GIGA_MAC_VER_18:
3530 case RTL_GIGA_MAC_VER_19:
3531 case RTL_GIGA_MAC_VER_20:
3532 case RTL_GIGA_MAC_VER_21:
3533 case RTL_GIGA_MAC_VER_22:
3534 case RTL_GIGA_MAC_VER_23:
3535 case RTL_GIGA_MAC_VER_24:
3536 case RTL_GIGA_MAC_VER_25:
3537 case RTL_GIGA_MAC_VER_26:
3538 case RTL_GIGA_MAC_VER_27:
3539 case RTL_GIGA_MAC_VER_28:
3540 case RTL_GIGA_MAC_VER_31:
3541 rtl_writephy(tp, 0x0e, 0x0000);
3542 break;
3543 default:
3544 break;
3545 }
065c27c1 3546 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3547}
3548
3549static void r8168_phy_power_down(struct rtl8169_private *tp)
3550{
3551 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3552 switch (tp->mac_version) {
3553 case RTL_GIGA_MAC_VER_32:
3554 case RTL_GIGA_MAC_VER_33:
3555 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
3556 break;
3557
3558 case RTL_GIGA_MAC_VER_11:
3559 case RTL_GIGA_MAC_VER_12:
3560 case RTL_GIGA_MAC_VER_17:
3561 case RTL_GIGA_MAC_VER_18:
3562 case RTL_GIGA_MAC_VER_19:
3563 case RTL_GIGA_MAC_VER_20:
3564 case RTL_GIGA_MAC_VER_21:
3565 case RTL_GIGA_MAC_VER_22:
3566 case RTL_GIGA_MAC_VER_23:
3567 case RTL_GIGA_MAC_VER_24:
3568 case RTL_GIGA_MAC_VER_25:
3569 case RTL_GIGA_MAC_VER_26:
3570 case RTL_GIGA_MAC_VER_27:
3571 case RTL_GIGA_MAC_VER_28:
3572 case RTL_GIGA_MAC_VER_31:
3573 rtl_writephy(tp, 0x0e, 0x0200);
3574 default:
3575 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3576 break;
3577 }
065c27c1 3578}
3579
3580static void r8168_pll_power_down(struct rtl8169_private *tp)
3581{
3582 void __iomem *ioaddr = tp->mmio_addr;
3583
cecb5fd7
FR		 3584 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3585 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3586 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
4804b3b3 3587 r8168dp_check_dash(tp)) {
065c27c1 3588 return;
5d2e1957 3589 }
065c27c1 3590
cecb5fd7
FR		 3591 if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
3592 tp->mac_version == RTL_GIGA_MAC_VER_24) &&
065c27c1 3593 (RTL_R16(CPlusCmd) & ASF)) {
3594 return;
3595 }
3596
01dc7fec 3597 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3598 tp->mac_version == RTL_GIGA_MAC_VER_33)
3599 rtl_ephy_write(ioaddr, 0x19, 0xff64);
3600
649b3b8c 3601 if (rtl_wol_pll_power_down(tp))
065c27c1 3602 return;
065c27c1 3603
3604 r8168_phy_power_down(tp);
3605
3606 switch (tp->mac_version) {
3607 case RTL_GIGA_MAC_VER_25:
3608 case RTL_GIGA_MAC_VER_26:
5d2e1957
HW		 3609 case RTL_GIGA_MAC_VER_27:
3610 case RTL_GIGA_MAC_VER_28:
4804b3b3 3611 case RTL_GIGA_MAC_VER_31:
01dc7fec 3612 case RTL_GIGA_MAC_VER_32:
3613 case RTL_GIGA_MAC_VER_33:
065c27c1 3614 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3615 break;
3616 }
3617}
3618
3619static void r8168_pll_power_up(struct rtl8169_private *tp)
3620{
3621 void __iomem *ioaddr = tp->mmio_addr;
3622
cecb5fd7
FR		 3623 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3624 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3625 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
4804b3b3 3626 r8168dp_check_dash(tp)) {
065c27c1 3627 return;
5d2e1957 3628 }
065c27c1 3629
3630 switch (tp->mac_version) {
3631 case RTL_GIGA_MAC_VER_25:
3632 case RTL_GIGA_MAC_VER_26:
5d2e1957
HW		 3633 case RTL_GIGA_MAC_VER_27:
3634 case RTL_GIGA_MAC_VER_28:
4804b3b3 3635 case RTL_GIGA_MAC_VER_31:
01dc7fec 3636 case RTL_GIGA_MAC_VER_32:
3637 case RTL_GIGA_MAC_VER_33:
065c27c1 3638 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3639 break;
3640 }
3641
3642 r8168_phy_power_up(tp);
3643}
3644
d58d46b5
FR		 3645static void rtl_generic_op(struct rtl8169_private *tp,
3646 void (*op)(struct rtl8169_private *))
065c27c1 3647{
3648 if (op)
3649 op(tp);
3650}
3651
3652static void rtl_pll_power_down(struct rtl8169_private *tp)
3653{
d58d46b5 3654 rtl_generic_op(tp, tp->pll_power_ops.down);
065c27c1 3655}
3656
3657static void rtl_pll_power_up(struct rtl8169_private *tp)
3658{
d58d46b5 3659 rtl_generic_op(tp, tp->pll_power_ops.up);
065c27c1 3660}
3661
3662static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
3663{
3664 struct pll_power_ops *ops = &tp->pll_power_ops;
3665
3666 switch (tp->mac_version) {
3667 case RTL_GIGA_MAC_VER_07:
3668 case RTL_GIGA_MAC_VER_08:
3669 case RTL_GIGA_MAC_VER_09:
3670 case RTL_GIGA_MAC_VER_10:
3671 case RTL_GIGA_MAC_VER_16:
5a5e4443
HW		 3672 case RTL_GIGA_MAC_VER_29:
3673 case RTL_GIGA_MAC_VER_30:
065c27c1 3674 ops->down = r810x_pll_power_down;
3675 ops->up = r810x_pll_power_up;
3676 break;
3677
3678 case RTL_GIGA_MAC_VER_11:
3679 case RTL_GIGA_MAC_VER_12:
3680 case RTL_GIGA_MAC_VER_17:
3681 case RTL_GIGA_MAC_VER_18:
3682 case RTL_GIGA_MAC_VER_19:
3683 case RTL_GIGA_MAC_VER_20:
3684 case RTL_GIGA_MAC_VER_21:
3685 case RTL_GIGA_MAC_VER_22:
3686 case RTL_GIGA_MAC_VER_23:
3687 case RTL_GIGA_MAC_VER_24:
3688 case RTL_GIGA_MAC_VER_25:
3689 case RTL_GIGA_MAC_VER_26:
3690 case RTL_GIGA_MAC_VER_27:
e6de30d6 3691 case RTL_GIGA_MAC_VER_28:
4804b3b3 3692 case RTL_GIGA_MAC_VER_31:
01dc7fec 3693 case RTL_GIGA_MAC_VER_32:
3694 case RTL_GIGA_MAC_VER_33:
70090424 3695 case RTL_GIGA_MAC_VER_34:
c2218925
HW		 3696 case RTL_GIGA_MAC_VER_35:
3697 case RTL_GIGA_MAC_VER_36:
065c27c1 3698 ops->down = r8168_pll_power_down;
3699 ops->up = r8168_pll_power_up;
3700 break;
3701
3702 default:
3703 ops->down = NULL;
3704 ops->up = NULL;
3705 break;
3706 }
3707}
3708
e542a226
HW		 3709static void rtl_init_rxcfg(struct rtl8169_private *tp)
3710{
3711 void __iomem *ioaddr = tp->mmio_addr;
3712
3713 switch (tp->mac_version) {
3714 case RTL_GIGA_MAC_VER_01:
3715 case RTL_GIGA_MAC_VER_02:
3716 case RTL_GIGA_MAC_VER_03:
3717 case RTL_GIGA_MAC_VER_04:
3718 case RTL_GIGA_MAC_VER_05:
3719 case RTL_GIGA_MAC_VER_06:
3720 case RTL_GIGA_MAC_VER_10:
3721 case RTL_GIGA_MAC_VER_11:
3722 case RTL_GIGA_MAC_VER_12:
3723 case RTL_GIGA_MAC_VER_13:
3724 case RTL_GIGA_MAC_VER_14:
3725 case RTL_GIGA_MAC_VER_15:
3726 case RTL_GIGA_MAC_VER_16:
3727 case RTL_GIGA_MAC_VER_17:
3728 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
3729 break;
3730 case RTL_GIGA_MAC_VER_18:
3731 case RTL_GIGA_MAC_VER_19:
3732 case RTL_GIGA_MAC_VER_20:
3733 case RTL_GIGA_MAC_VER_21:
3734 case RTL_GIGA_MAC_VER_22:
3735 case RTL_GIGA_MAC_VER_23:
3736 case RTL_GIGA_MAC_VER_24:
3737 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
3738 break;
3739 default:
3740 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
3741 break;
3742 }
3743}
3744
92fc43b4
HW		 3745static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
3746{
3747 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
3748}
3749
d58d46b5
FR		 3750static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
3751{
9c5028e9 3752 void __iomem *ioaddr = tp->mmio_addr;
3753
3754 RTL_W8(Cfg9346, Cfg9346_Unlock);
d58d46b5 3755 rtl_generic_op(tp, tp->jumbo_ops.enable);
9c5028e9 3756 RTL_W8(Cfg9346, Cfg9346_Lock);
d58d46b5
FR		 3757}
3758
3759static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
3760{
9c5028e9 3761 void __iomem *ioaddr = tp->mmio_addr;
3762
3763 RTL_W8(Cfg9346, Cfg9346_Unlock);
d58d46b5 3764 rtl_generic_op(tp, tp->jumbo_ops.disable);
9c5028e9 3765 RTL_W8(Cfg9346, Cfg9346_Lock);
d58d46b5
FR		 3766}
3767
3768static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
3769{
3770 void __iomem *ioaddr = tp->mmio_addr;
3771
3772 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3773 RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
3774 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
3775}
3776
3777static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
3778{
3779 void __iomem *ioaddr = tp->mmio_addr;
3780
3781 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3782 RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
3783 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
3784}
3785
3786static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
3787{
3788 void __iomem *ioaddr = tp->mmio_addr;
3789
3790 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3791}
3792
3793static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
3794{
3795 void __iomem *ioaddr = tp->mmio_addr;
3796
3797 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3798}
3799
3800static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
3801{
3802 void __iomem *ioaddr = tp->mmio_addr;
d58d46b5
FR		 3803
3804 RTL_W8(MaxTxPacketSize, 0x3f);
3805 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3806 RTL_W8(Config4, RTL_R8(Config4) | 0x01);
4512ff9f 3807 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
d58d46b5
FR		 3808}
3809
3810static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
3811{
3812 void __iomem *ioaddr = tp->mmio_addr;
d58d46b5
FR		 3813
3814 RTL_W8(MaxTxPacketSize, 0x0c);
3815 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3816 RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
4512ff9f 3817 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
d58d46b5
FR		 3818}
3819
3820static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
3821{
3822 rtl_tx_performance_tweak(tp->pci_dev,
3823 (0x2 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3824}
3825
3826static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
3827{
3828 rtl_tx_performance_tweak(tp->pci_dev,
3829 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3830}
3831
3832static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
3833{
3834 void __iomem *ioaddr = tp->mmio_addr;
3835
3836 r8168b_0_hw_jumbo_enable(tp);
3837
3838 RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
3839}
3840
3841static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
3842{
3843 void __iomem *ioaddr = tp->mmio_addr;
3844
3845 r8168b_0_hw_jumbo_disable(tp);
3846
3847 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
3848}
3849
3850static void __devinit rtl_init_jumbo_ops(struct rtl8169_private *tp)
3851{
3852 struct jumbo_ops *ops = &tp->jumbo_ops;
3853
3854 switch (tp->mac_version) {
3855 case RTL_GIGA_MAC_VER_11:
3856 ops->disable = r8168b_0_hw_jumbo_disable;
3857 ops->enable = r8168b_0_hw_jumbo_enable;
3858 break;
3859 case RTL_GIGA_MAC_VER_12:
3860 case RTL_GIGA_MAC_VER_17:
3861 ops->disable = r8168b_1_hw_jumbo_disable;
3862 ops->enable = r8168b_1_hw_jumbo_enable;
3863 break;
3864 case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
3865 case RTL_GIGA_MAC_VER_19:
3866 case RTL_GIGA_MAC_VER_20:
3867 case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
3868 case RTL_GIGA_MAC_VER_22:
3869 case RTL_GIGA_MAC_VER_23:
3870 case RTL_GIGA_MAC_VER_24:
3871 case RTL_GIGA_MAC_VER_25:
3872 case RTL_GIGA_MAC_VER_26:
3873 ops->disable = r8168c_hw_jumbo_disable;
3874 ops->enable = r8168c_hw_jumbo_enable;
3875 break;
3876 case RTL_GIGA_MAC_VER_27:
3877 case RTL_GIGA_MAC_VER_28:
3878 ops->disable = r8168dp_hw_jumbo_disable;
3879 ops->enable = r8168dp_hw_jumbo_enable;
3880 break;
3881 case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
3882 case RTL_GIGA_MAC_VER_32:
3883 case RTL_GIGA_MAC_VER_33:
3884 case RTL_GIGA_MAC_VER_34:
3885 ops->disable = r8168e_hw_jumbo_disable;
3886 ops->enable = r8168e_hw_jumbo_enable;
3887 break;
3888
3889 /*
3890 * No action needed for jumbo frames with 8169.
3891 * No jumbo for 810x at all.
3892 */
3893 default:
3894 ops->disable = NULL;
3895 ops->enable = NULL;
3896 break;
3897 }
3898}
3899
6f43adc8
FR		 3900static void rtl_hw_reset(struct rtl8169_private *tp)
3901{
3902 void __iomem *ioaddr = tp->mmio_addr;
3903 int i;
3904
3905 /* Soft reset the chip. */
3906 RTL_W8(ChipCmd, CmdReset);
3907
3908 /* Check that the chip has finished the reset. */
3909 for (i = 0; i < 100; i++) {
3910 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3911 break;
92fc43b4 3912 udelay(100);
6f43adc8
FR		 3913 }
3914}
3915
b6ffd97f 3916static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
953a12cc 3917{
b6ffd97f
FR		 3918 struct rtl_fw *rtl_fw;
3919 const char *name;
3920 int rc = -ENOMEM;
953a12cc 3921
b6ffd97f
FR		 3922 name = rtl_lookup_firmware_name(tp);
3923 if (!name)
3924 goto out_no_firmware;
953a12cc 3925
b6ffd97f
FR		 3926 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
3927 if (!rtl_fw)
3928 goto err_warn;
31bd204f 3929
b6ffd97f
FR		 3930 rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
3931 if (rc < 0)
3932 goto err_free;
3933
fd112f2e
FR		 3934 rc = rtl_check_firmware(tp, rtl_fw);
3935 if (rc < 0)
3936 goto err_release_firmware;
3937
b6ffd97f
FR		 3938 tp->rtl_fw = rtl_fw;
3939out:
3940 return;
3941
fd112f2e
FR		 3942err_release_firmware:
3943 release_firmware(rtl_fw->fw);
b6ffd97f
FR		 3944err_free:
3945 kfree(rtl_fw);
3946err_warn:
3947 netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
3948 name, rc);
3949out_no_firmware:
3950 tp->rtl_fw = NULL;
3951 goto out;
3952}
3953
3954static void rtl_request_firmware(struct rtl8169_private *tp)
3955{
3956 if (IS_ERR(tp->rtl_fw))
3957 rtl_request_uncached_firmware(tp);
953a12cc
FR		 3958}
3959
92fc43b4
HW		 3960static void rtl_rx_close(struct rtl8169_private *tp)
3961{
3962 void __iomem *ioaddr = tp->mmio_addr;
92fc43b4 3963
1687b566 3964 RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
92fc43b4
HW		 3965}
3966
e6de30d6 3967static void rtl8169_hw_reset(struct rtl8169_private *tp)
1da177e4 3968{
e6de30d6 3969 void __iomem *ioaddr = tp->mmio_addr;
3970
1da177e4 3971 /* Disable interrupts */
811fd301 3972 rtl8169_irq_mask_and_ack(tp);
1da177e4 3973
92fc43b4
HW		 3974 rtl_rx_close(tp);
3975
5d2e1957 3976 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4804b3b3 3977 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3978 tp->mac_version == RTL_GIGA_MAC_VER_31) {
e6de30d6 3979 while (RTL_R8(TxPoll) & NPQ)
3980 udelay(20);
c2218925
HW		 3981 } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
3982 tp->mac_version == RTL_GIGA_MAC_VER_35 ||
3983 tp->mac_version == RTL_GIGA_MAC_VER_36) {
c2b0c1e7 3984 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
70090424
HW		 3985 while (!(RTL_R32(TxConfig) & TXCFG_EMPTY))
3986 udelay(100);
92fc43b4
HW		 3987 } else {
3988 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
3989 udelay(100);
e6de30d6 3990 }
3991
92fc43b4 3992 rtl_hw_reset(tp);
1da177e4
LT		 3993}
3994
7f796d83 3995static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
9cb427b6
FR		 3996{
3997 void __iomem *ioaddr = tp->mmio_addr;
9cb427b6
FR		 3998
3999 /* Set DMA burst size and Interframe Gap Time */
4000 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4001 (InterFrameGap << TxInterFrameGapShift));
4002}
4003
07ce4064 4004static void rtl_hw_start(struct net_device *dev)
1da177e4
LT		 4005{
4006 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 4007
07ce4064
FR		 4008 tp->hw_start(dev);
4009
da78dbff 4010 rtl_irq_enable_all(tp);
07ce4064
FR		 4011}
4012
7f796d83
FR		 4013static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
4014 void __iomem *ioaddr)
4015{
4016 /*
4017 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4018 * register to be written before TxDescAddrLow to work.
4019 * Switching from MMIO to I/O access fixes the issue as well.
4020 */
4021 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
284901a9 4022 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
7f796d83 4023 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
284901a9 4024 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
7f796d83
FR		 4025}
4026
4027static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
4028{
4029 u16 cmd;
4030
4031 cmd = RTL_R16(CPlusCmd);
4032 RTL_W16(CPlusCmd, cmd);
4033 return cmd;
4034}
4035
fdd7b4c3 4036static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
7f796d83
FR		 4037{
4038 /* Low hurts. Let's disable the filtering. */
207d6e87 4039 RTL_W16(RxMaxSize, rx_buf_sz + 1);
7f796d83
FR		 4040}
4041
6dccd16b
FR		 4042static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
4043{
3744100e 4044 static const struct rtl_cfg2_info {
6dccd16b
FR		 4045 u32 mac_version;
4046 u32 clk;
4047 u32 val;
4048 } cfg2_info [] = {
4049 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
4050 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
4051 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
4052 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3744100e
FR		 4053 };
4054 const struct rtl_cfg2_info *p = cfg2_info;
6dccd16b
FR		 4055 unsigned int i;
4056 u32 clk;
4057
4058 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
cadf1855 4059 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
6dccd16b
FR		 4060 if ((p->mac_version == mac_version) && (p->clk == clk)) {
4061 RTL_W32(0x7c, p->val);
4062 break;
4063 }
4064 }
4065}
4066
e6b763ea
FR		 4067static void rtl_set_rx_mode(struct net_device *dev)
4068{
4069 struct rtl8169_private *tp = netdev_priv(dev);
4070 void __iomem *ioaddr = tp->mmio_addr;
4071 u32 mc_filter[2]; /* Multicast hash filter */
4072 int rx_mode;
4073 u32 tmp = 0;
4074
4075 if (dev->flags & IFF_PROMISC) {
4076 /* Unconditionally log net taps. */
4077 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4078 rx_mode =
4079 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4080 AcceptAllPhys;
4081 mc_filter[1] = mc_filter[0] = 0xffffffff;
4082 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4083 (dev->flags & IFF_ALLMULTI)) {
4084 /* Too many to filter perfectly -- accept all multicasts. */
4085 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4086 mc_filter[1] = mc_filter[0] = 0xffffffff;
4087 } else {
4088 struct netdev_hw_addr *ha;
4089
4090 rx_mode = AcceptBroadcast | AcceptMyPhys;
4091 mc_filter[1] = mc_filter[0] = 0;
4092 netdev_for_each_mc_addr(ha, dev) {
4093 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4094 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4095 rx_mode |= AcceptMulticast;
4096 }
4097 }
4098
4099 if (dev->features & NETIF_F_RXALL)
4100 rx_mode |= (AcceptErr | AcceptRunt);
4101
4102 tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
4103
4104 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4105 u32 data = mc_filter[0];
4106
4107 mc_filter[0] = swab32(mc_filter[1]);
4108 mc_filter[1] = swab32(data);
4109 }
4110
4111 RTL_W32(MAR0 + 4, mc_filter[1]);
4112 RTL_W32(MAR0 + 0, mc_filter[0]);
4113
4114 RTL_W32(RxConfig, tmp);
4115}
4116
07ce4064
FR		 4117static void rtl_hw_start_8169(struct net_device *dev)
4118{
4119 struct rtl8169_private *tp = netdev_priv(dev);
4120 void __iomem *ioaddr = tp->mmio_addr;
4121 struct pci_dev *pdev = tp->pci_dev;
07ce4064 4122
9cb427b6
FR		 4123 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
4124 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
4125 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
4126 }
4127
1da177e4 4128 RTL_W8(Cfg9346, Cfg9346_Unlock);
cecb5fd7
FR		 4129 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4130 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4131 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4132 tp->mac_version == RTL_GIGA_MAC_VER_04)
9cb427b6
FR		 4133 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4134
e542a226
HW		 4135 rtl_init_rxcfg(tp);
4136
f0298f81 4137 RTL_W8(EarlyTxThres, NoEarlyTx);
1da177e4 4138
6f0333b8 4139 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
1da177e4 4140
cecb5fd7
FR		 4141 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4142 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4143 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4144 tp->mac_version == RTL_GIGA_MAC_VER_04)
c946b304 4145 rtl_set_rx_tx_config_registers(tp);
1da177e4 4146
7f796d83 4147 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1da177e4 4148
cecb5fd7
FR		 4149 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4150 tp->mac_version == RTL_GIGA_MAC_VER_03) {
06fa7358 4151 dprintk("Set MAC Reg C+CR Offset 0xE0. "
1da177e4 4152 "Bit-3 and bit-14 MUST be 1\n");
bcf0bf90 4153 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 4154 }
4155
bcf0bf90
FR		 4156 RTL_W16(CPlusCmd, tp->cp_cmd);
4157
6dccd16b
FR		 4158 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
4159
1da177e4
LT		 4160 /*
4161 * Undocumented corner. Supposedly:
4162 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4163 */
4164 RTL_W16(IntrMitigate, 0x0000);
4165
7f796d83 4166 rtl_set_rx_tx_desc_registers(tp, ioaddr);
9cb427b6 4167
cecb5fd7
FR		 4168 if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
4169 tp->mac_version != RTL_GIGA_MAC_VER_02 &&
4170 tp->mac_version != RTL_GIGA_MAC_VER_03 &&
4171 tp->mac_version != RTL_GIGA_MAC_VER_04) {
c946b304
FR		 4172 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4173 rtl_set_rx_tx_config_registers(tp);
4174 }
4175
1da177e4 4176 RTL_W8(Cfg9346, Cfg9346_Lock);
b518fa8e
FR		 4177
4178 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4179 RTL_R8(IntrMask);
1da177e4
LT		 4180
4181 RTL_W32(RxMissed, 0);
4182
07ce4064 4183 rtl_set_rx_mode(dev);
1da177e4
LT		 4184
4185 /* no early-rx interrupts */
4186 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
07ce4064 4187}
1da177e4 4188
650e8d5d 4189static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits)
dacf8154
FR		 4190{
4191 u32 csi;
4192
4193 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
650e8d5d 4194 rtl_csi_write(ioaddr, 0x070c, csi | bits);
4195}
4196
e6de30d6 4197static void rtl_csi_access_enable_1(void __iomem *ioaddr)
4198{
4199 rtl_csi_access_enable(ioaddr, 0x17000000);
4200}
4201
650e8d5d 4202static void rtl_csi_access_enable_2(void __iomem *ioaddr)
4203{
4204 rtl_csi_access_enable(ioaddr, 0x27000000);
dacf8154
FR		 4205}
4206
4207struct ephy_info {
4208 unsigned int offset;
4209 u16 mask;
4210 u16 bits;
4211};
4212
350f7596 4213static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
dacf8154
FR		 4214{
4215 u16 w;
4216
4217 while (len-- > 0) {
4218 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
4219 rtl_ephy_write(ioaddr, e->offset, w);
4220 e++;
4221 }
4222}
4223
b726e493
FR		 4224static void rtl_disable_clock_request(struct pci_dev *pdev)
4225{
e44daade 4226 int cap = pci_pcie_cap(pdev);
b726e493
FR		 4227
4228 if (cap) {
4229 u16 ctl;
4230
4231 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4232 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
4233 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4234 }
4235}
4236
e6de30d6 4237static void rtl_enable_clock_request(struct pci_dev *pdev)
4238{
e44daade 4239 int cap = pci_pcie_cap(pdev);
e6de30d6 4240
4241 if (cap) {
4242 u16 ctl;
4243
4244 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4245 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
4246 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4247 }
4248}
4249
b726e493
FR		 4250#define R8168_CPCMD_QUIRK_MASK (\
4251 EnableBist | \
4252 Mac_dbgo_oe | \
4253 Force_half_dup | \
4254 Force_rxflow_en | \
4255 Force_txflow_en | \
4256 Cxpl_dbg_sel | \
4257 ASF | \
4258 PktCntrDisable | \
4259 Mac_dbgo_sel)
4260
219a1e9d
FR		 4261static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
4262{
b726e493
FR		 4263 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4264
4265 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4266
2e68ae44
FR		 4267 rtl_tx_performance_tweak(pdev,
4268 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
219a1e9d
FR		 4269}
4270
4271static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
4272{
4273 rtl_hw_start_8168bb(ioaddr, pdev);
b726e493 4274
f0298f81 4275 RTL_W8(MaxTxPacketSize, TxPacketMax);
b726e493
FR		 4276
4277 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
219a1e9d
FR		 4278}
4279
4280static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
4281{
b726e493
FR		 4282 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
4283
4284 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4285
219a1e9d 4286 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
b726e493
FR		 4287
4288 rtl_disable_clock_request(pdev);
4289
4290 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
219a1e9d
FR		 4291}
4292
ef3386f0 4293static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
219a1e9d 4294{
350f7596 4295 static const struct ephy_info e_info_8168cp[] = {
b726e493
FR		 4296 { 0x01, 0, 0x0001 },
4297 { 0x02, 0x0800, 0x1000 },
4298 { 0x03, 0, 0x0042 },
4299 { 0x06, 0x0080, 0x0000 },
4300 { 0x07, 0, 0x2000 }
4301 };
4302
650e8d5d 4303 rtl_csi_access_enable_2(ioaddr);
b726e493
FR		 4304
4305 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
4306
219a1e9d
FR		 4307 __rtl_hw_start_8168cp(ioaddr, pdev);
4308}
4309
ef3386f0
FR		 4310static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
4311{
650e8d5d 4312 rtl_csi_access_enable_2(ioaddr);
ef3386f0
FR		 4313
4314 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4315
4316 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4317
4318 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4319}
4320
7f3e3d3a
FR		 4321static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
4322{
650e8d5d 4323 rtl_csi_access_enable_2(ioaddr);
7f3e3d3a
FR		 4324
4325 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4326
4327 /* Magic. */
4328 RTL_W8(DBG_REG, 0x20);
4329
f0298f81 4330 RTL_W8(MaxTxPacketSize, TxPacketMax);
7f3e3d3a
FR		 4331
4332 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4333
4334 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4335}
4336
219a1e9d
FR		 4337static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
4338{
350f7596 4339 static const struct ephy_info e_info_8168c_1[] = {
b726e493
FR		 4340 { 0x02, 0x0800, 0x1000 },
4341 { 0x03, 0, 0x0002 },
4342 { 0x06, 0x0080, 0x0000 }
4343 };
4344
650e8d5d 4345 rtl_csi_access_enable_2(ioaddr);
b726e493
FR		 4346
4347 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4348
4349 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
4350
219a1e9d
FR		 4351 __rtl_hw_start_8168cp(ioaddr, pdev);
4352}
4353
4354static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
4355{
350f7596 4356 static const struct ephy_info e_info_8168c_2[] = {
b726e493
FR		 4357 { 0x01, 0, 0x0001 },
4358 { 0x03, 0x0400, 0x0220 }
4359 };
4360
650e8d5d 4361 rtl_csi_access_enable_2(ioaddr);
b726e493
FR		 4362
4363 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
4364
219a1e9d
FR		 4365 __rtl_hw_start_8168cp(ioaddr, pdev);
4366}
4367
197ff761
FR		 4368static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
4369{
4370 rtl_hw_start_8168c_2(ioaddr, pdev);
4371}
4372
6fb07058
FR		 4373static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
4374{
650e8d5d 4375 rtl_csi_access_enable_2(ioaddr);
6fb07058
FR		 4376
4377 __rtl_hw_start_8168cp(ioaddr, pdev);
4378}
4379
5b538df9
FR		 4380static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
4381{
650e8d5d 4382 rtl_csi_access_enable_2(ioaddr);
5b538df9
FR		 4383
4384 rtl_disable_clock_request(pdev);
4385
f0298f81 4386 RTL_W8(MaxTxPacketSize, TxPacketMax);
5b538df9
FR		 4387
4388 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4389
4390 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4391}
4392
4804b3b3 4393static void rtl_hw_start_8168dp(void __iomem *ioaddr, struct pci_dev *pdev)
4394{
4395 rtl_csi_access_enable_1(ioaddr);
4396
4397 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4398
4399 RTL_W8(MaxTxPacketSize, TxPacketMax);
4400
4401 rtl_disable_clock_request(pdev);
4402}
4403
e6de30d6 4404static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
4405{
4406 static const struct ephy_info e_info_8168d_4[] = {
4407 { 0x0b, ~0, 0x48 },
4408 { 0x19, 0x20, 0x50 },
4409 { 0x0c, ~0, 0x20 }
4410 };
4411 int i;
4412
4413 rtl_csi_access_enable_1(ioaddr);
4414
4415 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4416
4417 RTL_W8(MaxTxPacketSize, TxPacketMax);
4418
4419 for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
4420 const struct ephy_info *e = e_info_8168d_4 + i;
4421 u16 w;
4422
4423 w = rtl_ephy_read(ioaddr, e->offset);
4424 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
4425 }
4426
4427 rtl_enable_clock_request(pdev);
4428}
4429
70090424 4430static void rtl_hw_start_8168e_1(void __iomem *ioaddr, struct pci_dev *pdev)
01dc7fec 4431{
70090424 4432 static const struct ephy_info e_info_8168e_1[] = {
01dc7fec 4433 { 0x00, 0x0200, 0x0100 },
4434 { 0x00, 0x0000, 0x0004 },
4435 { 0x06, 0x0002, 0x0001 },
4436 { 0x06, 0x0000, 0x0030 },
4437 { 0x07, 0x0000, 0x2000 },
4438 { 0x00, 0x0000, 0x0020 },
4439 { 0x03, 0x5800, 0x2000 },
4440 { 0x03, 0x0000, 0x0001 },
4441 { 0x01, 0x0800, 0x1000 },
4442 { 0x07, 0x0000, 0x4000 },
4443 { 0x1e, 0x0000, 0x2000 },
4444 { 0x19, 0xffff, 0xfe6c },
4445 { 0x0a, 0x0000, 0x0040 }
4446 };
4447
4448 rtl_csi_access_enable_2(ioaddr);
4449
70090424 4450 rtl_ephy_init(ioaddr, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
01dc7fec 4451
4452 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4453
4454 RTL_W8(MaxTxPacketSize, TxPacketMax);
4455
4456 rtl_disable_clock_request(pdev);
4457
4458 /* Reset tx FIFO pointer */
cecb5fd7
FR		 4459 RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
4460 RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
01dc7fec 4461
cecb5fd7 4462 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
01dc7fec 4463}
4464
70090424
HW		 4465static void rtl_hw_start_8168e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4466{
4467 static const struct ephy_info e_info_8168e_2[] = {
4468 { 0x09, 0x0000, 0x0080 },
4469 { 0x19, 0x0000, 0x0224 }
4470 };
4471
4472 rtl_csi_access_enable_1(ioaddr);
4473
4474 rtl_ephy_init(ioaddr, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
4475
4476 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4477
4478 rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4479 rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4480 rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
4481 rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
4482 rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
4483 rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
4484 rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4485 rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00,
4486 ERIAR_EXGMAC);
4487
3090bd9a 4488 RTL_W8(MaxTxPacketSize, EarlySize);
70090424
HW		 4489
4490 rtl_disable_clock_request(pdev);
4491
4492 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
4493 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
4494
4495 /* Adjust EEE LED frequency */
4496 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
4497
4498 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4499 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4500 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4501}
4502
c2218925
HW		 4503static void rtl_hw_start_8168f_1(void __iomem *ioaddr, struct pci_dev *pdev)
4504{
4505 static const struct ephy_info e_info_8168f_1[] = {
4506 { 0x06, 0x00c0, 0x0020 },
4507 { 0x08, 0x0001, 0x0002 },
4508 { 0x09, 0x0000, 0x0080 },
4509 { 0x19, 0x0000, 0x0224 }
4510 };
4511
4512 rtl_csi_access_enable_1(ioaddr);
4513
4514 rtl_ephy_init(ioaddr, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
4515
4516 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4517
4518 rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4519 rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4520 rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
4521 rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
4522 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
4523 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
4524 rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4525 rtl_w1w0_eri(ioaddr, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4526 rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
4527 rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
4528 rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00,
4529 ERIAR_EXGMAC);
4530
4531 RTL_W8(MaxTxPacketSize, EarlySize);
4532
4533 rtl_disable_clock_request(pdev);
4534
4535 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
4536 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
4537
4538 /* Adjust EEE LED frequency */
4539 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
4540
4541 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4542 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4543 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4544}
4545
07ce4064
FR		 4546static void rtl_hw_start_8168(struct net_device *dev)
4547{
2dd99530
FR		 4548 struct rtl8169_private *tp = netdev_priv(dev);
4549 void __iomem *ioaddr = tp->mmio_addr;
0e485150 4550 struct pci_dev *pdev = tp->pci_dev;
2dd99530
FR		 4551
4552 RTL_W8(Cfg9346, Cfg9346_Unlock);
4553
f0298f81 4554 RTL_W8(MaxTxPacketSize, TxPacketMax);
2dd99530 4555
6f0333b8 4556 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
2dd99530 4557
0e485150 4558 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2dd99530
FR		 4559
4560 RTL_W16(CPlusCmd, tp->cp_cmd);
4561
0e485150 4562 RTL_W16(IntrMitigate, 0x5151);
2dd99530 4563
0e485150 4564 /* Work around for RxFIFO overflow. */
811fd301 4565 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
da78dbff
FR		 4566 tp->event_slow |= RxFIFOOver | PCSTimeout;
4567 tp->event_slow &= ~RxOverflow;
0e485150
FR		 4568 }
4569
4570 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2dd99530 4571
b8363901
FR		 4572 rtl_set_rx_mode(dev);
4573
4574 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4575 (InterFrameGap << TxInterFrameGapShift));
2dd99530
FR		 4576
4577 RTL_R8(IntrMask);
4578
219a1e9d
FR		 4579 switch (tp->mac_version) {
4580 case RTL_GIGA_MAC_VER_11:
4581 rtl_hw_start_8168bb(ioaddr, pdev);
4804b3b3 4582 break;
219a1e9d
FR		 4583
4584 case RTL_GIGA_MAC_VER_12:
4585 case RTL_GIGA_MAC_VER_17:
4586 rtl_hw_start_8168bef(ioaddr, pdev);
4804b3b3 4587 break;
219a1e9d
FR		 4588
4589 case RTL_GIGA_MAC_VER_18:
ef3386f0 4590 rtl_hw_start_8168cp_1(ioaddr, pdev);
4804b3b3 4591 break;
219a1e9d
FR		 4592
4593 case RTL_GIGA_MAC_VER_19:
4594 rtl_hw_start_8168c_1(ioaddr, pdev);
4804b3b3 4595 break;
219a1e9d
FR		 4596
4597 case RTL_GIGA_MAC_VER_20:
4598 rtl_hw_start_8168c_2(ioaddr, pdev);
4804b3b3 4599 break;
219a1e9d 4600
197ff761
FR		 4601 case RTL_GIGA_MAC_VER_21:
4602 rtl_hw_start_8168c_3(ioaddr, pdev);
4804b3b3 4603 break;
197ff761 4604
6fb07058
FR		 4605 case RTL_GIGA_MAC_VER_22:
4606 rtl_hw_start_8168c_4(ioaddr, pdev);
4804b3b3 4607 break;
6fb07058 4608
ef3386f0
FR		 4609 case RTL_GIGA_MAC_VER_23:
4610 rtl_hw_start_8168cp_2(ioaddr, pdev);
4804b3b3 4611 break;
ef3386f0 4612
7f3e3d3a
FR		 4613 case RTL_GIGA_MAC_VER_24:
4614 rtl_hw_start_8168cp_3(ioaddr, pdev);
4804b3b3 4615 break;
7f3e3d3a 4616
5b538df9 4617 case RTL_GIGA_MAC_VER_25:
daf9df6d 4618 case RTL_GIGA_MAC_VER_26:
4619 case RTL_GIGA_MAC_VER_27:
5b538df9 4620 rtl_hw_start_8168d(ioaddr, pdev);
4804b3b3 4621 break;
5b538df9 4622
e6de30d6 4623 case RTL_GIGA_MAC_VER_28:
4624 rtl_hw_start_8168d_4(ioaddr, pdev);
4804b3b3 4625 break;
cecb5fd7 4626
4804b3b3 4627 case RTL_GIGA_MAC_VER_31:
4628 rtl_hw_start_8168dp(ioaddr, pdev);
4629 break;
4630
01dc7fec 4631 case RTL_GIGA_MAC_VER_32:
4632 case RTL_GIGA_MAC_VER_33:
70090424
HW		 4633 rtl_hw_start_8168e_1(ioaddr, pdev);
4634 break;
4635 case RTL_GIGA_MAC_VER_34:
4636 rtl_hw_start_8168e_2(ioaddr, pdev);
01dc7fec 4637 break;
e6de30d6 4638
c2218925
HW		 4639 case RTL_GIGA_MAC_VER_35:
4640 case RTL_GIGA_MAC_VER_36:
4641 rtl_hw_start_8168f_1(ioaddr, pdev);
4642 break;
4643
219a1e9d
FR		 4644 default:
4645 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
4646 dev->name, tp->mac_version);
4804b3b3 4647 break;
219a1e9d 4648 }
2dd99530 4649
0e485150
FR		 4650 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4651
b8363901
FR		 4652 RTL_W8(Cfg9346, Cfg9346_Lock);
4653
2dd99530 4654 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
07ce4064 4655}
1da177e4 4656
2857ffb7
FR		 4657#define R810X_CPCMD_QUIRK_MASK (\
4658 EnableBist | \
4659 Mac_dbgo_oe | \
4660 Force_half_dup | \
5edcc537 4661 Force_rxflow_en | \
2857ffb7
FR		 4662 Force_txflow_en | \
4663 Cxpl_dbg_sel | \
4664 ASF | \
4665 PktCntrDisable | \
d24e9aaf 4666 Mac_dbgo_sel)
2857ffb7
FR		 4667
4668static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4669{
350f7596 4670 static const struct ephy_info e_info_8102e_1[] = {
2857ffb7
FR		 4671 { 0x01, 0, 0x6e65 },
4672 { 0x02, 0, 0x091f },
4673 { 0x03, 0, 0xc2f9 },
4674 { 0x06, 0, 0xafb5 },
4675 { 0x07, 0, 0x0e00 },
4676 { 0x19, 0, 0xec80 },
4677 { 0x01, 0, 0x2e65 },
4678 { 0x01, 0, 0x6e65 }
4679 };
4680 u8 cfg1;
4681
650e8d5d 4682 rtl_csi_access_enable_2(ioaddr);
2857ffb7
FR		 4683
4684 RTL_W8(DBG_REG, FIX_NAK_1);
4685
4686 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4687
4688 RTL_W8(Config1,
4689 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
4690 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4691
4692 cfg1 = RTL_R8(Config1);
4693 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
4694 RTL_W8(Config1, cfg1 & ~LEDS0);
4695
2857ffb7
FR		 4696 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
4697}
4698
4699static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4700{
650e8d5d 4701 rtl_csi_access_enable_2(ioaddr);
2857ffb7
FR		 4702
4703 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4704
4705 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
4706 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2857ffb7
FR		 4707}
4708
4709static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
4710{
4711 rtl_hw_start_8102e_2(ioaddr, pdev);
4712
4713 rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
4714}
4715
5a5e4443
HW		 4716static void rtl_hw_start_8105e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4717{
4718 static const struct ephy_info e_info_8105e_1[] = {
4719 { 0x07, 0, 0x4000 },
4720 { 0x19, 0, 0x0200 },
4721 { 0x19, 0, 0x0020 },
4722 { 0x1e, 0, 0x2000 },
4723 { 0x03, 0, 0x0001 },
4724 { 0x19, 0, 0x0100 },
4725 { 0x19, 0, 0x0004 },
4726 { 0x0a, 0, 0x0020 }
4727 };
4728
cecb5fd7 4729 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5a5e4443
HW		 4730 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
4731
cecb5fd7 4732 /* Disable Early Tally Counter */
5a5e4443
HW		 4733 RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
4734
4735 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
4f6b00e5 4736 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5a5e4443
HW		 4737
4738 rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
4739}
4740
4741static void rtl_hw_start_8105e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4742{
4743 rtl_hw_start_8105e_1(ioaddr, pdev);
4744 rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000);
4745}
4746
07ce4064
FR		 4747static void rtl_hw_start_8101(struct net_device *dev)
4748{
cdf1a608
FR		 4749 struct rtl8169_private *tp = netdev_priv(dev);
4750 void __iomem *ioaddr = tp->mmio_addr;
4751 struct pci_dev *pdev = tp->pci_dev;
4752
da78dbff
FR		 4753 if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
4754 tp->event_slow &= ~RxFIFOOver;
811fd301 4755
cecb5fd7
FR		 4756 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
4757 tp->mac_version == RTL_GIGA_MAC_VER_16) {
e44daade 4758 int cap = pci_pcie_cap(pdev);
9c14ceaf
FR		 4759
4760 if (cap) {
4761 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
4762 PCI_EXP_DEVCTL_NOSNOOP_EN);
4763 }
cdf1a608
FR		 4764 }
4765
d24e9aaf
HW		 4766 RTL_W8(Cfg9346, Cfg9346_Unlock);
4767
2857ffb7
FR		 4768 switch (tp->mac_version) {
4769 case RTL_GIGA_MAC_VER_07:
4770 rtl_hw_start_8102e_1(ioaddr, pdev);
4771 break;
4772
4773 case RTL_GIGA_MAC_VER_08:
4774 rtl_hw_start_8102e_3(ioaddr, pdev);
4775 break;
4776
4777 case RTL_GIGA_MAC_VER_09:
4778 rtl_hw_start_8102e_2(ioaddr, pdev);
4779 break;
5a5e4443
HW		 4780
4781 case RTL_GIGA_MAC_VER_29:
4782 rtl_hw_start_8105e_1(ioaddr, pdev);
4783 break;
4784 case RTL_GIGA_MAC_VER_30:
4785 rtl_hw_start_8105e_2(ioaddr, pdev);
4786 break;
cdf1a608
FR		 4787 }
4788
d24e9aaf 4789 RTL_W8(Cfg9346, Cfg9346_Lock);
cdf1a608 4790
f0298f81 4791 RTL_W8(MaxTxPacketSize, TxPacketMax);
cdf1a608 4792
6f0333b8 4793 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
cdf1a608 4794
d24e9aaf 4795 tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
cdf1a608
FR		 4796 RTL_W16(CPlusCmd, tp->cp_cmd);
4797
4798 RTL_W16(IntrMitigate, 0x0000);
4799
4800 rtl_set_rx_tx_desc_registers(tp, ioaddr);
4801
4802 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4803 rtl_set_rx_tx_config_registers(tp);
4804
cdf1a608
FR		 4805 RTL_R8(IntrMask);
4806
cdf1a608
FR		 4807 rtl_set_rx_mode(dev);
4808
4809 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
1da177e4
LT		 4810}
4811
4812static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
4813{
d58d46b5
FR		 4814 struct rtl8169_private *tp = netdev_priv(dev);
4815
4816 if (new_mtu < ETH_ZLEN ||
4817 new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max)
1da177e4
LT		 4818 return -EINVAL;
4819
d58d46b5
FR		 4820 if (new_mtu > ETH_DATA_LEN)
4821 rtl_hw_jumbo_enable(tp);
4822 else
4823 rtl_hw_jumbo_disable(tp);
4824
1da177e4 4825 dev->mtu = new_mtu;
350fb32a
MM		 4826 netdev_update_features(dev);
4827
323bb685 4828 return 0;
1da177e4
LT		 4829}
4830
4831static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
4832{
95e0918d 4833 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
1da177e4
LT		 4834 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
4835}
4836
6f0333b8
ED		 4837static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
4838 void **data_buff, struct RxDesc *desc)
1da177e4 4839{
48addcc9 4840 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
231aee63 4841 DMA_FROM_DEVICE);
48addcc9 4842
6f0333b8
ED		 4843 kfree(*data_buff);
4844 *data_buff = NULL;
1da177e4
LT		 4845 rtl8169_make_unusable_by_asic(desc);
4846}
4847
4848static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
4849{
4850 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
4851
4852 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
4853}
4854
4855static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
4856 u32 rx_buf_sz)
4857{
4858 desc->addr = cpu_to_le64(mapping);
4859 wmb();
4860 rtl8169_mark_to_asic(desc, rx_buf_sz);
4861}
4862
6f0333b8
ED		 4863static inline void *rtl8169_align(void *data)
4864{
4865 return (void *)ALIGN((long)data, 16);
4866}
4867
0ecbe1ca
SG		 4868static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
4869 struct RxDesc *desc)
1da177e4 4870{
6f0333b8 4871 void *data;
1da177e4 4872 dma_addr_t mapping;
48addcc9 4873 struct device *d = &tp->pci_dev->dev;
0ecbe1ca 4874 struct net_device *dev = tp->dev;
6f0333b8 4875 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
1da177e4 4876
6f0333b8
ED		 4877 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
4878 if (!data)
4879 return NULL;
e9f63f30 4880
6f0333b8
ED		 4881 if (rtl8169_align(data) != data) {
4882 kfree(data);
4883 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
4884 if (!data)
4885 return NULL;
4886 }
3eafe507 4887
48addcc9 4888 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
231aee63 4889 DMA_FROM_DEVICE);
d827d86b
SG		 4890 if (unlikely(dma_mapping_error(d, mapping))) {
4891 if (net_ratelimit())
4892 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
3eafe507 4893 goto err_out;
d827d86b 4894 }
1da177e4
LT		 4895
4896 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
6f0333b8 4897 return data;
3eafe507
SG		 4898
4899err_out:
4900 kfree(data);
4901 return NULL;
1da177e4
LT		 4902}
4903
4904static void rtl8169_rx_clear(struct rtl8169_private *tp)
4905{
07d3f51f 4906 unsigned int i;
1da177e4
LT		 4907
4908 for (i = 0; i < NUM_RX_DESC; i++) {
6f0333b8
ED		 4909 if (tp->Rx_databuff[i]) {
4910 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
1da177e4
LT		 4911 tp->RxDescArray + i);
4912 }
4913 }
4914}
4915
0ecbe1ca 4916static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
1da177e4 4917{
0ecbe1ca
SG		 4918 desc->opts1 |= cpu_to_le32(RingEnd);
4919}
5b0384f4 4920
0ecbe1ca
SG		 4921static int rtl8169_rx_fill(struct rtl8169_private *tp)
4922{
4923 unsigned int i;
1da177e4 4924
0ecbe1ca
SG		 4925 for (i = 0; i < NUM_RX_DESC; i++) {
4926 void *data;
4ae47c2d 4927
6f0333b8 4928 if (tp->Rx_databuff[i])
1da177e4 4929 continue;
bcf0bf90 4930
0ecbe1ca 4931 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
6f0333b8
ED		 4932 if (!data) {
4933 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
0ecbe1ca 4934 goto err_out;
6f0333b8
ED		 4935 }
4936 tp->Rx_databuff[i] = data;
1da177e4 4937 }
1da177e4 4938
0ecbe1ca
SG		 4939 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
4940 return 0;
4941
4942err_out:
4943 rtl8169_rx_clear(tp);
4944 return -ENOMEM;
1da177e4
LT		 4945}
4946
1da177e4
LT		 4947static int rtl8169_init_ring(struct net_device *dev)
4948{
4949 struct rtl8169_private *tp = netdev_priv(dev);
4950
4951 rtl8169_init_ring_indexes(tp);
4952
4953 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
6f0333b8 4954 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
1da177e4 4955
0ecbe1ca 4956 return rtl8169_rx_fill(tp);
1da177e4
LT		 4957}
4958
48addcc9 4959static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
1da177e4
LT		 4960 struct TxDesc *desc)
4961{
4962 unsigned int len = tx_skb->len;
4963
48addcc9
SG		 4964 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
4965
1da177e4
LT		 4966 desc->opts1 = 0x00;
4967 desc->opts2 = 0x00;
4968 desc->addr = 0x00;
4969 tx_skb->len = 0;
4970}
4971
3eafe507
SG		 4972static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
4973 unsigned int n)
1da177e4
LT		 4974{
4975 unsigned int i;
4976
3eafe507
SG		 4977 for (i = 0; i < n; i++) {
4978 unsigned int entry = (start + i) % NUM_TX_DESC;
1da177e4
LT		 4979 struct ring_info *tx_skb = tp->tx_skb + entry;
4980 unsigned int len = tx_skb->len;
4981
4982 if (len) {
4983 struct sk_buff *skb = tx_skb->skb;
4984
48addcc9 4985 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
1da177e4
LT		 4986 tp->TxDescArray + entry);
4987 if (skb) {
cac4b22f 4988 tp->dev->stats.tx_dropped++;
1da177e4
LT		 4989 dev_kfree_skb(skb);
4990 tx_skb->skb = NULL;
4991 }
1da177e4
LT		 4992 }
4993 }
3eafe507
SG		 4994}
4995
4996static void rtl8169_tx_clear(struct rtl8169_private *tp)
4997{
4998 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
1da177e4 4999 tp->cur_tx = tp->dirty_tx = 0;
036dafa2 5000 netdev_reset_queue(tp->dev);
1da177e4
LT		 5001}
5002
4422bcd4 5003static void rtl_reset_work(struct rtl8169_private *tp)
1da177e4 5004{
c4028958 5005 struct net_device *dev = tp->dev;
56de414c 5006 int i;
1da177e4 5007
da78dbff
FR		 5008 napi_disable(&tp->napi);
5009 netif_stop_queue(dev);
5010 synchronize_sched();
1da177e4 5011
c7c2c39b 5012 rtl8169_hw_reset(tp);
5013
56de414c
FR		 5014 for (i = 0; i < NUM_RX_DESC; i++)
5015 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
5016
1da177e4 5017 rtl8169_tx_clear(tp);
c7c2c39b 5018 rtl8169_init_ring_indexes(tp);
1da177e4 5019
da78dbff 5020 napi_enable(&tp->napi);
56de414c
FR		 5021 rtl_hw_start(dev);
5022 netif_wake_queue(dev);
5023 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1da177e4
LT		 5024}
5025
5026static void rtl8169_tx_timeout(struct net_device *dev)
5027{
da78dbff
FR		 5028 struct rtl8169_private *tp = netdev_priv(dev);
5029
5030 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
1da177e4
LT		 5031}
5032
5033static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2b7b4318 5034 u32 *opts)
1da177e4
LT		 5035{
5036 struct skb_shared_info *info = skb_shinfo(skb);
5037 unsigned int cur_frag, entry;
a6343afb 5038 struct TxDesc * uninitialized_var(txd);
48addcc9 5039 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 5040
5041 entry = tp->cur_tx;
5042 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
9e903e08 5043 const skb_frag_t *frag = info->frags + cur_frag;
1da177e4
LT		 5044 dma_addr_t mapping;
5045 u32 status, len;
5046 void *addr;
5047
5048 entry = (entry + 1) % NUM_TX_DESC;
5049
5050 txd = tp->TxDescArray + entry;
9e903e08 5051 len = skb_frag_size(frag);
929f6189 5052 addr = skb_frag_address(frag);
48addcc9 5053 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
d827d86b
SG		 5054 if (unlikely(dma_mapping_error(d, mapping))) {
5055 if (net_ratelimit())
5056 netif_err(tp, drv, tp->dev,
5057 "Failed to map TX fragments DMA!\n");
3eafe507 5058 goto err_out;
d827d86b 5059 }
1da177e4 5060
cecb5fd7 5061 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318
FR		 5062 status = opts[0] | len |
5063 (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 5064
5065 txd->opts1 = cpu_to_le32(status);
2b7b4318 5066 txd->opts2 = cpu_to_le32(opts[1]);
1da177e4
LT		 5067 txd->addr = cpu_to_le64(mapping);
5068
5069 tp->tx_skb[entry].len = len;
5070 }
5071
5072 if (cur_frag) {
5073 tp->tx_skb[entry].skb = skb;
5074 txd->opts1 |= cpu_to_le32(LastFrag);
5075 }
5076
5077 return cur_frag;
3eafe507
SG		 5078
5079err_out:
5080 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5081 return -EIO;
1da177e4
LT		 5082}
5083
2b7b4318
FR		 5084static inline void rtl8169_tso_csum(struct rtl8169_private *tp,
5085 struct sk_buff *skb, u32 *opts)
1da177e4 5086{
2b7b4318 5087 const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
350fb32a 5088 u32 mss = skb_shinfo(skb)->gso_size;
2b7b4318 5089 int offset = info->opts_offset;
350fb32a 5090
2b7b4318
FR		 5091 if (mss) {
5092 opts[0] |= TD_LSO;
5093 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
5094 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
eddc9ec5 5095 const struct iphdr *ip = ip_hdr(skb);
1da177e4
LT		 5096
5097 if (ip->protocol == IPPROTO_TCP)
2b7b4318 5098 opts[offset] |= info->checksum.tcp;
1da177e4 5099 else if (ip->protocol == IPPROTO_UDP)
2b7b4318
FR		 5100 opts[offset] |= info->checksum.udp;
5101 else
5102 WARN_ON_ONCE(1);
1da177e4 5103 }
1da177e4
LT		 5104}
5105
61357325
SH		 5106static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5107 struct net_device *dev)
1da177e4
LT		 5108{
5109 struct rtl8169_private *tp = netdev_priv(dev);
3eafe507 5110 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
1da177e4
LT		 5111 struct TxDesc *txd = tp->TxDescArray + entry;
5112 void __iomem *ioaddr = tp->mmio_addr;
48addcc9 5113 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 5114 dma_addr_t mapping;
5115 u32 status, len;
2b7b4318 5116 u32 opts[2];
3eafe507 5117 int frags;
5b0384f4 5118
1da177e4 5119 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
bf82c189 5120 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
3eafe507 5121 goto err_stop_0;
1da177e4
LT		 5122 }
5123
5124 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
3eafe507
SG		 5125 goto err_stop_0;
5126
5127 len = skb_headlen(skb);
48addcc9 5128 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
d827d86b
SG		 5129 if (unlikely(dma_mapping_error(d, mapping))) {
5130 if (net_ratelimit())
5131 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
3eafe507 5132 goto err_dma_0;
d827d86b 5133 }
3eafe507
SG		 5134
5135 tp->tx_skb[entry].len = len;
5136 txd->addr = cpu_to_le64(mapping);
1da177e4 5137
2b7b4318
FR		 5138 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
5139 opts[0] = DescOwn;
1da177e4 5140
2b7b4318
FR		 5141 rtl8169_tso_csum(tp, skb, opts);
5142
5143 frags = rtl8169_xmit_frags(tp, skb, opts);
3eafe507
SG		 5144 if (frags < 0)
5145 goto err_dma_1;
5146 else if (frags)
2b7b4318 5147 opts[0] |= FirstFrag;
3eafe507 5148 else {
2b7b4318 5149 opts[0] |= FirstFrag | LastFrag;
1da177e4
LT		 5150 tp->tx_skb[entry].skb = skb;
5151 }
5152
2b7b4318
FR		 5153 txd->opts2 = cpu_to_le32(opts[1]);
5154
036dafa2
IM		 5155 netdev_sent_queue(dev, skb->len);
5156
5047fb5d
RC		 5157 skb_tx_timestamp(skb);
5158
1da177e4
LT		 5159 wmb();
5160
cecb5fd7 5161 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318 5162 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 5163 txd->opts1 = cpu_to_le32(status);
5164
1da177e4
LT		 5165 tp->cur_tx += frags + 1;
5166
4c020a96 5167 wmb();
1da177e4 5168
cecb5fd7 5169 RTL_W8(TxPoll, NPQ);
1da177e4 5170
da78dbff
FR		 5171 mmiowb();
5172
1da177e4 5173 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
ae1f23fb
FR		 5174 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
5175 * not miss a ring update when it notices a stopped queue.
5176 */
5177 smp_wmb();
1da177e4 5178 netif_stop_queue(dev);
ae1f23fb
FR		 5179 /* Sync with rtl_tx:
5180 * - publish queue status and cur_tx ring index (write barrier)
5181 * - refresh dirty_tx ring index (read barrier).
5182 * May the current thread have a pessimistic view of the ring
5183 * status and forget to wake up queue, a racing rtl_tx thread
5184 * can't.
5185 */
1e874e04 5186 smp_mb();
1da177e4
LT		 5187 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
5188 netif_wake_queue(dev);
5189 }
5190
61357325 5191 return NETDEV_TX_OK;
1da177e4 5192
3eafe507 5193err_dma_1:
48addcc9 5194 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
3eafe507
SG		 5195err_dma_0:
5196 dev_kfree_skb(skb);
5197 dev->stats.tx_dropped++;
5198 return NETDEV_TX_OK;
5199
5200err_stop_0:
1da177e4 5201 netif_stop_queue(dev);
cebf8cc7 5202 dev->stats.tx_dropped++;
61357325 5203 return NETDEV_TX_BUSY;
1da177e4
LT		 5204}
5205
5206static void rtl8169_pcierr_interrupt(struct net_device *dev)
5207{
5208 struct rtl8169_private *tp = netdev_priv(dev);
5209 struct pci_dev *pdev = tp->pci_dev;
1da177e4
LT		 5210 u16 pci_status, pci_cmd;
5211
5212 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
5213 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
5214
bf82c189
JP		 5215 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
5216 pci_cmd, pci_status);
1da177e4
LT		 5217
5218 /*
5219 * The recovery sequence below admits a very elaborated explanation:
5220 * - it seems to work;
d03902b8
FR		 5221 * - I did not see what else could be done;
5222 * - it makes iop3xx happy.
1da177e4
LT		 5223 *
5224 * Feel free to adjust to your needs.
5225 */
a27993f3 5226 if (pdev->broken_parity_status)
d03902b8
FR		 5227 pci_cmd &= ~PCI_COMMAND_PARITY;
5228 else
5229 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
5230
5231 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 5232
5233 pci_write_config_word(pdev, PCI_STATUS,
5234 pci_status & (PCI_STATUS_DETECTED_PARITY |
5235 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
5236 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
5237
5238 /* The infamous DAC f*ckup only happens at boot time */
5239 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
e6de30d6 5240 void __iomem *ioaddr = tp->mmio_addr;
5241
bf82c189 5242 netif_info(tp, intr, dev, "disabling PCI DAC\n");
1da177e4
LT		 5243 tp->cp_cmd &= ~PCIDAC;
5244 RTL_W16(CPlusCmd, tp->cp_cmd);
5245 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 5246 }
5247
e6de30d6 5248 rtl8169_hw_reset(tp);
d03902b8 5249
98ddf986 5250 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
1da177e4
LT		 5251}
5252
036dafa2
IM		 5253struct rtl_txc {
5254 int packets;
5255 int bytes;
5256};
5257
da78dbff 5258static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
1da177e4 5259{
036dafa2 5260 struct rtl8169_stats *tx_stats = &tp->tx_stats;
1da177e4 5261 unsigned int dirty_tx, tx_left;
036dafa2 5262 struct rtl_txc txc = { 0, 0 };
1da177e4 5263
1da177e4
LT		 5264 dirty_tx = tp->dirty_tx;
5265 smp_rmb();
5266 tx_left = tp->cur_tx - dirty_tx;
5267
5268 while (tx_left > 0) {
5269 unsigned int entry = dirty_tx % NUM_TX_DESC;
5270 struct ring_info *tx_skb = tp->tx_skb + entry;
1da177e4
LT		 5271 u32 status;
5272
5273 rmb();
5274 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
5275 if (status & DescOwn)
5276 break;
5277
48addcc9
SG		 5278 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5279 tp->TxDescArray + entry);
1da177e4 5280 if (status & LastFrag) {
036dafa2
IM		 5281 struct sk_buff *skb = tx_skb->skb;
5282
5283 txc.packets++;
5284 txc.bytes += skb->len;
5285 dev_kfree_skb(skb);
1da177e4
LT		 5286 tx_skb->skb = NULL;
5287 }
5288 dirty_tx++;
5289 tx_left--;
5290 }
5291
036dafa2
IM		 5292 u64_stats_update_begin(&tx_stats->syncp);
5293 tx_stats->packets += txc.packets;
5294 tx_stats->bytes += txc.bytes;
5295 u64_stats_update_end(&tx_stats->syncp);
5296
5297 netdev_completed_queue(dev, txc.packets, txc.bytes);
5298
1da177e4
LT		 5299 if (tp->dirty_tx != dirty_tx) {
5300 tp->dirty_tx = dirty_tx;
ae1f23fb
FR		 5301 /* Sync with rtl8169_start_xmit:
5302 * - publish dirty_tx ring index (write barrier)
5303 * - refresh cur_tx ring index and queue status (read barrier)
5304 * May the current thread miss the stopped queue condition,
5305 * a racing xmit thread can only have a right view of the
5306 * ring status.
5307 */
1e874e04 5308 smp_mb();
1da177e4
LT		 5309 if (netif_queue_stopped(dev) &&
5310 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
5311 netif_wake_queue(dev);
5312 }
d78ae2dc
FR		 5313 /*
5314 * 8168 hack: TxPoll requests are lost when the Tx packets are
5315 * too close. Let's kick an extra TxPoll request when a burst
5316 * of start_xmit activity is detected (if it is not detected,
5317 * it is slow enough). -- FR
5318 */
da78dbff
FR		 5319 if (tp->cur_tx != dirty_tx) {
5320 void __iomem *ioaddr = tp->mmio_addr;
5321
d78ae2dc 5322 RTL_W8(TxPoll, NPQ);
da78dbff 5323 }
1da177e4
LT		 5324 }
5325}
5326
126fa4b9
FR		 5327static inline int rtl8169_fragmented_frame(u32 status)
5328{
5329 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
5330}
5331
adea1ac7 5332static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
1da177e4 5333{
1da177e4
LT		 5334 u32 status = opts1 & RxProtoMask;
5335
5336 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
d5d3ebe3 5337 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
1da177e4
LT		 5338 skb->ip_summed = CHECKSUM_UNNECESSARY;
5339 else
bc8acf2c 5340 skb_checksum_none_assert(skb);
1da177e4
LT		 5341}
5342
6f0333b8
ED		 5343static struct sk_buff *rtl8169_try_rx_copy(void *data,
5344 struct rtl8169_private *tp,
5345 int pkt_size,
5346 dma_addr_t addr)
1da177e4 5347{
b449655f 5348 struct sk_buff *skb;
48addcc9 5349 struct device *d = &tp->pci_dev->dev;
b449655f 5350
6f0333b8 5351 data = rtl8169_align(data);
48addcc9 5352 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6f0333b8
ED		 5353 prefetch(data);
5354 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
5355 if (skb)
5356 memcpy(skb->data, data, pkt_size);
48addcc9
SG		 5357 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
5358
6f0333b8 5359 return skb;
1da177e4
LT		 5360}
5361
da78dbff 5362static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
1da177e4
LT		 5363{
5364 unsigned int cur_rx, rx_left;
6f0333b8 5365 unsigned int count;
1da177e4 5366
1da177e4
LT		 5367 cur_rx = tp->cur_rx;
5368 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
865c652d 5369 rx_left = min(rx_left, budget);
1da177e4 5370
4dcb7d33 5371 for (; rx_left > 0; rx_left--, cur_rx++) {
1da177e4 5372 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 5373 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 5374 u32 status;
5375
5376 rmb();
e03f33af 5377 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
1da177e4
LT		 5378
5379 if (status & DescOwn)
5380 break;
4dcb7d33 5381 if (unlikely(status & RxRES)) {
bf82c189
JP		 5382 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
5383 status);
cebf8cc7 5384 dev->stats.rx_errors++;
1da177e4 5385 if (status & (RxRWT | RxRUNT))
cebf8cc7 5386 dev->stats.rx_length_errors++;
1da177e4 5387 if (status & RxCRC)
cebf8cc7 5388 dev->stats.rx_crc_errors++;
9dccf611 5389 if (status & RxFOVF) {
da78dbff 5390 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
cebf8cc7 5391 dev->stats.rx_fifo_errors++;
9dccf611 5392 }
6bbe021d
BG		 5393 if ((status & (RxRUNT | RxCRC)) &&
5394 !(status & (RxRWT | RxFOVF)) &&
5395 (dev->features & NETIF_F_RXALL))
5396 goto process_pkt;
5397
6f0333b8 5398 rtl8169_mark_to_asic(desc, rx_buf_sz);
1da177e4 5399 } else {
6f0333b8 5400 struct sk_buff *skb;
6bbe021d
BG		 5401 dma_addr_t addr;
5402 int pkt_size;
5403
5404process_pkt:
5405 addr = le64_to_cpu(desc->addr);
79d0c1d2
BG		 5406 if (likely(!(dev->features & NETIF_F_RXFCS)))
5407 pkt_size = (status & 0x00003fff) - 4;
5408 else
5409 pkt_size = status & 0x00003fff;
1da177e4 5410
126fa4b9
FR		 5411 /*
5412 * The driver does not support incoming fragmented
5413 * frames. They are seen as a symptom of over-mtu
5414 * sized frames.
5415 */
5416 if (unlikely(rtl8169_fragmented_frame(status))) {
cebf8cc7
FR		 5417 dev->stats.rx_dropped++;
5418 dev->stats.rx_length_errors++;
6f0333b8 5419 rtl8169_mark_to_asic(desc, rx_buf_sz);
4dcb7d33 5420 continue;
126fa4b9
FR		 5421 }
5422
6f0333b8
ED		 5423 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
5424 tp, pkt_size, addr);
5425 rtl8169_mark_to_asic(desc, rx_buf_sz);
5426 if (!skb) {
5427 dev->stats.rx_dropped++;
5428 continue;
1da177e4
LT		 5429 }
5430
adea1ac7 5431 rtl8169_rx_csum(skb, status);
1da177e4
LT		 5432 skb_put(skb, pkt_size);
5433 skb->protocol = eth_type_trans(skb, dev);
5434
7a8fc77b
FR		 5435 rtl8169_rx_vlan_tag(desc, skb);
5436
56de414c 5437 napi_gro_receive(&tp->napi, skb);
1da177e4 5438
8027aa24
JW		 5439 u64_stats_update_begin(&tp->rx_stats.syncp);
5440 tp->rx_stats.packets++;
5441 tp->rx_stats.bytes += pkt_size;
5442 u64_stats_update_end(&tp->rx_stats.syncp);
1da177e4 5443 }
6dccd16b
FR		 5444
5445 /* Work around for AMD plateform. */
95e0918d 5446 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
6dccd16b
FR		 5447 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
5448 desc->opts2 = 0;
5449 cur_rx++;
5450 }
1da177e4
LT		 5451 }
5452
5453 count = cur_rx - tp->cur_rx;
5454 tp->cur_rx = cur_rx;
5455
6f0333b8 5456 tp->dirty_rx += count;
1da177e4
LT		 5457
5458 return count;
5459}
5460
07d3f51f 5461static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 5462{
07d3f51f 5463 struct net_device *dev = dev_instance;
1da177e4 5464 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 5465 int handled = 0;
9085cdfa 5466 u16 status;
1da177e4 5467
9085cdfa 5468 status = rtl_get_events(tp);
da78dbff
FR		 5469 if (status && status != 0xffff) {
5470 status &= RTL_EVENT_NAPI | tp->event_slow;
5471 if (status) {
5472 handled = 1;
1da177e4 5473
da78dbff
FR		 5474 rtl_irq_disable(tp);
5475 napi_schedule(&tp->napi);
f11a377b 5476 }
da78dbff
FR		 5477 }
5478 return IRQ_RETVAL(handled);
5479}
1da177e4 5480
da78dbff
FR		 5481/*
5482 * Workqueue context.
5483 */
5484static void rtl_slow_event_work(struct rtl8169_private *tp)
5485{
5486 struct net_device *dev = tp->dev;
5487 u16 status;
5488
5489 status = rtl_get_events(tp) & tp->event_slow;
5490 rtl_ack_events(tp, status);
1da177e4 5491
da78dbff
FR		 5492 if (unlikely(status & RxFIFOOver)) {
5493 switch (tp->mac_version) {
5494 /* Work around for rx fifo overflow */
5495 case RTL_GIGA_MAC_VER_11:
5496 netif_stop_queue(dev);
934714d0
FR		 5497 /* XXX - Hack alert. See rtl_task(). */
5498 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
da78dbff 5499 default:
f11a377b
DD		 5500 break;
5501 }
da78dbff 5502 }
1da177e4 5503
da78dbff
FR		 5504 if (unlikely(status & SYSErr))
5505 rtl8169_pcierr_interrupt(dev);
0e485150 5506
da78dbff
FR		 5507 if (status & LinkChg)
5508 __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true);
1da177e4 5509
da78dbff
FR		 5510 napi_disable(&tp->napi);
5511 rtl_irq_disable(tp);
5512
5513 napi_enable(&tp->napi);
5514 napi_schedule(&tp->napi);
1da177e4
LT		 5515}
5516
4422bcd4
FR		 5517static void rtl_task(struct work_struct *work)
5518{
da78dbff
FR		 5519 static const struct {
5520 int bitnr;
5521 void (*action)(struct rtl8169_private *);
5522 } rtl_work[] = {
934714d0 5523 /* XXX - keep rtl_slow_event_work() as first element. */
da78dbff
FR		 5524 { RTL_FLAG_TASK_SLOW_PENDING, rtl_slow_event_work },
5525 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work },
5526 { RTL_FLAG_TASK_PHY_PENDING, rtl_phy_work }
5527 };
4422bcd4
FR		 5528 struct rtl8169_private *tp =
5529 container_of(work, struct rtl8169_private, wk.work);
da78dbff
FR		 5530 struct net_device *dev = tp->dev;
5531 int i;
5532
5533 rtl_lock_work(tp);
5534
6c4a70c5
FR		 5535 if (!netif_running(dev) ||
5536 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
da78dbff
FR		 5537 goto out_unlock;
5538
5539 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
5540 bool pending;
5541
da78dbff 5542 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
da78dbff
FR		 5543 if (pending)
5544 rtl_work[i].action(tp);
5545 }
4422bcd4 5546
da78dbff
FR		 5547out_unlock:
5548 rtl_unlock_work(tp);
4422bcd4
FR		 5549}
5550
bea3348e 5551static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 5552{
bea3348e
SH		 5553 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
5554 struct net_device *dev = tp->dev;
da78dbff
FR		 5555 u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
5556 int work_done= 0;
5557 u16 status;
5558
5559 status = rtl_get_events(tp);
5560 rtl_ack_events(tp, status & ~tp->event_slow);
5561
5562 if (status & RTL_EVENT_NAPI_RX)
5563 work_done = rtl_rx(dev, tp, (u32) budget);
5564
5565 if (status & RTL_EVENT_NAPI_TX)
5566 rtl_tx(dev, tp);
1da177e4 5567
da78dbff
FR		 5568 if (status & tp->event_slow) {
5569 enable_mask &= ~tp->event_slow;
5570
5571 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
5572 }
1da177e4 5573
bea3348e 5574 if (work_done < budget) {
288379f0 5575 napi_complete(napi);
f11a377b 5576
da78dbff
FR		 5577 rtl_irq_enable(tp, enable_mask);
5578 mmiowb();
1da177e4
LT		 5579 }
5580
bea3348e 5581 return work_done;
1da177e4 5582}
1da177e4 5583
523a6094
FR		 5584static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
5585{
5586 struct rtl8169_private *tp = netdev_priv(dev);
5587
5588 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
5589 return;
5590
5591 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
5592 RTL_W32(RxMissed, 0);
5593}
5594
1da177e4
LT		 5595static void rtl8169_down(struct net_device *dev)
5596{
5597 struct rtl8169_private *tp = netdev_priv(dev);
5598 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 5599
4876cc1e 5600 del_timer_sync(&tp->timer);
1da177e4 5601
93dd79e8 5602 napi_disable(&tp->napi);
da78dbff 5603 netif_stop_queue(dev);
1da177e4 5604
92fc43b4 5605 rtl8169_hw_reset(tp);
323bb685
SG		 5606 /*
5607 * At this point device interrupts can not be enabled in any function,
209e5ac8
FR		 5608 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
5609 * and napi is disabled (rtl8169_poll).
323bb685 5610 */
523a6094 5611 rtl8169_rx_missed(dev, ioaddr);
1da177e4 5612
1da177e4 5613 /* Give a racing hard_start_xmit a few cycles to complete. */
da78dbff 5614 synchronize_sched();
1da177e4 5615
1da177e4
LT		 5616 rtl8169_tx_clear(tp);
5617
5618 rtl8169_rx_clear(tp);
065c27c1 5619
5620 rtl_pll_power_down(tp);
1da177e4
LT		 5621}
5622
5623static int rtl8169_close(struct net_device *dev)
5624{
5625 struct rtl8169_private *tp = netdev_priv(dev);
5626 struct pci_dev *pdev = tp->pci_dev;
5627
e1759441
RW		 5628 pm_runtime_get_sync(&pdev->dev);
5629
cecb5fd7 5630 /* Update counters before going down */
355423d0
IV		 5631 rtl8169_update_counters(dev);
5632
da78dbff 5633 rtl_lock_work(tp);
6c4a70c5 5634 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
da78dbff 5635
1da177e4 5636 rtl8169_down(dev);
da78dbff 5637 rtl_unlock_work(tp);
1da177e4 5638
92a7c4e7 5639 free_irq(pdev->irq, dev);
1da177e4 5640
82553bb6
SG		 5641 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
5642 tp->RxPhyAddr);
5643 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
5644 tp->TxPhyAddr);
1da177e4
LT		 5645 tp->TxDescArray = NULL;
5646 tp->RxDescArray = NULL;
5647
e1759441
RW		 5648 pm_runtime_put_sync(&pdev->dev);
5649
1da177e4
LT		 5650 return 0;
5651}
5652
dc1c00ce
FR		 5653#ifdef CONFIG_NET_POLL_CONTROLLER
5654static void rtl8169_netpoll(struct net_device *dev)
5655{
5656 struct rtl8169_private *tp = netdev_priv(dev);
5657
5658 rtl8169_interrupt(tp->pci_dev->irq, dev);
5659}
5660#endif
5661
df43ac78
FR		 5662static int rtl_open(struct net_device *dev)
5663{
5664 struct rtl8169_private *tp = netdev_priv(dev);
5665 void __iomem *ioaddr = tp->mmio_addr;
5666 struct pci_dev *pdev = tp->pci_dev;
5667 int retval = -ENOMEM;
5668
5669 pm_runtime_get_sync(&pdev->dev);
5670
5671 /*
5672 * Rx and Tx desscriptors needs 256 bytes alignment.
5673 * dma_alloc_coherent provides more.
5674 */
5675 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
5676 &tp->TxPhyAddr, GFP_KERNEL);
5677 if (!tp->TxDescArray)
5678 goto err_pm_runtime_put;
5679
5680 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
5681 &tp->RxPhyAddr, GFP_KERNEL);
5682 if (!tp->RxDescArray)
5683 goto err_free_tx_0;
5684
5685 retval = rtl8169_init_ring(dev);
5686 if (retval < 0)
5687 goto err_free_rx_1;
5688
5689 INIT_WORK(&tp->wk.work, rtl_task);
5690
5691 smp_mb();
5692
5693 rtl_request_firmware(tp);
5694
92a7c4e7 5695 retval = request_irq(pdev->irq, rtl8169_interrupt,
df43ac78
FR		 5696 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
5697 dev->name, dev);
5698 if (retval < 0)
5699 goto err_release_fw_2;
5700
5701 rtl_lock_work(tp);
5702
5703 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
5704
5705 napi_enable(&tp->napi);
5706
5707 rtl8169_init_phy(dev, tp);
5708
5709 __rtl8169_set_features(dev, dev->features);
5710
5711 rtl_pll_power_up(tp);
5712
5713 rtl_hw_start(dev);
5714
5715 netif_start_queue(dev);
5716
5717 rtl_unlock_work(tp);
5718
5719 tp->saved_wolopts = 0;
5720 pm_runtime_put_noidle(&pdev->dev);
5721
5722 rtl8169_check_link_status(dev, tp, ioaddr);
5723out:
5724 return retval;
5725
5726err_release_fw_2:
5727 rtl_release_firmware(tp);
5728 rtl8169_rx_clear(tp);
5729err_free_rx_1:
5730 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
5731 tp->RxPhyAddr);
5732 tp->RxDescArray = NULL;
5733err_free_tx_0:
5734 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
5735 tp->TxPhyAddr);
5736 tp->TxDescArray = NULL;
5737err_pm_runtime_put:
5738 pm_runtime_put_noidle(&pdev->dev);
5739 goto out;
5740}
5741
8027aa24
JW		 5742static struct rtnl_link_stats64 *
5743rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
1da177e4
LT		 5744{
5745 struct rtl8169_private *tp = netdev_priv(dev);
5746 void __iomem *ioaddr = tp->mmio_addr;
8027aa24 5747 unsigned int start;
1da177e4 5748
da78dbff 5749 if (netif_running(dev))
523a6094 5750 rtl8169_rx_missed(dev, ioaddr);
5b0384f4 5751
8027aa24
JW		 5752 do {
5753 start = u64_stats_fetch_begin_bh(&tp->rx_stats.syncp);
5754 stats->rx_packets = tp->rx_stats.packets;
5755 stats->rx_bytes = tp->rx_stats.bytes;
5756 } while (u64_stats_fetch_retry_bh(&tp->rx_stats.syncp, start));
5757
5758
5759 do {
5760 start = u64_stats_fetch_begin_bh(&tp->tx_stats.syncp);
5761 stats->tx_packets = tp->tx_stats.packets;
5762 stats->tx_bytes = tp->tx_stats.bytes;
5763 } while (u64_stats_fetch_retry_bh(&tp->tx_stats.syncp, start));
5764
5765 stats->rx_dropped = dev->stats.rx_dropped;
5766 stats->tx_dropped = dev->stats.tx_dropped;
5767 stats->rx_length_errors = dev->stats.rx_length_errors;
5768 stats->rx_errors = dev->stats.rx_errors;
5769 stats->rx_crc_errors = dev->stats.rx_crc_errors;
5770 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
5771 stats->rx_missed_errors = dev->stats.rx_missed_errors;
5772
5773 return stats;
1da177e4
LT		 5774}
5775
861ab440 5776static void rtl8169_net_suspend(struct net_device *dev)
5d06a99f 5777{
065c27c1 5778 struct rtl8169_private *tp = netdev_priv(dev);
5779
5d06a99f 5780 if (!netif_running(dev))
861ab440 5781 return;
5d06a99f
FR		 5782
5783 netif_device_detach(dev);
5784 netif_stop_queue(dev);
da78dbff
FR		 5785
5786 rtl_lock_work(tp);
5787 napi_disable(&tp->napi);
6c4a70c5 5788 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
da78dbff
FR		 5789 rtl_unlock_work(tp);
5790
5791 rtl_pll_power_down(tp);
861ab440
RW		 5792}
5793
5794#ifdef CONFIG_PM
5795
5796static int rtl8169_suspend(struct device *device)
5797{
5798 struct pci_dev *pdev = to_pci_dev(device);
5799 struct net_device *dev = pci_get_drvdata(pdev);
5d06a99f 5800
861ab440 5801 rtl8169_net_suspend(dev);
1371fa6d 5802
5d06a99f
FR		 5803 return 0;
5804}
5805
e1759441
RW		 5806static void __rtl8169_resume(struct net_device *dev)
5807{
065c27c1 5808 struct rtl8169_private *tp = netdev_priv(dev);
5809
e1759441 5810 netif_device_attach(dev);
065c27c1 5811
5812 rtl_pll_power_up(tp);
5813
cff4c162
AS		 5814 rtl_lock_work(tp);
5815 napi_enable(&tp->napi);
6c4a70c5 5816 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
cff4c162 5817 rtl_unlock_work(tp);
da78dbff 5818
98ddf986 5819 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
e1759441
RW		 5820}
5821
861ab440 5822static int rtl8169_resume(struct device *device)
5d06a99f 5823{
861ab440 5824 struct pci_dev *pdev = to_pci_dev(device);
5d06a99f 5825 struct net_device *dev = pci_get_drvdata(pdev);
fccec10b
SG		 5826 struct rtl8169_private *tp = netdev_priv(dev);
5827
5828 rtl8169_init_phy(dev, tp);
5d06a99f 5829
e1759441
RW		 5830 if (netif_running(dev))
5831 __rtl8169_resume(dev);
5d06a99f 5832
e1759441
RW		 5833 return 0;
5834}
5835
5836static int rtl8169_runtime_suspend(struct device *device)
5837{
5838 struct pci_dev *pdev = to_pci_dev(device);
5839 struct net_device *dev = pci_get_drvdata(pdev);
5840 struct rtl8169_private *tp = netdev_priv(dev);
5841
5842 if (!tp->TxDescArray)
5843 return 0;
5844
da78dbff 5845 rtl_lock_work(tp);
e1759441
RW		 5846 tp->saved_wolopts = __rtl8169_get_wol(tp);
5847 __rtl8169_set_wol(tp, WAKE_ANY);
da78dbff 5848 rtl_unlock_work(tp);
e1759441
RW		 5849
5850 rtl8169_net_suspend(dev);
5851
5852 return 0;
5853}
5854
5855static int rtl8169_runtime_resume(struct device *device)
5856{
5857 struct pci_dev *pdev = to_pci_dev(device);
5858 struct net_device *dev = pci_get_drvdata(pdev);
5859 struct rtl8169_private *tp = netdev_priv(dev);
5860
5861 if (!tp->TxDescArray)
5862 return 0;
5863
da78dbff 5864 rtl_lock_work(tp);
e1759441
RW		 5865 __rtl8169_set_wol(tp, tp->saved_wolopts);
5866 tp->saved_wolopts = 0;
da78dbff 5867 rtl_unlock_work(tp);
e1759441 5868
fccec10b
SG		 5869 rtl8169_init_phy(dev, tp);
5870
e1759441 5871 __rtl8169_resume(dev);
5d06a99f 5872
5d06a99f
FR		 5873 return 0;
5874}
5875
e1759441
RW		 5876static int rtl8169_runtime_idle(struct device *device)
5877{
5878 struct pci_dev *pdev = to_pci_dev(device);
5879 struct net_device *dev = pci_get_drvdata(pdev);
5880 struct rtl8169_private *tp = netdev_priv(dev);
5881
e4fbce74 5882 return tp->TxDescArray ? -EBUSY : 0;
e1759441
RW		 5883}
5884
47145210 5885static const struct dev_pm_ops rtl8169_pm_ops = {
cecb5fd7
FR		 5886 .suspend = rtl8169_suspend,
5887 .resume = rtl8169_resume,
5888 .freeze = rtl8169_suspend,
5889 .thaw = rtl8169_resume,
5890 .poweroff = rtl8169_suspend,
5891 .restore = rtl8169_resume,
5892 .runtime_suspend = rtl8169_runtime_suspend,
5893 .runtime_resume = rtl8169_runtime_resume,
5894 .runtime_idle = rtl8169_runtime_idle,
861ab440
RW		 5895};
5896
5897#define RTL8169_PM_OPS (&rtl8169_pm_ops)
5898
5899#else /* !CONFIG_PM */
5900
5901#define RTL8169_PM_OPS NULL
5902
5903#endif /* !CONFIG_PM */
5904
649b3b8c 5905static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
5906{
5907 void __iomem *ioaddr = tp->mmio_addr;
5908
5909 /* WoL fails with 8168b when the receiver is disabled. */
5910 switch (tp->mac_version) {
5911 case RTL_GIGA_MAC_VER_11:
5912 case RTL_GIGA_MAC_VER_12:
5913 case RTL_GIGA_MAC_VER_17:
5914 pci_clear_master(tp->pci_dev);
5915
5916 RTL_W8(ChipCmd, CmdRxEnb);
5917 /* PCI commit */
5918 RTL_R8(ChipCmd);
5919 break;
5920 default:
5921 break;
5922 }
5923}
5924
1765f95d
FR		 5925static void rtl_shutdown(struct pci_dev *pdev)
5926{
861ab440 5927 struct net_device *dev = pci_get_drvdata(pdev);
4bb3f522 5928 struct rtl8169_private *tp = netdev_priv(dev);
2a15cd2f 5929 struct device *d = &pdev->dev;
5930
5931 pm_runtime_get_sync(d);
861ab440
RW		 5932
5933 rtl8169_net_suspend(dev);
1765f95d 5934
cecb5fd7 5935 /* Restore original MAC address */
cc098dc7
IV		 5936 rtl_rar_set(tp, dev->perm_addr);
5937
92fc43b4 5938 rtl8169_hw_reset(tp);
4bb3f522 5939
861ab440 5940 if (system_state == SYSTEM_POWER_OFF) {
649b3b8c 5941 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
5942 rtl_wol_suspend_quirk(tp);
5943 rtl_wol_shutdown_quirk(tp);
ca52efd5 5944 }
5945
861ab440
RW		 5946 pci_wake_from_d3(pdev, true);
5947 pci_set_power_state(pdev, PCI_D3hot);
5948 }
2a15cd2f 5949
5950 pm_runtime_put_noidle(d);
861ab440 5951}
5d06a99f 5952
e27566ed
FR		 5953static void __devexit rtl_remove_one(struct pci_dev *pdev)
5954{
5955 struct net_device *dev = pci_get_drvdata(pdev);
5956 struct rtl8169_private *tp = netdev_priv(dev);
5957
5958 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
5959 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
5960 tp->mac_version == RTL_GIGA_MAC_VER_31) {
5961 rtl8168_driver_stop(tp);
5962 }
5963
5964 cancel_work_sync(&tp->wk.work);
5965
5966 unregister_netdev(dev);
5967
5968 rtl_release_firmware(tp);
5969
5970 if (pci_dev_run_wake(pdev))
5971 pm_runtime_get_noresume(&pdev->dev);
5972
5973 /* restore original MAC address */
5974 rtl_rar_set(tp, dev->perm_addr);
5975
5976 rtl_disable_msi(pdev, tp);
5977 rtl8169_release_board(pdev, dev, tp->mmio_addr);
5978 pci_set_drvdata(pdev, NULL);
5979}
5980
fa9c385e 5981static const struct net_device_ops rtl_netdev_ops = {
df43ac78 5982 .ndo_open = rtl_open,
fa9c385e
FR		 5983 .ndo_stop = rtl8169_close,
5984 .ndo_get_stats64 = rtl8169_get_stats64,
5985 .ndo_start_xmit = rtl8169_start_xmit,
5986 .ndo_tx_timeout = rtl8169_tx_timeout,
5987 .ndo_validate_addr = eth_validate_addr,
5988 .ndo_change_mtu = rtl8169_change_mtu,
5989 .ndo_fix_features = rtl8169_fix_features,
5990 .ndo_set_features = rtl8169_set_features,
5991 .ndo_set_mac_address = rtl_set_mac_address,
5992 .ndo_do_ioctl = rtl8169_ioctl,
5993 .ndo_set_rx_mode = rtl_set_rx_mode,
5994#ifdef CONFIG_NET_POLL_CONTROLLER
5995 .ndo_poll_controller = rtl8169_netpoll,
5996#endif
5997
5998};
5999
31fa8b18
FR		 6000static const struct rtl_cfg_info {
6001 void (*hw_start)(struct net_device *);
6002 unsigned int region;
6003 unsigned int align;
6004 u16 event_slow;
6005 unsigned features;
6006 u8 default_ver;
6007} rtl_cfg_infos [] = {
6008 [RTL_CFG_0] = {
6009 .hw_start = rtl_hw_start_8169,
6010 .region = 1,
6011 .align = 0,
6012 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
6013 .features = RTL_FEATURE_GMII,
6014 .default_ver = RTL_GIGA_MAC_VER_01,
6015 },
6016 [RTL_CFG_1] = {
6017 .hw_start = rtl_hw_start_8168,
6018 .region = 2,
6019 .align = 8,
6020 .event_slow = SYSErr | LinkChg | RxOverflow,
6021 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
6022 .default_ver = RTL_GIGA_MAC_VER_11,
6023 },
6024 [RTL_CFG_2] = {
6025 .hw_start = rtl_hw_start_8101,
6026 .region = 2,
6027 .align = 8,
6028 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
6029 PCSTimeout,
6030 .features = RTL_FEATURE_MSI,
6031 .default_ver = RTL_GIGA_MAC_VER_13,
6032 }
6033};
6034
6035/* Cfg9346_Unlock assumed. */
6036static unsigned rtl_try_msi(struct rtl8169_private *tp,
6037 const struct rtl_cfg_info *cfg)
6038{
6039 void __iomem *ioaddr = tp->mmio_addr;
6040 unsigned msi = 0;
6041 u8 cfg2;
6042
6043 cfg2 = RTL_R8(Config2) & ~MSIEnable;
6044 if (cfg->features & RTL_FEATURE_MSI) {
6045 if (pci_enable_msi(tp->pci_dev)) {
6046 netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
6047 } else {
6048 cfg2 |= MSIEnable;
6049 msi = RTL_FEATURE_MSI;
6050 }
6051 }
6052 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
6053 RTL_W8(Config2, cfg2);
6054 return msi;
6055}
6056
3b6cf25d
FR		 6057static int __devinit
6058rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
6059{
6060 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
6061 const unsigned int region = cfg->region;
6062 struct rtl8169_private *tp;
6063 struct mii_if_info *mii;
6064 struct net_device *dev;
6065 void __iomem *ioaddr;
6066 int chipset, i;
6067 int rc;
6068
6069 if (netif_msg_drv(&debug)) {
6070 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
6071 MODULENAME, RTL8169_VERSION);
6072 }
6073
6074 dev = alloc_etherdev(sizeof (*tp));
6075 if (!dev) {
6076 rc = -ENOMEM;
6077 goto out;
6078 }
6079
6080 SET_NETDEV_DEV(dev, &pdev->dev);
fa9c385e 6081 dev->netdev_ops = &rtl_netdev_ops;
3b6cf25d
FR		 6082 tp = netdev_priv(dev);
6083 tp->dev = dev;
6084 tp->pci_dev = pdev;
6085 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
6086
6087 mii = &tp->mii;
6088 mii->dev = dev;
6089 mii->mdio_read = rtl_mdio_read;
6090 mii->mdio_write = rtl_mdio_write;
6091 mii->phy_id_mask = 0x1f;
6092 mii->reg_num_mask = 0x1f;
6093 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
6094
6095 /* disable ASPM completely as that cause random device stop working
6096 * problems as well as full system hangs for some PCIe devices users */
6097 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
6098 PCIE_LINK_STATE_CLKPM);
6099
6100 /* enable device (incl. PCI PM wakeup and hotplug setup) */
6101 rc = pci_enable_device(pdev);
6102 if (rc < 0) {
6103 netif_err(tp, probe, dev, "enable failure\n");
6104 goto err_out_free_dev_1;
6105 }
6106
6107 if (pci_set_mwi(pdev) < 0)
6108 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
6109
6110 /* make sure PCI base addr 1 is MMIO */
6111 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
6112 netif_err(tp, probe, dev,
6113 "region #%d not an MMIO resource, aborting\n",
6114 region);
6115 rc = -ENODEV;
6116 goto err_out_mwi_2;
6117 }
6118
6119 /* check for weird/broken PCI region reporting */
6120 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
6121 netif_err(tp, probe, dev,
6122 "Invalid PCI region size(s), aborting\n");
6123 rc = -ENODEV;
6124 goto err_out_mwi_2;
6125 }
6126
6127 rc = pci_request_regions(pdev, MODULENAME);
6128 if (rc < 0) {
6129 netif_err(tp, probe, dev, "could not request regions\n");
6130 goto err_out_mwi_2;
6131 }
6132
6133 tp->cp_cmd = RxChkSum;
6134
6135 if ((sizeof(dma_addr_t) > 4) &&
6136 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
6137 tp->cp_cmd |= PCIDAC;
6138 dev->features |= NETIF_F_HIGHDMA;
6139 } else {
6140 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6141 if (rc < 0) {
6142 netif_err(tp, probe, dev, "DMA configuration failed\n");
6143 goto err_out_free_res_3;
6144 }
6145 }
6146
6147 /* ioremap MMIO region */
6148 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
6149 if (!ioaddr) {
6150 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
6151 rc = -EIO;
6152 goto err_out_free_res_3;
6153 }
6154 tp->mmio_addr = ioaddr;
6155
6156 if (!pci_is_pcie(pdev))
6157 netif_info(tp, probe, dev, "not PCI Express\n");
6158
6159 /* Identify chip attached to board */
6160 rtl8169_get_mac_version(tp, dev, cfg->default_ver);
6161
6162 rtl_init_rxcfg(tp);
6163
6164 rtl_irq_disable(tp);
6165
6166 rtl_hw_reset(tp);
6167
6168 rtl_ack_events(tp, 0xffff);
6169
6170 pci_set_master(pdev);
6171
6172 /*
6173 * Pretend we are using VLANs; This bypasses a nasty bug where
6174 * Interrupts stop flowing on high load on 8110SCd controllers.
6175 */
6176 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
6177 tp->cp_cmd |= RxVlan;
6178
6179 rtl_init_mdio_ops(tp);
6180 rtl_init_pll_power_ops(tp);
6181 rtl_init_jumbo_ops(tp);
6182
6183 rtl8169_print_mac_version(tp);
6184
6185 chipset = tp->mac_version;
6186 tp->txd_version = rtl_chip_infos[chipset].txd_version;
6187
6188 RTL_W8(Cfg9346, Cfg9346_Unlock);
6189 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
6190 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
6191 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
6192 tp->features |= RTL_FEATURE_WOL;
6193 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
6194 tp->features |= RTL_FEATURE_WOL;
6195 tp->features |= rtl_try_msi(tp, cfg);
6196 RTL_W8(Cfg9346, Cfg9346_Lock);
6197
6198 if (rtl_tbi_enabled(tp)) {
6199 tp->set_speed = rtl8169_set_speed_tbi;
6200 tp->get_settings = rtl8169_gset_tbi;
6201 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
6202 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
6203 tp->link_ok = rtl8169_tbi_link_ok;
6204 tp->do_ioctl = rtl_tbi_ioctl;
6205 } else {
6206 tp->set_speed = rtl8169_set_speed_xmii;
6207 tp->get_settings = rtl8169_gset_xmii;
6208 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
6209 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
6210 tp->link_ok = rtl8169_xmii_link_ok;
6211 tp->do_ioctl = rtl_xmii_ioctl;
6212 }
6213
6214 mutex_init(&tp->wk.mutex);
6215
6216 /* Get MAC address */
6217 for (i = 0; i < ETH_ALEN; i++)
6218 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6219 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
6220
6221 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
6222 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3b6cf25d
FR		 6223
6224 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
6225
6226 /* don't enable SG, IP_CSUM and TSO by default - it might not work
6227 * properly for all devices */
6228 dev->features |= NETIF_F_RXCSUM |
6229 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
6230
6231 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6232 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
6233 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6234 NETIF_F_HIGHDMA;
6235
6236 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
6237 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
6238 dev->hw_features &= ~NETIF_F_HW_VLAN_RX;
6239
6240 dev->hw_features |= NETIF_F_RXALL;
6241 dev->hw_features |= NETIF_F_RXFCS;
6242
6243 tp->hw_start = cfg->hw_start;
6244 tp->event_slow = cfg->event_slow;
6245
6246 tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
6247 ~(RxBOVF | RxFOVF) : ~0;
6248
6249 init_timer(&tp->timer);
6250 tp->timer.data = (unsigned long) dev;
6251 tp->timer.function = rtl8169_phy_timer;
6252
6253 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
6254
6255 rc = register_netdev(dev);
6256 if (rc < 0)
6257 goto err_out_msi_4;
6258
6259 pci_set_drvdata(pdev, dev);
6260
92a7c4e7
FR		 6261 netif_info(tp, probe, dev, "%s at 0x%p, %pM, XID %08x IRQ %d\n",
6262 rtl_chip_infos[chipset].name, ioaddr, dev->dev_addr,
6263 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), pdev->irq);
3b6cf25d
FR		 6264 if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
6265 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
6266 "tx checksumming: %s]\n",
6267 rtl_chip_infos[chipset].jumbo_max,
6268 rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
6269 }
6270
6271 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
6272 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
6273 tp->mac_version == RTL_GIGA_MAC_VER_31) {
6274 rtl8168_driver_start(tp);
6275 }
6276
6277 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
6278
6279 if (pci_dev_run_wake(pdev))
6280 pm_runtime_put_noidle(&pdev->dev);
6281
6282 netif_carrier_off(dev);
6283
6284out:
6285 return rc;
6286
6287err_out_msi_4:
6288 rtl_disable_msi(pdev, tp);
6289 iounmap(ioaddr);
6290err_out_free_res_3:
6291 pci_release_regions(pdev);
6292err_out_mwi_2:
6293 pci_clear_mwi(pdev);
6294 pci_disable_device(pdev);
6295err_out_free_dev_1:
6296 free_netdev(dev);
6297 goto out;
6298}
6299
1da177e4
LT		 6300static struct pci_driver rtl8169_pci_driver = {
6301 .name = MODULENAME,
6302 .id_table = rtl8169_pci_tbl,
3b6cf25d 6303 .probe = rtl_init_one,
e27566ed 6304 .remove = __devexit_p(rtl_remove_one),
1765f95d 6305 .shutdown = rtl_shutdown,
861ab440 6306 .driver.pm = RTL8169_PM_OPS,
1da177e4
LT		 6307};
6308
07d3f51f 6309static int __init rtl8169_init_module(void)
1da177e4 6310{
29917620 6311 return pci_register_driver(&rtl8169_pci_driver);
1da177e4
LT		 6312}
6313
07d3f51f 6314static void __exit rtl8169_cleanup_module(void)
1da177e4
LT		 6315{
6316 pci_unregister_driver(&rtl8169_pci_driver);
6317}
6318
6319module_init(rtl8169_init_module);
6320module_exit(rtl8169_cleanup_module);
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