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r8169: Update PHY settings of RTL8111G
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / realtek / r8169.c
CommitLineData
1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
18#include <linux/mii.h>
19#include <linux/if_vlan.h>
20#include <linux/crc32.h>
21#include <linux/in.h>
22#include <linux/ip.h>
23#include <linux/tcp.h>
24#include <linux/init.h>
a6b7a407 25#include <linux/interrupt.h>
1da177e4 26#include <linux/dma-mapping.h>
e1759441 27#include <linux/pm_runtime.h>
bca03d5f 28#include <linux/firmware.h>
ba04c7c9 29#include <linux/pci-aspm.h>
70c71606 30#include <linux/prefetch.h>
1da177e4
LT		 31
32#include <asm/io.h>
33#include <asm/irq.h>
34
865c652d 35#define RTL8169_VERSION "2.3LK-NAPI"
1da177e4
LT		 36#define MODULENAME "r8169"
37#define PFX MODULENAME ": "
38
bca03d5f 39#define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
40#define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
01dc7fec 41#define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
42#define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
70090424 43#define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
c2218925
HW		 44#define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
45#define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
5a5e4443 46#define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
7e18dca1 47#define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
b3d7b2f2 48#define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
5598bfe5 49#define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
c558386b 50#define FIRMWARE_8168G_1 "rtl_nic/rtl8168g-1.fw"
bca03d5f 51
1da177e4
LT		 52#ifdef RTL8169_DEBUG
53#define assert(expr) \
5b0384f4
FR		 54 if (!(expr)) { \
55 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
b39d66a8 56 #expr,__FILE__,__func__,__LINE__); \
5b0384f4 57 }
06fa7358
JP		 58#define dprintk(fmt, args...) \
59 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
1da177e4
LT		 60#else
61#define assert(expr) do {} while (0)
62#define dprintk(fmt, args...) do {} while (0)
63#endif /* RTL8169_DEBUG */
64
b57b7e5a 65#define R8169_MSG_DEFAULT \
f0e837d9 66 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 67
477206a0
JD		 68#define TX_SLOTS_AVAIL(tp) \
69 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
70
71/* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
72#define TX_FRAGS_READY_FOR(tp,nr_frags) \
73 (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
1da177e4 74
1da177e4
LT		 75/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
76 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 77static const int multicast_filter_limit = 32;
1da177e4 78
9c14ceaf 79#define MAX_READ_REQUEST_SHIFT 12
aee77e4a 80#define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
1da177e4
LT		 81#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
82
83#define R8169_REGS_SIZE 256
84#define R8169_NAPI_WEIGHT 64
85#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
9fba0812 86#define NUM_RX_DESC 256U /* Number of Rx descriptor registers */
1da177e4
LT		 87#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
88#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
89
90#define RTL8169_TX_TIMEOUT (6*HZ)
91#define RTL8169_PHY_TIMEOUT (10*HZ)
92
93/* write/read MMIO register */
94#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
95#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
96#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
97#define RTL_R8(reg) readb (ioaddr + (reg))
98#define RTL_R16(reg) readw (ioaddr + (reg))
06f555f3 99#define RTL_R32(reg) readl (ioaddr + (reg))
1da177e4
LT		 100
101enum mac_version {
85bffe6c
FR		 102 RTL_GIGA_MAC_VER_01 = 0,
103 RTL_GIGA_MAC_VER_02,
104 RTL_GIGA_MAC_VER_03,
105 RTL_GIGA_MAC_VER_04,
106 RTL_GIGA_MAC_VER_05,
107 RTL_GIGA_MAC_VER_06,
108 RTL_GIGA_MAC_VER_07,
109 RTL_GIGA_MAC_VER_08,
110 RTL_GIGA_MAC_VER_09,
111 RTL_GIGA_MAC_VER_10,
112 RTL_GIGA_MAC_VER_11,
113 RTL_GIGA_MAC_VER_12,
114 RTL_GIGA_MAC_VER_13,
115 RTL_GIGA_MAC_VER_14,
116 RTL_GIGA_MAC_VER_15,
117 RTL_GIGA_MAC_VER_16,
118 RTL_GIGA_MAC_VER_17,
119 RTL_GIGA_MAC_VER_18,
120 RTL_GIGA_MAC_VER_19,
121 RTL_GIGA_MAC_VER_20,
122 RTL_GIGA_MAC_VER_21,
123 RTL_GIGA_MAC_VER_22,
124 RTL_GIGA_MAC_VER_23,
125 RTL_GIGA_MAC_VER_24,
126 RTL_GIGA_MAC_VER_25,
127 RTL_GIGA_MAC_VER_26,
128 RTL_GIGA_MAC_VER_27,
129 RTL_GIGA_MAC_VER_28,
130 RTL_GIGA_MAC_VER_29,
131 RTL_GIGA_MAC_VER_30,
132 RTL_GIGA_MAC_VER_31,
133 RTL_GIGA_MAC_VER_32,
134 RTL_GIGA_MAC_VER_33,
70090424 135 RTL_GIGA_MAC_VER_34,
c2218925
HW		 136 RTL_GIGA_MAC_VER_35,
137 RTL_GIGA_MAC_VER_36,
7e18dca1 138 RTL_GIGA_MAC_VER_37,
b3d7b2f2 139 RTL_GIGA_MAC_VER_38,
5598bfe5 140 RTL_GIGA_MAC_VER_39,
c558386b
HW		 141 RTL_GIGA_MAC_VER_40,
142 RTL_GIGA_MAC_VER_41,
85bffe6c 143 RTL_GIGA_MAC_NONE = 0xff,
1da177e4
LT		 144};
145
2b7b4318
FR		 146enum rtl_tx_desc_version {
147 RTL_TD_0 = 0,
148 RTL_TD_1 = 1,
149};
150
d58d46b5
FR		 151#define JUMBO_1K ETH_DATA_LEN
152#define JUMBO_4K (4*1024 - ETH_HLEN - 2)
153#define JUMBO_6K (6*1024 - ETH_HLEN - 2)
154#define JUMBO_7K (7*1024 - ETH_HLEN - 2)
155#define JUMBO_9K (9*1024 - ETH_HLEN - 2)
156
157#define _R(NAME,TD,FW,SZ,B) { \
158 .name = NAME, \
159 .txd_version = TD, \
160 .fw_name = FW, \
161 .jumbo_max = SZ, \
162 .jumbo_tx_csum = B \
163}
1da177e4 164
3c6bee1d 165static const struct {
1da177e4 166 const char *name;
2b7b4318 167 enum rtl_tx_desc_version txd_version;
953a12cc 168 const char *fw_name;
d58d46b5
FR		 169 u16 jumbo_max;
170 bool jumbo_tx_csum;
85bffe6c
FR		 171} rtl_chip_infos[] = {
172 /* PCI devices. */
173 [RTL_GIGA_MAC_VER_01] =
d58d46b5 174 _R("RTL8169", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 175 [RTL_GIGA_MAC_VER_02] =
d58d46b5 176 _R("RTL8169s", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 177 [RTL_GIGA_MAC_VER_03] =
d58d46b5 178 _R("RTL8110s", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 179 [RTL_GIGA_MAC_VER_04] =
d58d46b5 180 _R("RTL8169sb/8110sb", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 181 [RTL_GIGA_MAC_VER_05] =
d58d46b5 182 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 183 [RTL_GIGA_MAC_VER_06] =
d58d46b5 184 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c
FR		 185 /* PCI-E devices. */
186 [RTL_GIGA_MAC_VER_07] =
d58d46b5 187 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
85bffe6c 188 [RTL_GIGA_MAC_VER_08] =
d58d46b5 189 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
85bffe6c 190 [RTL_GIGA_MAC_VER_09] =
d58d46b5 191 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
85bffe6c 192 [RTL_GIGA_MAC_VER_10] =
d58d46b5 193 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 194 [RTL_GIGA_MAC_VER_11] =
d58d46b5 195 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
85bffe6c 196 [RTL_GIGA_MAC_VER_12] =
d58d46b5 197 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
85bffe6c 198 [RTL_GIGA_MAC_VER_13] =
d58d46b5 199 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 200 [RTL_GIGA_MAC_VER_14] =
d58d46b5 201 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 202 [RTL_GIGA_MAC_VER_15] =
d58d46b5 203 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 204 [RTL_GIGA_MAC_VER_16] =
d58d46b5 205 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 206 [RTL_GIGA_MAC_VER_17] =
d58d46b5 207 _R("RTL8168b/8111b", RTL_TD_1, NULL, JUMBO_4K, false),
85bffe6c 208 [RTL_GIGA_MAC_VER_18] =
d58d46b5 209 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 210 [RTL_GIGA_MAC_VER_19] =
d58d46b5 211 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 212 [RTL_GIGA_MAC_VER_20] =
d58d46b5 213 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 214 [RTL_GIGA_MAC_VER_21] =
d58d46b5 215 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 216 [RTL_GIGA_MAC_VER_22] =
d58d46b5 217 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 218 [RTL_GIGA_MAC_VER_23] =
d58d46b5 219 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 220 [RTL_GIGA_MAC_VER_24] =
d58d46b5 221 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 222 [RTL_GIGA_MAC_VER_25] =
d58d46b5
FR		 223 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1,
224 JUMBO_9K, false),
85bffe6c 225 [RTL_GIGA_MAC_VER_26] =
d58d46b5
FR		 226 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2,
227 JUMBO_9K, false),
85bffe6c 228 [RTL_GIGA_MAC_VER_27] =
d58d46b5 229 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
85bffe6c 230 [RTL_GIGA_MAC_VER_28] =
d58d46b5 231 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
85bffe6c 232 [RTL_GIGA_MAC_VER_29] =
d58d46b5
FR		 233 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
234 JUMBO_1K, true),
85bffe6c 235 [RTL_GIGA_MAC_VER_30] =
d58d46b5
FR		 236 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
237 JUMBO_1K, true),
85bffe6c 238 [RTL_GIGA_MAC_VER_31] =
d58d46b5 239 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
85bffe6c 240 [RTL_GIGA_MAC_VER_32] =
d58d46b5
FR		 241 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1,
242 JUMBO_9K, false),
85bffe6c 243 [RTL_GIGA_MAC_VER_33] =
d58d46b5
FR		 244 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2,
245 JUMBO_9K, false),
70090424 246 [RTL_GIGA_MAC_VER_34] =
d58d46b5
FR		 247 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
248 JUMBO_9K, false),
c2218925 249 [RTL_GIGA_MAC_VER_35] =
d58d46b5
FR		 250 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_1,
251 JUMBO_9K, false),
c2218925 252 [RTL_GIGA_MAC_VER_36] =
d58d46b5
FR		 253 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_2,
254 JUMBO_9K, false),
7e18dca1
HW		 255 [RTL_GIGA_MAC_VER_37] =
256 _R("RTL8402", RTL_TD_1, FIRMWARE_8402_1,
257 JUMBO_1K, true),
b3d7b2f2
HW		 258 [RTL_GIGA_MAC_VER_38] =
259 _R("RTL8411", RTL_TD_1, FIRMWARE_8411_1,
260 JUMBO_9K, false),
5598bfe5
HW		 261 [RTL_GIGA_MAC_VER_39] =
262 _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_1,
263 JUMBO_1K, true),
c558386b
HW		 264 [RTL_GIGA_MAC_VER_40] =
265 _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_1,
266 JUMBO_9K, false),
267 [RTL_GIGA_MAC_VER_41] =
268 _R("RTL8168g/8111g", RTL_TD_1, NULL, JUMBO_9K, false),
953a12cc 269};
85bffe6c 270#undef _R
953a12cc 271
bcf0bf90
FR		 272enum cfg_version {
273 RTL_CFG_0 = 0x00,
274 RTL_CFG_1,
275 RTL_CFG_2
276};
277
a3aa1884 278static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
bcf0bf90 279 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 280 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
d81bf551 281 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 282 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90 283 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
2a35cfa5
FR		 284 { PCI_VENDOR_ID_DLINK, 0x4300,
285 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0, RTL_CFG_1 },
bcf0bf90 286 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
93a3aa25 287 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 },
bc1660b5 288 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 289 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
290 { PCI_VENDOR_ID_LINKSYS, 0x1032,
291 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
11d2e282
CM		 292 { 0x0001, 0x8168,
293 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
1da177e4
LT		 294 {0,},
295};
296
297MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
298
6f0333b8 299static int rx_buf_sz = 16383;
4300e8c7 300static int use_dac;
b57b7e5a
SH		 301static struct {
302 u32 msg_enable;
303} debug = { -1 };
1da177e4 304
07d3f51f
FR		 305enum rtl_registers {
306 MAC0 = 0, /* Ethernet hardware address. */
773d2021 307 MAC4 = 4,
07d3f51f
FR		 308 MAR0 = 8, /* Multicast filter. */
309 CounterAddrLow = 0x10,
310 CounterAddrHigh = 0x14,
311 TxDescStartAddrLow = 0x20,
312 TxDescStartAddrHigh = 0x24,
313 TxHDescStartAddrLow = 0x28,
314 TxHDescStartAddrHigh = 0x2c,
315 FLASH = 0x30,
316 ERSR = 0x36,
317 ChipCmd = 0x37,
318 TxPoll = 0x38,
319 IntrMask = 0x3c,
320 IntrStatus = 0x3e,
4f6b00e5 321
07d3f51f 322 TxConfig = 0x40,
4f6b00e5
HW		 323#define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
324#define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
2b7b4318 325
4f6b00e5
HW		 326 RxConfig = 0x44,
327#define RX128_INT_EN (1 << 15) /* 8111c and later */
328#define RX_MULTI_EN (1 << 14) /* 8111c only */
329#define RXCFG_FIFO_SHIFT 13
330 /* No threshold before first PCI xfer */
331#define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
332#define RXCFG_DMA_SHIFT 8
333 /* Unlimited maximum PCI burst. */
334#define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
2b7b4318 335
07d3f51f
FR		 336 RxMissed = 0x4c,
337 Cfg9346 = 0x50,
338 Config0 = 0x51,
339 Config1 = 0x52,
340 Config2 = 0x53,
d387b427
FR		 341#define PME_SIGNAL (1 << 5) /* 8168c and later */
342
07d3f51f
FR		 343 Config3 = 0x54,
344 Config4 = 0x55,
345 Config5 = 0x56,
346 MultiIntr = 0x5c,
347 PHYAR = 0x60,
07d3f51f
FR		 348 PHYstatus = 0x6c,
349 RxMaxSize = 0xda,
350 CPlusCmd = 0xe0,
351 IntrMitigate = 0xe2,
352 RxDescAddrLow = 0xe4,
353 RxDescAddrHigh = 0xe8,
f0298f81 354 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
355
356#define NoEarlyTx 0x3f /* Max value : no early transmit. */
357
358 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
359
360#define TxPacketMax (8064 >> 7)
3090bd9a 361#define EarlySize 0x27
f0298f81 362
07d3f51f
FR		 363 FuncEvent = 0xf0,
364 FuncEventMask = 0xf4,
365 FuncPresetState = 0xf8,
366 FuncForceEvent = 0xfc,
1da177e4
LT		 367};
368
f162a5d1
FR		 369enum rtl8110_registers {
370 TBICSR = 0x64,
371 TBI_ANAR = 0x68,
372 TBI_LPAR = 0x6a,
373};
374
375enum rtl8168_8101_registers {
376 CSIDR = 0x64,
377 CSIAR = 0x68,
378#define CSIAR_FLAG 0x80000000
379#define CSIAR_WRITE_CMD 0x80000000
380#define CSIAR_BYTE_ENABLE 0x0f
381#define CSIAR_BYTE_ENABLE_SHIFT 12
382#define CSIAR_ADDR_MASK 0x0fff
7e18dca1
HW		 383#define CSIAR_FUNC_CARD 0x00000000
384#define CSIAR_FUNC_SDIO 0x00010000
385#define CSIAR_FUNC_NIC 0x00020000
065c27c1 386 PMCH = 0x6f,
f162a5d1
FR		 387 EPHYAR = 0x80,
388#define EPHYAR_FLAG 0x80000000
389#define EPHYAR_WRITE_CMD 0x80000000
390#define EPHYAR_REG_MASK 0x1f
391#define EPHYAR_REG_SHIFT 16
392#define EPHYAR_DATA_MASK 0xffff
5a5e4443 393 DLLPR = 0xd0,
4f6b00e5 394#define PFM_EN (1 << 6)
f162a5d1
FR		 395 DBG_REG = 0xd1,
396#define FIX_NAK_1 (1 << 4)
397#define FIX_NAK_2 (1 << 3)
5a5e4443
HW		 398 TWSI = 0xd2,
399 MCU = 0xd3,
4f6b00e5 400#define NOW_IS_OOB (1 << 7)
c558386b
HW		 401#define TX_EMPTY (1 << 5)
402#define RX_EMPTY (1 << 4)
403#define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
5a5e4443
HW		 404#define EN_NDP (1 << 3)
405#define EN_OOB_RESET (1 << 2)
c558386b 406#define LINK_LIST_RDY (1 << 1)
daf9df6d 407 EFUSEAR = 0xdc,
408#define EFUSEAR_FLAG 0x80000000
409#define EFUSEAR_WRITE_CMD 0x80000000
410#define EFUSEAR_READ_CMD 0x00000000
411#define EFUSEAR_REG_MASK 0x03ff
412#define EFUSEAR_REG_SHIFT 8
413#define EFUSEAR_DATA_MASK 0xff
f162a5d1
FR		 414};
415
c0e45c1c 416enum rtl8168_registers {
4f6b00e5
HW		 417 LED_FREQ = 0x1a,
418 EEE_LED = 0x1b,
b646d900 419 ERIDR = 0x70,
420 ERIAR = 0x74,
421#define ERIAR_FLAG 0x80000000
422#define ERIAR_WRITE_CMD 0x80000000
423#define ERIAR_READ_CMD 0x00000000
424#define ERIAR_ADDR_BYTE_ALIGN 4
b646d900 425#define ERIAR_TYPE_SHIFT 16
4f6b00e5
HW		 426#define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
427#define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
428#define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
429#define ERIAR_MASK_SHIFT 12
430#define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
431#define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
c558386b 432#define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
4f6b00e5 433#define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
c0e45c1c 434 EPHY_RXER_NUM = 0x7c,
435 OCPDR = 0xb0, /* OCP GPHY access */
436#define OCPDR_WRITE_CMD 0x80000000
437#define OCPDR_READ_CMD 0x00000000
438#define OCPDR_REG_MASK 0x7f
439#define OCPDR_GPHY_REG_SHIFT 16
440#define OCPDR_DATA_MASK 0xffff
441 OCPAR = 0xb4,
442#define OCPAR_FLAG 0x80000000
443#define OCPAR_GPHY_WRITE_CMD 0x8000f060
444#define OCPAR_GPHY_READ_CMD 0x0000f060
c558386b 445 GPHY_OCP = 0xb8,
01dc7fec 446 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
447 MISC = 0xf0, /* 8168e only. */
cecb5fd7 448#define TXPLA_RST (1 << 29)
5598bfe5 449#define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
4f6b00e5 450#define PWM_EN (1 << 22)
c558386b 451#define RXDV_GATED_EN (1 << 19)
5598bfe5 452#define EARLY_TALLY_EN (1 << 16)
c0e45c1c 453};
454
07d3f51f 455enum rtl_register_content {
1da177e4 456 /* InterruptStatusBits */
07d3f51f
FR		 457 SYSErr = 0x8000,
458 PCSTimeout = 0x4000,
459 SWInt = 0x0100,
460 TxDescUnavail = 0x0080,
461 RxFIFOOver = 0x0040,
462 LinkChg = 0x0020,
463 RxOverflow = 0x0010,
464 TxErr = 0x0008,
465 TxOK = 0x0004,
466 RxErr = 0x0002,
467 RxOK = 0x0001,
1da177e4
LT		 468
469 /* RxStatusDesc */
e03f33af 470 RxBOVF = (1 << 24),
9dccf611
FR		 471 RxFOVF = (1 << 23),
472 RxRWT = (1 << 22),
473 RxRES = (1 << 21),
474 RxRUNT = (1 << 20),
475 RxCRC = (1 << 19),
1da177e4
LT		 476
477 /* ChipCmdBits */
4f6b00e5 478 StopReq = 0x80,
07d3f51f
FR		 479 CmdReset = 0x10,
480 CmdRxEnb = 0x08,
481 CmdTxEnb = 0x04,
482 RxBufEmpty = 0x01,
1da177e4 483
275391a4
FR		 484 /* TXPoll register p.5 */
485 HPQ = 0x80, /* Poll cmd on the high prio queue */
486 NPQ = 0x40, /* Poll cmd on the low prio queue */
487 FSWInt = 0x01, /* Forced software interrupt */
488
1da177e4 489 /* Cfg9346Bits */
07d3f51f
FR		 490 Cfg9346_Lock = 0x00,
491 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 492
493 /* rx_mode_bits */
07d3f51f
FR		 494 AcceptErr = 0x20,
495 AcceptRunt = 0x10,
496 AcceptBroadcast = 0x08,
497 AcceptMulticast = 0x04,
498 AcceptMyPhys = 0x02,
499 AcceptAllPhys = 0x01,
1687b566 500#define RX_CONFIG_ACCEPT_MASK 0x3f
1da177e4 501
1da177e4
LT		 502 /* TxConfigBits */
503 TxInterFrameGapShift = 24,
504 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
505
5d06a99f 506 /* Config1 register p.24 */
f162a5d1
FR		 507 LEDS1 = (1 << 7),
508 LEDS0 = (1 << 6),
f162a5d1
FR		 509 Speed_down = (1 << 4),
510 MEMMAP = (1 << 3),
511 IOMAP = (1 << 2),
512 VPD = (1 << 1),
5d06a99f
FR		 513 PMEnable = (1 << 0), /* Power Management Enable */
514
6dccd16b 515 /* Config2 register p. 25 */
2ca6cf06 516 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
6dccd16b
FR		 517 PCI_Clock_66MHz = 0x01,
518 PCI_Clock_33MHz = 0x00,
519
61a4dcc2
FR		 520 /* Config3 register p.25 */
521 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
522 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
d58d46b5 523 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
f162a5d1 524 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
61a4dcc2 525
d58d46b5
FR		 526 /* Config4 register */
527 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
528
5d06a99f 529 /* Config5 register p.27 */
61a4dcc2
FR		 530 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
531 MWF = (1 << 5), /* Accept Multicast wakeup frame */
532 UWF = (1 << 4), /* Accept Unicast wakeup frame */
cecb5fd7 533 Spi_en = (1 << 3),
61a4dcc2 534 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f
FR		 535 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
536
1da177e4
LT		 537 /* TBICSR p.28 */
538 TBIReset = 0x80000000,
539 TBILoopback = 0x40000000,
540 TBINwEnable = 0x20000000,
541 TBINwRestart = 0x10000000,
542 TBILinkOk = 0x02000000,
543 TBINwComplete = 0x01000000,
544
545 /* CPlusCmd p.31 */
f162a5d1
FR		 546 EnableBist = (1 << 15), // 8168 8101
547 Mac_dbgo_oe = (1 << 14), // 8168 8101
548 Normal_mode = (1 << 13), // unused
549 Force_half_dup = (1 << 12), // 8168 8101
550 Force_rxflow_en = (1 << 11), // 8168 8101
551 Force_txflow_en = (1 << 10), // 8168 8101
552 Cxpl_dbg_sel = (1 << 9), // 8168 8101
553 ASF = (1 << 8), // 8168 8101
554 PktCntrDisable = (1 << 7), // 8168 8101
555 Mac_dbgo_sel = 0x001c, // 8168
1da177e4
LT		 556 RxVlan = (1 << 6),
557 RxChkSum = (1 << 5),
558 PCIDAC = (1 << 4),
559 PCIMulRW = (1 << 3),
0e485150
FR		 560 INTT_0 = 0x0000, // 8168
561 INTT_1 = 0x0001, // 8168
562 INTT_2 = 0x0002, // 8168
563 INTT_3 = 0x0003, // 8168
1da177e4
LT		 564
565 /* rtl8169_PHYstatus */
07d3f51f
FR		 566 TBI_Enable = 0x80,
567 TxFlowCtrl = 0x40,
568 RxFlowCtrl = 0x20,
569 _1000bpsF = 0x10,
570 _100bps = 0x08,
571 _10bps = 0x04,
572 LinkStatus = 0x02,
573 FullDup = 0x01,
1da177e4 574
1da177e4 575 /* _TBICSRBit */
07d3f51f 576 TBILinkOK = 0x02000000,
d4a3a0fc
SH		 577
578 /* DumpCounterCommand */
07d3f51f 579 CounterDump = 0x8,
1da177e4
LT		 580};
581
2b7b4318
FR		 582enum rtl_desc_bit {
583 /* First doubleword. */
1da177e4
LT		 584 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
585 RingEnd = (1 << 30), /* End of descriptor ring */
586 FirstFrag = (1 << 29), /* First segment of a packet */
587 LastFrag = (1 << 28), /* Final segment of a packet */
2b7b4318
FR		 588};
589
590/* Generic case. */
591enum rtl_tx_desc_bit {
592 /* First doubleword. */
593 TD_LSO = (1 << 27), /* Large Send Offload */
594#define TD_MSS_MAX 0x07ffu /* MSS value */
1da177e4 595
2b7b4318
FR		 596 /* Second doubleword. */
597 TxVlanTag = (1 << 17), /* Add VLAN tag */
598};
599
600/* 8169, 8168b and 810x except 8102e. */
601enum rtl_tx_desc_bit_0 {
602 /* First doubleword. */
603#define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
604 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
605 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
606 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
607};
608
609/* 8102e, 8168c and beyond. */
610enum rtl_tx_desc_bit_1 {
611 /* Second doubleword. */
612#define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
613 TD1_IP_CS = (1 << 29), /* Calculate IP checksum */
614 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
615 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
616};
1da177e4 617
2b7b4318
FR		 618static const struct rtl_tx_desc_info {
619 struct {
620 u32 udp;
621 u32 tcp;
622 } checksum;
623 u16 mss_shift;
624 u16 opts_offset;
625} tx_desc_info [] = {
626 [RTL_TD_0] = {
627 .checksum = {
628 .udp = TD0_IP_CS | TD0_UDP_CS,
629 .tcp = TD0_IP_CS | TD0_TCP_CS
630 },
631 .mss_shift = TD0_MSS_SHIFT,
632 .opts_offset = 0
633 },
634 [RTL_TD_1] = {
635 .checksum = {
636 .udp = TD1_IP_CS | TD1_UDP_CS,
637 .tcp = TD1_IP_CS | TD1_TCP_CS
638 },
639 .mss_shift = TD1_MSS_SHIFT,
640 .opts_offset = 1
641 }
642};
643
644enum rtl_rx_desc_bit {
1da177e4
LT		 645 /* Rx private */
646 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
647 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
648
649#define RxProtoUDP (PID1)
650#define RxProtoTCP (PID0)
651#define RxProtoIP (PID1 | PID0)
652#define RxProtoMask RxProtoIP
653
654 IPFail = (1 << 16), /* IP checksum failed */
655 UDPFail = (1 << 15), /* UDP/IP checksum failed */
656 TCPFail = (1 << 14), /* TCP/IP checksum failed */
657 RxVlanTag = (1 << 16), /* VLAN tag available */
658};
659
660#define RsvdMask 0x3fffc000
661
662struct TxDesc {
6cccd6e7
REB		 663 __le32 opts1;
664 __le32 opts2;
665 __le64 addr;
1da177e4
LT		 666};
667
668struct RxDesc {
6cccd6e7
REB		 669 __le32 opts1;
670 __le32 opts2;
671 __le64 addr;
1da177e4
LT		 672};
673
674struct ring_info {
675 struct sk_buff *skb;
676 u32 len;
677 u8 __pad[sizeof(void *) - sizeof(u32)];
678};
679
f23e7fda 680enum features {
ccdffb9a
FR		 681 RTL_FEATURE_WOL = (1 << 0),
682 RTL_FEATURE_MSI = (1 << 1),
683 RTL_FEATURE_GMII = (1 << 2),
f23e7fda
FR		 684};
685
355423d0
IV		 686struct rtl8169_counters {
687 __le64 tx_packets;
688 __le64 rx_packets;
689 __le64 tx_errors;
690 __le32 rx_errors;
691 __le16 rx_missed;
692 __le16 align_errors;
693 __le32 tx_one_collision;
694 __le32 tx_multi_collision;
695 __le64 rx_unicast;
696 __le64 rx_broadcast;
697 __le32 rx_multicast;
698 __le16 tx_aborted;
699 __le16 tx_underun;
700};
701
da78dbff 702enum rtl_flag {
6c4a70c5 703 RTL_FLAG_TASK_ENABLED,
da78dbff
FR		 704 RTL_FLAG_TASK_SLOW_PENDING,
705 RTL_FLAG_TASK_RESET_PENDING,
706 RTL_FLAG_TASK_PHY_PENDING,
707 RTL_FLAG_MAX
708};
709
8027aa24
JW		 710struct rtl8169_stats {
711 u64 packets;
712 u64 bytes;
713 struct u64_stats_sync syncp;
714};
715
1da177e4
LT		 716struct rtl8169_private {
717 void __iomem *mmio_addr; /* memory map physical address */
cecb5fd7 718 struct pci_dev *pci_dev;
c4028958 719 struct net_device *dev;
bea3348e 720 struct napi_struct napi;
b57b7e5a 721 u32 msg_enable;
2b7b4318
FR		 722 u16 txd_version;
723 u16 mac_version;
1da177e4
LT		 724 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
725 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
1da177e4 726 u32 dirty_tx;
8027aa24
JW		 727 struct rtl8169_stats rx_stats;
728 struct rtl8169_stats tx_stats;
1da177e4
LT		 729 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
730 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
731 dma_addr_t TxPhyAddr;
732 dma_addr_t RxPhyAddr;
6f0333b8 733 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
1da177e4 734 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
1da177e4
LT		 735 struct timer_list timer;
736 u16 cp_cmd;
da78dbff
FR		 737
738 u16 event_slow;
c0e45c1c 739
740 struct mdio_ops {
24192210
FR		 741 void (*write)(struct rtl8169_private *, int, int);
742 int (*read)(struct rtl8169_private *, int);
c0e45c1c 743 } mdio_ops;
744
065c27c1 745 struct pll_power_ops {
746 void (*down)(struct rtl8169_private *);
747 void (*up)(struct rtl8169_private *);
748 } pll_power_ops;
749
d58d46b5
FR		 750 struct jumbo_ops {
751 void (*enable)(struct rtl8169_private *);
752 void (*disable)(struct rtl8169_private *);
753 } jumbo_ops;
754
beb1fe18 755 struct csi_ops {
52989f0e
FR		 756 void (*write)(struct rtl8169_private *, int, int);
757 u32 (*read)(struct rtl8169_private *, int);
beb1fe18
HW		 758 } csi_ops;
759
54405cde 760 int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
ccdffb9a 761 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
4da19633 762 void (*phy_reset_enable)(struct rtl8169_private *tp);
07ce4064 763 void (*hw_start)(struct net_device *);
4da19633 764 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
1da177e4 765 unsigned int (*link_ok)(void __iomem *);
8b4ab28d 766 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
4422bcd4
FR		 767
768 struct {
da78dbff
FR		 769 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
770 struct mutex mutex;
4422bcd4
FR		 771 struct work_struct work;
772 } wk;
773
f23e7fda 774 unsigned features;
ccdffb9a
FR		 775
776 struct mii_if_info mii;
355423d0 777 struct rtl8169_counters counters;
e1759441 778 u32 saved_wolopts;
e03f33af 779 u32 opts1_mask;
f1e02ed1 780
b6ffd97f
FR		 781 struct rtl_fw {
782 const struct firmware *fw;
1c361efb
FR		 783
784#define RTL_VER_SIZE 32
785
786 char version[RTL_VER_SIZE];
787
788 struct rtl_fw_phy_action {
789 __le32 *code;
790 size_t size;
791 } phy_action;
b6ffd97f 792 } *rtl_fw;
497888cf 793#define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
c558386b
HW		 794
795 u32 ocp_base;
1da177e4
LT		 796};
797
979b6c13 798MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 799MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 800module_param(use_dac, int, 0);
4300e8c7 801MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 802module_param_named(debug, debug.msg_enable, int, 0);
803MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 804MODULE_LICENSE("GPL");
805MODULE_VERSION(RTL8169_VERSION);
bca03d5f 806MODULE_FIRMWARE(FIRMWARE_8168D_1);
807MODULE_FIRMWARE(FIRMWARE_8168D_2);
01dc7fec 808MODULE_FIRMWARE(FIRMWARE_8168E_1);
809MODULE_FIRMWARE(FIRMWARE_8168E_2);
bbb8af75 810MODULE_FIRMWARE(FIRMWARE_8168E_3);
5a5e4443 811MODULE_FIRMWARE(FIRMWARE_8105E_1);
c2218925
HW		 812MODULE_FIRMWARE(FIRMWARE_8168F_1);
813MODULE_FIRMWARE(FIRMWARE_8168F_2);
7e18dca1 814MODULE_FIRMWARE(FIRMWARE_8402_1);
b3d7b2f2 815MODULE_FIRMWARE(FIRMWARE_8411_1);
5598bfe5 816MODULE_FIRMWARE(FIRMWARE_8106E_1);
c558386b 817MODULE_FIRMWARE(FIRMWARE_8168G_1);
1da177e4 818
da78dbff
FR		 819static void rtl_lock_work(struct rtl8169_private *tp)
820{
821 mutex_lock(&tp->wk.mutex);
822}
823
824static void rtl_unlock_work(struct rtl8169_private *tp)
825{
826 mutex_unlock(&tp->wk.mutex);
827}
828
d58d46b5
FR		 829static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
830{
7d7903b2
JL		 831 pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL,
832 PCI_EXP_DEVCTL_READRQ, force);
d58d46b5
FR		 833}
834
ffc46952
FR		 835struct rtl_cond {
836 bool (*check)(struct rtl8169_private *);
837 const char *msg;
838};
839
840static void rtl_udelay(unsigned int d)
841{
842 udelay(d);
843}
844
845static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
846 void (*delay)(unsigned int), unsigned int d, int n,
847 bool high)
848{
849 int i;
850
851 for (i = 0; i < n; i++) {
852 delay(d);
853 if (c->check(tp) == high)
854 return true;
855 }
82e316ef
FR		 856 netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
857 c->msg, !high, n, d);
ffc46952
FR		 858 return false;
859}
860
861static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
862 const struct rtl_cond *c,
863 unsigned int d, int n)
864{
865 return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
866}
867
868static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
869 const struct rtl_cond *c,
870 unsigned int d, int n)
871{
872 return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
873}
874
875static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
876 const struct rtl_cond *c,
877 unsigned int d, int n)
878{
879 return rtl_loop_wait(tp, c, msleep, d, n, true);
880}
881
882static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
883 const struct rtl_cond *c,
884 unsigned int d, int n)
885{
886 return rtl_loop_wait(tp, c, msleep, d, n, false);
887}
888
889#define DECLARE_RTL_COND(name) \
890static bool name ## _check(struct rtl8169_private *); \
891 \
892static const struct rtl_cond name = { \
893 .check = name ## _check, \
894 .msg = #name \
895}; \
896 \
897static bool name ## _check(struct rtl8169_private *tp)
898
899DECLARE_RTL_COND(rtl_ocpar_cond)
900{
901 void __iomem *ioaddr = tp->mmio_addr;
902
903 return RTL_R32(OCPAR) & OCPAR_FLAG;
904}
905
b646d900 906static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
907{
908 void __iomem *ioaddr = tp->mmio_addr;
b646d900 909
910 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
ffc46952
FR		 911
912 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
913 RTL_R32(OCPDR) : ~0;
b646d900 914}
915
916static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
917{
918 void __iomem *ioaddr = tp->mmio_addr;
b646d900 919
920 RTL_W32(OCPDR, data);
921 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
ffc46952
FR		 922
923 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
924}
925
926DECLARE_RTL_COND(rtl_eriar_cond)
927{
928 void __iomem *ioaddr = tp->mmio_addr;
929
930 return RTL_R32(ERIAR) & ERIAR_FLAG;
b646d900 931}
932
fac5b3ca 933static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
b646d900 934{
fac5b3ca 935 void __iomem *ioaddr = tp->mmio_addr;
b646d900 936
937 RTL_W8(ERIDR, cmd);
938 RTL_W32(ERIAR, 0x800010e8);
939 msleep(2);
ffc46952
FR		 940
941 if (!rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 5))
942 return;
b646d900 943
fac5b3ca 944 ocp_write(tp, 0x1, 0x30, 0x00000001);
b646d900 945}
946
947#define OOB_CMD_RESET 0x00
948#define OOB_CMD_DRIVER_START 0x05
949#define OOB_CMD_DRIVER_STOP 0x06
950
cecb5fd7
FR		 951static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
952{
953 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
954}
955
ffc46952 956DECLARE_RTL_COND(rtl_ocp_read_cond)
b646d900 957{
cecb5fd7 958 u16 reg;
b646d900 959
cecb5fd7 960 reg = rtl8168_get_ocp_reg(tp);
4804b3b3 961
ffc46952 962 return ocp_read(tp, 0x0f, reg) & 0x00000800;
b646d900 963}
964
ffc46952 965static void rtl8168_driver_start(struct rtl8169_private *tp)
b646d900 966{
ffc46952 967 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
b646d900 968
ffc46952
FR		 969 rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
970}
b646d900 971
ffc46952
FR		 972static void rtl8168_driver_stop(struct rtl8169_private *tp)
973{
974 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
4804b3b3 975
ffc46952 976 rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
b646d900 977}
978
4804b3b3 979static int r8168dp_check_dash(struct rtl8169_private *tp)
980{
cecb5fd7 981 u16 reg = rtl8168_get_ocp_reg(tp);
4804b3b3 982
cecb5fd7 983 return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
4804b3b3 984}
b646d900 985
c558386b
HW		 986static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
987{
988 if (reg & 0xffff0001) {
989 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
990 return true;
991 }
992 return false;
993}
994
995DECLARE_RTL_COND(rtl_ocp_gphy_cond)
996{
997 void __iomem *ioaddr = tp->mmio_addr;
998
999 return RTL_R32(GPHY_OCP) & OCPAR_FLAG;
1000}
1001
1002static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1003{
1004 void __iomem *ioaddr = tp->mmio_addr;
1005
1006 if (rtl_ocp_reg_failure(tp, reg))
1007 return;
1008
1009 RTL_W32(GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
1010
1011 rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
1012}
1013
1014static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
1015{
1016 void __iomem *ioaddr = tp->mmio_addr;
1017
1018 if (rtl_ocp_reg_failure(tp, reg))
1019 return 0;
1020
1021 RTL_W32(GPHY_OCP, reg << 15);
1022
1023 return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
1024 (RTL_R32(GPHY_OCP) & 0xffff) : ~0;
1025}
1026
c558386b
HW		 1027static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1028{
1029 void __iomem *ioaddr = tp->mmio_addr;
1030
1031 if (rtl_ocp_reg_failure(tp, reg))
1032 return;
1033
1034 RTL_W32(OCPDR, OCPAR_FLAG | (reg << 15) | data);
c558386b
HW		 1035}
1036
1037static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
1038{
1039 void __iomem *ioaddr = tp->mmio_addr;
1040
1041 if (rtl_ocp_reg_failure(tp, reg))
1042 return 0;
1043
1044 RTL_W32(OCPDR, reg << 15);
1045
3a83ad12 1046 return RTL_R32(OCPDR);
c558386b
HW		 1047}
1048
1049#define OCP_STD_PHY_BASE 0xa400
1050
1051static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
1052{
1053 if (reg == 0x1f) {
1054 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
1055 return;
1056 }
1057
1058 if (tp->ocp_base != OCP_STD_PHY_BASE)
1059 reg -= 0x10;
1060
1061 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
1062}
1063
1064static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
1065{
1066 if (tp->ocp_base != OCP_STD_PHY_BASE)
1067 reg -= 0x10;
1068
1069 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
1070}
1071
ffc46952
FR		 1072DECLARE_RTL_COND(rtl_phyar_cond)
1073{
1074 void __iomem *ioaddr = tp->mmio_addr;
1075
1076 return RTL_R32(PHYAR) & 0x80000000;
1077}
1078
24192210 1079static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
1da177e4 1080{
24192210 1081 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 1082
24192210 1083 RTL_W32(PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
1da177e4 1084
ffc46952 1085 rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
024a07ba 1086 /*
81a95f04
TT		 1087 * According to hardware specs a 20us delay is required after write
1088 * complete indication, but before sending next command.
024a07ba 1089 */
81a95f04 1090 udelay(20);
1da177e4
LT		 1091}
1092
24192210 1093static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1da177e4 1094{
24192210 1095 void __iomem *ioaddr = tp->mmio_addr;
ffc46952 1096 int value;
1da177e4 1097
24192210 1098 RTL_W32(PHYAR, 0x0 | (reg & 0x1f) << 16);
1da177e4 1099
ffc46952
FR		 1100 value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
1101 RTL_R32(PHYAR) & 0xffff : ~0;
1102
81a95f04
TT		 1103 /*
1104 * According to hardware specs a 20us delay is required after read
1105 * complete indication, but before sending next command.
1106 */
1107 udelay(20);
1108
1da177e4
LT		 1109 return value;
1110}
1111
24192210 1112static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
c0e45c1c 1113{
24192210 1114 void __iomem *ioaddr = tp->mmio_addr;
c0e45c1c 1115
24192210 1116 RTL_W32(OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
c0e45c1c 1117 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
1118 RTL_W32(EPHY_RXER_NUM, 0);
1119
ffc46952 1120 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
c0e45c1c 1121}
1122
24192210 1123static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
c0e45c1c 1124{
24192210
FR		 1125 r8168dp_1_mdio_access(tp, reg,
1126 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
c0e45c1c 1127}
1128
24192210 1129static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
c0e45c1c 1130{
24192210 1131 void __iomem *ioaddr = tp->mmio_addr;
c0e45c1c 1132
24192210 1133 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
c0e45c1c 1134
1135 mdelay(1);
1136 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
1137 RTL_W32(EPHY_RXER_NUM, 0);
1138
ffc46952
FR		 1139 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
1140 RTL_R32(OCPDR) & OCPDR_DATA_MASK : ~0;
c0e45c1c 1141}
1142
e6de30d6 1143#define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
1144
1145static void r8168dp_2_mdio_start(void __iomem *ioaddr)
1146{
1147 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1148}
1149
1150static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
1151{
1152 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1153}
1154
24192210 1155static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
e6de30d6 1156{
24192210
FR		 1157 void __iomem *ioaddr = tp->mmio_addr;
1158
e6de30d6 1159 r8168dp_2_mdio_start(ioaddr);
1160
24192210 1161 r8169_mdio_write(tp, reg, value);
e6de30d6 1162
1163 r8168dp_2_mdio_stop(ioaddr);
1164}
1165
24192210 1166static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
e6de30d6 1167{
24192210 1168 void __iomem *ioaddr = tp->mmio_addr;
e6de30d6 1169 int value;
1170
1171 r8168dp_2_mdio_start(ioaddr);
1172
24192210 1173 value = r8169_mdio_read(tp, reg);
e6de30d6 1174
1175 r8168dp_2_mdio_stop(ioaddr);
1176
1177 return value;
1178}
1179
4da19633 1180static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
dacf8154 1181{
24192210 1182 tp->mdio_ops.write(tp, location, val);
dacf8154
FR		 1183}
1184
4da19633 1185static int rtl_readphy(struct rtl8169_private *tp, int location)
1186{
24192210 1187 return tp->mdio_ops.read(tp, location);
4da19633 1188}
1189
1190static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1191{
1192 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1193}
1194
1195static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
daf9df6d 1196{
1197 int val;
1198
4da19633 1199 val = rtl_readphy(tp, reg_addr);
1200 rtl_writephy(tp, reg_addr, (val | p) & ~m);
daf9df6d 1201}
1202
ccdffb9a
FR		 1203static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1204 int val)
1205{
1206 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 1207
4da19633 1208 rtl_writephy(tp, location, val);
ccdffb9a
FR		 1209}
1210
1211static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1212{
1213 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 1214
4da19633 1215 return rtl_readphy(tp, location);
ccdffb9a
FR		 1216}
1217
ffc46952
FR		 1218DECLARE_RTL_COND(rtl_ephyar_cond)
1219{
1220 void __iomem *ioaddr = tp->mmio_addr;
1221
1222 return RTL_R32(EPHYAR) & EPHYAR_FLAG;
1223}
1224
fdf6fc06 1225static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
dacf8154 1226{
fdf6fc06 1227 void __iomem *ioaddr = tp->mmio_addr;
dacf8154
FR		 1228
1229 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1230 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1231
ffc46952
FR		 1232 rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1233
1234 udelay(10);
dacf8154
FR		 1235}
1236
fdf6fc06 1237static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
dacf8154 1238{
fdf6fc06 1239 void __iomem *ioaddr = tp->mmio_addr;
dacf8154
FR		 1240
1241 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1242
ffc46952
FR		 1243 return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1244 RTL_R32(EPHYAR) & EPHYAR_DATA_MASK : ~0;
dacf8154
FR		 1245}
1246
fdf6fc06
FR		 1247static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1248 u32 val, int type)
133ac40a 1249{
fdf6fc06 1250 void __iomem *ioaddr = tp->mmio_addr;
133ac40a
HW		 1251
1252 BUG_ON((addr & 3) || (mask == 0));
1253 RTL_W32(ERIDR, val);
1254 RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1255
ffc46952 1256 rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
133ac40a
HW		 1257}
1258
fdf6fc06 1259static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
133ac40a 1260{
fdf6fc06 1261 void __iomem *ioaddr = tp->mmio_addr;
133ac40a
HW		 1262
1263 RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1264
ffc46952
FR		 1265 return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1266 RTL_R32(ERIDR) : ~0;
133ac40a
HW		 1267}
1268
fdf6fc06
FR		 1269static void rtl_w1w0_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1270 u32 m, int type)
133ac40a
HW		 1271{
1272 u32 val;
1273
fdf6fc06
FR		 1274 val = rtl_eri_read(tp, addr, type);
1275 rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
133ac40a
HW		 1276}
1277
c28aa385 1278struct exgmac_reg {
1279 u16 addr;
1280 u16 mask;
1281 u32 val;
1282};
1283
fdf6fc06 1284static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
c28aa385 1285 const struct exgmac_reg *r, int len)
1286{
1287 while (len-- > 0) {
fdf6fc06 1288 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
c28aa385 1289 r++;
1290 }
1291}
1292
ffc46952
FR		 1293DECLARE_RTL_COND(rtl_efusear_cond)
1294{
1295 void __iomem *ioaddr = tp->mmio_addr;
1296
1297 return RTL_R32(EFUSEAR) & EFUSEAR_FLAG;
1298}
1299
fdf6fc06 1300static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
daf9df6d 1301{
fdf6fc06 1302 void __iomem *ioaddr = tp->mmio_addr;
daf9df6d 1303
1304 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1305
ffc46952
FR		 1306 return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1307 RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
daf9df6d 1308}
1309
9085cdfa
FR		 1310static u16 rtl_get_events(struct rtl8169_private *tp)
1311{
1312 void __iomem *ioaddr = tp->mmio_addr;
1313
1314 return RTL_R16(IntrStatus);
1315}
1316
1317static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1318{
1319 void __iomem *ioaddr = tp->mmio_addr;
1320
1321 RTL_W16(IntrStatus, bits);
1322 mmiowb();
1323}
1324
1325static void rtl_irq_disable(struct rtl8169_private *tp)
1326{
1327 void __iomem *ioaddr = tp->mmio_addr;
1328
1329 RTL_W16(IntrMask, 0);
1330 mmiowb();
1331}
1332
3e990ff5
FR		 1333static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1334{
1335 void __iomem *ioaddr = tp->mmio_addr;
1336
1337 RTL_W16(IntrMask, bits);
1338}
1339
da78dbff
FR		 1340#define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1341#define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1342#define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1343
1344static void rtl_irq_enable_all(struct rtl8169_private *tp)
1345{
1346 rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1347}
1348
811fd301 1349static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1da177e4 1350{
811fd301 1351 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 1352
9085cdfa 1353 rtl_irq_disable(tp);
da78dbff 1354 rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
811fd301 1355 RTL_R8(ChipCmd);
1da177e4
LT		 1356}
1357
4da19633 1358static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1da177e4 1359{
4da19633 1360 void __iomem *ioaddr = tp->mmio_addr;
1361
1da177e4
LT		 1362 return RTL_R32(TBICSR) & TBIReset;
1363}
1364
4da19633 1365static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1da177e4 1366{
4da19633 1367 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1da177e4
LT		 1368}
1369
1370static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1371{
1372 return RTL_R32(TBICSR) & TBILinkOk;
1373}
1374
1375static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1376{
1377 return RTL_R8(PHYstatus) & LinkStatus;
1378}
1379
4da19633 1380static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1da177e4 1381{
4da19633 1382 void __iomem *ioaddr = tp->mmio_addr;
1383
1da177e4
LT		 1384 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1385}
1386
4da19633 1387static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1da177e4
LT		 1388{
1389 unsigned int val;
1390
4da19633 1391 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1392 rtl_writephy(tp, MII_BMCR, val & 0xffff);
1da177e4
LT		 1393}
1394
70090424
HW		 1395static void rtl_link_chg_patch(struct rtl8169_private *tp)
1396{
1397 void __iomem *ioaddr = tp->mmio_addr;
1398 struct net_device *dev = tp->dev;
1399
1400 if (!netif_running(dev))
1401 return;
1402
b3d7b2f2
HW		 1403 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1404 tp->mac_version == RTL_GIGA_MAC_VER_38) {
70090424 1405 if (RTL_R8(PHYstatus) & _1000bpsF) {
fdf6fc06
FR		 1406 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1407 ERIAR_EXGMAC);
1408 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1409 ERIAR_EXGMAC);
70090424 1410 } else if (RTL_R8(PHYstatus) & _100bps) {
fdf6fc06
FR		 1411 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1412 ERIAR_EXGMAC);
1413 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1414 ERIAR_EXGMAC);
70090424 1415 } else {
fdf6fc06
FR		 1416 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1417 ERIAR_EXGMAC);
1418 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1419 ERIAR_EXGMAC);
70090424
HW		 1420 }
1421 /* Reset packet filter */
fdf6fc06 1422 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
70090424 1423 ERIAR_EXGMAC);
fdf6fc06 1424 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
70090424 1425 ERIAR_EXGMAC);
c2218925
HW		 1426 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1427 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1428 if (RTL_R8(PHYstatus) & _1000bpsF) {
fdf6fc06
FR		 1429 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1430 ERIAR_EXGMAC);
1431 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1432 ERIAR_EXGMAC);
c2218925 1433 } else {
fdf6fc06
FR		 1434 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1435 ERIAR_EXGMAC);
1436 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1437 ERIAR_EXGMAC);
c2218925 1438 }
7e18dca1
HW		 1439 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1440 if (RTL_R8(PHYstatus) & _10bps) {
fdf6fc06
FR		 1441 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1442 ERIAR_EXGMAC);
1443 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1444 ERIAR_EXGMAC);
7e18dca1 1445 } else {
fdf6fc06
FR		 1446 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1447 ERIAR_EXGMAC);
7e18dca1 1448 }
70090424
HW		 1449 }
1450}
1451
e4fbce74 1452static void __rtl8169_check_link_status(struct net_device *dev,
cecb5fd7
FR		 1453 struct rtl8169_private *tp,
1454 void __iomem *ioaddr, bool pm)
1da177e4 1455{
1da177e4 1456 if (tp->link_ok(ioaddr)) {
70090424 1457 rtl_link_chg_patch(tp);
e1759441 1458 /* This is to cancel a scheduled suspend if there's one. */
e4fbce74
RW		 1459 if (pm)
1460 pm_request_resume(&tp->pci_dev->dev);
1da177e4 1461 netif_carrier_on(dev);
1519e57f
FR		 1462 if (net_ratelimit())
1463 netif_info(tp, ifup, dev, "link up\n");
b57b7e5a 1464 } else {
1da177e4 1465 netif_carrier_off(dev);
bf82c189 1466 netif_info(tp, ifdown, dev, "link down\n");
e4fbce74 1467 if (pm)
10953db8 1468 pm_schedule_suspend(&tp->pci_dev->dev, 5000);
b57b7e5a 1469 }
1da177e4
LT		 1470}
1471
e4fbce74
RW		 1472static void rtl8169_check_link_status(struct net_device *dev,
1473 struct rtl8169_private *tp,
1474 void __iomem *ioaddr)
1475{
1476 __rtl8169_check_link_status(dev, tp, ioaddr, false);
1477}
1478
e1759441
RW		 1479#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1480
1481static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
61a4dcc2 1482{
61a4dcc2
FR		 1483 void __iomem *ioaddr = tp->mmio_addr;
1484 u8 options;
e1759441 1485 u32 wolopts = 0;
61a4dcc2
FR		 1486
1487 options = RTL_R8(Config1);
1488 if (!(options & PMEnable))
e1759441 1489 return 0;
61a4dcc2
FR		 1490
1491 options = RTL_R8(Config3);
1492 if (options & LinkUp)
e1759441 1493 wolopts |= WAKE_PHY;
61a4dcc2 1494 if (options & MagicPacket)
e1759441 1495 wolopts |= WAKE_MAGIC;
61a4dcc2
FR		 1496
1497 options = RTL_R8(Config5);
1498 if (options & UWF)
e1759441 1499 wolopts |= WAKE_UCAST;
61a4dcc2 1500 if (options & BWF)
e1759441 1501 wolopts |= WAKE_BCAST;
61a4dcc2 1502 if (options & MWF)
e1759441 1503 wolopts |= WAKE_MCAST;
61a4dcc2 1504
e1759441 1505 return wolopts;
61a4dcc2
FR		 1506}
1507
e1759441 1508static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
61a4dcc2
FR		 1509{
1510 struct rtl8169_private *tp = netdev_priv(dev);
e1759441 1511
da78dbff 1512 rtl_lock_work(tp);
e1759441
RW		 1513
1514 wol->supported = WAKE_ANY;
1515 wol->wolopts = __rtl8169_get_wol(tp);
1516
da78dbff 1517 rtl_unlock_work(tp);
e1759441
RW		 1518}
1519
1520static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1521{
61a4dcc2 1522 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 1523 unsigned int i;
350f7596 1524 static const struct {
61a4dcc2
FR		 1525 u32 opt;
1526 u16 reg;
1527 u8 mask;
1528 } cfg[] = {
61a4dcc2
FR		 1529 { WAKE_PHY, Config3, LinkUp },
1530 { WAKE_MAGIC, Config3, MagicPacket },
1531 { WAKE_UCAST, Config5, UWF },
1532 { WAKE_BCAST, Config5, BWF },
1533 { WAKE_MCAST, Config5, MWF },
1534 { WAKE_ANY, Config5, LanWake }
1535 };
851e6022 1536 u8 options;
61a4dcc2 1537
61a4dcc2
FR		 1538 RTL_W8(Cfg9346, Cfg9346_Unlock);
1539
1540 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
851e6022 1541 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
e1759441 1542 if (wolopts & cfg[i].opt)
61a4dcc2
FR		 1543 options |= cfg[i].mask;
1544 RTL_W8(cfg[i].reg, options);
1545 }
1546
851e6022
FR		 1547 switch (tp->mac_version) {
1548 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1549 options = RTL_R8(Config1) & ~PMEnable;
1550 if (wolopts)
1551 options |= PMEnable;
1552 RTL_W8(Config1, options);
1553 break;
1554 default:
d387b427
FR		 1555 options = RTL_R8(Config2) & ~PME_SIGNAL;
1556 if (wolopts)
1557 options |= PME_SIGNAL;
1558 RTL_W8(Config2, options);
851e6022
FR		 1559 break;
1560 }
1561
61a4dcc2 1562 RTL_W8(Cfg9346, Cfg9346_Lock);
e1759441
RW		 1563}
1564
1565static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1566{
1567 struct rtl8169_private *tp = netdev_priv(dev);
1568
da78dbff 1569 rtl_lock_work(tp);
61a4dcc2 1570
f23e7fda
FR		 1571 if (wol->wolopts)
1572 tp->features |= RTL_FEATURE_WOL;
1573 else
1574 tp->features &= ~RTL_FEATURE_WOL;
e1759441 1575 __rtl8169_set_wol(tp, wol->wolopts);
da78dbff
FR		 1576
1577 rtl_unlock_work(tp);
61a4dcc2 1578
ea80907f 1579 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1580
61a4dcc2
FR		 1581 return 0;
1582}
1583
31bd204f
FR		 1584static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1585{
85bffe6c 1586 return rtl_chip_infos[tp->mac_version].fw_name;
31bd204f
FR		 1587}
1588
1da177e4
LT		 1589static void rtl8169_get_drvinfo(struct net_device *dev,
1590 struct ethtool_drvinfo *info)
1591{
1592 struct rtl8169_private *tp = netdev_priv(dev);
b6ffd97f 1593 struct rtl_fw *rtl_fw = tp->rtl_fw;
1da177e4 1594
68aad78c
RJ		 1595 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1596 strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1597 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1c361efb 1598 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
8ac72d16
RJ		 1599 if (!IS_ERR_OR_NULL(rtl_fw))
1600 strlcpy(info->fw_version, rtl_fw->version,
1601 sizeof(info->fw_version));
1da177e4
LT		 1602}
1603
1604static int rtl8169_get_regs_len(struct net_device *dev)
1605{
1606 return R8169_REGS_SIZE;
1607}
1608
1609static int rtl8169_set_speed_tbi(struct net_device *dev,
54405cde 1610 u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1da177e4
LT		 1611{
1612 struct rtl8169_private *tp = netdev_priv(dev);
1613 void __iomem *ioaddr = tp->mmio_addr;
1614 int ret = 0;
1615 u32 reg;
1616
1617 reg = RTL_R32(TBICSR);
1618 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1619 (duplex == DUPLEX_FULL)) {
1620 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1621 } else if (autoneg == AUTONEG_ENABLE)
1622 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1623 else {
bf82c189
JP		 1624 netif_warn(tp, link, dev,
1625 "incorrect speed setting refused in TBI mode\n");
1da177e4
LT		 1626 ret = -EOPNOTSUPP;
1627 }
1628
1629 return ret;
1630}
1631
1632static int rtl8169_set_speed_xmii(struct net_device *dev,
54405cde 1633 u8 autoneg, u16 speed, u8 duplex, u32 adv)
1da177e4
LT		 1634{
1635 struct rtl8169_private *tp = netdev_priv(dev);
3577aa1b 1636 int giga_ctrl, bmcr;
54405cde 1637 int rc = -EINVAL;
1da177e4 1638
716b50a3 1639 rtl_writephy(tp, 0x1f, 0x0000);
1da177e4
LT		 1640
1641 if (autoneg == AUTONEG_ENABLE) {
3577aa1b 1642 int auto_nego;
1643
4da19633 1644 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
54405cde
ON		 1645 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1646 ADVERTISE_100HALF | ADVERTISE_100FULL);
1647
1648 if (adv & ADVERTISED_10baseT_Half)
1649 auto_nego |= ADVERTISE_10HALF;
1650 if (adv & ADVERTISED_10baseT_Full)
1651 auto_nego |= ADVERTISE_10FULL;
1652 if (adv & ADVERTISED_100baseT_Half)
1653 auto_nego |= ADVERTISE_100HALF;
1654 if (adv & ADVERTISED_100baseT_Full)
1655 auto_nego |= ADVERTISE_100FULL;
1656
3577aa1b 1657 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1da177e4 1658
4da19633 1659 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
3577aa1b 1660 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
bcf0bf90 1661
3577aa1b 1662 /* The 8100e/8101e/8102e do Fast Ethernet only. */
826e6cbd 1663 if (tp->mii.supports_gmii) {
54405cde
ON		 1664 if (adv & ADVERTISED_1000baseT_Half)
1665 giga_ctrl |= ADVERTISE_1000HALF;
1666 if (adv & ADVERTISED_1000baseT_Full)
1667 giga_ctrl |= ADVERTISE_1000FULL;
1668 } else if (adv & (ADVERTISED_1000baseT_Half |
1669 ADVERTISED_1000baseT_Full)) {
bf82c189
JP		 1670 netif_info(tp, link, dev,
1671 "PHY does not support 1000Mbps\n");
54405cde 1672 goto out;
bcf0bf90 1673 }
1da177e4 1674
3577aa1b 1675 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1676
4da19633 1677 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1678 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
3577aa1b 1679 } else {
1680 giga_ctrl = 0;
1681
1682 if (speed == SPEED_10)
1683 bmcr = 0;
1684 else if (speed == SPEED_100)
1685 bmcr = BMCR_SPEED100;
1686 else
54405cde 1687 goto out;
3577aa1b 1688
1689 if (duplex == DUPLEX_FULL)
1690 bmcr |= BMCR_FULLDPLX;
2584fbc3
RS		 1691 }
1692
4da19633 1693 rtl_writephy(tp, MII_BMCR, bmcr);
3577aa1b 1694
cecb5fd7
FR		 1695 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1696 tp->mac_version == RTL_GIGA_MAC_VER_03) {
3577aa1b 1697 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
4da19633 1698 rtl_writephy(tp, 0x17, 0x2138);
1699 rtl_writephy(tp, 0x0e, 0x0260);
3577aa1b 1700 } else {
4da19633 1701 rtl_writephy(tp, 0x17, 0x2108);
1702 rtl_writephy(tp, 0x0e, 0x0000);
3577aa1b 1703 }
1704 }
1705
54405cde
ON		 1706 rc = 0;
1707out:
1708 return rc;
1da177e4
LT		 1709}
1710
1711static int rtl8169_set_speed(struct net_device *dev,
54405cde 1712 u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1da177e4
LT		 1713{
1714 struct rtl8169_private *tp = netdev_priv(dev);
1715 int ret;
1716
54405cde 1717 ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
4876cc1e
FR		 1718 if (ret < 0)
1719 goto out;
1da177e4 1720
4876cc1e
FR		 1721 if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1722 (advertising & ADVERTISED_1000baseT_Full)) {
1da177e4 1723 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
4876cc1e
FR		 1724 }
1725out:
1da177e4
LT		 1726 return ret;
1727}
1728
1729static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1730{
1731 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4
LT		 1732 int ret;
1733
4876cc1e
FR		 1734 del_timer_sync(&tp->timer);
1735
da78dbff 1736 rtl_lock_work(tp);
cecb5fd7 1737 ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
25db0338 1738 cmd->duplex, cmd->advertising);
da78dbff 1739 rtl_unlock_work(tp);
5b0384f4 1740
1da177e4
LT		 1741 return ret;
1742}
1743
c8f44aff
MM		 1744static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1745 netdev_features_t features)
1da177e4 1746{
d58d46b5
FR		 1747 struct rtl8169_private *tp = netdev_priv(dev);
1748
2b7b4318 1749 if (dev->mtu > TD_MSS_MAX)
350fb32a 1750 features &= ~NETIF_F_ALL_TSO;
1da177e4 1751
d58d46b5
FR		 1752 if (dev->mtu > JUMBO_1K &&
1753 !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
1754 features &= ~NETIF_F_IP_CSUM;
1755
350fb32a 1756 return features;
1da177e4
LT		 1757}
1758
da78dbff
FR		 1759static void __rtl8169_set_features(struct net_device *dev,
1760 netdev_features_t features)
1da177e4
LT		 1761{
1762 struct rtl8169_private *tp = netdev_priv(dev);
6bbe021d 1763 netdev_features_t changed = features ^ dev->features;
da78dbff 1764 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 1765
6bbe021d
BG		 1766 if (!(changed & (NETIF_F_RXALL | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX)))
1767 return;
1da177e4 1768
6bbe021d
BG		 1769 if (changed & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX)) {
1770 if (features & NETIF_F_RXCSUM)
1771 tp->cp_cmd |= RxChkSum;
1772 else
1773 tp->cp_cmd &= ~RxChkSum;
350fb32a 1774
6bbe021d
BG		 1775 if (dev->features & NETIF_F_HW_VLAN_RX)
1776 tp->cp_cmd |= RxVlan;
1777 else
1778 tp->cp_cmd &= ~RxVlan;
1779
1780 RTL_W16(CPlusCmd, tp->cp_cmd);
1781 RTL_R16(CPlusCmd);
1782 }
1783 if (changed & NETIF_F_RXALL) {
1784 int tmp = (RTL_R32(RxConfig) & ~(AcceptErr | AcceptRunt));
1785 if (features & NETIF_F_RXALL)
1786 tmp |= (AcceptErr | AcceptRunt);
1787 RTL_W32(RxConfig, tmp);
1788 }
da78dbff 1789}
1da177e4 1790
da78dbff
FR		 1791static int rtl8169_set_features(struct net_device *dev,
1792 netdev_features_t features)
1793{
1794 struct rtl8169_private *tp = netdev_priv(dev);
1795
1796 rtl_lock_work(tp);
1797 __rtl8169_set_features(dev, features);
1798 rtl_unlock_work(tp);
1da177e4
LT		 1799
1800 return 0;
1801}
1802
da78dbff 1803
810f4893 1804static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1da177e4 1805{
eab6d18d 1806 return (vlan_tx_tag_present(skb)) ?
1da177e4
LT		 1807 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1808}
1809
7a8fc77b 1810static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1da177e4
LT		 1811{
1812 u32 opts2 = le32_to_cpu(desc->opts2);
1da177e4 1813
7a8fc77b
FR		 1814 if (opts2 & RxVlanTag)
1815 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
1da177e4
LT		 1816}
1817
ccdffb9a 1818static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1819{
1820 struct rtl8169_private *tp = netdev_priv(dev);
1821 void __iomem *ioaddr = tp->mmio_addr;
1822 u32 status;
1823
1824 cmd->supported =
1825 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1826 cmd->port = PORT_FIBRE;
1827 cmd->transceiver = XCVR_INTERNAL;
1828
1829 status = RTL_R32(TBICSR);
1830 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1831 cmd->autoneg = !!(status & TBINwEnable);
1832
70739497 1833 ethtool_cmd_speed_set(cmd, SPEED_1000);
1da177e4 1834 cmd->duplex = DUPLEX_FULL; /* Always set */
ccdffb9a
FR		 1835
1836 return 0;
1da177e4
LT		 1837}
1838
ccdffb9a 1839static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1840{
1841 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a
FR		 1842
1843 return mii_ethtool_gset(&tp->mii, cmd);
1da177e4
LT		 1844}
1845
1846static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1847{
1848 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 1849 int rc;
1da177e4 1850
da78dbff 1851 rtl_lock_work(tp);
ccdffb9a 1852 rc = tp->get_settings(dev, cmd);
da78dbff 1853 rtl_unlock_work(tp);
1da177e4 1854
ccdffb9a 1855 return rc;
1da177e4
LT		 1856}
1857
1858static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1859 void *p)
1860{
5b0384f4 1861 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 1862
5b0384f4
FR		 1863 if (regs->len > R8169_REGS_SIZE)
1864 regs->len = R8169_REGS_SIZE;
1da177e4 1865
da78dbff 1866 rtl_lock_work(tp);
5b0384f4 1867 memcpy_fromio(p, tp->mmio_addr, regs->len);
da78dbff 1868 rtl_unlock_work(tp);
1da177e4
LT		 1869}
1870
b57b7e5a
SH		 1871static u32 rtl8169_get_msglevel(struct net_device *dev)
1872{
1873 struct rtl8169_private *tp = netdev_priv(dev);
1874
1875 return tp->msg_enable;
1876}
1877
1878static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1879{
1880 struct rtl8169_private *tp = netdev_priv(dev);
1881
1882 tp->msg_enable = value;
1883}
1884
d4a3a0fc
SH		 1885static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1886 "tx_packets",
1887 "rx_packets",
1888 "tx_errors",
1889 "rx_errors",
1890 "rx_missed",
1891 "align_errors",
1892 "tx_single_collisions",
1893 "tx_multi_collisions",
1894 "unicast",
1895 "broadcast",
1896 "multicast",
1897 "tx_aborted",
1898 "tx_underrun",
1899};
1900
b9f2c044 1901static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 1902{
b9f2c044
JG		 1903 switch (sset) {
1904 case ETH_SS_STATS:
1905 return ARRAY_SIZE(rtl8169_gstrings);
1906 default:
1907 return -EOPNOTSUPP;
1908 }
d4a3a0fc
SH		 1909}
1910
ffc46952
FR		 1911DECLARE_RTL_COND(rtl_counters_cond)
1912{
1913 void __iomem *ioaddr = tp->mmio_addr;
1914
1915 return RTL_R32(CounterAddrLow) & CounterDump;
1916}
1917
355423d0 1918static void rtl8169_update_counters(struct net_device *dev)
d4a3a0fc
SH		 1919{
1920 struct rtl8169_private *tp = netdev_priv(dev);
1921 void __iomem *ioaddr = tp->mmio_addr;
cecb5fd7 1922 struct device *d = &tp->pci_dev->dev;
d4a3a0fc
SH		 1923 struct rtl8169_counters *counters;
1924 dma_addr_t paddr;
1925 u32 cmd;
1926
355423d0
IV		 1927 /*
1928 * Some chips are unable to dump tally counters when the receiver
1929 * is disabled.
1930 */
1931 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1932 return;
d4a3a0fc 1933
48addcc9 1934 counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
d4a3a0fc
SH		 1935 if (!counters)
1936 return;
1937
1938 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
284901a9 1939 cmd = (u64)paddr & DMA_BIT_MASK(32);
d4a3a0fc
SH		 1940 RTL_W32(CounterAddrLow, cmd);
1941 RTL_W32(CounterAddrLow, cmd | CounterDump);
1942
ffc46952
FR		 1943 if (rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000))
1944 memcpy(&tp->counters, counters, sizeof(*counters));
d4a3a0fc
SH		 1945
1946 RTL_W32(CounterAddrLow, 0);
1947 RTL_W32(CounterAddrHigh, 0);
1948
48addcc9 1949 dma_free_coherent(d, sizeof(*counters), counters, paddr);
d4a3a0fc
SH		 1950}
1951
355423d0
IV		 1952static void rtl8169_get_ethtool_stats(struct net_device *dev,
1953 struct ethtool_stats *stats, u64 *data)
1954{
1955 struct rtl8169_private *tp = netdev_priv(dev);
1956
1957 ASSERT_RTNL();
1958
1959 rtl8169_update_counters(dev);
1960
1961 data[0] = le64_to_cpu(tp->counters.tx_packets);
1962 data[1] = le64_to_cpu(tp->counters.rx_packets);
1963 data[2] = le64_to_cpu(tp->counters.tx_errors);
1964 data[3] = le32_to_cpu(tp->counters.rx_errors);
1965 data[4] = le16_to_cpu(tp->counters.rx_missed);
1966 data[5] = le16_to_cpu(tp->counters.align_errors);
1967 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1968 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1969 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1970 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1971 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1972 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1973 data[12] = le16_to_cpu(tp->counters.tx_underun);
1974}
1975
d4a3a0fc
SH		 1976static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1977{
1978 switch(stringset) {
1979 case ETH_SS_STATS:
1980 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1981 break;
1982 }
1983}
1984
7282d491 1985static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 1986 .get_drvinfo = rtl8169_get_drvinfo,
1987 .get_regs_len = rtl8169_get_regs_len,
1988 .get_link = ethtool_op_get_link,
1989 .get_settings = rtl8169_get_settings,
1990 .set_settings = rtl8169_set_settings,
b57b7e5a
SH		 1991 .get_msglevel = rtl8169_get_msglevel,
1992 .set_msglevel = rtl8169_set_msglevel,
1da177e4 1993 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 1994 .get_wol = rtl8169_get_wol,
1995 .set_wol = rtl8169_set_wol,
d4a3a0fc 1996 .get_strings = rtl8169_get_strings,
b9f2c044 1997 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 1998 .get_ethtool_stats = rtl8169_get_ethtool_stats,
e1593bb1 1999 .get_ts_info = ethtool_op_get_ts_info,
1da177e4
LT		 2000};
2001
07d3f51f 2002static void rtl8169_get_mac_version(struct rtl8169_private *tp,
5d320a20 2003 struct net_device *dev, u8 default_version)
1da177e4 2004{
5d320a20 2005 void __iomem *ioaddr = tp->mmio_addr;
0e485150
FR		 2006 /*
2007 * The driver currently handles the 8168Bf and the 8168Be identically
2008 * but they can be identified more specifically through the test below
2009 * if needed:
2010 *
2011 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 2012 *
2013 * Same thing for the 8101Eb and the 8101Ec:
2014 *
2015 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 2016 */
3744100e 2017 static const struct rtl_mac_info {
1da177e4 2018 u32 mask;
e3cf0cc0 2019 u32 val;
1da177e4
LT		 2020 int mac_version;
2021 } mac_info[] = {
c558386b
HW		 2022 /* 8168G family. */
2023 { 0x7cf00000, 0x4c100000, RTL_GIGA_MAC_VER_41 },
2024 { 0x7cf00000, 0x4c000000, RTL_GIGA_MAC_VER_40 },
2025
c2218925 2026 /* 8168F family. */
b3d7b2f2 2027 { 0x7c800000, 0x48800000, RTL_GIGA_MAC_VER_38 },
c2218925
HW		 2028 { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36 },
2029 { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35 },
2030
01dc7fec 2031 /* 8168E family. */
70090424 2032 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 },
01dc7fec 2033 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 },
2034 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
2035 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
2036
5b538df9 2037 /* 8168D family. */
daf9df6d 2038 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
2039 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
daf9df6d 2040 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
5b538df9 2041
e6de30d6 2042 /* 8168DP family. */
2043 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
2044 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
4804b3b3 2045 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
e6de30d6 2046
ef808d50 2047 /* 8168C family. */
17c99297 2048 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
ef3386f0 2049 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
ef808d50 2050 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
7f3e3d3a 2051 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
e3cf0cc0
FR		 2052 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
2053 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
197ff761 2054 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
6fb07058 2055 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
ef808d50 2056 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
e3cf0cc0
FR		 2057
2058 /* 8168B family. */
2059 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
2060 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
2061 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
2062 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
2063
2064 /* 8101 family. */
5598bfe5
HW		 2065 { 0x7cf00000, 0x44900000, RTL_GIGA_MAC_VER_39 },
2066 { 0x7c800000, 0x44800000, RTL_GIGA_MAC_VER_39 },
7e18dca1 2067 { 0x7c800000, 0x44000000, RTL_GIGA_MAC_VER_37 },
36a0e6c2 2068 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 },
5a5e4443
HW		 2069 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 },
2070 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
2071 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
2857ffb7
FR		 2072 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
2073 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
2074 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
2075 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
2076 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
2077 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
e3cf0cc0 2078 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2857ffb7 2079 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
e3cf0cc0 2080 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2857ffb7
FR		 2081 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
2082 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
e3cf0cc0
FR		 2083 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
2084 /* FIXME: where did these entries come from ? -- FR */
2085 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
2086 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
2087
2088 /* 8110 family. */
2089 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
2090 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
2091 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
2092 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
2093 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
2094 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
2095
f21b75e9
JD		 2096 /* Catch-all */
2097 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
3744100e
FR		 2098 };
2099 const struct rtl_mac_info *p = mac_info;
1da177e4
LT		 2100 u32 reg;
2101
e3cf0cc0
FR		 2102 reg = RTL_R32(TxConfig);
2103 while ((reg & p->mask) != p->val)
1da177e4
LT		 2104 p++;
2105 tp->mac_version = p->mac_version;
5d320a20
FR		 2106
2107 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2108 netif_notice(tp, probe, dev,
2109 "unknown MAC, using family default\n");
2110 tp->mac_version = default_version;
2111 }
1da177e4
LT		 2112}
2113
2114static void rtl8169_print_mac_version(struct rtl8169_private *tp)
2115{
bcf0bf90 2116 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 2117}
2118
867763c1
FR		 2119struct phy_reg {
2120 u16 reg;
2121 u16 val;
2122};
2123
4da19633 2124static void rtl_writephy_batch(struct rtl8169_private *tp,
2125 const struct phy_reg *regs, int len)
867763c1
FR		 2126{
2127 while (len-- > 0) {
4da19633 2128 rtl_writephy(tp, regs->reg, regs->val);
867763c1
FR		 2129 regs++;
2130 }
2131}
2132
bca03d5f 2133#define PHY_READ 0x00000000
2134#define PHY_DATA_OR 0x10000000
2135#define PHY_DATA_AND 0x20000000
2136#define PHY_BJMPN 0x30000000
2137#define PHY_READ_EFUSE 0x40000000
2138#define PHY_READ_MAC_BYTE 0x50000000
2139#define PHY_WRITE_MAC_BYTE 0x60000000
2140#define PHY_CLEAR_READCOUNT 0x70000000
2141#define PHY_WRITE 0x80000000
2142#define PHY_READCOUNT_EQ_SKIP 0x90000000
2143#define PHY_COMP_EQ_SKIPN 0xa0000000
2144#define PHY_COMP_NEQ_SKIPN 0xb0000000
2145#define PHY_WRITE_PREVIOUS 0xc0000000
2146#define PHY_SKIPN 0xd0000000
2147#define PHY_DELAY_MS 0xe0000000
2148#define PHY_WRITE_ERI_WORD 0xf0000000
2149
960aee6c
HW		 2150struct fw_info {
2151 u32 magic;
2152 char version[RTL_VER_SIZE];
2153 __le32 fw_start;
2154 __le32 fw_len;
2155 u8 chksum;
2156} __packed;
2157
1c361efb
FR		 2158#define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2159
2160static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
bca03d5f 2161{
b6ffd97f 2162 const struct firmware *fw = rtl_fw->fw;
960aee6c 2163 struct fw_info *fw_info = (struct fw_info *)fw->data;
1c361efb
FR		 2164 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2165 char *version = rtl_fw->version;
2166 bool rc = false;
2167
2168 if (fw->size < FW_OPCODE_SIZE)
2169 goto out;
960aee6c
HW		 2170
2171 if (!fw_info->magic) {
2172 size_t i, size, start;
2173 u8 checksum = 0;
2174
2175 if (fw->size < sizeof(*fw_info))
2176 goto out;
2177
2178 for (i = 0; i < fw->size; i++)
2179 checksum += fw->data[i];
2180 if (checksum != 0)
2181 goto out;
2182
2183 start = le32_to_cpu(fw_info->fw_start);
2184 if (start > fw->size)
2185 goto out;
2186
2187 size = le32_to_cpu(fw_info->fw_len);
2188 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2189 goto out;
2190
2191 memcpy(version, fw_info->version, RTL_VER_SIZE);
2192
2193 pa->code = (__le32 *)(fw->data + start);
2194 pa->size = size;
2195 } else {
1c361efb
FR		 2196 if (fw->size % FW_OPCODE_SIZE)
2197 goto out;
2198
2199 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2200
2201 pa->code = (__le32 *)fw->data;
2202 pa->size = fw->size / FW_OPCODE_SIZE;
2203 }
2204 version[RTL_VER_SIZE - 1] = 0;
2205
2206 rc = true;
2207out:
2208 return rc;
2209}
2210
fd112f2e
FR		 2211static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2212 struct rtl_fw_phy_action *pa)
1c361efb 2213{
fd112f2e 2214 bool rc = false;
1c361efb 2215 size_t index;
bca03d5f 2216
1c361efb
FR		 2217 for (index = 0; index < pa->size; index++) {
2218 u32 action = le32_to_cpu(pa->code[index]);
42b82dc1 2219 u32 regno = (action & 0x0fff0000) >> 16;
bca03d5f 2220
42b82dc1 2221 switch(action & 0xf0000000) {
2222 case PHY_READ:
2223 case PHY_DATA_OR:
2224 case PHY_DATA_AND:
2225 case PHY_READ_EFUSE:
2226 case PHY_CLEAR_READCOUNT:
2227 case PHY_WRITE:
2228 case PHY_WRITE_PREVIOUS:
2229 case PHY_DELAY_MS:
2230 break;
2231
2232 case PHY_BJMPN:
2233 if (regno > index) {
fd112f2e 2234 netif_err(tp, ifup, tp->dev,
cecb5fd7 2235 "Out of range of firmware\n");
fd112f2e 2236 goto out;
42b82dc1 2237 }
2238 break;
2239 case PHY_READCOUNT_EQ_SKIP:
1c361efb 2240 if (index + 2 >= pa->size) {
fd112f2e 2241 netif_err(tp, ifup, tp->dev,
cecb5fd7 2242 "Out of range of firmware\n");
fd112f2e 2243 goto out;
42b82dc1 2244 }
2245 break;
2246 case PHY_COMP_EQ_SKIPN:
2247 case PHY_COMP_NEQ_SKIPN:
2248 case PHY_SKIPN:
1c361efb 2249 if (index + 1 + regno >= pa->size) {
fd112f2e 2250 netif_err(tp, ifup, tp->dev,
cecb5fd7 2251 "Out of range of firmware\n");
fd112f2e 2252 goto out;
42b82dc1 2253 }
bca03d5f 2254 break;
2255
42b82dc1 2256 case PHY_READ_MAC_BYTE:
2257 case PHY_WRITE_MAC_BYTE:
2258 case PHY_WRITE_ERI_WORD:
2259 default:
fd112f2e 2260 netif_err(tp, ifup, tp->dev,
42b82dc1 2261 "Invalid action 0x%08x\n", action);
fd112f2e 2262 goto out;
bca03d5f 2263 }
2264 }
fd112f2e
FR		 2265 rc = true;
2266out:
2267 return rc;
2268}
bca03d5f 2269
fd112f2e
FR		 2270static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2271{
2272 struct net_device *dev = tp->dev;
2273 int rc = -EINVAL;
2274
2275 if (!rtl_fw_format_ok(tp, rtl_fw)) {
2276 netif_err(tp, ifup, dev, "invalid firwmare\n");
2277 goto out;
2278 }
2279
2280 if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2281 rc = 0;
2282out:
2283 return rc;
2284}
2285
2286static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2287{
2288 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2289 u32 predata, count;
2290 size_t index;
2291
2292 predata = count = 0;
42b82dc1 2293
1c361efb
FR		 2294 for (index = 0; index < pa->size; ) {
2295 u32 action = le32_to_cpu(pa->code[index]);
bca03d5f 2296 u32 data = action & 0x0000ffff;
42b82dc1 2297 u32 regno = (action & 0x0fff0000) >> 16;
2298
2299 if (!action)
2300 break;
bca03d5f 2301
2302 switch(action & 0xf0000000) {
42b82dc1 2303 case PHY_READ:
2304 predata = rtl_readphy(tp, regno);
2305 count++;
2306 index++;
2307 break;
2308 case PHY_DATA_OR:
2309 predata |= data;
2310 index++;
2311 break;
2312 case PHY_DATA_AND:
2313 predata &= data;
2314 index++;
2315 break;
2316 case PHY_BJMPN:
2317 index -= regno;
2318 break;
2319 case PHY_READ_EFUSE:
fdf6fc06 2320 predata = rtl8168d_efuse_read(tp, regno);
42b82dc1 2321 index++;
2322 break;
2323 case PHY_CLEAR_READCOUNT:
2324 count = 0;
2325 index++;
2326 break;
bca03d5f 2327 case PHY_WRITE:
42b82dc1 2328 rtl_writephy(tp, regno, data);
2329 index++;
2330 break;
2331 case PHY_READCOUNT_EQ_SKIP:
cecb5fd7 2332 index += (count == data) ? 2 : 1;
bca03d5f 2333 break;
42b82dc1 2334 case PHY_COMP_EQ_SKIPN:
2335 if (predata == data)
2336 index += regno;
2337 index++;
2338 break;
2339 case PHY_COMP_NEQ_SKIPN:
2340 if (predata != data)
2341 index += regno;
2342 index++;
2343 break;
2344 case PHY_WRITE_PREVIOUS:
2345 rtl_writephy(tp, regno, predata);
2346 index++;
2347 break;
2348 case PHY_SKIPN:
2349 index += regno + 1;
2350 break;
2351 case PHY_DELAY_MS:
2352 mdelay(data);
2353 index++;
2354 break;
2355
2356 case PHY_READ_MAC_BYTE:
2357 case PHY_WRITE_MAC_BYTE:
2358 case PHY_WRITE_ERI_WORD:
bca03d5f 2359 default:
2360 BUG();
2361 }
2362 }
2363}
2364
f1e02ed1 2365static void rtl_release_firmware(struct rtl8169_private *tp)
2366{
b6ffd97f
FR		 2367 if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2368 release_firmware(tp->rtl_fw->fw);
2369 kfree(tp->rtl_fw);
2370 }
2371 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
f1e02ed1 2372}
2373
953a12cc 2374static void rtl_apply_firmware(struct rtl8169_private *tp)
f1e02ed1 2375{
b6ffd97f 2376 struct rtl_fw *rtl_fw = tp->rtl_fw;
f1e02ed1 2377
2378 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
eef63cc1 2379 if (!IS_ERR_OR_NULL(rtl_fw))
b6ffd97f 2380 rtl_phy_write_fw(tp, rtl_fw);
953a12cc
FR		 2381}
2382
2383static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2384{
2385 if (rtl_readphy(tp, reg) != val)
2386 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2387 else
2388 rtl_apply_firmware(tp);
f1e02ed1 2389}
2390
4da19633 2391static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1da177e4 2392{
350f7596 2393 static const struct phy_reg phy_reg_init[] = {
0b9b571d 2394 { 0x1f, 0x0001 },
2395 { 0x06, 0x006e },
2396 { 0x08, 0x0708 },
2397 { 0x15, 0x4000 },
2398 { 0x18, 0x65c7 },
1da177e4 2399
0b9b571d 2400 { 0x1f, 0x0001 },
2401 { 0x03, 0x00a1 },
2402 { 0x02, 0x0008 },
2403 { 0x01, 0x0120 },
2404 { 0x00, 0x1000 },
2405 { 0x04, 0x0800 },
2406 { 0x04, 0x0000 },
1da177e4 2407
0b9b571d 2408 { 0x03, 0xff41 },
2409 { 0x02, 0xdf60 },
2410 { 0x01, 0x0140 },
2411 { 0x00, 0x0077 },
2412 { 0x04, 0x7800 },
2413 { 0x04, 0x7000 },
2414
2415 { 0x03, 0x802f },
2416 { 0x02, 0x4f02 },
2417 { 0x01, 0x0409 },
2418 { 0x00, 0xf0f9 },
2419 { 0x04, 0x9800 },
2420 { 0x04, 0x9000 },
2421
2422 { 0x03, 0xdf01 },
2423 { 0x02, 0xdf20 },
2424 { 0x01, 0xff95 },
2425 { 0x00, 0xba00 },
2426 { 0x04, 0xa800 },
2427 { 0x04, 0xa000 },
2428
2429 { 0x03, 0xff41 },
2430 { 0x02, 0xdf20 },
2431 { 0x01, 0x0140 },
2432 { 0x00, 0x00bb },
2433 { 0x04, 0xb800 },
2434 { 0x04, 0xb000 },
2435
2436 { 0x03, 0xdf41 },
2437 { 0x02, 0xdc60 },
2438 { 0x01, 0x6340 },
2439 { 0x00, 0x007d },
2440 { 0x04, 0xd800 },
2441 { 0x04, 0xd000 },
2442
2443 { 0x03, 0xdf01 },
2444 { 0x02, 0xdf20 },
2445 { 0x01, 0x100a },
2446 { 0x00, 0xa0ff },
2447 { 0x04, 0xf800 },
2448 { 0x04, 0xf000 },
2449
2450 { 0x1f, 0x0000 },
2451 { 0x0b, 0x0000 },
2452 { 0x00, 0x9200 }
2453 };
1da177e4 2454
4da19633 2455 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1da177e4
LT		 2456}
2457
4da19633 2458static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
5615d9f1 2459{
350f7596 2460 static const struct phy_reg phy_reg_init[] = {
a441d7b6
FR		 2461 { 0x1f, 0x0002 },
2462 { 0x01, 0x90d0 },
2463 { 0x1f, 0x0000 }
2464 };
2465
4da19633 2466 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5615d9f1
FR		 2467}
2468
4da19633 2469static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2e955856 2470{
2471 struct pci_dev *pdev = tp->pci_dev;
2e955856 2472
ccbae55e
SS		 2473 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2474 (pdev->subsystem_device != 0xe000))
2e955856 2475 return;
2476
4da19633 2477 rtl_writephy(tp, 0x1f, 0x0001);
2478 rtl_writephy(tp, 0x10, 0xf01b);
2479 rtl_writephy(tp, 0x1f, 0x0000);
2e955856 2480}
2481
4da19633 2482static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2e955856 2483{
350f7596 2484 static const struct phy_reg phy_reg_init[] = {
2e955856 2485 { 0x1f, 0x0001 },
2486 { 0x04, 0x0000 },
2487 { 0x03, 0x00a1 },
2488 { 0x02, 0x0008 },
2489 { 0x01, 0x0120 },
2490 { 0x00, 0x1000 },
2491 { 0x04, 0x0800 },
2492 { 0x04, 0x9000 },
2493 { 0x03, 0x802f },
2494 { 0x02, 0x4f02 },
2495 { 0x01, 0x0409 },
2496 { 0x00, 0xf099 },
2497 { 0x04, 0x9800 },
2498 { 0x04, 0xa000 },
2499 { 0x03, 0xdf01 },
2500 { 0x02, 0xdf20 },
2501 { 0x01, 0xff95 },
2502 { 0x00, 0xba00 },
2503 { 0x04, 0xa800 },
2504 { 0x04, 0xf000 },
2505 { 0x03, 0xdf01 },
2506 { 0x02, 0xdf20 },
2507 { 0x01, 0x101a },
2508 { 0x00, 0xa0ff },
2509 { 0x04, 0xf800 },
2510 { 0x04, 0x0000 },
2511 { 0x1f, 0x0000 },
2512
2513 { 0x1f, 0x0001 },
2514 { 0x10, 0xf41b },
2515 { 0x14, 0xfb54 },
2516 { 0x18, 0xf5c7 },
2517 { 0x1f, 0x0000 },
2518
2519 { 0x1f, 0x0001 },
2520 { 0x17, 0x0cc0 },
2521 { 0x1f, 0x0000 }
2522 };
2523
4da19633 2524 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2e955856 2525
4da19633 2526 rtl8169scd_hw_phy_config_quirk(tp);
2e955856 2527}
2528
4da19633 2529static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
8c7006aa 2530{
350f7596 2531 static const struct phy_reg phy_reg_init[] = {
8c7006aa 2532 { 0x1f, 0x0001 },
2533 { 0x04, 0x0000 },
2534 { 0x03, 0x00a1 },
2535 { 0x02, 0x0008 },
2536 { 0x01, 0x0120 },
2537 { 0x00, 0x1000 },
2538 { 0x04, 0x0800 },
2539 { 0x04, 0x9000 },
2540 { 0x03, 0x802f },
2541 { 0x02, 0x4f02 },
2542 { 0x01, 0x0409 },
2543 { 0x00, 0xf099 },
2544 { 0x04, 0x9800 },
2545 { 0x04, 0xa000 },
2546 { 0x03, 0xdf01 },
2547 { 0x02, 0xdf20 },
2548 { 0x01, 0xff95 },
2549 { 0x00, 0xba00 },
2550 { 0x04, 0xa800 },
2551 { 0x04, 0xf000 },
2552 { 0x03, 0xdf01 },
2553 { 0x02, 0xdf20 },
2554 { 0x01, 0x101a },
2555 { 0x00, 0xa0ff },
2556 { 0x04, 0xf800 },
2557 { 0x04, 0x0000 },
2558 { 0x1f, 0x0000 },
2559
2560 { 0x1f, 0x0001 },
2561 { 0x0b, 0x8480 },
2562 { 0x1f, 0x0000 },
2563
2564 { 0x1f, 0x0001 },
2565 { 0x18, 0x67c7 },
2566 { 0x04, 0x2000 },
2567 { 0x03, 0x002f },
2568 { 0x02, 0x4360 },
2569 { 0x01, 0x0109 },
2570 { 0x00, 0x3022 },
2571 { 0x04, 0x2800 },
2572 { 0x1f, 0x0000 },
2573
2574 { 0x1f, 0x0001 },
2575 { 0x17, 0x0cc0 },
2576 { 0x1f, 0x0000 }
2577 };
2578
4da19633 2579 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
8c7006aa 2580}
2581
4da19633 2582static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
236b8082 2583{
350f7596 2584 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2585 { 0x10, 0xf41b },
2586 { 0x1f, 0x0000 }
2587 };
2588
4da19633 2589 rtl_writephy(tp, 0x1f, 0x0001);
2590 rtl_patchphy(tp, 0x16, 1 << 0);
236b8082 2591
4da19633 2592 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2593}
2594
4da19633 2595static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
236b8082 2596{
350f7596 2597 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2598 { 0x1f, 0x0001 },
2599 { 0x10, 0xf41b },
2600 { 0x1f, 0x0000 }
2601 };
2602
4da19633 2603 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2604}
2605
4da19633 2606static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2607{
350f7596 2608 static const struct phy_reg phy_reg_init[] = {
867763c1
FR		 2609 { 0x1f, 0x0000 },
2610 { 0x1d, 0x0f00 },
2611 { 0x1f, 0x0002 },
2612 { 0x0c, 0x1ec8 },
2613 { 0x1f, 0x0000 }
2614 };
2615
4da19633 2616 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
867763c1
FR		 2617}
2618
4da19633 2619static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
ef3386f0 2620{
350f7596 2621 static const struct phy_reg phy_reg_init[] = {
ef3386f0
FR		 2622 { 0x1f, 0x0001 },
2623 { 0x1d, 0x3d98 },
2624 { 0x1f, 0x0000 }
2625 };
2626
4da19633 2627 rtl_writephy(tp, 0x1f, 0x0000);
2628 rtl_patchphy(tp, 0x14, 1 << 5);
2629 rtl_patchphy(tp, 0x0d, 1 << 5);
ef3386f0 2630
4da19633 2631 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
ef3386f0
FR		 2632}
2633
4da19633 2634static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2635{
350f7596 2636 static const struct phy_reg phy_reg_init[] = {
a3f80671
FR		 2637 { 0x1f, 0x0001 },
2638 { 0x12, 0x2300 },
867763c1
FR		 2639 { 0x1f, 0x0002 },
2640 { 0x00, 0x88d4 },
2641 { 0x01, 0x82b1 },
2642 { 0x03, 0x7002 },
2643 { 0x08, 0x9e30 },
2644 { 0x09, 0x01f0 },
2645 { 0x0a, 0x5500 },
2646 { 0x0c, 0x00c8 },
2647 { 0x1f, 0x0003 },
2648 { 0x12, 0xc096 },
2649 { 0x16, 0x000a },
f50d4275
FR		 2650 { 0x1f, 0x0000 },
2651 { 0x1f, 0x0000 },
2652 { 0x09, 0x2000 },
2653 { 0x09, 0x0000 }
867763c1
FR		 2654 };
2655
4da19633 2656 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2657
4da19633 2658 rtl_patchphy(tp, 0x14, 1 << 5);
2659 rtl_patchphy(tp, 0x0d, 1 << 5);
2660 rtl_writephy(tp, 0x1f, 0x0000);
867763c1
FR		 2661}
2662
4da19633 2663static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
7da97ec9 2664{
350f7596 2665 static const struct phy_reg phy_reg_init[] = {
f50d4275 2666 { 0x1f, 0x0001 },
7da97ec9 2667 { 0x12, 0x2300 },
f50d4275
FR		 2668 { 0x03, 0x802f },
2669 { 0x02, 0x4f02 },
2670 { 0x01, 0x0409 },
2671 { 0x00, 0xf099 },
2672 { 0x04, 0x9800 },
2673 { 0x04, 0x9000 },
2674 { 0x1d, 0x3d98 },
7da97ec9
FR		 2675 { 0x1f, 0x0002 },
2676 { 0x0c, 0x7eb8 },
f50d4275
FR		 2677 { 0x06, 0x0761 },
2678 { 0x1f, 0x0003 },
2679 { 0x16, 0x0f0a },
7da97ec9
FR		 2680 { 0x1f, 0x0000 }
2681 };
2682
4da19633 2683 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2684
4da19633 2685 rtl_patchphy(tp, 0x16, 1 << 0);
2686 rtl_patchphy(tp, 0x14, 1 << 5);
2687 rtl_patchphy(tp, 0x0d, 1 << 5);
2688 rtl_writephy(tp, 0x1f, 0x0000);
7da97ec9
FR		 2689}
2690
4da19633 2691static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
197ff761 2692{
350f7596 2693 static const struct phy_reg phy_reg_init[] = {
197ff761
FR		 2694 { 0x1f, 0x0001 },
2695 { 0x12, 0x2300 },
2696 { 0x1d, 0x3d98 },
2697 { 0x1f, 0x0002 },
2698 { 0x0c, 0x7eb8 },
2699 { 0x06, 0x5461 },
2700 { 0x1f, 0x0003 },
2701 { 0x16, 0x0f0a },
2702 { 0x1f, 0x0000 }
2703 };
2704
4da19633 2705 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
197ff761 2706
4da19633 2707 rtl_patchphy(tp, 0x16, 1 << 0);
2708 rtl_patchphy(tp, 0x14, 1 << 5);
2709 rtl_patchphy(tp, 0x0d, 1 << 5);
2710 rtl_writephy(tp, 0x1f, 0x0000);
197ff761
FR		 2711}
2712
4da19633 2713static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
6fb07058 2714{
4da19633 2715 rtl8168c_3_hw_phy_config(tp);
6fb07058
FR		 2716}
2717
bca03d5f 2718static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
5b538df9 2719{
350f7596 2720 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2721 /* Channel Estimation */
5b538df9 2722 { 0x1f, 0x0001 },
daf9df6d 2723 { 0x06, 0x4064 },
2724 { 0x07, 0x2863 },
2725 { 0x08, 0x059c },
2726 { 0x09, 0x26b4 },
2727 { 0x0a, 0x6a19 },
2728 { 0x0b, 0xdcc8 },
2729 { 0x10, 0xf06d },
2730 { 0x14, 0x7f68 },
2731 { 0x18, 0x7fd9 },
2732 { 0x1c, 0xf0ff },
2733 { 0x1d, 0x3d9c },
5b538df9 2734 { 0x1f, 0x0003 },
daf9df6d 2735 { 0x12, 0xf49f },
2736 { 0x13, 0x070b },
2737 { 0x1a, 0x05ad },
bca03d5f 2738 { 0x14, 0x94c0 },
2739
2740 /*
2741 * Tx Error Issue
cecb5fd7 2742 * Enhance line driver power
bca03d5f 2743 */
5b538df9 2744 { 0x1f, 0x0002 },
daf9df6d 2745 { 0x06, 0x5561 },
2746 { 0x1f, 0x0005 },
2747 { 0x05, 0x8332 },
bca03d5f 2748 { 0x06, 0x5561 },
2749
2750 /*
2751 * Can not link to 1Gbps with bad cable
2752 * Decrease SNR threshold form 21.07dB to 19.04dB
2753 */
2754 { 0x1f, 0x0001 },
2755 { 0x17, 0x0cc0 },
daf9df6d 2756
5b538df9 2757 { 0x1f, 0x0000 },
bca03d5f 2758 { 0x0d, 0xf880 }
daf9df6d 2759 };
2760
4da19633 2761 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
daf9df6d 2762
bca03d5f 2763 /*
2764 * Rx Error Issue
2765 * Fine Tune Switching regulator parameter
2766 */
4da19633 2767 rtl_writephy(tp, 0x1f, 0x0002);
2768 rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2769 rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
daf9df6d 2770
fdf6fc06 2771 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
350f7596 2772 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2773 { 0x1f, 0x0002 },
2774 { 0x05, 0x669a },
2775 { 0x1f, 0x0005 },
2776 { 0x05, 0x8330 },
2777 { 0x06, 0x669a },
2778 { 0x1f, 0x0002 }
2779 };
2780 int val;
2781
4da19633 2782 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2783
4da19633 2784 val = rtl_readphy(tp, 0x0d);
daf9df6d 2785
2786 if ((val & 0x00ff) != 0x006c) {
350f7596 2787 static const u32 set[] = {
daf9df6d 2788 0x0065, 0x0066, 0x0067, 0x0068,
2789 0x0069, 0x006a, 0x006b, 0x006c
2790 };
2791 int i;
2792
4da19633 2793 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2794
2795 val &= 0xff00;
2796 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2797 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2798 }
2799 } else {
350f7596 2800 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2801 { 0x1f, 0x0002 },
2802 { 0x05, 0x6662 },
2803 { 0x1f, 0x0005 },
2804 { 0x05, 0x8330 },
2805 { 0x06, 0x6662 }
2806 };
2807
4da19633 2808 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2809 }
2810
bca03d5f 2811 /* RSET couple improve */
4da19633 2812 rtl_writephy(tp, 0x1f, 0x0002);
2813 rtl_patchphy(tp, 0x0d, 0x0300);
2814 rtl_patchphy(tp, 0x0f, 0x0010);
daf9df6d 2815
bca03d5f 2816 /* Fine tune PLL performance */
4da19633 2817 rtl_writephy(tp, 0x1f, 0x0002);
2818 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2819 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2820
4da19633 2821 rtl_writephy(tp, 0x1f, 0x0005);
2822 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 2823
2824 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
bca03d5f 2825
4da19633 2826 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2827}
2828
bca03d5f 2829static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2830{
350f7596 2831 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2832 /* Channel Estimation */
daf9df6d 2833 { 0x1f, 0x0001 },
2834 { 0x06, 0x4064 },
2835 { 0x07, 0x2863 },
2836 { 0x08, 0x059c },
2837 { 0x09, 0x26b4 },
2838 { 0x0a, 0x6a19 },
2839 { 0x0b, 0xdcc8 },
2840 { 0x10, 0xf06d },
2841 { 0x14, 0x7f68 },
2842 { 0x18, 0x7fd9 },
2843 { 0x1c, 0xf0ff },
2844 { 0x1d, 0x3d9c },
2845 { 0x1f, 0x0003 },
2846 { 0x12, 0xf49f },
2847 { 0x13, 0x070b },
2848 { 0x1a, 0x05ad },
2849 { 0x14, 0x94c0 },
2850
bca03d5f 2851 /*
2852 * Tx Error Issue
cecb5fd7 2853 * Enhance line driver power
bca03d5f 2854 */
daf9df6d 2855 { 0x1f, 0x0002 },
2856 { 0x06, 0x5561 },
2857 { 0x1f, 0x0005 },
2858 { 0x05, 0x8332 },
bca03d5f 2859 { 0x06, 0x5561 },
2860
2861 /*
2862 * Can not link to 1Gbps with bad cable
2863 * Decrease SNR threshold form 21.07dB to 19.04dB
2864 */
2865 { 0x1f, 0x0001 },
2866 { 0x17, 0x0cc0 },
daf9df6d 2867
2868 { 0x1f, 0x0000 },
bca03d5f 2869 { 0x0d, 0xf880 }
5b538df9
FR		 2870 };
2871
4da19633 2872 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
5b538df9 2873
fdf6fc06 2874 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
350f7596 2875 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2876 { 0x1f, 0x0002 },
2877 { 0x05, 0x669a },
5b538df9 2878 { 0x1f, 0x0005 },
daf9df6d 2879 { 0x05, 0x8330 },
2880 { 0x06, 0x669a },
2881
2882 { 0x1f, 0x0002 }
2883 };
2884 int val;
2885
4da19633 2886 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2887
4da19633 2888 val = rtl_readphy(tp, 0x0d);
daf9df6d 2889 if ((val & 0x00ff) != 0x006c) {
b6bc7650 2890 static const u32 set[] = {
daf9df6d 2891 0x0065, 0x0066, 0x0067, 0x0068,
2892 0x0069, 0x006a, 0x006b, 0x006c
2893 };
2894 int i;
2895
4da19633 2896 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2897
2898 val &= 0xff00;
2899 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2900 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2901 }
2902 } else {
350f7596 2903 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2904 { 0x1f, 0x0002 },
2905 { 0x05, 0x2642 },
5b538df9 2906 { 0x1f, 0x0005 },
daf9df6d 2907 { 0x05, 0x8330 },
2908 { 0x06, 0x2642 }
5b538df9
FR		 2909 };
2910
4da19633 2911 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2912 }
2913
bca03d5f 2914 /* Fine tune PLL performance */
4da19633 2915 rtl_writephy(tp, 0x1f, 0x0002);
2916 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2917 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2918
bca03d5f 2919 /* Switching regulator Slew rate */
4da19633 2920 rtl_writephy(tp, 0x1f, 0x0002);
2921 rtl_patchphy(tp, 0x0f, 0x0017);
daf9df6d 2922
4da19633 2923 rtl_writephy(tp, 0x1f, 0x0005);
2924 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 2925
2926 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
bca03d5f 2927
4da19633 2928 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2929}
2930
4da19633 2931static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2932{
350f7596 2933 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2934 { 0x1f, 0x0002 },
2935 { 0x10, 0x0008 },
2936 { 0x0d, 0x006c },
2937
2938 { 0x1f, 0x0000 },
2939 { 0x0d, 0xf880 },
2940
2941 { 0x1f, 0x0001 },
2942 { 0x17, 0x0cc0 },
2943
2944 { 0x1f, 0x0001 },
2945 { 0x0b, 0xa4d8 },
2946 { 0x09, 0x281c },
2947 { 0x07, 0x2883 },
2948 { 0x0a, 0x6b35 },
2949 { 0x1d, 0x3da4 },
2950 { 0x1c, 0xeffd },
2951 { 0x14, 0x7f52 },
2952 { 0x18, 0x7fc6 },
2953 { 0x08, 0x0601 },
2954 { 0x06, 0x4063 },
2955 { 0x10, 0xf074 },
2956 { 0x1f, 0x0003 },
2957 { 0x13, 0x0789 },
2958 { 0x12, 0xf4bd },
2959 { 0x1a, 0x04fd },
2960 { 0x14, 0x84b0 },
2961 { 0x1f, 0x0000 },
2962 { 0x00, 0x9200 },
2963
2964 { 0x1f, 0x0005 },
2965 { 0x01, 0x0340 },
2966 { 0x1f, 0x0001 },
2967 { 0x04, 0x4000 },
2968 { 0x03, 0x1d21 },
2969 { 0x02, 0x0c32 },
2970 { 0x01, 0x0200 },
2971 { 0x00, 0x5554 },
2972 { 0x04, 0x4800 },
2973 { 0x04, 0x4000 },
2974 { 0x04, 0xf000 },
2975 { 0x03, 0xdf01 },
2976 { 0x02, 0xdf20 },
2977 { 0x01, 0x101a },
2978 { 0x00, 0xa0ff },
2979 { 0x04, 0xf800 },
2980 { 0x04, 0xf000 },
2981 { 0x1f, 0x0000 },
2982
2983 { 0x1f, 0x0007 },
2984 { 0x1e, 0x0023 },
2985 { 0x16, 0x0000 },
2986 { 0x1f, 0x0000 }
2987 };
2988
4da19633 2989 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2990}
2991
e6de30d6 2992static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2993{
2994 static const struct phy_reg phy_reg_init[] = {
2995 { 0x1f, 0x0001 },
2996 { 0x17, 0x0cc0 },
2997
2998 { 0x1f, 0x0007 },
2999 { 0x1e, 0x002d },
3000 { 0x18, 0x0040 },
3001 { 0x1f, 0x0000 }
3002 };
3003
3004 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3005 rtl_patchphy(tp, 0x0d, 1 << 5);
3006}
3007
70090424 3008static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
01dc7fec 3009{
3010 static const struct phy_reg phy_reg_init[] = {
3011 /* Enable Delay cap */
3012 { 0x1f, 0x0005 },
3013 { 0x05, 0x8b80 },
3014 { 0x06, 0xc896 },
3015 { 0x1f, 0x0000 },
3016
3017 /* Channel estimation fine tune */
3018 { 0x1f, 0x0001 },
3019 { 0x0b, 0x6c20 },
3020 { 0x07, 0x2872 },
3021 { 0x1c, 0xefff },
3022 { 0x1f, 0x0003 },
3023 { 0x14, 0x6420 },
3024 { 0x1f, 0x0000 },
3025
3026 /* Update PFM & 10M TX idle timer */
3027 { 0x1f, 0x0007 },
3028 { 0x1e, 0x002f },
3029 { 0x15, 0x1919 },
3030 { 0x1f, 0x0000 },
3031
3032 { 0x1f, 0x0007 },
3033 { 0x1e, 0x00ac },
3034 { 0x18, 0x0006 },
3035 { 0x1f, 0x0000 }
3036 };
3037
15ecd039
FR		 3038 rtl_apply_firmware(tp);
3039
01dc7fec 3040 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3041
3042 /* DCO enable for 10M IDLE Power */
3043 rtl_writephy(tp, 0x1f, 0x0007);
3044 rtl_writephy(tp, 0x1e, 0x0023);
3045 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
3046 rtl_writephy(tp, 0x1f, 0x0000);
3047
3048 /* For impedance matching */
3049 rtl_writephy(tp, 0x1f, 0x0002);
3050 rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
cecb5fd7 3051 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3052
3053 /* PHY auto speed down */
3054 rtl_writephy(tp, 0x1f, 0x0007);
3055 rtl_writephy(tp, 0x1e, 0x002d);
3056 rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
3057 rtl_writephy(tp, 0x1f, 0x0000);
3058 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3059
3060 rtl_writephy(tp, 0x1f, 0x0005);
3061 rtl_writephy(tp, 0x05, 0x8b86);
3062 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3063 rtl_writephy(tp, 0x1f, 0x0000);
3064
3065 rtl_writephy(tp, 0x1f, 0x0005);
3066 rtl_writephy(tp, 0x05, 0x8b85);
3067 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3068 rtl_writephy(tp, 0x1f, 0x0007);
3069 rtl_writephy(tp, 0x1e, 0x0020);
3070 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
3071 rtl_writephy(tp, 0x1f, 0x0006);
3072 rtl_writephy(tp, 0x00, 0x5a00);
3073 rtl_writephy(tp, 0x1f, 0x0000);
3074 rtl_writephy(tp, 0x0d, 0x0007);
3075 rtl_writephy(tp, 0x0e, 0x003c);
3076 rtl_writephy(tp, 0x0d, 0x4007);
3077 rtl_writephy(tp, 0x0e, 0x0000);
3078 rtl_writephy(tp, 0x0d, 0x0000);
3079}
3080
9ecb9aab 3081static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3082{
3083 const u16 w[] = {
3084 addr[0] | (addr[1] << 8),
3085 addr[2] | (addr[3] << 8),
3086 addr[4] | (addr[5] << 8)
3087 };
3088 const struct exgmac_reg e[] = {
3089 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3090 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3091 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3092 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3093 };
3094
3095 rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3096}
3097
70090424
HW		 3098static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3099{
3100 static const struct phy_reg phy_reg_init[] = {
3101 /* Enable Delay cap */
3102 { 0x1f, 0x0004 },
3103 { 0x1f, 0x0007 },
3104 { 0x1e, 0x00ac },
3105 { 0x18, 0x0006 },
3106 { 0x1f, 0x0002 },
3107 { 0x1f, 0x0000 },
3108 { 0x1f, 0x0000 },
3109
3110 /* Channel estimation fine tune */
3111 { 0x1f, 0x0003 },
3112 { 0x09, 0xa20f },
3113 { 0x1f, 0x0000 },
3114 { 0x1f, 0x0000 },
3115
3116 /* Green Setting */
3117 { 0x1f, 0x0005 },
3118 { 0x05, 0x8b5b },
3119 { 0x06, 0x9222 },
3120 { 0x05, 0x8b6d },
3121 { 0x06, 0x8000 },
3122 { 0x05, 0x8b76 },
3123 { 0x06, 0x8000 },
3124 { 0x1f, 0x0000 }
3125 };
3126
3127 rtl_apply_firmware(tp);
3128
3129 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3130
3131 /* For 4-corner performance improve */
3132 rtl_writephy(tp, 0x1f, 0x0005);
3133 rtl_writephy(tp, 0x05, 0x8b80);
3134 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
3135 rtl_writephy(tp, 0x1f, 0x0000);
3136
3137 /* PHY auto speed down */
3138 rtl_writephy(tp, 0x1f, 0x0004);
3139 rtl_writephy(tp, 0x1f, 0x0007);
3140 rtl_writephy(tp, 0x1e, 0x002d);
3141 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3142 rtl_writephy(tp, 0x1f, 0x0002);
3143 rtl_writephy(tp, 0x1f, 0x0000);
3144 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3145
3146 /* improve 10M EEE waveform */
3147 rtl_writephy(tp, 0x1f, 0x0005);
3148 rtl_writephy(tp, 0x05, 0x8b86);
3149 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3150 rtl_writephy(tp, 0x1f, 0x0000);
3151
3152 /* Improve 2-pair detection performance */
3153 rtl_writephy(tp, 0x1f, 0x0005);
3154 rtl_writephy(tp, 0x05, 0x8b85);
3155 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3156 rtl_writephy(tp, 0x1f, 0x0000);
3157
3158 /* EEE setting */
fdf6fc06 3159 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003, ERIAR_EXGMAC);
70090424
HW		 3160 rtl_writephy(tp, 0x1f, 0x0005);
3161 rtl_writephy(tp, 0x05, 0x8b85);
3162 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3163 rtl_writephy(tp, 0x1f, 0x0004);
3164 rtl_writephy(tp, 0x1f, 0x0007);
3165 rtl_writephy(tp, 0x1e, 0x0020);
1b23a3e3 3166 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
70090424
HW		 3167 rtl_writephy(tp, 0x1f, 0x0002);
3168 rtl_writephy(tp, 0x1f, 0x0000);
3169 rtl_writephy(tp, 0x0d, 0x0007);
3170 rtl_writephy(tp, 0x0e, 0x003c);
3171 rtl_writephy(tp, 0x0d, 0x4007);
3172 rtl_writephy(tp, 0x0e, 0x0000);
3173 rtl_writephy(tp, 0x0d, 0x0000);
3174
3175 /* Green feature */
3176 rtl_writephy(tp, 0x1f, 0x0003);
3177 rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
3178 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
3179 rtl_writephy(tp, 0x1f, 0x0000);
e0c07557 3180
9ecb9aab 3181 /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3182 rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
70090424
HW		 3183}
3184
5f886e08
HW		 3185static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3186{
3187 /* For 4-corner performance improve */
3188 rtl_writephy(tp, 0x1f, 0x0005);
3189 rtl_writephy(tp, 0x05, 0x8b80);
3190 rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
3191 rtl_writephy(tp, 0x1f, 0x0000);
3192
3193 /* PHY auto speed down */
3194 rtl_writephy(tp, 0x1f, 0x0007);
3195 rtl_writephy(tp, 0x1e, 0x002d);
3196 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3197 rtl_writephy(tp, 0x1f, 0x0000);
3198 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3199
3200 /* Improve 10M EEE waveform */
3201 rtl_writephy(tp, 0x1f, 0x0005);
3202 rtl_writephy(tp, 0x05, 0x8b86);
3203 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3204 rtl_writephy(tp, 0x1f, 0x0000);
3205}
3206
c2218925
HW		 3207static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3208{
3209 static const struct phy_reg phy_reg_init[] = {
3210 /* Channel estimation fine tune */
3211 { 0x1f, 0x0003 },
3212 { 0x09, 0xa20f },
3213 { 0x1f, 0x0000 },
3214
3215 /* Modify green table for giga & fnet */
3216 { 0x1f, 0x0005 },
3217 { 0x05, 0x8b55 },
3218 { 0x06, 0x0000 },
3219 { 0x05, 0x8b5e },
3220 { 0x06, 0x0000 },
3221 { 0x05, 0x8b67 },
3222 { 0x06, 0x0000 },
3223 { 0x05, 0x8b70 },
3224 { 0x06, 0x0000 },
3225 { 0x1f, 0x0000 },
3226 { 0x1f, 0x0007 },
3227 { 0x1e, 0x0078 },
3228 { 0x17, 0x0000 },
3229 { 0x19, 0x00fb },
3230 { 0x1f, 0x0000 },
3231
3232 /* Modify green table for 10M */
3233 { 0x1f, 0x0005 },
3234 { 0x05, 0x8b79 },
3235 { 0x06, 0xaa00 },
3236 { 0x1f, 0x0000 },
3237
3238 /* Disable hiimpedance detection (RTCT) */
3239 { 0x1f, 0x0003 },
3240 { 0x01, 0x328a },
3241 { 0x1f, 0x0000 }
3242 };
3243
3244 rtl_apply_firmware(tp);
3245
3246 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3247
5f886e08 3248 rtl8168f_hw_phy_config(tp);
c2218925
HW		 3249
3250 /* Improve 2-pair detection performance */
3251 rtl_writephy(tp, 0x1f, 0x0005);
3252 rtl_writephy(tp, 0x05, 0x8b85);
3253 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3254 rtl_writephy(tp, 0x1f, 0x0000);
3255}
3256
3257static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3258{
3259 rtl_apply_firmware(tp);
3260
5f886e08 3261 rtl8168f_hw_phy_config(tp);
c2218925
HW		 3262}
3263
b3d7b2f2
HW		 3264static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3265{
b3d7b2f2
HW		 3266 static const struct phy_reg phy_reg_init[] = {
3267 /* Channel estimation fine tune */
3268 { 0x1f, 0x0003 },
3269 { 0x09, 0xa20f },
3270 { 0x1f, 0x0000 },
3271
3272 /* Modify green table for giga & fnet */
3273 { 0x1f, 0x0005 },
3274 { 0x05, 0x8b55 },
3275 { 0x06, 0x0000 },
3276 { 0x05, 0x8b5e },
3277 { 0x06, 0x0000 },
3278 { 0x05, 0x8b67 },
3279 { 0x06, 0x0000 },
3280 { 0x05, 0x8b70 },
3281 { 0x06, 0x0000 },
3282 { 0x1f, 0x0000 },
3283 { 0x1f, 0x0007 },
3284 { 0x1e, 0x0078 },
3285 { 0x17, 0x0000 },
3286 { 0x19, 0x00aa },
3287 { 0x1f, 0x0000 },
3288
3289 /* Modify green table for 10M */
3290 { 0x1f, 0x0005 },
3291 { 0x05, 0x8b79 },
3292 { 0x06, 0xaa00 },
3293 { 0x1f, 0x0000 },
3294
3295 /* Disable hiimpedance detection (RTCT) */
3296 { 0x1f, 0x0003 },
3297 { 0x01, 0x328a },
3298 { 0x1f, 0x0000 }
3299 };
3300
3301
3302 rtl_apply_firmware(tp);
3303
3304 rtl8168f_hw_phy_config(tp);
3305
3306 /* Improve 2-pair detection performance */
3307 rtl_writephy(tp, 0x1f, 0x0005);
3308 rtl_writephy(tp, 0x05, 0x8b85);
3309 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3310 rtl_writephy(tp, 0x1f, 0x0000);
3311
3312 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3313
3314 /* Modify green table for giga */
3315 rtl_writephy(tp, 0x1f, 0x0005);
3316 rtl_writephy(tp, 0x05, 0x8b54);
3317 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0800);
3318 rtl_writephy(tp, 0x05, 0x8b5d);
3319 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0800);
3320 rtl_writephy(tp, 0x05, 0x8a7c);
3321 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3322 rtl_writephy(tp, 0x05, 0x8a7f);
3323 rtl_w1w0_phy(tp, 0x06, 0x0100, 0x0000);
3324 rtl_writephy(tp, 0x05, 0x8a82);
3325 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3326 rtl_writephy(tp, 0x05, 0x8a85);
3327 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3328 rtl_writephy(tp, 0x05, 0x8a88);
3329 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3330 rtl_writephy(tp, 0x1f, 0x0000);
3331
3332 /* uc same-seed solution */
3333 rtl_writephy(tp, 0x1f, 0x0005);
3334 rtl_writephy(tp, 0x05, 0x8b85);
3335 rtl_w1w0_phy(tp, 0x06, 0x8000, 0x0000);
3336 rtl_writephy(tp, 0x1f, 0x0000);
3337
3338 /* eee setting */
fdf6fc06 3339 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
b3d7b2f2
HW		 3340 rtl_writephy(tp, 0x1f, 0x0005);
3341 rtl_writephy(tp, 0x05, 0x8b85);
3342 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3343 rtl_writephy(tp, 0x1f, 0x0004);
3344 rtl_writephy(tp, 0x1f, 0x0007);
3345 rtl_writephy(tp, 0x1e, 0x0020);
3346 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
3347 rtl_writephy(tp, 0x1f, 0x0000);
3348 rtl_writephy(tp, 0x0d, 0x0007);
3349 rtl_writephy(tp, 0x0e, 0x003c);
3350 rtl_writephy(tp, 0x0d, 0x4007);
3351 rtl_writephy(tp, 0x0e, 0x0000);
3352 rtl_writephy(tp, 0x0d, 0x0000);
3353
3354 /* Green feature */
3355 rtl_writephy(tp, 0x1f, 0x0003);
3356 rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
3357 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
3358 rtl_writephy(tp, 0x1f, 0x0000);
3359}
3360
c558386b
HW		 3361static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3362{
c558386b
HW		 3363 rtl_apply_firmware(tp);
3364
41f44d13 3365 rtl_writephy(tp, 0x1f, 0x0a46);
3366 if (rtl_readphy(tp, 0x10) & 0x0100) {
3367 rtl_writephy(tp, 0x1f, 0x0bcc);
3368 rtl_w1w0_phy(tp, 0x12, 0x0000, 0x8000);
3369 } else {
3370 rtl_writephy(tp, 0x1f, 0x0bcc);
3371 rtl_w1w0_phy(tp, 0x12, 0x8000, 0x0000);
3372 }
c558386b 3373
41f44d13 3374 rtl_writephy(tp, 0x1f, 0x0a46);
3375 if (rtl_readphy(tp, 0x13) & 0x0100) {
3376 rtl_writephy(tp, 0x1f, 0x0c41);
3377 rtl_w1w0_phy(tp, 0x15, 0x0002, 0x0000);
3378 } else {
fe7524c0 3379 rtl_writephy(tp, 0x1f, 0x0c41);
3380 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0002);
41f44d13 3381 }
c558386b 3382
41f44d13 3383 /* Enable PHY auto speed down */
3384 rtl_writephy(tp, 0x1f, 0x0a44);
3385 rtl_w1w0_phy(tp, 0x11, 0x000c, 0x0000);
c558386b 3386
fe7524c0 3387 rtl_writephy(tp, 0x1f, 0x0bcc);
3388 rtl_w1w0_phy(tp, 0x14, 0x0100, 0x0000);
3389 rtl_writephy(tp, 0x1f, 0x0a44);
3390 rtl_w1w0_phy(tp, 0x11, 0x00c0, 0x0000);
3391 rtl_writephy(tp, 0x1f, 0x0a43);
3392 rtl_writephy(tp, 0x13, 0x8084);
3393 rtl_w1w0_phy(tp, 0x14, 0x0000, 0x6000);
3394 rtl_w1w0_phy(tp, 0x10, 0x1003, 0x0000);
3395
41f44d13 3396 /* EEE auto-fallback function */
3397 rtl_writephy(tp, 0x1f, 0x0a4b);
3398 rtl_w1w0_phy(tp, 0x11, 0x0004, 0x0000);
c558386b 3399
41f44d13 3400 /* Enable UC LPF tune function */
3401 rtl_writephy(tp, 0x1f, 0x0a43);
3402 rtl_writephy(tp, 0x13, 0x8012);
3403 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3404
3405 rtl_writephy(tp, 0x1f, 0x0c42);
3406 rtl_w1w0_phy(tp, 0x11, 0x4000, 0x2000);
3407
fe7524c0 3408 /* Improve SWR Efficiency */
3409 rtl_writephy(tp, 0x1f, 0x0bcd);
3410 rtl_writephy(tp, 0x14, 0x5065);
3411 rtl_writephy(tp, 0x14, 0xd065);
3412 rtl_writephy(tp, 0x1f, 0x0bc8);
3413 rtl_writephy(tp, 0x11, 0x5655);
3414 rtl_writephy(tp, 0x1f, 0x0bcd);
3415 rtl_writephy(tp, 0x14, 0x1065);
3416 rtl_writephy(tp, 0x14, 0x9065);
3417 rtl_writephy(tp, 0x14, 0x1065);
3418
41f44d13 3419 rtl_writephy(tp, 0x1f, 0x0000);
c558386b
HW		 3420}
3421
4da19633 3422static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2857ffb7 3423{
350f7596 3424 static const struct phy_reg phy_reg_init[] = {
2857ffb7
FR		 3425 { 0x1f, 0x0003 },
3426 { 0x08, 0x441d },
3427 { 0x01, 0x9100 },
3428 { 0x1f, 0x0000 }
3429 };
3430
4da19633 3431 rtl_writephy(tp, 0x1f, 0x0000);
3432 rtl_patchphy(tp, 0x11, 1 << 12);
3433 rtl_patchphy(tp, 0x19, 1 << 13);
3434 rtl_patchphy(tp, 0x10, 1 << 15);
2857ffb7 3435
4da19633 3436 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2857ffb7
FR		 3437}
3438
5a5e4443
HW		 3439static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3440{
3441 static const struct phy_reg phy_reg_init[] = {
3442 { 0x1f, 0x0005 },
3443 { 0x1a, 0x0000 },
3444 { 0x1f, 0x0000 },
3445
3446 { 0x1f, 0x0004 },
3447 { 0x1c, 0x0000 },
3448 { 0x1f, 0x0000 },
3449
3450 { 0x1f, 0x0001 },
3451 { 0x15, 0x7701 },
3452 { 0x1f, 0x0000 }
3453 };
3454
3455 /* Disable ALDPS before ram code */
eef63cc1
FR		 3456 rtl_writephy(tp, 0x1f, 0x0000);
3457 rtl_writephy(tp, 0x18, 0x0310);
3458 msleep(100);
5a5e4443 3459
953a12cc 3460 rtl_apply_firmware(tp);
5a5e4443
HW		 3461
3462 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3463}
3464
7e18dca1
HW		 3465static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
3466{
7e18dca1 3467 /* Disable ALDPS before setting firmware */
eef63cc1
FR		 3468 rtl_writephy(tp, 0x1f, 0x0000);
3469 rtl_writephy(tp, 0x18, 0x0310);
3470 msleep(20);
7e18dca1
HW		 3471
3472 rtl_apply_firmware(tp);
3473
3474 /* EEE setting */
fdf6fc06 3475 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
7e18dca1
HW		 3476 rtl_writephy(tp, 0x1f, 0x0004);
3477 rtl_writephy(tp, 0x10, 0x401f);
3478 rtl_writephy(tp, 0x19, 0x7030);
3479 rtl_writephy(tp, 0x1f, 0x0000);
3480}
3481
5598bfe5
HW		 3482static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
3483{
5598bfe5
HW		 3484 static const struct phy_reg phy_reg_init[] = {
3485 { 0x1f, 0x0004 },
3486 { 0x10, 0xc07f },
3487 { 0x19, 0x7030 },
3488 { 0x1f, 0x0000 }
3489 };
3490
3491 /* Disable ALDPS before ram code */
eef63cc1
FR		 3492 rtl_writephy(tp, 0x1f, 0x0000);
3493 rtl_writephy(tp, 0x18, 0x0310);
3494 msleep(100);
5598bfe5
HW		 3495
3496 rtl_apply_firmware(tp);
3497
fdf6fc06 3498 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5598bfe5
HW		 3499 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3500
fdf6fc06 3501 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5598bfe5
HW		 3502}
3503
5615d9f1
FR		 3504static void rtl_hw_phy_config(struct net_device *dev)
3505{
3506 struct rtl8169_private *tp = netdev_priv(dev);
5615d9f1
FR		 3507
3508 rtl8169_print_mac_version(tp);
3509
3510 switch (tp->mac_version) {
3511 case RTL_GIGA_MAC_VER_01:
3512 break;
3513 case RTL_GIGA_MAC_VER_02:
3514 case RTL_GIGA_MAC_VER_03:
4da19633 3515 rtl8169s_hw_phy_config(tp);
5615d9f1
FR		 3516 break;
3517 case RTL_GIGA_MAC_VER_04:
4da19633 3518 rtl8169sb_hw_phy_config(tp);
5615d9f1 3519 break;
2e955856 3520 case RTL_GIGA_MAC_VER_05:
4da19633 3521 rtl8169scd_hw_phy_config(tp);
2e955856 3522 break;
8c7006aa 3523 case RTL_GIGA_MAC_VER_06:
4da19633 3524 rtl8169sce_hw_phy_config(tp);
8c7006aa 3525 break;
2857ffb7
FR		 3526 case RTL_GIGA_MAC_VER_07:
3527 case RTL_GIGA_MAC_VER_08:
3528 case RTL_GIGA_MAC_VER_09:
4da19633 3529 rtl8102e_hw_phy_config(tp);
2857ffb7 3530 break;
236b8082 3531 case RTL_GIGA_MAC_VER_11:
4da19633 3532 rtl8168bb_hw_phy_config(tp);
236b8082
FR		 3533 break;
3534 case RTL_GIGA_MAC_VER_12:
4da19633 3535 rtl8168bef_hw_phy_config(tp);
236b8082
FR		 3536 break;
3537 case RTL_GIGA_MAC_VER_17:
4da19633 3538 rtl8168bef_hw_phy_config(tp);
236b8082 3539 break;
867763c1 3540 case RTL_GIGA_MAC_VER_18:
4da19633 3541 rtl8168cp_1_hw_phy_config(tp);
867763c1
FR		 3542 break;
3543 case RTL_GIGA_MAC_VER_19:
4da19633 3544 rtl8168c_1_hw_phy_config(tp);
867763c1 3545 break;
7da97ec9 3546 case RTL_GIGA_MAC_VER_20:
4da19633 3547 rtl8168c_2_hw_phy_config(tp);
7da97ec9 3548 break;
197ff761 3549 case RTL_GIGA_MAC_VER_21:
4da19633 3550 rtl8168c_3_hw_phy_config(tp);
197ff761 3551 break;
6fb07058 3552 case RTL_GIGA_MAC_VER_22:
4da19633 3553 rtl8168c_4_hw_phy_config(tp);
6fb07058 3554 break;
ef3386f0 3555 case RTL_GIGA_MAC_VER_23:
7f3e3d3a 3556 case RTL_GIGA_MAC_VER_24:
4da19633 3557 rtl8168cp_2_hw_phy_config(tp);
ef3386f0 3558 break;
5b538df9 3559 case RTL_GIGA_MAC_VER_25:
bca03d5f 3560 rtl8168d_1_hw_phy_config(tp);
daf9df6d 3561 break;
3562 case RTL_GIGA_MAC_VER_26:
bca03d5f 3563 rtl8168d_2_hw_phy_config(tp);
daf9df6d 3564 break;
3565 case RTL_GIGA_MAC_VER_27:
4da19633 3566 rtl8168d_3_hw_phy_config(tp);
5b538df9 3567 break;
e6de30d6 3568 case RTL_GIGA_MAC_VER_28:
3569 rtl8168d_4_hw_phy_config(tp);
3570 break;
5a5e4443
HW		 3571 case RTL_GIGA_MAC_VER_29:
3572 case RTL_GIGA_MAC_VER_30:
3573 rtl8105e_hw_phy_config(tp);
3574 break;
cecb5fd7
FR		 3575 case RTL_GIGA_MAC_VER_31:
3576 /* None. */
3577 break;
01dc7fec 3578 case RTL_GIGA_MAC_VER_32:
01dc7fec 3579 case RTL_GIGA_MAC_VER_33:
70090424
HW		 3580 rtl8168e_1_hw_phy_config(tp);
3581 break;
3582 case RTL_GIGA_MAC_VER_34:
3583 rtl8168e_2_hw_phy_config(tp);
01dc7fec 3584 break;
c2218925
HW		 3585 case RTL_GIGA_MAC_VER_35:
3586 rtl8168f_1_hw_phy_config(tp);
3587 break;
3588 case RTL_GIGA_MAC_VER_36:
3589 rtl8168f_2_hw_phy_config(tp);
3590 break;
ef3386f0 3591
7e18dca1
HW		 3592 case RTL_GIGA_MAC_VER_37:
3593 rtl8402_hw_phy_config(tp);
3594 break;
3595
b3d7b2f2
HW		 3596 case RTL_GIGA_MAC_VER_38:
3597 rtl8411_hw_phy_config(tp);
3598 break;
3599
5598bfe5
HW		 3600 case RTL_GIGA_MAC_VER_39:
3601 rtl8106e_hw_phy_config(tp);
3602 break;
3603
c558386b
HW		 3604 case RTL_GIGA_MAC_VER_40:
3605 rtl8168g_1_hw_phy_config(tp);
3606 break;
3607
3608 case RTL_GIGA_MAC_VER_41:
5615d9f1
FR		 3609 default:
3610 break;
3611 }
3612}
3613
da78dbff 3614static void rtl_phy_work(struct rtl8169_private *tp)
1da177e4 3615{
1da177e4
LT		 3616 struct timer_list *timer = &tp->timer;
3617 void __iomem *ioaddr = tp->mmio_addr;
3618 unsigned long timeout = RTL8169_PHY_TIMEOUT;
3619
bcf0bf90 3620 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1da177e4 3621
4da19633 3622 if (tp->phy_reset_pending(tp)) {
5b0384f4 3623 /*
1da177e4
LT		 3624 * A busy loop could burn quite a few cycles on nowadays CPU.
3625 * Let's delay the execution of the timer for a few ticks.
3626 */
3627 timeout = HZ/10;
3628 goto out_mod_timer;
3629 }
3630
3631 if (tp->link_ok(ioaddr))
da78dbff 3632 return;
1da177e4 3633
da78dbff 3634 netif_warn(tp, link, tp->dev, "PHY reset until link up\n");
1da177e4 3635
4da19633 3636 tp->phy_reset_enable(tp);
1da177e4
LT		 3637
3638out_mod_timer:
3639 mod_timer(timer, jiffies + timeout);
da78dbff
FR		 3640}
3641
3642static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
3643{
da78dbff
FR		 3644 if (!test_and_set_bit(flag, tp->wk.flags))
3645 schedule_work(&tp->wk.work);
da78dbff
FR		 3646}
3647
3648static void rtl8169_phy_timer(unsigned long __opaque)
3649{
3650 struct net_device *dev = (struct net_device *)__opaque;
3651 struct rtl8169_private *tp = netdev_priv(dev);
3652
98ddf986 3653 rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
1da177e4
LT		 3654}
3655
1da177e4
LT		 3656static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
3657 void __iomem *ioaddr)
3658{
3659 iounmap(ioaddr);
3660 pci_release_regions(pdev);
87aeec76 3661 pci_clear_mwi(pdev);
1da177e4
LT		 3662 pci_disable_device(pdev);
3663 free_netdev(dev);
3664}
3665
ffc46952
FR		 3666DECLARE_RTL_COND(rtl_phy_reset_cond)
3667{
3668 return tp->phy_reset_pending(tp);
3669}
3670
bf793295
FR		 3671static void rtl8169_phy_reset(struct net_device *dev,
3672 struct rtl8169_private *tp)
3673{
4da19633 3674 tp->phy_reset_enable(tp);
ffc46952 3675 rtl_msleep_loop_wait_low(tp, &rtl_phy_reset_cond, 1, 100);
bf793295
FR		 3676}
3677
2544bfc0
FR		 3678static bool rtl_tbi_enabled(struct rtl8169_private *tp)
3679{
3680 void __iomem *ioaddr = tp->mmio_addr;
3681
3682 return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
3683 (RTL_R8(PHYstatus) & TBI_Enable);
3684}
3685
4ff96fa6
FR		 3686static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3687{
3688 void __iomem *ioaddr = tp->mmio_addr;
4ff96fa6 3689
5615d9f1 3690 rtl_hw_phy_config(dev);
4ff96fa6 3691
77332894
MS		 3692 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3693 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3694 RTL_W8(0x82, 0x01);
3695 }
4ff96fa6 3696
6dccd16b
FR		 3697 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3698
3699 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3700 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 3701
bcf0bf90 3702 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4ff96fa6
FR		 3703 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3704 RTL_W8(0x82, 0x01);
3705 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
4da19633 3706 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4ff96fa6
FR		 3707 }
3708
bf793295
FR		 3709 rtl8169_phy_reset(dev, tp);
3710
54405cde 3711 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
cecb5fd7
FR		 3712 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3713 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
3714 (tp->mii.supports_gmii ?
3715 ADVERTISED_1000baseT_Half |
3716 ADVERTISED_1000baseT_Full : 0));
4ff96fa6 3717
2544bfc0 3718 if (rtl_tbi_enabled(tp))
bf82c189 3719 netif_info(tp, link, dev, "TBI auto-negotiating\n");
4ff96fa6
FR		 3720}
3721
773d2021
FR		 3722static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3723{
3724 void __iomem *ioaddr = tp->mmio_addr;
773d2021 3725
da78dbff 3726 rtl_lock_work(tp);
773d2021
FR		 3727
3728 RTL_W8(Cfg9346, Cfg9346_Unlock);
908ba2bf 3729
9ecb9aab 3730 RTL_W32(MAC4, addr[4] | addr[5] << 8);
908ba2bf 3731 RTL_R32(MAC4);
3732
9ecb9aab 3733 RTL_W32(MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
908ba2bf 3734 RTL_R32(MAC0);
3735
9ecb9aab 3736 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
3737 rtl_rar_exgmac_set(tp, addr);
c28aa385 3738
773d2021
FR		 3739 RTL_W8(Cfg9346, Cfg9346_Lock);
3740
da78dbff 3741 rtl_unlock_work(tp);
773d2021
FR		 3742}
3743
3744static int rtl_set_mac_address(struct net_device *dev, void *p)
3745{
3746 struct rtl8169_private *tp = netdev_priv(dev);
3747 struct sockaddr *addr = p;
3748
3749 if (!is_valid_ether_addr(addr->sa_data))
3750 return -EADDRNOTAVAIL;
3751
3752 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3753
3754 rtl_rar_set(tp, dev->dev_addr);
3755
3756 return 0;
3757}
3758
5f787a1a
FR		 3759static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3760{
3761 struct rtl8169_private *tp = netdev_priv(dev);
3762 struct mii_ioctl_data *data = if_mii(ifr);
3763
8b4ab28d
FR		 3764 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
3765}
5f787a1a 3766
cecb5fd7
FR		 3767static int rtl_xmii_ioctl(struct rtl8169_private *tp,
3768 struct mii_ioctl_data *data, int cmd)
8b4ab28d 3769{
5f787a1a
FR		 3770 switch (cmd) {
3771 case SIOCGMIIPHY:
3772 data->phy_id = 32; /* Internal PHY */
3773 return 0;
3774
3775 case SIOCGMIIREG:
4da19633 3776 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
5f787a1a
FR		 3777 return 0;
3778
3779 case SIOCSMIIREG:
4da19633 3780 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
5f787a1a
FR		 3781 return 0;
3782 }
3783 return -EOPNOTSUPP;
3784}
3785
8b4ab28d
FR		 3786static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
3787{
3788 return -EOPNOTSUPP;
3789}
3790
fbac58fc
FR		 3791static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
3792{
3793 if (tp->features & RTL_FEATURE_MSI) {
3794 pci_disable_msi(pdev);
3795 tp->features &= ~RTL_FEATURE_MSI;
3796 }
3797}
3798
baf63293 3799static void rtl_init_mdio_ops(struct rtl8169_private *tp)
c0e45c1c 3800{
3801 struct mdio_ops *ops = &tp->mdio_ops;
3802
3803 switch (tp->mac_version) {
3804 case RTL_GIGA_MAC_VER_27:
3805 ops->write = r8168dp_1_mdio_write;
3806 ops->read = r8168dp_1_mdio_read;
3807 break;
e6de30d6 3808 case RTL_GIGA_MAC_VER_28:
4804b3b3 3809 case RTL_GIGA_MAC_VER_31:
e6de30d6 3810 ops->write = r8168dp_2_mdio_write;
3811 ops->read = r8168dp_2_mdio_read;
3812 break;
c558386b
HW		 3813 case RTL_GIGA_MAC_VER_40:
3814 case RTL_GIGA_MAC_VER_41:
3815 ops->write = r8168g_mdio_write;
3816 ops->read = r8168g_mdio_read;
3817 break;
c0e45c1c 3818 default:
3819 ops->write = r8169_mdio_write;
3820 ops->read = r8169_mdio_read;
3821 break;
3822 }
3823}
3824
649b3b8c 3825static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
3826{
3827 void __iomem *ioaddr = tp->mmio_addr;
3828
3829 switch (tp->mac_version) {
b00e69de
CB		 3830 case RTL_GIGA_MAC_VER_25:
3831 case RTL_GIGA_MAC_VER_26:
649b3b8c 3832 case RTL_GIGA_MAC_VER_29:
3833 case RTL_GIGA_MAC_VER_30:
3834 case RTL_GIGA_MAC_VER_32:
3835 case RTL_GIGA_MAC_VER_33:
3836 case RTL_GIGA_MAC_VER_34:
7e18dca1 3837 case RTL_GIGA_MAC_VER_37:
b3d7b2f2 3838 case RTL_GIGA_MAC_VER_38:
5598bfe5 3839 case RTL_GIGA_MAC_VER_39:
c558386b
HW		 3840 case RTL_GIGA_MAC_VER_40:
3841 case RTL_GIGA_MAC_VER_41:
649b3b8c 3842 RTL_W32(RxConfig, RTL_R32(RxConfig) |
3843 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3844 break;
3845 default:
3846 break;
3847 }
3848}
3849
3850static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
3851{
3852 if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
3853 return false;
3854
3855 rtl_writephy(tp, 0x1f, 0x0000);
3856 rtl_writephy(tp, MII_BMCR, 0x0000);
3857
3858 rtl_wol_suspend_quirk(tp);
3859
3860 return true;
3861}
3862
065c27c1 3863static void r810x_phy_power_down(struct rtl8169_private *tp)
3864{
3865 rtl_writephy(tp, 0x1f, 0x0000);
3866 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3867}
3868
3869static void r810x_phy_power_up(struct rtl8169_private *tp)
3870{
3871 rtl_writephy(tp, 0x1f, 0x0000);
3872 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3873}
3874
3875static void r810x_pll_power_down(struct rtl8169_private *tp)
3876{
0004299a
HW		 3877 void __iomem *ioaddr = tp->mmio_addr;
3878
649b3b8c 3879 if (rtl_wol_pll_power_down(tp))
065c27c1 3880 return;
065c27c1 3881
3882 r810x_phy_power_down(tp);
0004299a
HW		 3883
3884 switch (tp->mac_version) {
3885 case RTL_GIGA_MAC_VER_07:
3886 case RTL_GIGA_MAC_VER_08:
3887 case RTL_GIGA_MAC_VER_09:
3888 case RTL_GIGA_MAC_VER_10:
3889 case RTL_GIGA_MAC_VER_13:
3890 case RTL_GIGA_MAC_VER_16:
3891 break;
3892 default:
3893 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3894 break;
3895 }
065c27c1 3896}
3897
3898static void r810x_pll_power_up(struct rtl8169_private *tp)
3899{
0004299a
HW		 3900 void __iomem *ioaddr = tp->mmio_addr;
3901
065c27c1 3902 r810x_phy_power_up(tp);
0004299a
HW		 3903
3904 switch (tp->mac_version) {
3905 case RTL_GIGA_MAC_VER_07:
3906 case RTL_GIGA_MAC_VER_08:
3907 case RTL_GIGA_MAC_VER_09:
3908 case RTL_GIGA_MAC_VER_10:
3909 case RTL_GIGA_MAC_VER_13:
3910 case RTL_GIGA_MAC_VER_16:
3911 break;
3912 default:
3913 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3914 break;
3915 }
065c27c1 3916}
3917
3918static void r8168_phy_power_up(struct rtl8169_private *tp)
3919{
3920 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3921 switch (tp->mac_version) {
3922 case RTL_GIGA_MAC_VER_11:
3923 case RTL_GIGA_MAC_VER_12:
3924 case RTL_GIGA_MAC_VER_17:
3925 case RTL_GIGA_MAC_VER_18:
3926 case RTL_GIGA_MAC_VER_19:
3927 case RTL_GIGA_MAC_VER_20:
3928 case RTL_GIGA_MAC_VER_21:
3929 case RTL_GIGA_MAC_VER_22:
3930 case RTL_GIGA_MAC_VER_23:
3931 case RTL_GIGA_MAC_VER_24:
3932 case RTL_GIGA_MAC_VER_25:
3933 case RTL_GIGA_MAC_VER_26:
3934 case RTL_GIGA_MAC_VER_27:
3935 case RTL_GIGA_MAC_VER_28:
3936 case RTL_GIGA_MAC_VER_31:
3937 rtl_writephy(tp, 0x0e, 0x0000);
3938 break;
3939 default:
3940 break;
3941 }
065c27c1 3942 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3943}
3944
3945static void r8168_phy_power_down(struct rtl8169_private *tp)
3946{
3947 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3948 switch (tp->mac_version) {
3949 case RTL_GIGA_MAC_VER_32:
3950 case RTL_GIGA_MAC_VER_33:
3951 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
3952 break;
3953
3954 case RTL_GIGA_MAC_VER_11:
3955 case RTL_GIGA_MAC_VER_12:
3956 case RTL_GIGA_MAC_VER_17:
3957 case RTL_GIGA_MAC_VER_18:
3958 case RTL_GIGA_MAC_VER_19:
3959 case RTL_GIGA_MAC_VER_20:
3960 case RTL_GIGA_MAC_VER_21:
3961 case RTL_GIGA_MAC_VER_22:
3962 case RTL_GIGA_MAC_VER_23:
3963 case RTL_GIGA_MAC_VER_24:
3964 case RTL_GIGA_MAC_VER_25:
3965 case RTL_GIGA_MAC_VER_26:
3966 case RTL_GIGA_MAC_VER_27:
3967 case RTL_GIGA_MAC_VER_28:
3968 case RTL_GIGA_MAC_VER_31:
3969 rtl_writephy(tp, 0x0e, 0x0200);
3970 default:
3971 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3972 break;
3973 }
065c27c1 3974}
3975
3976static void r8168_pll_power_down(struct rtl8169_private *tp)
3977{
3978 void __iomem *ioaddr = tp->mmio_addr;
3979
cecb5fd7
FR		 3980 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3981 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3982 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
4804b3b3 3983 r8168dp_check_dash(tp)) {
065c27c1 3984 return;
5d2e1957 3985 }
065c27c1 3986
cecb5fd7
FR		 3987 if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
3988 tp->mac_version == RTL_GIGA_MAC_VER_24) &&
065c27c1 3989 (RTL_R16(CPlusCmd) & ASF)) {
3990 return;
3991 }
3992
01dc7fec 3993 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3994 tp->mac_version == RTL_GIGA_MAC_VER_33)
fdf6fc06 3995 rtl_ephy_write(tp, 0x19, 0xff64);
01dc7fec 3996
649b3b8c 3997 if (rtl_wol_pll_power_down(tp))
065c27c1 3998 return;
065c27c1 3999
4000 r8168_phy_power_down(tp);
4001
4002 switch (tp->mac_version) {
4003 case RTL_GIGA_MAC_VER_25:
4004 case RTL_GIGA_MAC_VER_26:
5d2e1957
HW		 4005 case RTL_GIGA_MAC_VER_27:
4006 case RTL_GIGA_MAC_VER_28:
4804b3b3 4007 case RTL_GIGA_MAC_VER_31:
01dc7fec 4008 case RTL_GIGA_MAC_VER_32:
4009 case RTL_GIGA_MAC_VER_33:
065c27c1 4010 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4011 break;
4012 }
4013}
4014
4015static void r8168_pll_power_up(struct rtl8169_private *tp)
4016{
4017 void __iomem *ioaddr = tp->mmio_addr;
4018
065c27c1 4019 switch (tp->mac_version) {
4020 case RTL_GIGA_MAC_VER_25:
4021 case RTL_GIGA_MAC_VER_26:
5d2e1957
HW		 4022 case RTL_GIGA_MAC_VER_27:
4023 case RTL_GIGA_MAC_VER_28:
4804b3b3 4024 case RTL_GIGA_MAC_VER_31:
01dc7fec 4025 case RTL_GIGA_MAC_VER_32:
4026 case RTL_GIGA_MAC_VER_33:
065c27c1 4027 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
4028 break;
4029 }
4030
4031 r8168_phy_power_up(tp);
4032}
4033
d58d46b5
FR		 4034static void rtl_generic_op(struct rtl8169_private *tp,
4035 void (*op)(struct rtl8169_private *))
065c27c1 4036{
4037 if (op)
4038 op(tp);
4039}
4040
4041static void rtl_pll_power_down(struct rtl8169_private *tp)
4042{
d58d46b5 4043 rtl_generic_op(tp, tp->pll_power_ops.down);
065c27c1 4044}
4045
4046static void rtl_pll_power_up(struct rtl8169_private *tp)
4047{
d58d46b5 4048 rtl_generic_op(tp, tp->pll_power_ops.up);
065c27c1 4049}
4050
baf63293 4051static void rtl_init_pll_power_ops(struct rtl8169_private *tp)
065c27c1 4052{
4053 struct pll_power_ops *ops = &tp->pll_power_ops;
4054
4055 switch (tp->mac_version) {
4056 case RTL_GIGA_MAC_VER_07:
4057 case RTL_GIGA_MAC_VER_08:
4058 case RTL_GIGA_MAC_VER_09:
4059 case RTL_GIGA_MAC_VER_10:
4060 case RTL_GIGA_MAC_VER_16:
5a5e4443
HW		 4061 case RTL_GIGA_MAC_VER_29:
4062 case RTL_GIGA_MAC_VER_30:
7e18dca1 4063 case RTL_GIGA_MAC_VER_37:
5598bfe5 4064 case RTL_GIGA_MAC_VER_39:
065c27c1 4065 ops->down = r810x_pll_power_down;
4066 ops->up = r810x_pll_power_up;
4067 break;
4068
4069 case RTL_GIGA_MAC_VER_11:
4070 case RTL_GIGA_MAC_VER_12:
4071 case RTL_GIGA_MAC_VER_17:
4072 case RTL_GIGA_MAC_VER_18:
4073 case RTL_GIGA_MAC_VER_19:
4074 case RTL_GIGA_MAC_VER_20:
4075 case RTL_GIGA_MAC_VER_21:
4076 case RTL_GIGA_MAC_VER_22:
4077 case RTL_GIGA_MAC_VER_23:
4078 case RTL_GIGA_MAC_VER_24:
4079 case RTL_GIGA_MAC_VER_25:
4080 case RTL_GIGA_MAC_VER_26:
4081 case RTL_GIGA_MAC_VER_27:
e6de30d6 4082 case RTL_GIGA_MAC_VER_28:
4804b3b3 4083 case RTL_GIGA_MAC_VER_31:
01dc7fec 4084 case RTL_GIGA_MAC_VER_32:
4085 case RTL_GIGA_MAC_VER_33:
70090424 4086 case RTL_GIGA_MAC_VER_34:
c2218925
HW		 4087 case RTL_GIGA_MAC_VER_35:
4088 case RTL_GIGA_MAC_VER_36:
b3d7b2f2 4089 case RTL_GIGA_MAC_VER_38:
c558386b
HW		 4090 case RTL_GIGA_MAC_VER_40:
4091 case RTL_GIGA_MAC_VER_41:
065c27c1 4092 ops->down = r8168_pll_power_down;
4093 ops->up = r8168_pll_power_up;
4094 break;
4095
4096 default:
4097 ops->down = NULL;
4098 ops->up = NULL;
4099 break;
4100 }
4101}
4102
e542a226
HW		 4103static void rtl_init_rxcfg(struct rtl8169_private *tp)
4104{
4105 void __iomem *ioaddr = tp->mmio_addr;
4106
4107 switch (tp->mac_version) {
4108 case RTL_GIGA_MAC_VER_01:
4109 case RTL_GIGA_MAC_VER_02:
4110 case RTL_GIGA_MAC_VER_03:
4111 case RTL_GIGA_MAC_VER_04:
4112 case RTL_GIGA_MAC_VER_05:
4113 case RTL_GIGA_MAC_VER_06:
4114 case RTL_GIGA_MAC_VER_10:
4115 case RTL_GIGA_MAC_VER_11:
4116 case RTL_GIGA_MAC_VER_12:
4117 case RTL_GIGA_MAC_VER_13:
4118 case RTL_GIGA_MAC_VER_14:
4119 case RTL_GIGA_MAC_VER_15:
4120 case RTL_GIGA_MAC_VER_16:
4121 case RTL_GIGA_MAC_VER_17:
4122 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
4123 break;
4124 case RTL_GIGA_MAC_VER_18:
4125 case RTL_GIGA_MAC_VER_19:
4126 case RTL_GIGA_MAC_VER_20:
4127 case RTL_GIGA_MAC_VER_21:
4128 case RTL_GIGA_MAC_VER_22:
4129 case RTL_GIGA_MAC_VER_23:
4130 case RTL_GIGA_MAC_VER_24:
eb2dc35d 4131 case RTL_GIGA_MAC_VER_34:
e542a226
HW		 4132 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
4133 break;
4134 default:
4135 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
4136 break;
4137 }
4138}
4139
92fc43b4
HW		 4140static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4141{
9fba0812 4142 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
92fc43b4
HW		 4143}
4144
d58d46b5
FR		 4145static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4146{
9c5028e9 4147 void __iomem *ioaddr = tp->mmio_addr;
4148
4149 RTL_W8(Cfg9346, Cfg9346_Unlock);
d58d46b5 4150 rtl_generic_op(tp, tp->jumbo_ops.enable);
9c5028e9 4151 RTL_W8(Cfg9346, Cfg9346_Lock);
d58d46b5
FR		 4152}
4153
4154static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4155{
9c5028e9 4156 void __iomem *ioaddr = tp->mmio_addr;
4157
4158 RTL_W8(Cfg9346, Cfg9346_Unlock);
d58d46b5 4159 rtl_generic_op(tp, tp->jumbo_ops.disable);
9c5028e9 4160 RTL_W8(Cfg9346, Cfg9346_Lock);
d58d46b5
FR		 4161}
4162
4163static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
4164{
4165 void __iomem *ioaddr = tp->mmio_addr;
4166
4167 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4168 RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
4169 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
4170}
4171
4172static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
4173{
4174 void __iomem *ioaddr = tp->mmio_addr;
4175
4176 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4177 RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
4178 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
4179}
4180
4181static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
4182{
4183 void __iomem *ioaddr = tp->mmio_addr;
4184
4185 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4186}
4187
4188static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
4189{
4190 void __iomem *ioaddr = tp->mmio_addr;
4191
4192 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4193}
4194
4195static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
4196{
4197 void __iomem *ioaddr = tp->mmio_addr;
d58d46b5
FR		 4198
4199 RTL_W8(MaxTxPacketSize, 0x3f);
4200 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4201 RTL_W8(Config4, RTL_R8(Config4) | 0x01);
4512ff9f 4202 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
d58d46b5
FR		 4203}
4204
4205static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
4206{
4207 void __iomem *ioaddr = tp->mmio_addr;
d58d46b5
FR		 4208
4209 RTL_W8(MaxTxPacketSize, 0x0c);
4210 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4211 RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
4512ff9f 4212 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
d58d46b5
FR		 4213}
4214
4215static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
4216{
4217 rtl_tx_performance_tweak(tp->pci_dev,
4218 (0x2 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4219}
4220
4221static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
4222{
4223 rtl_tx_performance_tweak(tp->pci_dev,
4224 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4225}
4226
4227static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
4228{
4229 void __iomem *ioaddr = tp->mmio_addr;
4230
4231 r8168b_0_hw_jumbo_enable(tp);
4232
4233 RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
4234}
4235
4236static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
4237{
4238 void __iomem *ioaddr = tp->mmio_addr;
4239
4240 r8168b_0_hw_jumbo_disable(tp);
4241
4242 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
4243}
4244
baf63293 4245static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
d58d46b5
FR		 4246{
4247 struct jumbo_ops *ops = &tp->jumbo_ops;
4248
4249 switch (tp->mac_version) {
4250 case RTL_GIGA_MAC_VER_11:
4251 ops->disable = r8168b_0_hw_jumbo_disable;
4252 ops->enable = r8168b_0_hw_jumbo_enable;
4253 break;
4254 case RTL_GIGA_MAC_VER_12:
4255 case RTL_GIGA_MAC_VER_17:
4256 ops->disable = r8168b_1_hw_jumbo_disable;
4257 ops->enable = r8168b_1_hw_jumbo_enable;
4258 break;
4259 case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
4260 case RTL_GIGA_MAC_VER_19:
4261 case RTL_GIGA_MAC_VER_20:
4262 case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
4263 case RTL_GIGA_MAC_VER_22:
4264 case RTL_GIGA_MAC_VER_23:
4265 case RTL_GIGA_MAC_VER_24:
4266 case RTL_GIGA_MAC_VER_25:
4267 case RTL_GIGA_MAC_VER_26:
4268 ops->disable = r8168c_hw_jumbo_disable;
4269 ops->enable = r8168c_hw_jumbo_enable;
4270 break;
4271 case RTL_GIGA_MAC_VER_27:
4272 case RTL_GIGA_MAC_VER_28:
4273 ops->disable = r8168dp_hw_jumbo_disable;
4274 ops->enable = r8168dp_hw_jumbo_enable;
4275 break;
4276 case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
4277 case RTL_GIGA_MAC_VER_32:
4278 case RTL_GIGA_MAC_VER_33:
4279 case RTL_GIGA_MAC_VER_34:
4280 ops->disable = r8168e_hw_jumbo_disable;
4281 ops->enable = r8168e_hw_jumbo_enable;
4282 break;
4283
4284 /*
4285 * No action needed for jumbo frames with 8169.
4286 * No jumbo for 810x at all.
4287 */
c558386b
HW		 4288 case RTL_GIGA_MAC_VER_40:
4289 case RTL_GIGA_MAC_VER_41:
d58d46b5
FR		 4290 default:
4291 ops->disable = NULL;
4292 ops->enable = NULL;
4293 break;
4294 }
4295}
4296
ffc46952
FR		 4297DECLARE_RTL_COND(rtl_chipcmd_cond)
4298{
4299 void __iomem *ioaddr = tp->mmio_addr;
4300
4301 return RTL_R8(ChipCmd) & CmdReset;
4302}
4303
6f43adc8
FR		 4304static void rtl_hw_reset(struct rtl8169_private *tp)
4305{
4306 void __iomem *ioaddr = tp->mmio_addr;
6f43adc8 4307
6f43adc8
FR		 4308 RTL_W8(ChipCmd, CmdReset);
4309
ffc46952 4310 rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
6f43adc8
FR		 4311}
4312
b6ffd97f 4313static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
953a12cc 4314{
b6ffd97f
FR		 4315 struct rtl_fw *rtl_fw;
4316 const char *name;
4317 int rc = -ENOMEM;
953a12cc 4318
b6ffd97f
FR		 4319 name = rtl_lookup_firmware_name(tp);
4320 if (!name)
4321 goto out_no_firmware;
953a12cc 4322
b6ffd97f
FR		 4323 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4324 if (!rtl_fw)
4325 goto err_warn;
31bd204f 4326
b6ffd97f
FR		 4327 rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
4328 if (rc < 0)
4329 goto err_free;
4330
fd112f2e
FR		 4331 rc = rtl_check_firmware(tp, rtl_fw);
4332 if (rc < 0)
4333 goto err_release_firmware;
4334
b6ffd97f
FR		 4335 tp->rtl_fw = rtl_fw;
4336out:
4337 return;
4338
fd112f2e
FR		 4339err_release_firmware:
4340 release_firmware(rtl_fw->fw);
b6ffd97f
FR		 4341err_free:
4342 kfree(rtl_fw);
4343err_warn:
4344 netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
4345 name, rc);
4346out_no_firmware:
4347 tp->rtl_fw = NULL;
4348 goto out;
4349}
4350
4351static void rtl_request_firmware(struct rtl8169_private *tp)
4352{
4353 if (IS_ERR(tp->rtl_fw))
4354 rtl_request_uncached_firmware(tp);
953a12cc
FR		 4355}
4356
92fc43b4
HW		 4357static void rtl_rx_close(struct rtl8169_private *tp)
4358{
4359 void __iomem *ioaddr = tp->mmio_addr;
92fc43b4 4360
1687b566 4361 RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
92fc43b4
HW		 4362}
4363
ffc46952
FR		 4364DECLARE_RTL_COND(rtl_npq_cond)
4365{
4366 void __iomem *ioaddr = tp->mmio_addr;
4367
4368 return RTL_R8(TxPoll) & NPQ;
4369}
4370
4371DECLARE_RTL_COND(rtl_txcfg_empty_cond)
4372{
4373 void __iomem *ioaddr = tp->mmio_addr;
4374
4375 return RTL_R32(TxConfig) & TXCFG_EMPTY;
4376}
4377
e6de30d6 4378static void rtl8169_hw_reset(struct rtl8169_private *tp)
1da177e4 4379{
e6de30d6 4380 void __iomem *ioaddr = tp->mmio_addr;
4381
1da177e4 4382 /* Disable interrupts */
811fd301 4383 rtl8169_irq_mask_and_ack(tp);
1da177e4 4384
92fc43b4
HW		 4385 rtl_rx_close(tp);
4386
5d2e1957 4387 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4804b3b3 4388 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4389 tp->mac_version == RTL_GIGA_MAC_VER_31) {
ffc46952 4390 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
c2218925
HW		 4391 } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
4392 tp->mac_version == RTL_GIGA_MAC_VER_35 ||
7e18dca1 4393 tp->mac_version == RTL_GIGA_MAC_VER_36 ||
b3d7b2f2 4394 tp->mac_version == RTL_GIGA_MAC_VER_37 ||
c558386b
HW		 4395 tp->mac_version == RTL_GIGA_MAC_VER_40 ||
4396 tp->mac_version == RTL_GIGA_MAC_VER_41 ||
b3d7b2f2 4397 tp->mac_version == RTL_GIGA_MAC_VER_38) {
c2b0c1e7 4398 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
ffc46952 4399 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
92fc43b4
HW		 4400 } else {
4401 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4402 udelay(100);
e6de30d6 4403 }
4404
92fc43b4 4405 rtl_hw_reset(tp);
1da177e4
LT		 4406}
4407
7f796d83 4408static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
9cb427b6
FR		 4409{
4410 void __iomem *ioaddr = tp->mmio_addr;
9cb427b6
FR		 4411
4412 /* Set DMA burst size and Interframe Gap Time */
4413 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4414 (InterFrameGap << TxInterFrameGapShift));
4415}
4416
07ce4064 4417static void rtl_hw_start(struct net_device *dev)
1da177e4
LT		 4418{
4419 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 4420
07ce4064
FR		 4421 tp->hw_start(dev);
4422
da78dbff 4423 rtl_irq_enable_all(tp);
07ce4064
FR		 4424}
4425
7f796d83
FR		 4426static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
4427 void __iomem *ioaddr)
4428{
4429 /*
4430 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4431 * register to be written before TxDescAddrLow to work.
4432 * Switching from MMIO to I/O access fixes the issue as well.
4433 */
4434 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
284901a9 4435 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
7f796d83 4436 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
284901a9 4437 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
7f796d83
FR		 4438}
4439
4440static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
4441{
4442 u16 cmd;
4443
4444 cmd = RTL_R16(CPlusCmd);
4445 RTL_W16(CPlusCmd, cmd);
4446 return cmd;
4447}
4448
fdd7b4c3 4449static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
7f796d83
FR		 4450{
4451 /* Low hurts. Let's disable the filtering. */
207d6e87 4452 RTL_W16(RxMaxSize, rx_buf_sz + 1);
7f796d83
FR		 4453}
4454
6dccd16b
FR		 4455static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
4456{
3744100e 4457 static const struct rtl_cfg2_info {
6dccd16b
FR		 4458 u32 mac_version;
4459 u32 clk;
4460 u32 val;
4461 } cfg2_info [] = {
4462 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
4463 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
4464 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
4465 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3744100e
FR		 4466 };
4467 const struct rtl_cfg2_info *p = cfg2_info;
6dccd16b
FR		 4468 unsigned int i;
4469 u32 clk;
4470
4471 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
cadf1855 4472 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
6dccd16b
FR		 4473 if ((p->mac_version == mac_version) && (p->clk == clk)) {
4474 RTL_W32(0x7c, p->val);
4475 break;
4476 }
4477 }
4478}
4479
e6b763ea
FR		 4480static void rtl_set_rx_mode(struct net_device *dev)
4481{
4482 struct rtl8169_private *tp = netdev_priv(dev);
4483 void __iomem *ioaddr = tp->mmio_addr;
4484 u32 mc_filter[2]; /* Multicast hash filter */
4485 int rx_mode;
4486 u32 tmp = 0;
4487
4488 if (dev->flags & IFF_PROMISC) {
4489 /* Unconditionally log net taps. */
4490 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4491 rx_mode =
4492 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4493 AcceptAllPhys;
4494 mc_filter[1] = mc_filter[0] = 0xffffffff;
4495 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4496 (dev->flags & IFF_ALLMULTI)) {
4497 /* Too many to filter perfectly -- accept all multicasts. */
4498 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4499 mc_filter[1] = mc_filter[0] = 0xffffffff;
4500 } else {
4501 struct netdev_hw_addr *ha;
4502
4503 rx_mode = AcceptBroadcast | AcceptMyPhys;
4504 mc_filter[1] = mc_filter[0] = 0;
4505 netdev_for_each_mc_addr(ha, dev) {
4506 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4507 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4508 rx_mode |= AcceptMulticast;
4509 }
4510 }
4511
4512 if (dev->features & NETIF_F_RXALL)
4513 rx_mode |= (AcceptErr | AcceptRunt);
4514
4515 tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
4516
4517 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4518 u32 data = mc_filter[0];
4519
4520 mc_filter[0] = swab32(mc_filter[1]);
4521 mc_filter[1] = swab32(data);
4522 }
4523
0481776b
NW		 4524 if (tp->mac_version == RTL_GIGA_MAC_VER_35)
4525 mc_filter[1] = mc_filter[0] = 0xffffffff;
4526
e6b763ea
FR		 4527 RTL_W32(MAR0 + 4, mc_filter[1]);
4528 RTL_W32(MAR0 + 0, mc_filter[0]);
4529
4530 RTL_W32(RxConfig, tmp);
4531}
4532
07ce4064
FR		 4533static void rtl_hw_start_8169(struct net_device *dev)
4534{
4535 struct rtl8169_private *tp = netdev_priv(dev);
4536 void __iomem *ioaddr = tp->mmio_addr;
4537 struct pci_dev *pdev = tp->pci_dev;
07ce4064 4538
9cb427b6
FR		 4539 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
4540 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
4541 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
4542 }
4543
1da177e4 4544 RTL_W8(Cfg9346, Cfg9346_Unlock);
cecb5fd7
FR		 4545 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4546 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4547 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4548 tp->mac_version == RTL_GIGA_MAC_VER_04)
9cb427b6
FR		 4549 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4550
e542a226
HW		 4551 rtl_init_rxcfg(tp);
4552
f0298f81 4553 RTL_W8(EarlyTxThres, NoEarlyTx);
1da177e4 4554
6f0333b8 4555 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
1da177e4 4556
cecb5fd7
FR		 4557 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4558 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4559 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4560 tp->mac_version == RTL_GIGA_MAC_VER_04)
c946b304 4561 rtl_set_rx_tx_config_registers(tp);
1da177e4 4562
7f796d83 4563 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1da177e4 4564
cecb5fd7
FR		 4565 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4566 tp->mac_version == RTL_GIGA_MAC_VER_03) {
06fa7358 4567 dprintk("Set MAC Reg C+CR Offset 0xE0. "
1da177e4 4568 "Bit-3 and bit-14 MUST be 1\n");
bcf0bf90 4569 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 4570 }
4571
bcf0bf90
FR		 4572 RTL_W16(CPlusCmd, tp->cp_cmd);
4573
6dccd16b
FR		 4574 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
4575
1da177e4
LT		 4576 /*
4577 * Undocumented corner. Supposedly:
4578 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4579 */
4580 RTL_W16(IntrMitigate, 0x0000);
4581
7f796d83 4582 rtl_set_rx_tx_desc_registers(tp, ioaddr);
9cb427b6 4583
cecb5fd7
FR		 4584 if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
4585 tp->mac_version != RTL_GIGA_MAC_VER_02 &&
4586 tp->mac_version != RTL_GIGA_MAC_VER_03 &&
4587 tp->mac_version != RTL_GIGA_MAC_VER_04) {
c946b304
FR		 4588 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4589 rtl_set_rx_tx_config_registers(tp);
4590 }
4591
1da177e4 4592 RTL_W8(Cfg9346, Cfg9346_Lock);
b518fa8e
FR		 4593
4594 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4595 RTL_R8(IntrMask);
1da177e4
LT		 4596
4597 RTL_W32(RxMissed, 0);
4598
07ce4064 4599 rtl_set_rx_mode(dev);
1da177e4
LT		 4600
4601 /* no early-rx interrupts */
4602 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
07ce4064 4603}
1da177e4 4604
beb1fe18
HW		 4605static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
4606{
4607 if (tp->csi_ops.write)
52989f0e 4608 tp->csi_ops.write(tp, addr, value);
beb1fe18
HW		 4609}
4610
4611static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
4612{
52989f0e 4613 return tp->csi_ops.read ? tp->csi_ops.read(tp, addr) : ~0;
beb1fe18
HW		 4614}
4615
4616static void rtl_csi_access_enable(struct rtl8169_private *tp, u32 bits)
dacf8154
FR		 4617{
4618 u32 csi;
4619
beb1fe18
HW		 4620 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
4621 rtl_csi_write(tp, 0x070c, csi | bits);
4622}
4623
4624static void rtl_csi_access_enable_1(struct rtl8169_private *tp)
4625{
4626 rtl_csi_access_enable(tp, 0x17000000);
650e8d5d 4627}
4628
beb1fe18 4629static void rtl_csi_access_enable_2(struct rtl8169_private *tp)
e6de30d6 4630{
beb1fe18 4631 rtl_csi_access_enable(tp, 0x27000000);
e6de30d6 4632}
4633
ffc46952
FR		 4634DECLARE_RTL_COND(rtl_csiar_cond)
4635{
4636 void __iomem *ioaddr = tp->mmio_addr;
4637
4638 return RTL_R32(CSIAR) & CSIAR_FLAG;
4639}
4640
52989f0e 4641static void r8169_csi_write(struct rtl8169_private *tp, int addr, int value)
650e8d5d 4642{
52989f0e 4643 void __iomem *ioaddr = tp->mmio_addr;
beb1fe18
HW		 4644
4645 RTL_W32(CSIDR, value);
4646 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4647 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4648
ffc46952 4649 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
beb1fe18
HW		 4650}
4651
52989f0e 4652static u32 r8169_csi_read(struct rtl8169_private *tp, int addr)
beb1fe18 4653{
52989f0e 4654 void __iomem *ioaddr = tp->mmio_addr;
beb1fe18
HW		 4655
4656 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
4657 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4658
ffc46952
FR		 4659 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4660 RTL_R32(CSIDR) : ~0;
beb1fe18
HW		 4661}
4662
52989f0e 4663static void r8402_csi_write(struct rtl8169_private *tp, int addr, int value)
7e18dca1 4664{
52989f0e 4665 void __iomem *ioaddr = tp->mmio_addr;
7e18dca1
HW		 4666
4667 RTL_W32(CSIDR, value);
4668 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4669 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
4670 CSIAR_FUNC_NIC);
4671
ffc46952 4672 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
7e18dca1
HW		 4673}
4674
52989f0e 4675static u32 r8402_csi_read(struct rtl8169_private *tp, int addr)
7e18dca1 4676{
52989f0e 4677 void __iomem *ioaddr = tp->mmio_addr;
7e18dca1
HW		 4678
4679 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC |
4680 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4681
ffc46952
FR		 4682 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4683 RTL_R32(CSIDR) : ~0;
7e18dca1
HW		 4684}
4685
baf63293 4686static void rtl_init_csi_ops(struct rtl8169_private *tp)
beb1fe18
HW		 4687{
4688 struct csi_ops *ops = &tp->csi_ops;
4689
4690 switch (tp->mac_version) {
4691 case RTL_GIGA_MAC_VER_01:
4692 case RTL_GIGA_MAC_VER_02:
4693 case RTL_GIGA_MAC_VER_03:
4694 case RTL_GIGA_MAC_VER_04:
4695 case RTL_GIGA_MAC_VER_05:
4696 case RTL_GIGA_MAC_VER_06:
4697 case RTL_GIGA_MAC_VER_10:
4698 case RTL_GIGA_MAC_VER_11:
4699 case RTL_GIGA_MAC_VER_12:
4700 case RTL_GIGA_MAC_VER_13:
4701 case RTL_GIGA_MAC_VER_14:
4702 case RTL_GIGA_MAC_VER_15:
4703 case RTL_GIGA_MAC_VER_16:
4704 case RTL_GIGA_MAC_VER_17:
4705 ops->write = NULL;
4706 ops->read = NULL;
4707 break;
4708
7e18dca1 4709 case RTL_GIGA_MAC_VER_37:
b3d7b2f2 4710 case RTL_GIGA_MAC_VER_38:
7e18dca1
HW		 4711 ops->write = r8402_csi_write;
4712 ops->read = r8402_csi_read;
4713 break;
4714
beb1fe18
HW		 4715 default:
4716 ops->write = r8169_csi_write;
4717 ops->read = r8169_csi_read;
4718 break;
4719 }
dacf8154
FR		 4720}
4721
4722struct ephy_info {
4723 unsigned int offset;
4724 u16 mask;
4725 u16 bits;
4726};
4727
fdf6fc06
FR		 4728static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
4729 int len)
dacf8154
FR		 4730{
4731 u16 w;
4732
4733 while (len-- > 0) {
fdf6fc06
FR		 4734 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
4735 rtl_ephy_write(tp, e->offset, w);
dacf8154
FR		 4736 e++;
4737 }
4738}
4739
b726e493
FR		 4740static void rtl_disable_clock_request(struct pci_dev *pdev)
4741{
7d7903b2
JL		 4742 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL,
4743 PCI_EXP_LNKCTL_CLKREQ_EN);
b726e493
FR		 4744}
4745
e6de30d6 4746static void rtl_enable_clock_request(struct pci_dev *pdev)
4747{
7d7903b2
JL		 4748 pcie_capability_set_word(pdev, PCI_EXP_LNKCTL,
4749 PCI_EXP_LNKCTL_CLKREQ_EN);
e6de30d6 4750}
4751
b726e493
FR		 4752#define R8168_CPCMD_QUIRK_MASK (\
4753 EnableBist | \
4754 Mac_dbgo_oe | \
4755 Force_half_dup | \
4756 Force_rxflow_en | \
4757 Force_txflow_en | \
4758 Cxpl_dbg_sel | \
4759 ASF | \
4760 PktCntrDisable | \
4761 Mac_dbgo_sel)
4762
beb1fe18 4763static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
219a1e9d 4764{
beb1fe18
HW		 4765 void __iomem *ioaddr = tp->mmio_addr;
4766 struct pci_dev *pdev = tp->pci_dev;
4767
b726e493
FR		 4768 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4769
4770 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4771
faf1e785 4772 if (tp->dev->mtu <= ETH_DATA_LEN) {
4773 rtl_tx_performance_tweak(pdev, (0x5 << MAX_READ_REQUEST_SHIFT) |
4774 PCI_EXP_DEVCTL_NOSNOOP_EN);
4775 }
219a1e9d
FR		 4776}
4777
beb1fe18 4778static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
219a1e9d 4779{
beb1fe18
HW		 4780 void __iomem *ioaddr = tp->mmio_addr;
4781
4782 rtl_hw_start_8168bb(tp);
b726e493 4783
f0298f81 4784 RTL_W8(MaxTxPacketSize, TxPacketMax);
b726e493
FR		 4785
4786 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
219a1e9d
FR		 4787}
4788
beb1fe18 4789static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
219a1e9d 4790{
beb1fe18
HW		 4791 void __iomem *ioaddr = tp->mmio_addr;
4792 struct pci_dev *pdev = tp->pci_dev;
4793
b726e493
FR		 4794 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
4795
4796 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4797
faf1e785 4798 if (tp->dev->mtu <= ETH_DATA_LEN)
4799 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
b726e493
FR		 4800
4801 rtl_disable_clock_request(pdev);
4802
4803 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
219a1e9d
FR		 4804}
4805
beb1fe18 4806static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
219a1e9d 4807{
350f7596 4808 static const struct ephy_info e_info_8168cp[] = {
b726e493
FR		 4809 { 0x01, 0, 0x0001 },
4810 { 0x02, 0x0800, 0x1000 },
4811 { 0x03, 0, 0x0042 },
4812 { 0x06, 0x0080, 0x0000 },
4813 { 0x07, 0, 0x2000 }
4814 };
4815
beb1fe18 4816 rtl_csi_access_enable_2(tp);
b726e493 4817
fdf6fc06 4818 rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
b726e493 4819
beb1fe18 4820 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 4821}
4822
beb1fe18 4823static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
ef3386f0 4824{
beb1fe18
HW		 4825 void __iomem *ioaddr = tp->mmio_addr;
4826 struct pci_dev *pdev = tp->pci_dev;
4827
4828 rtl_csi_access_enable_2(tp);
ef3386f0
FR		 4829
4830 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4831
faf1e785 4832 if (tp->dev->mtu <= ETH_DATA_LEN)
4833 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
ef3386f0
FR		 4834
4835 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4836}
4837
beb1fe18 4838static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
7f3e3d3a 4839{
beb1fe18
HW		 4840 void __iomem *ioaddr = tp->mmio_addr;
4841 struct pci_dev *pdev = tp->pci_dev;
4842
4843 rtl_csi_access_enable_2(tp);
7f3e3d3a
FR		 4844
4845 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4846
4847 /* Magic. */
4848 RTL_W8(DBG_REG, 0x20);
4849
f0298f81 4850 RTL_W8(MaxTxPacketSize, TxPacketMax);
7f3e3d3a 4851
faf1e785 4852 if (tp->dev->mtu <= ETH_DATA_LEN)
4853 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
7f3e3d3a
FR		 4854
4855 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4856}
4857
beb1fe18 4858static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
219a1e9d 4859{
beb1fe18 4860 void __iomem *ioaddr = tp->mmio_addr;
350f7596 4861 static const struct ephy_info e_info_8168c_1[] = {
b726e493
FR		 4862 { 0x02, 0x0800, 0x1000 },
4863 { 0x03, 0, 0x0002 },
4864 { 0x06, 0x0080, 0x0000 }
4865 };
4866
beb1fe18 4867 rtl_csi_access_enable_2(tp);
b726e493
FR		 4868
4869 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4870
fdf6fc06 4871 rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
b726e493 4872
beb1fe18 4873 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 4874}
4875
beb1fe18 4876static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
219a1e9d 4877{
350f7596 4878 static const struct ephy_info e_info_8168c_2[] = {
b726e493
FR		 4879 { 0x01, 0, 0x0001 },
4880 { 0x03, 0x0400, 0x0220 }
4881 };
4882
beb1fe18 4883 rtl_csi_access_enable_2(tp);
b726e493 4884
fdf6fc06 4885 rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
b726e493 4886
beb1fe18 4887 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 4888}
4889
beb1fe18 4890static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
197ff761 4891{
beb1fe18 4892 rtl_hw_start_8168c_2(tp);
197ff761
FR		 4893}
4894
beb1fe18 4895static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
6fb07058 4896{
beb1fe18 4897 rtl_csi_access_enable_2(tp);
6fb07058 4898
beb1fe18 4899 __rtl_hw_start_8168cp(tp);
6fb07058
FR		 4900}
4901
beb1fe18 4902static void rtl_hw_start_8168d(struct rtl8169_private *tp)
5b538df9 4903{
beb1fe18
HW		 4904 void __iomem *ioaddr = tp->mmio_addr;
4905 struct pci_dev *pdev = tp->pci_dev;
4906
4907 rtl_csi_access_enable_2(tp);
5b538df9
FR		 4908
4909 rtl_disable_clock_request(pdev);
4910
f0298f81 4911 RTL_W8(MaxTxPacketSize, TxPacketMax);
5b538df9 4912
faf1e785 4913 if (tp->dev->mtu <= ETH_DATA_LEN)
4914 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5b538df9
FR		 4915
4916 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4917}
4918
beb1fe18 4919static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
4804b3b3 4920{
beb1fe18
HW		 4921 void __iomem *ioaddr = tp->mmio_addr;
4922 struct pci_dev *pdev = tp->pci_dev;
4923
4924 rtl_csi_access_enable_1(tp);
4804b3b3 4925
faf1e785 4926 if (tp->dev->mtu <= ETH_DATA_LEN)
4927 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4804b3b3 4928
4929 RTL_W8(MaxTxPacketSize, TxPacketMax);
4930
4931 rtl_disable_clock_request(pdev);
4932}
4933
beb1fe18 4934static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
e6de30d6 4935{
beb1fe18
HW		 4936 void __iomem *ioaddr = tp->mmio_addr;
4937 struct pci_dev *pdev = tp->pci_dev;
e6de30d6 4938 static const struct ephy_info e_info_8168d_4[] = {
4939 { 0x0b, ~0, 0x48 },
4940 { 0x19, 0x20, 0x50 },
4941 { 0x0c, ~0, 0x20 }
4942 };
4943 int i;
4944
beb1fe18 4945 rtl_csi_access_enable_1(tp);
e6de30d6 4946
4947 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4948
4949 RTL_W8(MaxTxPacketSize, TxPacketMax);
4950
4951 for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
4952 const struct ephy_info *e = e_info_8168d_4 + i;
4953 u16 w;
4954
fdf6fc06
FR		 4955 w = rtl_ephy_read(tp, e->offset);
4956 rtl_ephy_write(tp, 0x03, (w & e->mask) | e->bits);
e6de30d6 4957 }
4958
4959 rtl_enable_clock_request(pdev);
4960}
4961
beb1fe18 4962static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
01dc7fec 4963{
beb1fe18
HW		 4964 void __iomem *ioaddr = tp->mmio_addr;
4965 struct pci_dev *pdev = tp->pci_dev;
70090424 4966 static const struct ephy_info e_info_8168e_1[] = {
01dc7fec 4967 { 0x00, 0x0200, 0x0100 },
4968 { 0x00, 0x0000, 0x0004 },
4969 { 0x06, 0x0002, 0x0001 },
4970 { 0x06, 0x0000, 0x0030 },
4971 { 0x07, 0x0000, 0x2000 },
4972 { 0x00, 0x0000, 0x0020 },
4973 { 0x03, 0x5800, 0x2000 },
4974 { 0x03, 0x0000, 0x0001 },
4975 { 0x01, 0x0800, 0x1000 },
4976 { 0x07, 0x0000, 0x4000 },
4977 { 0x1e, 0x0000, 0x2000 },
4978 { 0x19, 0xffff, 0xfe6c },
4979 { 0x0a, 0x0000, 0x0040 }
4980 };
4981
beb1fe18 4982 rtl_csi_access_enable_2(tp);
01dc7fec 4983
fdf6fc06 4984 rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
01dc7fec 4985
faf1e785 4986 if (tp->dev->mtu <= ETH_DATA_LEN)
4987 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
01dc7fec 4988
4989 RTL_W8(MaxTxPacketSize, TxPacketMax);
4990
4991 rtl_disable_clock_request(pdev);
4992
4993 /* Reset tx FIFO pointer */
cecb5fd7
FR		 4994 RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
4995 RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
01dc7fec 4996
cecb5fd7 4997 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
01dc7fec 4998}
4999
beb1fe18 5000static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
70090424 5001{
beb1fe18
HW		 5002 void __iomem *ioaddr = tp->mmio_addr;
5003 struct pci_dev *pdev = tp->pci_dev;
70090424
HW		 5004 static const struct ephy_info e_info_8168e_2[] = {
5005 { 0x09, 0x0000, 0x0080 },
5006 { 0x19, 0x0000, 0x0224 }
5007 };
5008
beb1fe18 5009 rtl_csi_access_enable_1(tp);
70090424 5010
fdf6fc06 5011 rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
70090424 5012
faf1e785 5013 if (tp->dev->mtu <= ETH_DATA_LEN)
5014 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
70090424 5015
fdf6fc06
FR		 5016 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5017 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5018 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5019 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5020 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5021 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
5022 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5023 rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
70090424 5024
3090bd9a 5025 RTL_W8(MaxTxPacketSize, EarlySize);
70090424 5026
4521e1a9
FR		 5027 rtl_disable_clock_request(pdev);
5028
70090424
HW		 5029 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5030 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5031
5032 /* Adjust EEE LED frequency */
5033 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5034
5035 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5036 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4521e1a9 5037 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
70090424
HW		 5038}
5039
5f886e08 5040static void rtl_hw_start_8168f(struct rtl8169_private *tp)
c2218925 5041{
beb1fe18
HW		 5042 void __iomem *ioaddr = tp->mmio_addr;
5043 struct pci_dev *pdev = tp->pci_dev;
c2218925 5044
5f886e08 5045 rtl_csi_access_enable_2(tp);
c2218925
HW		 5046
5047 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5048
fdf6fc06
FR		 5049 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5050 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5051 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5052 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5053 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5054 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5055 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5056 rtl_w1w0_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5057 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5058 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
c2218925
HW		 5059
5060 RTL_W8(MaxTxPacketSize, EarlySize);
5061
4521e1a9
FR		 5062 rtl_disable_clock_request(pdev);
5063
c2218925
HW		 5064 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5065 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
c2218925 5066 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4521e1a9
FR		 5067 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
5068 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
c2218925
HW		 5069}
5070
5f886e08
HW		 5071static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
5072{
5073 void __iomem *ioaddr = tp->mmio_addr;
5074 static const struct ephy_info e_info_8168f_1[] = {
5075 { 0x06, 0x00c0, 0x0020 },
5076 { 0x08, 0x0001, 0x0002 },
5077 { 0x09, 0x0000, 0x0080 },
5078 { 0x19, 0x0000, 0x0224 }
5079 };
5080
5081 rtl_hw_start_8168f(tp);
5082
fdf6fc06 5083 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5f886e08 5084
fdf6fc06 5085 rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5f886e08
HW		 5086
5087 /* Adjust EEE LED frequency */
5088 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5089}
5090
b3d7b2f2
HW		 5091static void rtl_hw_start_8411(struct rtl8169_private *tp)
5092{
b3d7b2f2
HW		 5093 static const struct ephy_info e_info_8168f_1[] = {
5094 { 0x06, 0x00c0, 0x0020 },
5095 { 0x0f, 0xffff, 0x5200 },
5096 { 0x1e, 0x0000, 0x4000 },
5097 { 0x19, 0x0000, 0x0224 }
5098 };
5099
5100 rtl_hw_start_8168f(tp);
5101
fdf6fc06 5102 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
b3d7b2f2 5103
fdf6fc06 5104 rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
b3d7b2f2
HW		 5105}
5106
c558386b
HW		 5107static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
5108{
5109 void __iomem *ioaddr = tp->mmio_addr;
5110 struct pci_dev *pdev = tp->pci_dev;
5111
5112 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
5113 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5114 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5115 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5116
5117 rtl_csi_access_enable_1(tp);
5118
5119 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5120
5121 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5122 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5123
5124 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4521e1a9 5125 RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
c558386b
HW		 5126 RTL_W8(MaxTxPacketSize, EarlySize);
5127
5128 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5129 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5130
5131 /* Adjust EEE LED frequency */
5132 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5133
5134 rtl_w1w0_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x02, ERIAR_EXGMAC);
5135}
5136
07ce4064
FR		 5137static void rtl_hw_start_8168(struct net_device *dev)
5138{
2dd99530
FR		 5139 struct rtl8169_private *tp = netdev_priv(dev);
5140 void __iomem *ioaddr = tp->mmio_addr;
5141
5142 RTL_W8(Cfg9346, Cfg9346_Unlock);
5143
f0298f81 5144 RTL_W8(MaxTxPacketSize, TxPacketMax);
2dd99530 5145
6f0333b8 5146 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
2dd99530 5147
0e485150 5148 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2dd99530
FR		 5149
5150 RTL_W16(CPlusCmd, tp->cp_cmd);
5151
0e485150 5152 RTL_W16(IntrMitigate, 0x5151);
2dd99530 5153
0e485150 5154 /* Work around for RxFIFO overflow. */
811fd301 5155 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
da78dbff
FR		 5156 tp->event_slow |= RxFIFOOver | PCSTimeout;
5157 tp->event_slow &= ~RxOverflow;
0e485150
FR		 5158 }
5159
5160 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2dd99530 5161
b8363901
FR		 5162 rtl_set_rx_mode(dev);
5163
5164 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
5165 (InterFrameGap << TxInterFrameGapShift));
2dd99530
FR		 5166
5167 RTL_R8(IntrMask);
5168
219a1e9d
FR		 5169 switch (tp->mac_version) {
5170 case RTL_GIGA_MAC_VER_11:
beb1fe18 5171 rtl_hw_start_8168bb(tp);
4804b3b3 5172 break;
219a1e9d
FR		 5173
5174 case RTL_GIGA_MAC_VER_12:
5175 case RTL_GIGA_MAC_VER_17:
beb1fe18 5176 rtl_hw_start_8168bef(tp);
4804b3b3 5177 break;
219a1e9d
FR		 5178
5179 case RTL_GIGA_MAC_VER_18:
beb1fe18 5180 rtl_hw_start_8168cp_1(tp);
4804b3b3 5181 break;
219a1e9d
FR		 5182
5183 case RTL_GIGA_MAC_VER_19:
beb1fe18 5184 rtl_hw_start_8168c_1(tp);
4804b3b3 5185 break;
219a1e9d
FR		 5186
5187 case RTL_GIGA_MAC_VER_20:
beb1fe18 5188 rtl_hw_start_8168c_2(tp);
4804b3b3 5189 break;
219a1e9d 5190
197ff761 5191 case RTL_GIGA_MAC_VER_21:
beb1fe18 5192 rtl_hw_start_8168c_3(tp);
4804b3b3 5193 break;
197ff761 5194
6fb07058 5195 case RTL_GIGA_MAC_VER_22:
beb1fe18 5196 rtl_hw_start_8168c_4(tp);
4804b3b3 5197 break;
6fb07058 5198
ef3386f0 5199 case RTL_GIGA_MAC_VER_23:
beb1fe18 5200 rtl_hw_start_8168cp_2(tp);
4804b3b3 5201 break;
ef3386f0 5202
7f3e3d3a 5203 case RTL_GIGA_MAC_VER_24:
beb1fe18 5204 rtl_hw_start_8168cp_3(tp);
4804b3b3 5205 break;
7f3e3d3a 5206
5b538df9 5207 case RTL_GIGA_MAC_VER_25:
daf9df6d 5208 case RTL_GIGA_MAC_VER_26:
5209 case RTL_GIGA_MAC_VER_27:
beb1fe18 5210 rtl_hw_start_8168d(tp);
4804b3b3 5211 break;
5b538df9 5212
e6de30d6 5213 case RTL_GIGA_MAC_VER_28:
beb1fe18 5214 rtl_hw_start_8168d_4(tp);
4804b3b3 5215 break;
cecb5fd7 5216
4804b3b3 5217 case RTL_GIGA_MAC_VER_31:
beb1fe18 5218 rtl_hw_start_8168dp(tp);
4804b3b3 5219 break;
5220
01dc7fec 5221 case RTL_GIGA_MAC_VER_32:
5222 case RTL_GIGA_MAC_VER_33:
beb1fe18 5223 rtl_hw_start_8168e_1(tp);
70090424
HW		 5224 break;
5225 case RTL_GIGA_MAC_VER_34:
beb1fe18 5226 rtl_hw_start_8168e_2(tp);
01dc7fec 5227 break;
e6de30d6 5228
c2218925
HW		 5229 case RTL_GIGA_MAC_VER_35:
5230 case RTL_GIGA_MAC_VER_36:
beb1fe18 5231 rtl_hw_start_8168f_1(tp);
c2218925
HW		 5232 break;
5233
b3d7b2f2
HW		 5234 case RTL_GIGA_MAC_VER_38:
5235 rtl_hw_start_8411(tp);
5236 break;
5237
c558386b
HW		 5238 case RTL_GIGA_MAC_VER_40:
5239 case RTL_GIGA_MAC_VER_41:
5240 rtl_hw_start_8168g_1(tp);
5241 break;
5242
219a1e9d
FR		 5243 default:
5244 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
5245 dev->name, tp->mac_version);
4804b3b3 5246 break;
219a1e9d 5247 }
2dd99530 5248
0e485150
FR		 5249 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5250
b8363901
FR		 5251 RTL_W8(Cfg9346, Cfg9346_Lock);
5252
2dd99530 5253 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
07ce4064 5254}
1da177e4 5255
2857ffb7
FR		 5256#define R810X_CPCMD_QUIRK_MASK (\
5257 EnableBist | \
5258 Mac_dbgo_oe | \
5259 Force_half_dup | \
5edcc537 5260 Force_rxflow_en | \
2857ffb7
FR		 5261 Force_txflow_en | \
5262 Cxpl_dbg_sel | \
5263 ASF | \
5264 PktCntrDisable | \
d24e9aaf 5265 Mac_dbgo_sel)
2857ffb7 5266
beb1fe18 5267static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
2857ffb7 5268{
beb1fe18
HW		 5269 void __iomem *ioaddr = tp->mmio_addr;
5270 struct pci_dev *pdev = tp->pci_dev;
350f7596 5271 static const struct ephy_info e_info_8102e_1[] = {
2857ffb7
FR		 5272 { 0x01, 0, 0x6e65 },
5273 { 0x02, 0, 0x091f },
5274 { 0x03, 0, 0xc2f9 },
5275 { 0x06, 0, 0xafb5 },
5276 { 0x07, 0, 0x0e00 },
5277 { 0x19, 0, 0xec80 },
5278 { 0x01, 0, 0x2e65 },
5279 { 0x01, 0, 0x6e65 }
5280 };
5281 u8 cfg1;
5282
beb1fe18 5283 rtl_csi_access_enable_2(tp);
2857ffb7
FR		 5284
5285 RTL_W8(DBG_REG, FIX_NAK_1);
5286
5287 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5288
5289 RTL_W8(Config1,
5290 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
5291 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5292
5293 cfg1 = RTL_R8(Config1);
5294 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
5295 RTL_W8(Config1, cfg1 & ~LEDS0);
5296
fdf6fc06 5297 rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
2857ffb7
FR		 5298}
5299
beb1fe18 5300static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
2857ffb7 5301{
beb1fe18
HW		 5302 void __iomem *ioaddr = tp->mmio_addr;
5303 struct pci_dev *pdev = tp->pci_dev;
5304
5305 rtl_csi_access_enable_2(tp);
2857ffb7
FR		 5306
5307 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5308
5309 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
5310 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2857ffb7
FR		 5311}
5312
beb1fe18 5313static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
2857ffb7 5314{
beb1fe18 5315 rtl_hw_start_8102e_2(tp);
2857ffb7 5316
fdf6fc06 5317 rtl_ephy_write(tp, 0x03, 0xc2f9);
2857ffb7
FR		 5318}
5319
beb1fe18 5320static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5a5e4443 5321{
beb1fe18 5322 void __iomem *ioaddr = tp->mmio_addr;
5a5e4443
HW		 5323 static const struct ephy_info e_info_8105e_1[] = {
5324 { 0x07, 0, 0x4000 },
5325 { 0x19, 0, 0x0200 },
5326 { 0x19, 0, 0x0020 },
5327 { 0x1e, 0, 0x2000 },
5328 { 0x03, 0, 0x0001 },
5329 { 0x19, 0, 0x0100 },
5330 { 0x19, 0, 0x0004 },
5331 { 0x0a, 0, 0x0020 }
5332 };
5333
cecb5fd7 5334 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5a5e4443
HW		 5335 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5336
cecb5fd7 5337 /* Disable Early Tally Counter */
5a5e4443
HW		 5338 RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
5339
5340 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
4f6b00e5 5341 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5a5e4443 5342
fdf6fc06 5343 rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
5a5e4443
HW		 5344}
5345
beb1fe18 5346static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5a5e4443 5347{
beb1fe18 5348 rtl_hw_start_8105e_1(tp);
fdf6fc06 5349 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5a5e4443
HW		 5350}
5351
7e18dca1
HW		 5352static void rtl_hw_start_8402(struct rtl8169_private *tp)
5353{
5354 void __iomem *ioaddr = tp->mmio_addr;
5355 static const struct ephy_info e_info_8402[] = {
5356 { 0x19, 0xffff, 0xff64 },
5357 { 0x1e, 0, 0x4000 }
5358 };
5359
5360 rtl_csi_access_enable_2(tp);
5361
5362 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5363 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5364
5365 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5366 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5367
fdf6fc06 5368 rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
7e18dca1
HW		 5369
5370 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
5371
fdf6fc06
FR		 5372 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
5373 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
5374 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5375 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5376 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5377 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5378 rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
7e18dca1
HW		 5379}
5380
5598bfe5
HW		 5381static void rtl_hw_start_8106(struct rtl8169_private *tp)
5382{
5383 void __iomem *ioaddr = tp->mmio_addr;
5384
5385 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5386 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5387
4521e1a9 5388 RTL_W32(MISC, (RTL_R32(MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
5598bfe5
HW		 5389 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
5390 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
5391}
5392
07ce4064
FR		 5393static void rtl_hw_start_8101(struct net_device *dev)
5394{
cdf1a608
FR		 5395 struct rtl8169_private *tp = netdev_priv(dev);
5396 void __iomem *ioaddr = tp->mmio_addr;
5397 struct pci_dev *pdev = tp->pci_dev;
5398
da78dbff
FR		 5399 if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
5400 tp->event_slow &= ~RxFIFOOver;
811fd301 5401
cecb5fd7 5402 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
7d7903b2 5403 tp->mac_version == RTL_GIGA_MAC_VER_16)
8200bc72
BH		 5404 pcie_capability_set_word(pdev, PCI_EXP_DEVCTL,
5405 PCI_EXP_DEVCTL_NOSNOOP_EN);
cdf1a608 5406
d24e9aaf
HW		 5407 RTL_W8(Cfg9346, Cfg9346_Unlock);
5408
2857ffb7
FR		 5409 switch (tp->mac_version) {
5410 case RTL_GIGA_MAC_VER_07:
beb1fe18 5411 rtl_hw_start_8102e_1(tp);
2857ffb7
FR		 5412 break;
5413
5414 case RTL_GIGA_MAC_VER_08:
beb1fe18 5415 rtl_hw_start_8102e_3(tp);
2857ffb7
FR		 5416 break;
5417
5418 case RTL_GIGA_MAC_VER_09:
beb1fe18 5419 rtl_hw_start_8102e_2(tp);
2857ffb7 5420 break;
5a5e4443
HW		 5421
5422 case RTL_GIGA_MAC_VER_29:
beb1fe18 5423 rtl_hw_start_8105e_1(tp);
5a5e4443
HW		 5424 break;
5425 case RTL_GIGA_MAC_VER_30:
beb1fe18 5426 rtl_hw_start_8105e_2(tp);
5a5e4443 5427 break;
7e18dca1
HW		 5428
5429 case RTL_GIGA_MAC_VER_37:
5430 rtl_hw_start_8402(tp);
5431 break;
5598bfe5
HW		 5432
5433 case RTL_GIGA_MAC_VER_39:
5434 rtl_hw_start_8106(tp);
5435 break;
cdf1a608
FR		 5436 }
5437
d24e9aaf 5438 RTL_W8(Cfg9346, Cfg9346_Lock);
cdf1a608 5439
f0298f81 5440 RTL_W8(MaxTxPacketSize, TxPacketMax);
cdf1a608 5441
6f0333b8 5442 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
cdf1a608 5443
d24e9aaf 5444 tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
cdf1a608
FR		 5445 RTL_W16(CPlusCmd, tp->cp_cmd);
5446
5447 RTL_W16(IntrMitigate, 0x0000);
5448
5449 rtl_set_rx_tx_desc_registers(tp, ioaddr);
5450
5451 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5452 rtl_set_rx_tx_config_registers(tp);
5453
cdf1a608
FR		 5454 RTL_R8(IntrMask);
5455
cdf1a608
FR		 5456 rtl_set_rx_mode(dev);
5457
5458 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
1da177e4
LT		 5459}
5460
5461static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5462{
d58d46b5
FR		 5463 struct rtl8169_private *tp = netdev_priv(dev);
5464
5465 if (new_mtu < ETH_ZLEN ||
5466 new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max)
1da177e4
LT		 5467 return -EINVAL;
5468
d58d46b5
FR		 5469 if (new_mtu > ETH_DATA_LEN)
5470 rtl_hw_jumbo_enable(tp);
5471 else
5472 rtl_hw_jumbo_disable(tp);
5473
1da177e4 5474 dev->mtu = new_mtu;
350fb32a
MM		 5475 netdev_update_features(dev);
5476
323bb685 5477 return 0;
1da177e4
LT		 5478}
5479
5480static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5481{
95e0918d 5482 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
1da177e4
LT		 5483 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5484}
5485
6f0333b8
ED		 5486static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
5487 void **data_buff, struct RxDesc *desc)
1da177e4 5488{
48addcc9 5489 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
231aee63 5490 DMA_FROM_DEVICE);
48addcc9 5491
6f0333b8
ED		 5492 kfree(*data_buff);
5493 *data_buff = NULL;
1da177e4
LT		 5494 rtl8169_make_unusable_by_asic(desc);
5495}
5496
5497static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
5498{
5499 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5500
5501 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
5502}
5503
5504static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
5505 u32 rx_buf_sz)
5506{
5507 desc->addr = cpu_to_le64(mapping);
5508 wmb();
5509 rtl8169_mark_to_asic(desc, rx_buf_sz);
5510}
5511
6f0333b8
ED		 5512static inline void *rtl8169_align(void *data)
5513{
5514 return (void *)ALIGN((long)data, 16);
5515}
5516
0ecbe1ca
SG		 5517static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5518 struct RxDesc *desc)
1da177e4 5519{
6f0333b8 5520 void *data;
1da177e4 5521 dma_addr_t mapping;
48addcc9 5522 struct device *d = &tp->pci_dev->dev;
0ecbe1ca 5523 struct net_device *dev = tp->dev;
6f0333b8 5524 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
1da177e4 5525
6f0333b8
ED		 5526 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
5527 if (!data)
5528 return NULL;
e9f63f30 5529
6f0333b8
ED		 5530 if (rtl8169_align(data) != data) {
5531 kfree(data);
5532 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
5533 if (!data)
5534 return NULL;
5535 }
3eafe507 5536
48addcc9 5537 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
231aee63 5538 DMA_FROM_DEVICE);
d827d86b
SG		 5539 if (unlikely(dma_mapping_error(d, mapping))) {
5540 if (net_ratelimit())
5541 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
3eafe507 5542 goto err_out;
d827d86b 5543 }
1da177e4
LT		 5544
5545 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
6f0333b8 5546 return data;
3eafe507
SG		 5547
5548err_out:
5549 kfree(data);
5550 return NULL;
1da177e4
LT		 5551}
5552
5553static void rtl8169_rx_clear(struct rtl8169_private *tp)
5554{
07d3f51f 5555 unsigned int i;
1da177e4
LT		 5556
5557 for (i = 0; i < NUM_RX_DESC; i++) {
6f0333b8
ED		 5558 if (tp->Rx_databuff[i]) {
5559 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
1da177e4
LT		 5560 tp->RxDescArray + i);
5561 }
5562 }
5563}
5564
0ecbe1ca 5565static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
1da177e4 5566{
0ecbe1ca
SG		 5567 desc->opts1 |= cpu_to_le32(RingEnd);
5568}
5b0384f4 5569
0ecbe1ca
SG		 5570static int rtl8169_rx_fill(struct rtl8169_private *tp)
5571{
5572 unsigned int i;
1da177e4 5573
0ecbe1ca
SG		 5574 for (i = 0; i < NUM_RX_DESC; i++) {
5575 void *data;
4ae47c2d 5576
6f0333b8 5577 if (tp->Rx_databuff[i])
1da177e4 5578 continue;
bcf0bf90 5579
0ecbe1ca 5580 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
6f0333b8
ED		 5581 if (!data) {
5582 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
0ecbe1ca 5583 goto err_out;
6f0333b8
ED		 5584 }
5585 tp->Rx_databuff[i] = data;
1da177e4 5586 }
1da177e4 5587
0ecbe1ca
SG		 5588 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5589 return 0;
5590
5591err_out:
5592 rtl8169_rx_clear(tp);
5593 return -ENOMEM;
1da177e4
LT		 5594}
5595
1da177e4
LT		 5596static int rtl8169_init_ring(struct net_device *dev)
5597{
5598 struct rtl8169_private *tp = netdev_priv(dev);
5599
5600 rtl8169_init_ring_indexes(tp);
5601
5602 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
6f0333b8 5603 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
1da177e4 5604
0ecbe1ca 5605 return rtl8169_rx_fill(tp);
1da177e4
LT		 5606}
5607
48addcc9 5608static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
1da177e4
LT		 5609 struct TxDesc *desc)
5610{
5611 unsigned int len = tx_skb->len;
5612
48addcc9
SG		 5613 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5614
1da177e4
LT		 5615 desc->opts1 = 0x00;
5616 desc->opts2 = 0x00;
5617 desc->addr = 0x00;
5618 tx_skb->len = 0;
5619}
5620
3eafe507
SG		 5621static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5622 unsigned int n)
1da177e4
LT		 5623{
5624 unsigned int i;
5625
3eafe507
SG		 5626 for (i = 0; i < n; i++) {
5627 unsigned int entry = (start + i) % NUM_TX_DESC;
1da177e4
LT		 5628 struct ring_info *tx_skb = tp->tx_skb + entry;
5629 unsigned int len = tx_skb->len;
5630
5631 if (len) {
5632 struct sk_buff *skb = tx_skb->skb;
5633
48addcc9 5634 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
1da177e4
LT		 5635 tp->TxDescArray + entry);
5636 if (skb) {
cac4b22f 5637 tp->dev->stats.tx_dropped++;
1da177e4
LT		 5638 dev_kfree_skb(skb);
5639 tx_skb->skb = NULL;
5640 }
1da177e4
LT		 5641 }
5642 }
3eafe507
SG		 5643}
5644
5645static void rtl8169_tx_clear(struct rtl8169_private *tp)
5646{
5647 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
1da177e4
LT		 5648 tp->cur_tx = tp->dirty_tx = 0;
5649}
5650
4422bcd4 5651static void rtl_reset_work(struct rtl8169_private *tp)
1da177e4 5652{
c4028958 5653 struct net_device *dev = tp->dev;
56de414c 5654 int i;
1da177e4 5655
da78dbff
FR		 5656 napi_disable(&tp->napi);
5657 netif_stop_queue(dev);
5658 synchronize_sched();
1da177e4 5659
c7c2c39b 5660 rtl8169_hw_reset(tp);
5661
56de414c
FR		 5662 for (i = 0; i < NUM_RX_DESC; i++)
5663 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
5664
1da177e4 5665 rtl8169_tx_clear(tp);
c7c2c39b 5666 rtl8169_init_ring_indexes(tp);
1da177e4 5667
da78dbff 5668 napi_enable(&tp->napi);
56de414c
FR		 5669 rtl_hw_start(dev);
5670 netif_wake_queue(dev);
5671 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1da177e4
LT		 5672}
5673
5674static void rtl8169_tx_timeout(struct net_device *dev)
5675{
da78dbff
FR		 5676 struct rtl8169_private *tp = netdev_priv(dev);
5677
5678 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
1da177e4
LT		 5679}
5680
5681static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2b7b4318 5682 u32 *opts)
1da177e4
LT		 5683{
5684 struct skb_shared_info *info = skb_shinfo(skb);
5685 unsigned int cur_frag, entry;
a6343afb 5686 struct TxDesc * uninitialized_var(txd);
48addcc9 5687 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 5688
5689 entry = tp->cur_tx;
5690 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
9e903e08 5691 const skb_frag_t *frag = info->frags + cur_frag;
1da177e4
LT		 5692 dma_addr_t mapping;
5693 u32 status, len;
5694 void *addr;
5695
5696 entry = (entry + 1) % NUM_TX_DESC;
5697
5698 txd = tp->TxDescArray + entry;
9e903e08 5699 len = skb_frag_size(frag);
929f6189 5700 addr = skb_frag_address(frag);
48addcc9 5701 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
d827d86b
SG		 5702 if (unlikely(dma_mapping_error(d, mapping))) {
5703 if (net_ratelimit())
5704 netif_err(tp, drv, tp->dev,
5705 "Failed to map TX fragments DMA!\n");
3eafe507 5706 goto err_out;
d827d86b 5707 }
1da177e4 5708
cecb5fd7 5709 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318
FR		 5710 status = opts[0] | len |
5711 (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 5712
5713 txd->opts1 = cpu_to_le32(status);
2b7b4318 5714 txd->opts2 = cpu_to_le32(opts[1]);
1da177e4
LT		 5715 txd->addr = cpu_to_le64(mapping);
5716
5717 tp->tx_skb[entry].len = len;
5718 }
5719
5720 if (cur_frag) {
5721 tp->tx_skb[entry].skb = skb;
5722 txd->opts1 |= cpu_to_le32(LastFrag);
5723 }
5724
5725 return cur_frag;
3eafe507
SG		 5726
5727err_out:
5728 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5729 return -EIO;
1da177e4
LT		 5730}
5731
2b7b4318
FR		 5732static inline void rtl8169_tso_csum(struct rtl8169_private *tp,
5733 struct sk_buff *skb, u32 *opts)
1da177e4 5734{
2b7b4318 5735 const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
350fb32a 5736 u32 mss = skb_shinfo(skb)->gso_size;
2b7b4318 5737 int offset = info->opts_offset;
350fb32a 5738
2b7b4318
FR		 5739 if (mss) {
5740 opts[0] |= TD_LSO;
5741 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
5742 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
eddc9ec5 5743 const struct iphdr *ip = ip_hdr(skb);
1da177e4
LT		 5744
5745 if (ip->protocol == IPPROTO_TCP)
2b7b4318 5746 opts[offset] |= info->checksum.tcp;
1da177e4 5747 else if (ip->protocol == IPPROTO_UDP)
2b7b4318
FR		 5748 opts[offset] |= info->checksum.udp;
5749 else
5750 WARN_ON_ONCE(1);
1da177e4 5751 }
1da177e4
LT		 5752}
5753
61357325
SH		 5754static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5755 struct net_device *dev)
1da177e4
LT		 5756{
5757 struct rtl8169_private *tp = netdev_priv(dev);
3eafe507 5758 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
1da177e4
LT		 5759 struct TxDesc *txd = tp->TxDescArray + entry;
5760 void __iomem *ioaddr = tp->mmio_addr;
48addcc9 5761 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 5762 dma_addr_t mapping;
5763 u32 status, len;
2b7b4318 5764 u32 opts[2];
3eafe507 5765 int frags;
5b0384f4 5766
477206a0 5767 if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
bf82c189 5768 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
3eafe507 5769 goto err_stop_0;
1da177e4
LT		 5770 }
5771
5772 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
3eafe507
SG		 5773 goto err_stop_0;
5774
5775 len = skb_headlen(skb);
48addcc9 5776 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
d827d86b
SG		 5777 if (unlikely(dma_mapping_error(d, mapping))) {
5778 if (net_ratelimit())
5779 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
3eafe507 5780 goto err_dma_0;
d827d86b 5781 }
3eafe507
SG		 5782
5783 tp->tx_skb[entry].len = len;
5784 txd->addr = cpu_to_le64(mapping);
1da177e4 5785
810f4893 5786 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
2b7b4318 5787 opts[0] = DescOwn;
1da177e4 5788
2b7b4318
FR		 5789 rtl8169_tso_csum(tp, skb, opts);
5790
5791 frags = rtl8169_xmit_frags(tp, skb, opts);
3eafe507
SG		 5792 if (frags < 0)
5793 goto err_dma_1;
5794 else if (frags)
2b7b4318 5795 opts[0] |= FirstFrag;
3eafe507 5796 else {
2b7b4318 5797 opts[0] |= FirstFrag | LastFrag;
1da177e4
LT		 5798 tp->tx_skb[entry].skb = skb;
5799 }
5800
2b7b4318
FR		 5801 txd->opts2 = cpu_to_le32(opts[1]);
5802
5047fb5d
RC		 5803 skb_tx_timestamp(skb);
5804
1da177e4
LT		 5805 wmb();
5806
cecb5fd7 5807 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318 5808 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 5809 txd->opts1 = cpu_to_le32(status);
5810
1da177e4
LT		 5811 tp->cur_tx += frags + 1;
5812
4c020a96 5813 wmb();
1da177e4 5814
cecb5fd7 5815 RTL_W8(TxPoll, NPQ);
1da177e4 5816
da78dbff
FR		 5817 mmiowb();
5818
477206a0 5819 if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
ae1f23fb
FR		 5820 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
5821 * not miss a ring update when it notices a stopped queue.
5822 */
5823 smp_wmb();
1da177e4 5824 netif_stop_queue(dev);
ae1f23fb
FR		 5825 /* Sync with rtl_tx:
5826 * - publish queue status and cur_tx ring index (write barrier)
5827 * - refresh dirty_tx ring index (read barrier).
5828 * May the current thread have a pessimistic view of the ring
5829 * status and forget to wake up queue, a racing rtl_tx thread
5830 * can't.
5831 */
1e874e04 5832 smp_mb();
477206a0 5833 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
1da177e4
LT		 5834 netif_wake_queue(dev);
5835 }
5836
61357325 5837 return NETDEV_TX_OK;
1da177e4 5838
3eafe507 5839err_dma_1:
48addcc9 5840 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
3eafe507
SG		 5841err_dma_0:
5842 dev_kfree_skb(skb);
5843 dev->stats.tx_dropped++;
5844 return NETDEV_TX_OK;
5845
5846err_stop_0:
1da177e4 5847 netif_stop_queue(dev);
cebf8cc7 5848 dev->stats.tx_dropped++;
61357325 5849 return NETDEV_TX_BUSY;
1da177e4
LT		 5850}
5851
5852static void rtl8169_pcierr_interrupt(struct net_device *dev)
5853{
5854 struct rtl8169_private *tp = netdev_priv(dev);
5855 struct pci_dev *pdev = tp->pci_dev;
1da177e4
LT		 5856 u16 pci_status, pci_cmd;
5857
5858 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
5859 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
5860
bf82c189
JP		 5861 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
5862 pci_cmd, pci_status);
1da177e4
LT		 5863
5864 /*
5865 * The recovery sequence below admits a very elaborated explanation:
5866 * - it seems to work;
d03902b8
FR		 5867 * - I did not see what else could be done;
5868 * - it makes iop3xx happy.
1da177e4
LT		 5869 *
5870 * Feel free to adjust to your needs.
5871 */
a27993f3 5872 if (pdev->broken_parity_status)
d03902b8
FR		 5873 pci_cmd &= ~PCI_COMMAND_PARITY;
5874 else
5875 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
5876
5877 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 5878
5879 pci_write_config_word(pdev, PCI_STATUS,
5880 pci_status & (PCI_STATUS_DETECTED_PARITY |
5881 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
5882 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
5883
5884 /* The infamous DAC f*ckup only happens at boot time */
9fba0812 5885 if ((tp->cp_cmd & PCIDAC) && !tp->cur_rx) {
e6de30d6 5886 void __iomem *ioaddr = tp->mmio_addr;
5887
bf82c189 5888 netif_info(tp, intr, dev, "disabling PCI DAC\n");
1da177e4
LT		 5889 tp->cp_cmd &= ~PCIDAC;
5890 RTL_W16(CPlusCmd, tp->cp_cmd);
5891 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 5892 }
5893
e6de30d6 5894 rtl8169_hw_reset(tp);
d03902b8 5895
98ddf986 5896 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
1da177e4
LT		 5897}
5898
da78dbff 5899static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
1da177e4
LT		 5900{
5901 unsigned int dirty_tx, tx_left;
5902
1da177e4
LT		 5903 dirty_tx = tp->dirty_tx;
5904 smp_rmb();
5905 tx_left = tp->cur_tx - dirty_tx;
5906
5907 while (tx_left > 0) {
5908 unsigned int entry = dirty_tx % NUM_TX_DESC;
5909 struct ring_info *tx_skb = tp->tx_skb + entry;
1da177e4
LT		 5910 u32 status;
5911
5912 rmb();
5913 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
5914 if (status & DescOwn)
5915 break;
5916
48addcc9
SG		 5917 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5918 tp->TxDescArray + entry);
1da177e4 5919 if (status & LastFrag) {
17bcb684
FR		 5920 u64_stats_update_begin(&tp->tx_stats.syncp);
5921 tp->tx_stats.packets++;
5922 tp->tx_stats.bytes += tx_skb->skb->len;
5923 u64_stats_update_end(&tp->tx_stats.syncp);
5924 dev_kfree_skb(tx_skb->skb);
1da177e4
LT		 5925 tx_skb->skb = NULL;
5926 }
5927 dirty_tx++;
5928 tx_left--;
5929 }
5930
5931 if (tp->dirty_tx != dirty_tx) {
5932 tp->dirty_tx = dirty_tx;
ae1f23fb
FR		 5933 /* Sync with rtl8169_start_xmit:
5934 * - publish dirty_tx ring index (write barrier)
5935 * - refresh cur_tx ring index and queue status (read barrier)
5936 * May the current thread miss the stopped queue condition,
5937 * a racing xmit thread can only have a right view of the
5938 * ring status.
5939 */
1e874e04 5940 smp_mb();
1da177e4 5941 if (netif_queue_stopped(dev) &&
477206a0 5942 TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
1da177e4
LT		 5943 netif_wake_queue(dev);
5944 }
d78ae2dc
FR		 5945 /*
5946 * 8168 hack: TxPoll requests are lost when the Tx packets are
5947 * too close. Let's kick an extra TxPoll request when a burst
5948 * of start_xmit activity is detected (if it is not detected,
5949 * it is slow enough). -- FR
5950 */
da78dbff
FR		 5951 if (tp->cur_tx != dirty_tx) {
5952 void __iomem *ioaddr = tp->mmio_addr;
5953
d78ae2dc 5954 RTL_W8(TxPoll, NPQ);
da78dbff 5955 }
1da177e4
LT		 5956 }
5957}
5958
126fa4b9
FR		 5959static inline int rtl8169_fragmented_frame(u32 status)
5960{
5961 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
5962}
5963
adea1ac7 5964static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
1da177e4 5965{
1da177e4
LT		 5966 u32 status = opts1 & RxProtoMask;
5967
5968 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
d5d3ebe3 5969 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
1da177e4
LT		 5970 skb->ip_summed = CHECKSUM_UNNECESSARY;
5971 else
bc8acf2c 5972 skb_checksum_none_assert(skb);
1da177e4
LT		 5973}
5974
6f0333b8
ED		 5975static struct sk_buff *rtl8169_try_rx_copy(void *data,
5976 struct rtl8169_private *tp,
5977 int pkt_size,
5978 dma_addr_t addr)
1da177e4 5979{
b449655f 5980 struct sk_buff *skb;
48addcc9 5981 struct device *d = &tp->pci_dev->dev;
b449655f 5982
6f0333b8 5983 data = rtl8169_align(data);
48addcc9 5984 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6f0333b8
ED		 5985 prefetch(data);
5986 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
5987 if (skb)
5988 memcpy(skb->data, data, pkt_size);
48addcc9
SG		 5989 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
5990
6f0333b8 5991 return skb;
1da177e4
LT		 5992}
5993
da78dbff 5994static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
1da177e4
LT		 5995{
5996 unsigned int cur_rx, rx_left;
6f0333b8 5997 unsigned int count;
1da177e4 5998
1da177e4 5999 cur_rx = tp->cur_rx;
1da177e4 6000
9fba0812 6001 for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
1da177e4 6002 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 6003 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 6004 u32 status;
6005
6006 rmb();
e03f33af 6007 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
1da177e4
LT		 6008
6009 if (status & DescOwn)
6010 break;
4dcb7d33 6011 if (unlikely(status & RxRES)) {
bf82c189
JP		 6012 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
6013 status);
cebf8cc7 6014 dev->stats.rx_errors++;
1da177e4 6015 if (status & (RxRWT | RxRUNT))
cebf8cc7 6016 dev->stats.rx_length_errors++;
1da177e4 6017 if (status & RxCRC)
cebf8cc7 6018 dev->stats.rx_crc_errors++;
9dccf611 6019 if (status & RxFOVF) {
da78dbff 6020 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
cebf8cc7 6021 dev->stats.rx_fifo_errors++;
9dccf611 6022 }
6bbe021d
BG		 6023 if ((status & (RxRUNT | RxCRC)) &&
6024 !(status & (RxRWT | RxFOVF)) &&
6025 (dev->features & NETIF_F_RXALL))
6026 goto process_pkt;
1da177e4 6027 } else {
6f0333b8 6028 struct sk_buff *skb;
6bbe021d
BG		 6029 dma_addr_t addr;
6030 int pkt_size;
6031
6032process_pkt:
6033 addr = le64_to_cpu(desc->addr);
79d0c1d2
BG		 6034 if (likely(!(dev->features & NETIF_F_RXFCS)))
6035 pkt_size = (status & 0x00003fff) - 4;
6036 else
6037 pkt_size = status & 0x00003fff;
1da177e4 6038
126fa4b9
FR		 6039 /*
6040 * The driver does not support incoming fragmented
6041 * frames. They are seen as a symptom of over-mtu
6042 * sized frames.
6043 */
6044 if (unlikely(rtl8169_fragmented_frame(status))) {
cebf8cc7
FR		 6045 dev->stats.rx_dropped++;
6046 dev->stats.rx_length_errors++;
ce11ff5e 6047 goto release_descriptor;
126fa4b9
FR		 6048 }
6049
6f0333b8
ED		 6050 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
6051 tp, pkt_size, addr);
6f0333b8
ED		 6052 if (!skb) {
6053 dev->stats.rx_dropped++;
ce11ff5e 6054 goto release_descriptor;
1da177e4
LT		 6055 }
6056
adea1ac7 6057 rtl8169_rx_csum(skb, status);
1da177e4
LT		 6058 skb_put(skb, pkt_size);
6059 skb->protocol = eth_type_trans(skb, dev);
6060
7a8fc77b
FR		 6061 rtl8169_rx_vlan_tag(desc, skb);
6062
56de414c 6063 napi_gro_receive(&tp->napi, skb);
1da177e4 6064
8027aa24
JW		 6065 u64_stats_update_begin(&tp->rx_stats.syncp);
6066 tp->rx_stats.packets++;
6067 tp->rx_stats.bytes += pkt_size;
6068 u64_stats_update_end(&tp->rx_stats.syncp);
1da177e4 6069 }
ce11ff5e 6070release_descriptor:
6071 desc->opts2 = 0;
6072 wmb();
6073 rtl8169_mark_to_asic(desc, rx_buf_sz);
1da177e4
LT		 6074 }
6075
6076 count = cur_rx - tp->cur_rx;
6077 tp->cur_rx = cur_rx;
6078
1da177e4
LT		 6079 return count;
6080}
6081
07d3f51f 6082static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 6083{
07d3f51f 6084 struct net_device *dev = dev_instance;
1da177e4 6085 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 6086 int handled = 0;
9085cdfa 6087 u16 status;
1da177e4 6088
9085cdfa 6089 status = rtl_get_events(tp);
da78dbff
FR		 6090 if (status && status != 0xffff) {
6091 status &= RTL_EVENT_NAPI | tp->event_slow;
6092 if (status) {
6093 handled = 1;
1da177e4 6094
da78dbff
FR		 6095 rtl_irq_disable(tp);
6096 napi_schedule(&tp->napi);
f11a377b 6097 }
da78dbff
FR		 6098 }
6099 return IRQ_RETVAL(handled);
6100}
1da177e4 6101
da78dbff
FR		 6102/*
6103 * Workqueue context.
6104 */
6105static void rtl_slow_event_work(struct rtl8169_private *tp)
6106{
6107 struct net_device *dev = tp->dev;
6108 u16 status;
6109
6110 status = rtl_get_events(tp) & tp->event_slow;
6111 rtl_ack_events(tp, status);
1da177e4 6112
da78dbff
FR		 6113 if (unlikely(status & RxFIFOOver)) {
6114 switch (tp->mac_version) {
6115 /* Work around for rx fifo overflow */
6116 case RTL_GIGA_MAC_VER_11:
6117 netif_stop_queue(dev);
934714d0
FR		 6118 /* XXX - Hack alert. See rtl_task(). */
6119 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
da78dbff 6120 default:
f11a377b
DD		 6121 break;
6122 }
da78dbff 6123 }
1da177e4 6124
da78dbff
FR		 6125 if (unlikely(status & SYSErr))
6126 rtl8169_pcierr_interrupt(dev);
0e485150 6127
da78dbff
FR		 6128 if (status & LinkChg)
6129 __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true);
1da177e4 6130
7dbb4918 6131 rtl_irq_enable_all(tp);
1da177e4
LT		 6132}
6133
4422bcd4
FR		 6134static void rtl_task(struct work_struct *work)
6135{
da78dbff
FR		 6136 static const struct {
6137 int bitnr;
6138 void (*action)(struct rtl8169_private *);
6139 } rtl_work[] = {
934714d0 6140 /* XXX - keep rtl_slow_event_work() as first element. */
da78dbff
FR		 6141 { RTL_FLAG_TASK_SLOW_PENDING, rtl_slow_event_work },
6142 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work },
6143 { RTL_FLAG_TASK_PHY_PENDING, rtl_phy_work }
6144 };
4422bcd4
FR		 6145 struct rtl8169_private *tp =
6146 container_of(work, struct rtl8169_private, wk.work);
da78dbff
FR		 6147 struct net_device *dev = tp->dev;
6148 int i;
6149
6150 rtl_lock_work(tp);
6151
6c4a70c5
FR		 6152 if (!netif_running(dev) ||
6153 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
da78dbff
FR		 6154 goto out_unlock;
6155
6156 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
6157 bool pending;
6158
da78dbff 6159 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
da78dbff
FR		 6160 if (pending)
6161 rtl_work[i].action(tp);
6162 }
4422bcd4 6163
da78dbff
FR		 6164out_unlock:
6165 rtl_unlock_work(tp);
4422bcd4
FR		 6166}
6167
bea3348e 6168static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 6169{
bea3348e
SH		 6170 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
6171 struct net_device *dev = tp->dev;
da78dbff
FR		 6172 u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
6173 int work_done= 0;
6174 u16 status;
6175
6176 status = rtl_get_events(tp);
6177 rtl_ack_events(tp, status & ~tp->event_slow);
6178
6179 if (status & RTL_EVENT_NAPI_RX)
6180 work_done = rtl_rx(dev, tp, (u32) budget);
6181
6182 if (status & RTL_EVENT_NAPI_TX)
6183 rtl_tx(dev, tp);
1da177e4 6184
da78dbff
FR		 6185 if (status & tp->event_slow) {
6186 enable_mask &= ~tp->event_slow;
6187
6188 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
6189 }
1da177e4 6190
bea3348e 6191 if (work_done < budget) {
288379f0 6192 napi_complete(napi);
f11a377b 6193
da78dbff
FR		 6194 rtl_irq_enable(tp, enable_mask);
6195 mmiowb();
1da177e4
LT		 6196 }
6197
bea3348e 6198 return work_done;
1da177e4 6199}
1da177e4 6200
523a6094
FR		 6201static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
6202{
6203 struct rtl8169_private *tp = netdev_priv(dev);
6204
6205 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
6206 return;
6207
6208 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
6209 RTL_W32(RxMissed, 0);
6210}
6211
1da177e4
LT		 6212static void rtl8169_down(struct net_device *dev)
6213{
6214 struct rtl8169_private *tp = netdev_priv(dev);
6215 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 6216
4876cc1e 6217 del_timer_sync(&tp->timer);
1da177e4 6218
93dd79e8 6219 napi_disable(&tp->napi);
da78dbff 6220 netif_stop_queue(dev);
1da177e4 6221
92fc43b4 6222 rtl8169_hw_reset(tp);
323bb685
SG		 6223 /*
6224 * At this point device interrupts can not be enabled in any function,
209e5ac8
FR		 6225 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
6226 * and napi is disabled (rtl8169_poll).
323bb685 6227 */
523a6094 6228 rtl8169_rx_missed(dev, ioaddr);
1da177e4 6229
1da177e4 6230 /* Give a racing hard_start_xmit a few cycles to complete. */
da78dbff 6231 synchronize_sched();
1da177e4 6232
1da177e4
LT		 6233 rtl8169_tx_clear(tp);
6234
6235 rtl8169_rx_clear(tp);
065c27c1 6236
6237 rtl_pll_power_down(tp);
1da177e4
LT		 6238}
6239
6240static int rtl8169_close(struct net_device *dev)
6241{
6242 struct rtl8169_private *tp = netdev_priv(dev);
6243 struct pci_dev *pdev = tp->pci_dev;
6244
e1759441
RW		 6245 pm_runtime_get_sync(&pdev->dev);
6246
cecb5fd7 6247 /* Update counters before going down */
355423d0
IV		 6248 rtl8169_update_counters(dev);
6249
da78dbff 6250 rtl_lock_work(tp);
6c4a70c5 6251 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
da78dbff 6252
1da177e4 6253 rtl8169_down(dev);
da78dbff 6254 rtl_unlock_work(tp);
1da177e4 6255
92a7c4e7 6256 free_irq(pdev->irq, dev);
1da177e4 6257
82553bb6
SG		 6258 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6259 tp->RxPhyAddr);
6260 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6261 tp->TxPhyAddr);
1da177e4
LT		 6262 tp->TxDescArray = NULL;
6263 tp->RxDescArray = NULL;
6264
e1759441
RW		 6265 pm_runtime_put_sync(&pdev->dev);
6266
1da177e4
LT		 6267 return 0;
6268}
6269
dc1c00ce
FR		 6270#ifdef CONFIG_NET_POLL_CONTROLLER
6271static void rtl8169_netpoll(struct net_device *dev)
6272{
6273 struct rtl8169_private *tp = netdev_priv(dev);
6274
6275 rtl8169_interrupt(tp->pci_dev->irq, dev);
6276}
6277#endif
6278
df43ac78
FR		 6279static int rtl_open(struct net_device *dev)
6280{
6281 struct rtl8169_private *tp = netdev_priv(dev);
6282 void __iomem *ioaddr = tp->mmio_addr;
6283 struct pci_dev *pdev = tp->pci_dev;
6284 int retval = -ENOMEM;
6285
6286 pm_runtime_get_sync(&pdev->dev);
6287
6288 /*
e75d6606 6289 * Rx and Tx descriptors needs 256 bytes alignment.
df43ac78
FR		 6290 * dma_alloc_coherent provides more.
6291 */
6292 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
6293 &tp->TxPhyAddr, GFP_KERNEL);
6294 if (!tp->TxDescArray)
6295 goto err_pm_runtime_put;
6296
6297 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
6298 &tp->RxPhyAddr, GFP_KERNEL);
6299 if (!tp->RxDescArray)
6300 goto err_free_tx_0;
6301
6302 retval = rtl8169_init_ring(dev);
6303 if (retval < 0)
6304 goto err_free_rx_1;
6305
6306 INIT_WORK(&tp->wk.work, rtl_task);
6307
6308 smp_mb();
6309
6310 rtl_request_firmware(tp);
6311
92a7c4e7 6312 retval = request_irq(pdev->irq, rtl8169_interrupt,
df43ac78
FR		 6313 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
6314 dev->name, dev);
6315 if (retval < 0)
6316 goto err_release_fw_2;
6317
6318 rtl_lock_work(tp);
6319
6320 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6321
6322 napi_enable(&tp->napi);
6323
6324 rtl8169_init_phy(dev, tp);
6325
6326 __rtl8169_set_features(dev, dev->features);
6327
6328 rtl_pll_power_up(tp);
6329
6330 rtl_hw_start(dev);
6331
6332 netif_start_queue(dev);
6333
6334 rtl_unlock_work(tp);
6335
6336 tp->saved_wolopts = 0;
6337 pm_runtime_put_noidle(&pdev->dev);
6338
6339 rtl8169_check_link_status(dev, tp, ioaddr);
6340out:
6341 return retval;
6342
6343err_release_fw_2:
6344 rtl_release_firmware(tp);
6345 rtl8169_rx_clear(tp);
6346err_free_rx_1:
6347 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6348 tp->RxPhyAddr);
6349 tp->RxDescArray = NULL;
6350err_free_tx_0:
6351 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6352 tp->TxPhyAddr);
6353 tp->TxDescArray = NULL;
6354err_pm_runtime_put:
6355 pm_runtime_put_noidle(&pdev->dev);
6356 goto out;
6357}
6358
8027aa24
JW		 6359static struct rtnl_link_stats64 *
6360rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
1da177e4
LT		 6361{
6362 struct rtl8169_private *tp = netdev_priv(dev);
6363 void __iomem *ioaddr = tp->mmio_addr;
8027aa24 6364 unsigned int start;
1da177e4 6365
da78dbff 6366 if (netif_running(dev))
523a6094 6367 rtl8169_rx_missed(dev, ioaddr);
5b0384f4 6368
8027aa24
JW		 6369 do {
6370 start = u64_stats_fetch_begin_bh(&tp->rx_stats.syncp);
6371 stats->rx_packets = tp->rx_stats.packets;
6372 stats->rx_bytes = tp->rx_stats.bytes;
6373 } while (u64_stats_fetch_retry_bh(&tp->rx_stats.syncp, start));
6374
6375
6376 do {
6377 start = u64_stats_fetch_begin_bh(&tp->tx_stats.syncp);
6378 stats->tx_packets = tp->tx_stats.packets;
6379 stats->tx_bytes = tp->tx_stats.bytes;
6380 } while (u64_stats_fetch_retry_bh(&tp->tx_stats.syncp, start));
6381
6382 stats->rx_dropped = dev->stats.rx_dropped;
6383 stats->tx_dropped = dev->stats.tx_dropped;
6384 stats->rx_length_errors = dev->stats.rx_length_errors;
6385 stats->rx_errors = dev->stats.rx_errors;
6386 stats->rx_crc_errors = dev->stats.rx_crc_errors;
6387 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
6388 stats->rx_missed_errors = dev->stats.rx_missed_errors;
6389
6390 return stats;
1da177e4
LT		 6391}
6392
861ab440 6393static void rtl8169_net_suspend(struct net_device *dev)
5d06a99f 6394{
065c27c1 6395 struct rtl8169_private *tp = netdev_priv(dev);
6396
5d06a99f 6397 if (!netif_running(dev))
861ab440 6398 return;
5d06a99f
FR		 6399
6400 netif_device_detach(dev);
6401 netif_stop_queue(dev);
da78dbff
FR		 6402
6403 rtl_lock_work(tp);
6404 napi_disable(&tp->napi);
6c4a70c5 6405 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
da78dbff
FR		 6406 rtl_unlock_work(tp);
6407
6408 rtl_pll_power_down(tp);
861ab440
RW		 6409}
6410
6411#ifdef CONFIG_PM
6412
6413static int rtl8169_suspend(struct device *device)
6414{
6415 struct pci_dev *pdev = to_pci_dev(device);
6416 struct net_device *dev = pci_get_drvdata(pdev);
5d06a99f 6417
861ab440 6418 rtl8169_net_suspend(dev);
1371fa6d 6419
5d06a99f
FR		 6420 return 0;
6421}
6422
e1759441
RW		 6423static void __rtl8169_resume(struct net_device *dev)
6424{
065c27c1 6425 struct rtl8169_private *tp = netdev_priv(dev);
6426
e1759441 6427 netif_device_attach(dev);
065c27c1 6428
6429 rtl_pll_power_up(tp);
6430
cff4c162
AS		 6431 rtl_lock_work(tp);
6432 napi_enable(&tp->napi);
6c4a70c5 6433 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
cff4c162 6434 rtl_unlock_work(tp);
da78dbff 6435
98ddf986 6436 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
e1759441
RW		 6437}
6438
861ab440 6439static int rtl8169_resume(struct device *device)
5d06a99f 6440{
861ab440 6441 struct pci_dev *pdev = to_pci_dev(device);
5d06a99f 6442 struct net_device *dev = pci_get_drvdata(pdev);
fccec10b
SG		 6443 struct rtl8169_private *tp = netdev_priv(dev);
6444
6445 rtl8169_init_phy(dev, tp);
5d06a99f 6446
e1759441
RW		 6447 if (netif_running(dev))
6448 __rtl8169_resume(dev);
5d06a99f 6449
e1759441
RW		 6450 return 0;
6451}
6452
6453static int rtl8169_runtime_suspend(struct device *device)
6454{
6455 struct pci_dev *pdev = to_pci_dev(device);
6456 struct net_device *dev = pci_get_drvdata(pdev);
6457 struct rtl8169_private *tp = netdev_priv(dev);
6458
6459 if (!tp->TxDescArray)
6460 return 0;
6461
da78dbff 6462 rtl_lock_work(tp);
e1759441
RW		 6463 tp->saved_wolopts = __rtl8169_get_wol(tp);
6464 __rtl8169_set_wol(tp, WAKE_ANY);
da78dbff 6465 rtl_unlock_work(tp);
e1759441
RW		 6466
6467 rtl8169_net_suspend(dev);
6468
6469 return 0;
6470}
6471
6472static int rtl8169_runtime_resume(struct device *device)
6473{
6474 struct pci_dev *pdev = to_pci_dev(device);
6475 struct net_device *dev = pci_get_drvdata(pdev);
6476 struct rtl8169_private *tp = netdev_priv(dev);
6477
6478 if (!tp->TxDescArray)
6479 return 0;
6480
da78dbff 6481 rtl_lock_work(tp);
e1759441
RW		 6482 __rtl8169_set_wol(tp, tp->saved_wolopts);
6483 tp->saved_wolopts = 0;
da78dbff 6484 rtl_unlock_work(tp);
e1759441 6485
fccec10b
SG		 6486 rtl8169_init_phy(dev, tp);
6487
e1759441 6488 __rtl8169_resume(dev);
5d06a99f 6489
5d06a99f
FR		 6490 return 0;
6491}
6492
e1759441
RW		 6493static int rtl8169_runtime_idle(struct device *device)
6494{
6495 struct pci_dev *pdev = to_pci_dev(device);
6496 struct net_device *dev = pci_get_drvdata(pdev);
6497 struct rtl8169_private *tp = netdev_priv(dev);
6498
e4fbce74 6499 return tp->TxDescArray ? -EBUSY : 0;
e1759441
RW		 6500}
6501
47145210 6502static const struct dev_pm_ops rtl8169_pm_ops = {
cecb5fd7
FR		 6503 .suspend = rtl8169_suspend,
6504 .resume = rtl8169_resume,
6505 .freeze = rtl8169_suspend,
6506 .thaw = rtl8169_resume,
6507 .poweroff = rtl8169_suspend,
6508 .restore = rtl8169_resume,
6509 .runtime_suspend = rtl8169_runtime_suspend,
6510 .runtime_resume = rtl8169_runtime_resume,
6511 .runtime_idle = rtl8169_runtime_idle,
861ab440
RW		 6512};
6513
6514#define RTL8169_PM_OPS (&rtl8169_pm_ops)
6515
6516#else /* !CONFIG_PM */
6517
6518#define RTL8169_PM_OPS NULL
6519
6520#endif /* !CONFIG_PM */
6521
649b3b8c 6522static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
6523{
6524 void __iomem *ioaddr = tp->mmio_addr;
6525
6526 /* WoL fails with 8168b when the receiver is disabled. */
6527 switch (tp->mac_version) {
6528 case RTL_GIGA_MAC_VER_11:
6529 case RTL_GIGA_MAC_VER_12:
6530 case RTL_GIGA_MAC_VER_17:
6531 pci_clear_master(tp->pci_dev);
6532
6533 RTL_W8(ChipCmd, CmdRxEnb);
6534 /* PCI commit */
6535 RTL_R8(ChipCmd);
6536 break;
6537 default:
6538 break;
6539 }
6540}
6541
1765f95d
FR		 6542static void rtl_shutdown(struct pci_dev *pdev)
6543{
861ab440 6544 struct net_device *dev = pci_get_drvdata(pdev);
4bb3f522 6545 struct rtl8169_private *tp = netdev_priv(dev);
2a15cd2f 6546 struct device *d = &pdev->dev;
6547
6548 pm_runtime_get_sync(d);
861ab440
RW		 6549
6550 rtl8169_net_suspend(dev);
1765f95d 6551
cecb5fd7 6552 /* Restore original MAC address */
cc098dc7
IV		 6553 rtl_rar_set(tp, dev->perm_addr);
6554
92fc43b4 6555 rtl8169_hw_reset(tp);
4bb3f522 6556
861ab440 6557 if (system_state == SYSTEM_POWER_OFF) {
649b3b8c 6558 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
6559 rtl_wol_suspend_quirk(tp);
6560 rtl_wol_shutdown_quirk(tp);
ca52efd5 6561 }
6562
861ab440
RW		 6563 pci_wake_from_d3(pdev, true);
6564 pci_set_power_state(pdev, PCI_D3hot);
6565 }
2a15cd2f 6566
6567 pm_runtime_put_noidle(d);
861ab440 6568}
5d06a99f 6569
baf63293 6570static void rtl_remove_one(struct pci_dev *pdev)
e27566ed
FR		 6571{
6572 struct net_device *dev = pci_get_drvdata(pdev);
6573 struct rtl8169_private *tp = netdev_priv(dev);
6574
6575 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
6576 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
6577 tp->mac_version == RTL_GIGA_MAC_VER_31) {
6578 rtl8168_driver_stop(tp);
6579 }
6580
6581 cancel_work_sync(&tp->wk.work);
6582
ad1be8d3
DN		 6583 netif_napi_del(&tp->napi);
6584
e27566ed
FR		 6585 unregister_netdev(dev);
6586
6587 rtl_release_firmware(tp);
6588
6589 if (pci_dev_run_wake(pdev))
6590 pm_runtime_get_noresume(&pdev->dev);
6591
6592 /* restore original MAC address */
6593 rtl_rar_set(tp, dev->perm_addr);
6594
6595 rtl_disable_msi(pdev, tp);
6596 rtl8169_release_board(pdev, dev, tp->mmio_addr);
6597 pci_set_drvdata(pdev, NULL);
6598}
6599
fa9c385e 6600static const struct net_device_ops rtl_netdev_ops = {
df43ac78 6601 .ndo_open = rtl_open,
fa9c385e
FR		 6602 .ndo_stop = rtl8169_close,
6603 .ndo_get_stats64 = rtl8169_get_stats64,
6604 .ndo_start_xmit = rtl8169_start_xmit,
6605 .ndo_tx_timeout = rtl8169_tx_timeout,
6606 .ndo_validate_addr = eth_validate_addr,
6607 .ndo_change_mtu = rtl8169_change_mtu,
6608 .ndo_fix_features = rtl8169_fix_features,
6609 .ndo_set_features = rtl8169_set_features,
6610 .ndo_set_mac_address = rtl_set_mac_address,
6611 .ndo_do_ioctl = rtl8169_ioctl,
6612 .ndo_set_rx_mode = rtl_set_rx_mode,
6613#ifdef CONFIG_NET_POLL_CONTROLLER
6614 .ndo_poll_controller = rtl8169_netpoll,
6615#endif
6616
6617};
6618
31fa8b18
FR		 6619static const struct rtl_cfg_info {
6620 void (*hw_start)(struct net_device *);
6621 unsigned int region;
6622 unsigned int align;
6623 u16 event_slow;
6624 unsigned features;
6625 u8 default_ver;
6626} rtl_cfg_infos [] = {
6627 [RTL_CFG_0] = {
6628 .hw_start = rtl_hw_start_8169,
6629 .region = 1,
6630 .align = 0,
6631 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
6632 .features = RTL_FEATURE_GMII,
6633 .default_ver = RTL_GIGA_MAC_VER_01,
6634 },
6635 [RTL_CFG_1] = {
6636 .hw_start = rtl_hw_start_8168,
6637 .region = 2,
6638 .align = 8,
6639 .event_slow = SYSErr | LinkChg | RxOverflow,
6640 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
6641 .default_ver = RTL_GIGA_MAC_VER_11,
6642 },
6643 [RTL_CFG_2] = {
6644 .hw_start = rtl_hw_start_8101,
6645 .region = 2,
6646 .align = 8,
6647 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
6648 PCSTimeout,
6649 .features = RTL_FEATURE_MSI,
6650 .default_ver = RTL_GIGA_MAC_VER_13,
6651 }
6652};
6653
6654/* Cfg9346_Unlock assumed. */
6655static unsigned rtl_try_msi(struct rtl8169_private *tp,
6656 const struct rtl_cfg_info *cfg)
6657{
6658 void __iomem *ioaddr = tp->mmio_addr;
6659 unsigned msi = 0;
6660 u8 cfg2;
6661
6662 cfg2 = RTL_R8(Config2) & ~MSIEnable;
6663 if (cfg->features & RTL_FEATURE_MSI) {
6664 if (pci_enable_msi(tp->pci_dev)) {
6665 netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
6666 } else {
6667 cfg2 |= MSIEnable;
6668 msi = RTL_FEATURE_MSI;
6669 }
6670 }
6671 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
6672 RTL_W8(Config2, cfg2);
6673 return msi;
6674}
6675
c558386b
HW		 6676DECLARE_RTL_COND(rtl_link_list_ready_cond)
6677{
6678 void __iomem *ioaddr = tp->mmio_addr;
6679
6680 return RTL_R8(MCU) & LINK_LIST_RDY;
6681}
6682
6683DECLARE_RTL_COND(rtl_rxtx_empty_cond)
6684{
6685 void __iomem *ioaddr = tp->mmio_addr;
6686
6687 return (RTL_R8(MCU) & RXTX_EMPTY) == RXTX_EMPTY;
6688}
6689
baf63293 6690static void rtl_hw_init_8168g(struct rtl8169_private *tp)
c558386b
HW		 6691{
6692 void __iomem *ioaddr = tp->mmio_addr;
6693 u32 data;
6694
6695 tp->ocp_base = OCP_STD_PHY_BASE;
6696
6697 RTL_W32(MISC, RTL_R32(MISC) | RXDV_GATED_EN);
6698
6699 if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
6700 return;
6701
6702 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
6703 return;
6704
6705 RTL_W8(ChipCmd, RTL_R8(ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
6706 msleep(1);
6707 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
6708
5f8bcce9 6709 data = r8168_mac_ocp_read(tp, 0xe8de);
c558386b
HW		 6710 data &= ~(1 << 14);
6711 r8168_mac_ocp_write(tp, 0xe8de, data);
6712
6713 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
6714 return;
6715
5f8bcce9 6716 data = r8168_mac_ocp_read(tp, 0xe8de);
c558386b
HW		 6717 data |= (1 << 15);
6718 r8168_mac_ocp_write(tp, 0xe8de, data);
6719
6720 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
6721 return;
6722}
6723
baf63293 6724static void rtl_hw_initialize(struct rtl8169_private *tp)
c558386b
HW		 6725{
6726 switch (tp->mac_version) {
6727 case RTL_GIGA_MAC_VER_40:
6728 case RTL_GIGA_MAC_VER_41:
6729 rtl_hw_init_8168g(tp);
6730 break;
6731
6732 default:
6733 break;
6734 }
6735}
6736
baf63293 6737static int
3b6cf25d
FR		 6738rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
6739{
6740 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
6741 const unsigned int region = cfg->region;
6742 struct rtl8169_private *tp;
6743 struct mii_if_info *mii;
6744 struct net_device *dev;
6745 void __iomem *ioaddr;
6746 int chipset, i;
6747 int rc;
6748
6749 if (netif_msg_drv(&debug)) {
6750 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
6751 MODULENAME, RTL8169_VERSION);
6752 }
6753
6754 dev = alloc_etherdev(sizeof (*tp));
6755 if (!dev) {
6756 rc = -ENOMEM;
6757 goto out;
6758 }
6759
6760 SET_NETDEV_DEV(dev, &pdev->dev);
fa9c385e 6761 dev->netdev_ops = &rtl_netdev_ops;
3b6cf25d
FR		 6762 tp = netdev_priv(dev);
6763 tp->dev = dev;
6764 tp->pci_dev = pdev;
6765 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
6766
6767 mii = &tp->mii;
6768 mii->dev = dev;
6769 mii->mdio_read = rtl_mdio_read;
6770 mii->mdio_write = rtl_mdio_write;
6771 mii->phy_id_mask = 0x1f;
6772 mii->reg_num_mask = 0x1f;
6773 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
6774
6775 /* disable ASPM completely as that cause random device stop working
6776 * problems as well as full system hangs for some PCIe devices users */
6777 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
6778 PCIE_LINK_STATE_CLKPM);
6779
6780 /* enable device (incl. PCI PM wakeup and hotplug setup) */
6781 rc = pci_enable_device(pdev);
6782 if (rc < 0) {
6783 netif_err(tp, probe, dev, "enable failure\n");
6784 goto err_out_free_dev_1;
6785 }
6786
6787 if (pci_set_mwi(pdev) < 0)
6788 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
6789
6790 /* make sure PCI base addr 1 is MMIO */
6791 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
6792 netif_err(tp, probe, dev,
6793 "region #%d not an MMIO resource, aborting\n",
6794 region);
6795 rc = -ENODEV;
6796 goto err_out_mwi_2;
6797 }
6798
6799 /* check for weird/broken PCI region reporting */
6800 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
6801 netif_err(tp, probe, dev,
6802 "Invalid PCI region size(s), aborting\n");
6803 rc = -ENODEV;
6804 goto err_out_mwi_2;
6805 }
6806
6807 rc = pci_request_regions(pdev, MODULENAME);
6808 if (rc < 0) {
6809 netif_err(tp, probe, dev, "could not request regions\n");
6810 goto err_out_mwi_2;
6811 }
6812
6813 tp->cp_cmd = RxChkSum;
6814
6815 if ((sizeof(dma_addr_t) > 4) &&
6816 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
6817 tp->cp_cmd |= PCIDAC;
6818 dev->features |= NETIF_F_HIGHDMA;
6819 } else {
6820 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6821 if (rc < 0) {
6822 netif_err(tp, probe, dev, "DMA configuration failed\n");
6823 goto err_out_free_res_3;
6824 }
6825 }
6826
6827 /* ioremap MMIO region */
6828 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
6829 if (!ioaddr) {
6830 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
6831 rc = -EIO;
6832 goto err_out_free_res_3;
6833 }
6834 tp->mmio_addr = ioaddr;
6835
6836 if (!pci_is_pcie(pdev))
6837 netif_info(tp, probe, dev, "not PCI Express\n");
6838
6839 /* Identify chip attached to board */
6840 rtl8169_get_mac_version(tp, dev, cfg->default_ver);
6841
6842 rtl_init_rxcfg(tp);
6843
6844 rtl_irq_disable(tp);
6845
c558386b
HW		 6846 rtl_hw_initialize(tp);
6847
3b6cf25d
FR		 6848 rtl_hw_reset(tp);
6849
6850 rtl_ack_events(tp, 0xffff);
6851
6852 pci_set_master(pdev);
6853
6854 /*
6855 * Pretend we are using VLANs; This bypasses a nasty bug where
6856 * Interrupts stop flowing on high load on 8110SCd controllers.
6857 */
6858 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
6859 tp->cp_cmd |= RxVlan;
6860
6861 rtl_init_mdio_ops(tp);
6862 rtl_init_pll_power_ops(tp);
6863 rtl_init_jumbo_ops(tp);
beb1fe18 6864 rtl_init_csi_ops(tp);
3b6cf25d
FR		 6865
6866 rtl8169_print_mac_version(tp);
6867
6868 chipset = tp->mac_version;
6869 tp->txd_version = rtl_chip_infos[chipset].txd_version;
6870
6871 RTL_W8(Cfg9346, Cfg9346_Unlock);
6872 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
6873 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
6874 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
6875 tp->features |= RTL_FEATURE_WOL;
6876 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
6877 tp->features |= RTL_FEATURE_WOL;
6878 tp->features |= rtl_try_msi(tp, cfg);
6879 RTL_W8(Cfg9346, Cfg9346_Lock);
6880
6881 if (rtl_tbi_enabled(tp)) {
6882 tp->set_speed = rtl8169_set_speed_tbi;
6883 tp->get_settings = rtl8169_gset_tbi;
6884 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
6885 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
6886 tp->link_ok = rtl8169_tbi_link_ok;
6887 tp->do_ioctl = rtl_tbi_ioctl;
6888 } else {
6889 tp->set_speed = rtl8169_set_speed_xmii;
6890 tp->get_settings = rtl8169_gset_xmii;
6891 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
6892 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
6893 tp->link_ok = rtl8169_xmii_link_ok;
6894 tp->do_ioctl = rtl_xmii_ioctl;
6895 }
6896
6897 mutex_init(&tp->wk.mutex);
6898
6899 /* Get MAC address */
6900 for (i = 0; i < ETH_ALEN; i++)
6901 dev->dev_addr[i] = RTL_R8(MAC0 + i);
3b6cf25d
FR		 6902
6903 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
6904 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3b6cf25d
FR		 6905
6906 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
6907
6908 /* don't enable SG, IP_CSUM and TSO by default - it might not work
6909 * properly for all devices */
6910 dev->features |= NETIF_F_RXCSUM |
6911 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
6912
6913 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6914 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
6915 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6916 NETIF_F_HIGHDMA;
6917
6918 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
6919 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
6920 dev->hw_features &= ~NETIF_F_HW_VLAN_RX;
6921
6922 dev->hw_features |= NETIF_F_RXALL;
6923 dev->hw_features |= NETIF_F_RXFCS;
6924
6925 tp->hw_start = cfg->hw_start;
6926 tp->event_slow = cfg->event_slow;
6927
6928 tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
6929 ~(RxBOVF | RxFOVF) : ~0;
6930
6931 init_timer(&tp->timer);
6932 tp->timer.data = (unsigned long) dev;
6933 tp->timer.function = rtl8169_phy_timer;
6934
6935 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
6936
6937 rc = register_netdev(dev);
6938 if (rc < 0)
6939 goto err_out_msi_4;
6940
6941 pci_set_drvdata(pdev, dev);
6942
92a7c4e7
FR		 6943 netif_info(tp, probe, dev, "%s at 0x%p, %pM, XID %08x IRQ %d\n",
6944 rtl_chip_infos[chipset].name, ioaddr, dev->dev_addr,
6945 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), pdev->irq);
3b6cf25d
FR		 6946 if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
6947 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
6948 "tx checksumming: %s]\n",
6949 rtl_chip_infos[chipset].jumbo_max,
6950 rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
6951 }
6952
6953 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
6954 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
6955 tp->mac_version == RTL_GIGA_MAC_VER_31) {
6956 rtl8168_driver_start(tp);
6957 }
6958
6959 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
6960
6961 if (pci_dev_run_wake(pdev))
6962 pm_runtime_put_noidle(&pdev->dev);
6963
6964 netif_carrier_off(dev);
6965
6966out:
6967 return rc;
6968
6969err_out_msi_4:
ad1be8d3 6970 netif_napi_del(&tp->napi);
3b6cf25d
FR		 6971 rtl_disable_msi(pdev, tp);
6972 iounmap(ioaddr);
6973err_out_free_res_3:
6974 pci_release_regions(pdev);
6975err_out_mwi_2:
6976 pci_clear_mwi(pdev);
6977 pci_disable_device(pdev);
6978err_out_free_dev_1:
6979 free_netdev(dev);
6980 goto out;
6981}
6982
1da177e4
LT		 6983static struct pci_driver rtl8169_pci_driver = {
6984 .name = MODULENAME,
6985 .id_table = rtl8169_pci_tbl,
3b6cf25d 6986 .probe = rtl_init_one,
baf63293 6987 .remove = rtl_remove_one,
1765f95d 6988 .shutdown = rtl_shutdown,
861ab440 6989 .driver.pm = RTL8169_PM_OPS,
1da177e4
LT		 6990};
6991
3eeb7da9 6992module_pci_driver(rtl8169_pci_driver);
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