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Commit | Line | Data |
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1da177e4 | 1 | /* |
07d3f51f FR |
2 | * r8169.c: RealTek 8169/8168/8101 ethernet driver. |
3 | * | |
4 | * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw> | |
5 | * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com> | |
6 | * Copyright (c) a lot of people too. Please respect their work. | |
7 | * | |
8 | * See MAINTAINERS file for support contact information. | |
1da177e4 LT |
9 | */ |
10 | ||
11 | #include <linux/module.h> | |
12 | #include <linux/moduleparam.h> | |
13 | #include <linux/pci.h> | |
14 | #include <linux/netdevice.h> | |
15 | #include <linux/etherdevice.h> | |
16 | #include <linux/delay.h> | |
17 | #include <linux/ethtool.h> | |
18 | #include <linux/mii.h> | |
19 | #include <linux/if_vlan.h> | |
20 | #include <linux/crc32.h> | |
21 | #include <linux/in.h> | |
22 | #include <linux/ip.h> | |
23 | #include <linux/tcp.h> | |
24 | #include <linux/init.h> | |
a6b7a407 | 25 | #include <linux/interrupt.h> |
1da177e4 | 26 | #include <linux/dma-mapping.h> |
e1759441 | 27 | #include <linux/pm_runtime.h> |
bca03d5f | 28 | #include <linux/firmware.h> |
ba04c7c9 | 29 | #include <linux/pci-aspm.h> |
70c71606 | 30 | #include <linux/prefetch.h> |
1da177e4 LT |
31 | |
32 | #include <asm/io.h> | |
33 | #include <asm/irq.h> | |
34 | ||
865c652d | 35 | #define RTL8169_VERSION "2.3LK-NAPI" |
1da177e4 LT |
36 | #define MODULENAME "r8169" |
37 | #define PFX MODULENAME ": " | |
38 | ||
bca03d5f | 39 | #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw" |
40 | #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw" | |
01dc7fec | 41 | #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw" |
42 | #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw" | |
70090424 | 43 | #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw" |
c2218925 HW |
44 | #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw" |
45 | #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw" | |
5a5e4443 | 46 | #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw" |
7e18dca1 | 47 | #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw" |
b3d7b2f2 | 48 | #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw" |
5598bfe5 | 49 | #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw" |
bca03d5f | 50 | |
1da177e4 LT |
51 | #ifdef RTL8169_DEBUG |
52 | #define assert(expr) \ | |
5b0384f4 FR |
53 | if (!(expr)) { \ |
54 | printk( "Assertion failed! %s,%s,%s,line=%d\n", \ | |
b39d66a8 | 55 | #expr,__FILE__,__func__,__LINE__); \ |
5b0384f4 | 56 | } |
06fa7358 JP |
57 | #define dprintk(fmt, args...) \ |
58 | do { printk(KERN_DEBUG PFX fmt, ## args); } while (0) | |
1da177e4 LT |
59 | #else |
60 | #define assert(expr) do {} while (0) | |
61 | #define dprintk(fmt, args...) do {} while (0) | |
62 | #endif /* RTL8169_DEBUG */ | |
63 | ||
b57b7e5a | 64 | #define R8169_MSG_DEFAULT \ |
f0e837d9 | 65 | (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN) |
b57b7e5a | 66 | |
477206a0 JD |
67 | #define TX_SLOTS_AVAIL(tp) \ |
68 | (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx) | |
69 | ||
70 | /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */ | |
71 | #define TX_FRAGS_READY_FOR(tp,nr_frags) \ | |
72 | (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1)) | |
1da177e4 | 73 | |
1da177e4 LT |
74 | /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). |
75 | The RTL chips use a 64 element hash table based on the Ethernet CRC. */ | |
f71e1309 | 76 | static const int multicast_filter_limit = 32; |
1da177e4 | 77 | |
9c14ceaf | 78 | #define MAX_READ_REQUEST_SHIFT 12 |
1da177e4 | 79 | #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ |
1da177e4 LT |
80 | #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */ |
81 | #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ | |
82 | ||
83 | #define R8169_REGS_SIZE 256 | |
84 | #define R8169_NAPI_WEIGHT 64 | |
85 | #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */ | |
86 | #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */ | |
87 | #define RX_BUF_SIZE 1536 /* Rx Buffer size */ | |
88 | #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc)) | |
89 | #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc)) | |
90 | ||
91 | #define RTL8169_TX_TIMEOUT (6*HZ) | |
92 | #define RTL8169_PHY_TIMEOUT (10*HZ) | |
93 | ||
ea8dbdd1 | 94 | #define RTL_EEPROM_SIG cpu_to_le32(0x8129) |
95 | #define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff) | |
e1564ec9 FR |
96 | #define RTL_EEPROM_SIG_ADDR 0x0000 |
97 | ||
1da177e4 LT |
98 | /* write/read MMIO register */ |
99 | #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg)) | |
100 | #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg)) | |
101 | #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg)) | |
102 | #define RTL_R8(reg) readb (ioaddr + (reg)) | |
103 | #define RTL_R16(reg) readw (ioaddr + (reg)) | |
06f555f3 | 104 | #define RTL_R32(reg) readl (ioaddr + (reg)) |
1da177e4 LT |
105 | |
106 | enum mac_version { | |
85bffe6c FR |
107 | RTL_GIGA_MAC_VER_01 = 0, |
108 | RTL_GIGA_MAC_VER_02, | |
109 | RTL_GIGA_MAC_VER_03, | |
110 | RTL_GIGA_MAC_VER_04, | |
111 | RTL_GIGA_MAC_VER_05, | |
112 | RTL_GIGA_MAC_VER_06, | |
113 | RTL_GIGA_MAC_VER_07, | |
114 | RTL_GIGA_MAC_VER_08, | |
115 | RTL_GIGA_MAC_VER_09, | |
116 | RTL_GIGA_MAC_VER_10, | |
117 | RTL_GIGA_MAC_VER_11, | |
118 | RTL_GIGA_MAC_VER_12, | |
119 | RTL_GIGA_MAC_VER_13, | |
120 | RTL_GIGA_MAC_VER_14, | |
121 | RTL_GIGA_MAC_VER_15, | |
122 | RTL_GIGA_MAC_VER_16, | |
123 | RTL_GIGA_MAC_VER_17, | |
124 | RTL_GIGA_MAC_VER_18, | |
125 | RTL_GIGA_MAC_VER_19, | |
126 | RTL_GIGA_MAC_VER_20, | |
127 | RTL_GIGA_MAC_VER_21, | |
128 | RTL_GIGA_MAC_VER_22, | |
129 | RTL_GIGA_MAC_VER_23, | |
130 | RTL_GIGA_MAC_VER_24, | |
131 | RTL_GIGA_MAC_VER_25, | |
132 | RTL_GIGA_MAC_VER_26, | |
133 | RTL_GIGA_MAC_VER_27, | |
134 | RTL_GIGA_MAC_VER_28, | |
135 | RTL_GIGA_MAC_VER_29, | |
136 | RTL_GIGA_MAC_VER_30, | |
137 | RTL_GIGA_MAC_VER_31, | |
138 | RTL_GIGA_MAC_VER_32, | |
139 | RTL_GIGA_MAC_VER_33, | |
70090424 | 140 | RTL_GIGA_MAC_VER_34, |
c2218925 HW |
141 | RTL_GIGA_MAC_VER_35, |
142 | RTL_GIGA_MAC_VER_36, | |
7e18dca1 | 143 | RTL_GIGA_MAC_VER_37, |
b3d7b2f2 | 144 | RTL_GIGA_MAC_VER_38, |
5598bfe5 | 145 | RTL_GIGA_MAC_VER_39, |
85bffe6c | 146 | RTL_GIGA_MAC_NONE = 0xff, |
1da177e4 LT |
147 | }; |
148 | ||
2b7b4318 FR |
149 | enum rtl_tx_desc_version { |
150 | RTL_TD_0 = 0, | |
151 | RTL_TD_1 = 1, | |
152 | }; | |
153 | ||
d58d46b5 FR |
154 | #define JUMBO_1K ETH_DATA_LEN |
155 | #define JUMBO_4K (4*1024 - ETH_HLEN - 2) | |
156 | #define JUMBO_6K (6*1024 - ETH_HLEN - 2) | |
157 | #define JUMBO_7K (7*1024 - ETH_HLEN - 2) | |
158 | #define JUMBO_9K (9*1024 - ETH_HLEN - 2) | |
159 | ||
160 | #define _R(NAME,TD,FW,SZ,B) { \ | |
161 | .name = NAME, \ | |
162 | .txd_version = TD, \ | |
163 | .fw_name = FW, \ | |
164 | .jumbo_max = SZ, \ | |
165 | .jumbo_tx_csum = B \ | |
166 | } | |
1da177e4 | 167 | |
3c6bee1d | 168 | static const struct { |
1da177e4 | 169 | const char *name; |
2b7b4318 | 170 | enum rtl_tx_desc_version txd_version; |
953a12cc | 171 | const char *fw_name; |
d58d46b5 FR |
172 | u16 jumbo_max; |
173 | bool jumbo_tx_csum; | |
85bffe6c FR |
174 | } rtl_chip_infos[] = { |
175 | /* PCI devices. */ | |
176 | [RTL_GIGA_MAC_VER_01] = | |
d58d46b5 | 177 | _R("RTL8169", RTL_TD_0, NULL, JUMBO_7K, true), |
85bffe6c | 178 | [RTL_GIGA_MAC_VER_02] = |
d58d46b5 | 179 | _R("RTL8169s", RTL_TD_0, NULL, JUMBO_7K, true), |
85bffe6c | 180 | [RTL_GIGA_MAC_VER_03] = |
d58d46b5 | 181 | _R("RTL8110s", RTL_TD_0, NULL, JUMBO_7K, true), |
85bffe6c | 182 | [RTL_GIGA_MAC_VER_04] = |
d58d46b5 | 183 | _R("RTL8169sb/8110sb", RTL_TD_0, NULL, JUMBO_7K, true), |
85bffe6c | 184 | [RTL_GIGA_MAC_VER_05] = |
d58d46b5 | 185 | _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true), |
85bffe6c | 186 | [RTL_GIGA_MAC_VER_06] = |
d58d46b5 | 187 | _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true), |
85bffe6c FR |
188 | /* PCI-E devices. */ |
189 | [RTL_GIGA_MAC_VER_07] = | |
d58d46b5 | 190 | _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true), |
85bffe6c | 191 | [RTL_GIGA_MAC_VER_08] = |
d58d46b5 | 192 | _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true), |
85bffe6c | 193 | [RTL_GIGA_MAC_VER_09] = |
d58d46b5 | 194 | _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true), |
85bffe6c | 195 | [RTL_GIGA_MAC_VER_10] = |
d58d46b5 | 196 | _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true), |
85bffe6c | 197 | [RTL_GIGA_MAC_VER_11] = |
d58d46b5 | 198 | _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false), |
85bffe6c | 199 | [RTL_GIGA_MAC_VER_12] = |
d58d46b5 | 200 | _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false), |
85bffe6c | 201 | [RTL_GIGA_MAC_VER_13] = |
d58d46b5 | 202 | _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true), |
85bffe6c | 203 | [RTL_GIGA_MAC_VER_14] = |
d58d46b5 | 204 | _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true), |
85bffe6c | 205 | [RTL_GIGA_MAC_VER_15] = |
d58d46b5 | 206 | _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true), |
85bffe6c | 207 | [RTL_GIGA_MAC_VER_16] = |
d58d46b5 | 208 | _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true), |
85bffe6c | 209 | [RTL_GIGA_MAC_VER_17] = |
d58d46b5 | 210 | _R("RTL8168b/8111b", RTL_TD_1, NULL, JUMBO_4K, false), |
85bffe6c | 211 | [RTL_GIGA_MAC_VER_18] = |
d58d46b5 | 212 | _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false), |
85bffe6c | 213 | [RTL_GIGA_MAC_VER_19] = |
d58d46b5 | 214 | _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false), |
85bffe6c | 215 | [RTL_GIGA_MAC_VER_20] = |
d58d46b5 | 216 | _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false), |
85bffe6c | 217 | [RTL_GIGA_MAC_VER_21] = |
d58d46b5 | 218 | _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false), |
85bffe6c | 219 | [RTL_GIGA_MAC_VER_22] = |
d58d46b5 | 220 | _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false), |
85bffe6c | 221 | [RTL_GIGA_MAC_VER_23] = |
d58d46b5 | 222 | _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false), |
85bffe6c | 223 | [RTL_GIGA_MAC_VER_24] = |
d58d46b5 | 224 | _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false), |
85bffe6c | 225 | [RTL_GIGA_MAC_VER_25] = |
d58d46b5 FR |
226 | _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1, |
227 | JUMBO_9K, false), | |
85bffe6c | 228 | [RTL_GIGA_MAC_VER_26] = |
d58d46b5 FR |
229 | _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2, |
230 | JUMBO_9K, false), | |
85bffe6c | 231 | [RTL_GIGA_MAC_VER_27] = |
d58d46b5 | 232 | _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false), |
85bffe6c | 233 | [RTL_GIGA_MAC_VER_28] = |
d58d46b5 | 234 | _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false), |
85bffe6c | 235 | [RTL_GIGA_MAC_VER_29] = |
d58d46b5 FR |
236 | _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1, |
237 | JUMBO_1K, true), | |
85bffe6c | 238 | [RTL_GIGA_MAC_VER_30] = |
d58d46b5 FR |
239 | _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1, |
240 | JUMBO_1K, true), | |
85bffe6c | 241 | [RTL_GIGA_MAC_VER_31] = |
d58d46b5 | 242 | _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false), |
85bffe6c | 243 | [RTL_GIGA_MAC_VER_32] = |
d58d46b5 FR |
244 | _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1, |
245 | JUMBO_9K, false), | |
85bffe6c | 246 | [RTL_GIGA_MAC_VER_33] = |
d58d46b5 FR |
247 | _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2, |
248 | JUMBO_9K, false), | |
70090424 | 249 | [RTL_GIGA_MAC_VER_34] = |
d58d46b5 FR |
250 | _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3, |
251 | JUMBO_9K, false), | |
c2218925 | 252 | [RTL_GIGA_MAC_VER_35] = |
d58d46b5 FR |
253 | _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_1, |
254 | JUMBO_9K, false), | |
c2218925 | 255 | [RTL_GIGA_MAC_VER_36] = |
d58d46b5 FR |
256 | _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_2, |
257 | JUMBO_9K, false), | |
7e18dca1 HW |
258 | [RTL_GIGA_MAC_VER_37] = |
259 | _R("RTL8402", RTL_TD_1, FIRMWARE_8402_1, | |
260 | JUMBO_1K, true), | |
b3d7b2f2 HW |
261 | [RTL_GIGA_MAC_VER_38] = |
262 | _R("RTL8411", RTL_TD_1, FIRMWARE_8411_1, | |
263 | JUMBO_9K, false), | |
5598bfe5 HW |
264 | [RTL_GIGA_MAC_VER_39] = |
265 | _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_1, | |
266 | JUMBO_1K, true), | |
953a12cc | 267 | }; |
85bffe6c | 268 | #undef _R |
953a12cc | 269 | |
bcf0bf90 FR |
270 | enum cfg_version { |
271 | RTL_CFG_0 = 0x00, | |
272 | RTL_CFG_1, | |
273 | RTL_CFG_2 | |
274 | }; | |
275 | ||
a3aa1884 | 276 | static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = { |
bcf0bf90 | 277 | { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 }, |
d2eed8cf | 278 | { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 }, |
d81bf551 | 279 | { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 }, |
07ce4064 | 280 | { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 }, |
bcf0bf90 FR |
281 | { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 }, |
282 | { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 }, | |
93a3aa25 | 283 | { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 }, |
bc1660b5 | 284 | { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 }, |
bcf0bf90 FR |
285 | { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 }, |
286 | { PCI_VENDOR_ID_LINKSYS, 0x1032, | |
287 | PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 }, | |
11d2e282 CM |
288 | { 0x0001, 0x8168, |
289 | PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 }, | |
1da177e4 LT |
290 | {0,}, |
291 | }; | |
292 | ||
293 | MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl); | |
294 | ||
6f0333b8 | 295 | static int rx_buf_sz = 16383; |
4300e8c7 | 296 | static int use_dac; |
b57b7e5a SH |
297 | static struct { |
298 | u32 msg_enable; | |
299 | } debug = { -1 }; | |
1da177e4 | 300 | |
07d3f51f FR |
301 | enum rtl_registers { |
302 | MAC0 = 0, /* Ethernet hardware address. */ | |
773d2021 | 303 | MAC4 = 4, |
07d3f51f FR |
304 | MAR0 = 8, /* Multicast filter. */ |
305 | CounterAddrLow = 0x10, | |
306 | CounterAddrHigh = 0x14, | |
307 | TxDescStartAddrLow = 0x20, | |
308 | TxDescStartAddrHigh = 0x24, | |
309 | TxHDescStartAddrLow = 0x28, | |
310 | TxHDescStartAddrHigh = 0x2c, | |
311 | FLASH = 0x30, | |
312 | ERSR = 0x36, | |
313 | ChipCmd = 0x37, | |
314 | TxPoll = 0x38, | |
315 | IntrMask = 0x3c, | |
316 | IntrStatus = 0x3e, | |
4f6b00e5 | 317 | |
07d3f51f | 318 | TxConfig = 0x40, |
4f6b00e5 HW |
319 | #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */ |
320 | #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */ | |
2b7b4318 | 321 | |
4f6b00e5 HW |
322 | RxConfig = 0x44, |
323 | #define RX128_INT_EN (1 << 15) /* 8111c and later */ | |
324 | #define RX_MULTI_EN (1 << 14) /* 8111c only */ | |
325 | #define RXCFG_FIFO_SHIFT 13 | |
326 | /* No threshold before first PCI xfer */ | |
327 | #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT) | |
328 | #define RXCFG_DMA_SHIFT 8 | |
329 | /* Unlimited maximum PCI burst. */ | |
330 | #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT) | |
2b7b4318 | 331 | |
07d3f51f FR |
332 | RxMissed = 0x4c, |
333 | Cfg9346 = 0x50, | |
334 | Config0 = 0x51, | |
335 | Config1 = 0x52, | |
336 | Config2 = 0x53, | |
d387b427 FR |
337 | #define PME_SIGNAL (1 << 5) /* 8168c and later */ |
338 | ||
07d3f51f FR |
339 | Config3 = 0x54, |
340 | Config4 = 0x55, | |
341 | Config5 = 0x56, | |
342 | MultiIntr = 0x5c, | |
343 | PHYAR = 0x60, | |
07d3f51f FR |
344 | PHYstatus = 0x6c, |
345 | RxMaxSize = 0xda, | |
346 | CPlusCmd = 0xe0, | |
347 | IntrMitigate = 0xe2, | |
348 | RxDescAddrLow = 0xe4, | |
349 | RxDescAddrHigh = 0xe8, | |
f0298f81 | 350 | EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */ |
351 | ||
352 | #define NoEarlyTx 0x3f /* Max value : no early transmit. */ | |
353 | ||
354 | MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */ | |
355 | ||
356 | #define TxPacketMax (8064 >> 7) | |
3090bd9a | 357 | #define EarlySize 0x27 |
f0298f81 | 358 | |
07d3f51f FR |
359 | FuncEvent = 0xf0, |
360 | FuncEventMask = 0xf4, | |
361 | FuncPresetState = 0xf8, | |
362 | FuncForceEvent = 0xfc, | |
1da177e4 LT |
363 | }; |
364 | ||
f162a5d1 FR |
365 | enum rtl8110_registers { |
366 | TBICSR = 0x64, | |
367 | TBI_ANAR = 0x68, | |
368 | TBI_LPAR = 0x6a, | |
369 | }; | |
370 | ||
371 | enum rtl8168_8101_registers { | |
372 | CSIDR = 0x64, | |
373 | CSIAR = 0x68, | |
374 | #define CSIAR_FLAG 0x80000000 | |
375 | #define CSIAR_WRITE_CMD 0x80000000 | |
376 | #define CSIAR_BYTE_ENABLE 0x0f | |
377 | #define CSIAR_BYTE_ENABLE_SHIFT 12 | |
378 | #define CSIAR_ADDR_MASK 0x0fff | |
7e18dca1 HW |
379 | #define CSIAR_FUNC_CARD 0x00000000 |
380 | #define CSIAR_FUNC_SDIO 0x00010000 | |
381 | #define CSIAR_FUNC_NIC 0x00020000 | |
065c27c1 | 382 | PMCH = 0x6f, |
f162a5d1 FR |
383 | EPHYAR = 0x80, |
384 | #define EPHYAR_FLAG 0x80000000 | |
385 | #define EPHYAR_WRITE_CMD 0x80000000 | |
386 | #define EPHYAR_REG_MASK 0x1f | |
387 | #define EPHYAR_REG_SHIFT 16 | |
388 | #define EPHYAR_DATA_MASK 0xffff | |
5a5e4443 | 389 | DLLPR = 0xd0, |
4f6b00e5 | 390 | #define PFM_EN (1 << 6) |
f162a5d1 FR |
391 | DBG_REG = 0xd1, |
392 | #define FIX_NAK_1 (1 << 4) | |
393 | #define FIX_NAK_2 (1 << 3) | |
5a5e4443 HW |
394 | TWSI = 0xd2, |
395 | MCU = 0xd3, | |
4f6b00e5 | 396 | #define NOW_IS_OOB (1 << 7) |
5a5e4443 HW |
397 | #define EN_NDP (1 << 3) |
398 | #define EN_OOB_RESET (1 << 2) | |
daf9df6d | 399 | EFUSEAR = 0xdc, |
400 | #define EFUSEAR_FLAG 0x80000000 | |
401 | #define EFUSEAR_WRITE_CMD 0x80000000 | |
402 | #define EFUSEAR_READ_CMD 0x00000000 | |
403 | #define EFUSEAR_REG_MASK 0x03ff | |
404 | #define EFUSEAR_REG_SHIFT 8 | |
405 | #define EFUSEAR_DATA_MASK 0xff | |
f162a5d1 FR |
406 | }; |
407 | ||
c0e45c1c | 408 | enum rtl8168_registers { |
4f6b00e5 HW |
409 | LED_FREQ = 0x1a, |
410 | EEE_LED = 0x1b, | |
b646d900 | 411 | ERIDR = 0x70, |
412 | ERIAR = 0x74, | |
413 | #define ERIAR_FLAG 0x80000000 | |
414 | #define ERIAR_WRITE_CMD 0x80000000 | |
415 | #define ERIAR_READ_CMD 0x00000000 | |
416 | #define ERIAR_ADDR_BYTE_ALIGN 4 | |
b646d900 | 417 | #define ERIAR_TYPE_SHIFT 16 |
4f6b00e5 HW |
418 | #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT) |
419 | #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT) | |
420 | #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT) | |
421 | #define ERIAR_MASK_SHIFT 12 | |
422 | #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT) | |
423 | #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT) | |
424 | #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT) | |
c0e45c1c | 425 | EPHY_RXER_NUM = 0x7c, |
426 | OCPDR = 0xb0, /* OCP GPHY access */ | |
427 | #define OCPDR_WRITE_CMD 0x80000000 | |
428 | #define OCPDR_READ_CMD 0x00000000 | |
429 | #define OCPDR_REG_MASK 0x7f | |
430 | #define OCPDR_GPHY_REG_SHIFT 16 | |
431 | #define OCPDR_DATA_MASK 0xffff | |
432 | OCPAR = 0xb4, | |
433 | #define OCPAR_FLAG 0x80000000 | |
434 | #define OCPAR_GPHY_WRITE_CMD 0x8000f060 | |
435 | #define OCPAR_GPHY_READ_CMD 0x0000f060 | |
01dc7fec | 436 | RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */ |
437 | MISC = 0xf0, /* 8168e only. */ | |
cecb5fd7 | 438 | #define TXPLA_RST (1 << 29) |
5598bfe5 | 439 | #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */ |
4f6b00e5 | 440 | #define PWM_EN (1 << 22) |
5598bfe5 | 441 | #define EARLY_TALLY_EN (1 << 16) |
c0e45c1c | 442 | }; |
443 | ||
07d3f51f | 444 | enum rtl_register_content { |
1da177e4 | 445 | /* InterruptStatusBits */ |
07d3f51f FR |
446 | SYSErr = 0x8000, |
447 | PCSTimeout = 0x4000, | |
448 | SWInt = 0x0100, | |
449 | TxDescUnavail = 0x0080, | |
450 | RxFIFOOver = 0x0040, | |
451 | LinkChg = 0x0020, | |
452 | RxOverflow = 0x0010, | |
453 | TxErr = 0x0008, | |
454 | TxOK = 0x0004, | |
455 | RxErr = 0x0002, | |
456 | RxOK = 0x0001, | |
1da177e4 LT |
457 | |
458 | /* RxStatusDesc */ | |
e03f33af | 459 | RxBOVF = (1 << 24), |
9dccf611 FR |
460 | RxFOVF = (1 << 23), |
461 | RxRWT = (1 << 22), | |
462 | RxRES = (1 << 21), | |
463 | RxRUNT = (1 << 20), | |
464 | RxCRC = (1 << 19), | |
1da177e4 LT |
465 | |
466 | /* ChipCmdBits */ | |
4f6b00e5 | 467 | StopReq = 0x80, |
07d3f51f FR |
468 | CmdReset = 0x10, |
469 | CmdRxEnb = 0x08, | |
470 | CmdTxEnb = 0x04, | |
471 | RxBufEmpty = 0x01, | |
1da177e4 | 472 | |
275391a4 FR |
473 | /* TXPoll register p.5 */ |
474 | HPQ = 0x80, /* Poll cmd on the high prio queue */ | |
475 | NPQ = 0x40, /* Poll cmd on the low prio queue */ | |
476 | FSWInt = 0x01, /* Forced software interrupt */ | |
477 | ||
1da177e4 | 478 | /* Cfg9346Bits */ |
07d3f51f FR |
479 | Cfg9346_Lock = 0x00, |
480 | Cfg9346_Unlock = 0xc0, | |
1da177e4 LT |
481 | |
482 | /* rx_mode_bits */ | |
07d3f51f FR |
483 | AcceptErr = 0x20, |
484 | AcceptRunt = 0x10, | |
485 | AcceptBroadcast = 0x08, | |
486 | AcceptMulticast = 0x04, | |
487 | AcceptMyPhys = 0x02, | |
488 | AcceptAllPhys = 0x01, | |
1687b566 | 489 | #define RX_CONFIG_ACCEPT_MASK 0x3f |
1da177e4 | 490 | |
1da177e4 LT |
491 | /* TxConfigBits */ |
492 | TxInterFrameGapShift = 24, | |
493 | TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ | |
494 | ||
5d06a99f | 495 | /* Config1 register p.24 */ |
f162a5d1 FR |
496 | LEDS1 = (1 << 7), |
497 | LEDS0 = (1 << 6), | |
f162a5d1 FR |
498 | Speed_down = (1 << 4), |
499 | MEMMAP = (1 << 3), | |
500 | IOMAP = (1 << 2), | |
501 | VPD = (1 << 1), | |
5d06a99f FR |
502 | PMEnable = (1 << 0), /* Power Management Enable */ |
503 | ||
6dccd16b | 504 | /* Config2 register p. 25 */ |
2ca6cf06 | 505 | MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */ |
6dccd16b FR |
506 | PCI_Clock_66MHz = 0x01, |
507 | PCI_Clock_33MHz = 0x00, | |
508 | ||
61a4dcc2 FR |
509 | /* Config3 register p.25 */ |
510 | MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */ | |
511 | LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */ | |
d58d46b5 | 512 | Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */ |
f162a5d1 | 513 | Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */ |
61a4dcc2 | 514 | |
d58d46b5 FR |
515 | /* Config4 register */ |
516 | Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */ | |
517 | ||
5d06a99f | 518 | /* Config5 register p.27 */ |
61a4dcc2 FR |
519 | BWF = (1 << 6), /* Accept Broadcast wakeup frame */ |
520 | MWF = (1 << 5), /* Accept Multicast wakeup frame */ | |
521 | UWF = (1 << 4), /* Accept Unicast wakeup frame */ | |
cecb5fd7 | 522 | Spi_en = (1 << 3), |
61a4dcc2 | 523 | LanWake = (1 << 1), /* LanWake enable/disable */ |
5d06a99f FR |
524 | PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */ |
525 | ||
1da177e4 LT |
526 | /* TBICSR p.28 */ |
527 | TBIReset = 0x80000000, | |
528 | TBILoopback = 0x40000000, | |
529 | TBINwEnable = 0x20000000, | |
530 | TBINwRestart = 0x10000000, | |
531 | TBILinkOk = 0x02000000, | |
532 | TBINwComplete = 0x01000000, | |
533 | ||
534 | /* CPlusCmd p.31 */ | |
f162a5d1 FR |
535 | EnableBist = (1 << 15), // 8168 8101 |
536 | Mac_dbgo_oe = (1 << 14), // 8168 8101 | |
537 | Normal_mode = (1 << 13), // unused | |
538 | Force_half_dup = (1 << 12), // 8168 8101 | |
539 | Force_rxflow_en = (1 << 11), // 8168 8101 | |
540 | Force_txflow_en = (1 << 10), // 8168 8101 | |
541 | Cxpl_dbg_sel = (1 << 9), // 8168 8101 | |
542 | ASF = (1 << 8), // 8168 8101 | |
543 | PktCntrDisable = (1 << 7), // 8168 8101 | |
544 | Mac_dbgo_sel = 0x001c, // 8168 | |
1da177e4 LT |
545 | RxVlan = (1 << 6), |
546 | RxChkSum = (1 << 5), | |
547 | PCIDAC = (1 << 4), | |
548 | PCIMulRW = (1 << 3), | |
0e485150 FR |
549 | INTT_0 = 0x0000, // 8168 |
550 | INTT_1 = 0x0001, // 8168 | |
551 | INTT_2 = 0x0002, // 8168 | |
552 | INTT_3 = 0x0003, // 8168 | |
1da177e4 LT |
553 | |
554 | /* rtl8169_PHYstatus */ | |
07d3f51f FR |
555 | TBI_Enable = 0x80, |
556 | TxFlowCtrl = 0x40, | |
557 | RxFlowCtrl = 0x20, | |
558 | _1000bpsF = 0x10, | |
559 | _100bps = 0x08, | |
560 | _10bps = 0x04, | |
561 | LinkStatus = 0x02, | |
562 | FullDup = 0x01, | |
1da177e4 | 563 | |
1da177e4 | 564 | /* _TBICSRBit */ |
07d3f51f | 565 | TBILinkOK = 0x02000000, |
d4a3a0fc SH |
566 | |
567 | /* DumpCounterCommand */ | |
07d3f51f | 568 | CounterDump = 0x8, |
1da177e4 LT |
569 | }; |
570 | ||
2b7b4318 FR |
571 | enum rtl_desc_bit { |
572 | /* First doubleword. */ | |
1da177e4 LT |
573 | DescOwn = (1 << 31), /* Descriptor is owned by NIC */ |
574 | RingEnd = (1 << 30), /* End of descriptor ring */ | |
575 | FirstFrag = (1 << 29), /* First segment of a packet */ | |
576 | LastFrag = (1 << 28), /* Final segment of a packet */ | |
2b7b4318 FR |
577 | }; |
578 | ||
579 | /* Generic case. */ | |
580 | enum rtl_tx_desc_bit { | |
581 | /* First doubleword. */ | |
582 | TD_LSO = (1 << 27), /* Large Send Offload */ | |
583 | #define TD_MSS_MAX 0x07ffu /* MSS value */ | |
1da177e4 | 584 | |
2b7b4318 FR |
585 | /* Second doubleword. */ |
586 | TxVlanTag = (1 << 17), /* Add VLAN tag */ | |
587 | }; | |
588 | ||
589 | /* 8169, 8168b and 810x except 8102e. */ | |
590 | enum rtl_tx_desc_bit_0 { | |
591 | /* First doubleword. */ | |
592 | #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */ | |
593 | TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */ | |
594 | TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */ | |
595 | TD0_IP_CS = (1 << 18), /* Calculate IP checksum */ | |
596 | }; | |
597 | ||
598 | /* 8102e, 8168c and beyond. */ | |
599 | enum rtl_tx_desc_bit_1 { | |
600 | /* Second doubleword. */ | |
601 | #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */ | |
602 | TD1_IP_CS = (1 << 29), /* Calculate IP checksum */ | |
603 | TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */ | |
604 | TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */ | |
605 | }; | |
1da177e4 | 606 | |
2b7b4318 FR |
607 | static const struct rtl_tx_desc_info { |
608 | struct { | |
609 | u32 udp; | |
610 | u32 tcp; | |
611 | } checksum; | |
612 | u16 mss_shift; | |
613 | u16 opts_offset; | |
614 | } tx_desc_info [] = { | |
615 | [RTL_TD_0] = { | |
616 | .checksum = { | |
617 | .udp = TD0_IP_CS | TD0_UDP_CS, | |
618 | .tcp = TD0_IP_CS | TD0_TCP_CS | |
619 | }, | |
620 | .mss_shift = TD0_MSS_SHIFT, | |
621 | .opts_offset = 0 | |
622 | }, | |
623 | [RTL_TD_1] = { | |
624 | .checksum = { | |
625 | .udp = TD1_IP_CS | TD1_UDP_CS, | |
626 | .tcp = TD1_IP_CS | TD1_TCP_CS | |
627 | }, | |
628 | .mss_shift = TD1_MSS_SHIFT, | |
629 | .opts_offset = 1 | |
630 | } | |
631 | }; | |
632 | ||
633 | enum rtl_rx_desc_bit { | |
1da177e4 LT |
634 | /* Rx private */ |
635 | PID1 = (1 << 18), /* Protocol ID bit 1/2 */ | |
636 | PID0 = (1 << 17), /* Protocol ID bit 2/2 */ | |
637 | ||
638 | #define RxProtoUDP (PID1) | |
639 | #define RxProtoTCP (PID0) | |
640 | #define RxProtoIP (PID1 | PID0) | |
641 | #define RxProtoMask RxProtoIP | |
642 | ||
643 | IPFail = (1 << 16), /* IP checksum failed */ | |
644 | UDPFail = (1 << 15), /* UDP/IP checksum failed */ | |
645 | TCPFail = (1 << 14), /* TCP/IP checksum failed */ | |
646 | RxVlanTag = (1 << 16), /* VLAN tag available */ | |
647 | }; | |
648 | ||
649 | #define RsvdMask 0x3fffc000 | |
650 | ||
651 | struct TxDesc { | |
6cccd6e7 REB |
652 | __le32 opts1; |
653 | __le32 opts2; | |
654 | __le64 addr; | |
1da177e4 LT |
655 | }; |
656 | ||
657 | struct RxDesc { | |
6cccd6e7 REB |
658 | __le32 opts1; |
659 | __le32 opts2; | |
660 | __le64 addr; | |
1da177e4 LT |
661 | }; |
662 | ||
663 | struct ring_info { | |
664 | struct sk_buff *skb; | |
665 | u32 len; | |
666 | u8 __pad[sizeof(void *) - sizeof(u32)]; | |
667 | }; | |
668 | ||
f23e7fda | 669 | enum features { |
ccdffb9a FR |
670 | RTL_FEATURE_WOL = (1 << 0), |
671 | RTL_FEATURE_MSI = (1 << 1), | |
672 | RTL_FEATURE_GMII = (1 << 2), | |
f23e7fda FR |
673 | }; |
674 | ||
355423d0 IV |
675 | struct rtl8169_counters { |
676 | __le64 tx_packets; | |
677 | __le64 rx_packets; | |
678 | __le64 tx_errors; | |
679 | __le32 rx_errors; | |
680 | __le16 rx_missed; | |
681 | __le16 align_errors; | |
682 | __le32 tx_one_collision; | |
683 | __le32 tx_multi_collision; | |
684 | __le64 rx_unicast; | |
685 | __le64 rx_broadcast; | |
686 | __le32 rx_multicast; | |
687 | __le16 tx_aborted; | |
688 | __le16 tx_underun; | |
689 | }; | |
690 | ||
da78dbff | 691 | enum rtl_flag { |
6c4a70c5 | 692 | RTL_FLAG_TASK_ENABLED, |
da78dbff FR |
693 | RTL_FLAG_TASK_SLOW_PENDING, |
694 | RTL_FLAG_TASK_RESET_PENDING, | |
695 | RTL_FLAG_TASK_PHY_PENDING, | |
696 | RTL_FLAG_MAX | |
697 | }; | |
698 | ||
8027aa24 JW |
699 | struct rtl8169_stats { |
700 | u64 packets; | |
701 | u64 bytes; | |
702 | struct u64_stats_sync syncp; | |
703 | }; | |
704 | ||
1da177e4 LT |
705 | struct rtl8169_private { |
706 | void __iomem *mmio_addr; /* memory map physical address */ | |
cecb5fd7 | 707 | struct pci_dev *pci_dev; |
c4028958 | 708 | struct net_device *dev; |
bea3348e | 709 | struct napi_struct napi; |
b57b7e5a | 710 | u32 msg_enable; |
2b7b4318 FR |
711 | u16 txd_version; |
712 | u16 mac_version; | |
1da177e4 LT |
713 | u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ |
714 | u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ | |
715 | u32 dirty_rx; | |
716 | u32 dirty_tx; | |
8027aa24 JW |
717 | struct rtl8169_stats rx_stats; |
718 | struct rtl8169_stats tx_stats; | |
1da177e4 LT |
719 | struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */ |
720 | struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */ | |
721 | dma_addr_t TxPhyAddr; | |
722 | dma_addr_t RxPhyAddr; | |
6f0333b8 | 723 | void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */ |
1da177e4 | 724 | struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */ |
1da177e4 LT |
725 | struct timer_list timer; |
726 | u16 cp_cmd; | |
da78dbff FR |
727 | |
728 | u16 event_slow; | |
c0e45c1c | 729 | |
730 | struct mdio_ops { | |
24192210 FR |
731 | void (*write)(struct rtl8169_private *, int, int); |
732 | int (*read)(struct rtl8169_private *, int); | |
c0e45c1c | 733 | } mdio_ops; |
734 | ||
065c27c1 | 735 | struct pll_power_ops { |
736 | void (*down)(struct rtl8169_private *); | |
737 | void (*up)(struct rtl8169_private *); | |
738 | } pll_power_ops; | |
739 | ||
d58d46b5 FR |
740 | struct jumbo_ops { |
741 | void (*enable)(struct rtl8169_private *); | |
742 | void (*disable)(struct rtl8169_private *); | |
743 | } jumbo_ops; | |
744 | ||
beb1fe18 | 745 | struct csi_ops { |
52989f0e FR |
746 | void (*write)(struct rtl8169_private *, int, int); |
747 | u32 (*read)(struct rtl8169_private *, int); | |
beb1fe18 HW |
748 | } csi_ops; |
749 | ||
54405cde | 750 | int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv); |
ccdffb9a | 751 | int (*get_settings)(struct net_device *, struct ethtool_cmd *); |
4da19633 | 752 | void (*phy_reset_enable)(struct rtl8169_private *tp); |
07ce4064 | 753 | void (*hw_start)(struct net_device *); |
4da19633 | 754 | unsigned int (*phy_reset_pending)(struct rtl8169_private *tp); |
1da177e4 | 755 | unsigned int (*link_ok)(void __iomem *); |
8b4ab28d | 756 | int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd); |
4422bcd4 FR |
757 | |
758 | struct { | |
da78dbff FR |
759 | DECLARE_BITMAP(flags, RTL_FLAG_MAX); |
760 | struct mutex mutex; | |
4422bcd4 FR |
761 | struct work_struct work; |
762 | } wk; | |
763 | ||
f23e7fda | 764 | unsigned features; |
ccdffb9a FR |
765 | |
766 | struct mii_if_info mii; | |
355423d0 | 767 | struct rtl8169_counters counters; |
e1759441 | 768 | u32 saved_wolopts; |
e03f33af | 769 | u32 opts1_mask; |
f1e02ed1 | 770 | |
b6ffd97f FR |
771 | struct rtl_fw { |
772 | const struct firmware *fw; | |
1c361efb FR |
773 | |
774 | #define RTL_VER_SIZE 32 | |
775 | ||
776 | char version[RTL_VER_SIZE]; | |
777 | ||
778 | struct rtl_fw_phy_action { | |
779 | __le32 *code; | |
780 | size_t size; | |
781 | } phy_action; | |
b6ffd97f | 782 | } *rtl_fw; |
497888cf | 783 | #define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN) |
1da177e4 LT |
784 | }; |
785 | ||
979b6c13 | 786 | MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>"); |
1da177e4 | 787 | MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver"); |
1da177e4 | 788 | module_param(use_dac, int, 0); |
4300e8c7 | 789 | MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot."); |
b57b7e5a SH |
790 | module_param_named(debug, debug.msg_enable, int, 0); |
791 | MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)"); | |
1da177e4 LT |
792 | MODULE_LICENSE("GPL"); |
793 | MODULE_VERSION(RTL8169_VERSION); | |
bca03d5f | 794 | MODULE_FIRMWARE(FIRMWARE_8168D_1); |
795 | MODULE_FIRMWARE(FIRMWARE_8168D_2); | |
01dc7fec | 796 | MODULE_FIRMWARE(FIRMWARE_8168E_1); |
797 | MODULE_FIRMWARE(FIRMWARE_8168E_2); | |
bbb8af75 | 798 | MODULE_FIRMWARE(FIRMWARE_8168E_3); |
5a5e4443 | 799 | MODULE_FIRMWARE(FIRMWARE_8105E_1); |
c2218925 HW |
800 | MODULE_FIRMWARE(FIRMWARE_8168F_1); |
801 | MODULE_FIRMWARE(FIRMWARE_8168F_2); | |
7e18dca1 | 802 | MODULE_FIRMWARE(FIRMWARE_8402_1); |
b3d7b2f2 | 803 | MODULE_FIRMWARE(FIRMWARE_8411_1); |
5598bfe5 | 804 | MODULE_FIRMWARE(FIRMWARE_8106E_1); |
1da177e4 | 805 | |
da78dbff FR |
806 | static void rtl_lock_work(struct rtl8169_private *tp) |
807 | { | |
808 | mutex_lock(&tp->wk.mutex); | |
809 | } | |
810 | ||
811 | static void rtl_unlock_work(struct rtl8169_private *tp) | |
812 | { | |
813 | mutex_unlock(&tp->wk.mutex); | |
814 | } | |
815 | ||
d58d46b5 FR |
816 | static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force) |
817 | { | |
818 | int cap = pci_pcie_cap(pdev); | |
819 | ||
820 | if (cap) { | |
821 | u16 ctl; | |
822 | ||
823 | pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl); | |
824 | ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force; | |
825 | pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl); | |
826 | } | |
827 | } | |
828 | ||
ffc46952 FR |
829 | struct rtl_cond { |
830 | bool (*check)(struct rtl8169_private *); | |
831 | const char *msg; | |
832 | }; | |
833 | ||
834 | static void rtl_udelay(unsigned int d) | |
835 | { | |
836 | udelay(d); | |
837 | } | |
838 | ||
839 | static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c, | |
840 | void (*delay)(unsigned int), unsigned int d, int n, | |
841 | bool high) | |
842 | { | |
843 | int i; | |
844 | ||
845 | for (i = 0; i < n; i++) { | |
846 | delay(d); | |
847 | if (c->check(tp) == high) | |
848 | return true; | |
849 | } | |
850 | netif_err(tp, drv, tp->dev, c->msg); | |
851 | return false; | |
852 | } | |
853 | ||
854 | static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp, | |
855 | const struct rtl_cond *c, | |
856 | unsigned int d, int n) | |
857 | { | |
858 | return rtl_loop_wait(tp, c, rtl_udelay, d, n, true); | |
859 | } | |
860 | ||
861 | static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp, | |
862 | const struct rtl_cond *c, | |
863 | unsigned int d, int n) | |
864 | { | |
865 | return rtl_loop_wait(tp, c, rtl_udelay, d, n, false); | |
866 | } | |
867 | ||
868 | static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp, | |
869 | const struct rtl_cond *c, | |
870 | unsigned int d, int n) | |
871 | { | |
872 | return rtl_loop_wait(tp, c, msleep, d, n, true); | |
873 | } | |
874 | ||
875 | static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp, | |
876 | const struct rtl_cond *c, | |
877 | unsigned int d, int n) | |
878 | { | |
879 | return rtl_loop_wait(tp, c, msleep, d, n, false); | |
880 | } | |
881 | ||
882 | #define DECLARE_RTL_COND(name) \ | |
883 | static bool name ## _check(struct rtl8169_private *); \ | |
884 | \ | |
885 | static const struct rtl_cond name = { \ | |
886 | .check = name ## _check, \ | |
887 | .msg = #name \ | |
888 | }; \ | |
889 | \ | |
890 | static bool name ## _check(struct rtl8169_private *tp) | |
891 | ||
892 | DECLARE_RTL_COND(rtl_ocpar_cond) | |
893 | { | |
894 | void __iomem *ioaddr = tp->mmio_addr; | |
895 | ||
896 | return RTL_R32(OCPAR) & OCPAR_FLAG; | |
897 | } | |
898 | ||
b646d900 | 899 | static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg) |
900 | { | |
901 | void __iomem *ioaddr = tp->mmio_addr; | |
b646d900 | 902 | |
903 | RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); | |
ffc46952 FR |
904 | |
905 | return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ? | |
906 | RTL_R32(OCPDR) : ~0; | |
b646d900 | 907 | } |
908 | ||
909 | static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data) | |
910 | { | |
911 | void __iomem *ioaddr = tp->mmio_addr; | |
b646d900 | 912 | |
913 | RTL_W32(OCPDR, data); | |
914 | RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); | |
ffc46952 FR |
915 | |
916 | rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20); | |
917 | } | |
918 | ||
919 | DECLARE_RTL_COND(rtl_eriar_cond) | |
920 | { | |
921 | void __iomem *ioaddr = tp->mmio_addr; | |
922 | ||
923 | return RTL_R32(ERIAR) & ERIAR_FLAG; | |
b646d900 | 924 | } |
925 | ||
fac5b3ca | 926 | static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd) |
b646d900 | 927 | { |
fac5b3ca | 928 | void __iomem *ioaddr = tp->mmio_addr; |
b646d900 | 929 | |
930 | RTL_W8(ERIDR, cmd); | |
931 | RTL_W32(ERIAR, 0x800010e8); | |
932 | msleep(2); | |
ffc46952 FR |
933 | |
934 | if (!rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 5)) | |
935 | return; | |
b646d900 | 936 | |
fac5b3ca | 937 | ocp_write(tp, 0x1, 0x30, 0x00000001); |
b646d900 | 938 | } |
939 | ||
940 | #define OOB_CMD_RESET 0x00 | |
941 | #define OOB_CMD_DRIVER_START 0x05 | |
942 | #define OOB_CMD_DRIVER_STOP 0x06 | |
943 | ||
cecb5fd7 FR |
944 | static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp) |
945 | { | |
946 | return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10; | |
947 | } | |
948 | ||
ffc46952 | 949 | DECLARE_RTL_COND(rtl_ocp_read_cond) |
b646d900 | 950 | { |
cecb5fd7 | 951 | u16 reg; |
b646d900 | 952 | |
cecb5fd7 | 953 | reg = rtl8168_get_ocp_reg(tp); |
4804b3b3 | 954 | |
ffc46952 | 955 | return ocp_read(tp, 0x0f, reg) & 0x00000800; |
b646d900 | 956 | } |
957 | ||
ffc46952 | 958 | static void rtl8168_driver_start(struct rtl8169_private *tp) |
b646d900 | 959 | { |
ffc46952 | 960 | rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START); |
b646d900 | 961 | |
ffc46952 FR |
962 | rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10); |
963 | } | |
b646d900 | 964 | |
ffc46952 FR |
965 | static void rtl8168_driver_stop(struct rtl8169_private *tp) |
966 | { | |
967 | rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP); | |
4804b3b3 | 968 | |
ffc46952 | 969 | rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10); |
b646d900 | 970 | } |
971 | ||
4804b3b3 | 972 | static int r8168dp_check_dash(struct rtl8169_private *tp) |
973 | { | |
cecb5fd7 | 974 | u16 reg = rtl8168_get_ocp_reg(tp); |
4804b3b3 | 975 | |
cecb5fd7 | 976 | return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0; |
4804b3b3 | 977 | } |
b646d900 | 978 | |
ffc46952 FR |
979 | DECLARE_RTL_COND(rtl_phyar_cond) |
980 | { | |
981 | void __iomem *ioaddr = tp->mmio_addr; | |
982 | ||
983 | return RTL_R32(PHYAR) & 0x80000000; | |
984 | } | |
985 | ||
24192210 | 986 | static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value) |
1da177e4 | 987 | { |
24192210 | 988 | void __iomem *ioaddr = tp->mmio_addr; |
1da177e4 | 989 | |
24192210 | 990 | RTL_W32(PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff)); |
1da177e4 | 991 | |
ffc46952 | 992 | rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20); |
024a07ba | 993 | /* |
81a95f04 TT |
994 | * According to hardware specs a 20us delay is required after write |
995 | * complete indication, but before sending next command. | |
024a07ba | 996 | */ |
81a95f04 | 997 | udelay(20); |
1da177e4 LT |
998 | } |
999 | ||
24192210 | 1000 | static int r8169_mdio_read(struct rtl8169_private *tp, int reg) |
1da177e4 | 1001 | { |
24192210 | 1002 | void __iomem *ioaddr = tp->mmio_addr; |
ffc46952 | 1003 | int value; |
1da177e4 | 1004 | |
24192210 | 1005 | RTL_W32(PHYAR, 0x0 | (reg & 0x1f) << 16); |
1da177e4 | 1006 | |
ffc46952 FR |
1007 | value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ? |
1008 | RTL_R32(PHYAR) & 0xffff : ~0; | |
1009 | ||
81a95f04 TT |
1010 | /* |
1011 | * According to hardware specs a 20us delay is required after read | |
1012 | * complete indication, but before sending next command. | |
1013 | */ | |
1014 | udelay(20); | |
1015 | ||
1da177e4 LT |
1016 | return value; |
1017 | } | |
1018 | ||
24192210 | 1019 | static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data) |
c0e45c1c | 1020 | { |
24192210 | 1021 | void __iomem *ioaddr = tp->mmio_addr; |
c0e45c1c | 1022 | |
24192210 | 1023 | RTL_W32(OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT)); |
c0e45c1c | 1024 | RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD); |
1025 | RTL_W32(EPHY_RXER_NUM, 0); | |
1026 | ||
ffc46952 | 1027 | rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100); |
c0e45c1c | 1028 | } |
1029 | ||
24192210 | 1030 | static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value) |
c0e45c1c | 1031 | { |
24192210 FR |
1032 | r8168dp_1_mdio_access(tp, reg, |
1033 | OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK)); | |
c0e45c1c | 1034 | } |
1035 | ||
24192210 | 1036 | static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg) |
c0e45c1c | 1037 | { |
24192210 | 1038 | void __iomem *ioaddr = tp->mmio_addr; |
c0e45c1c | 1039 | |
24192210 | 1040 | r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD); |
c0e45c1c | 1041 | |
1042 | mdelay(1); | |
1043 | RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD); | |
1044 | RTL_W32(EPHY_RXER_NUM, 0); | |
1045 | ||
ffc46952 FR |
1046 | return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ? |
1047 | RTL_R32(OCPDR) & OCPDR_DATA_MASK : ~0; | |
c0e45c1c | 1048 | } |
1049 | ||
e6de30d6 | 1050 | #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000 |
1051 | ||
1052 | static void r8168dp_2_mdio_start(void __iomem *ioaddr) | |
1053 | { | |
1054 | RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT); | |
1055 | } | |
1056 | ||
1057 | static void r8168dp_2_mdio_stop(void __iomem *ioaddr) | |
1058 | { | |
1059 | RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT); | |
1060 | } | |
1061 | ||
24192210 | 1062 | static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value) |
e6de30d6 | 1063 | { |
24192210 FR |
1064 | void __iomem *ioaddr = tp->mmio_addr; |
1065 | ||
e6de30d6 | 1066 | r8168dp_2_mdio_start(ioaddr); |
1067 | ||
24192210 | 1068 | r8169_mdio_write(tp, reg, value); |
e6de30d6 | 1069 | |
1070 | r8168dp_2_mdio_stop(ioaddr); | |
1071 | } | |
1072 | ||
24192210 | 1073 | static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg) |
e6de30d6 | 1074 | { |
24192210 | 1075 | void __iomem *ioaddr = tp->mmio_addr; |
e6de30d6 | 1076 | int value; |
1077 | ||
1078 | r8168dp_2_mdio_start(ioaddr); | |
1079 | ||
24192210 | 1080 | value = r8169_mdio_read(tp, reg); |
e6de30d6 | 1081 | |
1082 | r8168dp_2_mdio_stop(ioaddr); | |
1083 | ||
1084 | return value; | |
1085 | } | |
1086 | ||
4da19633 | 1087 | static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val) |
dacf8154 | 1088 | { |
24192210 | 1089 | tp->mdio_ops.write(tp, location, val); |
dacf8154 FR |
1090 | } |
1091 | ||
4da19633 | 1092 | static int rtl_readphy(struct rtl8169_private *tp, int location) |
1093 | { | |
24192210 | 1094 | return tp->mdio_ops.read(tp, location); |
4da19633 | 1095 | } |
1096 | ||
1097 | static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value) | |
1098 | { | |
1099 | rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value); | |
1100 | } | |
1101 | ||
1102 | static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m) | |
daf9df6d | 1103 | { |
1104 | int val; | |
1105 | ||
4da19633 | 1106 | val = rtl_readphy(tp, reg_addr); |
1107 | rtl_writephy(tp, reg_addr, (val | p) & ~m); | |
daf9df6d | 1108 | } |
1109 | ||
ccdffb9a FR |
1110 | static void rtl_mdio_write(struct net_device *dev, int phy_id, int location, |
1111 | int val) | |
1112 | { | |
1113 | struct rtl8169_private *tp = netdev_priv(dev); | |
ccdffb9a | 1114 | |
4da19633 | 1115 | rtl_writephy(tp, location, val); |
ccdffb9a FR |
1116 | } |
1117 | ||
1118 | static int rtl_mdio_read(struct net_device *dev, int phy_id, int location) | |
1119 | { | |
1120 | struct rtl8169_private *tp = netdev_priv(dev); | |
ccdffb9a | 1121 | |
4da19633 | 1122 | return rtl_readphy(tp, location); |
ccdffb9a FR |
1123 | } |
1124 | ||
ffc46952 FR |
1125 | DECLARE_RTL_COND(rtl_ephyar_cond) |
1126 | { | |
1127 | void __iomem *ioaddr = tp->mmio_addr; | |
1128 | ||
1129 | return RTL_R32(EPHYAR) & EPHYAR_FLAG; | |
1130 | } | |
1131 | ||
fdf6fc06 | 1132 | static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value) |
dacf8154 | 1133 | { |
fdf6fc06 | 1134 | void __iomem *ioaddr = tp->mmio_addr; |
dacf8154 FR |
1135 | |
1136 | RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) | | |
1137 | (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); | |
1138 | ||
ffc46952 FR |
1139 | rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100); |
1140 | ||
1141 | udelay(10); | |
dacf8154 FR |
1142 | } |
1143 | ||
fdf6fc06 | 1144 | static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr) |
dacf8154 | 1145 | { |
fdf6fc06 | 1146 | void __iomem *ioaddr = tp->mmio_addr; |
dacf8154 FR |
1147 | |
1148 | RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); | |
1149 | ||
ffc46952 FR |
1150 | return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ? |
1151 | RTL_R32(EPHYAR) & EPHYAR_DATA_MASK : ~0; | |
dacf8154 FR |
1152 | } |
1153 | ||
fdf6fc06 FR |
1154 | static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, |
1155 | u32 val, int type) | |
133ac40a | 1156 | { |
fdf6fc06 | 1157 | void __iomem *ioaddr = tp->mmio_addr; |
133ac40a HW |
1158 | |
1159 | BUG_ON((addr & 3) || (mask == 0)); | |
1160 | RTL_W32(ERIDR, val); | |
1161 | RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr); | |
1162 | ||
ffc46952 | 1163 | rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100); |
133ac40a HW |
1164 | } |
1165 | ||
fdf6fc06 | 1166 | static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type) |
133ac40a | 1167 | { |
fdf6fc06 | 1168 | void __iomem *ioaddr = tp->mmio_addr; |
133ac40a HW |
1169 | |
1170 | RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr); | |
1171 | ||
ffc46952 FR |
1172 | return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ? |
1173 | RTL_R32(ERIDR) : ~0; | |
133ac40a HW |
1174 | } |
1175 | ||
fdf6fc06 FR |
1176 | static void rtl_w1w0_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p, |
1177 | u32 m, int type) | |
133ac40a HW |
1178 | { |
1179 | u32 val; | |
1180 | ||
fdf6fc06 FR |
1181 | val = rtl_eri_read(tp, addr, type); |
1182 | rtl_eri_write(tp, addr, mask, (val & ~m) | p, type); | |
133ac40a HW |
1183 | } |
1184 | ||
c28aa385 | 1185 | struct exgmac_reg { |
1186 | u16 addr; | |
1187 | u16 mask; | |
1188 | u32 val; | |
1189 | }; | |
1190 | ||
fdf6fc06 | 1191 | static void rtl_write_exgmac_batch(struct rtl8169_private *tp, |
c28aa385 | 1192 | const struct exgmac_reg *r, int len) |
1193 | { | |
1194 | while (len-- > 0) { | |
fdf6fc06 | 1195 | rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC); |
c28aa385 | 1196 | r++; |
1197 | } | |
1198 | } | |
1199 | ||
ffc46952 FR |
1200 | DECLARE_RTL_COND(rtl_efusear_cond) |
1201 | { | |
1202 | void __iomem *ioaddr = tp->mmio_addr; | |
1203 | ||
1204 | return RTL_R32(EFUSEAR) & EFUSEAR_FLAG; | |
1205 | } | |
1206 | ||
fdf6fc06 | 1207 | static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr) |
daf9df6d | 1208 | { |
fdf6fc06 | 1209 | void __iomem *ioaddr = tp->mmio_addr; |
daf9df6d | 1210 | |
1211 | RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT); | |
1212 | ||
ffc46952 FR |
1213 | return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ? |
1214 | RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK : ~0; | |
daf9df6d | 1215 | } |
1216 | ||
9085cdfa FR |
1217 | static u16 rtl_get_events(struct rtl8169_private *tp) |
1218 | { | |
1219 | void __iomem *ioaddr = tp->mmio_addr; | |
1220 | ||
1221 | return RTL_R16(IntrStatus); | |
1222 | } | |
1223 | ||
1224 | static void rtl_ack_events(struct rtl8169_private *tp, u16 bits) | |
1225 | { | |
1226 | void __iomem *ioaddr = tp->mmio_addr; | |
1227 | ||
1228 | RTL_W16(IntrStatus, bits); | |
1229 | mmiowb(); | |
1230 | } | |
1231 | ||
1232 | static void rtl_irq_disable(struct rtl8169_private *tp) | |
1233 | { | |
1234 | void __iomem *ioaddr = tp->mmio_addr; | |
1235 | ||
1236 | RTL_W16(IntrMask, 0); | |
1237 | mmiowb(); | |
1238 | } | |
1239 | ||
3e990ff5 FR |
1240 | static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits) |
1241 | { | |
1242 | void __iomem *ioaddr = tp->mmio_addr; | |
1243 | ||
1244 | RTL_W16(IntrMask, bits); | |
1245 | } | |
1246 | ||
da78dbff FR |
1247 | #define RTL_EVENT_NAPI_RX (RxOK | RxErr) |
1248 | #define RTL_EVENT_NAPI_TX (TxOK | TxErr) | |
1249 | #define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX) | |
1250 | ||
1251 | static void rtl_irq_enable_all(struct rtl8169_private *tp) | |
1252 | { | |
1253 | rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow); | |
1254 | } | |
1255 | ||
811fd301 | 1256 | static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp) |
1da177e4 | 1257 | { |
811fd301 | 1258 | void __iomem *ioaddr = tp->mmio_addr; |
1da177e4 | 1259 | |
9085cdfa | 1260 | rtl_irq_disable(tp); |
da78dbff | 1261 | rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow); |
811fd301 | 1262 | RTL_R8(ChipCmd); |
1da177e4 LT |
1263 | } |
1264 | ||
4da19633 | 1265 | static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp) |
1da177e4 | 1266 | { |
4da19633 | 1267 | void __iomem *ioaddr = tp->mmio_addr; |
1268 | ||
1da177e4 LT |
1269 | return RTL_R32(TBICSR) & TBIReset; |
1270 | } | |
1271 | ||
4da19633 | 1272 | static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp) |
1da177e4 | 1273 | { |
4da19633 | 1274 | return rtl_readphy(tp, MII_BMCR) & BMCR_RESET; |
1da177e4 LT |
1275 | } |
1276 | ||
1277 | static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr) | |
1278 | { | |
1279 | return RTL_R32(TBICSR) & TBILinkOk; | |
1280 | } | |
1281 | ||
1282 | static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr) | |
1283 | { | |
1284 | return RTL_R8(PHYstatus) & LinkStatus; | |
1285 | } | |
1286 | ||
4da19633 | 1287 | static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp) |
1da177e4 | 1288 | { |
4da19633 | 1289 | void __iomem *ioaddr = tp->mmio_addr; |
1290 | ||
1da177e4 LT |
1291 | RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset); |
1292 | } | |
1293 | ||
4da19633 | 1294 | static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp) |
1da177e4 LT |
1295 | { |
1296 | unsigned int val; | |
1297 | ||
4da19633 | 1298 | val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET; |
1299 | rtl_writephy(tp, MII_BMCR, val & 0xffff); | |
1da177e4 LT |
1300 | } |
1301 | ||
70090424 HW |
1302 | static void rtl_link_chg_patch(struct rtl8169_private *tp) |
1303 | { | |
1304 | void __iomem *ioaddr = tp->mmio_addr; | |
1305 | struct net_device *dev = tp->dev; | |
1306 | ||
1307 | if (!netif_running(dev)) | |
1308 | return; | |
1309 | ||
b3d7b2f2 HW |
1310 | if (tp->mac_version == RTL_GIGA_MAC_VER_34 || |
1311 | tp->mac_version == RTL_GIGA_MAC_VER_38) { | |
70090424 | 1312 | if (RTL_R8(PHYstatus) & _1000bpsF) { |
fdf6fc06 FR |
1313 | rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011, |
1314 | ERIAR_EXGMAC); | |
1315 | rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005, | |
1316 | ERIAR_EXGMAC); | |
70090424 | 1317 | } else if (RTL_R8(PHYstatus) & _100bps) { |
fdf6fc06 FR |
1318 | rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f, |
1319 | ERIAR_EXGMAC); | |
1320 | rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005, | |
1321 | ERIAR_EXGMAC); | |
70090424 | 1322 | } else { |
fdf6fc06 FR |
1323 | rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f, |
1324 | ERIAR_EXGMAC); | |
1325 | rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f, | |
1326 | ERIAR_EXGMAC); | |
70090424 HW |
1327 | } |
1328 | /* Reset packet filter */ | |
fdf6fc06 | 1329 | rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, |
70090424 | 1330 | ERIAR_EXGMAC); |
fdf6fc06 | 1331 | rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, |
70090424 | 1332 | ERIAR_EXGMAC); |
c2218925 HW |
1333 | } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 || |
1334 | tp->mac_version == RTL_GIGA_MAC_VER_36) { | |
1335 | if (RTL_R8(PHYstatus) & _1000bpsF) { | |
fdf6fc06 FR |
1336 | rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011, |
1337 | ERIAR_EXGMAC); | |
1338 | rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005, | |
1339 | ERIAR_EXGMAC); | |
c2218925 | 1340 | } else { |
fdf6fc06 FR |
1341 | rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f, |
1342 | ERIAR_EXGMAC); | |
1343 | rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f, | |
1344 | ERIAR_EXGMAC); | |
c2218925 | 1345 | } |
7e18dca1 HW |
1346 | } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) { |
1347 | if (RTL_R8(PHYstatus) & _10bps) { | |
fdf6fc06 FR |
1348 | rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02, |
1349 | ERIAR_EXGMAC); | |
1350 | rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060, | |
1351 | ERIAR_EXGMAC); | |
7e18dca1 | 1352 | } else { |
fdf6fc06 FR |
1353 | rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, |
1354 | ERIAR_EXGMAC); | |
7e18dca1 | 1355 | } |
70090424 HW |
1356 | } |
1357 | } | |
1358 | ||
e4fbce74 | 1359 | static void __rtl8169_check_link_status(struct net_device *dev, |
cecb5fd7 FR |
1360 | struct rtl8169_private *tp, |
1361 | void __iomem *ioaddr, bool pm) | |
1da177e4 | 1362 | { |
1da177e4 | 1363 | if (tp->link_ok(ioaddr)) { |
70090424 | 1364 | rtl_link_chg_patch(tp); |
e1759441 | 1365 | /* This is to cancel a scheduled suspend if there's one. */ |
e4fbce74 RW |
1366 | if (pm) |
1367 | pm_request_resume(&tp->pci_dev->dev); | |
1da177e4 | 1368 | netif_carrier_on(dev); |
1519e57f FR |
1369 | if (net_ratelimit()) |
1370 | netif_info(tp, ifup, dev, "link up\n"); | |
b57b7e5a | 1371 | } else { |
1da177e4 | 1372 | netif_carrier_off(dev); |
bf82c189 | 1373 | netif_info(tp, ifdown, dev, "link down\n"); |
e4fbce74 | 1374 | if (pm) |
10953db8 | 1375 | pm_schedule_suspend(&tp->pci_dev->dev, 5000); |
b57b7e5a | 1376 | } |
1da177e4 LT |
1377 | } |
1378 | ||
e4fbce74 RW |
1379 | static void rtl8169_check_link_status(struct net_device *dev, |
1380 | struct rtl8169_private *tp, | |
1381 | void __iomem *ioaddr) | |
1382 | { | |
1383 | __rtl8169_check_link_status(dev, tp, ioaddr, false); | |
1384 | } | |
1385 | ||
e1759441 RW |
1386 | #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) |
1387 | ||
1388 | static u32 __rtl8169_get_wol(struct rtl8169_private *tp) | |
61a4dcc2 | 1389 | { |
61a4dcc2 FR |
1390 | void __iomem *ioaddr = tp->mmio_addr; |
1391 | u8 options; | |
e1759441 | 1392 | u32 wolopts = 0; |
61a4dcc2 FR |
1393 | |
1394 | options = RTL_R8(Config1); | |
1395 | if (!(options & PMEnable)) | |
e1759441 | 1396 | return 0; |
61a4dcc2 FR |
1397 | |
1398 | options = RTL_R8(Config3); | |
1399 | if (options & LinkUp) | |
e1759441 | 1400 | wolopts |= WAKE_PHY; |
61a4dcc2 | 1401 | if (options & MagicPacket) |
e1759441 | 1402 | wolopts |= WAKE_MAGIC; |
61a4dcc2 FR |
1403 | |
1404 | options = RTL_R8(Config5); | |
1405 | if (options & UWF) | |
e1759441 | 1406 | wolopts |= WAKE_UCAST; |
61a4dcc2 | 1407 | if (options & BWF) |
e1759441 | 1408 | wolopts |= WAKE_BCAST; |
61a4dcc2 | 1409 | if (options & MWF) |
e1759441 | 1410 | wolopts |= WAKE_MCAST; |
61a4dcc2 | 1411 | |
e1759441 | 1412 | return wolopts; |
61a4dcc2 FR |
1413 | } |
1414 | ||
e1759441 | 1415 | static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) |
61a4dcc2 FR |
1416 | { |
1417 | struct rtl8169_private *tp = netdev_priv(dev); | |
e1759441 | 1418 | |
da78dbff | 1419 | rtl_lock_work(tp); |
e1759441 RW |
1420 | |
1421 | wol->supported = WAKE_ANY; | |
1422 | wol->wolopts = __rtl8169_get_wol(tp); | |
1423 | ||
da78dbff | 1424 | rtl_unlock_work(tp); |
e1759441 RW |
1425 | } |
1426 | ||
1427 | static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts) | |
1428 | { | |
61a4dcc2 | 1429 | void __iomem *ioaddr = tp->mmio_addr; |
07d3f51f | 1430 | unsigned int i; |
350f7596 | 1431 | static const struct { |
61a4dcc2 FR |
1432 | u32 opt; |
1433 | u16 reg; | |
1434 | u8 mask; | |
1435 | } cfg[] = { | |
61a4dcc2 FR |
1436 | { WAKE_PHY, Config3, LinkUp }, |
1437 | { WAKE_MAGIC, Config3, MagicPacket }, | |
1438 | { WAKE_UCAST, Config5, UWF }, | |
1439 | { WAKE_BCAST, Config5, BWF }, | |
1440 | { WAKE_MCAST, Config5, MWF }, | |
1441 | { WAKE_ANY, Config5, LanWake } | |
1442 | }; | |
851e6022 | 1443 | u8 options; |
61a4dcc2 | 1444 | |
61a4dcc2 FR |
1445 | RTL_W8(Cfg9346, Cfg9346_Unlock); |
1446 | ||
1447 | for (i = 0; i < ARRAY_SIZE(cfg); i++) { | |
851e6022 | 1448 | options = RTL_R8(cfg[i].reg) & ~cfg[i].mask; |
e1759441 | 1449 | if (wolopts & cfg[i].opt) |
61a4dcc2 FR |
1450 | options |= cfg[i].mask; |
1451 | RTL_W8(cfg[i].reg, options); | |
1452 | } | |
1453 | ||
851e6022 FR |
1454 | switch (tp->mac_version) { |
1455 | case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17: | |
1456 | options = RTL_R8(Config1) & ~PMEnable; | |
1457 | if (wolopts) | |
1458 | options |= PMEnable; | |
1459 | RTL_W8(Config1, options); | |
1460 | break; | |
1461 | default: | |
d387b427 FR |
1462 | options = RTL_R8(Config2) & ~PME_SIGNAL; |
1463 | if (wolopts) | |
1464 | options |= PME_SIGNAL; | |
1465 | RTL_W8(Config2, options); | |
851e6022 FR |
1466 | break; |
1467 | } | |
1468 | ||
61a4dcc2 | 1469 | RTL_W8(Cfg9346, Cfg9346_Lock); |
e1759441 RW |
1470 | } |
1471 | ||
1472 | static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
1473 | { | |
1474 | struct rtl8169_private *tp = netdev_priv(dev); | |
1475 | ||
da78dbff | 1476 | rtl_lock_work(tp); |
61a4dcc2 | 1477 | |
f23e7fda FR |
1478 | if (wol->wolopts) |
1479 | tp->features |= RTL_FEATURE_WOL; | |
1480 | else | |
1481 | tp->features &= ~RTL_FEATURE_WOL; | |
e1759441 | 1482 | __rtl8169_set_wol(tp, wol->wolopts); |
da78dbff FR |
1483 | |
1484 | rtl_unlock_work(tp); | |
61a4dcc2 | 1485 | |
ea80907f | 1486 | device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts); |
1487 | ||
61a4dcc2 FR |
1488 | return 0; |
1489 | } | |
1490 | ||
31bd204f FR |
1491 | static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp) |
1492 | { | |
85bffe6c | 1493 | return rtl_chip_infos[tp->mac_version].fw_name; |
31bd204f FR |
1494 | } |
1495 | ||
1da177e4 LT |
1496 | static void rtl8169_get_drvinfo(struct net_device *dev, |
1497 | struct ethtool_drvinfo *info) | |
1498 | { | |
1499 | struct rtl8169_private *tp = netdev_priv(dev); | |
b6ffd97f | 1500 | struct rtl_fw *rtl_fw = tp->rtl_fw; |
1da177e4 | 1501 | |
68aad78c RJ |
1502 | strlcpy(info->driver, MODULENAME, sizeof(info->driver)); |
1503 | strlcpy(info->version, RTL8169_VERSION, sizeof(info->version)); | |
1504 | strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info)); | |
1c361efb | 1505 | BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version)); |
8ac72d16 RJ |
1506 | if (!IS_ERR_OR_NULL(rtl_fw)) |
1507 | strlcpy(info->fw_version, rtl_fw->version, | |
1508 | sizeof(info->fw_version)); | |
1da177e4 LT |
1509 | } |
1510 | ||
1511 | static int rtl8169_get_regs_len(struct net_device *dev) | |
1512 | { | |
1513 | return R8169_REGS_SIZE; | |
1514 | } | |
1515 | ||
1516 | static int rtl8169_set_speed_tbi(struct net_device *dev, | |
54405cde | 1517 | u8 autoneg, u16 speed, u8 duplex, u32 ignored) |
1da177e4 LT |
1518 | { |
1519 | struct rtl8169_private *tp = netdev_priv(dev); | |
1520 | void __iomem *ioaddr = tp->mmio_addr; | |
1521 | int ret = 0; | |
1522 | u32 reg; | |
1523 | ||
1524 | reg = RTL_R32(TBICSR); | |
1525 | if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) && | |
1526 | (duplex == DUPLEX_FULL)) { | |
1527 | RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart)); | |
1528 | } else if (autoneg == AUTONEG_ENABLE) | |
1529 | RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart); | |
1530 | else { | |
bf82c189 JP |
1531 | netif_warn(tp, link, dev, |
1532 | "incorrect speed setting refused in TBI mode\n"); | |
1da177e4 LT |
1533 | ret = -EOPNOTSUPP; |
1534 | } | |
1535 | ||
1536 | return ret; | |
1537 | } | |
1538 | ||
1539 | static int rtl8169_set_speed_xmii(struct net_device *dev, | |
54405cde | 1540 | u8 autoneg, u16 speed, u8 duplex, u32 adv) |
1da177e4 LT |
1541 | { |
1542 | struct rtl8169_private *tp = netdev_priv(dev); | |
3577aa1b | 1543 | int giga_ctrl, bmcr; |
54405cde | 1544 | int rc = -EINVAL; |
1da177e4 | 1545 | |
716b50a3 | 1546 | rtl_writephy(tp, 0x1f, 0x0000); |
1da177e4 LT |
1547 | |
1548 | if (autoneg == AUTONEG_ENABLE) { | |
3577aa1b | 1549 | int auto_nego; |
1550 | ||
4da19633 | 1551 | auto_nego = rtl_readphy(tp, MII_ADVERTISE); |
54405cde ON |
1552 | auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL | |
1553 | ADVERTISE_100HALF | ADVERTISE_100FULL); | |
1554 | ||
1555 | if (adv & ADVERTISED_10baseT_Half) | |
1556 | auto_nego |= ADVERTISE_10HALF; | |
1557 | if (adv & ADVERTISED_10baseT_Full) | |
1558 | auto_nego |= ADVERTISE_10FULL; | |
1559 | if (adv & ADVERTISED_100baseT_Half) | |
1560 | auto_nego |= ADVERTISE_100HALF; | |
1561 | if (adv & ADVERTISED_100baseT_Full) | |
1562 | auto_nego |= ADVERTISE_100FULL; | |
1563 | ||
3577aa1b | 1564 | auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; |
1da177e4 | 1565 | |
4da19633 | 1566 | giga_ctrl = rtl_readphy(tp, MII_CTRL1000); |
3577aa1b | 1567 | giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF); |
bcf0bf90 | 1568 | |
3577aa1b | 1569 | /* The 8100e/8101e/8102e do Fast Ethernet only. */ |
826e6cbd | 1570 | if (tp->mii.supports_gmii) { |
54405cde ON |
1571 | if (adv & ADVERTISED_1000baseT_Half) |
1572 | giga_ctrl |= ADVERTISE_1000HALF; | |
1573 | if (adv & ADVERTISED_1000baseT_Full) | |
1574 | giga_ctrl |= ADVERTISE_1000FULL; | |
1575 | } else if (adv & (ADVERTISED_1000baseT_Half | | |
1576 | ADVERTISED_1000baseT_Full)) { | |
bf82c189 JP |
1577 | netif_info(tp, link, dev, |
1578 | "PHY does not support 1000Mbps\n"); | |
54405cde | 1579 | goto out; |
bcf0bf90 | 1580 | } |
1da177e4 | 1581 | |
3577aa1b | 1582 | bmcr = BMCR_ANENABLE | BMCR_ANRESTART; |
1583 | ||
4da19633 | 1584 | rtl_writephy(tp, MII_ADVERTISE, auto_nego); |
1585 | rtl_writephy(tp, MII_CTRL1000, giga_ctrl); | |
3577aa1b | 1586 | } else { |
1587 | giga_ctrl = 0; | |
1588 | ||
1589 | if (speed == SPEED_10) | |
1590 | bmcr = 0; | |
1591 | else if (speed == SPEED_100) | |
1592 | bmcr = BMCR_SPEED100; | |
1593 | else | |
54405cde | 1594 | goto out; |
3577aa1b | 1595 | |
1596 | if (duplex == DUPLEX_FULL) | |
1597 | bmcr |= BMCR_FULLDPLX; | |
2584fbc3 RS |
1598 | } |
1599 | ||
4da19633 | 1600 | rtl_writephy(tp, MII_BMCR, bmcr); |
3577aa1b | 1601 | |
cecb5fd7 FR |
1602 | if (tp->mac_version == RTL_GIGA_MAC_VER_02 || |
1603 | tp->mac_version == RTL_GIGA_MAC_VER_03) { | |
3577aa1b | 1604 | if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) { |
4da19633 | 1605 | rtl_writephy(tp, 0x17, 0x2138); |
1606 | rtl_writephy(tp, 0x0e, 0x0260); | |
3577aa1b | 1607 | } else { |
4da19633 | 1608 | rtl_writephy(tp, 0x17, 0x2108); |
1609 | rtl_writephy(tp, 0x0e, 0x0000); | |
3577aa1b | 1610 | } |
1611 | } | |
1612 | ||
54405cde ON |
1613 | rc = 0; |
1614 | out: | |
1615 | return rc; | |
1da177e4 LT |
1616 | } |
1617 | ||
1618 | static int rtl8169_set_speed(struct net_device *dev, | |
54405cde | 1619 | u8 autoneg, u16 speed, u8 duplex, u32 advertising) |
1da177e4 LT |
1620 | { |
1621 | struct rtl8169_private *tp = netdev_priv(dev); | |
1622 | int ret; | |
1623 | ||
54405cde | 1624 | ret = tp->set_speed(dev, autoneg, speed, duplex, advertising); |
4876cc1e FR |
1625 | if (ret < 0) |
1626 | goto out; | |
1da177e4 | 1627 | |
4876cc1e FR |
1628 | if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) && |
1629 | (advertising & ADVERTISED_1000baseT_Full)) { | |
1da177e4 | 1630 | mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT); |
4876cc1e FR |
1631 | } |
1632 | out: | |
1da177e4 LT |
1633 | return ret; |
1634 | } | |
1635 | ||
1636 | static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
1637 | { | |
1638 | struct rtl8169_private *tp = netdev_priv(dev); | |
1da177e4 LT |
1639 | int ret; |
1640 | ||
4876cc1e FR |
1641 | del_timer_sync(&tp->timer); |
1642 | ||
da78dbff | 1643 | rtl_lock_work(tp); |
cecb5fd7 | 1644 | ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd), |
25db0338 | 1645 | cmd->duplex, cmd->advertising); |
da78dbff | 1646 | rtl_unlock_work(tp); |
5b0384f4 | 1647 | |
1da177e4 LT |
1648 | return ret; |
1649 | } | |
1650 | ||
c8f44aff MM |
1651 | static netdev_features_t rtl8169_fix_features(struct net_device *dev, |
1652 | netdev_features_t features) | |
1da177e4 | 1653 | { |
d58d46b5 FR |
1654 | struct rtl8169_private *tp = netdev_priv(dev); |
1655 | ||
2b7b4318 | 1656 | if (dev->mtu > TD_MSS_MAX) |
350fb32a | 1657 | features &= ~NETIF_F_ALL_TSO; |
1da177e4 | 1658 | |
d58d46b5 FR |
1659 | if (dev->mtu > JUMBO_1K && |
1660 | !rtl_chip_infos[tp->mac_version].jumbo_tx_csum) | |
1661 | features &= ~NETIF_F_IP_CSUM; | |
1662 | ||
350fb32a | 1663 | return features; |
1da177e4 LT |
1664 | } |
1665 | ||
da78dbff FR |
1666 | static void __rtl8169_set_features(struct net_device *dev, |
1667 | netdev_features_t features) | |
1da177e4 LT |
1668 | { |
1669 | struct rtl8169_private *tp = netdev_priv(dev); | |
6bbe021d | 1670 | netdev_features_t changed = features ^ dev->features; |
da78dbff | 1671 | void __iomem *ioaddr = tp->mmio_addr; |
1da177e4 | 1672 | |
6bbe021d BG |
1673 | if (!(changed & (NETIF_F_RXALL | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX))) |
1674 | return; | |
1da177e4 | 1675 | |
6bbe021d BG |
1676 | if (changed & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX)) { |
1677 | if (features & NETIF_F_RXCSUM) | |
1678 | tp->cp_cmd |= RxChkSum; | |
1679 | else | |
1680 | tp->cp_cmd &= ~RxChkSum; | |
350fb32a | 1681 | |
6bbe021d BG |
1682 | if (dev->features & NETIF_F_HW_VLAN_RX) |
1683 | tp->cp_cmd |= RxVlan; | |
1684 | else | |
1685 | tp->cp_cmd &= ~RxVlan; | |
1686 | ||
1687 | RTL_W16(CPlusCmd, tp->cp_cmd); | |
1688 | RTL_R16(CPlusCmd); | |
1689 | } | |
1690 | if (changed & NETIF_F_RXALL) { | |
1691 | int tmp = (RTL_R32(RxConfig) & ~(AcceptErr | AcceptRunt)); | |
1692 | if (features & NETIF_F_RXALL) | |
1693 | tmp |= (AcceptErr | AcceptRunt); | |
1694 | RTL_W32(RxConfig, tmp); | |
1695 | } | |
da78dbff | 1696 | } |
1da177e4 | 1697 | |
da78dbff FR |
1698 | static int rtl8169_set_features(struct net_device *dev, |
1699 | netdev_features_t features) | |
1700 | { | |
1701 | struct rtl8169_private *tp = netdev_priv(dev); | |
1702 | ||
1703 | rtl_lock_work(tp); | |
1704 | __rtl8169_set_features(dev, features); | |
1705 | rtl_unlock_work(tp); | |
1da177e4 LT |
1706 | |
1707 | return 0; | |
1708 | } | |
1709 | ||
da78dbff | 1710 | |
1da177e4 LT |
1711 | static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp, |
1712 | struct sk_buff *skb) | |
1713 | { | |
eab6d18d | 1714 | return (vlan_tx_tag_present(skb)) ? |
1da177e4 LT |
1715 | TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00; |
1716 | } | |
1717 | ||
7a8fc77b | 1718 | static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb) |
1da177e4 LT |
1719 | { |
1720 | u32 opts2 = le32_to_cpu(desc->opts2); | |
1da177e4 | 1721 | |
7a8fc77b FR |
1722 | if (opts2 & RxVlanTag) |
1723 | __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff)); | |
2edae08e | 1724 | |
1da177e4 | 1725 | desc->opts2 = 0; |
1da177e4 LT |
1726 | } |
1727 | ||
ccdffb9a | 1728 | static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd) |
1da177e4 LT |
1729 | { |
1730 | struct rtl8169_private *tp = netdev_priv(dev); | |
1731 | void __iomem *ioaddr = tp->mmio_addr; | |
1732 | u32 status; | |
1733 | ||
1734 | cmd->supported = | |
1735 | SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE; | |
1736 | cmd->port = PORT_FIBRE; | |
1737 | cmd->transceiver = XCVR_INTERNAL; | |
1738 | ||
1739 | status = RTL_R32(TBICSR); | |
1740 | cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0; | |
1741 | cmd->autoneg = !!(status & TBINwEnable); | |
1742 | ||
70739497 | 1743 | ethtool_cmd_speed_set(cmd, SPEED_1000); |
1da177e4 | 1744 | cmd->duplex = DUPLEX_FULL; /* Always set */ |
ccdffb9a FR |
1745 | |
1746 | return 0; | |
1da177e4 LT |
1747 | } |
1748 | ||
ccdffb9a | 1749 | static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd) |
1da177e4 LT |
1750 | { |
1751 | struct rtl8169_private *tp = netdev_priv(dev); | |
ccdffb9a FR |
1752 | |
1753 | return mii_ethtool_gset(&tp->mii, cmd); | |
1da177e4 LT |
1754 | } |
1755 | ||
1756 | static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
1757 | { | |
1758 | struct rtl8169_private *tp = netdev_priv(dev); | |
ccdffb9a | 1759 | int rc; |
1da177e4 | 1760 | |
da78dbff | 1761 | rtl_lock_work(tp); |
ccdffb9a | 1762 | rc = tp->get_settings(dev, cmd); |
da78dbff | 1763 | rtl_unlock_work(tp); |
1da177e4 | 1764 | |
ccdffb9a | 1765 | return rc; |
1da177e4 LT |
1766 | } |
1767 | ||
1768 | static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs, | |
1769 | void *p) | |
1770 | { | |
5b0384f4 | 1771 | struct rtl8169_private *tp = netdev_priv(dev); |
1da177e4 | 1772 | |
5b0384f4 FR |
1773 | if (regs->len > R8169_REGS_SIZE) |
1774 | regs->len = R8169_REGS_SIZE; | |
1da177e4 | 1775 | |
da78dbff | 1776 | rtl_lock_work(tp); |
5b0384f4 | 1777 | memcpy_fromio(p, tp->mmio_addr, regs->len); |
da78dbff | 1778 | rtl_unlock_work(tp); |
1da177e4 LT |
1779 | } |
1780 | ||
b57b7e5a SH |
1781 | static u32 rtl8169_get_msglevel(struct net_device *dev) |
1782 | { | |
1783 | struct rtl8169_private *tp = netdev_priv(dev); | |
1784 | ||
1785 | return tp->msg_enable; | |
1786 | } | |
1787 | ||
1788 | static void rtl8169_set_msglevel(struct net_device *dev, u32 value) | |
1789 | { | |
1790 | struct rtl8169_private *tp = netdev_priv(dev); | |
1791 | ||
1792 | tp->msg_enable = value; | |
1793 | } | |
1794 | ||
d4a3a0fc SH |
1795 | static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = { |
1796 | "tx_packets", | |
1797 | "rx_packets", | |
1798 | "tx_errors", | |
1799 | "rx_errors", | |
1800 | "rx_missed", | |
1801 | "align_errors", | |
1802 | "tx_single_collisions", | |
1803 | "tx_multi_collisions", | |
1804 | "unicast", | |
1805 | "broadcast", | |
1806 | "multicast", | |
1807 | "tx_aborted", | |
1808 | "tx_underrun", | |
1809 | }; | |
1810 | ||
b9f2c044 | 1811 | static int rtl8169_get_sset_count(struct net_device *dev, int sset) |
d4a3a0fc | 1812 | { |
b9f2c044 JG |
1813 | switch (sset) { |
1814 | case ETH_SS_STATS: | |
1815 | return ARRAY_SIZE(rtl8169_gstrings); | |
1816 | default: | |
1817 | return -EOPNOTSUPP; | |
1818 | } | |
d4a3a0fc SH |
1819 | } |
1820 | ||
ffc46952 FR |
1821 | DECLARE_RTL_COND(rtl_counters_cond) |
1822 | { | |
1823 | void __iomem *ioaddr = tp->mmio_addr; | |
1824 | ||
1825 | return RTL_R32(CounterAddrLow) & CounterDump; | |
1826 | } | |
1827 | ||
355423d0 | 1828 | static void rtl8169_update_counters(struct net_device *dev) |
d4a3a0fc SH |
1829 | { |
1830 | struct rtl8169_private *tp = netdev_priv(dev); | |
1831 | void __iomem *ioaddr = tp->mmio_addr; | |
cecb5fd7 | 1832 | struct device *d = &tp->pci_dev->dev; |
d4a3a0fc SH |
1833 | struct rtl8169_counters *counters; |
1834 | dma_addr_t paddr; | |
1835 | u32 cmd; | |
1836 | ||
355423d0 IV |
1837 | /* |
1838 | * Some chips are unable to dump tally counters when the receiver | |
1839 | * is disabled. | |
1840 | */ | |
1841 | if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0) | |
1842 | return; | |
d4a3a0fc | 1843 | |
48addcc9 | 1844 | counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL); |
d4a3a0fc SH |
1845 | if (!counters) |
1846 | return; | |
1847 | ||
1848 | RTL_W32(CounterAddrHigh, (u64)paddr >> 32); | |
284901a9 | 1849 | cmd = (u64)paddr & DMA_BIT_MASK(32); |
d4a3a0fc SH |
1850 | RTL_W32(CounterAddrLow, cmd); |
1851 | RTL_W32(CounterAddrLow, cmd | CounterDump); | |
1852 | ||
ffc46952 FR |
1853 | if (rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000)) |
1854 | memcpy(&tp->counters, counters, sizeof(*counters)); | |
d4a3a0fc SH |
1855 | |
1856 | RTL_W32(CounterAddrLow, 0); | |
1857 | RTL_W32(CounterAddrHigh, 0); | |
1858 | ||
48addcc9 | 1859 | dma_free_coherent(d, sizeof(*counters), counters, paddr); |
d4a3a0fc SH |
1860 | } |
1861 | ||
355423d0 IV |
1862 | static void rtl8169_get_ethtool_stats(struct net_device *dev, |
1863 | struct ethtool_stats *stats, u64 *data) | |
1864 | { | |
1865 | struct rtl8169_private *tp = netdev_priv(dev); | |
1866 | ||
1867 | ASSERT_RTNL(); | |
1868 | ||
1869 | rtl8169_update_counters(dev); | |
1870 | ||
1871 | data[0] = le64_to_cpu(tp->counters.tx_packets); | |
1872 | data[1] = le64_to_cpu(tp->counters.rx_packets); | |
1873 | data[2] = le64_to_cpu(tp->counters.tx_errors); | |
1874 | data[3] = le32_to_cpu(tp->counters.rx_errors); | |
1875 | data[4] = le16_to_cpu(tp->counters.rx_missed); | |
1876 | data[5] = le16_to_cpu(tp->counters.align_errors); | |
1877 | data[6] = le32_to_cpu(tp->counters.tx_one_collision); | |
1878 | data[7] = le32_to_cpu(tp->counters.tx_multi_collision); | |
1879 | data[8] = le64_to_cpu(tp->counters.rx_unicast); | |
1880 | data[9] = le64_to_cpu(tp->counters.rx_broadcast); | |
1881 | data[10] = le32_to_cpu(tp->counters.rx_multicast); | |
1882 | data[11] = le16_to_cpu(tp->counters.tx_aborted); | |
1883 | data[12] = le16_to_cpu(tp->counters.tx_underun); | |
1884 | } | |
1885 | ||
d4a3a0fc SH |
1886 | static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data) |
1887 | { | |
1888 | switch(stringset) { | |
1889 | case ETH_SS_STATS: | |
1890 | memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings)); | |
1891 | break; | |
1892 | } | |
1893 | } | |
1894 | ||
7282d491 | 1895 | static const struct ethtool_ops rtl8169_ethtool_ops = { |
1da177e4 LT |
1896 | .get_drvinfo = rtl8169_get_drvinfo, |
1897 | .get_regs_len = rtl8169_get_regs_len, | |
1898 | .get_link = ethtool_op_get_link, | |
1899 | .get_settings = rtl8169_get_settings, | |
1900 | .set_settings = rtl8169_set_settings, | |
b57b7e5a SH |
1901 | .get_msglevel = rtl8169_get_msglevel, |
1902 | .set_msglevel = rtl8169_set_msglevel, | |
1da177e4 | 1903 | .get_regs = rtl8169_get_regs, |
61a4dcc2 FR |
1904 | .get_wol = rtl8169_get_wol, |
1905 | .set_wol = rtl8169_set_wol, | |
d4a3a0fc | 1906 | .get_strings = rtl8169_get_strings, |
b9f2c044 | 1907 | .get_sset_count = rtl8169_get_sset_count, |
d4a3a0fc | 1908 | .get_ethtool_stats = rtl8169_get_ethtool_stats, |
e1593bb1 | 1909 | .get_ts_info = ethtool_op_get_ts_info, |
1da177e4 LT |
1910 | }; |
1911 | ||
07d3f51f | 1912 | static void rtl8169_get_mac_version(struct rtl8169_private *tp, |
5d320a20 | 1913 | struct net_device *dev, u8 default_version) |
1da177e4 | 1914 | { |
5d320a20 | 1915 | void __iomem *ioaddr = tp->mmio_addr; |
0e485150 FR |
1916 | /* |
1917 | * The driver currently handles the 8168Bf and the 8168Be identically | |
1918 | * but they can be identified more specifically through the test below | |
1919 | * if needed: | |
1920 | * | |
1921 | * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be | |
0127215c FR |
1922 | * |
1923 | * Same thing for the 8101Eb and the 8101Ec: | |
1924 | * | |
1925 | * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec | |
0e485150 | 1926 | */ |
3744100e | 1927 | static const struct rtl_mac_info { |
1da177e4 | 1928 | u32 mask; |
e3cf0cc0 | 1929 | u32 val; |
1da177e4 LT |
1930 | int mac_version; |
1931 | } mac_info[] = { | |
c2218925 | 1932 | /* 8168F family. */ |
b3d7b2f2 | 1933 | { 0x7c800000, 0x48800000, RTL_GIGA_MAC_VER_38 }, |
c2218925 HW |
1934 | { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36 }, |
1935 | { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35 }, | |
1936 | ||
01dc7fec | 1937 | /* 8168E family. */ |
70090424 | 1938 | { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 }, |
01dc7fec | 1939 | { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 }, |
1940 | { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 }, | |
1941 | { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 }, | |
1942 | ||
5b538df9 | 1943 | /* 8168D family. */ |
daf9df6d | 1944 | { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 }, |
1945 | { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 }, | |
daf9df6d | 1946 | { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 }, |
5b538df9 | 1947 | |
e6de30d6 | 1948 | /* 8168DP family. */ |
1949 | { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 }, | |
1950 | { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 }, | |
4804b3b3 | 1951 | { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 }, |
e6de30d6 | 1952 | |
ef808d50 | 1953 | /* 8168C family. */ |
17c99297 | 1954 | { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 }, |
ef3386f0 | 1955 | { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 }, |
ef808d50 | 1956 | { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 }, |
7f3e3d3a | 1957 | { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 }, |
e3cf0cc0 FR |
1958 | { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 }, |
1959 | { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 }, | |
197ff761 | 1960 | { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 }, |
6fb07058 | 1961 | { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 }, |
ef808d50 | 1962 | { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 }, |
e3cf0cc0 FR |
1963 | |
1964 | /* 8168B family. */ | |
1965 | { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 }, | |
1966 | { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 }, | |
1967 | { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 }, | |
1968 | { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 }, | |
1969 | ||
1970 | /* 8101 family. */ | |
5598bfe5 HW |
1971 | { 0x7cf00000, 0x44900000, RTL_GIGA_MAC_VER_39 }, |
1972 | { 0x7c800000, 0x44800000, RTL_GIGA_MAC_VER_39 }, | |
7e18dca1 | 1973 | { 0x7c800000, 0x44000000, RTL_GIGA_MAC_VER_37 }, |
36a0e6c2 | 1974 | { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 }, |
5a5e4443 HW |
1975 | { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 }, |
1976 | { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 }, | |
1977 | { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 }, | |
2857ffb7 FR |
1978 | { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 }, |
1979 | { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 }, | |
1980 | { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 }, | |
1981 | { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 }, | |
1982 | { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 }, | |
1983 | { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 }, | |
e3cf0cc0 | 1984 | { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 }, |
2857ffb7 | 1985 | { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 }, |
e3cf0cc0 | 1986 | { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 }, |
2857ffb7 FR |
1987 | { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 }, |
1988 | { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 }, | |
e3cf0cc0 FR |
1989 | { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 }, |
1990 | /* FIXME: where did these entries come from ? -- FR */ | |
1991 | { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 }, | |
1992 | { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 }, | |
1993 | ||
1994 | /* 8110 family. */ | |
1995 | { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 }, | |
1996 | { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 }, | |
1997 | { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 }, | |
1998 | { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 }, | |
1999 | { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 }, | |
2000 | { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 }, | |
2001 | ||
f21b75e9 JD |
2002 | /* Catch-all */ |
2003 | { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE } | |
3744100e FR |
2004 | }; |
2005 | const struct rtl_mac_info *p = mac_info; | |
1da177e4 LT |
2006 | u32 reg; |
2007 | ||
e3cf0cc0 FR |
2008 | reg = RTL_R32(TxConfig); |
2009 | while ((reg & p->mask) != p->val) | |
1da177e4 LT |
2010 | p++; |
2011 | tp->mac_version = p->mac_version; | |
5d320a20 FR |
2012 | |
2013 | if (tp->mac_version == RTL_GIGA_MAC_NONE) { | |
2014 | netif_notice(tp, probe, dev, | |
2015 | "unknown MAC, using family default\n"); | |
2016 | tp->mac_version = default_version; | |
2017 | } | |
1da177e4 LT |
2018 | } |
2019 | ||
2020 | static void rtl8169_print_mac_version(struct rtl8169_private *tp) | |
2021 | { | |
bcf0bf90 | 2022 | dprintk("mac_version = 0x%02x\n", tp->mac_version); |
1da177e4 LT |
2023 | } |
2024 | ||
867763c1 FR |
2025 | struct phy_reg { |
2026 | u16 reg; | |
2027 | u16 val; | |
2028 | }; | |
2029 | ||
4da19633 | 2030 | static void rtl_writephy_batch(struct rtl8169_private *tp, |
2031 | const struct phy_reg *regs, int len) | |
867763c1 FR |
2032 | { |
2033 | while (len-- > 0) { | |
4da19633 | 2034 | rtl_writephy(tp, regs->reg, regs->val); |
867763c1 FR |
2035 | regs++; |
2036 | } | |
2037 | } | |
2038 | ||
bca03d5f | 2039 | #define PHY_READ 0x00000000 |
2040 | #define PHY_DATA_OR 0x10000000 | |
2041 | #define PHY_DATA_AND 0x20000000 | |
2042 | #define PHY_BJMPN 0x30000000 | |
2043 | #define PHY_READ_EFUSE 0x40000000 | |
2044 | #define PHY_READ_MAC_BYTE 0x50000000 | |
2045 | #define PHY_WRITE_MAC_BYTE 0x60000000 | |
2046 | #define PHY_CLEAR_READCOUNT 0x70000000 | |
2047 | #define PHY_WRITE 0x80000000 | |
2048 | #define PHY_READCOUNT_EQ_SKIP 0x90000000 | |
2049 | #define PHY_COMP_EQ_SKIPN 0xa0000000 | |
2050 | #define PHY_COMP_NEQ_SKIPN 0xb0000000 | |
2051 | #define PHY_WRITE_PREVIOUS 0xc0000000 | |
2052 | #define PHY_SKIPN 0xd0000000 | |
2053 | #define PHY_DELAY_MS 0xe0000000 | |
2054 | #define PHY_WRITE_ERI_WORD 0xf0000000 | |
2055 | ||
960aee6c HW |
2056 | struct fw_info { |
2057 | u32 magic; | |
2058 | char version[RTL_VER_SIZE]; | |
2059 | __le32 fw_start; | |
2060 | __le32 fw_len; | |
2061 | u8 chksum; | |
2062 | } __packed; | |
2063 | ||
1c361efb FR |
2064 | #define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code)) |
2065 | ||
2066 | static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw) | |
bca03d5f | 2067 | { |
b6ffd97f | 2068 | const struct firmware *fw = rtl_fw->fw; |
960aee6c | 2069 | struct fw_info *fw_info = (struct fw_info *)fw->data; |
1c361efb FR |
2070 | struct rtl_fw_phy_action *pa = &rtl_fw->phy_action; |
2071 | char *version = rtl_fw->version; | |
2072 | bool rc = false; | |
2073 | ||
2074 | if (fw->size < FW_OPCODE_SIZE) | |
2075 | goto out; | |
960aee6c HW |
2076 | |
2077 | if (!fw_info->magic) { | |
2078 | size_t i, size, start; | |
2079 | u8 checksum = 0; | |
2080 | ||
2081 | if (fw->size < sizeof(*fw_info)) | |
2082 | goto out; | |
2083 | ||
2084 | for (i = 0; i < fw->size; i++) | |
2085 | checksum += fw->data[i]; | |
2086 | if (checksum != 0) | |
2087 | goto out; | |
2088 | ||
2089 | start = le32_to_cpu(fw_info->fw_start); | |
2090 | if (start > fw->size) | |
2091 | goto out; | |
2092 | ||
2093 | size = le32_to_cpu(fw_info->fw_len); | |
2094 | if (size > (fw->size - start) / FW_OPCODE_SIZE) | |
2095 | goto out; | |
2096 | ||
2097 | memcpy(version, fw_info->version, RTL_VER_SIZE); | |
2098 | ||
2099 | pa->code = (__le32 *)(fw->data + start); | |
2100 | pa->size = size; | |
2101 | } else { | |
1c361efb FR |
2102 | if (fw->size % FW_OPCODE_SIZE) |
2103 | goto out; | |
2104 | ||
2105 | strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE); | |
2106 | ||
2107 | pa->code = (__le32 *)fw->data; | |
2108 | pa->size = fw->size / FW_OPCODE_SIZE; | |
2109 | } | |
2110 | version[RTL_VER_SIZE - 1] = 0; | |
2111 | ||
2112 | rc = true; | |
2113 | out: | |
2114 | return rc; | |
2115 | } | |
2116 | ||
fd112f2e FR |
2117 | static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev, |
2118 | struct rtl_fw_phy_action *pa) | |
1c361efb | 2119 | { |
fd112f2e | 2120 | bool rc = false; |
1c361efb | 2121 | size_t index; |
bca03d5f | 2122 | |
1c361efb FR |
2123 | for (index = 0; index < pa->size; index++) { |
2124 | u32 action = le32_to_cpu(pa->code[index]); | |
42b82dc1 | 2125 | u32 regno = (action & 0x0fff0000) >> 16; |
bca03d5f | 2126 | |
42b82dc1 | 2127 | switch(action & 0xf0000000) { |
2128 | case PHY_READ: | |
2129 | case PHY_DATA_OR: | |
2130 | case PHY_DATA_AND: | |
2131 | case PHY_READ_EFUSE: | |
2132 | case PHY_CLEAR_READCOUNT: | |
2133 | case PHY_WRITE: | |
2134 | case PHY_WRITE_PREVIOUS: | |
2135 | case PHY_DELAY_MS: | |
2136 | break; | |
2137 | ||
2138 | case PHY_BJMPN: | |
2139 | if (regno > index) { | |
fd112f2e | 2140 | netif_err(tp, ifup, tp->dev, |
cecb5fd7 | 2141 | "Out of range of firmware\n"); |
fd112f2e | 2142 | goto out; |
42b82dc1 | 2143 | } |
2144 | break; | |
2145 | case PHY_READCOUNT_EQ_SKIP: | |
1c361efb | 2146 | if (index + 2 >= pa->size) { |
fd112f2e | 2147 | netif_err(tp, ifup, tp->dev, |
cecb5fd7 | 2148 | "Out of range of firmware\n"); |
fd112f2e | 2149 | goto out; |
42b82dc1 | 2150 | } |
2151 | break; | |
2152 | case PHY_COMP_EQ_SKIPN: | |
2153 | case PHY_COMP_NEQ_SKIPN: | |
2154 | case PHY_SKIPN: | |
1c361efb | 2155 | if (index + 1 + regno >= pa->size) { |
fd112f2e | 2156 | netif_err(tp, ifup, tp->dev, |
cecb5fd7 | 2157 | "Out of range of firmware\n"); |
fd112f2e | 2158 | goto out; |
42b82dc1 | 2159 | } |
bca03d5f | 2160 | break; |
2161 | ||
42b82dc1 | 2162 | case PHY_READ_MAC_BYTE: |
2163 | case PHY_WRITE_MAC_BYTE: | |
2164 | case PHY_WRITE_ERI_WORD: | |
2165 | default: | |
fd112f2e | 2166 | netif_err(tp, ifup, tp->dev, |
42b82dc1 | 2167 | "Invalid action 0x%08x\n", action); |
fd112f2e | 2168 | goto out; |
bca03d5f | 2169 | } |
2170 | } | |
fd112f2e FR |
2171 | rc = true; |
2172 | out: | |
2173 | return rc; | |
2174 | } | |
bca03d5f | 2175 | |
fd112f2e FR |
2176 | static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw) |
2177 | { | |
2178 | struct net_device *dev = tp->dev; | |
2179 | int rc = -EINVAL; | |
2180 | ||
2181 | if (!rtl_fw_format_ok(tp, rtl_fw)) { | |
2182 | netif_err(tp, ifup, dev, "invalid firwmare\n"); | |
2183 | goto out; | |
2184 | } | |
2185 | ||
2186 | if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action)) | |
2187 | rc = 0; | |
2188 | out: | |
2189 | return rc; | |
2190 | } | |
2191 | ||
2192 | static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw) | |
2193 | { | |
2194 | struct rtl_fw_phy_action *pa = &rtl_fw->phy_action; | |
2195 | u32 predata, count; | |
2196 | size_t index; | |
2197 | ||
2198 | predata = count = 0; | |
42b82dc1 | 2199 | |
1c361efb FR |
2200 | for (index = 0; index < pa->size; ) { |
2201 | u32 action = le32_to_cpu(pa->code[index]); | |
bca03d5f | 2202 | u32 data = action & 0x0000ffff; |
42b82dc1 | 2203 | u32 regno = (action & 0x0fff0000) >> 16; |
2204 | ||
2205 | if (!action) | |
2206 | break; | |
bca03d5f | 2207 | |
2208 | switch(action & 0xf0000000) { | |
42b82dc1 | 2209 | case PHY_READ: |
2210 | predata = rtl_readphy(tp, regno); | |
2211 | count++; | |
2212 | index++; | |
2213 | break; | |
2214 | case PHY_DATA_OR: | |
2215 | predata |= data; | |
2216 | index++; | |
2217 | break; | |
2218 | case PHY_DATA_AND: | |
2219 | predata &= data; | |
2220 | index++; | |
2221 | break; | |
2222 | case PHY_BJMPN: | |
2223 | index -= regno; | |
2224 | break; | |
2225 | case PHY_READ_EFUSE: | |
fdf6fc06 | 2226 | predata = rtl8168d_efuse_read(tp, regno); |
42b82dc1 | 2227 | index++; |
2228 | break; | |
2229 | case PHY_CLEAR_READCOUNT: | |
2230 | count = 0; | |
2231 | index++; | |
2232 | break; | |
bca03d5f | 2233 | case PHY_WRITE: |
42b82dc1 | 2234 | rtl_writephy(tp, regno, data); |
2235 | index++; | |
2236 | break; | |
2237 | case PHY_READCOUNT_EQ_SKIP: | |
cecb5fd7 | 2238 | index += (count == data) ? 2 : 1; |
bca03d5f | 2239 | break; |
42b82dc1 | 2240 | case PHY_COMP_EQ_SKIPN: |
2241 | if (predata == data) | |
2242 | index += regno; | |
2243 | index++; | |
2244 | break; | |
2245 | case PHY_COMP_NEQ_SKIPN: | |
2246 | if (predata != data) | |
2247 | index += regno; | |
2248 | index++; | |
2249 | break; | |
2250 | case PHY_WRITE_PREVIOUS: | |
2251 | rtl_writephy(tp, regno, predata); | |
2252 | index++; | |
2253 | break; | |
2254 | case PHY_SKIPN: | |
2255 | index += regno + 1; | |
2256 | break; | |
2257 | case PHY_DELAY_MS: | |
2258 | mdelay(data); | |
2259 | index++; | |
2260 | break; | |
2261 | ||
2262 | case PHY_READ_MAC_BYTE: | |
2263 | case PHY_WRITE_MAC_BYTE: | |
2264 | case PHY_WRITE_ERI_WORD: | |
bca03d5f | 2265 | default: |
2266 | BUG(); | |
2267 | } | |
2268 | } | |
2269 | } | |
2270 | ||
f1e02ed1 | 2271 | static void rtl_release_firmware(struct rtl8169_private *tp) |
2272 | { | |
b6ffd97f FR |
2273 | if (!IS_ERR_OR_NULL(tp->rtl_fw)) { |
2274 | release_firmware(tp->rtl_fw->fw); | |
2275 | kfree(tp->rtl_fw); | |
2276 | } | |
2277 | tp->rtl_fw = RTL_FIRMWARE_UNKNOWN; | |
f1e02ed1 | 2278 | } |
2279 | ||
953a12cc | 2280 | static void rtl_apply_firmware(struct rtl8169_private *tp) |
f1e02ed1 | 2281 | { |
b6ffd97f | 2282 | struct rtl_fw *rtl_fw = tp->rtl_fw; |
f1e02ed1 | 2283 | |
2284 | /* TODO: release firmware once rtl_phy_write_fw signals failures. */ | |
b6ffd97f FR |
2285 | if (!IS_ERR_OR_NULL(rtl_fw)) |
2286 | rtl_phy_write_fw(tp, rtl_fw); | |
953a12cc FR |
2287 | } |
2288 | ||
2289 | static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val) | |
2290 | { | |
2291 | if (rtl_readphy(tp, reg) != val) | |
2292 | netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n"); | |
2293 | else | |
2294 | rtl_apply_firmware(tp); | |
f1e02ed1 | 2295 | } |
2296 | ||
4da19633 | 2297 | static void rtl8169s_hw_phy_config(struct rtl8169_private *tp) |
1da177e4 | 2298 | { |
350f7596 | 2299 | static const struct phy_reg phy_reg_init[] = { |
0b9b571d | 2300 | { 0x1f, 0x0001 }, |
2301 | { 0x06, 0x006e }, | |
2302 | { 0x08, 0x0708 }, | |
2303 | { 0x15, 0x4000 }, | |
2304 | { 0x18, 0x65c7 }, | |
1da177e4 | 2305 | |
0b9b571d | 2306 | { 0x1f, 0x0001 }, |
2307 | { 0x03, 0x00a1 }, | |
2308 | { 0x02, 0x0008 }, | |
2309 | { 0x01, 0x0120 }, | |
2310 | { 0x00, 0x1000 }, | |
2311 | { 0x04, 0x0800 }, | |
2312 | { 0x04, 0x0000 }, | |
1da177e4 | 2313 | |
0b9b571d | 2314 | { 0x03, 0xff41 }, |
2315 | { 0x02, 0xdf60 }, | |
2316 | { 0x01, 0x0140 }, | |
2317 | { 0x00, 0x0077 }, | |
2318 | { 0x04, 0x7800 }, | |
2319 | { 0x04, 0x7000 }, | |
2320 | ||
2321 | { 0x03, 0x802f }, | |
2322 | { 0x02, 0x4f02 }, | |
2323 | { 0x01, 0x0409 }, | |
2324 | { 0x00, 0xf0f9 }, | |
2325 | { 0x04, 0x9800 }, | |
2326 | { 0x04, 0x9000 }, | |
2327 | ||
2328 | { 0x03, 0xdf01 }, | |
2329 | { 0x02, 0xdf20 }, | |
2330 | { 0x01, 0xff95 }, | |
2331 | { 0x00, 0xba00 }, | |
2332 | { 0x04, 0xa800 }, | |
2333 | { 0x04, 0xa000 }, | |
2334 | ||
2335 | { 0x03, 0xff41 }, | |
2336 | { 0x02, 0xdf20 }, | |
2337 | { 0x01, 0x0140 }, | |
2338 | { 0x00, 0x00bb }, | |
2339 | { 0x04, 0xb800 }, | |
2340 | { 0x04, 0xb000 }, | |
2341 | ||
2342 | { 0x03, 0xdf41 }, | |
2343 | { 0x02, 0xdc60 }, | |
2344 | { 0x01, 0x6340 }, | |
2345 | { 0x00, 0x007d }, | |
2346 | { 0x04, 0xd800 }, | |
2347 | { 0x04, 0xd000 }, | |
2348 | ||
2349 | { 0x03, 0xdf01 }, | |
2350 | { 0x02, 0xdf20 }, | |
2351 | { 0x01, 0x100a }, | |
2352 | { 0x00, 0xa0ff }, | |
2353 | { 0x04, 0xf800 }, | |
2354 | { 0x04, 0xf000 }, | |
2355 | ||
2356 | { 0x1f, 0x0000 }, | |
2357 | { 0x0b, 0x0000 }, | |
2358 | { 0x00, 0x9200 } | |
2359 | }; | |
1da177e4 | 2360 | |
4da19633 | 2361 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
1da177e4 LT |
2362 | } |
2363 | ||
4da19633 | 2364 | static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp) |
5615d9f1 | 2365 | { |
350f7596 | 2366 | static const struct phy_reg phy_reg_init[] = { |
a441d7b6 FR |
2367 | { 0x1f, 0x0002 }, |
2368 | { 0x01, 0x90d0 }, | |
2369 | { 0x1f, 0x0000 } | |
2370 | }; | |
2371 | ||
4da19633 | 2372 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
5615d9f1 FR |
2373 | } |
2374 | ||
4da19633 | 2375 | static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp) |
2e955856 | 2376 | { |
2377 | struct pci_dev *pdev = tp->pci_dev; | |
2e955856 | 2378 | |
ccbae55e SS |
2379 | if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) || |
2380 | (pdev->subsystem_device != 0xe000)) | |
2e955856 | 2381 | return; |
2382 | ||
4da19633 | 2383 | rtl_writephy(tp, 0x1f, 0x0001); |
2384 | rtl_writephy(tp, 0x10, 0xf01b); | |
2385 | rtl_writephy(tp, 0x1f, 0x0000); | |
2e955856 | 2386 | } |
2387 | ||
4da19633 | 2388 | static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp) |
2e955856 | 2389 | { |
350f7596 | 2390 | static const struct phy_reg phy_reg_init[] = { |
2e955856 | 2391 | { 0x1f, 0x0001 }, |
2392 | { 0x04, 0x0000 }, | |
2393 | { 0x03, 0x00a1 }, | |
2394 | { 0x02, 0x0008 }, | |
2395 | { 0x01, 0x0120 }, | |
2396 | { 0x00, 0x1000 }, | |
2397 | { 0x04, 0x0800 }, | |
2398 | { 0x04, 0x9000 }, | |
2399 | { 0x03, 0x802f }, | |
2400 | { 0x02, 0x4f02 }, | |
2401 | { 0x01, 0x0409 }, | |
2402 | { 0x00, 0xf099 }, | |
2403 | { 0x04, 0x9800 }, | |
2404 | { 0x04, 0xa000 }, | |
2405 | { 0x03, 0xdf01 }, | |
2406 | { 0x02, 0xdf20 }, | |
2407 | { 0x01, 0xff95 }, | |
2408 | { 0x00, 0xba00 }, | |
2409 | { 0x04, 0xa800 }, | |
2410 | { 0x04, 0xf000 }, | |
2411 | { 0x03, 0xdf01 }, | |
2412 | { 0x02, 0xdf20 }, | |
2413 | { 0x01, 0x101a }, | |
2414 | { 0x00, 0xa0ff }, | |
2415 | { 0x04, 0xf800 }, | |
2416 | { 0x04, 0x0000 }, | |
2417 | { 0x1f, 0x0000 }, | |
2418 | ||
2419 | { 0x1f, 0x0001 }, | |
2420 | { 0x10, 0xf41b }, | |
2421 | { 0x14, 0xfb54 }, | |
2422 | { 0x18, 0xf5c7 }, | |
2423 | { 0x1f, 0x0000 }, | |
2424 | ||
2425 | { 0x1f, 0x0001 }, | |
2426 | { 0x17, 0x0cc0 }, | |
2427 | { 0x1f, 0x0000 } | |
2428 | }; | |
2429 | ||
4da19633 | 2430 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
2e955856 | 2431 | |
4da19633 | 2432 | rtl8169scd_hw_phy_config_quirk(tp); |
2e955856 | 2433 | } |
2434 | ||
4da19633 | 2435 | static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp) |
8c7006aa | 2436 | { |
350f7596 | 2437 | static const struct phy_reg phy_reg_init[] = { |
8c7006aa | 2438 | { 0x1f, 0x0001 }, |
2439 | { 0x04, 0x0000 }, | |
2440 | { 0x03, 0x00a1 }, | |
2441 | { 0x02, 0x0008 }, | |
2442 | { 0x01, 0x0120 }, | |
2443 | { 0x00, 0x1000 }, | |
2444 | { 0x04, 0x0800 }, | |
2445 | { 0x04, 0x9000 }, | |
2446 | { 0x03, 0x802f }, | |
2447 | { 0x02, 0x4f02 }, | |
2448 | { 0x01, 0x0409 }, | |
2449 | { 0x00, 0xf099 }, | |
2450 | { 0x04, 0x9800 }, | |
2451 | { 0x04, 0xa000 }, | |
2452 | { 0x03, 0xdf01 }, | |
2453 | { 0x02, 0xdf20 }, | |
2454 | { 0x01, 0xff95 }, | |
2455 | { 0x00, 0xba00 }, | |
2456 | { 0x04, 0xa800 }, | |
2457 | { 0x04, 0xf000 }, | |
2458 | { 0x03, 0xdf01 }, | |
2459 | { 0x02, 0xdf20 }, | |
2460 | { 0x01, 0x101a }, | |
2461 | { 0x00, 0xa0ff }, | |
2462 | { 0x04, 0xf800 }, | |
2463 | { 0x04, 0x0000 }, | |
2464 | { 0x1f, 0x0000 }, | |
2465 | ||
2466 | { 0x1f, 0x0001 }, | |
2467 | { 0x0b, 0x8480 }, | |
2468 | { 0x1f, 0x0000 }, | |
2469 | ||
2470 | { 0x1f, 0x0001 }, | |
2471 | { 0x18, 0x67c7 }, | |
2472 | { 0x04, 0x2000 }, | |
2473 | { 0x03, 0x002f }, | |
2474 | { 0x02, 0x4360 }, | |
2475 | { 0x01, 0x0109 }, | |
2476 | { 0x00, 0x3022 }, | |
2477 | { 0x04, 0x2800 }, | |
2478 | { 0x1f, 0x0000 }, | |
2479 | ||
2480 | { 0x1f, 0x0001 }, | |
2481 | { 0x17, 0x0cc0 }, | |
2482 | { 0x1f, 0x0000 } | |
2483 | }; | |
2484 | ||
4da19633 | 2485 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
8c7006aa | 2486 | } |
2487 | ||
4da19633 | 2488 | static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp) |
236b8082 | 2489 | { |
350f7596 | 2490 | static const struct phy_reg phy_reg_init[] = { |
236b8082 FR |
2491 | { 0x10, 0xf41b }, |
2492 | { 0x1f, 0x0000 } | |
2493 | }; | |
2494 | ||
4da19633 | 2495 | rtl_writephy(tp, 0x1f, 0x0001); |
2496 | rtl_patchphy(tp, 0x16, 1 << 0); | |
236b8082 | 2497 | |
4da19633 | 2498 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
236b8082 FR |
2499 | } |
2500 | ||
4da19633 | 2501 | static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp) |
236b8082 | 2502 | { |
350f7596 | 2503 | static const struct phy_reg phy_reg_init[] = { |
236b8082 FR |
2504 | { 0x1f, 0x0001 }, |
2505 | { 0x10, 0xf41b }, | |
2506 | { 0x1f, 0x0000 } | |
2507 | }; | |
2508 | ||
4da19633 | 2509 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
236b8082 FR |
2510 | } |
2511 | ||
4da19633 | 2512 | static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp) |
867763c1 | 2513 | { |
350f7596 | 2514 | static const struct phy_reg phy_reg_init[] = { |
867763c1 FR |
2515 | { 0x1f, 0x0000 }, |
2516 | { 0x1d, 0x0f00 }, | |
2517 | { 0x1f, 0x0002 }, | |
2518 | { 0x0c, 0x1ec8 }, | |
2519 | { 0x1f, 0x0000 } | |
2520 | }; | |
2521 | ||
4da19633 | 2522 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
867763c1 FR |
2523 | } |
2524 | ||
4da19633 | 2525 | static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp) |
ef3386f0 | 2526 | { |
350f7596 | 2527 | static const struct phy_reg phy_reg_init[] = { |
ef3386f0 FR |
2528 | { 0x1f, 0x0001 }, |
2529 | { 0x1d, 0x3d98 }, | |
2530 | { 0x1f, 0x0000 } | |
2531 | }; | |
2532 | ||
4da19633 | 2533 | rtl_writephy(tp, 0x1f, 0x0000); |
2534 | rtl_patchphy(tp, 0x14, 1 << 5); | |
2535 | rtl_patchphy(tp, 0x0d, 1 << 5); | |
ef3386f0 | 2536 | |
4da19633 | 2537 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
ef3386f0 FR |
2538 | } |
2539 | ||
4da19633 | 2540 | static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp) |
867763c1 | 2541 | { |
350f7596 | 2542 | static const struct phy_reg phy_reg_init[] = { |
a3f80671 FR |
2543 | { 0x1f, 0x0001 }, |
2544 | { 0x12, 0x2300 }, | |
867763c1 FR |
2545 | { 0x1f, 0x0002 }, |
2546 | { 0x00, 0x88d4 }, | |
2547 | { 0x01, 0x82b1 }, | |
2548 | { 0x03, 0x7002 }, | |
2549 | { 0x08, 0x9e30 }, | |
2550 | { 0x09, 0x01f0 }, | |
2551 | { 0x0a, 0x5500 }, | |
2552 | { 0x0c, 0x00c8 }, | |
2553 | { 0x1f, 0x0003 }, | |
2554 | { 0x12, 0xc096 }, | |
2555 | { 0x16, 0x000a }, | |
f50d4275 FR |
2556 | { 0x1f, 0x0000 }, |
2557 | { 0x1f, 0x0000 }, | |
2558 | { 0x09, 0x2000 }, | |
2559 | { 0x09, 0x0000 } | |
867763c1 FR |
2560 | }; |
2561 | ||
4da19633 | 2562 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
f50d4275 | 2563 | |
4da19633 | 2564 | rtl_patchphy(tp, 0x14, 1 << 5); |
2565 | rtl_patchphy(tp, 0x0d, 1 << 5); | |
2566 | rtl_writephy(tp, 0x1f, 0x0000); | |
867763c1 FR |
2567 | } |
2568 | ||
4da19633 | 2569 | static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp) |
7da97ec9 | 2570 | { |
350f7596 | 2571 | static const struct phy_reg phy_reg_init[] = { |
f50d4275 | 2572 | { 0x1f, 0x0001 }, |
7da97ec9 | 2573 | { 0x12, 0x2300 }, |
f50d4275 FR |
2574 | { 0x03, 0x802f }, |
2575 | { 0x02, 0x4f02 }, | |
2576 | { 0x01, 0x0409 }, | |
2577 | { 0x00, 0xf099 }, | |
2578 | { 0x04, 0x9800 }, | |
2579 | { 0x04, 0x9000 }, | |
2580 | { 0x1d, 0x3d98 }, | |
7da97ec9 FR |
2581 | { 0x1f, 0x0002 }, |
2582 | { 0x0c, 0x7eb8 }, | |
f50d4275 FR |
2583 | { 0x06, 0x0761 }, |
2584 | { 0x1f, 0x0003 }, | |
2585 | { 0x16, 0x0f0a }, | |
7da97ec9 FR |
2586 | { 0x1f, 0x0000 } |
2587 | }; | |
2588 | ||
4da19633 | 2589 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
f50d4275 | 2590 | |
4da19633 | 2591 | rtl_patchphy(tp, 0x16, 1 << 0); |
2592 | rtl_patchphy(tp, 0x14, 1 << 5); | |
2593 | rtl_patchphy(tp, 0x0d, 1 << 5); | |
2594 | rtl_writephy(tp, 0x1f, 0x0000); | |
7da97ec9 FR |
2595 | } |
2596 | ||
4da19633 | 2597 | static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp) |
197ff761 | 2598 | { |
350f7596 | 2599 | static const struct phy_reg phy_reg_init[] = { |
197ff761 FR |
2600 | { 0x1f, 0x0001 }, |
2601 | { 0x12, 0x2300 }, | |
2602 | { 0x1d, 0x3d98 }, | |
2603 | { 0x1f, 0x0002 }, | |
2604 | { 0x0c, 0x7eb8 }, | |
2605 | { 0x06, 0x5461 }, | |
2606 | { 0x1f, 0x0003 }, | |
2607 | { 0x16, 0x0f0a }, | |
2608 | { 0x1f, 0x0000 } | |
2609 | }; | |
2610 | ||
4da19633 | 2611 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
197ff761 | 2612 | |
4da19633 | 2613 | rtl_patchphy(tp, 0x16, 1 << 0); |
2614 | rtl_patchphy(tp, 0x14, 1 << 5); | |
2615 | rtl_patchphy(tp, 0x0d, 1 << 5); | |
2616 | rtl_writephy(tp, 0x1f, 0x0000); | |
197ff761 FR |
2617 | } |
2618 | ||
4da19633 | 2619 | static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp) |
6fb07058 | 2620 | { |
4da19633 | 2621 | rtl8168c_3_hw_phy_config(tp); |
6fb07058 FR |
2622 | } |
2623 | ||
bca03d5f | 2624 | static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp) |
5b538df9 | 2625 | { |
350f7596 | 2626 | static const struct phy_reg phy_reg_init_0[] = { |
bca03d5f | 2627 | /* Channel Estimation */ |
5b538df9 | 2628 | { 0x1f, 0x0001 }, |
daf9df6d | 2629 | { 0x06, 0x4064 }, |
2630 | { 0x07, 0x2863 }, | |
2631 | { 0x08, 0x059c }, | |
2632 | { 0x09, 0x26b4 }, | |
2633 | { 0x0a, 0x6a19 }, | |
2634 | { 0x0b, 0xdcc8 }, | |
2635 | { 0x10, 0xf06d }, | |
2636 | { 0x14, 0x7f68 }, | |
2637 | { 0x18, 0x7fd9 }, | |
2638 | { 0x1c, 0xf0ff }, | |
2639 | { 0x1d, 0x3d9c }, | |
5b538df9 | 2640 | { 0x1f, 0x0003 }, |
daf9df6d | 2641 | { 0x12, 0xf49f }, |
2642 | { 0x13, 0x070b }, | |
2643 | { 0x1a, 0x05ad }, | |
bca03d5f | 2644 | { 0x14, 0x94c0 }, |
2645 | ||
2646 | /* | |
2647 | * Tx Error Issue | |
cecb5fd7 | 2648 | * Enhance line driver power |
bca03d5f | 2649 | */ |
5b538df9 | 2650 | { 0x1f, 0x0002 }, |
daf9df6d | 2651 | { 0x06, 0x5561 }, |
2652 | { 0x1f, 0x0005 }, | |
2653 | { 0x05, 0x8332 }, | |
bca03d5f | 2654 | { 0x06, 0x5561 }, |
2655 | ||
2656 | /* | |
2657 | * Can not link to 1Gbps with bad cable | |
2658 | * Decrease SNR threshold form 21.07dB to 19.04dB | |
2659 | */ | |
2660 | { 0x1f, 0x0001 }, | |
2661 | { 0x17, 0x0cc0 }, | |
daf9df6d | 2662 | |
5b538df9 | 2663 | { 0x1f, 0x0000 }, |
bca03d5f | 2664 | { 0x0d, 0xf880 } |
daf9df6d | 2665 | }; |
2666 | ||
4da19633 | 2667 | rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0)); |
daf9df6d | 2668 | |
bca03d5f | 2669 | /* |
2670 | * Rx Error Issue | |
2671 | * Fine Tune Switching regulator parameter | |
2672 | */ | |
4da19633 | 2673 | rtl_writephy(tp, 0x1f, 0x0002); |
2674 | rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef); | |
2675 | rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00); | |
daf9df6d | 2676 | |
fdf6fc06 | 2677 | if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) { |
350f7596 | 2678 | static const struct phy_reg phy_reg_init[] = { |
daf9df6d | 2679 | { 0x1f, 0x0002 }, |
2680 | { 0x05, 0x669a }, | |
2681 | { 0x1f, 0x0005 }, | |
2682 | { 0x05, 0x8330 }, | |
2683 | { 0x06, 0x669a }, | |
2684 | { 0x1f, 0x0002 } | |
2685 | }; | |
2686 | int val; | |
2687 | ||
4da19633 | 2688 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
daf9df6d | 2689 | |
4da19633 | 2690 | val = rtl_readphy(tp, 0x0d); |
daf9df6d | 2691 | |
2692 | if ((val & 0x00ff) != 0x006c) { | |
350f7596 | 2693 | static const u32 set[] = { |
daf9df6d | 2694 | 0x0065, 0x0066, 0x0067, 0x0068, |
2695 | 0x0069, 0x006a, 0x006b, 0x006c | |
2696 | }; | |
2697 | int i; | |
2698 | ||
4da19633 | 2699 | rtl_writephy(tp, 0x1f, 0x0002); |
daf9df6d | 2700 | |
2701 | val &= 0xff00; | |
2702 | for (i = 0; i < ARRAY_SIZE(set); i++) | |
4da19633 | 2703 | rtl_writephy(tp, 0x0d, val | set[i]); |
daf9df6d | 2704 | } |
2705 | } else { | |
350f7596 | 2706 | static const struct phy_reg phy_reg_init[] = { |
daf9df6d | 2707 | { 0x1f, 0x0002 }, |
2708 | { 0x05, 0x6662 }, | |
2709 | { 0x1f, 0x0005 }, | |
2710 | { 0x05, 0x8330 }, | |
2711 | { 0x06, 0x6662 } | |
2712 | }; | |
2713 | ||
4da19633 | 2714 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
daf9df6d | 2715 | } |
2716 | ||
bca03d5f | 2717 | /* RSET couple improve */ |
4da19633 | 2718 | rtl_writephy(tp, 0x1f, 0x0002); |
2719 | rtl_patchphy(tp, 0x0d, 0x0300); | |
2720 | rtl_patchphy(tp, 0x0f, 0x0010); | |
daf9df6d | 2721 | |
bca03d5f | 2722 | /* Fine tune PLL performance */ |
4da19633 | 2723 | rtl_writephy(tp, 0x1f, 0x0002); |
2724 | rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600); | |
2725 | rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000); | |
daf9df6d | 2726 | |
4da19633 | 2727 | rtl_writephy(tp, 0x1f, 0x0005); |
2728 | rtl_writephy(tp, 0x05, 0x001b); | |
953a12cc FR |
2729 | |
2730 | rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00); | |
bca03d5f | 2731 | |
4da19633 | 2732 | rtl_writephy(tp, 0x1f, 0x0000); |
daf9df6d | 2733 | } |
2734 | ||
bca03d5f | 2735 | static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp) |
daf9df6d | 2736 | { |
350f7596 | 2737 | static const struct phy_reg phy_reg_init_0[] = { |
bca03d5f | 2738 | /* Channel Estimation */ |
daf9df6d | 2739 | { 0x1f, 0x0001 }, |
2740 | { 0x06, 0x4064 }, | |
2741 | { 0x07, 0x2863 }, | |
2742 | { 0x08, 0x059c }, | |
2743 | { 0x09, 0x26b4 }, | |
2744 | { 0x0a, 0x6a19 }, | |
2745 | { 0x0b, 0xdcc8 }, | |
2746 | { 0x10, 0xf06d }, | |
2747 | { 0x14, 0x7f68 }, | |
2748 | { 0x18, 0x7fd9 }, | |
2749 | { 0x1c, 0xf0ff }, | |
2750 | { 0x1d, 0x3d9c }, | |
2751 | { 0x1f, 0x0003 }, | |
2752 | { 0x12, 0xf49f }, | |
2753 | { 0x13, 0x070b }, | |
2754 | { 0x1a, 0x05ad }, | |
2755 | { 0x14, 0x94c0 }, | |
2756 | ||
bca03d5f | 2757 | /* |
2758 | * Tx Error Issue | |
cecb5fd7 | 2759 | * Enhance line driver power |
bca03d5f | 2760 | */ |
daf9df6d | 2761 | { 0x1f, 0x0002 }, |
2762 | { 0x06, 0x5561 }, | |
2763 | { 0x1f, 0x0005 }, | |
2764 | { 0x05, 0x8332 }, | |
bca03d5f | 2765 | { 0x06, 0x5561 }, |
2766 | ||
2767 | /* | |
2768 | * Can not link to 1Gbps with bad cable | |
2769 | * Decrease SNR threshold form 21.07dB to 19.04dB | |
2770 | */ | |
2771 | { 0x1f, 0x0001 }, | |
2772 | { 0x17, 0x0cc0 }, | |
daf9df6d | 2773 | |
2774 | { 0x1f, 0x0000 }, | |
bca03d5f | 2775 | { 0x0d, 0xf880 } |
5b538df9 FR |
2776 | }; |
2777 | ||
4da19633 | 2778 | rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0)); |
5b538df9 | 2779 | |
fdf6fc06 | 2780 | if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) { |
350f7596 | 2781 | static const struct phy_reg phy_reg_init[] = { |
daf9df6d | 2782 | { 0x1f, 0x0002 }, |
2783 | { 0x05, 0x669a }, | |
5b538df9 | 2784 | { 0x1f, 0x0005 }, |
daf9df6d | 2785 | { 0x05, 0x8330 }, |
2786 | { 0x06, 0x669a }, | |
2787 | ||
2788 | { 0x1f, 0x0002 } | |
2789 | }; | |
2790 | int val; | |
2791 | ||
4da19633 | 2792 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
daf9df6d | 2793 | |
4da19633 | 2794 | val = rtl_readphy(tp, 0x0d); |
daf9df6d | 2795 | if ((val & 0x00ff) != 0x006c) { |
b6bc7650 | 2796 | static const u32 set[] = { |
daf9df6d | 2797 | 0x0065, 0x0066, 0x0067, 0x0068, |
2798 | 0x0069, 0x006a, 0x006b, 0x006c | |
2799 | }; | |
2800 | int i; | |
2801 | ||
4da19633 | 2802 | rtl_writephy(tp, 0x1f, 0x0002); |
daf9df6d | 2803 | |
2804 | val &= 0xff00; | |
2805 | for (i = 0; i < ARRAY_SIZE(set); i++) | |
4da19633 | 2806 | rtl_writephy(tp, 0x0d, val | set[i]); |
daf9df6d | 2807 | } |
2808 | } else { | |
350f7596 | 2809 | static const struct phy_reg phy_reg_init[] = { |
daf9df6d | 2810 | { 0x1f, 0x0002 }, |
2811 | { 0x05, 0x2642 }, | |
5b538df9 | 2812 | { 0x1f, 0x0005 }, |
daf9df6d | 2813 | { 0x05, 0x8330 }, |
2814 | { 0x06, 0x2642 } | |
5b538df9 FR |
2815 | }; |
2816 | ||
4da19633 | 2817 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
5b538df9 FR |
2818 | } |
2819 | ||
bca03d5f | 2820 | /* Fine tune PLL performance */ |
4da19633 | 2821 | rtl_writephy(tp, 0x1f, 0x0002); |
2822 | rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600); | |
2823 | rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000); | |
daf9df6d | 2824 | |
bca03d5f | 2825 | /* Switching regulator Slew rate */ |
4da19633 | 2826 | rtl_writephy(tp, 0x1f, 0x0002); |
2827 | rtl_patchphy(tp, 0x0f, 0x0017); | |
daf9df6d | 2828 | |
4da19633 | 2829 | rtl_writephy(tp, 0x1f, 0x0005); |
2830 | rtl_writephy(tp, 0x05, 0x001b); | |
953a12cc FR |
2831 | |
2832 | rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300); | |
bca03d5f | 2833 | |
4da19633 | 2834 | rtl_writephy(tp, 0x1f, 0x0000); |
daf9df6d | 2835 | } |
2836 | ||
4da19633 | 2837 | static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp) |
daf9df6d | 2838 | { |
350f7596 | 2839 | static const struct phy_reg phy_reg_init[] = { |
daf9df6d | 2840 | { 0x1f, 0x0002 }, |
2841 | { 0x10, 0x0008 }, | |
2842 | { 0x0d, 0x006c }, | |
2843 | ||
2844 | { 0x1f, 0x0000 }, | |
2845 | { 0x0d, 0xf880 }, | |
2846 | ||
2847 | { 0x1f, 0x0001 }, | |
2848 | { 0x17, 0x0cc0 }, | |
2849 | ||
2850 | { 0x1f, 0x0001 }, | |
2851 | { 0x0b, 0xa4d8 }, | |
2852 | { 0x09, 0x281c }, | |
2853 | { 0x07, 0x2883 }, | |
2854 | { 0x0a, 0x6b35 }, | |
2855 | { 0x1d, 0x3da4 }, | |
2856 | { 0x1c, 0xeffd }, | |
2857 | { 0x14, 0x7f52 }, | |
2858 | { 0x18, 0x7fc6 }, | |
2859 | { 0x08, 0x0601 }, | |
2860 | { 0x06, 0x4063 }, | |
2861 | { 0x10, 0xf074 }, | |
2862 | { 0x1f, 0x0003 }, | |
2863 | { 0x13, 0x0789 }, | |
2864 | { 0x12, 0xf4bd }, | |
2865 | { 0x1a, 0x04fd }, | |
2866 | { 0x14, 0x84b0 }, | |
2867 | { 0x1f, 0x0000 }, | |
2868 | { 0x00, 0x9200 }, | |
2869 | ||
2870 | { 0x1f, 0x0005 }, | |
2871 | { 0x01, 0x0340 }, | |
2872 | { 0x1f, 0x0001 }, | |
2873 | { 0x04, 0x4000 }, | |
2874 | { 0x03, 0x1d21 }, | |
2875 | { 0x02, 0x0c32 }, | |
2876 | { 0x01, 0x0200 }, | |
2877 | { 0x00, 0x5554 }, | |
2878 | { 0x04, 0x4800 }, | |
2879 | { 0x04, 0x4000 }, | |
2880 | { 0x04, 0xf000 }, | |
2881 | { 0x03, 0xdf01 }, | |
2882 | { 0x02, 0xdf20 }, | |
2883 | { 0x01, 0x101a }, | |
2884 | { 0x00, 0xa0ff }, | |
2885 | { 0x04, 0xf800 }, | |
2886 | { 0x04, 0xf000 }, | |
2887 | { 0x1f, 0x0000 }, | |
2888 | ||
2889 | { 0x1f, 0x0007 }, | |
2890 | { 0x1e, 0x0023 }, | |
2891 | { 0x16, 0x0000 }, | |
2892 | { 0x1f, 0x0000 } | |
2893 | }; | |
2894 | ||
4da19633 | 2895 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
5b538df9 FR |
2896 | } |
2897 | ||
e6de30d6 | 2898 | static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp) |
2899 | { | |
2900 | static const struct phy_reg phy_reg_init[] = { | |
2901 | { 0x1f, 0x0001 }, | |
2902 | { 0x17, 0x0cc0 }, | |
2903 | ||
2904 | { 0x1f, 0x0007 }, | |
2905 | { 0x1e, 0x002d }, | |
2906 | { 0x18, 0x0040 }, | |
2907 | { 0x1f, 0x0000 } | |
2908 | }; | |
2909 | ||
2910 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); | |
2911 | rtl_patchphy(tp, 0x0d, 1 << 5); | |
2912 | } | |
2913 | ||
70090424 | 2914 | static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp) |
01dc7fec | 2915 | { |
2916 | static const struct phy_reg phy_reg_init[] = { | |
2917 | /* Enable Delay cap */ | |
2918 | { 0x1f, 0x0005 }, | |
2919 | { 0x05, 0x8b80 }, | |
2920 | { 0x06, 0xc896 }, | |
2921 | { 0x1f, 0x0000 }, | |
2922 | ||
2923 | /* Channel estimation fine tune */ | |
2924 | { 0x1f, 0x0001 }, | |
2925 | { 0x0b, 0x6c20 }, | |
2926 | { 0x07, 0x2872 }, | |
2927 | { 0x1c, 0xefff }, | |
2928 | { 0x1f, 0x0003 }, | |
2929 | { 0x14, 0x6420 }, | |
2930 | { 0x1f, 0x0000 }, | |
2931 | ||
2932 | /* Update PFM & 10M TX idle timer */ | |
2933 | { 0x1f, 0x0007 }, | |
2934 | { 0x1e, 0x002f }, | |
2935 | { 0x15, 0x1919 }, | |
2936 | { 0x1f, 0x0000 }, | |
2937 | ||
2938 | { 0x1f, 0x0007 }, | |
2939 | { 0x1e, 0x00ac }, | |
2940 | { 0x18, 0x0006 }, | |
2941 | { 0x1f, 0x0000 } | |
2942 | }; | |
2943 | ||
15ecd039 FR |
2944 | rtl_apply_firmware(tp); |
2945 | ||
01dc7fec | 2946 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
2947 | ||
2948 | /* DCO enable for 10M IDLE Power */ | |
2949 | rtl_writephy(tp, 0x1f, 0x0007); | |
2950 | rtl_writephy(tp, 0x1e, 0x0023); | |
2951 | rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000); | |
2952 | rtl_writephy(tp, 0x1f, 0x0000); | |
2953 | ||
2954 | /* For impedance matching */ | |
2955 | rtl_writephy(tp, 0x1f, 0x0002); | |
2956 | rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00); | |
cecb5fd7 | 2957 | rtl_writephy(tp, 0x1f, 0x0000); |
01dc7fec | 2958 | |
2959 | /* PHY auto speed down */ | |
2960 | rtl_writephy(tp, 0x1f, 0x0007); | |
2961 | rtl_writephy(tp, 0x1e, 0x002d); | |
2962 | rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000); | |
2963 | rtl_writephy(tp, 0x1f, 0x0000); | |
2964 | rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000); | |
2965 | ||
2966 | rtl_writephy(tp, 0x1f, 0x0005); | |
2967 | rtl_writephy(tp, 0x05, 0x8b86); | |
2968 | rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000); | |
2969 | rtl_writephy(tp, 0x1f, 0x0000); | |
2970 | ||
2971 | rtl_writephy(tp, 0x1f, 0x0005); | |
2972 | rtl_writephy(tp, 0x05, 0x8b85); | |
2973 | rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000); | |
2974 | rtl_writephy(tp, 0x1f, 0x0007); | |
2975 | rtl_writephy(tp, 0x1e, 0x0020); | |
2976 | rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100); | |
2977 | rtl_writephy(tp, 0x1f, 0x0006); | |
2978 | rtl_writephy(tp, 0x00, 0x5a00); | |
2979 | rtl_writephy(tp, 0x1f, 0x0000); | |
2980 | rtl_writephy(tp, 0x0d, 0x0007); | |
2981 | rtl_writephy(tp, 0x0e, 0x003c); | |
2982 | rtl_writephy(tp, 0x0d, 0x4007); | |
2983 | rtl_writephy(tp, 0x0e, 0x0000); | |
2984 | rtl_writephy(tp, 0x0d, 0x0000); | |
2985 | } | |
2986 | ||
70090424 HW |
2987 | static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp) |
2988 | { | |
2989 | static const struct phy_reg phy_reg_init[] = { | |
2990 | /* Enable Delay cap */ | |
2991 | { 0x1f, 0x0004 }, | |
2992 | { 0x1f, 0x0007 }, | |
2993 | { 0x1e, 0x00ac }, | |
2994 | { 0x18, 0x0006 }, | |
2995 | { 0x1f, 0x0002 }, | |
2996 | { 0x1f, 0x0000 }, | |
2997 | { 0x1f, 0x0000 }, | |
2998 | ||
2999 | /* Channel estimation fine tune */ | |
3000 | { 0x1f, 0x0003 }, | |
3001 | { 0x09, 0xa20f }, | |
3002 | { 0x1f, 0x0000 }, | |
3003 | { 0x1f, 0x0000 }, | |
3004 | ||
3005 | /* Green Setting */ | |
3006 | { 0x1f, 0x0005 }, | |
3007 | { 0x05, 0x8b5b }, | |
3008 | { 0x06, 0x9222 }, | |
3009 | { 0x05, 0x8b6d }, | |
3010 | { 0x06, 0x8000 }, | |
3011 | { 0x05, 0x8b76 }, | |
3012 | { 0x06, 0x8000 }, | |
3013 | { 0x1f, 0x0000 } | |
3014 | }; | |
3015 | ||
3016 | rtl_apply_firmware(tp); | |
3017 | ||
3018 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); | |
3019 | ||
3020 | /* For 4-corner performance improve */ | |
3021 | rtl_writephy(tp, 0x1f, 0x0005); | |
3022 | rtl_writephy(tp, 0x05, 0x8b80); | |
3023 | rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000); | |
3024 | rtl_writephy(tp, 0x1f, 0x0000); | |
3025 | ||
3026 | /* PHY auto speed down */ | |
3027 | rtl_writephy(tp, 0x1f, 0x0004); | |
3028 | rtl_writephy(tp, 0x1f, 0x0007); | |
3029 | rtl_writephy(tp, 0x1e, 0x002d); | |
3030 | rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000); | |
3031 | rtl_writephy(tp, 0x1f, 0x0002); | |
3032 | rtl_writephy(tp, 0x1f, 0x0000); | |
3033 | rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000); | |
3034 | ||
3035 | /* improve 10M EEE waveform */ | |
3036 | rtl_writephy(tp, 0x1f, 0x0005); | |
3037 | rtl_writephy(tp, 0x05, 0x8b86); | |
3038 | rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000); | |
3039 | rtl_writephy(tp, 0x1f, 0x0000); | |
3040 | ||
3041 | /* Improve 2-pair detection performance */ | |
3042 | rtl_writephy(tp, 0x1f, 0x0005); | |
3043 | rtl_writephy(tp, 0x05, 0x8b85); | |
3044 | rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000); | |
3045 | rtl_writephy(tp, 0x1f, 0x0000); | |
3046 | ||
3047 | /* EEE setting */ | |
fdf6fc06 | 3048 | rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003, ERIAR_EXGMAC); |
70090424 HW |
3049 | rtl_writephy(tp, 0x1f, 0x0005); |
3050 | rtl_writephy(tp, 0x05, 0x8b85); | |
3051 | rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000); | |
3052 | rtl_writephy(tp, 0x1f, 0x0004); | |
3053 | rtl_writephy(tp, 0x1f, 0x0007); | |
3054 | rtl_writephy(tp, 0x1e, 0x0020); | |
1b23a3e3 | 3055 | rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100); |
70090424 HW |
3056 | rtl_writephy(tp, 0x1f, 0x0002); |
3057 | rtl_writephy(tp, 0x1f, 0x0000); | |
3058 | rtl_writephy(tp, 0x0d, 0x0007); | |
3059 | rtl_writephy(tp, 0x0e, 0x003c); | |
3060 | rtl_writephy(tp, 0x0d, 0x4007); | |
3061 | rtl_writephy(tp, 0x0e, 0x0000); | |
3062 | rtl_writephy(tp, 0x0d, 0x0000); | |
3063 | ||
3064 | /* Green feature */ | |
3065 | rtl_writephy(tp, 0x1f, 0x0003); | |
3066 | rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001); | |
3067 | rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400); | |
3068 | rtl_writephy(tp, 0x1f, 0x0000); | |
3069 | } | |
3070 | ||
5f886e08 HW |
3071 | static void rtl8168f_hw_phy_config(struct rtl8169_private *tp) |
3072 | { | |
3073 | /* For 4-corner performance improve */ | |
3074 | rtl_writephy(tp, 0x1f, 0x0005); | |
3075 | rtl_writephy(tp, 0x05, 0x8b80); | |
3076 | rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000); | |
3077 | rtl_writephy(tp, 0x1f, 0x0000); | |
3078 | ||
3079 | /* PHY auto speed down */ | |
3080 | rtl_writephy(tp, 0x1f, 0x0007); | |
3081 | rtl_writephy(tp, 0x1e, 0x002d); | |
3082 | rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000); | |
3083 | rtl_writephy(tp, 0x1f, 0x0000); | |
3084 | rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000); | |
3085 | ||
3086 | /* Improve 10M EEE waveform */ | |
3087 | rtl_writephy(tp, 0x1f, 0x0005); | |
3088 | rtl_writephy(tp, 0x05, 0x8b86); | |
3089 | rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000); | |
3090 | rtl_writephy(tp, 0x1f, 0x0000); | |
3091 | } | |
3092 | ||
c2218925 HW |
3093 | static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp) |
3094 | { | |
3095 | static const struct phy_reg phy_reg_init[] = { | |
3096 | /* Channel estimation fine tune */ | |
3097 | { 0x1f, 0x0003 }, | |
3098 | { 0x09, 0xa20f }, | |
3099 | { 0x1f, 0x0000 }, | |
3100 | ||
3101 | /* Modify green table for giga & fnet */ | |
3102 | { 0x1f, 0x0005 }, | |
3103 | { 0x05, 0x8b55 }, | |
3104 | { 0x06, 0x0000 }, | |
3105 | { 0x05, 0x8b5e }, | |
3106 | { 0x06, 0x0000 }, | |
3107 | { 0x05, 0x8b67 }, | |
3108 | { 0x06, 0x0000 }, | |
3109 | { 0x05, 0x8b70 }, | |
3110 | { 0x06, 0x0000 }, | |
3111 | { 0x1f, 0x0000 }, | |
3112 | { 0x1f, 0x0007 }, | |
3113 | { 0x1e, 0x0078 }, | |
3114 | { 0x17, 0x0000 }, | |
3115 | { 0x19, 0x00fb }, | |
3116 | { 0x1f, 0x0000 }, | |
3117 | ||
3118 | /* Modify green table for 10M */ | |
3119 | { 0x1f, 0x0005 }, | |
3120 | { 0x05, 0x8b79 }, | |
3121 | { 0x06, 0xaa00 }, | |
3122 | { 0x1f, 0x0000 }, | |
3123 | ||
3124 | /* Disable hiimpedance detection (RTCT) */ | |
3125 | { 0x1f, 0x0003 }, | |
3126 | { 0x01, 0x328a }, | |
3127 | { 0x1f, 0x0000 } | |
3128 | }; | |
3129 | ||
3130 | rtl_apply_firmware(tp); | |
3131 | ||
3132 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); | |
3133 | ||
5f886e08 | 3134 | rtl8168f_hw_phy_config(tp); |
c2218925 HW |
3135 | |
3136 | /* Improve 2-pair detection performance */ | |
3137 | rtl_writephy(tp, 0x1f, 0x0005); | |
3138 | rtl_writephy(tp, 0x05, 0x8b85); | |
3139 | rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000); | |
3140 | rtl_writephy(tp, 0x1f, 0x0000); | |
3141 | } | |
3142 | ||
3143 | static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp) | |
3144 | { | |
3145 | rtl_apply_firmware(tp); | |
3146 | ||
5f886e08 | 3147 | rtl8168f_hw_phy_config(tp); |
c2218925 HW |
3148 | } |
3149 | ||
b3d7b2f2 HW |
3150 | static void rtl8411_hw_phy_config(struct rtl8169_private *tp) |
3151 | { | |
b3d7b2f2 HW |
3152 | static const struct phy_reg phy_reg_init[] = { |
3153 | /* Channel estimation fine tune */ | |
3154 | { 0x1f, 0x0003 }, | |
3155 | { 0x09, 0xa20f }, | |
3156 | { 0x1f, 0x0000 }, | |
3157 | ||
3158 | /* Modify green table for giga & fnet */ | |
3159 | { 0x1f, 0x0005 }, | |
3160 | { 0x05, 0x8b55 }, | |
3161 | { 0x06, 0x0000 }, | |
3162 | { 0x05, 0x8b5e }, | |
3163 | { 0x06, 0x0000 }, | |
3164 | { 0x05, 0x8b67 }, | |
3165 | { 0x06, 0x0000 }, | |
3166 | { 0x05, 0x8b70 }, | |
3167 | { 0x06, 0x0000 }, | |
3168 | { 0x1f, 0x0000 }, | |
3169 | { 0x1f, 0x0007 }, | |
3170 | { 0x1e, 0x0078 }, | |
3171 | { 0x17, 0x0000 }, | |
3172 | { 0x19, 0x00aa }, | |
3173 | { 0x1f, 0x0000 }, | |
3174 | ||
3175 | /* Modify green table for 10M */ | |
3176 | { 0x1f, 0x0005 }, | |
3177 | { 0x05, 0x8b79 }, | |
3178 | { 0x06, 0xaa00 }, | |
3179 | { 0x1f, 0x0000 }, | |
3180 | ||
3181 | /* Disable hiimpedance detection (RTCT) */ | |
3182 | { 0x1f, 0x0003 }, | |
3183 | { 0x01, 0x328a }, | |
3184 | { 0x1f, 0x0000 } | |
3185 | }; | |
3186 | ||
3187 | ||
3188 | rtl_apply_firmware(tp); | |
3189 | ||
3190 | rtl8168f_hw_phy_config(tp); | |
3191 | ||
3192 | /* Improve 2-pair detection performance */ | |
3193 | rtl_writephy(tp, 0x1f, 0x0005); | |
3194 | rtl_writephy(tp, 0x05, 0x8b85); | |
3195 | rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000); | |
3196 | rtl_writephy(tp, 0x1f, 0x0000); | |
3197 | ||
3198 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); | |
3199 | ||
3200 | /* Modify green table for giga */ | |
3201 | rtl_writephy(tp, 0x1f, 0x0005); | |
3202 | rtl_writephy(tp, 0x05, 0x8b54); | |
3203 | rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0800); | |
3204 | rtl_writephy(tp, 0x05, 0x8b5d); | |
3205 | rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0800); | |
3206 | rtl_writephy(tp, 0x05, 0x8a7c); | |
3207 | rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100); | |
3208 | rtl_writephy(tp, 0x05, 0x8a7f); | |
3209 | rtl_w1w0_phy(tp, 0x06, 0x0100, 0x0000); | |
3210 | rtl_writephy(tp, 0x05, 0x8a82); | |
3211 | rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100); | |
3212 | rtl_writephy(tp, 0x05, 0x8a85); | |
3213 | rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100); | |
3214 | rtl_writephy(tp, 0x05, 0x8a88); | |
3215 | rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100); | |
3216 | rtl_writephy(tp, 0x1f, 0x0000); | |
3217 | ||
3218 | /* uc same-seed solution */ | |
3219 | rtl_writephy(tp, 0x1f, 0x0005); | |
3220 | rtl_writephy(tp, 0x05, 0x8b85); | |
3221 | rtl_w1w0_phy(tp, 0x06, 0x8000, 0x0000); | |
3222 | rtl_writephy(tp, 0x1f, 0x0000); | |
3223 | ||
3224 | /* eee setting */ | |
fdf6fc06 | 3225 | rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC); |
b3d7b2f2 HW |
3226 | rtl_writephy(tp, 0x1f, 0x0005); |
3227 | rtl_writephy(tp, 0x05, 0x8b85); | |
3228 | rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000); | |
3229 | rtl_writephy(tp, 0x1f, 0x0004); | |
3230 | rtl_writephy(tp, 0x1f, 0x0007); | |
3231 | rtl_writephy(tp, 0x1e, 0x0020); | |
3232 | rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100); | |
3233 | rtl_writephy(tp, 0x1f, 0x0000); | |
3234 | rtl_writephy(tp, 0x0d, 0x0007); | |
3235 | rtl_writephy(tp, 0x0e, 0x003c); | |
3236 | rtl_writephy(tp, 0x0d, 0x4007); | |
3237 | rtl_writephy(tp, 0x0e, 0x0000); | |
3238 | rtl_writephy(tp, 0x0d, 0x0000); | |
3239 | ||
3240 | /* Green feature */ | |
3241 | rtl_writephy(tp, 0x1f, 0x0003); | |
3242 | rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001); | |
3243 | rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400); | |
3244 | rtl_writephy(tp, 0x1f, 0x0000); | |
3245 | } | |
3246 | ||
4da19633 | 3247 | static void rtl8102e_hw_phy_config(struct rtl8169_private *tp) |
2857ffb7 | 3248 | { |
350f7596 | 3249 | static const struct phy_reg phy_reg_init[] = { |
2857ffb7 FR |
3250 | { 0x1f, 0x0003 }, |
3251 | { 0x08, 0x441d }, | |
3252 | { 0x01, 0x9100 }, | |
3253 | { 0x1f, 0x0000 } | |
3254 | }; | |
3255 | ||
4da19633 | 3256 | rtl_writephy(tp, 0x1f, 0x0000); |
3257 | rtl_patchphy(tp, 0x11, 1 << 12); | |
3258 | rtl_patchphy(tp, 0x19, 1 << 13); | |
3259 | rtl_patchphy(tp, 0x10, 1 << 15); | |
2857ffb7 | 3260 | |
4da19633 | 3261 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
2857ffb7 FR |
3262 | } |
3263 | ||
5a5e4443 HW |
3264 | static void rtl8105e_hw_phy_config(struct rtl8169_private *tp) |
3265 | { | |
3266 | static const struct phy_reg phy_reg_init[] = { | |
3267 | { 0x1f, 0x0005 }, | |
3268 | { 0x1a, 0x0000 }, | |
3269 | { 0x1f, 0x0000 }, | |
3270 | ||
3271 | { 0x1f, 0x0004 }, | |
3272 | { 0x1c, 0x0000 }, | |
3273 | { 0x1f, 0x0000 }, | |
3274 | ||
3275 | { 0x1f, 0x0001 }, | |
3276 | { 0x15, 0x7701 }, | |
3277 | { 0x1f, 0x0000 } | |
3278 | }; | |
3279 | ||
3280 | /* Disable ALDPS before ram code */ | |
3281 | rtl_writephy(tp, 0x1f, 0x0000); | |
3282 | rtl_writephy(tp, 0x18, 0x0310); | |
3283 | msleep(100); | |
3284 | ||
953a12cc | 3285 | rtl_apply_firmware(tp); |
5a5e4443 HW |
3286 | |
3287 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); | |
3288 | } | |
3289 | ||
7e18dca1 HW |
3290 | static void rtl8402_hw_phy_config(struct rtl8169_private *tp) |
3291 | { | |
7e18dca1 HW |
3292 | /* Disable ALDPS before setting firmware */ |
3293 | rtl_writephy(tp, 0x1f, 0x0000); | |
3294 | rtl_writephy(tp, 0x18, 0x0310); | |
3295 | msleep(20); | |
3296 | ||
3297 | rtl_apply_firmware(tp); | |
3298 | ||
3299 | /* EEE setting */ | |
fdf6fc06 | 3300 | rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); |
7e18dca1 HW |
3301 | rtl_writephy(tp, 0x1f, 0x0004); |
3302 | rtl_writephy(tp, 0x10, 0x401f); | |
3303 | rtl_writephy(tp, 0x19, 0x7030); | |
3304 | rtl_writephy(tp, 0x1f, 0x0000); | |
3305 | } | |
3306 | ||
5598bfe5 HW |
3307 | static void rtl8106e_hw_phy_config(struct rtl8169_private *tp) |
3308 | { | |
5598bfe5 HW |
3309 | static const struct phy_reg phy_reg_init[] = { |
3310 | { 0x1f, 0x0004 }, | |
3311 | { 0x10, 0xc07f }, | |
3312 | { 0x19, 0x7030 }, | |
3313 | { 0x1f, 0x0000 } | |
3314 | }; | |
3315 | ||
3316 | /* Disable ALDPS before ram code */ | |
3317 | rtl_writephy(tp, 0x1f, 0x0000); | |
3318 | rtl_writephy(tp, 0x18, 0x0310); | |
3319 | msleep(100); | |
3320 | ||
3321 | rtl_apply_firmware(tp); | |
3322 | ||
fdf6fc06 | 3323 | rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); |
5598bfe5 HW |
3324 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
3325 | ||
fdf6fc06 | 3326 | rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); |
5598bfe5 HW |
3327 | } |
3328 | ||
5615d9f1 FR |
3329 | static void rtl_hw_phy_config(struct net_device *dev) |
3330 | { | |
3331 | struct rtl8169_private *tp = netdev_priv(dev); | |
5615d9f1 FR |
3332 | |
3333 | rtl8169_print_mac_version(tp); | |
3334 | ||
3335 | switch (tp->mac_version) { | |
3336 | case RTL_GIGA_MAC_VER_01: | |
3337 | break; | |
3338 | case RTL_GIGA_MAC_VER_02: | |
3339 | case RTL_GIGA_MAC_VER_03: | |
4da19633 | 3340 | rtl8169s_hw_phy_config(tp); |
5615d9f1 FR |
3341 | break; |
3342 | case RTL_GIGA_MAC_VER_04: | |
4da19633 | 3343 | rtl8169sb_hw_phy_config(tp); |
5615d9f1 | 3344 | break; |
2e955856 | 3345 | case RTL_GIGA_MAC_VER_05: |
4da19633 | 3346 | rtl8169scd_hw_phy_config(tp); |
2e955856 | 3347 | break; |
8c7006aa | 3348 | case RTL_GIGA_MAC_VER_06: |
4da19633 | 3349 | rtl8169sce_hw_phy_config(tp); |
8c7006aa | 3350 | break; |
2857ffb7 FR |
3351 | case RTL_GIGA_MAC_VER_07: |
3352 | case RTL_GIGA_MAC_VER_08: | |
3353 | case RTL_GIGA_MAC_VER_09: | |
4da19633 | 3354 | rtl8102e_hw_phy_config(tp); |
2857ffb7 | 3355 | break; |
236b8082 | 3356 | case RTL_GIGA_MAC_VER_11: |
4da19633 | 3357 | rtl8168bb_hw_phy_config(tp); |
236b8082 FR |
3358 | break; |
3359 | case RTL_GIGA_MAC_VER_12: | |
4da19633 | 3360 | rtl8168bef_hw_phy_config(tp); |
236b8082 FR |
3361 | break; |
3362 | case RTL_GIGA_MAC_VER_17: | |
4da19633 | 3363 | rtl8168bef_hw_phy_config(tp); |
236b8082 | 3364 | break; |
867763c1 | 3365 | case RTL_GIGA_MAC_VER_18: |
4da19633 | 3366 | rtl8168cp_1_hw_phy_config(tp); |
867763c1 FR |
3367 | break; |
3368 | case RTL_GIGA_MAC_VER_19: | |
4da19633 | 3369 | rtl8168c_1_hw_phy_config(tp); |
867763c1 | 3370 | break; |
7da97ec9 | 3371 | case RTL_GIGA_MAC_VER_20: |
4da19633 | 3372 | rtl8168c_2_hw_phy_config(tp); |
7da97ec9 | 3373 | break; |
197ff761 | 3374 | case RTL_GIGA_MAC_VER_21: |
4da19633 | 3375 | rtl8168c_3_hw_phy_config(tp); |
197ff761 | 3376 | break; |
6fb07058 | 3377 | case RTL_GIGA_MAC_VER_22: |
4da19633 | 3378 | rtl8168c_4_hw_phy_config(tp); |
6fb07058 | 3379 | break; |
ef3386f0 | 3380 | case RTL_GIGA_MAC_VER_23: |
7f3e3d3a | 3381 | case RTL_GIGA_MAC_VER_24: |
4da19633 | 3382 | rtl8168cp_2_hw_phy_config(tp); |
ef3386f0 | 3383 | break; |
5b538df9 | 3384 | case RTL_GIGA_MAC_VER_25: |
bca03d5f | 3385 | rtl8168d_1_hw_phy_config(tp); |
daf9df6d | 3386 | break; |
3387 | case RTL_GIGA_MAC_VER_26: | |
bca03d5f | 3388 | rtl8168d_2_hw_phy_config(tp); |
daf9df6d | 3389 | break; |
3390 | case RTL_GIGA_MAC_VER_27: | |
4da19633 | 3391 | rtl8168d_3_hw_phy_config(tp); |
5b538df9 | 3392 | break; |
e6de30d6 | 3393 | case RTL_GIGA_MAC_VER_28: |
3394 | rtl8168d_4_hw_phy_config(tp); | |
3395 | break; | |
5a5e4443 HW |
3396 | case RTL_GIGA_MAC_VER_29: |
3397 | case RTL_GIGA_MAC_VER_30: | |
3398 | rtl8105e_hw_phy_config(tp); | |
3399 | break; | |
cecb5fd7 FR |
3400 | case RTL_GIGA_MAC_VER_31: |
3401 | /* None. */ | |
3402 | break; | |
01dc7fec | 3403 | case RTL_GIGA_MAC_VER_32: |
01dc7fec | 3404 | case RTL_GIGA_MAC_VER_33: |
70090424 HW |
3405 | rtl8168e_1_hw_phy_config(tp); |
3406 | break; | |
3407 | case RTL_GIGA_MAC_VER_34: | |
3408 | rtl8168e_2_hw_phy_config(tp); | |
01dc7fec | 3409 | break; |
c2218925 HW |
3410 | case RTL_GIGA_MAC_VER_35: |
3411 | rtl8168f_1_hw_phy_config(tp); | |
3412 | break; | |
3413 | case RTL_GIGA_MAC_VER_36: | |
3414 | rtl8168f_2_hw_phy_config(tp); | |
3415 | break; | |
ef3386f0 | 3416 | |
7e18dca1 HW |
3417 | case RTL_GIGA_MAC_VER_37: |
3418 | rtl8402_hw_phy_config(tp); | |
3419 | break; | |
3420 | ||
b3d7b2f2 HW |
3421 | case RTL_GIGA_MAC_VER_38: |
3422 | rtl8411_hw_phy_config(tp); | |
3423 | break; | |
3424 | ||
5598bfe5 HW |
3425 | case RTL_GIGA_MAC_VER_39: |
3426 | rtl8106e_hw_phy_config(tp); | |
3427 | break; | |
3428 | ||
5615d9f1 FR |
3429 | default: |
3430 | break; | |
3431 | } | |
3432 | } | |
3433 | ||
da78dbff | 3434 | static void rtl_phy_work(struct rtl8169_private *tp) |
1da177e4 | 3435 | { |
1da177e4 LT |
3436 | struct timer_list *timer = &tp->timer; |
3437 | void __iomem *ioaddr = tp->mmio_addr; | |
3438 | unsigned long timeout = RTL8169_PHY_TIMEOUT; | |
3439 | ||
bcf0bf90 | 3440 | assert(tp->mac_version > RTL_GIGA_MAC_VER_01); |
1da177e4 | 3441 | |
4da19633 | 3442 | if (tp->phy_reset_pending(tp)) { |
5b0384f4 | 3443 | /* |
1da177e4 LT |
3444 | * A busy loop could burn quite a few cycles on nowadays CPU. |
3445 | * Let's delay the execution of the timer for a few ticks. | |
3446 | */ | |
3447 | timeout = HZ/10; | |
3448 | goto out_mod_timer; | |
3449 | } | |
3450 | ||
3451 | if (tp->link_ok(ioaddr)) | |
da78dbff | 3452 | return; |
1da177e4 | 3453 | |
da78dbff | 3454 | netif_warn(tp, link, tp->dev, "PHY reset until link up\n"); |
1da177e4 | 3455 | |
4da19633 | 3456 | tp->phy_reset_enable(tp); |
1da177e4 LT |
3457 | |
3458 | out_mod_timer: | |
3459 | mod_timer(timer, jiffies + timeout); | |
da78dbff FR |
3460 | } |
3461 | ||
3462 | static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag) | |
3463 | { | |
da78dbff FR |
3464 | if (!test_and_set_bit(flag, tp->wk.flags)) |
3465 | schedule_work(&tp->wk.work); | |
da78dbff FR |
3466 | } |
3467 | ||
3468 | static void rtl8169_phy_timer(unsigned long __opaque) | |
3469 | { | |
3470 | struct net_device *dev = (struct net_device *)__opaque; | |
3471 | struct rtl8169_private *tp = netdev_priv(dev); | |
3472 | ||
98ddf986 | 3473 | rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING); |
1da177e4 LT |
3474 | } |
3475 | ||
1da177e4 LT |
3476 | static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev, |
3477 | void __iomem *ioaddr) | |
3478 | { | |
3479 | iounmap(ioaddr); | |
3480 | pci_release_regions(pdev); | |
87aeec76 | 3481 | pci_clear_mwi(pdev); |
1da177e4 LT |
3482 | pci_disable_device(pdev); |
3483 | free_netdev(dev); | |
3484 | } | |
3485 | ||
ffc46952 FR |
3486 | DECLARE_RTL_COND(rtl_phy_reset_cond) |
3487 | { | |
3488 | return tp->phy_reset_pending(tp); | |
3489 | } | |
3490 | ||
bf793295 FR |
3491 | static void rtl8169_phy_reset(struct net_device *dev, |
3492 | struct rtl8169_private *tp) | |
3493 | { | |
4da19633 | 3494 | tp->phy_reset_enable(tp); |
ffc46952 | 3495 | rtl_msleep_loop_wait_low(tp, &rtl_phy_reset_cond, 1, 100); |
bf793295 FR |
3496 | } |
3497 | ||
2544bfc0 FR |
3498 | static bool rtl_tbi_enabled(struct rtl8169_private *tp) |
3499 | { | |
3500 | void __iomem *ioaddr = tp->mmio_addr; | |
3501 | ||
3502 | return (tp->mac_version == RTL_GIGA_MAC_VER_01) && | |
3503 | (RTL_R8(PHYstatus) & TBI_Enable); | |
3504 | } | |
3505 | ||
4ff96fa6 FR |
3506 | static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp) |
3507 | { | |
3508 | void __iomem *ioaddr = tp->mmio_addr; | |
4ff96fa6 | 3509 | |
5615d9f1 | 3510 | rtl_hw_phy_config(dev); |
4ff96fa6 | 3511 | |
77332894 MS |
3512 | if (tp->mac_version <= RTL_GIGA_MAC_VER_06) { |
3513 | dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n"); | |
3514 | RTL_W8(0x82, 0x01); | |
3515 | } | |
4ff96fa6 | 3516 | |
6dccd16b FR |
3517 | pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); |
3518 | ||
3519 | if (tp->mac_version <= RTL_GIGA_MAC_VER_06) | |
3520 | pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); | |
4ff96fa6 | 3521 | |
bcf0bf90 | 3522 | if (tp->mac_version == RTL_GIGA_MAC_VER_02) { |
4ff96fa6 FR |
3523 | dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n"); |
3524 | RTL_W8(0x82, 0x01); | |
3525 | dprintk("Set PHY Reg 0x0bh = 0x00h\n"); | |
4da19633 | 3526 | rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0 |
4ff96fa6 FR |
3527 | } |
3528 | ||
bf793295 FR |
3529 | rtl8169_phy_reset(dev, tp); |
3530 | ||
54405cde | 3531 | rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL, |
cecb5fd7 FR |
3532 | ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | |
3533 | ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | | |
3534 | (tp->mii.supports_gmii ? | |
3535 | ADVERTISED_1000baseT_Half | | |
3536 | ADVERTISED_1000baseT_Full : 0)); | |
4ff96fa6 | 3537 | |
2544bfc0 | 3538 | if (rtl_tbi_enabled(tp)) |
bf82c189 | 3539 | netif_info(tp, link, dev, "TBI auto-negotiating\n"); |
4ff96fa6 FR |
3540 | } |
3541 | ||
773d2021 FR |
3542 | static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr) |
3543 | { | |
3544 | void __iomem *ioaddr = tp->mmio_addr; | |
3545 | u32 high; | |
3546 | u32 low; | |
3547 | ||
3548 | low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24); | |
3549 | high = addr[4] | (addr[5] << 8); | |
3550 | ||
da78dbff | 3551 | rtl_lock_work(tp); |
773d2021 FR |
3552 | |
3553 | RTL_W8(Cfg9346, Cfg9346_Unlock); | |
908ba2bf | 3554 | |
773d2021 | 3555 | RTL_W32(MAC4, high); |
908ba2bf | 3556 | RTL_R32(MAC4); |
3557 | ||
78f1cd02 | 3558 | RTL_W32(MAC0, low); |
908ba2bf | 3559 | RTL_R32(MAC0); |
3560 | ||
c28aa385 | 3561 | if (tp->mac_version == RTL_GIGA_MAC_VER_34) { |
3562 | const struct exgmac_reg e[] = { | |
3563 | { .addr = 0xe0, ERIAR_MASK_1111, .val = low }, | |
3564 | { .addr = 0xe4, ERIAR_MASK_1111, .val = high }, | |
3565 | { .addr = 0xf0, ERIAR_MASK_1111, .val = low << 16 }, | |
3566 | { .addr = 0xf4, ERIAR_MASK_1111, .val = high << 16 | | |
3567 | low >> 16 }, | |
3568 | }; | |
3569 | ||
fdf6fc06 | 3570 | rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e)); |
c28aa385 | 3571 | } |
3572 | ||
773d2021 FR |
3573 | RTL_W8(Cfg9346, Cfg9346_Lock); |
3574 | ||
da78dbff | 3575 | rtl_unlock_work(tp); |
773d2021 FR |
3576 | } |
3577 | ||
3578 | static int rtl_set_mac_address(struct net_device *dev, void *p) | |
3579 | { | |
3580 | struct rtl8169_private *tp = netdev_priv(dev); | |
3581 | struct sockaddr *addr = p; | |
3582 | ||
3583 | if (!is_valid_ether_addr(addr->sa_data)) | |
3584 | return -EADDRNOTAVAIL; | |
3585 | ||
3586 | memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); | |
3587 | ||
3588 | rtl_rar_set(tp, dev->dev_addr); | |
3589 | ||
3590 | return 0; | |
3591 | } | |
3592 | ||
5f787a1a FR |
3593 | static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
3594 | { | |
3595 | struct rtl8169_private *tp = netdev_priv(dev); | |
3596 | struct mii_ioctl_data *data = if_mii(ifr); | |
3597 | ||
8b4ab28d FR |
3598 | return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV; |
3599 | } | |
5f787a1a | 3600 | |
cecb5fd7 FR |
3601 | static int rtl_xmii_ioctl(struct rtl8169_private *tp, |
3602 | struct mii_ioctl_data *data, int cmd) | |
8b4ab28d | 3603 | { |
5f787a1a FR |
3604 | switch (cmd) { |
3605 | case SIOCGMIIPHY: | |
3606 | data->phy_id = 32; /* Internal PHY */ | |
3607 | return 0; | |
3608 | ||
3609 | case SIOCGMIIREG: | |
4da19633 | 3610 | data->val_out = rtl_readphy(tp, data->reg_num & 0x1f); |
5f787a1a FR |
3611 | return 0; |
3612 | ||
3613 | case SIOCSMIIREG: | |
4da19633 | 3614 | rtl_writephy(tp, data->reg_num & 0x1f, data->val_in); |
5f787a1a FR |
3615 | return 0; |
3616 | } | |
3617 | return -EOPNOTSUPP; | |
3618 | } | |
3619 | ||
8b4ab28d FR |
3620 | static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd) |
3621 | { | |
3622 | return -EOPNOTSUPP; | |
3623 | } | |
3624 | ||
fbac58fc FR |
3625 | static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp) |
3626 | { | |
3627 | if (tp->features & RTL_FEATURE_MSI) { | |
3628 | pci_disable_msi(pdev); | |
3629 | tp->features &= ~RTL_FEATURE_MSI; | |
3630 | } | |
3631 | } | |
3632 | ||
c0e45c1c | 3633 | static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp) |
3634 | { | |
3635 | struct mdio_ops *ops = &tp->mdio_ops; | |
3636 | ||
3637 | switch (tp->mac_version) { | |
3638 | case RTL_GIGA_MAC_VER_27: | |
3639 | ops->write = r8168dp_1_mdio_write; | |
3640 | ops->read = r8168dp_1_mdio_read; | |
3641 | break; | |
e6de30d6 | 3642 | case RTL_GIGA_MAC_VER_28: |
4804b3b3 | 3643 | case RTL_GIGA_MAC_VER_31: |
e6de30d6 | 3644 | ops->write = r8168dp_2_mdio_write; |
3645 | ops->read = r8168dp_2_mdio_read; | |
3646 | break; | |
c0e45c1c | 3647 | default: |
3648 | ops->write = r8169_mdio_write; | |
3649 | ops->read = r8169_mdio_read; | |
3650 | break; | |
3651 | } | |
3652 | } | |
3653 | ||
649b3b8c | 3654 | static void rtl_wol_suspend_quirk(struct rtl8169_private *tp) |
3655 | { | |
3656 | void __iomem *ioaddr = tp->mmio_addr; | |
3657 | ||
3658 | switch (tp->mac_version) { | |
3659 | case RTL_GIGA_MAC_VER_29: | |
3660 | case RTL_GIGA_MAC_VER_30: | |
3661 | case RTL_GIGA_MAC_VER_32: | |
3662 | case RTL_GIGA_MAC_VER_33: | |
3663 | case RTL_GIGA_MAC_VER_34: | |
7e18dca1 | 3664 | case RTL_GIGA_MAC_VER_37: |
b3d7b2f2 | 3665 | case RTL_GIGA_MAC_VER_38: |
5598bfe5 | 3666 | case RTL_GIGA_MAC_VER_39: |
649b3b8c | 3667 | RTL_W32(RxConfig, RTL_R32(RxConfig) | |
3668 | AcceptBroadcast | AcceptMulticast | AcceptMyPhys); | |
3669 | break; | |
3670 | default: | |
3671 | break; | |
3672 | } | |
3673 | } | |
3674 | ||
3675 | static bool rtl_wol_pll_power_down(struct rtl8169_private *tp) | |
3676 | { | |
3677 | if (!(__rtl8169_get_wol(tp) & WAKE_ANY)) | |
3678 | return false; | |
3679 | ||
3680 | rtl_writephy(tp, 0x1f, 0x0000); | |
3681 | rtl_writephy(tp, MII_BMCR, 0x0000); | |
3682 | ||
3683 | rtl_wol_suspend_quirk(tp); | |
3684 | ||
3685 | return true; | |
3686 | } | |
3687 | ||
065c27c1 | 3688 | static void r810x_phy_power_down(struct rtl8169_private *tp) |
3689 | { | |
3690 | rtl_writephy(tp, 0x1f, 0x0000); | |
3691 | rtl_writephy(tp, MII_BMCR, BMCR_PDOWN); | |
3692 | } | |
3693 | ||
3694 | static void r810x_phy_power_up(struct rtl8169_private *tp) | |
3695 | { | |
3696 | rtl_writephy(tp, 0x1f, 0x0000); | |
3697 | rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE); | |
3698 | } | |
3699 | ||
3700 | static void r810x_pll_power_down(struct rtl8169_private *tp) | |
3701 | { | |
0004299a HW |
3702 | void __iomem *ioaddr = tp->mmio_addr; |
3703 | ||
649b3b8c | 3704 | if (rtl_wol_pll_power_down(tp)) |
065c27c1 | 3705 | return; |
065c27c1 | 3706 | |
3707 | r810x_phy_power_down(tp); | |
0004299a HW |
3708 | |
3709 | switch (tp->mac_version) { | |
3710 | case RTL_GIGA_MAC_VER_07: | |
3711 | case RTL_GIGA_MAC_VER_08: | |
3712 | case RTL_GIGA_MAC_VER_09: | |
3713 | case RTL_GIGA_MAC_VER_10: | |
3714 | case RTL_GIGA_MAC_VER_13: | |
3715 | case RTL_GIGA_MAC_VER_16: | |
3716 | break; | |
3717 | default: | |
3718 | RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80); | |
3719 | break; | |
3720 | } | |
065c27c1 | 3721 | } |
3722 | ||
3723 | static void r810x_pll_power_up(struct rtl8169_private *tp) | |
3724 | { | |
0004299a HW |
3725 | void __iomem *ioaddr = tp->mmio_addr; |
3726 | ||
065c27c1 | 3727 | r810x_phy_power_up(tp); |
0004299a HW |
3728 | |
3729 | switch (tp->mac_version) { | |
3730 | case RTL_GIGA_MAC_VER_07: | |
3731 | case RTL_GIGA_MAC_VER_08: | |
3732 | case RTL_GIGA_MAC_VER_09: | |
3733 | case RTL_GIGA_MAC_VER_10: | |
3734 | case RTL_GIGA_MAC_VER_13: | |
3735 | case RTL_GIGA_MAC_VER_16: | |
3736 | break; | |
3737 | default: | |
3738 | RTL_W8(PMCH, RTL_R8(PMCH) | 0x80); | |
3739 | break; | |
3740 | } | |
065c27c1 | 3741 | } |
3742 | ||
3743 | static void r8168_phy_power_up(struct rtl8169_private *tp) | |
3744 | { | |
3745 | rtl_writephy(tp, 0x1f, 0x0000); | |
01dc7fec | 3746 | switch (tp->mac_version) { |
3747 | case RTL_GIGA_MAC_VER_11: | |
3748 | case RTL_GIGA_MAC_VER_12: | |
3749 | case RTL_GIGA_MAC_VER_17: | |
3750 | case RTL_GIGA_MAC_VER_18: | |
3751 | case RTL_GIGA_MAC_VER_19: | |
3752 | case RTL_GIGA_MAC_VER_20: | |
3753 | case RTL_GIGA_MAC_VER_21: | |
3754 | case RTL_GIGA_MAC_VER_22: | |
3755 | case RTL_GIGA_MAC_VER_23: | |
3756 | case RTL_GIGA_MAC_VER_24: | |
3757 | case RTL_GIGA_MAC_VER_25: | |
3758 | case RTL_GIGA_MAC_VER_26: | |
3759 | case RTL_GIGA_MAC_VER_27: | |
3760 | case RTL_GIGA_MAC_VER_28: | |
3761 | case RTL_GIGA_MAC_VER_31: | |
3762 | rtl_writephy(tp, 0x0e, 0x0000); | |
3763 | break; | |
3764 | default: | |
3765 | break; | |
3766 | } | |
065c27c1 | 3767 | rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE); |
3768 | } | |
3769 | ||
3770 | static void r8168_phy_power_down(struct rtl8169_private *tp) | |
3771 | { | |
3772 | rtl_writephy(tp, 0x1f, 0x0000); | |
01dc7fec | 3773 | switch (tp->mac_version) { |
3774 | case RTL_GIGA_MAC_VER_32: | |
3775 | case RTL_GIGA_MAC_VER_33: | |
3776 | rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN); | |
3777 | break; | |
3778 | ||
3779 | case RTL_GIGA_MAC_VER_11: | |
3780 | case RTL_GIGA_MAC_VER_12: | |
3781 | case RTL_GIGA_MAC_VER_17: | |
3782 | case RTL_GIGA_MAC_VER_18: | |
3783 | case RTL_GIGA_MAC_VER_19: | |
3784 | case RTL_GIGA_MAC_VER_20: | |
3785 | case RTL_GIGA_MAC_VER_21: | |
3786 | case RTL_GIGA_MAC_VER_22: | |
3787 | case RTL_GIGA_MAC_VER_23: | |
3788 | case RTL_GIGA_MAC_VER_24: | |
3789 | case RTL_GIGA_MAC_VER_25: | |
3790 | case RTL_GIGA_MAC_VER_26: | |
3791 | case RTL_GIGA_MAC_VER_27: | |
3792 | case RTL_GIGA_MAC_VER_28: | |
3793 | case RTL_GIGA_MAC_VER_31: | |
3794 | rtl_writephy(tp, 0x0e, 0x0200); | |
3795 | default: | |
3796 | rtl_writephy(tp, MII_BMCR, BMCR_PDOWN); | |
3797 | break; | |
3798 | } | |
065c27c1 | 3799 | } |
3800 | ||
3801 | static void r8168_pll_power_down(struct rtl8169_private *tp) | |
3802 | { | |
3803 | void __iomem *ioaddr = tp->mmio_addr; | |
3804 | ||
cecb5fd7 FR |
3805 | if ((tp->mac_version == RTL_GIGA_MAC_VER_27 || |
3806 | tp->mac_version == RTL_GIGA_MAC_VER_28 || | |
3807 | tp->mac_version == RTL_GIGA_MAC_VER_31) && | |
4804b3b3 | 3808 | r8168dp_check_dash(tp)) { |
065c27c1 | 3809 | return; |
5d2e1957 | 3810 | } |
065c27c1 | 3811 | |
cecb5fd7 FR |
3812 | if ((tp->mac_version == RTL_GIGA_MAC_VER_23 || |
3813 | tp->mac_version == RTL_GIGA_MAC_VER_24) && | |
065c27c1 | 3814 | (RTL_R16(CPlusCmd) & ASF)) { |
3815 | return; | |
3816 | } | |
3817 | ||
01dc7fec | 3818 | if (tp->mac_version == RTL_GIGA_MAC_VER_32 || |
3819 | tp->mac_version == RTL_GIGA_MAC_VER_33) | |
fdf6fc06 | 3820 | rtl_ephy_write(tp, 0x19, 0xff64); |
01dc7fec | 3821 | |
649b3b8c | 3822 | if (rtl_wol_pll_power_down(tp)) |
065c27c1 | 3823 | return; |
065c27c1 | 3824 | |
3825 | r8168_phy_power_down(tp); | |
3826 | ||
3827 | switch (tp->mac_version) { | |
3828 | case RTL_GIGA_MAC_VER_25: | |
3829 | case RTL_GIGA_MAC_VER_26: | |
5d2e1957 HW |
3830 | case RTL_GIGA_MAC_VER_27: |
3831 | case RTL_GIGA_MAC_VER_28: | |
4804b3b3 | 3832 | case RTL_GIGA_MAC_VER_31: |
01dc7fec | 3833 | case RTL_GIGA_MAC_VER_32: |
3834 | case RTL_GIGA_MAC_VER_33: | |
065c27c1 | 3835 | RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80); |
3836 | break; | |
3837 | } | |
3838 | } | |
3839 | ||
3840 | static void r8168_pll_power_up(struct rtl8169_private *tp) | |
3841 | { | |
3842 | void __iomem *ioaddr = tp->mmio_addr; | |
3843 | ||
065c27c1 | 3844 | switch (tp->mac_version) { |
3845 | case RTL_GIGA_MAC_VER_25: | |
3846 | case RTL_GIGA_MAC_VER_26: | |
5d2e1957 HW |
3847 | case RTL_GIGA_MAC_VER_27: |
3848 | case RTL_GIGA_MAC_VER_28: | |
4804b3b3 | 3849 | case RTL_GIGA_MAC_VER_31: |
01dc7fec | 3850 | case RTL_GIGA_MAC_VER_32: |
3851 | case RTL_GIGA_MAC_VER_33: | |
065c27c1 | 3852 | RTL_W8(PMCH, RTL_R8(PMCH) | 0x80); |
3853 | break; | |
3854 | } | |
3855 | ||
3856 | r8168_phy_power_up(tp); | |
3857 | } | |
3858 | ||
d58d46b5 FR |
3859 | static void rtl_generic_op(struct rtl8169_private *tp, |
3860 | void (*op)(struct rtl8169_private *)) | |
065c27c1 | 3861 | { |
3862 | if (op) | |
3863 | op(tp); | |
3864 | } | |
3865 | ||
3866 | static void rtl_pll_power_down(struct rtl8169_private *tp) | |
3867 | { | |
d58d46b5 | 3868 | rtl_generic_op(tp, tp->pll_power_ops.down); |
065c27c1 | 3869 | } |
3870 | ||
3871 | static void rtl_pll_power_up(struct rtl8169_private *tp) | |
3872 | { | |
d58d46b5 | 3873 | rtl_generic_op(tp, tp->pll_power_ops.up); |
065c27c1 | 3874 | } |
3875 | ||
3876 | static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp) | |
3877 | { | |
3878 | struct pll_power_ops *ops = &tp->pll_power_ops; | |
3879 | ||
3880 | switch (tp->mac_version) { | |
3881 | case RTL_GIGA_MAC_VER_07: | |
3882 | case RTL_GIGA_MAC_VER_08: | |
3883 | case RTL_GIGA_MAC_VER_09: | |
3884 | case RTL_GIGA_MAC_VER_10: | |
3885 | case RTL_GIGA_MAC_VER_16: | |
5a5e4443 HW |
3886 | case RTL_GIGA_MAC_VER_29: |
3887 | case RTL_GIGA_MAC_VER_30: | |
7e18dca1 | 3888 | case RTL_GIGA_MAC_VER_37: |
5598bfe5 | 3889 | case RTL_GIGA_MAC_VER_39: |
065c27c1 | 3890 | ops->down = r810x_pll_power_down; |
3891 | ops->up = r810x_pll_power_up; | |
3892 | break; | |
3893 | ||
3894 | case RTL_GIGA_MAC_VER_11: | |
3895 | case RTL_GIGA_MAC_VER_12: | |
3896 | case RTL_GIGA_MAC_VER_17: | |
3897 | case RTL_GIGA_MAC_VER_18: | |
3898 | case RTL_GIGA_MAC_VER_19: | |
3899 | case RTL_GIGA_MAC_VER_20: | |
3900 | case RTL_GIGA_MAC_VER_21: | |
3901 | case RTL_GIGA_MAC_VER_22: | |
3902 | case RTL_GIGA_MAC_VER_23: | |
3903 | case RTL_GIGA_MAC_VER_24: | |
3904 | case RTL_GIGA_MAC_VER_25: | |
3905 | case RTL_GIGA_MAC_VER_26: | |
3906 | case RTL_GIGA_MAC_VER_27: | |
e6de30d6 | 3907 | case RTL_GIGA_MAC_VER_28: |
4804b3b3 | 3908 | case RTL_GIGA_MAC_VER_31: |
01dc7fec | 3909 | case RTL_GIGA_MAC_VER_32: |
3910 | case RTL_GIGA_MAC_VER_33: | |
70090424 | 3911 | case RTL_GIGA_MAC_VER_34: |
c2218925 HW |
3912 | case RTL_GIGA_MAC_VER_35: |
3913 | case RTL_GIGA_MAC_VER_36: | |
b3d7b2f2 | 3914 | case RTL_GIGA_MAC_VER_38: |
065c27c1 | 3915 | ops->down = r8168_pll_power_down; |
3916 | ops->up = r8168_pll_power_up; | |
3917 | break; | |
3918 | ||
3919 | default: | |
3920 | ops->down = NULL; | |
3921 | ops->up = NULL; | |
3922 | break; | |
3923 | } | |
3924 | } | |
3925 | ||
e542a226 HW |
3926 | static void rtl_init_rxcfg(struct rtl8169_private *tp) |
3927 | { | |
3928 | void __iomem *ioaddr = tp->mmio_addr; | |
3929 | ||
3930 | switch (tp->mac_version) { | |
3931 | case RTL_GIGA_MAC_VER_01: | |
3932 | case RTL_GIGA_MAC_VER_02: | |
3933 | case RTL_GIGA_MAC_VER_03: | |
3934 | case RTL_GIGA_MAC_VER_04: | |
3935 | case RTL_GIGA_MAC_VER_05: | |
3936 | case RTL_GIGA_MAC_VER_06: | |
3937 | case RTL_GIGA_MAC_VER_10: | |
3938 | case RTL_GIGA_MAC_VER_11: | |
3939 | case RTL_GIGA_MAC_VER_12: | |
3940 | case RTL_GIGA_MAC_VER_13: | |
3941 | case RTL_GIGA_MAC_VER_14: | |
3942 | case RTL_GIGA_MAC_VER_15: | |
3943 | case RTL_GIGA_MAC_VER_16: | |
3944 | case RTL_GIGA_MAC_VER_17: | |
3945 | RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST); | |
3946 | break; | |
3947 | case RTL_GIGA_MAC_VER_18: | |
3948 | case RTL_GIGA_MAC_VER_19: | |
3949 | case RTL_GIGA_MAC_VER_20: | |
3950 | case RTL_GIGA_MAC_VER_21: | |
3951 | case RTL_GIGA_MAC_VER_22: | |
3952 | case RTL_GIGA_MAC_VER_23: | |
3953 | case RTL_GIGA_MAC_VER_24: | |
eb2dc35d | 3954 | case RTL_GIGA_MAC_VER_34: |
e542a226 HW |
3955 | RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST); |
3956 | break; | |
3957 | default: | |
3958 | RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST); | |
3959 | break; | |
3960 | } | |
3961 | } | |
3962 | ||
92fc43b4 HW |
3963 | static void rtl8169_init_ring_indexes(struct rtl8169_private *tp) |
3964 | { | |
3965 | tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0; | |
3966 | } | |
3967 | ||
d58d46b5 FR |
3968 | static void rtl_hw_jumbo_enable(struct rtl8169_private *tp) |
3969 | { | |
9c5028e9 | 3970 | void __iomem *ioaddr = tp->mmio_addr; |
3971 | ||
3972 | RTL_W8(Cfg9346, Cfg9346_Unlock); | |
d58d46b5 | 3973 | rtl_generic_op(tp, tp->jumbo_ops.enable); |
9c5028e9 | 3974 | RTL_W8(Cfg9346, Cfg9346_Lock); |
d58d46b5 FR |
3975 | } |
3976 | ||
3977 | static void rtl_hw_jumbo_disable(struct rtl8169_private *tp) | |
3978 | { | |
9c5028e9 | 3979 | void __iomem *ioaddr = tp->mmio_addr; |
3980 | ||
3981 | RTL_W8(Cfg9346, Cfg9346_Unlock); | |
d58d46b5 | 3982 | rtl_generic_op(tp, tp->jumbo_ops.disable); |
9c5028e9 | 3983 | RTL_W8(Cfg9346, Cfg9346_Lock); |
d58d46b5 FR |
3984 | } |
3985 | ||
3986 | static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp) | |
3987 | { | |
3988 | void __iomem *ioaddr = tp->mmio_addr; | |
3989 | ||
3990 | RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0); | |
3991 | RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1); | |
3992 | rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT); | |
3993 | } | |
3994 | ||
3995 | static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp) | |
3996 | { | |
3997 | void __iomem *ioaddr = tp->mmio_addr; | |
3998 | ||
3999 | RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0); | |
4000 | RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1); | |
4001 | rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
4002 | } | |
4003 | ||
4004 | static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp) | |
4005 | { | |
4006 | void __iomem *ioaddr = tp->mmio_addr; | |
4007 | ||
4008 | RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0); | |
4009 | } | |
4010 | ||
4011 | static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp) | |
4012 | { | |
4013 | void __iomem *ioaddr = tp->mmio_addr; | |
4014 | ||
4015 | RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0); | |
4016 | } | |
4017 | ||
4018 | static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp) | |
4019 | { | |
4020 | void __iomem *ioaddr = tp->mmio_addr; | |
d58d46b5 FR |
4021 | |
4022 | RTL_W8(MaxTxPacketSize, 0x3f); | |
4023 | RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0); | |
4024 | RTL_W8(Config4, RTL_R8(Config4) | 0x01); | |
4512ff9f | 4025 | rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT); |
d58d46b5 FR |
4026 | } |
4027 | ||
4028 | static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp) | |
4029 | { | |
4030 | void __iomem *ioaddr = tp->mmio_addr; | |
d58d46b5 FR |
4031 | |
4032 | RTL_W8(MaxTxPacketSize, 0x0c); | |
4033 | RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0); | |
4034 | RTL_W8(Config4, RTL_R8(Config4) & ~0x01); | |
4512ff9f | 4035 | rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT); |
d58d46b5 FR |
4036 | } |
4037 | ||
4038 | static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp) | |
4039 | { | |
4040 | rtl_tx_performance_tweak(tp->pci_dev, | |
4041 | (0x2 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN); | |
4042 | } | |
4043 | ||
4044 | static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp) | |
4045 | { | |
4046 | rtl_tx_performance_tweak(tp->pci_dev, | |
4047 | (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN); | |
4048 | } | |
4049 | ||
4050 | static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp) | |
4051 | { | |
4052 | void __iomem *ioaddr = tp->mmio_addr; | |
4053 | ||
4054 | r8168b_0_hw_jumbo_enable(tp); | |
4055 | ||
4056 | RTL_W8(Config4, RTL_R8(Config4) | (1 << 0)); | |
4057 | } | |
4058 | ||
4059 | static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp) | |
4060 | { | |
4061 | void __iomem *ioaddr = tp->mmio_addr; | |
4062 | ||
4063 | r8168b_0_hw_jumbo_disable(tp); | |
4064 | ||
4065 | RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0)); | |
4066 | } | |
4067 | ||
4068 | static void __devinit rtl_init_jumbo_ops(struct rtl8169_private *tp) | |
4069 | { | |
4070 | struct jumbo_ops *ops = &tp->jumbo_ops; | |
4071 | ||
4072 | switch (tp->mac_version) { | |
4073 | case RTL_GIGA_MAC_VER_11: | |
4074 | ops->disable = r8168b_0_hw_jumbo_disable; | |
4075 | ops->enable = r8168b_0_hw_jumbo_enable; | |
4076 | break; | |
4077 | case RTL_GIGA_MAC_VER_12: | |
4078 | case RTL_GIGA_MAC_VER_17: | |
4079 | ops->disable = r8168b_1_hw_jumbo_disable; | |
4080 | ops->enable = r8168b_1_hw_jumbo_enable; | |
4081 | break; | |
4082 | case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */ | |
4083 | case RTL_GIGA_MAC_VER_19: | |
4084 | case RTL_GIGA_MAC_VER_20: | |
4085 | case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */ | |
4086 | case RTL_GIGA_MAC_VER_22: | |
4087 | case RTL_GIGA_MAC_VER_23: | |
4088 | case RTL_GIGA_MAC_VER_24: | |
4089 | case RTL_GIGA_MAC_VER_25: | |
4090 | case RTL_GIGA_MAC_VER_26: | |
4091 | ops->disable = r8168c_hw_jumbo_disable; | |
4092 | ops->enable = r8168c_hw_jumbo_enable; | |
4093 | break; | |
4094 | case RTL_GIGA_MAC_VER_27: | |
4095 | case RTL_GIGA_MAC_VER_28: | |
4096 | ops->disable = r8168dp_hw_jumbo_disable; | |
4097 | ops->enable = r8168dp_hw_jumbo_enable; | |
4098 | break; | |
4099 | case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */ | |
4100 | case RTL_GIGA_MAC_VER_32: | |
4101 | case RTL_GIGA_MAC_VER_33: | |
4102 | case RTL_GIGA_MAC_VER_34: | |
4103 | ops->disable = r8168e_hw_jumbo_disable; | |
4104 | ops->enable = r8168e_hw_jumbo_enable; | |
4105 | break; | |
4106 | ||
4107 | /* | |
4108 | * No action needed for jumbo frames with 8169. | |
4109 | * No jumbo for 810x at all. | |
4110 | */ | |
4111 | default: | |
4112 | ops->disable = NULL; | |
4113 | ops->enable = NULL; | |
4114 | break; | |
4115 | } | |
4116 | } | |
4117 | ||
ffc46952 FR |
4118 | DECLARE_RTL_COND(rtl_chipcmd_cond) |
4119 | { | |
4120 | void __iomem *ioaddr = tp->mmio_addr; | |
4121 | ||
4122 | return RTL_R8(ChipCmd) & CmdReset; | |
4123 | } | |
4124 | ||
6f43adc8 FR |
4125 | static void rtl_hw_reset(struct rtl8169_private *tp) |
4126 | { | |
4127 | void __iomem *ioaddr = tp->mmio_addr; | |
6f43adc8 | 4128 | |
6f43adc8 FR |
4129 | RTL_W8(ChipCmd, CmdReset); |
4130 | ||
ffc46952 | 4131 | rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100); |
6f43adc8 FR |
4132 | } |
4133 | ||
b6ffd97f | 4134 | static void rtl_request_uncached_firmware(struct rtl8169_private *tp) |
953a12cc | 4135 | { |
b6ffd97f FR |
4136 | struct rtl_fw *rtl_fw; |
4137 | const char *name; | |
4138 | int rc = -ENOMEM; | |
953a12cc | 4139 | |
b6ffd97f FR |
4140 | name = rtl_lookup_firmware_name(tp); |
4141 | if (!name) | |
4142 | goto out_no_firmware; | |
953a12cc | 4143 | |
b6ffd97f FR |
4144 | rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL); |
4145 | if (!rtl_fw) | |
4146 | goto err_warn; | |
31bd204f | 4147 | |
b6ffd97f FR |
4148 | rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev); |
4149 | if (rc < 0) | |
4150 | goto err_free; | |
4151 | ||
fd112f2e FR |
4152 | rc = rtl_check_firmware(tp, rtl_fw); |
4153 | if (rc < 0) | |
4154 | goto err_release_firmware; | |
4155 | ||
b6ffd97f FR |
4156 | tp->rtl_fw = rtl_fw; |
4157 | out: | |
4158 | return; | |
4159 | ||
fd112f2e FR |
4160 | err_release_firmware: |
4161 | release_firmware(rtl_fw->fw); | |
b6ffd97f FR |
4162 | err_free: |
4163 | kfree(rtl_fw); | |
4164 | err_warn: | |
4165 | netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n", | |
4166 | name, rc); | |
4167 | out_no_firmware: | |
4168 | tp->rtl_fw = NULL; | |
4169 | goto out; | |
4170 | } | |
4171 | ||
4172 | static void rtl_request_firmware(struct rtl8169_private *tp) | |
4173 | { | |
4174 | if (IS_ERR(tp->rtl_fw)) | |
4175 | rtl_request_uncached_firmware(tp); | |
953a12cc FR |
4176 | } |
4177 | ||
92fc43b4 HW |
4178 | static void rtl_rx_close(struct rtl8169_private *tp) |
4179 | { | |
4180 | void __iomem *ioaddr = tp->mmio_addr; | |
92fc43b4 | 4181 | |
1687b566 | 4182 | RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK); |
92fc43b4 HW |
4183 | } |
4184 | ||
ffc46952 FR |
4185 | DECLARE_RTL_COND(rtl_npq_cond) |
4186 | { | |
4187 | void __iomem *ioaddr = tp->mmio_addr; | |
4188 | ||
4189 | return RTL_R8(TxPoll) & NPQ; | |
4190 | } | |
4191 | ||
4192 | DECLARE_RTL_COND(rtl_txcfg_empty_cond) | |
4193 | { | |
4194 | void __iomem *ioaddr = tp->mmio_addr; | |
4195 | ||
4196 | return RTL_R32(TxConfig) & TXCFG_EMPTY; | |
4197 | } | |
4198 | ||
e6de30d6 | 4199 | static void rtl8169_hw_reset(struct rtl8169_private *tp) |
1da177e4 | 4200 | { |
e6de30d6 | 4201 | void __iomem *ioaddr = tp->mmio_addr; |
4202 | ||
1da177e4 | 4203 | /* Disable interrupts */ |
811fd301 | 4204 | rtl8169_irq_mask_and_ack(tp); |
1da177e4 | 4205 | |
92fc43b4 HW |
4206 | rtl_rx_close(tp); |
4207 | ||
5d2e1957 | 4208 | if (tp->mac_version == RTL_GIGA_MAC_VER_27 || |
4804b3b3 | 4209 | tp->mac_version == RTL_GIGA_MAC_VER_28 || |
4210 | tp->mac_version == RTL_GIGA_MAC_VER_31) { | |
ffc46952 | 4211 | rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42); |
c2218925 HW |
4212 | } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 || |
4213 | tp->mac_version == RTL_GIGA_MAC_VER_35 || | |
7e18dca1 | 4214 | tp->mac_version == RTL_GIGA_MAC_VER_36 || |
b3d7b2f2 HW |
4215 | tp->mac_version == RTL_GIGA_MAC_VER_37 || |
4216 | tp->mac_version == RTL_GIGA_MAC_VER_38) { | |
c2b0c1e7 | 4217 | RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq); |
ffc46952 | 4218 | rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666); |
92fc43b4 HW |
4219 | } else { |
4220 | RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq); | |
4221 | udelay(100); | |
e6de30d6 | 4222 | } |
4223 | ||
92fc43b4 | 4224 | rtl_hw_reset(tp); |
1da177e4 LT |
4225 | } |
4226 | ||
7f796d83 | 4227 | static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp) |
9cb427b6 FR |
4228 | { |
4229 | void __iomem *ioaddr = tp->mmio_addr; | |
9cb427b6 FR |
4230 | |
4231 | /* Set DMA burst size and Interframe Gap Time */ | |
4232 | RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) | | |
4233 | (InterFrameGap << TxInterFrameGapShift)); | |
4234 | } | |
4235 | ||
07ce4064 | 4236 | static void rtl_hw_start(struct net_device *dev) |
1da177e4 LT |
4237 | { |
4238 | struct rtl8169_private *tp = netdev_priv(dev); | |
1da177e4 | 4239 | |
07ce4064 FR |
4240 | tp->hw_start(dev); |
4241 | ||
da78dbff | 4242 | rtl_irq_enable_all(tp); |
07ce4064 FR |
4243 | } |
4244 | ||
7f796d83 FR |
4245 | static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp, |
4246 | void __iomem *ioaddr) | |
4247 | { | |
4248 | /* | |
4249 | * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh | |
4250 | * register to be written before TxDescAddrLow to work. | |
4251 | * Switching from MMIO to I/O access fixes the issue as well. | |
4252 | */ | |
4253 | RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32); | |
284901a9 | 4254 | RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32)); |
7f796d83 | 4255 | RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32); |
284901a9 | 4256 | RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32)); |
7f796d83 FR |
4257 | } |
4258 | ||
4259 | static u16 rtl_rw_cpluscmd(void __iomem *ioaddr) | |
4260 | { | |
4261 | u16 cmd; | |
4262 | ||
4263 | cmd = RTL_R16(CPlusCmd); | |
4264 | RTL_W16(CPlusCmd, cmd); | |
4265 | return cmd; | |
4266 | } | |
4267 | ||
fdd7b4c3 | 4268 | static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz) |
7f796d83 FR |
4269 | { |
4270 | /* Low hurts. Let's disable the filtering. */ | |
207d6e87 | 4271 | RTL_W16(RxMaxSize, rx_buf_sz + 1); |
7f796d83 FR |
4272 | } |
4273 | ||
6dccd16b FR |
4274 | static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version) |
4275 | { | |
3744100e | 4276 | static const struct rtl_cfg2_info { |
6dccd16b FR |
4277 | u32 mac_version; |
4278 | u32 clk; | |
4279 | u32 val; | |
4280 | } cfg2_info [] = { | |
4281 | { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd | |
4282 | { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff }, | |
4283 | { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe | |
4284 | { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff } | |
3744100e FR |
4285 | }; |
4286 | const struct rtl_cfg2_info *p = cfg2_info; | |
6dccd16b FR |
4287 | unsigned int i; |
4288 | u32 clk; | |
4289 | ||
4290 | clk = RTL_R8(Config2) & PCI_Clock_66MHz; | |
cadf1855 | 4291 | for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) { |
6dccd16b FR |
4292 | if ((p->mac_version == mac_version) && (p->clk == clk)) { |
4293 | RTL_W32(0x7c, p->val); | |
4294 | break; | |
4295 | } | |
4296 | } | |
4297 | } | |
4298 | ||
e6b763ea FR |
4299 | static void rtl_set_rx_mode(struct net_device *dev) |
4300 | { | |
4301 | struct rtl8169_private *tp = netdev_priv(dev); | |
4302 | void __iomem *ioaddr = tp->mmio_addr; | |
4303 | u32 mc_filter[2]; /* Multicast hash filter */ | |
4304 | int rx_mode; | |
4305 | u32 tmp = 0; | |
4306 | ||
4307 | if (dev->flags & IFF_PROMISC) { | |
4308 | /* Unconditionally log net taps. */ | |
4309 | netif_notice(tp, link, dev, "Promiscuous mode enabled\n"); | |
4310 | rx_mode = | |
4311 | AcceptBroadcast | AcceptMulticast | AcceptMyPhys | | |
4312 | AcceptAllPhys; | |
4313 | mc_filter[1] = mc_filter[0] = 0xffffffff; | |
4314 | } else if ((netdev_mc_count(dev) > multicast_filter_limit) || | |
4315 | (dev->flags & IFF_ALLMULTI)) { | |
4316 | /* Too many to filter perfectly -- accept all multicasts. */ | |
4317 | rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys; | |
4318 | mc_filter[1] = mc_filter[0] = 0xffffffff; | |
4319 | } else { | |
4320 | struct netdev_hw_addr *ha; | |
4321 | ||
4322 | rx_mode = AcceptBroadcast | AcceptMyPhys; | |
4323 | mc_filter[1] = mc_filter[0] = 0; | |
4324 | netdev_for_each_mc_addr(ha, dev) { | |
4325 | int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; | |
4326 | mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); | |
4327 | rx_mode |= AcceptMulticast; | |
4328 | } | |
4329 | } | |
4330 | ||
4331 | if (dev->features & NETIF_F_RXALL) | |
4332 | rx_mode |= (AcceptErr | AcceptRunt); | |
4333 | ||
4334 | tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode; | |
4335 | ||
4336 | if (tp->mac_version > RTL_GIGA_MAC_VER_06) { | |
4337 | u32 data = mc_filter[0]; | |
4338 | ||
4339 | mc_filter[0] = swab32(mc_filter[1]); | |
4340 | mc_filter[1] = swab32(data); | |
4341 | } | |
4342 | ||
4343 | RTL_W32(MAR0 + 4, mc_filter[1]); | |
4344 | RTL_W32(MAR0 + 0, mc_filter[0]); | |
4345 | ||
4346 | RTL_W32(RxConfig, tmp); | |
4347 | } | |
4348 | ||
07ce4064 FR |
4349 | static void rtl_hw_start_8169(struct net_device *dev) |
4350 | { | |
4351 | struct rtl8169_private *tp = netdev_priv(dev); | |
4352 | void __iomem *ioaddr = tp->mmio_addr; | |
4353 | struct pci_dev *pdev = tp->pci_dev; | |
07ce4064 | 4354 | |
9cb427b6 FR |
4355 | if (tp->mac_version == RTL_GIGA_MAC_VER_05) { |
4356 | RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW); | |
4357 | pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08); | |
4358 | } | |
4359 | ||
1da177e4 | 4360 | RTL_W8(Cfg9346, Cfg9346_Unlock); |
cecb5fd7 FR |
4361 | if (tp->mac_version == RTL_GIGA_MAC_VER_01 || |
4362 | tp->mac_version == RTL_GIGA_MAC_VER_02 || | |
4363 | tp->mac_version == RTL_GIGA_MAC_VER_03 || | |
4364 | tp->mac_version == RTL_GIGA_MAC_VER_04) | |
9cb427b6 FR |
4365 | RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); |
4366 | ||
e542a226 HW |
4367 | rtl_init_rxcfg(tp); |
4368 | ||
f0298f81 | 4369 | RTL_W8(EarlyTxThres, NoEarlyTx); |
1da177e4 | 4370 | |
6f0333b8 | 4371 | rtl_set_rx_max_size(ioaddr, rx_buf_sz); |
1da177e4 | 4372 | |
cecb5fd7 FR |
4373 | if (tp->mac_version == RTL_GIGA_MAC_VER_01 || |
4374 | tp->mac_version == RTL_GIGA_MAC_VER_02 || | |
4375 | tp->mac_version == RTL_GIGA_MAC_VER_03 || | |
4376 | tp->mac_version == RTL_GIGA_MAC_VER_04) | |
c946b304 | 4377 | rtl_set_rx_tx_config_registers(tp); |
1da177e4 | 4378 | |
7f796d83 | 4379 | tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW; |
1da177e4 | 4380 | |
cecb5fd7 FR |
4381 | if (tp->mac_version == RTL_GIGA_MAC_VER_02 || |
4382 | tp->mac_version == RTL_GIGA_MAC_VER_03) { | |
06fa7358 | 4383 | dprintk("Set MAC Reg C+CR Offset 0xE0. " |
1da177e4 | 4384 | "Bit-3 and bit-14 MUST be 1\n"); |
bcf0bf90 | 4385 | tp->cp_cmd |= (1 << 14); |
1da177e4 LT |
4386 | } |
4387 | ||
bcf0bf90 FR |
4388 | RTL_W16(CPlusCmd, tp->cp_cmd); |
4389 | ||
6dccd16b FR |
4390 | rtl8169_set_magic_reg(ioaddr, tp->mac_version); |
4391 | ||
1da177e4 LT |
4392 | /* |
4393 | * Undocumented corner. Supposedly: | |
4394 | * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets | |
4395 | */ | |
4396 | RTL_W16(IntrMitigate, 0x0000); | |
4397 | ||
7f796d83 | 4398 | rtl_set_rx_tx_desc_registers(tp, ioaddr); |
9cb427b6 | 4399 | |
cecb5fd7 FR |
4400 | if (tp->mac_version != RTL_GIGA_MAC_VER_01 && |
4401 | tp->mac_version != RTL_GIGA_MAC_VER_02 && | |
4402 | tp->mac_version != RTL_GIGA_MAC_VER_03 && | |
4403 | tp->mac_version != RTL_GIGA_MAC_VER_04) { | |
c946b304 FR |
4404 | RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); |
4405 | rtl_set_rx_tx_config_registers(tp); | |
4406 | } | |
4407 | ||
1da177e4 | 4408 | RTL_W8(Cfg9346, Cfg9346_Lock); |
b518fa8e FR |
4409 | |
4410 | /* Initially a 10 us delay. Turned it into a PCI commit. - FR */ | |
4411 | RTL_R8(IntrMask); | |
1da177e4 LT |
4412 | |
4413 | RTL_W32(RxMissed, 0); | |
4414 | ||
07ce4064 | 4415 | rtl_set_rx_mode(dev); |
1da177e4 LT |
4416 | |
4417 | /* no early-rx interrupts */ | |
4418 | RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000); | |
07ce4064 | 4419 | } |
1da177e4 | 4420 | |
beb1fe18 HW |
4421 | static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value) |
4422 | { | |
4423 | if (tp->csi_ops.write) | |
52989f0e | 4424 | tp->csi_ops.write(tp, addr, value); |
beb1fe18 HW |
4425 | } |
4426 | ||
4427 | static u32 rtl_csi_read(struct rtl8169_private *tp, int addr) | |
4428 | { | |
52989f0e | 4429 | return tp->csi_ops.read ? tp->csi_ops.read(tp, addr) : ~0; |
beb1fe18 HW |
4430 | } |
4431 | ||
4432 | static void rtl_csi_access_enable(struct rtl8169_private *tp, u32 bits) | |
dacf8154 FR |
4433 | { |
4434 | u32 csi; | |
4435 | ||
beb1fe18 HW |
4436 | csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff; |
4437 | rtl_csi_write(tp, 0x070c, csi | bits); | |
4438 | } | |
4439 | ||
4440 | static void rtl_csi_access_enable_1(struct rtl8169_private *tp) | |
4441 | { | |
4442 | rtl_csi_access_enable(tp, 0x17000000); | |
650e8d5d | 4443 | } |
4444 | ||
beb1fe18 | 4445 | static void rtl_csi_access_enable_2(struct rtl8169_private *tp) |
e6de30d6 | 4446 | { |
beb1fe18 | 4447 | rtl_csi_access_enable(tp, 0x27000000); |
e6de30d6 | 4448 | } |
4449 | ||
ffc46952 FR |
4450 | DECLARE_RTL_COND(rtl_csiar_cond) |
4451 | { | |
4452 | void __iomem *ioaddr = tp->mmio_addr; | |
4453 | ||
4454 | return RTL_R32(CSIAR) & CSIAR_FLAG; | |
4455 | } | |
4456 | ||
52989f0e | 4457 | static void r8169_csi_write(struct rtl8169_private *tp, int addr, int value) |
650e8d5d | 4458 | { |
52989f0e | 4459 | void __iomem *ioaddr = tp->mmio_addr; |
beb1fe18 HW |
4460 | |
4461 | RTL_W32(CSIDR, value); | |
4462 | RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | | |
4463 | CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT); | |
4464 | ||
ffc46952 | 4465 | rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100); |
beb1fe18 HW |
4466 | } |
4467 | ||
52989f0e | 4468 | static u32 r8169_csi_read(struct rtl8169_private *tp, int addr) |
beb1fe18 | 4469 | { |
52989f0e | 4470 | void __iomem *ioaddr = tp->mmio_addr; |
beb1fe18 HW |
4471 | |
4472 | RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | | |
4473 | CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT); | |
4474 | ||
ffc46952 FR |
4475 | return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ? |
4476 | RTL_R32(CSIDR) : ~0; | |
beb1fe18 HW |
4477 | } |
4478 | ||
52989f0e | 4479 | static void r8402_csi_write(struct rtl8169_private *tp, int addr, int value) |
7e18dca1 | 4480 | { |
52989f0e | 4481 | void __iomem *ioaddr = tp->mmio_addr; |
7e18dca1 HW |
4482 | |
4483 | RTL_W32(CSIDR, value); | |
4484 | RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | | |
4485 | CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT | | |
4486 | CSIAR_FUNC_NIC); | |
4487 | ||
ffc46952 | 4488 | rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100); |
7e18dca1 HW |
4489 | } |
4490 | ||
52989f0e | 4491 | static u32 r8402_csi_read(struct rtl8169_private *tp, int addr) |
7e18dca1 | 4492 | { |
52989f0e | 4493 | void __iomem *ioaddr = tp->mmio_addr; |
7e18dca1 HW |
4494 | |
4495 | RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC | | |
4496 | CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT); | |
4497 | ||
ffc46952 FR |
4498 | return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ? |
4499 | RTL_R32(CSIDR) : ~0; | |
7e18dca1 HW |
4500 | } |
4501 | ||
beb1fe18 HW |
4502 | static void __devinit rtl_init_csi_ops(struct rtl8169_private *tp) |
4503 | { | |
4504 | struct csi_ops *ops = &tp->csi_ops; | |
4505 | ||
4506 | switch (tp->mac_version) { | |
4507 | case RTL_GIGA_MAC_VER_01: | |
4508 | case RTL_GIGA_MAC_VER_02: | |
4509 | case RTL_GIGA_MAC_VER_03: | |
4510 | case RTL_GIGA_MAC_VER_04: | |
4511 | case RTL_GIGA_MAC_VER_05: | |
4512 | case RTL_GIGA_MAC_VER_06: | |
4513 | case RTL_GIGA_MAC_VER_10: | |
4514 | case RTL_GIGA_MAC_VER_11: | |
4515 | case RTL_GIGA_MAC_VER_12: | |
4516 | case RTL_GIGA_MAC_VER_13: | |
4517 | case RTL_GIGA_MAC_VER_14: | |
4518 | case RTL_GIGA_MAC_VER_15: | |
4519 | case RTL_GIGA_MAC_VER_16: | |
4520 | case RTL_GIGA_MAC_VER_17: | |
4521 | ops->write = NULL; | |
4522 | ops->read = NULL; | |
4523 | break; | |
4524 | ||
7e18dca1 | 4525 | case RTL_GIGA_MAC_VER_37: |
b3d7b2f2 | 4526 | case RTL_GIGA_MAC_VER_38: |
7e18dca1 HW |
4527 | ops->write = r8402_csi_write; |
4528 | ops->read = r8402_csi_read; | |
4529 | break; | |
4530 | ||
beb1fe18 HW |
4531 | default: |
4532 | ops->write = r8169_csi_write; | |
4533 | ops->read = r8169_csi_read; | |
4534 | break; | |
4535 | } | |
dacf8154 FR |
4536 | } |
4537 | ||
4538 | struct ephy_info { | |
4539 | unsigned int offset; | |
4540 | u16 mask; | |
4541 | u16 bits; | |
4542 | }; | |
4543 | ||
fdf6fc06 FR |
4544 | static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e, |
4545 | int len) | |
dacf8154 FR |
4546 | { |
4547 | u16 w; | |
4548 | ||
4549 | while (len-- > 0) { | |
fdf6fc06 FR |
4550 | w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits; |
4551 | rtl_ephy_write(tp, e->offset, w); | |
dacf8154 FR |
4552 | e++; |
4553 | } | |
4554 | } | |
4555 | ||
b726e493 FR |
4556 | static void rtl_disable_clock_request(struct pci_dev *pdev) |
4557 | { | |
e44daade | 4558 | int cap = pci_pcie_cap(pdev); |
b726e493 FR |
4559 | |
4560 | if (cap) { | |
4561 | u16 ctl; | |
4562 | ||
4563 | pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl); | |
4564 | ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN; | |
4565 | pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl); | |
4566 | } | |
4567 | } | |
4568 | ||
e6de30d6 | 4569 | static void rtl_enable_clock_request(struct pci_dev *pdev) |
4570 | { | |
e44daade | 4571 | int cap = pci_pcie_cap(pdev); |
e6de30d6 | 4572 | |
4573 | if (cap) { | |
4574 | u16 ctl; | |
4575 | ||
4576 | pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl); | |
4577 | ctl |= PCI_EXP_LNKCTL_CLKREQ_EN; | |
4578 | pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl); | |
4579 | } | |
4580 | } | |
4581 | ||
b726e493 FR |
4582 | #define R8168_CPCMD_QUIRK_MASK (\ |
4583 | EnableBist | \ | |
4584 | Mac_dbgo_oe | \ | |
4585 | Force_half_dup | \ | |
4586 | Force_rxflow_en | \ | |
4587 | Force_txflow_en | \ | |
4588 | Cxpl_dbg_sel | \ | |
4589 | ASF | \ | |
4590 | PktCntrDisable | \ | |
4591 | Mac_dbgo_sel) | |
4592 | ||
beb1fe18 | 4593 | static void rtl_hw_start_8168bb(struct rtl8169_private *tp) |
219a1e9d | 4594 | { |
beb1fe18 HW |
4595 | void __iomem *ioaddr = tp->mmio_addr; |
4596 | struct pci_dev *pdev = tp->pci_dev; | |
4597 | ||
b726e493 FR |
4598 | RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); |
4599 | ||
4600 | RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); | |
4601 | ||
2e68ae44 FR |
4602 | rtl_tx_performance_tweak(pdev, |
4603 | (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN); | |
219a1e9d FR |
4604 | } |
4605 | ||
beb1fe18 | 4606 | static void rtl_hw_start_8168bef(struct rtl8169_private *tp) |
219a1e9d | 4607 | { |
beb1fe18 HW |
4608 | void __iomem *ioaddr = tp->mmio_addr; |
4609 | ||
4610 | rtl_hw_start_8168bb(tp); | |
b726e493 | 4611 | |
f0298f81 | 4612 | RTL_W8(MaxTxPacketSize, TxPacketMax); |
b726e493 FR |
4613 | |
4614 | RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0)); | |
219a1e9d FR |
4615 | } |
4616 | ||
beb1fe18 | 4617 | static void __rtl_hw_start_8168cp(struct rtl8169_private *tp) |
219a1e9d | 4618 | { |
beb1fe18 HW |
4619 | void __iomem *ioaddr = tp->mmio_addr; |
4620 | struct pci_dev *pdev = tp->pci_dev; | |
4621 | ||
b726e493 FR |
4622 | RTL_W8(Config1, RTL_R8(Config1) | Speed_down); |
4623 | ||
4624 | RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); | |
4625 | ||
219a1e9d | 4626 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); |
b726e493 FR |
4627 | |
4628 | rtl_disable_clock_request(pdev); | |
4629 | ||
4630 | RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); | |
219a1e9d FR |
4631 | } |
4632 | ||
beb1fe18 | 4633 | static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp) |
219a1e9d | 4634 | { |
350f7596 | 4635 | static const struct ephy_info e_info_8168cp[] = { |
b726e493 FR |
4636 | { 0x01, 0, 0x0001 }, |
4637 | { 0x02, 0x0800, 0x1000 }, | |
4638 | { 0x03, 0, 0x0042 }, | |
4639 | { 0x06, 0x0080, 0x0000 }, | |
4640 | { 0x07, 0, 0x2000 } | |
4641 | }; | |
4642 | ||
beb1fe18 | 4643 | rtl_csi_access_enable_2(tp); |
b726e493 | 4644 | |
fdf6fc06 | 4645 | rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp)); |
b726e493 | 4646 | |
beb1fe18 | 4647 | __rtl_hw_start_8168cp(tp); |
219a1e9d FR |
4648 | } |
4649 | ||
beb1fe18 | 4650 | static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp) |
ef3386f0 | 4651 | { |
beb1fe18 HW |
4652 | void __iomem *ioaddr = tp->mmio_addr; |
4653 | struct pci_dev *pdev = tp->pci_dev; | |
4654 | ||
4655 | rtl_csi_access_enable_2(tp); | |
ef3386f0 FR |
4656 | |
4657 | RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); | |
4658 | ||
4659 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
4660 | ||
4661 | RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); | |
4662 | } | |
4663 | ||
beb1fe18 | 4664 | static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp) |
7f3e3d3a | 4665 | { |
beb1fe18 HW |
4666 | void __iomem *ioaddr = tp->mmio_addr; |
4667 | struct pci_dev *pdev = tp->pci_dev; | |
4668 | ||
4669 | rtl_csi_access_enable_2(tp); | |
7f3e3d3a FR |
4670 | |
4671 | RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); | |
4672 | ||
4673 | /* Magic. */ | |
4674 | RTL_W8(DBG_REG, 0x20); | |
4675 | ||
f0298f81 | 4676 | RTL_W8(MaxTxPacketSize, TxPacketMax); |
7f3e3d3a FR |
4677 | |
4678 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
4679 | ||
4680 | RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); | |
4681 | } | |
4682 | ||
beb1fe18 | 4683 | static void rtl_hw_start_8168c_1(struct rtl8169_private *tp) |
219a1e9d | 4684 | { |
beb1fe18 | 4685 | void __iomem *ioaddr = tp->mmio_addr; |
350f7596 | 4686 | static const struct ephy_info e_info_8168c_1[] = { |
b726e493 FR |
4687 | { 0x02, 0x0800, 0x1000 }, |
4688 | { 0x03, 0, 0x0002 }, | |
4689 | { 0x06, 0x0080, 0x0000 } | |
4690 | }; | |
4691 | ||
beb1fe18 | 4692 | rtl_csi_access_enable_2(tp); |
b726e493 FR |
4693 | |
4694 | RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2); | |
4695 | ||
fdf6fc06 | 4696 | rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1)); |
b726e493 | 4697 | |
beb1fe18 | 4698 | __rtl_hw_start_8168cp(tp); |
219a1e9d FR |
4699 | } |
4700 | ||
beb1fe18 | 4701 | static void rtl_hw_start_8168c_2(struct rtl8169_private *tp) |
219a1e9d | 4702 | { |
350f7596 | 4703 | static const struct ephy_info e_info_8168c_2[] = { |
b726e493 FR |
4704 | { 0x01, 0, 0x0001 }, |
4705 | { 0x03, 0x0400, 0x0220 } | |
4706 | }; | |
4707 | ||
beb1fe18 | 4708 | rtl_csi_access_enable_2(tp); |
b726e493 | 4709 | |
fdf6fc06 | 4710 | rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2)); |
b726e493 | 4711 | |
beb1fe18 | 4712 | __rtl_hw_start_8168cp(tp); |
219a1e9d FR |
4713 | } |
4714 | ||
beb1fe18 | 4715 | static void rtl_hw_start_8168c_3(struct rtl8169_private *tp) |
197ff761 | 4716 | { |
beb1fe18 | 4717 | rtl_hw_start_8168c_2(tp); |
197ff761 FR |
4718 | } |
4719 | ||
beb1fe18 | 4720 | static void rtl_hw_start_8168c_4(struct rtl8169_private *tp) |
6fb07058 | 4721 | { |
beb1fe18 | 4722 | rtl_csi_access_enable_2(tp); |
6fb07058 | 4723 | |
beb1fe18 | 4724 | __rtl_hw_start_8168cp(tp); |
6fb07058 FR |
4725 | } |
4726 | ||
beb1fe18 | 4727 | static void rtl_hw_start_8168d(struct rtl8169_private *tp) |
5b538df9 | 4728 | { |
beb1fe18 HW |
4729 | void __iomem *ioaddr = tp->mmio_addr; |
4730 | struct pci_dev *pdev = tp->pci_dev; | |
4731 | ||
4732 | rtl_csi_access_enable_2(tp); | |
5b538df9 FR |
4733 | |
4734 | rtl_disable_clock_request(pdev); | |
4735 | ||
f0298f81 | 4736 | RTL_W8(MaxTxPacketSize, TxPacketMax); |
5b538df9 FR |
4737 | |
4738 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
4739 | ||
4740 | RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); | |
4741 | } | |
4742 | ||
beb1fe18 | 4743 | static void rtl_hw_start_8168dp(struct rtl8169_private *tp) |
4804b3b3 | 4744 | { |
beb1fe18 HW |
4745 | void __iomem *ioaddr = tp->mmio_addr; |
4746 | struct pci_dev *pdev = tp->pci_dev; | |
4747 | ||
4748 | rtl_csi_access_enable_1(tp); | |
4804b3b3 | 4749 | |
4750 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
4751 | ||
4752 | RTL_W8(MaxTxPacketSize, TxPacketMax); | |
4753 | ||
4754 | rtl_disable_clock_request(pdev); | |
4755 | } | |
4756 | ||
beb1fe18 | 4757 | static void rtl_hw_start_8168d_4(struct rtl8169_private *tp) |
e6de30d6 | 4758 | { |
beb1fe18 HW |
4759 | void __iomem *ioaddr = tp->mmio_addr; |
4760 | struct pci_dev *pdev = tp->pci_dev; | |
e6de30d6 | 4761 | static const struct ephy_info e_info_8168d_4[] = { |
4762 | { 0x0b, ~0, 0x48 }, | |
4763 | { 0x19, 0x20, 0x50 }, | |
4764 | { 0x0c, ~0, 0x20 } | |
4765 | }; | |
4766 | int i; | |
4767 | ||
beb1fe18 | 4768 | rtl_csi_access_enable_1(tp); |
e6de30d6 | 4769 | |
4770 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
4771 | ||
4772 | RTL_W8(MaxTxPacketSize, TxPacketMax); | |
4773 | ||
4774 | for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) { | |
4775 | const struct ephy_info *e = e_info_8168d_4 + i; | |
4776 | u16 w; | |
4777 | ||
fdf6fc06 FR |
4778 | w = rtl_ephy_read(tp, e->offset); |
4779 | rtl_ephy_write(tp, 0x03, (w & e->mask) | e->bits); | |
e6de30d6 | 4780 | } |
4781 | ||
4782 | rtl_enable_clock_request(pdev); | |
4783 | } | |
4784 | ||
beb1fe18 | 4785 | static void rtl_hw_start_8168e_1(struct rtl8169_private *tp) |
01dc7fec | 4786 | { |
beb1fe18 HW |
4787 | void __iomem *ioaddr = tp->mmio_addr; |
4788 | struct pci_dev *pdev = tp->pci_dev; | |
70090424 | 4789 | static const struct ephy_info e_info_8168e_1[] = { |
01dc7fec | 4790 | { 0x00, 0x0200, 0x0100 }, |
4791 | { 0x00, 0x0000, 0x0004 }, | |
4792 | { 0x06, 0x0002, 0x0001 }, | |
4793 | { 0x06, 0x0000, 0x0030 }, | |
4794 | { 0x07, 0x0000, 0x2000 }, | |
4795 | { 0x00, 0x0000, 0x0020 }, | |
4796 | { 0x03, 0x5800, 0x2000 }, | |
4797 | { 0x03, 0x0000, 0x0001 }, | |
4798 | { 0x01, 0x0800, 0x1000 }, | |
4799 | { 0x07, 0x0000, 0x4000 }, | |
4800 | { 0x1e, 0x0000, 0x2000 }, | |
4801 | { 0x19, 0xffff, 0xfe6c }, | |
4802 | { 0x0a, 0x0000, 0x0040 } | |
4803 | }; | |
4804 | ||
beb1fe18 | 4805 | rtl_csi_access_enable_2(tp); |
01dc7fec | 4806 | |
fdf6fc06 | 4807 | rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1)); |
01dc7fec | 4808 | |
4809 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
4810 | ||
4811 | RTL_W8(MaxTxPacketSize, TxPacketMax); | |
4812 | ||
4813 | rtl_disable_clock_request(pdev); | |
4814 | ||
4815 | /* Reset tx FIFO pointer */ | |
cecb5fd7 FR |
4816 | RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST); |
4817 | RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST); | |
01dc7fec | 4818 | |
cecb5fd7 | 4819 | RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en); |
01dc7fec | 4820 | } |
4821 | ||
beb1fe18 | 4822 | static void rtl_hw_start_8168e_2(struct rtl8169_private *tp) |
70090424 | 4823 | { |
beb1fe18 HW |
4824 | void __iomem *ioaddr = tp->mmio_addr; |
4825 | struct pci_dev *pdev = tp->pci_dev; | |
70090424 HW |
4826 | static const struct ephy_info e_info_8168e_2[] = { |
4827 | { 0x09, 0x0000, 0x0080 }, | |
4828 | { 0x19, 0x0000, 0x0224 } | |
4829 | }; | |
4830 | ||
beb1fe18 | 4831 | rtl_csi_access_enable_1(tp); |
70090424 | 4832 | |
fdf6fc06 | 4833 | rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2)); |
70090424 HW |
4834 | |
4835 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
4836 | ||
fdf6fc06 FR |
4837 | rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); |
4838 | rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); | |
4839 | rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC); | |
4840 | rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC); | |
4841 | rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC); | |
4842 | rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC); | |
4843 | rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC); | |
4844 | rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC); | |
70090424 | 4845 | |
3090bd9a | 4846 | RTL_W8(MaxTxPacketSize, EarlySize); |
70090424 HW |
4847 | |
4848 | rtl_disable_clock_request(pdev); | |
4849 | ||
4850 | RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO); | |
4851 | RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB); | |
4852 | ||
4853 | /* Adjust EEE LED frequency */ | |
4854 | RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07); | |
4855 | ||
4856 | RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN); | |
4857 | RTL_W32(MISC, RTL_R32(MISC) | PWM_EN); | |
4858 | RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en); | |
4859 | } | |
4860 | ||
5f886e08 | 4861 | static void rtl_hw_start_8168f(struct rtl8169_private *tp) |
c2218925 | 4862 | { |
beb1fe18 HW |
4863 | void __iomem *ioaddr = tp->mmio_addr; |
4864 | struct pci_dev *pdev = tp->pci_dev; | |
c2218925 | 4865 | |
5f886e08 | 4866 | rtl_csi_access_enable_2(tp); |
c2218925 HW |
4867 | |
4868 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
4869 | ||
fdf6fc06 FR |
4870 | rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); |
4871 | rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); | |
4872 | rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC); | |
4873 | rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC); | |
4874 | rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC); | |
4875 | rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC); | |
4876 | rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC); | |
4877 | rtl_w1w0_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC); | |
4878 | rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC); | |
4879 | rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC); | |
c2218925 HW |
4880 | |
4881 | RTL_W8(MaxTxPacketSize, EarlySize); | |
4882 | ||
4883 | rtl_disable_clock_request(pdev); | |
4884 | ||
4885 | RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO); | |
4886 | RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB); | |
c2218925 HW |
4887 | RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN); |
4888 | RTL_W32(MISC, RTL_R32(MISC) | PWM_EN); | |
4889 | RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en); | |
4890 | } | |
4891 | ||
5f886e08 HW |
4892 | static void rtl_hw_start_8168f_1(struct rtl8169_private *tp) |
4893 | { | |
4894 | void __iomem *ioaddr = tp->mmio_addr; | |
4895 | static const struct ephy_info e_info_8168f_1[] = { | |
4896 | { 0x06, 0x00c0, 0x0020 }, | |
4897 | { 0x08, 0x0001, 0x0002 }, | |
4898 | { 0x09, 0x0000, 0x0080 }, | |
4899 | { 0x19, 0x0000, 0x0224 } | |
4900 | }; | |
4901 | ||
4902 | rtl_hw_start_8168f(tp); | |
4903 | ||
fdf6fc06 | 4904 | rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1)); |
5f886e08 | 4905 | |
fdf6fc06 | 4906 | rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC); |
5f886e08 HW |
4907 | |
4908 | /* Adjust EEE LED frequency */ | |
4909 | RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07); | |
4910 | } | |
4911 | ||
b3d7b2f2 HW |
4912 | static void rtl_hw_start_8411(struct rtl8169_private *tp) |
4913 | { | |
b3d7b2f2 HW |
4914 | static const struct ephy_info e_info_8168f_1[] = { |
4915 | { 0x06, 0x00c0, 0x0020 }, | |
4916 | { 0x0f, 0xffff, 0x5200 }, | |
4917 | { 0x1e, 0x0000, 0x4000 }, | |
4918 | { 0x19, 0x0000, 0x0224 } | |
4919 | }; | |
4920 | ||
4921 | rtl_hw_start_8168f(tp); | |
4922 | ||
fdf6fc06 | 4923 | rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1)); |
b3d7b2f2 | 4924 | |
fdf6fc06 | 4925 | rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC); |
b3d7b2f2 HW |
4926 | } |
4927 | ||
07ce4064 FR |
4928 | static void rtl_hw_start_8168(struct net_device *dev) |
4929 | { | |
2dd99530 FR |
4930 | struct rtl8169_private *tp = netdev_priv(dev); |
4931 | void __iomem *ioaddr = tp->mmio_addr; | |
4932 | ||
4933 | RTL_W8(Cfg9346, Cfg9346_Unlock); | |
4934 | ||
f0298f81 | 4935 | RTL_W8(MaxTxPacketSize, TxPacketMax); |
2dd99530 | 4936 | |
6f0333b8 | 4937 | rtl_set_rx_max_size(ioaddr, rx_buf_sz); |
2dd99530 | 4938 | |
0e485150 | 4939 | tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1; |
2dd99530 FR |
4940 | |
4941 | RTL_W16(CPlusCmd, tp->cp_cmd); | |
4942 | ||
0e485150 | 4943 | RTL_W16(IntrMitigate, 0x5151); |
2dd99530 | 4944 | |
0e485150 | 4945 | /* Work around for RxFIFO overflow. */ |
811fd301 | 4946 | if (tp->mac_version == RTL_GIGA_MAC_VER_11) { |
da78dbff FR |
4947 | tp->event_slow |= RxFIFOOver | PCSTimeout; |
4948 | tp->event_slow &= ~RxOverflow; | |
0e485150 FR |
4949 | } |
4950 | ||
4951 | rtl_set_rx_tx_desc_registers(tp, ioaddr); | |
2dd99530 | 4952 | |
b8363901 FR |
4953 | rtl_set_rx_mode(dev); |
4954 | ||
4955 | RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) | | |
4956 | (InterFrameGap << TxInterFrameGapShift)); | |
2dd99530 FR |
4957 | |
4958 | RTL_R8(IntrMask); | |
4959 | ||
219a1e9d FR |
4960 | switch (tp->mac_version) { |
4961 | case RTL_GIGA_MAC_VER_11: | |
beb1fe18 | 4962 | rtl_hw_start_8168bb(tp); |
4804b3b3 | 4963 | break; |
219a1e9d FR |
4964 | |
4965 | case RTL_GIGA_MAC_VER_12: | |
4966 | case RTL_GIGA_MAC_VER_17: | |
beb1fe18 | 4967 | rtl_hw_start_8168bef(tp); |
4804b3b3 | 4968 | break; |
219a1e9d FR |
4969 | |
4970 | case RTL_GIGA_MAC_VER_18: | |
beb1fe18 | 4971 | rtl_hw_start_8168cp_1(tp); |
4804b3b3 | 4972 | break; |
219a1e9d FR |
4973 | |
4974 | case RTL_GIGA_MAC_VER_19: | |
beb1fe18 | 4975 | rtl_hw_start_8168c_1(tp); |
4804b3b3 | 4976 | break; |
219a1e9d FR |
4977 | |
4978 | case RTL_GIGA_MAC_VER_20: | |
beb1fe18 | 4979 | rtl_hw_start_8168c_2(tp); |
4804b3b3 | 4980 | break; |
219a1e9d | 4981 | |
197ff761 | 4982 | case RTL_GIGA_MAC_VER_21: |
beb1fe18 | 4983 | rtl_hw_start_8168c_3(tp); |
4804b3b3 | 4984 | break; |
197ff761 | 4985 | |
6fb07058 | 4986 | case RTL_GIGA_MAC_VER_22: |
beb1fe18 | 4987 | rtl_hw_start_8168c_4(tp); |
4804b3b3 | 4988 | break; |
6fb07058 | 4989 | |
ef3386f0 | 4990 | case RTL_GIGA_MAC_VER_23: |
beb1fe18 | 4991 | rtl_hw_start_8168cp_2(tp); |
4804b3b3 | 4992 | break; |
ef3386f0 | 4993 | |
7f3e3d3a | 4994 | case RTL_GIGA_MAC_VER_24: |
beb1fe18 | 4995 | rtl_hw_start_8168cp_3(tp); |
4804b3b3 | 4996 | break; |
7f3e3d3a | 4997 | |
5b538df9 | 4998 | case RTL_GIGA_MAC_VER_25: |
daf9df6d | 4999 | case RTL_GIGA_MAC_VER_26: |
5000 | case RTL_GIGA_MAC_VER_27: | |
beb1fe18 | 5001 | rtl_hw_start_8168d(tp); |
4804b3b3 | 5002 | break; |
5b538df9 | 5003 | |
e6de30d6 | 5004 | case RTL_GIGA_MAC_VER_28: |
beb1fe18 | 5005 | rtl_hw_start_8168d_4(tp); |
4804b3b3 | 5006 | break; |
cecb5fd7 | 5007 | |
4804b3b3 | 5008 | case RTL_GIGA_MAC_VER_31: |
beb1fe18 | 5009 | rtl_hw_start_8168dp(tp); |
4804b3b3 | 5010 | break; |
5011 | ||
01dc7fec | 5012 | case RTL_GIGA_MAC_VER_32: |
5013 | case RTL_GIGA_MAC_VER_33: | |
beb1fe18 | 5014 | rtl_hw_start_8168e_1(tp); |
70090424 HW |
5015 | break; |
5016 | case RTL_GIGA_MAC_VER_34: | |
beb1fe18 | 5017 | rtl_hw_start_8168e_2(tp); |
01dc7fec | 5018 | break; |
e6de30d6 | 5019 | |
c2218925 HW |
5020 | case RTL_GIGA_MAC_VER_35: |
5021 | case RTL_GIGA_MAC_VER_36: | |
beb1fe18 | 5022 | rtl_hw_start_8168f_1(tp); |
c2218925 HW |
5023 | break; |
5024 | ||
b3d7b2f2 HW |
5025 | case RTL_GIGA_MAC_VER_38: |
5026 | rtl_hw_start_8411(tp); | |
5027 | break; | |
5028 | ||
219a1e9d FR |
5029 | default: |
5030 | printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n", | |
5031 | dev->name, tp->mac_version); | |
4804b3b3 | 5032 | break; |
219a1e9d | 5033 | } |
2dd99530 | 5034 | |
0e485150 FR |
5035 | RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); |
5036 | ||
b8363901 FR |
5037 | RTL_W8(Cfg9346, Cfg9346_Lock); |
5038 | ||
2dd99530 | 5039 | RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000); |
07ce4064 | 5040 | } |
1da177e4 | 5041 | |
2857ffb7 FR |
5042 | #define R810X_CPCMD_QUIRK_MASK (\ |
5043 | EnableBist | \ | |
5044 | Mac_dbgo_oe | \ | |
5045 | Force_half_dup | \ | |
5edcc537 | 5046 | Force_rxflow_en | \ |
2857ffb7 FR |
5047 | Force_txflow_en | \ |
5048 | Cxpl_dbg_sel | \ | |
5049 | ASF | \ | |
5050 | PktCntrDisable | \ | |
d24e9aaf | 5051 | Mac_dbgo_sel) |
2857ffb7 | 5052 | |
beb1fe18 | 5053 | static void rtl_hw_start_8102e_1(struct rtl8169_private *tp) |
2857ffb7 | 5054 | { |
beb1fe18 HW |
5055 | void __iomem *ioaddr = tp->mmio_addr; |
5056 | struct pci_dev *pdev = tp->pci_dev; | |
350f7596 | 5057 | static const struct ephy_info e_info_8102e_1[] = { |
2857ffb7 FR |
5058 | { 0x01, 0, 0x6e65 }, |
5059 | { 0x02, 0, 0x091f }, | |
5060 | { 0x03, 0, 0xc2f9 }, | |
5061 | { 0x06, 0, 0xafb5 }, | |
5062 | { 0x07, 0, 0x0e00 }, | |
5063 | { 0x19, 0, 0xec80 }, | |
5064 | { 0x01, 0, 0x2e65 }, | |
5065 | { 0x01, 0, 0x6e65 } | |
5066 | }; | |
5067 | u8 cfg1; | |
5068 | ||
beb1fe18 | 5069 | rtl_csi_access_enable_2(tp); |
2857ffb7 FR |
5070 | |
5071 | RTL_W8(DBG_REG, FIX_NAK_1); | |
5072 | ||
5073 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
5074 | ||
5075 | RTL_W8(Config1, | |
5076 | LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable); | |
5077 | RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); | |
5078 | ||
5079 | cfg1 = RTL_R8(Config1); | |
5080 | if ((cfg1 & LEDS0) && (cfg1 & LEDS1)) | |
5081 | RTL_W8(Config1, cfg1 & ~LEDS0); | |
5082 | ||
fdf6fc06 | 5083 | rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1)); |
2857ffb7 FR |
5084 | } |
5085 | ||
beb1fe18 | 5086 | static void rtl_hw_start_8102e_2(struct rtl8169_private *tp) |
2857ffb7 | 5087 | { |
beb1fe18 HW |
5088 | void __iomem *ioaddr = tp->mmio_addr; |
5089 | struct pci_dev *pdev = tp->pci_dev; | |
5090 | ||
5091 | rtl_csi_access_enable_2(tp); | |
2857ffb7 FR |
5092 | |
5093 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
5094 | ||
5095 | RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable); | |
5096 | RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); | |
2857ffb7 FR |
5097 | } |
5098 | ||
beb1fe18 | 5099 | static void rtl_hw_start_8102e_3(struct rtl8169_private *tp) |
2857ffb7 | 5100 | { |
beb1fe18 | 5101 | rtl_hw_start_8102e_2(tp); |
2857ffb7 | 5102 | |
fdf6fc06 | 5103 | rtl_ephy_write(tp, 0x03, 0xc2f9); |
2857ffb7 FR |
5104 | } |
5105 | ||
beb1fe18 | 5106 | static void rtl_hw_start_8105e_1(struct rtl8169_private *tp) |
5a5e4443 | 5107 | { |
beb1fe18 | 5108 | void __iomem *ioaddr = tp->mmio_addr; |
5a5e4443 HW |
5109 | static const struct ephy_info e_info_8105e_1[] = { |
5110 | { 0x07, 0, 0x4000 }, | |
5111 | { 0x19, 0, 0x0200 }, | |
5112 | { 0x19, 0, 0x0020 }, | |
5113 | { 0x1e, 0, 0x2000 }, | |
5114 | { 0x03, 0, 0x0001 }, | |
5115 | { 0x19, 0, 0x0100 }, | |
5116 | { 0x19, 0, 0x0004 }, | |
5117 | { 0x0a, 0, 0x0020 } | |
5118 | }; | |
5119 | ||
cecb5fd7 | 5120 | /* Force LAN exit from ASPM if Rx/Tx are not idle */ |
5a5e4443 HW |
5121 | RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800); |
5122 | ||
cecb5fd7 | 5123 | /* Disable Early Tally Counter */ |
5a5e4443 HW |
5124 | RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000); |
5125 | ||
5126 | RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET); | |
4f6b00e5 | 5127 | RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN); |
5a5e4443 | 5128 | |
fdf6fc06 | 5129 | rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1)); |
5a5e4443 HW |
5130 | } |
5131 | ||
beb1fe18 | 5132 | static void rtl_hw_start_8105e_2(struct rtl8169_private *tp) |
5a5e4443 | 5133 | { |
beb1fe18 | 5134 | rtl_hw_start_8105e_1(tp); |
fdf6fc06 | 5135 | rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000); |
5a5e4443 HW |
5136 | } |
5137 | ||
7e18dca1 HW |
5138 | static void rtl_hw_start_8402(struct rtl8169_private *tp) |
5139 | { | |
5140 | void __iomem *ioaddr = tp->mmio_addr; | |
5141 | static const struct ephy_info e_info_8402[] = { | |
5142 | { 0x19, 0xffff, 0xff64 }, | |
5143 | { 0x1e, 0, 0x4000 } | |
5144 | }; | |
5145 | ||
5146 | rtl_csi_access_enable_2(tp); | |
5147 | ||
5148 | /* Force LAN exit from ASPM if Rx/Tx are not idle */ | |
5149 | RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800); | |
5150 | ||
5151 | RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO); | |
5152 | RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB); | |
5153 | ||
fdf6fc06 | 5154 | rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402)); |
7e18dca1 HW |
5155 | |
5156 | rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
5157 | ||
fdf6fc06 FR |
5158 | rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC); |
5159 | rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC); | |
5160 | rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC); | |
5161 | rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC); | |
5162 | rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); | |
5163 | rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); | |
5164 | rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC); | |
7e18dca1 HW |
5165 | } |
5166 | ||
5598bfe5 HW |
5167 | static void rtl_hw_start_8106(struct rtl8169_private *tp) |
5168 | { | |
5169 | void __iomem *ioaddr = tp->mmio_addr; | |
5170 | ||
5171 | /* Force LAN exit from ASPM if Rx/Tx are not idle */ | |
5172 | RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800); | |
5173 | ||
5174 | RTL_W32(MISC, (RTL_R32(MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN); | |
5175 | RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET); | |
5176 | RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN); | |
5177 | } | |
5178 | ||
07ce4064 FR |
5179 | static void rtl_hw_start_8101(struct net_device *dev) |
5180 | { | |
cdf1a608 FR |
5181 | struct rtl8169_private *tp = netdev_priv(dev); |
5182 | void __iomem *ioaddr = tp->mmio_addr; | |
5183 | struct pci_dev *pdev = tp->pci_dev; | |
5184 | ||
da78dbff FR |
5185 | if (tp->mac_version >= RTL_GIGA_MAC_VER_30) |
5186 | tp->event_slow &= ~RxFIFOOver; | |
811fd301 | 5187 | |
cecb5fd7 FR |
5188 | if (tp->mac_version == RTL_GIGA_MAC_VER_13 || |
5189 | tp->mac_version == RTL_GIGA_MAC_VER_16) { | |
e44daade | 5190 | int cap = pci_pcie_cap(pdev); |
9c14ceaf FR |
5191 | |
5192 | if (cap) { | |
5193 | pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, | |
5194 | PCI_EXP_DEVCTL_NOSNOOP_EN); | |
5195 | } | |
cdf1a608 FR |
5196 | } |
5197 | ||
d24e9aaf HW |
5198 | RTL_W8(Cfg9346, Cfg9346_Unlock); |
5199 | ||
2857ffb7 FR |
5200 | switch (tp->mac_version) { |
5201 | case RTL_GIGA_MAC_VER_07: | |
beb1fe18 | 5202 | rtl_hw_start_8102e_1(tp); |
2857ffb7 FR |
5203 | break; |
5204 | ||
5205 | case RTL_GIGA_MAC_VER_08: | |
beb1fe18 | 5206 | rtl_hw_start_8102e_3(tp); |
2857ffb7 FR |
5207 | break; |
5208 | ||
5209 | case RTL_GIGA_MAC_VER_09: | |
beb1fe18 | 5210 | rtl_hw_start_8102e_2(tp); |
2857ffb7 | 5211 | break; |
5a5e4443 HW |
5212 | |
5213 | case RTL_GIGA_MAC_VER_29: | |
beb1fe18 | 5214 | rtl_hw_start_8105e_1(tp); |
5a5e4443 HW |
5215 | break; |
5216 | case RTL_GIGA_MAC_VER_30: | |
beb1fe18 | 5217 | rtl_hw_start_8105e_2(tp); |
5a5e4443 | 5218 | break; |
7e18dca1 HW |
5219 | |
5220 | case RTL_GIGA_MAC_VER_37: | |
5221 | rtl_hw_start_8402(tp); | |
5222 | break; | |
5598bfe5 HW |
5223 | |
5224 | case RTL_GIGA_MAC_VER_39: | |
5225 | rtl_hw_start_8106(tp); | |
5226 | break; | |
cdf1a608 FR |
5227 | } |
5228 | ||
d24e9aaf | 5229 | RTL_W8(Cfg9346, Cfg9346_Lock); |
cdf1a608 | 5230 | |
f0298f81 | 5231 | RTL_W8(MaxTxPacketSize, TxPacketMax); |
cdf1a608 | 5232 | |
6f0333b8 | 5233 | rtl_set_rx_max_size(ioaddr, rx_buf_sz); |
cdf1a608 | 5234 | |
d24e9aaf | 5235 | tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK; |
cdf1a608 FR |
5236 | RTL_W16(CPlusCmd, tp->cp_cmd); |
5237 | ||
5238 | RTL_W16(IntrMitigate, 0x0000); | |
5239 | ||
5240 | rtl_set_rx_tx_desc_registers(tp, ioaddr); | |
5241 | ||
5242 | RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); | |
5243 | rtl_set_rx_tx_config_registers(tp); | |
5244 | ||
cdf1a608 FR |
5245 | RTL_R8(IntrMask); |
5246 | ||
cdf1a608 FR |
5247 | rtl_set_rx_mode(dev); |
5248 | ||
5249 | RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000); | |
1da177e4 LT |
5250 | } |
5251 | ||
5252 | static int rtl8169_change_mtu(struct net_device *dev, int new_mtu) | |
5253 | { | |
d58d46b5 FR |
5254 | struct rtl8169_private *tp = netdev_priv(dev); |
5255 | ||
5256 | if (new_mtu < ETH_ZLEN || | |
5257 | new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max) | |
1da177e4 LT |
5258 | return -EINVAL; |
5259 | ||
d58d46b5 FR |
5260 | if (new_mtu > ETH_DATA_LEN) |
5261 | rtl_hw_jumbo_enable(tp); | |
5262 | else | |
5263 | rtl_hw_jumbo_disable(tp); | |
5264 | ||
1da177e4 | 5265 | dev->mtu = new_mtu; |
350fb32a MM |
5266 | netdev_update_features(dev); |
5267 | ||
323bb685 | 5268 | return 0; |
1da177e4 LT |
5269 | } |
5270 | ||
5271 | static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc) | |
5272 | { | |
95e0918d | 5273 | desc->addr = cpu_to_le64(0x0badbadbadbadbadull); |
1da177e4 LT |
5274 | desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask); |
5275 | } | |
5276 | ||
6f0333b8 ED |
5277 | static void rtl8169_free_rx_databuff(struct rtl8169_private *tp, |
5278 | void **data_buff, struct RxDesc *desc) | |
1da177e4 | 5279 | { |
48addcc9 | 5280 | dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz, |
231aee63 | 5281 | DMA_FROM_DEVICE); |
48addcc9 | 5282 | |
6f0333b8 ED |
5283 | kfree(*data_buff); |
5284 | *data_buff = NULL; | |
1da177e4 LT |
5285 | rtl8169_make_unusable_by_asic(desc); |
5286 | } | |
5287 | ||
5288 | static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz) | |
5289 | { | |
5290 | u32 eor = le32_to_cpu(desc->opts1) & RingEnd; | |
5291 | ||
5292 | desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz); | |
5293 | } | |
5294 | ||
5295 | static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping, | |
5296 | u32 rx_buf_sz) | |
5297 | { | |
5298 | desc->addr = cpu_to_le64(mapping); | |
5299 | wmb(); | |
5300 | rtl8169_mark_to_asic(desc, rx_buf_sz); | |
5301 | } | |
5302 | ||
6f0333b8 ED |
5303 | static inline void *rtl8169_align(void *data) |
5304 | { | |
5305 | return (void *)ALIGN((long)data, 16); | |
5306 | } | |
5307 | ||
0ecbe1ca SG |
5308 | static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp, |
5309 | struct RxDesc *desc) | |
1da177e4 | 5310 | { |
6f0333b8 | 5311 | void *data; |
1da177e4 | 5312 | dma_addr_t mapping; |
48addcc9 | 5313 | struct device *d = &tp->pci_dev->dev; |
0ecbe1ca | 5314 | struct net_device *dev = tp->dev; |
6f0333b8 | 5315 | int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1; |
1da177e4 | 5316 | |
6f0333b8 ED |
5317 | data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node); |
5318 | if (!data) | |
5319 | return NULL; | |
e9f63f30 | 5320 | |
6f0333b8 ED |
5321 | if (rtl8169_align(data) != data) { |
5322 | kfree(data); | |
5323 | data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node); | |
5324 | if (!data) | |
5325 | return NULL; | |
5326 | } | |
3eafe507 | 5327 | |
48addcc9 | 5328 | mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz, |
231aee63 | 5329 | DMA_FROM_DEVICE); |
d827d86b SG |
5330 | if (unlikely(dma_mapping_error(d, mapping))) { |
5331 | if (net_ratelimit()) | |
5332 | netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n"); | |
3eafe507 | 5333 | goto err_out; |
d827d86b | 5334 | } |
1da177e4 LT |
5335 | |
5336 | rtl8169_map_to_asic(desc, mapping, rx_buf_sz); | |
6f0333b8 | 5337 | return data; |
3eafe507 SG |
5338 | |
5339 | err_out: | |
5340 | kfree(data); | |
5341 | return NULL; | |
1da177e4 LT |
5342 | } |
5343 | ||
5344 | static void rtl8169_rx_clear(struct rtl8169_private *tp) | |
5345 | { | |
07d3f51f | 5346 | unsigned int i; |
1da177e4 LT |
5347 | |
5348 | for (i = 0; i < NUM_RX_DESC; i++) { | |
6f0333b8 ED |
5349 | if (tp->Rx_databuff[i]) { |
5350 | rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i, | |
1da177e4 LT |
5351 | tp->RxDescArray + i); |
5352 | } | |
5353 | } | |
5354 | } | |
5355 | ||
0ecbe1ca | 5356 | static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc) |
1da177e4 | 5357 | { |
0ecbe1ca SG |
5358 | desc->opts1 |= cpu_to_le32(RingEnd); |
5359 | } | |
5b0384f4 | 5360 | |
0ecbe1ca SG |
5361 | static int rtl8169_rx_fill(struct rtl8169_private *tp) |
5362 | { | |
5363 | unsigned int i; | |
1da177e4 | 5364 | |
0ecbe1ca SG |
5365 | for (i = 0; i < NUM_RX_DESC; i++) { |
5366 | void *data; | |
4ae47c2d | 5367 | |
6f0333b8 | 5368 | if (tp->Rx_databuff[i]) |
1da177e4 | 5369 | continue; |
bcf0bf90 | 5370 | |
0ecbe1ca | 5371 | data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i); |
6f0333b8 ED |
5372 | if (!data) { |
5373 | rtl8169_make_unusable_by_asic(tp->RxDescArray + i); | |
0ecbe1ca | 5374 | goto err_out; |
6f0333b8 ED |
5375 | } |
5376 | tp->Rx_databuff[i] = data; | |
1da177e4 | 5377 | } |
1da177e4 | 5378 | |
0ecbe1ca SG |
5379 | rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1); |
5380 | return 0; | |
5381 | ||
5382 | err_out: | |
5383 | rtl8169_rx_clear(tp); | |
5384 | return -ENOMEM; | |
1da177e4 LT |
5385 | } |
5386 | ||
1da177e4 LT |
5387 | static int rtl8169_init_ring(struct net_device *dev) |
5388 | { | |
5389 | struct rtl8169_private *tp = netdev_priv(dev); | |
5390 | ||
5391 | rtl8169_init_ring_indexes(tp); | |
5392 | ||
5393 | memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info)); | |
6f0333b8 | 5394 | memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *)); |
1da177e4 | 5395 | |
0ecbe1ca | 5396 | return rtl8169_rx_fill(tp); |
1da177e4 LT |
5397 | } |
5398 | ||
48addcc9 | 5399 | static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb, |
1da177e4 LT |
5400 | struct TxDesc *desc) |
5401 | { | |
5402 | unsigned int len = tx_skb->len; | |
5403 | ||
48addcc9 SG |
5404 | dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE); |
5405 | ||
1da177e4 LT |
5406 | desc->opts1 = 0x00; |
5407 | desc->opts2 = 0x00; | |
5408 | desc->addr = 0x00; | |
5409 | tx_skb->len = 0; | |
5410 | } | |
5411 | ||
3eafe507 SG |
5412 | static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start, |
5413 | unsigned int n) | |
1da177e4 LT |
5414 | { |
5415 | unsigned int i; | |
5416 | ||
3eafe507 SG |
5417 | for (i = 0; i < n; i++) { |
5418 | unsigned int entry = (start + i) % NUM_TX_DESC; | |
1da177e4 LT |
5419 | struct ring_info *tx_skb = tp->tx_skb + entry; |
5420 | unsigned int len = tx_skb->len; | |
5421 | ||
5422 | if (len) { | |
5423 | struct sk_buff *skb = tx_skb->skb; | |
5424 | ||
48addcc9 | 5425 | rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb, |
1da177e4 LT |
5426 | tp->TxDescArray + entry); |
5427 | if (skb) { | |
cac4b22f | 5428 | tp->dev->stats.tx_dropped++; |
1da177e4 LT |
5429 | dev_kfree_skb(skb); |
5430 | tx_skb->skb = NULL; | |
5431 | } | |
1da177e4 LT |
5432 | } |
5433 | } | |
3eafe507 SG |
5434 | } |
5435 | ||
5436 | static void rtl8169_tx_clear(struct rtl8169_private *tp) | |
5437 | { | |
5438 | rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC); | |
1da177e4 | 5439 | tp->cur_tx = tp->dirty_tx = 0; |
036dafa2 | 5440 | netdev_reset_queue(tp->dev); |
1da177e4 LT |
5441 | } |
5442 | ||
4422bcd4 | 5443 | static void rtl_reset_work(struct rtl8169_private *tp) |
1da177e4 | 5444 | { |
c4028958 | 5445 | struct net_device *dev = tp->dev; |
56de414c | 5446 | int i; |
1da177e4 | 5447 | |
da78dbff FR |
5448 | napi_disable(&tp->napi); |
5449 | netif_stop_queue(dev); | |
5450 | synchronize_sched(); | |
1da177e4 | 5451 | |
c7c2c39b | 5452 | rtl8169_hw_reset(tp); |
5453 | ||
56de414c FR |
5454 | for (i = 0; i < NUM_RX_DESC; i++) |
5455 | rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz); | |
5456 | ||
1da177e4 | 5457 | rtl8169_tx_clear(tp); |
c7c2c39b | 5458 | rtl8169_init_ring_indexes(tp); |
1da177e4 | 5459 | |
da78dbff | 5460 | napi_enable(&tp->napi); |
56de414c FR |
5461 | rtl_hw_start(dev); |
5462 | netif_wake_queue(dev); | |
5463 | rtl8169_check_link_status(dev, tp, tp->mmio_addr); | |
1da177e4 LT |
5464 | } |
5465 | ||
5466 | static void rtl8169_tx_timeout(struct net_device *dev) | |
5467 | { | |
da78dbff FR |
5468 | struct rtl8169_private *tp = netdev_priv(dev); |
5469 | ||
5470 | rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); | |
1da177e4 LT |
5471 | } |
5472 | ||
5473 | static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb, | |
2b7b4318 | 5474 | u32 *opts) |
1da177e4 LT |
5475 | { |
5476 | struct skb_shared_info *info = skb_shinfo(skb); | |
5477 | unsigned int cur_frag, entry; | |
a6343afb | 5478 | struct TxDesc * uninitialized_var(txd); |
48addcc9 | 5479 | struct device *d = &tp->pci_dev->dev; |
1da177e4 LT |
5480 | |
5481 | entry = tp->cur_tx; | |
5482 | for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) { | |
9e903e08 | 5483 | const skb_frag_t *frag = info->frags + cur_frag; |
1da177e4 LT |
5484 | dma_addr_t mapping; |
5485 | u32 status, len; | |
5486 | void *addr; | |
5487 | ||
5488 | entry = (entry + 1) % NUM_TX_DESC; | |
5489 | ||
5490 | txd = tp->TxDescArray + entry; | |
9e903e08 | 5491 | len = skb_frag_size(frag); |
929f6189 | 5492 | addr = skb_frag_address(frag); |
48addcc9 | 5493 | mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE); |
d827d86b SG |
5494 | if (unlikely(dma_mapping_error(d, mapping))) { |
5495 | if (net_ratelimit()) | |
5496 | netif_err(tp, drv, tp->dev, | |
5497 | "Failed to map TX fragments DMA!\n"); | |
3eafe507 | 5498 | goto err_out; |
d827d86b | 5499 | } |
1da177e4 | 5500 | |
cecb5fd7 | 5501 | /* Anti gcc 2.95.3 bugware (sic) */ |
2b7b4318 FR |
5502 | status = opts[0] | len | |
5503 | (RingEnd * !((entry + 1) % NUM_TX_DESC)); | |
1da177e4 LT |
5504 | |
5505 | txd->opts1 = cpu_to_le32(status); | |
2b7b4318 | 5506 | txd->opts2 = cpu_to_le32(opts[1]); |
1da177e4 LT |
5507 | txd->addr = cpu_to_le64(mapping); |
5508 | ||
5509 | tp->tx_skb[entry].len = len; | |
5510 | } | |
5511 | ||
5512 | if (cur_frag) { | |
5513 | tp->tx_skb[entry].skb = skb; | |
5514 | txd->opts1 |= cpu_to_le32(LastFrag); | |
5515 | } | |
5516 | ||
5517 | return cur_frag; | |
3eafe507 SG |
5518 | |
5519 | err_out: | |
5520 | rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag); | |
5521 | return -EIO; | |
1da177e4 LT |
5522 | } |
5523 | ||
2b7b4318 FR |
5524 | static inline void rtl8169_tso_csum(struct rtl8169_private *tp, |
5525 | struct sk_buff *skb, u32 *opts) | |
1da177e4 | 5526 | { |
2b7b4318 | 5527 | const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version; |
350fb32a | 5528 | u32 mss = skb_shinfo(skb)->gso_size; |
2b7b4318 | 5529 | int offset = info->opts_offset; |
350fb32a | 5530 | |
2b7b4318 FR |
5531 | if (mss) { |
5532 | opts[0] |= TD_LSO; | |
5533 | opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift; | |
5534 | } else if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
eddc9ec5 | 5535 | const struct iphdr *ip = ip_hdr(skb); |
1da177e4 LT |
5536 | |
5537 | if (ip->protocol == IPPROTO_TCP) | |
2b7b4318 | 5538 | opts[offset] |= info->checksum.tcp; |
1da177e4 | 5539 | else if (ip->protocol == IPPROTO_UDP) |
2b7b4318 FR |
5540 | opts[offset] |= info->checksum.udp; |
5541 | else | |
5542 | WARN_ON_ONCE(1); | |
1da177e4 | 5543 | } |
1da177e4 LT |
5544 | } |
5545 | ||
61357325 SH |
5546 | static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb, |
5547 | struct net_device *dev) | |
1da177e4 LT |
5548 | { |
5549 | struct rtl8169_private *tp = netdev_priv(dev); | |
3eafe507 | 5550 | unsigned int entry = tp->cur_tx % NUM_TX_DESC; |
1da177e4 LT |
5551 | struct TxDesc *txd = tp->TxDescArray + entry; |
5552 | void __iomem *ioaddr = tp->mmio_addr; | |
48addcc9 | 5553 | struct device *d = &tp->pci_dev->dev; |
1da177e4 LT |
5554 | dma_addr_t mapping; |
5555 | u32 status, len; | |
2b7b4318 | 5556 | u32 opts[2]; |
3eafe507 | 5557 | int frags; |
5b0384f4 | 5558 | |
477206a0 | 5559 | if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) { |
bf82c189 | 5560 | netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n"); |
3eafe507 | 5561 | goto err_stop_0; |
1da177e4 LT |
5562 | } |
5563 | ||
5564 | if (unlikely(le32_to_cpu(txd->opts1) & DescOwn)) | |
3eafe507 SG |
5565 | goto err_stop_0; |
5566 | ||
5567 | len = skb_headlen(skb); | |
48addcc9 | 5568 | mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE); |
d827d86b SG |
5569 | if (unlikely(dma_mapping_error(d, mapping))) { |
5570 | if (net_ratelimit()) | |
5571 | netif_err(tp, drv, dev, "Failed to map TX DMA!\n"); | |
3eafe507 | 5572 | goto err_dma_0; |
d827d86b | 5573 | } |
3eafe507 SG |
5574 | |
5575 | tp->tx_skb[entry].len = len; | |
5576 | txd->addr = cpu_to_le64(mapping); | |
1da177e4 | 5577 | |
2b7b4318 FR |
5578 | opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb)); |
5579 | opts[0] = DescOwn; | |
1da177e4 | 5580 | |
2b7b4318 FR |
5581 | rtl8169_tso_csum(tp, skb, opts); |
5582 | ||
5583 | frags = rtl8169_xmit_frags(tp, skb, opts); | |
3eafe507 SG |
5584 | if (frags < 0) |
5585 | goto err_dma_1; | |
5586 | else if (frags) | |
2b7b4318 | 5587 | opts[0] |= FirstFrag; |
3eafe507 | 5588 | else { |
2b7b4318 | 5589 | opts[0] |= FirstFrag | LastFrag; |
1da177e4 LT |
5590 | tp->tx_skb[entry].skb = skb; |
5591 | } | |
5592 | ||
2b7b4318 FR |
5593 | txd->opts2 = cpu_to_le32(opts[1]); |
5594 | ||
036dafa2 IM |
5595 | netdev_sent_queue(dev, skb->len); |
5596 | ||
5047fb5d RC |
5597 | skb_tx_timestamp(skb); |
5598 | ||
1da177e4 LT |
5599 | wmb(); |
5600 | ||
cecb5fd7 | 5601 | /* Anti gcc 2.95.3 bugware (sic) */ |
2b7b4318 | 5602 | status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC)); |
1da177e4 LT |
5603 | txd->opts1 = cpu_to_le32(status); |
5604 | ||
1da177e4 LT |
5605 | tp->cur_tx += frags + 1; |
5606 | ||
4c020a96 | 5607 | wmb(); |
1da177e4 | 5608 | |
cecb5fd7 | 5609 | RTL_W8(TxPoll, NPQ); |
1da177e4 | 5610 | |
da78dbff FR |
5611 | mmiowb(); |
5612 | ||
477206a0 | 5613 | if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) { |
ae1f23fb FR |
5614 | /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must |
5615 | * not miss a ring update when it notices a stopped queue. | |
5616 | */ | |
5617 | smp_wmb(); | |
1da177e4 | 5618 | netif_stop_queue(dev); |
ae1f23fb FR |
5619 | /* Sync with rtl_tx: |
5620 | * - publish queue status and cur_tx ring index (write barrier) | |
5621 | * - refresh dirty_tx ring index (read barrier). | |
5622 | * May the current thread have a pessimistic view of the ring | |
5623 | * status and forget to wake up queue, a racing rtl_tx thread | |
5624 | * can't. | |
5625 | */ | |
1e874e04 | 5626 | smp_mb(); |
477206a0 | 5627 | if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) |
1da177e4 LT |
5628 | netif_wake_queue(dev); |
5629 | } | |
5630 | ||
61357325 | 5631 | return NETDEV_TX_OK; |
1da177e4 | 5632 | |
3eafe507 | 5633 | err_dma_1: |
48addcc9 | 5634 | rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd); |
3eafe507 SG |
5635 | err_dma_0: |
5636 | dev_kfree_skb(skb); | |
5637 | dev->stats.tx_dropped++; | |
5638 | return NETDEV_TX_OK; | |
5639 | ||
5640 | err_stop_0: | |
1da177e4 | 5641 | netif_stop_queue(dev); |
cebf8cc7 | 5642 | dev->stats.tx_dropped++; |
61357325 | 5643 | return NETDEV_TX_BUSY; |
1da177e4 LT |
5644 | } |
5645 | ||
5646 | static void rtl8169_pcierr_interrupt(struct net_device *dev) | |
5647 | { | |
5648 | struct rtl8169_private *tp = netdev_priv(dev); | |
5649 | struct pci_dev *pdev = tp->pci_dev; | |
1da177e4 LT |
5650 | u16 pci_status, pci_cmd; |
5651 | ||
5652 | pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); | |
5653 | pci_read_config_word(pdev, PCI_STATUS, &pci_status); | |
5654 | ||
bf82c189 JP |
5655 | netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n", |
5656 | pci_cmd, pci_status); | |
1da177e4 LT |
5657 | |
5658 | /* | |
5659 | * The recovery sequence below admits a very elaborated explanation: | |
5660 | * - it seems to work; | |
d03902b8 FR |
5661 | * - I did not see what else could be done; |
5662 | * - it makes iop3xx happy. | |
1da177e4 LT |
5663 | * |
5664 | * Feel free to adjust to your needs. | |
5665 | */ | |
a27993f3 | 5666 | if (pdev->broken_parity_status) |
d03902b8 FR |
5667 | pci_cmd &= ~PCI_COMMAND_PARITY; |
5668 | else | |
5669 | pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY; | |
5670 | ||
5671 | pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); | |
1da177e4 LT |
5672 | |
5673 | pci_write_config_word(pdev, PCI_STATUS, | |
5674 | pci_status & (PCI_STATUS_DETECTED_PARITY | | |
5675 | PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT | | |
5676 | PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT)); | |
5677 | ||
5678 | /* The infamous DAC f*ckup only happens at boot time */ | |
5679 | if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) { | |
e6de30d6 | 5680 | void __iomem *ioaddr = tp->mmio_addr; |
5681 | ||
bf82c189 | 5682 | netif_info(tp, intr, dev, "disabling PCI DAC\n"); |
1da177e4 LT |
5683 | tp->cp_cmd &= ~PCIDAC; |
5684 | RTL_W16(CPlusCmd, tp->cp_cmd); | |
5685 | dev->features &= ~NETIF_F_HIGHDMA; | |
1da177e4 LT |
5686 | } |
5687 | ||
e6de30d6 | 5688 | rtl8169_hw_reset(tp); |
d03902b8 | 5689 | |
98ddf986 | 5690 | rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); |
1da177e4 LT |
5691 | } |
5692 | ||
036dafa2 IM |
5693 | struct rtl_txc { |
5694 | int packets; | |
5695 | int bytes; | |
5696 | }; | |
5697 | ||
da78dbff | 5698 | static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp) |
1da177e4 | 5699 | { |
036dafa2 | 5700 | struct rtl8169_stats *tx_stats = &tp->tx_stats; |
1da177e4 | 5701 | unsigned int dirty_tx, tx_left; |
036dafa2 | 5702 | struct rtl_txc txc = { 0, 0 }; |
1da177e4 | 5703 | |
1da177e4 LT |
5704 | dirty_tx = tp->dirty_tx; |
5705 | smp_rmb(); | |
5706 | tx_left = tp->cur_tx - dirty_tx; | |
5707 | ||
5708 | while (tx_left > 0) { | |
5709 | unsigned int entry = dirty_tx % NUM_TX_DESC; | |
5710 | struct ring_info *tx_skb = tp->tx_skb + entry; | |
1da177e4 LT |
5711 | u32 status; |
5712 | ||
5713 | rmb(); | |
5714 | status = le32_to_cpu(tp->TxDescArray[entry].opts1); | |
5715 | if (status & DescOwn) | |
5716 | break; | |
5717 | ||
48addcc9 SG |
5718 | rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb, |
5719 | tp->TxDescArray + entry); | |
1da177e4 | 5720 | if (status & LastFrag) { |
036dafa2 IM |
5721 | struct sk_buff *skb = tx_skb->skb; |
5722 | ||
5723 | txc.packets++; | |
5724 | txc.bytes += skb->len; | |
5725 | dev_kfree_skb(skb); | |
1da177e4 LT |
5726 | tx_skb->skb = NULL; |
5727 | } | |
5728 | dirty_tx++; | |
5729 | tx_left--; | |
5730 | } | |
5731 | ||
036dafa2 IM |
5732 | u64_stats_update_begin(&tx_stats->syncp); |
5733 | tx_stats->packets += txc.packets; | |
5734 | tx_stats->bytes += txc.bytes; | |
5735 | u64_stats_update_end(&tx_stats->syncp); | |
5736 | ||
5737 | netdev_completed_queue(dev, txc.packets, txc.bytes); | |
5738 | ||
1da177e4 LT |
5739 | if (tp->dirty_tx != dirty_tx) { |
5740 | tp->dirty_tx = dirty_tx; | |
ae1f23fb FR |
5741 | /* Sync with rtl8169_start_xmit: |
5742 | * - publish dirty_tx ring index (write barrier) | |
5743 | * - refresh cur_tx ring index and queue status (read barrier) | |
5744 | * May the current thread miss the stopped queue condition, | |
5745 | * a racing xmit thread can only have a right view of the | |
5746 | * ring status. | |
5747 | */ | |
1e874e04 | 5748 | smp_mb(); |
1da177e4 | 5749 | if (netif_queue_stopped(dev) && |
477206a0 | 5750 | TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) { |
1da177e4 LT |
5751 | netif_wake_queue(dev); |
5752 | } | |
d78ae2dc FR |
5753 | /* |
5754 | * 8168 hack: TxPoll requests are lost when the Tx packets are | |
5755 | * too close. Let's kick an extra TxPoll request when a burst | |
5756 | * of start_xmit activity is detected (if it is not detected, | |
5757 | * it is slow enough). -- FR | |
5758 | */ | |
da78dbff FR |
5759 | if (tp->cur_tx != dirty_tx) { |
5760 | void __iomem *ioaddr = tp->mmio_addr; | |
5761 | ||
d78ae2dc | 5762 | RTL_W8(TxPoll, NPQ); |
da78dbff | 5763 | } |
1da177e4 LT |
5764 | } |
5765 | } | |
5766 | ||
126fa4b9 FR |
5767 | static inline int rtl8169_fragmented_frame(u32 status) |
5768 | { | |
5769 | return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag); | |
5770 | } | |
5771 | ||
adea1ac7 | 5772 | static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1) |
1da177e4 | 5773 | { |
1da177e4 LT |
5774 | u32 status = opts1 & RxProtoMask; |
5775 | ||
5776 | if (((status == RxProtoTCP) && !(opts1 & TCPFail)) || | |
d5d3ebe3 | 5777 | ((status == RxProtoUDP) && !(opts1 & UDPFail))) |
1da177e4 LT |
5778 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
5779 | else | |
bc8acf2c | 5780 | skb_checksum_none_assert(skb); |
1da177e4 LT |
5781 | } |
5782 | ||
6f0333b8 ED |
5783 | static struct sk_buff *rtl8169_try_rx_copy(void *data, |
5784 | struct rtl8169_private *tp, | |
5785 | int pkt_size, | |
5786 | dma_addr_t addr) | |
1da177e4 | 5787 | { |
b449655f | 5788 | struct sk_buff *skb; |
48addcc9 | 5789 | struct device *d = &tp->pci_dev->dev; |
b449655f | 5790 | |
6f0333b8 | 5791 | data = rtl8169_align(data); |
48addcc9 | 5792 | dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE); |
6f0333b8 ED |
5793 | prefetch(data); |
5794 | skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size); | |
5795 | if (skb) | |
5796 | memcpy(skb->data, data, pkt_size); | |
48addcc9 SG |
5797 | dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE); |
5798 | ||
6f0333b8 | 5799 | return skb; |
1da177e4 LT |
5800 | } |
5801 | ||
da78dbff | 5802 | static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget) |
1da177e4 LT |
5803 | { |
5804 | unsigned int cur_rx, rx_left; | |
6f0333b8 | 5805 | unsigned int count; |
1da177e4 | 5806 | |
1da177e4 LT |
5807 | cur_rx = tp->cur_rx; |
5808 | rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx; | |
865c652d | 5809 | rx_left = min(rx_left, budget); |
1da177e4 | 5810 | |
4dcb7d33 | 5811 | for (; rx_left > 0; rx_left--, cur_rx++) { |
1da177e4 | 5812 | unsigned int entry = cur_rx % NUM_RX_DESC; |
126fa4b9 | 5813 | struct RxDesc *desc = tp->RxDescArray + entry; |
1da177e4 LT |
5814 | u32 status; |
5815 | ||
5816 | rmb(); | |
e03f33af | 5817 | status = le32_to_cpu(desc->opts1) & tp->opts1_mask; |
1da177e4 LT |
5818 | |
5819 | if (status & DescOwn) | |
5820 | break; | |
4dcb7d33 | 5821 | if (unlikely(status & RxRES)) { |
bf82c189 JP |
5822 | netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n", |
5823 | status); | |
cebf8cc7 | 5824 | dev->stats.rx_errors++; |
1da177e4 | 5825 | if (status & (RxRWT | RxRUNT)) |
cebf8cc7 | 5826 | dev->stats.rx_length_errors++; |
1da177e4 | 5827 | if (status & RxCRC) |
cebf8cc7 | 5828 | dev->stats.rx_crc_errors++; |
9dccf611 | 5829 | if (status & RxFOVF) { |
da78dbff | 5830 | rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); |
cebf8cc7 | 5831 | dev->stats.rx_fifo_errors++; |
9dccf611 | 5832 | } |
6bbe021d BG |
5833 | if ((status & (RxRUNT | RxCRC)) && |
5834 | !(status & (RxRWT | RxFOVF)) && | |
5835 | (dev->features & NETIF_F_RXALL)) | |
5836 | goto process_pkt; | |
5837 | ||
6f0333b8 | 5838 | rtl8169_mark_to_asic(desc, rx_buf_sz); |
1da177e4 | 5839 | } else { |
6f0333b8 | 5840 | struct sk_buff *skb; |
6bbe021d BG |
5841 | dma_addr_t addr; |
5842 | int pkt_size; | |
5843 | ||
5844 | process_pkt: | |
5845 | addr = le64_to_cpu(desc->addr); | |
79d0c1d2 BG |
5846 | if (likely(!(dev->features & NETIF_F_RXFCS))) |
5847 | pkt_size = (status & 0x00003fff) - 4; | |
5848 | else | |
5849 | pkt_size = status & 0x00003fff; | |
1da177e4 | 5850 | |
126fa4b9 FR |
5851 | /* |
5852 | * The driver does not support incoming fragmented | |
5853 | * frames. They are seen as a symptom of over-mtu | |
5854 | * sized frames. | |
5855 | */ | |
5856 | if (unlikely(rtl8169_fragmented_frame(status))) { | |
cebf8cc7 FR |
5857 | dev->stats.rx_dropped++; |
5858 | dev->stats.rx_length_errors++; | |
6f0333b8 | 5859 | rtl8169_mark_to_asic(desc, rx_buf_sz); |
4dcb7d33 | 5860 | continue; |
126fa4b9 FR |
5861 | } |
5862 | ||
6f0333b8 ED |
5863 | skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry], |
5864 | tp, pkt_size, addr); | |
5865 | rtl8169_mark_to_asic(desc, rx_buf_sz); | |
5866 | if (!skb) { | |
5867 | dev->stats.rx_dropped++; | |
5868 | continue; | |
1da177e4 LT |
5869 | } |
5870 | ||
adea1ac7 | 5871 | rtl8169_rx_csum(skb, status); |
1da177e4 LT |
5872 | skb_put(skb, pkt_size); |
5873 | skb->protocol = eth_type_trans(skb, dev); | |
5874 | ||
7a8fc77b FR |
5875 | rtl8169_rx_vlan_tag(desc, skb); |
5876 | ||
56de414c | 5877 | napi_gro_receive(&tp->napi, skb); |
1da177e4 | 5878 | |
8027aa24 JW |
5879 | u64_stats_update_begin(&tp->rx_stats.syncp); |
5880 | tp->rx_stats.packets++; | |
5881 | tp->rx_stats.bytes += pkt_size; | |
5882 | u64_stats_update_end(&tp->rx_stats.syncp); | |
1da177e4 | 5883 | } |
6dccd16b FR |
5884 | |
5885 | /* Work around for AMD plateform. */ | |
95e0918d | 5886 | if ((desc->opts2 & cpu_to_le32(0xfffe000)) && |
6dccd16b FR |
5887 | (tp->mac_version == RTL_GIGA_MAC_VER_05)) { |
5888 | desc->opts2 = 0; | |
5889 | cur_rx++; | |
5890 | } | |
1da177e4 LT |
5891 | } |
5892 | ||
5893 | count = cur_rx - tp->cur_rx; | |
5894 | tp->cur_rx = cur_rx; | |
5895 | ||
6f0333b8 | 5896 | tp->dirty_rx += count; |
1da177e4 LT |
5897 | |
5898 | return count; | |
5899 | } | |
5900 | ||
07d3f51f | 5901 | static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance) |
1da177e4 | 5902 | { |
07d3f51f | 5903 | struct net_device *dev = dev_instance; |
1da177e4 | 5904 | struct rtl8169_private *tp = netdev_priv(dev); |
1da177e4 | 5905 | int handled = 0; |
9085cdfa | 5906 | u16 status; |
1da177e4 | 5907 | |
9085cdfa | 5908 | status = rtl_get_events(tp); |
da78dbff FR |
5909 | if (status && status != 0xffff) { |
5910 | status &= RTL_EVENT_NAPI | tp->event_slow; | |
5911 | if (status) { | |
5912 | handled = 1; | |
1da177e4 | 5913 | |
da78dbff FR |
5914 | rtl_irq_disable(tp); |
5915 | napi_schedule(&tp->napi); | |
f11a377b | 5916 | } |
da78dbff FR |
5917 | } |
5918 | return IRQ_RETVAL(handled); | |
5919 | } | |
1da177e4 | 5920 | |
da78dbff FR |
5921 | /* |
5922 | * Workqueue context. | |
5923 | */ | |
5924 | static void rtl_slow_event_work(struct rtl8169_private *tp) | |
5925 | { | |
5926 | struct net_device *dev = tp->dev; | |
5927 | u16 status; | |
5928 | ||
5929 | status = rtl_get_events(tp) & tp->event_slow; | |
5930 | rtl_ack_events(tp, status); | |
1da177e4 | 5931 | |
da78dbff FR |
5932 | if (unlikely(status & RxFIFOOver)) { |
5933 | switch (tp->mac_version) { | |
5934 | /* Work around for rx fifo overflow */ | |
5935 | case RTL_GIGA_MAC_VER_11: | |
5936 | netif_stop_queue(dev); | |
934714d0 FR |
5937 | /* XXX - Hack alert. See rtl_task(). */ |
5938 | set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags); | |
da78dbff | 5939 | default: |
f11a377b DD |
5940 | break; |
5941 | } | |
da78dbff | 5942 | } |
1da177e4 | 5943 | |
da78dbff FR |
5944 | if (unlikely(status & SYSErr)) |
5945 | rtl8169_pcierr_interrupt(dev); | |
0e485150 | 5946 | |
da78dbff FR |
5947 | if (status & LinkChg) |
5948 | __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true); | |
1da177e4 | 5949 | |
7dbb4918 | 5950 | rtl_irq_enable_all(tp); |
1da177e4 LT |
5951 | } |
5952 | ||
4422bcd4 FR |
5953 | static void rtl_task(struct work_struct *work) |
5954 | { | |
da78dbff FR |
5955 | static const struct { |
5956 | int bitnr; | |
5957 | void (*action)(struct rtl8169_private *); | |
5958 | } rtl_work[] = { | |
934714d0 | 5959 | /* XXX - keep rtl_slow_event_work() as first element. */ |
da78dbff FR |
5960 | { RTL_FLAG_TASK_SLOW_PENDING, rtl_slow_event_work }, |
5961 | { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work }, | |
5962 | { RTL_FLAG_TASK_PHY_PENDING, rtl_phy_work } | |
5963 | }; | |
4422bcd4 FR |
5964 | struct rtl8169_private *tp = |
5965 | container_of(work, struct rtl8169_private, wk.work); | |
da78dbff FR |
5966 | struct net_device *dev = tp->dev; |
5967 | int i; | |
5968 | ||
5969 | rtl_lock_work(tp); | |
5970 | ||
6c4a70c5 FR |
5971 | if (!netif_running(dev) || |
5972 | !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags)) | |
da78dbff FR |
5973 | goto out_unlock; |
5974 | ||
5975 | for (i = 0; i < ARRAY_SIZE(rtl_work); i++) { | |
5976 | bool pending; | |
5977 | ||
da78dbff | 5978 | pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags); |
da78dbff FR |
5979 | if (pending) |
5980 | rtl_work[i].action(tp); | |
5981 | } | |
4422bcd4 | 5982 | |
da78dbff FR |
5983 | out_unlock: |
5984 | rtl_unlock_work(tp); | |
4422bcd4 FR |
5985 | } |
5986 | ||
bea3348e | 5987 | static int rtl8169_poll(struct napi_struct *napi, int budget) |
1da177e4 | 5988 | { |
bea3348e SH |
5989 | struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi); |
5990 | struct net_device *dev = tp->dev; | |
da78dbff FR |
5991 | u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow; |
5992 | int work_done= 0; | |
5993 | u16 status; | |
5994 | ||
5995 | status = rtl_get_events(tp); | |
5996 | rtl_ack_events(tp, status & ~tp->event_slow); | |
5997 | ||
5998 | if (status & RTL_EVENT_NAPI_RX) | |
5999 | work_done = rtl_rx(dev, tp, (u32) budget); | |
6000 | ||
6001 | if (status & RTL_EVENT_NAPI_TX) | |
6002 | rtl_tx(dev, tp); | |
1da177e4 | 6003 | |
da78dbff FR |
6004 | if (status & tp->event_slow) { |
6005 | enable_mask &= ~tp->event_slow; | |
6006 | ||
6007 | rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING); | |
6008 | } | |
1da177e4 | 6009 | |
bea3348e | 6010 | if (work_done < budget) { |
288379f0 | 6011 | napi_complete(napi); |
f11a377b | 6012 | |
da78dbff FR |
6013 | rtl_irq_enable(tp, enable_mask); |
6014 | mmiowb(); | |
1da177e4 LT |
6015 | } |
6016 | ||
bea3348e | 6017 | return work_done; |
1da177e4 | 6018 | } |
1da177e4 | 6019 | |
523a6094 FR |
6020 | static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr) |
6021 | { | |
6022 | struct rtl8169_private *tp = netdev_priv(dev); | |
6023 | ||
6024 | if (tp->mac_version > RTL_GIGA_MAC_VER_06) | |
6025 | return; | |
6026 | ||
6027 | dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff); | |
6028 | RTL_W32(RxMissed, 0); | |
6029 | } | |
6030 | ||
1da177e4 LT |
6031 | static void rtl8169_down(struct net_device *dev) |
6032 | { | |
6033 | struct rtl8169_private *tp = netdev_priv(dev); | |
6034 | void __iomem *ioaddr = tp->mmio_addr; | |
1da177e4 | 6035 | |
4876cc1e | 6036 | del_timer_sync(&tp->timer); |
1da177e4 | 6037 | |
93dd79e8 | 6038 | napi_disable(&tp->napi); |
da78dbff | 6039 | netif_stop_queue(dev); |
1da177e4 | 6040 | |
92fc43b4 | 6041 | rtl8169_hw_reset(tp); |
323bb685 SG |
6042 | /* |
6043 | * At this point device interrupts can not be enabled in any function, | |
209e5ac8 FR |
6044 | * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task) |
6045 | * and napi is disabled (rtl8169_poll). | |
323bb685 | 6046 | */ |
523a6094 | 6047 | rtl8169_rx_missed(dev, ioaddr); |
1da177e4 | 6048 | |
1da177e4 | 6049 | /* Give a racing hard_start_xmit a few cycles to complete. */ |
da78dbff | 6050 | synchronize_sched(); |
1da177e4 | 6051 | |
1da177e4 LT |
6052 | rtl8169_tx_clear(tp); |
6053 | ||
6054 | rtl8169_rx_clear(tp); | |
065c27c1 | 6055 | |
6056 | rtl_pll_power_down(tp); | |
1da177e4 LT |
6057 | } |
6058 | ||
6059 | static int rtl8169_close(struct net_device *dev) | |
6060 | { | |
6061 | struct rtl8169_private *tp = netdev_priv(dev); | |
6062 | struct pci_dev *pdev = tp->pci_dev; | |
6063 | ||
e1759441 RW |
6064 | pm_runtime_get_sync(&pdev->dev); |
6065 | ||
cecb5fd7 | 6066 | /* Update counters before going down */ |
355423d0 IV |
6067 | rtl8169_update_counters(dev); |
6068 | ||
da78dbff | 6069 | rtl_lock_work(tp); |
6c4a70c5 | 6070 | clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags); |
da78dbff | 6071 | |
1da177e4 | 6072 | rtl8169_down(dev); |
da78dbff | 6073 | rtl_unlock_work(tp); |
1da177e4 | 6074 | |
92a7c4e7 | 6075 | free_irq(pdev->irq, dev); |
1da177e4 | 6076 | |
82553bb6 SG |
6077 | dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, |
6078 | tp->RxPhyAddr); | |
6079 | dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, | |
6080 | tp->TxPhyAddr); | |
1da177e4 LT |
6081 | tp->TxDescArray = NULL; |
6082 | tp->RxDescArray = NULL; | |
6083 | ||
e1759441 RW |
6084 | pm_runtime_put_sync(&pdev->dev); |
6085 | ||
1da177e4 LT |
6086 | return 0; |
6087 | } | |
6088 | ||
dc1c00ce FR |
6089 | #ifdef CONFIG_NET_POLL_CONTROLLER |
6090 | static void rtl8169_netpoll(struct net_device *dev) | |
6091 | { | |
6092 | struct rtl8169_private *tp = netdev_priv(dev); | |
6093 | ||
6094 | rtl8169_interrupt(tp->pci_dev->irq, dev); | |
6095 | } | |
6096 | #endif | |
6097 | ||
df43ac78 FR |
6098 | static int rtl_open(struct net_device *dev) |
6099 | { | |
6100 | struct rtl8169_private *tp = netdev_priv(dev); | |
6101 | void __iomem *ioaddr = tp->mmio_addr; | |
6102 | struct pci_dev *pdev = tp->pci_dev; | |
6103 | int retval = -ENOMEM; | |
6104 | ||
6105 | pm_runtime_get_sync(&pdev->dev); | |
6106 | ||
6107 | /* | |
e75d6606 | 6108 | * Rx and Tx descriptors needs 256 bytes alignment. |
df43ac78 FR |
6109 | * dma_alloc_coherent provides more. |
6110 | */ | |
6111 | tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES, | |
6112 | &tp->TxPhyAddr, GFP_KERNEL); | |
6113 | if (!tp->TxDescArray) | |
6114 | goto err_pm_runtime_put; | |
6115 | ||
6116 | tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES, | |
6117 | &tp->RxPhyAddr, GFP_KERNEL); | |
6118 | if (!tp->RxDescArray) | |
6119 | goto err_free_tx_0; | |
6120 | ||
6121 | retval = rtl8169_init_ring(dev); | |
6122 | if (retval < 0) | |
6123 | goto err_free_rx_1; | |
6124 | ||
6125 | INIT_WORK(&tp->wk.work, rtl_task); | |
6126 | ||
6127 | smp_mb(); | |
6128 | ||
6129 | rtl_request_firmware(tp); | |
6130 | ||
92a7c4e7 | 6131 | retval = request_irq(pdev->irq, rtl8169_interrupt, |
df43ac78 FR |
6132 | (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED, |
6133 | dev->name, dev); | |
6134 | if (retval < 0) | |
6135 | goto err_release_fw_2; | |
6136 | ||
6137 | rtl_lock_work(tp); | |
6138 | ||
6139 | set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags); | |
6140 | ||
6141 | napi_enable(&tp->napi); | |
6142 | ||
6143 | rtl8169_init_phy(dev, tp); | |
6144 | ||
6145 | __rtl8169_set_features(dev, dev->features); | |
6146 | ||
6147 | rtl_pll_power_up(tp); | |
6148 | ||
6149 | rtl_hw_start(dev); | |
6150 | ||
6151 | netif_start_queue(dev); | |
6152 | ||
6153 | rtl_unlock_work(tp); | |
6154 | ||
6155 | tp->saved_wolopts = 0; | |
6156 | pm_runtime_put_noidle(&pdev->dev); | |
6157 | ||
6158 | rtl8169_check_link_status(dev, tp, ioaddr); | |
6159 | out: | |
6160 | return retval; | |
6161 | ||
6162 | err_release_fw_2: | |
6163 | rtl_release_firmware(tp); | |
6164 | rtl8169_rx_clear(tp); | |
6165 | err_free_rx_1: | |
6166 | dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, | |
6167 | tp->RxPhyAddr); | |
6168 | tp->RxDescArray = NULL; | |
6169 | err_free_tx_0: | |
6170 | dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, | |
6171 | tp->TxPhyAddr); | |
6172 | tp->TxDescArray = NULL; | |
6173 | err_pm_runtime_put: | |
6174 | pm_runtime_put_noidle(&pdev->dev); | |
6175 | goto out; | |
6176 | } | |
6177 | ||
8027aa24 JW |
6178 | static struct rtnl_link_stats64 * |
6179 | rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) | |
1da177e4 LT |
6180 | { |
6181 | struct rtl8169_private *tp = netdev_priv(dev); | |
6182 | void __iomem *ioaddr = tp->mmio_addr; | |
8027aa24 | 6183 | unsigned int start; |
1da177e4 | 6184 | |
da78dbff | 6185 | if (netif_running(dev)) |
523a6094 | 6186 | rtl8169_rx_missed(dev, ioaddr); |
5b0384f4 | 6187 | |
8027aa24 JW |
6188 | do { |
6189 | start = u64_stats_fetch_begin_bh(&tp->rx_stats.syncp); | |
6190 | stats->rx_packets = tp->rx_stats.packets; | |
6191 | stats->rx_bytes = tp->rx_stats.bytes; | |
6192 | } while (u64_stats_fetch_retry_bh(&tp->rx_stats.syncp, start)); | |
6193 | ||
6194 | ||
6195 | do { | |
6196 | start = u64_stats_fetch_begin_bh(&tp->tx_stats.syncp); | |
6197 | stats->tx_packets = tp->tx_stats.packets; | |
6198 | stats->tx_bytes = tp->tx_stats.bytes; | |
6199 | } while (u64_stats_fetch_retry_bh(&tp->tx_stats.syncp, start)); | |
6200 | ||
6201 | stats->rx_dropped = dev->stats.rx_dropped; | |
6202 | stats->tx_dropped = dev->stats.tx_dropped; | |
6203 | stats->rx_length_errors = dev->stats.rx_length_errors; | |
6204 | stats->rx_errors = dev->stats.rx_errors; | |
6205 | stats->rx_crc_errors = dev->stats.rx_crc_errors; | |
6206 | stats->rx_fifo_errors = dev->stats.rx_fifo_errors; | |
6207 | stats->rx_missed_errors = dev->stats.rx_missed_errors; | |
6208 | ||
6209 | return stats; | |
1da177e4 LT |
6210 | } |
6211 | ||
861ab440 | 6212 | static void rtl8169_net_suspend(struct net_device *dev) |
5d06a99f | 6213 | { |
065c27c1 | 6214 | struct rtl8169_private *tp = netdev_priv(dev); |
6215 | ||
5d06a99f | 6216 | if (!netif_running(dev)) |
861ab440 | 6217 | return; |
5d06a99f FR |
6218 | |
6219 | netif_device_detach(dev); | |
6220 | netif_stop_queue(dev); | |
da78dbff FR |
6221 | |
6222 | rtl_lock_work(tp); | |
6223 | napi_disable(&tp->napi); | |
6c4a70c5 | 6224 | clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags); |
da78dbff FR |
6225 | rtl_unlock_work(tp); |
6226 | ||
6227 | rtl_pll_power_down(tp); | |
861ab440 RW |
6228 | } |
6229 | ||
6230 | #ifdef CONFIG_PM | |
6231 | ||
6232 | static int rtl8169_suspend(struct device *device) | |
6233 | { | |
6234 | struct pci_dev *pdev = to_pci_dev(device); | |
6235 | struct net_device *dev = pci_get_drvdata(pdev); | |
5d06a99f | 6236 | |
861ab440 | 6237 | rtl8169_net_suspend(dev); |
1371fa6d | 6238 | |
5d06a99f FR |
6239 | return 0; |
6240 | } | |
6241 | ||
e1759441 RW |
6242 | static void __rtl8169_resume(struct net_device *dev) |
6243 | { | |
065c27c1 | 6244 | struct rtl8169_private *tp = netdev_priv(dev); |
6245 | ||
e1759441 | 6246 | netif_device_attach(dev); |
065c27c1 | 6247 | |
6248 | rtl_pll_power_up(tp); | |
6249 | ||
cff4c162 AS |
6250 | rtl_lock_work(tp); |
6251 | napi_enable(&tp->napi); | |
6c4a70c5 | 6252 | set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags); |
cff4c162 | 6253 | rtl_unlock_work(tp); |
da78dbff | 6254 | |
98ddf986 | 6255 | rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); |
e1759441 RW |
6256 | } |
6257 | ||
861ab440 | 6258 | static int rtl8169_resume(struct device *device) |
5d06a99f | 6259 | { |
861ab440 | 6260 | struct pci_dev *pdev = to_pci_dev(device); |
5d06a99f | 6261 | struct net_device *dev = pci_get_drvdata(pdev); |
fccec10b SG |
6262 | struct rtl8169_private *tp = netdev_priv(dev); |
6263 | ||
6264 | rtl8169_init_phy(dev, tp); | |
5d06a99f | 6265 | |
e1759441 RW |
6266 | if (netif_running(dev)) |
6267 | __rtl8169_resume(dev); | |
5d06a99f | 6268 | |
e1759441 RW |
6269 | return 0; |
6270 | } | |
6271 | ||
6272 | static int rtl8169_runtime_suspend(struct device *device) | |
6273 | { | |
6274 | struct pci_dev *pdev = to_pci_dev(device); | |
6275 | struct net_device *dev = pci_get_drvdata(pdev); | |
6276 | struct rtl8169_private *tp = netdev_priv(dev); | |
6277 | ||
6278 | if (!tp->TxDescArray) | |
6279 | return 0; | |
6280 | ||
da78dbff | 6281 | rtl_lock_work(tp); |
e1759441 RW |
6282 | tp->saved_wolopts = __rtl8169_get_wol(tp); |
6283 | __rtl8169_set_wol(tp, WAKE_ANY); | |
da78dbff | 6284 | rtl_unlock_work(tp); |
e1759441 RW |
6285 | |
6286 | rtl8169_net_suspend(dev); | |
6287 | ||
6288 | return 0; | |
6289 | } | |
6290 | ||
6291 | static int rtl8169_runtime_resume(struct device *device) | |
6292 | { | |
6293 | struct pci_dev *pdev = to_pci_dev(device); | |
6294 | struct net_device *dev = pci_get_drvdata(pdev); | |
6295 | struct rtl8169_private *tp = netdev_priv(dev); | |
6296 | ||
6297 | if (!tp->TxDescArray) | |
6298 | return 0; | |
6299 | ||
da78dbff | 6300 | rtl_lock_work(tp); |
e1759441 RW |
6301 | __rtl8169_set_wol(tp, tp->saved_wolopts); |
6302 | tp->saved_wolopts = 0; | |
da78dbff | 6303 | rtl_unlock_work(tp); |
e1759441 | 6304 | |
fccec10b SG |
6305 | rtl8169_init_phy(dev, tp); |
6306 | ||
e1759441 | 6307 | __rtl8169_resume(dev); |
5d06a99f | 6308 | |
5d06a99f FR |
6309 | return 0; |
6310 | } | |
6311 | ||
e1759441 RW |
6312 | static int rtl8169_runtime_idle(struct device *device) |
6313 | { | |
6314 | struct pci_dev *pdev = to_pci_dev(device); | |
6315 | struct net_device *dev = pci_get_drvdata(pdev); | |
6316 | struct rtl8169_private *tp = netdev_priv(dev); | |
6317 | ||
e4fbce74 | 6318 | return tp->TxDescArray ? -EBUSY : 0; |
e1759441 RW |
6319 | } |
6320 | ||
47145210 | 6321 | static const struct dev_pm_ops rtl8169_pm_ops = { |
cecb5fd7 FR |
6322 | .suspend = rtl8169_suspend, |
6323 | .resume = rtl8169_resume, | |
6324 | .freeze = rtl8169_suspend, | |
6325 | .thaw = rtl8169_resume, | |
6326 | .poweroff = rtl8169_suspend, | |
6327 | .restore = rtl8169_resume, | |
6328 | .runtime_suspend = rtl8169_runtime_suspend, | |
6329 | .runtime_resume = rtl8169_runtime_resume, | |
6330 | .runtime_idle = rtl8169_runtime_idle, | |
861ab440 RW |
6331 | }; |
6332 | ||
6333 | #define RTL8169_PM_OPS (&rtl8169_pm_ops) | |
6334 | ||
6335 | #else /* !CONFIG_PM */ | |
6336 | ||
6337 | #define RTL8169_PM_OPS NULL | |
6338 | ||
6339 | #endif /* !CONFIG_PM */ | |
6340 | ||
649b3b8c | 6341 | static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp) |
6342 | { | |
6343 | void __iomem *ioaddr = tp->mmio_addr; | |
6344 | ||
6345 | /* WoL fails with 8168b when the receiver is disabled. */ | |
6346 | switch (tp->mac_version) { | |
6347 | case RTL_GIGA_MAC_VER_11: | |
6348 | case RTL_GIGA_MAC_VER_12: | |
6349 | case RTL_GIGA_MAC_VER_17: | |
6350 | pci_clear_master(tp->pci_dev); | |
6351 | ||
6352 | RTL_W8(ChipCmd, CmdRxEnb); | |
6353 | /* PCI commit */ | |
6354 | RTL_R8(ChipCmd); | |
6355 | break; | |
6356 | default: | |
6357 | break; | |
6358 | } | |
6359 | } | |
6360 | ||
1765f95d FR |
6361 | static void rtl_shutdown(struct pci_dev *pdev) |
6362 | { | |
861ab440 | 6363 | struct net_device *dev = pci_get_drvdata(pdev); |
4bb3f522 | 6364 | struct rtl8169_private *tp = netdev_priv(dev); |
2a15cd2f | 6365 | struct device *d = &pdev->dev; |
6366 | ||
6367 | pm_runtime_get_sync(d); | |
861ab440 RW |
6368 | |
6369 | rtl8169_net_suspend(dev); | |
1765f95d | 6370 | |
cecb5fd7 | 6371 | /* Restore original MAC address */ |
cc098dc7 IV |
6372 | rtl_rar_set(tp, dev->perm_addr); |
6373 | ||
92fc43b4 | 6374 | rtl8169_hw_reset(tp); |
4bb3f522 | 6375 | |
861ab440 | 6376 | if (system_state == SYSTEM_POWER_OFF) { |
649b3b8c | 6377 | if (__rtl8169_get_wol(tp) & WAKE_ANY) { |
6378 | rtl_wol_suspend_quirk(tp); | |
6379 | rtl_wol_shutdown_quirk(tp); | |
ca52efd5 | 6380 | } |
6381 | ||
861ab440 RW |
6382 | pci_wake_from_d3(pdev, true); |
6383 | pci_set_power_state(pdev, PCI_D3hot); | |
6384 | } | |
2a15cd2f | 6385 | |
6386 | pm_runtime_put_noidle(d); | |
861ab440 | 6387 | } |
5d06a99f | 6388 | |
e27566ed FR |
6389 | static void __devexit rtl_remove_one(struct pci_dev *pdev) |
6390 | { | |
6391 | struct net_device *dev = pci_get_drvdata(pdev); | |
6392 | struct rtl8169_private *tp = netdev_priv(dev); | |
6393 | ||
6394 | if (tp->mac_version == RTL_GIGA_MAC_VER_27 || | |
6395 | tp->mac_version == RTL_GIGA_MAC_VER_28 || | |
6396 | tp->mac_version == RTL_GIGA_MAC_VER_31) { | |
6397 | rtl8168_driver_stop(tp); | |
6398 | } | |
6399 | ||
6400 | cancel_work_sync(&tp->wk.work); | |
6401 | ||
ad1be8d3 DN |
6402 | netif_napi_del(&tp->napi); |
6403 | ||
e27566ed FR |
6404 | unregister_netdev(dev); |
6405 | ||
6406 | rtl_release_firmware(tp); | |
6407 | ||
6408 | if (pci_dev_run_wake(pdev)) | |
6409 | pm_runtime_get_noresume(&pdev->dev); | |
6410 | ||
6411 | /* restore original MAC address */ | |
6412 | rtl_rar_set(tp, dev->perm_addr); | |
6413 | ||
6414 | rtl_disable_msi(pdev, tp); | |
6415 | rtl8169_release_board(pdev, dev, tp->mmio_addr); | |
6416 | pci_set_drvdata(pdev, NULL); | |
6417 | } | |
6418 | ||
fa9c385e | 6419 | static const struct net_device_ops rtl_netdev_ops = { |
df43ac78 | 6420 | .ndo_open = rtl_open, |
fa9c385e FR |
6421 | .ndo_stop = rtl8169_close, |
6422 | .ndo_get_stats64 = rtl8169_get_stats64, | |
6423 | .ndo_start_xmit = rtl8169_start_xmit, | |
6424 | .ndo_tx_timeout = rtl8169_tx_timeout, | |
6425 | .ndo_validate_addr = eth_validate_addr, | |
6426 | .ndo_change_mtu = rtl8169_change_mtu, | |
6427 | .ndo_fix_features = rtl8169_fix_features, | |
6428 | .ndo_set_features = rtl8169_set_features, | |
6429 | .ndo_set_mac_address = rtl_set_mac_address, | |
6430 | .ndo_do_ioctl = rtl8169_ioctl, | |
6431 | .ndo_set_rx_mode = rtl_set_rx_mode, | |
6432 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
6433 | .ndo_poll_controller = rtl8169_netpoll, | |
6434 | #endif | |
6435 | ||
6436 | }; | |
6437 | ||
31fa8b18 FR |
6438 | static const struct rtl_cfg_info { |
6439 | void (*hw_start)(struct net_device *); | |
6440 | unsigned int region; | |
6441 | unsigned int align; | |
6442 | u16 event_slow; | |
6443 | unsigned features; | |
6444 | u8 default_ver; | |
6445 | } rtl_cfg_infos [] = { | |
6446 | [RTL_CFG_0] = { | |
6447 | .hw_start = rtl_hw_start_8169, | |
6448 | .region = 1, | |
6449 | .align = 0, | |
6450 | .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver, | |
6451 | .features = RTL_FEATURE_GMII, | |
6452 | .default_ver = RTL_GIGA_MAC_VER_01, | |
6453 | }, | |
6454 | [RTL_CFG_1] = { | |
6455 | .hw_start = rtl_hw_start_8168, | |
6456 | .region = 2, | |
6457 | .align = 8, | |
6458 | .event_slow = SYSErr | LinkChg | RxOverflow, | |
6459 | .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI, | |
6460 | .default_ver = RTL_GIGA_MAC_VER_11, | |
6461 | }, | |
6462 | [RTL_CFG_2] = { | |
6463 | .hw_start = rtl_hw_start_8101, | |
6464 | .region = 2, | |
6465 | .align = 8, | |
6466 | .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver | | |
6467 | PCSTimeout, | |
6468 | .features = RTL_FEATURE_MSI, | |
6469 | .default_ver = RTL_GIGA_MAC_VER_13, | |
6470 | } | |
6471 | }; | |
6472 | ||
6473 | /* Cfg9346_Unlock assumed. */ | |
6474 | static unsigned rtl_try_msi(struct rtl8169_private *tp, | |
6475 | const struct rtl_cfg_info *cfg) | |
6476 | { | |
6477 | void __iomem *ioaddr = tp->mmio_addr; | |
6478 | unsigned msi = 0; | |
6479 | u8 cfg2; | |
6480 | ||
6481 | cfg2 = RTL_R8(Config2) & ~MSIEnable; | |
6482 | if (cfg->features & RTL_FEATURE_MSI) { | |
6483 | if (pci_enable_msi(tp->pci_dev)) { | |
6484 | netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n"); | |
6485 | } else { | |
6486 | cfg2 |= MSIEnable; | |
6487 | msi = RTL_FEATURE_MSI; | |
6488 | } | |
6489 | } | |
6490 | if (tp->mac_version <= RTL_GIGA_MAC_VER_06) | |
6491 | RTL_W8(Config2, cfg2); | |
6492 | return msi; | |
6493 | } | |
6494 | ||
3b6cf25d FR |
6495 | static int __devinit |
6496 | rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) | |
6497 | { | |
6498 | const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data; | |
6499 | const unsigned int region = cfg->region; | |
6500 | struct rtl8169_private *tp; | |
6501 | struct mii_if_info *mii; | |
6502 | struct net_device *dev; | |
6503 | void __iomem *ioaddr; | |
6504 | int chipset, i; | |
6505 | int rc; | |
6506 | ||
6507 | if (netif_msg_drv(&debug)) { | |
6508 | printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n", | |
6509 | MODULENAME, RTL8169_VERSION); | |
6510 | } | |
6511 | ||
6512 | dev = alloc_etherdev(sizeof (*tp)); | |
6513 | if (!dev) { | |
6514 | rc = -ENOMEM; | |
6515 | goto out; | |
6516 | } | |
6517 | ||
6518 | SET_NETDEV_DEV(dev, &pdev->dev); | |
fa9c385e | 6519 | dev->netdev_ops = &rtl_netdev_ops; |
3b6cf25d FR |
6520 | tp = netdev_priv(dev); |
6521 | tp->dev = dev; | |
6522 | tp->pci_dev = pdev; | |
6523 | tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT); | |
6524 | ||
6525 | mii = &tp->mii; | |
6526 | mii->dev = dev; | |
6527 | mii->mdio_read = rtl_mdio_read; | |
6528 | mii->mdio_write = rtl_mdio_write; | |
6529 | mii->phy_id_mask = 0x1f; | |
6530 | mii->reg_num_mask = 0x1f; | |
6531 | mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII); | |
6532 | ||
6533 | /* disable ASPM completely as that cause random device stop working | |
6534 | * problems as well as full system hangs for some PCIe devices users */ | |
6535 | pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 | | |
6536 | PCIE_LINK_STATE_CLKPM); | |
6537 | ||
6538 | /* enable device (incl. PCI PM wakeup and hotplug setup) */ | |
6539 | rc = pci_enable_device(pdev); | |
6540 | if (rc < 0) { | |
6541 | netif_err(tp, probe, dev, "enable failure\n"); | |
6542 | goto err_out_free_dev_1; | |
6543 | } | |
6544 | ||
6545 | if (pci_set_mwi(pdev) < 0) | |
6546 | netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n"); | |
6547 | ||
6548 | /* make sure PCI base addr 1 is MMIO */ | |
6549 | if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) { | |
6550 | netif_err(tp, probe, dev, | |
6551 | "region #%d not an MMIO resource, aborting\n", | |
6552 | region); | |
6553 | rc = -ENODEV; | |
6554 | goto err_out_mwi_2; | |
6555 | } | |
6556 | ||
6557 | /* check for weird/broken PCI region reporting */ | |
6558 | if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) { | |
6559 | netif_err(tp, probe, dev, | |
6560 | "Invalid PCI region size(s), aborting\n"); | |
6561 | rc = -ENODEV; | |
6562 | goto err_out_mwi_2; | |
6563 | } | |
6564 | ||
6565 | rc = pci_request_regions(pdev, MODULENAME); | |
6566 | if (rc < 0) { | |
6567 | netif_err(tp, probe, dev, "could not request regions\n"); | |
6568 | goto err_out_mwi_2; | |
6569 | } | |
6570 | ||
6571 | tp->cp_cmd = RxChkSum; | |
6572 | ||
6573 | if ((sizeof(dma_addr_t) > 4) && | |
6574 | !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) { | |
6575 | tp->cp_cmd |= PCIDAC; | |
6576 | dev->features |= NETIF_F_HIGHDMA; | |
6577 | } else { | |
6578 | rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); | |
6579 | if (rc < 0) { | |
6580 | netif_err(tp, probe, dev, "DMA configuration failed\n"); | |
6581 | goto err_out_free_res_3; | |
6582 | } | |
6583 | } | |
6584 | ||
6585 | /* ioremap MMIO region */ | |
6586 | ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE); | |
6587 | if (!ioaddr) { | |
6588 | netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n"); | |
6589 | rc = -EIO; | |
6590 | goto err_out_free_res_3; | |
6591 | } | |
6592 | tp->mmio_addr = ioaddr; | |
6593 | ||
6594 | if (!pci_is_pcie(pdev)) | |
6595 | netif_info(tp, probe, dev, "not PCI Express\n"); | |
6596 | ||
6597 | /* Identify chip attached to board */ | |
6598 | rtl8169_get_mac_version(tp, dev, cfg->default_ver); | |
6599 | ||
6600 | rtl_init_rxcfg(tp); | |
6601 | ||
6602 | rtl_irq_disable(tp); | |
6603 | ||
6604 | rtl_hw_reset(tp); | |
6605 | ||
6606 | rtl_ack_events(tp, 0xffff); | |
6607 | ||
6608 | pci_set_master(pdev); | |
6609 | ||
6610 | /* | |
6611 | * Pretend we are using VLANs; This bypasses a nasty bug where | |
6612 | * Interrupts stop flowing on high load on 8110SCd controllers. | |
6613 | */ | |
6614 | if (tp->mac_version == RTL_GIGA_MAC_VER_05) | |
6615 | tp->cp_cmd |= RxVlan; | |
6616 | ||
6617 | rtl_init_mdio_ops(tp); | |
6618 | rtl_init_pll_power_ops(tp); | |
6619 | rtl_init_jumbo_ops(tp); | |
beb1fe18 | 6620 | rtl_init_csi_ops(tp); |
3b6cf25d FR |
6621 | |
6622 | rtl8169_print_mac_version(tp); | |
6623 | ||
6624 | chipset = tp->mac_version; | |
6625 | tp->txd_version = rtl_chip_infos[chipset].txd_version; | |
6626 | ||
6627 | RTL_W8(Cfg9346, Cfg9346_Unlock); | |
6628 | RTL_W8(Config1, RTL_R8(Config1) | PMEnable); | |
6629 | RTL_W8(Config5, RTL_R8(Config5) & PMEStatus); | |
6630 | if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0) | |
6631 | tp->features |= RTL_FEATURE_WOL; | |
6632 | if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0) | |
6633 | tp->features |= RTL_FEATURE_WOL; | |
6634 | tp->features |= rtl_try_msi(tp, cfg); | |
6635 | RTL_W8(Cfg9346, Cfg9346_Lock); | |
6636 | ||
6637 | if (rtl_tbi_enabled(tp)) { | |
6638 | tp->set_speed = rtl8169_set_speed_tbi; | |
6639 | tp->get_settings = rtl8169_gset_tbi; | |
6640 | tp->phy_reset_enable = rtl8169_tbi_reset_enable; | |
6641 | tp->phy_reset_pending = rtl8169_tbi_reset_pending; | |
6642 | tp->link_ok = rtl8169_tbi_link_ok; | |
6643 | tp->do_ioctl = rtl_tbi_ioctl; | |
6644 | } else { | |
6645 | tp->set_speed = rtl8169_set_speed_xmii; | |
6646 | tp->get_settings = rtl8169_gset_xmii; | |
6647 | tp->phy_reset_enable = rtl8169_xmii_reset_enable; | |
6648 | tp->phy_reset_pending = rtl8169_xmii_reset_pending; | |
6649 | tp->link_ok = rtl8169_xmii_link_ok; | |
6650 | tp->do_ioctl = rtl_xmii_ioctl; | |
6651 | } | |
6652 | ||
6653 | mutex_init(&tp->wk.mutex); | |
6654 | ||
6655 | /* Get MAC address */ | |
6656 | for (i = 0; i < ETH_ALEN; i++) | |
6657 | dev->dev_addr[i] = RTL_R8(MAC0 + i); | |
6658 | memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); | |
6659 | ||
6660 | SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops); | |
6661 | dev->watchdog_timeo = RTL8169_TX_TIMEOUT; | |
3b6cf25d FR |
6662 | |
6663 | netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT); | |
6664 | ||
6665 | /* don't enable SG, IP_CSUM and TSO by default - it might not work | |
6666 | * properly for all devices */ | |
6667 | dev->features |= NETIF_F_RXCSUM | | |
6668 | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; | |
6669 | ||
6670 | dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | | |
6671 | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; | |
6672 | dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | | |
6673 | NETIF_F_HIGHDMA; | |
6674 | ||
6675 | if (tp->mac_version == RTL_GIGA_MAC_VER_05) | |
6676 | /* 8110SCd requires hardware Rx VLAN - disallow toggling */ | |
6677 | dev->hw_features &= ~NETIF_F_HW_VLAN_RX; | |
6678 | ||
6679 | dev->hw_features |= NETIF_F_RXALL; | |
6680 | dev->hw_features |= NETIF_F_RXFCS; | |
6681 | ||
6682 | tp->hw_start = cfg->hw_start; | |
6683 | tp->event_slow = cfg->event_slow; | |
6684 | ||
6685 | tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ? | |
6686 | ~(RxBOVF | RxFOVF) : ~0; | |
6687 | ||
6688 | init_timer(&tp->timer); | |
6689 | tp->timer.data = (unsigned long) dev; | |
6690 | tp->timer.function = rtl8169_phy_timer; | |
6691 | ||
6692 | tp->rtl_fw = RTL_FIRMWARE_UNKNOWN; | |
6693 | ||
6694 | rc = register_netdev(dev); | |
6695 | if (rc < 0) | |
6696 | goto err_out_msi_4; | |
6697 | ||
6698 | pci_set_drvdata(pdev, dev); | |
6699 | ||
92a7c4e7 FR |
6700 | netif_info(tp, probe, dev, "%s at 0x%p, %pM, XID %08x IRQ %d\n", |
6701 | rtl_chip_infos[chipset].name, ioaddr, dev->dev_addr, | |
6702 | (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), pdev->irq); | |
3b6cf25d FR |
6703 | if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) { |
6704 | netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, " | |
6705 | "tx checksumming: %s]\n", | |
6706 | rtl_chip_infos[chipset].jumbo_max, | |
6707 | rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko"); | |
6708 | } | |
6709 | ||
6710 | if (tp->mac_version == RTL_GIGA_MAC_VER_27 || | |
6711 | tp->mac_version == RTL_GIGA_MAC_VER_28 || | |
6712 | tp->mac_version == RTL_GIGA_MAC_VER_31) { | |
6713 | rtl8168_driver_start(tp); | |
6714 | } | |
6715 | ||
6716 | device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL); | |
6717 | ||
6718 | if (pci_dev_run_wake(pdev)) | |
6719 | pm_runtime_put_noidle(&pdev->dev); | |
6720 | ||
6721 | netif_carrier_off(dev); | |
6722 | ||
6723 | out: | |
6724 | return rc; | |
6725 | ||
6726 | err_out_msi_4: | |
ad1be8d3 | 6727 | netif_napi_del(&tp->napi); |
3b6cf25d FR |
6728 | rtl_disable_msi(pdev, tp); |
6729 | iounmap(ioaddr); | |
6730 | err_out_free_res_3: | |
6731 | pci_release_regions(pdev); | |
6732 | err_out_mwi_2: | |
6733 | pci_clear_mwi(pdev); | |
6734 | pci_disable_device(pdev); | |
6735 | err_out_free_dev_1: | |
6736 | free_netdev(dev); | |
6737 | goto out; | |
6738 | } | |
6739 | ||
1da177e4 LT |
6740 | static struct pci_driver rtl8169_pci_driver = { |
6741 | .name = MODULENAME, | |
6742 | .id_table = rtl8169_pci_tbl, | |
3b6cf25d | 6743 | .probe = rtl_init_one, |
e27566ed | 6744 | .remove = __devexit_p(rtl_remove_one), |
1765f95d | 6745 | .shutdown = rtl_shutdown, |
861ab440 | 6746 | .driver.pm = RTL8169_PM_OPS, |
1da177e4 LT |
6747 | }; |
6748 | ||
07d3f51f | 6749 | static int __init rtl8169_init_module(void) |
1da177e4 | 6750 | { |
29917620 | 6751 | return pci_register_driver(&rtl8169_pci_driver); |
1da177e4 LT |
6752 | } |
6753 | ||
07d3f51f | 6754 | static void __exit rtl8169_cleanup_module(void) |
1da177e4 LT |
6755 | { |
6756 | pci_unregister_driver(&rtl8169_pci_driver); | |
6757 | } | |
6758 | ||
6759 | module_init(rtl8169_init_module); | |
6760 | module_exit(rtl8169_cleanup_module); |