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09c434b8 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
1da177e4 | 2 | /* |
07d3f51f FR |
3 | * r8169.c: RealTek 8169/8168/8101 ethernet driver. |
4 | * | |
5 | * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw> | |
6 | * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com> | |
7 | * Copyright (c) a lot of people too. Please respect their work. | |
8 | * | |
9 | * See MAINTAINERS file for support contact information. | |
1da177e4 LT |
10 | */ |
11 | ||
12 | #include <linux/module.h> | |
1da177e4 LT |
13 | #include <linux/pci.h> |
14 | #include <linux/netdevice.h> | |
15 | #include <linux/etherdevice.h> | |
c2f6f3ee | 16 | #include <linux/clk.h> |
1da177e4 LT |
17 | #include <linux/delay.h> |
18 | #include <linux/ethtool.h> | |
f1e911d5 | 19 | #include <linux/phy.h> |
1da177e4 | 20 | #include <linux/if_vlan.h> |
1da177e4 | 21 | #include <linux/in.h> |
098b01ad | 22 | #include <linux/io.h> |
1da177e4 LT |
23 | #include <linux/ip.h> |
24 | #include <linux/tcp.h> | |
a6b7a407 | 25 | #include <linux/interrupt.h> |
1da177e4 | 26 | #include <linux/dma-mapping.h> |
e1759441 | 27 | #include <linux/pm_runtime.h> |
6cf96dd4 | 28 | #include <linux/bitfield.h> |
70c71606 | 29 | #include <linux/prefetch.h> |
e974604b | 30 | #include <linux/ipv6.h> |
ae1e82c6 | 31 | #include <asm/unaligned.h> |
e974604b | 32 | #include <net/ip6_checksum.h> |
1da177e4 | 33 | |
2992bdfa | 34 | #include "r8169.h" |
8197f9d2 HK |
35 | #include "r8169_firmware.h" |
36 | ||
bca03d5f | 37 | #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw" |
38 | #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw" | |
01dc7fec | 39 | #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw" |
40 | #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw" | |
70090424 | 41 | #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw" |
c2218925 HW |
42 | #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw" |
43 | #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw" | |
5a5e4443 | 44 | #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw" |
7e18dca1 | 45 | #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw" |
b3d7b2f2 | 46 | #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw" |
45dd95c4 | 47 | #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw" |
5598bfe5 | 48 | #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw" |
58152cd4 | 49 | #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw" |
beb330a4 | 50 | #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw" |
57538c4a | 51 | #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw" |
6e1d0b89 CHL |
52 | #define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw" |
53 | #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw" | |
229c1e0d | 54 | #define FIRMWARE_8168FP_3 "rtl_nic/rtl8168fp-3.fw" |
6e1d0b89 CHL |
55 | #define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw" |
56 | #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw" | |
02bf642b | 57 | #define FIRMWARE_8125A_3 "rtl_nic/rtl8125a-3.fw" |
0439297b | 58 | #define FIRMWARE_8125B_2 "rtl_nic/rtl8125b-2.fw" |
bca03d5f | 59 | |
1da177e4 LT |
60 | /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). |
61 | The RTL chips use a 64 element hash table based on the Ethernet CRC. */ | |
81cd17a4 | 62 | #define MC_FILTER_LIMIT 32 |
1da177e4 | 63 | |
aee77e4a | 64 | #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */ |
1da177e4 LT |
65 | #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ |
66 | ||
67 | #define R8169_REGS_SIZE 256 | |
1d0254dd | 68 | #define R8169_RX_BUF_SIZE (SZ_16K - 1) |
f06059c2 | 69 | #define NUM_TX_DESC 256 /* Number of Tx descriptor registers */ |
ed22a8ff | 70 | #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */ |
1da177e4 LT |
71 | #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc)) |
72 | #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc)) | |
73 | ||
0360c046 HK |
74 | #define OCP_STD_PHY_BASE 0xa400 |
75 | ||
145a40e8 HK |
76 | #define RTL_CFG_NO_GBIT 1 |
77 | ||
1da177e4 | 78 | /* write/read MMIO register */ |
1ef7286e AS |
79 | #define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg)) |
80 | #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg)) | |
81 | #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg)) | |
82 | #define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg)) | |
83 | #define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg)) | |
84 | #define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg)) | |
1da177e4 | 85 | |
b410439c HK |
86 | #define JUMBO_4K (4 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) |
87 | #define JUMBO_6K (6 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) | |
88 | #define JUMBO_7K (7 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) | |
89 | #define JUMBO_9K (9 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) | |
d58d46b5 | 90 | |
3c6bee1d | 91 | static const struct { |
1da177e4 | 92 | const char *name; |
953a12cc | 93 | const char *fw_name; |
85bffe6c FR |
94 | } rtl_chip_infos[] = { |
95 | /* PCI devices. */ | |
abe8b2f7 HK |
96 | [RTL_GIGA_MAC_VER_02] = {"RTL8169s" }, |
97 | [RTL_GIGA_MAC_VER_03] = {"RTL8110s" }, | |
98 | [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb" }, | |
99 | [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc" }, | |
100 | [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc" }, | |
85bffe6c | 101 | /* PCI-E devices. */ |
abe8b2f7 HK |
102 | [RTL_GIGA_MAC_VER_07] = {"RTL8102e" }, |
103 | [RTL_GIGA_MAC_VER_08] = {"RTL8102e" }, | |
9e0773c3 | 104 | [RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e" }, |
abe8b2f7 HK |
105 | [RTL_GIGA_MAC_VER_10] = {"RTL8101e" }, |
106 | [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b" }, | |
107 | [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b" }, | |
93c09ca6 | 108 | [RTL_GIGA_MAC_VER_13] = {"RTL8101e/RTL8100e" }, |
cdafdc29 | 109 | [RTL_GIGA_MAC_VER_14] = {"RTL8401" }, |
abe8b2f7 HK |
110 | [RTL_GIGA_MAC_VER_16] = {"RTL8101e" }, |
111 | [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b" }, | |
112 | [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp" }, | |
113 | [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c" }, | |
114 | [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c" }, | |
115 | [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c" }, | |
116 | [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c" }, | |
117 | [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp" }, | |
118 | [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp" }, | |
119 | [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d", FIRMWARE_8168D_1}, | |
120 | [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d", FIRMWARE_8168D_2}, | |
121 | [RTL_GIGA_MAC_VER_27] = {"RTL8168dp/8111dp" }, | |
122 | [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp" }, | |
123 | [RTL_GIGA_MAC_VER_29] = {"RTL8105e", FIRMWARE_8105E_1}, | |
124 | [RTL_GIGA_MAC_VER_30] = {"RTL8105e", FIRMWARE_8105E_1}, | |
125 | [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp" }, | |
126 | [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e", FIRMWARE_8168E_1}, | |
127 | [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e", FIRMWARE_8168E_2}, | |
128 | [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3}, | |
129 | [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f", FIRMWARE_8168F_1}, | |
130 | [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f", FIRMWARE_8168F_2}, | |
131 | [RTL_GIGA_MAC_VER_37] = {"RTL8402", FIRMWARE_8402_1 }, | |
132 | [RTL_GIGA_MAC_VER_38] = {"RTL8411", FIRMWARE_8411_1 }, | |
133 | [RTL_GIGA_MAC_VER_39] = {"RTL8106e", FIRMWARE_8106E_1}, | |
134 | [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g", FIRMWARE_8168G_2}, | |
135 | [RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g" }, | |
9e0773c3 HK |
136 | [RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu", FIRMWARE_8168G_3}, |
137 | [RTL_GIGA_MAC_VER_43] = {"RTL8106eus", FIRMWARE_8106E_2}, | |
138 | [RTL_GIGA_MAC_VER_44] = {"RTL8411b", FIRMWARE_8411_2 }, | |
abe8b2f7 HK |
139 | [RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h", FIRMWARE_8168H_1}, |
140 | [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h", FIRMWARE_8168H_2}, | |
141 | [RTL_GIGA_MAC_VER_47] = {"RTL8107e", FIRMWARE_8107E_1}, | |
142 | [RTL_GIGA_MAC_VER_48] = {"RTL8107e", FIRMWARE_8107E_2}, | |
143 | [RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep" }, | |
144 | [RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep" }, | |
145 | [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep" }, | |
229c1e0d | 146 | [RTL_GIGA_MAC_VER_52] = {"RTL8168fp/RTL8117", FIRMWARE_8168FP_3}, |
e6d6ca6e | 147 | [RTL_GIGA_MAC_VER_53] = {"RTL8168fp/RTL8117", }, |
4640338c HK |
148 | [RTL_GIGA_MAC_VER_60] = {"RTL8125A" }, |
149 | [RTL_GIGA_MAC_VER_61] = {"RTL8125A", FIRMWARE_8125A_3}, | |
0439297b HK |
150 | /* reserve 62 for CFG_METHOD_4 in the vendor driver */ |
151 | [RTL_GIGA_MAC_VER_63] = {"RTL8125B", FIRMWARE_8125B_2}, | |
953a12cc FR |
152 | }; |
153 | ||
9baa3c34 | 154 | static const struct pci_device_id rtl8169_pci_tbl[] = { |
145a40e8 HK |
155 | { PCI_VDEVICE(REALTEK, 0x2502) }, |
156 | { PCI_VDEVICE(REALTEK, 0x2600) }, | |
157 | { PCI_VDEVICE(REALTEK, 0x8129) }, | |
158 | { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_NO_GBIT }, | |
159 | { PCI_VDEVICE(REALTEK, 0x8161) }, | |
72f898ca | 160 | { PCI_VDEVICE(REALTEK, 0x8162) }, |
145a40e8 HK |
161 | { PCI_VDEVICE(REALTEK, 0x8167) }, |
162 | { PCI_VDEVICE(REALTEK, 0x8168) }, | |
163 | { PCI_VDEVICE(NCUBE, 0x8168) }, | |
164 | { PCI_VDEVICE(REALTEK, 0x8169) }, | |
6f0d3088 | 165 | { PCI_VENDOR_ID_DLINK, 0x4300, |
145a40e8 | 166 | PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 }, |
9d9f3fba HK |
167 | { PCI_VDEVICE(DLINK, 0x4300) }, |
168 | { PCI_VDEVICE(DLINK, 0x4302) }, | |
169 | { PCI_VDEVICE(AT, 0xc107) }, | |
170 | { PCI_VDEVICE(USR, 0x0116) }, | |
171 | { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 }, | |
172 | { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 }, | |
f1bce4ad HK |
173 | { PCI_VDEVICE(REALTEK, 0x8125) }, |
174 | { PCI_VDEVICE(REALTEK, 0x3000) }, | |
6f0d3088 | 175 | {} |
1da177e4 LT |
176 | }; |
177 | ||
178 | MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl); | |
179 | ||
07d3f51f FR |
180 | enum rtl_registers { |
181 | MAC0 = 0, /* Ethernet hardware address. */ | |
773d2021 | 182 | MAC4 = 4, |
07d3f51f FR |
183 | MAR0 = 8, /* Multicast filter. */ |
184 | CounterAddrLow = 0x10, | |
185 | CounterAddrHigh = 0x14, | |
186 | TxDescStartAddrLow = 0x20, | |
187 | TxDescStartAddrHigh = 0x24, | |
188 | TxHDescStartAddrLow = 0x28, | |
189 | TxHDescStartAddrHigh = 0x2c, | |
190 | FLASH = 0x30, | |
191 | ERSR = 0x36, | |
192 | ChipCmd = 0x37, | |
193 | TxPoll = 0x38, | |
194 | IntrMask = 0x3c, | |
195 | IntrStatus = 0x3e, | |
4f6b00e5 | 196 | |
07d3f51f | 197 | TxConfig = 0x40, |
4f6b00e5 HW |
198 | #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */ |
199 | #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */ | |
2b7b4318 | 200 | |
4f6b00e5 HW |
201 | RxConfig = 0x44, |
202 | #define RX128_INT_EN (1 << 15) /* 8111c and later */ | |
203 | #define RX_MULTI_EN (1 << 14) /* 8111c only */ | |
204 | #define RXCFG_FIFO_SHIFT 13 | |
205 | /* No threshold before first PCI xfer */ | |
206 | #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT) | |
beb330a4 | 207 | #define RX_EARLY_OFF (1 << 11) |
4f6b00e5 HW |
208 | #define RXCFG_DMA_SHIFT 8 |
209 | /* Unlimited maximum PCI burst. */ | |
210 | #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT) | |
2b7b4318 | 211 | |
07d3f51f FR |
212 | Cfg9346 = 0x50, |
213 | Config0 = 0x51, | |
214 | Config1 = 0x52, | |
215 | Config2 = 0x53, | |
d387b427 FR |
216 | #define PME_SIGNAL (1 << 5) /* 8168c and later */ |
217 | ||
07d3f51f FR |
218 | Config3 = 0x54, |
219 | Config4 = 0x55, | |
220 | Config5 = 0x56, | |
07d3f51f | 221 | PHYAR = 0x60, |
07d3f51f FR |
222 | PHYstatus = 0x6c, |
223 | RxMaxSize = 0xda, | |
224 | CPlusCmd = 0xe0, | |
225 | IntrMitigate = 0xe2, | |
50970831 | 226 | |
6cf96dd4 HK |
227 | #define RTL_COALESCE_TX_USECS GENMASK(15, 12) |
228 | #define RTL_COALESCE_TX_FRAMES GENMASK(11, 8) | |
229 | #define RTL_COALESCE_RX_USECS GENMASK(7, 4) | |
230 | #define RTL_COALESCE_RX_FRAMES GENMASK(3, 0) | |
231 | ||
2b3e48b6 HK |
232 | #define RTL_COALESCE_T_MAX 0x0fU |
233 | #define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_T_MAX * 4) | |
50970831 | 234 | |
07d3f51f FR |
235 | RxDescAddrLow = 0xe4, |
236 | RxDescAddrHigh = 0xe8, | |
f0298f81 | 237 | EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */ |
238 | ||
239 | #define NoEarlyTx 0x3f /* Max value : no early transmit. */ | |
240 | ||
241 | MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */ | |
242 | ||
243 | #define TxPacketMax (8064 >> 7) | |
3090bd9a | 244 | #define EarlySize 0x27 |
f0298f81 | 245 | |
07d3f51f FR |
246 | FuncEvent = 0xf0, |
247 | FuncEventMask = 0xf4, | |
248 | FuncPresetState = 0xf8, | |
935e2218 CHL |
249 | IBCR0 = 0xf8, |
250 | IBCR2 = 0xf9, | |
251 | IBIMR0 = 0xfa, | |
252 | IBISR0 = 0xfb, | |
07d3f51f | 253 | FuncForceEvent = 0xfc, |
1da177e4 LT |
254 | }; |
255 | ||
f162a5d1 FR |
256 | enum rtl8168_8101_registers { |
257 | CSIDR = 0x64, | |
258 | CSIAR = 0x68, | |
259 | #define CSIAR_FLAG 0x80000000 | |
260 | #define CSIAR_WRITE_CMD 0x80000000 | |
ff1d7331 HK |
261 | #define CSIAR_BYTE_ENABLE 0x0000f000 |
262 | #define CSIAR_ADDR_MASK 0x00000fff | |
065c27c1 | 263 | PMCH = 0x6f, |
128735a1 HK |
264 | #define D3COLD_NO_PLL_DOWN BIT(7) |
265 | #define D3HOT_NO_PLL_DOWN BIT(6) | |
266 | #define D3_NO_PLL_DOWN (BIT(7) | BIT(6)) | |
f162a5d1 FR |
267 | EPHYAR = 0x80, |
268 | #define EPHYAR_FLAG 0x80000000 | |
269 | #define EPHYAR_WRITE_CMD 0x80000000 | |
270 | #define EPHYAR_REG_MASK 0x1f | |
271 | #define EPHYAR_REG_SHIFT 16 | |
272 | #define EPHYAR_DATA_MASK 0xffff | |
5a5e4443 | 273 | DLLPR = 0xd0, |
4f6b00e5 | 274 | #define PFM_EN (1 << 6) |
6e1d0b89 | 275 | #define TX_10M_PS_EN (1 << 7) |
f162a5d1 FR |
276 | DBG_REG = 0xd1, |
277 | #define FIX_NAK_1 (1 << 4) | |
278 | #define FIX_NAK_2 (1 << 3) | |
5a5e4443 HW |
279 | TWSI = 0xd2, |
280 | MCU = 0xd3, | |
4f6b00e5 | 281 | #define NOW_IS_OOB (1 << 7) |
c558386b HW |
282 | #define TX_EMPTY (1 << 5) |
283 | #define RX_EMPTY (1 << 4) | |
284 | #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY) | |
5a5e4443 HW |
285 | #define EN_NDP (1 << 3) |
286 | #define EN_OOB_RESET (1 << 2) | |
c558386b | 287 | #define LINK_LIST_RDY (1 << 1) |
daf9df6d | 288 | EFUSEAR = 0xdc, |
289 | #define EFUSEAR_FLAG 0x80000000 | |
290 | #define EFUSEAR_WRITE_CMD 0x80000000 | |
291 | #define EFUSEAR_READ_CMD 0x00000000 | |
292 | #define EFUSEAR_REG_MASK 0x03ff | |
293 | #define EFUSEAR_REG_SHIFT 8 | |
294 | #define EFUSEAR_DATA_MASK 0xff | |
6e1d0b89 CHL |
295 | MISC_1 = 0xf2, |
296 | #define PFM_D3COLD_EN (1 << 6) | |
f162a5d1 FR |
297 | }; |
298 | ||
c0e45c1c | 299 | enum rtl8168_registers { |
4f6b00e5 HW |
300 | LED_FREQ = 0x1a, |
301 | EEE_LED = 0x1b, | |
b646d900 | 302 | ERIDR = 0x70, |
303 | ERIAR = 0x74, | |
304 | #define ERIAR_FLAG 0x80000000 | |
305 | #define ERIAR_WRITE_CMD 0x80000000 | |
306 | #define ERIAR_READ_CMD 0x00000000 | |
307 | #define ERIAR_ADDR_BYTE_ALIGN 4 | |
b646d900 | 308 | #define ERIAR_TYPE_SHIFT 16 |
4f6b00e5 HW |
309 | #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT) |
310 | #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT) | |
311 | #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT) | |
935e2218 | 312 | #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT) |
4f6b00e5 HW |
313 | #define ERIAR_MASK_SHIFT 12 |
314 | #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT) | |
315 | #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT) | |
6e1d0b89 | 316 | #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT) |
c558386b | 317 | #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT) |
4f6b00e5 | 318 | #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT) |
c0e45c1c | 319 | EPHY_RXER_NUM = 0x7c, |
320 | OCPDR = 0xb0, /* OCP GPHY access */ | |
321 | #define OCPDR_WRITE_CMD 0x80000000 | |
322 | #define OCPDR_READ_CMD 0x00000000 | |
323 | #define OCPDR_REG_MASK 0x7f | |
324 | #define OCPDR_GPHY_REG_SHIFT 16 | |
325 | #define OCPDR_DATA_MASK 0xffff | |
326 | OCPAR = 0xb4, | |
327 | #define OCPAR_FLAG 0x80000000 | |
328 | #define OCPAR_GPHY_WRITE_CMD 0x8000f060 | |
329 | #define OCPAR_GPHY_READ_CMD 0x0000f060 | |
c558386b | 330 | GPHY_OCP = 0xb8, |
01dc7fec | 331 | RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */ |
332 | MISC = 0xf0, /* 8168e only. */ | |
cecb5fd7 | 333 | #define TXPLA_RST (1 << 29) |
5598bfe5 | 334 | #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */ |
4f6b00e5 | 335 | #define PWM_EN (1 << 22) |
c558386b | 336 | #define RXDV_GATED_EN (1 << 19) |
5598bfe5 | 337 | #define EARLY_TALLY_EN (1 << 16) |
c0e45c1c | 338 | }; |
339 | ||
f1bce4ad HK |
340 | enum rtl8125_registers { |
341 | IntrMask_8125 = 0x38, | |
342 | IntrStatus_8125 = 0x3c, | |
343 | TxPoll_8125 = 0x90, | |
344 | MAC0_BKP = 0x19e0, | |
0439297b | 345 | EEE_TXIDLE_TIMER_8125 = 0x6048, |
f1bce4ad HK |
346 | }; |
347 | ||
348 | #define RX_VLAN_INNER_8125 BIT(22) | |
349 | #define RX_VLAN_OUTER_8125 BIT(23) | |
350 | #define RX_VLAN_8125 (RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125) | |
351 | ||
352 | #define RX_FETCH_DFLT_8125 (8 << 27) | |
353 | ||
07d3f51f | 354 | enum rtl_register_content { |
1da177e4 | 355 | /* InterruptStatusBits */ |
07d3f51f FR |
356 | SYSErr = 0x8000, |
357 | PCSTimeout = 0x4000, | |
358 | SWInt = 0x0100, | |
359 | TxDescUnavail = 0x0080, | |
360 | RxFIFOOver = 0x0040, | |
361 | LinkChg = 0x0020, | |
362 | RxOverflow = 0x0010, | |
363 | TxErr = 0x0008, | |
364 | TxOK = 0x0004, | |
365 | RxErr = 0x0002, | |
366 | RxOK = 0x0001, | |
1da177e4 LT |
367 | |
368 | /* RxStatusDesc */ | |
9dccf611 FR |
369 | RxRWT = (1 << 22), |
370 | RxRES = (1 << 21), | |
371 | RxRUNT = (1 << 20), | |
372 | RxCRC = (1 << 19), | |
1da177e4 LT |
373 | |
374 | /* ChipCmdBits */ | |
4f6b00e5 | 375 | StopReq = 0x80, |
07d3f51f FR |
376 | CmdReset = 0x10, |
377 | CmdRxEnb = 0x08, | |
378 | CmdTxEnb = 0x04, | |
379 | RxBufEmpty = 0x01, | |
1da177e4 | 380 | |
275391a4 FR |
381 | /* TXPoll register p.5 */ |
382 | HPQ = 0x80, /* Poll cmd on the high prio queue */ | |
383 | NPQ = 0x40, /* Poll cmd on the low prio queue */ | |
384 | FSWInt = 0x01, /* Forced software interrupt */ | |
385 | ||
1da177e4 | 386 | /* Cfg9346Bits */ |
07d3f51f FR |
387 | Cfg9346_Lock = 0x00, |
388 | Cfg9346_Unlock = 0xc0, | |
1da177e4 LT |
389 | |
390 | /* rx_mode_bits */ | |
07d3f51f FR |
391 | AcceptErr = 0x20, |
392 | AcceptRunt = 0x10, | |
10478283 | 393 | #define RX_CONFIG_ACCEPT_ERR_MASK 0x30 |
07d3f51f FR |
394 | AcceptBroadcast = 0x08, |
395 | AcceptMulticast = 0x04, | |
396 | AcceptMyPhys = 0x02, | |
397 | AcceptAllPhys = 0x01, | |
10478283 | 398 | #define RX_CONFIG_ACCEPT_OK_MASK 0x0f |
1687b566 | 399 | #define RX_CONFIG_ACCEPT_MASK 0x3f |
1da177e4 | 400 | |
1da177e4 LT |
401 | /* TxConfigBits */ |
402 | TxInterFrameGapShift = 24, | |
403 | TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ | |
404 | ||
5d06a99f | 405 | /* Config1 register p.24 */ |
f162a5d1 FR |
406 | LEDS1 = (1 << 7), |
407 | LEDS0 = (1 << 6), | |
f162a5d1 FR |
408 | Speed_down = (1 << 4), |
409 | MEMMAP = (1 << 3), | |
410 | IOMAP = (1 << 2), | |
411 | VPD = (1 << 1), | |
5d06a99f FR |
412 | PMEnable = (1 << 0), /* Power Management Enable */ |
413 | ||
6dccd16b | 414 | /* Config2 register p. 25 */ |
57538c4a | 415 | ClkReqEn = (1 << 7), /* Clock Request Enable */ |
2ca6cf06 | 416 | MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */ |
6dccd16b FR |
417 | PCI_Clock_66MHz = 0x01, |
418 | PCI_Clock_33MHz = 0x00, | |
419 | ||
61a4dcc2 FR |
420 | /* Config3 register p.25 */ |
421 | MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */ | |
422 | LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */ | |
d58d46b5 | 423 | Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */ |
b51ecea8 | 424 | Rdy_to_L23 = (1 << 1), /* L23 Enable */ |
f162a5d1 | 425 | Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */ |
61a4dcc2 | 426 | |
d58d46b5 FR |
427 | /* Config4 register */ |
428 | Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */ | |
429 | ||
5d06a99f | 430 | /* Config5 register p.27 */ |
61a4dcc2 FR |
431 | BWF = (1 << 6), /* Accept Broadcast wakeup frame */ |
432 | MWF = (1 << 5), /* Accept Multicast wakeup frame */ | |
433 | UWF = (1 << 4), /* Accept Unicast wakeup frame */ | |
cecb5fd7 | 434 | Spi_en = (1 << 3), |
61a4dcc2 | 435 | LanWake = (1 << 1), /* LanWake enable/disable */ |
5d06a99f | 436 | PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */ |
57538c4a | 437 | ASPM_en = (1 << 0), /* ASPM enable */ |
5d06a99f | 438 | |
1da177e4 | 439 | /* CPlusCmd p.31 */ |
f162a5d1 FR |
440 | EnableBist = (1 << 15), // 8168 8101 |
441 | Mac_dbgo_oe = (1 << 14), // 8168 8101 | |
09e65335 | 442 | EnAnaPLL = (1 << 14), // 8169 |
f162a5d1 FR |
443 | Normal_mode = (1 << 13), // unused |
444 | Force_half_dup = (1 << 12), // 8168 8101 | |
445 | Force_rxflow_en = (1 << 11), // 8168 8101 | |
446 | Force_txflow_en = (1 << 10), // 8168 8101 | |
447 | Cxpl_dbg_sel = (1 << 9), // 8168 8101 | |
448 | ASF = (1 << 8), // 8168 8101 | |
449 | PktCntrDisable = (1 << 7), // 8168 8101 | |
450 | Mac_dbgo_sel = 0x001c, // 8168 | |
1da177e4 LT |
451 | RxVlan = (1 << 6), |
452 | RxChkSum = (1 << 5), | |
453 | PCIDAC = (1 << 4), | |
454 | PCIMulRW = (1 << 3), | |
9a3c81fa | 455 | #define INTT_MASK GENMASK(1, 0) |
bc73241e | 456 | #define CPCMD_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK) |
1da177e4 LT |
457 | |
458 | /* rtl8169_PHYstatus */ | |
07d3f51f FR |
459 | TBI_Enable = 0x80, |
460 | TxFlowCtrl = 0x40, | |
461 | RxFlowCtrl = 0x20, | |
462 | _1000bpsF = 0x10, | |
463 | _100bps = 0x08, | |
464 | _10bps = 0x04, | |
465 | LinkStatus = 0x02, | |
466 | FullDup = 0x01, | |
1da177e4 | 467 | |
6e85d5ad CV |
468 | /* ResetCounterCommand */ |
469 | CounterReset = 0x1, | |
470 | ||
d4a3a0fc | 471 | /* DumpCounterCommand */ |
07d3f51f | 472 | CounterDump = 0x8, |
6e1d0b89 CHL |
473 | |
474 | /* magic enable v2 */ | |
475 | MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */ | |
1da177e4 LT |
476 | }; |
477 | ||
2b7b4318 FR |
478 | enum rtl_desc_bit { |
479 | /* First doubleword. */ | |
1da177e4 LT |
480 | DescOwn = (1 << 31), /* Descriptor is owned by NIC */ |
481 | RingEnd = (1 << 30), /* End of descriptor ring */ | |
482 | FirstFrag = (1 << 29), /* First segment of a packet */ | |
483 | LastFrag = (1 << 28), /* Final segment of a packet */ | |
2b7b4318 FR |
484 | }; |
485 | ||
486 | /* Generic case. */ | |
487 | enum rtl_tx_desc_bit { | |
488 | /* First doubleword. */ | |
489 | TD_LSO = (1 << 27), /* Large Send Offload */ | |
490 | #define TD_MSS_MAX 0x07ffu /* MSS value */ | |
1da177e4 | 491 | |
2b7b4318 FR |
492 | /* Second doubleword. */ |
493 | TxVlanTag = (1 << 17), /* Add VLAN tag */ | |
494 | }; | |
495 | ||
496 | /* 8169, 8168b and 810x except 8102e. */ | |
497 | enum rtl_tx_desc_bit_0 { | |
498 | /* First doubleword. */ | |
499 | #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */ | |
500 | TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */ | |
501 | TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */ | |
502 | TD0_IP_CS = (1 << 18), /* Calculate IP checksum */ | |
503 | }; | |
504 | ||
505 | /* 8102e, 8168c and beyond. */ | |
506 | enum rtl_tx_desc_bit_1 { | |
bdfa4ed6 | 507 | /* First doubleword. */ |
508 | TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */ | |
e974604b | 509 | TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */ |
bdfa4ed6 | 510 | #define GTTCPHO_SHIFT 18 |
e64e0c89 | 511 | #define GTTCPHO_MAX 0x7f |
bdfa4ed6 | 512 | |
2b7b4318 | 513 | /* Second doubleword. */ |
e974604b | 514 | #define TCPHO_SHIFT 18 |
e64e0c89 | 515 | #define TCPHO_MAX 0x3ff |
2b7b4318 | 516 | #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */ |
e974604b | 517 | TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */ |
518 | TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */ | |
2b7b4318 FR |
519 | TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */ |
520 | TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */ | |
521 | }; | |
1da177e4 | 522 | |
2b7b4318 | 523 | enum rtl_rx_desc_bit { |
1da177e4 LT |
524 | /* Rx private */ |
525 | PID1 = (1 << 18), /* Protocol ID bit 1/2 */ | |
9b60047a | 526 | PID0 = (1 << 17), /* Protocol ID bit 0/2 */ |
1da177e4 LT |
527 | |
528 | #define RxProtoUDP (PID1) | |
529 | #define RxProtoTCP (PID0) | |
530 | #define RxProtoIP (PID1 | PID0) | |
531 | #define RxProtoMask RxProtoIP | |
532 | ||
533 | IPFail = (1 << 16), /* IP checksum failed */ | |
534 | UDPFail = (1 << 15), /* UDP/IP checksum failed */ | |
535 | TCPFail = (1 << 14), /* TCP/IP checksum failed */ | |
206a75e0 HK |
536 | |
537 | #define RxCSFailMask (IPFail | UDPFail | TCPFail) | |
538 | ||
1da177e4 LT |
539 | RxVlanTag = (1 << 16), /* VLAN tag available */ |
540 | }; | |
541 | ||
0170d594 HK |
542 | #define RTL_GSO_MAX_SIZE_V1 32000 |
543 | #define RTL_GSO_MAX_SEGS_V1 24 | |
544 | #define RTL_GSO_MAX_SIZE_V2 64000 | |
545 | #define RTL_GSO_MAX_SEGS_V2 64 | |
546 | ||
1da177e4 | 547 | struct TxDesc { |
6cccd6e7 REB |
548 | __le32 opts1; |
549 | __le32 opts2; | |
550 | __le64 addr; | |
1da177e4 LT |
551 | }; |
552 | ||
553 | struct RxDesc { | |
6cccd6e7 REB |
554 | __le32 opts1; |
555 | __le32 opts2; | |
556 | __le64 addr; | |
1da177e4 LT |
557 | }; |
558 | ||
559 | struct ring_info { | |
560 | struct sk_buff *skb; | |
561 | u32 len; | |
1da177e4 LT |
562 | }; |
563 | ||
355423d0 IV |
564 | struct rtl8169_counters { |
565 | __le64 tx_packets; | |
566 | __le64 rx_packets; | |
567 | __le64 tx_errors; | |
568 | __le32 rx_errors; | |
569 | __le16 rx_missed; | |
570 | __le16 align_errors; | |
571 | __le32 tx_one_collision; | |
572 | __le32 tx_multi_collision; | |
573 | __le64 rx_unicast; | |
574 | __le64 rx_broadcast; | |
575 | __le32 rx_multicast; | |
576 | __le16 tx_aborted; | |
577 | __le16 tx_underun; | |
578 | }; | |
579 | ||
6e85d5ad CV |
580 | struct rtl8169_tc_offsets { |
581 | bool inited; | |
582 | __le64 tx_errors; | |
583 | __le32 tx_multi_collision; | |
6e85d5ad | 584 | __le16 tx_aborted; |
0da3359a | 585 | __le16 rx_missed; |
6e85d5ad CV |
586 | }; |
587 | ||
da78dbff | 588 | enum rtl_flag { |
6ad56901 | 589 | RTL_FLAG_TASK_ENABLED = 0, |
da78dbff | 590 | RTL_FLAG_TASK_RESET_PENDING, |
da78dbff FR |
591 | RTL_FLAG_MAX |
592 | }; | |
593 | ||
e0d38b58 HK |
594 | enum rtl_dash_type { |
595 | RTL_DASH_NONE, | |
596 | RTL_DASH_DP, | |
597 | RTL_DASH_EP, | |
598 | }; | |
599 | ||
1da177e4 LT |
600 | struct rtl8169_private { |
601 | void __iomem *mmio_addr; /* memory map physical address */ | |
cecb5fd7 | 602 | struct pci_dev *pci_dev; |
c4028958 | 603 | struct net_device *dev; |
703732f0 | 604 | struct phy_device *phydev; |
bea3348e | 605 | struct napi_struct napi; |
76719ee2 | 606 | enum mac_version mac_version; |
e0d38b58 | 607 | enum rtl_dash_type dash_type; |
1da177e4 LT |
608 | u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ |
609 | u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ | |
1da177e4 LT |
610 | u32 dirty_tx; |
611 | struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */ | |
612 | struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */ | |
613 | dma_addr_t TxPhyAddr; | |
614 | dma_addr_t RxPhyAddr; | |
32879f00 | 615 | struct page *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */ |
1da177e4 | 616 | struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */ |
1da177e4 | 617 | u16 cp_cmd; |
c1d532d2 | 618 | u32 irq_mask; |
c2f6f3ee | 619 | struct clk *clk; |
c0e45c1c | 620 | |
4422bcd4 | 621 | struct { |
da78dbff | 622 | DECLARE_BITMAP(flags, RTL_FLAG_MAX); |
4422bcd4 FR |
623 | struct work_struct work; |
624 | } wk; | |
625 | ||
f7ffa9ae | 626 | unsigned supports_gmii:1; |
55c779f2 KHF |
627 | unsigned rtl_aspm_enabled:1; |
628 | struct delayed_work aspm_toggle; | |
629 | atomic_t aspm_packet_count; | |
630 | struct mutex config_lock; | |
631 | ||
42020320 CV |
632 | dma_addr_t counters_phys_addr; |
633 | struct rtl8169_counters *counters; | |
6e85d5ad | 634 | struct rtl8169_tc_offsets tc_offset; |
e1759441 | 635 | u32 saved_wolopts; |
7ec3f872 | 636 | int eee_adv; |
f1e02ed1 | 637 | |
254764e5 | 638 | const char *fw_name; |
8197f9d2 | 639 | struct rtl_fw *rtl_fw; |
c558386b HW |
640 | |
641 | u32 ocp_base; | |
1da177e4 LT |
642 | }; |
643 | ||
1fcd1658 HK |
644 | typedef void (*rtl_generic_fct)(struct rtl8169_private *tp); |
645 | ||
979b6c13 | 646 | MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>"); |
1da177e4 | 647 | MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver"); |
11287b69 | 648 | MODULE_SOFTDEP("pre: realtek"); |
1da177e4 | 649 | MODULE_LICENSE("GPL"); |
bca03d5f | 650 | MODULE_FIRMWARE(FIRMWARE_8168D_1); |
651 | MODULE_FIRMWARE(FIRMWARE_8168D_2); | |
01dc7fec | 652 | MODULE_FIRMWARE(FIRMWARE_8168E_1); |
653 | MODULE_FIRMWARE(FIRMWARE_8168E_2); | |
bbb8af75 | 654 | MODULE_FIRMWARE(FIRMWARE_8168E_3); |
5a5e4443 | 655 | MODULE_FIRMWARE(FIRMWARE_8105E_1); |
c2218925 HW |
656 | MODULE_FIRMWARE(FIRMWARE_8168F_1); |
657 | MODULE_FIRMWARE(FIRMWARE_8168F_2); | |
7e18dca1 | 658 | MODULE_FIRMWARE(FIRMWARE_8402_1); |
b3d7b2f2 | 659 | MODULE_FIRMWARE(FIRMWARE_8411_1); |
45dd95c4 | 660 | MODULE_FIRMWARE(FIRMWARE_8411_2); |
5598bfe5 | 661 | MODULE_FIRMWARE(FIRMWARE_8106E_1); |
58152cd4 | 662 | MODULE_FIRMWARE(FIRMWARE_8106E_2); |
beb330a4 | 663 | MODULE_FIRMWARE(FIRMWARE_8168G_2); |
57538c4a | 664 | MODULE_FIRMWARE(FIRMWARE_8168G_3); |
6e1d0b89 CHL |
665 | MODULE_FIRMWARE(FIRMWARE_8168H_1); |
666 | MODULE_FIRMWARE(FIRMWARE_8168H_2); | |
229c1e0d | 667 | MODULE_FIRMWARE(FIRMWARE_8168FP_3); |
a3bf5c42 FR |
668 | MODULE_FIRMWARE(FIRMWARE_8107E_1); |
669 | MODULE_FIRMWARE(FIRMWARE_8107E_2); | |
02bf642b | 670 | MODULE_FIRMWARE(FIRMWARE_8125A_3); |
0439297b | 671 | MODULE_FIRMWARE(FIRMWARE_8125B_2); |
1da177e4 | 672 | |
1e1205b7 HK |
673 | static inline struct device *tp_to_dev(struct rtl8169_private *tp) |
674 | { | |
675 | return &tp->pci_dev->dev; | |
676 | } | |
677 | ||
df320ed7 HK |
678 | static void rtl_lock_config_regs(struct rtl8169_private *tp) |
679 | { | |
55c779f2 | 680 | mutex_lock(&tp->config_lock); |
df320ed7 HK |
681 | RTL_W8(tp, Cfg9346, Cfg9346_Lock); |
682 | } | |
683 | ||
684 | static void rtl_unlock_config_regs(struct rtl8169_private *tp) | |
685 | { | |
686 | RTL_W8(tp, Cfg9346, Cfg9346_Unlock); | |
55c779f2 | 687 | mutex_unlock(&tp->config_lock); |
df320ed7 HK |
688 | } |
689 | ||
711463f8 HK |
690 | static void rtl_pci_commit(struct rtl8169_private *tp) |
691 | { | |
692 | /* Read an arbitrary register to commit a preceding PCI write */ | |
693 | RTL_R8(tp, ChipCmd); | |
694 | } | |
695 | ||
f1bce4ad HK |
696 | static bool rtl_is_8125(struct rtl8169_private *tp) |
697 | { | |
698 | return tp->mac_version >= RTL_GIGA_MAC_VER_60; | |
699 | } | |
700 | ||
9e9f33ba HK |
701 | static bool rtl_is_8168evl_up(struct rtl8169_private *tp) |
702 | { | |
703 | return tp->mac_version >= RTL_GIGA_MAC_VER_34 && | |
c623305b | 704 | tp->mac_version != RTL_GIGA_MAC_VER_39 && |
e6d6ca6e | 705 | tp->mac_version <= RTL_GIGA_MAC_VER_53; |
9e9f33ba HK |
706 | } |
707 | ||
2e779ddb HK |
708 | static bool rtl_supports_eee(struct rtl8169_private *tp) |
709 | { | |
710 | return tp->mac_version >= RTL_GIGA_MAC_VER_34 && | |
711 | tp->mac_version != RTL_GIGA_MAC_VER_37 && | |
712 | tp->mac_version != RTL_GIGA_MAC_VER_39; | |
713 | } | |
714 | ||
ce37115e HK |
715 | static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg) |
716 | { | |
717 | int i; | |
718 | ||
719 | for (i = 0; i < ETH_ALEN; i++) | |
720 | mac[i] = RTL_R8(tp, reg + i); | |
721 | } | |
722 | ||
ffc46952 FR |
723 | struct rtl_cond { |
724 | bool (*check)(struct rtl8169_private *); | |
725 | const char *msg; | |
726 | }; | |
727 | ||
ffc46952 | 728 | static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c, |
d6836ef0 | 729 | unsigned long usecs, int n, bool high) |
ffc46952 FR |
730 | { |
731 | int i; | |
732 | ||
733 | for (i = 0; i < n; i++) { | |
ffc46952 FR |
734 | if (c->check(tp) == high) |
735 | return true; | |
d6836ef0 | 736 | fsleep(usecs); |
ffc46952 | 737 | } |
93882c6f HK |
738 | |
739 | if (net_ratelimit()) | |
d6836ef0 HK |
740 | netdev_err(tp->dev, "%s == %d (loop: %d, delay: %lu).\n", |
741 | c->msg, !high, n, usecs); | |
ffc46952 FR |
742 | return false; |
743 | } | |
744 | ||
d6836ef0 HK |
745 | static bool rtl_loop_wait_high(struct rtl8169_private *tp, |
746 | const struct rtl_cond *c, | |
747 | unsigned long d, int n) | |
ffc46952 | 748 | { |
d6836ef0 | 749 | return rtl_loop_wait(tp, c, d, n, true); |
ffc46952 FR |
750 | } |
751 | ||
d6836ef0 HK |
752 | static bool rtl_loop_wait_low(struct rtl8169_private *tp, |
753 | const struct rtl_cond *c, | |
754 | unsigned long d, int n) | |
ffc46952 | 755 | { |
d6836ef0 | 756 | return rtl_loop_wait(tp, c, d, n, false); |
ffc46952 FR |
757 | } |
758 | ||
759 | #define DECLARE_RTL_COND(name) \ | |
760 | static bool name ## _check(struct rtl8169_private *); \ | |
761 | \ | |
762 | static const struct rtl_cond name = { \ | |
763 | .check = name ## _check, \ | |
764 | .msg = #name \ | |
765 | }; \ | |
766 | \ | |
767 | static bool name ## _check(struct rtl8169_private *tp) | |
768 | ||
c6cff9df HK |
769 | static void r8168fp_adjust_ocp_cmd(struct rtl8169_private *tp, u32 *cmd, int type) |
770 | { | |
771 | /* based on RTL8168FP_OOBMAC_BASE in vendor driver */ | |
e6d6ca6e KHF |
772 | if (type == ERIAR_OOB && |
773 | (tp->mac_version == RTL_GIGA_MAC_VER_52 || | |
774 | tp->mac_version == RTL_GIGA_MAC_VER_53)) | |
abbf9a0e | 775 | *cmd |= 0xf70 << 18; |
c6cff9df HK |
776 | } |
777 | ||
778 | DECLARE_RTL_COND(rtl_eriar_cond) | |
779 | { | |
780 | return RTL_R32(tp, ERIAR) & ERIAR_FLAG; | |
781 | } | |
782 | ||
783 | static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, | |
784 | u32 val, int type) | |
785 | { | |
786 | u32 cmd = ERIAR_WRITE_CMD | type | mask | addr; | |
787 | ||
5f1e1224 HK |
788 | if (WARN(addr & 3 || !mask, "addr: 0x%x, mask: 0x%08x\n", addr, mask)) |
789 | return; | |
790 | ||
c6cff9df HK |
791 | RTL_W32(tp, ERIDR, val); |
792 | r8168fp_adjust_ocp_cmd(tp, &cmd, type); | |
793 | RTL_W32(tp, ERIAR, cmd); | |
794 | ||
795 | rtl_loop_wait_low(tp, &rtl_eriar_cond, 100, 100); | |
796 | } | |
797 | ||
798 | static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, | |
799 | u32 val) | |
800 | { | |
801 | _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC); | |
802 | } | |
803 | ||
804 | static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type) | |
805 | { | |
806 | u32 cmd = ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr; | |
807 | ||
808 | r8168fp_adjust_ocp_cmd(tp, &cmd, type); | |
809 | RTL_W32(tp, ERIAR, cmd); | |
810 | ||
811 | return rtl_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ? | |
812 | RTL_R32(tp, ERIDR) : ~0; | |
813 | } | |
814 | ||
815 | static u32 rtl_eri_read(struct rtl8169_private *tp, int addr) | |
816 | { | |
817 | return _rtl_eri_read(tp, addr, ERIAR_EXGMAC); | |
818 | } | |
819 | ||
820 | static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 p, u32 m) | |
821 | { | |
822 | u32 val = rtl_eri_read(tp, addr); | |
823 | ||
824 | rtl_eri_write(tp, addr, ERIAR_MASK_1111, (val & ~m) | p); | |
825 | } | |
826 | ||
827 | static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 p) | |
828 | { | |
829 | rtl_w0w1_eri(tp, addr, p, 0); | |
830 | } | |
831 | ||
832 | static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 m) | |
833 | { | |
834 | rtl_w0w1_eri(tp, addr, 0, m); | |
835 | } | |
836 | ||
a46604d7 | 837 | static bool rtl_ocp_reg_failure(u32 reg) |
c558386b | 838 | { |
a46604d7 | 839 | return WARN_ONCE(reg & 0xffff0001, "Invalid ocp reg %x!\n", reg); |
c558386b HW |
840 | } |
841 | ||
842 | DECLARE_RTL_COND(rtl_ocp_gphy_cond) | |
843 | { | |
1ef7286e | 844 | return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG; |
c558386b HW |
845 | } |
846 | ||
847 | static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) | |
848 | { | |
a46604d7 | 849 | if (rtl_ocp_reg_failure(reg)) |
c558386b HW |
850 | return; |
851 | ||
1ef7286e | 852 | RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data); |
c558386b | 853 | |
d6836ef0 | 854 | rtl_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10); |
c558386b HW |
855 | } |
856 | ||
9b994b4a | 857 | static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg) |
c558386b | 858 | { |
a46604d7 | 859 | if (rtl_ocp_reg_failure(reg)) |
c558386b HW |
860 | return 0; |
861 | ||
1ef7286e | 862 | RTL_W32(tp, GPHY_OCP, reg << 15); |
c558386b | 863 | |
d6836ef0 | 864 | return rtl_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ? |
9b994b4a | 865 | (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT; |
c558386b HW |
866 | } |
867 | ||
c558386b HW |
868 | static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) |
869 | { | |
a46604d7 | 870 | if (rtl_ocp_reg_failure(reg)) |
c558386b HW |
871 | return; |
872 | ||
1ef7286e | 873 | RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data); |
c558386b HW |
874 | } |
875 | ||
876 | static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg) | |
877 | { | |
a46604d7 | 878 | if (rtl_ocp_reg_failure(reg)) |
c558386b HW |
879 | return 0; |
880 | ||
1ef7286e | 881 | RTL_W32(tp, OCPDR, reg << 15); |
c558386b | 882 | |
1ef7286e | 883 | return RTL_R32(tp, OCPDR); |
c558386b HW |
884 | } |
885 | ||
ef712ede HK |
886 | static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask, |
887 | u16 set) | |
888 | { | |
889 | u16 data = r8168_mac_ocp_read(tp, reg); | |
890 | ||
891 | r8168_mac_ocp_write(tp, reg, (data & ~mask) | set); | |
892 | } | |
893 | ||
acb58657 HK |
894 | /* Work around a hw issue with RTL8168g PHY, the quirk disables |
895 | * PHY MCU interrupts before PHY power-down. | |
896 | */ | |
897 | static void rtl8168g_phy_suspend_quirk(struct rtl8169_private *tp, int value) | |
898 | { | |
899 | switch (tp->mac_version) { | |
900 | case RTL_GIGA_MAC_VER_40: | |
901 | case RTL_GIGA_MAC_VER_41: | |
902 | case RTL_GIGA_MAC_VER_49: | |
903 | if (value & BMCR_RESET || !(value & BMCR_PDOWN)) | |
904 | rtl_eri_set_bits(tp, 0x1a8, 0xfc000000); | |
905 | else | |
906 | rtl_eri_clear_bits(tp, 0x1a8, 0xfc000000); | |
907 | break; | |
908 | default: | |
909 | break; | |
910 | } | |
911 | }; | |
912 | ||
c558386b HW |
913 | static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value) |
914 | { | |
915 | if (reg == 0x1f) { | |
916 | tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE; | |
917 | return; | |
918 | } | |
919 | ||
920 | if (tp->ocp_base != OCP_STD_PHY_BASE) | |
921 | reg -= 0x10; | |
922 | ||
acb58657 HK |
923 | if (tp->ocp_base == OCP_STD_PHY_BASE && reg == MII_BMCR) |
924 | rtl8168g_phy_suspend_quirk(tp, value); | |
925 | ||
c558386b HW |
926 | r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value); |
927 | } | |
928 | ||
929 | static int r8168g_mdio_read(struct rtl8169_private *tp, int reg) | |
930 | { | |
9c6850fe HK |
931 | if (reg == 0x1f) |
932 | return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4; | |
933 | ||
c558386b HW |
934 | if (tp->ocp_base != OCP_STD_PHY_BASE) |
935 | reg -= 0x10; | |
936 | ||
937 | return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2); | |
938 | } | |
939 | ||
eee3786f | 940 | static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value) |
941 | { | |
942 | if (reg == 0x1f) { | |
943 | tp->ocp_base = value << 4; | |
944 | return; | |
945 | } | |
946 | ||
947 | r8168_mac_ocp_write(tp, tp->ocp_base + reg, value); | |
948 | } | |
949 | ||
950 | static int mac_mcu_read(struct rtl8169_private *tp, int reg) | |
951 | { | |
952 | return r8168_mac_ocp_read(tp, tp->ocp_base + reg); | |
953 | } | |
954 | ||
ffc46952 FR |
955 | DECLARE_RTL_COND(rtl_phyar_cond) |
956 | { | |
1ef7286e | 957 | return RTL_R32(tp, PHYAR) & 0x80000000; |
ffc46952 FR |
958 | } |
959 | ||
24192210 | 960 | static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value) |
1da177e4 | 961 | { |
1ef7286e | 962 | RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff)); |
1da177e4 | 963 | |
d6836ef0 | 964 | rtl_loop_wait_low(tp, &rtl_phyar_cond, 25, 20); |
024a07ba | 965 | /* |
81a95f04 TT |
966 | * According to hardware specs a 20us delay is required after write |
967 | * complete indication, but before sending next command. | |
024a07ba | 968 | */ |
81a95f04 | 969 | udelay(20); |
1da177e4 LT |
970 | } |
971 | ||
24192210 | 972 | static int r8169_mdio_read(struct rtl8169_private *tp, int reg) |
1da177e4 | 973 | { |
ffc46952 | 974 | int value; |
1da177e4 | 975 | |
1ef7286e | 976 | RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16); |
1da177e4 | 977 | |
d6836ef0 | 978 | value = rtl_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ? |
9b994b4a | 979 | RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT; |
ffc46952 | 980 | |
81a95f04 TT |
981 | /* |
982 | * According to hardware specs a 20us delay is required after read | |
983 | * complete indication, but before sending next command. | |
984 | */ | |
985 | udelay(20); | |
986 | ||
1da177e4 LT |
987 | return value; |
988 | } | |
989 | ||
935e2218 CHL |
990 | DECLARE_RTL_COND(rtl_ocpar_cond) |
991 | { | |
1ef7286e | 992 | return RTL_R32(tp, OCPAR) & OCPAR_FLAG; |
935e2218 CHL |
993 | } |
994 | ||
24192210 | 995 | static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data) |
c0e45c1c | 996 | { |
1ef7286e AS |
997 | RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT)); |
998 | RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD); | |
999 | RTL_W32(tp, EPHY_RXER_NUM, 0); | |
c0e45c1c | 1000 | |
d6836ef0 | 1001 | rtl_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100); |
c0e45c1c | 1002 | } |
1003 | ||
24192210 | 1004 | static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value) |
c0e45c1c | 1005 | { |
24192210 FR |
1006 | r8168dp_1_mdio_access(tp, reg, |
1007 | OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK)); | |
c0e45c1c | 1008 | } |
1009 | ||
24192210 | 1010 | static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg) |
c0e45c1c | 1011 | { |
24192210 | 1012 | r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD); |
c0e45c1c | 1013 | |
1014 | mdelay(1); | |
1ef7286e AS |
1015 | RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD); |
1016 | RTL_W32(tp, EPHY_RXER_NUM, 0); | |
c0e45c1c | 1017 | |
d6836ef0 | 1018 | return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ? |
9b994b4a | 1019 | RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : -ETIMEDOUT; |
c0e45c1c | 1020 | } |
1021 | ||
e6de30d6 | 1022 | #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000 |
1023 | ||
1ef7286e | 1024 | static void r8168dp_2_mdio_start(struct rtl8169_private *tp) |
e6de30d6 | 1025 | { |
1ef7286e | 1026 | RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT); |
e6de30d6 | 1027 | } |
1028 | ||
1ef7286e | 1029 | static void r8168dp_2_mdio_stop(struct rtl8169_private *tp) |
e6de30d6 | 1030 | { |
1ef7286e | 1031 | RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT); |
e6de30d6 | 1032 | } |
1033 | ||
24192210 | 1034 | static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value) |
e6de30d6 | 1035 | { |
1ef7286e | 1036 | r8168dp_2_mdio_start(tp); |
e6de30d6 | 1037 | |
24192210 | 1038 | r8169_mdio_write(tp, reg, value); |
e6de30d6 | 1039 | |
1ef7286e | 1040 | r8168dp_2_mdio_stop(tp); |
e6de30d6 | 1041 | } |
1042 | ||
24192210 | 1043 | static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg) |
e6de30d6 | 1044 | { |
1045 | int value; | |
1046 | ||
62bdc8fd HK |
1047 | /* Work around issue with chip reporting wrong PHY ID */ |
1048 | if (reg == MII_PHYSID2) | |
1049 | return 0xc912; | |
1050 | ||
1ef7286e | 1051 | r8168dp_2_mdio_start(tp); |
e6de30d6 | 1052 | |
24192210 | 1053 | value = r8169_mdio_read(tp, reg); |
e6de30d6 | 1054 | |
1ef7286e | 1055 | r8168dp_2_mdio_stop(tp); |
e6de30d6 | 1056 | |
1057 | return value; | |
1058 | } | |
1059 | ||
ce8843ab | 1060 | static void rtl_writephy(struct rtl8169_private *tp, int location, int val) |
dacf8154 | 1061 | { |
5f950523 HK |
1062 | switch (tp->mac_version) { |
1063 | case RTL_GIGA_MAC_VER_27: | |
1064 | r8168dp_1_mdio_write(tp, location, val); | |
1065 | break; | |
1066 | case RTL_GIGA_MAC_VER_28: | |
1067 | case RTL_GIGA_MAC_VER_31: | |
1068 | r8168dp_2_mdio_write(tp, location, val); | |
1069 | break; | |
0439297b | 1070 | case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: |
5f950523 HK |
1071 | r8168g_mdio_write(tp, location, val); |
1072 | break; | |
1073 | default: | |
1074 | r8169_mdio_write(tp, location, val); | |
1075 | break; | |
1076 | } | |
dacf8154 FR |
1077 | } |
1078 | ||
4da19633 | 1079 | static int rtl_readphy(struct rtl8169_private *tp, int location) |
1080 | { | |
5f950523 HK |
1081 | switch (tp->mac_version) { |
1082 | case RTL_GIGA_MAC_VER_27: | |
1083 | return r8168dp_1_mdio_read(tp, location); | |
1084 | case RTL_GIGA_MAC_VER_28: | |
1085 | case RTL_GIGA_MAC_VER_31: | |
1086 | return r8168dp_2_mdio_read(tp, location); | |
0439297b | 1087 | case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: |
5f950523 HK |
1088 | return r8168g_mdio_read(tp, location); |
1089 | default: | |
1090 | return r8169_mdio_read(tp, location); | |
1091 | } | |
4da19633 | 1092 | } |
1093 | ||
ffc46952 FR |
1094 | DECLARE_RTL_COND(rtl_ephyar_cond) |
1095 | { | |
1ef7286e | 1096 | return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG; |
ffc46952 FR |
1097 | } |
1098 | ||
fdf6fc06 | 1099 | static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value) |
dacf8154 | 1100 | { |
1ef7286e | 1101 | RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) | |
dacf8154 FR |
1102 | (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); |
1103 | ||
d6836ef0 | 1104 | rtl_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100); |
ffc46952 FR |
1105 | |
1106 | udelay(10); | |
dacf8154 FR |
1107 | } |
1108 | ||
fdf6fc06 | 1109 | static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr) |
dacf8154 | 1110 | { |
1ef7286e | 1111 | RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); |
dacf8154 | 1112 | |
d6836ef0 | 1113 | return rtl_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ? |
1ef7286e | 1114 | RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0; |
dacf8154 FR |
1115 | } |
1116 | ||
a15aaa03 | 1117 | static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u16 reg) |
935e2218 | 1118 | { |
a15aaa03 | 1119 | RTL_W32(tp, OCPAR, 0x0fu << 12 | (reg & 0x0fff)); |
d6836ef0 | 1120 | return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ? |
1ef7286e | 1121 | RTL_R32(tp, OCPDR) : ~0; |
935e2218 CHL |
1122 | } |
1123 | ||
787c0c04 | 1124 | static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u16 reg) |
935e2218 | 1125 | { |
724c6fd0 | 1126 | return _rtl_eri_read(tp, reg, ERIAR_OOB); |
935e2218 CHL |
1127 | } |
1128 | ||
935e2218 CHL |
1129 | static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, |
1130 | u32 data) | |
1131 | { | |
1ef7286e AS |
1132 | RTL_W32(tp, OCPDR, data); |
1133 | RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); | |
d6836ef0 | 1134 | rtl_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20); |
935e2218 CHL |
1135 | } |
1136 | ||
1137 | static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, | |
1138 | u32 data) | |
1139 | { | |
724c6fd0 HK |
1140 | _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT, |
1141 | data, ERIAR_OOB); | |
935e2218 CHL |
1142 | } |
1143 | ||
3c72bf71 | 1144 | static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd) |
2a9b4d96 | 1145 | { |
724c6fd0 | 1146 | rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd); |
2a9b4d96 | 1147 | |
3c72bf71 | 1148 | r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001); |
2a9b4d96 CHL |
1149 | } |
1150 | ||
1151 | #define OOB_CMD_RESET 0x00 | |
1152 | #define OOB_CMD_DRIVER_START 0x05 | |
1153 | #define OOB_CMD_DRIVER_STOP 0x06 | |
1154 | ||
1155 | static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp) | |
1156 | { | |
1157 | return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10; | |
1158 | } | |
1159 | ||
3c72bf71 | 1160 | DECLARE_RTL_COND(rtl_dp_ocp_read_cond) |
2a9b4d96 CHL |
1161 | { |
1162 | u16 reg; | |
1163 | ||
1164 | reg = rtl8168_get_ocp_reg(tp); | |
1165 | ||
a15aaa03 | 1166 | return r8168dp_ocp_read(tp, reg) & 0x00000800; |
2a9b4d96 CHL |
1167 | } |
1168 | ||
935e2218 | 1169 | DECLARE_RTL_COND(rtl_ep_ocp_read_cond) |
2a9b4d96 | 1170 | { |
787c0c04 | 1171 | return r8168ep_ocp_read(tp, 0x124) & 0x00000001; |
935e2218 CHL |
1172 | } |
1173 | ||
1174 | DECLARE_RTL_COND(rtl_ocp_tx_cond) | |
1175 | { | |
1ef7286e | 1176 | return RTL_R8(tp, IBISR0) & 0x20; |
935e2218 | 1177 | } |
2a9b4d96 | 1178 | |
003609da CHL |
1179 | static void rtl8168ep_stop_cmac(struct rtl8169_private *tp) |
1180 | { | |
1ef7286e | 1181 | RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01); |
d6836ef0 | 1182 | rtl_loop_wait_high(tp, &rtl_ocp_tx_cond, 50000, 2000); |
1ef7286e AS |
1183 | RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20); |
1184 | RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01); | |
003609da CHL |
1185 | } |
1186 | ||
935e2218 CHL |
1187 | static void rtl8168dp_driver_start(struct rtl8169_private *tp) |
1188 | { | |
3c72bf71 | 1189 | r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START); |
d6836ef0 | 1190 | rtl_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10000, 10); |
2a9b4d96 CHL |
1191 | } |
1192 | ||
935e2218 | 1193 | static void rtl8168ep_driver_start(struct rtl8169_private *tp) |
2a9b4d96 | 1194 | { |
3c72bf71 | 1195 | r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START); |
787c0c04 | 1196 | r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); |
d6836ef0 | 1197 | rtl_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10000, 10); |
935e2218 CHL |
1198 | } |
1199 | ||
1200 | static void rtl8168_driver_start(struct rtl8169_private *tp) | |
1201 | { | |
e0d38b58 | 1202 | if (tp->dash_type == RTL_DASH_DP) |
935e2218 | 1203 | rtl8168dp_driver_start(tp); |
e0d38b58 | 1204 | else |
935e2218 | 1205 | rtl8168ep_driver_start(tp); |
935e2218 | 1206 | } |
2a9b4d96 | 1207 | |
935e2218 CHL |
1208 | static void rtl8168dp_driver_stop(struct rtl8169_private *tp) |
1209 | { | |
3c72bf71 | 1210 | r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP); |
d6836ef0 | 1211 | rtl_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10000, 10); |
2a9b4d96 CHL |
1212 | } |
1213 | ||
935e2218 CHL |
1214 | static void rtl8168ep_driver_stop(struct rtl8169_private *tp) |
1215 | { | |
003609da | 1216 | rtl8168ep_stop_cmac(tp); |
3c72bf71 | 1217 | r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP); |
787c0c04 | 1218 | r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); |
d6836ef0 | 1219 | rtl_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10000, 10); |
935e2218 CHL |
1220 | } |
1221 | ||
1222 | static void rtl8168_driver_stop(struct rtl8169_private *tp) | |
1223 | { | |
e0d38b58 | 1224 | if (tp->dash_type == RTL_DASH_DP) |
935e2218 | 1225 | rtl8168dp_driver_stop(tp); |
e0d38b58 | 1226 | else |
935e2218 | 1227 | rtl8168ep_driver_stop(tp); |
935e2218 CHL |
1228 | } |
1229 | ||
9dbe7896 | 1230 | static bool r8168dp_check_dash(struct rtl8169_private *tp) |
2a9b4d96 CHL |
1231 | { |
1232 | u16 reg = rtl8168_get_ocp_reg(tp); | |
1233 | ||
e0d38b58 | 1234 | return r8168dp_ocp_read(tp, reg) & BIT(15); |
2a9b4d96 CHL |
1235 | } |
1236 | ||
9dbe7896 | 1237 | static bool r8168ep_check_dash(struct rtl8169_private *tp) |
935e2218 | 1238 | { |
e0d38b58 | 1239 | return r8168ep_ocp_read(tp, 0x128) & BIT(0); |
935e2218 CHL |
1240 | } |
1241 | ||
e0d38b58 | 1242 | static enum rtl_dash_type rtl_check_dash(struct rtl8169_private *tp) |
935e2218 CHL |
1243 | { |
1244 | switch (tp->mac_version) { | |
1245 | case RTL_GIGA_MAC_VER_27: | |
1246 | case RTL_GIGA_MAC_VER_28: | |
1247 | case RTL_GIGA_MAC_VER_31: | |
e0d38b58 | 1248 | return r8168dp_check_dash(tp) ? RTL_DASH_DP : RTL_DASH_NONE; |
e6d6ca6e | 1249 | case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_53: |
e0d38b58 | 1250 | return r8168ep_check_dash(tp) ? RTL_DASH_EP : RTL_DASH_NONE; |
935e2218 | 1251 | default: |
e0d38b58 | 1252 | return RTL_DASH_NONE; |
935e2218 CHL |
1253 | } |
1254 | } | |
1255 | ||
128735a1 HK |
1256 | static void rtl_set_d3_pll_down(struct rtl8169_private *tp, bool enable) |
1257 | { | |
1258 | switch (tp->mac_version) { | |
1259 | case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_26: | |
d2a04370 | 1260 | case RTL_GIGA_MAC_VER_29 ... RTL_GIGA_MAC_VER_30: |
128735a1 HK |
1261 | case RTL_GIGA_MAC_VER_32 ... RTL_GIGA_MAC_VER_37: |
1262 | case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_63: | |
1263 | if (enable) | |
1264 | RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~D3_NO_PLL_DOWN); | |
1265 | else | |
1266 | RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | D3_NO_PLL_DOWN); | |
1267 | break; | |
1268 | default: | |
1269 | break; | |
1270 | } | |
1271 | } | |
1272 | ||
4e7e4621 HK |
1273 | static void rtl_reset_packet_filter(struct rtl8169_private *tp) |
1274 | { | |
54113ded HK |
1275 | rtl_eri_clear_bits(tp, 0xdc, BIT(0)); |
1276 | rtl_eri_set_bits(tp, 0xdc, BIT(0)); | |
4e7e4621 HK |
1277 | } |
1278 | ||
ffc46952 FR |
1279 | DECLARE_RTL_COND(rtl_efusear_cond) |
1280 | { | |
1ef7286e | 1281 | return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG; |
ffc46952 FR |
1282 | } |
1283 | ||
2992bdfa | 1284 | u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr) |
daf9df6d | 1285 | { |
1ef7286e | 1286 | RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT); |
daf9df6d | 1287 | |
d6836ef0 | 1288 | return rtl_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ? |
1ef7286e | 1289 | RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0; |
daf9df6d | 1290 | } |
1291 | ||
c1d532d2 HK |
1292 | static u32 rtl_get_events(struct rtl8169_private *tp) |
1293 | { | |
f1bce4ad HK |
1294 | if (rtl_is_8125(tp)) |
1295 | return RTL_R32(tp, IntrStatus_8125); | |
1296 | else | |
1297 | return RTL_R16(tp, IntrStatus); | |
c1d532d2 HK |
1298 | } |
1299 | ||
1300 | static void rtl_ack_events(struct rtl8169_private *tp, u32 bits) | |
9085cdfa | 1301 | { |
f1bce4ad HK |
1302 | if (rtl_is_8125(tp)) |
1303 | RTL_W32(tp, IntrStatus_8125, bits); | |
1304 | else | |
1305 | RTL_W16(tp, IntrStatus, bits); | |
9085cdfa FR |
1306 | } |
1307 | ||
1308 | static void rtl_irq_disable(struct rtl8169_private *tp) | |
1309 | { | |
f1bce4ad HK |
1310 | if (rtl_is_8125(tp)) |
1311 | RTL_W32(tp, IntrMask_8125, 0); | |
1312 | else | |
1313 | RTL_W16(tp, IntrMask, 0); | |
3e990ff5 FR |
1314 | } |
1315 | ||
fe716f8a | 1316 | static void rtl_irq_enable(struct rtl8169_private *tp) |
da78dbff | 1317 | { |
f1bce4ad HK |
1318 | if (rtl_is_8125(tp)) |
1319 | RTL_W32(tp, IntrMask_8125, tp->irq_mask); | |
1320 | else | |
1321 | RTL_W16(tp, IntrMask, tp->irq_mask); | |
da78dbff FR |
1322 | } |
1323 | ||
811fd301 | 1324 | static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp) |
1da177e4 | 1325 | { |
9085cdfa | 1326 | rtl_irq_disable(tp); |
c1d532d2 | 1327 | rtl_ack_events(tp, 0xffffffff); |
711463f8 | 1328 | rtl_pci_commit(tp); |
1da177e4 LT |
1329 | } |
1330 | ||
70090424 HW |
1331 | static void rtl_link_chg_patch(struct rtl8169_private *tp) |
1332 | { | |
703732f0 | 1333 | struct phy_device *phydev = tp->phydev; |
70090424 | 1334 | |
b3d7b2f2 HW |
1335 | if (tp->mac_version == RTL_GIGA_MAC_VER_34 || |
1336 | tp->mac_version == RTL_GIGA_MAC_VER_38) { | |
29a12b49 | 1337 | if (phydev->speed == SPEED_1000) { |
724c6fd0 HK |
1338 | rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); |
1339 | rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); | |
29a12b49 | 1340 | } else if (phydev->speed == SPEED_100) { |
724c6fd0 HK |
1341 | rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); |
1342 | rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); | |
70090424 | 1343 | } else { |
724c6fd0 HK |
1344 | rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); |
1345 | rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); | |
70090424 | 1346 | } |
4e7e4621 | 1347 | rtl_reset_packet_filter(tp); |
c2218925 HW |
1348 | } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 || |
1349 | tp->mac_version == RTL_GIGA_MAC_VER_36) { | |
29a12b49 | 1350 | if (phydev->speed == SPEED_1000) { |
724c6fd0 HK |
1351 | rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); |
1352 | rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); | |
c2218925 | 1353 | } else { |
724c6fd0 HK |
1354 | rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); |
1355 | rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); | |
c2218925 | 1356 | } |
7e18dca1 | 1357 | } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) { |
29a12b49 | 1358 | if (phydev->speed == SPEED_10) { |
724c6fd0 HK |
1359 | rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02); |
1360 | rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a); | |
7e18dca1 | 1361 | } else { |
724c6fd0 | 1362 | rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); |
7e18dca1 | 1363 | } |
70090424 HW |
1364 | } |
1365 | } | |
1366 | ||
e1759441 RW |
1367 | #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) |
1368 | ||
e1759441 | 1369 | static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) |
61a4dcc2 FR |
1370 | { |
1371 | struct rtl8169_private *tp = netdev_priv(dev); | |
e1759441 | 1372 | |
e1759441 | 1373 | wol->supported = WAKE_ANY; |
433f9d0d | 1374 | wol->wolopts = tp->saved_wolopts; |
e1759441 RW |
1375 | } |
1376 | ||
1377 | static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts) | |
1378 | { | |
350f7596 | 1379 | static const struct { |
61a4dcc2 FR |
1380 | u32 opt; |
1381 | u16 reg; | |
1382 | u8 mask; | |
1383 | } cfg[] = { | |
61a4dcc2 | 1384 | { WAKE_PHY, Config3, LinkUp }, |
61a4dcc2 FR |
1385 | { WAKE_UCAST, Config5, UWF }, |
1386 | { WAKE_BCAST, Config5, BWF }, | |
1387 | { WAKE_MCAST, Config5, MWF }, | |
6e1d0b89 CHL |
1388 | { WAKE_ANY, Config5, LanWake }, |
1389 | { WAKE_MAGIC, Config3, MagicPacket } | |
61a4dcc2 | 1390 | }; |
f1bce4ad | 1391 | unsigned int i, tmp = ARRAY_SIZE(cfg); |
851e6022 | 1392 | u8 options; |
61a4dcc2 | 1393 | |
df320ed7 | 1394 | rtl_unlock_config_regs(tp); |
61a4dcc2 | 1395 | |
9e9f33ba | 1396 | if (rtl_is_8168evl_up(tp)) { |
f1bce4ad | 1397 | tmp--; |
6e1d0b89 | 1398 | if (wolopts & WAKE_MAGIC) |
54113ded | 1399 | rtl_eri_set_bits(tp, 0x0dc, MagicPacket_v2); |
6e1d0b89 | 1400 | else |
54113ded | 1401 | rtl_eri_clear_bits(tp, 0x0dc, MagicPacket_v2); |
f1bce4ad HK |
1402 | } else if (rtl_is_8125(tp)) { |
1403 | tmp--; | |
1404 | if (wolopts & WAKE_MAGIC) | |
1405 | r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0)); | |
1406 | else | |
1407 | r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0); | |
6e1d0b89 CHL |
1408 | } |
1409 | ||
1410 | for (i = 0; i < tmp; i++) { | |
1ef7286e | 1411 | options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask; |
e1759441 | 1412 | if (wolopts & cfg[i].opt) |
61a4dcc2 | 1413 | options |= cfg[i].mask; |
1ef7286e | 1414 | RTL_W8(tp, cfg[i].reg, options); |
61a4dcc2 FR |
1415 | } |
1416 | ||
851e6022 | 1417 | switch (tp->mac_version) { |
edcde3ee | 1418 | case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: |
1ef7286e | 1419 | options = RTL_R8(tp, Config1) & ~PMEnable; |
851e6022 FR |
1420 | if (wolopts) |
1421 | options |= PMEnable; | |
1ef7286e | 1422 | RTL_W8(tp, Config1, options); |
851e6022 | 1423 | break; |
edcde3ee HK |
1424 | case RTL_GIGA_MAC_VER_34: |
1425 | case RTL_GIGA_MAC_VER_37: | |
0439297b | 1426 | case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_63: |
1ef7286e | 1427 | options = RTL_R8(tp, Config2) & ~PME_SIGNAL; |
d387b427 FR |
1428 | if (wolopts) |
1429 | options |= PME_SIGNAL; | |
1ef7286e | 1430 | RTL_W8(tp, Config2, options); |
851e6022 | 1431 | break; |
edcde3ee HK |
1432 | default: |
1433 | break; | |
851e6022 FR |
1434 | } |
1435 | ||
df320ed7 | 1436 | rtl_lock_config_regs(tp); |
3bd82645 HK |
1437 | |
1438 | device_set_wakeup_enable(tp_to_dev(tp), wolopts); | |
128735a1 | 1439 | rtl_set_d3_pll_down(tp, !wolopts); |
398fd408 | 1440 | tp->dev->wol_enabled = wolopts ? 1 : 0; |
e1759441 RW |
1441 | } |
1442 | ||
1443 | static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
1444 | { | |
1445 | struct rtl8169_private *tp = netdev_priv(dev); | |
5fa80a32 | 1446 | |
2f533f6b HK |
1447 | if (wol->wolopts & ~WAKE_ANY) |
1448 | return -EINVAL; | |
1449 | ||
2f533f6b | 1450 | tp->saved_wolopts = wol->wolopts; |
ec2f204b | 1451 | __rtl8169_set_wol(tp, tp->saved_wolopts); |
da78dbff | 1452 | |
61a4dcc2 FR |
1453 | return 0; |
1454 | } | |
1455 | ||
1da177e4 LT |
1456 | static void rtl8169_get_drvinfo(struct net_device *dev, |
1457 | struct ethtool_drvinfo *info) | |
1458 | { | |
1459 | struct rtl8169_private *tp = netdev_priv(dev); | |
b6ffd97f | 1460 | struct rtl_fw *rtl_fw = tp->rtl_fw; |
1da177e4 | 1461 | |
7cb7541a | 1462 | strlcpy(info->driver, KBUILD_MODNAME, sizeof(info->driver)); |
68aad78c | 1463 | strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info)); |
1c361efb | 1464 | BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version)); |
254764e5 | 1465 | if (rtl_fw) |
8ac72d16 RJ |
1466 | strlcpy(info->fw_version, rtl_fw->version, |
1467 | sizeof(info->fw_version)); | |
1da177e4 LT |
1468 | } |
1469 | ||
1470 | static int rtl8169_get_regs_len(struct net_device *dev) | |
1471 | { | |
1472 | return R8169_REGS_SIZE; | |
1473 | } | |
1474 | ||
c8f44aff MM |
1475 | static netdev_features_t rtl8169_fix_features(struct net_device *dev, |
1476 | netdev_features_t features) | |
1da177e4 | 1477 | { |
d58d46b5 FR |
1478 | struct rtl8169_private *tp = netdev_priv(dev); |
1479 | ||
2b7b4318 | 1480 | if (dev->mtu > TD_MSS_MAX) |
350fb32a | 1481 | features &= ~NETIF_F_ALL_TSO; |
1da177e4 | 1482 | |
a8ec173a | 1483 | if (dev->mtu > ETH_DATA_LEN && |
6ed0e08f | 1484 | tp->mac_version > RTL_GIGA_MAC_VER_06) |
7cb83b21 | 1485 | features &= ~(NETIF_F_CSUM_MASK | NETIF_F_ALL_TSO); |
d58d46b5 | 1486 | |
350fb32a | 1487 | return features; |
1da177e4 LT |
1488 | } |
1489 | ||
10478283 HK |
1490 | static void rtl_set_rx_config_features(struct rtl8169_private *tp, |
1491 | netdev_features_t features) | |
1da177e4 | 1492 | { |
10478283 | 1493 | u32 rx_config = RTL_R32(tp, RxConfig); |
a3984578 | 1494 | |
929a031d | 1495 | if (features & NETIF_F_RXALL) |
10478283 | 1496 | rx_config |= RX_CONFIG_ACCEPT_ERR_MASK; |
929a031d | 1497 | else |
10478283 | 1498 | rx_config &= ~RX_CONFIG_ACCEPT_ERR_MASK; |
1da177e4 | 1499 | |
f1bce4ad HK |
1500 | if (rtl_is_8125(tp)) { |
1501 | if (features & NETIF_F_HW_VLAN_CTAG_RX) | |
1502 | rx_config |= RX_VLAN_8125; | |
1503 | else | |
1504 | rx_config &= ~RX_VLAN_8125; | |
1505 | } | |
1506 | ||
1ef7286e | 1507 | RTL_W32(tp, RxConfig, rx_config); |
10478283 HK |
1508 | } |
1509 | ||
1510 | static int rtl8169_set_features(struct net_device *dev, | |
1511 | netdev_features_t features) | |
1512 | { | |
1513 | struct rtl8169_private *tp = netdev_priv(dev); | |
1514 | ||
10478283 | 1515 | rtl_set_rx_config_features(tp, features); |
350fb32a | 1516 | |
929a031d | 1517 | if (features & NETIF_F_RXCSUM) |
1518 | tp->cp_cmd |= RxChkSum; | |
1519 | else | |
1520 | tp->cp_cmd &= ~RxChkSum; | |
6bbe021d | 1521 | |
f1bce4ad HK |
1522 | if (!rtl_is_8125(tp)) { |
1523 | if (features & NETIF_F_HW_VLAN_CTAG_RX) | |
1524 | tp->cp_cmd |= RxVlan; | |
1525 | else | |
1526 | tp->cp_cmd &= ~RxVlan; | |
1527 | } | |
929a031d | 1528 | |
1ef7286e | 1529 | RTL_W16(tp, CPlusCmd, tp->cp_cmd); |
711463f8 | 1530 | rtl_pci_commit(tp); |
1da177e4 | 1531 | |
1da177e4 LT |
1532 | return 0; |
1533 | } | |
1534 | ||
810f4893 | 1535 | static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb) |
1da177e4 | 1536 | { |
df8a39de | 1537 | return (skb_vlan_tag_present(skb)) ? |
7424edbb | 1538 | TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00; |
1da177e4 LT |
1539 | } |
1540 | ||
7a8fc77b | 1541 | static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb) |
1da177e4 LT |
1542 | { |
1543 | u32 opts2 = le32_to_cpu(desc->opts2); | |
1da177e4 | 1544 | |
7a8fc77b | 1545 | if (opts2 & RxVlanTag) |
7424edbb | 1546 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff)); |
1da177e4 LT |
1547 | } |
1548 | ||
1da177e4 LT |
1549 | static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs, |
1550 | void *p) | |
1551 | { | |
5b0384f4 | 1552 | struct rtl8169_private *tp = netdev_priv(dev); |
15edae91 PW |
1553 | u32 __iomem *data = tp->mmio_addr; |
1554 | u32 *dw = p; | |
1555 | int i; | |
1da177e4 | 1556 | |
15edae91 PW |
1557 | for (i = 0; i < R8169_REGS_SIZE; i += 4) |
1558 | memcpy_fromio(dw++, data++, 4); | |
1da177e4 LT |
1559 | } |
1560 | ||
d4a3a0fc SH |
1561 | static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = { |
1562 | "tx_packets", | |
1563 | "rx_packets", | |
1564 | "tx_errors", | |
1565 | "rx_errors", | |
1566 | "rx_missed", | |
1567 | "align_errors", | |
1568 | "tx_single_collisions", | |
1569 | "tx_multi_collisions", | |
1570 | "unicast", | |
1571 | "broadcast", | |
1572 | "multicast", | |
1573 | "tx_aborted", | |
1574 | "tx_underrun", | |
1575 | }; | |
1576 | ||
b9f2c044 | 1577 | static int rtl8169_get_sset_count(struct net_device *dev, int sset) |
d4a3a0fc | 1578 | { |
b9f2c044 JG |
1579 | switch (sset) { |
1580 | case ETH_SS_STATS: | |
1581 | return ARRAY_SIZE(rtl8169_gstrings); | |
1582 | default: | |
1583 | return -EOPNOTSUPP; | |
1584 | } | |
d4a3a0fc SH |
1585 | } |
1586 | ||
42020320 | 1587 | DECLARE_RTL_COND(rtl_counters_cond) |
6e85d5ad | 1588 | { |
1ef7286e | 1589 | return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump); |
6e85d5ad CV |
1590 | } |
1591 | ||
d56f58ce | 1592 | static void rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd) |
6e85d5ad | 1593 | { |
b498ee3f | 1594 | u32 cmd = lower_32_bits(tp->counters_phys_addr); |
6e85d5ad | 1595 | |
b498ee3f | 1596 | RTL_W32(tp, CounterAddrHigh, upper_32_bits(tp->counters_phys_addr)); |
711463f8 | 1597 | rtl_pci_commit(tp); |
1ef7286e AS |
1598 | RTL_W32(tp, CounterAddrLow, cmd); |
1599 | RTL_W32(tp, CounterAddrLow, cmd | counter_cmd); | |
6e85d5ad | 1600 | |
d6836ef0 | 1601 | rtl_loop_wait_low(tp, &rtl_counters_cond, 10, 1000); |
6e85d5ad CV |
1602 | } |
1603 | ||
d56f58ce | 1604 | static void rtl8169_update_counters(struct rtl8169_private *tp) |
d4a3a0fc | 1605 | { |
10262b0b HK |
1606 | u8 val = RTL_R8(tp, ChipCmd); |
1607 | ||
355423d0 IV |
1608 | /* |
1609 | * Some chips are unable to dump tally counters when the receiver | |
10262b0b | 1610 | * is disabled. If 0xff chip may be in a PCI power-save state. |
355423d0 | 1611 | */ |
d56f58ce HK |
1612 | if (val & CmdRxEnb && val != 0xff) |
1613 | rtl8169_do_counters(tp, CounterDump); | |
6e85d5ad CV |
1614 | } |
1615 | ||
d56f58ce | 1616 | static void rtl8169_init_counter_offsets(struct rtl8169_private *tp) |
6e85d5ad | 1617 | { |
42020320 | 1618 | struct rtl8169_counters *counters = tp->counters; |
6e85d5ad CV |
1619 | |
1620 | /* | |
1621 | * rtl8169_init_counter_offsets is called from rtl_open. On chip | |
1622 | * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only | |
1623 | * reset by a power cycle, while the counter values collected by the | |
1624 | * driver are reset at every driver unload/load cycle. | |
1625 | * | |
1626 | * To make sure the HW values returned by @get_stats64 match the SW | |
1627 | * values, we collect the initial values at first open(*) and use them | |
1628 | * as offsets to normalize the values returned by @get_stats64. | |
1629 | * | |
1630 | * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one | |
1631 | * for the reason stated in rtl8169_update_counters; CmdRxEnb is only | |
1632 | * set at open time by rtl_hw_start. | |
1633 | */ | |
1634 | ||
1635 | if (tp->tc_offset.inited) | |
d56f58ce | 1636 | return; |
6e85d5ad | 1637 | |
6b4f5031 HK |
1638 | if (tp->mac_version >= RTL_GIGA_MAC_VER_19) { |
1639 | rtl8169_do_counters(tp, CounterReset); | |
1640 | } else { | |
1641 | rtl8169_update_counters(tp); | |
1642 | tp->tc_offset.tx_errors = counters->tx_errors; | |
1643 | tp->tc_offset.tx_multi_collision = counters->tx_multi_collision; | |
1644 | tp->tc_offset.tx_aborted = counters->tx_aborted; | |
1645 | tp->tc_offset.rx_missed = counters->rx_missed; | |
1646 | } | |
6e85d5ad | 1647 | |
6e85d5ad | 1648 | tp->tc_offset.inited = true; |
d4a3a0fc SH |
1649 | } |
1650 | ||
355423d0 IV |
1651 | static void rtl8169_get_ethtool_stats(struct net_device *dev, |
1652 | struct ethtool_stats *stats, u64 *data) | |
1653 | { | |
1654 | struct rtl8169_private *tp = netdev_priv(dev); | |
ec2f204b | 1655 | struct rtl8169_counters *counters; |
e0636236 | 1656 | |
ec2f204b HK |
1657 | counters = tp->counters; |
1658 | rtl8169_update_counters(tp); | |
355423d0 | 1659 | |
42020320 CV |
1660 | data[0] = le64_to_cpu(counters->tx_packets); |
1661 | data[1] = le64_to_cpu(counters->rx_packets); | |
1662 | data[2] = le64_to_cpu(counters->tx_errors); | |
1663 | data[3] = le32_to_cpu(counters->rx_errors); | |
1664 | data[4] = le16_to_cpu(counters->rx_missed); | |
1665 | data[5] = le16_to_cpu(counters->align_errors); | |
1666 | data[6] = le32_to_cpu(counters->tx_one_collision); | |
1667 | data[7] = le32_to_cpu(counters->tx_multi_collision); | |
1668 | data[8] = le64_to_cpu(counters->rx_unicast); | |
1669 | data[9] = le64_to_cpu(counters->rx_broadcast); | |
1670 | data[10] = le32_to_cpu(counters->rx_multicast); | |
1671 | data[11] = le16_to_cpu(counters->tx_aborted); | |
1672 | data[12] = le16_to_cpu(counters->tx_underun); | |
355423d0 IV |
1673 | } |
1674 | ||
d4a3a0fc SH |
1675 | static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data) |
1676 | { | |
1677 | switch(stringset) { | |
1678 | case ETH_SS_STATS: | |
da5ac772 | 1679 | memcpy(data, rtl8169_gstrings, sizeof(rtl8169_gstrings)); |
d4a3a0fc SH |
1680 | break; |
1681 | } | |
1682 | } | |
1683 | ||
50970831 FR |
1684 | /* |
1685 | * Interrupt coalescing | |
1686 | * | |
1687 | * > 1 - the availability of the IntrMitigate (0xe2) register through the | |
1688 | * > 8169, 8168 and 810x line of chipsets | |
1689 | * | |
1690 | * 8169, 8168, and 8136(810x) serial chipsets support it. | |
1691 | * | |
1692 | * > 2 - the Tx timer unit at gigabit speed | |
1693 | * | |
1694 | * The unit of the timer depends on both the speed and the setting of CPlusCmd | |
1695 | * (0xe0) bit 1 and bit 0. | |
1696 | * | |
1697 | * For 8169 | |
1698 | * bit[1:0] \ speed 1000M 100M 10M | |
1699 | * 0 0 320ns 2.56us 40.96us | |
1700 | * 0 1 2.56us 20.48us 327.7us | |
1701 | * 1 0 5.12us 40.96us 655.4us | |
1702 | * 1 1 10.24us 81.92us 1.31ms | |
1703 | * | |
1704 | * For the other | |
1705 | * bit[1:0] \ speed 1000M 100M 10M | |
1706 | * 0 0 5us 2.56us 40.96us | |
1707 | * 0 1 40us 20.48us 327.7us | |
1708 | * 1 0 80us 40.96us 655.4us | |
1709 | * 1 1 160us 81.92us 1.31ms | |
1710 | */ | |
1711 | ||
50970831 FR |
1712 | /* rx/tx scale factors for all CPlusCmd[0:1] cases */ |
1713 | struct rtl_coalesce_info { | |
1714 | u32 speed; | |
2815b305 | 1715 | u32 scale_nsecs[4]; |
50970831 FR |
1716 | }; |
1717 | ||
2815b305 HK |
1718 | /* produce array with base delay *1, *8, *8*2, *8*2*2 */ |
1719 | #define COALESCE_DELAY(d) { (d), 8 * (d), 16 * (d), 32 * (d) } | |
1720 | ||
50970831 | 1721 | static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = { |
2815b305 | 1722 | { SPEED_1000, COALESCE_DELAY(320) }, |
51f6291b HK |
1723 | { SPEED_100, COALESCE_DELAY(2560) }, |
1724 | { SPEED_10, COALESCE_DELAY(40960) }, | |
50970831 FR |
1725 | { 0 }, |
1726 | }; | |
1727 | ||
1728 | static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = { | |
2815b305 | 1729 | { SPEED_1000, COALESCE_DELAY(5000) }, |
51f6291b HK |
1730 | { SPEED_100, COALESCE_DELAY(2560) }, |
1731 | { SPEED_10, COALESCE_DELAY(40960) }, | |
50970831 FR |
1732 | { 0 }, |
1733 | }; | |
2815b305 | 1734 | #undef COALESCE_DELAY |
50970831 FR |
1735 | |
1736 | /* get rx/tx scale vector corresponding to current speed */ | |
ef2c0a78 HK |
1737 | static const struct rtl_coalesce_info * |
1738 | rtl_coalesce_info(struct rtl8169_private *tp) | |
50970831 | 1739 | { |
50970831 | 1740 | const struct rtl_coalesce_info *ci; |
50970831 | 1741 | |
20023d3e HK |
1742 | if (tp->mac_version <= RTL_GIGA_MAC_VER_06) |
1743 | ci = rtl_coalesce_info_8169; | |
1744 | else | |
1745 | ci = rtl_coalesce_info_8168_8136; | |
50970831 | 1746 | |
51f6291b HK |
1747 | /* if speed is unknown assume highest one */ |
1748 | if (tp->phydev->speed == SPEED_UNKNOWN) | |
1749 | return ci; | |
1750 | ||
20023d3e HK |
1751 | for (; ci->speed; ci++) { |
1752 | if (tp->phydev->speed == ci->speed) | |
50970831 | 1753 | return ci; |
50970831 FR |
1754 | } |
1755 | ||
1756 | return ERR_PTR(-ELNRNG); | |
1757 | } | |
1758 | ||
f3ccfda1 YM |
1759 | static int rtl_get_coalesce(struct net_device *dev, |
1760 | struct ethtool_coalesce *ec, | |
1761 | struct kernel_ethtool_coalesce *kernel_coal, | |
1762 | struct netlink_ext_ack *extack) | |
50970831 FR |
1763 | { |
1764 | struct rtl8169_private *tp = netdev_priv(dev); | |
50970831 | 1765 | const struct rtl_coalesce_info *ci; |
6cf96dd4 HK |
1766 | u32 scale, c_us, c_fr; |
1767 | u16 intrmit; | |
50970831 | 1768 | |
f1bce4ad HK |
1769 | if (rtl_is_8125(tp)) |
1770 | return -EOPNOTSUPP; | |
1771 | ||
50970831 FR |
1772 | memset(ec, 0, sizeof(*ec)); |
1773 | ||
1774 | /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */ | |
ef2c0a78 | 1775 | ci = rtl_coalesce_info(tp); |
50970831 FR |
1776 | if (IS_ERR(ci)) |
1777 | return PTR_ERR(ci); | |
1778 | ||
2815b305 | 1779 | scale = ci->scale_nsecs[tp->cp_cmd & INTT_MASK]; |
50970831 | 1780 | |
6cf96dd4 | 1781 | intrmit = RTL_R16(tp, IntrMitigate); |
50970831 | 1782 | |
6cf96dd4 HK |
1783 | c_us = FIELD_GET(RTL_COALESCE_TX_USECS, intrmit); |
1784 | ec->tx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000); | |
50970831 | 1785 | |
6cf96dd4 HK |
1786 | c_fr = FIELD_GET(RTL_COALESCE_TX_FRAMES, intrmit); |
1787 | /* ethtool_coalesce states usecs and max_frames must not both be 0 */ | |
1788 | ec->tx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1; | |
1789 | ||
1790 | c_us = FIELD_GET(RTL_COALESCE_RX_USECS, intrmit); | |
1791 | ec->rx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000); | |
1792 | ||
1793 | c_fr = FIELD_GET(RTL_COALESCE_RX_FRAMES, intrmit); | |
1794 | ec->rx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1; | |
50970831 FR |
1795 | |
1796 | return 0; | |
1797 | } | |
1798 | ||
cb9d97de HK |
1799 | /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, usec) */ |
1800 | static int rtl_coalesce_choose_scale(struct rtl8169_private *tp, u32 usec, | |
2815b305 | 1801 | u16 *cp01) |
50970831 FR |
1802 | { |
1803 | const struct rtl_coalesce_info *ci; | |
1804 | u16 i; | |
1805 | ||
ef2c0a78 | 1806 | ci = rtl_coalesce_info(tp); |
50970831 | 1807 | if (IS_ERR(ci)) |
2815b305 | 1808 | return PTR_ERR(ci); |
50970831 FR |
1809 | |
1810 | for (i = 0; i < 4; i++) { | |
cb9d97de | 1811 | if (usec <= ci->scale_nsecs[i] * RTL_COALESCE_T_MAX / 1000U) { |
50970831 | 1812 | *cp01 = i; |
2815b305 | 1813 | return ci->scale_nsecs[i]; |
50970831 FR |
1814 | } |
1815 | } | |
1816 | ||
cb9d97de | 1817 | return -ERANGE; |
50970831 FR |
1818 | } |
1819 | ||
f3ccfda1 YM |
1820 | static int rtl_set_coalesce(struct net_device *dev, |
1821 | struct ethtool_coalesce *ec, | |
1822 | struct kernel_ethtool_coalesce *kernel_coal, | |
1823 | struct netlink_ext_ack *extack) | |
50970831 FR |
1824 | { |
1825 | struct rtl8169_private *tp = netdev_priv(dev); | |
2b3e48b6 HK |
1826 | u32 tx_fr = ec->tx_max_coalesced_frames; |
1827 | u32 rx_fr = ec->rx_max_coalesced_frames; | |
1828 | u32 coal_usec_max, units; | |
2815b305 | 1829 | u16 w = 0, cp01 = 0; |
2b3e48b6 | 1830 | int scale; |
50970831 | 1831 | |
f1bce4ad HK |
1832 | if (rtl_is_8125(tp)) |
1833 | return -EOPNOTSUPP; | |
1834 | ||
2b3e48b6 HK |
1835 | if (rx_fr > RTL_COALESCE_FRAME_MAX || tx_fr > RTL_COALESCE_FRAME_MAX) |
1836 | return -ERANGE; | |
1837 | ||
cb9d97de HK |
1838 | coal_usec_max = max(ec->rx_coalesce_usecs, ec->tx_coalesce_usecs); |
1839 | scale = rtl_coalesce_choose_scale(tp, coal_usec_max, &cp01); | |
2815b305 HK |
1840 | if (scale < 0) |
1841 | return scale; | |
50970831 | 1842 | |
2b3e48b6 HK |
1843 | /* Accept max_frames=1 we returned in rtl_get_coalesce. Accept it |
1844 | * not only when usecs=0 because of e.g. the following scenario: | |
1845 | * | |
1846 | * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX) | |
1847 | * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1 | |
1848 | * - then user does `ethtool -C eth0 rx-usecs 100` | |
1849 | * | |
1850 | * Since ethtool sends to kernel whole ethtool_coalesce settings, | |
1851 | * if we want to ignore rx_frames then it has to be set to 0. | |
1852 | */ | |
1853 | if (rx_fr == 1) | |
1854 | rx_fr = 0; | |
1855 | if (tx_fr == 1) | |
1856 | tx_fr = 0; | |
50970831 | 1857 | |
81496b72 HK |
1858 | /* HW requires time limit to be set if frame limit is set */ |
1859 | if ((tx_fr && !ec->tx_coalesce_usecs) || | |
1860 | (rx_fr && !ec->rx_coalesce_usecs)) | |
1861 | return -EINVAL; | |
1862 | ||
2b3e48b6 HK |
1863 | w |= FIELD_PREP(RTL_COALESCE_TX_FRAMES, DIV_ROUND_UP(tx_fr, 4)); |
1864 | w |= FIELD_PREP(RTL_COALESCE_RX_FRAMES, DIV_ROUND_UP(rx_fr, 4)); | |
50970831 | 1865 | |
2b3e48b6 HK |
1866 | units = DIV_ROUND_UP(ec->tx_coalesce_usecs * 1000U, scale); |
1867 | w |= FIELD_PREP(RTL_COALESCE_TX_USECS, units); | |
1868 | units = DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000U, scale); | |
1869 | w |= FIELD_PREP(RTL_COALESCE_RX_USECS, units); | |
50970831 | 1870 | |
2b3e48b6 | 1871 | RTL_W16(tp, IntrMitigate, w); |
50970831 | 1872 | |
5cdfe830 HK |
1873 | /* Meaning of PktCntrDisable bit changed from RTL8168e-vl */ |
1874 | if (rtl_is_8168evl_up(tp)) { | |
1875 | if (!rx_fr && !tx_fr) | |
1876 | /* disable packet counter */ | |
1877 | tp->cp_cmd |= PktCntrDisable; | |
1878 | else | |
1879 | tp->cp_cmd &= ~PktCntrDisable; | |
1880 | } | |
1881 | ||
9a3c81fa | 1882 | tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01; |
1ef7286e | 1883 | RTL_W16(tp, CPlusCmd, tp->cp_cmd); |
711463f8 | 1884 | rtl_pci_commit(tp); |
50970831 | 1885 | |
50970831 FR |
1886 | return 0; |
1887 | } | |
1888 | ||
df6f1856 HK |
1889 | static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data) |
1890 | { | |
1891 | struct rtl8169_private *tp = netdev_priv(dev); | |
df6f1856 | 1892 | |
2e779ddb HK |
1893 | if (!rtl_supports_eee(tp)) |
1894 | return -EOPNOTSUPP; | |
1895 | ||
ec2f204b | 1896 | return phy_ethtool_get_eee(tp->phydev, data); |
df6f1856 HK |
1897 | } |
1898 | ||
1899 | static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data) | |
1900 | { | |
1901 | struct rtl8169_private *tp = netdev_priv(dev); | |
2e779ddb HK |
1902 | int ret; |
1903 | ||
1904 | if (!rtl_supports_eee(tp)) | |
1905 | return -EOPNOTSUPP; | |
df6f1856 | 1906 | |
2e779ddb | 1907 | ret = phy_ethtool_set_eee(tp->phydev, data); |
7ec3f872 HK |
1908 | |
1909 | if (!ret) | |
1910 | tp->eee_adv = phy_read_mmd(dev->phydev, MDIO_MMD_AN, | |
1911 | MDIO_AN_EEE_ADV); | |
2e779ddb | 1912 | return ret; |
df6f1856 HK |
1913 | } |
1914 | ||
dc4aa50b HK |
1915 | static void rtl8169_get_ringparam(struct net_device *dev, |
1916 | struct ethtool_ringparam *data) | |
1917 | { | |
1918 | data->rx_max_pending = NUM_RX_DESC; | |
1919 | data->rx_pending = NUM_RX_DESC; | |
1920 | data->tx_max_pending = NUM_TX_DESC; | |
1921 | data->tx_pending = NUM_TX_DESC; | |
1922 | } | |
1923 | ||
216f78ea HK |
1924 | static void rtl8169_get_pauseparam(struct net_device *dev, |
1925 | struct ethtool_pauseparam *data) | |
1926 | { | |
1927 | struct rtl8169_private *tp = netdev_priv(dev); | |
1928 | bool tx_pause, rx_pause; | |
1929 | ||
1930 | phy_get_pause(tp->phydev, &tx_pause, &rx_pause); | |
1931 | ||
1932 | data->autoneg = tp->phydev->autoneg; | |
1933 | data->tx_pause = tx_pause ? 1 : 0; | |
1934 | data->rx_pause = rx_pause ? 1 : 0; | |
1935 | } | |
1936 | ||
1937 | static int rtl8169_set_pauseparam(struct net_device *dev, | |
1938 | struct ethtool_pauseparam *data) | |
1939 | { | |
1940 | struct rtl8169_private *tp = netdev_priv(dev); | |
1941 | ||
1942 | if (dev->mtu > ETH_DATA_LEN) | |
1943 | return -EOPNOTSUPP; | |
1944 | ||
1945 | phy_set_asym_pause(tp->phydev, data->rx_pause, data->tx_pause); | |
1946 | ||
1947 | return 0; | |
1948 | } | |
1949 | ||
7282d491 | 1950 | static const struct ethtool_ops rtl8169_ethtool_ops = { |
b604eb31 JK |
1951 | .supported_coalesce_params = ETHTOOL_COALESCE_USECS | |
1952 | ETHTOOL_COALESCE_MAX_FRAMES, | |
1da177e4 LT |
1953 | .get_drvinfo = rtl8169_get_drvinfo, |
1954 | .get_regs_len = rtl8169_get_regs_len, | |
1955 | .get_link = ethtool_op_get_link, | |
50970831 FR |
1956 | .get_coalesce = rtl_get_coalesce, |
1957 | .set_coalesce = rtl_set_coalesce, | |
1da177e4 | 1958 | .get_regs = rtl8169_get_regs, |
61a4dcc2 FR |
1959 | .get_wol = rtl8169_get_wol, |
1960 | .set_wol = rtl8169_set_wol, | |
d4a3a0fc | 1961 | .get_strings = rtl8169_get_strings, |
b9f2c044 | 1962 | .get_sset_count = rtl8169_get_sset_count, |
d4a3a0fc | 1963 | .get_ethtool_stats = rtl8169_get_ethtool_stats, |
e1593bb1 | 1964 | .get_ts_info = ethtool_op_get_ts_info, |
dd84957e | 1965 | .nway_reset = phy_ethtool_nway_reset, |
df6f1856 HK |
1966 | .get_eee = rtl8169_get_eee, |
1967 | .set_eee = rtl8169_set_eee, | |
45772433 HK |
1968 | .get_link_ksettings = phy_ethtool_get_link_ksettings, |
1969 | .set_link_ksettings = phy_ethtool_set_link_ksettings, | |
dc4aa50b | 1970 | .get_ringparam = rtl8169_get_ringparam, |
216f78ea HK |
1971 | .get_pauseparam = rtl8169_get_pauseparam, |
1972 | .set_pauseparam = rtl8169_set_pauseparam, | |
1da177e4 LT |
1973 | }; |
1974 | ||
b6c7fa40 HK |
1975 | static void rtl_enable_eee(struct rtl8169_private *tp) |
1976 | { | |
2e779ddb | 1977 | struct phy_device *phydev = tp->phydev; |
7ec3f872 HK |
1978 | int adv; |
1979 | ||
1980 | /* respect EEE advertisement the user may have set */ | |
1981 | if (tp->eee_adv >= 0) | |
1982 | adv = tp->eee_adv; | |
1983 | else | |
1984 | adv = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE); | |
b6c7fa40 | 1985 | |
7ec3f872 HK |
1986 | if (adv >= 0) |
1987 | phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, adv); | |
b6c7fa40 HK |
1988 | } |
1989 | ||
f1f9ca28 | 1990 | static enum mac_version rtl8169_get_mac_version(u16 xid, bool gmii) |
1da177e4 | 1991 | { |
0e485150 FR |
1992 | /* |
1993 | * The driver currently handles the 8168Bf and the 8168Be identically | |
1994 | * but they can be identified more specifically through the test below | |
1995 | * if needed: | |
1996 | * | |
1ef7286e | 1997 | * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be |
0127215c FR |
1998 | * |
1999 | * Same thing for the 8101Eb and the 8101Ec: | |
2000 | * | |
1ef7286e | 2001 | * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec |
0e485150 | 2002 | */ |
3744100e | 2003 | static const struct rtl_mac_info { |
55d2ad7b HK |
2004 | u16 mask; |
2005 | u16 val; | |
f1f9ca28 | 2006 | enum mac_version ver; |
1da177e4 | 2007 | } mac_info[] = { |
0439297b HK |
2008 | /* 8125B family. */ |
2009 | { 0x7cf, 0x641, RTL_GIGA_MAC_VER_63 }, | |
2010 | ||
2011 | /* 8125A family. */ | |
f1bce4ad HK |
2012 | { 0x7cf, 0x608, RTL_GIGA_MAC_VER_60 }, |
2013 | { 0x7c8, 0x608, RTL_GIGA_MAC_VER_61 }, | |
2014 | ||
1287723a | 2015 | /* RTL8117 */ |
e6d6ca6e | 2016 | { 0x7cf, 0x54b, RTL_GIGA_MAC_VER_53 }, |
1287723a HK |
2017 | { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52 }, |
2018 | ||
935e2218 | 2019 | /* 8168EP family. */ |
55d2ad7b HK |
2020 | { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 }, |
2021 | { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 }, | |
2022 | { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 }, | |
935e2218 | 2023 | |
6e1d0b89 | 2024 | /* 8168H family. */ |
55d2ad7b HK |
2025 | { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 }, |
2026 | { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 }, | |
6e1d0b89 | 2027 | |
c558386b | 2028 | /* 8168G family. */ |
55d2ad7b HK |
2029 | { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 }, |
2030 | { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 }, | |
2031 | { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 }, | |
2032 | { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 }, | |
c558386b | 2033 | |
c2218925 | 2034 | /* 8168F family. */ |
55d2ad7b HK |
2035 | { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 }, |
2036 | { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 }, | |
2037 | { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 }, | |
c2218925 | 2038 | |
01dc7fec | 2039 | /* 8168E family. */ |
55d2ad7b HK |
2040 | { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 }, |
2041 | { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 }, | |
2042 | { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 }, | |
01dc7fec | 2043 | |
5b538df9 | 2044 | /* 8168D family. */ |
55d2ad7b HK |
2045 | { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 }, |
2046 | { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 }, | |
5b538df9 | 2047 | |
e6de30d6 | 2048 | /* 8168DP family. */ |
beb401ec HK |
2049 | /* It seems this early RTL8168dp version never made it to |
2050 | * the wild. Let's see whether somebody complains, if not | |
2051 | * we'll remove support for this chip version completely. | |
2052 | * { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 }, | |
2053 | */ | |
55d2ad7b HK |
2054 | { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 }, |
2055 | { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 }, | |
e6de30d6 | 2056 | |
ef808d50 | 2057 | /* 8168C family. */ |
55d2ad7b HK |
2058 | { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 }, |
2059 | { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 }, | |
2060 | { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 }, | |
2061 | { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 }, | |
2062 | { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 }, | |
2063 | { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 }, | |
2064 | { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 }, | |
e3cf0cc0 FR |
2065 | |
2066 | /* 8168B family. */ | |
55d2ad7b HK |
2067 | { 0x7cf, 0x380, RTL_GIGA_MAC_VER_12 }, |
2068 | { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 }, | |
2069 | { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 }, | |
e3cf0cc0 FR |
2070 | |
2071 | /* 8101 family. */ | |
55d2ad7b HK |
2072 | { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 }, |
2073 | { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 }, | |
2074 | { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 }, | |
2075 | { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 }, | |
2076 | { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 }, | |
2077 | { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 }, | |
2078 | { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 }, | |
2079 | { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 }, | |
2080 | { 0x7cf, 0x340, RTL_GIGA_MAC_VER_13 }, | |
cdafdc29 | 2081 | { 0x7cf, 0x240, RTL_GIGA_MAC_VER_14 }, |
55d2ad7b HK |
2082 | { 0x7cf, 0x343, RTL_GIGA_MAC_VER_10 }, |
2083 | { 0x7cf, 0x342, RTL_GIGA_MAC_VER_16 }, | |
2084 | { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 }, | |
2085 | { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 }, | |
2086 | { 0x7c8, 0x340, RTL_GIGA_MAC_VER_16 }, | |
cb456fce HK |
2087 | /* FIXME: where did these entries come from ? -- FR |
2088 | * Not even r8101 vendor driver knows these id's, | |
2089 | * so let's disable detection for now. -- HK | |
2090 | * { 0xfc8, 0x388, RTL_GIGA_MAC_VER_13 }, | |
2091 | * { 0xfc8, 0x308, RTL_GIGA_MAC_VER_13 }, | |
2092 | */ | |
e3cf0cc0 FR |
2093 | |
2094 | /* 8110 family. */ | |
55d2ad7b HK |
2095 | { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 }, |
2096 | { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 }, | |
2097 | { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 }, | |
2098 | { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 }, | |
2099 | { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 }, | |
e3cf0cc0 | 2100 | |
f21b75e9 | 2101 | /* Catch-all */ |
55d2ad7b | 2102 | { 0x000, 0x000, RTL_GIGA_MAC_NONE } |
3744100e FR |
2103 | }; |
2104 | const struct rtl_mac_info *p = mac_info; | |
f1f9ca28 | 2105 | enum mac_version ver; |
1da177e4 | 2106 | |
f1f9ca28 | 2107 | while ((xid & p->mask) != p->val) |
1da177e4 | 2108 | p++; |
f1f9ca28 HK |
2109 | ver = p->ver; |
2110 | ||
2111 | if (ver != RTL_GIGA_MAC_NONE && !gmii) { | |
2112 | if (ver == RTL_GIGA_MAC_VER_42) | |
2113 | ver = RTL_GIGA_MAC_VER_43; | |
2114 | else if (ver == RTL_GIGA_MAC_VER_45) | |
2115 | ver = RTL_GIGA_MAC_VER_47; | |
2116 | else if (ver == RTL_GIGA_MAC_VER_46) | |
2117 | ver = RTL_GIGA_MAC_VER_48; | |
5d320a20 | 2118 | } |
f1f9ca28 HK |
2119 | |
2120 | return ver; | |
1da177e4 LT |
2121 | } |
2122 | ||
f1e02ed1 | 2123 | static void rtl_release_firmware(struct rtl8169_private *tp) |
2124 | { | |
254764e5 | 2125 | if (tp->rtl_fw) { |
47ad5931 | 2126 | rtl_fw_release_firmware(tp->rtl_fw); |
b6ffd97f | 2127 | kfree(tp->rtl_fw); |
254764e5 | 2128 | tp->rtl_fw = NULL; |
b6ffd97f | 2129 | } |
f1e02ed1 | 2130 | } |
2131 | ||
2992bdfa | 2132 | void r8169_apply_firmware(struct rtl8169_private *tp) |
f1e02ed1 | 2133 | { |
47dda786 HK |
2134 | int val; |
2135 | ||
ce8843ab | 2136 | /* TODO: release firmware if rtl_fw_write_firmware signals failure. */ |
89fbd26c | 2137 | if (tp->rtl_fw) { |
ce8843ab | 2138 | rtl_fw_write_firmware(tp, tp->rtl_fw); |
89fbd26c HK |
2139 | /* At least one firmware doesn't reset tp->ocp_base. */ |
2140 | tp->ocp_base = OCP_STD_PHY_BASE; | |
47dda786 HK |
2141 | |
2142 | /* PHY soft reset may still be in progress */ | |
2143 | phy_read_poll_timeout(tp->phydev, MII_BMCR, val, | |
2144 | !(val & BMCR_RESET), | |
2145 | 50000, 600000, true); | |
89fbd26c | 2146 | } |
953a12cc FR |
2147 | } |
2148 | ||
df6f1856 HK |
2149 | static void rtl8168_config_eee_mac(struct rtl8169_private *tp) |
2150 | { | |
f452825d HK |
2151 | /* Adjust EEE LED frequency */ |
2152 | if (tp->mac_version != RTL_GIGA_MAC_VER_38) | |
2153 | RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07); | |
2154 | ||
54113ded | 2155 | rtl_eri_set_bits(tp, 0x1b0, 0x0003); |
df6f1856 HK |
2156 | } |
2157 | ||
4640338c | 2158 | static void rtl8125a_config_eee_mac(struct rtl8169_private *tp) |
b3a42e3a HK |
2159 | { |
2160 | r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); | |
2161 | r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1)); | |
2162 | } | |
2163 | ||
0439297b HK |
2164 | static void rtl8125_set_eee_txidle_timer(struct rtl8169_private *tp) |
2165 | { | |
2166 | RTL_W16(tp, EEE_TXIDLE_TIMER_8125, tp->dev->mtu + ETH_HLEN + 0x20); | |
2167 | } | |
2168 | ||
2169 | static void rtl8125b_config_eee_mac(struct rtl8169_private *tp) | |
2170 | { | |
2171 | rtl8125_set_eee_txidle_timer(tp); | |
2172 | r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); | |
2173 | } | |
2174 | ||
ae1e82c6 | 2175 | static void rtl_rar_exgmac_set(struct rtl8169_private *tp, const u8 *addr) |
9ecb9aab | 2176 | { |
ae1e82c6 HK |
2177 | rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, get_unaligned_le32(addr)); |
2178 | rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, get_unaligned_le16(addr + 4)); | |
2179 | rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, get_unaligned_le16(addr) << 16); | |
2180 | rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, get_unaligned_le32(addr + 2)); | |
9ecb9aab | 2181 | } |
2182 | ||
2992bdfa | 2183 | u16 rtl8168h_2_get_adc_bias_ioffset(struct rtl8169_private *tp) |
3127f7c9 HK |
2184 | { |
2185 | u16 data1, data2, ioffset; | |
2186 | ||
2187 | r8168_mac_ocp_write(tp, 0xdd02, 0x807d); | |
2188 | data1 = r8168_mac_ocp_read(tp, 0xdd02); | |
2189 | data2 = r8168_mac_ocp_read(tp, 0xdd00); | |
2190 | ||
2191 | ioffset = (data2 >> 1) & 0x7ff8; | |
2192 | ioffset |= data2 & 0x0007; | |
2193 | if (data1 & BIT(7)) | |
2194 | ioffset |= BIT(15); | |
2195 | ||
2196 | return ioffset; | |
2197 | } | |
2198 | ||
da78dbff FR |
2199 | static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag) |
2200 | { | |
3f6ca6c7 HK |
2201 | set_bit(flag, tp->wk.flags); |
2202 | schedule_work(&tp->wk.work); | |
da78dbff FR |
2203 | } |
2204 | ||
b5aed0b3 | 2205 | static void rtl8169_init_phy(struct rtl8169_private *tp) |
4ff96fa6 | 2206 | { |
becd837e | 2207 | r8169_hw_phy_config(tp, tp->phydev, tp->mac_version); |
4ff96fa6 | 2208 | |
77332894 | 2209 | if (tp->mac_version <= RTL_GIGA_MAC_VER_06) { |
7a67e11d HK |
2210 | pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); |
2211 | pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); | |
b5aed0b3 | 2212 | /* set undocumented MAC Reg C+CR Offset 0x82h */ |
1ef7286e | 2213 | RTL_W8(tp, 0x82, 0x01); |
77332894 | 2214 | } |
4ff96fa6 | 2215 | |
fc712387 HK |
2216 | if (tp->mac_version == RTL_GIGA_MAC_VER_05 && |
2217 | tp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_GIGABYTE && | |
2218 | tp->pci_dev->subsystem_device == 0xe000) | |
2219 | phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b); | |
2220 | ||
5b7ad4b7 | 2221 | /* We may have called phy_speed_down before */ |
703732f0 | 2222 | phy_speed_up(tp->phydev); |
5b7ad4b7 | 2223 | |
af779778 HK |
2224 | if (rtl_supports_eee(tp)) |
2225 | rtl_enable_eee(tp); | |
2226 | ||
703732f0 | 2227 | genphy_soft_reset(tp->phydev); |
4ff96fa6 FR |
2228 | } |
2229 | ||
ae1e82c6 | 2230 | static void rtl_rar_set(struct rtl8169_private *tp, const u8 *addr) |
773d2021 | 2231 | { |
df320ed7 | 2232 | rtl_unlock_config_regs(tp); |
908ba2bf | 2233 | |
ae1e82c6 | 2234 | RTL_W32(tp, MAC4, get_unaligned_le16(addr + 4)); |
711463f8 | 2235 | rtl_pci_commit(tp); |
908ba2bf | 2236 | |
ae1e82c6 | 2237 | RTL_W32(tp, MAC0, get_unaligned_le32(addr)); |
711463f8 | 2238 | rtl_pci_commit(tp); |
908ba2bf | 2239 | |
9ecb9aab | 2240 | if (tp->mac_version == RTL_GIGA_MAC_VER_34) |
2241 | rtl_rar_exgmac_set(tp, addr); | |
c28aa385 | 2242 | |
df320ed7 | 2243 | rtl_lock_config_regs(tp); |
773d2021 FR |
2244 | } |
2245 | ||
2246 | static int rtl_set_mac_address(struct net_device *dev, void *p) | |
2247 | { | |
2248 | struct rtl8169_private *tp = netdev_priv(dev); | |
1f7aa2bc | 2249 | int ret; |
773d2021 | 2250 | |
1f7aa2bc HK |
2251 | ret = eth_mac_addr(dev, p); |
2252 | if (ret) | |
2253 | return ret; | |
773d2021 | 2254 | |
ec2f204b | 2255 | rtl_rar_set(tp, dev->dev_addr); |
773d2021 FR |
2256 | |
2257 | return 0; | |
2258 | } | |
2259 | ||
1e8636b3 | 2260 | static void rtl_wol_enable_rx(struct rtl8169_private *tp) |
649b3b8c | 2261 | { |
1e8636b3 | 2262 | if (tp->mac_version >= RTL_GIGA_MAC_VER_25) |
1ef7286e | 2263 | RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) | |
649b3b8c | 2264 | AcceptBroadcast | AcceptMulticast | AcceptMyPhys); |
649b3b8c | 2265 | } |
2266 | ||
7257c977 | 2267 | static void rtl_prepare_power_down(struct rtl8169_private *tp) |
065c27c1 | 2268 | { |
e0d38b58 | 2269 | if (tp->dash_type != RTL_DASH_NONE) |
065c27c1 | 2270 | return; |
2271 | ||
01dc7fec | 2272 | if (tp->mac_version == RTL_GIGA_MAC_VER_32 || |
2273 | tp->mac_version == RTL_GIGA_MAC_VER_33) | |
fdf6fc06 | 2274 | rtl_ephy_write(tp, 0x19, 0xff64); |
01dc7fec | 2275 | |
5ea25b12 HK |
2276 | if (device_may_wakeup(tp_to_dev(tp))) { |
2277 | phy_speed_down(tp->phydev, false); | |
1e8636b3 | 2278 | rtl_wol_enable_rx(tp); |
065c27c1 | 2279 | } |
2280 | } | |
2281 | ||
e542a226 HW |
2282 | static void rtl_init_rxcfg(struct rtl8169_private *tp) |
2283 | { | |
e542a226 | 2284 | switch (tp->mac_version) { |
e9588eb9 | 2285 | case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: |
2a71883c | 2286 | case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: |
1ef7286e | 2287 | RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST); |
e542a226 | 2288 | break; |
2a71883c | 2289 | case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: |
511cfd58 MS |
2290 | case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36: |
2291 | case RTL_GIGA_MAC_VER_38: | |
1ef7286e | 2292 | RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST); |
e542a226 | 2293 | break; |
e6d6ca6e | 2294 | case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53: |
1ef7286e | 2295 | RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF); |
beb330a4 | 2296 | break; |
0439297b | 2297 | case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_63: |
10478283 | 2298 | RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST); |
f1bce4ad | 2299 | break; |
e542a226 | 2300 | default: |
1ef7286e | 2301 | RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST); |
e542a226 HW |
2302 | break; |
2303 | } | |
2304 | } | |
2305 | ||
92fc43b4 HW |
2306 | static void rtl8169_init_ring_indexes(struct rtl8169_private *tp) |
2307 | { | |
9fba0812 | 2308 | tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0; |
92fc43b4 HW |
2309 | } |
2310 | ||
d58d46b5 FR |
2311 | static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp) |
2312 | { | |
1ef7286e AS |
2313 | RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); |
2314 | RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1); | |
d58d46b5 FR |
2315 | } |
2316 | ||
2317 | static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp) | |
2318 | { | |
1ef7286e AS |
2319 | RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); |
2320 | RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1); | |
d58d46b5 FR |
2321 | } |
2322 | ||
2323 | static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp) | |
2324 | { | |
1ef7286e | 2325 | RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); |
d58d46b5 FR |
2326 | } |
2327 | ||
2328 | static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp) | |
2329 | { | |
1ef7286e | 2330 | RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); |
d58d46b5 FR |
2331 | } |
2332 | ||
2333 | static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp) | |
2334 | { | |
6cf73913 | 2335 | RTL_W8(tp, MaxTxPacketSize, 0x24); |
1ef7286e AS |
2336 | RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); |
2337 | RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01); | |
d58d46b5 FR |
2338 | } |
2339 | ||
2340 | static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp) | |
2341 | { | |
6cf73913 | 2342 | RTL_W8(tp, MaxTxPacketSize, 0x3f); |
1ef7286e AS |
2343 | RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); |
2344 | RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01); | |
d58d46b5 FR |
2345 | } |
2346 | ||
d58d46b5 FR |
2347 | static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp) |
2348 | { | |
1ef7286e | 2349 | RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0)); |
d58d46b5 FR |
2350 | } |
2351 | ||
2352 | static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp) | |
2353 | { | |
1ef7286e | 2354 | RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0)); |
d58d46b5 FR |
2355 | } |
2356 | ||
9db0ac57 | 2357 | static void rtl_jumbo_config(struct rtl8169_private *tp) |
d58d46b5 | 2358 | { |
9db0ac57 | 2359 | bool jumbo = tp->dev->mtu > ETH_DATA_LEN; |
5e00e16c | 2360 | int readrq = 4096; |
d58d46b5 | 2361 | |
485bb1b3 HK |
2362 | rtl_unlock_config_regs(tp); |
2363 | switch (tp->mac_version) { | |
485bb1b3 HK |
2364 | case RTL_GIGA_MAC_VER_12: |
2365 | case RTL_GIGA_MAC_VER_17: | |
9db0ac57 | 2366 | if (jumbo) { |
5e00e16c | 2367 | readrq = 512; |
9db0ac57 HK |
2368 | r8168b_1_hw_jumbo_enable(tp); |
2369 | } else { | |
2370 | r8168b_1_hw_jumbo_disable(tp); | |
2371 | } | |
485bb1b3 HK |
2372 | break; |
2373 | case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26: | |
9db0ac57 | 2374 | if (jumbo) { |
5e00e16c | 2375 | readrq = 512; |
9db0ac57 HK |
2376 | r8168c_hw_jumbo_enable(tp); |
2377 | } else { | |
2378 | r8168c_hw_jumbo_disable(tp); | |
2379 | } | |
485bb1b3 HK |
2380 | break; |
2381 | case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28: | |
9db0ac57 HK |
2382 | if (jumbo) |
2383 | r8168dp_hw_jumbo_enable(tp); | |
2384 | else | |
2385 | r8168dp_hw_jumbo_disable(tp); | |
485bb1b3 | 2386 | break; |
0fc75219 | 2387 | case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33: |
2007317e | 2388 | if (jumbo) |
9db0ac57 | 2389 | r8168e_hw_jumbo_enable(tp); |
2007317e | 2390 | else |
9db0ac57 | 2391 | r8168e_hw_jumbo_disable(tp); |
485bb1b3 | 2392 | break; |
d58d46b5 | 2393 | default: |
d58d46b5 FR |
2394 | break; |
2395 | } | |
485bb1b3 | 2396 | rtl_lock_config_regs(tp); |
21b5f672 | 2397 | |
5e00e16c HK |
2398 | if (pci_is_pcie(tp->pci_dev) && tp->supports_gmii) |
2399 | pcie_set_readrq(tp->pci_dev, readrq); | |
453a7789 HK |
2400 | |
2401 | /* Chip doesn't support pause in jumbo mode */ | |
11ac4e66 HK |
2402 | if (jumbo) { |
2403 | linkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT, | |
2404 | tp->phydev->advertising); | |
2405 | linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, | |
2406 | tp->phydev->advertising); | |
2407 | phy_start_aneg(tp->phydev); | |
2408 | } | |
d58d46b5 FR |
2409 | } |
2410 | ||
ffc46952 FR |
2411 | DECLARE_RTL_COND(rtl_chipcmd_cond) |
2412 | { | |
1ef7286e | 2413 | return RTL_R8(tp, ChipCmd) & CmdReset; |
ffc46952 FR |
2414 | } |
2415 | ||
6f43adc8 FR |
2416 | static void rtl_hw_reset(struct rtl8169_private *tp) |
2417 | { | |
1ef7286e | 2418 | RTL_W8(tp, ChipCmd, CmdReset); |
6f43adc8 | 2419 | |
d6836ef0 | 2420 | rtl_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100); |
6f43adc8 FR |
2421 | } |
2422 | ||
254764e5 | 2423 | static void rtl_request_firmware(struct rtl8169_private *tp) |
953a12cc | 2424 | { |
b6ffd97f | 2425 | struct rtl_fw *rtl_fw; |
953a12cc | 2426 | |
254764e5 HK |
2427 | /* firmware loaded already or no firmware available */ |
2428 | if (tp->rtl_fw || !tp->fw_name) | |
2429 | return; | |
953a12cc | 2430 | |
b6ffd97f | 2431 | rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL); |
3bf6ff3c | 2432 | if (!rtl_fw) |
47ad5931 | 2433 | return; |
31bd204f | 2434 | |
ce8843ab HK |
2435 | rtl_fw->phy_write = rtl_writephy; |
2436 | rtl_fw->phy_read = rtl_readphy; | |
2437 | rtl_fw->mac_mcu_write = mac_mcu_write; | |
2438 | rtl_fw->mac_mcu_read = mac_mcu_read; | |
4edb00f3 HK |
2439 | rtl_fw->fw_name = tp->fw_name; |
2440 | rtl_fw->dev = tp_to_dev(tp); | |
ce8843ab | 2441 | |
47ad5931 HK |
2442 | if (rtl_fw_request_firmware(rtl_fw)) |
2443 | kfree(rtl_fw); | |
2444 | else | |
2445 | tp->rtl_fw = rtl_fw; | |
953a12cc FR |
2446 | } |
2447 | ||
92fc43b4 HW |
2448 | static void rtl_rx_close(struct rtl8169_private *tp) |
2449 | { | |
1ef7286e | 2450 | RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK); |
92fc43b4 HW |
2451 | } |
2452 | ||
ffc46952 FR |
2453 | DECLARE_RTL_COND(rtl_npq_cond) |
2454 | { | |
1ef7286e | 2455 | return RTL_R8(tp, TxPoll) & NPQ; |
ffc46952 FR |
2456 | } |
2457 | ||
2458 | DECLARE_RTL_COND(rtl_txcfg_empty_cond) | |
2459 | { | |
1ef7286e | 2460 | return RTL_R32(tp, TxConfig) & TXCFG_EMPTY; |
ffc46952 FR |
2461 | } |
2462 | ||
6f9395c6 HK |
2463 | DECLARE_RTL_COND(rtl_rxtx_empty_cond) |
2464 | { | |
2465 | return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY; | |
2466 | } | |
2467 | ||
0439297b HK |
2468 | DECLARE_RTL_COND(rtl_rxtx_empty_cond_2) |
2469 | { | |
2470 | /* IntrMitigate has new functionality on RTL8125 */ | |
2471 | return (RTL_R16(tp, IntrMitigate) & 0x0103) == 0x0103; | |
2472 | } | |
2473 | ||
6f9395c6 HK |
2474 | static void rtl_wait_txrx_fifo_empty(struct rtl8169_private *tp) |
2475 | { | |
2476 | switch (tp->mac_version) { | |
e6d6ca6e | 2477 | case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53: |
6f9395c6 HK |
2478 | rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42); |
2479 | rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); | |
2480 | break; | |
2481 | case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_61: | |
2482 | rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); | |
2483 | break; | |
0439297b HK |
2484 | case RTL_GIGA_MAC_VER_63: |
2485 | RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); | |
2486 | rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); | |
2487 | rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond_2, 100, 42); | |
2488 | break; | |
6f9395c6 HK |
2489 | default: |
2490 | break; | |
2491 | } | |
2492 | } | |
2493 | ||
9617886f HK |
2494 | static void rtl_enable_rxdvgate(struct rtl8169_private *tp) |
2495 | { | |
2496 | RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN); | |
2497 | fsleep(2000); | |
6f9395c6 | 2498 | rtl_wait_txrx_fifo_empty(tp); |
9617886f HK |
2499 | } |
2500 | ||
05212ba8 | 2501 | static void rtl_set_tx_config_registers(struct rtl8169_private *tp) |
9cb427b6 | 2502 | { |
ad5f97fa HK |
2503 | u32 val = TX_DMA_BURST << TxDMAShift | |
2504 | InterFrameGap << TxInterFrameGapShift; | |
2505 | ||
9e9f33ba | 2506 | if (rtl_is_8168evl_up(tp)) |
ad5f97fa HK |
2507 | val |= TXCFG_AUTO_FIFO; |
2508 | ||
2509 | RTL_W32(tp, TxConfig, val); | |
9cb427b6 FR |
2510 | } |
2511 | ||
4fd48c4a | 2512 | static void rtl_set_rx_max_size(struct rtl8169_private *tp) |
1da177e4 | 2513 | { |
4fd48c4a HK |
2514 | /* Low hurts. Let's disable the filtering. */ |
2515 | RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1); | |
07ce4064 FR |
2516 | } |
2517 | ||
1ef7286e | 2518 | static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp) |
7f796d83 FR |
2519 | { |
2520 | /* | |
2521 | * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh | |
2522 | * register to be written before TxDescAddrLow to work. | |
2523 | * Switching from MMIO to I/O access fixes the issue as well. | |
2524 | */ | |
1ef7286e AS |
2525 | RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32); |
2526 | RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32)); | |
2527 | RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32); | |
2528 | RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32)); | |
7f796d83 FR |
2529 | } |
2530 | ||
ef891284 | 2531 | static void rtl8169_set_magic_reg(struct rtl8169_private *tp) |
6dccd16b | 2532 | { |
34bc0095 HK |
2533 | u32 val; |
2534 | ||
2535 | if (tp->mac_version == RTL_GIGA_MAC_VER_05) | |
2536 | val = 0x000fff00; | |
2537 | else if (tp->mac_version == RTL_GIGA_MAC_VER_06) | |
2538 | val = 0x00ffff00; | |
2539 | else | |
2540 | return; | |
2541 | ||
2542 | if (RTL_R8(tp, Config2) & PCI_Clock_66MHz) | |
2543 | val |= 0xff; | |
2544 | ||
2545 | RTL_W32(tp, 0x7c, val); | |
6dccd16b FR |
2546 | } |
2547 | ||
e6b763ea FR |
2548 | static void rtl_set_rx_mode(struct net_device *dev) |
2549 | { | |
81cd17a4 HK |
2550 | u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast; |
2551 | /* Multicast hash filter */ | |
2552 | u32 mc_filter[2] = { 0xffffffff, 0xffffffff }; | |
e6b763ea | 2553 | struct rtl8169_private *tp = netdev_priv(dev); |
81cd17a4 | 2554 | u32 tmp; |
e6b763ea FR |
2555 | |
2556 | if (dev->flags & IFF_PROMISC) { | |
81cd17a4 HK |
2557 | rx_mode |= AcceptAllPhys; |
2558 | } else if (netdev_mc_count(dev) > MC_FILTER_LIMIT || | |
2559 | dev->flags & IFF_ALLMULTI || | |
2560 | tp->mac_version == RTL_GIGA_MAC_VER_35) { | |
2561 | /* accept all multicasts */ | |
2562 | } else if (netdev_mc_empty(dev)) { | |
2563 | rx_mode &= ~AcceptMulticast; | |
e6b763ea FR |
2564 | } else { |
2565 | struct netdev_hw_addr *ha; | |
2566 | ||
e6b763ea FR |
2567 | mc_filter[1] = mc_filter[0] = 0; |
2568 | netdev_for_each_mc_addr(ha, dev) { | |
bc54ac36 | 2569 | u32 bit_nr = eth_hw_addr_crc(ha) >> 26; |
81cd17a4 HK |
2570 | mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31); |
2571 | } | |
2572 | ||
2573 | if (tp->mac_version > RTL_GIGA_MAC_VER_06) { | |
2574 | tmp = mc_filter[0]; | |
2575 | mc_filter[0] = swab32(mc_filter[1]); | |
2576 | mc_filter[1] = swab32(tmp); | |
e6b763ea FR |
2577 | } |
2578 | } | |
2579 | ||
1ef7286e AS |
2580 | RTL_W32(tp, MAR0 + 4, mc_filter[1]); |
2581 | RTL_W32(tp, MAR0 + 0, mc_filter[0]); | |
e6b763ea | 2582 | |
81cd17a4 | 2583 | tmp = RTL_R32(tp, RxConfig); |
10478283 | 2584 | RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_OK_MASK) | rx_mode); |
e6b763ea FR |
2585 | } |
2586 | ||
ffc46952 FR |
2587 | DECLARE_RTL_COND(rtl_csiar_cond) |
2588 | { | |
1ef7286e | 2589 | return RTL_R32(tp, CSIAR) & CSIAR_FLAG; |
ffc46952 FR |
2590 | } |
2591 | ||
ff1d7331 | 2592 | static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value) |
beb1fe18 | 2593 | { |
ff1d7331 | 2594 | u32 func = PCI_FUNC(tp->pci_dev->devfn); |
beb1fe18 | 2595 | |
1ef7286e AS |
2596 | RTL_W32(tp, CSIDR, value); |
2597 | RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | | |
ff1d7331 | 2598 | CSIAR_BYTE_ENABLE | func << 16); |
7e18dca1 | 2599 | |
d6836ef0 | 2600 | rtl_loop_wait_low(tp, &rtl_csiar_cond, 10, 100); |
7e18dca1 HW |
2601 | } |
2602 | ||
ff1d7331 | 2603 | static u32 rtl_csi_read(struct rtl8169_private *tp, int addr) |
7e18dca1 | 2604 | { |
ff1d7331 HK |
2605 | u32 func = PCI_FUNC(tp->pci_dev->devfn); |
2606 | ||
2607 | RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 | | |
2608 | CSIAR_BYTE_ENABLE); | |
7e18dca1 | 2609 | |
d6836ef0 | 2610 | return rtl_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ? |
1ef7286e | 2611 | RTL_R32(tp, CSIDR) : ~0; |
7e18dca1 HW |
2612 | } |
2613 | ||
c07c8ffc | 2614 | static void rtl_set_aspm_entry_latency(struct rtl8169_private *tp, u8 val) |
45dd95c4 | 2615 | { |
ff1d7331 HK |
2616 | struct pci_dev *pdev = tp->pci_dev; |
2617 | u32 csi; | |
45dd95c4 | 2618 | |
ff1d7331 HK |
2619 | /* According to Realtek the value at config space address 0x070f |
2620 | * controls the L0s/L1 entrance latency. We try standard ECAM access | |
2621 | * first and if it fails fall back to CSI. | |
c07c8ffc HK |
2622 | * bit 0..2: L0: 0 = 1us, 1 = 2us .. 6 = 7us, 7 = 7us (no typo) |
2623 | * bit 3..5: L1: 0 = 1us, 1 = 2us .. 6 = 64us, 7 = 64us | |
ff1d7331 HK |
2624 | */ |
2625 | if (pdev->cfg_size > 0x070f && | |
2626 | pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL) | |
2627 | return; | |
2628 | ||
2629 | netdev_notice_once(tp->dev, | |
2630 | "No native access to PCI extended config space, falling back to CSI\n"); | |
2631 | csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff; | |
2632 | rtl_csi_write(tp, 0x070c, csi | val << 24); | |
45dd95c4 | 2633 | } |
2634 | ||
f37658da | 2635 | static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp) |
beb1fe18 | 2636 | { |
c07c8ffc HK |
2637 | /* L0 7us, L1 16us */ |
2638 | rtl_set_aspm_entry_latency(tp, 0x27); | |
dacf8154 FR |
2639 | } |
2640 | ||
2641 | struct ephy_info { | |
2642 | unsigned int offset; | |
2643 | u16 mask; | |
2644 | u16 bits; | |
2645 | }; | |
2646 | ||
1791ad50 HK |
2647 | static void __rtl_ephy_init(struct rtl8169_private *tp, |
2648 | const struct ephy_info *e, int len) | |
dacf8154 FR |
2649 | { |
2650 | u16 w; | |
2651 | ||
2652 | while (len-- > 0) { | |
fdf6fc06 FR |
2653 | w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits; |
2654 | rtl_ephy_write(tp, e->offset, w); | |
dacf8154 FR |
2655 | e++; |
2656 | } | |
2657 | } | |
2658 | ||
1791ad50 HK |
2659 | #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a)) |
2660 | ||
73c86ee3 | 2661 | static void rtl_disable_clock_request(struct rtl8169_private *tp) |
b726e493 | 2662 | { |
73c86ee3 | 2663 | pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL, |
7d7903b2 | 2664 | PCI_EXP_LNKCTL_CLKREQ_EN); |
b726e493 FR |
2665 | } |
2666 | ||
73c86ee3 | 2667 | static void rtl_enable_clock_request(struct rtl8169_private *tp) |
e6de30d6 | 2668 | { |
73c86ee3 | 2669 | pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL, |
7d7903b2 | 2670 | PCI_EXP_LNKCTL_CLKREQ_EN); |
e6de30d6 | 2671 | } |
2672 | ||
c259b7f4 | 2673 | static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp) |
b51ecea8 | 2674 | { |
c259b7f4 HK |
2675 | /* work around an issue when PCI reset occurs during L2/L3 state */ |
2676 | RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23); | |
b51ecea8 | 2677 | } |
2678 | ||
4b33433e HK |
2679 | static void rtl_enable_exit_l1(struct rtl8169_private *tp) |
2680 | { | |
2681 | /* Bits control which events trigger ASPM L1 exit: | |
2682 | * Bit 12: rxdv | |
2683 | * Bit 11: ltr_msg | |
2684 | * Bit 10: txdma_poll | |
2685 | * Bit 9: xadm | |
2686 | * Bit 8: pktavi | |
2687 | * Bit 7: txpla | |
2688 | */ | |
2689 | switch (tp->mac_version) { | |
2690 | case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36: | |
2691 | rtl_eri_set_bits(tp, 0xd4, 0x1f00); | |
2692 | break; | |
2693 | case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_38: | |
2694 | rtl_eri_set_bits(tp, 0xd4, 0x0c00); | |
2695 | break; | |
2696 | case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53: | |
2697 | rtl_eri_set_bits(tp, 0xd4, 0x1f80); | |
2698 | break; | |
2699 | case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_63: | |
2700 | r8168_mac_ocp_modify(tp, 0xc0ac, 0, 0x1f80); | |
2701 | break; | |
2702 | default: | |
2703 | break; | |
2704 | } | |
2705 | } | |
2706 | ||
a99790bf KHF |
2707 | static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable) |
2708 | { | |
e71bf686 KHF |
2709 | struct pci_dev *pdev = tp->pci_dev; |
2710 | ||
2711 | /* Skip if PCIe ASPM isn't possible */ | |
2712 | if (!pcie_aspm_support_enabled() || !pcie_aspm_capable(pdev)) | |
2713 | return; | |
2714 | ||
55c779f2 KHF |
2715 | tp->rtl_aspm_enabled = enable; |
2716 | ||
e71bf686 | 2717 | if (enable) { |
a99790bf | 2718 | RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en); |
94235460 | 2719 | RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn); |
a99790bf KHF |
2720 | } else { |
2721 | RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn); | |
2722 | RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en); | |
2723 | } | |
94235460 KHF |
2724 | |
2725 | udelay(10); | |
a99790bf KHF |
2726 | } |
2727 | ||
6b1bd242 HK |
2728 | static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat, |
2729 | u16 tx_stat, u16 rx_dyn, u16 tx_dyn) | |
2730 | { | |
2731 | /* Usage of dynamic vs. static FIFO is controlled by bit | |
2732 | * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known. | |
2733 | */ | |
2734 | rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn); | |
2735 | rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn); | |
2736 | } | |
2737 | ||
0ebacd12 HK |
2738 | static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp, |
2739 | u8 low, u8 high) | |
2740 | { | |
2741 | /* FIFO thresholds for pause flow control */ | |
2742 | rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low); | |
2743 | rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high); | |
2744 | } | |
2745 | ||
94b5ff74 | 2746 | static void rtl_hw_start_8168b(struct rtl8169_private *tp) |
219a1e9d | 2747 | { |
1ef7286e | 2748 | RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); |
219a1e9d FR |
2749 | } |
2750 | ||
beb1fe18 | 2751 | static void __rtl_hw_start_8168cp(struct rtl8169_private *tp) |
219a1e9d | 2752 | { |
1ef7286e | 2753 | RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down); |
b726e493 | 2754 | |
1ef7286e | 2755 | RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); |
b726e493 | 2756 | |
73c86ee3 | 2757 | rtl_disable_clock_request(tp); |
219a1e9d FR |
2758 | } |
2759 | ||
beb1fe18 | 2760 | static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp) |
219a1e9d | 2761 | { |
350f7596 | 2762 | static const struct ephy_info e_info_8168cp[] = { |
b726e493 FR |
2763 | { 0x01, 0, 0x0001 }, |
2764 | { 0x02, 0x0800, 0x1000 }, | |
2765 | { 0x03, 0, 0x0042 }, | |
2766 | { 0x06, 0x0080, 0x0000 }, | |
2767 | { 0x07, 0, 0x2000 } | |
2768 | }; | |
2769 | ||
f37658da | 2770 | rtl_set_def_aspm_entry_latency(tp); |
b726e493 | 2771 | |
1791ad50 | 2772 | rtl_ephy_init(tp, e_info_8168cp); |
b726e493 | 2773 | |
beb1fe18 | 2774 | __rtl_hw_start_8168cp(tp); |
219a1e9d FR |
2775 | } |
2776 | ||
beb1fe18 | 2777 | static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp) |
ef3386f0 | 2778 | { |
f37658da | 2779 | rtl_set_def_aspm_entry_latency(tp); |
ef3386f0 | 2780 | |
1ef7286e | 2781 | RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); |
ef3386f0 FR |
2782 | } |
2783 | ||
beb1fe18 | 2784 | static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp) |
7f3e3d3a | 2785 | { |
f37658da | 2786 | rtl_set_def_aspm_entry_latency(tp); |
7f3e3d3a | 2787 | |
1ef7286e | 2788 | RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); |
7f3e3d3a FR |
2789 | |
2790 | /* Magic. */ | |
1ef7286e | 2791 | RTL_W8(tp, DBG_REG, 0x20); |
7f3e3d3a FR |
2792 | } |
2793 | ||
beb1fe18 | 2794 | static void rtl_hw_start_8168c_1(struct rtl8169_private *tp) |
219a1e9d | 2795 | { |
350f7596 | 2796 | static const struct ephy_info e_info_8168c_1[] = { |
b726e493 FR |
2797 | { 0x02, 0x0800, 0x1000 }, |
2798 | { 0x03, 0, 0x0002 }, | |
2799 | { 0x06, 0x0080, 0x0000 } | |
2800 | }; | |
2801 | ||
f37658da | 2802 | rtl_set_def_aspm_entry_latency(tp); |
b726e493 | 2803 | |
1ef7286e | 2804 | RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2); |
b726e493 | 2805 | |
1791ad50 | 2806 | rtl_ephy_init(tp, e_info_8168c_1); |
b726e493 | 2807 | |
beb1fe18 | 2808 | __rtl_hw_start_8168cp(tp); |
219a1e9d FR |
2809 | } |
2810 | ||
beb1fe18 | 2811 | static void rtl_hw_start_8168c_2(struct rtl8169_private *tp) |
219a1e9d | 2812 | { |
350f7596 | 2813 | static const struct ephy_info e_info_8168c_2[] = { |
b726e493 | 2814 | { 0x01, 0, 0x0001 }, |
a7a92cf8 | 2815 | { 0x03, 0x0400, 0x0020 } |
b726e493 FR |
2816 | }; |
2817 | ||
f37658da | 2818 | rtl_set_def_aspm_entry_latency(tp); |
b726e493 | 2819 | |
1791ad50 | 2820 | rtl_ephy_init(tp, e_info_8168c_2); |
b726e493 | 2821 | |
beb1fe18 | 2822 | __rtl_hw_start_8168cp(tp); |
219a1e9d FR |
2823 | } |
2824 | ||
beb1fe18 | 2825 | static void rtl_hw_start_8168c_4(struct rtl8169_private *tp) |
6fb07058 | 2826 | { |
f37658da | 2827 | rtl_set_def_aspm_entry_latency(tp); |
6fb07058 | 2828 | |
beb1fe18 | 2829 | __rtl_hw_start_8168cp(tp); |
6fb07058 FR |
2830 | } |
2831 | ||
beb1fe18 | 2832 | static void rtl_hw_start_8168d(struct rtl8169_private *tp) |
5b538df9 | 2833 | { |
f37658da | 2834 | rtl_set_def_aspm_entry_latency(tp); |
5b538df9 | 2835 | |
73c86ee3 | 2836 | rtl_disable_clock_request(tp); |
5b538df9 FR |
2837 | } |
2838 | ||
beb1fe18 | 2839 | static void rtl_hw_start_8168d_4(struct rtl8169_private *tp) |
e6de30d6 | 2840 | { |
2841 | static const struct ephy_info e_info_8168d_4[] = { | |
1016a4a1 CHL |
2842 | { 0x0b, 0x0000, 0x0048 }, |
2843 | { 0x19, 0x0020, 0x0050 }, | |
a7a92cf8 HK |
2844 | { 0x0c, 0x0100, 0x0020 }, |
2845 | { 0x10, 0x0004, 0x0000 }, | |
e6de30d6 | 2846 | }; |
e6de30d6 | 2847 | |
f37658da | 2848 | rtl_set_def_aspm_entry_latency(tp); |
e6de30d6 | 2849 | |
1791ad50 | 2850 | rtl_ephy_init(tp, e_info_8168d_4); |
e6de30d6 | 2851 | |
73c86ee3 | 2852 | rtl_enable_clock_request(tp); |
e6de30d6 | 2853 | } |
2854 | ||
beb1fe18 | 2855 | static void rtl_hw_start_8168e_1(struct rtl8169_private *tp) |
01dc7fec | 2856 | { |
70090424 | 2857 | static const struct ephy_info e_info_8168e_1[] = { |
01dc7fec | 2858 | { 0x00, 0x0200, 0x0100 }, |
2859 | { 0x00, 0x0000, 0x0004 }, | |
2860 | { 0x06, 0x0002, 0x0001 }, | |
2861 | { 0x06, 0x0000, 0x0030 }, | |
2862 | { 0x07, 0x0000, 0x2000 }, | |
2863 | { 0x00, 0x0000, 0x0020 }, | |
2864 | { 0x03, 0x5800, 0x2000 }, | |
2865 | { 0x03, 0x0000, 0x0001 }, | |
2866 | { 0x01, 0x0800, 0x1000 }, | |
2867 | { 0x07, 0x0000, 0x4000 }, | |
2868 | { 0x1e, 0x0000, 0x2000 }, | |
2869 | { 0x19, 0xffff, 0xfe6c }, | |
2870 | { 0x0a, 0x0000, 0x0040 } | |
2871 | }; | |
2872 | ||
f37658da | 2873 | rtl_set_def_aspm_entry_latency(tp); |
01dc7fec | 2874 | |
1791ad50 | 2875 | rtl_ephy_init(tp, e_info_8168e_1); |
01dc7fec | 2876 | |
73c86ee3 | 2877 | rtl_disable_clock_request(tp); |
01dc7fec | 2878 | |
2879 | /* Reset tx FIFO pointer */ | |
1ef7286e AS |
2880 | RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST); |
2881 | RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST); | |
01dc7fec | 2882 | |
1ef7286e | 2883 | RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en); |
01dc7fec | 2884 | } |
2885 | ||
beb1fe18 | 2886 | static void rtl_hw_start_8168e_2(struct rtl8169_private *tp) |
70090424 HW |
2887 | { |
2888 | static const struct ephy_info e_info_8168e_2[] = { | |
2889 | { 0x09, 0x0000, 0x0080 }, | |
a7a92cf8 HK |
2890 | { 0x19, 0x0000, 0x0224 }, |
2891 | { 0x00, 0x0000, 0x0004 }, | |
2892 | { 0x0c, 0x3df0, 0x0200 }, | |
70090424 HW |
2893 | }; |
2894 | ||
f37658da | 2895 | rtl_set_def_aspm_entry_latency(tp); |
70090424 | 2896 | |
1791ad50 | 2897 | rtl_ephy_init(tp, e_info_8168e_2); |
70090424 | 2898 | |
724c6fd0 | 2899 | rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); |
33b00ca1 | 2900 | rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); |
6b1bd242 | 2901 | rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); |
33b00ca1 HK |
2902 | rtl_eri_set_bits(tp, 0x1d0, BIT(1)); |
2903 | rtl_reset_packet_filter(tp); | |
2904 | rtl_eri_set_bits(tp, 0x1b0, BIT(4)); | |
724c6fd0 HK |
2905 | rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); |
2906 | rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060); | |
70090424 | 2907 | |
73c86ee3 | 2908 | rtl_disable_clock_request(tp); |
4521e1a9 | 2909 | |
1ef7286e | 2910 | RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); |
70090424 | 2911 | |
cc07d271 HK |
2912 | rtl8168_config_eee_mac(tp); |
2913 | ||
1ef7286e AS |
2914 | RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); |
2915 | RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); | |
2916 | RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en); | |
aa1e7d2c HK |
2917 | |
2918 | rtl_hw_aspm_clkreq_enable(tp, true); | |
70090424 HW |
2919 | } |
2920 | ||
5f886e08 | 2921 | static void rtl_hw_start_8168f(struct rtl8169_private *tp) |
c2218925 | 2922 | { |
f37658da | 2923 | rtl_set_def_aspm_entry_latency(tp); |
c2218925 | 2924 | |
724c6fd0 | 2925 | rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); |
d05890c5 | 2926 | rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); |
6b1bd242 | 2927 | rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); |
4e7e4621 | 2928 | rtl_reset_packet_filter(tp); |
54113ded | 2929 | rtl_eri_set_bits(tp, 0x1b0, BIT(4)); |
d05890c5 | 2930 | rtl_eri_set_bits(tp, 0x1d0, BIT(4) | BIT(1)); |
724c6fd0 HK |
2931 | rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); |
2932 | rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060); | |
c2218925 | 2933 | |
73c86ee3 | 2934 | rtl_disable_clock_request(tp); |
4521e1a9 | 2935 | |
1ef7286e AS |
2936 | RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); |
2937 | RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); | |
2938 | RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); | |
2939 | RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en); | |
cc07d271 HK |
2940 | |
2941 | rtl8168_config_eee_mac(tp); | |
c2218925 HW |
2942 | } |
2943 | ||
5f886e08 HW |
2944 | static void rtl_hw_start_8168f_1(struct rtl8169_private *tp) |
2945 | { | |
5f886e08 HW |
2946 | static const struct ephy_info e_info_8168f_1[] = { |
2947 | { 0x06, 0x00c0, 0x0020 }, | |
2948 | { 0x08, 0x0001, 0x0002 }, | |
2949 | { 0x09, 0x0000, 0x0080 }, | |
a7a92cf8 | 2950 | { 0x19, 0x0000, 0x0224 }, |
709a16be | 2951 | { 0x00, 0x0000, 0x0008 }, |
a7a92cf8 | 2952 | { 0x0c, 0x3df0, 0x0200 }, |
5f886e08 HW |
2953 | }; |
2954 | ||
2955 | rtl_hw_start_8168f(tp); | |
2956 | ||
1791ad50 | 2957 | rtl_ephy_init(tp, e_info_8168f_1); |
5f886e08 HW |
2958 | } |
2959 | ||
b3d7b2f2 HW |
2960 | static void rtl_hw_start_8411(struct rtl8169_private *tp) |
2961 | { | |
b3d7b2f2 HW |
2962 | static const struct ephy_info e_info_8168f_1[] = { |
2963 | { 0x06, 0x00c0, 0x0020 }, | |
2964 | { 0x0f, 0xffff, 0x5200 }, | |
a7a92cf8 | 2965 | { 0x19, 0x0000, 0x0224 }, |
709a16be | 2966 | { 0x00, 0x0000, 0x0008 }, |
a7a92cf8 | 2967 | { 0x0c, 0x3df0, 0x0200 }, |
b3d7b2f2 HW |
2968 | }; |
2969 | ||
2970 | rtl_hw_start_8168f(tp); | |
c259b7f4 | 2971 | rtl_pcie_state_l2l3_disable(tp); |
b3d7b2f2 | 2972 | |
1791ad50 | 2973 | rtl_ephy_init(tp, e_info_8168f_1); |
b3d7b2f2 HW |
2974 | } |
2975 | ||
5fbea337 | 2976 | static void rtl_hw_start_8168g(struct rtl8169_private *tp) |
c558386b | 2977 | { |
6b1bd242 | 2978 | rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); |
0ebacd12 | 2979 | rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); |
c558386b | 2980 | |
f37658da | 2981 | rtl_set_def_aspm_entry_latency(tp); |
c558386b | 2982 | |
4e7e4621 | 2983 | rtl_reset_packet_filter(tp); |
724c6fd0 | 2984 | rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f); |
c558386b | 2985 | |
1ef7286e | 2986 | RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); |
c558386b | 2987 | |
724c6fd0 HK |
2988 | rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); |
2989 | rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); | |
c558386b | 2990 | |
df6f1856 HK |
2991 | rtl8168_config_eee_mac(tp); |
2992 | ||
54113ded HK |
2993 | rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); |
2994 | rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); | |
b51ecea8 | 2995 | |
c259b7f4 | 2996 | rtl_pcie_state_l2l3_disable(tp); |
c558386b HW |
2997 | } |
2998 | ||
5fbea337 CHL |
2999 | static void rtl_hw_start_8168g_1(struct rtl8169_private *tp) |
3000 | { | |
5fbea337 | 3001 | static const struct ephy_info e_info_8168g_1[] = { |
a7a92cf8 HK |
3002 | { 0x00, 0x0008, 0x0000 }, |
3003 | { 0x0c, 0x3ff0, 0x0820 }, | |
5fbea337 CHL |
3004 | { 0x1e, 0x0000, 0x0001 }, |
3005 | { 0x19, 0x8000, 0x0000 } | |
3006 | }; | |
3007 | ||
3008 | rtl_hw_start_8168g(tp); | |
3009 | ||
3010 | /* disable aspm and clock request before access ephy */ | |
a99790bf | 3011 | rtl_hw_aspm_clkreq_enable(tp, false); |
1791ad50 | 3012 | rtl_ephy_init(tp, e_info_8168g_1); |
a99790bf | 3013 | rtl_hw_aspm_clkreq_enable(tp, true); |
5fbea337 CHL |
3014 | } |
3015 | ||
57538c4a | 3016 | static void rtl_hw_start_8168g_2(struct rtl8169_private *tp) |
3017 | { | |
57538c4a | 3018 | static const struct ephy_info e_info_8168g_2[] = { |
a7a92cf8 HK |
3019 | { 0x00, 0x0008, 0x0000 }, |
3020 | { 0x0c, 0x3ff0, 0x0820 }, | |
3021 | { 0x19, 0xffff, 0x7c00 }, | |
3022 | { 0x1e, 0xffff, 0x20eb }, | |
3023 | { 0x0d, 0xffff, 0x1666 }, | |
3024 | { 0x00, 0xffff, 0x10a3 }, | |
3025 | { 0x06, 0xffff, 0xf050 }, | |
3026 | { 0x04, 0x0000, 0x0010 }, | |
3027 | { 0x1d, 0x4000, 0x0000 }, | |
57538c4a | 3028 | }; |
3029 | ||
5fbea337 | 3030 | rtl_hw_start_8168g(tp); |
57538c4a | 3031 | |
3032 | /* disable aspm and clock request before access ephy */ | |
ebdcebcb | 3033 | rtl_hw_aspm_clkreq_enable(tp, false); |
1791ad50 | 3034 | rtl_ephy_init(tp, e_info_8168g_2); |
57538c4a | 3035 | } |
3036 | ||
45dd95c4 | 3037 | static void rtl_hw_start_8411_2(struct rtl8169_private *tp) |
3038 | { | |
45dd95c4 | 3039 | static const struct ephy_info e_info_8411_2[] = { |
a7a92cf8 HK |
3040 | { 0x00, 0x0008, 0x0000 }, |
3041 | { 0x0c, 0x37d0, 0x0820 }, | |
3042 | { 0x1e, 0x0000, 0x0001 }, | |
3043 | { 0x19, 0x8021, 0x0000 }, | |
3044 | { 0x1e, 0x0000, 0x2000 }, | |
3045 | { 0x0d, 0x0100, 0x0200 }, | |
3046 | { 0x00, 0x0000, 0x0080 }, | |
3047 | { 0x06, 0x0000, 0x0010 }, | |
3048 | { 0x04, 0x0000, 0x0010 }, | |
3049 | { 0x1d, 0x0000, 0x4000 }, | |
45dd95c4 | 3050 | }; |
3051 | ||
5fbea337 | 3052 | rtl_hw_start_8168g(tp); |
45dd95c4 | 3053 | |
3054 | /* disable aspm and clock request before access ephy */ | |
a99790bf | 3055 | rtl_hw_aspm_clkreq_enable(tp, false); |
1791ad50 | 3056 | rtl_ephy_init(tp, e_info_8411_2); |
fe4e8db0 HK |
3057 | |
3058 | /* The following Realtek-provided magic fixes an issue with the RX unit | |
3059 | * getting confused after the PHY having been powered-down. | |
3060 | */ | |
3061 | r8168_mac_ocp_write(tp, 0xFC28, 0x0000); | |
3062 | r8168_mac_ocp_write(tp, 0xFC2A, 0x0000); | |
3063 | r8168_mac_ocp_write(tp, 0xFC2C, 0x0000); | |
3064 | r8168_mac_ocp_write(tp, 0xFC2E, 0x0000); | |
3065 | r8168_mac_ocp_write(tp, 0xFC30, 0x0000); | |
3066 | r8168_mac_ocp_write(tp, 0xFC32, 0x0000); | |
3067 | r8168_mac_ocp_write(tp, 0xFC34, 0x0000); | |
3068 | r8168_mac_ocp_write(tp, 0xFC36, 0x0000); | |
3069 | mdelay(3); | |
3070 | r8168_mac_ocp_write(tp, 0xFC26, 0x0000); | |
3071 | ||
3072 | r8168_mac_ocp_write(tp, 0xF800, 0xE008); | |
3073 | r8168_mac_ocp_write(tp, 0xF802, 0xE00A); | |
3074 | r8168_mac_ocp_write(tp, 0xF804, 0xE00C); | |
3075 | r8168_mac_ocp_write(tp, 0xF806, 0xE00E); | |
3076 | r8168_mac_ocp_write(tp, 0xF808, 0xE027); | |
3077 | r8168_mac_ocp_write(tp, 0xF80A, 0xE04F); | |
3078 | r8168_mac_ocp_write(tp, 0xF80C, 0xE05E); | |
3079 | r8168_mac_ocp_write(tp, 0xF80E, 0xE065); | |
3080 | r8168_mac_ocp_write(tp, 0xF810, 0xC602); | |
3081 | r8168_mac_ocp_write(tp, 0xF812, 0xBE00); | |
3082 | r8168_mac_ocp_write(tp, 0xF814, 0x0000); | |
3083 | r8168_mac_ocp_write(tp, 0xF816, 0xC502); | |
3084 | r8168_mac_ocp_write(tp, 0xF818, 0xBD00); | |
3085 | r8168_mac_ocp_write(tp, 0xF81A, 0x074C); | |
3086 | r8168_mac_ocp_write(tp, 0xF81C, 0xC302); | |
3087 | r8168_mac_ocp_write(tp, 0xF81E, 0xBB00); | |
3088 | r8168_mac_ocp_write(tp, 0xF820, 0x080A); | |
3089 | r8168_mac_ocp_write(tp, 0xF822, 0x6420); | |
3090 | r8168_mac_ocp_write(tp, 0xF824, 0x48C2); | |
3091 | r8168_mac_ocp_write(tp, 0xF826, 0x8C20); | |
3092 | r8168_mac_ocp_write(tp, 0xF828, 0xC516); | |
3093 | r8168_mac_ocp_write(tp, 0xF82A, 0x64A4); | |
3094 | r8168_mac_ocp_write(tp, 0xF82C, 0x49C0); | |
3095 | r8168_mac_ocp_write(tp, 0xF82E, 0xF009); | |
3096 | r8168_mac_ocp_write(tp, 0xF830, 0x74A2); | |
3097 | r8168_mac_ocp_write(tp, 0xF832, 0x8CA5); | |
3098 | r8168_mac_ocp_write(tp, 0xF834, 0x74A0); | |
3099 | r8168_mac_ocp_write(tp, 0xF836, 0xC50E); | |
3100 | r8168_mac_ocp_write(tp, 0xF838, 0x9CA2); | |
3101 | r8168_mac_ocp_write(tp, 0xF83A, 0x1C11); | |
3102 | r8168_mac_ocp_write(tp, 0xF83C, 0x9CA0); | |
3103 | r8168_mac_ocp_write(tp, 0xF83E, 0xE006); | |
3104 | r8168_mac_ocp_write(tp, 0xF840, 0x74F8); | |
3105 | r8168_mac_ocp_write(tp, 0xF842, 0x48C4); | |
3106 | r8168_mac_ocp_write(tp, 0xF844, 0x8CF8); | |
3107 | r8168_mac_ocp_write(tp, 0xF846, 0xC404); | |
3108 | r8168_mac_ocp_write(tp, 0xF848, 0xBC00); | |
3109 | r8168_mac_ocp_write(tp, 0xF84A, 0xC403); | |
3110 | r8168_mac_ocp_write(tp, 0xF84C, 0xBC00); | |
3111 | r8168_mac_ocp_write(tp, 0xF84E, 0x0BF2); | |
3112 | r8168_mac_ocp_write(tp, 0xF850, 0x0C0A); | |
3113 | r8168_mac_ocp_write(tp, 0xF852, 0xE434); | |
3114 | r8168_mac_ocp_write(tp, 0xF854, 0xD3C0); | |
3115 | r8168_mac_ocp_write(tp, 0xF856, 0x49D9); | |
3116 | r8168_mac_ocp_write(tp, 0xF858, 0xF01F); | |
3117 | r8168_mac_ocp_write(tp, 0xF85A, 0xC526); | |
3118 | r8168_mac_ocp_write(tp, 0xF85C, 0x64A5); | |
3119 | r8168_mac_ocp_write(tp, 0xF85E, 0x1400); | |
3120 | r8168_mac_ocp_write(tp, 0xF860, 0xF007); | |
3121 | r8168_mac_ocp_write(tp, 0xF862, 0x0C01); | |
3122 | r8168_mac_ocp_write(tp, 0xF864, 0x8CA5); | |
3123 | r8168_mac_ocp_write(tp, 0xF866, 0x1C15); | |
3124 | r8168_mac_ocp_write(tp, 0xF868, 0xC51B); | |
3125 | r8168_mac_ocp_write(tp, 0xF86A, 0x9CA0); | |
3126 | r8168_mac_ocp_write(tp, 0xF86C, 0xE013); | |
3127 | r8168_mac_ocp_write(tp, 0xF86E, 0xC519); | |
3128 | r8168_mac_ocp_write(tp, 0xF870, 0x74A0); | |
3129 | r8168_mac_ocp_write(tp, 0xF872, 0x48C4); | |
3130 | r8168_mac_ocp_write(tp, 0xF874, 0x8CA0); | |
3131 | r8168_mac_ocp_write(tp, 0xF876, 0xC516); | |
3132 | r8168_mac_ocp_write(tp, 0xF878, 0x74A4); | |
3133 | r8168_mac_ocp_write(tp, 0xF87A, 0x48C8); | |
3134 | r8168_mac_ocp_write(tp, 0xF87C, 0x48CA); | |
3135 | r8168_mac_ocp_write(tp, 0xF87E, 0x9CA4); | |
3136 | r8168_mac_ocp_write(tp, 0xF880, 0xC512); | |
3137 | r8168_mac_ocp_write(tp, 0xF882, 0x1B00); | |
3138 | r8168_mac_ocp_write(tp, 0xF884, 0x9BA0); | |
3139 | r8168_mac_ocp_write(tp, 0xF886, 0x1B1C); | |
3140 | r8168_mac_ocp_write(tp, 0xF888, 0x483F); | |
3141 | r8168_mac_ocp_write(tp, 0xF88A, 0x9BA2); | |
3142 | r8168_mac_ocp_write(tp, 0xF88C, 0x1B04); | |
3143 | r8168_mac_ocp_write(tp, 0xF88E, 0xC508); | |
3144 | r8168_mac_ocp_write(tp, 0xF890, 0x9BA0); | |
3145 | r8168_mac_ocp_write(tp, 0xF892, 0xC505); | |
3146 | r8168_mac_ocp_write(tp, 0xF894, 0xBD00); | |
3147 | r8168_mac_ocp_write(tp, 0xF896, 0xC502); | |
3148 | r8168_mac_ocp_write(tp, 0xF898, 0xBD00); | |
3149 | r8168_mac_ocp_write(tp, 0xF89A, 0x0300); | |
3150 | r8168_mac_ocp_write(tp, 0xF89C, 0x051E); | |
3151 | r8168_mac_ocp_write(tp, 0xF89E, 0xE434); | |
3152 | r8168_mac_ocp_write(tp, 0xF8A0, 0xE018); | |
3153 | r8168_mac_ocp_write(tp, 0xF8A2, 0xE092); | |
3154 | r8168_mac_ocp_write(tp, 0xF8A4, 0xDE20); | |
3155 | r8168_mac_ocp_write(tp, 0xF8A6, 0xD3C0); | |
3156 | r8168_mac_ocp_write(tp, 0xF8A8, 0xC50F); | |
3157 | r8168_mac_ocp_write(tp, 0xF8AA, 0x76A4); | |
3158 | r8168_mac_ocp_write(tp, 0xF8AC, 0x49E3); | |
3159 | r8168_mac_ocp_write(tp, 0xF8AE, 0xF007); | |
3160 | r8168_mac_ocp_write(tp, 0xF8B0, 0x49C0); | |
3161 | r8168_mac_ocp_write(tp, 0xF8B2, 0xF103); | |
3162 | r8168_mac_ocp_write(tp, 0xF8B4, 0xC607); | |
3163 | r8168_mac_ocp_write(tp, 0xF8B6, 0xBE00); | |
3164 | r8168_mac_ocp_write(tp, 0xF8B8, 0xC606); | |
3165 | r8168_mac_ocp_write(tp, 0xF8BA, 0xBE00); | |
3166 | r8168_mac_ocp_write(tp, 0xF8BC, 0xC602); | |
3167 | r8168_mac_ocp_write(tp, 0xF8BE, 0xBE00); | |
3168 | r8168_mac_ocp_write(tp, 0xF8C0, 0x0C4C); | |
3169 | r8168_mac_ocp_write(tp, 0xF8C2, 0x0C28); | |
3170 | r8168_mac_ocp_write(tp, 0xF8C4, 0x0C2C); | |
3171 | r8168_mac_ocp_write(tp, 0xF8C6, 0xDC00); | |
3172 | r8168_mac_ocp_write(tp, 0xF8C8, 0xC707); | |
3173 | r8168_mac_ocp_write(tp, 0xF8CA, 0x1D00); | |
3174 | r8168_mac_ocp_write(tp, 0xF8CC, 0x8DE2); | |
3175 | r8168_mac_ocp_write(tp, 0xF8CE, 0x48C1); | |
3176 | r8168_mac_ocp_write(tp, 0xF8D0, 0xC502); | |
3177 | r8168_mac_ocp_write(tp, 0xF8D2, 0xBD00); | |
3178 | r8168_mac_ocp_write(tp, 0xF8D4, 0x00AA); | |
3179 | r8168_mac_ocp_write(tp, 0xF8D6, 0xE0C0); | |
3180 | r8168_mac_ocp_write(tp, 0xF8D8, 0xC502); | |
3181 | r8168_mac_ocp_write(tp, 0xF8DA, 0xBD00); | |
3182 | r8168_mac_ocp_write(tp, 0xF8DC, 0x0132); | |
3183 | ||
3184 | r8168_mac_ocp_write(tp, 0xFC26, 0x8000); | |
3185 | ||
3186 | r8168_mac_ocp_write(tp, 0xFC2A, 0x0743); | |
3187 | r8168_mac_ocp_write(tp, 0xFC2C, 0x0801); | |
3188 | r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9); | |
3189 | r8168_mac_ocp_write(tp, 0xFC30, 0x02FD); | |
3190 | r8168_mac_ocp_write(tp, 0xFC32, 0x0C25); | |
3191 | r8168_mac_ocp_write(tp, 0xFC34, 0x00A9); | |
3192 | r8168_mac_ocp_write(tp, 0xFC36, 0x012D); | |
3193 | ||
a99790bf | 3194 | rtl_hw_aspm_clkreq_enable(tp, true); |
45dd95c4 | 3195 | } |
3196 | ||
6e1d0b89 CHL |
3197 | static void rtl_hw_start_8168h_1(struct rtl8169_private *tp) |
3198 | { | |
6e1d0b89 CHL |
3199 | static const struct ephy_info e_info_8168h_1[] = { |
3200 | { 0x1e, 0x0800, 0x0001 }, | |
3201 | { 0x1d, 0x0000, 0x0800 }, | |
3202 | { 0x05, 0xffff, 0x2089 }, | |
3203 | { 0x06, 0xffff, 0x5881 }, | |
a7a92cf8 | 3204 | { 0x04, 0xffff, 0x854a }, |
6e1d0b89 CHL |
3205 | { 0x01, 0xffff, 0x068b } |
3206 | }; | |
ef712ede | 3207 | int rg_saw_cnt; |
6e1d0b89 CHL |
3208 | |
3209 | /* disable aspm and clock request before access ephy */ | |
a99790bf | 3210 | rtl_hw_aspm_clkreq_enable(tp, false); |
1791ad50 | 3211 | rtl_ephy_init(tp, e_info_8168h_1); |
6e1d0b89 | 3212 | |
6b1bd242 | 3213 | rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); |
0ebacd12 | 3214 | rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); |
6e1d0b89 | 3215 | |
f37658da | 3216 | rtl_set_def_aspm_entry_latency(tp); |
6e1d0b89 | 3217 | |
4e7e4621 | 3218 | rtl_reset_packet_filter(tp); |
6e1d0b89 | 3219 | |
ee1350f9 | 3220 | rtl_eri_set_bits(tp, 0xdc, 0x001c); |
6e1d0b89 | 3221 | |
724c6fd0 | 3222 | rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); |
6e1d0b89 | 3223 | |
1ef7286e | 3224 | RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); |
6e1d0b89 | 3225 | |
724c6fd0 HK |
3226 | rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); |
3227 | rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); | |
6e1d0b89 | 3228 | |
df6f1856 HK |
3229 | rtl8168_config_eee_mac(tp); |
3230 | ||
1ef7286e AS |
3231 | RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); |
3232 | RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); | |
6e1d0b89 | 3233 | |
1ef7286e | 3234 | RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); |
6e1d0b89 | 3235 | |
54113ded | 3236 | rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); |
6e1d0b89 | 3237 | |
c259b7f4 | 3238 | rtl_pcie_state_l2l3_disable(tp); |
6e1d0b89 | 3239 | |
3ab077d2 | 3240 | rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; |
6e1d0b89 CHL |
3241 | if (rg_saw_cnt > 0) { |
3242 | u16 sw_cnt_1ms_ini; | |
3243 | ||
3244 | sw_cnt_1ms_ini = 16000000/rg_saw_cnt; | |
3245 | sw_cnt_1ms_ini &= 0x0fff; | |
ef712ede | 3246 | r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); |
6e1d0b89 CHL |
3247 | } |
3248 | ||
ef712ede HK |
3249 | r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); |
3250 | r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008); | |
3251 | r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f); | |
3252 | r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); | |
6e1d0b89 CHL |
3253 | |
3254 | r8168_mac_ocp_write(tp, 0xe63e, 0x0001); | |
3255 | r8168_mac_ocp_write(tp, 0xe63e, 0x0000); | |
3256 | r8168_mac_ocp_write(tp, 0xc094, 0x0000); | |
3257 | r8168_mac_ocp_write(tp, 0xc09e, 0x0000); | |
a99790bf KHF |
3258 | |
3259 | rtl_hw_aspm_clkreq_enable(tp, true); | |
6e1d0b89 CHL |
3260 | } |
3261 | ||
935e2218 CHL |
3262 | static void rtl_hw_start_8168ep(struct rtl8169_private *tp) |
3263 | { | |
003609da CHL |
3264 | rtl8168ep_stop_cmac(tp); |
3265 | ||
6b1bd242 | 3266 | rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); |
0ebacd12 | 3267 | rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); |
935e2218 | 3268 | |
f37658da | 3269 | rtl_set_def_aspm_entry_latency(tp); |
935e2218 | 3270 | |
4e7e4621 | 3271 | rtl_reset_packet_filter(tp); |
935e2218 | 3272 | |
724c6fd0 | 3273 | rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); |
935e2218 | 3274 | |
1ef7286e | 3275 | RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); |
935e2218 | 3276 | |
724c6fd0 HK |
3277 | rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); |
3278 | rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); | |
935e2218 | 3279 | |
df6f1856 HK |
3280 | rtl8168_config_eee_mac(tp); |
3281 | ||
54113ded | 3282 | rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); |
935e2218 | 3283 | |
1ef7286e | 3284 | RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); |
935e2218 | 3285 | |
c259b7f4 | 3286 | rtl_pcie_state_l2l3_disable(tp); |
935e2218 CHL |
3287 | } |
3288 | ||
3289 | static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp) | |
3290 | { | |
935e2218 CHL |
3291 | static const struct ephy_info e_info_8168ep_1[] = { |
3292 | { 0x00, 0xffff, 0x10ab }, | |
3293 | { 0x06, 0xffff, 0xf030 }, | |
3294 | { 0x08, 0xffff, 0x2006 }, | |
3295 | { 0x0d, 0xffff, 0x1666 }, | |
3296 | { 0x0c, 0x3ff0, 0x0000 } | |
3297 | }; | |
3298 | ||
3299 | /* disable aspm and clock request before access ephy */ | |
a99790bf | 3300 | rtl_hw_aspm_clkreq_enable(tp, false); |
1791ad50 | 3301 | rtl_ephy_init(tp, e_info_8168ep_1); |
935e2218 CHL |
3302 | |
3303 | rtl_hw_start_8168ep(tp); | |
a99790bf KHF |
3304 | |
3305 | rtl_hw_aspm_clkreq_enable(tp, true); | |
935e2218 CHL |
3306 | } |
3307 | ||
3308 | static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp) | |
3309 | { | |
935e2218 CHL |
3310 | static const struct ephy_info e_info_8168ep_2[] = { |
3311 | { 0x00, 0xffff, 0x10a3 }, | |
3312 | { 0x19, 0xffff, 0xfc00 }, | |
3313 | { 0x1e, 0xffff, 0x20ea } | |
3314 | }; | |
3315 | ||
3316 | /* disable aspm and clock request before access ephy */ | |
a99790bf | 3317 | rtl_hw_aspm_clkreq_enable(tp, false); |
1791ad50 | 3318 | rtl_ephy_init(tp, e_info_8168ep_2); |
935e2218 CHL |
3319 | |
3320 | rtl_hw_start_8168ep(tp); | |
3321 | ||
1ef7286e AS |
3322 | RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); |
3323 | RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); | |
a99790bf KHF |
3324 | |
3325 | rtl_hw_aspm_clkreq_enable(tp, true); | |
935e2218 CHL |
3326 | } |
3327 | ||
3328 | static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp) | |
3329 | { | |
935e2218 | 3330 | static const struct ephy_info e_info_8168ep_3[] = { |
a7a92cf8 HK |
3331 | { 0x00, 0x0000, 0x0080 }, |
3332 | { 0x0d, 0x0100, 0x0200 }, | |
3333 | { 0x19, 0x8021, 0x0000 }, | |
3334 | { 0x1e, 0x0000, 0x2000 }, | |
935e2218 CHL |
3335 | }; |
3336 | ||
3337 | /* disable aspm and clock request before access ephy */ | |
a99790bf | 3338 | rtl_hw_aspm_clkreq_enable(tp, false); |
1791ad50 | 3339 | rtl_ephy_init(tp, e_info_8168ep_3); |
935e2218 CHL |
3340 | |
3341 | rtl_hw_start_8168ep(tp); | |
3342 | ||
1ef7286e AS |
3343 | RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); |
3344 | RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); | |
935e2218 | 3345 | |
ef712ede HK |
3346 | r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271); |
3347 | r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); | |
3348 | r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); | |
a99790bf KHF |
3349 | |
3350 | rtl_hw_aspm_clkreq_enable(tp, true); | |
935e2218 CHL |
3351 | } |
3352 | ||
1287723a HK |
3353 | static void rtl_hw_start_8117(struct rtl8169_private *tp) |
3354 | { | |
3355 | static const struct ephy_info e_info_8117[] = { | |
3356 | { 0x19, 0x0040, 0x1100 }, | |
3357 | { 0x59, 0x0040, 0x1100 }, | |
3358 | }; | |
3359 | int rg_saw_cnt; | |
3360 | ||
3361 | rtl8168ep_stop_cmac(tp); | |
3362 | ||
3363 | /* disable aspm and clock request before access ephy */ | |
3364 | rtl_hw_aspm_clkreq_enable(tp, false); | |
3365 | rtl_ephy_init(tp, e_info_8117); | |
3366 | ||
3367 | rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); | |
3368 | rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); | |
3369 | ||
3370 | rtl_set_def_aspm_entry_latency(tp); | |
3371 | ||
3372 | rtl_reset_packet_filter(tp); | |
3373 | ||
4b33433e | 3374 | rtl_eri_set_bits(tp, 0xd4, 0x0010); |
1287723a HK |
3375 | |
3376 | rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); | |
3377 | ||
3378 | RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); | |
3379 | ||
3380 | rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); | |
3381 | rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); | |
3382 | ||
3383 | rtl8168_config_eee_mac(tp); | |
3384 | ||
3385 | RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); | |
3386 | RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); | |
3387 | ||
3388 | RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); | |
3389 | ||
54113ded | 3390 | rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); |
1287723a HK |
3391 | |
3392 | rtl_pcie_state_l2l3_disable(tp); | |
3393 | ||
3394 | rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; | |
3395 | if (rg_saw_cnt > 0) { | |
3396 | u16 sw_cnt_1ms_ini; | |
3397 | ||
3398 | sw_cnt_1ms_ini = (16000000 / rg_saw_cnt) & 0x0fff; | |
3399 | r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); | |
3400 | } | |
3401 | ||
3402 | r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); | |
3403 | r8168_mac_ocp_write(tp, 0xea80, 0x0003); | |
3404 | r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009); | |
3405 | r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); | |
3406 | ||
3407 | r8168_mac_ocp_write(tp, 0xe63e, 0x0001); | |
3408 | r8168_mac_ocp_write(tp, 0xe63e, 0x0000); | |
3409 | r8168_mac_ocp_write(tp, 0xc094, 0x0000); | |
3410 | r8168_mac_ocp_write(tp, 0xc09e, 0x0000); | |
3411 | ||
229c1e0d | 3412 | /* firmware is for MAC only */ |
1c5be5e9 | 3413 | r8169_apply_firmware(tp); |
229c1e0d | 3414 | |
1287723a HK |
3415 | rtl_hw_aspm_clkreq_enable(tp, true); |
3416 | } | |
3417 | ||
beb1fe18 | 3418 | static void rtl_hw_start_8102e_1(struct rtl8169_private *tp) |
2857ffb7 | 3419 | { |
350f7596 | 3420 | static const struct ephy_info e_info_8102e_1[] = { |
2857ffb7 FR |
3421 | { 0x01, 0, 0x6e65 }, |
3422 | { 0x02, 0, 0x091f }, | |
3423 | { 0x03, 0, 0xc2f9 }, | |
3424 | { 0x06, 0, 0xafb5 }, | |
3425 | { 0x07, 0, 0x0e00 }, | |
3426 | { 0x19, 0, 0xec80 }, | |
3427 | { 0x01, 0, 0x2e65 }, | |
3428 | { 0x01, 0, 0x6e65 } | |
3429 | }; | |
3430 | u8 cfg1; | |
3431 | ||
f37658da | 3432 | rtl_set_def_aspm_entry_latency(tp); |
2857ffb7 | 3433 | |
1ef7286e | 3434 | RTL_W8(tp, DBG_REG, FIX_NAK_1); |
2857ffb7 | 3435 | |
1ef7286e | 3436 | RTL_W8(tp, Config1, |
2857ffb7 | 3437 | LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable); |
1ef7286e | 3438 | RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); |
2857ffb7 | 3439 | |
1ef7286e | 3440 | cfg1 = RTL_R8(tp, Config1); |
2857ffb7 | 3441 | if ((cfg1 & LEDS0) && (cfg1 & LEDS1)) |
1ef7286e | 3442 | RTL_W8(tp, Config1, cfg1 & ~LEDS0); |
2857ffb7 | 3443 | |
1791ad50 | 3444 | rtl_ephy_init(tp, e_info_8102e_1); |
2857ffb7 FR |
3445 | } |
3446 | ||
beb1fe18 | 3447 | static void rtl_hw_start_8102e_2(struct rtl8169_private *tp) |
2857ffb7 | 3448 | { |
f37658da | 3449 | rtl_set_def_aspm_entry_latency(tp); |
2857ffb7 | 3450 | |
1ef7286e AS |
3451 | RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable); |
3452 | RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); | |
2857ffb7 FR |
3453 | } |
3454 | ||
beb1fe18 | 3455 | static void rtl_hw_start_8102e_3(struct rtl8169_private *tp) |
2857ffb7 | 3456 | { |
beb1fe18 | 3457 | rtl_hw_start_8102e_2(tp); |
2857ffb7 | 3458 | |
fdf6fc06 | 3459 | rtl_ephy_write(tp, 0x03, 0xc2f9); |
2857ffb7 FR |
3460 | } |
3461 | ||
cdafdc29 HK |
3462 | static void rtl_hw_start_8401(struct rtl8169_private *tp) |
3463 | { | |
3464 | static const struct ephy_info e_info_8401[] = { | |
3465 | { 0x01, 0xffff, 0x6fe5 }, | |
3466 | { 0x03, 0xffff, 0x0599 }, | |
3467 | { 0x06, 0xffff, 0xaf25 }, | |
3468 | { 0x07, 0xffff, 0x8e68 }, | |
3469 | }; | |
3470 | ||
3471 | rtl_ephy_init(tp, e_info_8401); | |
3472 | RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); | |
3473 | } | |
3474 | ||
beb1fe18 | 3475 | static void rtl_hw_start_8105e_1(struct rtl8169_private *tp) |
5a5e4443 HW |
3476 | { |
3477 | static const struct ephy_info e_info_8105e_1[] = { | |
3478 | { 0x07, 0, 0x4000 }, | |
3479 | { 0x19, 0, 0x0200 }, | |
3480 | { 0x19, 0, 0x0020 }, | |
3481 | { 0x1e, 0, 0x2000 }, | |
3482 | { 0x03, 0, 0x0001 }, | |
3483 | { 0x19, 0, 0x0100 }, | |
3484 | { 0x19, 0, 0x0004 }, | |
3485 | { 0x0a, 0, 0x0020 } | |
3486 | }; | |
3487 | ||
cecb5fd7 | 3488 | /* Force LAN exit from ASPM if Rx/Tx are not idle */ |
1ef7286e | 3489 | RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); |
5a5e4443 | 3490 | |
cecb5fd7 | 3491 | /* Disable Early Tally Counter */ |
1ef7286e | 3492 | RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000); |
5a5e4443 | 3493 | |
1ef7286e AS |
3494 | RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); |
3495 | RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); | |
5a5e4443 | 3496 | |
1791ad50 | 3497 | rtl_ephy_init(tp, e_info_8105e_1); |
b51ecea8 | 3498 | |
c259b7f4 | 3499 | rtl_pcie_state_l2l3_disable(tp); |
5a5e4443 HW |
3500 | } |
3501 | ||
beb1fe18 | 3502 | static void rtl_hw_start_8105e_2(struct rtl8169_private *tp) |
5a5e4443 | 3503 | { |
beb1fe18 | 3504 | rtl_hw_start_8105e_1(tp); |
fdf6fc06 | 3505 | rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000); |
5a5e4443 HW |
3506 | } |
3507 | ||
7e18dca1 HW |
3508 | static void rtl_hw_start_8402(struct rtl8169_private *tp) |
3509 | { | |
7e18dca1 HW |
3510 | static const struct ephy_info e_info_8402[] = { |
3511 | { 0x19, 0xffff, 0xff64 }, | |
3512 | { 0x1e, 0, 0x4000 } | |
3513 | }; | |
3514 | ||
f37658da | 3515 | rtl_set_def_aspm_entry_latency(tp); |
7e18dca1 HW |
3516 | |
3517 | /* Force LAN exit from ASPM if Rx/Tx are not idle */ | |
1ef7286e | 3518 | RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); |
7e18dca1 | 3519 | |
1ef7286e | 3520 | RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); |
7e18dca1 | 3521 | |
1791ad50 | 3522 | rtl_ephy_init(tp, e_info_8402); |
7e18dca1 | 3523 | |
6b1bd242 | 3524 | rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06); |
4e7e4621 | 3525 | rtl_reset_packet_filter(tp); |
724c6fd0 HK |
3526 | rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); |
3527 | rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); | |
54113ded | 3528 | rtl_w0w1_eri(tp, 0x0d4, 0x0e00, 0xff00); |
b51ecea8 | 3529 | |
6d7a631e HK |
3530 | /* disable EEE */ |
3531 | rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); | |
3532 | ||
c259b7f4 | 3533 | rtl_pcie_state_l2l3_disable(tp); |
a603dfe8 | 3534 | rtl_hw_aspm_clkreq_enable(tp, true); |
7e18dca1 HW |
3535 | } |
3536 | ||
5598bfe5 HW |
3537 | static void rtl_hw_start_8106(struct rtl8169_private *tp) |
3538 | { | |
0866cd15 KHF |
3539 | rtl_hw_aspm_clkreq_enable(tp, false); |
3540 | ||
5598bfe5 | 3541 | /* Force LAN exit from ASPM if Rx/Tx are not idle */ |
1ef7286e | 3542 | RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); |
5598bfe5 | 3543 | |
1ef7286e AS |
3544 | RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN); |
3545 | RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); | |
3546 | RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); | |
b51ecea8 | 3547 | |
c07c8ffc HK |
3548 | /* L0 7us, L1 32us - needed to avoid issues with link-up detection */ |
3549 | rtl_set_aspm_entry_latency(tp, 0x2f); | |
9c401864 | 3550 | |
8d46f620 HK |
3551 | rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); |
3552 | ||
6d7a631e HK |
3553 | /* disable EEE */ |
3554 | rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); | |
3555 | ||
c259b7f4 | 3556 | rtl_pcie_state_l2l3_disable(tp); |
2115d3d4 | 3557 | rtl_hw_aspm_clkreq_enable(tp, true); |
5598bfe5 HW |
3558 | } |
3559 | ||
f1bce4ad HK |
3560 | DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond) |
3561 | { | |
3562 | return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13); | |
3563 | } | |
3564 | ||
3565 | static void rtl_hw_start_8125_common(struct rtl8169_private *tp) | |
3566 | { | |
3567 | rtl_pcie_state_l2l3_disable(tp); | |
3568 | ||
3569 | RTL_W16(tp, 0x382, 0x221b); | |
3570 | RTL_W8(tp, 0x4500, 0); | |
3571 | RTL_W16(tp, 0x4800, 0); | |
3572 | ||
3573 | /* disable UPS */ | |
3574 | r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000); | |
3575 | ||
3576 | RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10); | |
3577 | ||
3578 | r8168_mac_ocp_write(tp, 0xc140, 0xffff); | |
3579 | r8168_mac_ocp_write(tp, 0xc142, 0xffff); | |
3580 | ||
3581 | r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9); | |
3582 | r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); | |
3583 | r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); | |
3584 | ||
3585 | /* disable new tx descriptor format */ | |
3586 | r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000); | |
3587 | ||
0439297b HK |
3588 | if (tp->mac_version == RTL_GIGA_MAC_VER_63) |
3589 | r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0200); | |
3590 | else | |
3591 | r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400); | |
3592 | ||
3593 | if (tp->mac_version == RTL_GIGA_MAC_VER_63) | |
3594 | r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0000); | |
3595 | else | |
3596 | r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020); | |
3597 | ||
f1bce4ad HK |
3598 | r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c); |
3599 | r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033); | |
3600 | r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040); | |
3601 | r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030); | |
3602 | r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000); | |
0439297b | 3603 | r8168_mac_ocp_modify(tp, 0xea1c, 0x0003, 0x0001); |
f1bce4ad | 3604 | r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403); |
0439297b | 3605 | r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0068); |
f1bce4ad | 3606 | r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f); |
0439297b | 3607 | |
f1bce4ad HK |
3608 | r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000); |
3609 | r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001); | |
3610 | udelay(1); | |
3611 | r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000); | |
3612 | RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030); | |
3613 | ||
3614 | r8168_mac_ocp_write(tp, 0xe098, 0xc302); | |
3615 | ||
d6836ef0 | 3616 | rtl_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10); |
f1bce4ad | 3617 | |
0439297b HK |
3618 | if (tp->mac_version == RTL_GIGA_MAC_VER_63) |
3619 | rtl8125b_config_eee_mac(tp); | |
3620 | else | |
3621 | rtl8125a_config_eee_mac(tp); | |
b3a42e3a | 3622 | |
f1bce4ad HK |
3623 | RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); |
3624 | udelay(10); | |
3625 | } | |
3626 | ||
4640338c | 3627 | static void rtl_hw_start_8125a_1(struct rtl8169_private *tp) |
f1bce4ad | 3628 | { |
4640338c | 3629 | static const struct ephy_info e_info_8125a_1[] = { |
f1bce4ad HK |
3630 | { 0x01, 0xffff, 0xa812 }, |
3631 | { 0x09, 0xffff, 0x520c }, | |
3632 | { 0x04, 0xffff, 0xd000 }, | |
3633 | { 0x0d, 0xffff, 0xf702 }, | |
3634 | { 0x0a, 0xffff, 0x8653 }, | |
3635 | { 0x06, 0xffff, 0x001e }, | |
3636 | { 0x08, 0xffff, 0x3595 }, | |
3637 | { 0x20, 0xffff, 0x9455 }, | |
3638 | { 0x21, 0xffff, 0x99ff }, | |
3639 | { 0x02, 0xffff, 0x6046 }, | |
3640 | { 0x29, 0xffff, 0xfe00 }, | |
3641 | { 0x23, 0xffff, 0xab62 }, | |
3642 | ||
3643 | { 0x41, 0xffff, 0xa80c }, | |
3644 | { 0x49, 0xffff, 0x520c }, | |
3645 | { 0x44, 0xffff, 0xd000 }, | |
3646 | { 0x4d, 0xffff, 0xf702 }, | |
3647 | { 0x4a, 0xffff, 0x8653 }, | |
3648 | { 0x46, 0xffff, 0x001e }, | |
3649 | { 0x48, 0xffff, 0x3595 }, | |
3650 | { 0x60, 0xffff, 0x9455 }, | |
3651 | { 0x61, 0xffff, 0x99ff }, | |
3652 | { 0x42, 0xffff, 0x6046 }, | |
3653 | { 0x69, 0xffff, 0xfe00 }, | |
3654 | { 0x63, 0xffff, 0xab62 }, | |
3655 | }; | |
3656 | ||
3657 | rtl_set_def_aspm_entry_latency(tp); | |
3658 | ||
3659 | /* disable aspm and clock request before access ephy */ | |
3660 | rtl_hw_aspm_clkreq_enable(tp, false); | |
4640338c | 3661 | rtl_ephy_init(tp, e_info_8125a_1); |
f1bce4ad HK |
3662 | |
3663 | rtl_hw_start_8125_common(tp); | |
3fc364c0 | 3664 | rtl_hw_aspm_clkreq_enable(tp, true); |
f1bce4ad HK |
3665 | } |
3666 | ||
4640338c | 3667 | static void rtl_hw_start_8125a_2(struct rtl8169_private *tp) |
f1bce4ad | 3668 | { |
4640338c | 3669 | static const struct ephy_info e_info_8125a_2[] = { |
f1bce4ad HK |
3670 | { 0x04, 0xffff, 0xd000 }, |
3671 | { 0x0a, 0xffff, 0x8653 }, | |
3672 | { 0x23, 0xffff, 0xab66 }, | |
3673 | { 0x20, 0xffff, 0x9455 }, | |
3674 | { 0x21, 0xffff, 0x99ff }, | |
3675 | { 0x29, 0xffff, 0xfe04 }, | |
3676 | ||
3677 | { 0x44, 0xffff, 0xd000 }, | |
3678 | { 0x4a, 0xffff, 0x8653 }, | |
3679 | { 0x63, 0xffff, 0xab66 }, | |
3680 | { 0x60, 0xffff, 0x9455 }, | |
3681 | { 0x61, 0xffff, 0x99ff }, | |
3682 | { 0x69, 0xffff, 0xfe04 }, | |
3683 | }; | |
3684 | ||
3685 | rtl_set_def_aspm_entry_latency(tp); | |
3686 | ||
3687 | /* disable aspm and clock request before access ephy */ | |
3688 | rtl_hw_aspm_clkreq_enable(tp, false); | |
4640338c | 3689 | rtl_ephy_init(tp, e_info_8125a_2); |
f1bce4ad HK |
3690 | |
3691 | rtl_hw_start_8125_common(tp); | |
3fc364c0 | 3692 | rtl_hw_aspm_clkreq_enable(tp, true); |
f1bce4ad HK |
3693 | } |
3694 | ||
0439297b HK |
3695 | static void rtl_hw_start_8125b(struct rtl8169_private *tp) |
3696 | { | |
3697 | static const struct ephy_info e_info_8125b[] = { | |
3698 | { 0x0b, 0xffff, 0xa908 }, | |
3699 | { 0x1e, 0xffff, 0x20eb }, | |
3700 | { 0x4b, 0xffff, 0xa908 }, | |
3701 | { 0x5e, 0xffff, 0x20eb }, | |
3702 | { 0x22, 0x0030, 0x0020 }, | |
3703 | { 0x62, 0x0030, 0x0020 }, | |
3704 | }; | |
3705 | ||
3706 | rtl_set_def_aspm_entry_latency(tp); | |
3707 | rtl_hw_aspm_clkreq_enable(tp, false); | |
3708 | ||
3709 | rtl_ephy_init(tp, e_info_8125b); | |
3710 | rtl_hw_start_8125_common(tp); | |
3711 | ||
3712 | rtl_hw_aspm_clkreq_enable(tp, true); | |
3713 | } | |
3714 | ||
8344ffff HK |
3715 | static void rtl_hw_config(struct rtl8169_private *tp) |
3716 | { | |
3717 | static const rtl_generic_fct hw_configs[] = { | |
3718 | [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1, | |
3719 | [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3, | |
3720 | [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2, | |
3721 | [RTL_GIGA_MAC_VER_10] = NULL, | |
94b5ff74 HK |
3722 | [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168b, |
3723 | [RTL_GIGA_MAC_VER_12] = rtl_hw_start_8168b, | |
8344ffff | 3724 | [RTL_GIGA_MAC_VER_13] = NULL, |
cdafdc29 | 3725 | [RTL_GIGA_MAC_VER_14] = rtl_hw_start_8401, |
8344ffff | 3726 | [RTL_GIGA_MAC_VER_16] = NULL, |
94b5ff74 | 3727 | [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168b, |
8344ffff HK |
3728 | [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1, |
3729 | [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1, | |
3730 | [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2, | |
96ef6928 | 3731 | [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_2, |
8344ffff HK |
3732 | [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4, |
3733 | [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2, | |
3734 | [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3, | |
3735 | [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d, | |
3736 | [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d, | |
3737 | [RTL_GIGA_MAC_VER_27] = rtl_hw_start_8168d, | |
3738 | [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4, | |
3739 | [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1, | |
3740 | [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2, | |
0a413e6b | 3741 | [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168d, |
8344ffff HK |
3742 | [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1, |
3743 | [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1, | |
3744 | [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2, | |
3745 | [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1, | |
3746 | [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1, | |
3747 | [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402, | |
3748 | [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411, | |
3749 | [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106, | |
3750 | [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1, | |
3751 | [RTL_GIGA_MAC_VER_41] = rtl_hw_start_8168g_1, | |
3752 | [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2, | |
3753 | [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2, | |
3754 | [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2, | |
3755 | [RTL_GIGA_MAC_VER_45] = rtl_hw_start_8168h_1, | |
3756 | [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1, | |
3757 | [RTL_GIGA_MAC_VER_47] = rtl_hw_start_8168h_1, | |
3758 | [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1, | |
3759 | [RTL_GIGA_MAC_VER_49] = rtl_hw_start_8168ep_1, | |
3760 | [RTL_GIGA_MAC_VER_50] = rtl_hw_start_8168ep_2, | |
3761 | [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3, | |
1287723a | 3762 | [RTL_GIGA_MAC_VER_52] = rtl_hw_start_8117, |
e6d6ca6e | 3763 | [RTL_GIGA_MAC_VER_53] = rtl_hw_start_8117, |
4640338c HK |
3764 | [RTL_GIGA_MAC_VER_60] = rtl_hw_start_8125a_1, |
3765 | [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125a_2, | |
0439297b | 3766 | [RTL_GIGA_MAC_VER_63] = rtl_hw_start_8125b, |
8344ffff HK |
3767 | }; |
3768 | ||
3769 | if (hw_configs[tp->mac_version]) | |
3770 | hw_configs[tp->mac_version](tp); | |
3771 | } | |
3772 | ||
f1bce4ad HK |
3773 | static void rtl_hw_start_8125(struct rtl8169_private *tp) |
3774 | { | |
3775 | int i; | |
3776 | ||
3777 | /* disable interrupt coalescing */ | |
3778 | for (i = 0xa00; i < 0xb00; i += 4) | |
3779 | RTL_W32(tp, i, 0); | |
3780 | ||
3781 | rtl_hw_config(tp); | |
3782 | } | |
3783 | ||
8344ffff | 3784 | static void rtl_hw_start_8168(struct rtl8169_private *tp) |
07ce4064 | 3785 | { |
272b2265 HK |
3786 | if (rtl_is_8168evl_up(tp)) |
3787 | RTL_W8(tp, MaxTxPacketSize, EarlySize); | |
3788 | else | |
3789 | RTL_W8(tp, MaxTxPacketSize, TxPacketMax); | |
1a964649 | 3790 | |
8344ffff | 3791 | rtl_hw_config(tp); |
bcf2b868 HK |
3792 | |
3793 | /* disable interrupt coalescing */ | |
3794 | RTL_W16(tp, IntrMitigate, 0x0000); | |
1da177e4 LT |
3795 | } |
3796 | ||
6c19156e HK |
3797 | static void rtl_hw_start_8169(struct rtl8169_private *tp) |
3798 | { | |
6c19156e HK |
3799 | RTL_W8(tp, EarlyTxThres, NoEarlyTx); |
3800 | ||
3801 | tp->cp_cmd |= PCIMulRW; | |
3802 | ||
3803 | if (tp->mac_version == RTL_GIGA_MAC_VER_02 || | |
09e65335 HK |
3804 | tp->mac_version == RTL_GIGA_MAC_VER_03) |
3805 | tp->cp_cmd |= EnAnaPLL; | |
6c19156e HK |
3806 | |
3807 | RTL_W16(tp, CPlusCmd, tp->cp_cmd); | |
3808 | ||
ef891284 | 3809 | rtl8169_set_magic_reg(tp); |
6c19156e | 3810 | |
bcf2b868 HK |
3811 | /* disable interrupt coalescing */ |
3812 | RTL_W16(tp, IntrMitigate, 0x0000); | |
6c19156e HK |
3813 | } |
3814 | ||
3815 | static void rtl_hw_start(struct rtl8169_private *tp) | |
3816 | { | |
3817 | rtl_unlock_config_regs(tp); | |
3818 | ||
6c19156e HK |
3819 | RTL_W16(tp, CPlusCmd, tp->cp_cmd); |
3820 | ||
3821 | if (tp->mac_version <= RTL_GIGA_MAC_VER_06) | |
3822 | rtl_hw_start_8169(tp); | |
f1bce4ad HK |
3823 | else if (rtl_is_8125(tp)) |
3824 | rtl_hw_start_8125(tp); | |
6c19156e HK |
3825 | else |
3826 | rtl_hw_start_8168(tp); | |
3827 | ||
4b33433e | 3828 | rtl_enable_exit_l1(tp); |
6c19156e HK |
3829 | rtl_set_rx_max_size(tp); |
3830 | rtl_set_rx_tx_desc_registers(tp); | |
3831 | rtl_lock_config_regs(tp); | |
3832 | ||
9db0ac57 | 3833 | rtl_jumbo_config(tp); |
4ebcb113 | 3834 | |
6c19156e | 3835 | /* Initially a 10 us delay. Turned it into a PCI commit. - FR */ |
711463f8 HK |
3836 | rtl_pci_commit(tp); |
3837 | ||
6c19156e HK |
3838 | RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb); |
3839 | rtl_init_rxcfg(tp); | |
3840 | rtl_set_tx_config_registers(tp); | |
10478283 | 3841 | rtl_set_rx_config_features(tp, tp->dev->features); |
6c19156e | 3842 | rtl_set_rx_mode(tp->dev); |
6c19156e HK |
3843 | rtl_irq_enable(tp); |
3844 | } | |
3845 | ||
1da177e4 LT |
3846 | static int rtl8169_change_mtu(struct net_device *dev, int new_mtu) |
3847 | { | |
d58d46b5 FR |
3848 | struct rtl8169_private *tp = netdev_priv(dev); |
3849 | ||
1da177e4 | 3850 | dev->mtu = new_mtu; |
350fb32a | 3851 | netdev_update_features(dev); |
9db0ac57 | 3852 | rtl_jumbo_config(tp); |
350fb32a | 3853 | |
0439297b HK |
3854 | switch (tp->mac_version) { |
3855 | case RTL_GIGA_MAC_VER_61: | |
3856 | case RTL_GIGA_MAC_VER_63: | |
3857 | rtl8125_set_eee_txidle_timer(tp); | |
3858 | break; | |
3859 | default: | |
3860 | break; | |
3861 | } | |
3862 | ||
323bb685 | 3863 | return 0; |
1da177e4 LT |
3864 | } |
3865 | ||
e2e5fb8d | 3866 | static void rtl8169_mark_to_asic(struct RxDesc *desc) |
1da177e4 LT |
3867 | { |
3868 | u32 eor = le32_to_cpu(desc->opts1) & RingEnd; | |
3869 | ||
047521d7 | 3870 | desc->opts2 = 0; |
a0750138 AD |
3871 | /* Force memory writes to complete before releasing descriptor */ |
3872 | dma_wmb(); | |
e2e5fb8d | 3873 | WRITE_ONCE(desc->opts1, cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE)); |
1da177e4 LT |
3874 | } |
3875 | ||
32879f00 HK |
3876 | static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp, |
3877 | struct RxDesc *desc) | |
1da177e4 | 3878 | { |
1e1205b7 | 3879 | struct device *d = tp_to_dev(tp); |
d3b404c2 | 3880 | int node = dev_to_node(d); |
32879f00 HK |
3881 | dma_addr_t mapping; |
3882 | struct page *data; | |
1da177e4 | 3883 | |
32879f00 | 3884 | data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE)); |
6f0333b8 ED |
3885 | if (!data) |
3886 | return NULL; | |
e9f63f30 | 3887 | |
32879f00 | 3888 | mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); |
d827d86b | 3889 | if (unlikely(dma_mapping_error(d, mapping))) { |
93882c6f | 3890 | netdev_err(tp->dev, "Failed to map RX DMA!\n"); |
32879f00 HK |
3891 | __free_pages(data, get_order(R8169_RX_BUF_SIZE)); |
3892 | return NULL; | |
d827d86b | 3893 | } |
1da177e4 | 3894 | |
d731af78 HK |
3895 | desc->addr = cpu_to_le64(mapping); |
3896 | rtl8169_mark_to_asic(desc); | |
3eafe507 | 3897 | |
32879f00 | 3898 | return data; |
1da177e4 LT |
3899 | } |
3900 | ||
3901 | static void rtl8169_rx_clear(struct rtl8169_private *tp) | |
3902 | { | |
ed22a8ff | 3903 | int i; |
1da177e4 | 3904 | |
eb2e7f09 HK |
3905 | for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) { |
3906 | dma_unmap_page(tp_to_dev(tp), | |
3907 | le64_to_cpu(tp->RxDescArray[i].addr), | |
3908 | R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); | |
3909 | __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE)); | |
3910 | tp->Rx_databuff[i] = NULL; | |
9d3679fe HK |
3911 | tp->RxDescArray[i].addr = 0; |
3912 | tp->RxDescArray[i].opts1 = 0; | |
1da177e4 LT |
3913 | } |
3914 | } | |
3915 | ||
0ecbe1ca SG |
3916 | static int rtl8169_rx_fill(struct rtl8169_private *tp) |
3917 | { | |
ed22a8ff | 3918 | int i; |
1da177e4 | 3919 | |
0ecbe1ca | 3920 | for (i = 0; i < NUM_RX_DESC; i++) { |
32879f00 | 3921 | struct page *data; |
4ae47c2d | 3922 | |
0ecbe1ca | 3923 | data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i); |
6f0333b8 | 3924 | if (!data) { |
e4b5c7a5 HK |
3925 | rtl8169_rx_clear(tp); |
3926 | return -ENOMEM; | |
6f0333b8 ED |
3927 | } |
3928 | tp->Rx_databuff[i] = data; | |
1da177e4 | 3929 | } |
1da177e4 | 3930 | |
2ac1fa43 HK |
3931 | /* mark as last descriptor in the ring */ |
3932 | tp->RxDescArray[NUM_RX_DESC - 1].opts1 |= cpu_to_le32(RingEnd); | |
0ecbe1ca | 3933 | |
e4b5c7a5 | 3934 | return 0; |
1da177e4 LT |
3935 | } |
3936 | ||
b1127e64 | 3937 | static int rtl8169_init_ring(struct rtl8169_private *tp) |
1da177e4 | 3938 | { |
1da177e4 LT |
3939 | rtl8169_init_ring_indexes(tp); |
3940 | ||
b1127e64 HK |
3941 | memset(tp->tx_skb, 0, sizeof(tp->tx_skb)); |
3942 | memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff)); | |
1da177e4 | 3943 | |
0ecbe1ca | 3944 | return rtl8169_rx_fill(tp); |
1da177e4 LT |
3945 | } |
3946 | ||
22d352c5 | 3947 | static void rtl8169_unmap_tx_skb(struct rtl8169_private *tp, unsigned int entry) |
1da177e4 | 3948 | { |
22d352c5 HK |
3949 | struct ring_info *tx_skb = tp->tx_skb + entry; |
3950 | struct TxDesc *desc = tp->TxDescArray + entry; | |
1da177e4 | 3951 | |
22d352c5 HK |
3952 | dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr), tx_skb->len, |
3953 | DMA_TO_DEVICE); | |
6a41f2b2 HK |
3954 | memset(desc, 0, sizeof(*desc)); |
3955 | memset(tx_skb, 0, sizeof(*tx_skb)); | |
1da177e4 LT |
3956 | } |
3957 | ||
3eafe507 SG |
3958 | static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start, |
3959 | unsigned int n) | |
1da177e4 LT |
3960 | { |
3961 | unsigned int i; | |
3962 | ||
3eafe507 SG |
3963 | for (i = 0; i < n; i++) { |
3964 | unsigned int entry = (start + i) % NUM_TX_DESC; | |
1da177e4 LT |
3965 | struct ring_info *tx_skb = tp->tx_skb + entry; |
3966 | unsigned int len = tx_skb->len; | |
3967 | ||
3968 | if (len) { | |
3969 | struct sk_buff *skb = tx_skb->skb; | |
3970 | ||
22d352c5 | 3971 | rtl8169_unmap_tx_skb(tp, entry); |
6a41f2b2 | 3972 | if (skb) |
7a4b813c | 3973 | dev_consume_skb_any(skb); |
1da177e4 LT |
3974 | } |
3975 | } | |
3eafe507 SG |
3976 | } |
3977 | ||
3978 | static void rtl8169_tx_clear(struct rtl8169_private *tp) | |
3979 | { | |
3980 | rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC); | |
d92060bc | 3981 | netdev_reset_queue(tp->dev); |
1da177e4 LT |
3982 | } |
3983 | ||
0c28a63a | 3984 | static void rtl8169_cleanup(struct rtl8169_private *tp, bool going_down) |
bac75d85 | 3985 | { |
0c28a63a HK |
3986 | napi_disable(&tp->napi); |
3987 | ||
bac75d85 | 3988 | /* Give a racing hard_start_xmit a few cycles to complete. */ |
7190aeec | 3989 | synchronize_net(); |
bac75d85 HK |
3990 | |
3991 | /* Disable interrupts */ | |
3992 | rtl8169_irq_mask_and_ack(tp); | |
3993 | ||
3994 | rtl_rx_close(tp); | |
3995 | ||
12006848 HK |
3996 | if (going_down && tp->dev->wol_enabled) |
3997 | goto no_reset; | |
3998 | ||
bac75d85 HK |
3999 | switch (tp->mac_version) { |
4000 | case RTL_GIGA_MAC_VER_27: | |
4001 | case RTL_GIGA_MAC_VER_28: | |
4002 | case RTL_GIGA_MAC_VER_31: | |
4003 | rtl_loop_wait_low(tp, &rtl_npq_cond, 20, 2000); | |
4004 | break; | |
4005 | case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38: | |
4006 | RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); | |
4007 | rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666); | |
4008 | break; | |
0439297b | 4009 | case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: |
bac75d85 HK |
4010 | rtl_enable_rxdvgate(tp); |
4011 | fsleep(2000); | |
4012 | break; | |
4013 | default: | |
4014 | RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); | |
4015 | fsleep(100); | |
4016 | break; | |
4017 | } | |
4018 | ||
4019 | rtl_hw_reset(tp); | |
12006848 | 4020 | no_reset: |
bac75d85 HK |
4021 | rtl8169_tx_clear(tp); |
4022 | rtl8169_init_ring_indexes(tp); | |
4023 | } | |
4024 | ||
4422bcd4 | 4025 | static void rtl_reset_work(struct rtl8169_private *tp) |
1da177e4 | 4026 | { |
56de414c | 4027 | int i; |
1da177e4 | 4028 | |
476c4f5d | 4029 | netif_stop_queue(tp->dev); |
1da177e4 | 4030 | |
0c28a63a | 4031 | rtl8169_cleanup(tp, false); |
c7c2c39b | 4032 | |
56de414c | 4033 | for (i = 0; i < NUM_RX_DESC; i++) |
1d0254dd | 4034 | rtl8169_mark_to_asic(tp->RxDescArray + i); |
56de414c | 4035 | |
da78dbff | 4036 | napi_enable(&tp->napi); |
61cb532d | 4037 | rtl_hw_start(tp); |
1da177e4 LT |
4038 | } |
4039 | ||
0290bd29 | 4040 | static void rtl8169_tx_timeout(struct net_device *dev, unsigned int txqueue) |
1da177e4 | 4041 | { |
da78dbff FR |
4042 | struct rtl8169_private *tp = netdev_priv(dev); |
4043 | ||
4044 | rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); | |
1da177e4 LT |
4045 | } |
4046 | ||
b8447abc HK |
4047 | static int rtl8169_tx_map(struct rtl8169_private *tp, const u32 *opts, u32 len, |
4048 | void *addr, unsigned int entry, bool desc_own) | |
734c1409 | 4049 | { |
b8447abc HK |
4050 | struct TxDesc *txd = tp->TxDescArray + entry; |
4051 | struct device *d = tp_to_dev(tp); | |
4052 | dma_addr_t mapping; | |
4053 | u32 opts1; | |
4054 | int ret; | |
4055 | ||
4056 | mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE); | |
4057 | ret = dma_mapping_error(d, mapping); | |
4058 | if (unlikely(ret)) { | |
4059 | if (net_ratelimit()) | |
93882c6f | 4060 | netdev_err(tp->dev, "Failed to map TX data!\n"); |
b8447abc HK |
4061 | return ret; |
4062 | } | |
4063 | ||
4064 | txd->addr = cpu_to_le64(mapping); | |
4065 | txd->opts2 = cpu_to_le32(opts[1]); | |
734c1409 | 4066 | |
b8447abc | 4067 | opts1 = opts[0] | len; |
734c1409 | 4068 | if (entry == NUM_TX_DESC - 1) |
b8447abc HK |
4069 | opts1 |= RingEnd; |
4070 | if (desc_own) | |
4071 | opts1 |= DescOwn; | |
4072 | txd->opts1 = cpu_to_le32(opts1); | |
734c1409 | 4073 | |
b8447abc HK |
4074 | tp->tx_skb[entry].len = len; |
4075 | ||
4076 | return 0; | |
734c1409 HK |
4077 | } |
4078 | ||
1da177e4 | 4079 | static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb, |
b8447abc | 4080 | const u32 *opts, unsigned int entry) |
1da177e4 LT |
4081 | { |
4082 | struct skb_shared_info *info = skb_shinfo(skb); | |
b8447abc | 4083 | unsigned int cur_frag; |
1da177e4 | 4084 | |
1da177e4 | 4085 | for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) { |
9e903e08 | 4086 | const skb_frag_t *frag = info->frags + cur_frag; |
b8447abc HK |
4087 | void *addr = skb_frag_address(frag); |
4088 | u32 len = skb_frag_size(frag); | |
1da177e4 LT |
4089 | |
4090 | entry = (entry + 1) % NUM_TX_DESC; | |
4091 | ||
b8447abc | 4092 | if (unlikely(rtl8169_tx_map(tp, opts, len, addr, entry, true))) |
3eafe507 | 4093 | goto err_out; |
1da177e4 LT |
4094 | } |
4095 | ||
9020845f | 4096 | return 0; |
3eafe507 SG |
4097 | |
4098 | err_out: | |
4099 | rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag); | |
4100 | return -EIO; | |
1da177e4 LT |
4101 | } |
4102 | ||
8d520b4d HK |
4103 | static bool rtl_skb_is_udp(struct sk_buff *skb) |
4104 | { | |
4105 | int no = skb_network_offset(skb); | |
4106 | struct ipv6hdr *i6h, _i6h; | |
4107 | struct iphdr *ih, _ih; | |
4108 | ||
4109 | switch (vlan_get_protocol(skb)) { | |
4110 | case htons(ETH_P_IP): | |
4111 | ih = skb_header_pointer(skb, no, sizeof(_ih), &_ih); | |
4112 | return ih && ih->protocol == IPPROTO_UDP; | |
4113 | case htons(ETH_P_IPV6): | |
4114 | i6h = skb_header_pointer(skb, no, sizeof(_i6h), &_i6h); | |
4115 | return i6h && i6h->nexthdr == IPPROTO_UDP; | |
4116 | default: | |
4117 | return false; | |
4118 | } | |
4119 | } | |
4120 | ||
4121 | #define RTL_MIN_PATCH_LEN 47 | |
4122 | ||
4123 | /* see rtl8125_get_patch_pad_len() in r8125 vendor driver */ | |
4124 | static unsigned int rtl8125_quirk_udp_padto(struct rtl8169_private *tp, | |
4125 | struct sk_buff *skb) | |
b423e9ae | 4126 | { |
8d520b4d HK |
4127 | unsigned int padto = 0, len = skb->len; |
4128 | ||
4129 | if (rtl_is_8125(tp) && len < 128 + RTL_MIN_PATCH_LEN && | |
4130 | rtl_skb_is_udp(skb) && skb_transport_header_was_set(skb)) { | |
4131 | unsigned int trans_data_len = skb_tail_pointer(skb) - | |
4132 | skb_transport_header(skb); | |
4133 | ||
4134 | if (trans_data_len >= offsetof(struct udphdr, len) && | |
4135 | trans_data_len < RTL_MIN_PATCH_LEN) { | |
4136 | u16 dest = ntohs(udp_hdr(skb)->dest); | |
4137 | ||
4138 | /* dest is a standard PTP port */ | |
4139 | if (dest == 319 || dest == 320) | |
4140 | padto = len + RTL_MIN_PATCH_LEN - trans_data_len; | |
4141 | } | |
4142 | ||
4143 | if (trans_data_len < sizeof(struct udphdr)) | |
4144 | padto = max_t(unsigned int, padto, | |
4145 | len + sizeof(struct udphdr) - trans_data_len); | |
4146 | } | |
4147 | ||
4148 | return padto; | |
4149 | } | |
4150 | ||
4151 | static unsigned int rtl_quirk_packet_padto(struct rtl8169_private *tp, | |
4152 | struct sk_buff *skb) | |
4153 | { | |
4154 | unsigned int padto; | |
4155 | ||
4156 | padto = rtl8125_quirk_udp_padto(tp, skb); | |
4157 | ||
2aaf09a0 HK |
4158 | switch (tp->mac_version) { |
4159 | case RTL_GIGA_MAC_VER_34: | |
4160 | case RTL_GIGA_MAC_VER_60: | |
4161 | case RTL_GIGA_MAC_VER_61: | |
4162 | case RTL_GIGA_MAC_VER_63: | |
8d520b4d | 4163 | padto = max_t(unsigned int, padto, ETH_ZLEN); |
ffb35c67 | 4164 | break; |
2aaf09a0 | 4165 | default: |
8d520b4d | 4166 | break; |
2aaf09a0 | 4167 | } |
8d520b4d HK |
4168 | |
4169 | return padto; | |
b423e9ae | 4170 | } |
4171 | ||
87945b6d | 4172 | static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts) |
1da177e4 | 4173 | { |
350fb32a MM |
4174 | u32 mss = skb_shinfo(skb)->gso_size; |
4175 | ||
2b7b4318 FR |
4176 | if (mss) { |
4177 | opts[0] |= TD_LSO; | |
4abc3c04 | 4178 | opts[0] |= mss << TD0_MSS_SHIFT; |
5888d3fc | 4179 | } else if (skb->ip_summed == CHECKSUM_PARTIAL) { |
4180 | const struct iphdr *ip = ip_hdr(skb); | |
4181 | ||
4182 | if (ip->protocol == IPPROTO_TCP) | |
4183 | opts[0] |= TD0_IP_CS | TD0_TCP_CS; | |
4184 | else if (ip->protocol == IPPROTO_UDP) | |
4185 | opts[0] |= TD0_IP_CS | TD0_UDP_CS; | |
4186 | else | |
4187 | WARN_ON_ONCE(1); | |
4188 | } | |
5888d3fc | 4189 | } |
4190 | ||
4191 | static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp, | |
4192 | struct sk_buff *skb, u32 *opts) | |
4193 | { | |
bdfa4ed6 | 4194 | u32 transport_offset = (u32)skb_transport_offset(skb); |
0623b98b HK |
4195 | struct skb_shared_info *shinfo = skb_shinfo(skb); |
4196 | u32 mss = shinfo->gso_size; | |
5888d3fc | 4197 | |
4198 | if (mss) { | |
0623b98b | 4199 | if (shinfo->gso_type & SKB_GSO_TCPV4) { |
e974604b | 4200 | opts[0] |= TD1_GTSENV4; |
0623b98b | 4201 | } else if (shinfo->gso_type & SKB_GSO_TCPV6) { |
8b19c68c | 4202 | if (skb_cow_head(skb, 0)) |
e974604b | 4203 | return false; |
4204 | ||
8b19c68c | 4205 | tcp_v6_gso_csum_prep(skb); |
e974604b | 4206 | opts[0] |= TD1_GTSENV6; |
0623b98b | 4207 | } else { |
e974604b | 4208 | WARN_ON_ONCE(1); |
e974604b | 4209 | } |
4210 | ||
bdfa4ed6 | 4211 | opts[0] |= transport_offset << GTTCPHO_SHIFT; |
4abc3c04 | 4212 | opts[1] |= mss << TD1_MSS_SHIFT; |
2b7b4318 | 4213 | } else if (skb->ip_summed == CHECKSUM_PARTIAL) { |
e974604b | 4214 | u8 ip_protocol; |
1da177e4 | 4215 | |
4ff36466 | 4216 | switch (vlan_get_protocol(skb)) { |
e974604b | 4217 | case htons(ETH_P_IP): |
4218 | opts[1] |= TD1_IPv4_CS; | |
4219 | ip_protocol = ip_hdr(skb)->protocol; | |
4220 | break; | |
4221 | ||
4222 | case htons(ETH_P_IPV6): | |
4223 | opts[1] |= TD1_IPv6_CS; | |
4224 | ip_protocol = ipv6_hdr(skb)->nexthdr; | |
4225 | break; | |
4226 | ||
4227 | default: | |
4228 | ip_protocol = IPPROTO_RAW; | |
4229 | break; | |
4230 | } | |
4231 | ||
4232 | if (ip_protocol == IPPROTO_TCP) | |
4233 | opts[1] |= TD1_TCP_CS; | |
4234 | else if (ip_protocol == IPPROTO_UDP) | |
4235 | opts[1] |= TD1_UDP_CS; | |
2b7b4318 FR |
4236 | else |
4237 | WARN_ON_ONCE(1); | |
e974604b | 4238 | |
4239 | opts[1] |= transport_offset << TCPHO_SHIFT; | |
b423e9ae | 4240 | } else { |
8d520b4d HK |
4241 | unsigned int padto = rtl_quirk_packet_padto(tp, skb); |
4242 | ||
4243 | /* skb_padto would free the skb on error */ | |
4244 | return !__skb_put_padto(skb, padto, false); | |
1da177e4 | 4245 | } |
5888d3fc | 4246 | |
b423e9ae | 4247 | return true; |
1da177e4 LT |
4248 | } |
4249 | ||
83c317d7 | 4250 | static bool rtl_tx_slots_avail(struct rtl8169_private *tp) |
76085c9e | 4251 | { |
95f3c545 HK |
4252 | unsigned int slots_avail = READ_ONCE(tp->dirty_tx) + NUM_TX_DESC |
4253 | - READ_ONCE(tp->cur_tx); | |
76085c9e HK |
4254 | |
4255 | /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */ | |
83c317d7 | 4256 | return slots_avail > MAX_SKB_FRAGS; |
76085c9e HK |
4257 | } |
4258 | ||
87945b6d HK |
4259 | /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */ |
4260 | static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp) | |
4261 | { | |
4262 | switch (tp->mac_version) { | |
4263 | case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: | |
4264 | case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: | |
4265 | return false; | |
4266 | default: | |
4267 | return true; | |
4268 | } | |
4269 | } | |
4270 | ||
f1bce4ad HK |
4271 | static void rtl8169_doorbell(struct rtl8169_private *tp) |
4272 | { | |
4273 | if (rtl_is_8125(tp)) | |
4274 | RTL_W16(tp, TxPoll_8125, BIT(0)); | |
4275 | else | |
4276 | RTL_W8(tp, TxPoll, NPQ); | |
4277 | } | |
4278 | ||
61357325 SH |
4279 | static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb, |
4280 | struct net_device *dev) | |
1da177e4 | 4281 | { |
9020845f | 4282 | unsigned int frags = skb_shinfo(skb)->nr_frags; |
1da177e4 | 4283 | struct rtl8169_private *tp = netdev_priv(dev); |
3eafe507 | 4284 | unsigned int entry = tp->cur_tx % NUM_TX_DESC; |
b8447abc HK |
4285 | struct TxDesc *txd_first, *txd_last; |
4286 | bool stop_queue, door_bell; | |
4287 | u32 opts[2]; | |
4288 | ||
83c317d7 | 4289 | if (unlikely(!rtl_tx_slots_avail(tp))) { |
93882c6f HK |
4290 | if (net_ratelimit()) |
4291 | netdev_err(dev, "BUG! Tx Ring full when queue awake!\n"); | |
3eafe507 | 4292 | goto err_stop_0; |
1da177e4 LT |
4293 | } |
4294 | ||
355f948a | 4295 | opts[1] = rtl8169_tx_vlan_tag(skb); |
b8447abc | 4296 | opts[0] = 0; |
b423e9ae | 4297 | |
b8447abc | 4298 | if (!rtl_chip_supports_csum_v2(tp)) |
87945b6d | 4299 | rtl8169_tso_csum_v1(skb, opts); |
b8447abc | 4300 | else if (!rtl8169_tso_csum_v2(tp, skb, opts)) |
3eafe507 SG |
4301 | goto err_dma_0; |
4302 | ||
b8447abc HK |
4303 | if (unlikely(rtl8169_tx_map(tp, opts, skb_headlen(skb), skb->data, |
4304 | entry, false))) | |
4305 | goto err_dma_0; | |
1da177e4 | 4306 | |
bd4bdeb4 HK |
4307 | txd_first = tp->TxDescArray + entry; |
4308 | ||
b8447abc HK |
4309 | if (frags) { |
4310 | if (rtl8169_xmit_frags(tp, skb, opts, entry)) | |
9020845f | 4311 | goto err_dma_1; |
b8447abc | 4312 | entry = (entry + frags) % NUM_TX_DESC; |
1da177e4 LT |
4313 | } |
4314 | ||
b8447abc HK |
4315 | txd_last = tp->TxDescArray + entry; |
4316 | txd_last->opts1 |= cpu_to_le32(LastFrag); | |
4317 | tp->tx_skb[entry].skb = skb; | |
2b7b4318 | 4318 | |
5047fb5d RC |
4319 | skb_tx_timestamp(skb); |
4320 | ||
a0750138 AD |
4321 | /* Force memory writes to complete before releasing descriptor */ |
4322 | dma_wmb(); | |
1da177e4 | 4323 | |
ef143585 HK |
4324 | door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more()); |
4325 | ||
b8447abc | 4326 | txd_first->opts1 |= cpu_to_le32(DescOwn | FirstFrag); |
1da177e4 | 4327 | |
794867ee HK |
4328 | /* rtl_tx needs to see descriptor changes before updated tp->cur_tx */ |
4329 | smp_wmb(); | |
1da177e4 | 4330 | |
41294e6a | 4331 | WRITE_ONCE(tp->cur_tx, tp->cur_tx + frags + 1); |
a0750138 | 4332 | |
83c317d7 | 4333 | stop_queue = !rtl_tx_slots_avail(tp); |
ef143585 | 4334 | if (unlikely(stop_queue)) { |
0255d592 HK |
4335 | /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must |
4336 | * not miss a ring update when it notices a stopped queue. | |
4337 | */ | |
4338 | smp_wmb(); | |
4339 | netif_stop_queue(dev); | |
ae1f23fb FR |
4340 | /* Sync with rtl_tx: |
4341 | * - publish queue status and cur_tx ring index (write barrier) | |
4342 | * - refresh dirty_tx ring index (read barrier). | |
4343 | * May the current thread have a pessimistic view of the ring | |
4344 | * status and forget to wake up queue, a racing rtl_tx thread | |
4345 | * can't. | |
4346 | */ | |
41294e6a | 4347 | smp_mb__after_atomic(); |
83c317d7 | 4348 | if (rtl_tx_slots_avail(tp)) |
601ed4d6 | 4349 | netif_start_queue(dev); |
41294e6a | 4350 | door_bell = true; |
1da177e4 LT |
4351 | } |
4352 | ||
41294e6a HK |
4353 | if (door_bell) |
4354 | rtl8169_doorbell(tp); | |
4355 | ||
61357325 | 4356 | return NETDEV_TX_OK; |
1da177e4 | 4357 | |
3eafe507 | 4358 | err_dma_1: |
22d352c5 | 4359 | rtl8169_unmap_tx_skb(tp, entry); |
3eafe507 | 4360 | err_dma_0: |
989c9ba1 | 4361 | dev_kfree_skb_any(skb); |
3eafe507 SG |
4362 | dev->stats.tx_dropped++; |
4363 | return NETDEV_TX_OK; | |
4364 | ||
4365 | err_stop_0: | |
1da177e4 | 4366 | netif_stop_queue(dev); |
cebf8cc7 | 4367 | dev->stats.tx_dropped++; |
61357325 | 4368 | return NETDEV_TX_BUSY; |
1da177e4 LT |
4369 | } |
4370 | ||
773235f4 HK |
4371 | static unsigned int rtl_last_frag_len(struct sk_buff *skb) |
4372 | { | |
4373 | struct skb_shared_info *info = skb_shinfo(skb); | |
4374 | unsigned int nr_frags = info->nr_frags; | |
4375 | ||
4376 | if (!nr_frags) | |
4377 | return UINT_MAX; | |
4378 | ||
4379 | return skb_frag_size(info->frags + nr_frags - 1); | |
4380 | } | |
4381 | ||
4382 | /* Workaround for hw issues with TSO on RTL8168evl */ | |
4383 | static netdev_features_t rtl8168evl_fix_tso(struct sk_buff *skb, | |
4384 | netdev_features_t features) | |
4385 | { | |
4386 | /* IPv4 header has options field */ | |
4387 | if (vlan_get_protocol(skb) == htons(ETH_P_IP) && | |
4388 | ip_hdrlen(skb) > sizeof(struct iphdr)) | |
4389 | features &= ~NETIF_F_ALL_TSO; | |
4390 | ||
4391 | /* IPv4 TCP header has options field */ | |
4392 | else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4 && | |
4393 | tcp_hdrlen(skb) > sizeof(struct tcphdr)) | |
4394 | features &= ~NETIF_F_ALL_TSO; | |
4395 | ||
4396 | else if (rtl_last_frag_len(skb) <= 6) | |
4397 | features &= ~NETIF_F_ALL_TSO; | |
4398 | ||
4399 | return features; | |
4400 | } | |
4401 | ||
e64e0c89 HK |
4402 | static netdev_features_t rtl8169_features_check(struct sk_buff *skb, |
4403 | struct net_device *dev, | |
4404 | netdev_features_t features) | |
4405 | { | |
4406 | int transport_offset = skb_transport_offset(skb); | |
4407 | struct rtl8169_private *tp = netdev_priv(dev); | |
4408 | ||
4409 | if (skb_is_gso(skb)) { | |
773235f4 HK |
4410 | if (tp->mac_version == RTL_GIGA_MAC_VER_34) |
4411 | features = rtl8168evl_fix_tso(skb, features); | |
4412 | ||
e64e0c89 HK |
4413 | if (transport_offset > GTTCPHO_MAX && |
4414 | rtl_chip_supports_csum_v2(tp)) | |
4415 | features &= ~NETIF_F_ALL_TSO; | |
4416 | } else if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
847f0a2b HK |
4417 | /* work around hw bug on some chip versions */ |
4418 | if (skb->len < ETH_ZLEN) | |
4419 | features &= ~NETIF_F_CSUM_MASK; | |
e64e0c89 | 4420 | |
8d520b4d HK |
4421 | if (rtl_quirk_packet_padto(tp, skb)) |
4422 | features &= ~NETIF_F_CSUM_MASK; | |
e64e0c89 HK |
4423 | |
4424 | if (transport_offset > TCPHO_MAX && | |
4425 | rtl_chip_supports_csum_v2(tp)) | |
4426 | features &= ~NETIF_F_CSUM_MASK; | |
4427 | } | |
4428 | ||
4429 | return vlan_features_check(skb, features); | |
4430 | } | |
4431 | ||
1da177e4 LT |
4432 | static void rtl8169_pcierr_interrupt(struct net_device *dev) |
4433 | { | |
4434 | struct rtl8169_private *tp = netdev_priv(dev); | |
4435 | struct pci_dev *pdev = tp->pci_dev; | |
2864a883 HK |
4436 | int pci_status_errs; |
4437 | u16 pci_cmd; | |
1da177e4 LT |
4438 | |
4439 | pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); | |
1da177e4 | 4440 | |
2864a883 HK |
4441 | pci_status_errs = pci_status_get_and_clear_errors(pdev); |
4442 | ||
93882c6f HK |
4443 | if (net_ratelimit()) |
4444 | netdev_err(dev, "PCI error (cmd = 0x%04x, status_errs = 0x%04x)\n", | |
4445 | pci_cmd, pci_status_errs); | |
1da177e4 | 4446 | |
98ddf986 | 4447 | rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); |
1da177e4 LT |
4448 | } |
4449 | ||
5317d5c6 HK |
4450 | static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp, |
4451 | int budget) | |
1da177e4 | 4452 | { |
ca1ab89c | 4453 | unsigned int dirty_tx, bytes_compl = 0, pkts_compl = 0; |
94d8a98e | 4454 | struct sk_buff *skb; |
1da177e4 | 4455 | |
1da177e4 | 4456 | dirty_tx = tp->dirty_tx; |
1da177e4 | 4457 | |
55c779f2 | 4458 | atomic_add(tp->cur_tx - dirty_tx, &tp->aspm_packet_count); |
ca1ab89c | 4459 | while (READ_ONCE(tp->cur_tx) != dirty_tx) { |
1da177e4 | 4460 | unsigned int entry = dirty_tx % NUM_TX_DESC; |
1da177e4 LT |
4461 | u32 status; |
4462 | ||
1da177e4 LT |
4463 | status = le32_to_cpu(tp->TxDescArray[entry].opts1); |
4464 | if (status & DescOwn) | |
4465 | break; | |
4466 | ||
94d8a98e | 4467 | skb = tp->tx_skb[entry].skb; |
22d352c5 HK |
4468 | rtl8169_unmap_tx_skb(tp, entry); |
4469 | ||
6a41f2b2 | 4470 | if (skb) { |
d92060bc | 4471 | pkts_compl++; |
6a41f2b2 HK |
4472 | bytes_compl += skb->len; |
4473 | napi_consume_skb(skb, budget); | |
1da177e4 LT |
4474 | } |
4475 | dirty_tx++; | |
1da177e4 LT |
4476 | } |
4477 | ||
4478 | if (tp->dirty_tx != dirty_tx) { | |
d92060bc | 4479 | netdev_completed_queue(dev, pkts_compl, bytes_compl); |
5e4cb480 | 4480 | dev_sw_netstats_tx_add(dev, pkts_compl, bytes_compl); |
d92060bc | 4481 | |
ae1f23fb FR |
4482 | /* Sync with rtl8169_start_xmit: |
4483 | * - publish dirty_tx ring index (write barrier) | |
4484 | * - refresh cur_tx ring index and queue status (read barrier) | |
4485 | * May the current thread miss the stopped queue condition, | |
4486 | * a racing xmit thread can only have a right view of the | |
4487 | * ring status. | |
4488 | */ | |
ca1ab89c | 4489 | smp_store_mb(tp->dirty_tx, dirty_tx); |
83c317d7 | 4490 | if (netif_queue_stopped(dev) && rtl_tx_slots_avail(tp)) |
1da177e4 | 4491 | netif_wake_queue(dev); |
d78ae2dc FR |
4492 | /* |
4493 | * 8168 hack: TxPoll requests are lost when the Tx packets are | |
4494 | * too close. Let's kick an extra TxPoll request when a burst | |
4495 | * of start_xmit activity is detected (if it is not detected, | |
4496 | * it is slow enough). -- FR | |
94d8a98e HK |
4497 | * If skb is NULL then we come here again once a tx irq is |
4498 | * triggered after the last fragment is marked transmitted. | |
d78ae2dc | 4499 | */ |
94d8a98e | 4500 | if (tp->cur_tx != dirty_tx && skb) |
f1bce4ad | 4501 | rtl8169_doorbell(tp); |
1da177e4 LT |
4502 | } |
4503 | } | |
4504 | ||
126fa4b9 FR |
4505 | static inline int rtl8169_fragmented_frame(u32 status) |
4506 | { | |
4507 | return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag); | |
4508 | } | |
4509 | ||
adea1ac7 | 4510 | static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1) |
1da177e4 | 4511 | { |
206a75e0 | 4512 | u32 status = opts1 & (RxProtoMask | RxCSFailMask); |
1da177e4 | 4513 | |
206a75e0 | 4514 | if (status == RxProtoTCP || status == RxProtoUDP) |
1da177e4 LT |
4515 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
4516 | else | |
bc8acf2c | 4517 | skb_checksum_none_assert(skb); |
1da177e4 LT |
4518 | } |
4519 | ||
2f53e9d7 | 4520 | static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, int budget) |
1da177e4 | 4521 | { |
588c7e5c | 4522 | struct device *d = tp_to_dev(tp); |
2f53e9d7 | 4523 | int count; |
1da177e4 | 4524 | |
2f53e9d7 HK |
4525 | for (count = 0; count < budget; count++, tp->cur_rx++) { |
4526 | unsigned int pkt_size, entry = tp->cur_rx % NUM_RX_DESC; | |
126fa4b9 | 4527 | struct RxDesc *desc = tp->RxDescArray + entry; |
588c7e5c HK |
4528 | struct sk_buff *skb; |
4529 | const void *rx_buf; | |
4530 | dma_addr_t addr; | |
1da177e4 LT |
4531 | u32 status; |
4532 | ||
6202806e | 4533 | status = le32_to_cpu(desc->opts1); |
1da177e4 LT |
4534 | if (status & DescOwn) |
4535 | break; | |
a0750138 AD |
4536 | |
4537 | /* This barrier is needed to keep us from reading | |
4538 | * any other fields out of the Rx descriptor until | |
4539 | * we know the status of DescOwn | |
4540 | */ | |
4541 | dma_rmb(); | |
4542 | ||
4dcb7d33 | 4543 | if (unlikely(status & RxRES)) { |
93882c6f HK |
4544 | if (net_ratelimit()) |
4545 | netdev_warn(dev, "Rx ERROR. status = %08x\n", | |
4546 | status); | |
cebf8cc7 | 4547 | dev->stats.rx_errors++; |
1da177e4 | 4548 | if (status & (RxRWT | RxRUNT)) |
cebf8cc7 | 4549 | dev->stats.rx_length_errors++; |
1da177e4 | 4550 | if (status & RxCRC) |
cebf8cc7 | 4551 | dev->stats.rx_crc_errors++; |
126fa4b9 | 4552 | |
588c7e5c | 4553 | if (!(dev->features & NETIF_F_RXALL)) |
ce11ff5e | 4554 | goto release_descriptor; |
588c7e5c HK |
4555 | else if (status & RxRWT || !(status & (RxRUNT | RxCRC))) |
4556 | goto release_descriptor; | |
4557 | } | |
1da177e4 | 4558 | |
588c7e5c HK |
4559 | pkt_size = status & GENMASK(13, 0); |
4560 | if (likely(!(dev->features & NETIF_F_RXFCS))) | |
4561 | pkt_size -= ETH_FCS_LEN; | |
fcd4e608 | 4562 | |
588c7e5c HK |
4563 | /* The driver does not support incoming fragmented frames. |
4564 | * They are seen as a symptom of over-mtu sized frames. | |
4565 | */ | |
4566 | if (unlikely(rtl8169_fragmented_frame(status))) { | |
4567 | dev->stats.rx_dropped++; | |
4568 | dev->stats.rx_length_errors++; | |
4569 | goto release_descriptor; | |
4570 | } | |
d4ed7463 | 4571 | |
588c7e5c HK |
4572 | skb = napi_alloc_skb(&tp->napi, pkt_size); |
4573 | if (unlikely(!skb)) { | |
4574 | dev->stats.rx_dropped++; | |
4575 | goto release_descriptor; | |
4576 | } | |
1da177e4 | 4577 | |
588c7e5c HK |
4578 | addr = le64_to_cpu(desc->addr); |
4579 | rx_buf = page_address(tp->Rx_databuff[entry]); | |
7a8fc77b | 4580 | |
588c7e5c HK |
4581 | dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE); |
4582 | prefetch(rx_buf); | |
4583 | skb_copy_to_linear_data(skb, rx_buf, pkt_size); | |
4584 | skb->tail += pkt_size; | |
4585 | skb->len = pkt_size; | |
4586 | dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE); | |
39174291 | 4587 | |
588c7e5c HK |
4588 | rtl8169_rx_csum(skb, status); |
4589 | skb->protocol = eth_type_trans(skb, dev); | |
4590 | ||
4591 | rtl8169_rx_vlan_tag(desc, skb); | |
4592 | ||
4593 | if (skb->pkt_type == PACKET_MULTICAST) | |
4594 | dev->stats.multicast++; | |
4595 | ||
4596 | napi_gro_receive(&tp->napi, skb); | |
4597 | ||
5e4cb480 | 4598 | dev_sw_netstats_rx_add(dev, pkt_size); |
ce11ff5e | 4599 | release_descriptor: |
1d0254dd | 4600 | rtl8169_mark_to_asic(desc); |
1da177e4 LT |
4601 | } |
4602 | ||
55c779f2 KHF |
4603 | atomic_add(count, &tp->aspm_packet_count); |
4604 | ||
1da177e4 LT |
4605 | return count; |
4606 | } | |
4607 | ||
07d3f51f | 4608 | static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance) |
1da177e4 | 4609 | { |
ebcd5daa | 4610 | struct rtl8169_private *tp = dev_instance; |
c1d532d2 | 4611 | u32 status = rtl_get_events(tp); |
1da177e4 | 4612 | |
9e89d719 | 4613 | if ((status & 0xffff) == 0xffff || !(status & tp->irq_mask)) |
05bbe558 | 4614 | return IRQ_NONE; |
1da177e4 | 4615 | |
38caff5a HK |
4616 | if (unlikely(status & SYSErr)) { |
4617 | rtl8169_pcierr_interrupt(tp->dev); | |
4618 | goto out; | |
4619 | } | |
da78dbff | 4620 | |
703732f0 HK |
4621 | if (status & LinkChg) |
4622 | phy_mac_interrupt(tp->phydev); | |
1da177e4 | 4623 | |
38caff5a HK |
4624 | if (unlikely(status & RxFIFOOver && |
4625 | tp->mac_version == RTL_GIGA_MAC_VER_11)) { | |
4626 | netif_stop_queue(tp->dev); | |
6b02e407 | 4627 | rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); |
da78dbff | 4628 | } |
1da177e4 | 4629 | |
7274c414 HK |
4630 | if (napi_schedule_prep(&tp->napi)) { |
4631 | rtl_irq_disable(tp); | |
4632 | __napi_schedule(&tp->napi); | |
4633 | } | |
38caff5a HK |
4634 | out: |
4635 | rtl_ack_events(tp, status); | |
1da177e4 | 4636 | |
38caff5a | 4637 | return IRQ_HANDLED; |
1da177e4 LT |
4638 | } |
4639 | ||
4422bcd4 FR |
4640 | static void rtl_task(struct work_struct *work) |
4641 | { | |
4642 | struct rtl8169_private *tp = | |
4643 | container_of(work, struct rtl8169_private, wk.work); | |
da78dbff | 4644 | |
abe5fc42 | 4645 | rtnl_lock(); |
da78dbff | 4646 | |
e18958c6 | 4647 | if (!netif_running(tp->dev) || |
6c4a70c5 | 4648 | !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags)) |
da78dbff FR |
4649 | goto out_unlock; |
4650 | ||
476c4f5d | 4651 | if (test_and_clear_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags)) { |
e18958c6 | 4652 | rtl_reset_work(tp); |
476c4f5d HK |
4653 | netif_wake_queue(tp->dev); |
4654 | } | |
da78dbff | 4655 | out_unlock: |
abe5fc42 | 4656 | rtnl_unlock(); |
4422bcd4 FR |
4657 | } |
4658 | ||
bea3348e | 4659 | static int rtl8169_poll(struct napi_struct *napi, int budget) |
1da177e4 | 4660 | { |
bea3348e SH |
4661 | struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi); |
4662 | struct net_device *dev = tp->dev; | |
6b839b6c | 4663 | int work_done; |
da78dbff | 4664 | |
5317d5c6 | 4665 | rtl_tx(dev, tp, budget); |
1da177e4 | 4666 | |
9fbb4a7a HK |
4667 | work_done = rtl_rx(dev, tp, budget); |
4668 | ||
52dbe846 | 4669 | if (work_done < budget && napi_complete_done(napi, work_done)) |
fe716f8a | 4670 | rtl_irq_enable(tp); |
1da177e4 | 4671 | |
bea3348e | 4672 | return work_done; |
1da177e4 | 4673 | } |
1da177e4 | 4674 | |
f1e911d5 HK |
4675 | static void r8169_phylink_handler(struct net_device *ndev) |
4676 | { | |
4677 | struct rtl8169_private *tp = netdev_priv(ndev); | |
4678 | ||
4679 | if (netif_carrier_ok(ndev)) { | |
4680 | rtl_link_chg_patch(tp); | |
4681 | pm_request_resume(&tp->pci_dev->dev); | |
4682 | } else { | |
4683 | pm_runtime_idle(&tp->pci_dev->dev); | |
4684 | } | |
4685 | ||
4686 | if (net_ratelimit()) | |
703732f0 | 4687 | phy_print_status(tp->phydev); |
f1e911d5 HK |
4688 | } |
4689 | ||
4690 | static int r8169_phy_connect(struct rtl8169_private *tp) | |
4691 | { | |
703732f0 | 4692 | struct phy_device *phydev = tp->phydev; |
f1e911d5 HK |
4693 | phy_interface_t phy_mode; |
4694 | int ret; | |
4695 | ||
f7ffa9ae | 4696 | phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII : |
f1e911d5 HK |
4697 | PHY_INTERFACE_MODE_MII; |
4698 | ||
4699 | ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler, | |
4700 | phy_mode); | |
4701 | if (ret) | |
4702 | return ret; | |
4703 | ||
66058b1c | 4704 | if (!tp->supports_gmii) |
f1e911d5 HK |
4705 | phy_set_max_speed(phydev, SPEED_100); |
4706 | ||
f1e911d5 HK |
4707 | phy_attached_info(phydev); |
4708 | ||
4709 | return 0; | |
4710 | } | |
4711 | ||
55c779f2 KHF |
4712 | #define ASPM_PACKET_THRESHOLD 10 |
4713 | #define ASPM_TOGGLE_INTERVAL 1000 | |
4714 | ||
4715 | static void rtl8169_aspm_toggle(struct work_struct *work) | |
4716 | { | |
4717 | struct rtl8169_private *tp = container_of(work, struct rtl8169_private, | |
4718 | aspm_toggle.work); | |
4719 | int packet_count; | |
4720 | bool enable; | |
4721 | ||
4722 | packet_count = atomic_xchg(&tp->aspm_packet_count, 0); | |
4723 | ||
4724 | if (pcie_aspm_enabled(tp->pci_dev)) { | |
4725 | enable = packet_count <= ASPM_PACKET_THRESHOLD; | |
4726 | ||
4727 | if (tp->rtl_aspm_enabled != enable) { | |
4728 | rtl_unlock_config_regs(tp); | |
4729 | rtl_hw_aspm_clkreq_enable(tp, enable); | |
4730 | rtl_lock_config_regs(tp); | |
4731 | } | |
4732 | } else if (tp->rtl_aspm_enabled) { | |
4733 | rtl_unlock_config_regs(tp); | |
4734 | rtl_hw_aspm_clkreq_enable(tp, false); | |
4735 | rtl_lock_config_regs(tp); | |
4736 | } | |
4737 | ||
4738 | schedule_delayed_work(&tp->aspm_toggle, msecs_to_jiffies(ASPM_TOGGLE_INTERVAL)); | |
4739 | } | |
4740 | ||
8ac8e8c6 | 4741 | static void rtl8169_down(struct rtl8169_private *tp) |
1da177e4 | 4742 | { |
55c779f2 KHF |
4743 | cancel_delayed_work_sync(&tp->aspm_toggle); |
4744 | ||
8ac8e8c6 HK |
4745 | /* Clear all task flags */ |
4746 | bitmap_zero(tp->wk.flags, RTL_FLAG_MAX); | |
f1e911d5 | 4747 | |
8ac8e8c6 | 4748 | phy_stop(tp->phydev); |
1da177e4 | 4749 | |
a2ee8472 HK |
4750 | rtl8169_update_counters(tp); |
4751 | ||
f658b909 HK |
4752 | pci_clear_master(tp->pci_dev); |
4753 | rtl_pci_commit(tp); | |
4754 | ||
0c28a63a | 4755 | rtl8169_cleanup(tp, true); |
1da177e4 | 4756 | |
7257c977 | 4757 | rtl_prepare_power_down(tp); |
1da177e4 LT |
4758 | } |
4759 | ||
567ca57f HK |
4760 | static void rtl8169_up(struct rtl8169_private *tp) |
4761 | { | |
f658b909 | 4762 | pci_set_master(tp->pci_dev); |
5c2280fc | 4763 | phy_init_hw(tp->phydev); |
7257c977 | 4764 | phy_resume(tp->phydev); |
567ca57f HK |
4765 | rtl8169_init_phy(tp); |
4766 | napi_enable(&tp->napi); | |
4767 | set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags); | |
4768 | rtl_reset_work(tp); | |
4769 | ||
4770 | phy_start(tp->phydev); | |
55c779f2 KHF |
4771 | |
4772 | /* pcie_aspm_capable may change after system resume */ | |
4773 | if (pcie_aspm_support_enabled() && pcie_aspm_capable(tp->pci_dev)) | |
4774 | schedule_delayed_work(&tp->aspm_toggle, 0); | |
567ca57f HK |
4775 | } |
4776 | ||
1da177e4 LT |
4777 | static int rtl8169_close(struct net_device *dev) |
4778 | { | |
4779 | struct rtl8169_private *tp = netdev_priv(dev); | |
4780 | struct pci_dev *pdev = tp->pci_dev; | |
4781 | ||
e1759441 RW |
4782 | pm_runtime_get_sync(&pdev->dev); |
4783 | ||
8ac8e8c6 HK |
4784 | netif_stop_queue(dev); |
4785 | rtl8169_down(tp); | |
4786 | rtl8169_rx_clear(tp); | |
1da177e4 | 4787 | |
4ea72445 L |
4788 | cancel_work_sync(&tp->wk.work); |
4789 | ||
424a646e | 4790 | free_irq(pci_irq_vector(pdev, 0), tp); |
1da177e4 | 4791 | |
cc9f07a8 HK |
4792 | phy_disconnect(tp->phydev); |
4793 | ||
82553bb6 SG |
4794 | dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, |
4795 | tp->RxPhyAddr); | |
4796 | dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, | |
4797 | tp->TxPhyAddr); | |
1da177e4 LT |
4798 | tp->TxDescArray = NULL; |
4799 | tp->RxDescArray = NULL; | |
4800 | ||
e1759441 RW |
4801 | pm_runtime_put_sync(&pdev->dev); |
4802 | ||
1da177e4 LT |
4803 | return 0; |
4804 | } | |
4805 | ||
dc1c00ce FR |
4806 | #ifdef CONFIG_NET_POLL_CONTROLLER |
4807 | static void rtl8169_netpoll(struct net_device *dev) | |
4808 | { | |
4809 | struct rtl8169_private *tp = netdev_priv(dev); | |
4810 | ||
6d8b8349 | 4811 | rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp); |
dc1c00ce FR |
4812 | } |
4813 | #endif | |
4814 | ||
df43ac78 FR |
4815 | static int rtl_open(struct net_device *dev) |
4816 | { | |
4817 | struct rtl8169_private *tp = netdev_priv(dev); | |
df43ac78 | 4818 | struct pci_dev *pdev = tp->pci_dev; |
870f531e | 4819 | unsigned long irqflags; |
df43ac78 FR |
4820 | int retval = -ENOMEM; |
4821 | ||
4822 | pm_runtime_get_sync(&pdev->dev); | |
4823 | ||
4824 | /* | |
e75d6606 | 4825 | * Rx and Tx descriptors needs 256 bytes alignment. |
df43ac78 FR |
4826 | * dma_alloc_coherent provides more. |
4827 | */ | |
4828 | tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES, | |
4829 | &tp->TxPhyAddr, GFP_KERNEL); | |
4830 | if (!tp->TxDescArray) | |
1c470b53 | 4831 | goto out; |
df43ac78 FR |
4832 | |
4833 | tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES, | |
4834 | &tp->RxPhyAddr, GFP_KERNEL); | |
4835 | if (!tp->RxDescArray) | |
4836 | goto err_free_tx_0; | |
4837 | ||
b1127e64 | 4838 | retval = rtl8169_init_ring(tp); |
df43ac78 FR |
4839 | if (retval < 0) |
4840 | goto err_free_rx_1; | |
4841 | ||
df43ac78 FR |
4842 | rtl_request_firmware(tp); |
4843 | ||
870f531e | 4844 | irqflags = pci_dev_msi_enabled(pdev) ? IRQF_NO_THREAD : IRQF_SHARED; |
424a646e | 4845 | retval = request_irq(pci_irq_vector(pdev, 0), rtl8169_interrupt, |
870f531e | 4846 | irqflags, dev->name, tp); |
df43ac78 FR |
4847 | if (retval < 0) |
4848 | goto err_release_fw_2; | |
4849 | ||
f1e911d5 HK |
4850 | retval = r8169_phy_connect(tp); |
4851 | if (retval) | |
4852 | goto err_free_irq; | |
4853 | ||
567ca57f | 4854 | rtl8169_up(tp); |
d56f58ce | 4855 | rtl8169_init_counter_offsets(tp); |
df43ac78 | 4856 | netif_start_queue(dev); |
df43ac78 | 4857 | out: |
1c470b53 HK |
4858 | pm_runtime_put_sync(&pdev->dev); |
4859 | ||
df43ac78 FR |
4860 | return retval; |
4861 | ||
f1e911d5 | 4862 | err_free_irq: |
424a646e | 4863 | free_irq(pci_irq_vector(pdev, 0), tp); |
df43ac78 FR |
4864 | err_release_fw_2: |
4865 | rtl_release_firmware(tp); | |
4866 | rtl8169_rx_clear(tp); | |
4867 | err_free_rx_1: | |
4868 | dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, | |
4869 | tp->RxPhyAddr); | |
4870 | tp->RxDescArray = NULL; | |
4871 | err_free_tx_0: | |
4872 | dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, | |
4873 | tp->TxPhyAddr); | |
4874 | tp->TxDescArray = NULL; | |
df43ac78 FR |
4875 | goto out; |
4876 | } | |
4877 | ||
bc1f4470 | 4878 | static void |
8027aa24 | 4879 | rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) |
1da177e4 LT |
4880 | { |
4881 | struct rtl8169_private *tp = netdev_priv(dev); | |
f09cf4b7 | 4882 | struct pci_dev *pdev = tp->pci_dev; |
42020320 | 4883 | struct rtl8169_counters *counters = tp->counters; |
1da177e4 | 4884 | |
f09cf4b7 CHL |
4885 | pm_runtime_get_noresume(&pdev->dev); |
4886 | ||
314a9cbb | 4887 | netdev_stats_to_stats64(stats, &dev->stats); |
5e4cb480 | 4888 | dev_fetch_sw_netstats(stats, dev->tstats); |
8027aa24 | 4889 | |
6e85d5ad | 4890 | /* |
ed72a9bb | 4891 | * Fetch additional counter values missing in stats collected by driver |
6e85d5ad CV |
4892 | * from tally counters. |
4893 | */ | |
f09cf4b7 | 4894 | if (pm_runtime_active(&pdev->dev)) |
e71c9ce2 | 4895 | rtl8169_update_counters(tp); |
6e85d5ad CV |
4896 | |
4897 | /* | |
4898 | * Subtract values fetched during initalization. | |
4899 | * See rtl8169_init_counter_offsets for a description why we do that. | |
4900 | */ | |
42020320 | 4901 | stats->tx_errors = le64_to_cpu(counters->tx_errors) - |
6e85d5ad | 4902 | le64_to_cpu(tp->tc_offset.tx_errors); |
42020320 | 4903 | stats->collisions = le32_to_cpu(counters->tx_multi_collision) - |
6e85d5ad | 4904 | le32_to_cpu(tp->tc_offset.tx_multi_collision); |
42020320 | 4905 | stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) - |
6e85d5ad | 4906 | le16_to_cpu(tp->tc_offset.tx_aborted); |
0da3359a HK |
4907 | stats->rx_missed_errors = le16_to_cpu(counters->rx_missed) - |
4908 | le16_to_cpu(tp->tc_offset.rx_missed); | |
6e85d5ad | 4909 | |
f09cf4b7 | 4910 | pm_runtime_put_noidle(&pdev->dev); |
1da177e4 LT |
4911 | } |
4912 | ||
27dc36ae | 4913 | static void rtl8169_net_suspend(struct rtl8169_private *tp) |
5d06a99f | 4914 | { |
27dc36ae | 4915 | netif_device_detach(tp->dev); |
476c4f5d HK |
4916 | |
4917 | if (netif_running(tp->dev)) | |
4918 | rtl8169_down(tp); | |
861ab440 RW |
4919 | } |
4920 | ||
4921 | #ifdef CONFIG_PM | |
4922 | ||
06e56697 | 4923 | static int rtl8169_runtime_resume(struct device *dev) |
bb13a800 | 4924 | { |
06e56697 HK |
4925 | struct rtl8169_private *tp = dev_get_drvdata(dev); |
4926 | ||
bb13a800 | 4927 | rtl_rar_set(tp, tp->dev->dev_addr); |
06e56697 | 4928 | __rtl8169_set_wol(tp, tp->saved_wolopts); |
bb13a800 HK |
4929 | |
4930 | if (tp->TxDescArray) | |
4931 | rtl8169_up(tp); | |
4932 | ||
4933 | netif_device_attach(tp->dev); | |
4934 | ||
4935 | return 0; | |
4936 | } | |
4937 | ||
67ee63ef | 4938 | static int __maybe_unused rtl8169_suspend(struct device *device) |
861ab440 | 4939 | { |
27dc36ae | 4940 | struct rtl8169_private *tp = dev_get_drvdata(device); |
5d06a99f | 4941 | |
abe5fc42 | 4942 | rtnl_lock(); |
27dc36ae | 4943 | rtl8169_net_suspend(tp); |
bb13a800 HK |
4944 | if (!device_may_wakeup(tp_to_dev(tp))) |
4945 | clk_disable_unprepare(tp->clk); | |
abe5fc42 | 4946 | rtnl_unlock(); |
1371fa6d | 4947 | |
5d06a99f FR |
4948 | return 0; |
4949 | } | |
4950 | ||
bb13a800 | 4951 | static int __maybe_unused rtl8169_resume(struct device *device) |
5d06a99f | 4952 | { |
27dc36ae | 4953 | struct rtl8169_private *tp = dev_get_drvdata(device); |
ac8bd9e1 | 4954 | |
bb13a800 HK |
4955 | if (!device_may_wakeup(tp_to_dev(tp))) |
4956 | clk_prepare_enable(tp->clk); | |
5d06a99f | 4957 | |
ef9da46d HK |
4958 | /* Reportedly at least Asus X453MA truncates packets otherwise */ |
4959 | if (tp->mac_version == RTL_GIGA_MAC_VER_37) | |
4960 | rtl_init_rxcfg(tp); | |
476c4f5d | 4961 | |
06e56697 | 4962 | return rtl8169_runtime_resume(device); |
e1759441 RW |
4963 | } |
4964 | ||
4965 | static int rtl8169_runtime_suspend(struct device *device) | |
4966 | { | |
27dc36ae | 4967 | struct rtl8169_private *tp = dev_get_drvdata(device); |
e1759441 | 4968 | |
476c4f5d HK |
4969 | if (!tp->TxDescArray) { |
4970 | netif_device_detach(tp->dev); | |
e1759441 | 4971 | return 0; |
476c4f5d | 4972 | } |
e1759441 | 4973 | |
abe5fc42 | 4974 | rtnl_lock(); |
01bd753d | 4975 | __rtl8169_set_wol(tp, WAKE_PHY); |
27dc36ae | 4976 | rtl8169_net_suspend(tp); |
abe5fc42 | 4977 | rtnl_unlock(); |
e1759441 RW |
4978 | |
4979 | return 0; | |
4980 | } | |
4981 | ||
e1759441 RW |
4982 | static int rtl8169_runtime_idle(struct device *device) |
4983 | { | |
27dc36ae | 4984 | struct rtl8169_private *tp = dev_get_drvdata(device); |
e1759441 | 4985 | |
27dc36ae | 4986 | if (!netif_running(tp->dev) || !netif_carrier_ok(tp->dev)) |
a92a0849 HK |
4987 | pm_schedule_suspend(device, 10000); |
4988 | ||
4989 | return -EBUSY; | |
e1759441 RW |
4990 | } |
4991 | ||
47145210 | 4992 | static const struct dev_pm_ops rtl8169_pm_ops = { |
67ee63ef HK |
4993 | SET_SYSTEM_SLEEP_PM_OPS(rtl8169_suspend, rtl8169_resume) |
4994 | SET_RUNTIME_PM_OPS(rtl8169_runtime_suspend, rtl8169_runtime_resume, | |
4995 | rtl8169_runtime_idle) | |
861ab440 RW |
4996 | }; |
4997 | ||
67ee63ef | 4998 | #endif /* CONFIG_PM */ |
861ab440 | 4999 | |
649b3b8c | 5000 | static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp) |
5001 | { | |
649b3b8c | 5002 | /* WoL fails with 8168b when the receiver is disabled. */ |
5003 | switch (tp->mac_version) { | |
5004 | case RTL_GIGA_MAC_VER_11: | |
5005 | case RTL_GIGA_MAC_VER_12: | |
5006 | case RTL_GIGA_MAC_VER_17: | |
5007 | pci_clear_master(tp->pci_dev); | |
5008 | ||
1ef7286e | 5009 | RTL_W8(tp, ChipCmd, CmdRxEnb); |
711463f8 | 5010 | rtl_pci_commit(tp); |
649b3b8c | 5011 | break; |
5012 | default: | |
5013 | break; | |
5014 | } | |
5015 | } | |
5016 | ||
1765f95d FR |
5017 | static void rtl_shutdown(struct pci_dev *pdev) |
5018 | { | |
27dc36ae | 5019 | struct rtl8169_private *tp = pci_get_drvdata(pdev); |
861ab440 | 5020 | |
abe5fc42 | 5021 | rtnl_lock(); |
27dc36ae | 5022 | rtl8169_net_suspend(tp); |
abe5fc42 | 5023 | rtnl_unlock(); |
1765f95d | 5024 | |
cecb5fd7 | 5025 | /* Restore original MAC address */ |
27dc36ae | 5026 | rtl_rar_set(tp, tp->dev->perm_addr); |
cc098dc7 | 5027 | |
861ab440 | 5028 | if (system_state == SYSTEM_POWER_OFF) { |
17ce76c4 | 5029 | if (tp->saved_wolopts) |
649b3b8c | 5030 | rtl_wol_shutdown_quirk(tp); |
ca52efd5 | 5031 | |
bb703e57 | 5032 | pci_wake_from_d3(pdev, tp->saved_wolopts); |
861ab440 RW |
5033 | pci_set_power_state(pdev, PCI_D3hot); |
5034 | } | |
5035 | } | |
5d06a99f | 5036 | |
baf63293 | 5037 | static void rtl_remove_one(struct pci_dev *pdev) |
e27566ed | 5038 | { |
27dc36ae | 5039 | struct rtl8169_private *tp = pci_get_drvdata(pdev); |
e27566ed | 5040 | |
12b1bc75 HK |
5041 | if (pci_dev_run_wake(pdev)) |
5042 | pm_runtime_get_noresume(&pdev->dev); | |
ad1be8d3 | 5043 | |
27dc36ae | 5044 | unregister_netdev(tp->dev); |
e27566ed | 5045 | |
e0d38b58 | 5046 | if (tp->dash_type != RTL_DASH_NONE) |
12b1bc75 | 5047 | rtl8168_driver_stop(tp); |
e27566ed | 5048 | |
12b1bc75 | 5049 | rtl_release_firmware(tp); |
e27566ed FR |
5050 | |
5051 | /* restore original MAC address */ | |
27dc36ae | 5052 | rtl_rar_set(tp, tp->dev->perm_addr); |
e27566ed FR |
5053 | } |
5054 | ||
fa9c385e | 5055 | static const struct net_device_ops rtl_netdev_ops = { |
df43ac78 | 5056 | .ndo_open = rtl_open, |
fa9c385e FR |
5057 | .ndo_stop = rtl8169_close, |
5058 | .ndo_get_stats64 = rtl8169_get_stats64, | |
5059 | .ndo_start_xmit = rtl8169_start_xmit, | |
e64e0c89 | 5060 | .ndo_features_check = rtl8169_features_check, |
fa9c385e FR |
5061 | .ndo_tx_timeout = rtl8169_tx_timeout, |
5062 | .ndo_validate_addr = eth_validate_addr, | |
5063 | .ndo_change_mtu = rtl8169_change_mtu, | |
5064 | .ndo_fix_features = rtl8169_fix_features, | |
5065 | .ndo_set_features = rtl8169_set_features, | |
5066 | .ndo_set_mac_address = rtl_set_mac_address, | |
a7605370 | 5067 | .ndo_eth_ioctl = phy_do_ioctl_running, |
fa9c385e FR |
5068 | .ndo_set_rx_mode = rtl_set_rx_mode, |
5069 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
5070 | .ndo_poll_controller = rtl8169_netpoll, | |
5071 | #endif | |
5072 | ||
5073 | }; | |
5074 | ||
ec9a4088 HK |
5075 | static void rtl_set_irq_mask(struct rtl8169_private *tp) |
5076 | { | |
2045e158 | 5077 | tp->irq_mask = RxOK | RxErr | TxOK | TxErr | LinkChg; |
ec9a4088 HK |
5078 | |
5079 | if (tp->mac_version <= RTL_GIGA_MAC_VER_06) | |
5080 | tp->irq_mask |= SYSErr | RxOverflow | RxFIFOOver; | |
5081 | else if (tp->mac_version == RTL_GIGA_MAC_VER_11) | |
5082 | /* special workaround needed */ | |
5083 | tp->irq_mask |= RxFIFOOver; | |
5084 | else | |
5085 | tp->irq_mask |= RxOverflow; | |
5086 | } | |
5087 | ||
6c6aa15f | 5088 | static int rtl_alloc_irq(struct rtl8169_private *tp) |
31fa8b18 | 5089 | { |
6c6aa15f | 5090 | unsigned int flags; |
31fa8b18 | 5091 | |
003bd5b4 HK |
5092 | switch (tp->mac_version) { |
5093 | case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: | |
df320ed7 | 5094 | rtl_unlock_config_regs(tp); |
1ef7286e | 5095 | RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable); |
df320ed7 | 5096 | rtl_lock_config_regs(tp); |
df561f66 | 5097 | fallthrough; |
f13bc681 | 5098 | case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_17: |
6c6aa15f | 5099 | flags = PCI_IRQ_LEGACY; |
003bd5b4 HK |
5100 | break; |
5101 | default: | |
6c6aa15f | 5102 | flags = PCI_IRQ_ALL_TYPES; |
003bd5b4 | 5103 | break; |
31fa8b18 | 5104 | } |
6c6aa15f HK |
5105 | |
5106 | return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags); | |
31fa8b18 FR |
5107 | } |
5108 | ||
04c7788c TR |
5109 | static void rtl_read_mac_address(struct rtl8169_private *tp, |
5110 | u8 mac_addr[ETH_ALEN]) | |
5111 | { | |
5112 | /* Get MAC address */ | |
9e9f33ba | 5113 | if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) { |
ae1e82c6 | 5114 | u32 value; |
deedf1fe | 5115 | |
ae1e82c6 HK |
5116 | value = rtl_eri_read(tp, 0xe0); |
5117 | put_unaligned_le32(value, mac_addr); | |
724c6fd0 | 5118 | value = rtl_eri_read(tp, 0xe4); |
ae1e82c6 | 5119 | put_unaligned_le16(value, mac_addr + 4); |
f1bce4ad HK |
5120 | } else if (rtl_is_8125(tp)) { |
5121 | rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP); | |
04c7788c TR |
5122 | } |
5123 | } | |
5124 | ||
c558386b HW |
5125 | DECLARE_RTL_COND(rtl_link_list_ready_cond) |
5126 | { | |
1ef7286e | 5127 | return RTL_R8(tp, MCU) & LINK_LIST_RDY; |
c558386b HW |
5128 | } |
5129 | ||
e031ce80 HK |
5130 | static void r8168g_wait_ll_share_fifo_ready(struct rtl8169_private *tp) |
5131 | { | |
5132 | rtl_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42); | |
5133 | } | |
5134 | ||
f1e911d5 HK |
5135 | static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg) |
5136 | { | |
5137 | struct rtl8169_private *tp = mii_bus->priv; | |
5138 | ||
5139 | if (phyaddr > 0) | |
5140 | return -ENODEV; | |
5141 | ||
5142 | return rtl_readphy(tp, phyreg); | |
5143 | } | |
5144 | ||
5145 | static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr, | |
5146 | int phyreg, u16 val) | |
5147 | { | |
5148 | struct rtl8169_private *tp = mii_bus->priv; | |
5149 | ||
5150 | if (phyaddr > 0) | |
5151 | return -ENODEV; | |
5152 | ||
5153 | rtl_writephy(tp, phyreg, val); | |
5154 | ||
5155 | return 0; | |
5156 | } | |
5157 | ||
5158 | static int r8169_mdio_register(struct rtl8169_private *tp) | |
5159 | { | |
5160 | struct pci_dev *pdev = tp->pci_dev; | |
f1e911d5 HK |
5161 | struct mii_bus *new_bus; |
5162 | int ret; | |
5163 | ||
5164 | new_bus = devm_mdiobus_alloc(&pdev->dev); | |
5165 | if (!new_bus) | |
5166 | return -ENOMEM; | |
5167 | ||
5168 | new_bus->name = "r8169"; | |
5169 | new_bus->priv = tp; | |
5170 | new_bus->parent = &pdev->dev; | |
93e8990c | 5171 | new_bus->irq[0] = PHY_MAC_INTERRUPT; |
e9a72f87 SP |
5172 | snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x-%x", |
5173 | pci_domain_nr(pdev->bus), pci_dev_id(pdev)); | |
f1e911d5 HK |
5174 | |
5175 | new_bus->read = r8169_mdio_read_reg; | |
5176 | new_bus->write = r8169_mdio_write_reg; | |
5177 | ||
ac3a68d5 | 5178 | ret = devm_mdiobus_register(&pdev->dev, new_bus); |
f1e911d5 HK |
5179 | if (ret) |
5180 | return ret; | |
5181 | ||
703732f0 HK |
5182 | tp->phydev = mdiobus_get_phy(new_bus, 0); |
5183 | if (!tp->phydev) { | |
f1e911d5 | 5184 | return -ENODEV; |
2e8c339b HK |
5185 | } else if (!tp->phydev->drv) { |
5186 | /* Most chip versions fail with the genphy driver. | |
5187 | * Therefore ensure that the dedicated PHY driver is loaded. | |
5188 | */ | |
0c2006b2 HK |
5189 | dev_err(&pdev->dev, "no dedicated PHY driver found for PHY ID 0x%08x, maybe realtek.ko needs to be added to initramfs?\n", |
5190 | tp->phydev->phy_id); | |
2e8c339b | 5191 | return -EUNATCH; |
f1e911d5 HK |
5192 | } |
5193 | ||
5c2280fc HK |
5194 | tp->phydev->mac_managed_pm = 1; |
5195 | ||
11ac4e66 HK |
5196 | phy_support_asym_pause(tp->phydev); |
5197 | ||
242cd9b5 | 5198 | /* PHY will be woken up in rtl_open() */ |
703732f0 | 5199 | phy_suspend(tp->phydev); |
f1e911d5 HK |
5200 | |
5201 | return 0; | |
5202 | } | |
5203 | ||
baf63293 | 5204 | static void rtl_hw_init_8168g(struct rtl8169_private *tp) |
c558386b | 5205 | { |
9617886f | 5206 | rtl_enable_rxdvgate(tp); |
c558386b | 5207 | |
1ef7286e | 5208 | RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); |
c558386b | 5209 | msleep(1); |
1ef7286e | 5210 | RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); |
c558386b | 5211 | |
ef712ede | 5212 | r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); |
e031ce80 | 5213 | r8168g_wait_ll_share_fifo_ready(tp); |
c558386b | 5214 | |
ef712ede | 5215 | r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15)); |
e031ce80 | 5216 | r8168g_wait_ll_share_fifo_ready(tp); |
c558386b HW |
5217 | } |
5218 | ||
f1bce4ad HK |
5219 | static void rtl_hw_init_8125(struct rtl8169_private *tp) |
5220 | { | |
9617886f | 5221 | rtl_enable_rxdvgate(tp); |
f1bce4ad | 5222 | |
f1bce4ad HK |
5223 | RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); |
5224 | msleep(1); | |
5225 | RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); | |
5226 | ||
5227 | r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); | |
e031ce80 | 5228 | r8168g_wait_ll_share_fifo_ready(tp); |
f1bce4ad HK |
5229 | |
5230 | r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0); | |
5231 | r8168_mac_ocp_write(tp, 0xc0a6, 0x0150); | |
5232 | r8168_mac_ocp_write(tp, 0xc01e, 0x5555); | |
e031ce80 | 5233 | r8168g_wait_ll_share_fifo_ready(tp); |
f1bce4ad HK |
5234 | } |
5235 | ||
baf63293 | 5236 | static void rtl_hw_initialize(struct rtl8169_private *tp) |
c558386b HW |
5237 | { |
5238 | switch (tp->mac_version) { | |
e6d6ca6e | 5239 | case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_53: |
29ec0482 | 5240 | rtl8168ep_stop_cmac(tp); |
df561f66 | 5241 | fallthrough; |
2a71883c | 5242 | case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48: |
003609da CHL |
5243 | rtl_hw_init_8168g(tp); |
5244 | break; | |
0439297b | 5245 | case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_63: |
f1bce4ad HK |
5246 | rtl_hw_init_8125(tp); |
5247 | break; | |
c558386b HW |
5248 | default: |
5249 | break; | |
5250 | } | |
5251 | } | |
5252 | ||
abe8b2f7 HK |
5253 | static int rtl_jumbo_max(struct rtl8169_private *tp) |
5254 | { | |
5255 | /* Non-GBit versions don't support jumbo frames */ | |
5256 | if (!tp->supports_gmii) | |
a8ec173a | 5257 | return 0; |
abe8b2f7 HK |
5258 | |
5259 | switch (tp->mac_version) { | |
5260 | /* RTL8169 */ | |
e9588eb9 | 5261 | case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: |
abe8b2f7 HK |
5262 | return JUMBO_7K; |
5263 | /* RTL8168b */ | |
5264 | case RTL_GIGA_MAC_VER_11: | |
5265 | case RTL_GIGA_MAC_VER_12: | |
5266 | case RTL_GIGA_MAC_VER_17: | |
5267 | return JUMBO_4K; | |
5268 | /* RTL8168c */ | |
5269 | case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: | |
5270 | return JUMBO_6K; | |
5271 | default: | |
5272 | return JUMBO_9K; | |
5273 | } | |
5274 | } | |
5275 | ||
c2f6f3ee HG |
5276 | static void rtl_disable_clk(void *data) |
5277 | { | |
5278 | clk_disable_unprepare(data); | |
5279 | } | |
5280 | ||
b779daea HK |
5281 | static int rtl_get_ether_clk(struct rtl8169_private *tp) |
5282 | { | |
5283 | struct device *d = tp_to_dev(tp); | |
5284 | struct clk *clk; | |
5285 | int rc; | |
5286 | ||
5287 | clk = devm_clk_get(d, "ether_clk"); | |
5288 | if (IS_ERR(clk)) { | |
5289 | rc = PTR_ERR(clk); | |
5290 | if (rc == -ENOENT) | |
5291 | /* clk-core allows NULL (for suspend / resume) */ | |
5292 | rc = 0; | |
bf7b0bf6 HK |
5293 | else |
5294 | dev_err_probe(d, rc, "failed to get clk\n"); | |
b779daea HK |
5295 | } else { |
5296 | tp->clk = clk; | |
5297 | rc = clk_prepare_enable(clk); | |
5298 | if (rc) | |
5299 | dev_err(d, "failed to enable clk: %d\n", rc); | |
5300 | else | |
5301 | rc = devm_add_action_or_reset(d, rtl_disable_clk, clk); | |
5302 | } | |
5303 | ||
5304 | return rc; | |
5305 | } | |
5306 | ||
c782e204 HK |
5307 | static void rtl_init_mac_address(struct rtl8169_private *tp) |
5308 | { | |
5309 | struct net_device *dev = tp->dev; | |
5310 | u8 *mac_addr = dev->dev_addr; | |
ce37115e | 5311 | int rc; |
c782e204 HK |
5312 | |
5313 | rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr); | |
5314 | if (!rc) | |
5315 | goto done; | |
5316 | ||
5317 | rtl_read_mac_address(tp, mac_addr); | |
5318 | if (is_valid_ether_addr(mac_addr)) | |
5319 | goto done; | |
5320 | ||
ce37115e | 5321 | rtl_read_mac_from_reg(tp, mac_addr, MAC0); |
c782e204 HK |
5322 | if (is_valid_ether_addr(mac_addr)) |
5323 | goto done; | |
5324 | ||
5325 | eth_hw_addr_random(dev); | |
5326 | dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n"); | |
5327 | done: | |
5328 | rtl_rar_set(tp, mac_addr); | |
5329 | } | |
5330 | ||
929a031d | 5331 | static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
3b6cf25d | 5332 | { |
3b6cf25d | 5333 | struct rtl8169_private *tp; |
f1f9ca28 HK |
5334 | int jumbo_max, region, rc; |
5335 | enum mac_version chipset; | |
3b6cf25d | 5336 | struct net_device *dev; |
f1f9ca28 | 5337 | u16 xid; |
3b6cf25d | 5338 | |
4c45d24a HK |
5339 | dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp)); |
5340 | if (!dev) | |
5341 | return -ENOMEM; | |
3b6cf25d FR |
5342 | |
5343 | SET_NETDEV_DEV(dev, &pdev->dev); | |
fa9c385e | 5344 | dev->netdev_ops = &rtl_netdev_ops; |
3b6cf25d FR |
5345 | tp = netdev_priv(dev); |
5346 | tp->dev = dev; | |
5347 | tp->pci_dev = pdev; | |
145a40e8 | 5348 | tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1; |
7ec3f872 | 5349 | tp->eee_adv = -1; |
0360c046 | 5350 | tp->ocp_base = OCP_STD_PHY_BASE; |
3b6cf25d | 5351 | |
5e4cb480 HK |
5352 | dev->tstats = devm_netdev_alloc_pcpu_stats(&pdev->dev, |
5353 | struct pcpu_sw_netstats); | |
5354 | if (!dev->tstats) | |
5355 | return -ENOMEM; | |
5356 | ||
c2f6f3ee | 5357 | /* Get the *optional* external "ether_clk" used on some boards */ |
b779daea HK |
5358 | rc = rtl_get_ether_clk(tp); |
5359 | if (rc) | |
5360 | return rc; | |
c2f6f3ee | 5361 | |
3b6cf25d | 5362 | /* enable device (incl. PCI PM wakeup and hotplug setup) */ |
4c45d24a | 5363 | rc = pcim_enable_device(pdev); |
3b6cf25d | 5364 | if (rc < 0) { |
22148df0 | 5365 | dev_err(&pdev->dev, "enable failure\n"); |
4c45d24a | 5366 | return rc; |
3b6cf25d FR |
5367 | } |
5368 | ||
4c45d24a | 5369 | if (pcim_set_mwi(pdev) < 0) |
22148df0 | 5370 | dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n"); |
3b6cf25d | 5371 | |
c8d48d9c HK |
5372 | /* use first MMIO region */ |
5373 | region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1; | |
5374 | if (region < 0) { | |
22148df0 | 5375 | dev_err(&pdev->dev, "no MMIO resource found\n"); |
4c45d24a | 5376 | return -ENODEV; |
3b6cf25d FR |
5377 | } |
5378 | ||
5379 | /* check for weird/broken PCI region reporting */ | |
5380 | if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) { | |
22148df0 | 5381 | dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n"); |
4c45d24a | 5382 | return -ENODEV; |
3b6cf25d FR |
5383 | } |
5384 | ||
7cb7541a | 5385 | rc = pcim_iomap_regions(pdev, BIT(region), KBUILD_MODNAME); |
3b6cf25d | 5386 | if (rc < 0) { |
22148df0 | 5387 | dev_err(&pdev->dev, "cannot remap MMIO, aborting\n"); |
4c45d24a | 5388 | return rc; |
3b6cf25d FR |
5389 | } |
5390 | ||
55c779f2 KHF |
5391 | mutex_init(&tp->config_lock); |
5392 | ||
93a00d4d | 5393 | tp->mmio_addr = pcim_iomap_table(pdev)[region]; |
3b6cf25d | 5394 | |
f1f9ca28 HK |
5395 | xid = (RTL_R32(tp, TxConfig) >> 20) & 0xfcf; |
5396 | ||
3b6cf25d | 5397 | /* Identify chip attached to board */ |
f1f9ca28 HK |
5398 | chipset = rtl8169_get_mac_version(xid, tp->supports_gmii); |
5399 | if (chipset == RTL_GIGA_MAC_NONE) { | |
beb401ec | 5400 | dev_err(&pdev->dev, "unknown chip XID %03x, contact r8169 maintainers (see MAINTAINERS file)\n", xid); |
b4cc2dcc | 5401 | return -ENODEV; |
f1f9ca28 HK |
5402 | } |
5403 | ||
5404 | tp->mac_version = chipset; | |
3b6cf25d | 5405 | |
e0d38b58 HK |
5406 | tp->dash_type = rtl_check_dash(tp); |
5407 | ||
975e8505 | 5408 | tp->cp_cmd = RTL_R16(tp, CPlusCmd) & CPCMD_MASK; |
27896c83 | 5409 | |
10b63e85 | 5410 | if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 && |
3c18cbe3 | 5411 | !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) |
27896c83 | 5412 | dev->features |= NETIF_F_HIGHDMA; |
27896c83 | 5413 | |
3b6cf25d FR |
5414 | rtl_init_rxcfg(tp); |
5415 | ||
de20e12f | 5416 | rtl8169_irq_mask_and_ack(tp); |
3b6cf25d | 5417 | |
c558386b HW |
5418 | rtl_hw_initialize(tp); |
5419 | ||
3b6cf25d FR |
5420 | rtl_hw_reset(tp); |
5421 | ||
6c6aa15f HK |
5422 | rc = rtl_alloc_irq(tp); |
5423 | if (rc < 0) { | |
22148df0 | 5424 | dev_err(&pdev->dev, "Can't allocate interrupt\n"); |
6c6aa15f HK |
5425 | return rc; |
5426 | } | |
3b6cf25d | 5427 | |
5c41e78f | 5428 | INIT_WORK(&tp->wk.work, rtl_task); |
3b6cf25d | 5429 | |
55c779f2 KHF |
5430 | INIT_DELAYED_WORK(&tp->aspm_toggle, rtl8169_aspm_toggle); |
5431 | ||
5432 | atomic_set(&tp->aspm_packet_count, 0); | |
5433 | ||
c782e204 | 5434 | rtl_init_mac_address(tp); |
3b6cf25d | 5435 | |
7ad24ea4 | 5436 | dev->ethtool_ops = &rtl8169_ethtool_ops; |
3b6cf25d | 5437 | |
37621493 | 5438 | netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT); |
3b6cf25d | 5439 | |
95099c56 HK |
5440 | dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM | |
5441 | NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX; | |
a9b3d568 | 5442 | dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO; |
2d0ec544 | 5443 | dev->priv_flags |= IFF_LIVE_ADDR_CHANGE; |
3b6cf25d | 5444 | |
929a031d | 5445 | /* |
5446 | * Pretend we are using VLANs; This bypasses a nasty bug where | |
5447 | * Interrupts stop flowing on high load on 8110SCd controllers. | |
5448 | */ | |
3b6cf25d | 5449 | if (tp->mac_version == RTL_GIGA_MAC_VER_05) |
929a031d | 5450 | /* Disallow toggling */ |
f646968f | 5451 | dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX; |
3b6cf25d | 5452 | |
95099c56 HK |
5453 | if (rtl_chip_supports_csum_v2(tp)) |
5454 | dev->hw_features |= NETIF_F_IPV6_CSUM; | |
5455 | ||
5456 | dev->features |= dev->hw_features; | |
5457 | ||
5458 | /* There has been a number of reports that using SG/TSO results in | |
5459 | * tx timeouts. However for a lot of people SG/TSO works fine. | |
5460 | * Therefore disable both features by default, but allow users to | |
5461 | * enable them. Use at own risk! | |
5462 | */ | |
0170d594 | 5463 | if (rtl_chip_supports_csum_v2(tp)) { |
95099c56 | 5464 | dev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6; |
0170d594 HK |
5465 | dev->gso_max_size = RTL_GSO_MAX_SIZE_V2; |
5466 | dev->gso_max_segs = RTL_GSO_MAX_SEGS_V2; | |
5467 | } else { | |
95099c56 | 5468 | dev->hw_features |= NETIF_F_SG | NETIF_F_TSO; |
0170d594 HK |
5469 | dev->gso_max_size = RTL_GSO_MAX_SIZE_V1; |
5470 | dev->gso_max_segs = RTL_GSO_MAX_SEGS_V1; | |
5471 | } | |
5888d3fc | 5472 | |
3b6cf25d FR |
5473 | dev->hw_features |= NETIF_F_RXALL; |
5474 | dev->hw_features |= NETIF_F_RXFCS; | |
5475 | ||
145192f8 HK |
5476 | /* configure chip for default features */ |
5477 | rtl8169_set_features(dev, dev->features); | |
5478 | ||
128735a1 HK |
5479 | rtl_set_d3_pll_down(tp, true); |
5480 | ||
abe8b2f7 | 5481 | jumbo_max = rtl_jumbo_max(tp); |
a8ec173a HK |
5482 | if (jumbo_max) |
5483 | dev->max_mtu = jumbo_max; | |
c7315a95 | 5484 | |
ec9a4088 | 5485 | rtl_set_irq_mask(tp); |
9fa0a8e1 | 5486 | |
254764e5 | 5487 | tp->fw_name = rtl_chip_infos[chipset].fw_name; |
3b6cf25d | 5488 | |
4c45d24a HK |
5489 | tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters), |
5490 | &tp->counters_phys_addr, | |
5491 | GFP_KERNEL); | |
4cf964af HK |
5492 | if (!tp->counters) |
5493 | return -ENOMEM; | |
42020320 | 5494 | |
27dc36ae | 5495 | pci_set_drvdata(pdev, tp); |
19c9ea36 | 5496 | |
f1e911d5 HK |
5497 | rc = r8169_mdio_register(tp); |
5498 | if (rc) | |
4cf964af | 5499 | return rc; |
3b6cf25d | 5500 | |
f1e911d5 HK |
5501 | rc = register_netdev(dev); |
5502 | if (rc) | |
0785dad4 | 5503 | return rc; |
f1e911d5 | 5504 | |
93882c6f HK |
5505 | netdev_info(dev, "%s, %pM, XID %03x, IRQ %d\n", |
5506 | rtl_chip_infos[chipset].name, dev->dev_addr, xid, | |
5507 | pci_irq_vector(pdev, 0)); | |
abe8b2f7 | 5508 | |
a8ec173a | 5509 | if (jumbo_max) |
93882c6f HK |
5510 | netdev_info(dev, "jumbo features [frames: %d bytes, tx checksumming: %s]\n", |
5511 | jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ? | |
5512 | "ok" : "ko"); | |
3b6cf25d | 5513 | |
e0d38b58 | 5514 | if (tp->dash_type != RTL_DASH_NONE) { |
a38b7fbf | 5515 | netdev_info(dev, "DASH enabled\n"); |
3b6cf25d | 5516 | rtl8168_driver_start(tp); |
a38b7fbf | 5517 | } |
3b6cf25d | 5518 | |
a92a0849 HK |
5519 | if (pci_dev_run_wake(pdev)) |
5520 | pm_runtime_put_sync(&pdev->dev); | |
5521 | ||
4c45d24a | 5522 | return 0; |
3b6cf25d FR |
5523 | } |
5524 | ||
1da177e4 | 5525 | static struct pci_driver rtl8169_pci_driver = { |
7cb7541a | 5526 | .name = KBUILD_MODNAME, |
1da177e4 | 5527 | .id_table = rtl8169_pci_tbl, |
3b6cf25d | 5528 | .probe = rtl_init_one, |
baf63293 | 5529 | .remove = rtl_remove_one, |
1765f95d | 5530 | .shutdown = rtl_shutdown, |
80a2a40b | 5531 | .driver.pm = pm_ptr(&rtl8169_pm_ops), |
1da177e4 LT |
5532 | }; |
5533 | ||
3eeb7da9 | 5534 | module_pci_driver(rtl8169_pci_driver); |