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r8169: remove fiddling with the PCIe max read request size
[mirror_ubuntu-focal-kernel.git] / drivers / net / ethernet / realtek / r8169_main.c
CommitLineData
09c434b8 1// SPDX-License-Identifier: GPL-2.0-only
1da177e4 2/*
07d3f51f
FR		 3 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 *
5 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
7 * Copyright (c) a lot of people too. Please respect their work.
8 *
9 * See MAINTAINERS file for support contact information.
1da177e4
LT		 10 */
11
12#include <linux/module.h>
13#include <linux/moduleparam.h>
14#include <linux/pci.h>
15#include <linux/netdevice.h>
16#include <linux/etherdevice.h>
c2f6f3ee 17#include <linux/clk.h>
1da177e4
LT		 18#include <linux/delay.h>
19#include <linux/ethtool.h>
f1e911d5 20#include <linux/phy.h>
1da177e4
LT		 21#include <linux/if_vlan.h>
22#include <linux/crc32.h>
23#include <linux/in.h>
098b01ad 24#include <linux/io.h>
1da177e4
LT		 25#include <linux/ip.h>
26#include <linux/tcp.h>
a6b7a407 27#include <linux/interrupt.h>
1da177e4 28#include <linux/dma-mapping.h>
e1759441 29#include <linux/pm_runtime.h>
70c71606 30#include <linux/prefetch.h>
e974604b 31#include <linux/ipv6.h>
32#include <net/ip6_checksum.h>
1da177e4 33
8197f9d2
HK		 34#include "r8169_firmware.h"
35
1da177e4 36#define MODULENAME "r8169"
1da177e4 37
bca03d5f 38#define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
39#define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
01dc7fec 40#define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
41#define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
70090424 42#define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
c2218925
HW		 43#define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
44#define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
5a5e4443 45#define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
7e18dca1 46#define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
b3d7b2f2 47#define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
45dd95c4 48#define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw"
5598bfe5 49#define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
58152cd4 50#define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw"
beb330a4 51#define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw"
57538c4a 52#define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw"
6e1d0b89
CHL		 53#define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw"
54#define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw"
6e526a7f 55#define FIRMWARE_8168FP_3 "rtl_nic/rtl8168fp-3.fw"
6e1d0b89
CHL		 56#define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw"
57#define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw"
02bf642b 58#define FIRMWARE_8125A_3 "rtl_nic/rtl8125a-3.fw"
bca03d5f 59
b57b7e5a 60#define R8169_MSG_DEFAULT \
f0e837d9 61 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 62
1da177e4
LT		 63/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
64 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
81cd17a4 65#define MC_FILTER_LIMIT 32
1da177e4 66
aee77e4a 67#define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
1da177e4
LT		 68#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
69
70#define R8169_REGS_SIZE 256
1d0254dd 71#define R8169_RX_BUF_SIZE (SZ_16K - 1)
1da177e4 72#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
9fba0812 73#define NUM_RX_DESC 256U /* Number of Rx descriptor registers */
1da177e4
LT		 74#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
75#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
76
145a40e8
HK		 77#define RTL_CFG_NO_GBIT 1
78
1da177e4 79/* write/read MMIO register */
1ef7286e
AS		 80#define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg))
81#define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
82#define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
83#define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg))
84#define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg))
85#define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg))
1da177e4
LT		 86
87enum mac_version {
e9588eb9 88 /* support for ancient RTL_GIGA_MAC_VER_01 has been removed */
85bffe6c
FR		 89 RTL_GIGA_MAC_VER_02,
90 RTL_GIGA_MAC_VER_03,
91 RTL_GIGA_MAC_VER_04,
92 RTL_GIGA_MAC_VER_05,
93 RTL_GIGA_MAC_VER_06,
94 RTL_GIGA_MAC_VER_07,
95 RTL_GIGA_MAC_VER_08,
96 RTL_GIGA_MAC_VER_09,
97 RTL_GIGA_MAC_VER_10,
98 RTL_GIGA_MAC_VER_11,
99 RTL_GIGA_MAC_VER_12,
100 RTL_GIGA_MAC_VER_13,
101 RTL_GIGA_MAC_VER_14,
102 RTL_GIGA_MAC_VER_15,
103 RTL_GIGA_MAC_VER_16,
104 RTL_GIGA_MAC_VER_17,
105 RTL_GIGA_MAC_VER_18,
106 RTL_GIGA_MAC_VER_19,
107 RTL_GIGA_MAC_VER_20,
108 RTL_GIGA_MAC_VER_21,
109 RTL_GIGA_MAC_VER_22,
110 RTL_GIGA_MAC_VER_23,
111 RTL_GIGA_MAC_VER_24,
112 RTL_GIGA_MAC_VER_25,
113 RTL_GIGA_MAC_VER_26,
114 RTL_GIGA_MAC_VER_27,
115 RTL_GIGA_MAC_VER_28,
116 RTL_GIGA_MAC_VER_29,
117 RTL_GIGA_MAC_VER_30,
118 RTL_GIGA_MAC_VER_31,
119 RTL_GIGA_MAC_VER_32,
120 RTL_GIGA_MAC_VER_33,
70090424 121 RTL_GIGA_MAC_VER_34,
c2218925
HW		 122 RTL_GIGA_MAC_VER_35,
123 RTL_GIGA_MAC_VER_36,
7e18dca1 124 RTL_GIGA_MAC_VER_37,
b3d7b2f2 125 RTL_GIGA_MAC_VER_38,
5598bfe5 126 RTL_GIGA_MAC_VER_39,
c558386b
HW		 127 RTL_GIGA_MAC_VER_40,
128 RTL_GIGA_MAC_VER_41,
57538c4a 129 RTL_GIGA_MAC_VER_42,
58152cd4 130 RTL_GIGA_MAC_VER_43,
45dd95c4 131 RTL_GIGA_MAC_VER_44,
6e1d0b89
CHL		 132 RTL_GIGA_MAC_VER_45,
133 RTL_GIGA_MAC_VER_46,
134 RTL_GIGA_MAC_VER_47,
135 RTL_GIGA_MAC_VER_48,
935e2218
CHL		 136 RTL_GIGA_MAC_VER_49,
137 RTL_GIGA_MAC_VER_50,
138 RTL_GIGA_MAC_VER_51,
2e13d773 139 RTL_GIGA_MAC_VER_52,
f1bce4ad
HK		 140 RTL_GIGA_MAC_VER_60,
141 RTL_GIGA_MAC_VER_61,
76719ee2 142 RTL_GIGA_MAC_NONE
1da177e4
LT		 143};
144
d58d46b5
FR		 145#define JUMBO_1K ETH_DATA_LEN
146#define JUMBO_4K (4*1024 - ETH_HLEN - 2)
147#define JUMBO_6K (6*1024 - ETH_HLEN - 2)
148#define JUMBO_7K (7*1024 - ETH_HLEN - 2)
149#define JUMBO_9K (9*1024 - ETH_HLEN - 2)
150
3c6bee1d 151static const struct {
1da177e4 152 const char *name;
953a12cc 153 const char *fw_name;
85bffe6c
FR		 154} rtl_chip_infos[] = {
155 /* PCI devices. */
abe8b2f7
HK		 156 [RTL_GIGA_MAC_VER_02] = {"RTL8169s" },
157 [RTL_GIGA_MAC_VER_03] = {"RTL8110s" },
158 [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb" },
159 [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc" },
160 [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc" },
85bffe6c 161 /* PCI-E devices. */
abe8b2f7
HK		 162 [RTL_GIGA_MAC_VER_07] = {"RTL8102e" },
163 [RTL_GIGA_MAC_VER_08] = {"RTL8102e" },
9e0773c3 164 [RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e" },
abe8b2f7
HK		 165 [RTL_GIGA_MAC_VER_10] = {"RTL8101e" },
166 [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b" },
167 [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b" },
168 [RTL_GIGA_MAC_VER_13] = {"RTL8101e" },
169 [RTL_GIGA_MAC_VER_14] = {"RTL8100e" },
170 [RTL_GIGA_MAC_VER_15] = {"RTL8100e" },
171 [RTL_GIGA_MAC_VER_16] = {"RTL8101e" },
172 [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b" },
173 [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp" },
174 [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c" },
175 [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c" },
176 [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c" },
177 [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c" },
178 [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp" },
179 [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp" },
180 [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d", FIRMWARE_8168D_1},
181 [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d", FIRMWARE_8168D_2},
182 [RTL_GIGA_MAC_VER_27] = {"RTL8168dp/8111dp" },
183 [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp" },
184 [RTL_GIGA_MAC_VER_29] = {"RTL8105e", FIRMWARE_8105E_1},
185 [RTL_GIGA_MAC_VER_30] = {"RTL8105e", FIRMWARE_8105E_1},
186 [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp" },
187 [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e", FIRMWARE_8168E_1},
188 [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e", FIRMWARE_8168E_2},
189 [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3},
190 [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f", FIRMWARE_8168F_1},
191 [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f", FIRMWARE_8168F_2},
192 [RTL_GIGA_MAC_VER_37] = {"RTL8402", FIRMWARE_8402_1 },
193 [RTL_GIGA_MAC_VER_38] = {"RTL8411", FIRMWARE_8411_1 },
194 [RTL_GIGA_MAC_VER_39] = {"RTL8106e", FIRMWARE_8106E_1},
195 [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g", FIRMWARE_8168G_2},
196 [RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g" },
9e0773c3
HK		 197 [RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu", FIRMWARE_8168G_3},
198 [RTL_GIGA_MAC_VER_43] = {"RTL8106eus", FIRMWARE_8106E_2},
199 [RTL_GIGA_MAC_VER_44] = {"RTL8411b", FIRMWARE_8411_2 },
abe8b2f7
HK		 200 [RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h", FIRMWARE_8168H_1},
201 [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h", FIRMWARE_8168H_2},
202 [RTL_GIGA_MAC_VER_47] = {"RTL8107e", FIRMWARE_8107E_1},
203 [RTL_GIGA_MAC_VER_48] = {"RTL8107e", FIRMWARE_8107E_2},
204 [RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep" },
205 [RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep" },
206 [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep" },
6e526a7f 207 [RTL_GIGA_MAC_VER_52] = {"RTL8168fp/RTL8117", FIRMWARE_8168FP_3},
f1bce4ad 208 [RTL_GIGA_MAC_VER_60] = {"RTL8125" },
02bf642b 209 [RTL_GIGA_MAC_VER_61] = {"RTL8125", FIRMWARE_8125A_3},
953a12cc
FR		 210};
211
9baa3c34 212static const struct pci_device_id rtl8169_pci_tbl[] = {
145a40e8
HK		 213 { PCI_VDEVICE(REALTEK, 0x2502) },
214 { PCI_VDEVICE(REALTEK, 0x2600) },
215 { PCI_VDEVICE(REALTEK, 0x8129) },
216 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_NO_GBIT },
217 { PCI_VDEVICE(REALTEK, 0x8161) },
218 { PCI_VDEVICE(REALTEK, 0x8167) },
219 { PCI_VDEVICE(REALTEK, 0x8168) },
220 { PCI_VDEVICE(NCUBE, 0x8168) },
221 { PCI_VDEVICE(REALTEK, 0x8169) },
6f0d3088 222 { PCI_VENDOR_ID_DLINK, 0x4300,
145a40e8 223 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 },
9d9f3fba
HK		 224 { PCI_VDEVICE(DLINK, 0x4300) },
225 { PCI_VDEVICE(DLINK, 0x4302) },
226 { PCI_VDEVICE(AT, 0xc107) },
227 { PCI_VDEVICE(USR, 0x0116) },
228 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 },
229 { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 },
f1bce4ad
HK		 230 { PCI_VDEVICE(REALTEK, 0x8125) },
231 { PCI_VDEVICE(REALTEK, 0x3000) },
6f0d3088 232 {}
1da177e4
LT		 233};
234
235MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
236
b57b7e5a
SH		 237static struct {
238 u32 msg_enable;
239} debug = { -1 };
1da177e4 240
07d3f51f
FR		 241enum rtl_registers {
242 MAC0 = 0, /* Ethernet hardware address. */
773d2021 243 MAC4 = 4,
07d3f51f
FR		 244 MAR0 = 8, /* Multicast filter. */
245 CounterAddrLow = 0x10,
246 CounterAddrHigh = 0x14,
247 TxDescStartAddrLow = 0x20,
248 TxDescStartAddrHigh = 0x24,
249 TxHDescStartAddrLow = 0x28,
250 TxHDescStartAddrHigh = 0x2c,
251 FLASH = 0x30,
252 ERSR = 0x36,
253 ChipCmd = 0x37,
254 TxPoll = 0x38,
255 IntrMask = 0x3c,
256 IntrStatus = 0x3e,
4f6b00e5 257
07d3f51f 258 TxConfig = 0x40,
4f6b00e5
HW		 259#define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
260#define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
2b7b4318 261
4f6b00e5
HW		 262 RxConfig = 0x44,
263#define RX128_INT_EN (1 << 15) /* 8111c and later */
264#define RX_MULTI_EN (1 << 14) /* 8111c only */
265#define RXCFG_FIFO_SHIFT 13
266 /* No threshold before first PCI xfer */
267#define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
beb330a4 268#define RX_EARLY_OFF (1 << 11)
4f6b00e5
HW		 269#define RXCFG_DMA_SHIFT 8
270 /* Unlimited maximum PCI burst. */
271#define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
2b7b4318 272
07d3f51f
FR		 273 RxMissed = 0x4c,
274 Cfg9346 = 0x50,
275 Config0 = 0x51,
276 Config1 = 0x52,
277 Config2 = 0x53,
d387b427
FR		 278#define PME_SIGNAL (1 << 5) /* 8168c and later */
279
07d3f51f
FR		 280 Config3 = 0x54,
281 Config4 = 0x55,
282 Config5 = 0x56,
07d3f51f 283 PHYAR = 0x60,
07d3f51f
FR		 284 PHYstatus = 0x6c,
285 RxMaxSize = 0xda,
286 CPlusCmd = 0xe0,
287 IntrMitigate = 0xe2,
50970831
FR		 288
289#define RTL_COALESCE_MASK 0x0f
290#define RTL_COALESCE_SHIFT 4
291#define RTL_COALESCE_T_MAX (RTL_COALESCE_MASK)
292#define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_MASK << 2)
293
07d3f51f
FR		 294 RxDescAddrLow = 0xe4,
295 RxDescAddrHigh = 0xe8,
f0298f81 296 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
297
298#define NoEarlyTx 0x3f /* Max value : no early transmit. */
299
300 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
301
302#define TxPacketMax (8064 >> 7)
3090bd9a 303#define EarlySize 0x27
f0298f81 304
07d3f51f
FR		 305 FuncEvent = 0xf0,
306 FuncEventMask = 0xf4,
307 FuncPresetState = 0xf8,
935e2218
CHL		 308 IBCR0 = 0xf8,
309 IBCR2 = 0xf9,
310 IBIMR0 = 0xfa,
311 IBISR0 = 0xfb,
07d3f51f 312 FuncForceEvent = 0xfc,
1da177e4
LT		 313};
314
f162a5d1
FR		 315enum rtl8168_8101_registers {
316 CSIDR = 0x64,
317 CSIAR = 0x68,
318#define CSIAR_FLAG 0x80000000
319#define CSIAR_WRITE_CMD 0x80000000
ff1d7331
HK		 320#define CSIAR_BYTE_ENABLE 0x0000f000
321#define CSIAR_ADDR_MASK 0x00000fff
065c27c1 322 PMCH = 0x6f,
f162a5d1
FR		 323 EPHYAR = 0x80,
324#define EPHYAR_FLAG 0x80000000
325#define EPHYAR_WRITE_CMD 0x80000000
326#define EPHYAR_REG_MASK 0x1f
327#define EPHYAR_REG_SHIFT 16
328#define EPHYAR_DATA_MASK 0xffff
5a5e4443 329 DLLPR = 0xd0,
4f6b00e5 330#define PFM_EN (1 << 6)
6e1d0b89 331#define TX_10M_PS_EN (1 << 7)
f162a5d1
FR		 332 DBG_REG = 0xd1,
333#define FIX_NAK_1 (1 << 4)
334#define FIX_NAK_2 (1 << 3)
5a5e4443
HW		 335 TWSI = 0xd2,
336 MCU = 0xd3,
4f6b00e5 337#define NOW_IS_OOB (1 << 7)
c558386b
HW		 338#define TX_EMPTY (1 << 5)
339#define RX_EMPTY (1 << 4)
340#define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
5a5e4443
HW		 341#define EN_NDP (1 << 3)
342#define EN_OOB_RESET (1 << 2)
c558386b 343#define LINK_LIST_RDY (1 << 1)
daf9df6d 344 EFUSEAR = 0xdc,
345#define EFUSEAR_FLAG 0x80000000
346#define EFUSEAR_WRITE_CMD 0x80000000
347#define EFUSEAR_READ_CMD 0x00000000
348#define EFUSEAR_REG_MASK 0x03ff
349#define EFUSEAR_REG_SHIFT 8
350#define EFUSEAR_DATA_MASK 0xff
6e1d0b89
CHL		 351 MISC_1 = 0xf2,
352#define PFM_D3COLD_EN (1 << 6)
f162a5d1
FR		 353};
354
c0e45c1c 355enum rtl8168_registers {
4f6b00e5
HW		 356 LED_FREQ = 0x1a,
357 EEE_LED = 0x1b,
b646d900 358 ERIDR = 0x70,
359 ERIAR = 0x74,
360#define ERIAR_FLAG 0x80000000
361#define ERIAR_WRITE_CMD 0x80000000
362#define ERIAR_READ_CMD 0x00000000
363#define ERIAR_ADDR_BYTE_ALIGN 4
b646d900 364#define ERIAR_TYPE_SHIFT 16
4f6b00e5
HW		 365#define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
366#define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
367#define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
935e2218 368#define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT)
4f6b00e5
HW		 369#define ERIAR_MASK_SHIFT 12
370#define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
371#define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
6e1d0b89 372#define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT)
c558386b 373#define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
4f6b00e5 374#define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
c0e45c1c 375 EPHY_RXER_NUM = 0x7c,
376 OCPDR = 0xb0, /* OCP GPHY access */
377#define OCPDR_WRITE_CMD 0x80000000
378#define OCPDR_READ_CMD 0x00000000
379#define OCPDR_REG_MASK 0x7f
380#define OCPDR_GPHY_REG_SHIFT 16
381#define OCPDR_DATA_MASK 0xffff
382 OCPAR = 0xb4,
383#define OCPAR_FLAG 0x80000000
384#define OCPAR_GPHY_WRITE_CMD 0x8000f060
385#define OCPAR_GPHY_READ_CMD 0x0000f060
c558386b 386 GPHY_OCP = 0xb8,
01dc7fec 387 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
388 MISC = 0xf0, /* 8168e only. */
cecb5fd7 389#define TXPLA_RST (1 << 29)
5598bfe5 390#define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
4f6b00e5 391#define PWM_EN (1 << 22)
c558386b 392#define RXDV_GATED_EN (1 << 19)
5598bfe5 393#define EARLY_TALLY_EN (1 << 16)
c0e45c1c 394};
395
f1bce4ad
HK		 396enum rtl8125_registers {
397 IntrMask_8125 = 0x38,
398 IntrStatus_8125 = 0x3c,
399 TxPoll_8125 = 0x90,
400 MAC0_BKP = 0x19e0,
401};
402
403#define RX_VLAN_INNER_8125 BIT(22)
404#define RX_VLAN_OUTER_8125 BIT(23)
405#define RX_VLAN_8125 (RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125)
406
407#define RX_FETCH_DFLT_8125 (8 << 27)
408
07d3f51f 409enum rtl_register_content {
1da177e4 410 /* InterruptStatusBits */
07d3f51f
FR		 411 SYSErr = 0x8000,
412 PCSTimeout = 0x4000,
413 SWInt = 0x0100,
414 TxDescUnavail = 0x0080,
415 RxFIFOOver = 0x0040,
416 LinkChg = 0x0020,
417 RxOverflow = 0x0010,
418 TxErr = 0x0008,
419 TxOK = 0x0004,
420 RxErr = 0x0002,
421 RxOK = 0x0001,
1da177e4
LT		 422
423 /* RxStatusDesc */
9dccf611
FR		 424 RxRWT = (1 << 22),
425 RxRES = (1 << 21),
426 RxRUNT = (1 << 20),
427 RxCRC = (1 << 19),
1da177e4
LT		 428
429 /* ChipCmdBits */
4f6b00e5 430 StopReq = 0x80,
07d3f51f
FR		 431 CmdReset = 0x10,
432 CmdRxEnb = 0x08,
433 CmdTxEnb = 0x04,
434 RxBufEmpty = 0x01,
1da177e4 435
275391a4
FR		 436 /* TXPoll register p.5 */
437 HPQ = 0x80, /* Poll cmd on the high prio queue */
438 NPQ = 0x40, /* Poll cmd on the low prio queue */
439 FSWInt = 0x01, /* Forced software interrupt */
440
1da177e4 441 /* Cfg9346Bits */
07d3f51f
FR		 442 Cfg9346_Lock = 0x00,
443 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 444
445 /* rx_mode_bits */
07d3f51f
FR		 446 AcceptErr = 0x20,
447 AcceptRunt = 0x10,
448 AcceptBroadcast = 0x08,
449 AcceptMulticast = 0x04,
450 AcceptMyPhys = 0x02,
451 AcceptAllPhys = 0x01,
1687b566 452#define RX_CONFIG_ACCEPT_MASK 0x3f
1da177e4 453
1da177e4
LT		 454 /* TxConfigBits */
455 TxInterFrameGapShift = 24,
456 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
457
5d06a99f 458 /* Config1 register p.24 */
f162a5d1
FR		 459 LEDS1 = (1 << 7),
460 LEDS0 = (1 << 6),
f162a5d1
FR		 461 Speed_down = (1 << 4),
462 MEMMAP = (1 << 3),
463 IOMAP = (1 << 2),
464 VPD = (1 << 1),
5d06a99f
FR		 465 PMEnable = (1 << 0), /* Power Management Enable */
466
6dccd16b 467 /* Config2 register p. 25 */
57538c4a 468 ClkReqEn = (1 << 7), /* Clock Request Enable */
2ca6cf06 469 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
6dccd16b
FR		 470 PCI_Clock_66MHz = 0x01,
471 PCI_Clock_33MHz = 0x00,
472
61a4dcc2
FR		 473 /* Config3 register p.25 */
474 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
475 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
d58d46b5 476 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
b51ecea8 477 Rdy_to_L23 = (1 << 1), /* L23 Enable */
f162a5d1 478 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
61a4dcc2 479
d58d46b5
FR		 480 /* Config4 register */
481 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
482
5d06a99f 483 /* Config5 register p.27 */
61a4dcc2
FR		 484 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
485 MWF = (1 << 5), /* Accept Multicast wakeup frame */
486 UWF = (1 << 4), /* Accept Unicast wakeup frame */
cecb5fd7 487 Spi_en = (1 << 3),
61a4dcc2 488 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f 489 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
57538c4a 490 ASPM_en = (1 << 0), /* ASPM enable */
5d06a99f 491
1da177e4 492 /* CPlusCmd p.31 */
f162a5d1
FR		 493 EnableBist = (1 << 15), // 8168 8101
494 Mac_dbgo_oe = (1 << 14), // 8168 8101
495 Normal_mode = (1 << 13), // unused
496 Force_half_dup = (1 << 12), // 8168 8101
497 Force_rxflow_en = (1 << 11), // 8168 8101
498 Force_txflow_en = (1 << 10), // 8168 8101
499 Cxpl_dbg_sel = (1 << 9), // 8168 8101
500 ASF = (1 << 8), // 8168 8101
501 PktCntrDisable = (1 << 7), // 8168 8101
502 Mac_dbgo_sel = 0x001c, // 8168
1da177e4
LT		 503 RxVlan = (1 << 6),
504 RxChkSum = (1 << 5),
505 PCIDAC = (1 << 4),
506 PCIMulRW = (1 << 3),
9a3c81fa 507#define INTT_MASK GENMASK(1, 0)
bc73241e 508#define CPCMD_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
1da177e4
LT		 509
510 /* rtl8169_PHYstatus */
07d3f51f
FR		 511 TBI_Enable = 0x80,
512 TxFlowCtrl = 0x40,
513 RxFlowCtrl = 0x20,
514 _1000bpsF = 0x10,
515 _100bps = 0x08,
516 _10bps = 0x04,
517 LinkStatus = 0x02,
518 FullDup = 0x01,
1da177e4 519
6e85d5ad
CV		 520 /* ResetCounterCommand */
521 CounterReset = 0x1,
522
d4a3a0fc 523 /* DumpCounterCommand */
07d3f51f 524 CounterDump = 0x8,
6e1d0b89
CHL		 525
526 /* magic enable v2 */
527 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */
1da177e4
LT		 528};
529
2b7b4318
FR		 530enum rtl_desc_bit {
531 /* First doubleword. */
1da177e4
LT		 532 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
533 RingEnd = (1 << 30), /* End of descriptor ring */
534 FirstFrag = (1 << 29), /* First segment of a packet */
535 LastFrag = (1 << 28), /* Final segment of a packet */
2b7b4318
FR		 536};
537
538/* Generic case. */
539enum rtl_tx_desc_bit {
540 /* First doubleword. */
541 TD_LSO = (1 << 27), /* Large Send Offload */
542#define TD_MSS_MAX 0x07ffu /* MSS value */
1da177e4 543
2b7b4318
FR		 544 /* Second doubleword. */
545 TxVlanTag = (1 << 17), /* Add VLAN tag */
546};
547
548/* 8169, 8168b and 810x except 8102e. */
549enum rtl_tx_desc_bit_0 {
550 /* First doubleword. */
551#define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
552 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
553 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
554 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
555};
556
557/* 8102e, 8168c and beyond. */
558enum rtl_tx_desc_bit_1 {
bdfa4ed6 559 /* First doubleword. */
560 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */
e974604b 561 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */
bdfa4ed6 562#define GTTCPHO_SHIFT 18
e64e0c89 563#define GTTCPHO_MAX 0x7f
bdfa4ed6 564
2b7b4318 565 /* Second doubleword. */
e974604b 566#define TCPHO_SHIFT 18
e64e0c89 567#define TCPHO_MAX 0x3ff
2b7b4318 568#define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
e974604b 569 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */
570 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */
2b7b4318
FR		 571 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
572 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
573};
1da177e4 574
2b7b4318 575enum rtl_rx_desc_bit {
1da177e4
LT		 576 /* Rx private */
577 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
9b60047a 578 PID0 = (1 << 17), /* Protocol ID bit 0/2 */
1da177e4
LT		 579
580#define RxProtoUDP (PID1)
581#define RxProtoTCP (PID0)
582#define RxProtoIP (PID1 | PID0)
583#define RxProtoMask RxProtoIP
584
585 IPFail = (1 << 16), /* IP checksum failed */
586 UDPFail = (1 << 15), /* UDP/IP checksum failed */
587 TCPFail = (1 << 14), /* TCP/IP checksum failed */
588 RxVlanTag = (1 << 16), /* VLAN tag available */
589};
590
591#define RsvdMask 0x3fffc000
592
0170d594
HK		 593#define RTL_GSO_MAX_SIZE_V1 32000
594#define RTL_GSO_MAX_SEGS_V1 24
595#define RTL_GSO_MAX_SIZE_V2 64000
596#define RTL_GSO_MAX_SEGS_V2 64
597
1da177e4 598struct TxDesc {
6cccd6e7
REB		 599 __le32 opts1;
600 __le32 opts2;
601 __le64 addr;
1da177e4
LT		 602};
603
604struct RxDesc {
6cccd6e7
REB		 605 __le32 opts1;
606 __le32 opts2;
607 __le64 addr;
1da177e4
LT		 608};
609
610struct ring_info {
611 struct sk_buff *skb;
612 u32 len;
1da177e4
LT		 613};
614
355423d0
IV		 615struct rtl8169_counters {
616 __le64 tx_packets;
617 __le64 rx_packets;
618 __le64 tx_errors;
619 __le32 rx_errors;
620 __le16 rx_missed;
621 __le16 align_errors;
622 __le32 tx_one_collision;
623 __le32 tx_multi_collision;
624 __le64 rx_unicast;
625 __le64 rx_broadcast;
626 __le32 rx_multicast;
627 __le16 tx_aborted;
628 __le16 tx_underun;
629};
630
6e85d5ad
CV		 631struct rtl8169_tc_offsets {
632 bool inited;
633 __le64 tx_errors;
634 __le32 tx_multi_collision;
6e85d5ad
CV		 635 __le16 tx_aborted;
636};
637
da78dbff 638enum rtl_flag {
6ad56901 639 RTL_FLAG_TASK_ENABLED = 0,
da78dbff 640 RTL_FLAG_TASK_RESET_PENDING,
da78dbff
FR		 641 RTL_FLAG_MAX
642};
643
8027aa24
JW		 644struct rtl8169_stats {
645 u64 packets;
646 u64 bytes;
647 struct u64_stats_sync syncp;
648};
649
1da177e4
LT		 650struct rtl8169_private {
651 void __iomem *mmio_addr; /* memory map physical address */
cecb5fd7 652 struct pci_dev *pci_dev;
c4028958 653 struct net_device *dev;
703732f0 654 struct phy_device *phydev;
bea3348e 655 struct napi_struct napi;
b57b7e5a 656 u32 msg_enable;
76719ee2 657 enum mac_version mac_version;
1da177e4
LT		 658 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
659 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
1da177e4 660 u32 dirty_tx;
8027aa24
JW		 661 struct rtl8169_stats rx_stats;
662 struct rtl8169_stats tx_stats;
1da177e4
LT		 663 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
664 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
665 dma_addr_t TxPhyAddr;
666 dma_addr_t RxPhyAddr;
32879f00 667 struct page *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
1da177e4 668 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
1da177e4 669 u16 cp_cmd;
c1d532d2 670 u32 irq_mask;
c2f6f3ee 671 struct clk *clk;
c0e45c1c 672
4422bcd4 673 struct {
da78dbff
FR		 674 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
675 struct mutex mutex;
4422bcd4
FR		 676 struct work_struct work;
677 } wk;
678
c8248c6c 679 unsigned irq_enabled:1;
f7ffa9ae 680 unsigned supports_gmii:1;
62b1b3b3 681 unsigned aspm_manageable:1;
42020320
CV		 682 dma_addr_t counters_phys_addr;
683 struct rtl8169_counters *counters;
6e85d5ad 684 struct rtl8169_tc_offsets tc_offset;
e1759441 685 u32 saved_wolopts;
488202f5 686 int eee_adv;
f1e02ed1 687
254764e5 688 const char *fw_name;
8197f9d2 689 struct rtl_fw *rtl_fw;
c558386b
HW		 690
691 u32 ocp_base;
1da177e4
LT		 692};
693
1fcd1658
HK		 694typedef void (*rtl_generic_fct)(struct rtl8169_private *tp);
695
979b6c13 696MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 697MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
b57b7e5a
SH		 698module_param_named(debug, debug.msg_enable, int, 0);
699MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
11287b69 700MODULE_SOFTDEP("pre: realtek");
1da177e4 701MODULE_LICENSE("GPL");
bca03d5f 702MODULE_FIRMWARE(FIRMWARE_8168D_1);
703MODULE_FIRMWARE(FIRMWARE_8168D_2);
01dc7fec 704MODULE_FIRMWARE(FIRMWARE_8168E_1);
705MODULE_FIRMWARE(FIRMWARE_8168E_2);
bbb8af75 706MODULE_FIRMWARE(FIRMWARE_8168E_3);
5a5e4443 707MODULE_FIRMWARE(FIRMWARE_8105E_1);
c2218925
HW		 708MODULE_FIRMWARE(FIRMWARE_8168F_1);
709MODULE_FIRMWARE(FIRMWARE_8168F_2);
7e18dca1 710MODULE_FIRMWARE(FIRMWARE_8402_1);
b3d7b2f2 711MODULE_FIRMWARE(FIRMWARE_8411_1);
45dd95c4 712MODULE_FIRMWARE(FIRMWARE_8411_2);
5598bfe5 713MODULE_FIRMWARE(FIRMWARE_8106E_1);
58152cd4 714MODULE_FIRMWARE(FIRMWARE_8106E_2);
beb330a4 715MODULE_FIRMWARE(FIRMWARE_8168G_2);
57538c4a 716MODULE_FIRMWARE(FIRMWARE_8168G_3);
6e1d0b89
CHL		 717MODULE_FIRMWARE(FIRMWARE_8168H_1);
718MODULE_FIRMWARE(FIRMWARE_8168H_2);
6e526a7f 719MODULE_FIRMWARE(FIRMWARE_8168FP_3);
a3bf5c42
FR		 720MODULE_FIRMWARE(FIRMWARE_8107E_1);
721MODULE_FIRMWARE(FIRMWARE_8107E_2);
02bf642b 722MODULE_FIRMWARE(FIRMWARE_8125A_3);
1da177e4 723
1e1205b7
HK		 724static inline struct device *tp_to_dev(struct rtl8169_private *tp)
725{
726 return &tp->pci_dev->dev;
727}
728
da78dbff
FR		 729static void rtl_lock_work(struct rtl8169_private *tp)
730{
731 mutex_lock(&tp->wk.mutex);
732}
733
734static void rtl_unlock_work(struct rtl8169_private *tp)
735{
736 mutex_unlock(&tp->wk.mutex);
737}
738
df320ed7
HK		 739static void rtl_lock_config_regs(struct rtl8169_private *tp)
740{
741 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
742}
743
744static void rtl_unlock_config_regs(struct rtl8169_private *tp)
745{
746 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
747}
748
f1bce4ad
HK		 749static bool rtl_is_8125(struct rtl8169_private *tp)
750{
751 return tp->mac_version >= RTL_GIGA_MAC_VER_60;
752}
753
9e9f33ba
HK		 754static bool rtl_is_8168evl_up(struct rtl8169_private *tp)
755{
756 return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
c623305b 757 tp->mac_version != RTL_GIGA_MAC_VER_39 &&
2e13d773 758 tp->mac_version <= RTL_GIGA_MAC_VER_52;
9e9f33ba
HK		 759}
760
2e779ddb
HK		 761static bool rtl_supports_eee(struct rtl8169_private *tp)
762{
763 return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
764 tp->mac_version != RTL_GIGA_MAC_VER_37 &&
765 tp->mac_version != RTL_GIGA_MAC_VER_39;
766}
767
ce37115e
HK		 768static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg)
769{
770 int i;
771
772 for (i = 0; i < ETH_ALEN; i++)
773 mac[i] = RTL_R8(tp, reg + i);
774}
775
ffc46952
FR		 776struct rtl_cond {
777 bool (*check)(struct rtl8169_private *);
778 const char *msg;
779};
780
781static void rtl_udelay(unsigned int d)
782{
783 udelay(d);
784}
785
786static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
787 void (*delay)(unsigned int), unsigned int d, int n,
788 bool high)
789{
790 int i;
791
792 for (i = 0; i < n; i++) {
ffc46952
FR		 793 if (c->check(tp) == high)
794 return true;
d1f5050b 795 delay(d);
ffc46952 796 }
82e316ef
FR		 797 netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
798 c->msg, !high, n, d);
ffc46952
FR		 799 return false;
800}
801
802static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
803 const struct rtl_cond *c,
804 unsigned int d, int n)
805{
806 return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
807}
808
809static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
810 const struct rtl_cond *c,
811 unsigned int d, int n)
812{
813 return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
814}
815
816static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
817 const struct rtl_cond *c,
818 unsigned int d, int n)
819{
820 return rtl_loop_wait(tp, c, msleep, d, n, true);
821}
822
823static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
824 const struct rtl_cond *c,
825 unsigned int d, int n)
826{
827 return rtl_loop_wait(tp, c, msleep, d, n, false);
828}
829
830#define DECLARE_RTL_COND(name) \
831static bool name ## _check(struct rtl8169_private *); \
832 \
833static const struct rtl_cond name = { \
834 .check = name ## _check, \
835 .msg = #name \
836}; \
837 \
838static bool name ## _check(struct rtl8169_private *tp)
839
c558386b
HW		 840static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
841{
842 if (reg & 0xffff0001) {
843 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
844 return true;
845 }
846 return false;
847}
848
849DECLARE_RTL_COND(rtl_ocp_gphy_cond)
850{
1ef7286e 851 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
c558386b
HW		 852}
853
854static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
855{
c558386b
HW		 856 if (rtl_ocp_reg_failure(tp, reg))
857 return;
858
1ef7286e 859 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
c558386b
HW		 860
861 rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
862}
863
9b994b4a 864static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
c558386b 865{
c558386b
HW		 866 if (rtl_ocp_reg_failure(tp, reg))
867 return 0;
868
1ef7286e 869 RTL_W32(tp, GPHY_OCP, reg << 15);
c558386b
HW		 870
871 return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
9b994b4a 872 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT;
c558386b
HW		 873}
874
c558386b
HW		 875static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
876{
c558386b
HW		 877 if (rtl_ocp_reg_failure(tp, reg))
878 return;
879
1ef7286e 880 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
c558386b
HW		 881}
882
883static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
884{
c558386b
HW		 885 if (rtl_ocp_reg_failure(tp, reg))
886 return 0;
887
1ef7286e 888 RTL_W32(tp, OCPDR, reg << 15);
c558386b 889
1ef7286e 890 return RTL_R32(tp, OCPDR);
c558386b
HW		 891}
892
ef712ede
HK		 893static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask,
894 u16 set)
895{
896 u16 data = r8168_mac_ocp_read(tp, reg);
897
898 r8168_mac_ocp_write(tp, reg, (data & ~mask) | set);
899}
900
c558386b
HW		 901#define OCP_STD_PHY_BASE 0xa400
902
903static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
904{
905 if (reg == 0x1f) {
906 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
907 return;
908 }
909
910 if (tp->ocp_base != OCP_STD_PHY_BASE)
911 reg -= 0x10;
912
913 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
914}
915
916static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
917{
9c6850fe
HK		 918 if (reg == 0x1f)
919 return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4;
920
c558386b
HW		 921 if (tp->ocp_base != OCP_STD_PHY_BASE)
922 reg -= 0x10;
923
924 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
925}
926
eee3786f 927static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
928{
929 if (reg == 0x1f) {
930 tp->ocp_base = value << 4;
931 return;
932 }
933
934 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
935}
936
937static int mac_mcu_read(struct rtl8169_private *tp, int reg)
938{
939 return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
940}
941
ffc46952
FR		 942DECLARE_RTL_COND(rtl_phyar_cond)
943{
1ef7286e 944 return RTL_R32(tp, PHYAR) & 0x80000000;
ffc46952
FR		 945}
946
24192210 947static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
1da177e4 948{
1ef7286e 949 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
1da177e4 950
ffc46952 951 rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
024a07ba 952 /*
81a95f04
TT		 953 * According to hardware specs a 20us delay is required after write
954 * complete indication, but before sending next command.
024a07ba 955 */
81a95f04 956 udelay(20);
1da177e4
LT		 957}
958
24192210 959static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1da177e4 960{
ffc46952 961 int value;
1da177e4 962
1ef7286e 963 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
1da177e4 964
ffc46952 965 value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
9b994b4a 966 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT;
ffc46952 967
81a95f04
TT		 968 /*
969 * According to hardware specs a 20us delay is required after read
970 * complete indication, but before sending next command.
971 */
972 udelay(20);
973
1da177e4
LT		 974 return value;
975}
976
935e2218
CHL		 977DECLARE_RTL_COND(rtl_ocpar_cond)
978{
1ef7286e 979 return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
935e2218
CHL		 980}
981
24192210 982static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
c0e45c1c 983{
1ef7286e
AS		 984 RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
985 RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD);
986 RTL_W32(tp, EPHY_RXER_NUM, 0);
c0e45c1c 987
ffc46952 988 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
c0e45c1c 989}
990
24192210 991static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
c0e45c1c 992{
24192210
FR		 993 r8168dp_1_mdio_access(tp, reg,
994 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
c0e45c1c 995}
996
24192210 997static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
c0e45c1c 998{
24192210 999 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
c0e45c1c 1000
1001 mdelay(1);
1ef7286e
AS		 1002 RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD);
1003 RTL_W32(tp, EPHY_RXER_NUM, 0);
c0e45c1c 1004
ffc46952 1005 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
9b994b4a 1006 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : -ETIMEDOUT;
c0e45c1c 1007}
1008
e6de30d6 1009#define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
1010
1ef7286e 1011static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
e6de30d6 1012{
1ef7286e 1013 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
e6de30d6 1014}
1015
1ef7286e 1016static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
e6de30d6 1017{
1ef7286e 1018 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
e6de30d6 1019}
1020
24192210 1021static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
e6de30d6 1022{
1ef7286e 1023 r8168dp_2_mdio_start(tp);
e6de30d6 1024
24192210 1025 r8169_mdio_write(tp, reg, value);
e6de30d6 1026
1ef7286e 1027 r8168dp_2_mdio_stop(tp);
e6de30d6 1028}
1029
24192210 1030static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
e6de30d6 1031{
1032 int value;
1033
62bdc8fd
HK		 1034 /* Work around issue with chip reporting wrong PHY ID */
1035 if (reg == MII_PHYSID2)
1036 return 0xc912;
1037
1ef7286e 1038 r8168dp_2_mdio_start(tp);
e6de30d6 1039
24192210 1040 value = r8169_mdio_read(tp, reg);
e6de30d6 1041
1ef7286e 1042 r8168dp_2_mdio_stop(tp);
e6de30d6 1043
1044 return value;
1045}
1046
ce8843ab 1047static void rtl_writephy(struct rtl8169_private *tp, int location, int val)
dacf8154 1048{
5f950523
HK		 1049 switch (tp->mac_version) {
1050 case RTL_GIGA_MAC_VER_27:
1051 r8168dp_1_mdio_write(tp, location, val);
1052 break;
1053 case RTL_GIGA_MAC_VER_28:
1054 case RTL_GIGA_MAC_VER_31:
1055 r8168dp_2_mdio_write(tp, location, val);
1056 break;
f1bce4ad 1057 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_61:
5f950523
HK		 1058 r8168g_mdio_write(tp, location, val);
1059 break;
1060 default:
1061 r8169_mdio_write(tp, location, val);
1062 break;
1063 }
dacf8154
FR		 1064}
1065
4da19633 1066static int rtl_readphy(struct rtl8169_private *tp, int location)
1067{
5f950523
HK		 1068 switch (tp->mac_version) {
1069 case RTL_GIGA_MAC_VER_27:
1070 return r8168dp_1_mdio_read(tp, location);
1071 case RTL_GIGA_MAC_VER_28:
1072 case RTL_GIGA_MAC_VER_31:
1073 return r8168dp_2_mdio_read(tp, location);
f1bce4ad 1074 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_61:
5f950523
HK		 1075 return r8168g_mdio_read(tp, location);
1076 default:
1077 return r8169_mdio_read(tp, location);
1078 }
4da19633 1079}
1080
1081static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1082{
1083 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1084}
1085
76564428 1086static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
daf9df6d 1087{
1088 int val;
1089
4da19633 1090 val = rtl_readphy(tp, reg_addr);
76564428 1091 rtl_writephy(tp, reg_addr, (val & ~m) | p);
daf9df6d 1092}
1093
424f2610
HK		 1094static void r8168g_phy_param(struct phy_device *phydev, u16 parm,
1095 u16 mask, u16 val)
1096{
1097 int oldpage = phy_select_page(phydev, 0x0a43);
1098
1099 __phy_write(phydev, 0x13, parm);
1100 __phy_modify(phydev, 0x14, mask, val);
1101
1102 phy_restore_page(phydev, oldpage, 0);
1103}
1104
ffc46952
FR		 1105DECLARE_RTL_COND(rtl_ephyar_cond)
1106{
1ef7286e 1107 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
ffc46952
FR		 1108}
1109
fdf6fc06 1110static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
dacf8154 1111{
1ef7286e 1112 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
dacf8154
FR		 1113 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1114
ffc46952
FR		 1115 rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1116
1117 udelay(10);
dacf8154
FR		 1118}
1119
fdf6fc06 1120static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
dacf8154 1121{
1ef7286e 1122 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
dacf8154 1123
ffc46952 1124 return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1ef7286e 1125 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
dacf8154
FR		 1126}
1127
5cca2f8a
HK		 1128static void r8168fp_adjust_ocp_cmd(struct rtl8169_private *tp, u32 *cmd, int type)
1129{
1130 /* based on RTL8168FP_OOBMAC_BASE in vendor driver */
1131 if (tp->mac_version == RTL_GIGA_MAC_VER_52 && type == ERIAR_OOB)
1132 *cmd |= 0x7f0 << 18;
1133}
1134
935e2218
CHL		 1135DECLARE_RTL_COND(rtl_eriar_cond)
1136{
1ef7286e 1137 return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
935e2218
CHL		 1138}
1139
724c6fd0
HK		 1140static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1141 u32 val, int type)
133ac40a 1142{
5cca2f8a
HK		 1143 u32 cmd = ERIAR_WRITE_CMD | type | mask | addr;
1144
133ac40a 1145 BUG_ON((addr & 3) || (mask == 0));
1ef7286e 1146 RTL_W32(tp, ERIDR, val);
5cca2f8a
HK		 1147 r8168fp_adjust_ocp_cmd(tp, &cmd, type);
1148 RTL_W32(tp, ERIAR, cmd);
133ac40a 1149
ffc46952 1150 rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
133ac40a
HW		 1151}
1152
724c6fd0
HK		 1153static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1154 u32 val)
1155{
1156 _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC);
1157}
1158
1159static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
133ac40a 1160{
5cca2f8a
HK		 1161 u32 cmd = ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr;
1162
1163 r8168fp_adjust_ocp_cmd(tp, &cmd, type);
1164 RTL_W32(tp, ERIAR, cmd);
133ac40a 1165
ffc46952 1166 return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1ef7286e 1167 RTL_R32(tp, ERIDR) : ~0;
133ac40a
HW		 1168}
1169
724c6fd0
HK		 1170static u32 rtl_eri_read(struct rtl8169_private *tp, int addr)
1171{
1172 return _rtl_eri_read(tp, addr, ERIAR_EXGMAC);
1173}
1174
706123d0 1175static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
724c6fd0 1176 u32 m)
133ac40a
HW		 1177{
1178 u32 val;
1179
724c6fd0
HK		 1180 val = rtl_eri_read(tp, addr);
1181 rtl_eri_write(tp, addr, mask, (val & ~m) | p);
133ac40a
HW		 1182}
1183
e719b3ea
HK		 1184static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 mask,
1185 u32 p)
1186{
1187 rtl_w0w1_eri(tp, addr, mask, p, 0);
1188}
1189
1190static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 mask,
1191 u32 m)
1192{
1193 rtl_w0w1_eri(tp, addr, mask, 0, m);
1194}
1195
935e2218
CHL		 1196static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1197{
1ef7286e 1198 RTL_W32(tp, OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
935e2218 1199 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1ef7286e 1200 RTL_R32(tp, OCPDR) : ~0;
935e2218
CHL		 1201}
1202
1203static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1204{
724c6fd0 1205 return _rtl_eri_read(tp, reg, ERIAR_OOB);
935e2218
CHL		 1206}
1207
935e2218
CHL		 1208static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1209 u32 data)
1210{
1ef7286e
AS		 1211 RTL_W32(tp, OCPDR, data);
1212 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
935e2218
CHL		 1213 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1214}
1215
1216static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1217 u32 data)
1218{
724c6fd0
HK		 1219 _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1220 data, ERIAR_OOB);
935e2218
CHL		 1221}
1222
3c72bf71 1223static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd)
2a9b4d96 1224{
724c6fd0 1225 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd);
2a9b4d96 1226
3c72bf71 1227 r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001);
2a9b4d96
CHL		 1228}
1229
1230#define OOB_CMD_RESET 0x00
1231#define OOB_CMD_DRIVER_START 0x05
1232#define OOB_CMD_DRIVER_STOP 0x06
1233
1234static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1235{
1236 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1237}
1238
3c72bf71 1239DECLARE_RTL_COND(rtl_dp_ocp_read_cond)
2a9b4d96
CHL		 1240{
1241 u16 reg;
1242
1243 reg = rtl8168_get_ocp_reg(tp);
1244
3c72bf71 1245 return r8168dp_ocp_read(tp, 0x0f, reg) & 0x00000800;
2a9b4d96
CHL		 1246}
1247
935e2218 1248DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
2a9b4d96 1249{
3c72bf71 1250 return r8168ep_ocp_read(tp, 0x0f, 0x124) & 0x00000001;
935e2218
CHL		 1251}
1252
1253DECLARE_RTL_COND(rtl_ocp_tx_cond)
1254{
1ef7286e 1255 return RTL_R8(tp, IBISR0) & 0x20;
935e2218 1256}
2a9b4d96 1257
003609da
CHL		 1258static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1259{
1ef7286e 1260 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
086ca23d 1261 rtl_msleep_loop_wait_high(tp, &rtl_ocp_tx_cond, 50, 2000);
1ef7286e
AS		 1262 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1263 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
003609da
CHL		 1264}
1265
935e2218
CHL		 1266static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1267{
3c72bf71
HK		 1268 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START);
1269 rtl_msleep_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10, 10);
2a9b4d96
CHL		 1270}
1271
935e2218 1272static void rtl8168ep_driver_start(struct rtl8169_private *tp)
2a9b4d96 1273{
3c72bf71
HK		 1274 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1275 r8168ep_ocp_write(tp, 0x01, 0x30,
1276 r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01);
935e2218
CHL		 1277 rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1278}
1279
1280static void rtl8168_driver_start(struct rtl8169_private *tp)
1281{
1282 switch (tp->mac_version) {
1283 case RTL_GIGA_MAC_VER_27:
1284 case RTL_GIGA_MAC_VER_28:
1285 case RTL_GIGA_MAC_VER_31:
1286 rtl8168dp_driver_start(tp);
1287 break;
2e13d773 1288 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52:
935e2218
CHL		 1289 rtl8168ep_driver_start(tp);
1290 break;
1291 default:
1292 BUG();
1293 break;
1294 }
1295}
2a9b4d96 1296
935e2218
CHL		 1297static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1298{
3c72bf71
HK		 1299 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1300 rtl_msleep_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10, 10);
2a9b4d96
CHL		 1301}
1302
935e2218
CHL		 1303static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1304{
003609da 1305 rtl8168ep_stop_cmac(tp);
3c72bf71
HK		 1306 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1307 r8168ep_ocp_write(tp, 0x01, 0x30,
1308 r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01);
935e2218
CHL		 1309 rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1310}
1311
1312static void rtl8168_driver_stop(struct rtl8169_private *tp)
1313{
1314 switch (tp->mac_version) {
1315 case RTL_GIGA_MAC_VER_27:
1316 case RTL_GIGA_MAC_VER_28:
1317 case RTL_GIGA_MAC_VER_31:
1318 rtl8168dp_driver_stop(tp);
1319 break;
2e13d773 1320 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52:
935e2218
CHL		 1321 rtl8168ep_driver_stop(tp);
1322 break;
1323 default:
1324 BUG();
1325 break;
1326 }
1327}
1328
9dbe7896 1329static bool r8168dp_check_dash(struct rtl8169_private *tp)
2a9b4d96
CHL		 1330{
1331 u16 reg = rtl8168_get_ocp_reg(tp);
1332
3c72bf71 1333 return !!(r8168dp_ocp_read(tp, 0x0f, reg) & 0x00008000);
2a9b4d96
CHL		 1334}
1335
9dbe7896 1336static bool r8168ep_check_dash(struct rtl8169_private *tp)
935e2218 1337{
3c72bf71 1338 return !!(r8168ep_ocp_read(tp, 0x0f, 0x128) & 0x00000001);
935e2218
CHL		 1339}
1340
9dbe7896 1341static bool r8168_check_dash(struct rtl8169_private *tp)
935e2218
CHL		 1342{
1343 switch (tp->mac_version) {
1344 case RTL_GIGA_MAC_VER_27:
1345 case RTL_GIGA_MAC_VER_28:
1346 case RTL_GIGA_MAC_VER_31:
1347 return r8168dp_check_dash(tp);
2e13d773 1348 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52:
935e2218
CHL		 1349 return r8168ep_check_dash(tp);
1350 default:
9dbe7896 1351 return false;
935e2218
CHL		 1352 }
1353}
1354
4e7e4621
HK		 1355static void rtl_reset_packet_filter(struct rtl8169_private *tp)
1356{
1357 rtl_eri_clear_bits(tp, 0xdc, ERIAR_MASK_0001, BIT(0));
1358 rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_0001, BIT(0));
1359}
1360
ffc46952
FR		 1361DECLARE_RTL_COND(rtl_efusear_cond)
1362{
1ef7286e 1363 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
ffc46952
FR		 1364}
1365
fdf6fc06 1366static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
daf9df6d 1367{
1ef7286e 1368 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
daf9df6d 1369
ffc46952 1370 return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1ef7286e 1371 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
daf9df6d 1372}
1373
c1d532d2
HK		 1374static u32 rtl_get_events(struct rtl8169_private *tp)
1375{
f1bce4ad
HK		 1376 if (rtl_is_8125(tp))
1377 return RTL_R32(tp, IntrStatus_8125);
1378 else
1379 return RTL_R16(tp, IntrStatus);
c1d532d2
HK		 1380}
1381
1382static void rtl_ack_events(struct rtl8169_private *tp, u32 bits)
9085cdfa 1383{
f1bce4ad
HK		 1384 if (rtl_is_8125(tp))
1385 RTL_W32(tp, IntrStatus_8125, bits);
1386 else
1387 RTL_W16(tp, IntrStatus, bits);
9085cdfa
FR		 1388}
1389
1390static void rtl_irq_disable(struct rtl8169_private *tp)
1391{
f1bce4ad
HK		 1392 if (rtl_is_8125(tp))
1393 RTL_W32(tp, IntrMask_8125, 0);
1394 else
1395 RTL_W16(tp, IntrMask, 0);
c8248c6c 1396 tp->irq_enabled = 0;
3e990ff5
FR		 1397}
1398
da78dbff
FR		 1399#define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1400#define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1401#define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1402
fe716f8a 1403static void rtl_irq_enable(struct rtl8169_private *tp)
da78dbff 1404{
c8248c6c 1405 tp->irq_enabled = 1;
f1bce4ad
HK		 1406 if (rtl_is_8125(tp))
1407 RTL_W32(tp, IntrMask_8125, tp->irq_mask);
1408 else
1409 RTL_W16(tp, IntrMask, tp->irq_mask);
da78dbff
FR		 1410}
1411
811fd301 1412static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1da177e4 1413{
9085cdfa 1414 rtl_irq_disable(tp);
c1d532d2 1415 rtl_ack_events(tp, 0xffffffff);
de20e12f 1416 /* PCI commit */
1ef7286e 1417 RTL_R8(tp, ChipCmd);
1da177e4
LT		 1418}
1419
70090424
HW		 1420static void rtl_link_chg_patch(struct rtl8169_private *tp)
1421{
70090424 1422 struct net_device *dev = tp->dev;
703732f0 1423 struct phy_device *phydev = tp->phydev;
70090424
HW		 1424
1425 if (!netif_running(dev))
1426 return;
1427
b3d7b2f2
HW		 1428 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1429 tp->mac_version == RTL_GIGA_MAC_VER_38) {
29a12b49 1430 if (phydev->speed == SPEED_1000) {
724c6fd0
HK		 1431 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1432 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
29a12b49 1433 } else if (phydev->speed == SPEED_100) {
724c6fd0
HK		 1434 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1435 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
70090424 1436 } else {
724c6fd0
HK		 1437 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1438 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
70090424 1439 }
4e7e4621 1440 rtl_reset_packet_filter(tp);
c2218925
HW		 1441 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1442 tp->mac_version == RTL_GIGA_MAC_VER_36) {
29a12b49 1443 if (phydev->speed == SPEED_1000) {
724c6fd0
HK		 1444 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1445 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
c2218925 1446 } else {
724c6fd0
HK		 1447 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1448 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
c2218925 1449 }
7e18dca1 1450 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
29a12b49 1451 if (phydev->speed == SPEED_10) {
724c6fd0
HK		 1452 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02);
1453 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a);
7e18dca1 1454 } else {
724c6fd0 1455 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
7e18dca1 1456 }
70090424
HW		 1457 }
1458}
1459
e1759441
RW		 1460#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1461
e1759441 1462static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
61a4dcc2
FR		 1463{
1464 struct rtl8169_private *tp = netdev_priv(dev);
e1759441 1465
da78dbff 1466 rtl_lock_work(tp);
e1759441 1467 wol->supported = WAKE_ANY;
433f9d0d 1468 wol->wolopts = tp->saved_wolopts;
da78dbff 1469 rtl_unlock_work(tp);
e1759441
RW		 1470}
1471
1472static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1473{
350f7596 1474 static const struct {
61a4dcc2
FR		 1475 u32 opt;
1476 u16 reg;
1477 u8 mask;
1478 } cfg[] = {
61a4dcc2 1479 { WAKE_PHY, Config3, LinkUp },
61a4dcc2
FR		 1480 { WAKE_UCAST, Config5, UWF },
1481 { WAKE_BCAST, Config5, BWF },
1482 { WAKE_MCAST, Config5, MWF },
6e1d0b89
CHL		 1483 { WAKE_ANY, Config5, LanWake },
1484 { WAKE_MAGIC, Config3, MagicPacket }
61a4dcc2 1485 };
f1bce4ad 1486 unsigned int i, tmp = ARRAY_SIZE(cfg);
851e6022 1487 u8 options;
61a4dcc2 1488
df320ed7 1489 rtl_unlock_config_regs(tp);
61a4dcc2 1490
9e9f33ba 1491 if (rtl_is_8168evl_up(tp)) {
f1bce4ad 1492 tmp--;
6e1d0b89 1493 if (wolopts & WAKE_MAGIC)
e719b3ea
HK		 1494 rtl_eri_set_bits(tp, 0x0dc, ERIAR_MASK_0100,
1495 MagicPacket_v2);
6e1d0b89 1496 else
e719b3ea
HK		 1497 rtl_eri_clear_bits(tp, 0x0dc, ERIAR_MASK_0100,
1498 MagicPacket_v2);
f1bce4ad
HK		 1499 } else if (rtl_is_8125(tp)) {
1500 tmp--;
1501 if (wolopts & WAKE_MAGIC)
1502 r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0));
1503 else
1504 r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0);
6e1d0b89
CHL		 1505 }
1506
1507 for (i = 0; i < tmp; i++) {
1ef7286e 1508 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
e1759441 1509 if (wolopts & cfg[i].opt)
61a4dcc2 1510 options |= cfg[i].mask;
1ef7286e 1511 RTL_W8(tp, cfg[i].reg, options);
61a4dcc2
FR		 1512 }
1513
851e6022 1514 switch (tp->mac_version) {
edcde3ee 1515 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
1ef7286e 1516 options = RTL_R8(tp, Config1) & ~PMEnable;
851e6022
FR		 1517 if (wolopts)
1518 options |= PMEnable;
1ef7286e 1519 RTL_W8(tp, Config1, options);
851e6022 1520 break;
edcde3ee
HK		 1521 case RTL_GIGA_MAC_VER_34:
1522 case RTL_GIGA_MAC_VER_37:
2e13d773 1523 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_52:
1ef7286e 1524 options = RTL_R8(tp, Config2) & ~PME_SIGNAL;
d387b427
FR		 1525 if (wolopts)
1526 options |= PME_SIGNAL;
1ef7286e 1527 RTL_W8(tp, Config2, options);
851e6022 1528 break;
edcde3ee
HK		 1529 default:
1530 break;
851e6022
FR		 1531 }
1532
df320ed7 1533 rtl_lock_config_regs(tp);
3bd82645
HK		 1534
1535 device_set_wakeup_enable(tp_to_dev(tp), wolopts);
51989384 1536 tp->dev->wol_enabled = wolopts ? 1 : 0;
e1759441
RW		 1537}
1538
1539static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1540{
1541 struct rtl8169_private *tp = netdev_priv(dev);
1e1205b7 1542 struct device *d = tp_to_dev(tp);
5fa80a32 1543
2f533f6b
HK		 1544 if (wol->wolopts & ~WAKE_ANY)
1545 return -EINVAL;
1546
5fa80a32 1547 pm_runtime_get_noresume(d);
e1759441 1548
da78dbff 1549 rtl_lock_work(tp);
61a4dcc2 1550
2f533f6b 1551 tp->saved_wolopts = wol->wolopts;
433f9d0d 1552
5fa80a32 1553 if (pm_runtime_active(d))
433f9d0d 1554 __rtl8169_set_wol(tp, tp->saved_wolopts);
da78dbff
FR		 1555
1556 rtl_unlock_work(tp);
61a4dcc2 1557
5fa80a32
CHL		 1558 pm_runtime_put_noidle(d);
1559
61a4dcc2
FR		 1560 return 0;
1561}
1562
1da177e4
LT		 1563static void rtl8169_get_drvinfo(struct net_device *dev,
1564 struct ethtool_drvinfo *info)
1565{
1566 struct rtl8169_private *tp = netdev_priv(dev);
b6ffd97f 1567 struct rtl_fw *rtl_fw = tp->rtl_fw;
1da177e4 1568
68aad78c 1569 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
68aad78c 1570 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1c361efb 1571 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
254764e5 1572 if (rtl_fw)
8ac72d16
RJ		 1573 strlcpy(info->fw_version, rtl_fw->version,
1574 sizeof(info->fw_version));
1da177e4
LT		 1575}
1576
1577static int rtl8169_get_regs_len(struct net_device *dev)
1578{
1579 return R8169_REGS_SIZE;
1580}
1581
c8f44aff
MM		 1582static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1583 netdev_features_t features)
1da177e4 1584{
d58d46b5
FR		 1585 struct rtl8169_private *tp = netdev_priv(dev);
1586
2b7b4318 1587 if (dev->mtu > TD_MSS_MAX)
350fb32a 1588 features &= ~NETIF_F_ALL_TSO;
1da177e4 1589
d58d46b5 1590 if (dev->mtu > JUMBO_1K &&
6ed0e08f 1591 tp->mac_version > RTL_GIGA_MAC_VER_06)
d58d46b5
FR		 1592 features &= ~NETIF_F_IP_CSUM;
1593
350fb32a 1594 return features;
1da177e4
LT		 1595}
1596
a3984578
HK		 1597static int rtl8169_set_features(struct net_device *dev,
1598 netdev_features_t features)
1da177e4
LT		 1599{
1600 struct rtl8169_private *tp = netdev_priv(dev);
929a031d 1601 u32 rx_config;
1da177e4 1602
a3984578
HK		 1603 rtl_lock_work(tp);
1604
1ef7286e 1605 rx_config = RTL_R32(tp, RxConfig);
929a031d 1606 if (features & NETIF_F_RXALL)
1607 rx_config |= (AcceptErr | AcceptRunt);
1608 else
1609 rx_config &= ~(AcceptErr | AcceptRunt);
1da177e4 1610
f1bce4ad
HK		 1611 if (rtl_is_8125(tp)) {
1612 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1613 rx_config |= RX_VLAN_8125;
1614 else
1615 rx_config &= ~RX_VLAN_8125;
1616 }
1617
1ef7286e 1618 RTL_W32(tp, RxConfig, rx_config);
350fb32a 1619
929a031d 1620 if (features & NETIF_F_RXCSUM)
1621 tp->cp_cmd |= RxChkSum;
1622 else
1623 tp->cp_cmd &= ~RxChkSum;
6bbe021d 1624
f1bce4ad
HK		 1625 if (!rtl_is_8125(tp)) {
1626 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1627 tp->cp_cmd |= RxVlan;
1628 else
1629 tp->cp_cmd &= ~RxVlan;
1630 }
929a031d 1631
1ef7286e
AS		 1632 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1633 RTL_R16(tp, CPlusCmd);
1da177e4 1634
da78dbff 1635 rtl_unlock_work(tp);
1da177e4
LT		 1636
1637 return 0;
1638}
1639
810f4893 1640static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1da177e4 1641{
df8a39de 1642 return (skb_vlan_tag_present(skb)) ?
7424edbb 1643 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1da177e4
LT		 1644}
1645
7a8fc77b 1646static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1da177e4
LT		 1647{
1648 u32 opts2 = le32_to_cpu(desc->opts2);
1da177e4 1649
7a8fc77b 1650 if (opts2 & RxVlanTag)
7424edbb 1651 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1da177e4
LT		 1652}
1653
1da177e4
LT		 1654static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1655 void *p)
1656{
5b0384f4 1657 struct rtl8169_private *tp = netdev_priv(dev);
15edae91
PW		 1658 u32 __iomem *data = tp->mmio_addr;
1659 u32 *dw = p;
1660 int i;
1da177e4 1661
da78dbff 1662 rtl_lock_work(tp);
15edae91
PW		 1663 for (i = 0; i < R8169_REGS_SIZE; i += 4)
1664 memcpy_fromio(dw++, data++, 4);
da78dbff 1665 rtl_unlock_work(tp);
1da177e4
LT		 1666}
1667
b57b7e5a
SH		 1668static u32 rtl8169_get_msglevel(struct net_device *dev)
1669{
1670 struct rtl8169_private *tp = netdev_priv(dev);
1671
1672 return tp->msg_enable;
1673}
1674
1675static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1676{
1677 struct rtl8169_private *tp = netdev_priv(dev);
1678
1679 tp->msg_enable = value;
1680}
1681
d4a3a0fc
SH		 1682static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1683 "tx_packets",
1684 "rx_packets",
1685 "tx_errors",
1686 "rx_errors",
1687 "rx_missed",
1688 "align_errors",
1689 "tx_single_collisions",
1690 "tx_multi_collisions",
1691 "unicast",
1692 "broadcast",
1693 "multicast",
1694 "tx_aborted",
1695 "tx_underrun",
1696};
1697
b9f2c044 1698static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 1699{
b9f2c044
JG		 1700 switch (sset) {
1701 case ETH_SS_STATS:
1702 return ARRAY_SIZE(rtl8169_gstrings);
1703 default:
1704 return -EOPNOTSUPP;
1705 }
d4a3a0fc
SH		 1706}
1707
42020320 1708DECLARE_RTL_COND(rtl_counters_cond)
6e85d5ad 1709{
1ef7286e 1710 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
6e85d5ad
CV		 1711}
1712
e71c9ce2 1713static bool rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
6e85d5ad 1714{
42020320
CV		 1715 dma_addr_t paddr = tp->counters_phys_addr;
1716 u32 cmd;
6e85d5ad 1717
1ef7286e
AS		 1718 RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32);
1719 RTL_R32(tp, CounterAddrHigh);
42020320 1720 cmd = (u64)paddr & DMA_BIT_MASK(32);
1ef7286e
AS		 1721 RTL_W32(tp, CounterAddrLow, cmd);
1722 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
6e85d5ad 1723
a78e9366 1724 return rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
6e85d5ad
CV		 1725}
1726
e71c9ce2 1727static bool rtl8169_reset_counters(struct rtl8169_private *tp)
6e85d5ad 1728{
6e85d5ad
CV		 1729 /*
1730 * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
1731 * tally counters.
1732 */
1733 if (tp->mac_version < RTL_GIGA_MAC_VER_19)
1734 return true;
1735
e71c9ce2 1736 return rtl8169_do_counters(tp, CounterReset);
ffc46952
FR		 1737}
1738
e71c9ce2 1739static bool rtl8169_update_counters(struct rtl8169_private *tp)
d4a3a0fc 1740{
10262b0b
HK		 1741 u8 val = RTL_R8(tp, ChipCmd);
1742
355423d0
IV		 1743 /*
1744 * Some chips are unable to dump tally counters when the receiver
10262b0b 1745 * is disabled. If 0xff chip may be in a PCI power-save state.
355423d0 1746 */
10262b0b 1747 if (!(val & CmdRxEnb) || val == 0xff)
6e85d5ad 1748 return true;
d4a3a0fc 1749
e71c9ce2 1750 return rtl8169_do_counters(tp, CounterDump);
6e85d5ad
CV		 1751}
1752
e71c9ce2 1753static bool rtl8169_init_counter_offsets(struct rtl8169_private *tp)
6e85d5ad 1754{
42020320 1755 struct rtl8169_counters *counters = tp->counters;
6e85d5ad
CV		 1756 bool ret = false;
1757
1758 /*
1759 * rtl8169_init_counter_offsets is called from rtl_open. On chip
1760 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
1761 * reset by a power cycle, while the counter values collected by the
1762 * driver are reset at every driver unload/load cycle.
1763 *
1764 * To make sure the HW values returned by @get_stats64 match the SW
1765 * values, we collect the initial values at first open(*) and use them
1766 * as offsets to normalize the values returned by @get_stats64.
1767 *
1768 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
1769 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
1770 * set at open time by rtl_hw_start.
1771 */
1772
1773 if (tp->tc_offset.inited)
1774 return true;
1775
1776 /* If both, reset and update fail, propagate to caller. */
e71c9ce2 1777 if (rtl8169_reset_counters(tp))
6e85d5ad
CV		 1778 ret = true;
1779
e71c9ce2 1780 if (rtl8169_update_counters(tp))
6e85d5ad
CV		 1781 ret = true;
1782
42020320
CV		 1783 tp->tc_offset.tx_errors = counters->tx_errors;
1784 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1785 tp->tc_offset.tx_aborted = counters->tx_aborted;
6e85d5ad
CV		 1786 tp->tc_offset.inited = true;
1787
1788 return ret;
d4a3a0fc
SH		 1789}
1790
355423d0
IV		 1791static void rtl8169_get_ethtool_stats(struct net_device *dev,
1792 struct ethtool_stats *stats, u64 *data)
1793{
1794 struct rtl8169_private *tp = netdev_priv(dev);
1e1205b7 1795 struct device *d = tp_to_dev(tp);
42020320 1796 struct rtl8169_counters *counters = tp->counters;
355423d0
IV		 1797
1798 ASSERT_RTNL();
1799
e0636236
CHL		 1800 pm_runtime_get_noresume(d);
1801
1802 if (pm_runtime_active(d))
e71c9ce2 1803 rtl8169_update_counters(tp);
e0636236
CHL		 1804
1805 pm_runtime_put_noidle(d);
355423d0 1806
42020320
CV		 1807 data[0] = le64_to_cpu(counters->tx_packets);
1808 data[1] = le64_to_cpu(counters->rx_packets);
1809 data[2] = le64_to_cpu(counters->tx_errors);
1810 data[3] = le32_to_cpu(counters->rx_errors);
1811 data[4] = le16_to_cpu(counters->rx_missed);
1812 data[5] = le16_to_cpu(counters->align_errors);
1813 data[6] = le32_to_cpu(counters->tx_one_collision);
1814 data[7] = le32_to_cpu(counters->tx_multi_collision);
1815 data[8] = le64_to_cpu(counters->rx_unicast);
1816 data[9] = le64_to_cpu(counters->rx_broadcast);
1817 data[10] = le32_to_cpu(counters->rx_multicast);
1818 data[11] = le16_to_cpu(counters->tx_aborted);
1819 data[12] = le16_to_cpu(counters->tx_underun);
355423d0
IV		 1820}
1821
d4a3a0fc
SH		 1822static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1823{
1824 switch(stringset) {
1825 case ETH_SS_STATS:
1826 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1827 break;
1828 }
1829}
1830
50970831
FR		 1831/*
1832 * Interrupt coalescing
1833 *
1834 * > 1 - the availability of the IntrMitigate (0xe2) register through the
1835 * > 8169, 8168 and 810x line of chipsets
1836 *
1837 * 8169, 8168, and 8136(810x) serial chipsets support it.
1838 *
1839 * > 2 - the Tx timer unit at gigabit speed
1840 *
1841 * The unit of the timer depends on both the speed and the setting of CPlusCmd
1842 * (0xe0) bit 1 and bit 0.
1843 *
1844 * For 8169
1845 * bit[1:0] \ speed 1000M 100M 10M
1846 * 0 0 320ns 2.56us 40.96us
1847 * 0 1 2.56us 20.48us 327.7us
1848 * 1 0 5.12us 40.96us 655.4us
1849 * 1 1 10.24us 81.92us 1.31ms
1850 *
1851 * For the other
1852 * bit[1:0] \ speed 1000M 100M 10M
1853 * 0 0 5us 2.56us 40.96us
1854 * 0 1 40us 20.48us 327.7us
1855 * 1 0 80us 40.96us 655.4us
1856 * 1 1 160us 81.92us 1.31ms
1857 */
1858
1859/* rx/tx scale factors for one particular CPlusCmd[0:1] value */
1860struct rtl_coalesce_scale {
1861 /* Rx / Tx */
1862 u32 nsecs[2];
1863};
1864
1865/* rx/tx scale factors for all CPlusCmd[0:1] cases */
1866struct rtl_coalesce_info {
1867 u32 speed;
1868 struct rtl_coalesce_scale scalev[4]; /* each CPlusCmd[0:1] case */
1869};
1870
1871/* produce (r,t) pairs with each being in series of *1, *8, *8*2, *8*2*2 */
1872#define rxtx_x1822(r, t) { \
1873 {{(r), (t)}}, \
1874 {{(r)*8, (t)*8}}, \
1875 {{(r)*8*2, (t)*8*2}}, \
1876 {{(r)*8*2*2, (t)*8*2*2}}, \
1877}
1878static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
1879 /* speed delays: rx00 tx00 */
1880 { SPEED_10, rxtx_x1822(40960, 40960) },
1881 { SPEED_100, rxtx_x1822( 2560, 2560) },
1882 { SPEED_1000, rxtx_x1822( 320, 320) },
1883 { 0 },
1884};
1885
1886static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
1887 /* speed delays: rx00 tx00 */
1888 { SPEED_10, rxtx_x1822(40960, 40960) },
1889 { SPEED_100, rxtx_x1822( 2560, 2560) },
1890 { SPEED_1000, rxtx_x1822( 5000, 5000) },
1891 { 0 },
1892};
1893#undef rxtx_x1822
1894
1895/* get rx/tx scale vector corresponding to current speed */
1896static const struct rtl_coalesce_info *rtl_coalesce_info(struct net_device *dev)
1897{
1898 struct rtl8169_private *tp = netdev_priv(dev);
50970831 1899 const struct rtl_coalesce_info *ci;
50970831 1900
20023d3e
HK		 1901 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1902 ci = rtl_coalesce_info_8169;
1903 else
1904 ci = rtl_coalesce_info_8168_8136;
50970831 1905
20023d3e
HK		 1906 for (; ci->speed; ci++) {
1907 if (tp->phydev->speed == ci->speed)
50970831 1908 return ci;
50970831
FR		 1909 }
1910
1911 return ERR_PTR(-ELNRNG);
1912}
1913
1914static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1915{
1916 struct rtl8169_private *tp = netdev_priv(dev);
50970831
FR		 1917 const struct rtl_coalesce_info *ci;
1918 const struct rtl_coalesce_scale *scale;
1919 struct {
1920 u32 *max_frames;
1921 u32 *usecs;
1922 } coal_settings [] = {
1923 { &ec->rx_max_coalesced_frames, &ec->rx_coalesce_usecs },
1924 { &ec->tx_max_coalesced_frames, &ec->tx_coalesce_usecs }
1925 }, *p = coal_settings;
1926 int i;
1927 u16 w;
1928
f1bce4ad
HK		 1929 if (rtl_is_8125(tp))
1930 return -EOPNOTSUPP;
1931
50970831
FR		 1932 memset(ec, 0, sizeof(*ec));
1933
1934 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
1935 ci = rtl_coalesce_info(dev);
1936 if (IS_ERR(ci))
1937 return PTR_ERR(ci);
1938
0ae0974e 1939 scale = &ci->scalev[tp->cp_cmd & INTT_MASK];
50970831
FR		 1940
1941 /* read IntrMitigate and adjust according to scale */
1ef7286e 1942 for (w = RTL_R16(tp, IntrMitigate); w; w >>= RTL_COALESCE_SHIFT, p++) {
50970831
FR		 1943 *p->max_frames = (w & RTL_COALESCE_MASK) << 2;
1944 w >>= RTL_COALESCE_SHIFT;
1945 *p->usecs = w & RTL_COALESCE_MASK;
1946 }
1947
1948 for (i = 0; i < 2; i++) {
1949 p = coal_settings + i;
1950 *p->usecs = (*p->usecs * scale->nsecs[i]) / 1000;
1951
1952 /*
1953 * ethtool_coalesce says it is illegal to set both usecs and
1954 * max_frames to 0.
1955 */
1956 if (!*p->usecs && !*p->max_frames)
1957 *p->max_frames = 1;
1958 }
1959
1960 return 0;
1961}
1962
1963/* choose appropriate scale factor and CPlusCmd[0:1] for (speed, nsec) */
1964static const struct rtl_coalesce_scale *rtl_coalesce_choose_scale(
1965 struct net_device *dev, u32 nsec, u16 *cp01)
1966{
1967 const struct rtl_coalesce_info *ci;
1968 u16 i;
1969
1970 ci = rtl_coalesce_info(dev);
1971 if (IS_ERR(ci))
1972 return ERR_CAST(ci);
1973
1974 for (i = 0; i < 4; i++) {
1975 u32 rxtx_maxscale = max(ci->scalev[i].nsecs[0],
1976 ci->scalev[i].nsecs[1]);
1977 if (nsec <= rxtx_maxscale * RTL_COALESCE_T_MAX) {
1978 *cp01 = i;
1979 return &ci->scalev[i];
1980 }
1981 }
1982
1983 return ERR_PTR(-EINVAL);
1984}
1985
1986static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1987{
1988 struct rtl8169_private *tp = netdev_priv(dev);
50970831
FR		 1989 const struct rtl_coalesce_scale *scale;
1990 struct {
1991 u32 frames;
1992 u32 usecs;
1993 } coal_settings [] = {
1994 { ec->rx_max_coalesced_frames, ec->rx_coalesce_usecs },
1995 { ec->tx_max_coalesced_frames, ec->tx_coalesce_usecs }
1996 }, *p = coal_settings;
1997 u16 w = 0, cp01;
1998 int i;
1999
f1bce4ad
HK		 2000 if (rtl_is_8125(tp))
2001 return -EOPNOTSUPP;
2002
50970831
FR		 2003 scale = rtl_coalesce_choose_scale(dev,
2004 max(p[0].usecs, p[1].usecs) * 1000, &cp01);
2005 if (IS_ERR(scale))
2006 return PTR_ERR(scale);
2007
2008 for (i = 0; i < 2; i++, p++) {
2009 u32 units;
2010
2011 /*
2012 * accept max_frames=1 we returned in rtl_get_coalesce.
2013 * accept it not only when usecs=0 because of e.g. the following scenario:
2014 *
2015 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
2016 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
2017 * - then user does `ethtool -C eth0 rx-usecs 100`
2018 *
2019 * since ethtool sends to kernel whole ethtool_coalesce
2020 * settings, if we do not handle rx_usecs=!0, rx_frames=1
2021 * we'll reject it below in `frames % 4 != 0`.
2022 */
2023 if (p->frames == 1) {
2024 p->frames = 0;
2025 }
2026
2027 units = p->usecs * 1000 / scale->nsecs[i];
2028 if (p->frames > RTL_COALESCE_FRAME_MAX || p->frames % 4)
2029 return -EINVAL;
2030
2031 w <<= RTL_COALESCE_SHIFT;
2032 w |= units;
2033 w <<= RTL_COALESCE_SHIFT;
2034 w |= p->frames >> 2;
2035 }
2036
2037 rtl_lock_work(tp);
2038
1ef7286e 2039 RTL_W16(tp, IntrMitigate, swab16(w));
50970831 2040
9a3c81fa 2041 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
1ef7286e
AS		 2042 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
2043 RTL_R16(tp, CPlusCmd);
50970831
FR		 2044
2045 rtl_unlock_work(tp);
2046
2047 return 0;
2048}
2049
df6f1856
HK		 2050static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data)
2051{
2052 struct rtl8169_private *tp = netdev_priv(dev);
2053 struct device *d = tp_to_dev(tp);
2054 int ret;
2055
2e779ddb
HK		 2056 if (!rtl_supports_eee(tp))
2057 return -EOPNOTSUPP;
2058
df6f1856
HK		 2059 pm_runtime_get_noresume(d);
2060
2061 if (!pm_runtime_active(d)) {
2062 ret = -EOPNOTSUPP;
2e779ddb
HK		 2063 } else {
2064 ret = phy_ethtool_get_eee(tp->phydev, data);
df6f1856
HK		 2065 }
2066
df6f1856 2067 pm_runtime_put_noidle(d);
2e779ddb
HK		 2068
2069 return ret;
df6f1856
HK		 2070}
2071
2072static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data)
2073{
2074 struct rtl8169_private *tp = netdev_priv(dev);
2075 struct device *d = tp_to_dev(tp);
2e779ddb
HK		 2076 int ret;
2077
2078 if (!rtl_supports_eee(tp))
2079 return -EOPNOTSUPP;
df6f1856
HK		 2080
2081 pm_runtime_get_noresume(d);
2082
2e779ddb 2083 if (!pm_runtime_active(d)) {
df6f1856
HK		 2084 ret = -EOPNOTSUPP;
2085 goto out;
2086 }
2087
2088 if (dev->phydev->autoneg == AUTONEG_DISABLE ||
2089 dev->phydev->duplex != DUPLEX_FULL) {
2090 ret = -EPROTONOSUPPORT;
2091 goto out;
2092 }
2093
2e779ddb 2094 ret = phy_ethtool_set_eee(tp->phydev, data);
488202f5
HK		 2095
2096 if (!ret)
2097 tp->eee_adv = phy_read_mmd(dev->phydev, MDIO_MMD_AN,
2098 MDIO_AN_EEE_ADV);
df6f1856
HK		 2099out:
2100 pm_runtime_put_noidle(d);
2e779ddb 2101 return ret;
df6f1856
HK		 2102}
2103
7282d491 2104static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 2105 .get_drvinfo = rtl8169_get_drvinfo,
2106 .get_regs_len = rtl8169_get_regs_len,
2107 .get_link = ethtool_op_get_link,
50970831
FR		 2108 .get_coalesce = rtl_get_coalesce,
2109 .set_coalesce = rtl_set_coalesce,
b57b7e5a
SH		 2110 .get_msglevel = rtl8169_get_msglevel,
2111 .set_msglevel = rtl8169_set_msglevel,
1da177e4 2112 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 2113 .get_wol = rtl8169_get_wol,
2114 .set_wol = rtl8169_set_wol,
d4a3a0fc 2115 .get_strings = rtl8169_get_strings,
b9f2c044 2116 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 2117 .get_ethtool_stats = rtl8169_get_ethtool_stats,
e1593bb1 2118 .get_ts_info = ethtool_op_get_ts_info,
dd84957e 2119 .nway_reset = phy_ethtool_nway_reset,
df6f1856
HK		 2120 .get_eee = rtl8169_get_eee,
2121 .set_eee = rtl8169_set_eee,
45772433
HK		 2122 .get_link_ksettings = phy_ethtool_get_link_ksettings,
2123 .set_link_ksettings = phy_ethtool_set_link_ksettings,
1da177e4
LT		 2124};
2125
b6c7fa40
HK		 2126static void rtl_enable_eee(struct rtl8169_private *tp)
2127{
2e779ddb 2128 struct phy_device *phydev = tp->phydev;
488202f5
HK		 2129 int adv;
2130
2131 /* respect EEE advertisement the user may have set */
2132 if (tp->eee_adv >= 0)
2133 adv = tp->eee_adv;
2134 else
2135 adv = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
b6c7fa40 2136
488202f5
HK		 2137 if (adv >= 0)
2138 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, adv);
b6c7fa40
HK		 2139}
2140
b4cc2dcc 2141static void rtl8169_get_mac_version(struct rtl8169_private *tp)
1da177e4 2142{
0e485150
FR		 2143 /*
2144 * The driver currently handles the 8168Bf and the 8168Be identically
2145 * but they can be identified more specifically through the test below
2146 * if needed:
2147 *
1ef7286e 2148 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 2149 *
2150 * Same thing for the 8101Eb and the 8101Ec:
2151 *
1ef7286e 2152 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 2153 */
3744100e 2154 static const struct rtl_mac_info {
55d2ad7b
HK		 2155 u16 mask;
2156 u16 val;
2157 u16 mac_version;
1da177e4 2158 } mac_info[] = {
f1bce4ad
HK		 2159 /* 8125 family. */
2160 { 0x7cf, 0x608, RTL_GIGA_MAC_VER_60 },
2161 { 0x7c8, 0x608, RTL_GIGA_MAC_VER_61 },
2162
2e13d773
HK		 2163 /* RTL8117 */
2164 { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52 },
2165
935e2218 2166 /* 8168EP family. */
55d2ad7b
HK		 2167 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 },
2168 { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 },
2169 { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 },
935e2218 2170
6e1d0b89 2171 /* 8168H family. */
55d2ad7b
HK		 2172 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 },
2173 { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 },
6e1d0b89 2174
c558386b 2175 /* 8168G family. */
55d2ad7b
HK		 2176 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 },
2177 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 },
2178 { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 },
2179 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 },
c558386b 2180
c2218925 2181 /* 8168F family. */
55d2ad7b
HK		 2182 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 },
2183 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 },
2184 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 },
c2218925 2185
01dc7fec 2186 /* 8168E family. */
55d2ad7b
HK		 2187 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 },
2188 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 },
2189 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 },
01dc7fec 2190
5b538df9 2191 /* 8168D family. */
55d2ad7b
HK		 2192 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 },
2193 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 },
5b538df9 2194
e6de30d6 2195 /* 8168DP family. */
55d2ad7b
HK		 2196 { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 },
2197 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 },
2198 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 },
e6de30d6 2199
ef808d50 2200 /* 8168C family. */
55d2ad7b
HK		 2201 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 },
2202 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 },
2203 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 },
2204 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 },
2205 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 },
2206 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 },
2207 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 },
e3cf0cc0
FR		 2208
2209 /* 8168B family. */
55d2ad7b
HK		 2210 { 0x7cf, 0x380, RTL_GIGA_MAC_VER_12 },
2211 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 },
2212 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 },
e3cf0cc0
FR		 2213
2214 /* 8101 family. */
55d2ad7b
HK		 2215 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 },
2216 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 },
2217 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 },
2218 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 },
2219 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 },
2220 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 },
2221 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 },
2222 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 },
2223 { 0x7cf, 0x340, RTL_GIGA_MAC_VER_13 },
35fb2a42
HK		 2224 /* RTL8401, reportedly works if treated as RTL8101e */
2225 { 0x7cf, 0x240, RTL_GIGA_MAC_VER_13 },
55d2ad7b
HK		 2226 { 0x7cf, 0x343, RTL_GIGA_MAC_VER_10 },
2227 { 0x7cf, 0x342, RTL_GIGA_MAC_VER_16 },
2228 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 },
2229 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 },
2230 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_16 },
e3cf0cc0 2231 /* FIXME: where did these entries come from ? -- FR */
55d2ad7b
HK		 2232 { 0xfc8, 0x388, RTL_GIGA_MAC_VER_15 },
2233 { 0xfc8, 0x308, RTL_GIGA_MAC_VER_14 },
e3cf0cc0
FR		 2234
2235 /* 8110 family. */
55d2ad7b
HK		 2236 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 },
2237 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 },
2238 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 },
2239 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 },
2240 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 },
e3cf0cc0 2241
f21b75e9 2242 /* Catch-all */
55d2ad7b 2243 { 0x000, 0x000, RTL_GIGA_MAC_NONE }
3744100e
FR		 2244 };
2245 const struct rtl_mac_info *p = mac_info;
55d2ad7b 2246 u16 reg = RTL_R32(tp, TxConfig) >> 20;
1da177e4 2247
e3cf0cc0 2248 while ((reg & p->mask) != p->val)
1da177e4
LT		 2249 p++;
2250 tp->mac_version = p->mac_version;
5d320a20
FR		 2251
2252 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
b4cc2dcc 2253 dev_err(tp_to_dev(tp), "unknown chip XID %03x\n", reg & 0xfcf);
45f1996f
HK		 2254 } else if (!tp->supports_gmii) {
2255 if (tp->mac_version == RTL_GIGA_MAC_VER_42)
2256 tp->mac_version = RTL_GIGA_MAC_VER_43;
2257 else if (tp->mac_version == RTL_GIGA_MAC_VER_45)
2258 tp->mac_version = RTL_GIGA_MAC_VER_47;
2259 else if (tp->mac_version == RTL_GIGA_MAC_VER_46)
2260 tp->mac_version = RTL_GIGA_MAC_VER_48;
5d320a20 2261 }
1da177e4
LT		 2262}
2263
867763c1
FR		 2264struct phy_reg {
2265 u16 reg;
2266 u16 val;
2267};
2268
1791ad50
HK		 2269static void __rtl_writephy_batch(struct rtl8169_private *tp,
2270 const struct phy_reg *regs, int len)
867763c1
FR		 2271{
2272 while (len-- > 0) {
4da19633 2273 rtl_writephy(tp, regs->reg, regs->val);
867763c1
FR		 2274 regs++;
2275 }
2276}
2277
1791ad50
HK		 2278#define rtl_writephy_batch(tp, a) __rtl_writephy_batch(tp, a, ARRAY_SIZE(a))
2279
f1e02ed1 2280static void rtl_release_firmware(struct rtl8169_private *tp)
2281{
254764e5 2282 if (tp->rtl_fw) {
47ad5931 2283 rtl_fw_release_firmware(tp->rtl_fw);
b6ffd97f 2284 kfree(tp->rtl_fw);
254764e5 2285 tp->rtl_fw = NULL;
b6ffd97f 2286 }
f1e02ed1 2287}
2288
953a12cc 2289static void rtl_apply_firmware(struct rtl8169_private *tp)
f1e02ed1 2290{
ce8843ab 2291 /* TODO: release firmware if rtl_fw_write_firmware signals failure. */
2097f276 2292 if (tp->rtl_fw) {
ce8843ab 2293 rtl_fw_write_firmware(tp, tp->rtl_fw);
2097f276
HK		 2294 /* At least one firmware doesn't reset tp->ocp_base. */
2295 tp->ocp_base = OCP_STD_PHY_BASE;
2296 }
953a12cc
FR		 2297}
2298
2299static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2300{
2301 if (rtl_readphy(tp, reg) != val)
2302 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2303 else
2304 rtl_apply_firmware(tp);
f1e02ed1 2305}
2306
df6f1856
HK		 2307static void rtl8168_config_eee_mac(struct rtl8169_private *tp)
2308{
f452825d
HK		 2309 /* Adjust EEE LED frequency */
2310 if (tp->mac_version != RTL_GIGA_MAC_VER_38)
2311 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
2312
e719b3ea 2313 rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_1111, 0x0003);
df6f1856
HK		 2314}
2315
b3a42e3a
HK		 2316static void rtl8125_config_eee_mac(struct rtl8169_private *tp)
2317{
2318 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0));
2319 r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1));
2320}
2321
cc07d271
HK		 2322static void rtl8168f_config_eee_phy(struct rtl8169_private *tp)
2323{
2324 struct phy_device *phydev = tp->phydev;
2325
2326 phy_write(phydev, 0x1f, 0x0007);
2327 phy_write(phydev, 0x1e, 0x0020);
2328 phy_set_bits(phydev, 0x15, BIT(8));
2329
2330 phy_write(phydev, 0x1f, 0x0005);
2331 phy_write(phydev, 0x05, 0x8b85);
2332 phy_set_bits(phydev, 0x06, BIT(13));
2333
2334 phy_write(phydev, 0x1f, 0x0000);
2335}
2336
df6f1856
HK		 2337static void rtl8168g_config_eee_phy(struct rtl8169_private *tp)
2338{
a2928d28 2339 phy_modify_paged(tp->phydev, 0x0a43, 0x11, 0, BIT(4));
df6f1856
HK		 2340}
2341
b6cef26f
HK		 2342static void rtl8168h_config_eee_phy(struct rtl8169_private *tp)
2343{
2344 struct phy_device *phydev = tp->phydev;
2345
2346 rtl8168g_config_eee_phy(tp);
2347
2348 phy_modify_paged(phydev, 0xa4a, 0x11, 0x0000, 0x0200);
2349 phy_modify_paged(phydev, 0xa42, 0x14, 0x0000, 0x0080);
2350}
2351
b3a42e3a
HK		 2352static void rtl8125_config_eee_phy(struct rtl8169_private *tp)
2353{
2354 struct phy_device *phydev = tp->phydev;
2355
2356 rtl8168h_config_eee_phy(tp);
2357
2358 phy_modify_paged(phydev, 0xa6d, 0x12, 0x0001, 0x0000);
2359 phy_modify_paged(phydev, 0xa6d, 0x14, 0x0010, 0x0000);
2360}
2361
4da19633 2362static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1da177e4 2363{
350f7596 2364 static const struct phy_reg phy_reg_init[] = {
0b9b571d 2365 { 0x1f, 0x0001 },
2366 { 0x06, 0x006e },
2367 { 0x08, 0x0708 },
2368 { 0x15, 0x4000 },
2369 { 0x18, 0x65c7 },
1da177e4 2370
0b9b571d 2371 { 0x1f, 0x0001 },
2372 { 0x03, 0x00a1 },
2373 { 0x02, 0x0008 },
2374 { 0x01, 0x0120 },
2375 { 0x00, 0x1000 },
2376 { 0x04, 0x0800 },
2377 { 0x04, 0x0000 },
1da177e4 2378
0b9b571d 2379 { 0x03, 0xff41 },
2380 { 0x02, 0xdf60 },
2381 { 0x01, 0x0140 },
2382 { 0x00, 0x0077 },
2383 { 0x04, 0x7800 },
2384 { 0x04, 0x7000 },
2385
2386 { 0x03, 0x802f },
2387 { 0x02, 0x4f02 },
2388 { 0x01, 0x0409 },
2389 { 0x00, 0xf0f9 },
2390 { 0x04, 0x9800 },
2391 { 0x04, 0x9000 },
2392
2393 { 0x03, 0xdf01 },
2394 { 0x02, 0xdf20 },
2395 { 0x01, 0xff95 },
2396 { 0x00, 0xba00 },
2397 { 0x04, 0xa800 },
2398 { 0x04, 0xa000 },
2399
2400 { 0x03, 0xff41 },
2401 { 0x02, 0xdf20 },
2402 { 0x01, 0x0140 },
2403 { 0x00, 0x00bb },
2404 { 0x04, 0xb800 },
2405 { 0x04, 0xb000 },
2406
2407 { 0x03, 0xdf41 },
2408 { 0x02, 0xdc60 },
2409 { 0x01, 0x6340 },
2410 { 0x00, 0x007d },
2411 { 0x04, 0xd800 },
2412 { 0x04, 0xd000 },
2413
2414 { 0x03, 0xdf01 },
2415 { 0x02, 0xdf20 },
2416 { 0x01, 0x100a },
2417 { 0x00, 0xa0ff },
2418 { 0x04, 0xf800 },
2419 { 0x04, 0xf000 },
2420
2421 { 0x1f, 0x0000 },
2422 { 0x0b, 0x0000 },
2423 { 0x00, 0x9200 }
2424 };
1da177e4 2425
1791ad50 2426 rtl_writephy_batch(tp, phy_reg_init);
1da177e4
LT		 2427}
2428
4da19633 2429static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
5615d9f1 2430{
350f7596 2431 static const struct phy_reg phy_reg_init[] = {
a441d7b6
FR		 2432 { 0x1f, 0x0002 },
2433 { 0x01, 0x90d0 },
2434 { 0x1f, 0x0000 }
2435 };
2436
1791ad50 2437 rtl_writephy_batch(tp, phy_reg_init);
5615d9f1
FR		 2438}
2439
4da19633 2440static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2e955856 2441{
2442 struct pci_dev *pdev = tp->pci_dev;
2e955856 2443
ccbae55e
SS		 2444 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2445 (pdev->subsystem_device != 0xe000))
2e955856 2446 return;
2447
4da19633 2448 rtl_writephy(tp, 0x1f, 0x0001);
2449 rtl_writephy(tp, 0x10, 0xf01b);
2450 rtl_writephy(tp, 0x1f, 0x0000);
2e955856 2451}
2452
4da19633 2453static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2e955856 2454{
350f7596 2455 static const struct phy_reg phy_reg_init[] = {
2e955856 2456 { 0x1f, 0x0001 },
2457 { 0x04, 0x0000 },
2458 { 0x03, 0x00a1 },
2459 { 0x02, 0x0008 },
2460 { 0x01, 0x0120 },
2461 { 0x00, 0x1000 },
2462 { 0x04, 0x0800 },
2463 { 0x04, 0x9000 },
2464 { 0x03, 0x802f },
2465 { 0x02, 0x4f02 },
2466 { 0x01, 0x0409 },
2467 { 0x00, 0xf099 },
2468 { 0x04, 0x9800 },
2469 { 0x04, 0xa000 },
2470 { 0x03, 0xdf01 },
2471 { 0x02, 0xdf20 },
2472 { 0x01, 0xff95 },
2473 { 0x00, 0xba00 },
2474 { 0x04, 0xa800 },
2475 { 0x04, 0xf000 },
2476 { 0x03, 0xdf01 },
2477 { 0x02, 0xdf20 },
2478 { 0x01, 0x101a },
2479 { 0x00, 0xa0ff },
2480 { 0x04, 0xf800 },
2481 { 0x04, 0x0000 },
2482 { 0x1f, 0x0000 },
2483
2484 { 0x1f, 0x0001 },
2485 { 0x10, 0xf41b },
2486 { 0x14, 0xfb54 },
2487 { 0x18, 0xf5c7 },
2488 { 0x1f, 0x0000 },
2489
2490 { 0x1f, 0x0001 },
2491 { 0x17, 0x0cc0 },
2492 { 0x1f, 0x0000 }
2493 };
2494
1791ad50 2495 rtl_writephy_batch(tp, phy_reg_init);
2e955856 2496
4da19633 2497 rtl8169scd_hw_phy_config_quirk(tp);
2e955856 2498}
2499
4da19633 2500static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
8c7006aa 2501{
350f7596 2502 static const struct phy_reg phy_reg_init[] = {
8c7006aa 2503 { 0x1f, 0x0001 },
2504 { 0x04, 0x0000 },
2505 { 0x03, 0x00a1 },
2506 { 0x02, 0x0008 },
2507 { 0x01, 0x0120 },
2508 { 0x00, 0x1000 },
2509 { 0x04, 0x0800 },
2510 { 0x04, 0x9000 },
2511 { 0x03, 0x802f },
2512 { 0x02, 0x4f02 },
2513 { 0x01, 0x0409 },
2514 { 0x00, 0xf099 },
2515 { 0x04, 0x9800 },
2516 { 0x04, 0xa000 },
2517 { 0x03, 0xdf01 },
2518 { 0x02, 0xdf20 },
2519 { 0x01, 0xff95 },
2520 { 0x00, 0xba00 },
2521 { 0x04, 0xa800 },
2522 { 0x04, 0xf000 },
2523 { 0x03, 0xdf01 },
2524 { 0x02, 0xdf20 },
2525 { 0x01, 0x101a },
2526 { 0x00, 0xa0ff },
2527 { 0x04, 0xf800 },
2528 { 0x04, 0x0000 },
2529 { 0x1f, 0x0000 },
2530
2531 { 0x1f, 0x0001 },
2532 { 0x0b, 0x8480 },
2533 { 0x1f, 0x0000 },
2534
2535 { 0x1f, 0x0001 },
2536 { 0x18, 0x67c7 },
2537 { 0x04, 0x2000 },
2538 { 0x03, 0x002f },
2539 { 0x02, 0x4360 },
2540 { 0x01, 0x0109 },
2541 { 0x00, 0x3022 },
2542 { 0x04, 0x2800 },
2543 { 0x1f, 0x0000 },
2544
2545 { 0x1f, 0x0001 },
2546 { 0x17, 0x0cc0 },
2547 { 0x1f, 0x0000 }
2548 };
2549
1791ad50 2550 rtl_writephy_batch(tp, phy_reg_init);
8c7006aa 2551}
2552
4da19633 2553static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
236b8082 2554{
350f7596 2555 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2556 { 0x10, 0xf41b },
2557 { 0x1f, 0x0000 }
2558 };
2559
4da19633 2560 rtl_writephy(tp, 0x1f, 0x0001);
2561 rtl_patchphy(tp, 0x16, 1 << 0);
236b8082 2562
1791ad50 2563 rtl_writephy_batch(tp, phy_reg_init);
236b8082
FR		 2564}
2565
4da19633 2566static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
236b8082 2567{
350f7596 2568 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2569 { 0x1f, 0x0001 },
2570 { 0x10, 0xf41b },
2571 { 0x1f, 0x0000 }
2572 };
2573
1791ad50 2574 rtl_writephy_batch(tp, phy_reg_init);
236b8082
FR		 2575}
2576
4da19633 2577static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2578{
350f7596 2579 static const struct phy_reg phy_reg_init[] = {
867763c1
FR		 2580 { 0x1f, 0x0000 },
2581 { 0x1d, 0x0f00 },
2582 { 0x1f, 0x0002 },
2583 { 0x0c, 0x1ec8 },
2584 { 0x1f, 0x0000 }
2585 };
2586
1791ad50 2587 rtl_writephy_batch(tp, phy_reg_init);
867763c1
FR		 2588}
2589
4da19633 2590static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
ef3386f0 2591{
350f7596 2592 static const struct phy_reg phy_reg_init[] = {
ef3386f0
FR		 2593 { 0x1f, 0x0001 },
2594 { 0x1d, 0x3d98 },
2595 { 0x1f, 0x0000 }
2596 };
2597
4da19633 2598 rtl_writephy(tp, 0x1f, 0x0000);
2599 rtl_patchphy(tp, 0x14, 1 << 5);
2600 rtl_patchphy(tp, 0x0d, 1 << 5);
ef3386f0 2601
1791ad50 2602 rtl_writephy_batch(tp, phy_reg_init);
ef3386f0
FR		 2603}
2604
4da19633 2605static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2606{
350f7596 2607 static const struct phy_reg phy_reg_init[] = {
a3f80671
FR		 2608 { 0x1f, 0x0001 },
2609 { 0x12, 0x2300 },
867763c1
FR		 2610 { 0x1f, 0x0002 },
2611 { 0x00, 0x88d4 },
2612 { 0x01, 0x82b1 },
2613 { 0x03, 0x7002 },
2614 { 0x08, 0x9e30 },
2615 { 0x09, 0x01f0 },
2616 { 0x0a, 0x5500 },
2617 { 0x0c, 0x00c8 },
2618 { 0x1f, 0x0003 },
2619 { 0x12, 0xc096 },
2620 { 0x16, 0x000a },
f50d4275
FR		 2621 { 0x1f, 0x0000 },
2622 { 0x1f, 0x0000 },
2623 { 0x09, 0x2000 },
2624 { 0x09, 0x0000 }
867763c1
FR		 2625 };
2626
1791ad50 2627 rtl_writephy_batch(tp, phy_reg_init);
f50d4275 2628
4da19633 2629 rtl_patchphy(tp, 0x14, 1 << 5);
2630 rtl_patchphy(tp, 0x0d, 1 << 5);
2631 rtl_writephy(tp, 0x1f, 0x0000);
867763c1
FR		 2632}
2633
4da19633 2634static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
7da97ec9 2635{
350f7596 2636 static const struct phy_reg phy_reg_init[] = {
f50d4275 2637 { 0x1f, 0x0001 },
7da97ec9 2638 { 0x12, 0x2300 },
f50d4275
FR		 2639 { 0x03, 0x802f },
2640 { 0x02, 0x4f02 },
2641 { 0x01, 0x0409 },
2642 { 0x00, 0xf099 },
2643 { 0x04, 0x9800 },
2644 { 0x04, 0x9000 },
2645 { 0x1d, 0x3d98 },
7da97ec9
FR		 2646 { 0x1f, 0x0002 },
2647 { 0x0c, 0x7eb8 },
f50d4275
FR		 2648 { 0x06, 0x0761 },
2649 { 0x1f, 0x0003 },
2650 { 0x16, 0x0f0a },
7da97ec9
FR		 2651 { 0x1f, 0x0000 }
2652 };
2653
1791ad50 2654 rtl_writephy_batch(tp, phy_reg_init);
f50d4275 2655
4da19633 2656 rtl_patchphy(tp, 0x16, 1 << 0);
2657 rtl_patchphy(tp, 0x14, 1 << 5);
2658 rtl_patchphy(tp, 0x0d, 1 << 5);
2659 rtl_writephy(tp, 0x1f, 0x0000);
7da97ec9
FR		 2660}
2661
4da19633 2662static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
197ff761 2663{
350f7596 2664 static const struct phy_reg phy_reg_init[] = {
197ff761
FR		 2665 { 0x1f, 0x0001 },
2666 { 0x12, 0x2300 },
2667 { 0x1d, 0x3d98 },
2668 { 0x1f, 0x0002 },
2669 { 0x0c, 0x7eb8 },
2670 { 0x06, 0x5461 },
2671 { 0x1f, 0x0003 },
2672 { 0x16, 0x0f0a },
2673 { 0x1f, 0x0000 }
2674 };
2675
1791ad50 2676 rtl_writephy_batch(tp, phy_reg_init);
197ff761 2677
4da19633 2678 rtl_patchphy(tp, 0x16, 1 << 0);
2679 rtl_patchphy(tp, 0x14, 1 << 5);
2680 rtl_patchphy(tp, 0x0d, 1 << 5);
2681 rtl_writephy(tp, 0x1f, 0x0000);
197ff761
FR		 2682}
2683
4da19633 2684static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
6fb07058 2685{
4da19633 2686 rtl8168c_3_hw_phy_config(tp);
6fb07058
FR		 2687}
2688
fcb40e16
HK		 2689static const struct phy_reg rtl8168d_1_phy_reg_init_0[] = {
2690 /* Channel Estimation */
2691 { 0x1f, 0x0001 },
2692 { 0x06, 0x4064 },
2693 { 0x07, 0x2863 },
2694 { 0x08, 0x059c },
2695 { 0x09, 0x26b4 },
2696 { 0x0a, 0x6a19 },
2697 { 0x0b, 0xdcc8 },
2698 { 0x10, 0xf06d },
2699 { 0x14, 0x7f68 },
2700 { 0x18, 0x7fd9 },
2701 { 0x1c, 0xf0ff },
2702 { 0x1d, 0x3d9c },
2703 { 0x1f, 0x0003 },
2704 { 0x12, 0xf49f },
2705 { 0x13, 0x070b },
2706 { 0x1a, 0x05ad },
2707 { 0x14, 0x94c0 },
bca03d5f 2708
fcb40e16
HK		 2709 /*
2710 * Tx Error Issue
2711 * Enhance line driver power
2712 */
2713 { 0x1f, 0x0002 },
2714 { 0x06, 0x5561 },
2715 { 0x1f, 0x0005 },
2716 { 0x05, 0x8332 },
2717 { 0x06, 0x5561 },
bca03d5f 2718
fcb40e16
HK		 2719 /*
2720 * Can not link to 1Gbps with bad cable
2721 * Decrease SNR threshold form 21.07dB to 19.04dB
2722 */
2723 { 0x1f, 0x0001 },
2724 { 0x17, 0x0cc0 },
daf9df6d 2725
fcb40e16
HK		 2726 { 0x1f, 0x0000 },
2727 { 0x0d, 0xf880 }
2728};
2729
2730static const struct phy_reg rtl8168d_1_phy_reg_init_1[] = {
2731 { 0x1f, 0x0002 },
2732 { 0x05, 0x669a },
2733 { 0x1f, 0x0005 },
2734 { 0x05, 0x8330 },
2735 { 0x06, 0x669a },
2736 { 0x1f, 0x0002 }
2737};
daf9df6d 2738
fcb40e16
HK		 2739static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2740{
2741 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_0);
daf9df6d 2742
bca03d5f 2743 /*
2744 * Rx Error Issue
2745 * Fine Tune Switching regulator parameter
2746 */
4da19633 2747 rtl_writephy(tp, 0x1f, 0x0002);
76564428
CHL		 2748 rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
2749 rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
daf9df6d 2750
fdf6fc06 2751 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
daf9df6d 2752 int val;
2753
fcb40e16 2754 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_1);
daf9df6d 2755
4da19633 2756 val = rtl_readphy(tp, 0x0d);
daf9df6d 2757
2758 if ((val & 0x00ff) != 0x006c) {
350f7596 2759 static const u32 set[] = {
daf9df6d 2760 0x0065, 0x0066, 0x0067, 0x0068,
2761 0x0069, 0x006a, 0x006b, 0x006c
2762 };
2763 int i;
2764
4da19633 2765 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2766
2767 val &= 0xff00;
2768 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2769 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2770 }
2771 } else {
350f7596 2772 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2773 { 0x1f, 0x0002 },
2774 { 0x05, 0x6662 },
2775 { 0x1f, 0x0005 },
2776 { 0x05, 0x8330 },
2777 { 0x06, 0x6662 }
2778 };
2779
1791ad50 2780 rtl_writephy_batch(tp, phy_reg_init);
daf9df6d 2781 }
2782
bca03d5f 2783 /* RSET couple improve */
4da19633 2784 rtl_writephy(tp, 0x1f, 0x0002);
2785 rtl_patchphy(tp, 0x0d, 0x0300);
2786 rtl_patchphy(tp, 0x0f, 0x0010);
daf9df6d 2787
bca03d5f 2788 /* Fine tune PLL performance */
4da19633 2789 rtl_writephy(tp, 0x1f, 0x0002);
76564428
CHL		 2790 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
2791 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2792
4da19633 2793 rtl_writephy(tp, 0x1f, 0x0005);
2794 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 2795
2796 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
bca03d5f 2797
4da19633 2798 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2799}
2800
bca03d5f 2801static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2802{
fcb40e16 2803 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_0);
5b538df9 2804
fdf6fc06 2805 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
daf9df6d 2806 int val;
2807
fcb40e16 2808 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_1);
daf9df6d 2809
4da19633 2810 val = rtl_readphy(tp, 0x0d);
daf9df6d 2811 if ((val & 0x00ff) != 0x006c) {
b6bc7650 2812 static const u32 set[] = {
daf9df6d 2813 0x0065, 0x0066, 0x0067, 0x0068,
2814 0x0069, 0x006a, 0x006b, 0x006c
2815 };
2816 int i;
2817
4da19633 2818 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2819
2820 val &= 0xff00;
2821 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2822 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2823 }
2824 } else {
350f7596 2825 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2826 { 0x1f, 0x0002 },
2827 { 0x05, 0x2642 },
5b538df9 2828 { 0x1f, 0x0005 },
daf9df6d 2829 { 0x05, 0x8330 },
2830 { 0x06, 0x2642 }
5b538df9
FR		 2831 };
2832
1791ad50 2833 rtl_writephy_batch(tp, phy_reg_init);
5b538df9
FR		 2834 }
2835
bca03d5f 2836 /* Fine tune PLL performance */
4da19633 2837 rtl_writephy(tp, 0x1f, 0x0002);
76564428
CHL		 2838 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
2839 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2840
bca03d5f 2841 /* Switching regulator Slew rate */
4da19633 2842 rtl_writephy(tp, 0x1f, 0x0002);
2843 rtl_patchphy(tp, 0x0f, 0x0017);
daf9df6d 2844
4da19633 2845 rtl_writephy(tp, 0x1f, 0x0005);
2846 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 2847
2848 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
bca03d5f 2849
4da19633 2850 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2851}
2852
4da19633 2853static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2854{
350f7596 2855 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2856 { 0x1f, 0x0002 },
2857 { 0x10, 0x0008 },
2858 { 0x0d, 0x006c },
2859
2860 { 0x1f, 0x0000 },
2861 { 0x0d, 0xf880 },
2862
2863 { 0x1f, 0x0001 },
2864 { 0x17, 0x0cc0 },
2865
2866 { 0x1f, 0x0001 },
2867 { 0x0b, 0xa4d8 },
2868 { 0x09, 0x281c },
2869 { 0x07, 0x2883 },
2870 { 0x0a, 0x6b35 },
2871 { 0x1d, 0x3da4 },
2872 { 0x1c, 0xeffd },
2873 { 0x14, 0x7f52 },
2874 { 0x18, 0x7fc6 },
2875 { 0x08, 0x0601 },
2876 { 0x06, 0x4063 },
2877 { 0x10, 0xf074 },
2878 { 0x1f, 0x0003 },
2879 { 0x13, 0x0789 },
2880 { 0x12, 0xf4bd },
2881 { 0x1a, 0x04fd },
2882 { 0x14, 0x84b0 },
2883 { 0x1f, 0x0000 },
2884 { 0x00, 0x9200 },
2885
2886 { 0x1f, 0x0005 },
2887 { 0x01, 0x0340 },
2888 { 0x1f, 0x0001 },
2889 { 0x04, 0x4000 },
2890 { 0x03, 0x1d21 },
2891 { 0x02, 0x0c32 },
2892 { 0x01, 0x0200 },
2893 { 0x00, 0x5554 },
2894 { 0x04, 0x4800 },
2895 { 0x04, 0x4000 },
2896 { 0x04, 0xf000 },
2897 { 0x03, 0xdf01 },
2898 { 0x02, 0xdf20 },
2899 { 0x01, 0x101a },
2900 { 0x00, 0xa0ff },
2901 { 0x04, 0xf800 },
2902 { 0x04, 0xf000 },
2903 { 0x1f, 0x0000 },
2904
2905 { 0x1f, 0x0007 },
2906 { 0x1e, 0x0023 },
2907 { 0x16, 0x0000 },
2908 { 0x1f, 0x0000 }
2909 };
2910
1791ad50 2911 rtl_writephy_batch(tp, phy_reg_init);
5b538df9
FR		 2912}
2913
e6de30d6 2914static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2915{
2916 static const struct phy_reg phy_reg_init[] = {
2917 { 0x1f, 0x0001 },
2918 { 0x17, 0x0cc0 },
2919
2920 { 0x1f, 0x0007 },
2921 { 0x1e, 0x002d },
2922 { 0x18, 0x0040 },
2923 { 0x1f, 0x0000 }
2924 };
2925
1791ad50 2926 rtl_writephy_batch(tp, phy_reg_init);
e6de30d6 2927 rtl_patchphy(tp, 0x0d, 1 << 5);
2928}
2929
70090424 2930static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
01dc7fec 2931{
2932 static const struct phy_reg phy_reg_init[] = {
2933 /* Enable Delay cap */
2934 { 0x1f, 0x0005 },
2935 { 0x05, 0x8b80 },
2936 { 0x06, 0xc896 },
2937 { 0x1f, 0x0000 },
2938
2939 /* Channel estimation fine tune */
2940 { 0x1f, 0x0001 },
2941 { 0x0b, 0x6c20 },
2942 { 0x07, 0x2872 },
2943 { 0x1c, 0xefff },
2944 { 0x1f, 0x0003 },
2945 { 0x14, 0x6420 },
2946 { 0x1f, 0x0000 },
2947
2948 /* Update PFM & 10M TX idle timer */
2949 { 0x1f, 0x0007 },
2950 { 0x1e, 0x002f },
2951 { 0x15, 0x1919 },
2952 { 0x1f, 0x0000 },
2953
2954 { 0x1f, 0x0007 },
2955 { 0x1e, 0x00ac },
2956 { 0x18, 0x0006 },
2957 { 0x1f, 0x0000 }
2958 };
2959
15ecd039
FR		 2960 rtl_apply_firmware(tp);
2961
1791ad50 2962 rtl_writephy_batch(tp, phy_reg_init);
01dc7fec 2963
2964 /* DCO enable for 10M IDLE Power */
2965 rtl_writephy(tp, 0x1f, 0x0007);
2966 rtl_writephy(tp, 0x1e, 0x0023);
76564428 2967 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
01dc7fec 2968 rtl_writephy(tp, 0x1f, 0x0000);
2969
2970 /* For impedance matching */
2971 rtl_writephy(tp, 0x1f, 0x0002);
76564428 2972 rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
cecb5fd7 2973 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 2974
2975 /* PHY auto speed down */
2976 rtl_writephy(tp, 0x1f, 0x0007);
2977 rtl_writephy(tp, 0x1e, 0x002d);
76564428 2978 rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
01dc7fec 2979 rtl_writephy(tp, 0x1f, 0x0000);
76564428 2980 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
01dc7fec 2981
2982 rtl_writephy(tp, 0x1f, 0x0005);
2983 rtl_writephy(tp, 0x05, 0x8b86);
76564428 2984 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
01dc7fec 2985 rtl_writephy(tp, 0x1f, 0x0000);
2986
2987 rtl_writephy(tp, 0x1f, 0x0005);
2988 rtl_writephy(tp, 0x05, 0x8b85);
76564428 2989 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
01dc7fec 2990 rtl_writephy(tp, 0x1f, 0x0007);
2991 rtl_writephy(tp, 0x1e, 0x0020);
76564428 2992 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
01dc7fec 2993 rtl_writephy(tp, 0x1f, 0x0006);
2994 rtl_writephy(tp, 0x00, 0x5a00);
2995 rtl_writephy(tp, 0x1f, 0x0000);
2996 rtl_writephy(tp, 0x0d, 0x0007);
2997 rtl_writephy(tp, 0x0e, 0x003c);
2998 rtl_writephy(tp, 0x0d, 0x4007);
2999 rtl_writephy(tp, 0x0e, 0x0000);
3000 rtl_writephy(tp, 0x0d, 0x0000);
3001}
3002
9ecb9aab 3003static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3004{
3005 const u16 w[] = {
3006 addr[0] | (addr[1] << 8),
3007 addr[2] | (addr[3] << 8),
3008 addr[4] | (addr[5] << 8)
3009 };
9ecb9aab 3010
3aa4c491
HK		 3011 rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, w[0] | (w[1] << 16));
3012 rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, w[2]);
3013 rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, w[0] << 16);
3014 rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, w[1] | (w[2] << 16));
9ecb9aab 3015}
3016
70090424
HW		 3017static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3018{
3019 static const struct phy_reg phy_reg_init[] = {
3020 /* Enable Delay cap */
3021 { 0x1f, 0x0004 },
3022 { 0x1f, 0x0007 },
3023 { 0x1e, 0x00ac },
3024 { 0x18, 0x0006 },
3025 { 0x1f, 0x0002 },
3026 { 0x1f, 0x0000 },
3027 { 0x1f, 0x0000 },
3028
3029 /* Channel estimation fine tune */
3030 { 0x1f, 0x0003 },
3031 { 0x09, 0xa20f },
3032 { 0x1f, 0x0000 },
3033 { 0x1f, 0x0000 },
3034
3035 /* Green Setting */
3036 { 0x1f, 0x0005 },
3037 { 0x05, 0x8b5b },
3038 { 0x06, 0x9222 },
3039 { 0x05, 0x8b6d },
3040 { 0x06, 0x8000 },
3041 { 0x05, 0x8b76 },
3042 { 0x06, 0x8000 },
3043 { 0x1f, 0x0000 }
3044 };
3045
3046 rtl_apply_firmware(tp);
3047
1791ad50 3048 rtl_writephy_batch(tp, phy_reg_init);
70090424
HW		 3049
3050 /* For 4-corner performance improve */
3051 rtl_writephy(tp, 0x1f, 0x0005);
3052 rtl_writephy(tp, 0x05, 0x8b80);
76564428 3053 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
70090424
HW		 3054 rtl_writephy(tp, 0x1f, 0x0000);
3055
3056 /* PHY auto speed down */
3057 rtl_writephy(tp, 0x1f, 0x0004);
3058 rtl_writephy(tp, 0x1f, 0x0007);
3059 rtl_writephy(tp, 0x1e, 0x002d);
76564428 3060 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
70090424
HW		 3061 rtl_writephy(tp, 0x1f, 0x0002);
3062 rtl_writephy(tp, 0x1f, 0x0000);
76564428 3063 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
70090424
HW		 3064
3065 /* improve 10M EEE waveform */
3066 rtl_writephy(tp, 0x1f, 0x0005);
3067 rtl_writephy(tp, 0x05, 0x8b86);
76564428 3068 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
70090424
HW		 3069 rtl_writephy(tp, 0x1f, 0x0000);
3070
3071 /* Improve 2-pair detection performance */
3072 rtl_writephy(tp, 0x1f, 0x0005);
3073 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3074 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
70090424
HW		 3075 rtl_writephy(tp, 0x1f, 0x0000);
3076
cc07d271 3077 rtl8168f_config_eee_phy(tp);
1563daa3 3078 rtl_enable_eee(tp);
70090424
HW		 3079
3080 /* Green feature */
3081 rtl_writephy(tp, 0x1f, 0x0003);
1814d6a8
HK		 3082 rtl_w0w1_phy(tp, 0x19, 0x0001, 0x0000);
3083 rtl_w0w1_phy(tp, 0x10, 0x0400, 0x0000);
70090424 3084 rtl_writephy(tp, 0x1f, 0x0000);
b399a394
HK		 3085 rtl_writephy(tp, 0x1f, 0x0005);
3086 rtl_w0w1_phy(tp, 0x01, 0x0100, 0x0000);
3087 rtl_writephy(tp, 0x1f, 0x0000);
e0c07557 3088
9ecb9aab 3089 /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3090 rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
70090424
HW		 3091}
3092
5f886e08
HW		 3093static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3094{
3095 /* For 4-corner performance improve */
3096 rtl_writephy(tp, 0x1f, 0x0005);
3097 rtl_writephy(tp, 0x05, 0x8b80);
76564428 3098 rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
5f886e08
HW		 3099 rtl_writephy(tp, 0x1f, 0x0000);
3100
3101 /* PHY auto speed down */
3102 rtl_writephy(tp, 0x1f, 0x0007);
3103 rtl_writephy(tp, 0x1e, 0x002d);
76564428 3104 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
5f886e08 3105 rtl_writephy(tp, 0x1f, 0x0000);
76564428 3106 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
5f886e08
HW		 3107
3108 /* Improve 10M EEE waveform */
3109 rtl_writephy(tp, 0x1f, 0x0005);
3110 rtl_writephy(tp, 0x05, 0x8b86);
76564428 3111 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
5f886e08 3112 rtl_writephy(tp, 0x1f, 0x0000);
cc07d271
HK		 3113
3114 rtl8168f_config_eee_phy(tp);
1563daa3 3115 rtl_enable_eee(tp);
5f886e08
HW		 3116}
3117
c2218925
HW		 3118static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3119{
3120 static const struct phy_reg phy_reg_init[] = {
3121 /* Channel estimation fine tune */
3122 { 0x1f, 0x0003 },
3123 { 0x09, 0xa20f },
3124 { 0x1f, 0x0000 },
3125
3126 /* Modify green table for giga & fnet */
3127 { 0x1f, 0x0005 },
3128 { 0x05, 0x8b55 },
3129 { 0x06, 0x0000 },
3130 { 0x05, 0x8b5e },
3131 { 0x06, 0x0000 },
3132 { 0x05, 0x8b67 },
3133 { 0x06, 0x0000 },
3134 { 0x05, 0x8b70 },
3135 { 0x06, 0x0000 },
3136 { 0x1f, 0x0000 },
3137 { 0x1f, 0x0007 },
3138 { 0x1e, 0x0078 },
3139 { 0x17, 0x0000 },
3140 { 0x19, 0x00fb },
3141 { 0x1f, 0x0000 },
3142
3143 /* Modify green table for 10M */
3144 { 0x1f, 0x0005 },
3145 { 0x05, 0x8b79 },
3146 { 0x06, 0xaa00 },
3147 { 0x1f, 0x0000 },
3148
3149 /* Disable hiimpedance detection (RTCT) */
3150 { 0x1f, 0x0003 },
3151 { 0x01, 0x328a },
3152 { 0x1f, 0x0000 }
3153 };
3154
3155 rtl_apply_firmware(tp);
3156
1791ad50 3157 rtl_writephy_batch(tp, phy_reg_init);
c2218925 3158
5f886e08 3159 rtl8168f_hw_phy_config(tp);
c2218925
HW		 3160
3161 /* Improve 2-pair detection performance */
3162 rtl_writephy(tp, 0x1f, 0x0005);
3163 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3164 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
c2218925
HW		 3165 rtl_writephy(tp, 0x1f, 0x0000);
3166}
3167
3168static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3169{
3170 rtl_apply_firmware(tp);
3171
5f886e08 3172 rtl8168f_hw_phy_config(tp);
c2218925
HW		 3173}
3174
b3d7b2f2
HW		 3175static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3176{
b3d7b2f2
HW		 3177 static const struct phy_reg phy_reg_init[] = {
3178 /* Channel estimation fine tune */
3179 { 0x1f, 0x0003 },
3180 { 0x09, 0xa20f },
3181 { 0x1f, 0x0000 },
3182
3183 /* Modify green table for giga & fnet */
3184 { 0x1f, 0x0005 },
3185 { 0x05, 0x8b55 },
3186 { 0x06, 0x0000 },
3187 { 0x05, 0x8b5e },
3188 { 0x06, 0x0000 },
3189 { 0x05, 0x8b67 },
3190 { 0x06, 0x0000 },
3191 { 0x05, 0x8b70 },
3192 { 0x06, 0x0000 },
3193 { 0x1f, 0x0000 },
3194 { 0x1f, 0x0007 },
3195 { 0x1e, 0x0078 },
3196 { 0x17, 0x0000 },
3197 { 0x19, 0x00aa },
3198 { 0x1f, 0x0000 },
3199
3200 /* Modify green table for 10M */
3201 { 0x1f, 0x0005 },
3202 { 0x05, 0x8b79 },
3203 { 0x06, 0xaa00 },
3204 { 0x1f, 0x0000 },
3205
3206 /* Disable hiimpedance detection (RTCT) */
3207 { 0x1f, 0x0003 },
3208 { 0x01, 0x328a },
3209 { 0x1f, 0x0000 }
3210 };
3211
3212
3213 rtl_apply_firmware(tp);
3214
3215 rtl8168f_hw_phy_config(tp);
3216
3217 /* Improve 2-pair detection performance */
3218 rtl_writephy(tp, 0x1f, 0x0005);
3219 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3220 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
b3d7b2f2
HW		 3221 rtl_writephy(tp, 0x1f, 0x0000);
3222
1791ad50 3223 rtl_writephy_batch(tp, phy_reg_init);
b3d7b2f2
HW		 3224
3225 /* Modify green table for giga */
3226 rtl_writephy(tp, 0x1f, 0x0005);
3227 rtl_writephy(tp, 0x05, 0x8b54);
76564428 3228 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
b3d7b2f2 3229 rtl_writephy(tp, 0x05, 0x8b5d);
76564428 3230 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
b3d7b2f2 3231 rtl_writephy(tp, 0x05, 0x8a7c);
76564428 3232 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
b3d7b2f2 3233 rtl_writephy(tp, 0x05, 0x8a7f);
76564428 3234 rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
b3d7b2f2 3235 rtl_writephy(tp, 0x05, 0x8a82);
76564428 3236 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
b3d7b2f2 3237 rtl_writephy(tp, 0x05, 0x8a85);
76564428 3238 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
b3d7b2f2 3239 rtl_writephy(tp, 0x05, 0x8a88);
76564428 3240 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
b3d7b2f2
HW		 3241 rtl_writephy(tp, 0x1f, 0x0000);
3242
3243 /* uc same-seed solution */
3244 rtl_writephy(tp, 0x1f, 0x0005);
3245 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3246 rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
b3d7b2f2
HW		 3247 rtl_writephy(tp, 0x1f, 0x0000);
3248
b3d7b2f2
HW		 3249 /* Green feature */
3250 rtl_writephy(tp, 0x1f, 0x0003);
76564428
CHL		 3251 rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3252 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
b3d7b2f2
HW		 3253 rtl_writephy(tp, 0x1f, 0x0000);
3254}
3255
c46863ab
HK		 3256static void rtl8168g_disable_aldps(struct rtl8169_private *tp)
3257{
a2928d28 3258 phy_modify_paged(tp->phydev, 0x0a43, 0x10, BIT(2), 0);
c46863ab
HK		 3259}
3260
a1ead2ec
HK		 3261static void rtl8168g_phy_adjust_10m_aldps(struct rtl8169_private *tp)
3262{
3263 struct phy_device *phydev = tp->phydev;
3264
a2928d28
HK		 3265 phy_modify_paged(phydev, 0x0bcc, 0x14, BIT(8), 0);
3266 phy_modify_paged(phydev, 0x0a44, 0x11, 0, BIT(7) | BIT(6));
424f2610
HK		 3267 r8168g_phy_param(phydev, 0x8084, 0x6000, 0x0000);
3268 phy_modify_paged(phydev, 0x0a43, 0x10, 0x0000, 0x1003);
a1ead2ec
HK		 3269}
3270
c558386b
HW		 3271static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3272{
a2928d28
HK		 3273 int ret;
3274
c558386b
HW		 3275 rtl_apply_firmware(tp);
3276
a2928d28
HK		 3277 ret = phy_read_paged(tp->phydev, 0x0a46, 0x10);
3278 if (ret & BIT(8))
3279 phy_modify_paged(tp->phydev, 0x0bcc, 0x12, BIT(15), 0);
3280 else
3281 phy_modify_paged(tp->phydev, 0x0bcc, 0x12, 0, BIT(15));
c558386b 3282
a2928d28
HK		 3283 ret = phy_read_paged(tp->phydev, 0x0a46, 0x13);
3284 if (ret & BIT(8))
1a03bb53 3285 phy_modify_paged(tp->phydev, 0x0c41, 0x15, 0, BIT(1));
a2928d28 3286 else
1a03bb53 3287 phy_modify_paged(tp->phydev, 0x0c41, 0x15, BIT(1), 0);
c558386b 3288
41f44d13 3289 /* Enable PHY auto speed down */
a2928d28 3290 phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(3) | BIT(2));
c558386b 3291
a1ead2ec 3292 rtl8168g_phy_adjust_10m_aldps(tp);
fe7524c0 3293
41f44d13 3294 /* EEE auto-fallback function */
a2928d28 3295 phy_modify_paged(tp->phydev, 0x0a4b, 0x11, 0, BIT(2));
c558386b 3296
41f44d13 3297 /* Enable UC LPF tune function */
424f2610 3298 r8168g_phy_param(tp->phydev, 0x8012, 0x0000, 0x8000);
41f44d13 3299
a2928d28 3300 phy_modify_paged(tp->phydev, 0x0c42, 0x11, BIT(13), BIT(14));
41f44d13 3301
fe7524c0 3302 /* Improve SWR Efficiency */
3303 rtl_writephy(tp, 0x1f, 0x0bcd);
3304 rtl_writephy(tp, 0x14, 0x5065);
3305 rtl_writephy(tp, 0x14, 0xd065);
3306 rtl_writephy(tp, 0x1f, 0x0bc8);
3307 rtl_writephy(tp, 0x11, 0x5655);
3308 rtl_writephy(tp, 0x1f, 0x0bcd);
3309 rtl_writephy(tp, 0x14, 0x1065);
3310 rtl_writephy(tp, 0x14, 0x9065);
3311 rtl_writephy(tp, 0x14, 0x1065);
a2928d28 3312 rtl_writephy(tp, 0x1f, 0x0000);
fe7524c0 3313
c46863ab 3314 rtl8168g_disable_aldps(tp);
df6f1856 3315 rtl8168g_config_eee_phy(tp);
b6c7fa40 3316 rtl_enable_eee(tp);
c558386b
HW		 3317}
3318
57538c4a 3319static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3320{
3321 rtl_apply_firmware(tp);
df6f1856 3322 rtl8168g_config_eee_phy(tp);
b6c7fa40 3323 rtl_enable_eee(tp);
57538c4a 3324}
3325
6e1d0b89
CHL		 3326static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3327{
424f2610 3328 struct phy_device *phydev = tp->phydev;
6e1d0b89
CHL		 3329 u16 dout_tapbin;
3330 u32 data;
3331
3332 rtl_apply_firmware(tp);
3333
3334 /* CHN EST parameters adjust - giga master */
424f2610
HK		 3335 r8168g_phy_param(phydev, 0x809b, 0xf800, 0x8000);
3336 r8168g_phy_param(phydev, 0x80a2, 0xff00, 0x8000);
3337 r8168g_phy_param(phydev, 0x80a4, 0xff00, 0x8500);
3338 r8168g_phy_param(phydev, 0x809c, 0xff00, 0xbd00);
6e1d0b89
CHL		 3339
3340 /* CHN EST parameters adjust - giga slave */
424f2610
HK		 3341 r8168g_phy_param(phydev, 0x80ad, 0xf800, 0x7000);
3342 r8168g_phy_param(phydev, 0x80b4, 0xff00, 0x5000);
3343 r8168g_phy_param(phydev, 0x80ac, 0xff00, 0x4000);
6e1d0b89
CHL		 3344
3345 /* CHN EST parameters adjust - fnet */
424f2610
HK		 3346 r8168g_phy_param(phydev, 0x808e, 0xff00, 0x1200);
3347 r8168g_phy_param(phydev, 0x8090, 0xff00, 0xe500);
3348 r8168g_phy_param(phydev, 0x8092, 0xff00, 0x9f00);
6e1d0b89
CHL		 3349
3350 /* enable R-tune & PGA-retune function */
3351 dout_tapbin = 0;
424f2610 3352 data = phy_read_paged(phydev, 0x0a46, 0x13);
6e1d0b89
CHL		 3353 data &= 3;
3354 data <<= 2;
3355 dout_tapbin |= data;
424f2610 3356 data = phy_read_paged(phydev, 0x0a46, 0x12);
6e1d0b89
CHL		 3357 data &= 0xc000;
3358 data >>= 14;
3359 dout_tapbin |= data;
3360 dout_tapbin = ~(dout_tapbin^0x08);
3361 dout_tapbin <<= 12;
3362 dout_tapbin &= 0xf000;
424f2610
HK		 3363
3364 r8168g_phy_param(phydev, 0x827a, 0xf000, dout_tapbin);
3365 r8168g_phy_param(phydev, 0x827b, 0xf000, dout_tapbin);
3366 r8168g_phy_param(phydev, 0x827c, 0xf000, dout_tapbin);
3367 r8168g_phy_param(phydev, 0x827d, 0xf000, dout_tapbin);
3368 r8168g_phy_param(phydev, 0x0811, 0x0000, 0x0800);
3369 phy_modify_paged(phydev, 0x0a42, 0x16, 0x0000, 0x0002);
6e1d0b89
CHL		 3370
3371 /* enable GPHY 10M */
a2928d28 3372 phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(11));
6e1d0b89
CHL		 3373
3374 /* SAR ADC performance */
a2928d28 3375 phy_modify_paged(tp->phydev, 0x0bca, 0x17, BIT(12) | BIT(13), BIT(14));
6e1d0b89 3376
424f2610
HK		 3377 r8168g_phy_param(phydev, 0x803f, 0x3000, 0x0000);
3378 r8168g_phy_param(phydev, 0x8047, 0x3000, 0x0000);
3379 r8168g_phy_param(phydev, 0x804f, 0x3000, 0x0000);
3380 r8168g_phy_param(phydev, 0x8057, 0x3000, 0x0000);
3381 r8168g_phy_param(phydev, 0x805f, 0x3000, 0x0000);
3382 r8168g_phy_param(phydev, 0x8067, 0x3000, 0x0000);
3383 r8168g_phy_param(phydev, 0x806f, 0x3000, 0x0000);
6e1d0b89
CHL		 3384
3385 /* disable phy pfm mode */
a2928d28 3386 phy_modify_paged(tp->phydev, 0x0a44, 0x11, BIT(7), 0);
6e1d0b89 3387
c46863ab 3388 rtl8168g_disable_aldps(tp);
b6cef26f 3389 rtl8168h_config_eee_phy(tp);
b6c7fa40 3390 rtl_enable_eee(tp);
6e1d0b89
CHL		 3391}
3392
3393static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
3394{
3395 u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
424f2610 3396 struct phy_device *phydev = tp->phydev;
6e1d0b89
CHL		 3397 u16 rlen;
3398 u32 data;
3399
3400 rtl_apply_firmware(tp);
3401
3402 /* CHIN EST parameter update */
424f2610 3403 r8168g_phy_param(phydev, 0x808a, 0x003f, 0x000a);
6e1d0b89
CHL		 3404
3405 /* enable R-tune & PGA-retune function */
424f2610
HK		 3406 r8168g_phy_param(phydev, 0x0811, 0x0000, 0x0800);
3407 phy_modify_paged(phydev, 0x0a42, 0x16, 0x0000, 0x0002);
6e1d0b89
CHL		 3408
3409 /* enable GPHY 10M */
a2928d28 3410 phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(11));
6e1d0b89
CHL		 3411
3412 r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
3413 data = r8168_mac_ocp_read(tp, 0xdd02);
3414 ioffset_p3 = ((data & 0x80)>>7);
3415 ioffset_p3 <<= 3;
3416
3417 data = r8168_mac_ocp_read(tp, 0xdd00);
3418 ioffset_p3 |= ((data & (0xe000))>>13);
3419 ioffset_p2 = ((data & (0x1e00))>>9);
3420 ioffset_p1 = ((data & (0x01e0))>>5);
3421 ioffset_p0 = ((data & 0x0010)>>4);
3422 ioffset_p0 <<= 3;
3423 ioffset_p0 |= (data & (0x07));
3424 data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
3425
05b9687b 3426 if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
424f2610
HK		 3427 (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f))
3428 phy_write_paged(phydev, 0x0bcf, 0x16, data);
6e1d0b89
CHL		 3429
3430 /* Modify rlen (TX LPF corner frequency) level */
424f2610 3431 data = phy_read_paged(phydev, 0x0bcd, 0x16);
6e1d0b89
CHL		 3432 data &= 0x000f;
3433 rlen = 0;
3434 if (data > 3)
3435 rlen = data - 3;
3436 data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
424f2610 3437 phy_write_paged(phydev, 0x0bcd, 0x17, data);
6e1d0b89
CHL		 3438
3439 /* disable phy pfm mode */
424f2610 3440 phy_modify_paged(phydev, 0x0a44, 0x11, BIT(7), 0);
6e1d0b89 3441
c46863ab 3442 rtl8168g_disable_aldps(tp);
df6f1856 3443 rtl8168g_config_eee_phy(tp);
b6c7fa40 3444 rtl_enable_eee(tp);
6e1d0b89
CHL		 3445}
3446
935e2218
CHL		 3447static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
3448{
424f2610
HK		 3449 struct phy_device *phydev = tp->phydev;
3450
935e2218 3451 /* Enable PHY auto speed down */
424f2610 3452 phy_modify_paged(phydev, 0x0a44, 0x11, 0, BIT(3) | BIT(2));
935e2218 3453
a1ead2ec 3454 rtl8168g_phy_adjust_10m_aldps(tp);
935e2218
CHL		 3455
3456 /* Enable EEE auto-fallback function */
424f2610 3457 phy_modify_paged(phydev, 0x0a4b, 0x11, 0, BIT(2));
935e2218
CHL		 3458
3459 /* Enable UC LPF tune function */
424f2610 3460 r8168g_phy_param(phydev, 0x8012, 0x0000, 0x8000);
935e2218
CHL		 3461
3462 /* set rg_sel_sdm_rate */
424f2610 3463 phy_modify_paged(phydev, 0x0c42, 0x11, BIT(13), BIT(14));
935e2218 3464
c46863ab 3465 rtl8168g_disable_aldps(tp);
df6f1856 3466 rtl8168g_config_eee_phy(tp);
b6c7fa40 3467 rtl_enable_eee(tp);
935e2218
CHL		 3468}
3469
3470static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
3471{
424f2610
HK		 3472 struct phy_device *phydev = tp->phydev;
3473
a1ead2ec 3474 rtl8168g_phy_adjust_10m_aldps(tp);
935e2218
CHL		 3475
3476 /* Enable UC LPF tune function */
424f2610 3477 r8168g_phy_param(phydev, 0x8012, 0x0000, 0x8000);
935e2218
CHL		 3478
3479 /* Set rg_sel_sdm_rate */
a2928d28 3480 phy_modify_paged(tp->phydev, 0x0c42, 0x11, BIT(13), BIT(14));
935e2218
CHL		 3481
3482 /* Channel estimation parameters */
424f2610
HK		 3483 r8168g_phy_param(phydev, 0x80f3, 0xff00, 0x8b00);
3484 r8168g_phy_param(phydev, 0x80f0, 0xff00, 0x3a00);
3485 r8168g_phy_param(phydev, 0x80ef, 0xff00, 0x0500);
3486 r8168g_phy_param(phydev, 0x80f6, 0xff00, 0x6e00);
3487 r8168g_phy_param(phydev, 0x80ec, 0xff00, 0x6800);
3488 r8168g_phy_param(phydev, 0x80ed, 0xff00, 0x7c00);
3489 r8168g_phy_param(phydev, 0x80f2, 0xff00, 0xf400);
3490 r8168g_phy_param(phydev, 0x80f4, 0xff00, 0x8500);
3491 r8168g_phy_param(phydev, 0x8110, 0xff00, 0xa800);
3492 r8168g_phy_param(phydev, 0x810f, 0xff00, 0x1d00);
3493 r8168g_phy_param(phydev, 0x8111, 0xff00, 0xf500);
3494 r8168g_phy_param(phydev, 0x8113, 0xff00, 0x6100);
3495 r8168g_phy_param(phydev, 0x8115, 0xff00, 0x9200);
3496 r8168g_phy_param(phydev, 0x810e, 0xff00, 0x0400);
3497 r8168g_phy_param(phydev, 0x810c, 0xff00, 0x7c00);
3498 r8168g_phy_param(phydev, 0x810b, 0xff00, 0x5a00);
3499 r8168g_phy_param(phydev, 0x80d1, 0xff00, 0xff00);
3500 r8168g_phy_param(phydev, 0x80cd, 0xff00, 0x9e00);
3501 r8168g_phy_param(phydev, 0x80d3, 0xff00, 0x0e00);
3502 r8168g_phy_param(phydev, 0x80d5, 0xff00, 0xca00);
3503 r8168g_phy_param(phydev, 0x80d7, 0xff00, 0x8400);
935e2218
CHL		 3504
3505 /* Force PWM-mode */
3506 rtl_writephy(tp, 0x1f, 0x0bcd);
3507 rtl_writephy(tp, 0x14, 0x5065);
3508 rtl_writephy(tp, 0x14, 0xd065);
3509 rtl_writephy(tp, 0x1f, 0x0bc8);
3510 rtl_writephy(tp, 0x12, 0x00ed);
3511 rtl_writephy(tp, 0x1f, 0x0bcd);
3512 rtl_writephy(tp, 0x14, 0x1065);
3513 rtl_writephy(tp, 0x14, 0x9065);
3514 rtl_writephy(tp, 0x14, 0x1065);
3515 rtl_writephy(tp, 0x1f, 0x0000);
3516
c46863ab 3517 rtl8168g_disable_aldps(tp);
df6f1856 3518 rtl8168g_config_eee_phy(tp);
b6c7fa40 3519 rtl_enable_eee(tp);
935e2218
CHL		 3520}
3521
2e13d773
HK		 3522static void rtl8117_hw_phy_config(struct rtl8169_private *tp)
3523{
3524 struct phy_device *phydev = tp->phydev;
3525
3526 /* CHN EST parameters adjust - fnet */
3527 r8168g_phy_param(phydev, 0x808e, 0xff00, 0x4800);
3528 r8168g_phy_param(phydev, 0x8090, 0xff00, 0xcc00);
3529 r8168g_phy_param(phydev, 0x8092, 0xff00, 0xb000);
3530
3531 r8168g_phy_param(phydev, 0x8088, 0xff00, 0x6000);
3532 r8168g_phy_param(phydev, 0x808b, 0x3f00, 0x0b00);
3533 r8168g_phy_param(phydev, 0x808d, 0x1f00, 0x0600);
3534 r8168g_phy_param(phydev, 0x808c, 0xff00, 0xb000);
3535 r8168g_phy_param(phydev, 0x80a0, 0xff00, 0x2800);
3536 r8168g_phy_param(phydev, 0x80a2, 0xff00, 0x5000);
3537 r8168g_phy_param(phydev, 0x809b, 0xf800, 0xb000);
3538 r8168g_phy_param(phydev, 0x809a, 0xff00, 0x4b00);
3539 r8168g_phy_param(phydev, 0x809d, 0x3f00, 0x0800);
3540 r8168g_phy_param(phydev, 0x80a1, 0xff00, 0x7000);
3541 r8168g_phy_param(phydev, 0x809f, 0x1f00, 0x0300);
3542 r8168g_phy_param(phydev, 0x809e, 0xff00, 0x8800);
3543 r8168g_phy_param(phydev, 0x80b2, 0xff00, 0x2200);
3544 r8168g_phy_param(phydev, 0x80ad, 0xf800, 0x9800);
3545 r8168g_phy_param(phydev, 0x80af, 0x3f00, 0x0800);
3546 r8168g_phy_param(phydev, 0x80b3, 0xff00, 0x6f00);
3547 r8168g_phy_param(phydev, 0x80b1, 0x1f00, 0x0300);
3548 r8168g_phy_param(phydev, 0x80b0, 0xff00, 0x9300);
3549
3550 r8168g_phy_param(phydev, 0x8011, 0x0000, 0x0800);
3551
3552 /* enable GPHY 10M */
3553 phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(11));
3554
3555 r8168g_phy_param(phydev, 0x8016, 0x0000, 0x0400);
3556
3557 rtl8168g_disable_aldps(tp);
3558 rtl8168h_config_eee_phy(tp);
3559 rtl_enable_eee(tp);
3560}
3561
4da19633 3562static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2857ffb7 3563{
350f7596 3564 static const struct phy_reg phy_reg_init[] = {
2857ffb7
FR		 3565 { 0x1f, 0x0003 },
3566 { 0x08, 0x441d },
3567 { 0x01, 0x9100 },
3568 { 0x1f, 0x0000 }
3569 };
3570
4da19633 3571 rtl_writephy(tp, 0x1f, 0x0000);
3572 rtl_patchphy(tp, 0x11, 1 << 12);
3573 rtl_patchphy(tp, 0x19, 1 << 13);
3574 rtl_patchphy(tp, 0x10, 1 << 15);
2857ffb7 3575
1791ad50 3576 rtl_writephy_batch(tp, phy_reg_init);
2857ffb7
FR		 3577}
3578
5a5e4443
HW		 3579static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3580{
3581 static const struct phy_reg phy_reg_init[] = {
3582 { 0x1f, 0x0005 },
3583 { 0x1a, 0x0000 },
3584 { 0x1f, 0x0000 },
3585
3586 { 0x1f, 0x0004 },
3587 { 0x1c, 0x0000 },
3588 { 0x1f, 0x0000 },
3589
3590 { 0x1f, 0x0001 },
3591 { 0x15, 0x7701 },
3592 { 0x1f, 0x0000 }
3593 };
3594
3595 /* Disable ALDPS before ram code */
eef63cc1
FR		 3596 rtl_writephy(tp, 0x1f, 0x0000);
3597 rtl_writephy(tp, 0x18, 0x0310);
3598 msleep(100);
5a5e4443 3599
953a12cc 3600 rtl_apply_firmware(tp);
5a5e4443 3601
1791ad50 3602 rtl_writephy_batch(tp, phy_reg_init);
5a5e4443
HW		 3603}
3604
7e18dca1
HW		 3605static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
3606{
7e18dca1 3607 /* Disable ALDPS before setting firmware */
eef63cc1
FR		 3608 rtl_writephy(tp, 0x1f, 0x0000);
3609 rtl_writephy(tp, 0x18, 0x0310);
3610 msleep(20);
7e18dca1
HW		 3611
3612 rtl_apply_firmware(tp);
3613
3614 /* EEE setting */
724c6fd0 3615 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
7e18dca1
HW		 3616 rtl_writephy(tp, 0x1f, 0x0004);
3617 rtl_writephy(tp, 0x10, 0x401f);
3618 rtl_writephy(tp, 0x19, 0x7030);
3619 rtl_writephy(tp, 0x1f, 0x0000);
3620}
3621
5598bfe5
HW		 3622static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
3623{
5598bfe5
HW		 3624 static const struct phy_reg phy_reg_init[] = {
3625 { 0x1f, 0x0004 },
3626 { 0x10, 0xc07f },
3627 { 0x19, 0x7030 },
3628 { 0x1f, 0x0000 }
3629 };
3630
3631 /* Disable ALDPS before ram code */
eef63cc1
FR		 3632 rtl_writephy(tp, 0x1f, 0x0000);
3633 rtl_writephy(tp, 0x18, 0x0310);
3634 msleep(100);
5598bfe5
HW		 3635
3636 rtl_apply_firmware(tp);
3637
724c6fd0 3638 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
1791ad50 3639 rtl_writephy_batch(tp, phy_reg_init);
5598bfe5 3640
724c6fd0 3641 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
5598bfe5
HW		 3642}
3643
02bf642b
HK		 3644static void rtl8125_1_hw_phy_config(struct rtl8169_private *tp)
3645{
3646 struct phy_device *phydev = tp->phydev;
3647
3648 phy_modify_paged(phydev, 0xad4, 0x10, 0x03ff, 0x0084);
3649 phy_modify_paged(phydev, 0xad4, 0x17, 0x0000, 0x0010);
3650 phy_modify_paged(phydev, 0xad1, 0x13, 0x03ff, 0x0006);
3651 phy_modify_paged(phydev, 0xad3, 0x11, 0x003f, 0x0006);
3652 phy_modify_paged(phydev, 0xac0, 0x14, 0x0000, 0x1100);
3653 phy_modify_paged(phydev, 0xac8, 0x15, 0xf000, 0x7000);
3654 phy_modify_paged(phydev, 0xad1, 0x14, 0x0000, 0x0400);
3655 phy_modify_paged(phydev, 0xad1, 0x15, 0x0000, 0x03ff);
3656 phy_modify_paged(phydev, 0xad1, 0x16, 0x0000, 0x03ff);
3657
424f2610
HK		 3658 r8168g_phy_param(phydev, 0x80ea, 0xff00, 0xc400);
3659 r8168g_phy_param(phydev, 0x80eb, 0x0700, 0x0300);
3660 r8168g_phy_param(phydev, 0x80f8, 0xff00, 0x1c00);
3661 r8168g_phy_param(phydev, 0x80f1, 0xff00, 0x3000);
3662 r8168g_phy_param(phydev, 0x80fe, 0xff00, 0xa500);
3663 r8168g_phy_param(phydev, 0x8102, 0xff00, 0x5000);
3664 r8168g_phy_param(phydev, 0x8105, 0xff00, 0x3300);
3665 r8168g_phy_param(phydev, 0x8100, 0xff00, 0x7000);
3666 r8168g_phy_param(phydev, 0x8104, 0xff00, 0xf000);
3667 r8168g_phy_param(phydev, 0x8106, 0xff00, 0x6500);
3668 r8168g_phy_param(phydev, 0x80dc, 0xff00, 0xed00);
3669 r8168g_phy_param(phydev, 0x80df, 0x0000, 0x0100);
3670 r8168g_phy_param(phydev, 0x80e1, 0x0100, 0x0000);
02bf642b
HK		 3671
3672 phy_modify_paged(phydev, 0xbf0, 0x13, 0x003f, 0x0038);
424f2610 3673 r8168g_phy_param(phydev, 0x819f, 0xffff, 0xd0b6);
02bf642b
HK		 3674
3675 phy_write_paged(phydev, 0xbc3, 0x12, 0x5555);
3676 phy_modify_paged(phydev, 0xbf0, 0x15, 0x0e00, 0x0a00);
3677 phy_modify_paged(phydev, 0xa5c, 0x10, 0x0400, 0x0000);
3678 phy_modify_paged(phydev, 0xa44, 0x11, 0x0000, 0x0800);
b3a42e3a
HK		 3679
3680 rtl8125_config_eee_phy(tp);
3681 rtl_enable_eee(tp);
02bf642b
HK		 3682}
3683
3684static void rtl8125_2_hw_phy_config(struct rtl8169_private *tp)
3685{
3686 struct phy_device *phydev = tp->phydev;
3687 int i;
3688
3689 phy_modify_paged(phydev, 0xad4, 0x17, 0x0000, 0x0010);
3690 phy_modify_paged(phydev, 0xad1, 0x13, 0x03ff, 0x03ff);
3691 phy_modify_paged(phydev, 0xad3, 0x11, 0x003f, 0x0006);
3692 phy_modify_paged(phydev, 0xac0, 0x14, 0x1100, 0x0000);
3693 phy_modify_paged(phydev, 0xacc, 0x10, 0x0003, 0x0002);
3694 phy_modify_paged(phydev, 0xad4, 0x10, 0x00e7, 0x0044);
3695 phy_modify_paged(phydev, 0xac1, 0x12, 0x0080, 0x0000);
3696 phy_modify_paged(phydev, 0xac8, 0x10, 0x0300, 0x0000);
3697 phy_modify_paged(phydev, 0xac5, 0x17, 0x0007, 0x0002);
3698 phy_write_paged(phydev, 0xad4, 0x16, 0x00a8);
3699 phy_write_paged(phydev, 0xac5, 0x16, 0x01ff);
3700 phy_modify_paged(phydev, 0xac8, 0x15, 0x00f0, 0x0030);
3701
3702 phy_write(phydev, 0x1f, 0x0b87);
3703 phy_write(phydev, 0x16, 0x80a2);
3704 phy_write(phydev, 0x17, 0x0153);
3705 phy_write(phydev, 0x16, 0x809c);
3706 phy_write(phydev, 0x17, 0x0153);
3707 phy_write(phydev, 0x1f, 0x0000);
3708
3709 phy_write(phydev, 0x1f, 0x0a43);
3710 phy_write(phydev, 0x13, 0x81B3);
3711 phy_write(phydev, 0x14, 0x0043);
3712 phy_write(phydev, 0x14, 0x00A7);
3713 phy_write(phydev, 0x14, 0x00D6);
3714 phy_write(phydev, 0x14, 0x00EC);
3715 phy_write(phydev, 0x14, 0x00F6);
3716 phy_write(phydev, 0x14, 0x00FB);
3717 phy_write(phydev, 0x14, 0x00FD);
3718 phy_write(phydev, 0x14, 0x00FF);
3719 phy_write(phydev, 0x14, 0x00BB);
3720 phy_write(phydev, 0x14, 0x0058);
3721 phy_write(phydev, 0x14, 0x0029);
3722 phy_write(phydev, 0x14, 0x0013);
3723 phy_write(phydev, 0x14, 0x0009);
3724 phy_write(phydev, 0x14, 0x0004);
3725 phy_write(phydev, 0x14, 0x0002);
3726 for (i = 0; i < 25; i++)
3727 phy_write(phydev, 0x14, 0x0000);
02bf642b
HK		 3728 phy_write(phydev, 0x1f, 0x0000);
3729
424f2610
HK		 3730 r8168g_phy_param(phydev, 0x8257, 0xffff, 0x020F);
3731 r8168g_phy_param(phydev, 0x80ea, 0xffff, 0x7843);
3732
02bf642b
HK		 3733 rtl_apply_firmware(tp);
3734
3735 phy_modify_paged(phydev, 0xd06, 0x14, 0x0000, 0x2000);
3736
424f2610 3737 r8168g_phy_param(phydev, 0x81a2, 0x0000, 0x0100);
02bf642b
HK		 3738
3739 phy_modify_paged(phydev, 0xb54, 0x16, 0xff00, 0xdb00);
3740 phy_modify_paged(phydev, 0xa45, 0x12, 0x0001, 0x0000);
3741 phy_modify_paged(phydev, 0xa5d, 0x12, 0x0000, 0x0020);
3742 phy_modify_paged(phydev, 0xad4, 0x17, 0x0010, 0x0000);
3743 phy_modify_paged(phydev, 0xa86, 0x15, 0x0001, 0x0000);
3744 phy_modify_paged(phydev, 0xa44, 0x11, 0x0000, 0x0800);
b3a42e3a
HK		 3745
3746 rtl8125_config_eee_phy(tp);
3747 rtl_enable_eee(tp);
02bf642b
HK		 3748}
3749
5615d9f1
FR		 3750static void rtl_hw_phy_config(struct net_device *dev)
3751{
1fcd1658
HK		 3752 static const rtl_generic_fct phy_configs[] = {
3753 /* PCI devices. */
1fcd1658
HK		 3754 [RTL_GIGA_MAC_VER_02] = rtl8169s_hw_phy_config,
3755 [RTL_GIGA_MAC_VER_03] = rtl8169s_hw_phy_config,
3756 [RTL_GIGA_MAC_VER_04] = rtl8169sb_hw_phy_config,
3757 [RTL_GIGA_MAC_VER_05] = rtl8169scd_hw_phy_config,
3758 [RTL_GIGA_MAC_VER_06] = rtl8169sce_hw_phy_config,
3759 /* PCI-E devices. */
3760 [RTL_GIGA_MAC_VER_07] = rtl8102e_hw_phy_config,
3761 [RTL_GIGA_MAC_VER_08] = rtl8102e_hw_phy_config,
3762 [RTL_GIGA_MAC_VER_09] = rtl8102e_hw_phy_config,
3763 [RTL_GIGA_MAC_VER_10] = NULL,
3764 [RTL_GIGA_MAC_VER_11] = rtl8168bb_hw_phy_config,
3765 [RTL_GIGA_MAC_VER_12] = rtl8168bef_hw_phy_config,
3766 [RTL_GIGA_MAC_VER_13] = NULL,
3767 [RTL_GIGA_MAC_VER_14] = NULL,
3768 [RTL_GIGA_MAC_VER_15] = NULL,
3769 [RTL_GIGA_MAC_VER_16] = NULL,
3770 [RTL_GIGA_MAC_VER_17] = rtl8168bef_hw_phy_config,
3771 [RTL_GIGA_MAC_VER_18] = rtl8168cp_1_hw_phy_config,
3772 [RTL_GIGA_MAC_VER_19] = rtl8168c_1_hw_phy_config,
3773 [RTL_GIGA_MAC_VER_20] = rtl8168c_2_hw_phy_config,
3774 [RTL_GIGA_MAC_VER_21] = rtl8168c_3_hw_phy_config,
3775 [RTL_GIGA_MAC_VER_22] = rtl8168c_4_hw_phy_config,
3776 [RTL_GIGA_MAC_VER_23] = rtl8168cp_2_hw_phy_config,
3777 [RTL_GIGA_MAC_VER_24] = rtl8168cp_2_hw_phy_config,
3778 [RTL_GIGA_MAC_VER_25] = rtl8168d_1_hw_phy_config,
3779 [RTL_GIGA_MAC_VER_26] = rtl8168d_2_hw_phy_config,
3780 [RTL_GIGA_MAC_VER_27] = rtl8168d_3_hw_phy_config,
3781 [RTL_GIGA_MAC_VER_28] = rtl8168d_4_hw_phy_config,
3782 [RTL_GIGA_MAC_VER_29] = rtl8105e_hw_phy_config,
3783 [RTL_GIGA_MAC_VER_30] = rtl8105e_hw_phy_config,
3784 [RTL_GIGA_MAC_VER_31] = NULL,
3785 [RTL_GIGA_MAC_VER_32] = rtl8168e_1_hw_phy_config,
3786 [RTL_GIGA_MAC_VER_33] = rtl8168e_1_hw_phy_config,
3787 [RTL_GIGA_MAC_VER_34] = rtl8168e_2_hw_phy_config,
3788 [RTL_GIGA_MAC_VER_35] = rtl8168f_1_hw_phy_config,
3789 [RTL_GIGA_MAC_VER_36] = rtl8168f_2_hw_phy_config,
3790 [RTL_GIGA_MAC_VER_37] = rtl8402_hw_phy_config,
3791 [RTL_GIGA_MAC_VER_38] = rtl8411_hw_phy_config,
3792 [RTL_GIGA_MAC_VER_39] = rtl8106e_hw_phy_config,
3793 [RTL_GIGA_MAC_VER_40] = rtl8168g_1_hw_phy_config,
3794 [RTL_GIGA_MAC_VER_41] = NULL,
3795 [RTL_GIGA_MAC_VER_42] = rtl8168g_2_hw_phy_config,
3796 [RTL_GIGA_MAC_VER_43] = rtl8168g_2_hw_phy_config,
3797 [RTL_GIGA_MAC_VER_44] = rtl8168g_2_hw_phy_config,
3798 [RTL_GIGA_MAC_VER_45] = rtl8168h_1_hw_phy_config,
3799 [RTL_GIGA_MAC_VER_46] = rtl8168h_2_hw_phy_config,
3800 [RTL_GIGA_MAC_VER_47] = rtl8168h_1_hw_phy_config,
3801 [RTL_GIGA_MAC_VER_48] = rtl8168h_2_hw_phy_config,
3802 [RTL_GIGA_MAC_VER_49] = rtl8168ep_1_hw_phy_config,
3803 [RTL_GIGA_MAC_VER_50] = rtl8168ep_2_hw_phy_config,
3804 [RTL_GIGA_MAC_VER_51] = rtl8168ep_2_hw_phy_config,
2e13d773 3805 [RTL_GIGA_MAC_VER_52] = rtl8117_hw_phy_config,
02bf642b
HK		 3806 [RTL_GIGA_MAC_VER_60] = rtl8125_1_hw_phy_config,
3807 [RTL_GIGA_MAC_VER_61] = rtl8125_2_hw_phy_config,
1fcd1658 3808 };
5615d9f1 3809 struct rtl8169_private *tp = netdev_priv(dev);
5615d9f1 3810
1fcd1658
HK		 3811 if (phy_configs[tp->mac_version])
3812 phy_configs[tp->mac_version](tp);
5615d9f1
FR		 3813}
3814
da78dbff
FR		 3815static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
3816{
da78dbff
FR		 3817 if (!test_and_set_bit(flag, tp->wk.flags))
3818 schedule_work(&tp->wk.work);
da78dbff
FR		 3819}
3820
4ff96fa6
FR		 3821static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3822{
5615d9f1 3823 rtl_hw_phy_config(dev);
4ff96fa6 3824
77332894 3825 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
7a67e11d
HK		 3826 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3827 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
49d17512
HK		 3828 netif_dbg(tp, drv, dev,
3829 "Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1ef7286e 3830 RTL_W8(tp, 0x82, 0x01);
77332894 3831 }
4ff96fa6 3832
5b7ad4b7 3833 /* We may have called phy_speed_down before */
703732f0 3834 phy_speed_up(tp->phydev);
5b7ad4b7 3835
703732f0 3836 genphy_soft_reset(tp->phydev);
4ff96fa6
FR		 3837}
3838
773d2021
FR		 3839static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3840{
da78dbff 3841 rtl_lock_work(tp);
773d2021 3842
df320ed7 3843 rtl_unlock_config_regs(tp);
908ba2bf 3844
1ef7286e
AS		 3845 RTL_W32(tp, MAC4, addr[4] | addr[5] << 8);
3846 RTL_R32(tp, MAC4);
908ba2bf 3847
1ef7286e
AS		 3848 RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
3849 RTL_R32(tp, MAC0);
908ba2bf 3850
9ecb9aab 3851 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
3852 rtl_rar_exgmac_set(tp, addr);
c28aa385 3853
df320ed7 3854 rtl_lock_config_regs(tp);
773d2021 3855
da78dbff 3856 rtl_unlock_work(tp);
773d2021
FR		 3857}
3858
3859static int rtl_set_mac_address(struct net_device *dev, void *p)
3860{
3861 struct rtl8169_private *tp = netdev_priv(dev);
1e1205b7 3862 struct device *d = tp_to_dev(tp);
1f7aa2bc 3863 int ret;
773d2021 3864
1f7aa2bc
HK		 3865 ret = eth_mac_addr(dev, p);
3866 if (ret)
3867 return ret;
773d2021 3868
f51d4a10
CHL		 3869 pm_runtime_get_noresume(d);
3870
3871 if (pm_runtime_active(d))
3872 rtl_rar_set(tp, dev->dev_addr);
3873
3874 pm_runtime_put_noidle(d);
773d2021
FR		 3875
3876 return 0;
3877}
3878
e397286b 3879static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
8b4ab28d 3880{
703732f0
HK		 3881 struct rtl8169_private *tp = netdev_priv(dev);
3882
69b3c59f
HK		 3883 if (!netif_running(dev))
3884 return -ENODEV;
e397286b 3885
703732f0 3886 return phy_mii_ioctl(tp->phydev, ifr, cmd);
8b4ab28d
FR		 3887}
3888
649b3b8c 3889static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
3890{
649b3b8c 3891 switch (tp->mac_version) {
b00e69de
CB		 3892 case RTL_GIGA_MAC_VER_25:
3893 case RTL_GIGA_MAC_VER_26:
649b3b8c 3894 case RTL_GIGA_MAC_VER_29:
3895 case RTL_GIGA_MAC_VER_30:
3896 case RTL_GIGA_MAC_VER_32:
3897 case RTL_GIGA_MAC_VER_33:
3898 case RTL_GIGA_MAC_VER_34:
50a03386 3899 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_61:
1ef7286e 3900 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
649b3b8c 3901 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3902 break;
3903 default:
3904 break;
3905 }
3906}
3907
25e94115 3908static void rtl_pll_power_down(struct rtl8169_private *tp)
065c27c1 3909{
9dbe7896 3910 if (r8168_check_dash(tp))
065c27c1 3911 return;
3912
01dc7fec 3913 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3914 tp->mac_version == RTL_GIGA_MAC_VER_33)
fdf6fc06 3915 rtl_ephy_write(tp, 0x19, 0xff64);
01dc7fec 3916
5ea25b12
HK		 3917 if (device_may_wakeup(tp_to_dev(tp))) {
3918 phy_speed_down(tp->phydev, false);
3919 rtl_wol_suspend_quirk(tp);
065c27c1 3920 return;
5ea25b12 3921 }
065c27c1 3922
065c27c1 3923 switch (tp->mac_version) {
5fdd9182 3924 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_26:
78c420de 3925 case RTL_GIGA_MAC_VER_29 ... RTL_GIGA_MAC_VER_30:
5fdd9182 3926 case RTL_GIGA_MAC_VER_32 ... RTL_GIGA_MAC_VER_33:
73570bf1
HK		 3927 case RTL_GIGA_MAC_VER_37:
3928 case RTL_GIGA_MAC_VER_39:
3929 case RTL_GIGA_MAC_VER_43:
42fde737 3930 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 3931 case RTL_GIGA_MAC_VER_45:
3932 case RTL_GIGA_MAC_VER_46:
73570bf1
HK		 3933 case RTL_GIGA_MAC_VER_47:
3934 case RTL_GIGA_MAC_VER_48:
935e2218
CHL		 3935 case RTL_GIGA_MAC_VER_50:
3936 case RTL_GIGA_MAC_VER_51:
2e13d773 3937 case RTL_GIGA_MAC_VER_52:
f1bce4ad
HK		 3938 case RTL_GIGA_MAC_VER_60:
3939 case RTL_GIGA_MAC_VER_61:
1ef7286e 3940 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
065c27c1 3941 break;
beb330a4 3942 case RTL_GIGA_MAC_VER_40:
3943 case RTL_GIGA_MAC_VER_41:
935e2218 3944 case RTL_GIGA_MAC_VER_49:
e719b3ea 3945 rtl_eri_clear_bits(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000);
1ef7286e 3946 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
beb330a4 3947 break;
76719ee2
HK		 3948 default:
3949 break;
065c27c1 3950 }
3951}
3952
25e94115 3953static void rtl_pll_power_up(struct rtl8169_private *tp)
065c27c1 3954{
065c27c1 3955 switch (tp->mac_version) {
5fdd9182 3956 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_26:
78c420de 3957 case RTL_GIGA_MAC_VER_29 ... RTL_GIGA_MAC_VER_30:
5fdd9182 3958 case RTL_GIGA_MAC_VER_32 ... RTL_GIGA_MAC_VER_33:
73570bf1
HK		 3959 case RTL_GIGA_MAC_VER_37:
3960 case RTL_GIGA_MAC_VER_39:
3961 case RTL_GIGA_MAC_VER_43:
1ef7286e 3962 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80);
065c27c1 3963 break;
42fde737 3964 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 3965 case RTL_GIGA_MAC_VER_45:
3966 case RTL_GIGA_MAC_VER_46:
73570bf1
HK		 3967 case RTL_GIGA_MAC_VER_47:
3968 case RTL_GIGA_MAC_VER_48:
935e2218
CHL		 3969 case RTL_GIGA_MAC_VER_50:
3970 case RTL_GIGA_MAC_VER_51:
2e13d773 3971 case RTL_GIGA_MAC_VER_52:
f1bce4ad
HK		 3972 case RTL_GIGA_MAC_VER_60:
3973 case RTL_GIGA_MAC_VER_61:
1ef7286e 3974 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
6e1d0b89 3975 break;
beb330a4 3976 case RTL_GIGA_MAC_VER_40:
3977 case RTL_GIGA_MAC_VER_41:
935e2218 3978 case RTL_GIGA_MAC_VER_49:
1ef7286e 3979 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
e719b3ea 3980 rtl_eri_set_bits(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000);
beb330a4 3981 break;
76719ee2
HK		 3982 default:
3983 break;
065c27c1 3984 }
3985
703732f0 3986 phy_resume(tp->phydev);
242cd9b5
HK		 3987 /* give MAC/PHY some time to resume */
3988 msleep(20);
065c27c1 3989}
3990
e542a226
HW		 3991static void rtl_init_rxcfg(struct rtl8169_private *tp)
3992{
e542a226 3993 switch (tp->mac_version) {
e9588eb9 3994 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
2a71883c 3995 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
1ef7286e 3996 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
e542a226 3997 break;
2a71883c 3998 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
511cfd58
MS		 3999 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
4000 case RTL_GIGA_MAC_VER_38:
1ef7286e 4001 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
e542a226 4002 break;
2e13d773 4003 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_52:
1ef7286e 4004 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
beb330a4 4005 break;
f1bce4ad
HK		 4006 case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_61:
4007 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_VLAN_8125 |
4008 RX_DMA_BURST);
4009 break;
e542a226 4010 default:
1ef7286e 4011 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
e542a226
HW		 4012 break;
4013 }
4014}
4015
92fc43b4
HW		 4016static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4017{
9fba0812 4018 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
92fc43b4
HW		 4019}
4020
d58d46b5
FR		 4021static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
4022{
1ef7286e
AS		 4023 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4024 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
d58d46b5
FR		 4025}
4026
4027static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
4028{
1ef7286e
AS		 4029 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4030 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
d58d46b5
FR		 4031}
4032
4033static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
4034{
1ef7286e 4035 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
d58d46b5
FR		 4036}
4037
4038static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
4039{
1ef7286e 4040 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
d58d46b5
FR		 4041}
4042
4043static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
4044{
141cd70d 4045 RTL_W8(tp, MaxTxPacketSize, 0x24);
1ef7286e
AS		 4046 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4047 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
d58d46b5
FR		 4048}
4049
4050static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
4051{
141cd70d 4052 RTL_W8(tp, MaxTxPacketSize, 0x3f);
1ef7286e
AS		 4053 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4054 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
d58d46b5
FR		 4055}
4056
4057static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
4058{
cb875de1
HK		 4059 pcie_capability_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
4060 PCI_EXP_DEVCTL_NOSNOOP_EN);
d58d46b5
FR		 4061}
4062
4063static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
4064{
cb875de1
HK		 4065 pcie_capability_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
4066 PCI_EXP_DEVCTL_NOSNOOP_EN);
d58d46b5
FR		 4067}
4068
4069static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
4070{
d58d46b5
FR		 4071 r8168b_0_hw_jumbo_enable(tp);
4072
1ef7286e 4073 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
d58d46b5
FR		 4074}
4075
4076static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
4077{
d58d46b5
FR		 4078 r8168b_0_hw_jumbo_disable(tp);
4079
1ef7286e 4080 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
d58d46b5
FR		 4081}
4082
485bb1b3 4083static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
d58d46b5 4084{
485bb1b3 4085 rtl_unlock_config_regs(tp);
d58d46b5
FR		 4086 switch (tp->mac_version) {
4087 case RTL_GIGA_MAC_VER_11:
485bb1b3 4088 r8168b_0_hw_jumbo_enable(tp);
d58d46b5
FR		 4089 break;
4090 case RTL_GIGA_MAC_VER_12:
4091 case RTL_GIGA_MAC_VER_17:
485bb1b3 4092 r8168b_1_hw_jumbo_enable(tp);
d58d46b5 4093 break;
485bb1b3
HK		 4094 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26:
4095 r8168c_hw_jumbo_enable(tp);
d58d46b5 4096 break;
485bb1b3
HK		 4097 case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28:
4098 r8168dp_hw_jumbo_enable(tp);
d58d46b5 4099 break;
9e7d190e 4100 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33:
485bb1b3
HK		 4101 r8168e_hw_jumbo_enable(tp);
4102 break;
4103 default:
d58d46b5 4104 break;
485bb1b3
HK		 4105 }
4106 rtl_lock_config_regs(tp);
4107}
d58d46b5 4108
485bb1b3
HK		 4109static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4110{
4111 rtl_unlock_config_regs(tp);
4112 switch (tp->mac_version) {
4113 case RTL_GIGA_MAC_VER_11:
4114 r8168b_0_hw_jumbo_disable(tp);
4115 break;
4116 case RTL_GIGA_MAC_VER_12:
4117 case RTL_GIGA_MAC_VER_17:
4118 r8168b_1_hw_jumbo_disable(tp);
4119 break;
4120 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26:
4121 r8168c_hw_jumbo_disable(tp);
4122 break;
4123 case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28:
4124 r8168dp_hw_jumbo_disable(tp);
4125 break;
2618eff1 4126 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33:
485bb1b3
HK		 4127 r8168e_hw_jumbo_disable(tp);
4128 break;
d58d46b5 4129 default:
d58d46b5
FR		 4130 break;
4131 }
485bb1b3 4132 rtl_lock_config_regs(tp);
d58d46b5
FR		 4133}
4134
4ebcb113
HK		 4135static void rtl_jumbo_config(struct rtl8169_private *tp, int mtu)
4136{
4137 if (mtu > ETH_DATA_LEN)
4138 rtl_hw_jumbo_enable(tp);
4139 else
4140 rtl_hw_jumbo_disable(tp);
4141}
4142
ffc46952
FR		 4143DECLARE_RTL_COND(rtl_chipcmd_cond)
4144{
1ef7286e 4145 return RTL_R8(tp, ChipCmd) & CmdReset;
ffc46952
FR		 4146}
4147
6f43adc8
FR		 4148static void rtl_hw_reset(struct rtl8169_private *tp)
4149{
1ef7286e 4150 RTL_W8(tp, ChipCmd, CmdReset);
6f43adc8 4151
ffc46952 4152 rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
6f43adc8
FR		 4153}
4154
254764e5 4155static void rtl_request_firmware(struct rtl8169_private *tp)
953a12cc 4156{
b6ffd97f 4157 struct rtl_fw *rtl_fw;
953a12cc 4158
254764e5
HK		 4159 /* firmware loaded already or no firmware available */
4160 if (tp->rtl_fw || !tp->fw_name)
4161 return;
953a12cc 4162
b6ffd97f 4163 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
47ad5931
HK		 4164 if (!rtl_fw) {
4165 netif_warn(tp, ifup, tp->dev, "Unable to load firmware, out of memory\n");
4166 return;
4167 }
31bd204f 4168
ce8843ab
HK		 4169 rtl_fw->phy_write = rtl_writephy;
4170 rtl_fw->phy_read = rtl_readphy;
4171 rtl_fw->mac_mcu_write = mac_mcu_write;
4172 rtl_fw->mac_mcu_read = mac_mcu_read;
4edb00f3
HK		 4173 rtl_fw->fw_name = tp->fw_name;
4174 rtl_fw->dev = tp_to_dev(tp);
ce8843ab 4175
47ad5931
HK		 4176 if (rtl_fw_request_firmware(rtl_fw))
4177 kfree(rtl_fw);
4178 else
4179 tp->rtl_fw = rtl_fw;
953a12cc
FR		 4180}
4181
92fc43b4
HW		 4182static void rtl_rx_close(struct rtl8169_private *tp)
4183{
1ef7286e 4184 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
92fc43b4
HW		 4185}
4186
ffc46952
FR		 4187DECLARE_RTL_COND(rtl_npq_cond)
4188{
1ef7286e 4189 return RTL_R8(tp, TxPoll) & NPQ;
ffc46952
FR		 4190}
4191
4192DECLARE_RTL_COND(rtl_txcfg_empty_cond)
4193{
1ef7286e 4194 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
ffc46952
FR		 4195}
4196
e6de30d6 4197static void rtl8169_hw_reset(struct rtl8169_private *tp)
1da177e4
LT		 4198{
4199 /* Disable interrupts */
811fd301 4200 rtl8169_irq_mask_and_ack(tp);
1da177e4 4201
92fc43b4
HW		 4202 rtl_rx_close(tp);
4203
b2d43e6e
HK		 4204 switch (tp->mac_version) {
4205 case RTL_GIGA_MAC_VER_27:
4206 case RTL_GIGA_MAC_VER_28:
4207 case RTL_GIGA_MAC_VER_31:
ffc46952 4208 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
b2d43e6e
HK		 4209 break;
4210 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
2e13d773 4211 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_52:
1ef7286e 4212 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
ffc46952 4213 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
b2d43e6e
HK		 4214 break;
4215 default:
1ef7286e 4216 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
92fc43b4 4217 udelay(100);
b2d43e6e 4218 break;
e6de30d6 4219 }
4220
92fc43b4 4221 rtl_hw_reset(tp);
1da177e4
LT		 4222}
4223
05212ba8 4224static void rtl_set_tx_config_registers(struct rtl8169_private *tp)
9cb427b6 4225{
ad5f97fa
HK		 4226 u32 val = TX_DMA_BURST << TxDMAShift |
4227 InterFrameGap << TxInterFrameGapShift;
4228
9e9f33ba 4229 if (rtl_is_8168evl_up(tp))
ad5f97fa
HK		 4230 val |= TXCFG_AUTO_FIFO;
4231
4232 RTL_W32(tp, TxConfig, val);
9cb427b6
FR		 4233}
4234
4fd48c4a 4235static void rtl_set_rx_max_size(struct rtl8169_private *tp)
1da177e4 4236{
4fd48c4a
HK		 4237 /* Low hurts. Let's disable the filtering. */
4238 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
07ce4064
FR		 4239}
4240
1ef7286e 4241static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
7f796d83
FR		 4242{
4243 /*
4244 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4245 * register to be written before TxDescAddrLow to work.
4246 * Switching from MMIO to I/O access fixes the issue as well.
4247 */
1ef7286e
AS		 4248 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4249 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4250 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4251 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
7f796d83
FR		 4252}
4253
1ef7286e 4254static void rtl8169_set_magic_reg(struct rtl8169_private *tp, unsigned mac_version)
6dccd16b 4255{
34bc0095
HK		 4256 u32 val;
4257
4258 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4259 val = 0x000fff00;
4260 else if (tp->mac_version == RTL_GIGA_MAC_VER_06)
4261 val = 0x00ffff00;
4262 else
4263 return;
4264
4265 if (RTL_R8(tp, Config2) & PCI_Clock_66MHz)
4266 val |= 0xff;
4267
4268 RTL_W32(tp, 0x7c, val);
6dccd16b
FR		 4269}
4270
e6b763ea
FR		 4271static void rtl_set_rx_mode(struct net_device *dev)
4272{
81cd17a4
HK		 4273 u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast;
4274 /* Multicast hash filter */
4275 u32 mc_filter[2] = { 0xffffffff, 0xffffffff };
e6b763ea 4276 struct rtl8169_private *tp = netdev_priv(dev);
81cd17a4 4277 u32 tmp;
e6b763ea
FR		 4278
4279 if (dev->flags & IFF_PROMISC) {
4280 /* Unconditionally log net taps. */
4281 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
81cd17a4
HK		 4282 rx_mode |= AcceptAllPhys;
4283 } else if (netdev_mc_count(dev) > MC_FILTER_LIMIT ||
4284 dev->flags & IFF_ALLMULTI ||
4285 tp->mac_version == RTL_GIGA_MAC_VER_35) {
4286 /* accept all multicasts */
4287 } else if (netdev_mc_empty(dev)) {
4288 rx_mode &= ~AcceptMulticast;
e6b763ea
FR		 4289 } else {
4290 struct netdev_hw_addr *ha;
4291
e6b763ea
FR		 4292 mc_filter[1] = mc_filter[0] = 0;
4293 netdev_for_each_mc_addr(ha, dev) {
81cd17a4
HK		 4294 u32 bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4295 mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31);
4296 }
4297
4298 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4299 tmp = mc_filter[0];
4300 mc_filter[0] = swab32(mc_filter[1]);
4301 mc_filter[1] = swab32(tmp);
e6b763ea
FR		 4302 }
4303 }
4304
4305 if (dev->features & NETIF_F_RXALL)
4306 rx_mode |= (AcceptErr | AcceptRunt);
4307
1ef7286e
AS		 4308 RTL_W32(tp, MAR0 + 4, mc_filter[1]);
4309 RTL_W32(tp, MAR0 + 0, mc_filter[0]);
e6b763ea 4310
81cd17a4
HK		 4311 tmp = RTL_R32(tp, RxConfig);
4312 RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_MASK) | rx_mode);
e6b763ea
FR		 4313}
4314
ffc46952
FR		 4315DECLARE_RTL_COND(rtl_csiar_cond)
4316{
1ef7286e 4317 return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
ffc46952
FR		 4318}
4319
ff1d7331 4320static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
beb1fe18 4321{
ff1d7331 4322 u32 func = PCI_FUNC(tp->pci_dev->devfn);
beb1fe18 4323
1ef7286e
AS		 4324 RTL_W32(tp, CSIDR, value);
4325 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
ff1d7331 4326 CSIAR_BYTE_ENABLE | func << 16);
7e18dca1 4327
ffc46952 4328 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
7e18dca1
HW		 4329}
4330
ff1d7331 4331static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
7e18dca1 4332{
ff1d7331
HK		 4333 u32 func = PCI_FUNC(tp->pci_dev->devfn);
4334
4335 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
4336 CSIAR_BYTE_ENABLE);
7e18dca1 4337
ffc46952 4338 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
1ef7286e 4339 RTL_R32(tp, CSIDR) : ~0;
7e18dca1
HW		 4340}
4341
ff1d7331 4342static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val)
45dd95c4 4343{
ff1d7331
HK		 4344 struct pci_dev *pdev = tp->pci_dev;
4345 u32 csi;
45dd95c4 4346
ff1d7331
HK		 4347 /* According to Realtek the value at config space address 0x070f
4348 * controls the L0s/L1 entrance latency. We try standard ECAM access
4349 * first and if it fails fall back to CSI.
4350 */
4351 if (pdev->cfg_size > 0x070f &&
4352 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL)
4353 return;
4354
4355 netdev_notice_once(tp->dev,
4356 "No native access to PCI extended config space, falling back to CSI\n");
4357 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
4358 rtl_csi_write(tp, 0x070c, csi | val << 24);
45dd95c4 4359}
4360
f37658da 4361static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
beb1fe18 4362{
ff1d7331 4363 rtl_csi_access_enable(tp, 0x27);
dacf8154
FR		 4364}
4365
4366struct ephy_info {
4367 unsigned int offset;
4368 u16 mask;
4369 u16 bits;
4370};
4371
1791ad50
HK		 4372static void __rtl_ephy_init(struct rtl8169_private *tp,
4373 const struct ephy_info *e, int len)
dacf8154
FR		 4374{
4375 u16 w;
4376
4377 while (len-- > 0) {
fdf6fc06
FR		 4378 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
4379 rtl_ephy_write(tp, e->offset, w);
dacf8154
FR		 4380 e++;
4381 }
4382}
4383
1791ad50
HK		 4384#define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a))
4385
73c86ee3 4386static void rtl_disable_clock_request(struct rtl8169_private *tp)
b726e493 4387{
73c86ee3 4388 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
7d7903b2 4389 PCI_EXP_LNKCTL_CLKREQ_EN);
b726e493
FR		 4390}
4391
73c86ee3 4392static void rtl_enable_clock_request(struct rtl8169_private *tp)
e6de30d6 4393{
73c86ee3 4394 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
7d7903b2 4395 PCI_EXP_LNKCTL_CLKREQ_EN);
e6de30d6 4396}
4397
c259b7f4 4398static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp)
b51ecea8 4399{
c259b7f4
HK		 4400 /* work around an issue when PCI reset occurs during L2/L3 state */
4401 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23);
b51ecea8 4402}
4403
a99790bf
KHF		 4404static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
4405{
62b1b3b3
HK		 4406 /* Don't enable ASPM in the chip if OS can't control ASPM */
4407 if (enable && tp->aspm_manageable) {
a99790bf 4408 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en);
94235460 4409 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn);
a99790bf
KHF		 4410 } else {
4411 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
4412 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
4413 }
94235460
KHF		 4414
4415 udelay(10);
a99790bf
KHF		 4416}
4417
6b1bd242
HK		 4418static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat,
4419 u16 tx_stat, u16 rx_dyn, u16 tx_dyn)
4420{
4421 /* Usage of dynamic vs. static FIFO is controlled by bit
4422 * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known.
4423 */
4424 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn);
4425 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn);
4426}
4427
0ebacd12
HK		 4428static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp,
4429 u8 low, u8 high)
4430{
4431 /* FIFO thresholds for pause flow control */
4432 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low);
4433 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high);
4434}
4435
beb1fe18 4436static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
219a1e9d 4437{
1ef7286e 4438 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
219a1e9d
FR		 4439}
4440
beb1fe18 4441static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
219a1e9d 4442{
beb1fe18 4443 rtl_hw_start_8168bb(tp);
b726e493 4444
1ef7286e 4445 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
219a1e9d
FR		 4446}
4447
beb1fe18 4448static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
219a1e9d 4449{
1ef7286e 4450 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
b726e493 4451
1ef7286e 4452 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
b726e493 4453
73c86ee3 4454 rtl_disable_clock_request(tp);
219a1e9d
FR		 4455}
4456
beb1fe18 4457static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
219a1e9d 4458{
350f7596 4459 static const struct ephy_info e_info_8168cp[] = {
b726e493
FR		 4460 { 0x01, 0, 0x0001 },
4461 { 0x02, 0x0800, 0x1000 },
4462 { 0x03, 0, 0x0042 },
4463 { 0x06, 0x0080, 0x0000 },
4464 { 0x07, 0, 0x2000 }
4465 };
4466
f37658da 4467 rtl_set_def_aspm_entry_latency(tp);
b726e493 4468
1791ad50 4469 rtl_ephy_init(tp, e_info_8168cp);
b726e493 4470
beb1fe18 4471 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 4472}
4473
beb1fe18 4474static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
ef3386f0 4475{
f37658da 4476 rtl_set_def_aspm_entry_latency(tp);
ef3386f0 4477
1ef7286e 4478 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
ef3386f0
FR		 4479}
4480
beb1fe18 4481static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
7f3e3d3a 4482{
f37658da 4483 rtl_set_def_aspm_entry_latency(tp);
7f3e3d3a 4484
1ef7286e 4485 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
7f3e3d3a
FR		 4486
4487 /* Magic. */
1ef7286e 4488 RTL_W8(tp, DBG_REG, 0x20);
7f3e3d3a
FR		 4489}
4490
beb1fe18 4491static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
219a1e9d 4492{
350f7596 4493 static const struct ephy_info e_info_8168c_1[] = {
b726e493
FR		 4494 { 0x02, 0x0800, 0x1000 },
4495 { 0x03, 0, 0x0002 },
4496 { 0x06, 0x0080, 0x0000 }
4497 };
4498
f37658da 4499 rtl_set_def_aspm_entry_latency(tp);
b726e493 4500
1ef7286e 4501 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
b726e493 4502
1791ad50 4503 rtl_ephy_init(tp, e_info_8168c_1);
b726e493 4504
beb1fe18 4505 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 4506}
4507
beb1fe18 4508static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
219a1e9d 4509{
350f7596 4510 static const struct ephy_info e_info_8168c_2[] = {
b726e493 4511 { 0x01, 0, 0x0001 },
a7a92cf8 4512 { 0x03, 0x0400, 0x0020 }
b726e493
FR		 4513 };
4514
f37658da 4515 rtl_set_def_aspm_entry_latency(tp);
b726e493 4516
1791ad50 4517 rtl_ephy_init(tp, e_info_8168c_2);
b726e493 4518
beb1fe18 4519 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 4520}
4521
beb1fe18 4522static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
197ff761 4523{
beb1fe18 4524 rtl_hw_start_8168c_2(tp);
197ff761
FR		 4525}
4526
beb1fe18 4527static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
6fb07058 4528{
f37658da 4529 rtl_set_def_aspm_entry_latency(tp);
6fb07058 4530
beb1fe18 4531 __rtl_hw_start_8168cp(tp);
6fb07058
FR		 4532}
4533
beb1fe18 4534static void rtl_hw_start_8168d(struct rtl8169_private *tp)
5b538df9 4535{
f37658da 4536 rtl_set_def_aspm_entry_latency(tp);
5b538df9 4537
73c86ee3 4538 rtl_disable_clock_request(tp);
5b538df9
FR		 4539}
4540
beb1fe18 4541static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
4804b3b3 4542{
f37658da 4543 rtl_set_def_aspm_entry_latency(tp);
4804b3b3 4544
73c86ee3 4545 rtl_disable_clock_request(tp);
4804b3b3 4546}
4547
beb1fe18 4548static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
e6de30d6 4549{
4550 static const struct ephy_info e_info_8168d_4[] = {
1016a4a1
CHL		 4551 { 0x0b, 0x0000, 0x0048 },
4552 { 0x19, 0x0020, 0x0050 },
a7a92cf8
HK		 4553 { 0x0c, 0x0100, 0x0020 },
4554 { 0x10, 0x0004, 0x0000 },
e6de30d6 4555 };
e6de30d6 4556
f37658da 4557 rtl_set_def_aspm_entry_latency(tp);
e6de30d6 4558
1791ad50 4559 rtl_ephy_init(tp, e_info_8168d_4);
e6de30d6 4560
73c86ee3 4561 rtl_enable_clock_request(tp);
e6de30d6 4562}
4563
beb1fe18 4564static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
01dc7fec 4565{
70090424 4566 static const struct ephy_info e_info_8168e_1[] = {
01dc7fec 4567 { 0x00, 0x0200, 0x0100 },
4568 { 0x00, 0x0000, 0x0004 },
4569 { 0x06, 0x0002, 0x0001 },
4570 { 0x06, 0x0000, 0x0030 },
4571 { 0x07, 0x0000, 0x2000 },
4572 { 0x00, 0x0000, 0x0020 },
4573 { 0x03, 0x5800, 0x2000 },
4574 { 0x03, 0x0000, 0x0001 },
4575 { 0x01, 0x0800, 0x1000 },
4576 { 0x07, 0x0000, 0x4000 },
4577 { 0x1e, 0x0000, 0x2000 },
4578 { 0x19, 0xffff, 0xfe6c },
4579 { 0x0a, 0x0000, 0x0040 }
4580 };
4581
f37658da 4582 rtl_set_def_aspm_entry_latency(tp);
01dc7fec 4583
1791ad50 4584 rtl_ephy_init(tp, e_info_8168e_1);
01dc7fec 4585
73c86ee3 4586 rtl_disable_clock_request(tp);
01dc7fec 4587
4588 /* Reset tx FIFO pointer */
1ef7286e
AS		 4589 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
4590 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
01dc7fec 4591
1ef7286e 4592 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
01dc7fec 4593}
4594
beb1fe18 4595static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
70090424
HW		 4596{
4597 static const struct ephy_info e_info_8168e_2[] = {
4598 { 0x09, 0x0000, 0x0080 },
a7a92cf8
HK		 4599 { 0x19, 0x0000, 0x0224 },
4600 { 0x00, 0x0000, 0x0004 },
4601 { 0x0c, 0x3df0, 0x0200 },
70090424
HW		 4602 };
4603
f37658da 4604 rtl_set_def_aspm_entry_latency(tp);
70090424 4605
1791ad50 4606 rtl_ephy_init(tp, e_info_8168e_2);
70090424 4607
724c6fd0
HK		 4608 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4609 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
6b1bd242 4610 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
724c6fd0
HK		 4611 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
4612 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060);
e719b3ea 4613 rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4));
724c6fd0 4614 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00);
70090424 4615
73c86ee3 4616 rtl_disable_clock_request(tp);
4521e1a9 4617
1ef7286e 4618 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
70090424 4619
cc07d271
HK		 4620 rtl8168_config_eee_mac(tp);
4621
1ef7286e
AS		 4622 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
4623 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
4624 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
aa1e7d2c
HK		 4625
4626 rtl_hw_aspm_clkreq_enable(tp, true);
70090424
HW		 4627}
4628
5f886e08 4629static void rtl_hw_start_8168f(struct rtl8169_private *tp)
c2218925 4630{
f37658da 4631 rtl_set_def_aspm_entry_latency(tp);
c2218925 4632
724c6fd0
HK		 4633 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4634 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
6b1bd242 4635 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
4e7e4621 4636 rtl_reset_packet_filter(tp);
e719b3ea
HK		 4637 rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4));
4638 rtl_eri_set_bits(tp, 0x1d0, ERIAR_MASK_0001, BIT(4));
724c6fd0
HK		 4639 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
4640 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060);
c2218925 4641
73c86ee3 4642 rtl_disable_clock_request(tp);
4521e1a9 4643
1ef7286e
AS		 4644 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
4645 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
4646 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
4647 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
cc07d271
HK		 4648
4649 rtl8168_config_eee_mac(tp);
c2218925
HW		 4650}
4651
5f886e08
HW		 4652static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
4653{
5f886e08
HW		 4654 static const struct ephy_info e_info_8168f_1[] = {
4655 { 0x06, 0x00c0, 0x0020 },
4656 { 0x08, 0x0001, 0x0002 },
4657 { 0x09, 0x0000, 0x0080 },
a7a92cf8 4658 { 0x19, 0x0000, 0x0224 },
13e242b6 4659 { 0x00, 0x0000, 0x0008 },
a7a92cf8 4660 { 0x0c, 0x3df0, 0x0200 },
5f886e08
HW		 4661 };
4662
4663 rtl_hw_start_8168f(tp);
4664
1791ad50 4665 rtl_ephy_init(tp, e_info_8168f_1);
5f886e08 4666
724c6fd0 4667 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00);
5f886e08
HW		 4668}
4669
b3d7b2f2
HW		 4670static void rtl_hw_start_8411(struct rtl8169_private *tp)
4671{
b3d7b2f2
HW		 4672 static const struct ephy_info e_info_8168f_1[] = {
4673 { 0x06, 0x00c0, 0x0020 },
4674 { 0x0f, 0xffff, 0x5200 },
a7a92cf8 4675 { 0x19, 0x0000, 0x0224 },
13e242b6 4676 { 0x00, 0x0000, 0x0008 },
a7a92cf8 4677 { 0x0c, 0x3df0, 0x0200 },
b3d7b2f2
HW		 4678 };
4679
4680 rtl_hw_start_8168f(tp);
c259b7f4 4681 rtl_pcie_state_l2l3_disable(tp);
b3d7b2f2 4682
1791ad50 4683 rtl_ephy_init(tp, e_info_8168f_1);
b3d7b2f2 4684
e719b3ea 4685 rtl_eri_set_bits(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00);
b3d7b2f2
HW		 4686}
4687
5fbea337 4688static void rtl_hw_start_8168g(struct rtl8169_private *tp)
c558386b 4689{
6b1bd242 4690 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
0ebacd12 4691 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
c558386b 4692
f37658da 4693 rtl_set_def_aspm_entry_latency(tp);
c558386b 4694
4e7e4621 4695 rtl_reset_packet_filter(tp);
724c6fd0 4696 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f);
c558386b 4697
1ef7286e 4698 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
c558386b 4699
724c6fd0
HK		 4700 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4701 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
c558386b 4702
df6f1856
HK		 4703 rtl8168_config_eee_mac(tp);
4704
724c6fd0 4705 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06);
e719b3ea 4706 rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12));
b51ecea8 4707
c259b7f4 4708 rtl_pcie_state_l2l3_disable(tp);
c558386b
HW		 4709}
4710
5fbea337
CHL		 4711static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
4712{
5fbea337 4713 static const struct ephy_info e_info_8168g_1[] = {
a7a92cf8
HK		 4714 { 0x00, 0x0008, 0x0000 },
4715 { 0x0c, 0x3ff0, 0x0820 },
5fbea337
CHL		 4716 { 0x1e, 0x0000, 0x0001 },
4717 { 0x19, 0x8000, 0x0000 }
4718 };
4719
4720 rtl_hw_start_8168g(tp);
4721
4722 /* disable aspm and clock request before access ephy */
a99790bf 4723 rtl_hw_aspm_clkreq_enable(tp, false);
1791ad50 4724 rtl_ephy_init(tp, e_info_8168g_1);
a99790bf 4725 rtl_hw_aspm_clkreq_enable(tp, true);
5fbea337
CHL		 4726}
4727
57538c4a 4728static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
4729{
57538c4a 4730 static const struct ephy_info e_info_8168g_2[] = {
a7a92cf8
HK		 4731 { 0x00, 0x0008, 0x0000 },
4732 { 0x0c, 0x3ff0, 0x0820 },
4733 { 0x19, 0xffff, 0x7c00 },
4734 { 0x1e, 0xffff, 0x20eb },
4735 { 0x0d, 0xffff, 0x1666 },
4736 { 0x00, 0xffff, 0x10a3 },
4737 { 0x06, 0xffff, 0xf050 },
4738 { 0x04, 0x0000, 0x0010 },
4739 { 0x1d, 0x4000, 0x0000 },
57538c4a 4740 };
4741
5fbea337 4742 rtl_hw_start_8168g(tp);
57538c4a 4743
4744 /* disable aspm and clock request before access ephy */
1ef7286e
AS		 4745 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
4746 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
1791ad50 4747 rtl_ephy_init(tp, e_info_8168g_2);
57538c4a 4748}
4749
45dd95c4 4750static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
4751{
45dd95c4 4752 static const struct ephy_info e_info_8411_2[] = {
a7a92cf8
HK		 4753 { 0x00, 0x0008, 0x0000 },
4754 { 0x0c, 0x37d0, 0x0820 },
4755 { 0x1e, 0x0000, 0x0001 },
4756 { 0x19, 0x8021, 0x0000 },
4757 { 0x1e, 0x0000, 0x2000 },
4758 { 0x0d, 0x0100, 0x0200 },
4759 { 0x00, 0x0000, 0x0080 },
4760 { 0x06, 0x0000, 0x0010 },
4761 { 0x04, 0x0000, 0x0010 },
4762 { 0x1d, 0x0000, 0x4000 },
45dd95c4 4763 };
4764
5fbea337 4765 rtl_hw_start_8168g(tp);
45dd95c4 4766
4767 /* disable aspm and clock request before access ephy */
a99790bf 4768 rtl_hw_aspm_clkreq_enable(tp, false);
1791ad50 4769 rtl_ephy_init(tp, e_info_8411_2);
fe4e8db0
HK		 4770
4771 /* The following Realtek-provided magic fixes an issue with the RX unit
4772 * getting confused after the PHY having been powered-down.
4773 */
4774 r8168_mac_ocp_write(tp, 0xFC28, 0x0000);
4775 r8168_mac_ocp_write(tp, 0xFC2A, 0x0000);
4776 r8168_mac_ocp_write(tp, 0xFC2C, 0x0000);
4777 r8168_mac_ocp_write(tp, 0xFC2E, 0x0000);
4778 r8168_mac_ocp_write(tp, 0xFC30, 0x0000);
4779 r8168_mac_ocp_write(tp, 0xFC32, 0x0000);
4780 r8168_mac_ocp_write(tp, 0xFC34, 0x0000);
4781 r8168_mac_ocp_write(tp, 0xFC36, 0x0000);
4782 mdelay(3);
4783 r8168_mac_ocp_write(tp, 0xFC26, 0x0000);
4784
4785 r8168_mac_ocp_write(tp, 0xF800, 0xE008);
4786 r8168_mac_ocp_write(tp, 0xF802, 0xE00A);
4787 r8168_mac_ocp_write(tp, 0xF804, 0xE00C);
4788 r8168_mac_ocp_write(tp, 0xF806, 0xE00E);
4789 r8168_mac_ocp_write(tp, 0xF808, 0xE027);
4790 r8168_mac_ocp_write(tp, 0xF80A, 0xE04F);
4791 r8168_mac_ocp_write(tp, 0xF80C, 0xE05E);
4792 r8168_mac_ocp_write(tp, 0xF80E, 0xE065);
4793 r8168_mac_ocp_write(tp, 0xF810, 0xC602);
4794 r8168_mac_ocp_write(tp, 0xF812, 0xBE00);
4795 r8168_mac_ocp_write(tp, 0xF814, 0x0000);
4796 r8168_mac_ocp_write(tp, 0xF816, 0xC502);
4797 r8168_mac_ocp_write(tp, 0xF818, 0xBD00);
4798 r8168_mac_ocp_write(tp, 0xF81A, 0x074C);
4799 r8168_mac_ocp_write(tp, 0xF81C, 0xC302);
4800 r8168_mac_ocp_write(tp, 0xF81E, 0xBB00);
4801 r8168_mac_ocp_write(tp, 0xF820, 0x080A);
4802 r8168_mac_ocp_write(tp, 0xF822, 0x6420);
4803 r8168_mac_ocp_write(tp, 0xF824, 0x48C2);
4804 r8168_mac_ocp_write(tp, 0xF826, 0x8C20);
4805 r8168_mac_ocp_write(tp, 0xF828, 0xC516);
4806 r8168_mac_ocp_write(tp, 0xF82A, 0x64A4);
4807 r8168_mac_ocp_write(tp, 0xF82C, 0x49C0);
4808 r8168_mac_ocp_write(tp, 0xF82E, 0xF009);
4809 r8168_mac_ocp_write(tp, 0xF830, 0x74A2);
4810 r8168_mac_ocp_write(tp, 0xF832, 0x8CA5);
4811 r8168_mac_ocp_write(tp, 0xF834, 0x74A0);
4812 r8168_mac_ocp_write(tp, 0xF836, 0xC50E);
4813 r8168_mac_ocp_write(tp, 0xF838, 0x9CA2);
4814 r8168_mac_ocp_write(tp, 0xF83A, 0x1C11);
4815 r8168_mac_ocp_write(tp, 0xF83C, 0x9CA0);
4816 r8168_mac_ocp_write(tp, 0xF83E, 0xE006);
4817 r8168_mac_ocp_write(tp, 0xF840, 0x74F8);
4818 r8168_mac_ocp_write(tp, 0xF842, 0x48C4);
4819 r8168_mac_ocp_write(tp, 0xF844, 0x8CF8);
4820 r8168_mac_ocp_write(tp, 0xF846, 0xC404);
4821 r8168_mac_ocp_write(tp, 0xF848, 0xBC00);
4822 r8168_mac_ocp_write(tp, 0xF84A, 0xC403);
4823 r8168_mac_ocp_write(tp, 0xF84C, 0xBC00);
4824 r8168_mac_ocp_write(tp, 0xF84E, 0x0BF2);
4825 r8168_mac_ocp_write(tp, 0xF850, 0x0C0A);
4826 r8168_mac_ocp_write(tp, 0xF852, 0xE434);
4827 r8168_mac_ocp_write(tp, 0xF854, 0xD3C0);
4828 r8168_mac_ocp_write(tp, 0xF856, 0x49D9);
4829 r8168_mac_ocp_write(tp, 0xF858, 0xF01F);
4830 r8168_mac_ocp_write(tp, 0xF85A, 0xC526);
4831 r8168_mac_ocp_write(tp, 0xF85C, 0x64A5);
4832 r8168_mac_ocp_write(tp, 0xF85E, 0x1400);
4833 r8168_mac_ocp_write(tp, 0xF860, 0xF007);
4834 r8168_mac_ocp_write(tp, 0xF862, 0x0C01);
4835 r8168_mac_ocp_write(tp, 0xF864, 0x8CA5);
4836 r8168_mac_ocp_write(tp, 0xF866, 0x1C15);
4837 r8168_mac_ocp_write(tp, 0xF868, 0xC51B);
4838 r8168_mac_ocp_write(tp, 0xF86A, 0x9CA0);
4839 r8168_mac_ocp_write(tp, 0xF86C, 0xE013);
4840 r8168_mac_ocp_write(tp, 0xF86E, 0xC519);
4841 r8168_mac_ocp_write(tp, 0xF870, 0x74A0);
4842 r8168_mac_ocp_write(tp, 0xF872, 0x48C4);
4843 r8168_mac_ocp_write(tp, 0xF874, 0x8CA0);
4844 r8168_mac_ocp_write(tp, 0xF876, 0xC516);
4845 r8168_mac_ocp_write(tp, 0xF878, 0x74A4);
4846 r8168_mac_ocp_write(tp, 0xF87A, 0x48C8);
4847 r8168_mac_ocp_write(tp, 0xF87C, 0x48CA);
4848 r8168_mac_ocp_write(tp, 0xF87E, 0x9CA4);
4849 r8168_mac_ocp_write(tp, 0xF880, 0xC512);
4850 r8168_mac_ocp_write(tp, 0xF882, 0x1B00);
4851 r8168_mac_ocp_write(tp, 0xF884, 0x9BA0);
4852 r8168_mac_ocp_write(tp, 0xF886, 0x1B1C);
4853 r8168_mac_ocp_write(tp, 0xF888, 0x483F);
4854 r8168_mac_ocp_write(tp, 0xF88A, 0x9BA2);
4855 r8168_mac_ocp_write(tp, 0xF88C, 0x1B04);
4856 r8168_mac_ocp_write(tp, 0xF88E, 0xC508);
4857 r8168_mac_ocp_write(tp, 0xF890, 0x9BA0);
4858 r8168_mac_ocp_write(tp, 0xF892, 0xC505);
4859 r8168_mac_ocp_write(tp, 0xF894, 0xBD00);
4860 r8168_mac_ocp_write(tp, 0xF896, 0xC502);
4861 r8168_mac_ocp_write(tp, 0xF898, 0xBD00);
4862 r8168_mac_ocp_write(tp, 0xF89A, 0x0300);
4863 r8168_mac_ocp_write(tp, 0xF89C, 0x051E);
4864 r8168_mac_ocp_write(tp, 0xF89E, 0xE434);
4865 r8168_mac_ocp_write(tp, 0xF8A0, 0xE018);
4866 r8168_mac_ocp_write(tp, 0xF8A2, 0xE092);
4867 r8168_mac_ocp_write(tp, 0xF8A4, 0xDE20);
4868 r8168_mac_ocp_write(tp, 0xF8A6, 0xD3C0);
4869 r8168_mac_ocp_write(tp, 0xF8A8, 0xC50F);
4870 r8168_mac_ocp_write(tp, 0xF8AA, 0x76A4);
4871 r8168_mac_ocp_write(tp, 0xF8AC, 0x49E3);
4872 r8168_mac_ocp_write(tp, 0xF8AE, 0xF007);
4873 r8168_mac_ocp_write(tp, 0xF8B0, 0x49C0);
4874 r8168_mac_ocp_write(tp, 0xF8B2, 0xF103);
4875 r8168_mac_ocp_write(tp, 0xF8B4, 0xC607);
4876 r8168_mac_ocp_write(tp, 0xF8B6, 0xBE00);
4877 r8168_mac_ocp_write(tp, 0xF8B8, 0xC606);
4878 r8168_mac_ocp_write(tp, 0xF8BA, 0xBE00);
4879 r8168_mac_ocp_write(tp, 0xF8BC, 0xC602);
4880 r8168_mac_ocp_write(tp, 0xF8BE, 0xBE00);
4881 r8168_mac_ocp_write(tp, 0xF8C0, 0x0C4C);
4882 r8168_mac_ocp_write(tp, 0xF8C2, 0x0C28);
4883 r8168_mac_ocp_write(tp, 0xF8C4, 0x0C2C);
4884 r8168_mac_ocp_write(tp, 0xF8C6, 0xDC00);
4885 r8168_mac_ocp_write(tp, 0xF8C8, 0xC707);
4886 r8168_mac_ocp_write(tp, 0xF8CA, 0x1D00);
4887 r8168_mac_ocp_write(tp, 0xF8CC, 0x8DE2);
4888 r8168_mac_ocp_write(tp, 0xF8CE, 0x48C1);
4889 r8168_mac_ocp_write(tp, 0xF8D0, 0xC502);
4890 r8168_mac_ocp_write(tp, 0xF8D2, 0xBD00);
4891 r8168_mac_ocp_write(tp, 0xF8D4, 0x00AA);
4892 r8168_mac_ocp_write(tp, 0xF8D6, 0xE0C0);
4893 r8168_mac_ocp_write(tp, 0xF8D8, 0xC502);
4894 r8168_mac_ocp_write(tp, 0xF8DA, 0xBD00);
4895 r8168_mac_ocp_write(tp, 0xF8DC, 0x0132);
4896
4897 r8168_mac_ocp_write(tp, 0xFC26, 0x8000);
4898
4899 r8168_mac_ocp_write(tp, 0xFC2A, 0x0743);
4900 r8168_mac_ocp_write(tp, 0xFC2C, 0x0801);
4901 r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9);
4902 r8168_mac_ocp_write(tp, 0xFC30, 0x02FD);
4903 r8168_mac_ocp_write(tp, 0xFC32, 0x0C25);
4904 r8168_mac_ocp_write(tp, 0xFC34, 0x00A9);
4905 r8168_mac_ocp_write(tp, 0xFC36, 0x012D);
4906
a99790bf 4907 rtl_hw_aspm_clkreq_enable(tp, true);
45dd95c4 4908}
4909
6e1d0b89
CHL		 4910static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
4911{
6e1d0b89
CHL		 4912 static const struct ephy_info e_info_8168h_1[] = {
4913 { 0x1e, 0x0800, 0x0001 },
4914 { 0x1d, 0x0000, 0x0800 },
4915 { 0x05, 0xffff, 0x2089 },
4916 { 0x06, 0xffff, 0x5881 },
a7a92cf8 4917 { 0x04, 0xffff, 0x854a },
6e1d0b89
CHL		 4918 { 0x01, 0xffff, 0x068b }
4919 };
ef712ede 4920 int rg_saw_cnt;
6e1d0b89
CHL		 4921
4922 /* disable aspm and clock request before access ephy */
a99790bf 4923 rtl_hw_aspm_clkreq_enable(tp, false);
1791ad50 4924 rtl_ephy_init(tp, e_info_8168h_1);
6e1d0b89 4925
6b1bd242 4926 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
0ebacd12 4927 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
6e1d0b89 4928
f37658da 4929 rtl_set_def_aspm_entry_latency(tp);
6e1d0b89 4930
4e7e4621 4931 rtl_reset_packet_filter(tp);
6e1d0b89 4932
e719b3ea 4933 rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_1111, BIT(4));
6e1d0b89 4934
e719b3ea 4935 rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f00);
6e1d0b89 4936
724c6fd0 4937 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
6e1d0b89 4938
1ef7286e 4939 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
6e1d0b89 4940
724c6fd0
HK		 4941 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4942 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
6e1d0b89 4943
df6f1856
HK		 4944 rtl8168_config_eee_mac(tp);
4945
1ef7286e
AS		 4946 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
4947 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
6e1d0b89 4948
1ef7286e 4949 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
6e1d0b89 4950
e719b3ea 4951 rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12));
6e1d0b89 4952
c259b7f4 4953 rtl_pcie_state_l2l3_disable(tp);
6e1d0b89
CHL		 4954
4955 rtl_writephy(tp, 0x1f, 0x0c42);
58493333 4956 rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff);
6e1d0b89
CHL		 4957 rtl_writephy(tp, 0x1f, 0x0000);
4958 if (rg_saw_cnt > 0) {
4959 u16 sw_cnt_1ms_ini;
4960
4961 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
4962 sw_cnt_1ms_ini &= 0x0fff;
ef712ede 4963 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini);
6e1d0b89
CHL		 4964 }
4965
ef712ede
HK		 4966 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070);
4967 r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008);
4968 r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f);
4969 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f);
6e1d0b89
CHL		 4970
4971 r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
4972 r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
4973 r8168_mac_ocp_write(tp, 0xc094, 0x0000);
4974 r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
a99790bf
KHF		 4975
4976 rtl_hw_aspm_clkreq_enable(tp, true);
6e1d0b89
CHL		 4977}
4978
935e2218
CHL		 4979static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
4980{
003609da
CHL		 4981 rtl8168ep_stop_cmac(tp);
4982
6b1bd242 4983 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
0ebacd12 4984 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
935e2218 4985
f37658da 4986 rtl_set_def_aspm_entry_latency(tp);
935e2218 4987
4e7e4621 4988 rtl_reset_packet_filter(tp);
935e2218 4989
e719b3ea 4990 rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f80);
935e2218 4991
724c6fd0 4992 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
935e2218 4993
1ef7286e 4994 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
935e2218 4995
724c6fd0
HK		 4996 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4997 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
935e2218 4998
df6f1856
HK		 4999 rtl8168_config_eee_mac(tp);
5000
724c6fd0 5001 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06);
935e2218 5002
1ef7286e 5003 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
935e2218 5004
c259b7f4 5005 rtl_pcie_state_l2l3_disable(tp);
935e2218
CHL		 5006}
5007
5008static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
5009{
935e2218
CHL		 5010 static const struct ephy_info e_info_8168ep_1[] = {
5011 { 0x00, 0xffff, 0x10ab },
5012 { 0x06, 0xffff, 0xf030 },
5013 { 0x08, 0xffff, 0x2006 },
5014 { 0x0d, 0xffff, 0x1666 },
5015 { 0x0c, 0x3ff0, 0x0000 }
5016 };
5017
5018 /* disable aspm and clock request before access ephy */
a99790bf 5019 rtl_hw_aspm_clkreq_enable(tp, false);
1791ad50 5020 rtl_ephy_init(tp, e_info_8168ep_1);
935e2218
CHL		 5021
5022 rtl_hw_start_8168ep(tp);
a99790bf
KHF		 5023
5024 rtl_hw_aspm_clkreq_enable(tp, true);
935e2218
CHL		 5025}
5026
5027static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
5028{
935e2218
CHL		 5029 static const struct ephy_info e_info_8168ep_2[] = {
5030 { 0x00, 0xffff, 0x10a3 },
5031 { 0x19, 0xffff, 0xfc00 },
5032 { 0x1e, 0xffff, 0x20ea }
5033 };
5034
5035 /* disable aspm and clock request before access ephy */
a99790bf 5036 rtl_hw_aspm_clkreq_enable(tp, false);
1791ad50 5037 rtl_ephy_init(tp, e_info_8168ep_2);
935e2218
CHL		 5038
5039 rtl_hw_start_8168ep(tp);
5040
1ef7286e
AS		 5041 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5042 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
a99790bf
KHF		 5043
5044 rtl_hw_aspm_clkreq_enable(tp, true);
935e2218
CHL		 5045}
5046
5047static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
5048{
935e2218 5049 static const struct ephy_info e_info_8168ep_3[] = {
a7a92cf8
HK		 5050 { 0x00, 0x0000, 0x0080 },
5051 { 0x0d, 0x0100, 0x0200 },
5052 { 0x19, 0x8021, 0x0000 },
5053 { 0x1e, 0x0000, 0x2000 },
935e2218
CHL		 5054 };
5055
5056 /* disable aspm and clock request before access ephy */
a99790bf 5057 rtl_hw_aspm_clkreq_enable(tp, false);
1791ad50 5058 rtl_ephy_init(tp, e_info_8168ep_3);
935e2218
CHL		 5059
5060 rtl_hw_start_8168ep(tp);
5061
1ef7286e
AS		 5062 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5063 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
935e2218 5064
ef712ede
HK		 5065 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271);
5066 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000);
5067 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080);
a99790bf
KHF		 5068
5069 rtl_hw_aspm_clkreq_enable(tp, true);
935e2218
CHL		 5070}
5071
2e13d773
HK		 5072static void rtl_hw_start_8117(struct rtl8169_private *tp)
5073{
5074 static const struct ephy_info e_info_8117[] = {
5075 { 0x19, 0x0040, 0x1100 },
5076 { 0x59, 0x0040, 0x1100 },
5077 };
5078 int rg_saw_cnt;
5079
5080 rtl8168ep_stop_cmac(tp);
5081
5082 /* disable aspm and clock request before access ephy */
5083 rtl_hw_aspm_clkreq_enable(tp, false);
5084 rtl_ephy_init(tp, e_info_8117);
5085
5086 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
5087 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
5088
5089 rtl_set_def_aspm_entry_latency(tp);
5090
5091 rtl_reset_packet_filter(tp);
5092
5093 rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f90);
5094
5095 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
5096
5097 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5098
5099 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
5100 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
5101
5102 rtl8168_config_eee_mac(tp);
5103
5104 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5105 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5106
5107 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
5108
5109 rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12));
5110
5111 rtl_pcie_state_l2l3_disable(tp);
5112
5113 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff;
5114 if (rg_saw_cnt > 0) {
5115 u16 sw_cnt_1ms_ini;
5116
5117 sw_cnt_1ms_ini = (16000000 / rg_saw_cnt) & 0x0fff;
5118 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini);
5119 }
5120
5121 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070);
5122 r8168_mac_ocp_write(tp, 0xea80, 0x0003);
5123 r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009);
5124 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f);
5125
5126 r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
5127 r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
5128 r8168_mac_ocp_write(tp, 0xc094, 0x0000);
5129 r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
5130
6e526a7f
HK		 5131 /* firmware is for MAC only */
5132 rtl_apply_firmware(tp);
5133
2e13d773
HK		 5134 rtl_hw_aspm_clkreq_enable(tp, true);
5135}
5136
beb1fe18 5137static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
2857ffb7 5138{
350f7596 5139 static const struct ephy_info e_info_8102e_1[] = {
2857ffb7
FR		 5140 { 0x01, 0, 0x6e65 },
5141 { 0x02, 0, 0x091f },
5142 { 0x03, 0, 0xc2f9 },
5143 { 0x06, 0, 0xafb5 },
5144 { 0x07, 0, 0x0e00 },
5145 { 0x19, 0, 0xec80 },
5146 { 0x01, 0, 0x2e65 },
5147 { 0x01, 0, 0x6e65 }
5148 };
5149 u8 cfg1;
5150
f37658da 5151 rtl_set_def_aspm_entry_latency(tp);
2857ffb7 5152
1ef7286e 5153 RTL_W8(tp, DBG_REG, FIX_NAK_1);
2857ffb7 5154
1ef7286e 5155 RTL_W8(tp, Config1,
2857ffb7 5156 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
1ef7286e 5157 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2857ffb7 5158
1ef7286e 5159 cfg1 = RTL_R8(tp, Config1);
2857ffb7 5160 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
1ef7286e 5161 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
2857ffb7 5162
1791ad50 5163 rtl_ephy_init(tp, e_info_8102e_1);
2857ffb7
FR		 5164}
5165
beb1fe18 5166static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
2857ffb7 5167{
f37658da 5168 rtl_set_def_aspm_entry_latency(tp);
2857ffb7 5169
1ef7286e
AS		 5170 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
5171 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2857ffb7
FR		 5172}
5173
beb1fe18 5174static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
2857ffb7 5175{
beb1fe18 5176 rtl_hw_start_8102e_2(tp);
2857ffb7 5177
fdf6fc06 5178 rtl_ephy_write(tp, 0x03, 0xc2f9);
2857ffb7
FR		 5179}
5180
beb1fe18 5181static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5a5e4443
HW		 5182{
5183 static const struct ephy_info e_info_8105e_1[] = {
5184 { 0x07, 0, 0x4000 },
5185 { 0x19, 0, 0x0200 },
5186 { 0x19, 0, 0x0020 },
5187 { 0x1e, 0, 0x2000 },
5188 { 0x03, 0, 0x0001 },
5189 { 0x19, 0, 0x0100 },
5190 { 0x19, 0, 0x0004 },
5191 { 0x0a, 0, 0x0020 }
5192 };
5193
cecb5fd7 5194 /* Force LAN exit from ASPM if Rx/Tx are not idle */
1ef7286e 5195 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5a5e4443 5196
cecb5fd7 5197 /* Disable Early Tally Counter */
1ef7286e 5198 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
5a5e4443 5199
1ef7286e
AS		 5200 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5201 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5a5e4443 5202
1791ad50 5203 rtl_ephy_init(tp, e_info_8105e_1);
b51ecea8 5204
c259b7f4 5205 rtl_pcie_state_l2l3_disable(tp);
5a5e4443
HW		 5206}
5207
beb1fe18 5208static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5a5e4443 5209{
beb1fe18 5210 rtl_hw_start_8105e_1(tp);
fdf6fc06 5211 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5a5e4443
HW		 5212}
5213
7e18dca1
HW		 5214static void rtl_hw_start_8402(struct rtl8169_private *tp)
5215{
7e18dca1
HW		 5216 static const struct ephy_info e_info_8402[] = {
5217 { 0x19, 0xffff, 0xff64 },
5218 { 0x1e, 0, 0x4000 }
5219 };
5220
f37658da 5221 rtl_set_def_aspm_entry_latency(tp);
7e18dca1
HW		 5222
5223 /* Force LAN exit from ASPM if Rx/Tx are not idle */
1ef7286e 5224 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
7e18dca1 5225
1ef7286e 5226 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
7e18dca1 5227
1791ad50 5228 rtl_ephy_init(tp, e_info_8402);
7e18dca1 5229
6b1bd242 5230 rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06);
4e7e4621 5231 rtl_reset_packet_filter(tp);
724c6fd0
HK		 5232 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
5233 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
5234 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00);
b51ecea8 5235
c259b7f4 5236 rtl_pcie_state_l2l3_disable(tp);
7e18dca1
HW		 5237}
5238
5598bfe5
HW		 5239static void rtl_hw_start_8106(struct rtl8169_private *tp)
5240{
0866cd15
KHF		 5241 rtl_hw_aspm_clkreq_enable(tp, false);
5242
5598bfe5 5243 /* Force LAN exit from ASPM if Rx/Tx are not idle */
1ef7286e 5244 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5598bfe5 5245
1ef7286e
AS		 5246 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
5247 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5248 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
b51ecea8 5249
c259b7f4 5250 rtl_pcie_state_l2l3_disable(tp);
0866cd15 5251 rtl_hw_aspm_clkreq_enable(tp, true);
5598bfe5
HW		 5252}
5253
f1bce4ad
HK		 5254DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond)
5255{
5256 return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13);
5257}
5258
5259static void rtl_hw_start_8125_common(struct rtl8169_private *tp)
5260{
5261 rtl_pcie_state_l2l3_disable(tp);
5262
5263 RTL_W16(tp, 0x382, 0x221b);
5264 RTL_W8(tp, 0x4500, 0);
5265 RTL_W16(tp, 0x4800, 0);
5266
5267 /* disable UPS */
5268 r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000);
5269
5270 RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10);
5271
5272 r8168_mac_ocp_write(tp, 0xc140, 0xffff);
5273 r8168_mac_ocp_write(tp, 0xc142, 0xffff);
5274
5275 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9);
5276 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000);
5277 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080);
5278
5279 /* disable new tx descriptor format */
5280 r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000);
5281
5282 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400);
5283 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020);
5284 r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c);
5285 r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033);
5286 r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040);
5287 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030);
5288 r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000);
5289 r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403);
5290 r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0067);
5291 r8168_mac_ocp_modify(tp, 0xc0ac, 0x0080, 0x1f00);
5292 r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f);
5293 r8168_mac_ocp_modify(tp, 0xe84c, 0x0000, 0x00c0);
5294 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000);
5295 r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001);
5296 udelay(1);
5297 r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000);
5298 RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030);
5299
5300 r8168_mac_ocp_write(tp, 0xe098, 0xc302);
5301
5302 rtl_udelay_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10);
5303
b3a42e3a
HK		 5304 rtl8125_config_eee_mac(tp);
5305
f1bce4ad
HK		 5306 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5307 udelay(10);
5308}
5309
5310static void rtl_hw_start_8125_1(struct rtl8169_private *tp)
5311{
5312 static const struct ephy_info e_info_8125_1[] = {
5313 { 0x01, 0xffff, 0xa812 },
5314 { 0x09, 0xffff, 0x520c },
5315 { 0x04, 0xffff, 0xd000 },
5316 { 0x0d, 0xffff, 0xf702 },
5317 { 0x0a, 0xffff, 0x8653 },
5318 { 0x06, 0xffff, 0x001e },
5319 { 0x08, 0xffff, 0x3595 },
5320 { 0x20, 0xffff, 0x9455 },
5321 { 0x21, 0xffff, 0x99ff },
5322 { 0x02, 0xffff, 0x6046 },
5323 { 0x29, 0xffff, 0xfe00 },
5324 { 0x23, 0xffff, 0xab62 },
5325
5326 { 0x41, 0xffff, 0xa80c },
5327 { 0x49, 0xffff, 0x520c },
5328 { 0x44, 0xffff, 0xd000 },
5329 { 0x4d, 0xffff, 0xf702 },
5330 { 0x4a, 0xffff, 0x8653 },
5331 { 0x46, 0xffff, 0x001e },
5332 { 0x48, 0xffff, 0x3595 },
5333 { 0x60, 0xffff, 0x9455 },
5334 { 0x61, 0xffff, 0x99ff },
5335 { 0x42, 0xffff, 0x6046 },
5336 { 0x69, 0xffff, 0xfe00 },
5337 { 0x63, 0xffff, 0xab62 },
5338 };
5339
5340 rtl_set_def_aspm_entry_latency(tp);
5341
5342 /* disable aspm and clock request before access ephy */
5343 rtl_hw_aspm_clkreq_enable(tp, false);
5344 rtl_ephy_init(tp, e_info_8125_1);
5345
5346 rtl_hw_start_8125_common(tp);
5347}
5348
5349static void rtl_hw_start_8125_2(struct rtl8169_private *tp)
5350{
5351 static const struct ephy_info e_info_8125_2[] = {
5352 { 0x04, 0xffff, 0xd000 },
5353 { 0x0a, 0xffff, 0x8653 },
5354 { 0x23, 0xffff, 0xab66 },
5355 { 0x20, 0xffff, 0x9455 },
5356 { 0x21, 0xffff, 0x99ff },
5357 { 0x29, 0xffff, 0xfe04 },
5358
5359 { 0x44, 0xffff, 0xd000 },
5360 { 0x4a, 0xffff, 0x8653 },
5361 { 0x63, 0xffff, 0xab66 },
5362 { 0x60, 0xffff, 0x9455 },
5363 { 0x61, 0xffff, 0x99ff },
5364 { 0x69, 0xffff, 0xfe04 },
5365 };
5366
5367 rtl_set_def_aspm_entry_latency(tp);
5368
5369 /* disable aspm and clock request before access ephy */
5370 rtl_hw_aspm_clkreq_enable(tp, false);
5371 rtl_ephy_init(tp, e_info_8125_2);
5372
5373 rtl_hw_start_8125_common(tp);
5374}
5375
8344ffff
HK		 5376static void rtl_hw_config(struct rtl8169_private *tp)
5377{
5378 static const rtl_generic_fct hw_configs[] = {
5379 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1,
5380 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3,
5381 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2,
5382 [RTL_GIGA_MAC_VER_10] = NULL,
5383 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168bb,
5384 [RTL_GIGA_MAC_VER_12] = rtl_hw_start_8168bef,
5385 [RTL_GIGA_MAC_VER_13] = NULL,
5386 [RTL_GIGA_MAC_VER_14] = NULL,
5387 [RTL_GIGA_MAC_VER_15] = NULL,
5388 [RTL_GIGA_MAC_VER_16] = NULL,
5389 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168bef,
5390 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1,
5391 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1,
5392 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2,
5393 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_3,
5394 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4,
5395 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2,
5396 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3,
5397 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d,
5398 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d,
5399 [RTL_GIGA_MAC_VER_27] = rtl_hw_start_8168d,
5400 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4,
5401 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1,
5402 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2,
5403 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168dp,
5404 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1,
5405 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1,
5406 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2,
5407 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1,
5408 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1,
5409 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402,
5410 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411,
5411 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106,
5412 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1,
5413 [RTL_GIGA_MAC_VER_41] = rtl_hw_start_8168g_1,
5414 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2,
5415 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2,
5416 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2,
5417 [RTL_GIGA_MAC_VER_45] = rtl_hw_start_8168h_1,
5418 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1,
5419 [RTL_GIGA_MAC_VER_47] = rtl_hw_start_8168h_1,
5420 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1,
5421 [RTL_GIGA_MAC_VER_49] = rtl_hw_start_8168ep_1,
5422 [RTL_GIGA_MAC_VER_50] = rtl_hw_start_8168ep_2,
5423 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3,
2e13d773 5424 [RTL_GIGA_MAC_VER_52] = rtl_hw_start_8117,
f1bce4ad
HK		 5425 [RTL_GIGA_MAC_VER_60] = rtl_hw_start_8125_1,
5426 [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125_2,
8344ffff
HK		 5427 };
5428
5429 if (hw_configs[tp->mac_version])
5430 hw_configs[tp->mac_version](tp);
5431}
5432
f1bce4ad
HK		 5433static void rtl_hw_start_8125(struct rtl8169_private *tp)
5434{
5435 int i;
5436
5437 /* disable interrupt coalescing */
5438 for (i = 0xa00; i < 0xb00; i += 4)
5439 RTL_W32(tp, i, 0);
5440
5441 rtl_hw_config(tp);
5442}
5443
8344ffff 5444static void rtl_hw_start_8168(struct rtl8169_private *tp)
07ce4064 5445{
cecb5fd7 5446 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
7d7903b2 5447 tp->mac_version == RTL_GIGA_MAC_VER_16)
61cb532d 5448 pcie_capability_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
8200bc72 5449 PCI_EXP_DEVCTL_NOSNOOP_EN);
cdf1a608 5450
272b2265
HK		 5451 if (rtl_is_8168evl_up(tp))
5452 RTL_W8(tp, MaxTxPacketSize, EarlySize);
5453 else
5454 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
1a964649 5455
8344ffff 5456 rtl_hw_config(tp);
bcf2b868
HK		 5457
5458 /* disable interrupt coalescing */
5459 RTL_W16(tp, IntrMitigate, 0x0000);
1da177e4
LT		 5460}
5461
6c19156e
HK		 5462static void rtl_hw_start_8169(struct rtl8169_private *tp)
5463{
5464 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
5465 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
5466
5467 RTL_W8(tp, EarlyTxThres, NoEarlyTx);
5468
5469 tp->cp_cmd |= PCIMulRW;
5470
5471 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5472 tp->mac_version == RTL_GIGA_MAC_VER_03) {
5473 netif_dbg(tp, drv, tp->dev,
5474 "Set MAC Reg C+CR Offset 0xe0. Bit 3 and Bit 14 MUST be 1\n");
5475 tp->cp_cmd |= (1 << 14);
5476 }
5477
5478 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5479
5480 rtl8169_set_magic_reg(tp, tp->mac_version);
5481
5482 RTL_W32(tp, RxMissed, 0);
bcf2b868
HK		 5483
5484 /* disable interrupt coalescing */
5485 RTL_W16(tp, IntrMitigate, 0x0000);
6c19156e
HK		 5486}
5487
5488static void rtl_hw_start(struct rtl8169_private *tp)
5489{
5490 rtl_unlock_config_regs(tp);
5491
5492 tp->cp_cmd &= CPCMD_MASK;
5493 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5494
5495 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
5496 rtl_hw_start_8169(tp);
f1bce4ad
HK		 5497 else if (rtl_is_8125(tp))
5498 rtl_hw_start_8125(tp);
6c19156e
HK		 5499 else
5500 rtl_hw_start_8168(tp);
5501
5502 rtl_set_rx_max_size(tp);
5503 rtl_set_rx_tx_desc_registers(tp);
5504 rtl_lock_config_regs(tp);
5505
4ebcb113
HK		 5506 rtl_jumbo_config(tp, tp->dev->mtu);
5507
6c19156e 5508 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
7366016d 5509 RTL_R16(tp, CPlusCmd);
6c19156e
HK		 5510 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
5511 rtl_init_rxcfg(tp);
5512 rtl_set_tx_config_registers(tp);
6c19156e 5513 rtl_set_rx_mode(tp->dev);
6c19156e
HK		 5514 rtl_irq_enable(tp);
5515}
5516
1da177e4
LT		 5517static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5518{
d58d46b5
FR		 5519 struct rtl8169_private *tp = netdev_priv(dev);
5520
4ebcb113 5521 rtl_jumbo_config(tp, new_mtu);
d58d46b5 5522
1da177e4 5523 dev->mtu = new_mtu;
350fb32a
MM		 5524 netdev_update_features(dev);
5525
5f1a1e18
HK		 5526 /* Reportedly at least Asus X453MA truncates packets otherwise */
5527 if (tp->mac_version == RTL_GIGA_MAC_VER_37)
5528 rtl_init_rxcfg(tp);
5529
323bb685 5530 return 0;
1da177e4
LT		 5531}
5532
5533static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5534{
95e0918d 5535 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
1da177e4
LT		 5536 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5537}
5538
1d0254dd 5539static inline void rtl8169_mark_to_asic(struct RxDesc *desc)
1da177e4
LT		 5540{
5541 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5542
a0750138
AD		 5543 /* Force memory writes to complete before releasing descriptor */
5544 dma_wmb();
5545
1d0254dd 5546 desc->opts1 = cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE);
1da177e4
LT		 5547}
5548
32879f00
HK		 5549static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5550 struct RxDesc *desc)
1da177e4 5551{
1e1205b7 5552 struct device *d = tp_to_dev(tp);
d3b404c2 5553 int node = dev_to_node(d);
32879f00
HK		 5554 dma_addr_t mapping;
5555 struct page *data;
1da177e4 5556
32879f00 5557 data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE));
6f0333b8
ED		 5558 if (!data)
5559 return NULL;
e9f63f30 5560
32879f00 5561 mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
d827d86b
SG		 5562 if (unlikely(dma_mapping_error(d, mapping))) {
5563 if (net_ratelimit())
5564 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
32879f00
HK		 5565 __free_pages(data, get_order(R8169_RX_BUF_SIZE));
5566 return NULL;
d827d86b 5567 }
1da177e4 5568
d731af78
HK		 5569 desc->addr = cpu_to_le64(mapping);
5570 rtl8169_mark_to_asic(desc);
3eafe507 5571
32879f00 5572 return data;
1da177e4
LT		 5573}
5574
5575static void rtl8169_rx_clear(struct rtl8169_private *tp)
5576{
07d3f51f 5577 unsigned int i;
1da177e4 5578
eb2e7f09
HK		 5579 for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) {
5580 dma_unmap_page(tp_to_dev(tp),
5581 le64_to_cpu(tp->RxDescArray[i].addr),
5582 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
5583 __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE));
5584 tp->Rx_databuff[i] = NULL;
5585 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
1da177e4
LT		 5586 }
5587}
5588
0ecbe1ca 5589static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
1da177e4 5590{
0ecbe1ca
SG		 5591 desc->opts1 |= cpu_to_le32(RingEnd);
5592}
5b0384f4 5593
0ecbe1ca
SG		 5594static int rtl8169_rx_fill(struct rtl8169_private *tp)
5595{
5596 unsigned int i;
1da177e4 5597
0ecbe1ca 5598 for (i = 0; i < NUM_RX_DESC; i++) {
32879f00 5599 struct page *data;
4ae47c2d 5600
0ecbe1ca 5601 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
6f0333b8
ED		 5602 if (!data) {
5603 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
0ecbe1ca 5604 goto err_out;
6f0333b8
ED		 5605 }
5606 tp->Rx_databuff[i] = data;
1da177e4 5607 }
1da177e4 5608
0ecbe1ca
SG		 5609 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5610 return 0;
5611
5612err_out:
5613 rtl8169_rx_clear(tp);
5614 return -ENOMEM;
1da177e4
LT		 5615}
5616
b1127e64 5617static int rtl8169_init_ring(struct rtl8169_private *tp)
1da177e4 5618{
1da177e4
LT		 5619 rtl8169_init_ring_indexes(tp);
5620
b1127e64
HK		 5621 memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
5622 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
1da177e4 5623
0ecbe1ca 5624 return rtl8169_rx_fill(tp);
1da177e4
LT		 5625}
5626
48addcc9 5627static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
1da177e4
LT		 5628 struct TxDesc *desc)
5629{
5630 unsigned int len = tx_skb->len;
5631
48addcc9
SG		 5632 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5633
1da177e4
LT		 5634 desc->opts1 = 0x00;
5635 desc->opts2 = 0x00;
5636 desc->addr = 0x00;
5637 tx_skb->len = 0;
5638}
5639
3eafe507
SG		 5640static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5641 unsigned int n)
1da177e4
LT		 5642{
5643 unsigned int i;
5644
3eafe507
SG		 5645 for (i = 0; i < n; i++) {
5646 unsigned int entry = (start + i) % NUM_TX_DESC;
1da177e4
LT		 5647 struct ring_info *tx_skb = tp->tx_skb + entry;
5648 unsigned int len = tx_skb->len;
5649
5650 if (len) {
5651 struct sk_buff *skb = tx_skb->skb;
5652
1e1205b7 5653 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
1da177e4
LT		 5654 tp->TxDescArray + entry);
5655 if (skb) {
7a4b813c 5656 dev_consume_skb_any(skb);
1da177e4
LT		 5657 tx_skb->skb = NULL;
5658 }
1da177e4
LT		 5659 }
5660 }
3eafe507
SG		 5661}
5662
5663static void rtl8169_tx_clear(struct rtl8169_private *tp)
5664{
5665 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
1da177e4 5666 tp->cur_tx = tp->dirty_tx = 0;
d92060bc 5667 netdev_reset_queue(tp->dev);
1da177e4
LT		 5668}
5669
4422bcd4 5670static void rtl_reset_work(struct rtl8169_private *tp)
1da177e4 5671{
c4028958 5672 struct net_device *dev = tp->dev;
56de414c 5673 int i;
1da177e4 5674
da78dbff
FR		 5675 napi_disable(&tp->napi);
5676 netif_stop_queue(dev);
16f11500 5677 synchronize_rcu();
1da177e4 5678
c7c2c39b 5679 rtl8169_hw_reset(tp);
5680
56de414c 5681 for (i = 0; i < NUM_RX_DESC; i++)
1d0254dd 5682 rtl8169_mark_to_asic(tp->RxDescArray + i);
56de414c 5683
1da177e4 5684 rtl8169_tx_clear(tp);
c7c2c39b 5685 rtl8169_init_ring_indexes(tp);
1da177e4 5686
da78dbff 5687 napi_enable(&tp->napi);
61cb532d 5688 rtl_hw_start(tp);
56de414c 5689 netif_wake_queue(dev);
1da177e4
LT		 5690}
5691
5692static void rtl8169_tx_timeout(struct net_device *dev)
5693{
da78dbff
FR		 5694 struct rtl8169_private *tp = netdev_priv(dev);
5695
5696 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
1da177e4
LT		 5697}
5698
734c1409
HK		 5699static __le32 rtl8169_get_txd_opts1(u32 opts0, u32 len, unsigned int entry)
5700{
5701 u32 status = opts0 | len;
5702
5703 if (entry == NUM_TX_DESC - 1)
5704 status |= RingEnd;
5705
5706 return cpu_to_le32(status);
5707}
5708
1da177e4 5709static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2b7b4318 5710 u32 *opts)
1da177e4
LT		 5711{
5712 struct skb_shared_info *info = skb_shinfo(skb);
5713 unsigned int cur_frag, entry;
6e1d0b89 5714 struct TxDesc *uninitialized_var(txd);
1e1205b7 5715 struct device *d = tp_to_dev(tp);
1da177e4
LT		 5716
5717 entry = tp->cur_tx;
5718 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
9e903e08 5719 const skb_frag_t *frag = info->frags + cur_frag;
1da177e4 5720 dma_addr_t mapping;
734c1409 5721 u32 len;
1da177e4
LT		 5722 void *addr;
5723
5724 entry = (entry + 1) % NUM_TX_DESC;
5725
5726 txd = tp->TxDescArray + entry;
9e903e08 5727 len = skb_frag_size(frag);
929f6189 5728 addr = skb_frag_address(frag);
48addcc9 5729 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
d827d86b
SG		 5730 if (unlikely(dma_mapping_error(d, mapping))) {
5731 if (net_ratelimit())
5732 netif_err(tp, drv, tp->dev,
5733 "Failed to map TX fragments DMA!\n");
3eafe507 5734 goto err_out;
d827d86b 5735 }
1da177e4 5736
734c1409 5737 txd->opts1 = rtl8169_get_txd_opts1(opts[0], len, entry);
2b7b4318 5738 txd->opts2 = cpu_to_le32(opts[1]);
1da177e4
LT		 5739 txd->addr = cpu_to_le64(mapping);
5740
5741 tp->tx_skb[entry].len = len;
5742 }
5743
5744 if (cur_frag) {
5745 tp->tx_skb[entry].skb = skb;
5746 txd->opts1 |= cpu_to_le32(LastFrag);
5747 }
5748
5749 return cur_frag;
3eafe507
SG		 5750
5751err_out:
5752 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5753 return -EIO;
1da177e4
LT		 5754}
5755
b423e9ae 5756static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
5757{
5758 return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
5759}
5760
e974604b 5761/* msdn_giant_send_check()
5762 * According to the document of microsoft, the TCP Pseudo Header excludes the
5763 * packet length for IPv6 TCP large packets.
5764 */
5765static int msdn_giant_send_check(struct sk_buff *skb)
5766{
5767 const struct ipv6hdr *ipv6h;
5768 struct tcphdr *th;
5769 int ret;
5770
5771 ret = skb_cow_head(skb, 0);
5772 if (ret)
5773 return ret;
5774
5775 ipv6h = ipv6_hdr(skb);
5776 th = tcp_hdr(skb);
5777
5778 th->check = 0;
5779 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
5780
5781 return ret;
5782}
5783
87945b6d 5784static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts)
1da177e4 5785{
350fb32a
MM		 5786 u32 mss = skb_shinfo(skb)->gso_size;
5787
2b7b4318
FR		 5788 if (mss) {
5789 opts[0] |= TD_LSO;
5888d3fc 5790 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
5791 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5792 const struct iphdr *ip = ip_hdr(skb);
5793
5794 if (ip->protocol == IPPROTO_TCP)
5795 opts[0] |= TD0_IP_CS | TD0_TCP_CS;
5796 else if (ip->protocol == IPPROTO_UDP)
5797 opts[0] |= TD0_IP_CS | TD0_UDP_CS;
5798 else
5799 WARN_ON_ONCE(1);
5800 }
5888d3fc 5801}
5802
5803static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
5804 struct sk_buff *skb, u32 *opts)
5805{
bdfa4ed6 5806 u32 transport_offset = (u32)skb_transport_offset(skb);
5888d3fc 5807 u32 mss = skb_shinfo(skb)->gso_size;
5808
5809 if (mss) {
4ff36466 5810 switch (vlan_get_protocol(skb)) {
e974604b 5811 case htons(ETH_P_IP):
5812 opts[0] |= TD1_GTSENV4;
5813 break;
5814
5815 case htons(ETH_P_IPV6):
5816 if (msdn_giant_send_check(skb))
5817 return false;
5818
5819 opts[0] |= TD1_GTSENV6;
5820 break;
5821
5822 default:
5823 WARN_ON_ONCE(1);
5824 break;
5825 }
5826
bdfa4ed6 5827 opts[0] |= transport_offset << GTTCPHO_SHIFT;
5888d3fc 5828 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
2b7b4318 5829 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
e974604b 5830 u8 ip_protocol;
1da177e4 5831
4ff36466 5832 switch (vlan_get_protocol(skb)) {
e974604b 5833 case htons(ETH_P_IP):
5834 opts[1] |= TD1_IPv4_CS;
5835 ip_protocol = ip_hdr(skb)->protocol;
5836 break;
5837
5838 case htons(ETH_P_IPV6):
5839 opts[1] |= TD1_IPv6_CS;
5840 ip_protocol = ipv6_hdr(skb)->nexthdr;
5841 break;
5842
5843 default:
5844 ip_protocol = IPPROTO_RAW;
5845 break;
5846 }
5847
5848 if (ip_protocol == IPPROTO_TCP)
5849 opts[1] |= TD1_TCP_CS;
5850 else if (ip_protocol == IPPROTO_UDP)
5851 opts[1] |= TD1_UDP_CS;
2b7b4318
FR		 5852 else
5853 WARN_ON_ONCE(1);
e974604b 5854
5855 opts[1] |= transport_offset << TCPHO_SHIFT;
b423e9ae 5856 } else {
5857 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
9215bee2
HK		 5858 /* eth_skb_pad would free the skb on error */
5859 return !__skb_put_padto(skb, ETH_ZLEN, false);
1da177e4 5860 }
5888d3fc 5861
b423e9ae 5862 return true;
1da177e4
LT		 5863}
5864
76085c9e
HK		 5865static bool rtl_tx_slots_avail(struct rtl8169_private *tp,
5866 unsigned int nr_frags)
5867{
5868 unsigned int slots_avail = tp->dirty_tx + NUM_TX_DESC - tp->cur_tx;
5869
5870 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
5871 return slots_avail > nr_frags;
5872}
5873
87945b6d
HK		 5874/* Versions RTL8102e and from RTL8168c onwards support csum_v2 */
5875static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp)
5876{
5877 switch (tp->mac_version) {
5878 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
5879 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
5880 return false;
5881 default:
5882 return true;
5883 }
5884}
5885
f1bce4ad
HK		 5886static void rtl8169_doorbell(struct rtl8169_private *tp)
5887{
5888 if (rtl_is_8125(tp))
5889 RTL_W16(tp, TxPoll_8125, BIT(0));
5890 else
5891 RTL_W8(tp, TxPoll, NPQ);
5892}
5893
61357325
SH		 5894static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5895 struct net_device *dev)
1da177e4
LT		 5896{
5897 struct rtl8169_private *tp = netdev_priv(dev);
3eafe507 5898 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
1da177e4 5899 struct TxDesc *txd = tp->TxDescArray + entry;
1e1205b7 5900 struct device *d = tp_to_dev(tp);
1da177e4 5901 dma_addr_t mapping;
734c1409 5902 u32 opts[2], len;
ef143585
HK		 5903 bool stop_queue;
5904 bool door_bell;
3eafe507 5905 int frags;
5b0384f4 5906
76085c9e 5907 if (unlikely(!rtl_tx_slots_avail(tp, skb_shinfo(skb)->nr_frags))) {
bf82c189 5908 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
3eafe507 5909 goto err_stop_0;
1da177e4
LT		 5910 }
5911
5912 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
3eafe507
SG		 5913 goto err_stop_0;
5914
355f948a 5915 opts[1] = rtl8169_tx_vlan_tag(skb);
b423e9ae 5916 opts[0] = DescOwn;
5917
87945b6d 5918 if (rtl_chip_supports_csum_v2(tp)) {
96ea772e
HK		 5919 if (!rtl8169_tso_csum_v2(tp, skb, opts))
5920 goto err_dma_0;
87945b6d
HK		 5921 } else {
5922 rtl8169_tso_csum_v1(skb, opts);
e974604b 5923 }
b423e9ae 5924
3eafe507 5925 len = skb_headlen(skb);
48addcc9 5926 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
d827d86b
SG		 5927 if (unlikely(dma_mapping_error(d, mapping))) {
5928 if (net_ratelimit())
5929 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
3eafe507 5930 goto err_dma_0;
d827d86b 5931 }
3eafe507
SG		 5932
5933 tp->tx_skb[entry].len = len;
5934 txd->addr = cpu_to_le64(mapping);
1da177e4 5935
2b7b4318 5936 frags = rtl8169_xmit_frags(tp, skb, opts);
3eafe507
SG		 5937 if (frags < 0)
5938 goto err_dma_1;
5939 else if (frags)
2b7b4318 5940 opts[0] |= FirstFrag;
3eafe507 5941 else {
2b7b4318 5942 opts[0] |= FirstFrag | LastFrag;
1da177e4
LT		 5943 tp->tx_skb[entry].skb = skb;
5944 }
5945
2b7b4318
FR		 5946 txd->opts2 = cpu_to_le32(opts[1]);
5947
5047fb5d
RC		 5948 skb_tx_timestamp(skb);
5949
a0750138
AD		 5950 /* Force memory writes to complete before releasing descriptor */
5951 dma_wmb();
1da177e4 5952
ef143585
HK		 5953 door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more());
5954
734c1409 5955 txd->opts1 = rtl8169_get_txd_opts1(opts[0], len, entry);
1da177e4 5956
a0750138 5957 /* Force all memory writes to complete before notifying device */
4c020a96 5958 wmb();
1da177e4 5959
a0750138
AD		 5960 tp->cur_tx += frags + 1;
5961
ef143585
HK		 5962 stop_queue = !rtl_tx_slots_avail(tp, MAX_SKB_FRAGS);
5963 if (unlikely(stop_queue)) {
0255d592
HK		 5964 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
5965 * not miss a ring update when it notices a stopped queue.
5966 */
5967 smp_wmb();
5968 netif_stop_queue(dev);
4773f9bd 5969 door_bell = true;
ef143585
HK		 5970 }
5971
5972 if (door_bell)
f1bce4ad 5973 rtl8169_doorbell(tp);
ef143585
HK		 5974
5975 if (unlikely(stop_queue)) {
ae1f23fb
FR		 5976 /* Sync with rtl_tx:
5977 * - publish queue status and cur_tx ring index (write barrier)
5978 * - refresh dirty_tx ring index (read barrier).
5979 * May the current thread have a pessimistic view of the ring
5980 * status and forget to wake up queue, a racing rtl_tx thread
5981 * can't.
5982 */
1e874e04 5983 smp_mb();
76085c9e 5984 if (rtl_tx_slots_avail(tp, MAX_SKB_FRAGS))
601ed4d6 5985 netif_start_queue(dev);
1da177e4
LT		 5986 }
5987
61357325 5988 return NETDEV_TX_OK;
1da177e4 5989
3eafe507 5990err_dma_1:
48addcc9 5991 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
3eafe507 5992err_dma_0:
989c9ba1 5993 dev_kfree_skb_any(skb);
3eafe507
SG		 5994 dev->stats.tx_dropped++;
5995 return NETDEV_TX_OK;
5996
5997err_stop_0:
1da177e4 5998 netif_stop_queue(dev);
cebf8cc7 5999 dev->stats.tx_dropped++;
61357325 6000 return NETDEV_TX_BUSY;
1da177e4
LT		 6001}
6002
e64e0c89
HK		 6003static netdev_features_t rtl8169_features_check(struct sk_buff *skb,
6004 struct net_device *dev,
6005 netdev_features_t features)
6006{
6007 int transport_offset = skb_transport_offset(skb);
6008 struct rtl8169_private *tp = netdev_priv(dev);
6009
6010 if (skb_is_gso(skb)) {
6011 if (transport_offset > GTTCPHO_MAX &&
6012 rtl_chip_supports_csum_v2(tp))
6013 features &= ~NETIF_F_ALL_TSO;
6014 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6015 if (skb->len < ETH_ZLEN) {
6016 switch (tp->mac_version) {
6017 case RTL_GIGA_MAC_VER_11:
6018 case RTL_GIGA_MAC_VER_12:
6019 case RTL_GIGA_MAC_VER_17:
6020 case RTL_GIGA_MAC_VER_34:
6021 features &= ~NETIF_F_CSUM_MASK;
6022 break;
6023 default:
6024 break;
6025 }
6026 }
6027
6028 if (transport_offset > TCPHO_MAX &&
6029 rtl_chip_supports_csum_v2(tp))
6030 features &= ~NETIF_F_CSUM_MASK;
6031 }
6032
6033 return vlan_features_check(skb, features);
6034}
6035
1da177e4
LT		 6036static void rtl8169_pcierr_interrupt(struct net_device *dev)
6037{
6038 struct rtl8169_private *tp = netdev_priv(dev);
6039 struct pci_dev *pdev = tp->pci_dev;
1da177e4
LT		 6040 u16 pci_status, pci_cmd;
6041
6042 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
6043 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
6044
bf82c189
JP		 6045 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
6046 pci_cmd, pci_status);
1da177e4
LT		 6047
6048 /*
6049 * The recovery sequence below admits a very elaborated explanation:
6050 * - it seems to work;
d03902b8
FR		 6051 * - I did not see what else could be done;
6052 * - it makes iop3xx happy.
1da177e4
LT		 6053 *
6054 * Feel free to adjust to your needs.
6055 */
a27993f3 6056 if (pdev->broken_parity_status)
d03902b8
FR		 6057 pci_cmd &= ~PCI_COMMAND_PARITY;
6058 else
6059 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
6060
6061 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 6062
6063 pci_write_config_word(pdev, PCI_STATUS,
6064 pci_status & (PCI_STATUS_DETECTED_PARITY |
6065 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
6066 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
6067
98ddf986 6068 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
1da177e4
LT		 6069}
6070
5317d5c6
HK		 6071static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp,
6072 int budget)
1da177e4 6073{
d92060bc 6074 unsigned int dirty_tx, tx_left, bytes_compl = 0, pkts_compl = 0;
1da177e4 6075
1da177e4
LT		 6076 dirty_tx = tp->dirty_tx;
6077 smp_rmb();
6078 tx_left = tp->cur_tx - dirty_tx;
6079
6080 while (tx_left > 0) {
6081 unsigned int entry = dirty_tx % NUM_TX_DESC;
6082 struct ring_info *tx_skb = tp->tx_skb + entry;
1da177e4
LT		 6083 u32 status;
6084
1da177e4
LT		 6085 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
6086 if (status & DescOwn)
6087 break;
6088
a0750138
AD		 6089 /* This barrier is needed to keep us from reading
6090 * any other fields out of the Tx descriptor until
6091 * we know the status of DescOwn
6092 */
6093 dma_rmb();
6094
1e1205b7 6095 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
48addcc9 6096 tp->TxDescArray + entry);
ae84bc18 6097 if (tx_skb->skb) {
d92060bc
FW		 6098 pkts_compl++;
6099 bytes_compl += tx_skb->skb->len;
5317d5c6 6100 napi_consume_skb(tx_skb->skb, budget);
1da177e4
LT		 6101 tx_skb->skb = NULL;
6102 }
6103 dirty_tx++;
6104 tx_left--;
6105 }
6106
6107 if (tp->dirty_tx != dirty_tx) {
d92060bc
FW		 6108 netdev_completed_queue(dev, pkts_compl, bytes_compl);
6109
6110 u64_stats_update_begin(&tp->tx_stats.syncp);
6111 tp->tx_stats.packets += pkts_compl;
6112 tp->tx_stats.bytes += bytes_compl;
6113 u64_stats_update_end(&tp->tx_stats.syncp);
6114
1da177e4 6115 tp->dirty_tx = dirty_tx;
ae1f23fb
FR		 6116 /* Sync with rtl8169_start_xmit:
6117 * - publish dirty_tx ring index (write barrier)
6118 * - refresh cur_tx ring index and queue status (read barrier)
6119 * May the current thread miss the stopped queue condition,
6120 * a racing xmit thread can only have a right view of the
6121 * ring status.
6122 */
1e874e04 6123 smp_mb();
1da177e4 6124 if (netif_queue_stopped(dev) &&
76085c9e 6125 rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) {
1da177e4
LT		 6126 netif_wake_queue(dev);
6127 }
d78ae2dc
FR		 6128 /*
6129 * 8168 hack: TxPoll requests are lost when the Tx packets are
6130 * too close. Let's kick an extra TxPoll request when a burst
6131 * of start_xmit activity is detected (if it is not detected,
6132 * it is slow enough). -- FR
6133 */
1ef7286e 6134 if (tp->cur_tx != dirty_tx)
f1bce4ad 6135 rtl8169_doorbell(tp);
1da177e4
LT		 6136 }
6137}
6138
126fa4b9
FR		 6139static inline int rtl8169_fragmented_frame(u32 status)
6140{
6141 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
6142}
6143
adea1ac7 6144static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
1da177e4 6145{
1da177e4
LT		 6146 u32 status = opts1 & RxProtoMask;
6147
6148 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
d5d3ebe3 6149 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
1da177e4
LT		 6150 skb->ip_summed = CHECKSUM_UNNECESSARY;
6151 else
bc8acf2c 6152 skb_checksum_none_assert(skb);
1da177e4
LT		 6153}
6154
da78dbff 6155static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
1da177e4
LT		 6156{
6157 unsigned int cur_rx, rx_left;
6f0333b8 6158 unsigned int count;
1da177e4 6159
1da177e4 6160 cur_rx = tp->cur_rx;
1da177e4 6161
9fba0812 6162 for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
1da177e4 6163 unsigned int entry = cur_rx % NUM_RX_DESC;
32879f00 6164 const void *rx_buf = page_address(tp->Rx_databuff[entry]);
126fa4b9 6165 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 6166 u32 status;
6167
6202806e 6168 status = le32_to_cpu(desc->opts1);
1da177e4
LT		 6169 if (status & DescOwn)
6170 break;
a0750138
AD		 6171
6172 /* This barrier is needed to keep us from reading
6173 * any other fields out of the Rx descriptor until
6174 * we know the status of DescOwn
6175 */
6176 dma_rmb();
6177
4dcb7d33 6178 if (unlikely(status & RxRES)) {
bf82c189
JP		 6179 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
6180 status);
cebf8cc7 6181 dev->stats.rx_errors++;
1da177e4 6182 if (status & (RxRWT | RxRUNT))
cebf8cc7 6183 dev->stats.rx_length_errors++;
1da177e4 6184 if (status & RxCRC)
cebf8cc7 6185 dev->stats.rx_crc_errors++;
e9588eb9
HK		 6186 if (status & (RxRUNT | RxCRC) && !(status & RxRWT) &&
6187 dev->features & NETIF_F_RXALL) {
6bbe021d 6188 goto process_pkt;
6202806e 6189 }
1da177e4 6190 } else {
fcd4e608 6191 unsigned int pkt_size;
6f0333b8 6192 struct sk_buff *skb;
6bbe021d
BG		 6193
6194process_pkt:
fcd4e608 6195 pkt_size = status & GENMASK(13, 0);
79d0c1d2 6196 if (likely(!(dev->features & NETIF_F_RXFCS)))
fcd4e608 6197 pkt_size -= ETH_FCS_LEN;
126fa4b9
FR		 6198 /*
6199 * The driver does not support incoming fragmented
6200 * frames. They are seen as a symptom of over-mtu
6201 * sized frames.
6202 */
6203 if (unlikely(rtl8169_fragmented_frame(status))) {
cebf8cc7
FR		 6204 dev->stats.rx_dropped++;
6205 dev->stats.rx_length_errors++;
ce11ff5e 6206 goto release_descriptor;
126fa4b9
FR		 6207 }
6208
fcd4e608
HK		 6209 skb = napi_alloc_skb(&tp->napi, pkt_size);
6210 if (unlikely(!skb)) {
6f0333b8 6211 dev->stats.rx_dropped++;
ce11ff5e 6212 goto release_descriptor;
1da177e4
LT		 6213 }
6214
3c95e501
HK		 6215 dma_sync_single_for_cpu(tp_to_dev(tp),
6216 le64_to_cpu(desc->addr),
6217 pkt_size, DMA_FROM_DEVICE);
32879f00
HK		 6218 prefetch(rx_buf);
6219 skb_copy_to_linear_data(skb, rx_buf, pkt_size);
fcd4e608
HK		 6220 skb->tail += pkt_size;
6221 skb->len = pkt_size;
6222
d4ed7463
HK		 6223 dma_sync_single_for_device(tp_to_dev(tp),
6224 le64_to_cpu(desc->addr),
6225 pkt_size, DMA_FROM_DEVICE);
6226
adea1ac7 6227 rtl8169_rx_csum(skb, status);
1da177e4
LT		 6228 skb->protocol = eth_type_trans(skb, dev);
6229
7a8fc77b
FR		 6230 rtl8169_rx_vlan_tag(desc, skb);
6231
39174291 6232 if (skb->pkt_type == PACKET_MULTICAST)
6233 dev->stats.multicast++;
6234
448a2413 6235 napi_gro_receive(&tp->napi, skb);
1da177e4 6236
8027aa24
JW		 6237 u64_stats_update_begin(&tp->rx_stats.syncp);
6238 tp->rx_stats.packets++;
6239 tp->rx_stats.bytes += pkt_size;
6240 u64_stats_update_end(&tp->rx_stats.syncp);
1da177e4 6241 }
ce11ff5e 6242release_descriptor:
6243 desc->opts2 = 0;
1d0254dd 6244 rtl8169_mark_to_asic(desc);
1da177e4
LT		 6245 }
6246
6247 count = cur_rx - tp->cur_rx;
6248 tp->cur_rx = cur_rx;
6249
1da177e4
LT		 6250 return count;
6251}
6252
07d3f51f 6253static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 6254{
ebcd5daa 6255 struct rtl8169_private *tp = dev_instance;
c1d532d2 6256 u32 status = rtl_get_events(tp);
1da177e4 6257
c1d532d2
HK		 6258 if (!tp->irq_enabled || (status & 0xffff) == 0xffff ||
6259 !(status & tp->irq_mask))
05bbe558 6260 return IRQ_NONE;
1da177e4 6261
38caff5a
HK		 6262 if (unlikely(status & SYSErr)) {
6263 rtl8169_pcierr_interrupt(tp->dev);
6264 goto out;
6265 }
da78dbff 6266
703732f0
HK		 6267 if (status & LinkChg)
6268 phy_mac_interrupt(tp->phydev);
1da177e4 6269
38caff5a
HK		 6270 if (unlikely(status & RxFIFOOver &&
6271 tp->mac_version == RTL_GIGA_MAC_VER_11)) {
6272 netif_stop_queue(tp->dev);
f0ff129e 6273 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
da78dbff 6274 }
1da177e4 6275
e62b2fd5 6276 rtl_irq_disable(tp);
fd3150ae 6277 napi_schedule(&tp->napi);
38caff5a
HK		 6278out:
6279 rtl_ack_events(tp, status);
1da177e4 6280
38caff5a 6281 return IRQ_HANDLED;
1da177e4
LT		 6282}
6283
4422bcd4
FR		 6284static void rtl_task(struct work_struct *work)
6285{
da78dbff
FR		 6286 static const struct {
6287 int bitnr;
6288 void (*action)(struct rtl8169_private *);
6289 } rtl_work[] = {
da78dbff 6290 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work },
da78dbff 6291 };
4422bcd4
FR		 6292 struct rtl8169_private *tp =
6293 container_of(work, struct rtl8169_private, wk.work);
da78dbff
FR		 6294 struct net_device *dev = tp->dev;
6295 int i;
6296
6297 rtl_lock_work(tp);
6298
6c4a70c5
FR		 6299 if (!netif_running(dev) ||
6300 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
da78dbff
FR		 6301 goto out_unlock;
6302
6303 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
6304 bool pending;
6305
da78dbff 6306 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
da78dbff
FR		 6307 if (pending)
6308 rtl_work[i].action(tp);
6309 }
4422bcd4 6310
da78dbff
FR		 6311out_unlock:
6312 rtl_unlock_work(tp);
4422bcd4
FR		 6313}
6314
bea3348e 6315static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 6316{
bea3348e
SH		 6317 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
6318 struct net_device *dev = tp->dev;
6b839b6c 6319 int work_done;
da78dbff 6320
6b839b6c 6321 work_done = rtl_rx(dev, tp, (u32) budget);
da78dbff 6322
5317d5c6 6323 rtl_tx(dev, tp, budget);
1da177e4 6324
bea3348e 6325 if (work_done < budget) {
6ad20165 6326 napi_complete_done(napi, work_done);
fe716f8a 6327 rtl_irq_enable(tp);
1da177e4
LT		 6328 }
6329
bea3348e 6330 return work_done;
1da177e4 6331}
1da177e4 6332
1ef7286e 6333static void rtl8169_rx_missed(struct net_device *dev)
523a6094
FR		 6334{
6335 struct rtl8169_private *tp = netdev_priv(dev);
6336
6337 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
6338 return;
6339
1ef7286e
AS		 6340 dev->stats.rx_missed_errors += RTL_R32(tp, RxMissed) & 0xffffff;
6341 RTL_W32(tp, RxMissed, 0);
523a6094
FR		 6342}
6343
f1e911d5
HK		 6344static void r8169_phylink_handler(struct net_device *ndev)
6345{
6346 struct rtl8169_private *tp = netdev_priv(ndev);
6347
6348 if (netif_carrier_ok(ndev)) {
6349 rtl_link_chg_patch(tp);
6350 pm_request_resume(&tp->pci_dev->dev);
6351 } else {
6352 pm_runtime_idle(&tp->pci_dev->dev);
6353 }
6354
6355 if (net_ratelimit())
703732f0 6356 phy_print_status(tp->phydev);
f1e911d5
HK		 6357}
6358
6359static int r8169_phy_connect(struct rtl8169_private *tp)
6360{
703732f0 6361 struct phy_device *phydev = tp->phydev;
f1e911d5
HK		 6362 phy_interface_t phy_mode;
6363 int ret;
6364
f7ffa9ae 6365 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII :
f1e911d5
HK		 6366 PHY_INTERFACE_MODE_MII;
6367
6368 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler,
6369 phy_mode);
6370 if (ret)
6371 return ret;
6372
66058b1c 6373 if (!tp->supports_gmii)
f1e911d5
HK		 6374 phy_set_max_speed(phydev, SPEED_100);
6375
9cf9b84c 6376 phy_support_asym_pause(phydev);
f1e911d5
HK		 6377
6378 phy_attached_info(phydev);
6379
6380 return 0;
6381}
6382
1da177e4
LT		 6383static void rtl8169_down(struct net_device *dev)
6384{
6385 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 6386
703732f0 6387 phy_stop(tp->phydev);
f1e911d5 6388
93dd79e8 6389 napi_disable(&tp->napi);
da78dbff 6390 netif_stop_queue(dev);
1da177e4 6391
92fc43b4 6392 rtl8169_hw_reset(tp);
323bb685
SG		 6393 /*
6394 * At this point device interrupts can not be enabled in any function,
209e5ac8
FR		 6395 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
6396 * and napi is disabled (rtl8169_poll).
323bb685 6397 */
1ef7286e 6398 rtl8169_rx_missed(dev);
1da177e4 6399
1da177e4 6400 /* Give a racing hard_start_xmit a few cycles to complete. */
16f11500 6401 synchronize_rcu();
1da177e4 6402
1da177e4
LT		 6403 rtl8169_tx_clear(tp);
6404
6405 rtl8169_rx_clear(tp);
065c27c1 6406
6407 rtl_pll_power_down(tp);
1da177e4
LT		 6408}
6409
6410static int rtl8169_close(struct net_device *dev)
6411{
6412 struct rtl8169_private *tp = netdev_priv(dev);
6413 struct pci_dev *pdev = tp->pci_dev;
6414
e1759441
RW		 6415 pm_runtime_get_sync(&pdev->dev);
6416
cecb5fd7 6417 /* Update counters before going down */
e71c9ce2 6418 rtl8169_update_counters(tp);
355423d0 6419
da78dbff 6420 rtl_lock_work(tp);
6ad56901
KHF		 6421 /* Clear all task flags */
6422 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
da78dbff 6423
1da177e4 6424 rtl8169_down(dev);
da78dbff 6425 rtl_unlock_work(tp);
1da177e4 6426
4ea72445
L		 6427 cancel_work_sync(&tp->wk.work);
6428
d5f04d39 6429 free_irq(pci_irq_vector(pdev, 0), tp);
1da177e4 6430
9344d919
HK		 6431 phy_disconnect(tp->phydev);
6432
82553bb6
SG		 6433 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6434 tp->RxPhyAddr);
6435 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6436 tp->TxPhyAddr);
1da177e4
LT		 6437 tp->TxDescArray = NULL;
6438 tp->RxDescArray = NULL;
6439
e1759441
RW		 6440 pm_runtime_put_sync(&pdev->dev);
6441
1da177e4
LT		 6442 return 0;
6443}
6444
dc1c00ce
FR		 6445#ifdef CONFIG_NET_POLL_CONTROLLER
6446static void rtl8169_netpoll(struct net_device *dev)
6447{
6448 struct rtl8169_private *tp = netdev_priv(dev);
6449
6d8b8349 6450 rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp);
dc1c00ce
FR		 6451}
6452#endif
6453
df43ac78
FR		 6454static int rtl_open(struct net_device *dev)
6455{
6456 struct rtl8169_private *tp = netdev_priv(dev);
df43ac78
FR		 6457 struct pci_dev *pdev = tp->pci_dev;
6458 int retval = -ENOMEM;
6459
6460 pm_runtime_get_sync(&pdev->dev);
6461
6462 /*
e75d6606 6463 * Rx and Tx descriptors needs 256 bytes alignment.
df43ac78
FR		 6464 * dma_alloc_coherent provides more.
6465 */
6466 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
6467 &tp->TxPhyAddr, GFP_KERNEL);
6468 if (!tp->TxDescArray)
6469 goto err_pm_runtime_put;
6470
6471 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
6472 &tp->RxPhyAddr, GFP_KERNEL);
6473 if (!tp->RxDescArray)
6474 goto err_free_tx_0;
6475
b1127e64 6476 retval = rtl8169_init_ring(tp);
df43ac78
FR		 6477 if (retval < 0)
6478 goto err_free_rx_1;
6479
df43ac78
FR		 6480 rtl_request_firmware(tp);
6481
d5f04d39 6482 retval = request_irq(pci_irq_vector(pdev, 0), rtl8169_interrupt,
fd3150ae 6483 IRQF_SHARED, dev->name, tp);
df43ac78
FR		 6484 if (retval < 0)
6485 goto err_release_fw_2;
6486
f1e911d5
HK		 6487 retval = r8169_phy_connect(tp);
6488 if (retval)
6489 goto err_free_irq;
6490
df43ac78
FR		 6491 rtl_lock_work(tp);
6492
6493 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6494
6495 napi_enable(&tp->napi);
6496
6497 rtl8169_init_phy(dev, tp);
6498
df43ac78
FR		 6499 rtl_pll_power_up(tp);
6500
61cb532d 6501 rtl_hw_start(tp);
df43ac78 6502
e71c9ce2 6503 if (!rtl8169_init_counter_offsets(tp))
6e85d5ad
CV		 6504 netif_warn(tp, hw, dev, "counter reset/update failed\n");
6505
703732f0 6506 phy_start(tp->phydev);
df43ac78
FR		 6507 netif_start_queue(dev);
6508
6509 rtl_unlock_work(tp);
6510
a92a0849 6511 pm_runtime_put_sync(&pdev->dev);
df43ac78
FR		 6512out:
6513 return retval;
6514
f1e911d5 6515err_free_irq:
d5f04d39 6516 free_irq(pci_irq_vector(pdev, 0), tp);
df43ac78
FR		 6517err_release_fw_2:
6518 rtl_release_firmware(tp);
6519 rtl8169_rx_clear(tp);
6520err_free_rx_1:
6521 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6522 tp->RxPhyAddr);
6523 tp->RxDescArray = NULL;
6524err_free_tx_0:
6525 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6526 tp->TxPhyAddr);
6527 tp->TxDescArray = NULL;
6528err_pm_runtime_put:
6529 pm_runtime_put_noidle(&pdev->dev);
6530 goto out;
6531}
6532
bc1f4470 6533static void
8027aa24 6534rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
1da177e4
LT		 6535{
6536 struct rtl8169_private *tp = netdev_priv(dev);
f09cf4b7 6537 struct pci_dev *pdev = tp->pci_dev;
42020320 6538 struct rtl8169_counters *counters = tp->counters;
8027aa24 6539 unsigned int start;
1da177e4 6540
f09cf4b7
CHL		 6541 pm_runtime_get_noresume(&pdev->dev);
6542
6543 if (netif_running(dev) && pm_runtime_active(&pdev->dev))
1ef7286e 6544 rtl8169_rx_missed(dev);
5b0384f4 6545
8027aa24 6546 do {
57a7744e 6547 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
8027aa24
JW		 6548 stats->rx_packets = tp->rx_stats.packets;
6549 stats->rx_bytes = tp->rx_stats.bytes;
57a7744e 6550 } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
8027aa24 6551
8027aa24 6552 do {
57a7744e 6553 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
8027aa24
JW		 6554 stats->tx_packets = tp->tx_stats.packets;
6555 stats->tx_bytes = tp->tx_stats.bytes;
57a7744e 6556 } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
8027aa24
JW		 6557
6558 stats->rx_dropped = dev->stats.rx_dropped;
6559 stats->tx_dropped = dev->stats.tx_dropped;
6560 stats->rx_length_errors = dev->stats.rx_length_errors;
6561 stats->rx_errors = dev->stats.rx_errors;
6562 stats->rx_crc_errors = dev->stats.rx_crc_errors;
6563 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
6564 stats->rx_missed_errors = dev->stats.rx_missed_errors;
d7d2d89d 6565 stats->multicast = dev->stats.multicast;
8027aa24 6566
6e85d5ad 6567 /*
ed72a9bb 6568 * Fetch additional counter values missing in stats collected by driver
6e85d5ad
CV		 6569 * from tally counters.
6570 */
f09cf4b7 6571 if (pm_runtime_active(&pdev->dev))
e71c9ce2 6572 rtl8169_update_counters(tp);
6e85d5ad
CV		 6573
6574 /*
6575 * Subtract values fetched during initalization.
6576 * See rtl8169_init_counter_offsets for a description why we do that.
6577 */
42020320 6578 stats->tx_errors = le64_to_cpu(counters->tx_errors) -
6e85d5ad 6579 le64_to_cpu(tp->tc_offset.tx_errors);
42020320 6580 stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
6e85d5ad 6581 le32_to_cpu(tp->tc_offset.tx_multi_collision);
42020320 6582 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
6e85d5ad
CV		 6583 le16_to_cpu(tp->tc_offset.tx_aborted);
6584
f09cf4b7 6585 pm_runtime_put_noidle(&pdev->dev);
1da177e4
LT		 6586}
6587
861ab440 6588static void rtl8169_net_suspend(struct net_device *dev)
5d06a99f 6589{
065c27c1 6590 struct rtl8169_private *tp = netdev_priv(dev);
6591
5d06a99f 6592 if (!netif_running(dev))
861ab440 6593 return;
5d06a99f 6594
703732f0 6595 phy_stop(tp->phydev);
5d06a99f 6596 netif_device_detach(dev);
da78dbff
FR		 6597
6598 rtl_lock_work(tp);
6599 napi_disable(&tp->napi);
6ad56901
KHF		 6600 /* Clear all task flags */
6601 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
6602
da78dbff
FR		 6603 rtl_unlock_work(tp);
6604
6605 rtl_pll_power_down(tp);
861ab440
RW		 6606}
6607
6608#ifdef CONFIG_PM
6609
6610static int rtl8169_suspend(struct device *device)
6611{
0f07bd85 6612 struct net_device *dev = dev_get_drvdata(device);
ac8bd9e1 6613 struct rtl8169_private *tp = netdev_priv(dev);
5d06a99f 6614
861ab440 6615 rtl8169_net_suspend(dev);
ac8bd9e1 6616 clk_disable_unprepare(tp->clk);
1371fa6d 6617
5d06a99f
FR		 6618 return 0;
6619}
6620
e1759441
RW		 6621static void __rtl8169_resume(struct net_device *dev)
6622{
065c27c1 6623 struct rtl8169_private *tp = netdev_priv(dev);
6624
e1759441 6625 netif_device_attach(dev);
065c27c1 6626
6627 rtl_pll_power_up(tp);
92bad850 6628 rtl8169_init_phy(dev, tp);
065c27c1 6629
703732f0 6630 phy_start(tp->phydev);
f1e911d5 6631
cff4c162
AS		 6632 rtl_lock_work(tp);
6633 napi_enable(&tp->napi);
6c4a70c5 6634 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
58ba566c 6635 rtl_reset_work(tp);
cff4c162 6636 rtl_unlock_work(tp);
e1759441
RW		 6637}
6638
861ab440 6639static int rtl8169_resume(struct device *device)
5d06a99f 6640{
0f07bd85 6641 struct net_device *dev = dev_get_drvdata(device);
ac8bd9e1
HG		 6642 struct rtl8169_private *tp = netdev_priv(dev);
6643
59715171
HK		 6644 rtl_rar_set(tp, dev->dev_addr);
6645
ac8bd9e1 6646 clk_prepare_enable(tp->clk);
5d06a99f 6647
e1759441
RW		 6648 if (netif_running(dev))
6649 __rtl8169_resume(dev);
5d06a99f 6650
e1759441
RW		 6651 return 0;
6652}
6653
6654static int rtl8169_runtime_suspend(struct device *device)
6655{
0f07bd85 6656 struct net_device *dev = dev_get_drvdata(device);
e1759441
RW		 6657 struct rtl8169_private *tp = netdev_priv(dev);
6658
07df5bd8 6659 if (!tp->TxDescArray)
e1759441
RW		 6660 return 0;
6661
da78dbff 6662 rtl_lock_work(tp);
e1759441 6663 __rtl8169_set_wol(tp, WAKE_ANY);
da78dbff 6664 rtl_unlock_work(tp);
e1759441
RW		 6665
6666 rtl8169_net_suspend(dev);
6667
f09cf4b7 6668 /* Update counters before going runtime suspend */
1ef7286e 6669 rtl8169_rx_missed(dev);
e71c9ce2 6670 rtl8169_update_counters(tp);
f09cf4b7 6671
e1759441
RW		 6672 return 0;
6673}
6674
6675static int rtl8169_runtime_resume(struct device *device)
6676{
0f07bd85 6677 struct net_device *dev = dev_get_drvdata(device);
e1759441 6678 struct rtl8169_private *tp = netdev_priv(dev);
59715171 6679
f51d4a10 6680 rtl_rar_set(tp, dev->dev_addr);
e1759441
RW		 6681
6682 if (!tp->TxDescArray)
6683 return 0;
6684
da78dbff 6685 rtl_lock_work(tp);
e1759441 6686 __rtl8169_set_wol(tp, tp->saved_wolopts);
da78dbff 6687 rtl_unlock_work(tp);
e1759441
RW		 6688
6689 __rtl8169_resume(dev);
5d06a99f 6690
5d06a99f
FR		 6691 return 0;
6692}
6693
e1759441
RW		 6694static int rtl8169_runtime_idle(struct device *device)
6695{
0f07bd85 6696 struct net_device *dev = dev_get_drvdata(device);
e1759441 6697
a92a0849
HK		 6698 if (!netif_running(dev) || !netif_carrier_ok(dev))
6699 pm_schedule_suspend(device, 10000);
6700
6701 return -EBUSY;
e1759441
RW		 6702}
6703
47145210 6704static const struct dev_pm_ops rtl8169_pm_ops = {
cecb5fd7
FR		 6705 .suspend = rtl8169_suspend,
6706 .resume = rtl8169_resume,
6707 .freeze = rtl8169_suspend,
6708 .thaw = rtl8169_resume,
6709 .poweroff = rtl8169_suspend,
6710 .restore = rtl8169_resume,
6711 .runtime_suspend = rtl8169_runtime_suspend,
6712 .runtime_resume = rtl8169_runtime_resume,
6713 .runtime_idle = rtl8169_runtime_idle,
861ab440
RW		 6714};
6715
6716#define RTL8169_PM_OPS (&rtl8169_pm_ops)
6717
6718#else /* !CONFIG_PM */
6719
6720#define RTL8169_PM_OPS NULL
6721
6722#endif /* !CONFIG_PM */
6723
649b3b8c 6724static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
6725{
649b3b8c 6726 /* WoL fails with 8168b when the receiver is disabled. */
6727 switch (tp->mac_version) {
6728 case RTL_GIGA_MAC_VER_11:
6729 case RTL_GIGA_MAC_VER_12:
6730 case RTL_GIGA_MAC_VER_17:
6731 pci_clear_master(tp->pci_dev);
6732
1ef7286e 6733 RTL_W8(tp, ChipCmd, CmdRxEnb);
649b3b8c 6734 /* PCI commit */
1ef7286e 6735 RTL_R8(tp, ChipCmd);
649b3b8c 6736 break;
6737 default:
6738 break;
6739 }
6740}
6741
1765f95d
FR		 6742static void rtl_shutdown(struct pci_dev *pdev)
6743{
861ab440 6744 struct net_device *dev = pci_get_drvdata(pdev);
4bb3f522 6745 struct rtl8169_private *tp = netdev_priv(dev);
861ab440
RW		 6746
6747 rtl8169_net_suspend(dev);
1765f95d 6748
cecb5fd7 6749 /* Restore original MAC address */
cc098dc7
IV		 6750 rtl_rar_set(tp, dev->perm_addr);
6751
92fc43b4 6752 rtl8169_hw_reset(tp);
4bb3f522 6753
861ab440 6754 if (system_state == SYSTEM_POWER_OFF) {
433f9d0d 6755 if (tp->saved_wolopts) {
649b3b8c 6756 rtl_wol_suspend_quirk(tp);
6757 rtl_wol_shutdown_quirk(tp);
ca52efd5 6758 }
6759
861ab440
RW		 6760 pci_wake_from_d3(pdev, true);
6761 pci_set_power_state(pdev, PCI_D3hot);
6762 }
6763}
5d06a99f 6764
baf63293 6765static void rtl_remove_one(struct pci_dev *pdev)
e27566ed
FR		 6766{
6767 struct net_device *dev = pci_get_drvdata(pdev);
6768 struct rtl8169_private *tp = netdev_priv(dev);
6769
9dbe7896 6770 if (r8168_check_dash(tp))
e27566ed 6771 rtl8168_driver_stop(tp);
e27566ed 6772
ad1be8d3
DN		 6773 netif_napi_del(&tp->napi);
6774
e27566ed 6775 unregister_netdev(dev);
703732f0 6776 mdiobus_unregister(tp->phydev->mdio.bus);
e27566ed
FR		 6777
6778 rtl_release_firmware(tp);
6779
6780 if (pci_dev_run_wake(pdev))
6781 pm_runtime_get_noresume(&pdev->dev);
6782
6783 /* restore original MAC address */
6784 rtl_rar_set(tp, dev->perm_addr);
e27566ed
FR		 6785}
6786
fa9c385e 6787static const struct net_device_ops rtl_netdev_ops = {
df43ac78 6788 .ndo_open = rtl_open,
fa9c385e
FR		 6789 .ndo_stop = rtl8169_close,
6790 .ndo_get_stats64 = rtl8169_get_stats64,
6791 .ndo_start_xmit = rtl8169_start_xmit,
e64e0c89 6792 .ndo_features_check = rtl8169_features_check,
fa9c385e
FR		 6793 .ndo_tx_timeout = rtl8169_tx_timeout,
6794 .ndo_validate_addr = eth_validate_addr,
6795 .ndo_change_mtu = rtl8169_change_mtu,
6796 .ndo_fix_features = rtl8169_fix_features,
6797 .ndo_set_features = rtl8169_set_features,
6798 .ndo_set_mac_address = rtl_set_mac_address,
6799 .ndo_do_ioctl = rtl8169_ioctl,
6800 .ndo_set_rx_mode = rtl_set_rx_mode,
6801#ifdef CONFIG_NET_POLL_CONTROLLER
6802 .ndo_poll_controller = rtl8169_netpoll,
6803#endif
6804
6805};
6806
ec9a4088
HK		 6807static void rtl_set_irq_mask(struct rtl8169_private *tp)
6808{
6809 tp->irq_mask = RTL_EVENT_NAPI | LinkChg;
6810
6811 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
6812 tp->irq_mask |= SYSErr | RxOverflow | RxFIFOOver;
6813 else if (tp->mac_version == RTL_GIGA_MAC_VER_11)
6814 /* special workaround needed */
6815 tp->irq_mask |= RxFIFOOver;
6816 else
6817 tp->irq_mask |= RxOverflow;
6818}
6819
6c6aa15f 6820static int rtl_alloc_irq(struct rtl8169_private *tp)
31fa8b18 6821{
6c6aa15f 6822 unsigned int flags;
31fa8b18 6823
003bd5b4
HK		 6824 switch (tp->mac_version) {
6825 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
df320ed7 6826 rtl_unlock_config_regs(tp);
1ef7286e 6827 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
df320ed7 6828 rtl_lock_config_regs(tp);
003bd5b4 6829 /* fall through */
8ff7ebf2 6830 case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_17:
6c6aa15f 6831 flags = PCI_IRQ_LEGACY;
003bd5b4
HK		 6832 break;
6833 default:
6c6aa15f 6834 flags = PCI_IRQ_ALL_TYPES;
003bd5b4 6835 break;
31fa8b18 6836 }
6c6aa15f
HK		 6837
6838 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
31fa8b18
FR		 6839}
6840
04c7788c
TR		 6841static void rtl_read_mac_address(struct rtl8169_private *tp,
6842 u8 mac_addr[ETH_ALEN])
6843{
6844 /* Get MAC address */
9e9f33ba
HK		 6845 if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) {
6846 u32 value = rtl_eri_read(tp, 0xe0);
6847
deedf1fe
TR		 6848 mac_addr[0] = (value >> 0) & 0xff;
6849 mac_addr[1] = (value >> 8) & 0xff;
6850 mac_addr[2] = (value >> 16) & 0xff;
6851 mac_addr[3] = (value >> 24) & 0xff;
6852
724c6fd0 6853 value = rtl_eri_read(tp, 0xe4);
deedf1fe
TR		 6854 mac_addr[4] = (value >> 0) & 0xff;
6855 mac_addr[5] = (value >> 8) & 0xff;
f1bce4ad
HK		 6856 } else if (rtl_is_8125(tp)) {
6857 rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP);
04c7788c
TR		 6858 }
6859}
6860
c558386b
HW		 6861DECLARE_RTL_COND(rtl_link_list_ready_cond)
6862{
1ef7286e 6863 return RTL_R8(tp, MCU) & LINK_LIST_RDY;
c558386b
HW		 6864}
6865
6866DECLARE_RTL_COND(rtl_rxtx_empty_cond)
6867{
1ef7286e 6868 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
c558386b
HW		 6869}
6870
f1e911d5
HK		 6871static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg)
6872{
6873 struct rtl8169_private *tp = mii_bus->priv;
6874
6875 if (phyaddr > 0)
6876 return -ENODEV;
6877
6878 return rtl_readphy(tp, phyreg);
6879}
6880
6881static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr,
6882 int phyreg, u16 val)
6883{
6884 struct rtl8169_private *tp = mii_bus->priv;
6885
6886 if (phyaddr > 0)
6887 return -ENODEV;
6888
6889 rtl_writephy(tp, phyreg, val);
6890
6891 return 0;
6892}
6893
6894static int r8169_mdio_register(struct rtl8169_private *tp)
6895{
6896 struct pci_dev *pdev = tp->pci_dev;
f1e911d5
HK		 6897 struct mii_bus *new_bus;
6898 int ret;
6899
6900 new_bus = devm_mdiobus_alloc(&pdev->dev);
6901 if (!new_bus)
6902 return -ENOMEM;
6903
6904 new_bus->name = "r8169";
6905 new_bus->priv = tp;
6906 new_bus->parent = &pdev->dev;
6907 new_bus->irq[0] = PHY_IGNORE_INTERRUPT;
a195016a 6908 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x", pci_dev_id(pdev));
f1e911d5
HK		 6909
6910 new_bus->read = r8169_mdio_read_reg;
6911 new_bus->write = r8169_mdio_write_reg;
6912
6913 ret = mdiobus_register(new_bus);
6914 if (ret)
6915 return ret;
6916
703732f0
HK		 6917 tp->phydev = mdiobus_get_phy(new_bus, 0);
6918 if (!tp->phydev) {
f1e911d5
HK		 6919 mdiobus_unregister(new_bus);
6920 return -ENODEV;
2f38bab7
HK		 6921 } else if (!tp->phydev->drv) {
6922 /* Most chip versions fail with the genphy driver.
6923 * Therefore ensure that the dedicated PHY driver is loaded.
6924 */
6925 dev_err(&pdev->dev, "realtek.ko not loaded, maybe it needs to be added to initramfs?\n");
6926 mdiobus_unregister(new_bus);
6927 return -EUNATCH;
f1e911d5
HK		 6928 }
6929
242cd9b5 6930 /* PHY will be woken up in rtl_open() */
703732f0 6931 phy_suspend(tp->phydev);
f1e911d5
HK		 6932
6933 return 0;
6934}
6935
baf63293 6936static void rtl_hw_init_8168g(struct rtl8169_private *tp)
c558386b 6937{
c558386b
HW		 6938 tp->ocp_base = OCP_STD_PHY_BASE;
6939
1ef7286e 6940 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
c558386b
HW		 6941
6942 if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
6943 return;
6944
6945 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
6946 return;
6947
1ef7286e 6948 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
c558386b 6949 msleep(1);
1ef7286e 6950 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
c558386b 6951
ef712ede 6952 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);
c558386b
HW		 6953
6954 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
6955 return;
6956
ef712ede 6957 r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15));
c558386b 6958
7160be2d 6959 rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42);
c558386b
HW		 6960}
6961
f1bce4ad
HK		 6962static void rtl_hw_init_8125(struct rtl8169_private *tp)
6963{
6964 tp->ocp_base = OCP_STD_PHY_BASE;
6965
6966 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
6967
6968 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
6969 return;
6970
6971 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
6972 msleep(1);
6973 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
6974
6975 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);
6976
6977 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
6978 return;
6979
6980 r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0);
6981 r8168_mac_ocp_write(tp, 0xc0a6, 0x0150);
6982 r8168_mac_ocp_write(tp, 0xc01e, 0x5555);
6983
6984 rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42);
6985}
6986
baf63293 6987static void rtl_hw_initialize(struct rtl8169_private *tp)
c558386b
HW		 6988{
6989 switch (tp->mac_version) {
2e13d773 6990 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52:
29ec0482
HK		 6991 rtl8168ep_stop_cmac(tp);
6992 /* fall through */
2a71883c 6993 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
003609da
CHL		 6994 rtl_hw_init_8168g(tp);
6995 break;
f1bce4ad
HK		 6996 case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_61:
6997 rtl_hw_init_8125(tp);
6998 break;
c558386b
HW		 6999 default:
7000 break;
7001 }
7002}
7003
abe8b2f7
HK		 7004static int rtl_jumbo_max(struct rtl8169_private *tp)
7005{
7006 /* Non-GBit versions don't support jumbo frames */
7007 if (!tp->supports_gmii)
7008 return JUMBO_1K;
7009
7010 switch (tp->mac_version) {
7011 /* RTL8169 */
e9588eb9 7012 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
abe8b2f7
HK		 7013 return JUMBO_7K;
7014 /* RTL8168b */
7015 case RTL_GIGA_MAC_VER_11:
7016 case RTL_GIGA_MAC_VER_12:
7017 case RTL_GIGA_MAC_VER_17:
7018 return JUMBO_4K;
7019 /* RTL8168c */
7020 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
7021 return JUMBO_6K;
7022 default:
7023 return JUMBO_9K;
7024 }
7025}
7026
c2f6f3ee
HG		 7027static void rtl_disable_clk(void *data)
7028{
7029 clk_disable_unprepare(data);
7030}
7031
b779daea
HK		 7032static int rtl_get_ether_clk(struct rtl8169_private *tp)
7033{
7034 struct device *d = tp_to_dev(tp);
7035 struct clk *clk;
7036 int rc;
7037
7038 clk = devm_clk_get(d, "ether_clk");
7039 if (IS_ERR(clk)) {
7040 rc = PTR_ERR(clk);
7041 if (rc == -ENOENT)
7042 /* clk-core allows NULL (for suspend / resume) */
7043 rc = 0;
7044 else if (rc != -EPROBE_DEFER)
7045 dev_err(d, "failed to get clk: %d\n", rc);
7046 } else {
7047 tp->clk = clk;
7048 rc = clk_prepare_enable(clk);
7049 if (rc)
7050 dev_err(d, "failed to enable clk: %d\n", rc);
7051 else
7052 rc = devm_add_action_or_reset(d, rtl_disable_clk, clk);
7053 }
7054
7055 return rc;
7056}
7057
c782e204
HK		 7058static void rtl_init_mac_address(struct rtl8169_private *tp)
7059{
7060 struct net_device *dev = tp->dev;
7061 u8 *mac_addr = dev->dev_addr;
ce37115e 7062 int rc;
c782e204
HK		 7063
7064 rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr);
7065 if (!rc)
7066 goto done;
7067
7068 rtl_read_mac_address(tp, mac_addr);
7069 if (is_valid_ether_addr(mac_addr))
7070 goto done;
7071
ce37115e 7072 rtl_read_mac_from_reg(tp, mac_addr, MAC0);
c782e204
HK		 7073 if (is_valid_ether_addr(mac_addr))
7074 goto done;
7075
7076 eth_hw_addr_random(dev);
7077 dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n");
7078done:
7079 rtl_rar_set(tp, mac_addr);
7080}
7081
929a031d 7082static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3b6cf25d 7083{
3b6cf25d 7084 struct rtl8169_private *tp;
3b6cf25d 7085 struct net_device *dev;
c782e204 7086 int chipset, region;
abe8b2f7 7087 int jumbo_max, rc;
3b6cf25d 7088
4c45d24a
HK		 7089 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
7090 if (!dev)
7091 return -ENOMEM;
3b6cf25d
FR		 7092
7093 SET_NETDEV_DEV(dev, &pdev->dev);
fa9c385e 7094 dev->netdev_ops = &rtl_netdev_ops;
3b6cf25d
FR		 7095 tp = netdev_priv(dev);
7096 tp->dev = dev;
7097 tp->pci_dev = pdev;
7098 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
145a40e8 7099 tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1;
488202f5 7100 tp->eee_adv = -1;
3b6cf25d 7101
c2f6f3ee 7102 /* Get the *optional* external "ether_clk" used on some boards */
b779daea
HK		 7103 rc = rtl_get_ether_clk(tp);
7104 if (rc)
7105 return rc;
c2f6f3ee 7106
b75bb8a5
HK		 7107 /* Disable ASPM completely as that cause random device stop working
7108 * problems as well as full system hangs for some PCIe devices users.
7109 */
47a7e9f7 7110 rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L1_1);
62b1b3b3 7111 tp->aspm_manageable = !rc;
b75bb8a5 7112
3b6cf25d 7113 /* enable device (incl. PCI PM wakeup and hotplug setup) */
4c45d24a 7114 rc = pcim_enable_device(pdev);
3b6cf25d 7115 if (rc < 0) {
22148df0 7116 dev_err(&pdev->dev, "enable failure\n");
4c45d24a 7117 return rc;
3b6cf25d
FR		 7118 }
7119
4c45d24a 7120 if (pcim_set_mwi(pdev) < 0)
22148df0 7121 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n");
3b6cf25d 7122
c8d48d9c
HK		 7123 /* use first MMIO region */
7124 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1;
7125 if (region < 0) {
22148df0 7126 dev_err(&pdev->dev, "no MMIO resource found\n");
4c45d24a 7127 return -ENODEV;
3b6cf25d
FR		 7128 }
7129
7130 /* check for weird/broken PCI region reporting */
7131 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
22148df0 7132 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n");
4c45d24a 7133 return -ENODEV;
3b6cf25d
FR		 7134 }
7135
93a00d4d 7136 rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME);
3b6cf25d 7137 if (rc < 0) {
22148df0 7138 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
4c45d24a 7139 return rc;
3b6cf25d
FR		 7140 }
7141
93a00d4d 7142 tp->mmio_addr = pcim_iomap_table(pdev)[region];
3b6cf25d 7143
3b6cf25d 7144 /* Identify chip attached to board */
b4cc2dcc
HK		 7145 rtl8169_get_mac_version(tp);
7146 if (tp->mac_version == RTL_GIGA_MAC_NONE)
7147 return -ENODEV;
3b6cf25d 7148
0ae0974e 7149 tp->cp_cmd = RTL_R16(tp, CPlusCmd);
27896c83 7150
10b63e85 7151 if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 &&
3c18cbe3 7152 !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)))
27896c83 7153 dev->features |= NETIF_F_HIGHDMA;
27896c83 7154
3b6cf25d
FR		 7155 rtl_init_rxcfg(tp);
7156
de20e12f 7157 rtl8169_irq_mask_and_ack(tp);
3b6cf25d 7158
c558386b
HW		 7159 rtl_hw_initialize(tp);
7160
3b6cf25d
FR		 7161 rtl_hw_reset(tp);
7162
3b6cf25d
FR		 7163 pci_set_master(pdev);
7164
3b6cf25d 7165 chipset = tp->mac_version;
3b6cf25d 7166
6c6aa15f
HK		 7167 rc = rtl_alloc_irq(tp);
7168 if (rc < 0) {
22148df0 7169 dev_err(&pdev->dev, "Can't allocate interrupt\n");
6c6aa15f
HK		 7170 return rc;
7171 }
3b6cf25d 7172
3b6cf25d 7173 mutex_init(&tp->wk.mutex);
5c41e78f 7174 INIT_WORK(&tp->wk.work, rtl_task);
340fea3d
KM		 7175 u64_stats_init(&tp->rx_stats.syncp);
7176 u64_stats_init(&tp->tx_stats.syncp);
3b6cf25d 7177
c782e204 7178 rtl_init_mac_address(tp);
3b6cf25d 7179
7ad24ea4 7180 dev->ethtool_ops = &rtl8169_ethtool_ops;
3b6cf25d 7181
37621493 7182 netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT);
3b6cf25d 7183
250c1837
HK		 7184 dev->features |= NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
7185 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
7186 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
7187 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
3b6cf25d
FR		 7188 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7189 NETIF_F_HIGHDMA;
2d0ec544 7190 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
3b6cf25d 7191
dc161162
HK		 7192 tp->cp_cmd |= RxChkSum;
7193 /* RTL8125 uses register RxConfig for VLAN offloading config */
7194 if (!rtl_is_8125(tp))
7195 tp->cp_cmd |= RxVlan;
929a031d 7196 /*
7197 * Pretend we are using VLANs; This bypasses a nasty bug where
7198 * Interrupts stop flowing on high load on 8110SCd controllers.
7199 */
3b6cf25d 7200 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
929a031d 7201 /* Disallow toggling */
f646968f 7202 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3b6cf25d 7203
0170d594 7204 if (rtl_chip_supports_csum_v2(tp)) {
250c1837
HK		 7205 dev->hw_features |= NETIF_F_IPV6_CSUM;
7206 dev->features |= NETIF_F_IPV6_CSUM;
7207 }
7208
7209 /* There has been a number of reports that using SG/TSO results in
7210 * tx timeouts. However for a lot of people SG/TSO works fine.
7211 * Therefore disable both features by default, but allow users to
7212 * enable them. Use at own risk!
7213 */
7214 if (rtl_chip_supports_csum_v2(tp)) {
7215 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6;
0170d594
HK		 7216 dev->gso_max_size = RTL_GSO_MAX_SIZE_V2;
7217 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V2;
7218 } else {
250c1837 7219 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO;
0170d594
HK		 7220 dev->gso_max_size = RTL_GSO_MAX_SIZE_V1;
7221 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V1;
7222 }
5888d3fc 7223
3b6cf25d
FR		 7224 dev->hw_features |= NETIF_F_RXALL;
7225 dev->hw_features |= NETIF_F_RXFCS;
7226
c7315a95
JW		 7227 /* MTU range: 60 - hw-specific max */
7228 dev->min_mtu = ETH_ZLEN;
abe8b2f7
HK		 7229 jumbo_max = rtl_jumbo_max(tp);
7230 dev->max_mtu = jumbo_max;
c7315a95 7231
ec9a4088 7232 rtl_set_irq_mask(tp);
9fa0a8e1 7233
254764e5 7234 tp->fw_name = rtl_chip_infos[chipset].fw_name;
3b6cf25d 7235
4c45d24a
HK		 7236 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
7237 &tp->counters_phys_addr,
7238 GFP_KERNEL);
4cf964af
HK		 7239 if (!tp->counters)
7240 return -ENOMEM;
42020320 7241
19c9ea36
HK		 7242 pci_set_drvdata(pdev, dev);
7243
f1e911d5
HK		 7244 rc = r8169_mdio_register(tp);
7245 if (rc)
4cf964af 7246 return rc;
3b6cf25d 7247
07df5bd8
HK		 7248 /* chip gets powered up in rtl_open() */
7249 rtl_pll_power_down(tp);
7250
f1e911d5
HK		 7251 rc = register_netdev(dev);
7252 if (rc)
7253 goto err_mdio_unregister;
7254
55d2ad7b 7255 netif_info(tp, probe, dev, "%s, %pM, XID %03x, IRQ %d\n",
2d6c5a61 7256 rtl_chip_infos[chipset].name, dev->dev_addr,
55d2ad7b 7257 (RTL_R32(tp, TxConfig) >> 20) & 0xfcf,
29274991 7258 pci_irq_vector(pdev, 0));
abe8b2f7
HK		 7259
7260 if (jumbo_max > JUMBO_1K)
7261 netif_info(tp, probe, dev,
7262 "jumbo features [frames: %d bytes, tx checksumming: %s]\n",
7263 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ?
7264 "ok" : "ko");
3b6cf25d 7265
9dbe7896 7266 if (r8168_check_dash(tp))
3b6cf25d 7267 rtl8168_driver_start(tp);
3b6cf25d 7268
a92a0849
HK		 7269 if (pci_dev_run_wake(pdev))
7270 pm_runtime_put_sync(&pdev->dev);
7271
4c45d24a 7272 return 0;
f1e911d5
HK		 7273
7274err_mdio_unregister:
703732f0 7275 mdiobus_unregister(tp->phydev->mdio.bus);
f1e911d5 7276 return rc;
3b6cf25d
FR		 7277}
7278
1da177e4
LT		 7279static struct pci_driver rtl8169_pci_driver = {
7280 .name = MODULENAME,
7281 .id_table = rtl8169_pci_tbl,
3b6cf25d 7282 .probe = rtl_init_one,
baf63293 7283 .remove = rtl_remove_one,
1765f95d 7284 .shutdown = rtl_shutdown,
861ab440 7285 .driver.pm = RTL8169_PM_OPS,
1da177e4
LT		 7286};
7287
3eeb7da9 7288module_pci_driver(rtl8169_pci_driver);
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