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r8169: improve RTL8168b FIFO overflow workaround
[mirror_ubuntu-focal-kernel.git] / drivers / net / ethernet / realtek / r8169_main.c
CommitLineData
09c434b8 1// SPDX-License-Identifier: GPL-2.0-only
1da177e4 2/*
07d3f51f
FR		 3 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 *
5 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
7 * Copyright (c) a lot of people too. Please respect their work.
8 *
9 * See MAINTAINERS file for support contact information.
1da177e4
LT		 10 */
11
12#include <linux/module.h>
13#include <linux/moduleparam.h>
14#include <linux/pci.h>
15#include <linux/netdevice.h>
16#include <linux/etherdevice.h>
c2f6f3ee 17#include <linux/clk.h>
1da177e4
LT		 18#include <linux/delay.h>
19#include <linux/ethtool.h>
f1e911d5 20#include <linux/phy.h>
1da177e4
LT		 21#include <linux/if_vlan.h>
22#include <linux/crc32.h>
23#include <linux/in.h>
098b01ad 24#include <linux/io.h>
1da177e4
LT		 25#include <linux/ip.h>
26#include <linux/tcp.h>
a6b7a407 27#include <linux/interrupt.h>
1da177e4 28#include <linux/dma-mapping.h>
e1759441 29#include <linux/pm_runtime.h>
70c71606 30#include <linux/prefetch.h>
e974604b 31#include <linux/ipv6.h>
32#include <net/ip6_checksum.h>
1da177e4 33
8197f9d2
HK		 34#include "r8169_firmware.h"
35
1da177e4 36#define MODULENAME "r8169"
1da177e4 37
bca03d5f 38#define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
39#define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
01dc7fec 40#define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
41#define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
70090424 42#define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
c2218925
HW		 43#define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
44#define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
5a5e4443 45#define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
7e18dca1 46#define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
b3d7b2f2 47#define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
45dd95c4 48#define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw"
5598bfe5 49#define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
58152cd4 50#define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw"
beb330a4 51#define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw"
57538c4a 52#define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw"
6e1d0b89
CHL		 53#define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw"
54#define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw"
6e526a7f 55#define FIRMWARE_8168FP_3 "rtl_nic/rtl8168fp-3.fw"
6e1d0b89
CHL		 56#define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw"
57#define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw"
02bf642b 58#define FIRMWARE_8125A_3 "rtl_nic/rtl8125a-3.fw"
bca03d5f 59
b57b7e5a 60#define R8169_MSG_DEFAULT \
f0e837d9 61 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 62
1da177e4
LT		 63/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
64 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
81cd17a4 65#define MC_FILTER_LIMIT 32
1da177e4 66
aee77e4a 67#define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
1da177e4
LT		 68#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
69
70#define R8169_REGS_SIZE 256
1d0254dd 71#define R8169_RX_BUF_SIZE (SZ_16K - 1)
1da177e4 72#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
9fba0812 73#define NUM_RX_DESC 256U /* Number of Rx descriptor registers */
1da177e4
LT		 74#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
75#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
76
145a40e8
HK		 77#define RTL_CFG_NO_GBIT 1
78
1da177e4 79/* write/read MMIO register */
1ef7286e
AS		 80#define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg))
81#define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
82#define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
83#define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg))
84#define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg))
85#define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg))
1da177e4
LT		 86
87enum mac_version {
e9588eb9 88 /* support for ancient RTL_GIGA_MAC_VER_01 has been removed */
85bffe6c
FR		 89 RTL_GIGA_MAC_VER_02,
90 RTL_GIGA_MAC_VER_03,
91 RTL_GIGA_MAC_VER_04,
92 RTL_GIGA_MAC_VER_05,
93 RTL_GIGA_MAC_VER_06,
94 RTL_GIGA_MAC_VER_07,
95 RTL_GIGA_MAC_VER_08,
96 RTL_GIGA_MAC_VER_09,
97 RTL_GIGA_MAC_VER_10,
98 RTL_GIGA_MAC_VER_11,
99 RTL_GIGA_MAC_VER_12,
100 RTL_GIGA_MAC_VER_13,
101 RTL_GIGA_MAC_VER_14,
102 RTL_GIGA_MAC_VER_15,
103 RTL_GIGA_MAC_VER_16,
104 RTL_GIGA_MAC_VER_17,
105 RTL_GIGA_MAC_VER_18,
106 RTL_GIGA_MAC_VER_19,
107 RTL_GIGA_MAC_VER_20,
108 RTL_GIGA_MAC_VER_21,
109 RTL_GIGA_MAC_VER_22,
110 RTL_GIGA_MAC_VER_23,
111 RTL_GIGA_MAC_VER_24,
112 RTL_GIGA_MAC_VER_25,
113 RTL_GIGA_MAC_VER_26,
114 RTL_GIGA_MAC_VER_27,
115 RTL_GIGA_MAC_VER_28,
116 RTL_GIGA_MAC_VER_29,
117 RTL_GIGA_MAC_VER_30,
118 RTL_GIGA_MAC_VER_31,
119 RTL_GIGA_MAC_VER_32,
120 RTL_GIGA_MAC_VER_33,
70090424 121 RTL_GIGA_MAC_VER_34,
c2218925
HW		 122 RTL_GIGA_MAC_VER_35,
123 RTL_GIGA_MAC_VER_36,
7e18dca1 124 RTL_GIGA_MAC_VER_37,
b3d7b2f2 125 RTL_GIGA_MAC_VER_38,
5598bfe5 126 RTL_GIGA_MAC_VER_39,
c558386b
HW		 127 RTL_GIGA_MAC_VER_40,
128 RTL_GIGA_MAC_VER_41,
57538c4a 129 RTL_GIGA_MAC_VER_42,
58152cd4 130 RTL_GIGA_MAC_VER_43,
45dd95c4 131 RTL_GIGA_MAC_VER_44,
6e1d0b89
CHL		 132 RTL_GIGA_MAC_VER_45,
133 RTL_GIGA_MAC_VER_46,
134 RTL_GIGA_MAC_VER_47,
135 RTL_GIGA_MAC_VER_48,
935e2218
CHL		 136 RTL_GIGA_MAC_VER_49,
137 RTL_GIGA_MAC_VER_50,
138 RTL_GIGA_MAC_VER_51,
2e13d773 139 RTL_GIGA_MAC_VER_52,
f1bce4ad
HK		 140 RTL_GIGA_MAC_VER_60,
141 RTL_GIGA_MAC_VER_61,
76719ee2 142 RTL_GIGA_MAC_NONE
1da177e4
LT		 143};
144
d58d46b5
FR		 145#define JUMBO_1K ETH_DATA_LEN
146#define JUMBO_4K (4*1024 - ETH_HLEN - 2)
147#define JUMBO_6K (6*1024 - ETH_HLEN - 2)
148#define JUMBO_7K (7*1024 - ETH_HLEN - 2)
149#define JUMBO_9K (9*1024 - ETH_HLEN - 2)
150
3c6bee1d 151static const struct {
1da177e4 152 const char *name;
953a12cc 153 const char *fw_name;
85bffe6c
FR		 154} rtl_chip_infos[] = {
155 /* PCI devices. */
abe8b2f7
HK		 156 [RTL_GIGA_MAC_VER_02] = {"RTL8169s" },
157 [RTL_GIGA_MAC_VER_03] = {"RTL8110s" },
158 [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb" },
159 [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc" },
160 [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc" },
85bffe6c 161 /* PCI-E devices. */
abe8b2f7
HK		 162 [RTL_GIGA_MAC_VER_07] = {"RTL8102e" },
163 [RTL_GIGA_MAC_VER_08] = {"RTL8102e" },
9e0773c3 164 [RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e" },
abe8b2f7
HK		 165 [RTL_GIGA_MAC_VER_10] = {"RTL8101e" },
166 [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b" },
167 [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b" },
168 [RTL_GIGA_MAC_VER_13] = {"RTL8101e" },
169 [RTL_GIGA_MAC_VER_14] = {"RTL8100e" },
170 [RTL_GIGA_MAC_VER_15] = {"RTL8100e" },
171 [RTL_GIGA_MAC_VER_16] = {"RTL8101e" },
172 [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b" },
173 [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp" },
174 [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c" },
175 [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c" },
176 [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c" },
177 [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c" },
178 [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp" },
179 [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp" },
180 [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d", FIRMWARE_8168D_1},
181 [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d", FIRMWARE_8168D_2},
182 [RTL_GIGA_MAC_VER_27] = {"RTL8168dp/8111dp" },
183 [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp" },
184 [RTL_GIGA_MAC_VER_29] = {"RTL8105e", FIRMWARE_8105E_1},
185 [RTL_GIGA_MAC_VER_30] = {"RTL8105e", FIRMWARE_8105E_1},
186 [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp" },
187 [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e", FIRMWARE_8168E_1},
188 [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e", FIRMWARE_8168E_2},
189 [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3},
190 [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f", FIRMWARE_8168F_1},
191 [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f", FIRMWARE_8168F_2},
192 [RTL_GIGA_MAC_VER_37] = {"RTL8402", FIRMWARE_8402_1 },
193 [RTL_GIGA_MAC_VER_38] = {"RTL8411", FIRMWARE_8411_1 },
194 [RTL_GIGA_MAC_VER_39] = {"RTL8106e", FIRMWARE_8106E_1},
195 [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g", FIRMWARE_8168G_2},
196 [RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g" },
9e0773c3
HK		 197 [RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu", FIRMWARE_8168G_3},
198 [RTL_GIGA_MAC_VER_43] = {"RTL8106eus", FIRMWARE_8106E_2},
199 [RTL_GIGA_MAC_VER_44] = {"RTL8411b", FIRMWARE_8411_2 },
abe8b2f7
HK		 200 [RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h", FIRMWARE_8168H_1},
201 [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h", FIRMWARE_8168H_2},
202 [RTL_GIGA_MAC_VER_47] = {"RTL8107e", FIRMWARE_8107E_1},
203 [RTL_GIGA_MAC_VER_48] = {"RTL8107e", FIRMWARE_8107E_2},
204 [RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep" },
205 [RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep" },
206 [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep" },
6e526a7f 207 [RTL_GIGA_MAC_VER_52] = {"RTL8168fp/RTL8117", FIRMWARE_8168FP_3},
f1bce4ad 208 [RTL_GIGA_MAC_VER_60] = {"RTL8125" },
02bf642b 209 [RTL_GIGA_MAC_VER_61] = {"RTL8125", FIRMWARE_8125A_3},
953a12cc
FR		 210};
211
9baa3c34 212static const struct pci_device_id rtl8169_pci_tbl[] = {
145a40e8
HK		 213 { PCI_VDEVICE(REALTEK, 0x2502) },
214 { PCI_VDEVICE(REALTEK, 0x2600) },
215 { PCI_VDEVICE(REALTEK, 0x8129) },
216 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_NO_GBIT },
217 { PCI_VDEVICE(REALTEK, 0x8161) },
218 { PCI_VDEVICE(REALTEK, 0x8167) },
219 { PCI_VDEVICE(REALTEK, 0x8168) },
220 { PCI_VDEVICE(NCUBE, 0x8168) },
221 { PCI_VDEVICE(REALTEK, 0x8169) },
6f0d3088 222 { PCI_VENDOR_ID_DLINK, 0x4300,
145a40e8 223 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 },
9d9f3fba
HK		 224 { PCI_VDEVICE(DLINK, 0x4300) },
225 { PCI_VDEVICE(DLINK, 0x4302) },
226 { PCI_VDEVICE(AT, 0xc107) },
227 { PCI_VDEVICE(USR, 0x0116) },
228 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 },
229 { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 },
f1bce4ad
HK		 230 { PCI_VDEVICE(REALTEK, 0x8125) },
231 { PCI_VDEVICE(REALTEK, 0x3000) },
6f0d3088 232 {}
1da177e4
LT		 233};
234
235MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
236
b57b7e5a
SH		 237static struct {
238 u32 msg_enable;
239} debug = { -1 };
1da177e4 240
07d3f51f
FR		 241enum rtl_registers {
242 MAC0 = 0, /* Ethernet hardware address. */
773d2021 243 MAC4 = 4,
07d3f51f
FR		 244 MAR0 = 8, /* Multicast filter. */
245 CounterAddrLow = 0x10,
246 CounterAddrHigh = 0x14,
247 TxDescStartAddrLow = 0x20,
248 TxDescStartAddrHigh = 0x24,
249 TxHDescStartAddrLow = 0x28,
250 TxHDescStartAddrHigh = 0x2c,
251 FLASH = 0x30,
252 ERSR = 0x36,
253 ChipCmd = 0x37,
254 TxPoll = 0x38,
255 IntrMask = 0x3c,
256 IntrStatus = 0x3e,
4f6b00e5 257
07d3f51f 258 TxConfig = 0x40,
4f6b00e5
HW		 259#define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
260#define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
2b7b4318 261
4f6b00e5
HW		 262 RxConfig = 0x44,
263#define RX128_INT_EN (1 << 15) /* 8111c and later */
264#define RX_MULTI_EN (1 << 14) /* 8111c only */
265#define RXCFG_FIFO_SHIFT 13
266 /* No threshold before first PCI xfer */
267#define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
beb330a4 268#define RX_EARLY_OFF (1 << 11)
4f6b00e5
HW		 269#define RXCFG_DMA_SHIFT 8
270 /* Unlimited maximum PCI burst. */
271#define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
2b7b4318 272
07d3f51f
FR		 273 RxMissed = 0x4c,
274 Cfg9346 = 0x50,
275 Config0 = 0x51,
276 Config1 = 0x52,
277 Config2 = 0x53,
d387b427
FR		 278#define PME_SIGNAL (1 << 5) /* 8168c and later */
279
07d3f51f
FR		 280 Config3 = 0x54,
281 Config4 = 0x55,
282 Config5 = 0x56,
07d3f51f 283 PHYAR = 0x60,
07d3f51f
FR		 284 PHYstatus = 0x6c,
285 RxMaxSize = 0xda,
286 CPlusCmd = 0xe0,
287 IntrMitigate = 0xe2,
50970831
FR		 288
289#define RTL_COALESCE_MASK 0x0f
290#define RTL_COALESCE_SHIFT 4
291#define RTL_COALESCE_T_MAX (RTL_COALESCE_MASK)
292#define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_MASK << 2)
293
07d3f51f
FR		 294 RxDescAddrLow = 0xe4,
295 RxDescAddrHigh = 0xe8,
f0298f81 296 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
297
298#define NoEarlyTx 0x3f /* Max value : no early transmit. */
299
300 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
301
302#define TxPacketMax (8064 >> 7)
3090bd9a 303#define EarlySize 0x27
f0298f81 304
07d3f51f
FR		 305 FuncEvent = 0xf0,
306 FuncEventMask = 0xf4,
307 FuncPresetState = 0xf8,
935e2218
CHL		 308 IBCR0 = 0xf8,
309 IBCR2 = 0xf9,
310 IBIMR0 = 0xfa,
311 IBISR0 = 0xfb,
07d3f51f 312 FuncForceEvent = 0xfc,
1da177e4
LT		 313};
314
f162a5d1
FR		 315enum rtl8168_8101_registers {
316 CSIDR = 0x64,
317 CSIAR = 0x68,
318#define CSIAR_FLAG 0x80000000
319#define CSIAR_WRITE_CMD 0x80000000
ff1d7331
HK		 320#define CSIAR_BYTE_ENABLE 0x0000f000
321#define CSIAR_ADDR_MASK 0x00000fff
065c27c1 322 PMCH = 0x6f,
f162a5d1
FR		 323 EPHYAR = 0x80,
324#define EPHYAR_FLAG 0x80000000
325#define EPHYAR_WRITE_CMD 0x80000000
326#define EPHYAR_REG_MASK 0x1f
327#define EPHYAR_REG_SHIFT 16
328#define EPHYAR_DATA_MASK 0xffff
5a5e4443 329 DLLPR = 0xd0,
4f6b00e5 330#define PFM_EN (1 << 6)
6e1d0b89 331#define TX_10M_PS_EN (1 << 7)
f162a5d1
FR		 332 DBG_REG = 0xd1,
333#define FIX_NAK_1 (1 << 4)
334#define FIX_NAK_2 (1 << 3)
5a5e4443
HW		 335 TWSI = 0xd2,
336 MCU = 0xd3,
4f6b00e5 337#define NOW_IS_OOB (1 << 7)
c558386b
HW		 338#define TX_EMPTY (1 << 5)
339#define RX_EMPTY (1 << 4)
340#define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
5a5e4443
HW		 341#define EN_NDP (1 << 3)
342#define EN_OOB_RESET (1 << 2)
c558386b 343#define LINK_LIST_RDY (1 << 1)
daf9df6d 344 EFUSEAR = 0xdc,
345#define EFUSEAR_FLAG 0x80000000
346#define EFUSEAR_WRITE_CMD 0x80000000
347#define EFUSEAR_READ_CMD 0x00000000
348#define EFUSEAR_REG_MASK 0x03ff
349#define EFUSEAR_REG_SHIFT 8
350#define EFUSEAR_DATA_MASK 0xff
6e1d0b89
CHL		 351 MISC_1 = 0xf2,
352#define PFM_D3COLD_EN (1 << 6)
f162a5d1
FR		 353};
354
c0e45c1c 355enum rtl8168_registers {
4f6b00e5
HW		 356 LED_FREQ = 0x1a,
357 EEE_LED = 0x1b,
b646d900 358 ERIDR = 0x70,
359 ERIAR = 0x74,
360#define ERIAR_FLAG 0x80000000
361#define ERIAR_WRITE_CMD 0x80000000
362#define ERIAR_READ_CMD 0x00000000
363#define ERIAR_ADDR_BYTE_ALIGN 4
b646d900 364#define ERIAR_TYPE_SHIFT 16
4f6b00e5
HW		 365#define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
366#define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
367#define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
935e2218 368#define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT)
4f6b00e5
HW		 369#define ERIAR_MASK_SHIFT 12
370#define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
371#define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
6e1d0b89 372#define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT)
c558386b 373#define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
4f6b00e5 374#define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
c0e45c1c 375 EPHY_RXER_NUM = 0x7c,
376 OCPDR = 0xb0, /* OCP GPHY access */
377#define OCPDR_WRITE_CMD 0x80000000
378#define OCPDR_READ_CMD 0x00000000
379#define OCPDR_REG_MASK 0x7f
380#define OCPDR_GPHY_REG_SHIFT 16
381#define OCPDR_DATA_MASK 0xffff
382 OCPAR = 0xb4,
383#define OCPAR_FLAG 0x80000000
384#define OCPAR_GPHY_WRITE_CMD 0x8000f060
385#define OCPAR_GPHY_READ_CMD 0x0000f060
c558386b 386 GPHY_OCP = 0xb8,
01dc7fec 387 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
388 MISC = 0xf0, /* 8168e only. */
cecb5fd7 389#define TXPLA_RST (1 << 29)
5598bfe5 390#define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
4f6b00e5 391#define PWM_EN (1 << 22)
c558386b 392#define RXDV_GATED_EN (1 << 19)
5598bfe5 393#define EARLY_TALLY_EN (1 << 16)
c0e45c1c 394};
395
f1bce4ad
HK		 396enum rtl8125_registers {
397 IntrMask_8125 = 0x38,
398 IntrStatus_8125 = 0x3c,
399 TxPoll_8125 = 0x90,
400 MAC0_BKP = 0x19e0,
401};
402
403#define RX_VLAN_INNER_8125 BIT(22)
404#define RX_VLAN_OUTER_8125 BIT(23)
405#define RX_VLAN_8125 (RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125)
406
407#define RX_FETCH_DFLT_8125 (8 << 27)
408
07d3f51f 409enum rtl_register_content {
1da177e4 410 /* InterruptStatusBits */
07d3f51f
FR		 411 SYSErr = 0x8000,
412 PCSTimeout = 0x4000,
413 SWInt = 0x0100,
414 TxDescUnavail = 0x0080,
415 RxFIFOOver = 0x0040,
416 LinkChg = 0x0020,
417 RxOverflow = 0x0010,
418 TxErr = 0x0008,
419 TxOK = 0x0004,
420 RxErr = 0x0002,
421 RxOK = 0x0001,
1da177e4
LT		 422
423 /* RxStatusDesc */
9dccf611
FR		 424 RxRWT = (1 << 22),
425 RxRES = (1 << 21),
426 RxRUNT = (1 << 20),
427 RxCRC = (1 << 19),
1da177e4
LT		 428
429 /* ChipCmdBits */
4f6b00e5 430 StopReq = 0x80,
07d3f51f
FR		 431 CmdReset = 0x10,
432 CmdRxEnb = 0x08,
433 CmdTxEnb = 0x04,
434 RxBufEmpty = 0x01,
1da177e4 435
275391a4
FR		 436 /* TXPoll register p.5 */
437 HPQ = 0x80, /* Poll cmd on the high prio queue */
438 NPQ = 0x40, /* Poll cmd on the low prio queue */
439 FSWInt = 0x01, /* Forced software interrupt */
440
1da177e4 441 /* Cfg9346Bits */
07d3f51f
FR		 442 Cfg9346_Lock = 0x00,
443 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 444
445 /* rx_mode_bits */
07d3f51f
FR		 446 AcceptErr = 0x20,
447 AcceptRunt = 0x10,
448 AcceptBroadcast = 0x08,
449 AcceptMulticast = 0x04,
450 AcceptMyPhys = 0x02,
451 AcceptAllPhys = 0x01,
1687b566 452#define RX_CONFIG_ACCEPT_MASK 0x3f
1da177e4 453
1da177e4
LT		 454 /* TxConfigBits */
455 TxInterFrameGapShift = 24,
456 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
457
5d06a99f 458 /* Config1 register p.24 */
f162a5d1
FR		 459 LEDS1 = (1 << 7),
460 LEDS0 = (1 << 6),
f162a5d1
FR		 461 Speed_down = (1 << 4),
462 MEMMAP = (1 << 3),
463 IOMAP = (1 << 2),
464 VPD = (1 << 1),
5d06a99f
FR		 465 PMEnable = (1 << 0), /* Power Management Enable */
466
6dccd16b 467 /* Config2 register p. 25 */
57538c4a 468 ClkReqEn = (1 << 7), /* Clock Request Enable */
2ca6cf06 469 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
6dccd16b
FR		 470 PCI_Clock_66MHz = 0x01,
471 PCI_Clock_33MHz = 0x00,
472
61a4dcc2
FR		 473 /* Config3 register p.25 */
474 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
475 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
d58d46b5 476 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
b51ecea8 477 Rdy_to_L23 = (1 << 1), /* L23 Enable */
f162a5d1 478 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
61a4dcc2 479
d58d46b5
FR		 480 /* Config4 register */
481 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
482
5d06a99f 483 /* Config5 register p.27 */
61a4dcc2
FR		 484 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
485 MWF = (1 << 5), /* Accept Multicast wakeup frame */
486 UWF = (1 << 4), /* Accept Unicast wakeup frame */
cecb5fd7 487 Spi_en = (1 << 3),
61a4dcc2 488 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f 489 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
57538c4a 490 ASPM_en = (1 << 0), /* ASPM enable */
5d06a99f 491
1da177e4 492 /* CPlusCmd p.31 */
f162a5d1
FR		 493 EnableBist = (1 << 15), // 8168 8101
494 Mac_dbgo_oe = (1 << 14), // 8168 8101
495 Normal_mode = (1 << 13), // unused
496 Force_half_dup = (1 << 12), // 8168 8101
497 Force_rxflow_en = (1 << 11), // 8168 8101
498 Force_txflow_en = (1 << 10), // 8168 8101
499 Cxpl_dbg_sel = (1 << 9), // 8168 8101
500 ASF = (1 << 8), // 8168 8101
501 PktCntrDisable = (1 << 7), // 8168 8101
502 Mac_dbgo_sel = 0x001c, // 8168
1da177e4
LT		 503 RxVlan = (1 << 6),
504 RxChkSum = (1 << 5),
505 PCIDAC = (1 << 4),
506 PCIMulRW = (1 << 3),
9a3c81fa 507#define INTT_MASK GENMASK(1, 0)
bc73241e 508#define CPCMD_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
1da177e4
LT		 509
510 /* rtl8169_PHYstatus */
07d3f51f
FR		 511 TBI_Enable = 0x80,
512 TxFlowCtrl = 0x40,
513 RxFlowCtrl = 0x20,
514 _1000bpsF = 0x10,
515 _100bps = 0x08,
516 _10bps = 0x04,
517 LinkStatus = 0x02,
518 FullDup = 0x01,
1da177e4 519
6e85d5ad
CV		 520 /* ResetCounterCommand */
521 CounterReset = 0x1,
522
d4a3a0fc 523 /* DumpCounterCommand */
07d3f51f 524 CounterDump = 0x8,
6e1d0b89
CHL		 525
526 /* magic enable v2 */
527 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */
1da177e4
LT		 528};
529
2b7b4318
FR		 530enum rtl_desc_bit {
531 /* First doubleword. */
1da177e4
LT		 532 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
533 RingEnd = (1 << 30), /* End of descriptor ring */
534 FirstFrag = (1 << 29), /* First segment of a packet */
535 LastFrag = (1 << 28), /* Final segment of a packet */
2b7b4318
FR		 536};
537
538/* Generic case. */
539enum rtl_tx_desc_bit {
540 /* First doubleword. */
541 TD_LSO = (1 << 27), /* Large Send Offload */
542#define TD_MSS_MAX 0x07ffu /* MSS value */
1da177e4 543
2b7b4318
FR		 544 /* Second doubleword. */
545 TxVlanTag = (1 << 17), /* Add VLAN tag */
546};
547
548/* 8169, 8168b and 810x except 8102e. */
549enum rtl_tx_desc_bit_0 {
550 /* First doubleword. */
551#define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
552 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
553 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
554 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
555};
556
557/* 8102e, 8168c and beyond. */
558enum rtl_tx_desc_bit_1 {
bdfa4ed6 559 /* First doubleword. */
560 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */
e974604b 561 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */
bdfa4ed6 562#define GTTCPHO_SHIFT 18
e64e0c89 563#define GTTCPHO_MAX 0x7f
bdfa4ed6 564
2b7b4318 565 /* Second doubleword. */
e974604b 566#define TCPHO_SHIFT 18
e64e0c89 567#define TCPHO_MAX 0x3ff
2b7b4318 568#define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
e974604b 569 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */
570 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */
2b7b4318
FR		 571 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
572 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
573};
1da177e4 574
2b7b4318 575enum rtl_rx_desc_bit {
1da177e4
LT		 576 /* Rx private */
577 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
9b60047a 578 PID0 = (1 << 17), /* Protocol ID bit 0/2 */
1da177e4
LT		 579
580#define RxProtoUDP (PID1)
581#define RxProtoTCP (PID0)
582#define RxProtoIP (PID1 | PID0)
583#define RxProtoMask RxProtoIP
584
585 IPFail = (1 << 16), /* IP checksum failed */
586 UDPFail = (1 << 15), /* UDP/IP checksum failed */
587 TCPFail = (1 << 14), /* TCP/IP checksum failed */
588 RxVlanTag = (1 << 16), /* VLAN tag available */
589};
590
591#define RsvdMask 0x3fffc000
592
0170d594
HK		 593#define RTL_GSO_MAX_SIZE_V1 32000
594#define RTL_GSO_MAX_SEGS_V1 24
595#define RTL_GSO_MAX_SIZE_V2 64000
596#define RTL_GSO_MAX_SEGS_V2 64
597
1da177e4 598struct TxDesc {
6cccd6e7
REB		 599 __le32 opts1;
600 __le32 opts2;
601 __le64 addr;
1da177e4
LT		 602};
603
604struct RxDesc {
6cccd6e7
REB		 605 __le32 opts1;
606 __le32 opts2;
607 __le64 addr;
1da177e4
LT		 608};
609
610struct ring_info {
611 struct sk_buff *skb;
612 u32 len;
1da177e4
LT		 613};
614
355423d0
IV		 615struct rtl8169_counters {
616 __le64 tx_packets;
617 __le64 rx_packets;
618 __le64 tx_errors;
619 __le32 rx_errors;
620 __le16 rx_missed;
621 __le16 align_errors;
622 __le32 tx_one_collision;
623 __le32 tx_multi_collision;
624 __le64 rx_unicast;
625 __le64 rx_broadcast;
626 __le32 rx_multicast;
627 __le16 tx_aborted;
628 __le16 tx_underun;
629};
630
6e85d5ad
CV		 631struct rtl8169_tc_offsets {
632 bool inited;
633 __le64 tx_errors;
634 __le32 tx_multi_collision;
6e85d5ad
CV		 635 __le16 tx_aborted;
636};
637
da78dbff 638enum rtl_flag {
6ad56901 639 RTL_FLAG_TASK_ENABLED = 0,
da78dbff 640 RTL_FLAG_TASK_RESET_PENDING,
da78dbff
FR		 641 RTL_FLAG_MAX
642};
643
8027aa24
JW		 644struct rtl8169_stats {
645 u64 packets;
646 u64 bytes;
647 struct u64_stats_sync syncp;
648};
649
1da177e4
LT		 650struct rtl8169_private {
651 void __iomem *mmio_addr; /* memory map physical address */
cecb5fd7 652 struct pci_dev *pci_dev;
c4028958 653 struct net_device *dev;
703732f0 654 struct phy_device *phydev;
bea3348e 655 struct napi_struct napi;
b57b7e5a 656 u32 msg_enable;
76719ee2 657 enum mac_version mac_version;
1da177e4
LT		 658 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
659 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
1da177e4 660 u32 dirty_tx;
8027aa24
JW		 661 struct rtl8169_stats rx_stats;
662 struct rtl8169_stats tx_stats;
1da177e4
LT		 663 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
664 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
665 dma_addr_t TxPhyAddr;
666 dma_addr_t RxPhyAddr;
32879f00 667 struct page *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
1da177e4 668 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
1da177e4 669 u16 cp_cmd;
c1d532d2 670 u32 irq_mask;
c2f6f3ee 671 struct clk *clk;
c0e45c1c 672
4422bcd4 673 struct {
da78dbff
FR		 674 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
675 struct mutex mutex;
4422bcd4
FR		 676 struct work_struct work;
677 } wk;
678
c8248c6c 679 unsigned irq_enabled:1;
f7ffa9ae 680 unsigned supports_gmii:1;
62b1b3b3 681 unsigned aspm_manageable:1;
42020320
CV		 682 dma_addr_t counters_phys_addr;
683 struct rtl8169_counters *counters;
6e85d5ad 684 struct rtl8169_tc_offsets tc_offset;
e1759441 685 u32 saved_wolopts;
488202f5 686 int eee_adv;
f1e02ed1 687
254764e5 688 const char *fw_name;
8197f9d2 689 struct rtl_fw *rtl_fw;
c558386b
HW		 690
691 u32 ocp_base;
1da177e4
LT		 692};
693
1fcd1658
HK		 694typedef void (*rtl_generic_fct)(struct rtl8169_private *tp);
695
979b6c13 696MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 697MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
b57b7e5a
SH		 698module_param_named(debug, debug.msg_enable, int, 0);
699MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
11287b69 700MODULE_SOFTDEP("pre: realtek");
1da177e4 701MODULE_LICENSE("GPL");
bca03d5f 702MODULE_FIRMWARE(FIRMWARE_8168D_1);
703MODULE_FIRMWARE(FIRMWARE_8168D_2);
01dc7fec 704MODULE_FIRMWARE(FIRMWARE_8168E_1);
705MODULE_FIRMWARE(FIRMWARE_8168E_2);
bbb8af75 706MODULE_FIRMWARE(FIRMWARE_8168E_3);
5a5e4443 707MODULE_FIRMWARE(FIRMWARE_8105E_1);
c2218925
HW		 708MODULE_FIRMWARE(FIRMWARE_8168F_1);
709MODULE_FIRMWARE(FIRMWARE_8168F_2);
7e18dca1 710MODULE_FIRMWARE(FIRMWARE_8402_1);
b3d7b2f2 711MODULE_FIRMWARE(FIRMWARE_8411_1);
45dd95c4 712MODULE_FIRMWARE(FIRMWARE_8411_2);
5598bfe5 713MODULE_FIRMWARE(FIRMWARE_8106E_1);
58152cd4 714MODULE_FIRMWARE(FIRMWARE_8106E_2);
beb330a4 715MODULE_FIRMWARE(FIRMWARE_8168G_2);
57538c4a 716MODULE_FIRMWARE(FIRMWARE_8168G_3);
6e1d0b89
CHL		 717MODULE_FIRMWARE(FIRMWARE_8168H_1);
718MODULE_FIRMWARE(FIRMWARE_8168H_2);
6e526a7f 719MODULE_FIRMWARE(FIRMWARE_8168FP_3);
a3bf5c42
FR		 720MODULE_FIRMWARE(FIRMWARE_8107E_1);
721MODULE_FIRMWARE(FIRMWARE_8107E_2);
02bf642b 722MODULE_FIRMWARE(FIRMWARE_8125A_3);
1da177e4 723
1e1205b7
HK		 724static inline struct device *tp_to_dev(struct rtl8169_private *tp)
725{
726 return &tp->pci_dev->dev;
727}
728
da78dbff
FR		 729static void rtl_lock_work(struct rtl8169_private *tp)
730{
731 mutex_lock(&tp->wk.mutex);
732}
733
734static void rtl_unlock_work(struct rtl8169_private *tp)
735{
736 mutex_unlock(&tp->wk.mutex);
737}
738
df320ed7
HK		 739static void rtl_lock_config_regs(struct rtl8169_private *tp)
740{
741 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
742}
743
744static void rtl_unlock_config_regs(struct rtl8169_private *tp)
745{
746 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
747}
748
cb73200c 749static void rtl_tx_performance_tweak(struct rtl8169_private *tp, u16 force)
d58d46b5 750{
cb73200c 751 pcie_capability_clear_and_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
7d7903b2 752 PCI_EXP_DEVCTL_READRQ, force);
d58d46b5
FR		 753}
754
f1bce4ad
HK		 755static bool rtl_is_8125(struct rtl8169_private *tp)
756{
757 return tp->mac_version >= RTL_GIGA_MAC_VER_60;
758}
759
9e9f33ba
HK		 760static bool rtl_is_8168evl_up(struct rtl8169_private *tp)
761{
762 return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
c623305b 763 tp->mac_version != RTL_GIGA_MAC_VER_39 &&
2e13d773 764 tp->mac_version <= RTL_GIGA_MAC_VER_52;
9e9f33ba
HK		 765}
766
2e779ddb
HK		 767static bool rtl_supports_eee(struct rtl8169_private *tp)
768{
769 return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
770 tp->mac_version != RTL_GIGA_MAC_VER_37 &&
771 tp->mac_version != RTL_GIGA_MAC_VER_39;
772}
773
ce37115e
HK		 774static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg)
775{
776 int i;
777
778 for (i = 0; i < ETH_ALEN; i++)
779 mac[i] = RTL_R8(tp, reg + i);
780}
781
ffc46952
FR		 782struct rtl_cond {
783 bool (*check)(struct rtl8169_private *);
784 const char *msg;
785};
786
787static void rtl_udelay(unsigned int d)
788{
789 udelay(d);
790}
791
792static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
793 void (*delay)(unsigned int), unsigned int d, int n,
794 bool high)
795{
796 int i;
797
798 for (i = 0; i < n; i++) {
ffc46952
FR		 799 if (c->check(tp) == high)
800 return true;
d1f5050b 801 delay(d);
ffc46952 802 }
82e316ef
FR		 803 netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
804 c->msg, !high, n, d);
ffc46952
FR		 805 return false;
806}
807
808static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
809 const struct rtl_cond *c,
810 unsigned int d, int n)
811{
812 return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
813}
814
815static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
816 const struct rtl_cond *c,
817 unsigned int d, int n)
818{
819 return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
820}
821
822static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
823 const struct rtl_cond *c,
824 unsigned int d, int n)
825{
826 return rtl_loop_wait(tp, c, msleep, d, n, true);
827}
828
829static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
830 const struct rtl_cond *c,
831 unsigned int d, int n)
832{
833 return rtl_loop_wait(tp, c, msleep, d, n, false);
834}
835
836#define DECLARE_RTL_COND(name) \
837static bool name ## _check(struct rtl8169_private *); \
838 \
839static const struct rtl_cond name = { \
840 .check = name ## _check, \
841 .msg = #name \
842}; \
843 \
844static bool name ## _check(struct rtl8169_private *tp)
845
c558386b
HW		 846static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
847{
848 if (reg & 0xffff0001) {
849 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
850 return true;
851 }
852 return false;
853}
854
855DECLARE_RTL_COND(rtl_ocp_gphy_cond)
856{
1ef7286e 857 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
c558386b
HW		 858}
859
860static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
861{
c558386b
HW		 862 if (rtl_ocp_reg_failure(tp, reg))
863 return;
864
1ef7286e 865 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
c558386b
HW		 866
867 rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
868}
869
9b994b4a 870static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
c558386b 871{
c558386b
HW		 872 if (rtl_ocp_reg_failure(tp, reg))
873 return 0;
874
1ef7286e 875 RTL_W32(tp, GPHY_OCP, reg << 15);
c558386b
HW		 876
877 return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
9b994b4a 878 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT;
c558386b
HW		 879}
880
c558386b
HW		 881static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
882{
c558386b
HW		 883 if (rtl_ocp_reg_failure(tp, reg))
884 return;
885
1ef7286e 886 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
c558386b
HW		 887}
888
889static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
890{
c558386b
HW		 891 if (rtl_ocp_reg_failure(tp, reg))
892 return 0;
893
1ef7286e 894 RTL_W32(tp, OCPDR, reg << 15);
c558386b 895
1ef7286e 896 return RTL_R32(tp, OCPDR);
c558386b
HW		 897}
898
ef712ede
HK		 899static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask,
900 u16 set)
901{
902 u16 data = r8168_mac_ocp_read(tp, reg);
903
904 r8168_mac_ocp_write(tp, reg, (data & ~mask) | set);
905}
906
c558386b
HW		 907#define OCP_STD_PHY_BASE 0xa400
908
909static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
910{
911 if (reg == 0x1f) {
912 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
913 return;
914 }
915
916 if (tp->ocp_base != OCP_STD_PHY_BASE)
917 reg -= 0x10;
918
919 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
920}
921
922static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
923{
9c6850fe
HK		 924 if (reg == 0x1f)
925 return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4;
926
c558386b
HW		 927 if (tp->ocp_base != OCP_STD_PHY_BASE)
928 reg -= 0x10;
929
930 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
931}
932
eee3786f 933static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
934{
935 if (reg == 0x1f) {
936 tp->ocp_base = value << 4;
937 return;
938 }
939
940 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
941}
942
943static int mac_mcu_read(struct rtl8169_private *tp, int reg)
944{
945 return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
946}
947
ffc46952
FR		 948DECLARE_RTL_COND(rtl_phyar_cond)
949{
1ef7286e 950 return RTL_R32(tp, PHYAR) & 0x80000000;
ffc46952
FR		 951}
952
24192210 953static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
1da177e4 954{
1ef7286e 955 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
1da177e4 956
ffc46952 957 rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
024a07ba 958 /*
81a95f04
TT		 959 * According to hardware specs a 20us delay is required after write
960 * complete indication, but before sending next command.
024a07ba 961 */
81a95f04 962 udelay(20);
1da177e4
LT		 963}
964
24192210 965static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1da177e4 966{
ffc46952 967 int value;
1da177e4 968
1ef7286e 969 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
1da177e4 970
ffc46952 971 value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
9b994b4a 972 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT;
ffc46952 973
81a95f04
TT		 974 /*
975 * According to hardware specs a 20us delay is required after read
976 * complete indication, but before sending next command.
977 */
978 udelay(20);
979
1da177e4
LT		 980 return value;
981}
982
935e2218
CHL		 983DECLARE_RTL_COND(rtl_ocpar_cond)
984{
1ef7286e 985 return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
935e2218
CHL		 986}
987
24192210 988static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
c0e45c1c 989{
1ef7286e
AS		 990 RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
991 RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD);
992 RTL_W32(tp, EPHY_RXER_NUM, 0);
c0e45c1c 993
ffc46952 994 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
c0e45c1c 995}
996
24192210 997static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
c0e45c1c 998{
24192210
FR		 999 r8168dp_1_mdio_access(tp, reg,
1000 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
c0e45c1c 1001}
1002
24192210 1003static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
c0e45c1c 1004{
24192210 1005 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
c0e45c1c 1006
1007 mdelay(1);
1ef7286e
AS		 1008 RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD);
1009 RTL_W32(tp, EPHY_RXER_NUM, 0);
c0e45c1c 1010
ffc46952 1011 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
9b994b4a 1012 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : -ETIMEDOUT;
c0e45c1c 1013}
1014
e6de30d6 1015#define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
1016
1ef7286e 1017static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
e6de30d6 1018{
1ef7286e 1019 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
e6de30d6 1020}
1021
1ef7286e 1022static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
e6de30d6 1023{
1ef7286e 1024 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
e6de30d6 1025}
1026
24192210 1027static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
e6de30d6 1028{
1ef7286e 1029 r8168dp_2_mdio_start(tp);
e6de30d6 1030
24192210 1031 r8169_mdio_write(tp, reg, value);
e6de30d6 1032
1ef7286e 1033 r8168dp_2_mdio_stop(tp);
e6de30d6 1034}
1035
24192210 1036static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
e6de30d6 1037{
1038 int value;
1039
62bdc8fd
HK		 1040 /* Work around issue with chip reporting wrong PHY ID */
1041 if (reg == MII_PHYSID2)
1042 return 0xc912;
1043
1ef7286e 1044 r8168dp_2_mdio_start(tp);
e6de30d6 1045
24192210 1046 value = r8169_mdio_read(tp, reg);
e6de30d6 1047
1ef7286e 1048 r8168dp_2_mdio_stop(tp);
e6de30d6 1049
1050 return value;
1051}
1052
ce8843ab 1053static void rtl_writephy(struct rtl8169_private *tp, int location, int val)
dacf8154 1054{
5f950523
HK		 1055 switch (tp->mac_version) {
1056 case RTL_GIGA_MAC_VER_27:
1057 r8168dp_1_mdio_write(tp, location, val);
1058 break;
1059 case RTL_GIGA_MAC_VER_28:
1060 case RTL_GIGA_MAC_VER_31:
1061 r8168dp_2_mdio_write(tp, location, val);
1062 break;
f1bce4ad 1063 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_61:
5f950523
HK		 1064 r8168g_mdio_write(tp, location, val);
1065 break;
1066 default:
1067 r8169_mdio_write(tp, location, val);
1068 break;
1069 }
dacf8154
FR		 1070}
1071
4da19633 1072static int rtl_readphy(struct rtl8169_private *tp, int location)
1073{
5f950523
HK		 1074 switch (tp->mac_version) {
1075 case RTL_GIGA_MAC_VER_27:
1076 return r8168dp_1_mdio_read(tp, location);
1077 case RTL_GIGA_MAC_VER_28:
1078 case RTL_GIGA_MAC_VER_31:
1079 return r8168dp_2_mdio_read(tp, location);
f1bce4ad 1080 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_61:
5f950523
HK		 1081 return r8168g_mdio_read(tp, location);
1082 default:
1083 return r8169_mdio_read(tp, location);
1084 }
4da19633 1085}
1086
1087static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1088{
1089 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1090}
1091
76564428 1092static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
daf9df6d 1093{
1094 int val;
1095
4da19633 1096 val = rtl_readphy(tp, reg_addr);
76564428 1097 rtl_writephy(tp, reg_addr, (val & ~m) | p);
daf9df6d 1098}
1099
424f2610
HK		 1100static void r8168g_phy_param(struct phy_device *phydev, u16 parm,
1101 u16 mask, u16 val)
1102{
1103 int oldpage = phy_select_page(phydev, 0x0a43);
1104
1105 __phy_write(phydev, 0x13, parm);
1106 __phy_modify(phydev, 0x14, mask, val);
1107
1108 phy_restore_page(phydev, oldpage, 0);
1109}
1110
ffc46952
FR		 1111DECLARE_RTL_COND(rtl_ephyar_cond)
1112{
1ef7286e 1113 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
ffc46952
FR		 1114}
1115
fdf6fc06 1116static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
dacf8154 1117{
1ef7286e 1118 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
dacf8154
FR		 1119 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1120
ffc46952
FR		 1121 rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1122
1123 udelay(10);
dacf8154
FR		 1124}
1125
fdf6fc06 1126static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
dacf8154 1127{
1ef7286e 1128 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
dacf8154 1129
ffc46952 1130 return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1ef7286e 1131 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
dacf8154
FR		 1132}
1133
5cca2f8a
HK		 1134static void r8168fp_adjust_ocp_cmd(struct rtl8169_private *tp, u32 *cmd, int type)
1135{
1136 /* based on RTL8168FP_OOBMAC_BASE in vendor driver */
1137 if (tp->mac_version == RTL_GIGA_MAC_VER_52 && type == ERIAR_OOB)
1138 *cmd |= 0x7f0 << 18;
1139}
1140
935e2218
CHL		 1141DECLARE_RTL_COND(rtl_eriar_cond)
1142{
1ef7286e 1143 return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
935e2218
CHL		 1144}
1145
724c6fd0
HK		 1146static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1147 u32 val, int type)
133ac40a 1148{
5cca2f8a
HK		 1149 u32 cmd = ERIAR_WRITE_CMD | type | mask | addr;
1150
133ac40a 1151 BUG_ON((addr & 3) || (mask == 0));
1ef7286e 1152 RTL_W32(tp, ERIDR, val);
5cca2f8a
HK		 1153 r8168fp_adjust_ocp_cmd(tp, &cmd, type);
1154 RTL_W32(tp, ERIAR, cmd);
133ac40a 1155
ffc46952 1156 rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
133ac40a
HW		 1157}
1158
724c6fd0
HK		 1159static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1160 u32 val)
1161{
1162 _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC);
1163}
1164
1165static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
133ac40a 1166{
5cca2f8a
HK		 1167 u32 cmd = ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr;
1168
1169 r8168fp_adjust_ocp_cmd(tp, &cmd, type);
1170 RTL_W32(tp, ERIAR, cmd);
133ac40a 1171
ffc46952 1172 return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1ef7286e 1173 RTL_R32(tp, ERIDR) : ~0;
133ac40a
HW		 1174}
1175
724c6fd0
HK		 1176static u32 rtl_eri_read(struct rtl8169_private *tp, int addr)
1177{
1178 return _rtl_eri_read(tp, addr, ERIAR_EXGMAC);
1179}
1180
706123d0 1181static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
724c6fd0 1182 u32 m)
133ac40a
HW		 1183{
1184 u32 val;
1185
724c6fd0
HK		 1186 val = rtl_eri_read(tp, addr);
1187 rtl_eri_write(tp, addr, mask, (val & ~m) | p);
133ac40a
HW		 1188}
1189
e719b3ea
HK		 1190static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 mask,
1191 u32 p)
1192{
1193 rtl_w0w1_eri(tp, addr, mask, p, 0);
1194}
1195
1196static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 mask,
1197 u32 m)
1198{
1199 rtl_w0w1_eri(tp, addr, mask, 0, m);
1200}
1201
935e2218
CHL		 1202static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1203{
1ef7286e 1204 RTL_W32(tp, OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
935e2218 1205 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1ef7286e 1206 RTL_R32(tp, OCPDR) : ~0;
935e2218
CHL		 1207}
1208
1209static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1210{
724c6fd0 1211 return _rtl_eri_read(tp, reg, ERIAR_OOB);
935e2218
CHL		 1212}
1213
935e2218
CHL		 1214static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1215 u32 data)
1216{
1ef7286e
AS		 1217 RTL_W32(tp, OCPDR, data);
1218 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
935e2218
CHL		 1219 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1220}
1221
1222static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1223 u32 data)
1224{
724c6fd0
HK		 1225 _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1226 data, ERIAR_OOB);
935e2218
CHL		 1227}
1228
3c72bf71 1229static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd)
2a9b4d96 1230{
724c6fd0 1231 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd);
2a9b4d96 1232
3c72bf71 1233 r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001);
2a9b4d96
CHL		 1234}
1235
1236#define OOB_CMD_RESET 0x00
1237#define OOB_CMD_DRIVER_START 0x05
1238#define OOB_CMD_DRIVER_STOP 0x06
1239
1240static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1241{
1242 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1243}
1244
3c72bf71 1245DECLARE_RTL_COND(rtl_dp_ocp_read_cond)
2a9b4d96
CHL		 1246{
1247 u16 reg;
1248
1249 reg = rtl8168_get_ocp_reg(tp);
1250
3c72bf71 1251 return r8168dp_ocp_read(tp, 0x0f, reg) & 0x00000800;
2a9b4d96
CHL		 1252}
1253
935e2218 1254DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
2a9b4d96 1255{
3c72bf71 1256 return r8168ep_ocp_read(tp, 0x0f, 0x124) & 0x00000001;
935e2218
CHL		 1257}
1258
1259DECLARE_RTL_COND(rtl_ocp_tx_cond)
1260{
1ef7286e 1261 return RTL_R8(tp, IBISR0) & 0x20;
935e2218 1262}
2a9b4d96 1263
003609da
CHL		 1264static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1265{
1ef7286e 1266 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
086ca23d 1267 rtl_msleep_loop_wait_high(tp, &rtl_ocp_tx_cond, 50, 2000);
1ef7286e
AS		 1268 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1269 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
003609da
CHL		 1270}
1271
935e2218
CHL		 1272static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1273{
3c72bf71
HK		 1274 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START);
1275 rtl_msleep_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10, 10);
2a9b4d96
CHL		 1276}
1277
935e2218 1278static void rtl8168ep_driver_start(struct rtl8169_private *tp)
2a9b4d96 1279{
3c72bf71
HK		 1280 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1281 r8168ep_ocp_write(tp, 0x01, 0x30,
1282 r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01);
935e2218
CHL		 1283 rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1284}
1285
1286static void rtl8168_driver_start(struct rtl8169_private *tp)
1287{
1288 switch (tp->mac_version) {
1289 case RTL_GIGA_MAC_VER_27:
1290 case RTL_GIGA_MAC_VER_28:
1291 case RTL_GIGA_MAC_VER_31:
1292 rtl8168dp_driver_start(tp);
1293 break;
2e13d773 1294 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52:
935e2218
CHL		 1295 rtl8168ep_driver_start(tp);
1296 break;
1297 default:
1298 BUG();
1299 break;
1300 }
1301}
2a9b4d96 1302
935e2218
CHL		 1303static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1304{
3c72bf71
HK		 1305 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1306 rtl_msleep_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10, 10);
2a9b4d96
CHL		 1307}
1308
935e2218
CHL		 1309static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1310{
003609da 1311 rtl8168ep_stop_cmac(tp);
3c72bf71
HK		 1312 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1313 r8168ep_ocp_write(tp, 0x01, 0x30,
1314 r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01);
935e2218
CHL		 1315 rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1316}
1317
1318static void rtl8168_driver_stop(struct rtl8169_private *tp)
1319{
1320 switch (tp->mac_version) {
1321 case RTL_GIGA_MAC_VER_27:
1322 case RTL_GIGA_MAC_VER_28:
1323 case RTL_GIGA_MAC_VER_31:
1324 rtl8168dp_driver_stop(tp);
1325 break;
2e13d773 1326 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52:
935e2218
CHL		 1327 rtl8168ep_driver_stop(tp);
1328 break;
1329 default:
1330 BUG();
1331 break;
1332 }
1333}
1334
9dbe7896 1335static bool r8168dp_check_dash(struct rtl8169_private *tp)
2a9b4d96
CHL		 1336{
1337 u16 reg = rtl8168_get_ocp_reg(tp);
1338
3c72bf71 1339 return !!(r8168dp_ocp_read(tp, 0x0f, reg) & 0x00008000);
2a9b4d96
CHL		 1340}
1341
9dbe7896 1342static bool r8168ep_check_dash(struct rtl8169_private *tp)
935e2218 1343{
3c72bf71 1344 return !!(r8168ep_ocp_read(tp, 0x0f, 0x128) & 0x00000001);
935e2218
CHL		 1345}
1346
9dbe7896 1347static bool r8168_check_dash(struct rtl8169_private *tp)
935e2218
CHL		 1348{
1349 switch (tp->mac_version) {
1350 case RTL_GIGA_MAC_VER_27:
1351 case RTL_GIGA_MAC_VER_28:
1352 case RTL_GIGA_MAC_VER_31:
1353 return r8168dp_check_dash(tp);
2e13d773 1354 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52:
935e2218
CHL		 1355 return r8168ep_check_dash(tp);
1356 default:
9dbe7896 1357 return false;
935e2218
CHL		 1358 }
1359}
1360
4e7e4621
HK		 1361static void rtl_reset_packet_filter(struct rtl8169_private *tp)
1362{
1363 rtl_eri_clear_bits(tp, 0xdc, ERIAR_MASK_0001, BIT(0));
1364 rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_0001, BIT(0));
1365}
1366
ffc46952
FR		 1367DECLARE_RTL_COND(rtl_efusear_cond)
1368{
1ef7286e 1369 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
ffc46952
FR		 1370}
1371
fdf6fc06 1372static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
daf9df6d 1373{
1ef7286e 1374 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
daf9df6d 1375
ffc46952 1376 return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1ef7286e 1377 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
daf9df6d 1378}
1379
c1d532d2
HK		 1380static u32 rtl_get_events(struct rtl8169_private *tp)
1381{
f1bce4ad
HK		 1382 if (rtl_is_8125(tp))
1383 return RTL_R32(tp, IntrStatus_8125);
1384 else
1385 return RTL_R16(tp, IntrStatus);
c1d532d2
HK		 1386}
1387
1388static void rtl_ack_events(struct rtl8169_private *tp, u32 bits)
9085cdfa 1389{
f1bce4ad
HK		 1390 if (rtl_is_8125(tp))
1391 RTL_W32(tp, IntrStatus_8125, bits);
1392 else
1393 RTL_W16(tp, IntrStatus, bits);
9085cdfa
FR		 1394}
1395
1396static void rtl_irq_disable(struct rtl8169_private *tp)
1397{
f1bce4ad
HK		 1398 if (rtl_is_8125(tp))
1399 RTL_W32(tp, IntrMask_8125, 0);
1400 else
1401 RTL_W16(tp, IntrMask, 0);
c8248c6c 1402 tp->irq_enabled = 0;
3e990ff5
FR		 1403}
1404
da78dbff
FR		 1405#define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1406#define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1407#define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1408
fe716f8a 1409static void rtl_irq_enable(struct rtl8169_private *tp)
da78dbff 1410{
c8248c6c 1411 tp->irq_enabled = 1;
f1bce4ad
HK		 1412 if (rtl_is_8125(tp))
1413 RTL_W32(tp, IntrMask_8125, tp->irq_mask);
1414 else
1415 RTL_W16(tp, IntrMask, tp->irq_mask);
da78dbff
FR		 1416}
1417
811fd301 1418static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1da177e4 1419{
9085cdfa 1420 rtl_irq_disable(tp);
c1d532d2 1421 rtl_ack_events(tp, 0xffffffff);
de20e12f 1422 /* PCI commit */
1ef7286e 1423 RTL_R8(tp, ChipCmd);
1da177e4
LT		 1424}
1425
70090424
HW		 1426static void rtl_link_chg_patch(struct rtl8169_private *tp)
1427{
70090424 1428 struct net_device *dev = tp->dev;
703732f0 1429 struct phy_device *phydev = tp->phydev;
70090424
HW		 1430
1431 if (!netif_running(dev))
1432 return;
1433
b3d7b2f2
HW		 1434 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1435 tp->mac_version == RTL_GIGA_MAC_VER_38) {
29a12b49 1436 if (phydev->speed == SPEED_1000) {
724c6fd0
HK		 1437 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1438 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
29a12b49 1439 } else if (phydev->speed == SPEED_100) {
724c6fd0
HK		 1440 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1441 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
70090424 1442 } else {
724c6fd0
HK		 1443 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1444 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
70090424 1445 }
4e7e4621 1446 rtl_reset_packet_filter(tp);
c2218925
HW		 1447 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1448 tp->mac_version == RTL_GIGA_MAC_VER_36) {
29a12b49 1449 if (phydev->speed == SPEED_1000) {
724c6fd0
HK		 1450 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1451 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
c2218925 1452 } else {
724c6fd0
HK		 1453 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1454 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
c2218925 1455 }
7e18dca1 1456 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
29a12b49 1457 if (phydev->speed == SPEED_10) {
724c6fd0
HK		 1458 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02);
1459 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a);
7e18dca1 1460 } else {
724c6fd0 1461 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
7e18dca1 1462 }
70090424
HW		 1463 }
1464}
1465
e1759441
RW		 1466#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1467
e1759441 1468static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
61a4dcc2
FR		 1469{
1470 struct rtl8169_private *tp = netdev_priv(dev);
e1759441 1471
da78dbff 1472 rtl_lock_work(tp);
e1759441 1473 wol->supported = WAKE_ANY;
433f9d0d 1474 wol->wolopts = tp->saved_wolopts;
da78dbff 1475 rtl_unlock_work(tp);
e1759441
RW		 1476}
1477
1478static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1479{
350f7596 1480 static const struct {
61a4dcc2
FR		 1481 u32 opt;
1482 u16 reg;
1483 u8 mask;
1484 } cfg[] = {
61a4dcc2 1485 { WAKE_PHY, Config3, LinkUp },
61a4dcc2
FR		 1486 { WAKE_UCAST, Config5, UWF },
1487 { WAKE_BCAST, Config5, BWF },
1488 { WAKE_MCAST, Config5, MWF },
6e1d0b89
CHL		 1489 { WAKE_ANY, Config5, LanWake },
1490 { WAKE_MAGIC, Config3, MagicPacket }
61a4dcc2 1491 };
f1bce4ad 1492 unsigned int i, tmp = ARRAY_SIZE(cfg);
851e6022 1493 u8 options;
61a4dcc2 1494
df320ed7 1495 rtl_unlock_config_regs(tp);
61a4dcc2 1496
9e9f33ba 1497 if (rtl_is_8168evl_up(tp)) {
f1bce4ad 1498 tmp--;
6e1d0b89 1499 if (wolopts & WAKE_MAGIC)
e719b3ea
HK		 1500 rtl_eri_set_bits(tp, 0x0dc, ERIAR_MASK_0100,
1501 MagicPacket_v2);
6e1d0b89 1502 else
e719b3ea
HK		 1503 rtl_eri_clear_bits(tp, 0x0dc, ERIAR_MASK_0100,
1504 MagicPacket_v2);
f1bce4ad
HK		 1505 } else if (rtl_is_8125(tp)) {
1506 tmp--;
1507 if (wolopts & WAKE_MAGIC)
1508 r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0));
1509 else
1510 r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0);
6e1d0b89
CHL		 1511 }
1512
1513 for (i = 0; i < tmp; i++) {
1ef7286e 1514 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
e1759441 1515 if (wolopts & cfg[i].opt)
61a4dcc2 1516 options |= cfg[i].mask;
1ef7286e 1517 RTL_W8(tp, cfg[i].reg, options);
61a4dcc2
FR		 1518 }
1519
851e6022 1520 switch (tp->mac_version) {
edcde3ee 1521 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
1ef7286e 1522 options = RTL_R8(tp, Config1) & ~PMEnable;
851e6022
FR		 1523 if (wolopts)
1524 options |= PMEnable;
1ef7286e 1525 RTL_W8(tp, Config1, options);
851e6022 1526 break;
edcde3ee
HK		 1527 case RTL_GIGA_MAC_VER_34:
1528 case RTL_GIGA_MAC_VER_37:
2e13d773 1529 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_52:
1ef7286e 1530 options = RTL_R8(tp, Config2) & ~PME_SIGNAL;
d387b427
FR		 1531 if (wolopts)
1532 options |= PME_SIGNAL;
1ef7286e 1533 RTL_W8(tp, Config2, options);
851e6022 1534 break;
edcde3ee
HK		 1535 default:
1536 break;
851e6022
FR		 1537 }
1538
df320ed7 1539 rtl_lock_config_regs(tp);
3bd82645
HK		 1540
1541 device_set_wakeup_enable(tp_to_dev(tp), wolopts);
51989384 1542 tp->dev->wol_enabled = wolopts ? 1 : 0;
e1759441
RW		 1543}
1544
1545static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1546{
1547 struct rtl8169_private *tp = netdev_priv(dev);
1e1205b7 1548 struct device *d = tp_to_dev(tp);
5fa80a32 1549
2f533f6b
HK		 1550 if (wol->wolopts & ~WAKE_ANY)
1551 return -EINVAL;
1552
5fa80a32 1553 pm_runtime_get_noresume(d);
e1759441 1554
da78dbff 1555 rtl_lock_work(tp);
61a4dcc2 1556
2f533f6b 1557 tp->saved_wolopts = wol->wolopts;
433f9d0d 1558
5fa80a32 1559 if (pm_runtime_active(d))
433f9d0d 1560 __rtl8169_set_wol(tp, tp->saved_wolopts);
da78dbff
FR		 1561
1562 rtl_unlock_work(tp);
61a4dcc2 1563
5fa80a32
CHL		 1564 pm_runtime_put_noidle(d);
1565
61a4dcc2
FR		 1566 return 0;
1567}
1568
1da177e4
LT		 1569static void rtl8169_get_drvinfo(struct net_device *dev,
1570 struct ethtool_drvinfo *info)
1571{
1572 struct rtl8169_private *tp = netdev_priv(dev);
b6ffd97f 1573 struct rtl_fw *rtl_fw = tp->rtl_fw;
1da177e4 1574
68aad78c 1575 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
68aad78c 1576 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1c361efb 1577 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
254764e5 1578 if (rtl_fw)
8ac72d16
RJ		 1579 strlcpy(info->fw_version, rtl_fw->version,
1580 sizeof(info->fw_version));
1da177e4
LT		 1581}
1582
1583static int rtl8169_get_regs_len(struct net_device *dev)
1584{
1585 return R8169_REGS_SIZE;
1586}
1587
c8f44aff
MM		 1588static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1589 netdev_features_t features)
1da177e4 1590{
d58d46b5
FR		 1591 struct rtl8169_private *tp = netdev_priv(dev);
1592
2b7b4318 1593 if (dev->mtu > TD_MSS_MAX)
350fb32a 1594 features &= ~NETIF_F_ALL_TSO;
1da177e4 1595
d58d46b5 1596 if (dev->mtu > JUMBO_1K &&
6ed0e08f 1597 tp->mac_version > RTL_GIGA_MAC_VER_06)
d58d46b5
FR		 1598 features &= ~NETIF_F_IP_CSUM;
1599
350fb32a 1600 return features;
1da177e4
LT		 1601}
1602
a3984578
HK		 1603static int rtl8169_set_features(struct net_device *dev,
1604 netdev_features_t features)
1da177e4
LT		 1605{
1606 struct rtl8169_private *tp = netdev_priv(dev);
929a031d 1607 u32 rx_config;
1da177e4 1608
a3984578
HK		 1609 rtl_lock_work(tp);
1610
1ef7286e 1611 rx_config = RTL_R32(tp, RxConfig);
929a031d 1612 if (features & NETIF_F_RXALL)
1613 rx_config |= (AcceptErr | AcceptRunt);
1614 else
1615 rx_config &= ~(AcceptErr | AcceptRunt);
1da177e4 1616
f1bce4ad
HK		 1617 if (rtl_is_8125(tp)) {
1618 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1619 rx_config |= RX_VLAN_8125;
1620 else
1621 rx_config &= ~RX_VLAN_8125;
1622 }
1623
1ef7286e 1624 RTL_W32(tp, RxConfig, rx_config);
350fb32a 1625
929a031d 1626 if (features & NETIF_F_RXCSUM)
1627 tp->cp_cmd |= RxChkSum;
1628 else
1629 tp->cp_cmd &= ~RxChkSum;
6bbe021d 1630
f1bce4ad
HK		 1631 if (!rtl_is_8125(tp)) {
1632 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1633 tp->cp_cmd |= RxVlan;
1634 else
1635 tp->cp_cmd &= ~RxVlan;
1636 }
929a031d 1637
1ef7286e
AS		 1638 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1639 RTL_R16(tp, CPlusCmd);
1da177e4 1640
da78dbff 1641 rtl_unlock_work(tp);
1da177e4
LT		 1642
1643 return 0;
1644}
1645
810f4893 1646static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1da177e4 1647{
df8a39de 1648 return (skb_vlan_tag_present(skb)) ?
7424edbb 1649 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1da177e4
LT		 1650}
1651
7a8fc77b 1652static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1da177e4
LT		 1653{
1654 u32 opts2 = le32_to_cpu(desc->opts2);
1da177e4 1655
7a8fc77b 1656 if (opts2 & RxVlanTag)
7424edbb 1657 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1da177e4
LT		 1658}
1659
1da177e4
LT		 1660static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1661 void *p)
1662{
5b0384f4 1663 struct rtl8169_private *tp = netdev_priv(dev);
15edae91
PW		 1664 u32 __iomem *data = tp->mmio_addr;
1665 u32 *dw = p;
1666 int i;
1da177e4 1667
da78dbff 1668 rtl_lock_work(tp);
15edae91
PW		 1669 for (i = 0; i < R8169_REGS_SIZE; i += 4)
1670 memcpy_fromio(dw++, data++, 4);
da78dbff 1671 rtl_unlock_work(tp);
1da177e4
LT		 1672}
1673
b57b7e5a
SH		 1674static u32 rtl8169_get_msglevel(struct net_device *dev)
1675{
1676 struct rtl8169_private *tp = netdev_priv(dev);
1677
1678 return tp->msg_enable;
1679}
1680
1681static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1682{
1683 struct rtl8169_private *tp = netdev_priv(dev);
1684
1685 tp->msg_enable = value;
1686}
1687
d4a3a0fc
SH		 1688static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1689 "tx_packets",
1690 "rx_packets",
1691 "tx_errors",
1692 "rx_errors",
1693 "rx_missed",
1694 "align_errors",
1695 "tx_single_collisions",
1696 "tx_multi_collisions",
1697 "unicast",
1698 "broadcast",
1699 "multicast",
1700 "tx_aborted",
1701 "tx_underrun",
1702};
1703
b9f2c044 1704static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 1705{
b9f2c044
JG		 1706 switch (sset) {
1707 case ETH_SS_STATS:
1708 return ARRAY_SIZE(rtl8169_gstrings);
1709 default:
1710 return -EOPNOTSUPP;
1711 }
d4a3a0fc
SH		 1712}
1713
42020320 1714DECLARE_RTL_COND(rtl_counters_cond)
6e85d5ad 1715{
1ef7286e 1716 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
6e85d5ad
CV		 1717}
1718
e71c9ce2 1719static bool rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
6e85d5ad 1720{
42020320
CV		 1721 dma_addr_t paddr = tp->counters_phys_addr;
1722 u32 cmd;
6e85d5ad 1723
1ef7286e
AS		 1724 RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32);
1725 RTL_R32(tp, CounterAddrHigh);
42020320 1726 cmd = (u64)paddr & DMA_BIT_MASK(32);
1ef7286e
AS		 1727 RTL_W32(tp, CounterAddrLow, cmd);
1728 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
6e85d5ad 1729
a78e9366 1730 return rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
6e85d5ad
CV		 1731}
1732
e71c9ce2 1733static bool rtl8169_reset_counters(struct rtl8169_private *tp)
6e85d5ad 1734{
6e85d5ad
CV		 1735 /*
1736 * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
1737 * tally counters.
1738 */
1739 if (tp->mac_version < RTL_GIGA_MAC_VER_19)
1740 return true;
1741
e71c9ce2 1742 return rtl8169_do_counters(tp, CounterReset);
ffc46952
FR		 1743}
1744
e71c9ce2 1745static bool rtl8169_update_counters(struct rtl8169_private *tp)
d4a3a0fc 1746{
10262b0b
HK		 1747 u8 val = RTL_R8(tp, ChipCmd);
1748
355423d0
IV		 1749 /*
1750 * Some chips are unable to dump tally counters when the receiver
10262b0b 1751 * is disabled. If 0xff chip may be in a PCI power-save state.
355423d0 1752 */
10262b0b 1753 if (!(val & CmdRxEnb) || val == 0xff)
6e85d5ad 1754 return true;
d4a3a0fc 1755
e71c9ce2 1756 return rtl8169_do_counters(tp, CounterDump);
6e85d5ad
CV		 1757}
1758
e71c9ce2 1759static bool rtl8169_init_counter_offsets(struct rtl8169_private *tp)
6e85d5ad 1760{
42020320 1761 struct rtl8169_counters *counters = tp->counters;
6e85d5ad
CV		 1762 bool ret = false;
1763
1764 /*
1765 * rtl8169_init_counter_offsets is called from rtl_open. On chip
1766 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
1767 * reset by a power cycle, while the counter values collected by the
1768 * driver are reset at every driver unload/load cycle.
1769 *
1770 * To make sure the HW values returned by @get_stats64 match the SW
1771 * values, we collect the initial values at first open(*) and use them
1772 * as offsets to normalize the values returned by @get_stats64.
1773 *
1774 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
1775 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
1776 * set at open time by rtl_hw_start.
1777 */
1778
1779 if (tp->tc_offset.inited)
1780 return true;
1781
1782 /* If both, reset and update fail, propagate to caller. */
e71c9ce2 1783 if (rtl8169_reset_counters(tp))
6e85d5ad
CV		 1784 ret = true;
1785
e71c9ce2 1786 if (rtl8169_update_counters(tp))
6e85d5ad
CV		 1787 ret = true;
1788
42020320
CV		 1789 tp->tc_offset.tx_errors = counters->tx_errors;
1790 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1791 tp->tc_offset.tx_aborted = counters->tx_aborted;
6e85d5ad
CV		 1792 tp->tc_offset.inited = true;
1793
1794 return ret;
d4a3a0fc
SH		 1795}
1796
355423d0
IV		 1797static void rtl8169_get_ethtool_stats(struct net_device *dev,
1798 struct ethtool_stats *stats, u64 *data)
1799{
1800 struct rtl8169_private *tp = netdev_priv(dev);
1e1205b7 1801 struct device *d = tp_to_dev(tp);
42020320 1802 struct rtl8169_counters *counters = tp->counters;
355423d0
IV		 1803
1804 ASSERT_RTNL();
1805
e0636236
CHL		 1806 pm_runtime_get_noresume(d);
1807
1808 if (pm_runtime_active(d))
e71c9ce2 1809 rtl8169_update_counters(tp);
e0636236
CHL		 1810
1811 pm_runtime_put_noidle(d);
355423d0 1812
42020320
CV		 1813 data[0] = le64_to_cpu(counters->tx_packets);
1814 data[1] = le64_to_cpu(counters->rx_packets);
1815 data[2] = le64_to_cpu(counters->tx_errors);
1816 data[3] = le32_to_cpu(counters->rx_errors);
1817 data[4] = le16_to_cpu(counters->rx_missed);
1818 data[5] = le16_to_cpu(counters->align_errors);
1819 data[6] = le32_to_cpu(counters->tx_one_collision);
1820 data[7] = le32_to_cpu(counters->tx_multi_collision);
1821 data[8] = le64_to_cpu(counters->rx_unicast);
1822 data[9] = le64_to_cpu(counters->rx_broadcast);
1823 data[10] = le32_to_cpu(counters->rx_multicast);
1824 data[11] = le16_to_cpu(counters->tx_aborted);
1825 data[12] = le16_to_cpu(counters->tx_underun);
355423d0
IV		 1826}
1827
d4a3a0fc
SH		 1828static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1829{
1830 switch(stringset) {
1831 case ETH_SS_STATS:
1832 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1833 break;
1834 }
1835}
1836
50970831
FR		 1837/*
1838 * Interrupt coalescing
1839 *
1840 * > 1 - the availability of the IntrMitigate (0xe2) register through the
1841 * > 8169, 8168 and 810x line of chipsets
1842 *
1843 * 8169, 8168, and 8136(810x) serial chipsets support it.
1844 *
1845 * > 2 - the Tx timer unit at gigabit speed
1846 *
1847 * The unit of the timer depends on both the speed and the setting of CPlusCmd
1848 * (0xe0) bit 1 and bit 0.
1849 *
1850 * For 8169
1851 * bit[1:0] \ speed 1000M 100M 10M
1852 * 0 0 320ns 2.56us 40.96us
1853 * 0 1 2.56us 20.48us 327.7us
1854 * 1 0 5.12us 40.96us 655.4us
1855 * 1 1 10.24us 81.92us 1.31ms
1856 *
1857 * For the other
1858 * bit[1:0] \ speed 1000M 100M 10M
1859 * 0 0 5us 2.56us 40.96us
1860 * 0 1 40us 20.48us 327.7us
1861 * 1 0 80us 40.96us 655.4us
1862 * 1 1 160us 81.92us 1.31ms
1863 */
1864
1865/* rx/tx scale factors for one particular CPlusCmd[0:1] value */
1866struct rtl_coalesce_scale {
1867 /* Rx / Tx */
1868 u32 nsecs[2];
1869};
1870
1871/* rx/tx scale factors for all CPlusCmd[0:1] cases */
1872struct rtl_coalesce_info {
1873 u32 speed;
1874 struct rtl_coalesce_scale scalev[4]; /* each CPlusCmd[0:1] case */
1875};
1876
1877/* produce (r,t) pairs with each being in series of *1, *8, *8*2, *8*2*2 */
1878#define rxtx_x1822(r, t) { \
1879 {{(r), (t)}}, \
1880 {{(r)*8, (t)*8}}, \
1881 {{(r)*8*2, (t)*8*2}}, \
1882 {{(r)*8*2*2, (t)*8*2*2}}, \
1883}
1884static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
1885 /* speed delays: rx00 tx00 */
1886 { SPEED_10, rxtx_x1822(40960, 40960) },
1887 { SPEED_100, rxtx_x1822( 2560, 2560) },
1888 { SPEED_1000, rxtx_x1822( 320, 320) },
1889 { 0 },
1890};
1891
1892static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
1893 /* speed delays: rx00 tx00 */
1894 { SPEED_10, rxtx_x1822(40960, 40960) },
1895 { SPEED_100, rxtx_x1822( 2560, 2560) },
1896 { SPEED_1000, rxtx_x1822( 5000, 5000) },
1897 { 0 },
1898};
1899#undef rxtx_x1822
1900
1901/* get rx/tx scale vector corresponding to current speed */
1902static const struct rtl_coalesce_info *rtl_coalesce_info(struct net_device *dev)
1903{
1904 struct rtl8169_private *tp = netdev_priv(dev);
50970831 1905 const struct rtl_coalesce_info *ci;
50970831 1906
20023d3e
HK		 1907 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1908 ci = rtl_coalesce_info_8169;
1909 else
1910 ci = rtl_coalesce_info_8168_8136;
50970831 1911
20023d3e
HK		 1912 for (; ci->speed; ci++) {
1913 if (tp->phydev->speed == ci->speed)
50970831 1914 return ci;
50970831
FR		 1915 }
1916
1917 return ERR_PTR(-ELNRNG);
1918}
1919
1920static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1921{
1922 struct rtl8169_private *tp = netdev_priv(dev);
50970831
FR		 1923 const struct rtl_coalesce_info *ci;
1924 const struct rtl_coalesce_scale *scale;
1925 struct {
1926 u32 *max_frames;
1927 u32 *usecs;
1928 } coal_settings [] = {
1929 { &ec->rx_max_coalesced_frames, &ec->rx_coalesce_usecs },
1930 { &ec->tx_max_coalesced_frames, &ec->tx_coalesce_usecs }
1931 }, *p = coal_settings;
1932 int i;
1933 u16 w;
1934
f1bce4ad
HK		 1935 if (rtl_is_8125(tp))
1936 return -EOPNOTSUPP;
1937
50970831
FR		 1938 memset(ec, 0, sizeof(*ec));
1939
1940 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
1941 ci = rtl_coalesce_info(dev);
1942 if (IS_ERR(ci))
1943 return PTR_ERR(ci);
1944
0ae0974e 1945 scale = &ci->scalev[tp->cp_cmd & INTT_MASK];
50970831
FR		 1946
1947 /* read IntrMitigate and adjust according to scale */
1ef7286e 1948 for (w = RTL_R16(tp, IntrMitigate); w; w >>= RTL_COALESCE_SHIFT, p++) {
50970831
FR		 1949 *p->max_frames = (w & RTL_COALESCE_MASK) << 2;
1950 w >>= RTL_COALESCE_SHIFT;
1951 *p->usecs = w & RTL_COALESCE_MASK;
1952 }
1953
1954 for (i = 0; i < 2; i++) {
1955 p = coal_settings + i;
1956 *p->usecs = (*p->usecs * scale->nsecs[i]) / 1000;
1957
1958 /*
1959 * ethtool_coalesce says it is illegal to set both usecs and
1960 * max_frames to 0.
1961 */
1962 if (!*p->usecs && !*p->max_frames)
1963 *p->max_frames = 1;
1964 }
1965
1966 return 0;
1967}
1968
1969/* choose appropriate scale factor and CPlusCmd[0:1] for (speed, nsec) */
1970static const struct rtl_coalesce_scale *rtl_coalesce_choose_scale(
1971 struct net_device *dev, u32 nsec, u16 *cp01)
1972{
1973 const struct rtl_coalesce_info *ci;
1974 u16 i;
1975
1976 ci = rtl_coalesce_info(dev);
1977 if (IS_ERR(ci))
1978 return ERR_CAST(ci);
1979
1980 for (i = 0; i < 4; i++) {
1981 u32 rxtx_maxscale = max(ci->scalev[i].nsecs[0],
1982 ci->scalev[i].nsecs[1]);
1983 if (nsec <= rxtx_maxscale * RTL_COALESCE_T_MAX) {
1984 *cp01 = i;
1985 return &ci->scalev[i];
1986 }
1987 }
1988
1989 return ERR_PTR(-EINVAL);
1990}
1991
1992static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1993{
1994 struct rtl8169_private *tp = netdev_priv(dev);
50970831
FR		 1995 const struct rtl_coalesce_scale *scale;
1996 struct {
1997 u32 frames;
1998 u32 usecs;
1999 } coal_settings [] = {
2000 { ec->rx_max_coalesced_frames, ec->rx_coalesce_usecs },
2001 { ec->tx_max_coalesced_frames, ec->tx_coalesce_usecs }
2002 }, *p = coal_settings;
2003 u16 w = 0, cp01;
2004 int i;
2005
f1bce4ad
HK		 2006 if (rtl_is_8125(tp))
2007 return -EOPNOTSUPP;
2008
50970831
FR		 2009 scale = rtl_coalesce_choose_scale(dev,
2010 max(p[0].usecs, p[1].usecs) * 1000, &cp01);
2011 if (IS_ERR(scale))
2012 return PTR_ERR(scale);
2013
2014 for (i = 0; i < 2; i++, p++) {
2015 u32 units;
2016
2017 /*
2018 * accept max_frames=1 we returned in rtl_get_coalesce.
2019 * accept it not only when usecs=0 because of e.g. the following scenario:
2020 *
2021 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
2022 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
2023 * - then user does `ethtool -C eth0 rx-usecs 100`
2024 *
2025 * since ethtool sends to kernel whole ethtool_coalesce
2026 * settings, if we do not handle rx_usecs=!0, rx_frames=1
2027 * we'll reject it below in `frames % 4 != 0`.
2028 */
2029 if (p->frames == 1) {
2030 p->frames = 0;
2031 }
2032
2033 units = p->usecs * 1000 / scale->nsecs[i];
2034 if (p->frames > RTL_COALESCE_FRAME_MAX || p->frames % 4)
2035 return -EINVAL;
2036
2037 w <<= RTL_COALESCE_SHIFT;
2038 w |= units;
2039 w <<= RTL_COALESCE_SHIFT;
2040 w |= p->frames >> 2;
2041 }
2042
2043 rtl_lock_work(tp);
2044
1ef7286e 2045 RTL_W16(tp, IntrMitigate, swab16(w));
50970831 2046
9a3c81fa 2047 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
1ef7286e
AS		 2048 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
2049 RTL_R16(tp, CPlusCmd);
50970831
FR		 2050
2051 rtl_unlock_work(tp);
2052
2053 return 0;
2054}
2055
df6f1856
HK		 2056static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data)
2057{
2058 struct rtl8169_private *tp = netdev_priv(dev);
2059 struct device *d = tp_to_dev(tp);
2060 int ret;
2061
2e779ddb
HK		 2062 if (!rtl_supports_eee(tp))
2063 return -EOPNOTSUPP;
2064
df6f1856
HK		 2065 pm_runtime_get_noresume(d);
2066
2067 if (!pm_runtime_active(d)) {
2068 ret = -EOPNOTSUPP;
2e779ddb
HK		 2069 } else {
2070 ret = phy_ethtool_get_eee(tp->phydev, data);
df6f1856
HK		 2071 }
2072
df6f1856 2073 pm_runtime_put_noidle(d);
2e779ddb
HK		 2074
2075 return ret;
df6f1856
HK		 2076}
2077
2078static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data)
2079{
2080 struct rtl8169_private *tp = netdev_priv(dev);
2081 struct device *d = tp_to_dev(tp);
2e779ddb
HK		 2082 int ret;
2083
2084 if (!rtl_supports_eee(tp))
2085 return -EOPNOTSUPP;
df6f1856
HK		 2086
2087 pm_runtime_get_noresume(d);
2088
2e779ddb 2089 if (!pm_runtime_active(d)) {
df6f1856
HK		 2090 ret = -EOPNOTSUPP;
2091 goto out;
2092 }
2093
2094 if (dev->phydev->autoneg == AUTONEG_DISABLE ||
2095 dev->phydev->duplex != DUPLEX_FULL) {
2096 ret = -EPROTONOSUPPORT;
2097 goto out;
2098 }
2099
2e779ddb 2100 ret = phy_ethtool_set_eee(tp->phydev, data);
488202f5
HK		 2101
2102 if (!ret)
2103 tp->eee_adv = phy_read_mmd(dev->phydev, MDIO_MMD_AN,
2104 MDIO_AN_EEE_ADV);
df6f1856
HK		 2105out:
2106 pm_runtime_put_noidle(d);
2e779ddb 2107 return ret;
df6f1856
HK		 2108}
2109
7282d491 2110static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 2111 .get_drvinfo = rtl8169_get_drvinfo,
2112 .get_regs_len = rtl8169_get_regs_len,
2113 .get_link = ethtool_op_get_link,
50970831
FR		 2114 .get_coalesce = rtl_get_coalesce,
2115 .set_coalesce = rtl_set_coalesce,
b57b7e5a
SH		 2116 .get_msglevel = rtl8169_get_msglevel,
2117 .set_msglevel = rtl8169_set_msglevel,
1da177e4 2118 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 2119 .get_wol = rtl8169_get_wol,
2120 .set_wol = rtl8169_set_wol,
d4a3a0fc 2121 .get_strings = rtl8169_get_strings,
b9f2c044 2122 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 2123 .get_ethtool_stats = rtl8169_get_ethtool_stats,
e1593bb1 2124 .get_ts_info = ethtool_op_get_ts_info,
dd84957e 2125 .nway_reset = phy_ethtool_nway_reset,
df6f1856
HK		 2126 .get_eee = rtl8169_get_eee,
2127 .set_eee = rtl8169_set_eee,
45772433
HK		 2128 .get_link_ksettings = phy_ethtool_get_link_ksettings,
2129 .set_link_ksettings = phy_ethtool_set_link_ksettings,
1da177e4
LT		 2130};
2131
b6c7fa40
HK		 2132static void rtl_enable_eee(struct rtl8169_private *tp)
2133{
2e779ddb 2134 struct phy_device *phydev = tp->phydev;
488202f5
HK		 2135 int adv;
2136
2137 /* respect EEE advertisement the user may have set */
2138 if (tp->eee_adv >= 0)
2139 adv = tp->eee_adv;
2140 else
2141 adv = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
b6c7fa40 2142
488202f5
HK		 2143 if (adv >= 0)
2144 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, adv);
b6c7fa40
HK		 2145}
2146
b4cc2dcc 2147static void rtl8169_get_mac_version(struct rtl8169_private *tp)
1da177e4 2148{
0e485150
FR		 2149 /*
2150 * The driver currently handles the 8168Bf and the 8168Be identically
2151 * but they can be identified more specifically through the test below
2152 * if needed:
2153 *
1ef7286e 2154 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 2155 *
2156 * Same thing for the 8101Eb and the 8101Ec:
2157 *
1ef7286e 2158 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 2159 */
3744100e 2160 static const struct rtl_mac_info {
55d2ad7b
HK		 2161 u16 mask;
2162 u16 val;
2163 u16 mac_version;
1da177e4 2164 } mac_info[] = {
f1bce4ad
HK		 2165 /* 8125 family. */
2166 { 0x7cf, 0x608, RTL_GIGA_MAC_VER_60 },
2167 { 0x7c8, 0x608, RTL_GIGA_MAC_VER_61 },
2168
2e13d773
HK		 2169 /* RTL8117 */
2170 { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52 },
2171
935e2218 2172 /* 8168EP family. */
55d2ad7b
HK		 2173 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 },
2174 { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 },
2175 { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 },
935e2218 2176
6e1d0b89 2177 /* 8168H family. */
55d2ad7b
HK		 2178 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 },
2179 { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 },
6e1d0b89 2180
c558386b 2181 /* 8168G family. */
55d2ad7b
HK		 2182 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 },
2183 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 },
2184 { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 },
2185 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 },
c558386b 2186
c2218925 2187 /* 8168F family. */
55d2ad7b
HK		 2188 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 },
2189 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 },
2190 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 },
c2218925 2191
01dc7fec 2192 /* 8168E family. */
55d2ad7b
HK		 2193 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 },
2194 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 },
2195 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 },
01dc7fec 2196
5b538df9 2197 /* 8168D family. */
55d2ad7b
HK		 2198 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 },
2199 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 },
5b538df9 2200
e6de30d6 2201 /* 8168DP family. */
55d2ad7b
HK		 2202 { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 },
2203 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 },
2204 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 },
e6de30d6 2205
ef808d50 2206 /* 8168C family. */
55d2ad7b
HK		 2207 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 },
2208 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 },
2209 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 },
2210 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 },
2211 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 },
2212 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 },
2213 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 },
e3cf0cc0
FR		 2214
2215 /* 8168B family. */
55d2ad7b
HK		 2216 { 0x7cf, 0x380, RTL_GIGA_MAC_VER_12 },
2217 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 },
2218 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 },
e3cf0cc0
FR		 2219
2220 /* 8101 family. */
55d2ad7b
HK		 2221 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 },
2222 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 },
2223 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 },
2224 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 },
2225 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 },
2226 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 },
2227 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 },
2228 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 },
2229 { 0x7cf, 0x340, RTL_GIGA_MAC_VER_13 },
35fb2a42
HK		 2230 /* RTL8401, reportedly works if treated as RTL8101e */
2231 { 0x7cf, 0x240, RTL_GIGA_MAC_VER_13 },
55d2ad7b
HK		 2232 { 0x7cf, 0x343, RTL_GIGA_MAC_VER_10 },
2233 { 0x7cf, 0x342, RTL_GIGA_MAC_VER_16 },
2234 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 },
2235 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 },
2236 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_16 },
e3cf0cc0 2237 /* FIXME: where did these entries come from ? -- FR */
55d2ad7b
HK		 2238 { 0xfc8, 0x388, RTL_GIGA_MAC_VER_15 },
2239 { 0xfc8, 0x308, RTL_GIGA_MAC_VER_14 },
e3cf0cc0
FR		 2240
2241 /* 8110 family. */
55d2ad7b
HK		 2242 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 },
2243 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 },
2244 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 },
2245 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 },
2246 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 },
e3cf0cc0 2247
f21b75e9 2248 /* Catch-all */
55d2ad7b 2249 { 0x000, 0x000, RTL_GIGA_MAC_NONE }
3744100e
FR		 2250 };
2251 const struct rtl_mac_info *p = mac_info;
55d2ad7b 2252 u16 reg = RTL_R32(tp, TxConfig) >> 20;
1da177e4 2253
e3cf0cc0 2254 while ((reg & p->mask) != p->val)
1da177e4
LT		 2255 p++;
2256 tp->mac_version = p->mac_version;
5d320a20
FR		 2257
2258 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
b4cc2dcc 2259 dev_err(tp_to_dev(tp), "unknown chip XID %03x\n", reg & 0xfcf);
45f1996f
HK		 2260 } else if (!tp->supports_gmii) {
2261 if (tp->mac_version == RTL_GIGA_MAC_VER_42)
2262 tp->mac_version = RTL_GIGA_MAC_VER_43;
2263 else if (tp->mac_version == RTL_GIGA_MAC_VER_45)
2264 tp->mac_version = RTL_GIGA_MAC_VER_47;
2265 else if (tp->mac_version == RTL_GIGA_MAC_VER_46)
2266 tp->mac_version = RTL_GIGA_MAC_VER_48;
5d320a20 2267 }
1da177e4
LT		 2268}
2269
867763c1
FR		 2270struct phy_reg {
2271 u16 reg;
2272 u16 val;
2273};
2274
1791ad50
HK		 2275static void __rtl_writephy_batch(struct rtl8169_private *tp,
2276 const struct phy_reg *regs, int len)
867763c1
FR		 2277{
2278 while (len-- > 0) {
4da19633 2279 rtl_writephy(tp, regs->reg, regs->val);
867763c1
FR		 2280 regs++;
2281 }
2282}
2283
1791ad50
HK		 2284#define rtl_writephy_batch(tp, a) __rtl_writephy_batch(tp, a, ARRAY_SIZE(a))
2285
f1e02ed1 2286static void rtl_release_firmware(struct rtl8169_private *tp)
2287{
254764e5 2288 if (tp->rtl_fw) {
47ad5931 2289 rtl_fw_release_firmware(tp->rtl_fw);
b6ffd97f 2290 kfree(tp->rtl_fw);
254764e5 2291 tp->rtl_fw = NULL;
b6ffd97f 2292 }
f1e02ed1 2293}
2294
953a12cc 2295static void rtl_apply_firmware(struct rtl8169_private *tp)
f1e02ed1 2296{
ce8843ab 2297 /* TODO: release firmware if rtl_fw_write_firmware signals failure. */
2097f276 2298 if (tp->rtl_fw) {
ce8843ab 2299 rtl_fw_write_firmware(tp, tp->rtl_fw);
2097f276
HK		 2300 /* At least one firmware doesn't reset tp->ocp_base. */
2301 tp->ocp_base = OCP_STD_PHY_BASE;
2302 }
953a12cc
FR		 2303}
2304
2305static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2306{
2307 if (rtl_readphy(tp, reg) != val)
2308 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2309 else
2310 rtl_apply_firmware(tp);
f1e02ed1 2311}
2312
df6f1856
HK		 2313static void rtl8168_config_eee_mac(struct rtl8169_private *tp)
2314{
f452825d
HK		 2315 /* Adjust EEE LED frequency */
2316 if (tp->mac_version != RTL_GIGA_MAC_VER_38)
2317 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
2318
e719b3ea 2319 rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_1111, 0x0003);
df6f1856
HK		 2320}
2321
b3a42e3a
HK		 2322static void rtl8125_config_eee_mac(struct rtl8169_private *tp)
2323{
2324 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0));
2325 r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1));
2326}
2327
cc07d271
HK		 2328static void rtl8168f_config_eee_phy(struct rtl8169_private *tp)
2329{
2330 struct phy_device *phydev = tp->phydev;
2331
2332 phy_write(phydev, 0x1f, 0x0007);
2333 phy_write(phydev, 0x1e, 0x0020);
2334 phy_set_bits(phydev, 0x15, BIT(8));
2335
2336 phy_write(phydev, 0x1f, 0x0005);
2337 phy_write(phydev, 0x05, 0x8b85);
2338 phy_set_bits(phydev, 0x06, BIT(13));
2339
2340 phy_write(phydev, 0x1f, 0x0000);
2341}
2342
df6f1856
HK		 2343static void rtl8168g_config_eee_phy(struct rtl8169_private *tp)
2344{
a2928d28 2345 phy_modify_paged(tp->phydev, 0x0a43, 0x11, 0, BIT(4));
df6f1856
HK		 2346}
2347
b6cef26f
HK		 2348static void rtl8168h_config_eee_phy(struct rtl8169_private *tp)
2349{
2350 struct phy_device *phydev = tp->phydev;
2351
2352 rtl8168g_config_eee_phy(tp);
2353
2354 phy_modify_paged(phydev, 0xa4a, 0x11, 0x0000, 0x0200);
2355 phy_modify_paged(phydev, 0xa42, 0x14, 0x0000, 0x0080);
2356}
2357
b3a42e3a
HK		 2358static void rtl8125_config_eee_phy(struct rtl8169_private *tp)
2359{
2360 struct phy_device *phydev = tp->phydev;
2361
2362 rtl8168h_config_eee_phy(tp);
2363
2364 phy_modify_paged(phydev, 0xa6d, 0x12, 0x0001, 0x0000);
2365 phy_modify_paged(phydev, 0xa6d, 0x14, 0x0010, 0x0000);
2366}
2367
4da19633 2368static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1da177e4 2369{
350f7596 2370 static const struct phy_reg phy_reg_init[] = {
0b9b571d 2371 { 0x1f, 0x0001 },
2372 { 0x06, 0x006e },
2373 { 0x08, 0x0708 },
2374 { 0x15, 0x4000 },
2375 { 0x18, 0x65c7 },
1da177e4 2376
0b9b571d 2377 { 0x1f, 0x0001 },
2378 { 0x03, 0x00a1 },
2379 { 0x02, 0x0008 },
2380 { 0x01, 0x0120 },
2381 { 0x00, 0x1000 },
2382 { 0x04, 0x0800 },
2383 { 0x04, 0x0000 },
1da177e4 2384
0b9b571d 2385 { 0x03, 0xff41 },
2386 { 0x02, 0xdf60 },
2387 { 0x01, 0x0140 },
2388 { 0x00, 0x0077 },
2389 { 0x04, 0x7800 },
2390 { 0x04, 0x7000 },
2391
2392 { 0x03, 0x802f },
2393 { 0x02, 0x4f02 },
2394 { 0x01, 0x0409 },
2395 { 0x00, 0xf0f9 },
2396 { 0x04, 0x9800 },
2397 { 0x04, 0x9000 },
2398
2399 { 0x03, 0xdf01 },
2400 { 0x02, 0xdf20 },
2401 { 0x01, 0xff95 },
2402 { 0x00, 0xba00 },
2403 { 0x04, 0xa800 },
2404 { 0x04, 0xa000 },
2405
2406 { 0x03, 0xff41 },
2407 { 0x02, 0xdf20 },
2408 { 0x01, 0x0140 },
2409 { 0x00, 0x00bb },
2410 { 0x04, 0xb800 },
2411 { 0x04, 0xb000 },
2412
2413 { 0x03, 0xdf41 },
2414 { 0x02, 0xdc60 },
2415 { 0x01, 0x6340 },
2416 { 0x00, 0x007d },
2417 { 0x04, 0xd800 },
2418 { 0x04, 0xd000 },
2419
2420 { 0x03, 0xdf01 },
2421 { 0x02, 0xdf20 },
2422 { 0x01, 0x100a },
2423 { 0x00, 0xa0ff },
2424 { 0x04, 0xf800 },
2425 { 0x04, 0xf000 },
2426
2427 { 0x1f, 0x0000 },
2428 { 0x0b, 0x0000 },
2429 { 0x00, 0x9200 }
2430 };
1da177e4 2431
1791ad50 2432 rtl_writephy_batch(tp, phy_reg_init);
1da177e4
LT		 2433}
2434
4da19633 2435static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
5615d9f1 2436{
350f7596 2437 static const struct phy_reg phy_reg_init[] = {
a441d7b6
FR		 2438 { 0x1f, 0x0002 },
2439 { 0x01, 0x90d0 },
2440 { 0x1f, 0x0000 }
2441 };
2442
1791ad50 2443 rtl_writephy_batch(tp, phy_reg_init);
5615d9f1
FR		 2444}
2445
4da19633 2446static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2e955856 2447{
2448 struct pci_dev *pdev = tp->pci_dev;
2e955856 2449
ccbae55e
SS		 2450 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2451 (pdev->subsystem_device != 0xe000))
2e955856 2452 return;
2453
4da19633 2454 rtl_writephy(tp, 0x1f, 0x0001);
2455 rtl_writephy(tp, 0x10, 0xf01b);
2456 rtl_writephy(tp, 0x1f, 0x0000);
2e955856 2457}
2458
4da19633 2459static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2e955856 2460{
350f7596 2461 static const struct phy_reg phy_reg_init[] = {
2e955856 2462 { 0x1f, 0x0001 },
2463 { 0x04, 0x0000 },
2464 { 0x03, 0x00a1 },
2465 { 0x02, 0x0008 },
2466 { 0x01, 0x0120 },
2467 { 0x00, 0x1000 },
2468 { 0x04, 0x0800 },
2469 { 0x04, 0x9000 },
2470 { 0x03, 0x802f },
2471 { 0x02, 0x4f02 },
2472 { 0x01, 0x0409 },
2473 { 0x00, 0xf099 },
2474 { 0x04, 0x9800 },
2475 { 0x04, 0xa000 },
2476 { 0x03, 0xdf01 },
2477 { 0x02, 0xdf20 },
2478 { 0x01, 0xff95 },
2479 { 0x00, 0xba00 },
2480 { 0x04, 0xa800 },
2481 { 0x04, 0xf000 },
2482 { 0x03, 0xdf01 },
2483 { 0x02, 0xdf20 },
2484 { 0x01, 0x101a },
2485 { 0x00, 0xa0ff },
2486 { 0x04, 0xf800 },
2487 { 0x04, 0x0000 },
2488 { 0x1f, 0x0000 },
2489
2490 { 0x1f, 0x0001 },
2491 { 0x10, 0xf41b },
2492 { 0x14, 0xfb54 },
2493 { 0x18, 0xf5c7 },
2494 { 0x1f, 0x0000 },
2495
2496 { 0x1f, 0x0001 },
2497 { 0x17, 0x0cc0 },
2498 { 0x1f, 0x0000 }
2499 };
2500
1791ad50 2501 rtl_writephy_batch(tp, phy_reg_init);
2e955856 2502
4da19633 2503 rtl8169scd_hw_phy_config_quirk(tp);
2e955856 2504}
2505
4da19633 2506static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
8c7006aa 2507{
350f7596 2508 static const struct phy_reg phy_reg_init[] = {
8c7006aa 2509 { 0x1f, 0x0001 },
2510 { 0x04, 0x0000 },
2511 { 0x03, 0x00a1 },
2512 { 0x02, 0x0008 },
2513 { 0x01, 0x0120 },
2514 { 0x00, 0x1000 },
2515 { 0x04, 0x0800 },
2516 { 0x04, 0x9000 },
2517 { 0x03, 0x802f },
2518 { 0x02, 0x4f02 },
2519 { 0x01, 0x0409 },
2520 { 0x00, 0xf099 },
2521 { 0x04, 0x9800 },
2522 { 0x04, 0xa000 },
2523 { 0x03, 0xdf01 },
2524 { 0x02, 0xdf20 },
2525 { 0x01, 0xff95 },
2526 { 0x00, 0xba00 },
2527 { 0x04, 0xa800 },
2528 { 0x04, 0xf000 },
2529 { 0x03, 0xdf01 },
2530 { 0x02, 0xdf20 },
2531 { 0x01, 0x101a },
2532 { 0x00, 0xa0ff },
2533 { 0x04, 0xf800 },
2534 { 0x04, 0x0000 },
2535 { 0x1f, 0x0000 },
2536
2537 { 0x1f, 0x0001 },
2538 { 0x0b, 0x8480 },
2539 { 0x1f, 0x0000 },
2540
2541 { 0x1f, 0x0001 },
2542 { 0x18, 0x67c7 },
2543 { 0x04, 0x2000 },
2544 { 0x03, 0x002f },
2545 { 0x02, 0x4360 },
2546 { 0x01, 0x0109 },
2547 { 0x00, 0x3022 },
2548 { 0x04, 0x2800 },
2549 { 0x1f, 0x0000 },
2550
2551 { 0x1f, 0x0001 },
2552 { 0x17, 0x0cc0 },
2553 { 0x1f, 0x0000 }
2554 };
2555
1791ad50 2556 rtl_writephy_batch(tp, phy_reg_init);
8c7006aa 2557}
2558
4da19633 2559static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
236b8082 2560{
350f7596 2561 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2562 { 0x10, 0xf41b },
2563 { 0x1f, 0x0000 }
2564 };
2565
4da19633 2566 rtl_writephy(tp, 0x1f, 0x0001);
2567 rtl_patchphy(tp, 0x16, 1 << 0);
236b8082 2568
1791ad50 2569 rtl_writephy_batch(tp, phy_reg_init);
236b8082
FR		 2570}
2571
4da19633 2572static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
236b8082 2573{
350f7596 2574 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2575 { 0x1f, 0x0001 },
2576 { 0x10, 0xf41b },
2577 { 0x1f, 0x0000 }
2578 };
2579
1791ad50 2580 rtl_writephy_batch(tp, phy_reg_init);
236b8082
FR		 2581}
2582
4da19633 2583static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2584{
350f7596 2585 static const struct phy_reg phy_reg_init[] = {
867763c1
FR		 2586 { 0x1f, 0x0000 },
2587 { 0x1d, 0x0f00 },
2588 { 0x1f, 0x0002 },
2589 { 0x0c, 0x1ec8 },
2590 { 0x1f, 0x0000 }
2591 };
2592
1791ad50 2593 rtl_writephy_batch(tp, phy_reg_init);
867763c1
FR		 2594}
2595
4da19633 2596static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
ef3386f0 2597{
350f7596 2598 static const struct phy_reg phy_reg_init[] = {
ef3386f0
FR		 2599 { 0x1f, 0x0001 },
2600 { 0x1d, 0x3d98 },
2601 { 0x1f, 0x0000 }
2602 };
2603
4da19633 2604 rtl_writephy(tp, 0x1f, 0x0000);
2605 rtl_patchphy(tp, 0x14, 1 << 5);
2606 rtl_patchphy(tp, 0x0d, 1 << 5);
ef3386f0 2607
1791ad50 2608 rtl_writephy_batch(tp, phy_reg_init);
ef3386f0
FR		 2609}
2610
4da19633 2611static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2612{
350f7596 2613 static const struct phy_reg phy_reg_init[] = {
a3f80671
FR		 2614 { 0x1f, 0x0001 },
2615 { 0x12, 0x2300 },
867763c1
FR		 2616 { 0x1f, 0x0002 },
2617 { 0x00, 0x88d4 },
2618 { 0x01, 0x82b1 },
2619 { 0x03, 0x7002 },
2620 { 0x08, 0x9e30 },
2621 { 0x09, 0x01f0 },
2622 { 0x0a, 0x5500 },
2623 { 0x0c, 0x00c8 },
2624 { 0x1f, 0x0003 },
2625 { 0x12, 0xc096 },
2626 { 0x16, 0x000a },
f50d4275
FR		 2627 { 0x1f, 0x0000 },
2628 { 0x1f, 0x0000 },
2629 { 0x09, 0x2000 },
2630 { 0x09, 0x0000 }
867763c1
FR		 2631 };
2632
1791ad50 2633 rtl_writephy_batch(tp, phy_reg_init);
f50d4275 2634
4da19633 2635 rtl_patchphy(tp, 0x14, 1 << 5);
2636 rtl_patchphy(tp, 0x0d, 1 << 5);
2637 rtl_writephy(tp, 0x1f, 0x0000);
867763c1
FR		 2638}
2639
4da19633 2640static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
7da97ec9 2641{
350f7596 2642 static const struct phy_reg phy_reg_init[] = {
f50d4275 2643 { 0x1f, 0x0001 },
7da97ec9 2644 { 0x12, 0x2300 },
f50d4275
FR		 2645 { 0x03, 0x802f },
2646 { 0x02, 0x4f02 },
2647 { 0x01, 0x0409 },
2648 { 0x00, 0xf099 },
2649 { 0x04, 0x9800 },
2650 { 0x04, 0x9000 },
2651 { 0x1d, 0x3d98 },
7da97ec9
FR		 2652 { 0x1f, 0x0002 },
2653 { 0x0c, 0x7eb8 },
f50d4275
FR		 2654 { 0x06, 0x0761 },
2655 { 0x1f, 0x0003 },
2656 { 0x16, 0x0f0a },
7da97ec9
FR		 2657 { 0x1f, 0x0000 }
2658 };
2659
1791ad50 2660 rtl_writephy_batch(tp, phy_reg_init);
f50d4275 2661
4da19633 2662 rtl_patchphy(tp, 0x16, 1 << 0);
2663 rtl_patchphy(tp, 0x14, 1 << 5);
2664 rtl_patchphy(tp, 0x0d, 1 << 5);
2665 rtl_writephy(tp, 0x1f, 0x0000);
7da97ec9
FR		 2666}
2667
4da19633 2668static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
197ff761 2669{
350f7596 2670 static const struct phy_reg phy_reg_init[] = {
197ff761
FR		 2671 { 0x1f, 0x0001 },
2672 { 0x12, 0x2300 },
2673 { 0x1d, 0x3d98 },
2674 { 0x1f, 0x0002 },
2675 { 0x0c, 0x7eb8 },
2676 { 0x06, 0x5461 },
2677 { 0x1f, 0x0003 },
2678 { 0x16, 0x0f0a },
2679 { 0x1f, 0x0000 }
2680 };
2681
1791ad50 2682 rtl_writephy_batch(tp, phy_reg_init);
197ff761 2683
4da19633 2684 rtl_patchphy(tp, 0x16, 1 << 0);
2685 rtl_patchphy(tp, 0x14, 1 << 5);
2686 rtl_patchphy(tp, 0x0d, 1 << 5);
2687 rtl_writephy(tp, 0x1f, 0x0000);
197ff761
FR		 2688}
2689
4da19633 2690static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
6fb07058 2691{
4da19633 2692 rtl8168c_3_hw_phy_config(tp);
6fb07058
FR		 2693}
2694
fcb40e16
HK		 2695static const struct phy_reg rtl8168d_1_phy_reg_init_0[] = {
2696 /* Channel Estimation */
2697 { 0x1f, 0x0001 },
2698 { 0x06, 0x4064 },
2699 { 0x07, 0x2863 },
2700 { 0x08, 0x059c },
2701 { 0x09, 0x26b4 },
2702 { 0x0a, 0x6a19 },
2703 { 0x0b, 0xdcc8 },
2704 { 0x10, 0xf06d },
2705 { 0x14, 0x7f68 },
2706 { 0x18, 0x7fd9 },
2707 { 0x1c, 0xf0ff },
2708 { 0x1d, 0x3d9c },
2709 { 0x1f, 0x0003 },
2710 { 0x12, 0xf49f },
2711 { 0x13, 0x070b },
2712 { 0x1a, 0x05ad },
2713 { 0x14, 0x94c0 },
bca03d5f 2714
fcb40e16
HK		 2715 /*
2716 * Tx Error Issue
2717 * Enhance line driver power
2718 */
2719 { 0x1f, 0x0002 },
2720 { 0x06, 0x5561 },
2721 { 0x1f, 0x0005 },
2722 { 0x05, 0x8332 },
2723 { 0x06, 0x5561 },
bca03d5f 2724
fcb40e16
HK		 2725 /*
2726 * Can not link to 1Gbps with bad cable
2727 * Decrease SNR threshold form 21.07dB to 19.04dB
2728 */
2729 { 0x1f, 0x0001 },
2730 { 0x17, 0x0cc0 },
daf9df6d 2731
fcb40e16
HK		 2732 { 0x1f, 0x0000 },
2733 { 0x0d, 0xf880 }
2734};
2735
2736static const struct phy_reg rtl8168d_1_phy_reg_init_1[] = {
2737 { 0x1f, 0x0002 },
2738 { 0x05, 0x669a },
2739 { 0x1f, 0x0005 },
2740 { 0x05, 0x8330 },
2741 { 0x06, 0x669a },
2742 { 0x1f, 0x0002 }
2743};
daf9df6d 2744
fcb40e16
HK		 2745static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2746{
2747 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_0);
daf9df6d 2748
bca03d5f 2749 /*
2750 * Rx Error Issue
2751 * Fine Tune Switching regulator parameter
2752 */
4da19633 2753 rtl_writephy(tp, 0x1f, 0x0002);
76564428
CHL		 2754 rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
2755 rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
daf9df6d 2756
fdf6fc06 2757 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
daf9df6d 2758 int val;
2759
fcb40e16 2760 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_1);
daf9df6d 2761
4da19633 2762 val = rtl_readphy(tp, 0x0d);
daf9df6d 2763
2764 if ((val & 0x00ff) != 0x006c) {
350f7596 2765 static const u32 set[] = {
daf9df6d 2766 0x0065, 0x0066, 0x0067, 0x0068,
2767 0x0069, 0x006a, 0x006b, 0x006c
2768 };
2769 int i;
2770
4da19633 2771 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2772
2773 val &= 0xff00;
2774 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2775 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2776 }
2777 } else {
350f7596 2778 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2779 { 0x1f, 0x0002 },
2780 { 0x05, 0x6662 },
2781 { 0x1f, 0x0005 },
2782 { 0x05, 0x8330 },
2783 { 0x06, 0x6662 }
2784 };
2785
1791ad50 2786 rtl_writephy_batch(tp, phy_reg_init);
daf9df6d 2787 }
2788
bca03d5f 2789 /* RSET couple improve */
4da19633 2790 rtl_writephy(tp, 0x1f, 0x0002);
2791 rtl_patchphy(tp, 0x0d, 0x0300);
2792 rtl_patchphy(tp, 0x0f, 0x0010);
daf9df6d 2793
bca03d5f 2794 /* Fine tune PLL performance */
4da19633 2795 rtl_writephy(tp, 0x1f, 0x0002);
76564428
CHL		 2796 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
2797 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2798
4da19633 2799 rtl_writephy(tp, 0x1f, 0x0005);
2800 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 2801
2802 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
bca03d5f 2803
4da19633 2804 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2805}
2806
bca03d5f 2807static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2808{
fcb40e16 2809 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_0);
5b538df9 2810
fdf6fc06 2811 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
daf9df6d 2812 int val;
2813
fcb40e16 2814 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_1);
daf9df6d 2815
4da19633 2816 val = rtl_readphy(tp, 0x0d);
daf9df6d 2817 if ((val & 0x00ff) != 0x006c) {
b6bc7650 2818 static const u32 set[] = {
daf9df6d 2819 0x0065, 0x0066, 0x0067, 0x0068,
2820 0x0069, 0x006a, 0x006b, 0x006c
2821 };
2822 int i;
2823
4da19633 2824 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2825
2826 val &= 0xff00;
2827 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2828 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2829 }
2830 } else {
350f7596 2831 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2832 { 0x1f, 0x0002 },
2833 { 0x05, 0x2642 },
5b538df9 2834 { 0x1f, 0x0005 },
daf9df6d 2835 { 0x05, 0x8330 },
2836 { 0x06, 0x2642 }
5b538df9
FR		 2837 };
2838
1791ad50 2839 rtl_writephy_batch(tp, phy_reg_init);
5b538df9
FR		 2840 }
2841
bca03d5f 2842 /* Fine tune PLL performance */
4da19633 2843 rtl_writephy(tp, 0x1f, 0x0002);
76564428
CHL		 2844 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
2845 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2846
bca03d5f 2847 /* Switching regulator Slew rate */
4da19633 2848 rtl_writephy(tp, 0x1f, 0x0002);
2849 rtl_patchphy(tp, 0x0f, 0x0017);
daf9df6d 2850
4da19633 2851 rtl_writephy(tp, 0x1f, 0x0005);
2852 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 2853
2854 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
bca03d5f 2855
4da19633 2856 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2857}
2858
4da19633 2859static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2860{
350f7596 2861 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2862 { 0x1f, 0x0002 },
2863 { 0x10, 0x0008 },
2864 { 0x0d, 0x006c },
2865
2866 { 0x1f, 0x0000 },
2867 { 0x0d, 0xf880 },
2868
2869 { 0x1f, 0x0001 },
2870 { 0x17, 0x0cc0 },
2871
2872 { 0x1f, 0x0001 },
2873 { 0x0b, 0xa4d8 },
2874 { 0x09, 0x281c },
2875 { 0x07, 0x2883 },
2876 { 0x0a, 0x6b35 },
2877 { 0x1d, 0x3da4 },
2878 { 0x1c, 0xeffd },
2879 { 0x14, 0x7f52 },
2880 { 0x18, 0x7fc6 },
2881 { 0x08, 0x0601 },
2882 { 0x06, 0x4063 },
2883 { 0x10, 0xf074 },
2884 { 0x1f, 0x0003 },
2885 { 0x13, 0x0789 },
2886 { 0x12, 0xf4bd },
2887 { 0x1a, 0x04fd },
2888 { 0x14, 0x84b0 },
2889 { 0x1f, 0x0000 },
2890 { 0x00, 0x9200 },
2891
2892 { 0x1f, 0x0005 },
2893 { 0x01, 0x0340 },
2894 { 0x1f, 0x0001 },
2895 { 0x04, 0x4000 },
2896 { 0x03, 0x1d21 },
2897 { 0x02, 0x0c32 },
2898 { 0x01, 0x0200 },
2899 { 0x00, 0x5554 },
2900 { 0x04, 0x4800 },
2901 { 0x04, 0x4000 },
2902 { 0x04, 0xf000 },
2903 { 0x03, 0xdf01 },
2904 { 0x02, 0xdf20 },
2905 { 0x01, 0x101a },
2906 { 0x00, 0xa0ff },
2907 { 0x04, 0xf800 },
2908 { 0x04, 0xf000 },
2909 { 0x1f, 0x0000 },
2910
2911 { 0x1f, 0x0007 },
2912 { 0x1e, 0x0023 },
2913 { 0x16, 0x0000 },
2914 { 0x1f, 0x0000 }
2915 };
2916
1791ad50 2917 rtl_writephy_batch(tp, phy_reg_init);
5b538df9
FR		 2918}
2919
e6de30d6 2920static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2921{
2922 static const struct phy_reg phy_reg_init[] = {
2923 { 0x1f, 0x0001 },
2924 { 0x17, 0x0cc0 },
2925
2926 { 0x1f, 0x0007 },
2927 { 0x1e, 0x002d },
2928 { 0x18, 0x0040 },
2929 { 0x1f, 0x0000 }
2930 };
2931
1791ad50 2932 rtl_writephy_batch(tp, phy_reg_init);
e6de30d6 2933 rtl_patchphy(tp, 0x0d, 1 << 5);
2934}
2935
70090424 2936static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
01dc7fec 2937{
2938 static const struct phy_reg phy_reg_init[] = {
2939 /* Enable Delay cap */
2940 { 0x1f, 0x0005 },
2941 { 0x05, 0x8b80 },
2942 { 0x06, 0xc896 },
2943 { 0x1f, 0x0000 },
2944
2945 /* Channel estimation fine tune */
2946 { 0x1f, 0x0001 },
2947 { 0x0b, 0x6c20 },
2948 { 0x07, 0x2872 },
2949 { 0x1c, 0xefff },
2950 { 0x1f, 0x0003 },
2951 { 0x14, 0x6420 },
2952 { 0x1f, 0x0000 },
2953
2954 /* Update PFM & 10M TX idle timer */
2955 { 0x1f, 0x0007 },
2956 { 0x1e, 0x002f },
2957 { 0x15, 0x1919 },
2958 { 0x1f, 0x0000 },
2959
2960 { 0x1f, 0x0007 },
2961 { 0x1e, 0x00ac },
2962 { 0x18, 0x0006 },
2963 { 0x1f, 0x0000 }
2964 };
2965
15ecd039
FR		 2966 rtl_apply_firmware(tp);
2967
1791ad50 2968 rtl_writephy_batch(tp, phy_reg_init);
01dc7fec 2969
2970 /* DCO enable for 10M IDLE Power */
2971 rtl_writephy(tp, 0x1f, 0x0007);
2972 rtl_writephy(tp, 0x1e, 0x0023);
76564428 2973 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
01dc7fec 2974 rtl_writephy(tp, 0x1f, 0x0000);
2975
2976 /* For impedance matching */
2977 rtl_writephy(tp, 0x1f, 0x0002);
76564428 2978 rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
cecb5fd7 2979 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 2980
2981 /* PHY auto speed down */
2982 rtl_writephy(tp, 0x1f, 0x0007);
2983 rtl_writephy(tp, 0x1e, 0x002d);
76564428 2984 rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
01dc7fec 2985 rtl_writephy(tp, 0x1f, 0x0000);
76564428 2986 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
01dc7fec 2987
2988 rtl_writephy(tp, 0x1f, 0x0005);
2989 rtl_writephy(tp, 0x05, 0x8b86);
76564428 2990 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
01dc7fec 2991 rtl_writephy(tp, 0x1f, 0x0000);
2992
2993 rtl_writephy(tp, 0x1f, 0x0005);
2994 rtl_writephy(tp, 0x05, 0x8b85);
76564428 2995 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
01dc7fec 2996 rtl_writephy(tp, 0x1f, 0x0007);
2997 rtl_writephy(tp, 0x1e, 0x0020);
76564428 2998 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
01dc7fec 2999 rtl_writephy(tp, 0x1f, 0x0006);
3000 rtl_writephy(tp, 0x00, 0x5a00);
3001 rtl_writephy(tp, 0x1f, 0x0000);
3002 rtl_writephy(tp, 0x0d, 0x0007);
3003 rtl_writephy(tp, 0x0e, 0x003c);
3004 rtl_writephy(tp, 0x0d, 0x4007);
3005 rtl_writephy(tp, 0x0e, 0x0000);
3006 rtl_writephy(tp, 0x0d, 0x0000);
3007}
3008
9ecb9aab 3009static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3010{
3011 const u16 w[] = {
3012 addr[0] | (addr[1] << 8),
3013 addr[2] | (addr[3] << 8),
3014 addr[4] | (addr[5] << 8)
3015 };
9ecb9aab 3016
3aa4c491
HK		 3017 rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, w[0] | (w[1] << 16));
3018 rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, w[2]);
3019 rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, w[0] << 16);
3020 rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, w[1] | (w[2] << 16));
9ecb9aab 3021}
3022
70090424
HW		 3023static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3024{
3025 static const struct phy_reg phy_reg_init[] = {
3026 /* Enable Delay cap */
3027 { 0x1f, 0x0004 },
3028 { 0x1f, 0x0007 },
3029 { 0x1e, 0x00ac },
3030 { 0x18, 0x0006 },
3031 { 0x1f, 0x0002 },
3032 { 0x1f, 0x0000 },
3033 { 0x1f, 0x0000 },
3034
3035 /* Channel estimation fine tune */
3036 { 0x1f, 0x0003 },
3037 { 0x09, 0xa20f },
3038 { 0x1f, 0x0000 },
3039 { 0x1f, 0x0000 },
3040
3041 /* Green Setting */
3042 { 0x1f, 0x0005 },
3043 { 0x05, 0x8b5b },
3044 { 0x06, 0x9222 },
3045 { 0x05, 0x8b6d },
3046 { 0x06, 0x8000 },
3047 { 0x05, 0x8b76 },
3048 { 0x06, 0x8000 },
3049 { 0x1f, 0x0000 }
3050 };
3051
3052 rtl_apply_firmware(tp);
3053
1791ad50 3054 rtl_writephy_batch(tp, phy_reg_init);
70090424
HW		 3055
3056 /* For 4-corner performance improve */
3057 rtl_writephy(tp, 0x1f, 0x0005);
3058 rtl_writephy(tp, 0x05, 0x8b80);
76564428 3059 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
70090424
HW		 3060 rtl_writephy(tp, 0x1f, 0x0000);
3061
3062 /* PHY auto speed down */
3063 rtl_writephy(tp, 0x1f, 0x0004);
3064 rtl_writephy(tp, 0x1f, 0x0007);
3065 rtl_writephy(tp, 0x1e, 0x002d);
76564428 3066 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
70090424
HW		 3067 rtl_writephy(tp, 0x1f, 0x0002);
3068 rtl_writephy(tp, 0x1f, 0x0000);
76564428 3069 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
70090424
HW		 3070
3071 /* improve 10M EEE waveform */
3072 rtl_writephy(tp, 0x1f, 0x0005);
3073 rtl_writephy(tp, 0x05, 0x8b86);
76564428 3074 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
70090424
HW		 3075 rtl_writephy(tp, 0x1f, 0x0000);
3076
3077 /* Improve 2-pair detection performance */
3078 rtl_writephy(tp, 0x1f, 0x0005);
3079 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3080 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
70090424
HW		 3081 rtl_writephy(tp, 0x1f, 0x0000);
3082
cc07d271 3083 rtl8168f_config_eee_phy(tp);
1563daa3 3084 rtl_enable_eee(tp);
70090424
HW		 3085
3086 /* Green feature */
3087 rtl_writephy(tp, 0x1f, 0x0003);
1814d6a8
HK		 3088 rtl_w0w1_phy(tp, 0x19, 0x0001, 0x0000);
3089 rtl_w0w1_phy(tp, 0x10, 0x0400, 0x0000);
70090424 3090 rtl_writephy(tp, 0x1f, 0x0000);
b399a394
HK		 3091 rtl_writephy(tp, 0x1f, 0x0005);
3092 rtl_w0w1_phy(tp, 0x01, 0x0100, 0x0000);
3093 rtl_writephy(tp, 0x1f, 0x0000);
e0c07557 3094
9ecb9aab 3095 /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3096 rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
70090424
HW		 3097}
3098
5f886e08
HW		 3099static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3100{
3101 /* For 4-corner performance improve */
3102 rtl_writephy(tp, 0x1f, 0x0005);
3103 rtl_writephy(tp, 0x05, 0x8b80);
76564428 3104 rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
5f886e08
HW		 3105 rtl_writephy(tp, 0x1f, 0x0000);
3106
3107 /* PHY auto speed down */
3108 rtl_writephy(tp, 0x1f, 0x0007);
3109 rtl_writephy(tp, 0x1e, 0x002d);
76564428 3110 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
5f886e08 3111 rtl_writephy(tp, 0x1f, 0x0000);
76564428 3112 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
5f886e08
HW		 3113
3114 /* Improve 10M EEE waveform */
3115 rtl_writephy(tp, 0x1f, 0x0005);
3116 rtl_writephy(tp, 0x05, 0x8b86);
76564428 3117 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
5f886e08 3118 rtl_writephy(tp, 0x1f, 0x0000);
cc07d271
HK		 3119
3120 rtl8168f_config_eee_phy(tp);
1563daa3 3121 rtl_enable_eee(tp);
5f886e08
HW		 3122}
3123
c2218925
HW		 3124static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3125{
3126 static const struct phy_reg phy_reg_init[] = {
3127 /* Channel estimation fine tune */
3128 { 0x1f, 0x0003 },
3129 { 0x09, 0xa20f },
3130 { 0x1f, 0x0000 },
3131
3132 /* Modify green table for giga & fnet */
3133 { 0x1f, 0x0005 },
3134 { 0x05, 0x8b55 },
3135 { 0x06, 0x0000 },
3136 { 0x05, 0x8b5e },
3137 { 0x06, 0x0000 },
3138 { 0x05, 0x8b67 },
3139 { 0x06, 0x0000 },
3140 { 0x05, 0x8b70 },
3141 { 0x06, 0x0000 },
3142 { 0x1f, 0x0000 },
3143 { 0x1f, 0x0007 },
3144 { 0x1e, 0x0078 },
3145 { 0x17, 0x0000 },
3146 { 0x19, 0x00fb },
3147 { 0x1f, 0x0000 },
3148
3149 /* Modify green table for 10M */
3150 { 0x1f, 0x0005 },
3151 { 0x05, 0x8b79 },
3152 { 0x06, 0xaa00 },
3153 { 0x1f, 0x0000 },
3154
3155 /* Disable hiimpedance detection (RTCT) */
3156 { 0x1f, 0x0003 },
3157 { 0x01, 0x328a },
3158 { 0x1f, 0x0000 }
3159 };
3160
3161 rtl_apply_firmware(tp);
3162
1791ad50 3163 rtl_writephy_batch(tp, phy_reg_init);
c2218925 3164
5f886e08 3165 rtl8168f_hw_phy_config(tp);
c2218925
HW		 3166
3167 /* Improve 2-pair detection performance */
3168 rtl_writephy(tp, 0x1f, 0x0005);
3169 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3170 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
c2218925
HW		 3171 rtl_writephy(tp, 0x1f, 0x0000);
3172}
3173
3174static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3175{
3176 rtl_apply_firmware(tp);
3177
5f886e08 3178 rtl8168f_hw_phy_config(tp);
c2218925
HW		 3179}
3180
b3d7b2f2
HW		 3181static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3182{
b3d7b2f2
HW		 3183 static const struct phy_reg phy_reg_init[] = {
3184 /* Channel estimation fine tune */
3185 { 0x1f, 0x0003 },
3186 { 0x09, 0xa20f },
3187 { 0x1f, 0x0000 },
3188
3189 /* Modify green table for giga & fnet */
3190 { 0x1f, 0x0005 },
3191 { 0x05, 0x8b55 },
3192 { 0x06, 0x0000 },
3193 { 0x05, 0x8b5e },
3194 { 0x06, 0x0000 },
3195 { 0x05, 0x8b67 },
3196 { 0x06, 0x0000 },
3197 { 0x05, 0x8b70 },
3198 { 0x06, 0x0000 },
3199 { 0x1f, 0x0000 },
3200 { 0x1f, 0x0007 },
3201 { 0x1e, 0x0078 },
3202 { 0x17, 0x0000 },
3203 { 0x19, 0x00aa },
3204 { 0x1f, 0x0000 },
3205
3206 /* Modify green table for 10M */
3207 { 0x1f, 0x0005 },
3208 { 0x05, 0x8b79 },
3209 { 0x06, 0xaa00 },
3210 { 0x1f, 0x0000 },
3211
3212 /* Disable hiimpedance detection (RTCT) */
3213 { 0x1f, 0x0003 },
3214 { 0x01, 0x328a },
3215 { 0x1f, 0x0000 }
3216 };
3217
3218
3219 rtl_apply_firmware(tp);
3220
3221 rtl8168f_hw_phy_config(tp);
3222
3223 /* Improve 2-pair detection performance */
3224 rtl_writephy(tp, 0x1f, 0x0005);
3225 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3226 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
b3d7b2f2
HW		 3227 rtl_writephy(tp, 0x1f, 0x0000);
3228
1791ad50 3229 rtl_writephy_batch(tp, phy_reg_init);
b3d7b2f2
HW		 3230
3231 /* Modify green table for giga */
3232 rtl_writephy(tp, 0x1f, 0x0005);
3233 rtl_writephy(tp, 0x05, 0x8b54);
76564428 3234 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
b3d7b2f2 3235 rtl_writephy(tp, 0x05, 0x8b5d);
76564428 3236 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
b3d7b2f2 3237 rtl_writephy(tp, 0x05, 0x8a7c);
76564428 3238 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
b3d7b2f2 3239 rtl_writephy(tp, 0x05, 0x8a7f);
76564428 3240 rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
b3d7b2f2 3241 rtl_writephy(tp, 0x05, 0x8a82);
76564428 3242 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
b3d7b2f2 3243 rtl_writephy(tp, 0x05, 0x8a85);
76564428 3244 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
b3d7b2f2 3245 rtl_writephy(tp, 0x05, 0x8a88);
76564428 3246 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
b3d7b2f2
HW		 3247 rtl_writephy(tp, 0x1f, 0x0000);
3248
3249 /* uc same-seed solution */
3250 rtl_writephy(tp, 0x1f, 0x0005);
3251 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3252 rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
b3d7b2f2
HW		 3253 rtl_writephy(tp, 0x1f, 0x0000);
3254
b3d7b2f2
HW		 3255 /* Green feature */
3256 rtl_writephy(tp, 0x1f, 0x0003);
76564428
CHL		 3257 rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3258 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
b3d7b2f2
HW		 3259 rtl_writephy(tp, 0x1f, 0x0000);
3260}
3261
c46863ab
HK		 3262static void rtl8168g_disable_aldps(struct rtl8169_private *tp)
3263{
a2928d28 3264 phy_modify_paged(tp->phydev, 0x0a43, 0x10, BIT(2), 0);
c46863ab
HK		 3265}
3266
a1ead2ec
HK		 3267static void rtl8168g_phy_adjust_10m_aldps(struct rtl8169_private *tp)
3268{
3269 struct phy_device *phydev = tp->phydev;
3270
a2928d28
HK		 3271 phy_modify_paged(phydev, 0x0bcc, 0x14, BIT(8), 0);
3272 phy_modify_paged(phydev, 0x0a44, 0x11, 0, BIT(7) | BIT(6));
424f2610
HK		 3273 r8168g_phy_param(phydev, 0x8084, 0x6000, 0x0000);
3274 phy_modify_paged(phydev, 0x0a43, 0x10, 0x0000, 0x1003);
a1ead2ec
HK		 3275}
3276
c558386b
HW		 3277static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3278{
a2928d28
HK		 3279 int ret;
3280
c558386b
HW		 3281 rtl_apply_firmware(tp);
3282
a2928d28
HK		 3283 ret = phy_read_paged(tp->phydev, 0x0a46, 0x10);
3284 if (ret & BIT(8))
3285 phy_modify_paged(tp->phydev, 0x0bcc, 0x12, BIT(15), 0);
3286 else
3287 phy_modify_paged(tp->phydev, 0x0bcc, 0x12, 0, BIT(15));
c558386b 3288
a2928d28
HK		 3289 ret = phy_read_paged(tp->phydev, 0x0a46, 0x13);
3290 if (ret & BIT(8))
1a03bb53 3291 phy_modify_paged(tp->phydev, 0x0c41, 0x15, 0, BIT(1));
a2928d28 3292 else
1a03bb53 3293 phy_modify_paged(tp->phydev, 0x0c41, 0x15, BIT(1), 0);
c558386b 3294
41f44d13 3295 /* Enable PHY auto speed down */
a2928d28 3296 phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(3) | BIT(2));
c558386b 3297
a1ead2ec 3298 rtl8168g_phy_adjust_10m_aldps(tp);
fe7524c0 3299
41f44d13 3300 /* EEE auto-fallback function */
a2928d28 3301 phy_modify_paged(tp->phydev, 0x0a4b, 0x11, 0, BIT(2));
c558386b 3302
41f44d13 3303 /* Enable UC LPF tune function */
424f2610 3304 r8168g_phy_param(tp->phydev, 0x8012, 0x0000, 0x8000);
41f44d13 3305
a2928d28 3306 phy_modify_paged(tp->phydev, 0x0c42, 0x11, BIT(13), BIT(14));
41f44d13 3307
fe7524c0 3308 /* Improve SWR Efficiency */
3309 rtl_writephy(tp, 0x1f, 0x0bcd);
3310 rtl_writephy(tp, 0x14, 0x5065);
3311 rtl_writephy(tp, 0x14, 0xd065);
3312 rtl_writephy(tp, 0x1f, 0x0bc8);
3313 rtl_writephy(tp, 0x11, 0x5655);
3314 rtl_writephy(tp, 0x1f, 0x0bcd);
3315 rtl_writephy(tp, 0x14, 0x1065);
3316 rtl_writephy(tp, 0x14, 0x9065);
3317 rtl_writephy(tp, 0x14, 0x1065);
a2928d28 3318 rtl_writephy(tp, 0x1f, 0x0000);
fe7524c0 3319
c46863ab 3320 rtl8168g_disable_aldps(tp);
df6f1856 3321 rtl8168g_config_eee_phy(tp);
b6c7fa40 3322 rtl_enable_eee(tp);
c558386b
HW		 3323}
3324
57538c4a 3325static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3326{
3327 rtl_apply_firmware(tp);
df6f1856 3328 rtl8168g_config_eee_phy(tp);
b6c7fa40 3329 rtl_enable_eee(tp);
57538c4a 3330}
3331
6e1d0b89
CHL		 3332static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3333{
424f2610 3334 struct phy_device *phydev = tp->phydev;
6e1d0b89
CHL		 3335 u16 dout_tapbin;
3336 u32 data;
3337
3338 rtl_apply_firmware(tp);
3339
3340 /* CHN EST parameters adjust - giga master */
424f2610
HK		 3341 r8168g_phy_param(phydev, 0x809b, 0xf800, 0x8000);
3342 r8168g_phy_param(phydev, 0x80a2, 0xff00, 0x8000);
3343 r8168g_phy_param(phydev, 0x80a4, 0xff00, 0x8500);
3344 r8168g_phy_param(phydev, 0x809c, 0xff00, 0xbd00);
6e1d0b89
CHL		 3345
3346 /* CHN EST parameters adjust - giga slave */
424f2610
HK		 3347 r8168g_phy_param(phydev, 0x80ad, 0xf800, 0x7000);
3348 r8168g_phy_param(phydev, 0x80b4, 0xff00, 0x5000);
3349 r8168g_phy_param(phydev, 0x80ac, 0xff00, 0x4000);
6e1d0b89
CHL		 3350
3351 /* CHN EST parameters adjust - fnet */
424f2610
HK		 3352 r8168g_phy_param(phydev, 0x808e, 0xff00, 0x1200);
3353 r8168g_phy_param(phydev, 0x8090, 0xff00, 0xe500);
3354 r8168g_phy_param(phydev, 0x8092, 0xff00, 0x9f00);
6e1d0b89
CHL		 3355
3356 /* enable R-tune & PGA-retune function */
3357 dout_tapbin = 0;
424f2610 3358 data = phy_read_paged(phydev, 0x0a46, 0x13);
6e1d0b89
CHL		 3359 data &= 3;
3360 data <<= 2;
3361 dout_tapbin |= data;
424f2610 3362 data = phy_read_paged(phydev, 0x0a46, 0x12);
6e1d0b89
CHL		 3363 data &= 0xc000;
3364 data >>= 14;
3365 dout_tapbin |= data;
3366 dout_tapbin = ~(dout_tapbin^0x08);
3367 dout_tapbin <<= 12;
3368 dout_tapbin &= 0xf000;
424f2610
HK		 3369
3370 r8168g_phy_param(phydev, 0x827a, 0xf000, dout_tapbin);
3371 r8168g_phy_param(phydev, 0x827b, 0xf000, dout_tapbin);
3372 r8168g_phy_param(phydev, 0x827c, 0xf000, dout_tapbin);
3373 r8168g_phy_param(phydev, 0x827d, 0xf000, dout_tapbin);
3374 r8168g_phy_param(phydev, 0x0811, 0x0000, 0x0800);
3375 phy_modify_paged(phydev, 0x0a42, 0x16, 0x0000, 0x0002);
6e1d0b89
CHL		 3376
3377 /* enable GPHY 10M */
a2928d28 3378 phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(11));
6e1d0b89
CHL		 3379
3380 /* SAR ADC performance */
a2928d28 3381 phy_modify_paged(tp->phydev, 0x0bca, 0x17, BIT(12) | BIT(13), BIT(14));
6e1d0b89 3382
424f2610
HK		 3383 r8168g_phy_param(phydev, 0x803f, 0x3000, 0x0000);
3384 r8168g_phy_param(phydev, 0x8047, 0x3000, 0x0000);
3385 r8168g_phy_param(phydev, 0x804f, 0x3000, 0x0000);
3386 r8168g_phy_param(phydev, 0x8057, 0x3000, 0x0000);
3387 r8168g_phy_param(phydev, 0x805f, 0x3000, 0x0000);
3388 r8168g_phy_param(phydev, 0x8067, 0x3000, 0x0000);
3389 r8168g_phy_param(phydev, 0x806f, 0x3000, 0x0000);
6e1d0b89
CHL		 3390
3391 /* disable phy pfm mode */
a2928d28 3392 phy_modify_paged(tp->phydev, 0x0a44, 0x11, BIT(7), 0);
6e1d0b89 3393
c46863ab 3394 rtl8168g_disable_aldps(tp);
b6cef26f 3395 rtl8168h_config_eee_phy(tp);
b6c7fa40 3396 rtl_enable_eee(tp);
6e1d0b89
CHL		 3397}
3398
3399static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
3400{
3401 u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
424f2610 3402 struct phy_device *phydev = tp->phydev;
6e1d0b89
CHL		 3403 u16 rlen;
3404 u32 data;
3405
3406 rtl_apply_firmware(tp);
3407
3408 /* CHIN EST parameter update */
424f2610 3409 r8168g_phy_param(phydev, 0x808a, 0x003f, 0x000a);
6e1d0b89
CHL		 3410
3411 /* enable R-tune & PGA-retune function */
424f2610
HK		 3412 r8168g_phy_param(phydev, 0x0811, 0x0000, 0x0800);
3413 phy_modify_paged(phydev, 0x0a42, 0x16, 0x0000, 0x0002);
6e1d0b89
CHL		 3414
3415 /* enable GPHY 10M */
a2928d28 3416 phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(11));
6e1d0b89
CHL		 3417
3418 r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
3419 data = r8168_mac_ocp_read(tp, 0xdd02);
3420 ioffset_p3 = ((data & 0x80)>>7);
3421 ioffset_p3 <<= 3;
3422
3423 data = r8168_mac_ocp_read(tp, 0xdd00);
3424 ioffset_p3 |= ((data & (0xe000))>>13);
3425 ioffset_p2 = ((data & (0x1e00))>>9);
3426 ioffset_p1 = ((data & (0x01e0))>>5);
3427 ioffset_p0 = ((data & 0x0010)>>4);
3428 ioffset_p0 <<= 3;
3429 ioffset_p0 |= (data & (0x07));
3430 data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
3431
05b9687b 3432 if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
424f2610
HK		 3433 (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f))
3434 phy_write_paged(phydev, 0x0bcf, 0x16, data);
6e1d0b89
CHL		 3435
3436 /* Modify rlen (TX LPF corner frequency) level */
424f2610 3437 data = phy_read_paged(phydev, 0x0bcd, 0x16);
6e1d0b89
CHL		 3438 data &= 0x000f;
3439 rlen = 0;
3440 if (data > 3)
3441 rlen = data - 3;
3442 data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
424f2610 3443 phy_write_paged(phydev, 0x0bcd, 0x17, data);
6e1d0b89
CHL		 3444
3445 /* disable phy pfm mode */
424f2610 3446 phy_modify_paged(phydev, 0x0a44, 0x11, BIT(7), 0);
6e1d0b89 3447
c46863ab 3448 rtl8168g_disable_aldps(tp);
df6f1856 3449 rtl8168g_config_eee_phy(tp);
b6c7fa40 3450 rtl_enable_eee(tp);
6e1d0b89
CHL		 3451}
3452
935e2218
CHL		 3453static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
3454{
424f2610
HK		 3455 struct phy_device *phydev = tp->phydev;
3456
935e2218 3457 /* Enable PHY auto speed down */
424f2610 3458 phy_modify_paged(phydev, 0x0a44, 0x11, 0, BIT(3) | BIT(2));
935e2218 3459
a1ead2ec 3460 rtl8168g_phy_adjust_10m_aldps(tp);
935e2218
CHL		 3461
3462 /* Enable EEE auto-fallback function */
424f2610 3463 phy_modify_paged(phydev, 0x0a4b, 0x11, 0, BIT(2));
935e2218
CHL		 3464
3465 /* Enable UC LPF tune function */
424f2610 3466 r8168g_phy_param(phydev, 0x8012, 0x0000, 0x8000);
935e2218
CHL		 3467
3468 /* set rg_sel_sdm_rate */
424f2610 3469 phy_modify_paged(phydev, 0x0c42, 0x11, BIT(13), BIT(14));
935e2218 3470
c46863ab 3471 rtl8168g_disable_aldps(tp);
df6f1856 3472 rtl8168g_config_eee_phy(tp);
b6c7fa40 3473 rtl_enable_eee(tp);
935e2218
CHL		 3474}
3475
3476static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
3477{
424f2610
HK		 3478 struct phy_device *phydev = tp->phydev;
3479
a1ead2ec 3480 rtl8168g_phy_adjust_10m_aldps(tp);
935e2218
CHL		 3481
3482 /* Enable UC LPF tune function */
424f2610 3483 r8168g_phy_param(phydev, 0x8012, 0x0000, 0x8000);
935e2218
CHL		 3484
3485 /* Set rg_sel_sdm_rate */
a2928d28 3486 phy_modify_paged(tp->phydev, 0x0c42, 0x11, BIT(13), BIT(14));
935e2218
CHL		 3487
3488 /* Channel estimation parameters */
424f2610
HK		 3489 r8168g_phy_param(phydev, 0x80f3, 0xff00, 0x8b00);
3490 r8168g_phy_param(phydev, 0x80f0, 0xff00, 0x3a00);
3491 r8168g_phy_param(phydev, 0x80ef, 0xff00, 0x0500);
3492 r8168g_phy_param(phydev, 0x80f6, 0xff00, 0x6e00);
3493 r8168g_phy_param(phydev, 0x80ec, 0xff00, 0x6800);
3494 r8168g_phy_param(phydev, 0x80ed, 0xff00, 0x7c00);
3495 r8168g_phy_param(phydev, 0x80f2, 0xff00, 0xf400);
3496 r8168g_phy_param(phydev, 0x80f4, 0xff00, 0x8500);
3497 r8168g_phy_param(phydev, 0x8110, 0xff00, 0xa800);
3498 r8168g_phy_param(phydev, 0x810f, 0xff00, 0x1d00);
3499 r8168g_phy_param(phydev, 0x8111, 0xff00, 0xf500);
3500 r8168g_phy_param(phydev, 0x8113, 0xff00, 0x6100);
3501 r8168g_phy_param(phydev, 0x8115, 0xff00, 0x9200);
3502 r8168g_phy_param(phydev, 0x810e, 0xff00, 0x0400);
3503 r8168g_phy_param(phydev, 0x810c, 0xff00, 0x7c00);
3504 r8168g_phy_param(phydev, 0x810b, 0xff00, 0x5a00);
3505 r8168g_phy_param(phydev, 0x80d1, 0xff00, 0xff00);
3506 r8168g_phy_param(phydev, 0x80cd, 0xff00, 0x9e00);
3507 r8168g_phy_param(phydev, 0x80d3, 0xff00, 0x0e00);
3508 r8168g_phy_param(phydev, 0x80d5, 0xff00, 0xca00);
3509 r8168g_phy_param(phydev, 0x80d7, 0xff00, 0x8400);
935e2218
CHL		 3510
3511 /* Force PWM-mode */
3512 rtl_writephy(tp, 0x1f, 0x0bcd);
3513 rtl_writephy(tp, 0x14, 0x5065);
3514 rtl_writephy(tp, 0x14, 0xd065);
3515 rtl_writephy(tp, 0x1f, 0x0bc8);
3516 rtl_writephy(tp, 0x12, 0x00ed);
3517 rtl_writephy(tp, 0x1f, 0x0bcd);
3518 rtl_writephy(tp, 0x14, 0x1065);
3519 rtl_writephy(tp, 0x14, 0x9065);
3520 rtl_writephy(tp, 0x14, 0x1065);
3521 rtl_writephy(tp, 0x1f, 0x0000);
3522
c46863ab 3523 rtl8168g_disable_aldps(tp);
df6f1856 3524 rtl8168g_config_eee_phy(tp);
b6c7fa40 3525 rtl_enable_eee(tp);
935e2218
CHL		 3526}
3527
2e13d773
HK		 3528static void rtl8117_hw_phy_config(struct rtl8169_private *tp)
3529{
3530 struct phy_device *phydev = tp->phydev;
3531
3532 /* CHN EST parameters adjust - fnet */
3533 r8168g_phy_param(phydev, 0x808e, 0xff00, 0x4800);
3534 r8168g_phy_param(phydev, 0x8090, 0xff00, 0xcc00);
3535 r8168g_phy_param(phydev, 0x8092, 0xff00, 0xb000);
3536
3537 r8168g_phy_param(phydev, 0x8088, 0xff00, 0x6000);
3538 r8168g_phy_param(phydev, 0x808b, 0x3f00, 0x0b00);
3539 r8168g_phy_param(phydev, 0x808d, 0x1f00, 0x0600);
3540 r8168g_phy_param(phydev, 0x808c, 0xff00, 0xb000);
3541 r8168g_phy_param(phydev, 0x80a0, 0xff00, 0x2800);
3542 r8168g_phy_param(phydev, 0x80a2, 0xff00, 0x5000);
3543 r8168g_phy_param(phydev, 0x809b, 0xf800, 0xb000);
3544 r8168g_phy_param(phydev, 0x809a, 0xff00, 0x4b00);
3545 r8168g_phy_param(phydev, 0x809d, 0x3f00, 0x0800);
3546 r8168g_phy_param(phydev, 0x80a1, 0xff00, 0x7000);
3547 r8168g_phy_param(phydev, 0x809f, 0x1f00, 0x0300);
3548 r8168g_phy_param(phydev, 0x809e, 0xff00, 0x8800);
3549 r8168g_phy_param(phydev, 0x80b2, 0xff00, 0x2200);
3550 r8168g_phy_param(phydev, 0x80ad, 0xf800, 0x9800);
3551 r8168g_phy_param(phydev, 0x80af, 0x3f00, 0x0800);
3552 r8168g_phy_param(phydev, 0x80b3, 0xff00, 0x6f00);
3553 r8168g_phy_param(phydev, 0x80b1, 0x1f00, 0x0300);
3554 r8168g_phy_param(phydev, 0x80b0, 0xff00, 0x9300);
3555
3556 r8168g_phy_param(phydev, 0x8011, 0x0000, 0x0800);
3557
3558 /* enable GPHY 10M */
3559 phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(11));
3560
3561 r8168g_phy_param(phydev, 0x8016, 0x0000, 0x0400);
3562
3563 rtl8168g_disable_aldps(tp);
3564 rtl8168h_config_eee_phy(tp);
3565 rtl_enable_eee(tp);
3566}
3567
4da19633 3568static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2857ffb7 3569{
350f7596 3570 static const struct phy_reg phy_reg_init[] = {
2857ffb7
FR		 3571 { 0x1f, 0x0003 },
3572 { 0x08, 0x441d },
3573 { 0x01, 0x9100 },
3574 { 0x1f, 0x0000 }
3575 };
3576
4da19633 3577 rtl_writephy(tp, 0x1f, 0x0000);
3578 rtl_patchphy(tp, 0x11, 1 << 12);
3579 rtl_patchphy(tp, 0x19, 1 << 13);
3580 rtl_patchphy(tp, 0x10, 1 << 15);
2857ffb7 3581
1791ad50 3582 rtl_writephy_batch(tp, phy_reg_init);
2857ffb7
FR		 3583}
3584
5a5e4443
HW		 3585static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3586{
3587 static const struct phy_reg phy_reg_init[] = {
3588 { 0x1f, 0x0005 },
3589 { 0x1a, 0x0000 },
3590 { 0x1f, 0x0000 },
3591
3592 { 0x1f, 0x0004 },
3593 { 0x1c, 0x0000 },
3594 { 0x1f, 0x0000 },
3595
3596 { 0x1f, 0x0001 },
3597 { 0x15, 0x7701 },
3598 { 0x1f, 0x0000 }
3599 };
3600
3601 /* Disable ALDPS before ram code */
eef63cc1
FR		 3602 rtl_writephy(tp, 0x1f, 0x0000);
3603 rtl_writephy(tp, 0x18, 0x0310);
3604 msleep(100);
5a5e4443 3605
953a12cc 3606 rtl_apply_firmware(tp);
5a5e4443 3607
1791ad50 3608 rtl_writephy_batch(tp, phy_reg_init);
5a5e4443
HW		 3609}
3610
7e18dca1
HW		 3611static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
3612{
7e18dca1 3613 /* Disable ALDPS before setting firmware */
eef63cc1
FR		 3614 rtl_writephy(tp, 0x1f, 0x0000);
3615 rtl_writephy(tp, 0x18, 0x0310);
3616 msleep(20);
7e18dca1
HW		 3617
3618 rtl_apply_firmware(tp);
3619
3620 /* EEE setting */
724c6fd0 3621 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
7e18dca1
HW		 3622 rtl_writephy(tp, 0x1f, 0x0004);
3623 rtl_writephy(tp, 0x10, 0x401f);
3624 rtl_writephy(tp, 0x19, 0x7030);
3625 rtl_writephy(tp, 0x1f, 0x0000);
3626}
3627
5598bfe5
HW		 3628static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
3629{
5598bfe5
HW		 3630 static const struct phy_reg phy_reg_init[] = {
3631 { 0x1f, 0x0004 },
3632 { 0x10, 0xc07f },
3633 { 0x19, 0x7030 },
3634 { 0x1f, 0x0000 }
3635 };
3636
3637 /* Disable ALDPS before ram code */
eef63cc1
FR		 3638 rtl_writephy(tp, 0x1f, 0x0000);
3639 rtl_writephy(tp, 0x18, 0x0310);
3640 msleep(100);
5598bfe5
HW		 3641
3642 rtl_apply_firmware(tp);
3643
724c6fd0 3644 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
1791ad50 3645 rtl_writephy_batch(tp, phy_reg_init);
5598bfe5 3646
724c6fd0 3647 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
5598bfe5
HW		 3648}
3649
02bf642b
HK		 3650static void rtl8125_1_hw_phy_config(struct rtl8169_private *tp)
3651{
3652 struct phy_device *phydev = tp->phydev;
3653
3654 phy_modify_paged(phydev, 0xad4, 0x10, 0x03ff, 0x0084);
3655 phy_modify_paged(phydev, 0xad4, 0x17, 0x0000, 0x0010);
3656 phy_modify_paged(phydev, 0xad1, 0x13, 0x03ff, 0x0006);
3657 phy_modify_paged(phydev, 0xad3, 0x11, 0x003f, 0x0006);
3658 phy_modify_paged(phydev, 0xac0, 0x14, 0x0000, 0x1100);
3659 phy_modify_paged(phydev, 0xac8, 0x15, 0xf000, 0x7000);
3660 phy_modify_paged(phydev, 0xad1, 0x14, 0x0000, 0x0400);
3661 phy_modify_paged(phydev, 0xad1, 0x15, 0x0000, 0x03ff);
3662 phy_modify_paged(phydev, 0xad1, 0x16, 0x0000, 0x03ff);
3663
424f2610
HK		 3664 r8168g_phy_param(phydev, 0x80ea, 0xff00, 0xc400);
3665 r8168g_phy_param(phydev, 0x80eb, 0x0700, 0x0300);
3666 r8168g_phy_param(phydev, 0x80f8, 0xff00, 0x1c00);
3667 r8168g_phy_param(phydev, 0x80f1, 0xff00, 0x3000);
3668 r8168g_phy_param(phydev, 0x80fe, 0xff00, 0xa500);
3669 r8168g_phy_param(phydev, 0x8102, 0xff00, 0x5000);
3670 r8168g_phy_param(phydev, 0x8105, 0xff00, 0x3300);
3671 r8168g_phy_param(phydev, 0x8100, 0xff00, 0x7000);
3672 r8168g_phy_param(phydev, 0x8104, 0xff00, 0xf000);
3673 r8168g_phy_param(phydev, 0x8106, 0xff00, 0x6500);
3674 r8168g_phy_param(phydev, 0x80dc, 0xff00, 0xed00);
3675 r8168g_phy_param(phydev, 0x80df, 0x0000, 0x0100);
3676 r8168g_phy_param(phydev, 0x80e1, 0x0100, 0x0000);
02bf642b
HK		 3677
3678 phy_modify_paged(phydev, 0xbf0, 0x13, 0x003f, 0x0038);
424f2610 3679 r8168g_phy_param(phydev, 0x819f, 0xffff, 0xd0b6);
02bf642b
HK		 3680
3681 phy_write_paged(phydev, 0xbc3, 0x12, 0x5555);
3682 phy_modify_paged(phydev, 0xbf0, 0x15, 0x0e00, 0x0a00);
3683 phy_modify_paged(phydev, 0xa5c, 0x10, 0x0400, 0x0000);
3684 phy_modify_paged(phydev, 0xa44, 0x11, 0x0000, 0x0800);
b3a42e3a
HK		 3685
3686 rtl8125_config_eee_phy(tp);
3687 rtl_enable_eee(tp);
02bf642b
HK		 3688}
3689
3690static void rtl8125_2_hw_phy_config(struct rtl8169_private *tp)
3691{
3692 struct phy_device *phydev = tp->phydev;
3693 int i;
3694
3695 phy_modify_paged(phydev, 0xad4, 0x17, 0x0000, 0x0010);
3696 phy_modify_paged(phydev, 0xad1, 0x13, 0x03ff, 0x03ff);
3697 phy_modify_paged(phydev, 0xad3, 0x11, 0x003f, 0x0006);
3698 phy_modify_paged(phydev, 0xac0, 0x14, 0x1100, 0x0000);
3699 phy_modify_paged(phydev, 0xacc, 0x10, 0x0003, 0x0002);
3700 phy_modify_paged(phydev, 0xad4, 0x10, 0x00e7, 0x0044);
3701 phy_modify_paged(phydev, 0xac1, 0x12, 0x0080, 0x0000);
3702 phy_modify_paged(phydev, 0xac8, 0x10, 0x0300, 0x0000);
3703 phy_modify_paged(phydev, 0xac5, 0x17, 0x0007, 0x0002);
3704 phy_write_paged(phydev, 0xad4, 0x16, 0x00a8);
3705 phy_write_paged(phydev, 0xac5, 0x16, 0x01ff);
3706 phy_modify_paged(phydev, 0xac8, 0x15, 0x00f0, 0x0030);
3707
3708 phy_write(phydev, 0x1f, 0x0b87);
3709 phy_write(phydev, 0x16, 0x80a2);
3710 phy_write(phydev, 0x17, 0x0153);
3711 phy_write(phydev, 0x16, 0x809c);
3712 phy_write(phydev, 0x17, 0x0153);
3713 phy_write(phydev, 0x1f, 0x0000);
3714
3715 phy_write(phydev, 0x1f, 0x0a43);
3716 phy_write(phydev, 0x13, 0x81B3);
3717 phy_write(phydev, 0x14, 0x0043);
3718 phy_write(phydev, 0x14, 0x00A7);
3719 phy_write(phydev, 0x14, 0x00D6);
3720 phy_write(phydev, 0x14, 0x00EC);
3721 phy_write(phydev, 0x14, 0x00F6);
3722 phy_write(phydev, 0x14, 0x00FB);
3723 phy_write(phydev, 0x14, 0x00FD);
3724 phy_write(phydev, 0x14, 0x00FF);
3725 phy_write(phydev, 0x14, 0x00BB);
3726 phy_write(phydev, 0x14, 0x0058);
3727 phy_write(phydev, 0x14, 0x0029);
3728 phy_write(phydev, 0x14, 0x0013);
3729 phy_write(phydev, 0x14, 0x0009);
3730 phy_write(phydev, 0x14, 0x0004);
3731 phy_write(phydev, 0x14, 0x0002);
3732 for (i = 0; i < 25; i++)
3733 phy_write(phydev, 0x14, 0x0000);
02bf642b
HK		 3734 phy_write(phydev, 0x1f, 0x0000);
3735
424f2610
HK		 3736 r8168g_phy_param(phydev, 0x8257, 0xffff, 0x020F);
3737 r8168g_phy_param(phydev, 0x80ea, 0xffff, 0x7843);
3738
02bf642b
HK		 3739 rtl_apply_firmware(tp);
3740
3741 phy_modify_paged(phydev, 0xd06, 0x14, 0x0000, 0x2000);
3742
424f2610 3743 r8168g_phy_param(phydev, 0x81a2, 0x0000, 0x0100);
02bf642b
HK		 3744
3745 phy_modify_paged(phydev, 0xb54, 0x16, 0xff00, 0xdb00);
3746 phy_modify_paged(phydev, 0xa45, 0x12, 0x0001, 0x0000);
3747 phy_modify_paged(phydev, 0xa5d, 0x12, 0x0000, 0x0020);
3748 phy_modify_paged(phydev, 0xad4, 0x17, 0x0010, 0x0000);
3749 phy_modify_paged(phydev, 0xa86, 0x15, 0x0001, 0x0000);
3750 phy_modify_paged(phydev, 0xa44, 0x11, 0x0000, 0x0800);
b3a42e3a
HK		 3751
3752 rtl8125_config_eee_phy(tp);
3753 rtl_enable_eee(tp);
02bf642b
HK		 3754}
3755
5615d9f1
FR		 3756static void rtl_hw_phy_config(struct net_device *dev)
3757{
1fcd1658
HK		 3758 static const rtl_generic_fct phy_configs[] = {
3759 /* PCI devices. */
1fcd1658
HK		 3760 [RTL_GIGA_MAC_VER_02] = rtl8169s_hw_phy_config,
3761 [RTL_GIGA_MAC_VER_03] = rtl8169s_hw_phy_config,
3762 [RTL_GIGA_MAC_VER_04] = rtl8169sb_hw_phy_config,
3763 [RTL_GIGA_MAC_VER_05] = rtl8169scd_hw_phy_config,
3764 [RTL_GIGA_MAC_VER_06] = rtl8169sce_hw_phy_config,
3765 /* PCI-E devices. */
3766 [RTL_GIGA_MAC_VER_07] = rtl8102e_hw_phy_config,
3767 [RTL_GIGA_MAC_VER_08] = rtl8102e_hw_phy_config,
3768 [RTL_GIGA_MAC_VER_09] = rtl8102e_hw_phy_config,
3769 [RTL_GIGA_MAC_VER_10] = NULL,
3770 [RTL_GIGA_MAC_VER_11] = rtl8168bb_hw_phy_config,
3771 [RTL_GIGA_MAC_VER_12] = rtl8168bef_hw_phy_config,
3772 [RTL_GIGA_MAC_VER_13] = NULL,
3773 [RTL_GIGA_MAC_VER_14] = NULL,
3774 [RTL_GIGA_MAC_VER_15] = NULL,
3775 [RTL_GIGA_MAC_VER_16] = NULL,
3776 [RTL_GIGA_MAC_VER_17] = rtl8168bef_hw_phy_config,
3777 [RTL_GIGA_MAC_VER_18] = rtl8168cp_1_hw_phy_config,
3778 [RTL_GIGA_MAC_VER_19] = rtl8168c_1_hw_phy_config,
3779 [RTL_GIGA_MAC_VER_20] = rtl8168c_2_hw_phy_config,
3780 [RTL_GIGA_MAC_VER_21] = rtl8168c_3_hw_phy_config,
3781 [RTL_GIGA_MAC_VER_22] = rtl8168c_4_hw_phy_config,
3782 [RTL_GIGA_MAC_VER_23] = rtl8168cp_2_hw_phy_config,
3783 [RTL_GIGA_MAC_VER_24] = rtl8168cp_2_hw_phy_config,
3784 [RTL_GIGA_MAC_VER_25] = rtl8168d_1_hw_phy_config,
3785 [RTL_GIGA_MAC_VER_26] = rtl8168d_2_hw_phy_config,
3786 [RTL_GIGA_MAC_VER_27] = rtl8168d_3_hw_phy_config,
3787 [RTL_GIGA_MAC_VER_28] = rtl8168d_4_hw_phy_config,
3788 [RTL_GIGA_MAC_VER_29] = rtl8105e_hw_phy_config,
3789 [RTL_GIGA_MAC_VER_30] = rtl8105e_hw_phy_config,
3790 [RTL_GIGA_MAC_VER_31] = NULL,
3791 [RTL_GIGA_MAC_VER_32] = rtl8168e_1_hw_phy_config,
3792 [RTL_GIGA_MAC_VER_33] = rtl8168e_1_hw_phy_config,
3793 [RTL_GIGA_MAC_VER_34] = rtl8168e_2_hw_phy_config,
3794 [RTL_GIGA_MAC_VER_35] = rtl8168f_1_hw_phy_config,
3795 [RTL_GIGA_MAC_VER_36] = rtl8168f_2_hw_phy_config,
3796 [RTL_GIGA_MAC_VER_37] = rtl8402_hw_phy_config,
3797 [RTL_GIGA_MAC_VER_38] = rtl8411_hw_phy_config,
3798 [RTL_GIGA_MAC_VER_39] = rtl8106e_hw_phy_config,
3799 [RTL_GIGA_MAC_VER_40] = rtl8168g_1_hw_phy_config,
3800 [RTL_GIGA_MAC_VER_41] = NULL,
3801 [RTL_GIGA_MAC_VER_42] = rtl8168g_2_hw_phy_config,
3802 [RTL_GIGA_MAC_VER_43] = rtl8168g_2_hw_phy_config,
3803 [RTL_GIGA_MAC_VER_44] = rtl8168g_2_hw_phy_config,
3804 [RTL_GIGA_MAC_VER_45] = rtl8168h_1_hw_phy_config,
3805 [RTL_GIGA_MAC_VER_46] = rtl8168h_2_hw_phy_config,
3806 [RTL_GIGA_MAC_VER_47] = rtl8168h_1_hw_phy_config,
3807 [RTL_GIGA_MAC_VER_48] = rtl8168h_2_hw_phy_config,
3808 [RTL_GIGA_MAC_VER_49] = rtl8168ep_1_hw_phy_config,
3809 [RTL_GIGA_MAC_VER_50] = rtl8168ep_2_hw_phy_config,
3810 [RTL_GIGA_MAC_VER_51] = rtl8168ep_2_hw_phy_config,
2e13d773 3811 [RTL_GIGA_MAC_VER_52] = rtl8117_hw_phy_config,
02bf642b
HK		 3812 [RTL_GIGA_MAC_VER_60] = rtl8125_1_hw_phy_config,
3813 [RTL_GIGA_MAC_VER_61] = rtl8125_2_hw_phy_config,
1fcd1658 3814 };
5615d9f1 3815 struct rtl8169_private *tp = netdev_priv(dev);
5615d9f1 3816
1fcd1658
HK		 3817 if (phy_configs[tp->mac_version])
3818 phy_configs[tp->mac_version](tp);
5615d9f1
FR		 3819}
3820
da78dbff
FR		 3821static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
3822{
da78dbff
FR		 3823 if (!test_and_set_bit(flag, tp->wk.flags))
3824 schedule_work(&tp->wk.work);
da78dbff
FR		 3825}
3826
4ff96fa6
FR		 3827static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3828{
5615d9f1 3829 rtl_hw_phy_config(dev);
4ff96fa6 3830
77332894 3831 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
7a67e11d
HK		 3832 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3833 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
49d17512
HK		 3834 netif_dbg(tp, drv, dev,
3835 "Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1ef7286e 3836 RTL_W8(tp, 0x82, 0x01);
77332894 3837 }
4ff96fa6 3838
5b7ad4b7 3839 /* We may have called phy_speed_down before */
703732f0 3840 phy_speed_up(tp->phydev);
5b7ad4b7 3841
703732f0 3842 genphy_soft_reset(tp->phydev);
4ff96fa6
FR		 3843}
3844
773d2021
FR		 3845static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3846{
da78dbff 3847 rtl_lock_work(tp);
773d2021 3848
df320ed7 3849 rtl_unlock_config_regs(tp);
908ba2bf 3850
1ef7286e
AS		 3851 RTL_W32(tp, MAC4, addr[4] | addr[5] << 8);
3852 RTL_R32(tp, MAC4);
908ba2bf 3853
1ef7286e
AS		 3854 RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
3855 RTL_R32(tp, MAC0);
908ba2bf 3856
9ecb9aab 3857 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
3858 rtl_rar_exgmac_set(tp, addr);
c28aa385 3859
df320ed7 3860 rtl_lock_config_regs(tp);
773d2021 3861
da78dbff 3862 rtl_unlock_work(tp);
773d2021
FR		 3863}
3864
3865static int rtl_set_mac_address(struct net_device *dev, void *p)
3866{
3867 struct rtl8169_private *tp = netdev_priv(dev);
1e1205b7 3868 struct device *d = tp_to_dev(tp);
1f7aa2bc 3869 int ret;
773d2021 3870
1f7aa2bc
HK		 3871 ret = eth_mac_addr(dev, p);
3872 if (ret)
3873 return ret;
773d2021 3874
f51d4a10
CHL		 3875 pm_runtime_get_noresume(d);
3876
3877 if (pm_runtime_active(d))
3878 rtl_rar_set(tp, dev->dev_addr);
3879
3880 pm_runtime_put_noidle(d);
773d2021
FR		 3881
3882 return 0;
3883}
3884
e397286b 3885static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
8b4ab28d 3886{
703732f0
HK		 3887 struct rtl8169_private *tp = netdev_priv(dev);
3888
69b3c59f
HK		 3889 if (!netif_running(dev))
3890 return -ENODEV;
e397286b 3891
703732f0 3892 return phy_mii_ioctl(tp->phydev, ifr, cmd);
8b4ab28d
FR		 3893}
3894
649b3b8c 3895static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
3896{
649b3b8c 3897 switch (tp->mac_version) {
b00e69de
CB		 3898 case RTL_GIGA_MAC_VER_25:
3899 case RTL_GIGA_MAC_VER_26:
649b3b8c 3900 case RTL_GIGA_MAC_VER_29:
3901 case RTL_GIGA_MAC_VER_30:
3902 case RTL_GIGA_MAC_VER_32:
3903 case RTL_GIGA_MAC_VER_33:
3904 case RTL_GIGA_MAC_VER_34:
50a03386 3905 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_61:
1ef7286e 3906 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
649b3b8c 3907 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3908 break;
3909 default:
3910 break;
3911 }
3912}
3913
25e94115 3914static void rtl_pll_power_down(struct rtl8169_private *tp)
065c27c1 3915{
9dbe7896 3916 if (r8168_check_dash(tp))
065c27c1 3917 return;
3918
01dc7fec 3919 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3920 tp->mac_version == RTL_GIGA_MAC_VER_33)
fdf6fc06 3921 rtl_ephy_write(tp, 0x19, 0xff64);
01dc7fec 3922
5ea25b12
HK		 3923 if (device_may_wakeup(tp_to_dev(tp))) {
3924 phy_speed_down(tp->phydev, false);
3925 rtl_wol_suspend_quirk(tp);
065c27c1 3926 return;
5ea25b12 3927 }
065c27c1 3928
065c27c1 3929 switch (tp->mac_version) {
2a71883c 3930 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
73570bf1
HK		 3931 case RTL_GIGA_MAC_VER_37:
3932 case RTL_GIGA_MAC_VER_39:
3933 case RTL_GIGA_MAC_VER_43:
42fde737 3934 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 3935 case RTL_GIGA_MAC_VER_45:
3936 case RTL_GIGA_MAC_VER_46:
73570bf1
HK		 3937 case RTL_GIGA_MAC_VER_47:
3938 case RTL_GIGA_MAC_VER_48:
935e2218
CHL		 3939 case RTL_GIGA_MAC_VER_50:
3940 case RTL_GIGA_MAC_VER_51:
2e13d773 3941 case RTL_GIGA_MAC_VER_52:
f1bce4ad
HK		 3942 case RTL_GIGA_MAC_VER_60:
3943 case RTL_GIGA_MAC_VER_61:
1ef7286e 3944 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
065c27c1 3945 break;
beb330a4 3946 case RTL_GIGA_MAC_VER_40:
3947 case RTL_GIGA_MAC_VER_41:
935e2218 3948 case RTL_GIGA_MAC_VER_49:
e719b3ea 3949 rtl_eri_clear_bits(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000);
1ef7286e 3950 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
beb330a4 3951 break;
76719ee2
HK		 3952 default:
3953 break;
065c27c1 3954 }
3955}
3956
25e94115 3957static void rtl_pll_power_up(struct rtl8169_private *tp)
065c27c1 3958{
065c27c1 3959 switch (tp->mac_version) {
2a71883c 3960 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
73570bf1
HK		 3961 case RTL_GIGA_MAC_VER_37:
3962 case RTL_GIGA_MAC_VER_39:
3963 case RTL_GIGA_MAC_VER_43:
1ef7286e 3964 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80);
065c27c1 3965 break;
42fde737 3966 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 3967 case RTL_GIGA_MAC_VER_45:
3968 case RTL_GIGA_MAC_VER_46:
73570bf1
HK		 3969 case RTL_GIGA_MAC_VER_47:
3970 case RTL_GIGA_MAC_VER_48:
935e2218
CHL		 3971 case RTL_GIGA_MAC_VER_50:
3972 case RTL_GIGA_MAC_VER_51:
2e13d773 3973 case RTL_GIGA_MAC_VER_52:
f1bce4ad
HK		 3974 case RTL_GIGA_MAC_VER_60:
3975 case RTL_GIGA_MAC_VER_61:
1ef7286e 3976 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
6e1d0b89 3977 break;
beb330a4 3978 case RTL_GIGA_MAC_VER_40:
3979 case RTL_GIGA_MAC_VER_41:
935e2218 3980 case RTL_GIGA_MAC_VER_49:
1ef7286e 3981 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
e719b3ea 3982 rtl_eri_set_bits(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000);
beb330a4 3983 break;
76719ee2
HK		 3984 default:
3985 break;
065c27c1 3986 }
3987
703732f0 3988 phy_resume(tp->phydev);
242cd9b5
HK		 3989 /* give MAC/PHY some time to resume */
3990 msleep(20);
065c27c1 3991}
3992
e542a226
HW		 3993static void rtl_init_rxcfg(struct rtl8169_private *tp)
3994{
e542a226 3995 switch (tp->mac_version) {
e9588eb9 3996 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
2a71883c 3997 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
1ef7286e 3998 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
e542a226 3999 break;
2a71883c 4000 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
511cfd58
MS		 4001 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
4002 case RTL_GIGA_MAC_VER_38:
1ef7286e 4003 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
e542a226 4004 break;
2e13d773 4005 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_52:
1ef7286e 4006 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
beb330a4 4007 break;
f1bce4ad
HK		 4008 case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_61:
4009 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_VLAN_8125 |
4010 RX_DMA_BURST);
4011 break;
e542a226 4012 default:
1ef7286e 4013 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
e542a226
HW		 4014 break;
4015 }
4016}
4017
92fc43b4
HW		 4018static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4019{
9fba0812 4020 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
92fc43b4
HW		 4021}
4022
d58d46b5
FR		 4023static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
4024{
1ef7286e
AS		 4025 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4026 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
cb73200c 4027 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
d58d46b5
FR		 4028}
4029
4030static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
4031{
1ef7286e
AS		 4032 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4033 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
8d98aa39 4034 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
d58d46b5
FR		 4035}
4036
4037static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
4038{
1ef7286e 4039 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
d58d46b5
FR		 4040}
4041
4042static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
4043{
1ef7286e 4044 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
d58d46b5
FR		 4045}
4046
4047static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
4048{
1ef7286e
AS		 4049 RTL_W8(tp, MaxTxPacketSize, 0x3f);
4050 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4051 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
cb73200c 4052 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
d58d46b5
FR		 4053}
4054
4055static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
4056{
1ef7286e
AS		 4057 RTL_W8(tp, MaxTxPacketSize, 0x0c);
4058 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4059 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
8d98aa39 4060 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
d58d46b5
FR		 4061}
4062
4063static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
4064{
cb73200c 4065 rtl_tx_performance_tweak(tp,
f65d539c 4066 PCI_EXP_DEVCTL_READRQ_512B | PCI_EXP_DEVCTL_NOSNOOP_EN);
d58d46b5
FR		 4067}
4068
4069static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
4070{
cb73200c 4071 rtl_tx_performance_tweak(tp,
8d98aa39 4072 PCI_EXP_DEVCTL_READRQ_4096B | PCI_EXP_DEVCTL_NOSNOOP_EN);
d58d46b5
FR		 4073}
4074
4075static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
4076{
d58d46b5
FR		 4077 r8168b_0_hw_jumbo_enable(tp);
4078
1ef7286e 4079 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
d58d46b5
FR		 4080}
4081
4082static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
4083{
d58d46b5
FR		 4084 r8168b_0_hw_jumbo_disable(tp);
4085
1ef7286e 4086 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
d58d46b5
FR		 4087}
4088
485bb1b3 4089static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
d58d46b5 4090{
485bb1b3 4091 rtl_unlock_config_regs(tp);
d58d46b5
FR		 4092 switch (tp->mac_version) {
4093 case RTL_GIGA_MAC_VER_11:
485bb1b3 4094 r8168b_0_hw_jumbo_enable(tp);
d58d46b5
FR		 4095 break;
4096 case RTL_GIGA_MAC_VER_12:
4097 case RTL_GIGA_MAC_VER_17:
485bb1b3 4098 r8168b_1_hw_jumbo_enable(tp);
d58d46b5 4099 break;
485bb1b3
HK		 4100 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26:
4101 r8168c_hw_jumbo_enable(tp);
d58d46b5 4102 break;
485bb1b3
HK		 4103 case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28:
4104 r8168dp_hw_jumbo_enable(tp);
d58d46b5 4105 break;
9e7d190e 4106 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33:
485bb1b3
HK		 4107 r8168e_hw_jumbo_enable(tp);
4108 break;
4109 default:
d58d46b5 4110 break;
485bb1b3
HK		 4111 }
4112 rtl_lock_config_regs(tp);
4113}
d58d46b5 4114
485bb1b3
HK		 4115static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4116{
4117 rtl_unlock_config_regs(tp);
4118 switch (tp->mac_version) {
4119 case RTL_GIGA_MAC_VER_11:
4120 r8168b_0_hw_jumbo_disable(tp);
4121 break;
4122 case RTL_GIGA_MAC_VER_12:
4123 case RTL_GIGA_MAC_VER_17:
4124 r8168b_1_hw_jumbo_disable(tp);
4125 break;
4126 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26:
4127 r8168c_hw_jumbo_disable(tp);
4128 break;
4129 case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28:
4130 r8168dp_hw_jumbo_disable(tp);
4131 break;
2618eff1 4132 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33:
485bb1b3
HK		 4133 r8168e_hw_jumbo_disable(tp);
4134 break;
d58d46b5 4135 default:
d58d46b5
FR		 4136 break;
4137 }
485bb1b3 4138 rtl_lock_config_regs(tp);
d58d46b5
FR		 4139}
4140
4ebcb113
HK		 4141static void rtl_jumbo_config(struct rtl8169_private *tp, int mtu)
4142{
4143 if (mtu > ETH_DATA_LEN)
4144 rtl_hw_jumbo_enable(tp);
4145 else
4146 rtl_hw_jumbo_disable(tp);
4147}
4148
ffc46952
FR		 4149DECLARE_RTL_COND(rtl_chipcmd_cond)
4150{
1ef7286e 4151 return RTL_R8(tp, ChipCmd) & CmdReset;
ffc46952
FR		 4152}
4153
6f43adc8
FR		 4154static void rtl_hw_reset(struct rtl8169_private *tp)
4155{
1ef7286e 4156 RTL_W8(tp, ChipCmd, CmdReset);
6f43adc8 4157
ffc46952 4158 rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
6f43adc8
FR		 4159}
4160
254764e5 4161static void rtl_request_firmware(struct rtl8169_private *tp)
953a12cc 4162{
b6ffd97f 4163 struct rtl_fw *rtl_fw;
953a12cc 4164
254764e5
HK		 4165 /* firmware loaded already or no firmware available */
4166 if (tp->rtl_fw || !tp->fw_name)
4167 return;
953a12cc 4168
b6ffd97f 4169 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
47ad5931
HK		 4170 if (!rtl_fw) {
4171 netif_warn(tp, ifup, tp->dev, "Unable to load firmware, out of memory\n");
4172 return;
4173 }
31bd204f 4174
ce8843ab
HK		 4175 rtl_fw->phy_write = rtl_writephy;
4176 rtl_fw->phy_read = rtl_readphy;
4177 rtl_fw->mac_mcu_write = mac_mcu_write;
4178 rtl_fw->mac_mcu_read = mac_mcu_read;
4edb00f3
HK		 4179 rtl_fw->fw_name = tp->fw_name;
4180 rtl_fw->dev = tp_to_dev(tp);
ce8843ab 4181
47ad5931
HK		 4182 if (rtl_fw_request_firmware(rtl_fw))
4183 kfree(rtl_fw);
4184 else
4185 tp->rtl_fw = rtl_fw;
953a12cc
FR		 4186}
4187
92fc43b4
HW		 4188static void rtl_rx_close(struct rtl8169_private *tp)
4189{
1ef7286e 4190 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
92fc43b4
HW		 4191}
4192
ffc46952
FR		 4193DECLARE_RTL_COND(rtl_npq_cond)
4194{
1ef7286e 4195 return RTL_R8(tp, TxPoll) & NPQ;
ffc46952
FR		 4196}
4197
4198DECLARE_RTL_COND(rtl_txcfg_empty_cond)
4199{
1ef7286e 4200 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
ffc46952
FR		 4201}
4202
e6de30d6 4203static void rtl8169_hw_reset(struct rtl8169_private *tp)
1da177e4
LT		 4204{
4205 /* Disable interrupts */
811fd301 4206 rtl8169_irq_mask_and_ack(tp);
1da177e4 4207
92fc43b4
HW		 4208 rtl_rx_close(tp);
4209
b2d43e6e
HK		 4210 switch (tp->mac_version) {
4211 case RTL_GIGA_MAC_VER_27:
4212 case RTL_GIGA_MAC_VER_28:
4213 case RTL_GIGA_MAC_VER_31:
ffc46952 4214 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
b2d43e6e
HK		 4215 break;
4216 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
2e13d773 4217 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_52:
1ef7286e 4218 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
ffc46952 4219 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
b2d43e6e
HK		 4220 break;
4221 default:
1ef7286e 4222 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
92fc43b4 4223 udelay(100);
b2d43e6e 4224 break;
e6de30d6 4225 }
4226
92fc43b4 4227 rtl_hw_reset(tp);
1da177e4
LT		 4228}
4229
05212ba8 4230static void rtl_set_tx_config_registers(struct rtl8169_private *tp)
9cb427b6 4231{
ad5f97fa
HK		 4232 u32 val = TX_DMA_BURST << TxDMAShift |
4233 InterFrameGap << TxInterFrameGapShift;
4234
9e9f33ba 4235 if (rtl_is_8168evl_up(tp))
ad5f97fa
HK		 4236 val |= TXCFG_AUTO_FIFO;
4237
4238 RTL_W32(tp, TxConfig, val);
9cb427b6
FR		 4239}
4240
4fd48c4a 4241static void rtl_set_rx_max_size(struct rtl8169_private *tp)
1da177e4 4242{
4fd48c4a
HK		 4243 /* Low hurts. Let's disable the filtering. */
4244 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
07ce4064
FR		 4245}
4246
1ef7286e 4247static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
7f796d83
FR		 4248{
4249 /*
4250 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4251 * register to be written before TxDescAddrLow to work.
4252 * Switching from MMIO to I/O access fixes the issue as well.
4253 */
1ef7286e
AS		 4254 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4255 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4256 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4257 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
7f796d83
FR		 4258}
4259
1ef7286e 4260static void rtl8169_set_magic_reg(struct rtl8169_private *tp, unsigned mac_version)
6dccd16b 4261{
34bc0095
HK		 4262 u32 val;
4263
4264 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4265 val = 0x000fff00;
4266 else if (tp->mac_version == RTL_GIGA_MAC_VER_06)
4267 val = 0x00ffff00;
4268 else
4269 return;
4270
4271 if (RTL_R8(tp, Config2) & PCI_Clock_66MHz)
4272 val |= 0xff;
4273
4274 RTL_W32(tp, 0x7c, val);
6dccd16b
FR		 4275}
4276
e6b763ea
FR		 4277static void rtl_set_rx_mode(struct net_device *dev)
4278{
81cd17a4
HK		 4279 u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast;
4280 /* Multicast hash filter */
4281 u32 mc_filter[2] = { 0xffffffff, 0xffffffff };
e6b763ea 4282 struct rtl8169_private *tp = netdev_priv(dev);
81cd17a4 4283 u32 tmp;
e6b763ea
FR		 4284
4285 if (dev->flags & IFF_PROMISC) {
4286 /* Unconditionally log net taps. */
4287 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
81cd17a4
HK		 4288 rx_mode |= AcceptAllPhys;
4289 } else if (netdev_mc_count(dev) > MC_FILTER_LIMIT ||
4290 dev->flags & IFF_ALLMULTI ||
4291 tp->mac_version == RTL_GIGA_MAC_VER_35) {
4292 /* accept all multicasts */
4293 } else if (netdev_mc_empty(dev)) {
4294 rx_mode &= ~AcceptMulticast;
e6b763ea
FR		 4295 } else {
4296 struct netdev_hw_addr *ha;
4297
e6b763ea
FR		 4298 mc_filter[1] = mc_filter[0] = 0;
4299 netdev_for_each_mc_addr(ha, dev) {
81cd17a4
HK		 4300 u32 bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4301 mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31);
4302 }
4303
4304 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4305 tmp = mc_filter[0];
4306 mc_filter[0] = swab32(mc_filter[1]);
4307 mc_filter[1] = swab32(tmp);
e6b763ea
FR		 4308 }
4309 }
4310
4311 if (dev->features & NETIF_F_RXALL)
4312 rx_mode |= (AcceptErr | AcceptRunt);
4313
1ef7286e
AS		 4314 RTL_W32(tp, MAR0 + 4, mc_filter[1]);
4315 RTL_W32(tp, MAR0 + 0, mc_filter[0]);
e6b763ea 4316
81cd17a4
HK		 4317 tmp = RTL_R32(tp, RxConfig);
4318 RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_MASK) | rx_mode);
e6b763ea
FR		 4319}
4320
ffc46952
FR		 4321DECLARE_RTL_COND(rtl_csiar_cond)
4322{
1ef7286e 4323 return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
ffc46952
FR		 4324}
4325
ff1d7331 4326static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
beb1fe18 4327{
ff1d7331 4328 u32 func = PCI_FUNC(tp->pci_dev->devfn);
beb1fe18 4329
1ef7286e
AS		 4330 RTL_W32(tp, CSIDR, value);
4331 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
ff1d7331 4332 CSIAR_BYTE_ENABLE | func << 16);
7e18dca1 4333
ffc46952 4334 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
7e18dca1
HW		 4335}
4336
ff1d7331 4337static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
7e18dca1 4338{
ff1d7331
HK		 4339 u32 func = PCI_FUNC(tp->pci_dev->devfn);
4340
4341 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
4342 CSIAR_BYTE_ENABLE);
7e18dca1 4343
ffc46952 4344 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
1ef7286e 4345 RTL_R32(tp, CSIDR) : ~0;
7e18dca1
HW		 4346}
4347
ff1d7331 4348static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val)
45dd95c4 4349{
ff1d7331
HK		 4350 struct pci_dev *pdev = tp->pci_dev;
4351 u32 csi;
45dd95c4 4352
ff1d7331
HK		 4353 /* According to Realtek the value at config space address 0x070f
4354 * controls the L0s/L1 entrance latency. We try standard ECAM access
4355 * first and if it fails fall back to CSI.
4356 */
4357 if (pdev->cfg_size > 0x070f &&
4358 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL)
4359 return;
4360
4361 netdev_notice_once(tp->dev,
4362 "No native access to PCI extended config space, falling back to CSI\n");
4363 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
4364 rtl_csi_write(tp, 0x070c, csi | val << 24);
45dd95c4 4365}
4366
f37658da 4367static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
beb1fe18 4368{
ff1d7331 4369 rtl_csi_access_enable(tp, 0x27);
dacf8154
FR		 4370}
4371
4372struct ephy_info {
4373 unsigned int offset;
4374 u16 mask;
4375 u16 bits;
4376};
4377
1791ad50
HK		 4378static void __rtl_ephy_init(struct rtl8169_private *tp,
4379 const struct ephy_info *e, int len)
dacf8154
FR		 4380{
4381 u16 w;
4382
4383 while (len-- > 0) {
fdf6fc06
FR		 4384 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
4385 rtl_ephy_write(tp, e->offset, w);
dacf8154
FR		 4386 e++;
4387 }
4388}
4389
1791ad50
HK		 4390#define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a))
4391
73c86ee3 4392static void rtl_disable_clock_request(struct rtl8169_private *tp)
b726e493 4393{
73c86ee3 4394 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
7d7903b2 4395 PCI_EXP_LNKCTL_CLKREQ_EN);
b726e493
FR		 4396}
4397
73c86ee3 4398static void rtl_enable_clock_request(struct rtl8169_private *tp)
e6de30d6 4399{
73c86ee3 4400 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
7d7903b2 4401 PCI_EXP_LNKCTL_CLKREQ_EN);
e6de30d6 4402}
4403
c259b7f4 4404static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp)
b51ecea8 4405{
c259b7f4
HK		 4406 /* work around an issue when PCI reset occurs during L2/L3 state */
4407 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23);
b51ecea8 4408}
4409
a99790bf
KHF		 4410static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
4411{
62b1b3b3
HK		 4412 /* Don't enable ASPM in the chip if OS can't control ASPM */
4413 if (enable && tp->aspm_manageable) {
a99790bf 4414 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en);
94235460 4415 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn);
a99790bf
KHF		 4416 } else {
4417 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
4418 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
4419 }
94235460
KHF		 4420
4421 udelay(10);
a99790bf
KHF		 4422}
4423
6b1bd242
HK		 4424static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat,
4425 u16 tx_stat, u16 rx_dyn, u16 tx_dyn)
4426{
4427 /* Usage of dynamic vs. static FIFO is controlled by bit
4428 * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known.
4429 */
4430 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn);
4431 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn);
4432}
4433
0ebacd12
HK		 4434static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp,
4435 u8 low, u8 high)
4436{
4437 /* FIFO thresholds for pause flow control */
4438 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low);
4439 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high);
4440}
4441
beb1fe18 4442static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
219a1e9d 4443{
1ef7286e 4444 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
219a1e9d
FR		 4445}
4446
beb1fe18 4447static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
219a1e9d 4448{
beb1fe18 4449 rtl_hw_start_8168bb(tp);
b726e493 4450
1ef7286e 4451 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
219a1e9d
FR		 4452}
4453
beb1fe18 4454static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
219a1e9d 4455{
1ef7286e 4456 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
b726e493 4457
1ef7286e 4458 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
b726e493 4459
73c86ee3 4460 rtl_disable_clock_request(tp);
219a1e9d
FR		 4461}
4462
beb1fe18 4463static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
219a1e9d 4464{
350f7596 4465 static const struct ephy_info e_info_8168cp[] = {
b726e493
FR		 4466 { 0x01, 0, 0x0001 },
4467 { 0x02, 0x0800, 0x1000 },
4468 { 0x03, 0, 0x0042 },
4469 { 0x06, 0x0080, 0x0000 },
4470 { 0x07, 0, 0x2000 }
4471 };
4472
f37658da 4473 rtl_set_def_aspm_entry_latency(tp);
b726e493 4474
1791ad50 4475 rtl_ephy_init(tp, e_info_8168cp);
b726e493 4476
beb1fe18 4477 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 4478}
4479
beb1fe18 4480static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
ef3386f0 4481{
f37658da 4482 rtl_set_def_aspm_entry_latency(tp);
ef3386f0 4483
1ef7286e 4484 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
ef3386f0
FR		 4485}
4486
beb1fe18 4487static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
7f3e3d3a 4488{
f37658da 4489 rtl_set_def_aspm_entry_latency(tp);
7f3e3d3a 4490
1ef7286e 4491 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
7f3e3d3a
FR		 4492
4493 /* Magic. */
1ef7286e 4494 RTL_W8(tp, DBG_REG, 0x20);
7f3e3d3a
FR		 4495}
4496
beb1fe18 4497static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
219a1e9d 4498{
350f7596 4499 static const struct ephy_info e_info_8168c_1[] = {
b726e493
FR		 4500 { 0x02, 0x0800, 0x1000 },
4501 { 0x03, 0, 0x0002 },
4502 { 0x06, 0x0080, 0x0000 }
4503 };
4504
f37658da 4505 rtl_set_def_aspm_entry_latency(tp);
b726e493 4506
1ef7286e 4507 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
b726e493 4508
1791ad50 4509 rtl_ephy_init(tp, e_info_8168c_1);
b726e493 4510
beb1fe18 4511 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 4512}
4513
beb1fe18 4514static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
219a1e9d 4515{
350f7596 4516 static const struct ephy_info e_info_8168c_2[] = {
b726e493 4517 { 0x01, 0, 0x0001 },
a7a92cf8 4518 { 0x03, 0x0400, 0x0020 }
b726e493
FR		 4519 };
4520
f37658da 4521 rtl_set_def_aspm_entry_latency(tp);
b726e493 4522
1791ad50 4523 rtl_ephy_init(tp, e_info_8168c_2);
b726e493 4524
beb1fe18 4525 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 4526}
4527
beb1fe18 4528static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
197ff761 4529{
beb1fe18 4530 rtl_hw_start_8168c_2(tp);
197ff761
FR		 4531}
4532
beb1fe18 4533static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
6fb07058 4534{
f37658da 4535 rtl_set_def_aspm_entry_latency(tp);
6fb07058 4536
beb1fe18 4537 __rtl_hw_start_8168cp(tp);
6fb07058
FR		 4538}
4539
beb1fe18 4540static void rtl_hw_start_8168d(struct rtl8169_private *tp)
5b538df9 4541{
f37658da 4542 rtl_set_def_aspm_entry_latency(tp);
5b538df9 4543
73c86ee3 4544 rtl_disable_clock_request(tp);
5b538df9 4545
faf1e785 4546 if (tp->dev->mtu <= ETH_DATA_LEN)
8d98aa39 4547 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5b538df9
FR		 4548}
4549
beb1fe18 4550static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
4804b3b3 4551{
f37658da 4552 rtl_set_def_aspm_entry_latency(tp);
4804b3b3 4553
faf1e785 4554 if (tp->dev->mtu <= ETH_DATA_LEN)
8d98aa39 4555 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4804b3b3 4556
73c86ee3 4557 rtl_disable_clock_request(tp);
4804b3b3 4558}
4559
beb1fe18 4560static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
e6de30d6 4561{
4562 static const struct ephy_info e_info_8168d_4[] = {
1016a4a1
CHL		 4563 { 0x0b, 0x0000, 0x0048 },
4564 { 0x19, 0x0020, 0x0050 },
a7a92cf8
HK		 4565 { 0x0c, 0x0100, 0x0020 },
4566 { 0x10, 0x0004, 0x0000 },
e6de30d6 4567 };
e6de30d6 4568
f37658da 4569 rtl_set_def_aspm_entry_latency(tp);
e6de30d6 4570
8d98aa39 4571 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
e6de30d6 4572
1791ad50 4573 rtl_ephy_init(tp, e_info_8168d_4);
e6de30d6 4574
73c86ee3 4575 rtl_enable_clock_request(tp);
e6de30d6 4576}
4577
beb1fe18 4578static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
01dc7fec 4579{
70090424 4580 static const struct ephy_info e_info_8168e_1[] = {
01dc7fec 4581 { 0x00, 0x0200, 0x0100 },
4582 { 0x00, 0x0000, 0x0004 },
4583 { 0x06, 0x0002, 0x0001 },
4584 { 0x06, 0x0000, 0x0030 },
4585 { 0x07, 0x0000, 0x2000 },
4586 { 0x00, 0x0000, 0x0020 },
4587 { 0x03, 0x5800, 0x2000 },
4588 { 0x03, 0x0000, 0x0001 },
4589 { 0x01, 0x0800, 0x1000 },
4590 { 0x07, 0x0000, 0x4000 },
4591 { 0x1e, 0x0000, 0x2000 },
4592 { 0x19, 0xffff, 0xfe6c },
4593 { 0x0a, 0x0000, 0x0040 }
4594 };
4595
f37658da 4596 rtl_set_def_aspm_entry_latency(tp);
01dc7fec 4597
1791ad50 4598 rtl_ephy_init(tp, e_info_8168e_1);
01dc7fec 4599
73c86ee3 4600 rtl_disable_clock_request(tp);
01dc7fec 4601
4602 /* Reset tx FIFO pointer */
1ef7286e
AS		 4603 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
4604 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
01dc7fec 4605
1ef7286e 4606 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
01dc7fec 4607}
4608
beb1fe18 4609static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
70090424
HW		 4610{
4611 static const struct ephy_info e_info_8168e_2[] = {
4612 { 0x09, 0x0000, 0x0080 },
a7a92cf8
HK		 4613 { 0x19, 0x0000, 0x0224 },
4614 { 0x00, 0x0000, 0x0004 },
4615 { 0x0c, 0x3df0, 0x0200 },
70090424
HW		 4616 };
4617
f37658da 4618 rtl_set_def_aspm_entry_latency(tp);
70090424 4619
1791ad50 4620 rtl_ephy_init(tp, e_info_8168e_2);
70090424 4621
724c6fd0
HK		 4622 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4623 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
6b1bd242 4624 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
724c6fd0
HK		 4625 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
4626 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060);
e719b3ea 4627 rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4));
724c6fd0 4628 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00);
70090424 4629
73c86ee3 4630 rtl_disable_clock_request(tp);
4521e1a9 4631
1ef7286e 4632 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
70090424 4633
cc07d271
HK		 4634 rtl8168_config_eee_mac(tp);
4635
1ef7286e
AS		 4636 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
4637 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
4638 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
aa1e7d2c
HK		 4639
4640 rtl_hw_aspm_clkreq_enable(tp, true);
70090424
HW		 4641}
4642
5f886e08 4643static void rtl_hw_start_8168f(struct rtl8169_private *tp)
c2218925 4644{
f37658da 4645 rtl_set_def_aspm_entry_latency(tp);
c2218925 4646
8d98aa39 4647 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
c2218925 4648
724c6fd0
HK		 4649 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4650 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
6b1bd242 4651 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
4e7e4621 4652 rtl_reset_packet_filter(tp);
e719b3ea
HK		 4653 rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4));
4654 rtl_eri_set_bits(tp, 0x1d0, ERIAR_MASK_0001, BIT(4));
724c6fd0
HK		 4655 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
4656 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060);
c2218925 4657
73c86ee3 4658 rtl_disable_clock_request(tp);
4521e1a9 4659
1ef7286e
AS		 4660 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
4661 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
4662 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
4663 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
cc07d271
HK		 4664
4665 rtl8168_config_eee_mac(tp);
c2218925
HW		 4666}
4667
5f886e08
HW		 4668static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
4669{
5f886e08
HW		 4670 static const struct ephy_info e_info_8168f_1[] = {
4671 { 0x06, 0x00c0, 0x0020 },
4672 { 0x08, 0x0001, 0x0002 },
4673 { 0x09, 0x0000, 0x0080 },
a7a92cf8
HK		 4674 { 0x19, 0x0000, 0x0224 },
4675 { 0x00, 0x0000, 0x0004 },
4676 { 0x0c, 0x3df0, 0x0200 },
5f886e08
HW		 4677 };
4678
4679 rtl_hw_start_8168f(tp);
4680
1791ad50 4681 rtl_ephy_init(tp, e_info_8168f_1);
5f886e08 4682
724c6fd0 4683 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00);
5f886e08
HW		 4684}
4685
b3d7b2f2
HW		 4686static void rtl_hw_start_8411(struct rtl8169_private *tp)
4687{
b3d7b2f2
HW		 4688 static const struct ephy_info e_info_8168f_1[] = {
4689 { 0x06, 0x00c0, 0x0020 },
4690 { 0x0f, 0xffff, 0x5200 },
a7a92cf8
HK		 4691 { 0x19, 0x0000, 0x0224 },
4692 { 0x00, 0x0000, 0x0004 },
4693 { 0x0c, 0x3df0, 0x0200 },
b3d7b2f2
HW		 4694 };
4695
4696 rtl_hw_start_8168f(tp);
c259b7f4 4697 rtl_pcie_state_l2l3_disable(tp);
b3d7b2f2 4698
1791ad50 4699 rtl_ephy_init(tp, e_info_8168f_1);
b3d7b2f2 4700
e719b3ea 4701 rtl_eri_set_bits(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00);
b3d7b2f2
HW		 4702}
4703
5fbea337 4704static void rtl_hw_start_8168g(struct rtl8169_private *tp)
c558386b 4705{
6b1bd242 4706 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
0ebacd12 4707 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
c558386b 4708
f37658da 4709 rtl_set_def_aspm_entry_latency(tp);
c558386b 4710
8d98aa39 4711 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
c558386b 4712
4e7e4621 4713 rtl_reset_packet_filter(tp);
724c6fd0 4714 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f);
c558386b 4715
1ef7286e 4716 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
c558386b 4717
724c6fd0
HK		 4718 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4719 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
c558386b 4720
df6f1856
HK		 4721 rtl8168_config_eee_mac(tp);
4722
724c6fd0 4723 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06);
e719b3ea 4724 rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12));
b51ecea8 4725
c259b7f4 4726 rtl_pcie_state_l2l3_disable(tp);
c558386b
HW		 4727}
4728
5fbea337
CHL		 4729static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
4730{
5fbea337 4731 static const struct ephy_info e_info_8168g_1[] = {
a7a92cf8
HK		 4732 { 0x00, 0x0008, 0x0000 },
4733 { 0x0c, 0x3ff0, 0x0820 },
5fbea337
CHL		 4734 { 0x1e, 0x0000, 0x0001 },
4735 { 0x19, 0x8000, 0x0000 }
4736 };
4737
4738 rtl_hw_start_8168g(tp);
4739
4740 /* disable aspm and clock request before access ephy */
a99790bf 4741 rtl_hw_aspm_clkreq_enable(tp, false);
1791ad50 4742 rtl_ephy_init(tp, e_info_8168g_1);
a99790bf 4743 rtl_hw_aspm_clkreq_enable(tp, true);
5fbea337
CHL		 4744}
4745
57538c4a 4746static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
4747{
57538c4a 4748 static const struct ephy_info e_info_8168g_2[] = {
a7a92cf8
HK		 4749 { 0x00, 0x0008, 0x0000 },
4750 { 0x0c, 0x3ff0, 0x0820 },
4751 { 0x19, 0xffff, 0x7c00 },
4752 { 0x1e, 0xffff, 0x20eb },
4753 { 0x0d, 0xffff, 0x1666 },
4754 { 0x00, 0xffff, 0x10a3 },
4755 { 0x06, 0xffff, 0xf050 },
4756 { 0x04, 0x0000, 0x0010 },
4757 { 0x1d, 0x4000, 0x0000 },
57538c4a 4758 };
4759
5fbea337 4760 rtl_hw_start_8168g(tp);
57538c4a 4761
4762 /* disable aspm and clock request before access ephy */
1ef7286e
AS		 4763 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
4764 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
1791ad50 4765 rtl_ephy_init(tp, e_info_8168g_2);
57538c4a 4766}
4767
45dd95c4 4768static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
4769{
45dd95c4 4770 static const struct ephy_info e_info_8411_2[] = {
a7a92cf8
HK		 4771 { 0x00, 0x0008, 0x0000 },
4772 { 0x0c, 0x37d0, 0x0820 },
4773 { 0x1e, 0x0000, 0x0001 },
4774 { 0x19, 0x8021, 0x0000 },
4775 { 0x1e, 0x0000, 0x2000 },
4776 { 0x0d, 0x0100, 0x0200 },
4777 { 0x00, 0x0000, 0x0080 },
4778 { 0x06, 0x0000, 0x0010 },
4779 { 0x04, 0x0000, 0x0010 },
4780 { 0x1d, 0x0000, 0x4000 },
45dd95c4 4781 };
4782
5fbea337 4783 rtl_hw_start_8168g(tp);
45dd95c4 4784
4785 /* disable aspm and clock request before access ephy */
a99790bf 4786 rtl_hw_aspm_clkreq_enable(tp, false);
1791ad50 4787 rtl_ephy_init(tp, e_info_8411_2);
fe4e8db0
HK		 4788
4789 /* The following Realtek-provided magic fixes an issue with the RX unit
4790 * getting confused after the PHY having been powered-down.
4791 */
4792 r8168_mac_ocp_write(tp, 0xFC28, 0x0000);
4793 r8168_mac_ocp_write(tp, 0xFC2A, 0x0000);
4794 r8168_mac_ocp_write(tp, 0xFC2C, 0x0000);
4795 r8168_mac_ocp_write(tp, 0xFC2E, 0x0000);
4796 r8168_mac_ocp_write(tp, 0xFC30, 0x0000);
4797 r8168_mac_ocp_write(tp, 0xFC32, 0x0000);
4798 r8168_mac_ocp_write(tp, 0xFC34, 0x0000);
4799 r8168_mac_ocp_write(tp, 0xFC36, 0x0000);
4800 mdelay(3);
4801 r8168_mac_ocp_write(tp, 0xFC26, 0x0000);
4802
4803 r8168_mac_ocp_write(tp, 0xF800, 0xE008);
4804 r8168_mac_ocp_write(tp, 0xF802, 0xE00A);
4805 r8168_mac_ocp_write(tp, 0xF804, 0xE00C);
4806 r8168_mac_ocp_write(tp, 0xF806, 0xE00E);
4807 r8168_mac_ocp_write(tp, 0xF808, 0xE027);
4808 r8168_mac_ocp_write(tp, 0xF80A, 0xE04F);
4809 r8168_mac_ocp_write(tp, 0xF80C, 0xE05E);
4810 r8168_mac_ocp_write(tp, 0xF80E, 0xE065);
4811 r8168_mac_ocp_write(tp, 0xF810, 0xC602);
4812 r8168_mac_ocp_write(tp, 0xF812, 0xBE00);
4813 r8168_mac_ocp_write(tp, 0xF814, 0x0000);
4814 r8168_mac_ocp_write(tp, 0xF816, 0xC502);
4815 r8168_mac_ocp_write(tp, 0xF818, 0xBD00);
4816 r8168_mac_ocp_write(tp, 0xF81A, 0x074C);
4817 r8168_mac_ocp_write(tp, 0xF81C, 0xC302);
4818 r8168_mac_ocp_write(tp, 0xF81E, 0xBB00);
4819 r8168_mac_ocp_write(tp, 0xF820, 0x080A);
4820 r8168_mac_ocp_write(tp, 0xF822, 0x6420);
4821 r8168_mac_ocp_write(tp, 0xF824, 0x48C2);
4822 r8168_mac_ocp_write(tp, 0xF826, 0x8C20);
4823 r8168_mac_ocp_write(tp, 0xF828, 0xC516);
4824 r8168_mac_ocp_write(tp, 0xF82A, 0x64A4);
4825 r8168_mac_ocp_write(tp, 0xF82C, 0x49C0);
4826 r8168_mac_ocp_write(tp, 0xF82E, 0xF009);
4827 r8168_mac_ocp_write(tp, 0xF830, 0x74A2);
4828 r8168_mac_ocp_write(tp, 0xF832, 0x8CA5);
4829 r8168_mac_ocp_write(tp, 0xF834, 0x74A0);
4830 r8168_mac_ocp_write(tp, 0xF836, 0xC50E);
4831 r8168_mac_ocp_write(tp, 0xF838, 0x9CA2);
4832 r8168_mac_ocp_write(tp, 0xF83A, 0x1C11);
4833 r8168_mac_ocp_write(tp, 0xF83C, 0x9CA0);
4834 r8168_mac_ocp_write(tp, 0xF83E, 0xE006);
4835 r8168_mac_ocp_write(tp, 0xF840, 0x74F8);
4836 r8168_mac_ocp_write(tp, 0xF842, 0x48C4);
4837 r8168_mac_ocp_write(tp, 0xF844, 0x8CF8);
4838 r8168_mac_ocp_write(tp, 0xF846, 0xC404);
4839 r8168_mac_ocp_write(tp, 0xF848, 0xBC00);
4840 r8168_mac_ocp_write(tp, 0xF84A, 0xC403);
4841 r8168_mac_ocp_write(tp, 0xF84C, 0xBC00);
4842 r8168_mac_ocp_write(tp, 0xF84E, 0x0BF2);
4843 r8168_mac_ocp_write(tp, 0xF850, 0x0C0A);
4844 r8168_mac_ocp_write(tp, 0xF852, 0xE434);
4845 r8168_mac_ocp_write(tp, 0xF854, 0xD3C0);
4846 r8168_mac_ocp_write(tp, 0xF856, 0x49D9);
4847 r8168_mac_ocp_write(tp, 0xF858, 0xF01F);
4848 r8168_mac_ocp_write(tp, 0xF85A, 0xC526);
4849 r8168_mac_ocp_write(tp, 0xF85C, 0x64A5);
4850 r8168_mac_ocp_write(tp, 0xF85E, 0x1400);
4851 r8168_mac_ocp_write(tp, 0xF860, 0xF007);
4852 r8168_mac_ocp_write(tp, 0xF862, 0x0C01);
4853 r8168_mac_ocp_write(tp, 0xF864, 0x8CA5);
4854 r8168_mac_ocp_write(tp, 0xF866, 0x1C15);
4855 r8168_mac_ocp_write(tp, 0xF868, 0xC51B);
4856 r8168_mac_ocp_write(tp, 0xF86A, 0x9CA0);
4857 r8168_mac_ocp_write(tp, 0xF86C, 0xE013);
4858 r8168_mac_ocp_write(tp, 0xF86E, 0xC519);
4859 r8168_mac_ocp_write(tp, 0xF870, 0x74A0);
4860 r8168_mac_ocp_write(tp, 0xF872, 0x48C4);
4861 r8168_mac_ocp_write(tp, 0xF874, 0x8CA0);
4862 r8168_mac_ocp_write(tp, 0xF876, 0xC516);
4863 r8168_mac_ocp_write(tp, 0xF878, 0x74A4);
4864 r8168_mac_ocp_write(tp, 0xF87A, 0x48C8);
4865 r8168_mac_ocp_write(tp, 0xF87C, 0x48CA);
4866 r8168_mac_ocp_write(tp, 0xF87E, 0x9CA4);
4867 r8168_mac_ocp_write(tp, 0xF880, 0xC512);
4868 r8168_mac_ocp_write(tp, 0xF882, 0x1B00);
4869 r8168_mac_ocp_write(tp, 0xF884, 0x9BA0);
4870 r8168_mac_ocp_write(tp, 0xF886, 0x1B1C);
4871 r8168_mac_ocp_write(tp, 0xF888, 0x483F);
4872 r8168_mac_ocp_write(tp, 0xF88A, 0x9BA2);
4873 r8168_mac_ocp_write(tp, 0xF88C, 0x1B04);
4874 r8168_mac_ocp_write(tp, 0xF88E, 0xC508);
4875 r8168_mac_ocp_write(tp, 0xF890, 0x9BA0);
4876 r8168_mac_ocp_write(tp, 0xF892, 0xC505);
4877 r8168_mac_ocp_write(tp, 0xF894, 0xBD00);
4878 r8168_mac_ocp_write(tp, 0xF896, 0xC502);
4879 r8168_mac_ocp_write(tp, 0xF898, 0xBD00);
4880 r8168_mac_ocp_write(tp, 0xF89A, 0x0300);
4881 r8168_mac_ocp_write(tp, 0xF89C, 0x051E);
4882 r8168_mac_ocp_write(tp, 0xF89E, 0xE434);
4883 r8168_mac_ocp_write(tp, 0xF8A0, 0xE018);
4884 r8168_mac_ocp_write(tp, 0xF8A2, 0xE092);
4885 r8168_mac_ocp_write(tp, 0xF8A4, 0xDE20);
4886 r8168_mac_ocp_write(tp, 0xF8A6, 0xD3C0);
4887 r8168_mac_ocp_write(tp, 0xF8A8, 0xC50F);
4888 r8168_mac_ocp_write(tp, 0xF8AA, 0x76A4);
4889 r8168_mac_ocp_write(tp, 0xF8AC, 0x49E3);
4890 r8168_mac_ocp_write(tp, 0xF8AE, 0xF007);
4891 r8168_mac_ocp_write(tp, 0xF8B0, 0x49C0);
4892 r8168_mac_ocp_write(tp, 0xF8B2, 0xF103);
4893 r8168_mac_ocp_write(tp, 0xF8B4, 0xC607);
4894 r8168_mac_ocp_write(tp, 0xF8B6, 0xBE00);
4895 r8168_mac_ocp_write(tp, 0xF8B8, 0xC606);
4896 r8168_mac_ocp_write(tp, 0xF8BA, 0xBE00);
4897 r8168_mac_ocp_write(tp, 0xF8BC, 0xC602);
4898 r8168_mac_ocp_write(tp, 0xF8BE, 0xBE00);
4899 r8168_mac_ocp_write(tp, 0xF8C0, 0x0C4C);
4900 r8168_mac_ocp_write(tp, 0xF8C2, 0x0C28);
4901 r8168_mac_ocp_write(tp, 0xF8C4, 0x0C2C);
4902 r8168_mac_ocp_write(tp, 0xF8C6, 0xDC00);
4903 r8168_mac_ocp_write(tp, 0xF8C8, 0xC707);
4904 r8168_mac_ocp_write(tp, 0xF8CA, 0x1D00);
4905 r8168_mac_ocp_write(tp, 0xF8CC, 0x8DE2);
4906 r8168_mac_ocp_write(tp, 0xF8CE, 0x48C1);
4907 r8168_mac_ocp_write(tp, 0xF8D0, 0xC502);
4908 r8168_mac_ocp_write(tp, 0xF8D2, 0xBD00);
4909 r8168_mac_ocp_write(tp, 0xF8D4, 0x00AA);
4910 r8168_mac_ocp_write(tp, 0xF8D6, 0xE0C0);
4911 r8168_mac_ocp_write(tp, 0xF8D8, 0xC502);
4912 r8168_mac_ocp_write(tp, 0xF8DA, 0xBD00);
4913 r8168_mac_ocp_write(tp, 0xF8DC, 0x0132);
4914
4915 r8168_mac_ocp_write(tp, 0xFC26, 0x8000);
4916
4917 r8168_mac_ocp_write(tp, 0xFC2A, 0x0743);
4918 r8168_mac_ocp_write(tp, 0xFC2C, 0x0801);
4919 r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9);
4920 r8168_mac_ocp_write(tp, 0xFC30, 0x02FD);
4921 r8168_mac_ocp_write(tp, 0xFC32, 0x0C25);
4922 r8168_mac_ocp_write(tp, 0xFC34, 0x00A9);
4923 r8168_mac_ocp_write(tp, 0xFC36, 0x012D);
4924
a99790bf 4925 rtl_hw_aspm_clkreq_enable(tp, true);
45dd95c4 4926}
4927
6e1d0b89
CHL		 4928static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
4929{
6e1d0b89
CHL		 4930 static const struct ephy_info e_info_8168h_1[] = {
4931 { 0x1e, 0x0800, 0x0001 },
4932 { 0x1d, 0x0000, 0x0800 },
4933 { 0x05, 0xffff, 0x2089 },
4934 { 0x06, 0xffff, 0x5881 },
a7a92cf8 4935 { 0x04, 0xffff, 0x854a },
6e1d0b89
CHL		 4936 { 0x01, 0xffff, 0x068b }
4937 };
ef712ede 4938 int rg_saw_cnt;
6e1d0b89
CHL		 4939
4940 /* disable aspm and clock request before access ephy */
a99790bf 4941 rtl_hw_aspm_clkreq_enable(tp, false);
1791ad50 4942 rtl_ephy_init(tp, e_info_8168h_1);
6e1d0b89 4943
6b1bd242 4944 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
0ebacd12 4945 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
6e1d0b89 4946
f37658da 4947 rtl_set_def_aspm_entry_latency(tp);
6e1d0b89 4948
8d98aa39 4949 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
6e1d0b89 4950
4e7e4621 4951 rtl_reset_packet_filter(tp);
6e1d0b89 4952
e719b3ea 4953 rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_1111, BIT(4));
6e1d0b89 4954
e719b3ea 4955 rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f00);
6e1d0b89 4956
724c6fd0 4957 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
6e1d0b89 4958
1ef7286e 4959 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
6e1d0b89 4960
724c6fd0
HK		 4961 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4962 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
6e1d0b89 4963
df6f1856
HK		 4964 rtl8168_config_eee_mac(tp);
4965
1ef7286e
AS		 4966 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
4967 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
6e1d0b89 4968
1ef7286e 4969 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
6e1d0b89 4970
e719b3ea 4971 rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12));
6e1d0b89 4972
c259b7f4 4973 rtl_pcie_state_l2l3_disable(tp);
6e1d0b89
CHL		 4974
4975 rtl_writephy(tp, 0x1f, 0x0c42);
58493333 4976 rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff);
6e1d0b89
CHL		 4977 rtl_writephy(tp, 0x1f, 0x0000);
4978 if (rg_saw_cnt > 0) {
4979 u16 sw_cnt_1ms_ini;
4980
4981 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
4982 sw_cnt_1ms_ini &= 0x0fff;
ef712ede 4983 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini);
6e1d0b89
CHL		 4984 }
4985
ef712ede
HK		 4986 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070);
4987 r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008);
4988 r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f);
4989 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f);
6e1d0b89
CHL		 4990
4991 r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
4992 r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
4993 r8168_mac_ocp_write(tp, 0xc094, 0x0000);
4994 r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
a99790bf
KHF		 4995
4996 rtl_hw_aspm_clkreq_enable(tp, true);
6e1d0b89
CHL		 4997}
4998
935e2218
CHL		 4999static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
5000{
003609da
CHL		 5001 rtl8168ep_stop_cmac(tp);
5002
6b1bd242 5003 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
0ebacd12 5004 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
935e2218 5005
f37658da 5006 rtl_set_def_aspm_entry_latency(tp);
935e2218 5007
8d98aa39 5008 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
935e2218 5009
4e7e4621 5010 rtl_reset_packet_filter(tp);
935e2218 5011
e719b3ea 5012 rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f80);
935e2218 5013
724c6fd0 5014 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
935e2218 5015
1ef7286e 5016 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
935e2218 5017
724c6fd0
HK		 5018 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
5019 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
935e2218 5020
df6f1856
HK		 5021 rtl8168_config_eee_mac(tp);
5022
724c6fd0 5023 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06);
935e2218 5024
1ef7286e 5025 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
935e2218 5026
c259b7f4 5027 rtl_pcie_state_l2l3_disable(tp);
935e2218
CHL		 5028}
5029
5030static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
5031{
935e2218
CHL		 5032 static const struct ephy_info e_info_8168ep_1[] = {
5033 { 0x00, 0xffff, 0x10ab },
5034 { 0x06, 0xffff, 0xf030 },
5035 { 0x08, 0xffff, 0x2006 },
5036 { 0x0d, 0xffff, 0x1666 },
5037 { 0x0c, 0x3ff0, 0x0000 }
5038 };
5039
5040 /* disable aspm and clock request before access ephy */
a99790bf 5041 rtl_hw_aspm_clkreq_enable(tp, false);
1791ad50 5042 rtl_ephy_init(tp, e_info_8168ep_1);
935e2218
CHL		 5043
5044 rtl_hw_start_8168ep(tp);
a99790bf
KHF		 5045
5046 rtl_hw_aspm_clkreq_enable(tp, true);
935e2218
CHL		 5047}
5048
5049static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
5050{
935e2218
CHL		 5051 static const struct ephy_info e_info_8168ep_2[] = {
5052 { 0x00, 0xffff, 0x10a3 },
5053 { 0x19, 0xffff, 0xfc00 },
5054 { 0x1e, 0xffff, 0x20ea }
5055 };
5056
5057 /* disable aspm and clock request before access ephy */
a99790bf 5058 rtl_hw_aspm_clkreq_enable(tp, false);
1791ad50 5059 rtl_ephy_init(tp, e_info_8168ep_2);
935e2218
CHL		 5060
5061 rtl_hw_start_8168ep(tp);
5062
1ef7286e
AS		 5063 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5064 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
a99790bf
KHF		 5065
5066 rtl_hw_aspm_clkreq_enable(tp, true);
935e2218
CHL		 5067}
5068
5069static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
5070{
935e2218 5071 static const struct ephy_info e_info_8168ep_3[] = {
a7a92cf8
HK		 5072 { 0x00, 0x0000, 0x0080 },
5073 { 0x0d, 0x0100, 0x0200 },
5074 { 0x19, 0x8021, 0x0000 },
5075 { 0x1e, 0x0000, 0x2000 },
935e2218
CHL		 5076 };
5077
5078 /* disable aspm and clock request before access ephy */
a99790bf 5079 rtl_hw_aspm_clkreq_enable(tp, false);
1791ad50 5080 rtl_ephy_init(tp, e_info_8168ep_3);
935e2218
CHL		 5081
5082 rtl_hw_start_8168ep(tp);
5083
1ef7286e
AS		 5084 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5085 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
935e2218 5086
ef712ede
HK		 5087 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271);
5088 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000);
5089 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080);
a99790bf
KHF		 5090
5091 rtl_hw_aspm_clkreq_enable(tp, true);
935e2218
CHL		 5092}
5093
2e13d773
HK		 5094static void rtl_hw_start_8117(struct rtl8169_private *tp)
5095{
5096 static const struct ephy_info e_info_8117[] = {
5097 { 0x19, 0x0040, 0x1100 },
5098 { 0x59, 0x0040, 0x1100 },
5099 };
5100 int rg_saw_cnt;
5101
5102 rtl8168ep_stop_cmac(tp);
5103
5104 /* disable aspm and clock request before access ephy */
5105 rtl_hw_aspm_clkreq_enable(tp, false);
5106 rtl_ephy_init(tp, e_info_8117);
5107
5108 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
5109 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
5110
5111 rtl_set_def_aspm_entry_latency(tp);
5112
5113 rtl_reset_packet_filter(tp);
5114
5115 rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f90);
5116
5117 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
5118
5119 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5120
5121 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
5122 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
5123
5124 rtl8168_config_eee_mac(tp);
5125
5126 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5127 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5128
5129 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
5130
5131 rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12));
5132
5133 rtl_pcie_state_l2l3_disable(tp);
5134
5135 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff;
5136 if (rg_saw_cnt > 0) {
5137 u16 sw_cnt_1ms_ini;
5138
5139 sw_cnt_1ms_ini = (16000000 / rg_saw_cnt) & 0x0fff;
5140 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini);
5141 }
5142
5143 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070);
5144 r8168_mac_ocp_write(tp, 0xea80, 0x0003);
5145 r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009);
5146 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f);
5147
5148 r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
5149 r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
5150 r8168_mac_ocp_write(tp, 0xc094, 0x0000);
5151 r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
5152
6e526a7f
HK		 5153 /* firmware is for MAC only */
5154 rtl_apply_firmware(tp);
5155
2e13d773
HK		 5156 rtl_hw_aspm_clkreq_enable(tp, true);
5157}
5158
beb1fe18 5159static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
2857ffb7 5160{
350f7596 5161 static const struct ephy_info e_info_8102e_1[] = {
2857ffb7
FR		 5162 { 0x01, 0, 0x6e65 },
5163 { 0x02, 0, 0x091f },
5164 { 0x03, 0, 0xc2f9 },
5165 { 0x06, 0, 0xafb5 },
5166 { 0x07, 0, 0x0e00 },
5167 { 0x19, 0, 0xec80 },
5168 { 0x01, 0, 0x2e65 },
5169 { 0x01, 0, 0x6e65 }
5170 };
5171 u8 cfg1;
5172
f37658da 5173 rtl_set_def_aspm_entry_latency(tp);
2857ffb7 5174
1ef7286e 5175 RTL_W8(tp, DBG_REG, FIX_NAK_1);
2857ffb7 5176
8d98aa39 5177 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
2857ffb7 5178
1ef7286e 5179 RTL_W8(tp, Config1,
2857ffb7 5180 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
1ef7286e 5181 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2857ffb7 5182
1ef7286e 5183 cfg1 = RTL_R8(tp, Config1);
2857ffb7 5184 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
1ef7286e 5185 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
2857ffb7 5186
1791ad50 5187 rtl_ephy_init(tp, e_info_8102e_1);
2857ffb7
FR		 5188}
5189
beb1fe18 5190static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
2857ffb7 5191{
f37658da 5192 rtl_set_def_aspm_entry_latency(tp);
2857ffb7 5193
8d98aa39 5194 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
2857ffb7 5195
1ef7286e
AS		 5196 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
5197 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2857ffb7
FR		 5198}
5199
beb1fe18 5200static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
2857ffb7 5201{
beb1fe18 5202 rtl_hw_start_8102e_2(tp);
2857ffb7 5203
fdf6fc06 5204 rtl_ephy_write(tp, 0x03, 0xc2f9);
2857ffb7
FR		 5205}
5206
beb1fe18 5207static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5a5e4443
HW		 5208{
5209 static const struct ephy_info e_info_8105e_1[] = {
5210 { 0x07, 0, 0x4000 },
5211 { 0x19, 0, 0x0200 },
5212 { 0x19, 0, 0x0020 },
5213 { 0x1e, 0, 0x2000 },
5214 { 0x03, 0, 0x0001 },
5215 { 0x19, 0, 0x0100 },
5216 { 0x19, 0, 0x0004 },
5217 { 0x0a, 0, 0x0020 }
5218 };
5219
cecb5fd7 5220 /* Force LAN exit from ASPM if Rx/Tx are not idle */
1ef7286e 5221 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5a5e4443 5222
cecb5fd7 5223 /* Disable Early Tally Counter */
1ef7286e 5224 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
5a5e4443 5225
1ef7286e
AS		 5226 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5227 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5a5e4443 5228
1791ad50 5229 rtl_ephy_init(tp, e_info_8105e_1);
b51ecea8 5230
c259b7f4 5231 rtl_pcie_state_l2l3_disable(tp);
5a5e4443
HW		 5232}
5233
beb1fe18 5234static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5a5e4443 5235{
beb1fe18 5236 rtl_hw_start_8105e_1(tp);
fdf6fc06 5237 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5a5e4443
HW		 5238}
5239
7e18dca1
HW		 5240static void rtl_hw_start_8402(struct rtl8169_private *tp)
5241{
7e18dca1
HW		 5242 static const struct ephy_info e_info_8402[] = {
5243 { 0x19, 0xffff, 0xff64 },
5244 { 0x1e, 0, 0x4000 }
5245 };
5246
f37658da 5247 rtl_set_def_aspm_entry_latency(tp);
7e18dca1
HW		 5248
5249 /* Force LAN exit from ASPM if Rx/Tx are not idle */
1ef7286e 5250 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
7e18dca1 5251
1ef7286e 5252 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
7e18dca1 5253
1791ad50 5254 rtl_ephy_init(tp, e_info_8402);
7e18dca1 5255
8d98aa39 5256 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
7e18dca1 5257
6b1bd242 5258 rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06);
4e7e4621 5259 rtl_reset_packet_filter(tp);
724c6fd0
HK		 5260 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
5261 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
5262 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00);
b51ecea8 5263
c259b7f4 5264 rtl_pcie_state_l2l3_disable(tp);
7e18dca1
HW		 5265}
5266
5598bfe5
HW		 5267static void rtl_hw_start_8106(struct rtl8169_private *tp)
5268{
0866cd15
KHF		 5269 rtl_hw_aspm_clkreq_enable(tp, false);
5270
5598bfe5 5271 /* Force LAN exit from ASPM if Rx/Tx are not idle */
1ef7286e 5272 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5598bfe5 5273
1ef7286e
AS		 5274 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
5275 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5276 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
b51ecea8 5277
c259b7f4 5278 rtl_pcie_state_l2l3_disable(tp);
0866cd15 5279 rtl_hw_aspm_clkreq_enable(tp, true);
5598bfe5
HW		 5280}
5281
f1bce4ad
HK		 5282DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond)
5283{
5284 return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13);
5285}
5286
5287static void rtl_hw_start_8125_common(struct rtl8169_private *tp)
5288{
5289 rtl_pcie_state_l2l3_disable(tp);
5290
5291 RTL_W16(tp, 0x382, 0x221b);
5292 RTL_W8(tp, 0x4500, 0);
5293 RTL_W16(tp, 0x4800, 0);
5294
5295 /* disable UPS */
5296 r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000);
5297
5298 RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10);
5299
5300 r8168_mac_ocp_write(tp, 0xc140, 0xffff);
5301 r8168_mac_ocp_write(tp, 0xc142, 0xffff);
5302
5303 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9);
5304 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000);
5305 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080);
5306
5307 /* disable new tx descriptor format */
5308 r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000);
5309
5310 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400);
5311 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020);
5312 r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c);
5313 r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033);
5314 r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040);
5315 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030);
5316 r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000);
5317 r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403);
5318 r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0067);
5319 r8168_mac_ocp_modify(tp, 0xc0ac, 0x0080, 0x1f00);
5320 r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f);
5321 r8168_mac_ocp_modify(tp, 0xe84c, 0x0000, 0x00c0);
5322 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000);
5323 r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001);
5324 udelay(1);
5325 r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000);
5326 RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030);
5327
5328 r8168_mac_ocp_write(tp, 0xe098, 0xc302);
5329
5330 rtl_udelay_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10);
5331
b3a42e3a
HK		 5332 rtl8125_config_eee_mac(tp);
5333
f1bce4ad
HK		 5334 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5335 udelay(10);
5336}
5337
5338static void rtl_hw_start_8125_1(struct rtl8169_private *tp)
5339{
5340 static const struct ephy_info e_info_8125_1[] = {
5341 { 0x01, 0xffff, 0xa812 },
5342 { 0x09, 0xffff, 0x520c },
5343 { 0x04, 0xffff, 0xd000 },
5344 { 0x0d, 0xffff, 0xf702 },
5345 { 0x0a, 0xffff, 0x8653 },
5346 { 0x06, 0xffff, 0x001e },
5347 { 0x08, 0xffff, 0x3595 },
5348 { 0x20, 0xffff, 0x9455 },
5349 { 0x21, 0xffff, 0x99ff },
5350 { 0x02, 0xffff, 0x6046 },
5351 { 0x29, 0xffff, 0xfe00 },
5352 { 0x23, 0xffff, 0xab62 },
5353
5354 { 0x41, 0xffff, 0xa80c },
5355 { 0x49, 0xffff, 0x520c },
5356 { 0x44, 0xffff, 0xd000 },
5357 { 0x4d, 0xffff, 0xf702 },
5358 { 0x4a, 0xffff, 0x8653 },
5359 { 0x46, 0xffff, 0x001e },
5360 { 0x48, 0xffff, 0x3595 },
5361 { 0x60, 0xffff, 0x9455 },
5362 { 0x61, 0xffff, 0x99ff },
5363 { 0x42, 0xffff, 0x6046 },
5364 { 0x69, 0xffff, 0xfe00 },
5365 { 0x63, 0xffff, 0xab62 },
5366 };
5367
5368 rtl_set_def_aspm_entry_latency(tp);
5369
5370 /* disable aspm and clock request before access ephy */
5371 rtl_hw_aspm_clkreq_enable(tp, false);
5372 rtl_ephy_init(tp, e_info_8125_1);
5373
5374 rtl_hw_start_8125_common(tp);
5375}
5376
5377static void rtl_hw_start_8125_2(struct rtl8169_private *tp)
5378{
5379 static const struct ephy_info e_info_8125_2[] = {
5380 { 0x04, 0xffff, 0xd000 },
5381 { 0x0a, 0xffff, 0x8653 },
5382 { 0x23, 0xffff, 0xab66 },
5383 { 0x20, 0xffff, 0x9455 },
5384 { 0x21, 0xffff, 0x99ff },
5385 { 0x29, 0xffff, 0xfe04 },
5386
5387 { 0x44, 0xffff, 0xd000 },
5388 { 0x4a, 0xffff, 0x8653 },
5389 { 0x63, 0xffff, 0xab66 },
5390 { 0x60, 0xffff, 0x9455 },
5391 { 0x61, 0xffff, 0x99ff },
5392 { 0x69, 0xffff, 0xfe04 },
5393 };
5394
5395 rtl_set_def_aspm_entry_latency(tp);
5396
5397 /* disable aspm and clock request before access ephy */
5398 rtl_hw_aspm_clkreq_enable(tp, false);
5399 rtl_ephy_init(tp, e_info_8125_2);
5400
5401 rtl_hw_start_8125_common(tp);
5402}
5403
8344ffff
HK		 5404static void rtl_hw_config(struct rtl8169_private *tp)
5405{
5406 static const rtl_generic_fct hw_configs[] = {
5407 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1,
5408 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3,
5409 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2,
5410 [RTL_GIGA_MAC_VER_10] = NULL,
5411 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168bb,
5412 [RTL_GIGA_MAC_VER_12] = rtl_hw_start_8168bef,
5413 [RTL_GIGA_MAC_VER_13] = NULL,
5414 [RTL_GIGA_MAC_VER_14] = NULL,
5415 [RTL_GIGA_MAC_VER_15] = NULL,
5416 [RTL_GIGA_MAC_VER_16] = NULL,
5417 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168bef,
5418 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1,
5419 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1,
5420 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2,
5421 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_3,
5422 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4,
5423 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2,
5424 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3,
5425 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d,
5426 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d,
5427 [RTL_GIGA_MAC_VER_27] = rtl_hw_start_8168d,
5428 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4,
5429 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1,
5430 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2,
5431 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168dp,
5432 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1,
5433 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1,
5434 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2,
5435 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1,
5436 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1,
5437 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402,
5438 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411,
5439 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106,
5440 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1,
5441 [RTL_GIGA_MAC_VER_41] = rtl_hw_start_8168g_1,
5442 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2,
5443 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2,
5444 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2,
5445 [RTL_GIGA_MAC_VER_45] = rtl_hw_start_8168h_1,
5446 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1,
5447 [RTL_GIGA_MAC_VER_47] = rtl_hw_start_8168h_1,
5448 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1,
5449 [RTL_GIGA_MAC_VER_49] = rtl_hw_start_8168ep_1,
5450 [RTL_GIGA_MAC_VER_50] = rtl_hw_start_8168ep_2,
5451 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3,
2e13d773 5452 [RTL_GIGA_MAC_VER_52] = rtl_hw_start_8117,
f1bce4ad
HK		 5453 [RTL_GIGA_MAC_VER_60] = rtl_hw_start_8125_1,
5454 [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125_2,
8344ffff
HK		 5455 };
5456
5457 if (hw_configs[tp->mac_version])
5458 hw_configs[tp->mac_version](tp);
5459}
5460
f1bce4ad
HK		 5461static void rtl_hw_start_8125(struct rtl8169_private *tp)
5462{
5463 int i;
5464
5465 /* disable interrupt coalescing */
5466 for (i = 0xa00; i < 0xb00; i += 4)
5467 RTL_W32(tp, i, 0);
5468
5469 rtl_hw_config(tp);
5470}
5471
8344ffff 5472static void rtl_hw_start_8168(struct rtl8169_private *tp)
07ce4064 5473{
cecb5fd7 5474 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
7d7903b2 5475 tp->mac_version == RTL_GIGA_MAC_VER_16)
61cb532d 5476 pcie_capability_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
8200bc72 5477 PCI_EXP_DEVCTL_NOSNOOP_EN);
cdf1a608 5478
272b2265
HK		 5479 if (rtl_is_8168evl_up(tp))
5480 RTL_W8(tp, MaxTxPacketSize, EarlySize);
5481 else
5482 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
1a964649 5483
8344ffff 5484 rtl_hw_config(tp);
bcf2b868
HK		 5485
5486 /* disable interrupt coalescing */
5487 RTL_W16(tp, IntrMitigate, 0x0000);
1da177e4
LT		 5488}
5489
6c19156e
HK		 5490static void rtl_hw_start_8169(struct rtl8169_private *tp)
5491{
5492 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
5493 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
5494
5495 RTL_W8(tp, EarlyTxThres, NoEarlyTx);
5496
5497 tp->cp_cmd |= PCIMulRW;
5498
5499 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5500 tp->mac_version == RTL_GIGA_MAC_VER_03) {
5501 netif_dbg(tp, drv, tp->dev,
5502 "Set MAC Reg C+CR Offset 0xe0. Bit 3 and Bit 14 MUST be 1\n");
5503 tp->cp_cmd |= (1 << 14);
5504 }
5505
5506 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5507
5508 rtl8169_set_magic_reg(tp, tp->mac_version);
5509
5510 RTL_W32(tp, RxMissed, 0);
bcf2b868
HK		 5511
5512 /* disable interrupt coalescing */
5513 RTL_W16(tp, IntrMitigate, 0x0000);
6c19156e
HK		 5514}
5515
5516static void rtl_hw_start(struct rtl8169_private *tp)
5517{
5518 rtl_unlock_config_regs(tp);
5519
5520 tp->cp_cmd &= CPCMD_MASK;
5521 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5522
5523 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
5524 rtl_hw_start_8169(tp);
f1bce4ad
HK		 5525 else if (rtl_is_8125(tp))
5526 rtl_hw_start_8125(tp);
6c19156e
HK		 5527 else
5528 rtl_hw_start_8168(tp);
5529
5530 rtl_set_rx_max_size(tp);
5531 rtl_set_rx_tx_desc_registers(tp);
5532 rtl_lock_config_regs(tp);
5533
4ebcb113
HK		 5534 rtl_jumbo_config(tp, tp->dev->mtu);
5535
6c19156e 5536 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
7366016d 5537 RTL_R16(tp, CPlusCmd);
6c19156e
HK		 5538 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
5539 rtl_init_rxcfg(tp);
5540 rtl_set_tx_config_registers(tp);
6c19156e 5541 rtl_set_rx_mode(tp->dev);
6c19156e
HK		 5542 rtl_irq_enable(tp);
5543}
5544
1da177e4
LT		 5545static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5546{
d58d46b5
FR		 5547 struct rtl8169_private *tp = netdev_priv(dev);
5548
4ebcb113 5549 rtl_jumbo_config(tp, new_mtu);
d58d46b5 5550
1da177e4 5551 dev->mtu = new_mtu;
350fb32a
MM		 5552 netdev_update_features(dev);
5553
323bb685 5554 return 0;
1da177e4
LT		 5555}
5556
5557static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5558{
95e0918d 5559 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
1da177e4
LT		 5560 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5561}
5562
1d0254dd 5563static inline void rtl8169_mark_to_asic(struct RxDesc *desc)
1da177e4
LT		 5564{
5565 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5566
a0750138
AD		 5567 /* Force memory writes to complete before releasing descriptor */
5568 dma_wmb();
5569
1d0254dd 5570 desc->opts1 = cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE);
1da177e4
LT		 5571}
5572
32879f00
HK		 5573static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5574 struct RxDesc *desc)
1da177e4 5575{
1e1205b7 5576 struct device *d = tp_to_dev(tp);
d3b404c2 5577 int node = dev_to_node(d);
32879f00
HK		 5578 dma_addr_t mapping;
5579 struct page *data;
1da177e4 5580
32879f00 5581 data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE));
6f0333b8
ED		 5582 if (!data)
5583 return NULL;
e9f63f30 5584
32879f00 5585 mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
d827d86b
SG		 5586 if (unlikely(dma_mapping_error(d, mapping))) {
5587 if (net_ratelimit())
5588 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
32879f00
HK		 5589 __free_pages(data, get_order(R8169_RX_BUF_SIZE));
5590 return NULL;
d827d86b 5591 }
1da177e4 5592
d731af78
HK		 5593 desc->addr = cpu_to_le64(mapping);
5594 rtl8169_mark_to_asic(desc);
3eafe507 5595
32879f00 5596 return data;
1da177e4
LT		 5597}
5598
5599static void rtl8169_rx_clear(struct rtl8169_private *tp)
5600{
07d3f51f 5601 unsigned int i;
1da177e4 5602
eb2e7f09
HK		 5603 for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) {
5604 dma_unmap_page(tp_to_dev(tp),
5605 le64_to_cpu(tp->RxDescArray[i].addr),
5606 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
5607 __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE));
5608 tp->Rx_databuff[i] = NULL;
5609 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
1da177e4
LT		 5610 }
5611}
5612
0ecbe1ca 5613static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
1da177e4 5614{
0ecbe1ca
SG		 5615 desc->opts1 |= cpu_to_le32(RingEnd);
5616}
5b0384f4 5617
0ecbe1ca
SG		 5618static int rtl8169_rx_fill(struct rtl8169_private *tp)
5619{
5620 unsigned int i;
1da177e4 5621
0ecbe1ca 5622 for (i = 0; i < NUM_RX_DESC; i++) {
32879f00 5623 struct page *data;
4ae47c2d 5624
0ecbe1ca 5625 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
6f0333b8
ED		 5626 if (!data) {
5627 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
0ecbe1ca 5628 goto err_out;
6f0333b8
ED		 5629 }
5630 tp->Rx_databuff[i] = data;
1da177e4 5631 }
1da177e4 5632
0ecbe1ca
SG		 5633 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5634 return 0;
5635
5636err_out:
5637 rtl8169_rx_clear(tp);
5638 return -ENOMEM;
1da177e4
LT		 5639}
5640
b1127e64 5641static int rtl8169_init_ring(struct rtl8169_private *tp)
1da177e4 5642{
1da177e4
LT		 5643 rtl8169_init_ring_indexes(tp);
5644
b1127e64
HK		 5645 memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
5646 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
1da177e4 5647
0ecbe1ca 5648 return rtl8169_rx_fill(tp);
1da177e4
LT		 5649}
5650
48addcc9 5651static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
1da177e4
LT		 5652 struct TxDesc *desc)
5653{
5654 unsigned int len = tx_skb->len;
5655
48addcc9
SG		 5656 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5657
1da177e4
LT		 5658 desc->opts1 = 0x00;
5659 desc->opts2 = 0x00;
5660 desc->addr = 0x00;
5661 tx_skb->len = 0;
5662}
5663
3eafe507
SG		 5664static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5665 unsigned int n)
1da177e4
LT		 5666{
5667 unsigned int i;
5668
3eafe507
SG		 5669 for (i = 0; i < n; i++) {
5670 unsigned int entry = (start + i) % NUM_TX_DESC;
1da177e4
LT		 5671 struct ring_info *tx_skb = tp->tx_skb + entry;
5672 unsigned int len = tx_skb->len;
5673
5674 if (len) {
5675 struct sk_buff *skb = tx_skb->skb;
5676
1e1205b7 5677 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
1da177e4
LT		 5678 tp->TxDescArray + entry);
5679 if (skb) {
7a4b813c 5680 dev_consume_skb_any(skb);
1da177e4
LT		 5681 tx_skb->skb = NULL;
5682 }
1da177e4
LT		 5683 }
5684 }
3eafe507
SG		 5685}
5686
5687static void rtl8169_tx_clear(struct rtl8169_private *tp)
5688{
5689 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
1da177e4 5690 tp->cur_tx = tp->dirty_tx = 0;
d92060bc 5691 netdev_reset_queue(tp->dev);
1da177e4
LT		 5692}
5693
4422bcd4 5694static void rtl_reset_work(struct rtl8169_private *tp)
1da177e4 5695{
c4028958 5696 struct net_device *dev = tp->dev;
56de414c 5697 int i;
1da177e4 5698
da78dbff
FR		 5699 napi_disable(&tp->napi);
5700 netif_stop_queue(dev);
16f11500 5701 synchronize_rcu();
1da177e4 5702
c7c2c39b 5703 rtl8169_hw_reset(tp);
5704
56de414c 5705 for (i = 0; i < NUM_RX_DESC; i++)
1d0254dd 5706 rtl8169_mark_to_asic(tp->RxDescArray + i);
56de414c 5707
1da177e4 5708 rtl8169_tx_clear(tp);
c7c2c39b 5709 rtl8169_init_ring_indexes(tp);
1da177e4 5710
da78dbff 5711 napi_enable(&tp->napi);
61cb532d 5712 rtl_hw_start(tp);
56de414c 5713 netif_wake_queue(dev);
1da177e4
LT		 5714}
5715
5716static void rtl8169_tx_timeout(struct net_device *dev)
5717{
da78dbff
FR		 5718 struct rtl8169_private *tp = netdev_priv(dev);
5719
5720 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
1da177e4
LT		 5721}
5722
734c1409
HK		 5723static __le32 rtl8169_get_txd_opts1(u32 opts0, u32 len, unsigned int entry)
5724{
5725 u32 status = opts0 | len;
5726
5727 if (entry == NUM_TX_DESC - 1)
5728 status |= RingEnd;
5729
5730 return cpu_to_le32(status);
5731}
5732
1da177e4 5733static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2b7b4318 5734 u32 *opts)
1da177e4
LT		 5735{
5736 struct skb_shared_info *info = skb_shinfo(skb);
5737 unsigned int cur_frag, entry;
6e1d0b89 5738 struct TxDesc *uninitialized_var(txd);
1e1205b7 5739 struct device *d = tp_to_dev(tp);
1da177e4
LT		 5740
5741 entry = tp->cur_tx;
5742 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
9e903e08 5743 const skb_frag_t *frag = info->frags + cur_frag;
1da177e4 5744 dma_addr_t mapping;
734c1409 5745 u32 len;
1da177e4
LT		 5746 void *addr;
5747
5748 entry = (entry + 1) % NUM_TX_DESC;
5749
5750 txd = tp->TxDescArray + entry;
9e903e08 5751 len = skb_frag_size(frag);
929f6189 5752 addr = skb_frag_address(frag);
48addcc9 5753 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
d827d86b
SG		 5754 if (unlikely(dma_mapping_error(d, mapping))) {
5755 if (net_ratelimit())
5756 netif_err(tp, drv, tp->dev,
5757 "Failed to map TX fragments DMA!\n");
3eafe507 5758 goto err_out;
d827d86b 5759 }
1da177e4 5760
734c1409 5761 txd->opts1 = rtl8169_get_txd_opts1(opts[0], len, entry);
2b7b4318 5762 txd->opts2 = cpu_to_le32(opts[1]);
1da177e4
LT		 5763 txd->addr = cpu_to_le64(mapping);
5764
5765 tp->tx_skb[entry].len = len;
5766 }
5767
5768 if (cur_frag) {
5769 tp->tx_skb[entry].skb = skb;
5770 txd->opts1 |= cpu_to_le32(LastFrag);
5771 }
5772
5773 return cur_frag;
3eafe507
SG		 5774
5775err_out:
5776 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5777 return -EIO;
1da177e4
LT		 5778}
5779
b423e9ae 5780static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
5781{
5782 return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
5783}
5784
e974604b 5785/* msdn_giant_send_check()
5786 * According to the document of microsoft, the TCP Pseudo Header excludes the
5787 * packet length for IPv6 TCP large packets.
5788 */
5789static int msdn_giant_send_check(struct sk_buff *skb)
5790{
5791 const struct ipv6hdr *ipv6h;
5792 struct tcphdr *th;
5793 int ret;
5794
5795 ret = skb_cow_head(skb, 0);
5796 if (ret)
5797 return ret;
5798
5799 ipv6h = ipv6_hdr(skb);
5800 th = tcp_hdr(skb);
5801
5802 th->check = 0;
5803 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
5804
5805 return ret;
5806}
5807
87945b6d 5808static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts)
1da177e4 5809{
350fb32a
MM		 5810 u32 mss = skb_shinfo(skb)->gso_size;
5811
2b7b4318
FR		 5812 if (mss) {
5813 opts[0] |= TD_LSO;
5888d3fc 5814 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
5815 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5816 const struct iphdr *ip = ip_hdr(skb);
5817
5818 if (ip->protocol == IPPROTO_TCP)
5819 opts[0] |= TD0_IP_CS | TD0_TCP_CS;
5820 else if (ip->protocol == IPPROTO_UDP)
5821 opts[0] |= TD0_IP_CS | TD0_UDP_CS;
5822 else
5823 WARN_ON_ONCE(1);
5824 }
5888d3fc 5825}
5826
5827static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
5828 struct sk_buff *skb, u32 *opts)
5829{
bdfa4ed6 5830 u32 transport_offset = (u32)skb_transport_offset(skb);
5888d3fc 5831 u32 mss = skb_shinfo(skb)->gso_size;
5832
5833 if (mss) {
4ff36466 5834 switch (vlan_get_protocol(skb)) {
e974604b 5835 case htons(ETH_P_IP):
5836 opts[0] |= TD1_GTSENV4;
5837 break;
5838
5839 case htons(ETH_P_IPV6):
5840 if (msdn_giant_send_check(skb))
5841 return false;
5842
5843 opts[0] |= TD1_GTSENV6;
5844 break;
5845
5846 default:
5847 WARN_ON_ONCE(1);
5848 break;
5849 }
5850
bdfa4ed6 5851 opts[0] |= transport_offset << GTTCPHO_SHIFT;
5888d3fc 5852 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
2b7b4318 5853 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
e974604b 5854 u8 ip_protocol;
1da177e4 5855
4ff36466 5856 switch (vlan_get_protocol(skb)) {
e974604b 5857 case htons(ETH_P_IP):
5858 opts[1] |= TD1_IPv4_CS;
5859 ip_protocol = ip_hdr(skb)->protocol;
5860 break;
5861
5862 case htons(ETH_P_IPV6):
5863 opts[1] |= TD1_IPv6_CS;
5864 ip_protocol = ipv6_hdr(skb)->nexthdr;
5865 break;
5866
5867 default:
5868 ip_protocol = IPPROTO_RAW;
5869 break;
5870 }
5871
5872 if (ip_protocol == IPPROTO_TCP)
5873 opts[1] |= TD1_TCP_CS;
5874 else if (ip_protocol == IPPROTO_UDP)
5875 opts[1] |= TD1_UDP_CS;
2b7b4318
FR		 5876 else
5877 WARN_ON_ONCE(1);
e974604b 5878
5879 opts[1] |= transport_offset << TCPHO_SHIFT;
b423e9ae 5880 } else {
5881 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
207c5f44 5882 return !eth_skb_pad(skb);
1da177e4 5883 }
5888d3fc 5884
b423e9ae 5885 return true;
1da177e4
LT		 5886}
5887
76085c9e
HK		 5888static bool rtl_tx_slots_avail(struct rtl8169_private *tp,
5889 unsigned int nr_frags)
5890{
5891 unsigned int slots_avail = tp->dirty_tx + NUM_TX_DESC - tp->cur_tx;
5892
5893 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
5894 return slots_avail > nr_frags;
5895}
5896
87945b6d
HK		 5897/* Versions RTL8102e and from RTL8168c onwards support csum_v2 */
5898static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp)
5899{
5900 switch (tp->mac_version) {
5901 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
5902 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
5903 return false;
5904 default:
5905 return true;
5906 }
5907}
5908
f1bce4ad
HK		 5909static void rtl8169_doorbell(struct rtl8169_private *tp)
5910{
5911 if (rtl_is_8125(tp))
5912 RTL_W16(tp, TxPoll_8125, BIT(0));
5913 else
5914 RTL_W8(tp, TxPoll, NPQ);
5915}
5916
61357325
SH		 5917static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5918 struct net_device *dev)
1da177e4
LT		 5919{
5920 struct rtl8169_private *tp = netdev_priv(dev);
3eafe507 5921 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
1da177e4 5922 struct TxDesc *txd = tp->TxDescArray + entry;
1e1205b7 5923 struct device *d = tp_to_dev(tp);
1da177e4 5924 dma_addr_t mapping;
734c1409 5925 u32 opts[2], len;
ef143585
HK		 5926 bool stop_queue;
5927 bool door_bell;
3eafe507 5928 int frags;
5b0384f4 5929
76085c9e 5930 if (unlikely(!rtl_tx_slots_avail(tp, skb_shinfo(skb)->nr_frags))) {
bf82c189 5931 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
3eafe507 5932 goto err_stop_0;
1da177e4
LT		 5933 }
5934
5935 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
3eafe507
SG		 5936 goto err_stop_0;
5937
355f948a 5938 opts[1] = rtl8169_tx_vlan_tag(skb);
b423e9ae 5939 opts[0] = DescOwn;
5940
87945b6d 5941 if (rtl_chip_supports_csum_v2(tp)) {
96ea772e
HK		 5942 if (!rtl8169_tso_csum_v2(tp, skb, opts))
5943 goto err_dma_0;
87945b6d
HK		 5944 } else {
5945 rtl8169_tso_csum_v1(skb, opts);
e974604b 5946 }
b423e9ae 5947
3eafe507 5948 len = skb_headlen(skb);
48addcc9 5949 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
d827d86b
SG		 5950 if (unlikely(dma_mapping_error(d, mapping))) {
5951 if (net_ratelimit())
5952 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
3eafe507 5953 goto err_dma_0;
d827d86b 5954 }
3eafe507
SG		 5955
5956 tp->tx_skb[entry].len = len;
5957 txd->addr = cpu_to_le64(mapping);
1da177e4 5958
2b7b4318 5959 frags = rtl8169_xmit_frags(tp, skb, opts);
3eafe507
SG		 5960 if (frags < 0)
5961 goto err_dma_1;
5962 else if (frags)
2b7b4318 5963 opts[0] |= FirstFrag;
3eafe507 5964 else {
2b7b4318 5965 opts[0] |= FirstFrag | LastFrag;
1da177e4
LT		 5966 tp->tx_skb[entry].skb = skb;
5967 }
5968
2b7b4318
FR		 5969 txd->opts2 = cpu_to_le32(opts[1]);
5970
5047fb5d
RC		 5971 skb_tx_timestamp(skb);
5972
a0750138
AD		 5973 /* Force memory writes to complete before releasing descriptor */
5974 dma_wmb();
1da177e4 5975
ef143585
HK		 5976 door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more());
5977
734c1409 5978 txd->opts1 = rtl8169_get_txd_opts1(opts[0], len, entry);
1da177e4 5979
a0750138 5980 /* Force all memory writes to complete before notifying device */
4c020a96 5981 wmb();
1da177e4 5982
a0750138
AD		 5983 tp->cur_tx += frags + 1;
5984
ef143585
HK		 5985 stop_queue = !rtl_tx_slots_avail(tp, MAX_SKB_FRAGS);
5986 if (unlikely(stop_queue)) {
0255d592
HK		 5987 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
5988 * not miss a ring update when it notices a stopped queue.
5989 */
5990 smp_wmb();
5991 netif_stop_queue(dev);
4773f9bd 5992 door_bell = true;
ef143585
HK		 5993 }
5994
5995 if (door_bell)
f1bce4ad 5996 rtl8169_doorbell(tp);
ef143585
HK		 5997
5998 if (unlikely(stop_queue)) {
ae1f23fb
FR		 5999 /* Sync with rtl_tx:
6000 * - publish queue status and cur_tx ring index (write barrier)
6001 * - refresh dirty_tx ring index (read barrier).
6002 * May the current thread have a pessimistic view of the ring
6003 * status and forget to wake up queue, a racing rtl_tx thread
6004 * can't.
6005 */
1e874e04 6006 smp_mb();
76085c9e 6007 if (rtl_tx_slots_avail(tp, MAX_SKB_FRAGS))
601ed4d6 6008 netif_start_queue(dev);
1da177e4
LT		 6009 }
6010
61357325 6011 return NETDEV_TX_OK;
1da177e4 6012
3eafe507 6013err_dma_1:
48addcc9 6014 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
3eafe507 6015err_dma_0:
989c9ba1 6016 dev_kfree_skb_any(skb);
3eafe507
SG		 6017 dev->stats.tx_dropped++;
6018 return NETDEV_TX_OK;
6019
6020err_stop_0:
1da177e4 6021 netif_stop_queue(dev);
cebf8cc7 6022 dev->stats.tx_dropped++;
61357325 6023 return NETDEV_TX_BUSY;
1da177e4
LT		 6024}
6025
e64e0c89
HK		 6026static netdev_features_t rtl8169_features_check(struct sk_buff *skb,
6027 struct net_device *dev,
6028 netdev_features_t features)
6029{
6030 int transport_offset = skb_transport_offset(skb);
6031 struct rtl8169_private *tp = netdev_priv(dev);
6032
6033 if (skb_is_gso(skb)) {
6034 if (transport_offset > GTTCPHO_MAX &&
6035 rtl_chip_supports_csum_v2(tp))
6036 features &= ~NETIF_F_ALL_TSO;
6037 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6038 if (skb->len < ETH_ZLEN) {
6039 switch (tp->mac_version) {
6040 case RTL_GIGA_MAC_VER_11:
6041 case RTL_GIGA_MAC_VER_12:
6042 case RTL_GIGA_MAC_VER_17:
6043 case RTL_GIGA_MAC_VER_34:
6044 features &= ~NETIF_F_CSUM_MASK;
6045 break;
6046 default:
6047 break;
6048 }
6049 }
6050
6051 if (transport_offset > TCPHO_MAX &&
6052 rtl_chip_supports_csum_v2(tp))
6053 features &= ~NETIF_F_CSUM_MASK;
6054 }
6055
6056 return vlan_features_check(skb, features);
6057}
6058
1da177e4
LT		 6059static void rtl8169_pcierr_interrupt(struct net_device *dev)
6060{
6061 struct rtl8169_private *tp = netdev_priv(dev);
6062 struct pci_dev *pdev = tp->pci_dev;
1da177e4
LT		 6063 u16 pci_status, pci_cmd;
6064
6065 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
6066 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
6067
bf82c189
JP		 6068 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
6069 pci_cmd, pci_status);
1da177e4
LT		 6070
6071 /*
6072 * The recovery sequence below admits a very elaborated explanation:
6073 * - it seems to work;
d03902b8
FR		 6074 * - I did not see what else could be done;
6075 * - it makes iop3xx happy.
1da177e4
LT		 6076 *
6077 * Feel free to adjust to your needs.
6078 */
a27993f3 6079 if (pdev->broken_parity_status)
d03902b8
FR		 6080 pci_cmd &= ~PCI_COMMAND_PARITY;
6081 else
6082 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
6083
6084 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 6085
6086 pci_write_config_word(pdev, PCI_STATUS,
6087 pci_status & (PCI_STATUS_DETECTED_PARITY |
6088 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
6089 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
6090
98ddf986 6091 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
1da177e4
LT		 6092}
6093
5317d5c6
HK		 6094static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp,
6095 int budget)
1da177e4 6096{
d92060bc 6097 unsigned int dirty_tx, tx_left, bytes_compl = 0, pkts_compl = 0;
1da177e4 6098
1da177e4
LT		 6099 dirty_tx = tp->dirty_tx;
6100 smp_rmb();
6101 tx_left = tp->cur_tx - dirty_tx;
6102
6103 while (tx_left > 0) {
6104 unsigned int entry = dirty_tx % NUM_TX_DESC;
6105 struct ring_info *tx_skb = tp->tx_skb + entry;
1da177e4
LT		 6106 u32 status;
6107
1da177e4
LT		 6108 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
6109 if (status & DescOwn)
6110 break;
6111
a0750138
AD		 6112 /* This barrier is needed to keep us from reading
6113 * any other fields out of the Tx descriptor until
6114 * we know the status of DescOwn
6115 */
6116 dma_rmb();
6117
1e1205b7 6118 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
48addcc9 6119 tp->TxDescArray + entry);
ae84bc18 6120 if (tx_skb->skb) {
d92060bc
FW		 6121 pkts_compl++;
6122 bytes_compl += tx_skb->skb->len;
5317d5c6 6123 napi_consume_skb(tx_skb->skb, budget);
1da177e4
LT		 6124 tx_skb->skb = NULL;
6125 }
6126 dirty_tx++;
6127 tx_left--;
6128 }
6129
6130 if (tp->dirty_tx != dirty_tx) {
d92060bc
FW		 6131 netdev_completed_queue(dev, pkts_compl, bytes_compl);
6132
6133 u64_stats_update_begin(&tp->tx_stats.syncp);
6134 tp->tx_stats.packets += pkts_compl;
6135 tp->tx_stats.bytes += bytes_compl;
6136 u64_stats_update_end(&tp->tx_stats.syncp);
6137
1da177e4 6138 tp->dirty_tx = dirty_tx;
ae1f23fb
FR		 6139 /* Sync with rtl8169_start_xmit:
6140 * - publish dirty_tx ring index (write barrier)
6141 * - refresh cur_tx ring index and queue status (read barrier)
6142 * May the current thread miss the stopped queue condition,
6143 * a racing xmit thread can only have a right view of the
6144 * ring status.
6145 */
1e874e04 6146 smp_mb();
1da177e4 6147 if (netif_queue_stopped(dev) &&
76085c9e 6148 rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) {
1da177e4
LT		 6149 netif_wake_queue(dev);
6150 }
d78ae2dc
FR		 6151 /*
6152 * 8168 hack: TxPoll requests are lost when the Tx packets are
6153 * too close. Let's kick an extra TxPoll request when a burst
6154 * of start_xmit activity is detected (if it is not detected,
6155 * it is slow enough). -- FR
6156 */
1ef7286e 6157 if (tp->cur_tx != dirty_tx)
f1bce4ad 6158 rtl8169_doorbell(tp);
1da177e4
LT		 6159 }
6160}
6161
126fa4b9
FR		 6162static inline int rtl8169_fragmented_frame(u32 status)
6163{
6164 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
6165}
6166
adea1ac7 6167static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
1da177e4 6168{
1da177e4
LT		 6169 u32 status = opts1 & RxProtoMask;
6170
6171 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
d5d3ebe3 6172 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
1da177e4
LT		 6173 skb->ip_summed = CHECKSUM_UNNECESSARY;
6174 else
bc8acf2c 6175 skb_checksum_none_assert(skb);
1da177e4
LT		 6176}
6177
da78dbff 6178static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
1da177e4
LT		 6179{
6180 unsigned int cur_rx, rx_left;
6f0333b8 6181 unsigned int count;
1da177e4 6182
1da177e4 6183 cur_rx = tp->cur_rx;
1da177e4 6184
9fba0812 6185 for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
1da177e4 6186 unsigned int entry = cur_rx % NUM_RX_DESC;
32879f00 6187 const void *rx_buf = page_address(tp->Rx_databuff[entry]);
126fa4b9 6188 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 6189 u32 status;
6190
6202806e 6191 status = le32_to_cpu(desc->opts1);
1da177e4
LT		 6192 if (status & DescOwn)
6193 break;
a0750138
AD		 6194
6195 /* This barrier is needed to keep us from reading
6196 * any other fields out of the Rx descriptor until
6197 * we know the status of DescOwn
6198 */
6199 dma_rmb();
6200
4dcb7d33 6201 if (unlikely(status & RxRES)) {
bf82c189
JP		 6202 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
6203 status);
cebf8cc7 6204 dev->stats.rx_errors++;
1da177e4 6205 if (status & (RxRWT | RxRUNT))
cebf8cc7 6206 dev->stats.rx_length_errors++;
1da177e4 6207 if (status & RxCRC)
cebf8cc7 6208 dev->stats.rx_crc_errors++;
e9588eb9
HK		 6209 if (status & (RxRUNT | RxCRC) && !(status & RxRWT) &&
6210 dev->features & NETIF_F_RXALL) {
6bbe021d 6211 goto process_pkt;
6202806e 6212 }
1da177e4 6213 } else {
fcd4e608 6214 unsigned int pkt_size;
6f0333b8 6215 struct sk_buff *skb;
6bbe021d
BG		 6216
6217process_pkt:
fcd4e608 6218 pkt_size = status & GENMASK(13, 0);
79d0c1d2 6219 if (likely(!(dev->features & NETIF_F_RXFCS)))
fcd4e608 6220 pkt_size -= ETH_FCS_LEN;
126fa4b9
FR		 6221 /*
6222 * The driver does not support incoming fragmented
6223 * frames. They are seen as a symptom of over-mtu
6224 * sized frames.
6225 */
6226 if (unlikely(rtl8169_fragmented_frame(status))) {
cebf8cc7
FR		 6227 dev->stats.rx_dropped++;
6228 dev->stats.rx_length_errors++;
ce11ff5e 6229 goto release_descriptor;
126fa4b9
FR		 6230 }
6231
fcd4e608
HK		 6232 skb = napi_alloc_skb(&tp->napi, pkt_size);
6233 if (unlikely(!skb)) {
6f0333b8 6234 dev->stats.rx_dropped++;
ce11ff5e 6235 goto release_descriptor;
1da177e4
LT		 6236 }
6237
3c95e501
HK		 6238 dma_sync_single_for_cpu(tp_to_dev(tp),
6239 le64_to_cpu(desc->addr),
6240 pkt_size, DMA_FROM_DEVICE);
32879f00
HK		 6241 prefetch(rx_buf);
6242 skb_copy_to_linear_data(skb, rx_buf, pkt_size);
fcd4e608
HK		 6243 skb->tail += pkt_size;
6244 skb->len = pkt_size;
6245
d4ed7463
HK		 6246 dma_sync_single_for_device(tp_to_dev(tp),
6247 le64_to_cpu(desc->addr),
6248 pkt_size, DMA_FROM_DEVICE);
6249
adea1ac7 6250 rtl8169_rx_csum(skb, status);
1da177e4
LT		 6251 skb->protocol = eth_type_trans(skb, dev);
6252
7a8fc77b
FR		 6253 rtl8169_rx_vlan_tag(desc, skb);
6254
39174291 6255 if (skb->pkt_type == PACKET_MULTICAST)
6256 dev->stats.multicast++;
6257
448a2413 6258 napi_gro_receive(&tp->napi, skb);
1da177e4 6259
8027aa24
JW		 6260 u64_stats_update_begin(&tp->rx_stats.syncp);
6261 tp->rx_stats.packets++;
6262 tp->rx_stats.bytes += pkt_size;
6263 u64_stats_update_end(&tp->rx_stats.syncp);
1da177e4 6264 }
ce11ff5e 6265release_descriptor:
6266 desc->opts2 = 0;
1d0254dd 6267 rtl8169_mark_to_asic(desc);
1da177e4
LT		 6268 }
6269
6270 count = cur_rx - tp->cur_rx;
6271 tp->cur_rx = cur_rx;
6272
1da177e4
LT		 6273 return count;
6274}
6275
07d3f51f 6276static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 6277{
ebcd5daa 6278 struct rtl8169_private *tp = dev_instance;
c1d532d2 6279 u32 status = rtl_get_events(tp);
1da177e4 6280
c1d532d2
HK		 6281 if (!tp->irq_enabled || (status & 0xffff) == 0xffff ||
6282 !(status & tp->irq_mask))
05bbe558 6283 return IRQ_NONE;
1da177e4 6284
38caff5a
HK		 6285 if (unlikely(status & SYSErr)) {
6286 rtl8169_pcierr_interrupt(tp->dev);
6287 goto out;
6288 }
da78dbff 6289
703732f0
HK		 6290 if (status & LinkChg)
6291 phy_mac_interrupt(tp->phydev);
1da177e4 6292
38caff5a
HK		 6293 if (unlikely(status & RxFIFOOver &&
6294 tp->mac_version == RTL_GIGA_MAC_VER_11)) {
6295 netif_stop_queue(tp->dev);
f0ff129e 6296 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
da78dbff 6297 }
1da177e4 6298
e62b2fd5
HK		 6299 rtl_irq_disable(tp);
6300 napi_schedule_irqoff(&tp->napi);
38caff5a
HK		 6301out:
6302 rtl_ack_events(tp, status);
1da177e4 6303
38caff5a 6304 return IRQ_HANDLED;
1da177e4
LT		 6305}
6306
4422bcd4
FR		 6307static void rtl_task(struct work_struct *work)
6308{
da78dbff
FR		 6309 static const struct {
6310 int bitnr;
6311 void (*action)(struct rtl8169_private *);
6312 } rtl_work[] = {
da78dbff 6313 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work },
da78dbff 6314 };
4422bcd4
FR		 6315 struct rtl8169_private *tp =
6316 container_of(work, struct rtl8169_private, wk.work);
da78dbff
FR		 6317 struct net_device *dev = tp->dev;
6318 int i;
6319
6320 rtl_lock_work(tp);
6321
6c4a70c5
FR		 6322 if (!netif_running(dev) ||
6323 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
da78dbff
FR		 6324 goto out_unlock;
6325
6326 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
6327 bool pending;
6328
da78dbff 6329 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
da78dbff
FR		 6330 if (pending)
6331 rtl_work[i].action(tp);
6332 }
4422bcd4 6333
da78dbff
FR		 6334out_unlock:
6335 rtl_unlock_work(tp);
4422bcd4
FR		 6336}
6337
bea3348e 6338static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 6339{
bea3348e
SH		 6340 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
6341 struct net_device *dev = tp->dev;
6b839b6c 6342 int work_done;
da78dbff 6343
6b839b6c 6344 work_done = rtl_rx(dev, tp, (u32) budget);
da78dbff 6345
5317d5c6 6346 rtl_tx(dev, tp, budget);
1da177e4 6347
bea3348e 6348 if (work_done < budget) {
6ad20165 6349 napi_complete_done(napi, work_done);
fe716f8a 6350 rtl_irq_enable(tp);
1da177e4
LT		 6351 }
6352
bea3348e 6353 return work_done;
1da177e4 6354}
1da177e4 6355
1ef7286e 6356static void rtl8169_rx_missed(struct net_device *dev)
523a6094
FR		 6357{
6358 struct rtl8169_private *tp = netdev_priv(dev);
6359
6360 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
6361 return;
6362
1ef7286e
AS		 6363 dev->stats.rx_missed_errors += RTL_R32(tp, RxMissed) & 0xffffff;
6364 RTL_W32(tp, RxMissed, 0);
523a6094
FR		 6365}
6366
f1e911d5
HK		 6367static void r8169_phylink_handler(struct net_device *ndev)
6368{
6369 struct rtl8169_private *tp = netdev_priv(ndev);
6370
6371 if (netif_carrier_ok(ndev)) {
6372 rtl_link_chg_patch(tp);
6373 pm_request_resume(&tp->pci_dev->dev);
6374 } else {
6375 pm_runtime_idle(&tp->pci_dev->dev);
6376 }
6377
6378 if (net_ratelimit())
703732f0 6379 phy_print_status(tp->phydev);
f1e911d5
HK		 6380}
6381
6382static int r8169_phy_connect(struct rtl8169_private *tp)
6383{
703732f0 6384 struct phy_device *phydev = tp->phydev;
f1e911d5
HK		 6385 phy_interface_t phy_mode;
6386 int ret;
6387
f7ffa9ae 6388 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII :
f1e911d5
HK		 6389 PHY_INTERFACE_MODE_MII;
6390
6391 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler,
6392 phy_mode);
6393 if (ret)
6394 return ret;
6395
66058b1c 6396 if (!tp->supports_gmii)
f1e911d5
HK		 6397 phy_set_max_speed(phydev, SPEED_100);
6398
9cf9b84c 6399 phy_support_asym_pause(phydev);
f1e911d5
HK		 6400
6401 phy_attached_info(phydev);
6402
6403 return 0;
6404}
6405
1da177e4
LT		 6406static void rtl8169_down(struct net_device *dev)
6407{
6408 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 6409
703732f0 6410 phy_stop(tp->phydev);
f1e911d5 6411
93dd79e8 6412 napi_disable(&tp->napi);
da78dbff 6413 netif_stop_queue(dev);
1da177e4 6414
92fc43b4 6415 rtl8169_hw_reset(tp);
323bb685
SG		 6416 /*
6417 * At this point device interrupts can not be enabled in any function,
209e5ac8
FR		 6418 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
6419 * and napi is disabled (rtl8169_poll).
323bb685 6420 */
1ef7286e 6421 rtl8169_rx_missed(dev);
1da177e4 6422
1da177e4 6423 /* Give a racing hard_start_xmit a few cycles to complete. */
16f11500 6424 synchronize_rcu();
1da177e4 6425
1da177e4
LT		 6426 rtl8169_tx_clear(tp);
6427
6428 rtl8169_rx_clear(tp);
065c27c1 6429
6430 rtl_pll_power_down(tp);
1da177e4
LT		 6431}
6432
6433static int rtl8169_close(struct net_device *dev)
6434{
6435 struct rtl8169_private *tp = netdev_priv(dev);
6436 struct pci_dev *pdev = tp->pci_dev;
6437
e1759441
RW		 6438 pm_runtime_get_sync(&pdev->dev);
6439
cecb5fd7 6440 /* Update counters before going down */
e71c9ce2 6441 rtl8169_update_counters(tp);
355423d0 6442
da78dbff 6443 rtl_lock_work(tp);
6ad56901
KHF		 6444 /* Clear all task flags */
6445 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
da78dbff 6446
1da177e4 6447 rtl8169_down(dev);
da78dbff 6448 rtl_unlock_work(tp);
1da177e4 6449
4ea72445
L		 6450 cancel_work_sync(&tp->wk.work);
6451
703732f0 6452 phy_disconnect(tp->phydev);
f1e911d5 6453
ebcd5daa 6454 pci_free_irq(pdev, 0, tp);
1da177e4 6455
82553bb6
SG		 6456 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6457 tp->RxPhyAddr);
6458 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6459 tp->TxPhyAddr);
1da177e4
LT		 6460 tp->TxDescArray = NULL;
6461 tp->RxDescArray = NULL;
6462
e1759441
RW		 6463 pm_runtime_put_sync(&pdev->dev);
6464
1da177e4
LT		 6465 return 0;
6466}
6467
dc1c00ce
FR		 6468#ifdef CONFIG_NET_POLL_CONTROLLER
6469static void rtl8169_netpoll(struct net_device *dev)
6470{
6471 struct rtl8169_private *tp = netdev_priv(dev);
6472
6d8b8349 6473 rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp);
dc1c00ce
FR		 6474}
6475#endif
6476
df43ac78
FR		 6477static int rtl_open(struct net_device *dev)
6478{
6479 struct rtl8169_private *tp = netdev_priv(dev);
df43ac78
FR		 6480 struct pci_dev *pdev = tp->pci_dev;
6481 int retval = -ENOMEM;
6482
6483 pm_runtime_get_sync(&pdev->dev);
6484
6485 /*
e75d6606 6486 * Rx and Tx descriptors needs 256 bytes alignment.
df43ac78
FR		 6487 * dma_alloc_coherent provides more.
6488 */
6489 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
6490 &tp->TxPhyAddr, GFP_KERNEL);
6491 if (!tp->TxDescArray)
6492 goto err_pm_runtime_put;
6493
6494 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
6495 &tp->RxPhyAddr, GFP_KERNEL);
6496 if (!tp->RxDescArray)
6497 goto err_free_tx_0;
6498
b1127e64 6499 retval = rtl8169_init_ring(tp);
df43ac78
FR		 6500 if (retval < 0)
6501 goto err_free_rx_1;
6502
df43ac78
FR		 6503 rtl_request_firmware(tp);
6504
ebcd5daa 6505 retval = pci_request_irq(pdev, 0, rtl8169_interrupt, NULL, tp,
6c6aa15f 6506 dev->name);
df43ac78
FR		 6507 if (retval < 0)
6508 goto err_release_fw_2;
6509
f1e911d5
HK		 6510 retval = r8169_phy_connect(tp);
6511 if (retval)
6512 goto err_free_irq;
6513
df43ac78
FR		 6514 rtl_lock_work(tp);
6515
6516 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6517
6518 napi_enable(&tp->napi);
6519
6520 rtl8169_init_phy(dev, tp);
6521
df43ac78
FR		 6522 rtl_pll_power_up(tp);
6523
61cb532d 6524 rtl_hw_start(tp);
df43ac78 6525
e71c9ce2 6526 if (!rtl8169_init_counter_offsets(tp))
6e85d5ad
CV		 6527 netif_warn(tp, hw, dev, "counter reset/update failed\n");
6528
703732f0 6529 phy_start(tp->phydev);
df43ac78
FR		 6530 netif_start_queue(dev);
6531
6532 rtl_unlock_work(tp);
6533
a92a0849 6534 pm_runtime_put_sync(&pdev->dev);
df43ac78
FR		 6535out:
6536 return retval;
6537
f1e911d5
HK		 6538err_free_irq:
6539 pci_free_irq(pdev, 0, tp);
df43ac78
FR		 6540err_release_fw_2:
6541 rtl_release_firmware(tp);
6542 rtl8169_rx_clear(tp);
6543err_free_rx_1:
6544 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6545 tp->RxPhyAddr);
6546 tp->RxDescArray = NULL;
6547err_free_tx_0:
6548 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6549 tp->TxPhyAddr);
6550 tp->TxDescArray = NULL;
6551err_pm_runtime_put:
6552 pm_runtime_put_noidle(&pdev->dev);
6553 goto out;
6554}
6555
bc1f4470 6556static void
8027aa24 6557rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
1da177e4
LT		 6558{
6559 struct rtl8169_private *tp = netdev_priv(dev);
f09cf4b7 6560 struct pci_dev *pdev = tp->pci_dev;
42020320 6561 struct rtl8169_counters *counters = tp->counters;
8027aa24 6562 unsigned int start;
1da177e4 6563
f09cf4b7
CHL		 6564 pm_runtime_get_noresume(&pdev->dev);
6565
6566 if (netif_running(dev) && pm_runtime_active(&pdev->dev))
1ef7286e 6567 rtl8169_rx_missed(dev);
5b0384f4 6568
8027aa24 6569 do {
57a7744e 6570 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
8027aa24
JW		 6571 stats->rx_packets = tp->rx_stats.packets;
6572 stats->rx_bytes = tp->rx_stats.bytes;
57a7744e 6573 } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
8027aa24 6574
8027aa24 6575 do {
57a7744e 6576 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
8027aa24
JW		 6577 stats->tx_packets = tp->tx_stats.packets;
6578 stats->tx_bytes = tp->tx_stats.bytes;
57a7744e 6579 } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
8027aa24
JW		 6580
6581 stats->rx_dropped = dev->stats.rx_dropped;
6582 stats->tx_dropped = dev->stats.tx_dropped;
6583 stats->rx_length_errors = dev->stats.rx_length_errors;
6584 stats->rx_errors = dev->stats.rx_errors;
6585 stats->rx_crc_errors = dev->stats.rx_crc_errors;
6586 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
6587 stats->rx_missed_errors = dev->stats.rx_missed_errors;
d7d2d89d 6588 stats->multicast = dev->stats.multicast;
8027aa24 6589
6e85d5ad 6590 /*
ed72a9bb 6591 * Fetch additional counter values missing in stats collected by driver
6e85d5ad
CV		 6592 * from tally counters.
6593 */
f09cf4b7 6594 if (pm_runtime_active(&pdev->dev))
e71c9ce2 6595 rtl8169_update_counters(tp);
6e85d5ad
CV		 6596
6597 /*
6598 * Subtract values fetched during initalization.
6599 * See rtl8169_init_counter_offsets for a description why we do that.
6600 */
42020320 6601 stats->tx_errors = le64_to_cpu(counters->tx_errors) -
6e85d5ad 6602 le64_to_cpu(tp->tc_offset.tx_errors);
42020320 6603 stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
6e85d5ad 6604 le32_to_cpu(tp->tc_offset.tx_multi_collision);
42020320 6605 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
6e85d5ad
CV		 6606 le16_to_cpu(tp->tc_offset.tx_aborted);
6607
f09cf4b7 6608 pm_runtime_put_noidle(&pdev->dev);
1da177e4
LT		 6609}
6610
861ab440 6611static void rtl8169_net_suspend(struct net_device *dev)
5d06a99f 6612{
065c27c1 6613 struct rtl8169_private *tp = netdev_priv(dev);
6614
5d06a99f 6615 if (!netif_running(dev))
861ab440 6616 return;
5d06a99f 6617
703732f0 6618 phy_stop(tp->phydev);
5d06a99f 6619 netif_device_detach(dev);
da78dbff
FR		 6620
6621 rtl_lock_work(tp);
6622 napi_disable(&tp->napi);
6ad56901
KHF		 6623 /* Clear all task flags */
6624 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
6625
da78dbff
FR		 6626 rtl_unlock_work(tp);
6627
6628 rtl_pll_power_down(tp);
861ab440
RW		 6629}
6630
6631#ifdef CONFIG_PM
6632
6633static int rtl8169_suspend(struct device *device)
6634{
0f07bd85 6635 struct net_device *dev = dev_get_drvdata(device);
ac8bd9e1 6636 struct rtl8169_private *tp = netdev_priv(dev);
5d06a99f 6637
861ab440 6638 rtl8169_net_suspend(dev);
ac8bd9e1 6639 clk_disable_unprepare(tp->clk);
1371fa6d 6640
5d06a99f
FR		 6641 return 0;
6642}
6643
e1759441
RW		 6644static void __rtl8169_resume(struct net_device *dev)
6645{
065c27c1 6646 struct rtl8169_private *tp = netdev_priv(dev);
6647
e1759441 6648 netif_device_attach(dev);
065c27c1 6649
6650 rtl_pll_power_up(tp);
92bad850 6651 rtl8169_init_phy(dev, tp);
065c27c1 6652
703732f0 6653 phy_start(tp->phydev);
f1e911d5 6654
cff4c162
AS		 6655 rtl_lock_work(tp);
6656 napi_enable(&tp->napi);
6c4a70c5 6657 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
58ba566c 6658 rtl_reset_work(tp);
cff4c162 6659 rtl_unlock_work(tp);
e1759441
RW		 6660}
6661
861ab440 6662static int rtl8169_resume(struct device *device)
5d06a99f 6663{
0f07bd85 6664 struct net_device *dev = dev_get_drvdata(device);
ac8bd9e1
HG		 6665 struct rtl8169_private *tp = netdev_priv(dev);
6666
59715171
HK		 6667 rtl_rar_set(tp, dev->dev_addr);
6668
ac8bd9e1 6669 clk_prepare_enable(tp->clk);
5d06a99f 6670
e1759441
RW		 6671 if (netif_running(dev))
6672 __rtl8169_resume(dev);
5d06a99f 6673
e1759441
RW		 6674 return 0;
6675}
6676
6677static int rtl8169_runtime_suspend(struct device *device)
6678{
0f07bd85 6679 struct net_device *dev = dev_get_drvdata(device);
e1759441
RW		 6680 struct rtl8169_private *tp = netdev_priv(dev);
6681
07df5bd8 6682 if (!tp->TxDescArray)
e1759441
RW		 6683 return 0;
6684
da78dbff 6685 rtl_lock_work(tp);
e1759441 6686 __rtl8169_set_wol(tp, WAKE_ANY);
da78dbff 6687 rtl_unlock_work(tp);
e1759441
RW		 6688
6689 rtl8169_net_suspend(dev);
6690
f09cf4b7 6691 /* Update counters before going runtime suspend */
1ef7286e 6692 rtl8169_rx_missed(dev);
e71c9ce2 6693 rtl8169_update_counters(tp);
f09cf4b7 6694
e1759441
RW		 6695 return 0;
6696}
6697
6698static int rtl8169_runtime_resume(struct device *device)
6699{
0f07bd85 6700 struct net_device *dev = dev_get_drvdata(device);
e1759441 6701 struct rtl8169_private *tp = netdev_priv(dev);
59715171 6702
f51d4a10 6703 rtl_rar_set(tp, dev->dev_addr);
e1759441
RW		 6704
6705 if (!tp->TxDescArray)
6706 return 0;
6707
da78dbff 6708 rtl_lock_work(tp);
e1759441 6709 __rtl8169_set_wol(tp, tp->saved_wolopts);
da78dbff 6710 rtl_unlock_work(tp);
e1759441
RW		 6711
6712 __rtl8169_resume(dev);
5d06a99f 6713
5d06a99f
FR		 6714 return 0;
6715}
6716
e1759441
RW		 6717static int rtl8169_runtime_idle(struct device *device)
6718{
0f07bd85 6719 struct net_device *dev = dev_get_drvdata(device);
e1759441 6720
a92a0849
HK		 6721 if (!netif_running(dev) || !netif_carrier_ok(dev))
6722 pm_schedule_suspend(device, 10000);
6723
6724 return -EBUSY;
e1759441
RW		 6725}
6726
47145210 6727static const struct dev_pm_ops rtl8169_pm_ops = {
cecb5fd7
FR		 6728 .suspend = rtl8169_suspend,
6729 .resume = rtl8169_resume,
6730 .freeze = rtl8169_suspend,
6731 .thaw = rtl8169_resume,
6732 .poweroff = rtl8169_suspend,
6733 .restore = rtl8169_resume,
6734 .runtime_suspend = rtl8169_runtime_suspend,
6735 .runtime_resume = rtl8169_runtime_resume,
6736 .runtime_idle = rtl8169_runtime_idle,
861ab440
RW		 6737};
6738
6739#define RTL8169_PM_OPS (&rtl8169_pm_ops)
6740
6741#else /* !CONFIG_PM */
6742
6743#define RTL8169_PM_OPS NULL
6744
6745#endif /* !CONFIG_PM */
6746
649b3b8c 6747static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
6748{
649b3b8c 6749 /* WoL fails with 8168b when the receiver is disabled. */
6750 switch (tp->mac_version) {
6751 case RTL_GIGA_MAC_VER_11:
6752 case RTL_GIGA_MAC_VER_12:
6753 case RTL_GIGA_MAC_VER_17:
6754 pci_clear_master(tp->pci_dev);
6755
1ef7286e 6756 RTL_W8(tp, ChipCmd, CmdRxEnb);
649b3b8c 6757 /* PCI commit */
1ef7286e 6758 RTL_R8(tp, ChipCmd);
649b3b8c 6759 break;
6760 default:
6761 break;
6762 }
6763}
6764
1765f95d
FR		 6765static void rtl_shutdown(struct pci_dev *pdev)
6766{
861ab440 6767 struct net_device *dev = pci_get_drvdata(pdev);
4bb3f522 6768 struct rtl8169_private *tp = netdev_priv(dev);
861ab440
RW		 6769
6770 rtl8169_net_suspend(dev);
1765f95d 6771
cecb5fd7 6772 /* Restore original MAC address */
cc098dc7
IV		 6773 rtl_rar_set(tp, dev->perm_addr);
6774
92fc43b4 6775 rtl8169_hw_reset(tp);
4bb3f522 6776
861ab440 6777 if (system_state == SYSTEM_POWER_OFF) {
433f9d0d 6778 if (tp->saved_wolopts) {
649b3b8c 6779 rtl_wol_suspend_quirk(tp);
6780 rtl_wol_shutdown_quirk(tp);
ca52efd5 6781 }
6782
861ab440
RW		 6783 pci_wake_from_d3(pdev, true);
6784 pci_set_power_state(pdev, PCI_D3hot);
6785 }
6786}
5d06a99f 6787
baf63293 6788static void rtl_remove_one(struct pci_dev *pdev)
e27566ed
FR		 6789{
6790 struct net_device *dev = pci_get_drvdata(pdev);
6791 struct rtl8169_private *tp = netdev_priv(dev);
6792
9dbe7896 6793 if (r8168_check_dash(tp))
e27566ed 6794 rtl8168_driver_stop(tp);
e27566ed 6795
ad1be8d3
DN		 6796 netif_napi_del(&tp->napi);
6797
e27566ed 6798 unregister_netdev(dev);
703732f0 6799 mdiobus_unregister(tp->phydev->mdio.bus);
e27566ed
FR		 6800
6801 rtl_release_firmware(tp);
6802
6803 if (pci_dev_run_wake(pdev))
6804 pm_runtime_get_noresume(&pdev->dev);
6805
6806 /* restore original MAC address */
6807 rtl_rar_set(tp, dev->perm_addr);
e27566ed
FR		 6808}
6809
fa9c385e 6810static const struct net_device_ops rtl_netdev_ops = {
df43ac78 6811 .ndo_open = rtl_open,
fa9c385e
FR		 6812 .ndo_stop = rtl8169_close,
6813 .ndo_get_stats64 = rtl8169_get_stats64,
6814 .ndo_start_xmit = rtl8169_start_xmit,
e64e0c89 6815 .ndo_features_check = rtl8169_features_check,
fa9c385e
FR		 6816 .ndo_tx_timeout = rtl8169_tx_timeout,
6817 .ndo_validate_addr = eth_validate_addr,
6818 .ndo_change_mtu = rtl8169_change_mtu,
6819 .ndo_fix_features = rtl8169_fix_features,
6820 .ndo_set_features = rtl8169_set_features,
6821 .ndo_set_mac_address = rtl_set_mac_address,
6822 .ndo_do_ioctl = rtl8169_ioctl,
6823 .ndo_set_rx_mode = rtl_set_rx_mode,
6824#ifdef CONFIG_NET_POLL_CONTROLLER
6825 .ndo_poll_controller = rtl8169_netpoll,
6826#endif
6827
6828};
6829
ec9a4088
HK		 6830static void rtl_set_irq_mask(struct rtl8169_private *tp)
6831{
6832 tp->irq_mask = RTL_EVENT_NAPI | LinkChg;
6833
6834 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
6835 tp->irq_mask |= SYSErr | RxOverflow | RxFIFOOver;
6836 else if (tp->mac_version == RTL_GIGA_MAC_VER_11)
6837 /* special workaround needed */
6838 tp->irq_mask |= RxFIFOOver;
6839 else
6840 tp->irq_mask |= RxOverflow;
6841}
6842
6c6aa15f 6843static int rtl_alloc_irq(struct rtl8169_private *tp)
31fa8b18 6844{
6c6aa15f 6845 unsigned int flags;
31fa8b18 6846
003bd5b4
HK		 6847 switch (tp->mac_version) {
6848 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
df320ed7 6849 rtl_unlock_config_regs(tp);
1ef7286e 6850 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
df320ed7 6851 rtl_lock_config_regs(tp);
003bd5b4 6852 /* fall through */
8ff7ebf2 6853 case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_17:
6c6aa15f 6854 flags = PCI_IRQ_LEGACY;
003bd5b4
HK		 6855 break;
6856 default:
6c6aa15f 6857 flags = PCI_IRQ_ALL_TYPES;
003bd5b4 6858 break;
31fa8b18 6859 }
6c6aa15f
HK		 6860
6861 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
31fa8b18
FR		 6862}
6863
04c7788c
TR		 6864static void rtl_read_mac_address(struct rtl8169_private *tp,
6865 u8 mac_addr[ETH_ALEN])
6866{
6867 /* Get MAC address */
9e9f33ba
HK		 6868 if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) {
6869 u32 value = rtl_eri_read(tp, 0xe0);
6870
deedf1fe
TR		 6871 mac_addr[0] = (value >> 0) & 0xff;
6872 mac_addr[1] = (value >> 8) & 0xff;
6873 mac_addr[2] = (value >> 16) & 0xff;
6874 mac_addr[3] = (value >> 24) & 0xff;
6875
724c6fd0 6876 value = rtl_eri_read(tp, 0xe4);
deedf1fe
TR		 6877 mac_addr[4] = (value >> 0) & 0xff;
6878 mac_addr[5] = (value >> 8) & 0xff;
f1bce4ad
HK		 6879 } else if (rtl_is_8125(tp)) {
6880 rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP);
04c7788c
TR		 6881 }
6882}
6883
c558386b
HW		 6884DECLARE_RTL_COND(rtl_link_list_ready_cond)
6885{
1ef7286e 6886 return RTL_R8(tp, MCU) & LINK_LIST_RDY;
c558386b
HW		 6887}
6888
6889DECLARE_RTL_COND(rtl_rxtx_empty_cond)
6890{
1ef7286e 6891 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
c558386b
HW		 6892}
6893
f1e911d5
HK		 6894static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg)
6895{
6896 struct rtl8169_private *tp = mii_bus->priv;
6897
6898 if (phyaddr > 0)
6899 return -ENODEV;
6900
6901 return rtl_readphy(tp, phyreg);
6902}
6903
6904static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr,
6905 int phyreg, u16 val)
6906{
6907 struct rtl8169_private *tp = mii_bus->priv;
6908
6909 if (phyaddr > 0)
6910 return -ENODEV;
6911
6912 rtl_writephy(tp, phyreg, val);
6913
6914 return 0;
6915}
6916
6917static int r8169_mdio_register(struct rtl8169_private *tp)
6918{
6919 struct pci_dev *pdev = tp->pci_dev;
f1e911d5
HK		 6920 struct mii_bus *new_bus;
6921 int ret;
6922
6923 new_bus = devm_mdiobus_alloc(&pdev->dev);
6924 if (!new_bus)
6925 return -ENOMEM;
6926
6927 new_bus->name = "r8169";
6928 new_bus->priv = tp;
6929 new_bus->parent = &pdev->dev;
6930 new_bus->irq[0] = PHY_IGNORE_INTERRUPT;
a195016a 6931 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x", pci_dev_id(pdev));
f1e911d5
HK		 6932
6933 new_bus->read = r8169_mdio_read_reg;
6934 new_bus->write = r8169_mdio_write_reg;
6935
6936 ret = mdiobus_register(new_bus);
6937 if (ret)
6938 return ret;
6939
703732f0
HK		 6940 tp->phydev = mdiobus_get_phy(new_bus, 0);
6941 if (!tp->phydev) {
f1e911d5
HK		 6942 mdiobus_unregister(new_bus);
6943 return -ENODEV;
2f38bab7
HK		 6944 } else if (!tp->phydev->drv) {
6945 /* Most chip versions fail with the genphy driver.
6946 * Therefore ensure that the dedicated PHY driver is loaded.
6947 */
6948 dev_err(&pdev->dev, "realtek.ko not loaded, maybe it needs to be added to initramfs?\n");
6949 mdiobus_unregister(new_bus);
6950 return -EUNATCH;
f1e911d5
HK		 6951 }
6952
242cd9b5 6953 /* PHY will be woken up in rtl_open() */
703732f0 6954 phy_suspend(tp->phydev);
f1e911d5
HK		 6955
6956 return 0;
6957}
6958
baf63293 6959static void rtl_hw_init_8168g(struct rtl8169_private *tp)
c558386b 6960{
c558386b
HW		 6961 tp->ocp_base = OCP_STD_PHY_BASE;
6962
1ef7286e 6963 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
c558386b
HW		 6964
6965 if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
6966 return;
6967
6968 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
6969 return;
6970
1ef7286e 6971 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
c558386b 6972 msleep(1);
1ef7286e 6973 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
c558386b 6974
ef712ede 6975 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);
c558386b
HW		 6976
6977 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
6978 return;
6979
ef712ede 6980 r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15));
c558386b 6981
7160be2d 6982 rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42);
c558386b
HW		 6983}
6984
f1bce4ad
HK		 6985static void rtl_hw_init_8125(struct rtl8169_private *tp)
6986{
6987 tp->ocp_base = OCP_STD_PHY_BASE;
6988
6989 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
6990
6991 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
6992 return;
6993
6994 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
6995 msleep(1);
6996 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
6997
6998 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);
6999
7000 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
7001 return;
7002
7003 r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0);
7004 r8168_mac_ocp_write(tp, 0xc0a6, 0x0150);
7005 r8168_mac_ocp_write(tp, 0xc01e, 0x5555);
7006
7007 rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42);
7008}
7009
baf63293 7010static void rtl_hw_initialize(struct rtl8169_private *tp)
c558386b
HW		 7011{
7012 switch (tp->mac_version) {
2e13d773 7013 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52:
29ec0482
HK		 7014 rtl8168ep_stop_cmac(tp);
7015 /* fall through */
2a71883c 7016 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
003609da
CHL		 7017 rtl_hw_init_8168g(tp);
7018 break;
f1bce4ad
HK		 7019 case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_61:
7020 rtl_hw_init_8125(tp);
7021 break;
c558386b
HW		 7022 default:
7023 break;
7024 }
7025}
7026
abe8b2f7
HK		 7027static int rtl_jumbo_max(struct rtl8169_private *tp)
7028{
7029 /* Non-GBit versions don't support jumbo frames */
7030 if (!tp->supports_gmii)
7031 return JUMBO_1K;
7032
7033 switch (tp->mac_version) {
7034 /* RTL8169 */
e9588eb9 7035 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
abe8b2f7
HK		 7036 return JUMBO_7K;
7037 /* RTL8168b */
7038 case RTL_GIGA_MAC_VER_11:
7039 case RTL_GIGA_MAC_VER_12:
7040 case RTL_GIGA_MAC_VER_17:
7041 return JUMBO_4K;
7042 /* RTL8168c */
7043 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
7044 return JUMBO_6K;
7045 default:
7046 return JUMBO_9K;
7047 }
7048}
7049
c2f6f3ee
HG		 7050static void rtl_disable_clk(void *data)
7051{
7052 clk_disable_unprepare(data);
7053}
7054
b779daea
HK		 7055static int rtl_get_ether_clk(struct rtl8169_private *tp)
7056{
7057 struct device *d = tp_to_dev(tp);
7058 struct clk *clk;
7059 int rc;
7060
7061 clk = devm_clk_get(d, "ether_clk");
7062 if (IS_ERR(clk)) {
7063 rc = PTR_ERR(clk);
7064 if (rc == -ENOENT)
7065 /* clk-core allows NULL (for suspend / resume) */
7066 rc = 0;
7067 else if (rc != -EPROBE_DEFER)
7068 dev_err(d, "failed to get clk: %d\n", rc);
7069 } else {
7070 tp->clk = clk;
7071 rc = clk_prepare_enable(clk);
7072 if (rc)
7073 dev_err(d, "failed to enable clk: %d\n", rc);
7074 else
7075 rc = devm_add_action_or_reset(d, rtl_disable_clk, clk);
7076 }
7077
7078 return rc;
7079}
7080
c782e204
HK		 7081static void rtl_init_mac_address(struct rtl8169_private *tp)
7082{
7083 struct net_device *dev = tp->dev;
7084 u8 *mac_addr = dev->dev_addr;
ce37115e 7085 int rc;
c782e204
HK		 7086
7087 rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr);
7088 if (!rc)
7089 goto done;
7090
7091 rtl_read_mac_address(tp, mac_addr);
7092 if (is_valid_ether_addr(mac_addr))
7093 goto done;
7094
ce37115e 7095 rtl_read_mac_from_reg(tp, mac_addr, MAC0);
c782e204
HK		 7096 if (is_valid_ether_addr(mac_addr))
7097 goto done;
7098
7099 eth_hw_addr_random(dev);
7100 dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n");
7101done:
7102 rtl_rar_set(tp, mac_addr);
7103}
7104
929a031d 7105static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3b6cf25d 7106{
3b6cf25d 7107 struct rtl8169_private *tp;
3b6cf25d 7108 struct net_device *dev;
c782e204 7109 int chipset, region;
abe8b2f7 7110 int jumbo_max, rc;
3b6cf25d 7111
4c45d24a
HK		 7112 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
7113 if (!dev)
7114 return -ENOMEM;
3b6cf25d
FR		 7115
7116 SET_NETDEV_DEV(dev, &pdev->dev);
fa9c385e 7117 dev->netdev_ops = &rtl_netdev_ops;
3b6cf25d
FR		 7118 tp = netdev_priv(dev);
7119 tp->dev = dev;
7120 tp->pci_dev = pdev;
7121 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
145a40e8 7122 tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1;
488202f5 7123 tp->eee_adv = -1;
3b6cf25d 7124
c2f6f3ee 7125 /* Get the *optional* external "ether_clk" used on some boards */
b779daea
HK		 7126 rc = rtl_get_ether_clk(tp);
7127 if (rc)
7128 return rc;
c2f6f3ee 7129
b75bb8a5
HK		 7130 /* Disable ASPM completely as that cause random device stop working
7131 * problems as well as full system hangs for some PCIe devices users.
7132 */
47a7e9f7 7133 rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L1_1);
62b1b3b3 7134 tp->aspm_manageable = !rc;
b75bb8a5 7135
3b6cf25d 7136 /* enable device (incl. PCI PM wakeup and hotplug setup) */
4c45d24a 7137 rc = pcim_enable_device(pdev);
3b6cf25d 7138 if (rc < 0) {
22148df0 7139 dev_err(&pdev->dev, "enable failure\n");
4c45d24a 7140 return rc;
3b6cf25d
FR		 7141 }
7142
4c45d24a 7143 if (pcim_set_mwi(pdev) < 0)
22148df0 7144 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n");
3b6cf25d 7145
c8d48d9c
HK		 7146 /* use first MMIO region */
7147 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1;
7148 if (region < 0) {
22148df0 7149 dev_err(&pdev->dev, "no MMIO resource found\n");
4c45d24a 7150 return -ENODEV;
3b6cf25d
FR		 7151 }
7152
7153 /* check for weird/broken PCI region reporting */
7154 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
22148df0 7155 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n");
4c45d24a 7156 return -ENODEV;
3b6cf25d
FR		 7157 }
7158
93a00d4d 7159 rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME);
3b6cf25d 7160 if (rc < 0) {
22148df0 7161 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
4c45d24a 7162 return rc;
3b6cf25d
FR		 7163 }
7164
93a00d4d 7165 tp->mmio_addr = pcim_iomap_table(pdev)[region];
3b6cf25d 7166
3b6cf25d 7167 /* Identify chip attached to board */
b4cc2dcc
HK		 7168 rtl8169_get_mac_version(tp);
7169 if (tp->mac_version == RTL_GIGA_MAC_NONE)
7170 return -ENODEV;
3b6cf25d 7171
0ae0974e 7172 tp->cp_cmd = RTL_R16(tp, CPlusCmd);
27896c83 7173
10b63e85 7174 if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 &&
3c18cbe3 7175 !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)))
27896c83 7176 dev->features |= NETIF_F_HIGHDMA;
27896c83 7177
3b6cf25d
FR		 7178 rtl_init_rxcfg(tp);
7179
de20e12f 7180 rtl8169_irq_mask_and_ack(tp);
3b6cf25d 7181
c558386b
HW		 7182 rtl_hw_initialize(tp);
7183
3b6cf25d
FR		 7184 rtl_hw_reset(tp);
7185
3b6cf25d
FR		 7186 pci_set_master(pdev);
7187
3b6cf25d 7188 chipset = tp->mac_version;
3b6cf25d 7189
6c6aa15f
HK		 7190 rc = rtl_alloc_irq(tp);
7191 if (rc < 0) {
22148df0 7192 dev_err(&pdev->dev, "Can't allocate interrupt\n");
6c6aa15f
HK		 7193 return rc;
7194 }
3b6cf25d 7195
3b6cf25d 7196 mutex_init(&tp->wk.mutex);
5c41e78f 7197 INIT_WORK(&tp->wk.work, rtl_task);
340fea3d
KM		 7198 u64_stats_init(&tp->rx_stats.syncp);
7199 u64_stats_init(&tp->tx_stats.syncp);
3b6cf25d 7200
c782e204 7201 rtl_init_mac_address(tp);
3b6cf25d 7202
7ad24ea4 7203 dev->ethtool_ops = &rtl8169_ethtool_ops;
3b6cf25d 7204
37621493 7205 netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT);
3b6cf25d 7206
250c1837
HK		 7207 dev->features |= NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
7208 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
7209 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
7210 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
3b6cf25d
FR		 7211 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7212 NETIF_F_HIGHDMA;
2d0ec544 7213 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
3b6cf25d 7214
dc161162
HK		 7215 tp->cp_cmd |= RxChkSum;
7216 /* RTL8125 uses register RxConfig for VLAN offloading config */
7217 if (!rtl_is_8125(tp))
7218 tp->cp_cmd |= RxVlan;
929a031d 7219 /*
7220 * Pretend we are using VLANs; This bypasses a nasty bug where
7221 * Interrupts stop flowing on high load on 8110SCd controllers.
7222 */
3b6cf25d 7223 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
929a031d 7224 /* Disallow toggling */
f646968f 7225 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3b6cf25d 7226
0170d594 7227 if (rtl_chip_supports_csum_v2(tp)) {
250c1837
HK		 7228 dev->hw_features |= NETIF_F_IPV6_CSUM;
7229 dev->features |= NETIF_F_IPV6_CSUM;
7230 }
7231
7232 /* There has been a number of reports that using SG/TSO results in
7233 * tx timeouts. However for a lot of people SG/TSO works fine.
7234 * Therefore disable both features by default, but allow users to
7235 * enable them. Use at own risk!
7236 */
7237 if (rtl_chip_supports_csum_v2(tp)) {
7238 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6;
0170d594
HK		 7239 dev->gso_max_size = RTL_GSO_MAX_SIZE_V2;
7240 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V2;
7241 } else {
250c1837 7242 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO;
0170d594
HK		 7243 dev->gso_max_size = RTL_GSO_MAX_SIZE_V1;
7244 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V1;
7245 }
5888d3fc 7246
3b6cf25d
FR		 7247 dev->hw_features |= NETIF_F_RXALL;
7248 dev->hw_features |= NETIF_F_RXFCS;
7249
c7315a95
JW		 7250 /* MTU range: 60 - hw-specific max */
7251 dev->min_mtu = ETH_ZLEN;
abe8b2f7
HK		 7252 jumbo_max = rtl_jumbo_max(tp);
7253 dev->max_mtu = jumbo_max;
c7315a95 7254
ec9a4088 7255 rtl_set_irq_mask(tp);
9fa0a8e1 7256
254764e5 7257 tp->fw_name = rtl_chip_infos[chipset].fw_name;
3b6cf25d 7258
4c45d24a
HK		 7259 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
7260 &tp->counters_phys_addr,
7261 GFP_KERNEL);
4cf964af
HK		 7262 if (!tp->counters)
7263 return -ENOMEM;
42020320 7264
19c9ea36
HK		 7265 pci_set_drvdata(pdev, dev);
7266
f1e911d5
HK		 7267 rc = r8169_mdio_register(tp);
7268 if (rc)
4cf964af 7269 return rc;
3b6cf25d 7270
07df5bd8
HK		 7271 /* chip gets powered up in rtl_open() */
7272 rtl_pll_power_down(tp);
7273
f1e911d5
HK		 7274 rc = register_netdev(dev);
7275 if (rc)
7276 goto err_mdio_unregister;
7277
55d2ad7b 7278 netif_info(tp, probe, dev, "%s, %pM, XID %03x, IRQ %d\n",
2d6c5a61 7279 rtl_chip_infos[chipset].name, dev->dev_addr,
55d2ad7b 7280 (RTL_R32(tp, TxConfig) >> 20) & 0xfcf,
29274991 7281 pci_irq_vector(pdev, 0));
abe8b2f7
HK		 7282
7283 if (jumbo_max > JUMBO_1K)
7284 netif_info(tp, probe, dev,
7285 "jumbo features [frames: %d bytes, tx checksumming: %s]\n",
7286 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ?
7287 "ok" : "ko");
3b6cf25d 7288
9dbe7896 7289 if (r8168_check_dash(tp))
3b6cf25d 7290 rtl8168_driver_start(tp);
3b6cf25d 7291
a92a0849
HK		 7292 if (pci_dev_run_wake(pdev))
7293 pm_runtime_put_sync(&pdev->dev);
7294
4c45d24a 7295 return 0;
f1e911d5
HK		 7296
7297err_mdio_unregister:
703732f0 7298 mdiobus_unregister(tp->phydev->mdio.bus);
f1e911d5 7299 return rc;
3b6cf25d
FR		 7300}
7301
1da177e4
LT		 7302static struct pci_driver rtl8169_pci_driver = {
7303 .name = MODULENAME,
7304 .id_table = rtl8169_pci_tbl,
3b6cf25d 7305 .probe = rtl_init_one,
baf63293 7306 .remove = rtl_remove_one,
1765f95d 7307 .shutdown = rtl_shutdown,
861ab440 7308 .driver.pm = RTL8169_PM_OPS,
1da177e4
LT		 7309};
7310
3eeb7da9 7311module_pci_driver(rtl8169_pci_driver);
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