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net: ethernet: renesas: ravb: use phydev from struct net_device
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / renesas / ravb_main.c
CommitLineData
c156633f
SS		 1/* Renesas Ethernet AVB device driver
2 *
3 * Copyright (C) 2014-2015 Renesas Electronics Corporation
4 * Copyright (C) 2015 Renesas Solutions Corp.
568b3ce7 5 * Copyright (C) 2015-2016 Cogent Embedded, Inc. <source@cogentembedded.com>
c156633f
SS		 6 *
7 * Based on the SuperH Ethernet driver
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms and conditions of the GNU General Public License version 2,
11 * as published by the Free Software Foundation.
12 */
13
14#include <linux/cache.h>
15#include <linux/clk.h>
16#include <linux/delay.h>
17#include <linux/dma-mapping.h>
18#include <linux/err.h>
19#include <linux/etherdevice.h>
20#include <linux/ethtool.h>
21#include <linux/if_vlan.h>
22#include <linux/kernel.h>
23#include <linux/list.h>
24#include <linux/module.h>
25#include <linux/net_tstamp.h>
26#include <linux/of.h>
27#include <linux/of_device.h>
28#include <linux/of_irq.h>
29#include <linux/of_mdio.h>
30#include <linux/of_net.h>
c156633f
SS		 31#include <linux/pm_runtime.h>
32#include <linux/slab.h>
33#include <linux/spinlock.h>
34
b3d39a88
SH		 35#include <asm/div64.h>
36
c156633f
SS		 37#include "ravb.h"
38
39#define RAVB_DEF_MSG_ENABLE \
40 (NETIF_MSG_LINK | \
41 NETIF_MSG_TIMER | \
42 NETIF_MSG_RX_ERR | \
43 NETIF_MSG_TX_ERR)
44
f51bdc23
KM		 45static const char *ravb_rx_irqs[NUM_RX_QUEUE] = {
46 "ch0", /* RAVB_BE */
47 "ch1", /* RAVB_NC */
48};
49
50static const char *ravb_tx_irqs[NUM_TX_QUEUE] = {
51 "ch18", /* RAVB_BE */
52 "ch19", /* RAVB_NC */
53};
54
568b3ce7
SS		 55void ravb_modify(struct net_device *ndev, enum ravb_reg reg, u32 clear,
56 u32 set)
57{
58 ravb_write(ndev, (ravb_read(ndev, reg) & ~clear) | set, reg);
59}
60
a0d2f206 61int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value)
c156633f
SS		 62{
63 int i;
64
65 for (i = 0; i < 10000; i++) {
66 if ((ravb_read(ndev, reg) & mask) == value)
67 return 0;
68 udelay(10);
69 }
70 return -ETIMEDOUT;
71}
72
73static int ravb_config(struct net_device *ndev)
74{
75 int error;
76
77 /* Set config mode */
568b3ce7 78 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG);
c156633f
SS		 79 /* Check if the operating mode is changed to the config mode */
80 error = ravb_wait(ndev, CSR, CSR_OPS, CSR_OPS_CONFIG);
81 if (error)
82 netdev_err(ndev, "failed to switch device to config mode\n");
83
84 return error;
85}
86
87static void ravb_set_duplex(struct net_device *ndev)
88{
89 struct ravb_private *priv = netdev_priv(ndev);
c156633f 90
568b3ce7 91 ravb_modify(ndev, ECMR, ECMR_DM, priv->duplex ? ECMR_DM : 0);
c156633f
SS		 92}
93
94static void ravb_set_rate(struct net_device *ndev)
95{
96 struct ravb_private *priv = netdev_priv(ndev);
97
98 switch (priv->speed) {
99 case 100: /* 100BASE */
100 ravb_write(ndev, GECMR_SPEED_100, GECMR);
101 break;
102 case 1000: /* 1000BASE */
103 ravb_write(ndev, GECMR_SPEED_1000, GECMR);
104 break;
c156633f
SS		 105 }
106}
107
108static void ravb_set_buffer_align(struct sk_buff *skb)
109{
110 u32 reserve = (unsigned long)skb->data & (RAVB_ALIGN - 1);
111
112 if (reserve)
113 skb_reserve(skb, RAVB_ALIGN - reserve);
114}
115
116/* Get MAC address from the MAC address registers
117 *
118 * Ethernet AVB device doesn't have ROM for MAC address.
119 * This function gets the MAC address that was used by a bootloader.
120 */
121static void ravb_read_mac_address(struct net_device *ndev, const u8 *mac)
122{
123 if (mac) {
124 ether_addr_copy(ndev->dev_addr, mac);
125 } else {
d9660638
SS		 126 u32 mahr = ravb_read(ndev, MAHR);
127 u32 malr = ravb_read(ndev, MALR);
128
129 ndev->dev_addr[0] = (mahr >> 24) & 0xFF;
130 ndev->dev_addr[1] = (mahr >> 16) & 0xFF;
131 ndev->dev_addr[2] = (mahr >> 8) & 0xFF;
132 ndev->dev_addr[3] = (mahr >> 0) & 0xFF;
133 ndev->dev_addr[4] = (malr >> 8) & 0xFF;
134 ndev->dev_addr[5] = (malr >> 0) & 0xFF;
c156633f
SS		 135 }
136}
137
138static void ravb_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set)
139{
140 struct ravb_private *priv = container_of(ctrl, struct ravb_private,
141 mdiobb);
c156633f 142
568b3ce7 143 ravb_modify(priv->ndev, PIR, mask, set ? mask : 0);
c156633f
SS		 144}
145
146/* MDC pin control */
147static void ravb_set_mdc(struct mdiobb_ctrl *ctrl, int level)
148{
149 ravb_mdio_ctrl(ctrl, PIR_MDC, level);
150}
151
152/* Data I/O pin control */
153static void ravb_set_mdio_dir(struct mdiobb_ctrl *ctrl, int output)
154{
155 ravb_mdio_ctrl(ctrl, PIR_MMD, output);
156}
157
158/* Set data bit */
159static void ravb_set_mdio_data(struct mdiobb_ctrl *ctrl, int value)
160{
161 ravb_mdio_ctrl(ctrl, PIR_MDO, value);
162}
163
164/* Get data bit */
165static int ravb_get_mdio_data(struct mdiobb_ctrl *ctrl)
166{
167 struct ravb_private *priv = container_of(ctrl, struct ravb_private,
168 mdiobb);
169
170 return (ravb_read(priv->ndev, PIR) & PIR_MDI) != 0;
171}
172
173/* MDIO bus control struct */
174static struct mdiobb_ops bb_ops = {
175 .owner = THIS_MODULE,
176 .set_mdc = ravb_set_mdc,
177 .set_mdio_dir = ravb_set_mdio_dir,
178 .set_mdio_data = ravb_set_mdio_data,
179 .get_mdio_data = ravb_get_mdio_data,
180};
181
182/* Free skb's and DMA buffers for Ethernet AVB */
183static void ravb_ring_free(struct net_device *ndev, int q)
184{
185 struct ravb_private *priv = netdev_priv(ndev);
186 int ring_size;
187 int i;
188
189 /* Free RX skb ringbuffer */
190 if (priv->rx_skb[q]) {
191 for (i = 0; i < priv->num_rx_ring[q]; i++)
192 dev_kfree_skb(priv->rx_skb[q][i]);
193 }
194 kfree(priv->rx_skb[q]);
195 priv->rx_skb[q] = NULL;
196
197 /* Free TX skb ringbuffer */
198 if (priv->tx_skb[q]) {
199 for (i = 0; i < priv->num_tx_ring[q]; i++)
200 dev_kfree_skb(priv->tx_skb[q][i]);
201 }
202 kfree(priv->tx_skb[q]);
203 priv->tx_skb[q] = NULL;
204
205 /* Free aligned TX buffers */
2f45d190
SS		 206 kfree(priv->tx_align[q]);
207 priv->tx_align[q] = NULL;
c156633f
SS		 208
209 if (priv->rx_ring[q]) {
210 ring_size = sizeof(struct ravb_ex_rx_desc) *
211 (priv->num_rx_ring[q] + 1);
e2dbb33a 212 dma_free_coherent(ndev->dev.parent, ring_size, priv->rx_ring[q],
c156633f
SS		 213 priv->rx_desc_dma[q]);
214 priv->rx_ring[q] = NULL;
215 }
216
217 if (priv->tx_ring[q]) {
218 ring_size = sizeof(struct ravb_tx_desc) *
2f45d190 219 (priv->num_tx_ring[q] * NUM_TX_DESC + 1);
e2dbb33a 220 dma_free_coherent(ndev->dev.parent, ring_size, priv->tx_ring[q],
c156633f
SS		 221 priv->tx_desc_dma[q]);
222 priv->tx_ring[q] = NULL;
223 }
224}
225
226/* Format skb and descriptor buffer for Ethernet AVB */
227static void ravb_ring_format(struct net_device *ndev, int q)
228{
229 struct ravb_private *priv = netdev_priv(ndev);
aad0d51e
SS		 230 struct ravb_ex_rx_desc *rx_desc;
231 struct ravb_tx_desc *tx_desc;
232 struct ravb_desc *desc;
c156633f 233 int rx_ring_size = sizeof(*rx_desc) * priv->num_rx_ring[q];
2f45d190
SS		 234 int tx_ring_size = sizeof(*tx_desc) * priv->num_tx_ring[q] *
235 NUM_TX_DESC;
c156633f 236 dma_addr_t dma_addr;
c156633f
SS		 237 int i;
238
239 priv->cur_rx[q] = 0;
240 priv->cur_tx[q] = 0;
241 priv->dirty_rx[q] = 0;
242 priv->dirty_tx[q] = 0;
243
244 memset(priv->rx_ring[q], 0, rx_ring_size);
245 /* Build RX ring buffer */
246 for (i = 0; i < priv->num_rx_ring[q]; i++) {
c156633f
SS		 247 /* RX descriptor */
248 rx_desc = &priv->rx_ring[q][i];
094e43d5 249 rx_desc->ds_cc = cpu_to_le16(PKT_BUF_SZ);
e2dbb33a 250 dma_addr = dma_map_single(ndev->dev.parent, priv->rx_skb[q][i]->data,
094e43d5 251 PKT_BUF_SZ,
c156633f 252 DMA_FROM_DEVICE);
d8b48911
SS		 253 /* We just set the data size to 0 for a failed mapping which
254 * should prevent DMA from happening...
255 */
e2dbb33a 256 if (dma_mapping_error(ndev->dev.parent, dma_addr))
d8b48911 257 rx_desc->ds_cc = cpu_to_le16(0);
c156633f
SS		 258 rx_desc->dptr = cpu_to_le32(dma_addr);
259 rx_desc->die_dt = DT_FEMPTY;
260 }
261 rx_desc = &priv->rx_ring[q][i];
262 rx_desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]);
263 rx_desc->die_dt = DT_LINKFIX; /* type */
c156633f
SS		 264
265 memset(priv->tx_ring[q], 0, tx_ring_size);
266 /* Build TX ring buffer */
2f45d190
SS		 267 for (i = 0, tx_desc = priv->tx_ring[q]; i < priv->num_tx_ring[q];
268 i++, tx_desc++) {
269 tx_desc->die_dt = DT_EEMPTY;
270 tx_desc++;
c156633f
SS		 271 tx_desc->die_dt = DT_EEMPTY;
272 }
c156633f
SS		 273 tx_desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]);
274 tx_desc->die_dt = DT_LINKFIX; /* type */
275
276 /* RX descriptor base address for best effort */
277 desc = &priv->desc_bat[RX_QUEUE_OFFSET + q];
278 desc->die_dt = DT_LINKFIX; /* type */
279 desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]);
280
281 /* TX descriptor base address for best effort */
282 desc = &priv->desc_bat[q];
283 desc->die_dt = DT_LINKFIX; /* type */
284 desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]);
285}
286
287/* Init skb and descriptor buffer for Ethernet AVB */
288static int ravb_ring_init(struct net_device *ndev, int q)
289{
290 struct ravb_private *priv = netdev_priv(ndev);
d8b48911 291 struct sk_buff *skb;
c156633f 292 int ring_size;
d8b48911 293 int i;
c156633f
SS		 294
295 /* Allocate RX and TX skb rings */
296 priv->rx_skb[q] = kcalloc(priv->num_rx_ring[q],
297 sizeof(*priv->rx_skb[q]), GFP_KERNEL);
298 priv->tx_skb[q] = kcalloc(priv->num_tx_ring[q],
299 sizeof(*priv->tx_skb[q]), GFP_KERNEL);
300 if (!priv->rx_skb[q] || !priv->tx_skb[q])
301 goto error;
302
d8b48911
SS		 303 for (i = 0; i < priv->num_rx_ring[q]; i++) {
304 skb = netdev_alloc_skb(ndev, PKT_BUF_SZ + RAVB_ALIGN - 1);
305 if (!skb)
306 goto error;
307 ravb_set_buffer_align(skb);
308 priv->rx_skb[q][i] = skb;
309 }
310
c156633f 311 /* Allocate rings for the aligned buffers */
2f45d190
SS		 312 priv->tx_align[q] = kmalloc(DPTR_ALIGN * priv->num_tx_ring[q] +
313 DPTR_ALIGN - 1, GFP_KERNEL);
314 if (!priv->tx_align[q])
c156633f
SS		 315 goto error;
316
317 /* Allocate all RX descriptors. */
318 ring_size = sizeof(struct ravb_ex_rx_desc) * (priv->num_rx_ring[q] + 1);
e2dbb33a 319 priv->rx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size,
c156633f
SS		 320 &priv->rx_desc_dma[q],
321 GFP_KERNEL);
322 if (!priv->rx_ring[q])
323 goto error;
324
325 priv->dirty_rx[q] = 0;
326
327 /* Allocate all TX descriptors. */
2f45d190
SS		 328 ring_size = sizeof(struct ravb_tx_desc) *
329 (priv->num_tx_ring[q] * NUM_TX_DESC + 1);
e2dbb33a 330 priv->tx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size,
c156633f
SS		 331 &priv->tx_desc_dma[q],
332 GFP_KERNEL);
333 if (!priv->tx_ring[q])
334 goto error;
335
336 return 0;
337
338error:
339 ravb_ring_free(ndev, q);
340
341 return -ENOMEM;
342}
343
344/* E-MAC init function */
345static void ravb_emac_init(struct net_device *ndev)
346{
347 struct ravb_private *priv = netdev_priv(ndev);
c156633f
SS		 348
349 /* Receive frame limit set register */
350 ravb_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, RFLR);
351
352 /* PAUSE prohibition */
1c1fa821
SS		 353 ravb_write(ndev, ECMR_ZPF | (priv->duplex ? ECMR_DM : 0) |
354 ECMR_TE | ECMR_RE, ECMR);
c156633f
SS		 355
356 ravb_set_rate(ndev);
357
358 /* Set MAC address */
359 ravb_write(ndev,
360 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
361 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
362 ravb_write(ndev,
363 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
364
c156633f
SS		 365 /* E-MAC status register clear */
366 ravb_write(ndev, ECSR_ICD | ECSR_MPD, ECSR);
367
368 /* E-MAC interrupt enable register */
369 ravb_write(ndev, ECSIPR_ICDIP | ECSIPR_MPDIP | ECSIPR_LCHNGIP, ECSIPR);
370}
371
372/* Device init function for Ethernet AVB */
373static int ravb_dmac_init(struct net_device *ndev)
374{
f51bdc23 375 struct ravb_private *priv = netdev_priv(ndev);
c156633f
SS		 376 int error;
377
378 /* Set CONFIG mode */
379 error = ravb_config(ndev);
380 if (error)
381 return error;
382
383 error = ravb_ring_init(ndev, RAVB_BE);
384 if (error)
385 return error;
386 error = ravb_ring_init(ndev, RAVB_NC);
387 if (error) {
388 ravb_ring_free(ndev, RAVB_BE);
389 return error;
390 }
391
392 /* Descriptor format */
393 ravb_ring_format(ndev, RAVB_BE);
394 ravb_ring_format(ndev, RAVB_NC);
395
396#if defined(__LITTLE_ENDIAN)
568b3ce7 397 ravb_modify(ndev, CCC, CCC_BOC, 0);
c156633f 398#else
568b3ce7 399 ravb_modify(ndev, CCC, CCC_BOC, CCC_BOC);
c156633f
SS		 400#endif
401
402 /* Set AVB RX */
8d9c418b
MN		 403 ravb_write(ndev,
404 RCR_EFFS | RCR_ENCF | RCR_ETS0 | RCR_ESF | 0x18000000, RCR);
c156633f
SS		 405
406 /* Set FIFO size */
407 ravb_write(ndev, TGC_TQP_AVBMODE1 | 0x00222200, TGC);
408
409 /* Timestamp enable */
410 ravb_write(ndev, TCCR_TFEN, TCCR);
411
6474de5f 412 /* Interrupt init: */
f51bdc23
KM		 413 if (priv->chip_id == RCAR_GEN3) {
414 /* Clear DIL.DPLx */
415 ravb_write(ndev, 0, DIL);
416 /* Set queue specific interrupt */
417 ravb_write(ndev, CIE_CRIE | CIE_CTIE | CIE_CL0M, CIE);
418 }
c156633f
SS		 419 /* Frame receive */
420 ravb_write(ndev, RIC0_FRE0 | RIC0_FRE1, RIC0);
6474de5f
KM		 421 /* Disable FIFO full warning */
422 ravb_write(ndev, 0, RIC1);
c156633f
SS		 423 /* Receive FIFO full error, descriptor empty */
424 ravb_write(ndev, RIC2_QFE0 | RIC2_QFE1 | RIC2_RFFE, RIC2);
425 /* Frame transmitted, timestamp FIFO updated */
426 ravb_write(ndev, TIC_FTE0 | TIC_FTE1 | TIC_TFUE, TIC);
427
428 /* Setting the control will start the AVB-DMAC process. */
568b3ce7 429 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_OPERATION);
c156633f
SS		 430
431 return 0;
432}
433
434/* Free TX skb function for AVB-IP */
435static int ravb_tx_free(struct net_device *ndev, int q)
436{
437 struct ravb_private *priv = netdev_priv(ndev);
438 struct net_device_stats *stats = &priv->stats[q];
439 struct ravb_tx_desc *desc;
440 int free_num = 0;
aad0d51e 441 int entry;
c156633f
SS		 442 u32 size;
443
444 for (; priv->cur_tx[q] - priv->dirty_tx[q] > 0; priv->dirty_tx[q]++) {
2f45d190
SS		 445 entry = priv->dirty_tx[q] % (priv->num_tx_ring[q] *
446 NUM_TX_DESC);
c156633f
SS		 447 desc = &priv->tx_ring[q][entry];
448 if (desc->die_dt != DT_FEMPTY)
449 break;
450 /* Descriptor type must be checked before all other reads */
451 dma_rmb();
452 size = le16_to_cpu(desc->ds_tagl) & TX_DS;
453 /* Free the original skb. */
2f45d190 454 if (priv->tx_skb[q][entry / NUM_TX_DESC]) {
e2dbb33a 455 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
c156633f 456 size, DMA_TO_DEVICE);
2f45d190
SS		 457 /* Last packet descriptor? */
458 if (entry % NUM_TX_DESC == NUM_TX_DESC - 1) {
459 entry /= NUM_TX_DESC;
460 dev_kfree_skb_any(priv->tx_skb[q][entry]);
461 priv->tx_skb[q][entry] = NULL;
462 stats->tx_packets++;
463 }
c156633f
SS		 464 free_num++;
465 }
c156633f
SS		 466 stats->tx_bytes += size;
467 desc->die_dt = DT_EEMPTY;
468 }
469 return free_num;
470}
471
472static void ravb_get_tx_tstamp(struct net_device *ndev)
473{
474 struct ravb_private *priv = netdev_priv(ndev);
475 struct ravb_tstamp_skb *ts_skb, *ts_skb2;
476 struct skb_shared_hwtstamps shhwtstamps;
477 struct sk_buff *skb;
478 struct timespec64 ts;
479 u16 tag, tfa_tag;
480 int count;
481 u32 tfa2;
482
483 count = (ravb_read(ndev, TSR) & TSR_TFFL) >> 8;
484 while (count--) {
485 tfa2 = ravb_read(ndev, TFA2);
486 tfa_tag = (tfa2 & TFA2_TST) >> 16;
487 ts.tv_nsec = (u64)ravb_read(ndev, TFA0);
488 ts.tv_sec = ((u64)(tfa2 & TFA2_TSV) << 32) |
489 ravb_read(ndev, TFA1);
490 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
491 shhwtstamps.hwtstamp = timespec64_to_ktime(ts);
492 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list,
493 list) {
494 skb = ts_skb->skb;
495 tag = ts_skb->tag;
496 list_del(&ts_skb->list);
497 kfree(ts_skb);
498 if (tag == tfa_tag) {
499 skb_tstamp_tx(skb, &shhwtstamps);
500 break;
501 }
502 }
568b3ce7 503 ravb_modify(ndev, TCCR, TCCR_TFR, TCCR_TFR);
c156633f
SS		 504 }
505}
506
507/* Packet receive function for Ethernet AVB */
508static bool ravb_rx(struct net_device *ndev, int *quota, int q)
509{
510 struct ravb_private *priv = netdev_priv(ndev);
511 int entry = priv->cur_rx[q] % priv->num_rx_ring[q];
512 int boguscnt = (priv->dirty_rx[q] + priv->num_rx_ring[q]) -
513 priv->cur_rx[q];
514 struct net_device_stats *stats = &priv->stats[q];
515 struct ravb_ex_rx_desc *desc;
516 struct sk_buff *skb;
517 dma_addr_t dma_addr;
518 struct timespec64 ts;
c156633f 519 u8 desc_status;
aad0d51e 520 u16 pkt_len;
c156633f
SS		 521 int limit;
522
523 boguscnt = min(boguscnt, *quota);
524 limit = boguscnt;
525 desc = &priv->rx_ring[q][entry];
526 while (desc->die_dt != DT_FEMPTY) {
527 /* Descriptor type must be checked before all other reads */
528 dma_rmb();
529 desc_status = desc->msc;
530 pkt_len = le16_to_cpu(desc->ds_cc) & RX_DS;
531
532 if (--boguscnt < 0)
533 break;
534
d8b48911
SS		 535 /* We use 0-byte descriptors to mark the DMA mapping errors */
536 if (!pkt_len)
537 continue;
538
c156633f
SS		 539 if (desc_status & MSC_MC)
540 stats->multicast++;
541
542 if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF |
543 MSC_CEEF)) {
544 stats->rx_errors++;
545 if (desc_status & MSC_CRC)
546 stats->rx_crc_errors++;
547 if (desc_status & MSC_RFE)
548 stats->rx_frame_errors++;
549 if (desc_status & (MSC_RTLF | MSC_RTSF))
550 stats->rx_length_errors++;
551 if (desc_status & MSC_CEEF)
552 stats->rx_missed_errors++;
553 } else {
554 u32 get_ts = priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE;
555
556 skb = priv->rx_skb[q][entry];
557 priv->rx_skb[q][entry] = NULL;
e2dbb33a 558 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
094e43d5 559 PKT_BUF_SZ,
e2370f07 560 DMA_FROM_DEVICE);
c156633f
SS		 561 get_ts &= (q == RAVB_NC) ?
562 RAVB_RXTSTAMP_TYPE_V2_L2_EVENT :
563 ~RAVB_RXTSTAMP_TYPE_V2_L2_EVENT;
564 if (get_ts) {
565 struct skb_shared_hwtstamps *shhwtstamps;
566
567 shhwtstamps = skb_hwtstamps(skb);
568 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
569 ts.tv_sec = ((u64) le16_to_cpu(desc->ts_sh) <<
570 32) | le32_to_cpu(desc->ts_sl);
571 ts.tv_nsec = le32_to_cpu(desc->ts_n);
572 shhwtstamps->hwtstamp = timespec64_to_ktime(ts);
573 }
574 skb_put(skb, pkt_len);
575 skb->protocol = eth_type_trans(skb, ndev);
576 napi_gro_receive(&priv->napi[q], skb);
577 stats->rx_packets++;
578 stats->rx_bytes += pkt_len;
579 }
580
581 entry = (++priv->cur_rx[q]) % priv->num_rx_ring[q];
582 desc = &priv->rx_ring[q][entry];
583 }
584
585 /* Refill the RX ring buffers. */
586 for (; priv->cur_rx[q] - priv->dirty_rx[q] > 0; priv->dirty_rx[q]++) {
587 entry = priv->dirty_rx[q] % priv->num_rx_ring[q];
588 desc = &priv->rx_ring[q][entry];
094e43d5 589 desc->ds_cc = cpu_to_le16(PKT_BUF_SZ);
c156633f
SS		 590
591 if (!priv->rx_skb[q][entry]) {
592 skb = netdev_alloc_skb(ndev,
593 PKT_BUF_SZ + RAVB_ALIGN - 1);
594 if (!skb)
595 break; /* Better luck next round. */
596 ravb_set_buffer_align(skb);
e2dbb33a 597 dma_addr = dma_map_single(ndev->dev.parent, skb->data,
c156633f
SS		 598 le16_to_cpu(desc->ds_cc),
599 DMA_FROM_DEVICE);
600 skb_checksum_none_assert(skb);
d8b48911
SS		 601 /* We just set the data size to 0 for a failed mapping
602 * which should prevent DMA from happening...
603 */
e2dbb33a 604 if (dma_mapping_error(ndev->dev.parent, dma_addr))
d8b48911 605 desc->ds_cc = cpu_to_le16(0);
c156633f
SS		 606 desc->dptr = cpu_to_le32(dma_addr);
607 priv->rx_skb[q][entry] = skb;
608 }
609 /* Descriptor type must be set after all the above writes */
610 dma_wmb();
611 desc->die_dt = DT_FEMPTY;
612 }
613
614 *quota -= limit - (++boguscnt);
615
616 return boguscnt <= 0;
617}
618
619static void ravb_rcv_snd_disable(struct net_device *ndev)
620{
621 /* Disable TX and RX */
568b3ce7 622 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0);
c156633f
SS		 623}
624
625static void ravb_rcv_snd_enable(struct net_device *ndev)
626{
627 /* Enable TX and RX */
568b3ce7 628 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE);
c156633f
SS		 629}
630
631/* function for waiting dma process finished */
632static int ravb_stop_dma(struct net_device *ndev)
633{
634 int error;
635
636 /* Wait for stopping the hardware TX process */
637 error = ravb_wait(ndev, TCCR,
638 TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 0);
639 if (error)
640 return error;
641
642 error = ravb_wait(ndev, CSR, CSR_TPO0 | CSR_TPO1 | CSR_TPO2 | CSR_TPO3,
643 0);
644 if (error)
645 return error;
646
647 /* Stop the E-MAC's RX/TX processes. */
648 ravb_rcv_snd_disable(ndev);
649
650 /* Wait for stopping the RX DMA process */
651 error = ravb_wait(ndev, CSR, CSR_RPO, 0);
652 if (error)
653 return error;
654
655 /* Stop AVB-DMAC process */
656 return ravb_config(ndev);
657}
658
659/* E-MAC interrupt handler */
f51bdc23 660static void ravb_emac_interrupt_unlocked(struct net_device *ndev)
c156633f
SS		 661{
662 struct ravb_private *priv = netdev_priv(ndev);
663 u32 ecsr, psr;
664
665 ecsr = ravb_read(ndev, ECSR);
666 ravb_write(ndev, ecsr, ECSR); /* clear interrupt */
667 if (ecsr & ECSR_ICD)
668 ndev->stats.tx_carrier_errors++;
669 if (ecsr & ECSR_LCHNG) {
670 /* Link changed */
671 if (priv->no_avb_link)
672 return;
673 psr = ravb_read(ndev, PSR);
674 if (priv->avb_link_active_low)
675 psr ^= PSR_LMON;
676 if (!(psr & PSR_LMON)) {
677 /* DIsable RX and TX */
678 ravb_rcv_snd_disable(ndev);
679 } else {
680 /* Enable RX and TX */
681 ravb_rcv_snd_enable(ndev);
682 }
683 }
684}
685
f51bdc23
KM		 686static irqreturn_t ravb_emac_interrupt(int irq, void *dev_id)
687{
688 struct net_device *ndev = dev_id;
689 struct ravb_private *priv = netdev_priv(ndev);
690
691 spin_lock(&priv->lock);
692 ravb_emac_interrupt_unlocked(ndev);
693 mmiowb();
694 spin_unlock(&priv->lock);
695 return IRQ_HANDLED;
696}
697
c156633f
SS		 698/* Error interrupt handler */
699static void ravb_error_interrupt(struct net_device *ndev)
700{
701 struct ravb_private *priv = netdev_priv(ndev);
702 u32 eis, ris2;
703
704 eis = ravb_read(ndev, EIS);
705 ravb_write(ndev, ~EIS_QFS, EIS);
706 if (eis & EIS_QFS) {
707 ris2 = ravb_read(ndev, RIS2);
708 ravb_write(ndev, ~(RIS2_QFF0 | RIS2_RFFF), RIS2);
709
710 /* Receive Descriptor Empty int */
711 if (ris2 & RIS2_QFF0)
712 priv->stats[RAVB_BE].rx_over_errors++;
713
714 /* Receive Descriptor Empty int */
715 if (ris2 & RIS2_QFF1)
716 priv->stats[RAVB_NC].rx_over_errors++;
717
718 /* Receive FIFO Overflow int */
719 if (ris2 & RIS2_RFFF)
720 priv->rx_fifo_errors++;
721 }
722}
723
f51bdc23
KM		 724static bool ravb_queue_interrupt(struct net_device *ndev, int q)
725{
726 struct ravb_private *priv = netdev_priv(ndev);
727 u32 ris0 = ravb_read(ndev, RIS0);
728 u32 ric0 = ravb_read(ndev, RIC0);
729 u32 tis = ravb_read(ndev, TIS);
730 u32 tic = ravb_read(ndev, TIC);
731
732 if (((ris0 & ric0) & BIT(q)) || ((tis & tic) & BIT(q))) {
733 if (napi_schedule_prep(&priv->napi[q])) {
734 /* Mask RX and TX interrupts */
735 if (priv->chip_id == RCAR_GEN2) {
736 ravb_write(ndev, ric0 & ~BIT(q), RIC0);
737 ravb_write(ndev, tic & ~BIT(q), TIC);
738 } else {
739 ravb_write(ndev, BIT(q), RID0);
740 ravb_write(ndev, BIT(q), TID);
741 }
742 __napi_schedule(&priv->napi[q]);
743 } else {
744 netdev_warn(ndev,
745 "ignoring interrupt, rx status 0x%08x, rx mask 0x%08x,\n",
746 ris0, ric0);
747 netdev_warn(ndev,
748 " tx status 0x%08x, tx mask 0x%08x.\n",
749 tis, tic);
750 }
751 return true;
752 }
753 return false;
754}
755
756static bool ravb_timestamp_interrupt(struct net_device *ndev)
757{
758 u32 tis = ravb_read(ndev, TIS);
759
760 if (tis & TIS_TFUF) {
761 ravb_write(ndev, ~TIS_TFUF, TIS);
762 ravb_get_tx_tstamp(ndev);
763 return true;
764 }
765 return false;
766}
767
c156633f
SS		 768static irqreturn_t ravb_interrupt(int irq, void *dev_id)
769{
770 struct net_device *ndev = dev_id;
771 struct ravb_private *priv = netdev_priv(ndev);
772 irqreturn_t result = IRQ_NONE;
773 u32 iss;
774
775 spin_lock(&priv->lock);
776 /* Get interrupt status */
777 iss = ravb_read(ndev, ISS);
778
779 /* Received and transmitted interrupts */
780 if (iss & (ISS_FRS | ISS_FTS | ISS_TFUS)) {
c156633f
SS		 781 int q;
782
783 /* Timestamp updated */
f51bdc23 784 if (ravb_timestamp_interrupt(ndev))
c156633f 785 result = IRQ_HANDLED;
c156633f
SS		 786
787 /* Network control and best effort queue RX/TX */
788 for (q = RAVB_NC; q >= RAVB_BE; q--) {
f51bdc23 789 if (ravb_queue_interrupt(ndev, q))
c156633f 790 result = IRQ_HANDLED;
c156633f
SS		 791 }
792 }
793
794 /* E-MAC status summary */
795 if (iss & ISS_MS) {
f51bdc23 796 ravb_emac_interrupt_unlocked(ndev);
c156633f
SS		 797 result = IRQ_HANDLED;
798 }
799
800 /* Error status summary */
801 if (iss & ISS_ES) {
802 ravb_error_interrupt(ndev);
803 result = IRQ_HANDLED;
804 }
805
f51bdc23 806 /* gPTP interrupt status summary */
d0988a5f
SS		 807 if (iss & ISS_CGIS) {
808 ravb_ptp_interrupt(ndev);
38c848c7 809 result = IRQ_HANDLED;
d0988a5f 810 }
a0d2f206 811
c156633f
SS		 812 mmiowb();
813 spin_unlock(&priv->lock);
814 return result;
815}
816
f51bdc23
KM		 817/* Timestamp/Error/gPTP interrupt handler */
818static irqreturn_t ravb_multi_interrupt(int irq, void *dev_id)
819{
820 struct net_device *ndev = dev_id;
821 struct ravb_private *priv = netdev_priv(ndev);
822 irqreturn_t result = IRQ_NONE;
823 u32 iss;
824
825 spin_lock(&priv->lock);
826 /* Get interrupt status */
827 iss = ravb_read(ndev, ISS);
828
829 /* Timestamp updated */
830 if ((iss & ISS_TFUS) && ravb_timestamp_interrupt(ndev))
831 result = IRQ_HANDLED;
832
833 /* Error status summary */
834 if (iss & ISS_ES) {
835 ravb_error_interrupt(ndev);
836 result = IRQ_HANDLED;
837 }
838
839 /* gPTP interrupt status summary */
d0988a5f
SS		 840 if (iss & ISS_CGIS) {
841 ravb_ptp_interrupt(ndev);
f51bdc23 842 result = IRQ_HANDLED;
d0988a5f 843 }
f51bdc23
KM		 844
845 mmiowb();
846 spin_unlock(&priv->lock);
847 return result;
848}
849
850static irqreturn_t ravb_dma_interrupt(int irq, void *dev_id, int q)
851{
852 struct net_device *ndev = dev_id;
853 struct ravb_private *priv = netdev_priv(ndev);
854 irqreturn_t result = IRQ_NONE;
855
856 spin_lock(&priv->lock);
857
858 /* Network control/Best effort queue RX/TX */
859 if (ravb_queue_interrupt(ndev, q))
860 result = IRQ_HANDLED;
861
862 mmiowb();
863 spin_unlock(&priv->lock);
864 return result;
865}
866
867static irqreturn_t ravb_be_interrupt(int irq, void *dev_id)
868{
869 return ravb_dma_interrupt(irq, dev_id, RAVB_BE);
870}
871
872static irqreturn_t ravb_nc_interrupt(int irq, void *dev_id)
873{
874 return ravb_dma_interrupt(irq, dev_id, RAVB_NC);
875}
876
c156633f
SS		 877static int ravb_poll(struct napi_struct *napi, int budget)
878{
879 struct net_device *ndev = napi->dev;
880 struct ravb_private *priv = netdev_priv(ndev);
881 unsigned long flags;
882 int q = napi - priv->napi;
883 int mask = BIT(q);
884 int quota = budget;
885 u32 ris0, tis;
886
887 for (;;) {
888 tis = ravb_read(ndev, TIS);
889 ris0 = ravb_read(ndev, RIS0);
890 if (!((ris0 & mask) || (tis & mask)))
891 break;
892
893 /* Processing RX Descriptor Ring */
894 if (ris0 & mask) {
895 /* Clear RX interrupt */
896 ravb_write(ndev, ~mask, RIS0);
897 if (ravb_rx(ndev, &quota, q))
898 goto out;
899 }
900 /* Processing TX Descriptor Ring */
901 if (tis & mask) {
902 spin_lock_irqsave(&priv->lock, flags);
903 /* Clear TX interrupt */
904 ravb_write(ndev, ~mask, TIS);
905 ravb_tx_free(ndev, q);
906 netif_wake_subqueue(ndev, q);
907 mmiowb();
908 spin_unlock_irqrestore(&priv->lock, flags);
909 }
910 }
911
912 napi_complete(napi);
913
914 /* Re-enable RX/TX interrupts */
915 spin_lock_irqsave(&priv->lock, flags);
f51bdc23
KM		 916 if (priv->chip_id == RCAR_GEN2) {
917 ravb_modify(ndev, RIC0, mask, mask);
918 ravb_modify(ndev, TIC, mask, mask);
919 } else {
920 ravb_write(ndev, mask, RIE0);
921 ravb_write(ndev, mask, TIE);
922 }
c156633f
SS		 923 mmiowb();
924 spin_unlock_irqrestore(&priv->lock, flags);
925
926 /* Receive error message handling */
927 priv->rx_over_errors = priv->stats[RAVB_BE].rx_over_errors;
928 priv->rx_over_errors += priv->stats[RAVB_NC].rx_over_errors;
929 if (priv->rx_over_errors != ndev->stats.rx_over_errors) {
930 ndev->stats.rx_over_errors = priv->rx_over_errors;
931 netif_err(priv, rx_err, ndev, "Receive Descriptor Empty\n");
932 }
933 if (priv->rx_fifo_errors != ndev->stats.rx_fifo_errors) {
934 ndev->stats.rx_fifo_errors = priv->rx_fifo_errors;
935 netif_err(priv, rx_err, ndev, "Receive FIFO Overflow\n");
936 }
937out:
938 return budget - quota;
939}
940
941/* PHY state control function */
942static void ravb_adjust_link(struct net_device *ndev)
943{
944 struct ravb_private *priv = netdev_priv(ndev);
0f635171 945 struct phy_device *phydev = ndev->phydev;
c156633f
SS		 946 bool new_state = false;
947
948 if (phydev->link) {
949 if (phydev->duplex != priv->duplex) {
950 new_state = true;
951 priv->duplex = phydev->duplex;
952 ravb_set_duplex(ndev);
953 }
954
955 if (phydev->speed != priv->speed) {
956 new_state = true;
957 priv->speed = phydev->speed;
958 ravb_set_rate(ndev);
959 }
960 if (!priv->link) {
568b3ce7 961 ravb_modify(ndev, ECMR, ECMR_TXF, 0);
c156633f
SS		 962 new_state = true;
963 priv->link = phydev->link;
964 if (priv->no_avb_link)
965 ravb_rcv_snd_enable(ndev);
966 }
967 } else if (priv->link) {
968 new_state = true;
969 priv->link = 0;
970 priv->speed = 0;
971 priv->duplex = -1;
972 if (priv->no_avb_link)
973 ravb_rcv_snd_disable(ndev);
974 }
975
976 if (new_state && netif_msg_link(priv))
977 phy_print_status(phydev);
978}
979
980/* PHY init function */
981static int ravb_phy_init(struct net_device *ndev)
982{
983 struct device_node *np = ndev->dev.parent->of_node;
984 struct ravb_private *priv = netdev_priv(ndev);
985 struct phy_device *phydev;
986 struct device_node *pn;
b4bc88a8 987 int err;
c156633f
SS		 988
989 priv->link = 0;
990 priv->speed = 0;
991 priv->duplex = -1;
992
993 /* Try connecting to PHY */
994 pn = of_parse_phandle(np, "phy-handle", 0);
b4bc88a8
KM		 995 if (!pn) {
996 /* In the case of a fixed PHY, the DT node associated
997 * to the PHY is the Ethernet MAC DT node.
998 */
999 if (of_phy_is_fixed_link(np)) {
1000 err = of_phy_register_fixed_link(np);
1001 if (err)
1002 return err;
1003 }
1004 pn = of_node_get(np);
1005 }
c156633f
SS		 1006 phydev = of_phy_connect(ndev, pn, ravb_adjust_link, 0,
1007 priv->phy_interface);
c9b1eb89 1008 of_node_put(pn);
c156633f
SS		 1009 if (!phydev) {
1010 netdev_err(ndev, "failed to connect PHY\n");
1011 return -ENOENT;
1012 }
1013
22d4df8f
KM		 1014 /* This driver only support 10/100Mbit speeds on Gen3
1015 * at this time.
1016 */
1017 if (priv->chip_id == RCAR_GEN3) {
1018 int err;
1019
1020 err = phy_set_max_speed(phydev, SPEED_100);
1021 if (err) {
1022 netdev_err(ndev, "failed to limit PHY to 100Mbit/s\n");
1023 phy_disconnect(phydev);
1024 return err;
1025 }
1026
1027 netdev_info(ndev, "limited PHY to 100Mbit/s\n");
1028 }
1029
54499969
KM		 1030 /* 10BASE is not supported */
1031 phydev->supported &= ~PHY_10BT_FEATURES;
1032
2220943a 1033 phy_attached_info(phydev);
c156633f 1034
c156633f
SS		 1035 return 0;
1036}
1037
1038/* PHY control start function */
1039static int ravb_phy_start(struct net_device *ndev)
1040{
c156633f
SS		 1041 int error;
1042
1043 error = ravb_phy_init(ndev);
1044 if (error)
1045 return error;
1046
0f635171 1047 phy_start(ndev->phydev);
c156633f
SS		 1048
1049 return 0;
1050}
1051
1052static int ravb_get_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
1053{
1054 struct ravb_private *priv = netdev_priv(ndev);
1055 int error = -ENODEV;
1056 unsigned long flags;
1057
0f635171 1058 if (ndev->phydev) {
c156633f 1059 spin_lock_irqsave(&priv->lock, flags);
0f635171 1060 error = phy_ethtool_gset(ndev->phydev, ecmd);
c156633f
SS		 1061 spin_unlock_irqrestore(&priv->lock, flags);
1062 }
1063
1064 return error;
1065}
1066
1067static int ravb_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
1068{
1069 struct ravb_private *priv = netdev_priv(ndev);
1070 unsigned long flags;
1071 int error;
1072
0f635171 1073 if (!ndev->phydev)
c156633f
SS		 1074 return -ENODEV;
1075
1076 spin_lock_irqsave(&priv->lock, flags);
1077
1078 /* Disable TX and RX */
1079 ravb_rcv_snd_disable(ndev);
1080
0f635171 1081 error = phy_ethtool_sset(ndev->phydev, ecmd);
c156633f
SS		 1082 if (error)
1083 goto error_exit;
1084
1085 if (ecmd->duplex == DUPLEX_FULL)
1086 priv->duplex = 1;
1087 else
1088 priv->duplex = 0;
1089
1090 ravb_set_duplex(ndev);
1091
1092error_exit:
1093 mdelay(1);
1094
1095 /* Enable TX and RX */
1096 ravb_rcv_snd_enable(ndev);
1097
1098 mmiowb();
1099 spin_unlock_irqrestore(&priv->lock, flags);
1100
1101 return error;
1102}
1103
1104static int ravb_nway_reset(struct net_device *ndev)
1105{
1106 struct ravb_private *priv = netdev_priv(ndev);
1107 int error = -ENODEV;
1108 unsigned long flags;
1109
0f635171 1110 if (ndev->phydev) {
c156633f 1111 spin_lock_irqsave(&priv->lock, flags);
0f635171 1112 error = phy_start_aneg(ndev->phydev);
c156633f
SS		 1113 spin_unlock_irqrestore(&priv->lock, flags);
1114 }
1115
1116 return error;
1117}
1118
1119static u32 ravb_get_msglevel(struct net_device *ndev)
1120{
1121 struct ravb_private *priv = netdev_priv(ndev);
1122
1123 return priv->msg_enable;
1124}
1125
1126static void ravb_set_msglevel(struct net_device *ndev, u32 value)
1127{
1128 struct ravb_private *priv = netdev_priv(ndev);
1129
1130 priv->msg_enable = value;
1131}
1132
1133static const char ravb_gstrings_stats[][ETH_GSTRING_LEN] = {
1134 "rx_queue_0_current",
1135 "tx_queue_0_current",
1136 "rx_queue_0_dirty",
1137 "tx_queue_0_dirty",
1138 "rx_queue_0_packets",
1139 "tx_queue_0_packets",
1140 "rx_queue_0_bytes",
1141 "tx_queue_0_bytes",
1142 "rx_queue_0_mcast_packets",
1143 "rx_queue_0_errors",
1144 "rx_queue_0_crc_errors",
1145 "rx_queue_0_frame_errors",
1146 "rx_queue_0_length_errors",
1147 "rx_queue_0_missed_errors",
1148 "rx_queue_0_over_errors",
1149
1150 "rx_queue_1_current",
1151 "tx_queue_1_current",
1152 "rx_queue_1_dirty",
1153 "tx_queue_1_dirty",
1154 "rx_queue_1_packets",
1155 "tx_queue_1_packets",
1156 "rx_queue_1_bytes",
1157 "tx_queue_1_bytes",
1158 "rx_queue_1_mcast_packets",
1159 "rx_queue_1_errors",
1160 "rx_queue_1_crc_errors",
b17c1d9a 1161 "rx_queue_1_frame_errors",
c156633f
SS		 1162 "rx_queue_1_length_errors",
1163 "rx_queue_1_missed_errors",
1164 "rx_queue_1_over_errors",
1165};
1166
1167#define RAVB_STATS_LEN ARRAY_SIZE(ravb_gstrings_stats)
1168
1169static int ravb_get_sset_count(struct net_device *netdev, int sset)
1170{
1171 switch (sset) {
1172 case ETH_SS_STATS:
1173 return RAVB_STATS_LEN;
1174 default:
1175 return -EOPNOTSUPP;
1176 }
1177}
1178
1179static void ravb_get_ethtool_stats(struct net_device *ndev,
1180 struct ethtool_stats *stats, u64 *data)
1181{
1182 struct ravb_private *priv = netdev_priv(ndev);
1183 int i = 0;
1184 int q;
1185
1186 /* Device-specific stats */
1187 for (q = RAVB_BE; q < NUM_RX_QUEUE; q++) {
1188 struct net_device_stats *stats = &priv->stats[q];
1189
1190 data[i++] = priv->cur_rx[q];
1191 data[i++] = priv->cur_tx[q];
1192 data[i++] = priv->dirty_rx[q];
1193 data[i++] = priv->dirty_tx[q];
1194 data[i++] = stats->rx_packets;
1195 data[i++] = stats->tx_packets;
1196 data[i++] = stats->rx_bytes;
1197 data[i++] = stats->tx_bytes;
1198 data[i++] = stats->multicast;
1199 data[i++] = stats->rx_errors;
1200 data[i++] = stats->rx_crc_errors;
1201 data[i++] = stats->rx_frame_errors;
1202 data[i++] = stats->rx_length_errors;
1203 data[i++] = stats->rx_missed_errors;
1204 data[i++] = stats->rx_over_errors;
1205 }
1206}
1207
1208static void ravb_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1209{
1210 switch (stringset) {
1211 case ETH_SS_STATS:
1212 memcpy(data, *ravb_gstrings_stats, sizeof(ravb_gstrings_stats));
1213 break;
1214 }
1215}
1216
1217static void ravb_get_ringparam(struct net_device *ndev,
1218 struct ethtool_ringparam *ring)
1219{
1220 struct ravb_private *priv = netdev_priv(ndev);
1221
1222 ring->rx_max_pending = BE_RX_RING_MAX;
1223 ring->tx_max_pending = BE_TX_RING_MAX;
1224 ring->rx_pending = priv->num_rx_ring[RAVB_BE];
1225 ring->tx_pending = priv->num_tx_ring[RAVB_BE];
1226}
1227
1228static int ravb_set_ringparam(struct net_device *ndev,
1229 struct ethtool_ringparam *ring)
1230{
1231 struct ravb_private *priv = netdev_priv(ndev);
1232 int error;
1233
1234 if (ring->tx_pending > BE_TX_RING_MAX ||
1235 ring->rx_pending > BE_RX_RING_MAX ||
1236 ring->tx_pending < BE_TX_RING_MIN ||
1237 ring->rx_pending < BE_RX_RING_MIN)
1238 return -EINVAL;
1239 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
1240 return -EINVAL;
1241
1242 if (netif_running(ndev)) {
1243 netif_device_detach(ndev);
a0d2f206 1244 /* Stop PTP Clock driver */
50bfd838
SS		 1245 if (priv->chip_id == RCAR_GEN2)
1246 ravb_ptp_stop(ndev);
c156633f
SS		 1247 /* Wait for DMA stopping */
1248 error = ravb_stop_dma(ndev);
1249 if (error) {
1250 netdev_err(ndev,
1251 "cannot set ringparam! Any AVB processes are still running?\n");
1252 return error;
1253 }
1254 synchronize_irq(ndev->irq);
1255
1256 /* Free all the skb's in the RX queue and the DMA buffers. */
1257 ravb_ring_free(ndev, RAVB_BE);
1258 ravb_ring_free(ndev, RAVB_NC);
1259 }
1260
1261 /* Set new parameters */
1262 priv->num_rx_ring[RAVB_BE] = ring->rx_pending;
1263 priv->num_tx_ring[RAVB_BE] = ring->tx_pending;
1264
1265 if (netif_running(ndev)) {
1266 error = ravb_dmac_init(ndev);
1267 if (error) {
1268 netdev_err(ndev,
1269 "%s: ravb_dmac_init() failed, error %d\n",
1270 __func__, error);
1271 return error;
1272 }
1273
1274 ravb_emac_init(ndev);
1275
a0d2f206 1276 /* Initialise PTP Clock driver */
50bfd838
SS		 1277 if (priv->chip_id == RCAR_GEN2)
1278 ravb_ptp_init(ndev, priv->pdev);
a0d2f206 1279
c156633f
SS		 1280 netif_device_attach(ndev);
1281 }
1282
1283 return 0;
1284}
1285
1286static int ravb_get_ts_info(struct net_device *ndev,
1287 struct ethtool_ts_info *info)
1288{
a0d2f206
SS		 1289 struct ravb_private *priv = netdev_priv(ndev);
1290
c156633f
SS		 1291 info->so_timestamping =
1292 SOF_TIMESTAMPING_TX_SOFTWARE |
1293 SOF_TIMESTAMPING_RX_SOFTWARE |
1294 SOF_TIMESTAMPING_SOFTWARE |
1295 SOF_TIMESTAMPING_TX_HARDWARE |
1296 SOF_TIMESTAMPING_RX_HARDWARE |
1297 SOF_TIMESTAMPING_RAW_HARDWARE;
1298 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON);
1299 info->rx_filters =
1300 (1 << HWTSTAMP_FILTER_NONE) |
1301 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
1302 (1 << HWTSTAMP_FILTER_ALL);
a0d2f206 1303 info->phc_index = ptp_clock_index(priv->ptp.clock);
c156633f
SS		 1304
1305 return 0;
1306}
1307
1308static const struct ethtool_ops ravb_ethtool_ops = {
1309 .get_settings = ravb_get_settings,
1310 .set_settings = ravb_set_settings,
1311 .nway_reset = ravb_nway_reset,
1312 .get_msglevel = ravb_get_msglevel,
1313 .set_msglevel = ravb_set_msglevel,
1314 .get_link = ethtool_op_get_link,
1315 .get_strings = ravb_get_strings,
1316 .get_ethtool_stats = ravb_get_ethtool_stats,
1317 .get_sset_count = ravb_get_sset_count,
1318 .get_ringparam = ravb_get_ringparam,
1319 .set_ringparam = ravb_set_ringparam,
1320 .get_ts_info = ravb_get_ts_info,
1321};
1322
f51bdc23
KM		 1323static inline int ravb_hook_irq(unsigned int irq, irq_handler_t handler,
1324 struct net_device *ndev, struct device *dev,
1325 const char *ch)
1326{
1327 char *name;
1328 int error;
1329
1330 name = devm_kasprintf(dev, GFP_KERNEL, "%s:%s", ndev->name, ch);
1331 if (!name)
1332 return -ENOMEM;
1333 error = request_irq(irq, handler, 0, name, ndev);
1334 if (error)
1335 netdev_err(ndev, "cannot request IRQ %s\n", name);
1336
1337 return error;
1338}
1339
c156633f
SS		 1340/* Network device open function for Ethernet AVB */
1341static int ravb_open(struct net_device *ndev)
1342{
1343 struct ravb_private *priv = netdev_priv(ndev);
f51bdc23
KM		 1344 struct platform_device *pdev = priv->pdev;
1345 struct device *dev = &pdev->dev;
c156633f
SS		 1346 int error;
1347
1348 napi_enable(&priv->napi[RAVB_BE]);
1349 napi_enable(&priv->napi[RAVB_NC]);
1350
f51bdc23
KM		 1351 if (priv->chip_id == RCAR_GEN2) {
1352 error = request_irq(ndev->irq, ravb_interrupt, IRQF_SHARED,
1353 ndev->name, ndev);
22d4df8f
KM		 1354 if (error) {
1355 netdev_err(ndev, "cannot request IRQ\n");
f51bdc23 1356 goto out_napi_off;
22d4df8f 1357 }
f51bdc23
KM		 1358 } else {
1359 error = ravb_hook_irq(ndev->irq, ravb_multi_interrupt, ndev,
1360 dev, "ch22:multi");
1361 if (error)
1362 goto out_napi_off;
1363 error = ravb_hook_irq(priv->emac_irq, ravb_emac_interrupt, ndev,
1364 dev, "ch24:emac");
1365 if (error)
1366 goto out_free_irq;
1367 error = ravb_hook_irq(priv->rx_irqs[RAVB_BE], ravb_be_interrupt,
1368 ndev, dev, "ch0:rx_be");
1369 if (error)
1370 goto out_free_irq_emac;
1371 error = ravb_hook_irq(priv->tx_irqs[RAVB_BE], ravb_be_interrupt,
1372 ndev, dev, "ch18:tx_be");
1373 if (error)
1374 goto out_free_irq_be_rx;
1375 error = ravb_hook_irq(priv->rx_irqs[RAVB_NC], ravb_nc_interrupt,
1376 ndev, dev, "ch1:rx_nc");
1377 if (error)
1378 goto out_free_irq_be_tx;
1379 error = ravb_hook_irq(priv->tx_irqs[RAVB_NC], ravb_nc_interrupt,
1380 ndev, dev, "ch19:tx_nc");
1381 if (error)
1382 goto out_free_irq_nc_rx;
22d4df8f
KM		 1383 }
1384
c156633f
SS		 1385 /* Device init */
1386 error = ravb_dmac_init(ndev);
1387 if (error)
f51bdc23 1388 goto out_free_irq_nc_tx;
c156633f
SS		 1389 ravb_emac_init(ndev);
1390
a0d2f206 1391 /* Initialise PTP Clock driver */
f5d7837f
KM		 1392 if (priv->chip_id == RCAR_GEN2)
1393 ravb_ptp_init(ndev, priv->pdev);
a0d2f206 1394
c156633f
SS		 1395 netif_tx_start_all_queues(ndev);
1396
1397 /* PHY control start */
1398 error = ravb_phy_start(ndev);
1399 if (error)
a0d2f206 1400 goto out_ptp_stop;
c156633f
SS		 1401
1402 return 0;
1403
a0d2f206
SS		 1404out_ptp_stop:
1405 /* Stop PTP Clock driver */
f5d7837f
KM		 1406 if (priv->chip_id == RCAR_GEN2)
1407 ravb_ptp_stop(ndev);
f51bdc23
KM		 1408out_free_irq_nc_tx:
1409 if (priv->chip_id == RCAR_GEN2)
1410 goto out_free_irq;
1411 free_irq(priv->tx_irqs[RAVB_NC], ndev);
1412out_free_irq_nc_rx:
1413 free_irq(priv->rx_irqs[RAVB_NC], ndev);
1414out_free_irq_be_tx:
1415 free_irq(priv->tx_irqs[RAVB_BE], ndev);
1416out_free_irq_be_rx:
1417 free_irq(priv->rx_irqs[RAVB_BE], ndev);
1418out_free_irq_emac:
1419 free_irq(priv->emac_irq, ndev);
c156633f
SS		 1420out_free_irq:
1421 free_irq(ndev->irq, ndev);
1422out_napi_off:
1423 napi_disable(&priv->napi[RAVB_NC]);
1424 napi_disable(&priv->napi[RAVB_BE]);
1425 return error;
1426}
1427
1428/* Timeout function for Ethernet AVB */
1429static void ravb_tx_timeout(struct net_device *ndev)
1430{
1431 struct ravb_private *priv = netdev_priv(ndev);
1432
1433 netif_err(priv, tx_err, ndev,
1434 "transmit timed out, status %08x, resetting...\n",
1435 ravb_read(ndev, ISS));
1436
1437 /* tx_errors count up */
1438 ndev->stats.tx_errors++;
1439
1440 schedule_work(&priv->work);
1441}
1442
1443static void ravb_tx_timeout_work(struct work_struct *work)
1444{
1445 struct ravb_private *priv = container_of(work, struct ravb_private,
1446 work);
1447 struct net_device *ndev = priv->ndev;
1448
1449 netif_tx_stop_all_queues(ndev);
1450
a0d2f206 1451 /* Stop PTP Clock driver */
50bfd838
SS		 1452 if (priv->chip_id == RCAR_GEN2)
1453 ravb_ptp_stop(ndev);
a0d2f206 1454
c156633f
SS		 1455 /* Wait for DMA stopping */
1456 ravb_stop_dma(ndev);
1457
1458 ravb_ring_free(ndev, RAVB_BE);
1459 ravb_ring_free(ndev, RAVB_NC);
1460
1461 /* Device init */
1462 ravb_dmac_init(ndev);
1463 ravb_emac_init(ndev);
1464
a0d2f206 1465 /* Initialise PTP Clock driver */
50bfd838
SS		 1466 if (priv->chip_id == RCAR_GEN2)
1467 ravb_ptp_init(ndev, priv->pdev);
a0d2f206 1468
c156633f
SS		 1469 netif_tx_start_all_queues(ndev);
1470}
1471
1472/* Packet transmit function for Ethernet AVB */
1473static netdev_tx_t ravb_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1474{
1475 struct ravb_private *priv = netdev_priv(ndev);
c156633f 1476 u16 q = skb_get_queue_mapping(skb);
aad0d51e 1477 struct ravb_tstamp_skb *ts_skb;
c156633f
SS		 1478 struct ravb_tx_desc *desc;
1479 unsigned long flags;
1480 u32 dma_addr;
1481 void *buffer;
1482 u32 entry;
2f45d190 1483 u32 len;
c156633f
SS		 1484
1485 spin_lock_irqsave(&priv->lock, flags);
2f45d190
SS		 1486 if (priv->cur_tx[q] - priv->dirty_tx[q] > (priv->num_tx_ring[q] - 1) *
1487 NUM_TX_DESC) {
c156633f
SS		 1488 netif_err(priv, tx_queued, ndev,
1489 "still transmitting with the full ring!\n");
1490 netif_stop_subqueue(ndev, q);
1491 spin_unlock_irqrestore(&priv->lock, flags);
1492 return NETDEV_TX_BUSY;
1493 }
2f45d190
SS		 1494 entry = priv->cur_tx[q] % (priv->num_tx_ring[q] * NUM_TX_DESC);
1495 priv->tx_skb[q][entry / NUM_TX_DESC] = skb;
c156633f
SS		 1496
1497 if (skb_put_padto(skb, ETH_ZLEN))
1498 goto drop;
1499
2f45d190
SS		 1500 buffer = PTR_ALIGN(priv->tx_align[q], DPTR_ALIGN) +
1501 entry / NUM_TX_DESC * DPTR_ALIGN;
1502 len = PTR_ALIGN(skb->data, DPTR_ALIGN) - skb->data;
1503 memcpy(buffer, skb->data, len);
e2dbb33a
KM		 1504 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, DMA_TO_DEVICE);
1505 if (dma_mapping_error(ndev->dev.parent, dma_addr))
c156633f 1506 goto drop;
2f45d190
SS		 1507
1508 desc = &priv->tx_ring[q][entry];
1509 desc->ds_tagl = cpu_to_le16(len);
1510 desc->dptr = cpu_to_le32(dma_addr);
1511
1512 buffer = skb->data + len;
1513 len = skb->len - len;
e2dbb33a
KM		 1514 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, DMA_TO_DEVICE);
1515 if (dma_mapping_error(ndev->dev.parent, dma_addr))
2f45d190
SS		 1516 goto unmap;
1517
1518 desc++;
1519 desc->ds_tagl = cpu_to_le16(len);
c156633f
SS		 1520 desc->dptr = cpu_to_le32(dma_addr);
1521
1522 /* TX timestamp required */
1523 if (q == RAVB_NC) {
1524 ts_skb = kmalloc(sizeof(*ts_skb), GFP_ATOMIC);
1525 if (!ts_skb) {
2f45d190 1526 desc--;
e2dbb33a 1527 dma_unmap_single(ndev->dev.parent, dma_addr, len,
c156633f 1528 DMA_TO_DEVICE);
2f45d190 1529 goto unmap;
c156633f
SS		 1530 }
1531 ts_skb->skb = skb;
1532 ts_skb->tag = priv->ts_skb_tag++;
1533 priv->ts_skb_tag &= 0x3ff;
1534 list_add_tail(&ts_skb->list, &priv->ts_skb_list);
1535
1536 /* TAG and timestamp required flag */
1537 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
c156633f
SS		 1538 desc->tagh_tsr = (ts_skb->tag >> 4) | TX_TSR;
1539 desc->ds_tagl |= le16_to_cpu(ts_skb->tag << 12);
1540 }
1541
d7be81a5 1542 skb_tx_timestamp(skb);
c156633f
SS		 1543 /* Descriptor type must be set after all the above writes */
1544 dma_wmb();
2f45d190
SS		 1545 desc->die_dt = DT_FEND;
1546 desc--;
1547 desc->die_dt = DT_FSTART;
c156633f 1548
568b3ce7 1549 ravb_modify(ndev, TCCR, TCCR_TSRQ0 << q, TCCR_TSRQ0 << q);
c156633f 1550
2f45d190
SS		 1551 priv->cur_tx[q] += NUM_TX_DESC;
1552 if (priv->cur_tx[q] - priv->dirty_tx[q] >
1553 (priv->num_tx_ring[q] - 1) * NUM_TX_DESC && !ravb_tx_free(ndev, q))
c156633f
SS		 1554 netif_stop_subqueue(ndev, q);
1555
1556exit:
1557 mmiowb();
1558 spin_unlock_irqrestore(&priv->lock, flags);
1559 return NETDEV_TX_OK;
1560
2f45d190 1561unmap:
e2dbb33a 1562 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
2f45d190 1563 le16_to_cpu(desc->ds_tagl), DMA_TO_DEVICE);
c156633f
SS		 1564drop:
1565 dev_kfree_skb_any(skb);
2f45d190 1566 priv->tx_skb[q][entry / NUM_TX_DESC] = NULL;
c156633f
SS		 1567 goto exit;
1568}
1569
1570static u16 ravb_select_queue(struct net_device *ndev, struct sk_buff *skb,
1571 void *accel_priv, select_queue_fallback_t fallback)
1572{
1573 /* If skb needs TX timestamp, it is handled in network control queue */
1574 return (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) ? RAVB_NC :
1575 RAVB_BE;
1576
1577}
1578
1579static struct net_device_stats *ravb_get_stats(struct net_device *ndev)
1580{
1581 struct ravb_private *priv = netdev_priv(ndev);
1582 struct net_device_stats *nstats, *stats0, *stats1;
1583
1584 nstats = &ndev->stats;
1585 stats0 = &priv->stats[RAVB_BE];
1586 stats1 = &priv->stats[RAVB_NC];
1587
1588 nstats->tx_dropped += ravb_read(ndev, TROCR);
1589 ravb_write(ndev, 0, TROCR); /* (write clear) */
1590 nstats->collisions += ravb_read(ndev, CDCR);
1591 ravb_write(ndev, 0, CDCR); /* (write clear) */
1592 nstats->tx_carrier_errors += ravb_read(ndev, LCCR);
1593 ravb_write(ndev, 0, LCCR); /* (write clear) */
1594
1595 nstats->tx_carrier_errors += ravb_read(ndev, CERCR);
1596 ravb_write(ndev, 0, CERCR); /* (write clear) */
1597 nstats->tx_carrier_errors += ravb_read(ndev, CEECR);
1598 ravb_write(ndev, 0, CEECR); /* (write clear) */
1599
1600 nstats->rx_packets = stats0->rx_packets + stats1->rx_packets;
1601 nstats->tx_packets = stats0->tx_packets + stats1->tx_packets;
1602 nstats->rx_bytes = stats0->rx_bytes + stats1->rx_bytes;
1603 nstats->tx_bytes = stats0->tx_bytes + stats1->tx_bytes;
1604 nstats->multicast = stats0->multicast + stats1->multicast;
1605 nstats->rx_errors = stats0->rx_errors + stats1->rx_errors;
1606 nstats->rx_crc_errors = stats0->rx_crc_errors + stats1->rx_crc_errors;
1607 nstats->rx_frame_errors =
1608 stats0->rx_frame_errors + stats1->rx_frame_errors;
1609 nstats->rx_length_errors =
1610 stats0->rx_length_errors + stats1->rx_length_errors;
1611 nstats->rx_missed_errors =
1612 stats0->rx_missed_errors + stats1->rx_missed_errors;
1613 nstats->rx_over_errors =
1614 stats0->rx_over_errors + stats1->rx_over_errors;
1615
1616 return nstats;
1617}
1618
1619/* Update promiscuous bit */
1620static void ravb_set_rx_mode(struct net_device *ndev)
1621{
1622 struct ravb_private *priv = netdev_priv(ndev);
1623 unsigned long flags;
c156633f
SS		 1624
1625 spin_lock_irqsave(&priv->lock, flags);
568b3ce7
SS		 1626 ravb_modify(ndev, ECMR, ECMR_PRM,
1627 ndev->flags & IFF_PROMISC ? ECMR_PRM : 0);
c156633f
SS		 1628 mmiowb();
1629 spin_unlock_irqrestore(&priv->lock, flags);
1630}
1631
1632/* Device close function for Ethernet AVB */
1633static int ravb_close(struct net_device *ndev)
1634{
1635 struct ravb_private *priv = netdev_priv(ndev);
1636 struct ravb_tstamp_skb *ts_skb, *ts_skb2;
1637
1638 netif_tx_stop_all_queues(ndev);
1639
1640 /* Disable interrupts by clearing the interrupt masks. */
1641 ravb_write(ndev, 0, RIC0);
c156633f
SS		 1642 ravb_write(ndev, 0, RIC2);
1643 ravb_write(ndev, 0, TIC);
1644
a0d2f206 1645 /* Stop PTP Clock driver */
f5d7837f
KM		 1646 if (priv->chip_id == RCAR_GEN2)
1647 ravb_ptp_stop(ndev);
a0d2f206 1648
c156633f
SS		 1649 /* Set the config mode to stop the AVB-DMAC's processes */
1650 if (ravb_stop_dma(ndev) < 0)
1651 netdev_err(ndev,
1652 "device will be stopped after h/w processes are done.\n");
1653
1654 /* Clear the timestamp list */
1655 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, list) {
1656 list_del(&ts_skb->list);
1657 kfree(ts_skb);
1658 }
1659
1660 /* PHY disconnect */
0f635171
PR		 1661 if (ndev->phydev) {
1662 phy_stop(ndev->phydev);
1663 phy_disconnect(ndev->phydev);
c156633f
SS		 1664 }
1665
ccf92824
GU		 1666 if (priv->chip_id != RCAR_GEN2) {
1667 free_irq(priv->tx_irqs[RAVB_NC], ndev);
1668 free_irq(priv->rx_irqs[RAVB_NC], ndev);
1669 free_irq(priv->tx_irqs[RAVB_BE], ndev);
1670 free_irq(priv->rx_irqs[RAVB_BE], ndev);
7fa816b9 1671 free_irq(priv->emac_irq, ndev);
ccf92824 1672 }
c156633f
SS		 1673 free_irq(ndev->irq, ndev);
1674
1675 napi_disable(&priv->napi[RAVB_NC]);
1676 napi_disable(&priv->napi[RAVB_BE]);
1677
1678 /* Free all the skb's in the RX queue and the DMA buffers. */
1679 ravb_ring_free(ndev, RAVB_BE);
1680 ravb_ring_free(ndev, RAVB_NC);
1681
1682 return 0;
1683}
1684
1685static int ravb_hwtstamp_get(struct net_device *ndev, struct ifreq *req)
1686{
1687 struct ravb_private *priv = netdev_priv(ndev);
1688 struct hwtstamp_config config;
1689
1690 config.flags = 0;
1691 config.tx_type = priv->tstamp_tx_ctrl ? HWTSTAMP_TX_ON :
1692 HWTSTAMP_TX_OFF;
1693 if (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE_V2_L2_EVENT)
1694 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
1695 else if (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE_ALL)
1696 config.rx_filter = HWTSTAMP_FILTER_ALL;
1697 else
1698 config.rx_filter = HWTSTAMP_FILTER_NONE;
1699
1700 return copy_to_user(req->ifr_data, &config, sizeof(config)) ?
1701 -EFAULT : 0;
1702}
1703
1704/* Control hardware time stamping */
1705static int ravb_hwtstamp_set(struct net_device *ndev, struct ifreq *req)
1706{
1707 struct ravb_private *priv = netdev_priv(ndev);
1708 struct hwtstamp_config config;
1709 u32 tstamp_rx_ctrl = RAVB_RXTSTAMP_ENABLED;
1710 u32 tstamp_tx_ctrl;
1711
1712 if (copy_from_user(&config, req->ifr_data, sizeof(config)))
1713 return -EFAULT;
1714
1715 /* Reserved for future extensions */
1716 if (config.flags)
1717 return -EINVAL;
1718
1719 switch (config.tx_type) {
1720 case HWTSTAMP_TX_OFF:
1721 tstamp_tx_ctrl = 0;
1722 break;
1723 case HWTSTAMP_TX_ON:
1724 tstamp_tx_ctrl = RAVB_TXTSTAMP_ENABLED;
1725 break;
1726 default:
1727 return -ERANGE;
1728 }
1729
1730 switch (config.rx_filter) {
1731 case HWTSTAMP_FILTER_NONE:
1732 tstamp_rx_ctrl = 0;
1733 break;
1734 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1735 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_V2_L2_EVENT;
1736 break;
1737 default:
1738 config.rx_filter = HWTSTAMP_FILTER_ALL;
1739 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_ALL;
1740 }
1741
1742 priv->tstamp_tx_ctrl = tstamp_tx_ctrl;
1743 priv->tstamp_rx_ctrl = tstamp_rx_ctrl;
1744
1745 return copy_to_user(req->ifr_data, &config, sizeof(config)) ?
1746 -EFAULT : 0;
1747}
1748
1749/* ioctl to device function */
1750static int ravb_do_ioctl(struct net_device *ndev, struct ifreq *req, int cmd)
1751{
0f635171 1752 struct phy_device *phydev = ndev->phydev;
c156633f
SS		 1753
1754 if (!netif_running(ndev))
1755 return -EINVAL;
1756
1757 if (!phydev)
1758 return -ENODEV;
1759
1760 switch (cmd) {
1761 case SIOCGHWTSTAMP:
1762 return ravb_hwtstamp_get(ndev, req);
1763 case SIOCSHWTSTAMP:
1764 return ravb_hwtstamp_set(ndev, req);
1765 }
1766
1767 return phy_mii_ioctl(phydev, req, cmd);
1768}
1769
1770static const struct net_device_ops ravb_netdev_ops = {
1771 .ndo_open = ravb_open,
1772 .ndo_stop = ravb_close,
1773 .ndo_start_xmit = ravb_start_xmit,
1774 .ndo_select_queue = ravb_select_queue,
1775 .ndo_get_stats = ravb_get_stats,
1776 .ndo_set_rx_mode = ravb_set_rx_mode,
1777 .ndo_tx_timeout = ravb_tx_timeout,
1778 .ndo_do_ioctl = ravb_do_ioctl,
1779 .ndo_validate_addr = eth_validate_addr,
1780 .ndo_set_mac_address = eth_mac_addr,
1781 .ndo_change_mtu = eth_change_mtu,
1782};
1783
1784/* MDIO bus init function */
1785static int ravb_mdio_init(struct ravb_private *priv)
1786{
1787 struct platform_device *pdev = priv->pdev;
1788 struct device *dev = &pdev->dev;
1789 int error;
1790
1791 /* Bitbang init */
1792 priv->mdiobb.ops = &bb_ops;
1793
1794 /* MII controller setting */
1795 priv->mii_bus = alloc_mdio_bitbang(&priv->mdiobb);
1796 if (!priv->mii_bus)
1797 return -ENOMEM;
1798
1799 /* Hook up MII support for ethtool */
1800 priv->mii_bus->name = "ravb_mii";
1801 priv->mii_bus->parent = dev;
1802 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
1803 pdev->name, pdev->id);
1804
1805 /* Register MDIO bus */
1806 error = of_mdiobus_register(priv->mii_bus, dev->of_node);
1807 if (error)
1808 goto out_free_bus;
1809
1810 return 0;
1811
1812out_free_bus:
1813 free_mdio_bitbang(priv->mii_bus);
1814 return error;
1815}
1816
1817/* MDIO bus release function */
1818static int ravb_mdio_release(struct ravb_private *priv)
1819{
1820 /* Unregister mdio bus */
1821 mdiobus_unregister(priv->mii_bus);
1822
1823 /* Free bitbang info */
1824 free_mdio_bitbang(priv->mii_bus);
1825
1826 return 0;
1827}
1828
22d4df8f
KM		 1829static const struct of_device_id ravb_match_table[] = {
1830 { .compatible = "renesas,etheravb-r8a7790", .data = (void *)RCAR_GEN2 },
1831 { .compatible = "renesas,etheravb-r8a7794", .data = (void *)RCAR_GEN2 },
0e874361 1832 { .compatible = "renesas,etheravb-rcar-gen2", .data = (void *)RCAR_GEN2 },
22d4df8f 1833 { .compatible = "renesas,etheravb-r8a7795", .data = (void *)RCAR_GEN3 },
0e874361 1834 { .compatible = "renesas,etheravb-rcar-gen3", .data = (void *)RCAR_GEN3 },
22d4df8f
KM		 1835 { }
1836};
1837MODULE_DEVICE_TABLE(of, ravb_match_table);
1838
b3d39a88
SH		 1839static int ravb_set_gti(struct net_device *ndev)
1840{
1841
1842 struct device *dev = ndev->dev.parent;
1843 struct device_node *np = dev->of_node;
1844 unsigned long rate;
1845 struct clk *clk;
1846 uint64_t inc;
1847
1848 clk = of_clk_get(np, 0);
1849 if (IS_ERR(clk)) {
1850 dev_err(dev, "could not get clock\n");
1851 return PTR_ERR(clk);
1852 }
1853
1854 rate = clk_get_rate(clk);
1855 clk_put(clk);
1856
a6d37131
WS		 1857 if (!rate)
1858 return -EINVAL;
1859
b3d39a88
SH		 1860 inc = 1000000000ULL << 20;
1861 do_div(inc, rate);
1862
1863 if (inc < GTI_TIV_MIN || inc > GTI_TIV_MAX) {
1864 dev_err(dev, "gti.tiv increment 0x%llx is outside the range 0x%x - 0x%x\n",
1865 inc, GTI_TIV_MIN, GTI_TIV_MAX);
1866 return -EINVAL;
1867 }
1868
1869 ravb_write(ndev, inc, GTI);
1870
1871 return 0;
1872}
1873
0184165b
NS		 1874static void ravb_set_config_mode(struct net_device *ndev)
1875{
1876 struct ravb_private *priv = netdev_priv(ndev);
1877
1878 if (priv->chip_id == RCAR_GEN2) {
1879 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG);
1880 /* Set CSEL value */
1881 ravb_modify(ndev, CCC, CCC_CSEL, CCC_CSEL_HPB);
1882 } else {
1883 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG |
1884 CCC_GAC | CCC_CSEL_HPB);
1885 }
1886}
1887
c156633f
SS		 1888static int ravb_probe(struct platform_device *pdev)
1889{
1890 struct device_node *np = pdev->dev.of_node;
1891 struct ravb_private *priv;
22d4df8f 1892 enum ravb_chip_id chip_id;
c156633f
SS		 1893 struct net_device *ndev;
1894 int error, irq, q;
1895 struct resource *res;
f51bdc23 1896 int i;
c156633f
SS		 1897
1898 if (!np) {
1899 dev_err(&pdev->dev,
1900 "this driver is required to be instantiated from device tree\n");
1901 return -EINVAL;
1902 }
1903
1904 /* Get base address */
1905 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1906 if (!res) {
1907 dev_err(&pdev->dev, "invalid resource\n");
1908 return -EINVAL;
1909 }
1910
1911 ndev = alloc_etherdev_mqs(sizeof(struct ravb_private),
1912 NUM_TX_QUEUE, NUM_RX_QUEUE);
1913 if (!ndev)
1914 return -ENOMEM;
1915
1916 pm_runtime_enable(&pdev->dev);
1917 pm_runtime_get_sync(&pdev->dev);
1918
1919 /* The Ether-specific entries in the device structure. */
1920 ndev->base_addr = res->start;
22d4df8f 1921
e8668630 1922 chip_id = (enum ravb_chip_id)of_device_get_match_data(&pdev->dev);
22d4df8f
KM		 1923
1924 if (chip_id == RCAR_GEN3)
1925 irq = platform_get_irq_byname(pdev, "ch22");
1926 else
1927 irq = platform_get_irq(pdev, 0);
c156633f 1928 if (irq < 0) {
f375339e 1929 error = irq;
c156633f
SS		 1930 goto out_release;
1931 }
1932 ndev->irq = irq;
1933
1934 SET_NETDEV_DEV(ndev, &pdev->dev);
1935
1936 priv = netdev_priv(ndev);
1937 priv->ndev = ndev;
1938 priv->pdev = pdev;
1939 priv->num_tx_ring[RAVB_BE] = BE_TX_RING_SIZE;
1940 priv->num_rx_ring[RAVB_BE] = BE_RX_RING_SIZE;
1941 priv->num_tx_ring[RAVB_NC] = NC_TX_RING_SIZE;
1942 priv->num_rx_ring[RAVB_NC] = NC_RX_RING_SIZE;
1943 priv->addr = devm_ioremap_resource(&pdev->dev, res);
1944 if (IS_ERR(priv->addr)) {
1945 error = PTR_ERR(priv->addr);
1946 goto out_release;
1947 }
1948
1949 spin_lock_init(&priv->lock);
1950 INIT_WORK(&priv->work, ravb_tx_timeout_work);
1951
1952 priv->phy_interface = of_get_phy_mode(np);
1953
1954 priv->no_avb_link = of_property_read_bool(np, "renesas,no-ether-link");
1955 priv->avb_link_active_low =
1956 of_property_read_bool(np, "renesas,ether-link-active-low");
1957
22d4df8f
KM		 1958 if (chip_id == RCAR_GEN3) {
1959 irq = platform_get_irq_byname(pdev, "ch24");
1960 if (irq < 0) {
1961 error = irq;
1962 goto out_release;
1963 }
1964 priv->emac_irq = irq;
f51bdc23
KM		 1965 for (i = 0; i < NUM_RX_QUEUE; i++) {
1966 irq = platform_get_irq_byname(pdev, ravb_rx_irqs[i]);
1967 if (irq < 0) {
1968 error = irq;
1969 goto out_release;
1970 }
1971 priv->rx_irqs[i] = irq;
1972 }
1973 for (i = 0; i < NUM_TX_QUEUE; i++) {
1974 irq = platform_get_irq_byname(pdev, ravb_tx_irqs[i]);
1975 if (irq < 0) {
1976 error = irq;
1977 goto out_release;
1978 }
1979 priv->tx_irqs[i] = irq;
1980 }
22d4df8f
KM		 1981 }
1982
1983 priv->chip_id = chip_id;
1984
c156633f
SS		 1985 /* Set function */
1986 ndev->netdev_ops = &ravb_netdev_ops;
1987 ndev->ethtool_ops = &ravb_ethtool_ops;
1988
1989 /* Set AVB config mode */
0184165b 1990 ravb_set_config_mode(ndev);
c156633f 1991
c156633f 1992 /* Set GTI value */
b3d39a88
SH		 1993 error = ravb_set_gti(ndev);
1994 if (error)
1995 goto out_release;
c156633f
SS		 1996
1997 /* Request GTI loading */
568b3ce7 1998 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI);
c156633f
SS		 1999
2000 /* Allocate descriptor base address table */
2001 priv->desc_bat_size = sizeof(struct ravb_desc) * DBAT_ENTRY_NUM;
e2dbb33a 2002 priv->desc_bat = dma_alloc_coherent(ndev->dev.parent, priv->desc_bat_size,
c156633f
SS		 2003 &priv->desc_bat_dma, GFP_KERNEL);
2004 if (!priv->desc_bat) {
c4511132 2005 dev_err(&pdev->dev,
c156633f
SS		 2006 "Cannot allocate desc base address table (size %d bytes)\n",
2007 priv->desc_bat_size);
2008 error = -ENOMEM;
2009 goto out_release;
2010 }
2011 for (q = RAVB_BE; q < DBAT_ENTRY_NUM; q++)
2012 priv->desc_bat[q].die_dt = DT_EOS;
2013 ravb_write(ndev, priv->desc_bat_dma, DBAT);
2014
2015 /* Initialise HW timestamp list */
2016 INIT_LIST_HEAD(&priv->ts_skb_list);
2017
f5d7837f
KM		 2018 /* Initialise PTP Clock driver */
2019 if (chip_id != RCAR_GEN2)
2020 ravb_ptp_init(ndev, pdev);
2021
c156633f
SS		 2022 /* Debug message level */
2023 priv->msg_enable = RAVB_DEF_MSG_ENABLE;
2024
2025 /* Read and set MAC address */
2026 ravb_read_mac_address(ndev, of_get_mac_address(np));
2027 if (!is_valid_ether_addr(ndev->dev_addr)) {
2028 dev_warn(&pdev->dev,
2029 "no valid MAC address supplied, using a random one\n");
2030 eth_hw_addr_random(ndev);
2031 }
2032
2033 /* MDIO bus init */
2034 error = ravb_mdio_init(priv);
2035 if (error) {
c4511132 2036 dev_err(&pdev->dev, "failed to initialize MDIO\n");
c156633f
SS		 2037 goto out_dma_free;
2038 }
2039
2040 netif_napi_add(ndev, &priv->napi[RAVB_BE], ravb_poll, 64);
2041 netif_napi_add(ndev, &priv->napi[RAVB_NC], ravb_poll, 64);
2042
2043 /* Network device register */
2044 error = register_netdev(ndev);
2045 if (error)
2046 goto out_napi_del;
2047
2048 /* Print device information */
2049 netdev_info(ndev, "Base address at %#x, %pM, IRQ %d.\n",
2050 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
2051
2052 platform_set_drvdata(pdev, ndev);
2053
2054 return 0;
2055
2056out_napi_del:
2057 netif_napi_del(&priv->napi[RAVB_NC]);
2058 netif_napi_del(&priv->napi[RAVB_BE]);
2059 ravb_mdio_release(priv);
2060out_dma_free:
e2dbb33a 2061 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat,
c156633f 2062 priv->desc_bat_dma);
f5d7837f
KM		 2063
2064 /* Stop PTP Clock driver */
2065 if (chip_id != RCAR_GEN2)
2066 ravb_ptp_stop(ndev);
c156633f
SS		 2067out_release:
2068 if (ndev)
2069 free_netdev(ndev);
2070
2071 pm_runtime_put(&pdev->dev);
2072 pm_runtime_disable(&pdev->dev);
2073 return error;
2074}
2075
2076static int ravb_remove(struct platform_device *pdev)
2077{
2078 struct net_device *ndev = platform_get_drvdata(pdev);
2079 struct ravb_private *priv = netdev_priv(ndev);
2080
f5d7837f
KM		 2081 /* Stop PTP Clock driver */
2082 if (priv->chip_id != RCAR_GEN2)
2083 ravb_ptp_stop(ndev);
2084
e2dbb33a 2085 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat,
c156633f
SS		 2086 priv->desc_bat_dma);
2087 /* Set reset mode */
2088 ravb_write(ndev, CCC_OPC_RESET, CCC);
2089 pm_runtime_put_sync(&pdev->dev);
2090 unregister_netdev(ndev);
2091 netif_napi_del(&priv->napi[RAVB_NC]);
2092 netif_napi_del(&priv->napi[RAVB_BE]);
2093 ravb_mdio_release(priv);
2094 pm_runtime_disable(&pdev->dev);
2095 free_netdev(ndev);
2096 platform_set_drvdata(pdev, NULL);
2097
2098 return 0;
2099}
2100
2101#ifdef CONFIG_PM
b89b815c 2102static int ravb_suspend(struct device *dev)
0184165b
NS		 2103{
2104 struct net_device *ndev = dev_get_drvdata(dev);
2105 int ret = 0;
2106
2107 if (netif_running(ndev)) {
2108 netif_device_detach(ndev);
2109 ret = ravb_close(ndev);
2110 }
2111
2112 return ret;
2113}
2114
b89b815c 2115static int ravb_resume(struct device *dev)
0184165b
NS		 2116{
2117 struct net_device *ndev = dev_get_drvdata(dev);
2118 struct ravb_private *priv = netdev_priv(ndev);
2119 int ret = 0;
2120
2121 /* All register have been reset to default values.
2122 * Restore all registers which where setup at probe time and
2123 * reopen device if it was running before system suspended.
2124 */
2125
2126 /* Set AVB config mode */
2127 ravb_set_config_mode(ndev);
2128
2129 /* Set GTI value */
2130 ret = ravb_set_gti(ndev);
2131 if (ret)
2132 return ret;
2133
2134 /* Request GTI loading */
2135 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI);
2136
2137 /* Restore descriptor base address table */
2138 ravb_write(ndev, priv->desc_bat_dma, DBAT);
2139
2140 if (netif_running(ndev)) {
2141 ret = ravb_open(ndev);
2142 if (ret < 0)
2143 return ret;
2144 netif_device_attach(ndev);
2145 }
2146
2147 return ret;
2148}
2149
c156633f
SS		 2150static int ravb_runtime_nop(struct device *dev)
2151{
2152 /* Runtime PM callback shared between ->runtime_suspend()
2153 * and ->runtime_resume(). Simply returns success.
2154 *
2155 * This driver re-initializes all registers after
2156 * pm_runtime_get_sync() anyway so there is no need
2157 * to save and restore registers here.
2158 */
2159 return 0;
2160}
2161
2162static const struct dev_pm_ops ravb_dev_pm_ops = {
b89b815c 2163 SET_SYSTEM_SLEEP_PM_OPS(ravb_suspend, ravb_resume)
524c6f69 2164 SET_RUNTIME_PM_OPS(ravb_runtime_nop, ravb_runtime_nop, NULL)
c156633f
SS		 2165};
2166
2167#define RAVB_PM_OPS (&ravb_dev_pm_ops)
2168#else
2169#define RAVB_PM_OPS NULL
2170#endif
2171
c156633f
SS		 2172static struct platform_driver ravb_driver = {
2173 .probe = ravb_probe,
2174 .remove = ravb_remove,
2175 .driver = {
2176 .name = "ravb",
2177 .pm = RAVB_PM_OPS,
2178 .of_match_table = ravb_match_table,
2179 },
2180};
2181
2182module_platform_driver(ravb_driver);
2183
2184MODULE_AUTHOR("Mitsuhiro Kimura, Masaru Nagai");
2185MODULE_DESCRIPTION("Renesas Ethernet AVB driver");
2186MODULE_LICENSE("GPL v2");
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