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c156633f SS |
1 | /* Renesas Ethernet AVB device driver |
2 | * | |
3 | * Copyright (C) 2014-2015 Renesas Electronics Corporation | |
4 | * Copyright (C) 2015 Renesas Solutions Corp. | |
5 | * Copyright (C) 2015 Cogent Embedded, Inc. <source@cogentembedded.com> | |
6 | * | |
7 | * Based on the SuperH Ethernet driver | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify it | |
10 | * under the terms and conditions of the GNU General Public License version 2, | |
11 | * as published by the Free Software Foundation. | |
12 | */ | |
13 | ||
14 | #include <linux/cache.h> | |
15 | #include <linux/clk.h> | |
16 | #include <linux/delay.h> | |
17 | #include <linux/dma-mapping.h> | |
18 | #include <linux/err.h> | |
19 | #include <linux/etherdevice.h> | |
20 | #include <linux/ethtool.h> | |
21 | #include <linux/if_vlan.h> | |
22 | #include <linux/kernel.h> | |
23 | #include <linux/list.h> | |
24 | #include <linux/module.h> | |
25 | #include <linux/net_tstamp.h> | |
26 | #include <linux/of.h> | |
27 | #include <linux/of_device.h> | |
28 | #include <linux/of_irq.h> | |
29 | #include <linux/of_mdio.h> | |
30 | #include <linux/of_net.h> | |
c156633f SS |
31 | #include <linux/pm_runtime.h> |
32 | #include <linux/slab.h> | |
33 | #include <linux/spinlock.h> | |
34 | ||
35 | #include "ravb.h" | |
36 | ||
37 | #define RAVB_DEF_MSG_ENABLE \ | |
38 | (NETIF_MSG_LINK | \ | |
39 | NETIF_MSG_TIMER | \ | |
40 | NETIF_MSG_RX_ERR | \ | |
41 | NETIF_MSG_TX_ERR) | |
42 | ||
a0d2f206 | 43 | int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value) |
c156633f SS |
44 | { |
45 | int i; | |
46 | ||
47 | for (i = 0; i < 10000; i++) { | |
48 | if ((ravb_read(ndev, reg) & mask) == value) | |
49 | return 0; | |
50 | udelay(10); | |
51 | } | |
52 | return -ETIMEDOUT; | |
53 | } | |
54 | ||
55 | static int ravb_config(struct net_device *ndev) | |
56 | { | |
57 | int error; | |
58 | ||
59 | /* Set config mode */ | |
60 | ravb_write(ndev, (ravb_read(ndev, CCC) & ~CCC_OPC) | CCC_OPC_CONFIG, | |
61 | CCC); | |
62 | /* Check if the operating mode is changed to the config mode */ | |
63 | error = ravb_wait(ndev, CSR, CSR_OPS, CSR_OPS_CONFIG); | |
64 | if (error) | |
65 | netdev_err(ndev, "failed to switch device to config mode\n"); | |
66 | ||
67 | return error; | |
68 | } | |
69 | ||
70 | static void ravb_set_duplex(struct net_device *ndev) | |
71 | { | |
72 | struct ravb_private *priv = netdev_priv(ndev); | |
73 | u32 ecmr = ravb_read(ndev, ECMR); | |
74 | ||
75 | if (priv->duplex) /* Full */ | |
76 | ecmr |= ECMR_DM; | |
77 | else /* Half */ | |
78 | ecmr &= ~ECMR_DM; | |
79 | ravb_write(ndev, ecmr, ECMR); | |
80 | } | |
81 | ||
82 | static void ravb_set_rate(struct net_device *ndev) | |
83 | { | |
84 | struct ravb_private *priv = netdev_priv(ndev); | |
85 | ||
86 | switch (priv->speed) { | |
87 | case 100: /* 100BASE */ | |
88 | ravb_write(ndev, GECMR_SPEED_100, GECMR); | |
89 | break; | |
90 | case 1000: /* 1000BASE */ | |
91 | ravb_write(ndev, GECMR_SPEED_1000, GECMR); | |
92 | break; | |
93 | default: | |
94 | break; | |
95 | } | |
96 | } | |
97 | ||
98 | static void ravb_set_buffer_align(struct sk_buff *skb) | |
99 | { | |
100 | u32 reserve = (unsigned long)skb->data & (RAVB_ALIGN - 1); | |
101 | ||
102 | if (reserve) | |
103 | skb_reserve(skb, RAVB_ALIGN - reserve); | |
104 | } | |
105 | ||
106 | /* Get MAC address from the MAC address registers | |
107 | * | |
108 | * Ethernet AVB device doesn't have ROM for MAC address. | |
109 | * This function gets the MAC address that was used by a bootloader. | |
110 | */ | |
111 | static void ravb_read_mac_address(struct net_device *ndev, const u8 *mac) | |
112 | { | |
113 | if (mac) { | |
114 | ether_addr_copy(ndev->dev_addr, mac); | |
115 | } else { | |
116 | ndev->dev_addr[0] = (ravb_read(ndev, MAHR) >> 24); | |
117 | ndev->dev_addr[1] = (ravb_read(ndev, MAHR) >> 16) & 0xFF; | |
118 | ndev->dev_addr[2] = (ravb_read(ndev, MAHR) >> 8) & 0xFF; | |
119 | ndev->dev_addr[3] = (ravb_read(ndev, MAHR) >> 0) & 0xFF; | |
120 | ndev->dev_addr[4] = (ravb_read(ndev, MALR) >> 8) & 0xFF; | |
121 | ndev->dev_addr[5] = (ravb_read(ndev, MALR) >> 0) & 0xFF; | |
122 | } | |
123 | } | |
124 | ||
125 | static void ravb_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set) | |
126 | { | |
127 | struct ravb_private *priv = container_of(ctrl, struct ravb_private, | |
128 | mdiobb); | |
129 | u32 pir = ravb_read(priv->ndev, PIR); | |
130 | ||
131 | if (set) | |
132 | pir |= mask; | |
133 | else | |
134 | pir &= ~mask; | |
135 | ravb_write(priv->ndev, pir, PIR); | |
136 | } | |
137 | ||
138 | /* MDC pin control */ | |
139 | static void ravb_set_mdc(struct mdiobb_ctrl *ctrl, int level) | |
140 | { | |
141 | ravb_mdio_ctrl(ctrl, PIR_MDC, level); | |
142 | } | |
143 | ||
144 | /* Data I/O pin control */ | |
145 | static void ravb_set_mdio_dir(struct mdiobb_ctrl *ctrl, int output) | |
146 | { | |
147 | ravb_mdio_ctrl(ctrl, PIR_MMD, output); | |
148 | } | |
149 | ||
150 | /* Set data bit */ | |
151 | static void ravb_set_mdio_data(struct mdiobb_ctrl *ctrl, int value) | |
152 | { | |
153 | ravb_mdio_ctrl(ctrl, PIR_MDO, value); | |
154 | } | |
155 | ||
156 | /* Get data bit */ | |
157 | static int ravb_get_mdio_data(struct mdiobb_ctrl *ctrl) | |
158 | { | |
159 | struct ravb_private *priv = container_of(ctrl, struct ravb_private, | |
160 | mdiobb); | |
161 | ||
162 | return (ravb_read(priv->ndev, PIR) & PIR_MDI) != 0; | |
163 | } | |
164 | ||
165 | /* MDIO bus control struct */ | |
166 | static struct mdiobb_ops bb_ops = { | |
167 | .owner = THIS_MODULE, | |
168 | .set_mdc = ravb_set_mdc, | |
169 | .set_mdio_dir = ravb_set_mdio_dir, | |
170 | .set_mdio_data = ravb_set_mdio_data, | |
171 | .get_mdio_data = ravb_get_mdio_data, | |
172 | }; | |
173 | ||
174 | /* Free skb's and DMA buffers for Ethernet AVB */ | |
175 | static void ravb_ring_free(struct net_device *ndev, int q) | |
176 | { | |
177 | struct ravb_private *priv = netdev_priv(ndev); | |
178 | int ring_size; | |
179 | int i; | |
180 | ||
181 | /* Free RX skb ringbuffer */ | |
182 | if (priv->rx_skb[q]) { | |
183 | for (i = 0; i < priv->num_rx_ring[q]; i++) | |
184 | dev_kfree_skb(priv->rx_skb[q][i]); | |
185 | } | |
186 | kfree(priv->rx_skb[q]); | |
187 | priv->rx_skb[q] = NULL; | |
188 | ||
189 | /* Free TX skb ringbuffer */ | |
190 | if (priv->tx_skb[q]) { | |
191 | for (i = 0; i < priv->num_tx_ring[q]; i++) | |
192 | dev_kfree_skb(priv->tx_skb[q][i]); | |
193 | } | |
194 | kfree(priv->tx_skb[q]); | |
195 | priv->tx_skb[q] = NULL; | |
196 | ||
197 | /* Free aligned TX buffers */ | |
2f45d190 SS |
198 | kfree(priv->tx_align[q]); |
199 | priv->tx_align[q] = NULL; | |
c156633f SS |
200 | |
201 | if (priv->rx_ring[q]) { | |
202 | ring_size = sizeof(struct ravb_ex_rx_desc) * | |
203 | (priv->num_rx_ring[q] + 1); | |
e2dbb33a | 204 | dma_free_coherent(ndev->dev.parent, ring_size, priv->rx_ring[q], |
c156633f SS |
205 | priv->rx_desc_dma[q]); |
206 | priv->rx_ring[q] = NULL; | |
207 | } | |
208 | ||
209 | if (priv->tx_ring[q]) { | |
210 | ring_size = sizeof(struct ravb_tx_desc) * | |
2f45d190 | 211 | (priv->num_tx_ring[q] * NUM_TX_DESC + 1); |
e2dbb33a | 212 | dma_free_coherent(ndev->dev.parent, ring_size, priv->tx_ring[q], |
c156633f SS |
213 | priv->tx_desc_dma[q]); |
214 | priv->tx_ring[q] = NULL; | |
215 | } | |
216 | } | |
217 | ||
218 | /* Format skb and descriptor buffer for Ethernet AVB */ | |
219 | static void ravb_ring_format(struct net_device *ndev, int q) | |
220 | { | |
221 | struct ravb_private *priv = netdev_priv(ndev); | |
aad0d51e SS |
222 | struct ravb_ex_rx_desc *rx_desc; |
223 | struct ravb_tx_desc *tx_desc; | |
224 | struct ravb_desc *desc; | |
c156633f | 225 | int rx_ring_size = sizeof(*rx_desc) * priv->num_rx_ring[q]; |
2f45d190 SS |
226 | int tx_ring_size = sizeof(*tx_desc) * priv->num_tx_ring[q] * |
227 | NUM_TX_DESC; | |
c156633f | 228 | dma_addr_t dma_addr; |
c156633f SS |
229 | int i; |
230 | ||
231 | priv->cur_rx[q] = 0; | |
232 | priv->cur_tx[q] = 0; | |
233 | priv->dirty_rx[q] = 0; | |
234 | priv->dirty_tx[q] = 0; | |
235 | ||
236 | memset(priv->rx_ring[q], 0, rx_ring_size); | |
237 | /* Build RX ring buffer */ | |
238 | for (i = 0; i < priv->num_rx_ring[q]; i++) { | |
c156633f SS |
239 | /* RX descriptor */ |
240 | rx_desc = &priv->rx_ring[q][i]; | |
241 | /* The size of the buffer should be on 16-byte boundary. */ | |
242 | rx_desc->ds_cc = cpu_to_le16(ALIGN(PKT_BUF_SZ, 16)); | |
e2dbb33a | 243 | dma_addr = dma_map_single(ndev->dev.parent, priv->rx_skb[q][i]->data, |
c156633f SS |
244 | ALIGN(PKT_BUF_SZ, 16), |
245 | DMA_FROM_DEVICE); | |
d8b48911 SS |
246 | /* We just set the data size to 0 for a failed mapping which |
247 | * should prevent DMA from happening... | |
248 | */ | |
e2dbb33a | 249 | if (dma_mapping_error(ndev->dev.parent, dma_addr)) |
d8b48911 | 250 | rx_desc->ds_cc = cpu_to_le16(0); |
c156633f SS |
251 | rx_desc->dptr = cpu_to_le32(dma_addr); |
252 | rx_desc->die_dt = DT_FEMPTY; | |
253 | } | |
254 | rx_desc = &priv->rx_ring[q][i]; | |
255 | rx_desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]); | |
256 | rx_desc->die_dt = DT_LINKFIX; /* type */ | |
c156633f SS |
257 | |
258 | memset(priv->tx_ring[q], 0, tx_ring_size); | |
259 | /* Build TX ring buffer */ | |
2f45d190 SS |
260 | for (i = 0, tx_desc = priv->tx_ring[q]; i < priv->num_tx_ring[q]; |
261 | i++, tx_desc++) { | |
262 | tx_desc->die_dt = DT_EEMPTY; | |
263 | tx_desc++; | |
c156633f SS |
264 | tx_desc->die_dt = DT_EEMPTY; |
265 | } | |
c156633f SS |
266 | tx_desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]); |
267 | tx_desc->die_dt = DT_LINKFIX; /* type */ | |
268 | ||
269 | /* RX descriptor base address for best effort */ | |
270 | desc = &priv->desc_bat[RX_QUEUE_OFFSET + q]; | |
271 | desc->die_dt = DT_LINKFIX; /* type */ | |
272 | desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]); | |
273 | ||
274 | /* TX descriptor base address for best effort */ | |
275 | desc = &priv->desc_bat[q]; | |
276 | desc->die_dt = DT_LINKFIX; /* type */ | |
277 | desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]); | |
278 | } | |
279 | ||
280 | /* Init skb and descriptor buffer for Ethernet AVB */ | |
281 | static int ravb_ring_init(struct net_device *ndev, int q) | |
282 | { | |
283 | struct ravb_private *priv = netdev_priv(ndev); | |
d8b48911 | 284 | struct sk_buff *skb; |
c156633f | 285 | int ring_size; |
d8b48911 | 286 | int i; |
c156633f SS |
287 | |
288 | /* Allocate RX and TX skb rings */ | |
289 | priv->rx_skb[q] = kcalloc(priv->num_rx_ring[q], | |
290 | sizeof(*priv->rx_skb[q]), GFP_KERNEL); | |
291 | priv->tx_skb[q] = kcalloc(priv->num_tx_ring[q], | |
292 | sizeof(*priv->tx_skb[q]), GFP_KERNEL); | |
293 | if (!priv->rx_skb[q] || !priv->tx_skb[q]) | |
294 | goto error; | |
295 | ||
d8b48911 SS |
296 | for (i = 0; i < priv->num_rx_ring[q]; i++) { |
297 | skb = netdev_alloc_skb(ndev, PKT_BUF_SZ + RAVB_ALIGN - 1); | |
298 | if (!skb) | |
299 | goto error; | |
300 | ravb_set_buffer_align(skb); | |
301 | priv->rx_skb[q][i] = skb; | |
302 | } | |
303 | ||
c156633f | 304 | /* Allocate rings for the aligned buffers */ |
2f45d190 SS |
305 | priv->tx_align[q] = kmalloc(DPTR_ALIGN * priv->num_tx_ring[q] + |
306 | DPTR_ALIGN - 1, GFP_KERNEL); | |
307 | if (!priv->tx_align[q]) | |
c156633f SS |
308 | goto error; |
309 | ||
310 | /* Allocate all RX descriptors. */ | |
311 | ring_size = sizeof(struct ravb_ex_rx_desc) * (priv->num_rx_ring[q] + 1); | |
e2dbb33a | 312 | priv->rx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size, |
c156633f SS |
313 | &priv->rx_desc_dma[q], |
314 | GFP_KERNEL); | |
315 | if (!priv->rx_ring[q]) | |
316 | goto error; | |
317 | ||
318 | priv->dirty_rx[q] = 0; | |
319 | ||
320 | /* Allocate all TX descriptors. */ | |
2f45d190 SS |
321 | ring_size = sizeof(struct ravb_tx_desc) * |
322 | (priv->num_tx_ring[q] * NUM_TX_DESC + 1); | |
e2dbb33a | 323 | priv->tx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size, |
c156633f SS |
324 | &priv->tx_desc_dma[q], |
325 | GFP_KERNEL); | |
326 | if (!priv->tx_ring[q]) | |
327 | goto error; | |
328 | ||
329 | return 0; | |
330 | ||
331 | error: | |
332 | ravb_ring_free(ndev, q); | |
333 | ||
334 | return -ENOMEM; | |
335 | } | |
336 | ||
337 | /* E-MAC init function */ | |
338 | static void ravb_emac_init(struct net_device *ndev) | |
339 | { | |
340 | struct ravb_private *priv = netdev_priv(ndev); | |
341 | u32 ecmr; | |
342 | ||
343 | /* Receive frame limit set register */ | |
344 | ravb_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, RFLR); | |
345 | ||
346 | /* PAUSE prohibition */ | |
347 | ecmr = ravb_read(ndev, ECMR); | |
348 | ecmr &= ECMR_DM; | |
349 | ecmr |= ECMR_ZPF | (priv->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE; | |
350 | ravb_write(ndev, ecmr, ECMR); | |
351 | ||
352 | ravb_set_rate(ndev); | |
353 | ||
354 | /* Set MAC address */ | |
355 | ravb_write(ndev, | |
356 | (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) | | |
357 | (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR); | |
358 | ravb_write(ndev, | |
359 | (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR); | |
360 | ||
361 | ravb_write(ndev, 1, MPR); | |
362 | ||
363 | /* E-MAC status register clear */ | |
364 | ravb_write(ndev, ECSR_ICD | ECSR_MPD, ECSR); | |
365 | ||
366 | /* E-MAC interrupt enable register */ | |
367 | ravb_write(ndev, ECSIPR_ICDIP | ECSIPR_MPDIP | ECSIPR_LCHNGIP, ECSIPR); | |
368 | } | |
369 | ||
370 | /* Device init function for Ethernet AVB */ | |
371 | static int ravb_dmac_init(struct net_device *ndev) | |
372 | { | |
373 | int error; | |
374 | ||
375 | /* Set CONFIG mode */ | |
376 | error = ravb_config(ndev); | |
377 | if (error) | |
378 | return error; | |
379 | ||
380 | error = ravb_ring_init(ndev, RAVB_BE); | |
381 | if (error) | |
382 | return error; | |
383 | error = ravb_ring_init(ndev, RAVB_NC); | |
384 | if (error) { | |
385 | ravb_ring_free(ndev, RAVB_BE); | |
386 | return error; | |
387 | } | |
388 | ||
389 | /* Descriptor format */ | |
390 | ravb_ring_format(ndev, RAVB_BE); | |
391 | ravb_ring_format(ndev, RAVB_NC); | |
392 | ||
393 | #if defined(__LITTLE_ENDIAN) | |
394 | ravb_write(ndev, ravb_read(ndev, CCC) & ~CCC_BOC, CCC); | |
395 | #else | |
396 | ravb_write(ndev, ravb_read(ndev, CCC) | CCC_BOC, CCC); | |
397 | #endif | |
398 | ||
399 | /* Set AVB RX */ | |
400 | ravb_write(ndev, RCR_EFFS | RCR_ENCF | RCR_ETS0 | 0x18000000, RCR); | |
401 | ||
402 | /* Set FIFO size */ | |
403 | ravb_write(ndev, TGC_TQP_AVBMODE1 | 0x00222200, TGC); | |
404 | ||
405 | /* Timestamp enable */ | |
406 | ravb_write(ndev, TCCR_TFEN, TCCR); | |
407 | ||
408 | /* Interrupt enable: */ | |
409 | /* Frame receive */ | |
410 | ravb_write(ndev, RIC0_FRE0 | RIC0_FRE1, RIC0); | |
411 | /* Receive FIFO full warning */ | |
412 | ravb_write(ndev, RIC1_RFWE, RIC1); | |
413 | /* Receive FIFO full error, descriptor empty */ | |
414 | ravb_write(ndev, RIC2_QFE0 | RIC2_QFE1 | RIC2_RFFE, RIC2); | |
415 | /* Frame transmitted, timestamp FIFO updated */ | |
416 | ravb_write(ndev, TIC_FTE0 | TIC_FTE1 | TIC_TFUE, TIC); | |
417 | ||
418 | /* Setting the control will start the AVB-DMAC process. */ | |
419 | ravb_write(ndev, (ravb_read(ndev, CCC) & ~CCC_OPC) | CCC_OPC_OPERATION, | |
420 | CCC); | |
421 | ||
422 | return 0; | |
423 | } | |
424 | ||
425 | /* Free TX skb function for AVB-IP */ | |
426 | static int ravb_tx_free(struct net_device *ndev, int q) | |
427 | { | |
428 | struct ravb_private *priv = netdev_priv(ndev); | |
429 | struct net_device_stats *stats = &priv->stats[q]; | |
430 | struct ravb_tx_desc *desc; | |
431 | int free_num = 0; | |
aad0d51e | 432 | int entry; |
c156633f SS |
433 | u32 size; |
434 | ||
435 | for (; priv->cur_tx[q] - priv->dirty_tx[q] > 0; priv->dirty_tx[q]++) { | |
2f45d190 SS |
436 | entry = priv->dirty_tx[q] % (priv->num_tx_ring[q] * |
437 | NUM_TX_DESC); | |
c156633f SS |
438 | desc = &priv->tx_ring[q][entry]; |
439 | if (desc->die_dt != DT_FEMPTY) | |
440 | break; | |
441 | /* Descriptor type must be checked before all other reads */ | |
442 | dma_rmb(); | |
443 | size = le16_to_cpu(desc->ds_tagl) & TX_DS; | |
444 | /* Free the original skb. */ | |
2f45d190 | 445 | if (priv->tx_skb[q][entry / NUM_TX_DESC]) { |
e2dbb33a | 446 | dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), |
c156633f | 447 | size, DMA_TO_DEVICE); |
2f45d190 SS |
448 | /* Last packet descriptor? */ |
449 | if (entry % NUM_TX_DESC == NUM_TX_DESC - 1) { | |
450 | entry /= NUM_TX_DESC; | |
451 | dev_kfree_skb_any(priv->tx_skb[q][entry]); | |
452 | priv->tx_skb[q][entry] = NULL; | |
453 | stats->tx_packets++; | |
454 | } | |
c156633f SS |
455 | free_num++; |
456 | } | |
c156633f SS |
457 | stats->tx_bytes += size; |
458 | desc->die_dt = DT_EEMPTY; | |
459 | } | |
460 | return free_num; | |
461 | } | |
462 | ||
463 | static void ravb_get_tx_tstamp(struct net_device *ndev) | |
464 | { | |
465 | struct ravb_private *priv = netdev_priv(ndev); | |
466 | struct ravb_tstamp_skb *ts_skb, *ts_skb2; | |
467 | struct skb_shared_hwtstamps shhwtstamps; | |
468 | struct sk_buff *skb; | |
469 | struct timespec64 ts; | |
470 | u16 tag, tfa_tag; | |
471 | int count; | |
472 | u32 tfa2; | |
473 | ||
474 | count = (ravb_read(ndev, TSR) & TSR_TFFL) >> 8; | |
475 | while (count--) { | |
476 | tfa2 = ravb_read(ndev, TFA2); | |
477 | tfa_tag = (tfa2 & TFA2_TST) >> 16; | |
478 | ts.tv_nsec = (u64)ravb_read(ndev, TFA0); | |
479 | ts.tv_sec = ((u64)(tfa2 & TFA2_TSV) << 32) | | |
480 | ravb_read(ndev, TFA1); | |
481 | memset(&shhwtstamps, 0, sizeof(shhwtstamps)); | |
482 | shhwtstamps.hwtstamp = timespec64_to_ktime(ts); | |
483 | list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, | |
484 | list) { | |
485 | skb = ts_skb->skb; | |
486 | tag = ts_skb->tag; | |
487 | list_del(&ts_skb->list); | |
488 | kfree(ts_skb); | |
489 | if (tag == tfa_tag) { | |
490 | skb_tstamp_tx(skb, &shhwtstamps); | |
491 | break; | |
492 | } | |
493 | } | |
494 | ravb_write(ndev, ravb_read(ndev, TCCR) | TCCR_TFR, TCCR); | |
495 | } | |
496 | } | |
497 | ||
498 | /* Packet receive function for Ethernet AVB */ | |
499 | static bool ravb_rx(struct net_device *ndev, int *quota, int q) | |
500 | { | |
501 | struct ravb_private *priv = netdev_priv(ndev); | |
502 | int entry = priv->cur_rx[q] % priv->num_rx_ring[q]; | |
503 | int boguscnt = (priv->dirty_rx[q] + priv->num_rx_ring[q]) - | |
504 | priv->cur_rx[q]; | |
505 | struct net_device_stats *stats = &priv->stats[q]; | |
506 | struct ravb_ex_rx_desc *desc; | |
507 | struct sk_buff *skb; | |
508 | dma_addr_t dma_addr; | |
509 | struct timespec64 ts; | |
c156633f | 510 | u8 desc_status; |
aad0d51e | 511 | u16 pkt_len; |
c156633f SS |
512 | int limit; |
513 | ||
514 | boguscnt = min(boguscnt, *quota); | |
515 | limit = boguscnt; | |
516 | desc = &priv->rx_ring[q][entry]; | |
517 | while (desc->die_dt != DT_FEMPTY) { | |
518 | /* Descriptor type must be checked before all other reads */ | |
519 | dma_rmb(); | |
520 | desc_status = desc->msc; | |
521 | pkt_len = le16_to_cpu(desc->ds_cc) & RX_DS; | |
522 | ||
523 | if (--boguscnt < 0) | |
524 | break; | |
525 | ||
d8b48911 SS |
526 | /* We use 0-byte descriptors to mark the DMA mapping errors */ |
527 | if (!pkt_len) | |
528 | continue; | |
529 | ||
c156633f SS |
530 | if (desc_status & MSC_MC) |
531 | stats->multicast++; | |
532 | ||
533 | if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF | | |
534 | MSC_CEEF)) { | |
535 | stats->rx_errors++; | |
536 | if (desc_status & MSC_CRC) | |
537 | stats->rx_crc_errors++; | |
538 | if (desc_status & MSC_RFE) | |
539 | stats->rx_frame_errors++; | |
540 | if (desc_status & (MSC_RTLF | MSC_RTSF)) | |
541 | stats->rx_length_errors++; | |
542 | if (desc_status & MSC_CEEF) | |
543 | stats->rx_missed_errors++; | |
544 | } else { | |
545 | u32 get_ts = priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE; | |
546 | ||
547 | skb = priv->rx_skb[q][entry]; | |
548 | priv->rx_skb[q][entry] = NULL; | |
e2dbb33a | 549 | dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), |
e2370f07 SS |
550 | ALIGN(PKT_BUF_SZ, 16), |
551 | DMA_FROM_DEVICE); | |
c156633f SS |
552 | get_ts &= (q == RAVB_NC) ? |
553 | RAVB_RXTSTAMP_TYPE_V2_L2_EVENT : | |
554 | ~RAVB_RXTSTAMP_TYPE_V2_L2_EVENT; | |
555 | if (get_ts) { | |
556 | struct skb_shared_hwtstamps *shhwtstamps; | |
557 | ||
558 | shhwtstamps = skb_hwtstamps(skb); | |
559 | memset(shhwtstamps, 0, sizeof(*shhwtstamps)); | |
560 | ts.tv_sec = ((u64) le16_to_cpu(desc->ts_sh) << | |
561 | 32) | le32_to_cpu(desc->ts_sl); | |
562 | ts.tv_nsec = le32_to_cpu(desc->ts_n); | |
563 | shhwtstamps->hwtstamp = timespec64_to_ktime(ts); | |
564 | } | |
565 | skb_put(skb, pkt_len); | |
566 | skb->protocol = eth_type_trans(skb, ndev); | |
567 | napi_gro_receive(&priv->napi[q], skb); | |
568 | stats->rx_packets++; | |
569 | stats->rx_bytes += pkt_len; | |
570 | } | |
571 | ||
572 | entry = (++priv->cur_rx[q]) % priv->num_rx_ring[q]; | |
573 | desc = &priv->rx_ring[q][entry]; | |
574 | } | |
575 | ||
576 | /* Refill the RX ring buffers. */ | |
577 | for (; priv->cur_rx[q] - priv->dirty_rx[q] > 0; priv->dirty_rx[q]++) { | |
578 | entry = priv->dirty_rx[q] % priv->num_rx_ring[q]; | |
579 | desc = &priv->rx_ring[q][entry]; | |
580 | /* The size of the buffer should be on 16-byte boundary. */ | |
581 | desc->ds_cc = cpu_to_le16(ALIGN(PKT_BUF_SZ, 16)); | |
582 | ||
583 | if (!priv->rx_skb[q][entry]) { | |
584 | skb = netdev_alloc_skb(ndev, | |
585 | PKT_BUF_SZ + RAVB_ALIGN - 1); | |
586 | if (!skb) | |
587 | break; /* Better luck next round. */ | |
588 | ravb_set_buffer_align(skb); | |
e2dbb33a | 589 | dma_addr = dma_map_single(ndev->dev.parent, skb->data, |
c156633f SS |
590 | le16_to_cpu(desc->ds_cc), |
591 | DMA_FROM_DEVICE); | |
592 | skb_checksum_none_assert(skb); | |
d8b48911 SS |
593 | /* We just set the data size to 0 for a failed mapping |
594 | * which should prevent DMA from happening... | |
595 | */ | |
e2dbb33a | 596 | if (dma_mapping_error(ndev->dev.parent, dma_addr)) |
d8b48911 | 597 | desc->ds_cc = cpu_to_le16(0); |
c156633f SS |
598 | desc->dptr = cpu_to_le32(dma_addr); |
599 | priv->rx_skb[q][entry] = skb; | |
600 | } | |
601 | /* Descriptor type must be set after all the above writes */ | |
602 | dma_wmb(); | |
603 | desc->die_dt = DT_FEMPTY; | |
604 | } | |
605 | ||
606 | *quota -= limit - (++boguscnt); | |
607 | ||
608 | return boguscnt <= 0; | |
609 | } | |
610 | ||
611 | static void ravb_rcv_snd_disable(struct net_device *ndev) | |
612 | { | |
613 | /* Disable TX and RX */ | |
614 | ravb_write(ndev, ravb_read(ndev, ECMR) & ~(ECMR_RE | ECMR_TE), ECMR); | |
615 | } | |
616 | ||
617 | static void ravb_rcv_snd_enable(struct net_device *ndev) | |
618 | { | |
619 | /* Enable TX and RX */ | |
620 | ravb_write(ndev, ravb_read(ndev, ECMR) | ECMR_RE | ECMR_TE, ECMR); | |
621 | } | |
622 | ||
623 | /* function for waiting dma process finished */ | |
624 | static int ravb_stop_dma(struct net_device *ndev) | |
625 | { | |
626 | int error; | |
627 | ||
628 | /* Wait for stopping the hardware TX process */ | |
629 | error = ravb_wait(ndev, TCCR, | |
630 | TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 0); | |
631 | if (error) | |
632 | return error; | |
633 | ||
634 | error = ravb_wait(ndev, CSR, CSR_TPO0 | CSR_TPO1 | CSR_TPO2 | CSR_TPO3, | |
635 | 0); | |
636 | if (error) | |
637 | return error; | |
638 | ||
639 | /* Stop the E-MAC's RX/TX processes. */ | |
640 | ravb_rcv_snd_disable(ndev); | |
641 | ||
642 | /* Wait for stopping the RX DMA process */ | |
643 | error = ravb_wait(ndev, CSR, CSR_RPO, 0); | |
644 | if (error) | |
645 | return error; | |
646 | ||
647 | /* Stop AVB-DMAC process */ | |
648 | return ravb_config(ndev); | |
649 | } | |
650 | ||
651 | /* E-MAC interrupt handler */ | |
652 | static void ravb_emac_interrupt(struct net_device *ndev) | |
653 | { | |
654 | struct ravb_private *priv = netdev_priv(ndev); | |
655 | u32 ecsr, psr; | |
656 | ||
657 | ecsr = ravb_read(ndev, ECSR); | |
658 | ravb_write(ndev, ecsr, ECSR); /* clear interrupt */ | |
659 | if (ecsr & ECSR_ICD) | |
660 | ndev->stats.tx_carrier_errors++; | |
661 | if (ecsr & ECSR_LCHNG) { | |
662 | /* Link changed */ | |
663 | if (priv->no_avb_link) | |
664 | return; | |
665 | psr = ravb_read(ndev, PSR); | |
666 | if (priv->avb_link_active_low) | |
667 | psr ^= PSR_LMON; | |
668 | if (!(psr & PSR_LMON)) { | |
669 | /* DIsable RX and TX */ | |
670 | ravb_rcv_snd_disable(ndev); | |
671 | } else { | |
672 | /* Enable RX and TX */ | |
673 | ravb_rcv_snd_enable(ndev); | |
674 | } | |
675 | } | |
676 | } | |
677 | ||
678 | /* Error interrupt handler */ | |
679 | static void ravb_error_interrupt(struct net_device *ndev) | |
680 | { | |
681 | struct ravb_private *priv = netdev_priv(ndev); | |
682 | u32 eis, ris2; | |
683 | ||
684 | eis = ravb_read(ndev, EIS); | |
685 | ravb_write(ndev, ~EIS_QFS, EIS); | |
686 | if (eis & EIS_QFS) { | |
687 | ris2 = ravb_read(ndev, RIS2); | |
688 | ravb_write(ndev, ~(RIS2_QFF0 | RIS2_RFFF), RIS2); | |
689 | ||
690 | /* Receive Descriptor Empty int */ | |
691 | if (ris2 & RIS2_QFF0) | |
692 | priv->stats[RAVB_BE].rx_over_errors++; | |
693 | ||
694 | /* Receive Descriptor Empty int */ | |
695 | if (ris2 & RIS2_QFF1) | |
696 | priv->stats[RAVB_NC].rx_over_errors++; | |
697 | ||
698 | /* Receive FIFO Overflow int */ | |
699 | if (ris2 & RIS2_RFFF) | |
700 | priv->rx_fifo_errors++; | |
701 | } | |
702 | } | |
703 | ||
704 | static irqreturn_t ravb_interrupt(int irq, void *dev_id) | |
705 | { | |
706 | struct net_device *ndev = dev_id; | |
707 | struct ravb_private *priv = netdev_priv(ndev); | |
708 | irqreturn_t result = IRQ_NONE; | |
709 | u32 iss; | |
710 | ||
711 | spin_lock(&priv->lock); | |
712 | /* Get interrupt status */ | |
713 | iss = ravb_read(ndev, ISS); | |
714 | ||
715 | /* Received and transmitted interrupts */ | |
716 | if (iss & (ISS_FRS | ISS_FTS | ISS_TFUS)) { | |
717 | u32 ris0 = ravb_read(ndev, RIS0); | |
718 | u32 ric0 = ravb_read(ndev, RIC0); | |
719 | u32 tis = ravb_read(ndev, TIS); | |
720 | u32 tic = ravb_read(ndev, TIC); | |
721 | int q; | |
722 | ||
723 | /* Timestamp updated */ | |
724 | if (tis & TIS_TFUF) { | |
725 | ravb_write(ndev, ~TIS_TFUF, TIS); | |
726 | ravb_get_tx_tstamp(ndev); | |
727 | result = IRQ_HANDLED; | |
728 | } | |
729 | ||
730 | /* Network control and best effort queue RX/TX */ | |
731 | for (q = RAVB_NC; q >= RAVB_BE; q--) { | |
732 | if (((ris0 & ric0) & BIT(q)) || | |
733 | ((tis & tic) & BIT(q))) { | |
734 | if (napi_schedule_prep(&priv->napi[q])) { | |
735 | /* Mask RX and TX interrupts */ | |
2452cb0c MN |
736 | ric0 &= ~BIT(q); |
737 | tic &= ~BIT(q); | |
738 | ravb_write(ndev, ric0, RIC0); | |
739 | ravb_write(ndev, tic, TIC); | |
c156633f SS |
740 | __napi_schedule(&priv->napi[q]); |
741 | } else { | |
742 | netdev_warn(ndev, | |
743 | "ignoring interrupt, rx status 0x%08x, rx mask 0x%08x,\n", | |
744 | ris0, ric0); | |
745 | netdev_warn(ndev, | |
746 | " tx status 0x%08x, tx mask 0x%08x.\n", | |
747 | tis, tic); | |
748 | } | |
749 | result = IRQ_HANDLED; | |
750 | } | |
751 | } | |
752 | } | |
753 | ||
754 | /* E-MAC status summary */ | |
755 | if (iss & ISS_MS) { | |
756 | ravb_emac_interrupt(ndev); | |
757 | result = IRQ_HANDLED; | |
758 | } | |
759 | ||
760 | /* Error status summary */ | |
761 | if (iss & ISS_ES) { | |
762 | ravb_error_interrupt(ndev); | |
763 | result = IRQ_HANDLED; | |
764 | } | |
765 | ||
a0d2f206 SS |
766 | if (iss & ISS_CGIS) |
767 | result = ravb_ptp_interrupt(ndev); | |
768 | ||
c156633f SS |
769 | mmiowb(); |
770 | spin_unlock(&priv->lock); | |
771 | return result; | |
772 | } | |
773 | ||
774 | static int ravb_poll(struct napi_struct *napi, int budget) | |
775 | { | |
776 | struct net_device *ndev = napi->dev; | |
777 | struct ravb_private *priv = netdev_priv(ndev); | |
778 | unsigned long flags; | |
779 | int q = napi - priv->napi; | |
780 | int mask = BIT(q); | |
781 | int quota = budget; | |
782 | u32 ris0, tis; | |
783 | ||
784 | for (;;) { | |
785 | tis = ravb_read(ndev, TIS); | |
786 | ris0 = ravb_read(ndev, RIS0); | |
787 | if (!((ris0 & mask) || (tis & mask))) | |
788 | break; | |
789 | ||
790 | /* Processing RX Descriptor Ring */ | |
791 | if (ris0 & mask) { | |
792 | /* Clear RX interrupt */ | |
793 | ravb_write(ndev, ~mask, RIS0); | |
794 | if (ravb_rx(ndev, "a, q)) | |
795 | goto out; | |
796 | } | |
797 | /* Processing TX Descriptor Ring */ | |
798 | if (tis & mask) { | |
799 | spin_lock_irqsave(&priv->lock, flags); | |
800 | /* Clear TX interrupt */ | |
801 | ravb_write(ndev, ~mask, TIS); | |
802 | ravb_tx_free(ndev, q); | |
803 | netif_wake_subqueue(ndev, q); | |
804 | mmiowb(); | |
805 | spin_unlock_irqrestore(&priv->lock, flags); | |
806 | } | |
807 | } | |
808 | ||
809 | napi_complete(napi); | |
810 | ||
811 | /* Re-enable RX/TX interrupts */ | |
812 | spin_lock_irqsave(&priv->lock, flags); | |
813 | ravb_write(ndev, ravb_read(ndev, RIC0) | mask, RIC0); | |
814 | ravb_write(ndev, ravb_read(ndev, TIC) | mask, TIC); | |
815 | mmiowb(); | |
816 | spin_unlock_irqrestore(&priv->lock, flags); | |
817 | ||
818 | /* Receive error message handling */ | |
819 | priv->rx_over_errors = priv->stats[RAVB_BE].rx_over_errors; | |
820 | priv->rx_over_errors += priv->stats[RAVB_NC].rx_over_errors; | |
821 | if (priv->rx_over_errors != ndev->stats.rx_over_errors) { | |
822 | ndev->stats.rx_over_errors = priv->rx_over_errors; | |
823 | netif_err(priv, rx_err, ndev, "Receive Descriptor Empty\n"); | |
824 | } | |
825 | if (priv->rx_fifo_errors != ndev->stats.rx_fifo_errors) { | |
826 | ndev->stats.rx_fifo_errors = priv->rx_fifo_errors; | |
827 | netif_err(priv, rx_err, ndev, "Receive FIFO Overflow\n"); | |
828 | } | |
829 | out: | |
830 | return budget - quota; | |
831 | } | |
832 | ||
833 | /* PHY state control function */ | |
834 | static void ravb_adjust_link(struct net_device *ndev) | |
835 | { | |
836 | struct ravb_private *priv = netdev_priv(ndev); | |
837 | struct phy_device *phydev = priv->phydev; | |
838 | bool new_state = false; | |
839 | ||
840 | if (phydev->link) { | |
841 | if (phydev->duplex != priv->duplex) { | |
842 | new_state = true; | |
843 | priv->duplex = phydev->duplex; | |
844 | ravb_set_duplex(ndev); | |
845 | } | |
846 | ||
847 | if (phydev->speed != priv->speed) { | |
848 | new_state = true; | |
849 | priv->speed = phydev->speed; | |
850 | ravb_set_rate(ndev); | |
851 | } | |
852 | if (!priv->link) { | |
853 | ravb_write(ndev, ravb_read(ndev, ECMR) & ~ECMR_TXF, | |
854 | ECMR); | |
855 | new_state = true; | |
856 | priv->link = phydev->link; | |
857 | if (priv->no_avb_link) | |
858 | ravb_rcv_snd_enable(ndev); | |
859 | } | |
860 | } else if (priv->link) { | |
861 | new_state = true; | |
862 | priv->link = 0; | |
863 | priv->speed = 0; | |
864 | priv->duplex = -1; | |
865 | if (priv->no_avb_link) | |
866 | ravb_rcv_snd_disable(ndev); | |
867 | } | |
868 | ||
869 | if (new_state && netif_msg_link(priv)) | |
870 | phy_print_status(phydev); | |
871 | } | |
872 | ||
873 | /* PHY init function */ | |
874 | static int ravb_phy_init(struct net_device *ndev) | |
875 | { | |
876 | struct device_node *np = ndev->dev.parent->of_node; | |
877 | struct ravb_private *priv = netdev_priv(ndev); | |
878 | struct phy_device *phydev; | |
879 | struct device_node *pn; | |
880 | ||
881 | priv->link = 0; | |
882 | priv->speed = 0; | |
883 | priv->duplex = -1; | |
884 | ||
885 | /* Try connecting to PHY */ | |
886 | pn = of_parse_phandle(np, "phy-handle", 0); | |
887 | phydev = of_phy_connect(ndev, pn, ravb_adjust_link, 0, | |
888 | priv->phy_interface); | |
889 | if (!phydev) { | |
890 | netdev_err(ndev, "failed to connect PHY\n"); | |
891 | return -ENOENT; | |
892 | } | |
893 | ||
22d4df8f KM |
894 | /* This driver only support 10/100Mbit speeds on Gen3 |
895 | * at this time. | |
896 | */ | |
897 | if (priv->chip_id == RCAR_GEN3) { | |
898 | int err; | |
899 | ||
900 | err = phy_set_max_speed(phydev, SPEED_100); | |
901 | if (err) { | |
902 | netdev_err(ndev, "failed to limit PHY to 100Mbit/s\n"); | |
903 | phy_disconnect(phydev); | |
904 | return err; | |
905 | } | |
906 | ||
907 | netdev_info(ndev, "limited PHY to 100Mbit/s\n"); | |
908 | } | |
909 | ||
c156633f SS |
910 | netdev_info(ndev, "attached PHY %d (IRQ %d) to driver %s\n", |
911 | phydev->addr, phydev->irq, phydev->drv->name); | |
912 | ||
913 | priv->phydev = phydev; | |
914 | ||
915 | return 0; | |
916 | } | |
917 | ||
918 | /* PHY control start function */ | |
919 | static int ravb_phy_start(struct net_device *ndev) | |
920 | { | |
921 | struct ravb_private *priv = netdev_priv(ndev); | |
922 | int error; | |
923 | ||
924 | error = ravb_phy_init(ndev); | |
925 | if (error) | |
926 | return error; | |
927 | ||
928 | phy_start(priv->phydev); | |
929 | ||
930 | return 0; | |
931 | } | |
932 | ||
933 | static int ravb_get_settings(struct net_device *ndev, struct ethtool_cmd *ecmd) | |
934 | { | |
935 | struct ravb_private *priv = netdev_priv(ndev); | |
936 | int error = -ENODEV; | |
937 | unsigned long flags; | |
938 | ||
939 | if (priv->phydev) { | |
940 | spin_lock_irqsave(&priv->lock, flags); | |
941 | error = phy_ethtool_gset(priv->phydev, ecmd); | |
942 | spin_unlock_irqrestore(&priv->lock, flags); | |
943 | } | |
944 | ||
945 | return error; | |
946 | } | |
947 | ||
948 | static int ravb_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd) | |
949 | { | |
950 | struct ravb_private *priv = netdev_priv(ndev); | |
951 | unsigned long flags; | |
952 | int error; | |
953 | ||
954 | if (!priv->phydev) | |
955 | return -ENODEV; | |
956 | ||
957 | spin_lock_irqsave(&priv->lock, flags); | |
958 | ||
959 | /* Disable TX and RX */ | |
960 | ravb_rcv_snd_disable(ndev); | |
961 | ||
962 | error = phy_ethtool_sset(priv->phydev, ecmd); | |
963 | if (error) | |
964 | goto error_exit; | |
965 | ||
966 | if (ecmd->duplex == DUPLEX_FULL) | |
967 | priv->duplex = 1; | |
968 | else | |
969 | priv->duplex = 0; | |
970 | ||
971 | ravb_set_duplex(ndev); | |
972 | ||
973 | error_exit: | |
974 | mdelay(1); | |
975 | ||
976 | /* Enable TX and RX */ | |
977 | ravb_rcv_snd_enable(ndev); | |
978 | ||
979 | mmiowb(); | |
980 | spin_unlock_irqrestore(&priv->lock, flags); | |
981 | ||
982 | return error; | |
983 | } | |
984 | ||
985 | static int ravb_nway_reset(struct net_device *ndev) | |
986 | { | |
987 | struct ravb_private *priv = netdev_priv(ndev); | |
988 | int error = -ENODEV; | |
989 | unsigned long flags; | |
990 | ||
991 | if (priv->phydev) { | |
992 | spin_lock_irqsave(&priv->lock, flags); | |
993 | error = phy_start_aneg(priv->phydev); | |
994 | spin_unlock_irqrestore(&priv->lock, flags); | |
995 | } | |
996 | ||
997 | return error; | |
998 | } | |
999 | ||
1000 | static u32 ravb_get_msglevel(struct net_device *ndev) | |
1001 | { | |
1002 | struct ravb_private *priv = netdev_priv(ndev); | |
1003 | ||
1004 | return priv->msg_enable; | |
1005 | } | |
1006 | ||
1007 | static void ravb_set_msglevel(struct net_device *ndev, u32 value) | |
1008 | { | |
1009 | struct ravb_private *priv = netdev_priv(ndev); | |
1010 | ||
1011 | priv->msg_enable = value; | |
1012 | } | |
1013 | ||
1014 | static const char ravb_gstrings_stats[][ETH_GSTRING_LEN] = { | |
1015 | "rx_queue_0_current", | |
1016 | "tx_queue_0_current", | |
1017 | "rx_queue_0_dirty", | |
1018 | "tx_queue_0_dirty", | |
1019 | "rx_queue_0_packets", | |
1020 | "tx_queue_0_packets", | |
1021 | "rx_queue_0_bytes", | |
1022 | "tx_queue_0_bytes", | |
1023 | "rx_queue_0_mcast_packets", | |
1024 | "rx_queue_0_errors", | |
1025 | "rx_queue_0_crc_errors", | |
1026 | "rx_queue_0_frame_errors", | |
1027 | "rx_queue_0_length_errors", | |
1028 | "rx_queue_0_missed_errors", | |
1029 | "rx_queue_0_over_errors", | |
1030 | ||
1031 | "rx_queue_1_current", | |
1032 | "tx_queue_1_current", | |
1033 | "rx_queue_1_dirty", | |
1034 | "tx_queue_1_dirty", | |
1035 | "rx_queue_1_packets", | |
1036 | "tx_queue_1_packets", | |
1037 | "rx_queue_1_bytes", | |
1038 | "tx_queue_1_bytes", | |
1039 | "rx_queue_1_mcast_packets", | |
1040 | "rx_queue_1_errors", | |
1041 | "rx_queue_1_crc_errors", | |
1042 | "rx_queue_1_frame_errors_", | |
1043 | "rx_queue_1_length_errors", | |
1044 | "rx_queue_1_missed_errors", | |
1045 | "rx_queue_1_over_errors", | |
1046 | }; | |
1047 | ||
1048 | #define RAVB_STATS_LEN ARRAY_SIZE(ravb_gstrings_stats) | |
1049 | ||
1050 | static int ravb_get_sset_count(struct net_device *netdev, int sset) | |
1051 | { | |
1052 | switch (sset) { | |
1053 | case ETH_SS_STATS: | |
1054 | return RAVB_STATS_LEN; | |
1055 | default: | |
1056 | return -EOPNOTSUPP; | |
1057 | } | |
1058 | } | |
1059 | ||
1060 | static void ravb_get_ethtool_stats(struct net_device *ndev, | |
1061 | struct ethtool_stats *stats, u64 *data) | |
1062 | { | |
1063 | struct ravb_private *priv = netdev_priv(ndev); | |
1064 | int i = 0; | |
1065 | int q; | |
1066 | ||
1067 | /* Device-specific stats */ | |
1068 | for (q = RAVB_BE; q < NUM_RX_QUEUE; q++) { | |
1069 | struct net_device_stats *stats = &priv->stats[q]; | |
1070 | ||
1071 | data[i++] = priv->cur_rx[q]; | |
1072 | data[i++] = priv->cur_tx[q]; | |
1073 | data[i++] = priv->dirty_rx[q]; | |
1074 | data[i++] = priv->dirty_tx[q]; | |
1075 | data[i++] = stats->rx_packets; | |
1076 | data[i++] = stats->tx_packets; | |
1077 | data[i++] = stats->rx_bytes; | |
1078 | data[i++] = stats->tx_bytes; | |
1079 | data[i++] = stats->multicast; | |
1080 | data[i++] = stats->rx_errors; | |
1081 | data[i++] = stats->rx_crc_errors; | |
1082 | data[i++] = stats->rx_frame_errors; | |
1083 | data[i++] = stats->rx_length_errors; | |
1084 | data[i++] = stats->rx_missed_errors; | |
1085 | data[i++] = stats->rx_over_errors; | |
1086 | } | |
1087 | } | |
1088 | ||
1089 | static void ravb_get_strings(struct net_device *ndev, u32 stringset, u8 *data) | |
1090 | { | |
1091 | switch (stringset) { | |
1092 | case ETH_SS_STATS: | |
1093 | memcpy(data, *ravb_gstrings_stats, sizeof(ravb_gstrings_stats)); | |
1094 | break; | |
1095 | } | |
1096 | } | |
1097 | ||
1098 | static void ravb_get_ringparam(struct net_device *ndev, | |
1099 | struct ethtool_ringparam *ring) | |
1100 | { | |
1101 | struct ravb_private *priv = netdev_priv(ndev); | |
1102 | ||
1103 | ring->rx_max_pending = BE_RX_RING_MAX; | |
1104 | ring->tx_max_pending = BE_TX_RING_MAX; | |
1105 | ring->rx_pending = priv->num_rx_ring[RAVB_BE]; | |
1106 | ring->tx_pending = priv->num_tx_ring[RAVB_BE]; | |
1107 | } | |
1108 | ||
1109 | static int ravb_set_ringparam(struct net_device *ndev, | |
1110 | struct ethtool_ringparam *ring) | |
1111 | { | |
1112 | struct ravb_private *priv = netdev_priv(ndev); | |
1113 | int error; | |
1114 | ||
1115 | if (ring->tx_pending > BE_TX_RING_MAX || | |
1116 | ring->rx_pending > BE_RX_RING_MAX || | |
1117 | ring->tx_pending < BE_TX_RING_MIN || | |
1118 | ring->rx_pending < BE_RX_RING_MIN) | |
1119 | return -EINVAL; | |
1120 | if (ring->rx_mini_pending || ring->rx_jumbo_pending) | |
1121 | return -EINVAL; | |
1122 | ||
1123 | if (netif_running(ndev)) { | |
1124 | netif_device_detach(ndev); | |
a0d2f206 SS |
1125 | /* Stop PTP Clock driver */ |
1126 | ravb_ptp_stop(ndev); | |
c156633f SS |
1127 | /* Wait for DMA stopping */ |
1128 | error = ravb_stop_dma(ndev); | |
1129 | if (error) { | |
1130 | netdev_err(ndev, | |
1131 | "cannot set ringparam! Any AVB processes are still running?\n"); | |
1132 | return error; | |
1133 | } | |
1134 | synchronize_irq(ndev->irq); | |
1135 | ||
1136 | /* Free all the skb's in the RX queue and the DMA buffers. */ | |
1137 | ravb_ring_free(ndev, RAVB_BE); | |
1138 | ravb_ring_free(ndev, RAVB_NC); | |
1139 | } | |
1140 | ||
1141 | /* Set new parameters */ | |
1142 | priv->num_rx_ring[RAVB_BE] = ring->rx_pending; | |
1143 | priv->num_tx_ring[RAVB_BE] = ring->tx_pending; | |
1144 | ||
1145 | if (netif_running(ndev)) { | |
1146 | error = ravb_dmac_init(ndev); | |
1147 | if (error) { | |
1148 | netdev_err(ndev, | |
1149 | "%s: ravb_dmac_init() failed, error %d\n", | |
1150 | __func__, error); | |
1151 | return error; | |
1152 | } | |
1153 | ||
1154 | ravb_emac_init(ndev); | |
1155 | ||
a0d2f206 SS |
1156 | /* Initialise PTP Clock driver */ |
1157 | ravb_ptp_init(ndev, priv->pdev); | |
1158 | ||
c156633f SS |
1159 | netif_device_attach(ndev); |
1160 | } | |
1161 | ||
1162 | return 0; | |
1163 | } | |
1164 | ||
1165 | static int ravb_get_ts_info(struct net_device *ndev, | |
1166 | struct ethtool_ts_info *info) | |
1167 | { | |
a0d2f206 SS |
1168 | struct ravb_private *priv = netdev_priv(ndev); |
1169 | ||
c156633f SS |
1170 | info->so_timestamping = |
1171 | SOF_TIMESTAMPING_TX_SOFTWARE | | |
1172 | SOF_TIMESTAMPING_RX_SOFTWARE | | |
1173 | SOF_TIMESTAMPING_SOFTWARE | | |
1174 | SOF_TIMESTAMPING_TX_HARDWARE | | |
1175 | SOF_TIMESTAMPING_RX_HARDWARE | | |
1176 | SOF_TIMESTAMPING_RAW_HARDWARE; | |
1177 | info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON); | |
1178 | info->rx_filters = | |
1179 | (1 << HWTSTAMP_FILTER_NONE) | | |
1180 | (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | | |
1181 | (1 << HWTSTAMP_FILTER_ALL); | |
a0d2f206 | 1182 | info->phc_index = ptp_clock_index(priv->ptp.clock); |
c156633f SS |
1183 | |
1184 | return 0; | |
1185 | } | |
1186 | ||
1187 | static const struct ethtool_ops ravb_ethtool_ops = { | |
1188 | .get_settings = ravb_get_settings, | |
1189 | .set_settings = ravb_set_settings, | |
1190 | .nway_reset = ravb_nway_reset, | |
1191 | .get_msglevel = ravb_get_msglevel, | |
1192 | .set_msglevel = ravb_set_msglevel, | |
1193 | .get_link = ethtool_op_get_link, | |
1194 | .get_strings = ravb_get_strings, | |
1195 | .get_ethtool_stats = ravb_get_ethtool_stats, | |
1196 | .get_sset_count = ravb_get_sset_count, | |
1197 | .get_ringparam = ravb_get_ringparam, | |
1198 | .set_ringparam = ravb_set_ringparam, | |
1199 | .get_ts_info = ravb_get_ts_info, | |
1200 | }; | |
1201 | ||
1202 | /* Network device open function for Ethernet AVB */ | |
1203 | static int ravb_open(struct net_device *ndev) | |
1204 | { | |
1205 | struct ravb_private *priv = netdev_priv(ndev); | |
1206 | int error; | |
1207 | ||
1208 | napi_enable(&priv->napi[RAVB_BE]); | |
1209 | napi_enable(&priv->napi[RAVB_NC]); | |
1210 | ||
1211 | error = request_irq(ndev->irq, ravb_interrupt, IRQF_SHARED, ndev->name, | |
1212 | ndev); | |
1213 | if (error) { | |
1214 | netdev_err(ndev, "cannot request IRQ\n"); | |
1215 | goto out_napi_off; | |
1216 | } | |
1217 | ||
22d4df8f KM |
1218 | if (priv->chip_id == RCAR_GEN3) { |
1219 | error = request_irq(priv->emac_irq, ravb_interrupt, | |
1220 | IRQF_SHARED, ndev->name, ndev); | |
1221 | if (error) { | |
1222 | netdev_err(ndev, "cannot request IRQ\n"); | |
1223 | goto out_free_irq; | |
1224 | } | |
1225 | } | |
1226 | ||
c156633f SS |
1227 | /* Device init */ |
1228 | error = ravb_dmac_init(ndev); | |
1229 | if (error) | |
1230 | goto out_free_irq; | |
1231 | ravb_emac_init(ndev); | |
1232 | ||
a0d2f206 SS |
1233 | /* Initialise PTP Clock driver */ |
1234 | ravb_ptp_init(ndev, priv->pdev); | |
1235 | ||
c156633f SS |
1236 | netif_tx_start_all_queues(ndev); |
1237 | ||
1238 | /* PHY control start */ | |
1239 | error = ravb_phy_start(ndev); | |
1240 | if (error) | |
a0d2f206 | 1241 | goto out_ptp_stop; |
c156633f SS |
1242 | |
1243 | return 0; | |
1244 | ||
a0d2f206 SS |
1245 | out_ptp_stop: |
1246 | /* Stop PTP Clock driver */ | |
1247 | ravb_ptp_stop(ndev); | |
c156633f SS |
1248 | out_free_irq: |
1249 | free_irq(ndev->irq, ndev); | |
22d4df8f | 1250 | free_irq(priv->emac_irq, ndev); |
c156633f SS |
1251 | out_napi_off: |
1252 | napi_disable(&priv->napi[RAVB_NC]); | |
1253 | napi_disable(&priv->napi[RAVB_BE]); | |
1254 | return error; | |
1255 | } | |
1256 | ||
1257 | /* Timeout function for Ethernet AVB */ | |
1258 | static void ravb_tx_timeout(struct net_device *ndev) | |
1259 | { | |
1260 | struct ravb_private *priv = netdev_priv(ndev); | |
1261 | ||
1262 | netif_err(priv, tx_err, ndev, | |
1263 | "transmit timed out, status %08x, resetting...\n", | |
1264 | ravb_read(ndev, ISS)); | |
1265 | ||
1266 | /* tx_errors count up */ | |
1267 | ndev->stats.tx_errors++; | |
1268 | ||
1269 | schedule_work(&priv->work); | |
1270 | } | |
1271 | ||
1272 | static void ravb_tx_timeout_work(struct work_struct *work) | |
1273 | { | |
1274 | struct ravb_private *priv = container_of(work, struct ravb_private, | |
1275 | work); | |
1276 | struct net_device *ndev = priv->ndev; | |
1277 | ||
1278 | netif_tx_stop_all_queues(ndev); | |
1279 | ||
a0d2f206 SS |
1280 | /* Stop PTP Clock driver */ |
1281 | ravb_ptp_stop(ndev); | |
1282 | ||
c156633f SS |
1283 | /* Wait for DMA stopping */ |
1284 | ravb_stop_dma(ndev); | |
1285 | ||
1286 | ravb_ring_free(ndev, RAVB_BE); | |
1287 | ravb_ring_free(ndev, RAVB_NC); | |
1288 | ||
1289 | /* Device init */ | |
1290 | ravb_dmac_init(ndev); | |
1291 | ravb_emac_init(ndev); | |
1292 | ||
a0d2f206 SS |
1293 | /* Initialise PTP Clock driver */ |
1294 | ravb_ptp_init(ndev, priv->pdev); | |
1295 | ||
c156633f SS |
1296 | netif_tx_start_all_queues(ndev); |
1297 | } | |
1298 | ||
1299 | /* Packet transmit function for Ethernet AVB */ | |
1300 | static netdev_tx_t ravb_start_xmit(struct sk_buff *skb, struct net_device *ndev) | |
1301 | { | |
1302 | struct ravb_private *priv = netdev_priv(ndev); | |
c156633f | 1303 | u16 q = skb_get_queue_mapping(skb); |
aad0d51e | 1304 | struct ravb_tstamp_skb *ts_skb; |
c156633f SS |
1305 | struct ravb_tx_desc *desc; |
1306 | unsigned long flags; | |
1307 | u32 dma_addr; | |
1308 | void *buffer; | |
1309 | u32 entry; | |
2f45d190 | 1310 | u32 len; |
c156633f SS |
1311 | |
1312 | spin_lock_irqsave(&priv->lock, flags); | |
2f45d190 SS |
1313 | if (priv->cur_tx[q] - priv->dirty_tx[q] > (priv->num_tx_ring[q] - 1) * |
1314 | NUM_TX_DESC) { | |
c156633f SS |
1315 | netif_err(priv, tx_queued, ndev, |
1316 | "still transmitting with the full ring!\n"); | |
1317 | netif_stop_subqueue(ndev, q); | |
1318 | spin_unlock_irqrestore(&priv->lock, flags); | |
1319 | return NETDEV_TX_BUSY; | |
1320 | } | |
2f45d190 SS |
1321 | entry = priv->cur_tx[q] % (priv->num_tx_ring[q] * NUM_TX_DESC); |
1322 | priv->tx_skb[q][entry / NUM_TX_DESC] = skb; | |
c156633f SS |
1323 | |
1324 | if (skb_put_padto(skb, ETH_ZLEN)) | |
1325 | goto drop; | |
1326 | ||
2f45d190 SS |
1327 | buffer = PTR_ALIGN(priv->tx_align[q], DPTR_ALIGN) + |
1328 | entry / NUM_TX_DESC * DPTR_ALIGN; | |
1329 | len = PTR_ALIGN(skb->data, DPTR_ALIGN) - skb->data; | |
1330 | memcpy(buffer, skb->data, len); | |
e2dbb33a KM |
1331 | dma_addr = dma_map_single(ndev->dev.parent, buffer, len, DMA_TO_DEVICE); |
1332 | if (dma_mapping_error(ndev->dev.parent, dma_addr)) | |
c156633f | 1333 | goto drop; |
2f45d190 SS |
1334 | |
1335 | desc = &priv->tx_ring[q][entry]; | |
1336 | desc->ds_tagl = cpu_to_le16(len); | |
1337 | desc->dptr = cpu_to_le32(dma_addr); | |
1338 | ||
1339 | buffer = skb->data + len; | |
1340 | len = skb->len - len; | |
e2dbb33a KM |
1341 | dma_addr = dma_map_single(ndev->dev.parent, buffer, len, DMA_TO_DEVICE); |
1342 | if (dma_mapping_error(ndev->dev.parent, dma_addr)) | |
2f45d190 SS |
1343 | goto unmap; |
1344 | ||
1345 | desc++; | |
1346 | desc->ds_tagl = cpu_to_le16(len); | |
c156633f SS |
1347 | desc->dptr = cpu_to_le32(dma_addr); |
1348 | ||
1349 | /* TX timestamp required */ | |
1350 | if (q == RAVB_NC) { | |
1351 | ts_skb = kmalloc(sizeof(*ts_skb), GFP_ATOMIC); | |
1352 | if (!ts_skb) { | |
2f45d190 | 1353 | desc--; |
e2dbb33a | 1354 | dma_unmap_single(ndev->dev.parent, dma_addr, len, |
c156633f | 1355 | DMA_TO_DEVICE); |
2f45d190 | 1356 | goto unmap; |
c156633f SS |
1357 | } |
1358 | ts_skb->skb = skb; | |
1359 | ts_skb->tag = priv->ts_skb_tag++; | |
1360 | priv->ts_skb_tag &= 0x3ff; | |
1361 | list_add_tail(&ts_skb->list, &priv->ts_skb_list); | |
1362 | ||
1363 | /* TAG and timestamp required flag */ | |
1364 | skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; | |
1365 | skb_tx_timestamp(skb); | |
1366 | desc->tagh_tsr = (ts_skb->tag >> 4) | TX_TSR; | |
1367 | desc->ds_tagl |= le16_to_cpu(ts_skb->tag << 12); | |
1368 | } | |
1369 | ||
1370 | /* Descriptor type must be set after all the above writes */ | |
1371 | dma_wmb(); | |
2f45d190 SS |
1372 | desc->die_dt = DT_FEND; |
1373 | desc--; | |
1374 | desc->die_dt = DT_FSTART; | |
c156633f | 1375 | |
06613e38 | 1376 | ravb_write(ndev, ravb_read(ndev, TCCR) | (TCCR_TSRQ0 << q), TCCR); |
c156633f | 1377 | |
2f45d190 SS |
1378 | priv->cur_tx[q] += NUM_TX_DESC; |
1379 | if (priv->cur_tx[q] - priv->dirty_tx[q] > | |
1380 | (priv->num_tx_ring[q] - 1) * NUM_TX_DESC && !ravb_tx_free(ndev, q)) | |
c156633f SS |
1381 | netif_stop_subqueue(ndev, q); |
1382 | ||
1383 | exit: | |
1384 | mmiowb(); | |
1385 | spin_unlock_irqrestore(&priv->lock, flags); | |
1386 | return NETDEV_TX_OK; | |
1387 | ||
2f45d190 | 1388 | unmap: |
e2dbb33a | 1389 | dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), |
2f45d190 | 1390 | le16_to_cpu(desc->ds_tagl), DMA_TO_DEVICE); |
c156633f SS |
1391 | drop: |
1392 | dev_kfree_skb_any(skb); | |
2f45d190 | 1393 | priv->tx_skb[q][entry / NUM_TX_DESC] = NULL; |
c156633f SS |
1394 | goto exit; |
1395 | } | |
1396 | ||
1397 | static u16 ravb_select_queue(struct net_device *ndev, struct sk_buff *skb, | |
1398 | void *accel_priv, select_queue_fallback_t fallback) | |
1399 | { | |
1400 | /* If skb needs TX timestamp, it is handled in network control queue */ | |
1401 | return (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) ? RAVB_NC : | |
1402 | RAVB_BE; | |
1403 | ||
1404 | } | |
1405 | ||
1406 | static struct net_device_stats *ravb_get_stats(struct net_device *ndev) | |
1407 | { | |
1408 | struct ravb_private *priv = netdev_priv(ndev); | |
1409 | struct net_device_stats *nstats, *stats0, *stats1; | |
1410 | ||
1411 | nstats = &ndev->stats; | |
1412 | stats0 = &priv->stats[RAVB_BE]; | |
1413 | stats1 = &priv->stats[RAVB_NC]; | |
1414 | ||
1415 | nstats->tx_dropped += ravb_read(ndev, TROCR); | |
1416 | ravb_write(ndev, 0, TROCR); /* (write clear) */ | |
1417 | nstats->collisions += ravb_read(ndev, CDCR); | |
1418 | ravb_write(ndev, 0, CDCR); /* (write clear) */ | |
1419 | nstats->tx_carrier_errors += ravb_read(ndev, LCCR); | |
1420 | ravb_write(ndev, 0, LCCR); /* (write clear) */ | |
1421 | ||
1422 | nstats->tx_carrier_errors += ravb_read(ndev, CERCR); | |
1423 | ravb_write(ndev, 0, CERCR); /* (write clear) */ | |
1424 | nstats->tx_carrier_errors += ravb_read(ndev, CEECR); | |
1425 | ravb_write(ndev, 0, CEECR); /* (write clear) */ | |
1426 | ||
1427 | nstats->rx_packets = stats0->rx_packets + stats1->rx_packets; | |
1428 | nstats->tx_packets = stats0->tx_packets + stats1->tx_packets; | |
1429 | nstats->rx_bytes = stats0->rx_bytes + stats1->rx_bytes; | |
1430 | nstats->tx_bytes = stats0->tx_bytes + stats1->tx_bytes; | |
1431 | nstats->multicast = stats0->multicast + stats1->multicast; | |
1432 | nstats->rx_errors = stats0->rx_errors + stats1->rx_errors; | |
1433 | nstats->rx_crc_errors = stats0->rx_crc_errors + stats1->rx_crc_errors; | |
1434 | nstats->rx_frame_errors = | |
1435 | stats0->rx_frame_errors + stats1->rx_frame_errors; | |
1436 | nstats->rx_length_errors = | |
1437 | stats0->rx_length_errors + stats1->rx_length_errors; | |
1438 | nstats->rx_missed_errors = | |
1439 | stats0->rx_missed_errors + stats1->rx_missed_errors; | |
1440 | nstats->rx_over_errors = | |
1441 | stats0->rx_over_errors + stats1->rx_over_errors; | |
1442 | ||
1443 | return nstats; | |
1444 | } | |
1445 | ||
1446 | /* Update promiscuous bit */ | |
1447 | static void ravb_set_rx_mode(struct net_device *ndev) | |
1448 | { | |
1449 | struct ravb_private *priv = netdev_priv(ndev); | |
1450 | unsigned long flags; | |
1451 | u32 ecmr; | |
1452 | ||
1453 | spin_lock_irqsave(&priv->lock, flags); | |
1454 | ecmr = ravb_read(ndev, ECMR); | |
1455 | if (ndev->flags & IFF_PROMISC) | |
1456 | ecmr |= ECMR_PRM; | |
1457 | else | |
1458 | ecmr &= ~ECMR_PRM; | |
1459 | ravb_write(ndev, ecmr, ECMR); | |
1460 | mmiowb(); | |
1461 | spin_unlock_irqrestore(&priv->lock, flags); | |
1462 | } | |
1463 | ||
1464 | /* Device close function for Ethernet AVB */ | |
1465 | static int ravb_close(struct net_device *ndev) | |
1466 | { | |
1467 | struct ravb_private *priv = netdev_priv(ndev); | |
1468 | struct ravb_tstamp_skb *ts_skb, *ts_skb2; | |
1469 | ||
1470 | netif_tx_stop_all_queues(ndev); | |
1471 | ||
1472 | /* Disable interrupts by clearing the interrupt masks. */ | |
1473 | ravb_write(ndev, 0, RIC0); | |
1474 | ravb_write(ndev, 0, RIC1); | |
1475 | ravb_write(ndev, 0, RIC2); | |
1476 | ravb_write(ndev, 0, TIC); | |
1477 | ||
a0d2f206 SS |
1478 | /* Stop PTP Clock driver */ |
1479 | ravb_ptp_stop(ndev); | |
1480 | ||
c156633f SS |
1481 | /* Set the config mode to stop the AVB-DMAC's processes */ |
1482 | if (ravb_stop_dma(ndev) < 0) | |
1483 | netdev_err(ndev, | |
1484 | "device will be stopped after h/w processes are done.\n"); | |
1485 | ||
1486 | /* Clear the timestamp list */ | |
1487 | list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, list) { | |
1488 | list_del(&ts_skb->list); | |
1489 | kfree(ts_skb); | |
1490 | } | |
1491 | ||
1492 | /* PHY disconnect */ | |
1493 | if (priv->phydev) { | |
1494 | phy_stop(priv->phydev); | |
1495 | phy_disconnect(priv->phydev); | |
1496 | priv->phydev = NULL; | |
1497 | } | |
1498 | ||
1499 | free_irq(ndev->irq, ndev); | |
1500 | ||
1501 | napi_disable(&priv->napi[RAVB_NC]); | |
1502 | napi_disable(&priv->napi[RAVB_BE]); | |
1503 | ||
1504 | /* Free all the skb's in the RX queue and the DMA buffers. */ | |
1505 | ravb_ring_free(ndev, RAVB_BE); | |
1506 | ravb_ring_free(ndev, RAVB_NC); | |
1507 | ||
1508 | return 0; | |
1509 | } | |
1510 | ||
1511 | static int ravb_hwtstamp_get(struct net_device *ndev, struct ifreq *req) | |
1512 | { | |
1513 | struct ravb_private *priv = netdev_priv(ndev); | |
1514 | struct hwtstamp_config config; | |
1515 | ||
1516 | config.flags = 0; | |
1517 | config.tx_type = priv->tstamp_tx_ctrl ? HWTSTAMP_TX_ON : | |
1518 | HWTSTAMP_TX_OFF; | |
1519 | if (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE_V2_L2_EVENT) | |
1520 | config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT; | |
1521 | else if (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE_ALL) | |
1522 | config.rx_filter = HWTSTAMP_FILTER_ALL; | |
1523 | else | |
1524 | config.rx_filter = HWTSTAMP_FILTER_NONE; | |
1525 | ||
1526 | return copy_to_user(req->ifr_data, &config, sizeof(config)) ? | |
1527 | -EFAULT : 0; | |
1528 | } | |
1529 | ||
1530 | /* Control hardware time stamping */ | |
1531 | static int ravb_hwtstamp_set(struct net_device *ndev, struct ifreq *req) | |
1532 | { | |
1533 | struct ravb_private *priv = netdev_priv(ndev); | |
1534 | struct hwtstamp_config config; | |
1535 | u32 tstamp_rx_ctrl = RAVB_RXTSTAMP_ENABLED; | |
1536 | u32 tstamp_tx_ctrl; | |
1537 | ||
1538 | if (copy_from_user(&config, req->ifr_data, sizeof(config))) | |
1539 | return -EFAULT; | |
1540 | ||
1541 | /* Reserved for future extensions */ | |
1542 | if (config.flags) | |
1543 | return -EINVAL; | |
1544 | ||
1545 | switch (config.tx_type) { | |
1546 | case HWTSTAMP_TX_OFF: | |
1547 | tstamp_tx_ctrl = 0; | |
1548 | break; | |
1549 | case HWTSTAMP_TX_ON: | |
1550 | tstamp_tx_ctrl = RAVB_TXTSTAMP_ENABLED; | |
1551 | break; | |
1552 | default: | |
1553 | return -ERANGE; | |
1554 | } | |
1555 | ||
1556 | switch (config.rx_filter) { | |
1557 | case HWTSTAMP_FILTER_NONE: | |
1558 | tstamp_rx_ctrl = 0; | |
1559 | break; | |
1560 | case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: | |
1561 | tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_V2_L2_EVENT; | |
1562 | break; | |
1563 | default: | |
1564 | config.rx_filter = HWTSTAMP_FILTER_ALL; | |
1565 | tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_ALL; | |
1566 | } | |
1567 | ||
1568 | priv->tstamp_tx_ctrl = tstamp_tx_ctrl; | |
1569 | priv->tstamp_rx_ctrl = tstamp_rx_ctrl; | |
1570 | ||
1571 | return copy_to_user(req->ifr_data, &config, sizeof(config)) ? | |
1572 | -EFAULT : 0; | |
1573 | } | |
1574 | ||
1575 | /* ioctl to device function */ | |
1576 | static int ravb_do_ioctl(struct net_device *ndev, struct ifreq *req, int cmd) | |
1577 | { | |
1578 | struct ravb_private *priv = netdev_priv(ndev); | |
1579 | struct phy_device *phydev = priv->phydev; | |
1580 | ||
1581 | if (!netif_running(ndev)) | |
1582 | return -EINVAL; | |
1583 | ||
1584 | if (!phydev) | |
1585 | return -ENODEV; | |
1586 | ||
1587 | switch (cmd) { | |
1588 | case SIOCGHWTSTAMP: | |
1589 | return ravb_hwtstamp_get(ndev, req); | |
1590 | case SIOCSHWTSTAMP: | |
1591 | return ravb_hwtstamp_set(ndev, req); | |
1592 | } | |
1593 | ||
1594 | return phy_mii_ioctl(phydev, req, cmd); | |
1595 | } | |
1596 | ||
1597 | static const struct net_device_ops ravb_netdev_ops = { | |
1598 | .ndo_open = ravb_open, | |
1599 | .ndo_stop = ravb_close, | |
1600 | .ndo_start_xmit = ravb_start_xmit, | |
1601 | .ndo_select_queue = ravb_select_queue, | |
1602 | .ndo_get_stats = ravb_get_stats, | |
1603 | .ndo_set_rx_mode = ravb_set_rx_mode, | |
1604 | .ndo_tx_timeout = ravb_tx_timeout, | |
1605 | .ndo_do_ioctl = ravb_do_ioctl, | |
1606 | .ndo_validate_addr = eth_validate_addr, | |
1607 | .ndo_set_mac_address = eth_mac_addr, | |
1608 | .ndo_change_mtu = eth_change_mtu, | |
1609 | }; | |
1610 | ||
1611 | /* MDIO bus init function */ | |
1612 | static int ravb_mdio_init(struct ravb_private *priv) | |
1613 | { | |
1614 | struct platform_device *pdev = priv->pdev; | |
1615 | struct device *dev = &pdev->dev; | |
1616 | int error; | |
1617 | ||
1618 | /* Bitbang init */ | |
1619 | priv->mdiobb.ops = &bb_ops; | |
1620 | ||
1621 | /* MII controller setting */ | |
1622 | priv->mii_bus = alloc_mdio_bitbang(&priv->mdiobb); | |
1623 | if (!priv->mii_bus) | |
1624 | return -ENOMEM; | |
1625 | ||
1626 | /* Hook up MII support for ethtool */ | |
1627 | priv->mii_bus->name = "ravb_mii"; | |
1628 | priv->mii_bus->parent = dev; | |
1629 | snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", | |
1630 | pdev->name, pdev->id); | |
1631 | ||
1632 | /* Register MDIO bus */ | |
1633 | error = of_mdiobus_register(priv->mii_bus, dev->of_node); | |
1634 | if (error) | |
1635 | goto out_free_bus; | |
1636 | ||
1637 | return 0; | |
1638 | ||
1639 | out_free_bus: | |
1640 | free_mdio_bitbang(priv->mii_bus); | |
1641 | return error; | |
1642 | } | |
1643 | ||
1644 | /* MDIO bus release function */ | |
1645 | static int ravb_mdio_release(struct ravb_private *priv) | |
1646 | { | |
1647 | /* Unregister mdio bus */ | |
1648 | mdiobus_unregister(priv->mii_bus); | |
1649 | ||
1650 | /* Free bitbang info */ | |
1651 | free_mdio_bitbang(priv->mii_bus); | |
1652 | ||
1653 | return 0; | |
1654 | } | |
1655 | ||
22d4df8f KM |
1656 | static const struct of_device_id ravb_match_table[] = { |
1657 | { .compatible = "renesas,etheravb-r8a7790", .data = (void *)RCAR_GEN2 }, | |
1658 | { .compatible = "renesas,etheravb-r8a7794", .data = (void *)RCAR_GEN2 }, | |
1659 | { .compatible = "renesas,etheravb-r8a7795", .data = (void *)RCAR_GEN3 }, | |
1660 | { } | |
1661 | }; | |
1662 | MODULE_DEVICE_TABLE(of, ravb_match_table); | |
1663 | ||
c156633f SS |
1664 | static int ravb_probe(struct platform_device *pdev) |
1665 | { | |
1666 | struct device_node *np = pdev->dev.of_node; | |
22d4df8f | 1667 | const struct of_device_id *match; |
c156633f | 1668 | struct ravb_private *priv; |
22d4df8f | 1669 | enum ravb_chip_id chip_id; |
c156633f SS |
1670 | struct net_device *ndev; |
1671 | int error, irq, q; | |
1672 | struct resource *res; | |
1673 | ||
1674 | if (!np) { | |
1675 | dev_err(&pdev->dev, | |
1676 | "this driver is required to be instantiated from device tree\n"); | |
1677 | return -EINVAL; | |
1678 | } | |
1679 | ||
1680 | /* Get base address */ | |
1681 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1682 | if (!res) { | |
1683 | dev_err(&pdev->dev, "invalid resource\n"); | |
1684 | return -EINVAL; | |
1685 | } | |
1686 | ||
1687 | ndev = alloc_etherdev_mqs(sizeof(struct ravb_private), | |
1688 | NUM_TX_QUEUE, NUM_RX_QUEUE); | |
1689 | if (!ndev) | |
1690 | return -ENOMEM; | |
1691 | ||
1692 | pm_runtime_enable(&pdev->dev); | |
1693 | pm_runtime_get_sync(&pdev->dev); | |
1694 | ||
1695 | /* The Ether-specific entries in the device structure. */ | |
1696 | ndev->base_addr = res->start; | |
1697 | ndev->dma = -1; | |
22d4df8f KM |
1698 | |
1699 | match = of_match_device(of_match_ptr(ravb_match_table), &pdev->dev); | |
1700 | chip_id = (enum ravb_chip_id)match->data; | |
1701 | ||
1702 | if (chip_id == RCAR_GEN3) | |
1703 | irq = platform_get_irq_byname(pdev, "ch22"); | |
1704 | else | |
1705 | irq = platform_get_irq(pdev, 0); | |
c156633f | 1706 | if (irq < 0) { |
f375339e | 1707 | error = irq; |
c156633f SS |
1708 | goto out_release; |
1709 | } | |
1710 | ndev->irq = irq; | |
1711 | ||
1712 | SET_NETDEV_DEV(ndev, &pdev->dev); | |
1713 | ||
1714 | priv = netdev_priv(ndev); | |
1715 | priv->ndev = ndev; | |
1716 | priv->pdev = pdev; | |
1717 | priv->num_tx_ring[RAVB_BE] = BE_TX_RING_SIZE; | |
1718 | priv->num_rx_ring[RAVB_BE] = BE_RX_RING_SIZE; | |
1719 | priv->num_tx_ring[RAVB_NC] = NC_TX_RING_SIZE; | |
1720 | priv->num_rx_ring[RAVB_NC] = NC_RX_RING_SIZE; | |
1721 | priv->addr = devm_ioremap_resource(&pdev->dev, res); | |
1722 | if (IS_ERR(priv->addr)) { | |
1723 | error = PTR_ERR(priv->addr); | |
1724 | goto out_release; | |
1725 | } | |
1726 | ||
1727 | spin_lock_init(&priv->lock); | |
1728 | INIT_WORK(&priv->work, ravb_tx_timeout_work); | |
1729 | ||
1730 | priv->phy_interface = of_get_phy_mode(np); | |
1731 | ||
1732 | priv->no_avb_link = of_property_read_bool(np, "renesas,no-ether-link"); | |
1733 | priv->avb_link_active_low = | |
1734 | of_property_read_bool(np, "renesas,ether-link-active-low"); | |
1735 | ||
22d4df8f KM |
1736 | if (chip_id == RCAR_GEN3) { |
1737 | irq = platform_get_irq_byname(pdev, "ch24"); | |
1738 | if (irq < 0) { | |
1739 | error = irq; | |
1740 | goto out_release; | |
1741 | } | |
1742 | priv->emac_irq = irq; | |
1743 | } | |
1744 | ||
1745 | priv->chip_id = chip_id; | |
1746 | ||
c156633f SS |
1747 | /* Set function */ |
1748 | ndev->netdev_ops = &ravb_netdev_ops; | |
1749 | ndev->ethtool_ops = &ravb_ethtool_ops; | |
1750 | ||
1751 | /* Set AVB config mode */ | |
1752 | ravb_write(ndev, (ravb_read(ndev, CCC) & ~CCC_OPC) | CCC_OPC_CONFIG, | |
1753 | CCC); | |
1754 | ||
1755 | /* Set CSEL value */ | |
1756 | ravb_write(ndev, (ravb_read(ndev, CCC) & ~CCC_CSEL) | CCC_CSEL_HPB, | |
1757 | CCC); | |
1758 | ||
1759 | /* Set GTI value */ | |
1760 | ravb_write(ndev, ((1000 << 20) / 130) & GTI_TIV, GTI); | |
1761 | ||
1762 | /* Request GTI loading */ | |
1763 | ravb_write(ndev, ravb_read(ndev, GCCR) | GCCR_LTI, GCCR); | |
1764 | ||
1765 | /* Allocate descriptor base address table */ | |
1766 | priv->desc_bat_size = sizeof(struct ravb_desc) * DBAT_ENTRY_NUM; | |
e2dbb33a | 1767 | priv->desc_bat = dma_alloc_coherent(ndev->dev.parent, priv->desc_bat_size, |
c156633f SS |
1768 | &priv->desc_bat_dma, GFP_KERNEL); |
1769 | if (!priv->desc_bat) { | |
c4511132 | 1770 | dev_err(&pdev->dev, |
c156633f SS |
1771 | "Cannot allocate desc base address table (size %d bytes)\n", |
1772 | priv->desc_bat_size); | |
1773 | error = -ENOMEM; | |
1774 | goto out_release; | |
1775 | } | |
1776 | for (q = RAVB_BE; q < DBAT_ENTRY_NUM; q++) | |
1777 | priv->desc_bat[q].die_dt = DT_EOS; | |
1778 | ravb_write(ndev, priv->desc_bat_dma, DBAT); | |
1779 | ||
1780 | /* Initialise HW timestamp list */ | |
1781 | INIT_LIST_HEAD(&priv->ts_skb_list); | |
1782 | ||
1783 | /* Debug message level */ | |
1784 | priv->msg_enable = RAVB_DEF_MSG_ENABLE; | |
1785 | ||
1786 | /* Read and set MAC address */ | |
1787 | ravb_read_mac_address(ndev, of_get_mac_address(np)); | |
1788 | if (!is_valid_ether_addr(ndev->dev_addr)) { | |
1789 | dev_warn(&pdev->dev, | |
1790 | "no valid MAC address supplied, using a random one\n"); | |
1791 | eth_hw_addr_random(ndev); | |
1792 | } | |
1793 | ||
1794 | /* MDIO bus init */ | |
1795 | error = ravb_mdio_init(priv); | |
1796 | if (error) { | |
c4511132 | 1797 | dev_err(&pdev->dev, "failed to initialize MDIO\n"); |
c156633f SS |
1798 | goto out_dma_free; |
1799 | } | |
1800 | ||
1801 | netif_napi_add(ndev, &priv->napi[RAVB_BE], ravb_poll, 64); | |
1802 | netif_napi_add(ndev, &priv->napi[RAVB_NC], ravb_poll, 64); | |
1803 | ||
1804 | /* Network device register */ | |
1805 | error = register_netdev(ndev); | |
1806 | if (error) | |
1807 | goto out_napi_del; | |
1808 | ||
1809 | /* Print device information */ | |
1810 | netdev_info(ndev, "Base address at %#x, %pM, IRQ %d.\n", | |
1811 | (u32)ndev->base_addr, ndev->dev_addr, ndev->irq); | |
1812 | ||
1813 | platform_set_drvdata(pdev, ndev); | |
1814 | ||
1815 | return 0; | |
1816 | ||
1817 | out_napi_del: | |
1818 | netif_napi_del(&priv->napi[RAVB_NC]); | |
1819 | netif_napi_del(&priv->napi[RAVB_BE]); | |
1820 | ravb_mdio_release(priv); | |
1821 | out_dma_free: | |
e2dbb33a | 1822 | dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat, |
c156633f SS |
1823 | priv->desc_bat_dma); |
1824 | out_release: | |
1825 | if (ndev) | |
1826 | free_netdev(ndev); | |
1827 | ||
1828 | pm_runtime_put(&pdev->dev); | |
1829 | pm_runtime_disable(&pdev->dev); | |
1830 | return error; | |
1831 | } | |
1832 | ||
1833 | static int ravb_remove(struct platform_device *pdev) | |
1834 | { | |
1835 | struct net_device *ndev = platform_get_drvdata(pdev); | |
1836 | struct ravb_private *priv = netdev_priv(ndev); | |
1837 | ||
e2dbb33a | 1838 | dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat, |
c156633f SS |
1839 | priv->desc_bat_dma); |
1840 | /* Set reset mode */ | |
1841 | ravb_write(ndev, CCC_OPC_RESET, CCC); | |
1842 | pm_runtime_put_sync(&pdev->dev); | |
1843 | unregister_netdev(ndev); | |
1844 | netif_napi_del(&priv->napi[RAVB_NC]); | |
1845 | netif_napi_del(&priv->napi[RAVB_BE]); | |
1846 | ravb_mdio_release(priv); | |
1847 | pm_runtime_disable(&pdev->dev); | |
1848 | free_netdev(ndev); | |
1849 | platform_set_drvdata(pdev, NULL); | |
1850 | ||
1851 | return 0; | |
1852 | } | |
1853 | ||
1854 | #ifdef CONFIG_PM | |
1855 | static int ravb_runtime_nop(struct device *dev) | |
1856 | { | |
1857 | /* Runtime PM callback shared between ->runtime_suspend() | |
1858 | * and ->runtime_resume(). Simply returns success. | |
1859 | * | |
1860 | * This driver re-initializes all registers after | |
1861 | * pm_runtime_get_sync() anyway so there is no need | |
1862 | * to save and restore registers here. | |
1863 | */ | |
1864 | return 0; | |
1865 | } | |
1866 | ||
1867 | static const struct dev_pm_ops ravb_dev_pm_ops = { | |
1868 | .runtime_suspend = ravb_runtime_nop, | |
1869 | .runtime_resume = ravb_runtime_nop, | |
1870 | }; | |
1871 | ||
1872 | #define RAVB_PM_OPS (&ravb_dev_pm_ops) | |
1873 | #else | |
1874 | #define RAVB_PM_OPS NULL | |
1875 | #endif | |
1876 | ||
c156633f SS |
1877 | static struct platform_driver ravb_driver = { |
1878 | .probe = ravb_probe, | |
1879 | .remove = ravb_remove, | |
1880 | .driver = { | |
1881 | .name = "ravb", | |
1882 | .pm = RAVB_PM_OPS, | |
1883 | .of_match_table = ravb_match_table, | |
1884 | }, | |
1885 | }; | |
1886 | ||
1887 | module_platform_driver(ravb_driver); | |
1888 | ||
1889 | MODULE_AUTHOR("Mitsuhiro Kimura, Masaru Nagai"); | |
1890 | MODULE_DESCRIPTION("Renesas Ethernet AVB driver"); | |
1891 | MODULE_LICENSE("GPL v2"); |