]> git.proxmox.com Git - mirror_ubuntu-hirsute-kernel.git/blame - drivers/net/ethernet/renesas/ravb_main.c
projects / mirror_ubuntu-hirsute-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
net, cgroup: cgroup_sk_updat_lock was missing initializer
[mirror_ubuntu-hirsute-kernel.git] / drivers / net / ethernet / renesas / ravb_main.c
CommitLineData
c156633f
SS		 1/* Renesas Ethernet AVB device driver
2 *
3 * Copyright (C) 2014-2015 Renesas Electronics Corporation
4 * Copyright (C) 2015 Renesas Solutions Corp.
5 * Copyright (C) 2015 Cogent Embedded, Inc. <source@cogentembedded.com>
6 *
7 * Based on the SuperH Ethernet driver
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms and conditions of the GNU General Public License version 2,
11 * as published by the Free Software Foundation.
12 */
13
14#include <linux/cache.h>
15#include <linux/clk.h>
16#include <linux/delay.h>
17#include <linux/dma-mapping.h>
18#include <linux/err.h>
19#include <linux/etherdevice.h>
20#include <linux/ethtool.h>
21#include <linux/if_vlan.h>
22#include <linux/kernel.h>
23#include <linux/list.h>
24#include <linux/module.h>
25#include <linux/net_tstamp.h>
26#include <linux/of.h>
27#include <linux/of_device.h>
28#include <linux/of_irq.h>
29#include <linux/of_mdio.h>
30#include <linux/of_net.h>
c156633f
SS		 31#include <linux/pm_runtime.h>
32#include <linux/slab.h>
33#include <linux/spinlock.h>
34
b3d39a88
SH		 35#include <asm/div64.h>
36
c156633f
SS		 37#include "ravb.h"
38
39#define RAVB_DEF_MSG_ENABLE \
40 (NETIF_MSG_LINK | \
41 NETIF_MSG_TIMER | \
42 NETIF_MSG_RX_ERR | \
43 NETIF_MSG_TX_ERR)
44
a0d2f206 45int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value)
c156633f
SS		 46{
47 int i;
48
49 for (i = 0; i < 10000; i++) {
50 if ((ravb_read(ndev, reg) & mask) == value)
51 return 0;
52 udelay(10);
53 }
54 return -ETIMEDOUT;
55}
56
57static int ravb_config(struct net_device *ndev)
58{
59 int error;
60
61 /* Set config mode */
62 ravb_write(ndev, (ravb_read(ndev, CCC) & ~CCC_OPC) | CCC_OPC_CONFIG,
63 CCC);
64 /* Check if the operating mode is changed to the config mode */
65 error = ravb_wait(ndev, CSR, CSR_OPS, CSR_OPS_CONFIG);
66 if (error)
67 netdev_err(ndev, "failed to switch device to config mode\n");
68
69 return error;
70}
71
72static void ravb_set_duplex(struct net_device *ndev)
73{
74 struct ravb_private *priv = netdev_priv(ndev);
75 u32 ecmr = ravb_read(ndev, ECMR);
76
77 if (priv->duplex) /* Full */
78 ecmr |= ECMR_DM;
79 else /* Half */
80 ecmr &= ~ECMR_DM;
81 ravb_write(ndev, ecmr, ECMR);
82}
83
84static void ravb_set_rate(struct net_device *ndev)
85{
86 struct ravb_private *priv = netdev_priv(ndev);
87
88 switch (priv->speed) {
89 case 100: /* 100BASE */
90 ravb_write(ndev, GECMR_SPEED_100, GECMR);
91 break;
92 case 1000: /* 1000BASE */
93 ravb_write(ndev, GECMR_SPEED_1000, GECMR);
94 break;
95 default:
96 break;
97 }
98}
99
100static void ravb_set_buffer_align(struct sk_buff *skb)
101{
102 u32 reserve = (unsigned long)skb->data & (RAVB_ALIGN - 1);
103
104 if (reserve)
105 skb_reserve(skb, RAVB_ALIGN - reserve);
106}
107
108/* Get MAC address from the MAC address registers
109 *
110 * Ethernet AVB device doesn't have ROM for MAC address.
111 * This function gets the MAC address that was used by a bootloader.
112 */
113static void ravb_read_mac_address(struct net_device *ndev, const u8 *mac)
114{
115 if (mac) {
116 ether_addr_copy(ndev->dev_addr, mac);
117 } else {
d9660638
SS		 118 u32 mahr = ravb_read(ndev, MAHR);
119 u32 malr = ravb_read(ndev, MALR);
120
121 ndev->dev_addr[0] = (mahr >> 24) & 0xFF;
122 ndev->dev_addr[1] = (mahr >> 16) & 0xFF;
123 ndev->dev_addr[2] = (mahr >> 8) & 0xFF;
124 ndev->dev_addr[3] = (mahr >> 0) & 0xFF;
125 ndev->dev_addr[4] = (malr >> 8) & 0xFF;
126 ndev->dev_addr[5] = (malr >> 0) & 0xFF;
c156633f
SS		 127 }
128}
129
130static void ravb_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set)
131{
132 struct ravb_private *priv = container_of(ctrl, struct ravb_private,
133 mdiobb);
134 u32 pir = ravb_read(priv->ndev, PIR);
135
136 if (set)
137 pir |= mask;
138 else
139 pir &= ~mask;
140 ravb_write(priv->ndev, pir, PIR);
141}
142
143/* MDC pin control */
144static void ravb_set_mdc(struct mdiobb_ctrl *ctrl, int level)
145{
146 ravb_mdio_ctrl(ctrl, PIR_MDC, level);
147}
148
149/* Data I/O pin control */
150static void ravb_set_mdio_dir(struct mdiobb_ctrl *ctrl, int output)
151{
152 ravb_mdio_ctrl(ctrl, PIR_MMD, output);
153}
154
155/* Set data bit */
156static void ravb_set_mdio_data(struct mdiobb_ctrl *ctrl, int value)
157{
158 ravb_mdio_ctrl(ctrl, PIR_MDO, value);
159}
160
161/* Get data bit */
162static int ravb_get_mdio_data(struct mdiobb_ctrl *ctrl)
163{
164 struct ravb_private *priv = container_of(ctrl, struct ravb_private,
165 mdiobb);
166
167 return (ravb_read(priv->ndev, PIR) & PIR_MDI) != 0;
168}
169
170/* MDIO bus control struct */
171static struct mdiobb_ops bb_ops = {
172 .owner = THIS_MODULE,
173 .set_mdc = ravb_set_mdc,
174 .set_mdio_dir = ravb_set_mdio_dir,
175 .set_mdio_data = ravb_set_mdio_data,
176 .get_mdio_data = ravb_get_mdio_data,
177};
178
179/* Free skb's and DMA buffers for Ethernet AVB */
180static void ravb_ring_free(struct net_device *ndev, int q)
181{
182 struct ravb_private *priv = netdev_priv(ndev);
183 int ring_size;
184 int i;
185
186 /* Free RX skb ringbuffer */
187 if (priv->rx_skb[q]) {
188 for (i = 0; i < priv->num_rx_ring[q]; i++)
189 dev_kfree_skb(priv->rx_skb[q][i]);
190 }
191 kfree(priv->rx_skb[q]);
192 priv->rx_skb[q] = NULL;
193
194 /* Free TX skb ringbuffer */
195 if (priv->tx_skb[q]) {
196 for (i = 0; i < priv->num_tx_ring[q]; i++)
197 dev_kfree_skb(priv->tx_skb[q][i]);
198 }
199 kfree(priv->tx_skb[q]);
200 priv->tx_skb[q] = NULL;
201
202 /* Free aligned TX buffers */
2f45d190
SS		 203 kfree(priv->tx_align[q]);
204 priv->tx_align[q] = NULL;
c156633f
SS		 205
206 if (priv->rx_ring[q]) {
207 ring_size = sizeof(struct ravb_ex_rx_desc) *
208 (priv->num_rx_ring[q] + 1);
e2dbb33a 209 dma_free_coherent(ndev->dev.parent, ring_size, priv->rx_ring[q],
c156633f
SS		 210 priv->rx_desc_dma[q]);
211 priv->rx_ring[q] = NULL;
212 }
213
214 if (priv->tx_ring[q]) {
215 ring_size = sizeof(struct ravb_tx_desc) *
2f45d190 216 (priv->num_tx_ring[q] * NUM_TX_DESC + 1);
e2dbb33a 217 dma_free_coherent(ndev->dev.parent, ring_size, priv->tx_ring[q],
c156633f
SS		 218 priv->tx_desc_dma[q]);
219 priv->tx_ring[q] = NULL;
220 }
221}
222
223/* Format skb and descriptor buffer for Ethernet AVB */
224static void ravb_ring_format(struct net_device *ndev, int q)
225{
226 struct ravb_private *priv = netdev_priv(ndev);
aad0d51e
SS		 227 struct ravb_ex_rx_desc *rx_desc;
228 struct ravb_tx_desc *tx_desc;
229 struct ravb_desc *desc;
c156633f 230 int rx_ring_size = sizeof(*rx_desc) * priv->num_rx_ring[q];
2f45d190
SS		 231 int tx_ring_size = sizeof(*tx_desc) * priv->num_tx_ring[q] *
232 NUM_TX_DESC;
c156633f 233 dma_addr_t dma_addr;
c156633f
SS		 234 int i;
235
236 priv->cur_rx[q] = 0;
237 priv->cur_tx[q] = 0;
238 priv->dirty_rx[q] = 0;
239 priv->dirty_tx[q] = 0;
240
241 memset(priv->rx_ring[q], 0, rx_ring_size);
242 /* Build RX ring buffer */
243 for (i = 0; i < priv->num_rx_ring[q]; i++) {
c156633f
SS		 244 /* RX descriptor */
245 rx_desc = &priv->rx_ring[q][i];
246 /* The size of the buffer should be on 16-byte boundary. */
247 rx_desc->ds_cc = cpu_to_le16(ALIGN(PKT_BUF_SZ, 16));
e2dbb33a 248 dma_addr = dma_map_single(ndev->dev.parent, priv->rx_skb[q][i]->data,
c156633f
SS		 249 ALIGN(PKT_BUF_SZ, 16),
250 DMA_FROM_DEVICE);
d8b48911
SS		 251 /* We just set the data size to 0 for a failed mapping which
252 * should prevent DMA from happening...
253 */
e2dbb33a 254 if (dma_mapping_error(ndev->dev.parent, dma_addr))
d8b48911 255 rx_desc->ds_cc = cpu_to_le16(0);
c156633f
SS		 256 rx_desc->dptr = cpu_to_le32(dma_addr);
257 rx_desc->die_dt = DT_FEMPTY;
258 }
259 rx_desc = &priv->rx_ring[q][i];
260 rx_desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]);
261 rx_desc->die_dt = DT_LINKFIX; /* type */
c156633f
SS		 262
263 memset(priv->tx_ring[q], 0, tx_ring_size);
264 /* Build TX ring buffer */
2f45d190
SS		 265 for (i = 0, tx_desc = priv->tx_ring[q]; i < priv->num_tx_ring[q];
266 i++, tx_desc++) {
267 tx_desc->die_dt = DT_EEMPTY;
268 tx_desc++;
c156633f
SS		 269 tx_desc->die_dt = DT_EEMPTY;
270 }
c156633f
SS		 271 tx_desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]);
272 tx_desc->die_dt = DT_LINKFIX; /* type */
273
274 /* RX descriptor base address for best effort */
275 desc = &priv->desc_bat[RX_QUEUE_OFFSET + q];
276 desc->die_dt = DT_LINKFIX; /* type */
277 desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]);
278
279 /* TX descriptor base address for best effort */
280 desc = &priv->desc_bat[q];
281 desc->die_dt = DT_LINKFIX; /* type */
282 desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]);
283}
284
285/* Init skb and descriptor buffer for Ethernet AVB */
286static int ravb_ring_init(struct net_device *ndev, int q)
287{
288 struct ravb_private *priv = netdev_priv(ndev);
d8b48911 289 struct sk_buff *skb;
c156633f 290 int ring_size;
d8b48911 291 int i;
c156633f
SS		 292
293 /* Allocate RX and TX skb rings */
294 priv->rx_skb[q] = kcalloc(priv->num_rx_ring[q],
295 sizeof(*priv->rx_skb[q]), GFP_KERNEL);
296 priv->tx_skb[q] = kcalloc(priv->num_tx_ring[q],
297 sizeof(*priv->tx_skb[q]), GFP_KERNEL);
298 if (!priv->rx_skb[q] || !priv->tx_skb[q])
299 goto error;
300
d8b48911
SS		 301 for (i = 0; i < priv->num_rx_ring[q]; i++) {
302 skb = netdev_alloc_skb(ndev, PKT_BUF_SZ + RAVB_ALIGN - 1);
303 if (!skb)
304 goto error;
305 ravb_set_buffer_align(skb);
306 priv->rx_skb[q][i] = skb;
307 }
308
c156633f 309 /* Allocate rings for the aligned buffers */
2f45d190
SS		 310 priv->tx_align[q] = kmalloc(DPTR_ALIGN * priv->num_tx_ring[q] +
311 DPTR_ALIGN - 1, GFP_KERNEL);
312 if (!priv->tx_align[q])
c156633f
SS		 313 goto error;
314
315 /* Allocate all RX descriptors. */
316 ring_size = sizeof(struct ravb_ex_rx_desc) * (priv->num_rx_ring[q] + 1);
e2dbb33a 317 priv->rx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size,
c156633f
SS		 318 &priv->rx_desc_dma[q],
319 GFP_KERNEL);
320 if (!priv->rx_ring[q])
321 goto error;
322
323 priv->dirty_rx[q] = 0;
324
325 /* Allocate all TX descriptors. */
2f45d190
SS		 326 ring_size = sizeof(struct ravb_tx_desc) *
327 (priv->num_tx_ring[q] * NUM_TX_DESC + 1);
e2dbb33a 328 priv->tx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size,
c156633f
SS		 329 &priv->tx_desc_dma[q],
330 GFP_KERNEL);
331 if (!priv->tx_ring[q])
332 goto error;
333
334 return 0;
335
336error:
337 ravb_ring_free(ndev, q);
338
339 return -ENOMEM;
340}
341
342/* E-MAC init function */
343static void ravb_emac_init(struct net_device *ndev)
344{
345 struct ravb_private *priv = netdev_priv(ndev);
346 u32 ecmr;
347
348 /* Receive frame limit set register */
349 ravb_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, RFLR);
350
351 /* PAUSE prohibition */
352 ecmr = ravb_read(ndev, ECMR);
353 ecmr &= ECMR_DM;
354 ecmr |= ECMR_ZPF | (priv->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE;
355 ravb_write(ndev, ecmr, ECMR);
356
357 ravb_set_rate(ndev);
358
359 /* Set MAC address */
360 ravb_write(ndev,
361 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
362 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
363 ravb_write(ndev,
364 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
365
366 ravb_write(ndev, 1, MPR);
367
368 /* E-MAC status register clear */
369 ravb_write(ndev, ECSR_ICD | ECSR_MPD, ECSR);
370
371 /* E-MAC interrupt enable register */
372 ravb_write(ndev, ECSIPR_ICDIP | ECSIPR_MPDIP | ECSIPR_LCHNGIP, ECSIPR);
373}
374
375/* Device init function for Ethernet AVB */
376static int ravb_dmac_init(struct net_device *ndev)
377{
378 int error;
379
380 /* Set CONFIG mode */
381 error = ravb_config(ndev);
382 if (error)
383 return error;
384
385 error = ravb_ring_init(ndev, RAVB_BE);
386 if (error)
387 return error;
388 error = ravb_ring_init(ndev, RAVB_NC);
389 if (error) {
390 ravb_ring_free(ndev, RAVB_BE);
391 return error;
392 }
393
394 /* Descriptor format */
395 ravb_ring_format(ndev, RAVB_BE);
396 ravb_ring_format(ndev, RAVB_NC);
397
398#if defined(__LITTLE_ENDIAN)
399 ravb_write(ndev, ravb_read(ndev, CCC) & ~CCC_BOC, CCC);
400#else
401 ravb_write(ndev, ravb_read(ndev, CCC) | CCC_BOC, CCC);
402#endif
403
404 /* Set AVB RX */
405 ravb_write(ndev, RCR_EFFS | RCR_ENCF | RCR_ETS0 | 0x18000000, RCR);
406
407 /* Set FIFO size */
408 ravb_write(ndev, TGC_TQP_AVBMODE1 | 0x00222200, TGC);
409
410 /* Timestamp enable */
411 ravb_write(ndev, TCCR_TFEN, TCCR);
412
413 /* Interrupt enable: */
414 /* Frame receive */
415 ravb_write(ndev, RIC0_FRE0 | RIC0_FRE1, RIC0);
c156633f
SS		 416 /* Receive FIFO full error, descriptor empty */
417 ravb_write(ndev, RIC2_QFE0 | RIC2_QFE1 | RIC2_RFFE, RIC2);
418 /* Frame transmitted, timestamp FIFO updated */
419 ravb_write(ndev, TIC_FTE0 | TIC_FTE1 | TIC_TFUE, TIC);
420
421 /* Setting the control will start the AVB-DMAC process. */
422 ravb_write(ndev, (ravb_read(ndev, CCC) & ~CCC_OPC) | CCC_OPC_OPERATION,
423 CCC);
424
425 return 0;
426}
427
428/* Free TX skb function for AVB-IP */
429static int ravb_tx_free(struct net_device *ndev, int q)
430{
431 struct ravb_private *priv = netdev_priv(ndev);
432 struct net_device_stats *stats = &priv->stats[q];
433 struct ravb_tx_desc *desc;
434 int free_num = 0;
aad0d51e 435 int entry;
c156633f
SS		 436 u32 size;
437
438 for (; priv->cur_tx[q] - priv->dirty_tx[q] > 0; priv->dirty_tx[q]++) {
2f45d190
SS		 439 entry = priv->dirty_tx[q] % (priv->num_tx_ring[q] *
440 NUM_TX_DESC);
c156633f
SS		 441 desc = &priv->tx_ring[q][entry];
442 if (desc->die_dt != DT_FEMPTY)
443 break;
444 /* Descriptor type must be checked before all other reads */
445 dma_rmb();
446 size = le16_to_cpu(desc->ds_tagl) & TX_DS;
447 /* Free the original skb. */
2f45d190 448 if (priv->tx_skb[q][entry / NUM_TX_DESC]) {
e2dbb33a 449 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
c156633f 450 size, DMA_TO_DEVICE);
2f45d190
SS		 451 /* Last packet descriptor? */
452 if (entry % NUM_TX_DESC == NUM_TX_DESC - 1) {
453 entry /= NUM_TX_DESC;
454 dev_kfree_skb_any(priv->tx_skb[q][entry]);
455 priv->tx_skb[q][entry] = NULL;
456 stats->tx_packets++;
457 }
c156633f
SS		 458 free_num++;
459 }
c156633f
SS		 460 stats->tx_bytes += size;
461 desc->die_dt = DT_EEMPTY;
462 }
463 return free_num;
464}
465
466static void ravb_get_tx_tstamp(struct net_device *ndev)
467{
468 struct ravb_private *priv = netdev_priv(ndev);
469 struct ravb_tstamp_skb *ts_skb, *ts_skb2;
470 struct skb_shared_hwtstamps shhwtstamps;
471 struct sk_buff *skb;
472 struct timespec64 ts;
473 u16 tag, tfa_tag;
474 int count;
475 u32 tfa2;
476
477 count = (ravb_read(ndev, TSR) & TSR_TFFL) >> 8;
478 while (count--) {
479 tfa2 = ravb_read(ndev, TFA2);
480 tfa_tag = (tfa2 & TFA2_TST) >> 16;
481 ts.tv_nsec = (u64)ravb_read(ndev, TFA0);
482 ts.tv_sec = ((u64)(tfa2 & TFA2_TSV) << 32) |
483 ravb_read(ndev, TFA1);
484 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
485 shhwtstamps.hwtstamp = timespec64_to_ktime(ts);
486 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list,
487 list) {
488 skb = ts_skb->skb;
489 tag = ts_skb->tag;
490 list_del(&ts_skb->list);
491 kfree(ts_skb);
492 if (tag == tfa_tag) {
493 skb_tstamp_tx(skb, &shhwtstamps);
494 break;
495 }
496 }
497 ravb_write(ndev, ravb_read(ndev, TCCR) | TCCR_TFR, TCCR);
498 }
499}
500
501/* Packet receive function for Ethernet AVB */
502static bool ravb_rx(struct net_device *ndev, int *quota, int q)
503{
504 struct ravb_private *priv = netdev_priv(ndev);
505 int entry = priv->cur_rx[q] % priv->num_rx_ring[q];
506 int boguscnt = (priv->dirty_rx[q] + priv->num_rx_ring[q]) -
507 priv->cur_rx[q];
508 struct net_device_stats *stats = &priv->stats[q];
509 struct ravb_ex_rx_desc *desc;
510 struct sk_buff *skb;
511 dma_addr_t dma_addr;
512 struct timespec64 ts;
c156633f 513 u8 desc_status;
aad0d51e 514 u16 pkt_len;
c156633f
SS		 515 int limit;
516
517 boguscnt = min(boguscnt, *quota);
518 limit = boguscnt;
519 desc = &priv->rx_ring[q][entry];
520 while (desc->die_dt != DT_FEMPTY) {
521 /* Descriptor type must be checked before all other reads */
522 dma_rmb();
523 desc_status = desc->msc;
524 pkt_len = le16_to_cpu(desc->ds_cc) & RX_DS;
525
526 if (--boguscnt < 0)
527 break;
528
d8b48911
SS		 529 /* We use 0-byte descriptors to mark the DMA mapping errors */
530 if (!pkt_len)
531 continue;
532
c156633f
SS		 533 if (desc_status & MSC_MC)
534 stats->multicast++;
535
536 if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF |
537 MSC_CEEF)) {
538 stats->rx_errors++;
539 if (desc_status & MSC_CRC)
540 stats->rx_crc_errors++;
541 if (desc_status & MSC_RFE)
542 stats->rx_frame_errors++;
543 if (desc_status & (MSC_RTLF | MSC_RTSF))
544 stats->rx_length_errors++;
545 if (desc_status & MSC_CEEF)
546 stats->rx_missed_errors++;
547 } else {
548 u32 get_ts = priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE;
549
550 skb = priv->rx_skb[q][entry];
551 priv->rx_skb[q][entry] = NULL;
e2dbb33a 552 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
e2370f07
SS		 553 ALIGN(PKT_BUF_SZ, 16),
554 DMA_FROM_DEVICE);
c156633f
SS		 555 get_ts &= (q == RAVB_NC) ?
556 RAVB_RXTSTAMP_TYPE_V2_L2_EVENT :
557 ~RAVB_RXTSTAMP_TYPE_V2_L2_EVENT;
558 if (get_ts) {
559 struct skb_shared_hwtstamps *shhwtstamps;
560
561 shhwtstamps = skb_hwtstamps(skb);
562 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
563 ts.tv_sec = ((u64) le16_to_cpu(desc->ts_sh) <<
564 32) | le32_to_cpu(desc->ts_sl);
565 ts.tv_nsec = le32_to_cpu(desc->ts_n);
566 shhwtstamps->hwtstamp = timespec64_to_ktime(ts);
567 }
568 skb_put(skb, pkt_len);
569 skb->protocol = eth_type_trans(skb, ndev);
570 napi_gro_receive(&priv->napi[q], skb);
571 stats->rx_packets++;
572 stats->rx_bytes += pkt_len;
573 }
574
575 entry = (++priv->cur_rx[q]) % priv->num_rx_ring[q];
576 desc = &priv->rx_ring[q][entry];
577 }
578
579 /* Refill the RX ring buffers. */
580 for (; priv->cur_rx[q] - priv->dirty_rx[q] > 0; priv->dirty_rx[q]++) {
581 entry = priv->dirty_rx[q] % priv->num_rx_ring[q];
582 desc = &priv->rx_ring[q][entry];
583 /* The size of the buffer should be on 16-byte boundary. */
584 desc->ds_cc = cpu_to_le16(ALIGN(PKT_BUF_SZ, 16));
585
586 if (!priv->rx_skb[q][entry]) {
587 skb = netdev_alloc_skb(ndev,
588 PKT_BUF_SZ + RAVB_ALIGN - 1);
589 if (!skb)
590 break; /* Better luck next round. */
591 ravb_set_buffer_align(skb);
e2dbb33a 592 dma_addr = dma_map_single(ndev->dev.parent, skb->data,
c156633f
SS		 593 le16_to_cpu(desc->ds_cc),
594 DMA_FROM_DEVICE);
595 skb_checksum_none_assert(skb);
d8b48911
SS		 596 /* We just set the data size to 0 for a failed mapping
597 * which should prevent DMA from happening...
598 */
e2dbb33a 599 if (dma_mapping_error(ndev->dev.parent, dma_addr))
d8b48911 600 desc->ds_cc = cpu_to_le16(0);
c156633f
SS		 601 desc->dptr = cpu_to_le32(dma_addr);
602 priv->rx_skb[q][entry] = skb;
603 }
604 /* Descriptor type must be set after all the above writes */
605 dma_wmb();
606 desc->die_dt = DT_FEMPTY;
607 }
608
609 *quota -= limit - (++boguscnt);
610
611 return boguscnt <= 0;
612}
613
614static void ravb_rcv_snd_disable(struct net_device *ndev)
615{
616 /* Disable TX and RX */
617 ravb_write(ndev, ravb_read(ndev, ECMR) & ~(ECMR_RE | ECMR_TE), ECMR);
618}
619
620static void ravb_rcv_snd_enable(struct net_device *ndev)
621{
622 /* Enable TX and RX */
623 ravb_write(ndev, ravb_read(ndev, ECMR) | ECMR_RE | ECMR_TE, ECMR);
624}
625
626/* function for waiting dma process finished */
627static int ravb_stop_dma(struct net_device *ndev)
628{
629 int error;
630
631 /* Wait for stopping the hardware TX process */
632 error = ravb_wait(ndev, TCCR,
633 TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 0);
634 if (error)
635 return error;
636
637 error = ravb_wait(ndev, CSR, CSR_TPO0 | CSR_TPO1 | CSR_TPO2 | CSR_TPO3,
638 0);
639 if (error)
640 return error;
641
642 /* Stop the E-MAC's RX/TX processes. */
643 ravb_rcv_snd_disable(ndev);
644
645 /* Wait for stopping the RX DMA process */
646 error = ravb_wait(ndev, CSR, CSR_RPO, 0);
647 if (error)
648 return error;
649
650 /* Stop AVB-DMAC process */
651 return ravb_config(ndev);
652}
653
654/* E-MAC interrupt handler */
655static void ravb_emac_interrupt(struct net_device *ndev)
656{
657 struct ravb_private *priv = netdev_priv(ndev);
658 u32 ecsr, psr;
659
660 ecsr = ravb_read(ndev, ECSR);
661 ravb_write(ndev, ecsr, ECSR); /* clear interrupt */
662 if (ecsr & ECSR_ICD)
663 ndev->stats.tx_carrier_errors++;
664 if (ecsr & ECSR_LCHNG) {
665 /* Link changed */
666 if (priv->no_avb_link)
667 return;
668 psr = ravb_read(ndev, PSR);
669 if (priv->avb_link_active_low)
670 psr ^= PSR_LMON;
671 if (!(psr & PSR_LMON)) {
672 /* DIsable RX and TX */
673 ravb_rcv_snd_disable(ndev);
674 } else {
675 /* Enable RX and TX */
676 ravb_rcv_snd_enable(ndev);
677 }
678 }
679}
680
681/* Error interrupt handler */
682static void ravb_error_interrupt(struct net_device *ndev)
683{
684 struct ravb_private *priv = netdev_priv(ndev);
685 u32 eis, ris2;
686
687 eis = ravb_read(ndev, EIS);
688 ravb_write(ndev, ~EIS_QFS, EIS);
689 if (eis & EIS_QFS) {
690 ris2 = ravb_read(ndev, RIS2);
691 ravb_write(ndev, ~(RIS2_QFF0 | RIS2_RFFF), RIS2);
692
693 /* Receive Descriptor Empty int */
694 if (ris2 & RIS2_QFF0)
695 priv->stats[RAVB_BE].rx_over_errors++;
696
697 /* Receive Descriptor Empty int */
698 if (ris2 & RIS2_QFF1)
699 priv->stats[RAVB_NC].rx_over_errors++;
700
701 /* Receive FIFO Overflow int */
702 if (ris2 & RIS2_RFFF)
703 priv->rx_fifo_errors++;
704 }
705}
706
707static irqreturn_t ravb_interrupt(int irq, void *dev_id)
708{
709 struct net_device *ndev = dev_id;
710 struct ravb_private *priv = netdev_priv(ndev);
711 irqreturn_t result = IRQ_NONE;
712 u32 iss;
713
714 spin_lock(&priv->lock);
715 /* Get interrupt status */
716 iss = ravb_read(ndev, ISS);
717
718 /* Received and transmitted interrupts */
719 if (iss & (ISS_FRS | ISS_FTS | ISS_TFUS)) {
720 u32 ris0 = ravb_read(ndev, RIS0);
721 u32 ric0 = ravb_read(ndev, RIC0);
722 u32 tis = ravb_read(ndev, TIS);
723 u32 tic = ravb_read(ndev, TIC);
724 int q;
725
726 /* Timestamp updated */
727 if (tis & TIS_TFUF) {
728 ravb_write(ndev, ~TIS_TFUF, TIS);
729 ravb_get_tx_tstamp(ndev);
730 result = IRQ_HANDLED;
731 }
732
733 /* Network control and best effort queue RX/TX */
734 for (q = RAVB_NC; q >= RAVB_BE; q--) {
735 if (((ris0 & ric0) & BIT(q)) ||
736 ((tis & tic) & BIT(q))) {
737 if (napi_schedule_prep(&priv->napi[q])) {
738 /* Mask RX and TX interrupts */
2452cb0c
MN		 739 ric0 &= ~BIT(q);
740 tic &= ~BIT(q);
741 ravb_write(ndev, ric0, RIC0);
742 ravb_write(ndev, tic, TIC);
c156633f
SS		 743 __napi_schedule(&priv->napi[q]);
744 } else {
745 netdev_warn(ndev,
746 "ignoring interrupt, rx status 0x%08x, rx mask 0x%08x,\n",
747 ris0, ric0);
748 netdev_warn(ndev,
749 " tx status 0x%08x, tx mask 0x%08x.\n",
750 tis, tic);
751 }
752 result = IRQ_HANDLED;
753 }
754 }
755 }
756
757 /* E-MAC status summary */
758 if (iss & ISS_MS) {
759 ravb_emac_interrupt(ndev);
760 result = IRQ_HANDLED;
761 }
762
763 /* Error status summary */
764 if (iss & ISS_ES) {
765 ravb_error_interrupt(ndev);
766 result = IRQ_HANDLED;
767 }
768
a0d2f206
SS		 769 if (iss & ISS_CGIS)
770 result = ravb_ptp_interrupt(ndev);
771
c156633f
SS		 772 mmiowb();
773 spin_unlock(&priv->lock);
774 return result;
775}
776
777static int ravb_poll(struct napi_struct *napi, int budget)
778{
779 struct net_device *ndev = napi->dev;
780 struct ravb_private *priv = netdev_priv(ndev);
781 unsigned long flags;
782 int q = napi - priv->napi;
783 int mask = BIT(q);
784 int quota = budget;
785 u32 ris0, tis;
786
787 for (;;) {
788 tis = ravb_read(ndev, TIS);
789 ris0 = ravb_read(ndev, RIS0);
790 if (!((ris0 & mask) || (tis & mask)))
791 break;
792
793 /* Processing RX Descriptor Ring */
794 if (ris0 & mask) {
795 /* Clear RX interrupt */
796 ravb_write(ndev, ~mask, RIS0);
797 if (ravb_rx(ndev, &quota, q))
798 goto out;
799 }
800 /* Processing TX Descriptor Ring */
801 if (tis & mask) {
802 spin_lock_irqsave(&priv->lock, flags);
803 /* Clear TX interrupt */
804 ravb_write(ndev, ~mask, TIS);
805 ravb_tx_free(ndev, q);
806 netif_wake_subqueue(ndev, q);
807 mmiowb();
808 spin_unlock_irqrestore(&priv->lock, flags);
809 }
810 }
811
812 napi_complete(napi);
813
814 /* Re-enable RX/TX interrupts */
815 spin_lock_irqsave(&priv->lock, flags);
816 ravb_write(ndev, ravb_read(ndev, RIC0) | mask, RIC0);
817 ravb_write(ndev, ravb_read(ndev, TIC) | mask, TIC);
818 mmiowb();
819 spin_unlock_irqrestore(&priv->lock, flags);
820
821 /* Receive error message handling */
822 priv->rx_over_errors = priv->stats[RAVB_BE].rx_over_errors;
823 priv->rx_over_errors += priv->stats[RAVB_NC].rx_over_errors;
824 if (priv->rx_over_errors != ndev->stats.rx_over_errors) {
825 ndev->stats.rx_over_errors = priv->rx_over_errors;
826 netif_err(priv, rx_err, ndev, "Receive Descriptor Empty\n");
827 }
828 if (priv->rx_fifo_errors != ndev->stats.rx_fifo_errors) {
829 ndev->stats.rx_fifo_errors = priv->rx_fifo_errors;
830 netif_err(priv, rx_err, ndev, "Receive FIFO Overflow\n");
831 }
832out:
833 return budget - quota;
834}
835
836/* PHY state control function */
837static void ravb_adjust_link(struct net_device *ndev)
838{
839 struct ravb_private *priv = netdev_priv(ndev);
840 struct phy_device *phydev = priv->phydev;
841 bool new_state = false;
842
843 if (phydev->link) {
844 if (phydev->duplex != priv->duplex) {
845 new_state = true;
846 priv->duplex = phydev->duplex;
847 ravb_set_duplex(ndev);
848 }
849
850 if (phydev->speed != priv->speed) {
851 new_state = true;
852 priv->speed = phydev->speed;
853 ravb_set_rate(ndev);
854 }
855 if (!priv->link) {
856 ravb_write(ndev, ravb_read(ndev, ECMR) & ~ECMR_TXF,
857 ECMR);
858 new_state = true;
859 priv->link = phydev->link;
860 if (priv->no_avb_link)
861 ravb_rcv_snd_enable(ndev);
862 }
863 } else if (priv->link) {
864 new_state = true;
865 priv->link = 0;
866 priv->speed = 0;
867 priv->duplex = -1;
868 if (priv->no_avb_link)
869 ravb_rcv_snd_disable(ndev);
870 }
871
872 if (new_state && netif_msg_link(priv))
873 phy_print_status(phydev);
874}
875
876/* PHY init function */
877static int ravb_phy_init(struct net_device *ndev)
878{
879 struct device_node *np = ndev->dev.parent->of_node;
880 struct ravb_private *priv = netdev_priv(ndev);
881 struct phy_device *phydev;
882 struct device_node *pn;
883
884 priv->link = 0;
885 priv->speed = 0;
886 priv->duplex = -1;
887
888 /* Try connecting to PHY */
889 pn = of_parse_phandle(np, "phy-handle", 0);
890 phydev = of_phy_connect(ndev, pn, ravb_adjust_link, 0,
891 priv->phy_interface);
892 if (!phydev) {
893 netdev_err(ndev, "failed to connect PHY\n");
894 return -ENOENT;
895 }
896
22d4df8f
KM		 897 /* This driver only support 10/100Mbit speeds on Gen3
898 * at this time.
899 */
900 if (priv->chip_id == RCAR_GEN3) {
901 int err;
902
903 err = phy_set_max_speed(phydev, SPEED_100);
904 if (err) {
905 netdev_err(ndev, "failed to limit PHY to 100Mbit/s\n");
906 phy_disconnect(phydev);
907 return err;
908 }
909
910 netdev_info(ndev, "limited PHY to 100Mbit/s\n");
911 }
912
c156633f
SS		 913 netdev_info(ndev, "attached PHY %d (IRQ %d) to driver %s\n",
914 phydev->addr, phydev->irq, phydev->drv->name);
915
916 priv->phydev = phydev;
917
918 return 0;
919}
920
921/* PHY control start function */
922static int ravb_phy_start(struct net_device *ndev)
923{
924 struct ravb_private *priv = netdev_priv(ndev);
925 int error;
926
927 error = ravb_phy_init(ndev);
928 if (error)
929 return error;
930
931 phy_start(priv->phydev);
932
933 return 0;
934}
935
936static int ravb_get_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
937{
938 struct ravb_private *priv = netdev_priv(ndev);
939 int error = -ENODEV;
940 unsigned long flags;
941
942 if (priv->phydev) {
943 spin_lock_irqsave(&priv->lock, flags);
944 error = phy_ethtool_gset(priv->phydev, ecmd);
945 spin_unlock_irqrestore(&priv->lock, flags);
946 }
947
948 return error;
949}
950
951static int ravb_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
952{
953 struct ravb_private *priv = netdev_priv(ndev);
954 unsigned long flags;
955 int error;
956
957 if (!priv->phydev)
958 return -ENODEV;
959
960 spin_lock_irqsave(&priv->lock, flags);
961
962 /* Disable TX and RX */
963 ravb_rcv_snd_disable(ndev);
964
965 error = phy_ethtool_sset(priv->phydev, ecmd);
966 if (error)
967 goto error_exit;
968
969 if (ecmd->duplex == DUPLEX_FULL)
970 priv->duplex = 1;
971 else
972 priv->duplex = 0;
973
974 ravb_set_duplex(ndev);
975
976error_exit:
977 mdelay(1);
978
979 /* Enable TX and RX */
980 ravb_rcv_snd_enable(ndev);
981
982 mmiowb();
983 spin_unlock_irqrestore(&priv->lock, flags);
984
985 return error;
986}
987
988static int ravb_nway_reset(struct net_device *ndev)
989{
990 struct ravb_private *priv = netdev_priv(ndev);
991 int error = -ENODEV;
992 unsigned long flags;
993
994 if (priv->phydev) {
995 spin_lock_irqsave(&priv->lock, flags);
996 error = phy_start_aneg(priv->phydev);
997 spin_unlock_irqrestore(&priv->lock, flags);
998 }
999
1000 return error;
1001}
1002
1003static u32 ravb_get_msglevel(struct net_device *ndev)
1004{
1005 struct ravb_private *priv = netdev_priv(ndev);
1006
1007 return priv->msg_enable;
1008}
1009
1010static void ravb_set_msglevel(struct net_device *ndev, u32 value)
1011{
1012 struct ravb_private *priv = netdev_priv(ndev);
1013
1014 priv->msg_enable = value;
1015}
1016
1017static const char ravb_gstrings_stats[][ETH_GSTRING_LEN] = {
1018 "rx_queue_0_current",
1019 "tx_queue_0_current",
1020 "rx_queue_0_dirty",
1021 "tx_queue_0_dirty",
1022 "rx_queue_0_packets",
1023 "tx_queue_0_packets",
1024 "rx_queue_0_bytes",
1025 "tx_queue_0_bytes",
1026 "rx_queue_0_mcast_packets",
1027 "rx_queue_0_errors",
1028 "rx_queue_0_crc_errors",
1029 "rx_queue_0_frame_errors",
1030 "rx_queue_0_length_errors",
1031 "rx_queue_0_missed_errors",
1032 "rx_queue_0_over_errors",
1033
1034 "rx_queue_1_current",
1035 "tx_queue_1_current",
1036 "rx_queue_1_dirty",
1037 "tx_queue_1_dirty",
1038 "rx_queue_1_packets",
1039 "tx_queue_1_packets",
1040 "rx_queue_1_bytes",
1041 "tx_queue_1_bytes",
1042 "rx_queue_1_mcast_packets",
1043 "rx_queue_1_errors",
1044 "rx_queue_1_crc_errors",
1045 "rx_queue_1_frame_errors_",
1046 "rx_queue_1_length_errors",
1047 "rx_queue_1_missed_errors",
1048 "rx_queue_1_over_errors",
1049};
1050
1051#define RAVB_STATS_LEN ARRAY_SIZE(ravb_gstrings_stats)
1052
1053static int ravb_get_sset_count(struct net_device *netdev, int sset)
1054{
1055 switch (sset) {
1056 case ETH_SS_STATS:
1057 return RAVB_STATS_LEN;
1058 default:
1059 return -EOPNOTSUPP;
1060 }
1061}
1062
1063static void ravb_get_ethtool_stats(struct net_device *ndev,
1064 struct ethtool_stats *stats, u64 *data)
1065{
1066 struct ravb_private *priv = netdev_priv(ndev);
1067 int i = 0;
1068 int q;
1069
1070 /* Device-specific stats */
1071 for (q = RAVB_BE; q < NUM_RX_QUEUE; q++) {
1072 struct net_device_stats *stats = &priv->stats[q];
1073
1074 data[i++] = priv->cur_rx[q];
1075 data[i++] = priv->cur_tx[q];
1076 data[i++] = priv->dirty_rx[q];
1077 data[i++] = priv->dirty_tx[q];
1078 data[i++] = stats->rx_packets;
1079 data[i++] = stats->tx_packets;
1080 data[i++] = stats->rx_bytes;
1081 data[i++] = stats->tx_bytes;
1082 data[i++] = stats->multicast;
1083 data[i++] = stats->rx_errors;
1084 data[i++] = stats->rx_crc_errors;
1085 data[i++] = stats->rx_frame_errors;
1086 data[i++] = stats->rx_length_errors;
1087 data[i++] = stats->rx_missed_errors;
1088 data[i++] = stats->rx_over_errors;
1089 }
1090}
1091
1092static void ravb_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1093{
1094 switch (stringset) {
1095 case ETH_SS_STATS:
1096 memcpy(data, *ravb_gstrings_stats, sizeof(ravb_gstrings_stats));
1097 break;
1098 }
1099}
1100
1101static void ravb_get_ringparam(struct net_device *ndev,
1102 struct ethtool_ringparam *ring)
1103{
1104 struct ravb_private *priv = netdev_priv(ndev);
1105
1106 ring->rx_max_pending = BE_RX_RING_MAX;
1107 ring->tx_max_pending = BE_TX_RING_MAX;
1108 ring->rx_pending = priv->num_rx_ring[RAVB_BE];
1109 ring->tx_pending = priv->num_tx_ring[RAVB_BE];
1110}
1111
1112static int ravb_set_ringparam(struct net_device *ndev,
1113 struct ethtool_ringparam *ring)
1114{
1115 struct ravb_private *priv = netdev_priv(ndev);
1116 int error;
1117
1118 if (ring->tx_pending > BE_TX_RING_MAX ||
1119 ring->rx_pending > BE_RX_RING_MAX ||
1120 ring->tx_pending < BE_TX_RING_MIN ||
1121 ring->rx_pending < BE_RX_RING_MIN)
1122 return -EINVAL;
1123 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
1124 return -EINVAL;
1125
1126 if (netif_running(ndev)) {
1127 netif_device_detach(ndev);
a0d2f206
SS		 1128 /* Stop PTP Clock driver */
1129 ravb_ptp_stop(ndev);
c156633f
SS		 1130 /* Wait for DMA stopping */
1131 error = ravb_stop_dma(ndev);
1132 if (error) {
1133 netdev_err(ndev,
1134 "cannot set ringparam! Any AVB processes are still running?\n");
1135 return error;
1136 }
1137 synchronize_irq(ndev->irq);
1138
1139 /* Free all the skb's in the RX queue and the DMA buffers. */
1140 ravb_ring_free(ndev, RAVB_BE);
1141 ravb_ring_free(ndev, RAVB_NC);
1142 }
1143
1144 /* Set new parameters */
1145 priv->num_rx_ring[RAVB_BE] = ring->rx_pending;
1146 priv->num_tx_ring[RAVB_BE] = ring->tx_pending;
1147
1148 if (netif_running(ndev)) {
1149 error = ravb_dmac_init(ndev);
1150 if (error) {
1151 netdev_err(ndev,
1152 "%s: ravb_dmac_init() failed, error %d\n",
1153 __func__, error);
1154 return error;
1155 }
1156
1157 ravb_emac_init(ndev);
1158
a0d2f206
SS		 1159 /* Initialise PTP Clock driver */
1160 ravb_ptp_init(ndev, priv->pdev);
1161
c156633f
SS		 1162 netif_device_attach(ndev);
1163 }
1164
1165 return 0;
1166}
1167
1168static int ravb_get_ts_info(struct net_device *ndev,
1169 struct ethtool_ts_info *info)
1170{
a0d2f206
SS		 1171 struct ravb_private *priv = netdev_priv(ndev);
1172
c156633f
SS		 1173 info->so_timestamping =
1174 SOF_TIMESTAMPING_TX_SOFTWARE |
1175 SOF_TIMESTAMPING_RX_SOFTWARE |
1176 SOF_TIMESTAMPING_SOFTWARE |
1177 SOF_TIMESTAMPING_TX_HARDWARE |
1178 SOF_TIMESTAMPING_RX_HARDWARE |
1179 SOF_TIMESTAMPING_RAW_HARDWARE;
1180 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON);
1181 info->rx_filters =
1182 (1 << HWTSTAMP_FILTER_NONE) |
1183 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
1184 (1 << HWTSTAMP_FILTER_ALL);
a0d2f206 1185 info->phc_index = ptp_clock_index(priv->ptp.clock);
c156633f
SS		 1186
1187 return 0;
1188}
1189
1190static const struct ethtool_ops ravb_ethtool_ops = {
1191 .get_settings = ravb_get_settings,
1192 .set_settings = ravb_set_settings,
1193 .nway_reset = ravb_nway_reset,
1194 .get_msglevel = ravb_get_msglevel,
1195 .set_msglevel = ravb_set_msglevel,
1196 .get_link = ethtool_op_get_link,
1197 .get_strings = ravb_get_strings,
1198 .get_ethtool_stats = ravb_get_ethtool_stats,
1199 .get_sset_count = ravb_get_sset_count,
1200 .get_ringparam = ravb_get_ringparam,
1201 .set_ringparam = ravb_set_ringparam,
1202 .get_ts_info = ravb_get_ts_info,
1203};
1204
1205/* Network device open function for Ethernet AVB */
1206static int ravb_open(struct net_device *ndev)
1207{
1208 struct ravb_private *priv = netdev_priv(ndev);
1209 int error;
1210
1211 napi_enable(&priv->napi[RAVB_BE]);
1212 napi_enable(&priv->napi[RAVB_NC]);
1213
1214 error = request_irq(ndev->irq, ravb_interrupt, IRQF_SHARED, ndev->name,
1215 ndev);
1216 if (error) {
1217 netdev_err(ndev, "cannot request IRQ\n");
1218 goto out_napi_off;
1219 }
1220
22d4df8f
KM		 1221 if (priv->chip_id == RCAR_GEN3) {
1222 error = request_irq(priv->emac_irq, ravb_interrupt,
1223 IRQF_SHARED, ndev->name, ndev);
1224 if (error) {
1225 netdev_err(ndev, "cannot request IRQ\n");
1226 goto out_free_irq;
1227 }
1228 }
1229
c156633f
SS		 1230 /* Device init */
1231 error = ravb_dmac_init(ndev);
1232 if (error)
508dc064 1233 goto out_free_irq2;
c156633f
SS		 1234 ravb_emac_init(ndev);
1235
a0d2f206 1236 /* Initialise PTP Clock driver */
f5d7837f
KM		 1237 if (priv->chip_id == RCAR_GEN2)
1238 ravb_ptp_init(ndev, priv->pdev);
a0d2f206 1239
c156633f
SS		 1240 netif_tx_start_all_queues(ndev);
1241
1242 /* PHY control start */
1243 error = ravb_phy_start(ndev);
1244 if (error)
a0d2f206 1245 goto out_ptp_stop;
c156633f
SS		 1246
1247 return 0;
1248
a0d2f206
SS		 1249out_ptp_stop:
1250 /* Stop PTP Clock driver */
f5d7837f
KM		 1251 if (priv->chip_id == RCAR_GEN2)
1252 ravb_ptp_stop(ndev);
508dc064
SS		 1253out_free_irq2:
1254 if (priv->chip_id == RCAR_GEN3)
1255 free_irq(priv->emac_irq, ndev);
c156633f
SS		 1256out_free_irq:
1257 free_irq(ndev->irq, ndev);
1258out_napi_off:
1259 napi_disable(&priv->napi[RAVB_NC]);
1260 napi_disable(&priv->napi[RAVB_BE]);
1261 return error;
1262}
1263
1264/* Timeout function for Ethernet AVB */
1265static void ravb_tx_timeout(struct net_device *ndev)
1266{
1267 struct ravb_private *priv = netdev_priv(ndev);
1268
1269 netif_err(priv, tx_err, ndev,
1270 "transmit timed out, status %08x, resetting...\n",
1271 ravb_read(ndev, ISS));
1272
1273 /* tx_errors count up */
1274 ndev->stats.tx_errors++;
1275
1276 schedule_work(&priv->work);
1277}
1278
1279static void ravb_tx_timeout_work(struct work_struct *work)
1280{
1281 struct ravb_private *priv = container_of(work, struct ravb_private,
1282 work);
1283 struct net_device *ndev = priv->ndev;
1284
1285 netif_tx_stop_all_queues(ndev);
1286
a0d2f206
SS		 1287 /* Stop PTP Clock driver */
1288 ravb_ptp_stop(ndev);
1289
c156633f
SS		 1290 /* Wait for DMA stopping */
1291 ravb_stop_dma(ndev);
1292
1293 ravb_ring_free(ndev, RAVB_BE);
1294 ravb_ring_free(ndev, RAVB_NC);
1295
1296 /* Device init */
1297 ravb_dmac_init(ndev);
1298 ravb_emac_init(ndev);
1299
a0d2f206
SS		 1300 /* Initialise PTP Clock driver */
1301 ravb_ptp_init(ndev, priv->pdev);
1302
c156633f
SS		 1303 netif_tx_start_all_queues(ndev);
1304}
1305
1306/* Packet transmit function for Ethernet AVB */
1307static netdev_tx_t ravb_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1308{
1309 struct ravb_private *priv = netdev_priv(ndev);
c156633f 1310 u16 q = skb_get_queue_mapping(skb);
aad0d51e 1311 struct ravb_tstamp_skb *ts_skb;
c156633f
SS		 1312 struct ravb_tx_desc *desc;
1313 unsigned long flags;
1314 u32 dma_addr;
1315 void *buffer;
1316 u32 entry;
2f45d190 1317 u32 len;
c156633f
SS		 1318
1319 spin_lock_irqsave(&priv->lock, flags);
2f45d190
SS		 1320 if (priv->cur_tx[q] - priv->dirty_tx[q] > (priv->num_tx_ring[q] - 1) *
1321 NUM_TX_DESC) {
c156633f
SS		 1322 netif_err(priv, tx_queued, ndev,
1323 "still transmitting with the full ring!\n");
1324 netif_stop_subqueue(ndev, q);
1325 spin_unlock_irqrestore(&priv->lock, flags);
1326 return NETDEV_TX_BUSY;
1327 }
2f45d190
SS		 1328 entry = priv->cur_tx[q] % (priv->num_tx_ring[q] * NUM_TX_DESC);
1329 priv->tx_skb[q][entry / NUM_TX_DESC] = skb;
c156633f
SS		 1330
1331 if (skb_put_padto(skb, ETH_ZLEN))
1332 goto drop;
1333
2f45d190
SS		 1334 buffer = PTR_ALIGN(priv->tx_align[q], DPTR_ALIGN) +
1335 entry / NUM_TX_DESC * DPTR_ALIGN;
1336 len = PTR_ALIGN(skb->data, DPTR_ALIGN) - skb->data;
1337 memcpy(buffer, skb->data, len);
e2dbb33a
KM		 1338 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, DMA_TO_DEVICE);
1339 if (dma_mapping_error(ndev->dev.parent, dma_addr))
c156633f 1340 goto drop;
2f45d190
SS		 1341
1342 desc = &priv->tx_ring[q][entry];
1343 desc->ds_tagl = cpu_to_le16(len);
1344 desc->dptr = cpu_to_le32(dma_addr);
1345
1346 buffer = skb->data + len;
1347 len = skb->len - len;
e2dbb33a
KM		 1348 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, DMA_TO_DEVICE);
1349 if (dma_mapping_error(ndev->dev.parent, dma_addr))
2f45d190
SS		 1350 goto unmap;
1351
1352 desc++;
1353 desc->ds_tagl = cpu_to_le16(len);
c156633f
SS		 1354 desc->dptr = cpu_to_le32(dma_addr);
1355
1356 /* TX timestamp required */
1357 if (q == RAVB_NC) {
1358 ts_skb = kmalloc(sizeof(*ts_skb), GFP_ATOMIC);
1359 if (!ts_skb) {
2f45d190 1360 desc--;
e2dbb33a 1361 dma_unmap_single(ndev->dev.parent, dma_addr, len,
c156633f 1362 DMA_TO_DEVICE);
2f45d190 1363 goto unmap;
c156633f
SS		 1364 }
1365 ts_skb->skb = skb;
1366 ts_skb->tag = priv->ts_skb_tag++;
1367 priv->ts_skb_tag &= 0x3ff;
1368 list_add_tail(&ts_skb->list, &priv->ts_skb_list);
1369
1370 /* TAG and timestamp required flag */
1371 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1372 skb_tx_timestamp(skb);
1373 desc->tagh_tsr = (ts_skb->tag >> 4) | TX_TSR;
1374 desc->ds_tagl |= le16_to_cpu(ts_skb->tag << 12);
1375 }
1376
1377 /* Descriptor type must be set after all the above writes */
1378 dma_wmb();
2f45d190
SS		 1379 desc->die_dt = DT_FEND;
1380 desc--;
1381 desc->die_dt = DT_FSTART;
c156633f 1382
06613e38 1383 ravb_write(ndev, ravb_read(ndev, TCCR) | (TCCR_TSRQ0 << q), TCCR);
c156633f 1384
2f45d190
SS		 1385 priv->cur_tx[q] += NUM_TX_DESC;
1386 if (priv->cur_tx[q] - priv->dirty_tx[q] >
1387 (priv->num_tx_ring[q] - 1) * NUM_TX_DESC && !ravb_tx_free(ndev, q))
c156633f
SS		 1388 netif_stop_subqueue(ndev, q);
1389
1390exit:
1391 mmiowb();
1392 spin_unlock_irqrestore(&priv->lock, flags);
1393 return NETDEV_TX_OK;
1394
2f45d190 1395unmap:
e2dbb33a 1396 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
2f45d190 1397 le16_to_cpu(desc->ds_tagl), DMA_TO_DEVICE);
c156633f
SS		 1398drop:
1399 dev_kfree_skb_any(skb);
2f45d190 1400 priv->tx_skb[q][entry / NUM_TX_DESC] = NULL;
c156633f
SS		 1401 goto exit;
1402}
1403
1404static u16 ravb_select_queue(struct net_device *ndev, struct sk_buff *skb,
1405 void *accel_priv, select_queue_fallback_t fallback)
1406{
1407 /* If skb needs TX timestamp, it is handled in network control queue */
1408 return (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) ? RAVB_NC :
1409 RAVB_BE;
1410
1411}
1412
1413static struct net_device_stats *ravb_get_stats(struct net_device *ndev)
1414{
1415 struct ravb_private *priv = netdev_priv(ndev);
1416 struct net_device_stats *nstats, *stats0, *stats1;
1417
1418 nstats = &ndev->stats;
1419 stats0 = &priv->stats[RAVB_BE];
1420 stats1 = &priv->stats[RAVB_NC];
1421
1422 nstats->tx_dropped += ravb_read(ndev, TROCR);
1423 ravb_write(ndev, 0, TROCR); /* (write clear) */
1424 nstats->collisions += ravb_read(ndev, CDCR);
1425 ravb_write(ndev, 0, CDCR); /* (write clear) */
1426 nstats->tx_carrier_errors += ravb_read(ndev, LCCR);
1427 ravb_write(ndev, 0, LCCR); /* (write clear) */
1428
1429 nstats->tx_carrier_errors += ravb_read(ndev, CERCR);
1430 ravb_write(ndev, 0, CERCR); /* (write clear) */
1431 nstats->tx_carrier_errors += ravb_read(ndev, CEECR);
1432 ravb_write(ndev, 0, CEECR); /* (write clear) */
1433
1434 nstats->rx_packets = stats0->rx_packets + stats1->rx_packets;
1435 nstats->tx_packets = stats0->tx_packets + stats1->tx_packets;
1436 nstats->rx_bytes = stats0->rx_bytes + stats1->rx_bytes;
1437 nstats->tx_bytes = stats0->tx_bytes + stats1->tx_bytes;
1438 nstats->multicast = stats0->multicast + stats1->multicast;
1439 nstats->rx_errors = stats0->rx_errors + stats1->rx_errors;
1440 nstats->rx_crc_errors = stats0->rx_crc_errors + stats1->rx_crc_errors;
1441 nstats->rx_frame_errors =
1442 stats0->rx_frame_errors + stats1->rx_frame_errors;
1443 nstats->rx_length_errors =
1444 stats0->rx_length_errors + stats1->rx_length_errors;
1445 nstats->rx_missed_errors =
1446 stats0->rx_missed_errors + stats1->rx_missed_errors;
1447 nstats->rx_over_errors =
1448 stats0->rx_over_errors + stats1->rx_over_errors;
1449
1450 return nstats;
1451}
1452
1453/* Update promiscuous bit */
1454static void ravb_set_rx_mode(struct net_device *ndev)
1455{
1456 struct ravb_private *priv = netdev_priv(ndev);
1457 unsigned long flags;
1458 u32 ecmr;
1459
1460 spin_lock_irqsave(&priv->lock, flags);
1461 ecmr = ravb_read(ndev, ECMR);
1462 if (ndev->flags & IFF_PROMISC)
1463 ecmr |= ECMR_PRM;
1464 else
1465 ecmr &= ~ECMR_PRM;
1466 ravb_write(ndev, ecmr, ECMR);
1467 mmiowb();
1468 spin_unlock_irqrestore(&priv->lock, flags);
1469}
1470
1471/* Device close function for Ethernet AVB */
1472static int ravb_close(struct net_device *ndev)
1473{
1474 struct ravb_private *priv = netdev_priv(ndev);
1475 struct ravb_tstamp_skb *ts_skb, *ts_skb2;
1476
1477 netif_tx_stop_all_queues(ndev);
1478
1479 /* Disable interrupts by clearing the interrupt masks. */
1480 ravb_write(ndev, 0, RIC0);
1481 ravb_write(ndev, 0, RIC1);
1482 ravb_write(ndev, 0, RIC2);
1483 ravb_write(ndev, 0, TIC);
1484
a0d2f206 1485 /* Stop PTP Clock driver */
f5d7837f
KM		 1486 if (priv->chip_id == RCAR_GEN2)
1487 ravb_ptp_stop(ndev);
a0d2f206 1488
c156633f
SS		 1489 /* Set the config mode to stop the AVB-DMAC's processes */
1490 if (ravb_stop_dma(ndev) < 0)
1491 netdev_err(ndev,
1492 "device will be stopped after h/w processes are done.\n");
1493
1494 /* Clear the timestamp list */
1495 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, list) {
1496 list_del(&ts_skb->list);
1497 kfree(ts_skb);
1498 }
1499
1500 /* PHY disconnect */
1501 if (priv->phydev) {
1502 phy_stop(priv->phydev);
1503 phy_disconnect(priv->phydev);
1504 priv->phydev = NULL;
1505 }
1506
1507 free_irq(ndev->irq, ndev);
1508
1509 napi_disable(&priv->napi[RAVB_NC]);
1510 napi_disable(&priv->napi[RAVB_BE]);
1511
1512 /* Free all the skb's in the RX queue and the DMA buffers. */
1513 ravb_ring_free(ndev, RAVB_BE);
1514 ravb_ring_free(ndev, RAVB_NC);
1515
1516 return 0;
1517}
1518
1519static int ravb_hwtstamp_get(struct net_device *ndev, struct ifreq *req)
1520{
1521 struct ravb_private *priv = netdev_priv(ndev);
1522 struct hwtstamp_config config;
1523
1524 config.flags = 0;
1525 config.tx_type = priv->tstamp_tx_ctrl ? HWTSTAMP_TX_ON :
1526 HWTSTAMP_TX_OFF;
1527 if (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE_V2_L2_EVENT)
1528 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
1529 else if (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE_ALL)
1530 config.rx_filter = HWTSTAMP_FILTER_ALL;
1531 else
1532 config.rx_filter = HWTSTAMP_FILTER_NONE;
1533
1534 return copy_to_user(req->ifr_data, &config, sizeof(config)) ?
1535 -EFAULT : 0;
1536}
1537
1538/* Control hardware time stamping */
1539static int ravb_hwtstamp_set(struct net_device *ndev, struct ifreq *req)
1540{
1541 struct ravb_private *priv = netdev_priv(ndev);
1542 struct hwtstamp_config config;
1543 u32 tstamp_rx_ctrl = RAVB_RXTSTAMP_ENABLED;
1544 u32 tstamp_tx_ctrl;
1545
1546 if (copy_from_user(&config, req->ifr_data, sizeof(config)))
1547 return -EFAULT;
1548
1549 /* Reserved for future extensions */
1550 if (config.flags)
1551 return -EINVAL;
1552
1553 switch (config.tx_type) {
1554 case HWTSTAMP_TX_OFF:
1555 tstamp_tx_ctrl = 0;
1556 break;
1557 case HWTSTAMP_TX_ON:
1558 tstamp_tx_ctrl = RAVB_TXTSTAMP_ENABLED;
1559 break;
1560 default:
1561 return -ERANGE;
1562 }
1563
1564 switch (config.rx_filter) {
1565 case HWTSTAMP_FILTER_NONE:
1566 tstamp_rx_ctrl = 0;
1567 break;
1568 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1569 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_V2_L2_EVENT;
1570 break;
1571 default:
1572 config.rx_filter = HWTSTAMP_FILTER_ALL;
1573 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_ALL;
1574 }
1575
1576 priv->tstamp_tx_ctrl = tstamp_tx_ctrl;
1577 priv->tstamp_rx_ctrl = tstamp_rx_ctrl;
1578
1579 return copy_to_user(req->ifr_data, &config, sizeof(config)) ?
1580 -EFAULT : 0;
1581}
1582
1583/* ioctl to device function */
1584static int ravb_do_ioctl(struct net_device *ndev, struct ifreq *req, int cmd)
1585{
1586 struct ravb_private *priv = netdev_priv(ndev);
1587 struct phy_device *phydev = priv->phydev;
1588
1589 if (!netif_running(ndev))
1590 return -EINVAL;
1591
1592 if (!phydev)
1593 return -ENODEV;
1594
1595 switch (cmd) {
1596 case SIOCGHWTSTAMP:
1597 return ravb_hwtstamp_get(ndev, req);
1598 case SIOCSHWTSTAMP:
1599 return ravb_hwtstamp_set(ndev, req);
1600 }
1601
1602 return phy_mii_ioctl(phydev, req, cmd);
1603}
1604
1605static const struct net_device_ops ravb_netdev_ops = {
1606 .ndo_open = ravb_open,
1607 .ndo_stop = ravb_close,
1608 .ndo_start_xmit = ravb_start_xmit,
1609 .ndo_select_queue = ravb_select_queue,
1610 .ndo_get_stats = ravb_get_stats,
1611 .ndo_set_rx_mode = ravb_set_rx_mode,
1612 .ndo_tx_timeout = ravb_tx_timeout,
1613 .ndo_do_ioctl = ravb_do_ioctl,
1614 .ndo_validate_addr = eth_validate_addr,
1615 .ndo_set_mac_address = eth_mac_addr,
1616 .ndo_change_mtu = eth_change_mtu,
1617};
1618
1619/* MDIO bus init function */
1620static int ravb_mdio_init(struct ravb_private *priv)
1621{
1622 struct platform_device *pdev = priv->pdev;
1623 struct device *dev = &pdev->dev;
1624 int error;
1625
1626 /* Bitbang init */
1627 priv->mdiobb.ops = &bb_ops;
1628
1629 /* MII controller setting */
1630 priv->mii_bus = alloc_mdio_bitbang(&priv->mdiobb);
1631 if (!priv->mii_bus)
1632 return -ENOMEM;
1633
1634 /* Hook up MII support for ethtool */
1635 priv->mii_bus->name = "ravb_mii";
1636 priv->mii_bus->parent = dev;
1637 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
1638 pdev->name, pdev->id);
1639
1640 /* Register MDIO bus */
1641 error = of_mdiobus_register(priv->mii_bus, dev->of_node);
1642 if (error)
1643 goto out_free_bus;
1644
1645 return 0;
1646
1647out_free_bus:
1648 free_mdio_bitbang(priv->mii_bus);
1649 return error;
1650}
1651
1652/* MDIO bus release function */
1653static int ravb_mdio_release(struct ravb_private *priv)
1654{
1655 /* Unregister mdio bus */
1656 mdiobus_unregister(priv->mii_bus);
1657
1658 /* Free bitbang info */
1659 free_mdio_bitbang(priv->mii_bus);
1660
1661 return 0;
1662}
1663
22d4df8f
KM		 1664static const struct of_device_id ravb_match_table[] = {
1665 { .compatible = "renesas,etheravb-r8a7790", .data = (void *)RCAR_GEN2 },
1666 { .compatible = "renesas,etheravb-r8a7794", .data = (void *)RCAR_GEN2 },
0e874361 1667 { .compatible = "renesas,etheravb-rcar-gen2", .data = (void *)RCAR_GEN2 },
22d4df8f 1668 { .compatible = "renesas,etheravb-r8a7795", .data = (void *)RCAR_GEN3 },
0e874361 1669 { .compatible = "renesas,etheravb-rcar-gen3", .data = (void *)RCAR_GEN3 },
22d4df8f
KM		 1670 { }
1671};
1672MODULE_DEVICE_TABLE(of, ravb_match_table);
1673
b3d39a88
SH		 1674static int ravb_set_gti(struct net_device *ndev)
1675{
1676
1677 struct device *dev = ndev->dev.parent;
1678 struct device_node *np = dev->of_node;
1679 unsigned long rate;
1680 struct clk *clk;
1681 uint64_t inc;
1682
1683 clk = of_clk_get(np, 0);
1684 if (IS_ERR(clk)) {
1685 dev_err(dev, "could not get clock\n");
1686 return PTR_ERR(clk);
1687 }
1688
1689 rate = clk_get_rate(clk);
1690 clk_put(clk);
1691
1692 inc = 1000000000ULL << 20;
1693 do_div(inc, rate);
1694
1695 if (inc < GTI_TIV_MIN || inc > GTI_TIV_MAX) {
1696 dev_err(dev, "gti.tiv increment 0x%llx is outside the range 0x%x - 0x%x\n",
1697 inc, GTI_TIV_MIN, GTI_TIV_MAX);
1698 return -EINVAL;
1699 }
1700
1701 ravb_write(ndev, inc, GTI);
1702
1703 return 0;
1704}
1705
c156633f
SS		 1706static int ravb_probe(struct platform_device *pdev)
1707{
1708 struct device_node *np = pdev->dev.of_node;
22d4df8f 1709 const struct of_device_id *match;
c156633f 1710 struct ravb_private *priv;
22d4df8f 1711 enum ravb_chip_id chip_id;
c156633f
SS		 1712 struct net_device *ndev;
1713 int error, irq, q;
1714 struct resource *res;
1715
1716 if (!np) {
1717 dev_err(&pdev->dev,
1718 "this driver is required to be instantiated from device tree\n");
1719 return -EINVAL;
1720 }
1721
1722 /* Get base address */
1723 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1724 if (!res) {
1725 dev_err(&pdev->dev, "invalid resource\n");
1726 return -EINVAL;
1727 }
1728
1729 ndev = alloc_etherdev_mqs(sizeof(struct ravb_private),
1730 NUM_TX_QUEUE, NUM_RX_QUEUE);
1731 if (!ndev)
1732 return -ENOMEM;
1733
1734 pm_runtime_enable(&pdev->dev);
1735 pm_runtime_get_sync(&pdev->dev);
1736
1737 /* The Ether-specific entries in the device structure. */
1738 ndev->base_addr = res->start;
1739 ndev->dma = -1;
22d4df8f
KM		 1740
1741 match = of_match_device(of_match_ptr(ravb_match_table), &pdev->dev);
1742 chip_id = (enum ravb_chip_id)match->data;
1743
1744 if (chip_id == RCAR_GEN3)
1745 irq = platform_get_irq_byname(pdev, "ch22");
1746 else
1747 irq = platform_get_irq(pdev, 0);
c156633f 1748 if (irq < 0) {
f375339e 1749 error = irq;
c156633f
SS		 1750 goto out_release;
1751 }
1752 ndev->irq = irq;
1753
1754 SET_NETDEV_DEV(ndev, &pdev->dev);
1755
1756 priv = netdev_priv(ndev);
1757 priv->ndev = ndev;
1758 priv->pdev = pdev;
1759 priv->num_tx_ring[RAVB_BE] = BE_TX_RING_SIZE;
1760 priv->num_rx_ring[RAVB_BE] = BE_RX_RING_SIZE;
1761 priv->num_tx_ring[RAVB_NC] = NC_TX_RING_SIZE;
1762 priv->num_rx_ring[RAVB_NC] = NC_RX_RING_SIZE;
1763 priv->addr = devm_ioremap_resource(&pdev->dev, res);
1764 if (IS_ERR(priv->addr)) {
1765 error = PTR_ERR(priv->addr);
1766 goto out_release;
1767 }
1768
1769 spin_lock_init(&priv->lock);
1770 INIT_WORK(&priv->work, ravb_tx_timeout_work);
1771
1772 priv->phy_interface = of_get_phy_mode(np);
1773
1774 priv->no_avb_link = of_property_read_bool(np, "renesas,no-ether-link");
1775 priv->avb_link_active_low =
1776 of_property_read_bool(np, "renesas,ether-link-active-low");
1777
22d4df8f
KM		 1778 if (chip_id == RCAR_GEN3) {
1779 irq = platform_get_irq_byname(pdev, "ch24");
1780 if (irq < 0) {
1781 error = irq;
1782 goto out_release;
1783 }
1784 priv->emac_irq = irq;
1785 }
1786
1787 priv->chip_id = chip_id;
1788
c156633f
SS		 1789 /* Set function */
1790 ndev->netdev_ops = &ravb_netdev_ops;
1791 ndev->ethtool_ops = &ravb_ethtool_ops;
1792
1793 /* Set AVB config mode */
f5d7837f
KM		 1794 if (chip_id == RCAR_GEN2) {
1795 ravb_write(ndev, (ravb_read(ndev, CCC) & ~CCC_OPC) |
1796 CCC_OPC_CONFIG, CCC);
1797 /* Set CSEL value */
1798 ravb_write(ndev, (ravb_read(ndev, CCC) & ~CCC_CSEL) |
1799 CCC_CSEL_HPB, CCC);
1800 } else {
1801 ravb_write(ndev, (ravb_read(ndev, CCC) & ~CCC_OPC) |
1802 CCC_OPC_CONFIG | CCC_GAC | CCC_CSEL_HPB, CCC);
1803 }
c156633f
SS		 1804
1805 /* Set CSEL value */
1806 ravb_write(ndev, (ravb_read(ndev, CCC) & ~CCC_CSEL) | CCC_CSEL_HPB,
1807 CCC);
1808
1809 /* Set GTI value */
b3d39a88
SH		 1810 error = ravb_set_gti(ndev);
1811 if (error)
1812 goto out_release;
c156633f
SS		 1813
1814 /* Request GTI loading */
1815 ravb_write(ndev, ravb_read(ndev, GCCR) | GCCR_LTI, GCCR);
1816
1817 /* Allocate descriptor base address table */
1818 priv->desc_bat_size = sizeof(struct ravb_desc) * DBAT_ENTRY_NUM;
e2dbb33a 1819 priv->desc_bat = dma_alloc_coherent(ndev->dev.parent, priv->desc_bat_size,
c156633f
SS		 1820 &priv->desc_bat_dma, GFP_KERNEL);
1821 if (!priv->desc_bat) {
c4511132 1822 dev_err(&pdev->dev,
c156633f
SS		 1823 "Cannot allocate desc base address table (size %d bytes)\n",
1824 priv->desc_bat_size);
1825 error = -ENOMEM;
1826 goto out_release;
1827 }
1828 for (q = RAVB_BE; q < DBAT_ENTRY_NUM; q++)
1829 priv->desc_bat[q].die_dt = DT_EOS;
1830 ravb_write(ndev, priv->desc_bat_dma, DBAT);
1831
1832 /* Initialise HW timestamp list */
1833 INIT_LIST_HEAD(&priv->ts_skb_list);
1834
f5d7837f
KM		 1835 /* Initialise PTP Clock driver */
1836 if (chip_id != RCAR_GEN2)
1837 ravb_ptp_init(ndev, pdev);
1838
c156633f
SS		 1839 /* Debug message level */
1840 priv->msg_enable = RAVB_DEF_MSG_ENABLE;
1841
1842 /* Read and set MAC address */
1843 ravb_read_mac_address(ndev, of_get_mac_address(np));
1844 if (!is_valid_ether_addr(ndev->dev_addr)) {
1845 dev_warn(&pdev->dev,
1846 "no valid MAC address supplied, using a random one\n");
1847 eth_hw_addr_random(ndev);
1848 }
1849
1850 /* MDIO bus init */
1851 error = ravb_mdio_init(priv);
1852 if (error) {
c4511132 1853 dev_err(&pdev->dev, "failed to initialize MDIO\n");
c156633f
SS		 1854 goto out_dma_free;
1855 }
1856
1857 netif_napi_add(ndev, &priv->napi[RAVB_BE], ravb_poll, 64);
1858 netif_napi_add(ndev, &priv->napi[RAVB_NC], ravb_poll, 64);
1859
1860 /* Network device register */
1861 error = register_netdev(ndev);
1862 if (error)
1863 goto out_napi_del;
1864
1865 /* Print device information */
1866 netdev_info(ndev, "Base address at %#x, %pM, IRQ %d.\n",
1867 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
1868
1869 platform_set_drvdata(pdev, ndev);
1870
1871 return 0;
1872
1873out_napi_del:
1874 netif_napi_del(&priv->napi[RAVB_NC]);
1875 netif_napi_del(&priv->napi[RAVB_BE]);
1876 ravb_mdio_release(priv);
1877out_dma_free:
e2dbb33a 1878 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat,
c156633f 1879 priv->desc_bat_dma);
f5d7837f
KM		 1880
1881 /* Stop PTP Clock driver */
1882 if (chip_id != RCAR_GEN2)
1883 ravb_ptp_stop(ndev);
c156633f
SS		 1884out_release:
1885 if (ndev)
1886 free_netdev(ndev);
1887
1888 pm_runtime_put(&pdev->dev);
1889 pm_runtime_disable(&pdev->dev);
1890 return error;
1891}
1892
1893static int ravb_remove(struct platform_device *pdev)
1894{
1895 struct net_device *ndev = platform_get_drvdata(pdev);
1896 struct ravb_private *priv = netdev_priv(ndev);
1897
f5d7837f
KM		 1898 /* Stop PTP Clock driver */
1899 if (priv->chip_id != RCAR_GEN2)
1900 ravb_ptp_stop(ndev);
1901
e2dbb33a 1902 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat,
c156633f
SS		 1903 priv->desc_bat_dma);
1904 /* Set reset mode */
1905 ravb_write(ndev, CCC_OPC_RESET, CCC);
1906 pm_runtime_put_sync(&pdev->dev);
1907 unregister_netdev(ndev);
1908 netif_napi_del(&priv->napi[RAVB_NC]);
1909 netif_napi_del(&priv->napi[RAVB_BE]);
1910 ravb_mdio_release(priv);
1911 pm_runtime_disable(&pdev->dev);
1912 free_netdev(ndev);
1913 platform_set_drvdata(pdev, NULL);
1914
1915 return 0;
1916}
1917
1918#ifdef CONFIG_PM
1919static int ravb_runtime_nop(struct device *dev)
1920{
1921 /* Runtime PM callback shared between ->runtime_suspend()
1922 * and ->runtime_resume(). Simply returns success.
1923 *
1924 * This driver re-initializes all registers after
1925 * pm_runtime_get_sync() anyway so there is no need
1926 * to save and restore registers here.
1927 */
1928 return 0;
1929}
1930
1931static const struct dev_pm_ops ravb_dev_pm_ops = {
1932 .runtime_suspend = ravb_runtime_nop,
1933 .runtime_resume = ravb_runtime_nop,
1934};
1935
1936#define RAVB_PM_OPS (&ravb_dev_pm_ops)
1937#else
1938#define RAVB_PM_OPS NULL
1939#endif
1940
c156633f
SS		 1941static struct platform_driver ravb_driver = {
1942 .probe = ravb_probe,
1943 .remove = ravb_remove,
1944 .driver = {
1945 .name = "ravb",
1946 .pm = RAVB_PM_OPS,
1947 .of_match_table = ravb_match_table,
1948 },
1949};
1950
1951module_platform_driver(ravb_driver);
1952
1953MODULE_AUTHOR("Mitsuhiro Kimura, Masaru Nagai");
1954MODULE_DESCRIPTION("Renesas Ethernet AVB driver");
1955MODULE_LICENSE("GPL v2");
Ubuntu Hirsute Linux kernel mirror