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[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / renesas / ravb_main.c
CommitLineData
c156633f
SS		 1/* Renesas Ethernet AVB device driver
2 *
3 * Copyright (C) 2014-2015 Renesas Electronics Corporation
4 * Copyright (C) 2015 Renesas Solutions Corp.
5 * Copyright (C) 2015 Cogent Embedded, Inc. <source@cogentembedded.com>
6 *
7 * Based on the SuperH Ethernet driver
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms and conditions of the GNU General Public License version 2,
11 * as published by the Free Software Foundation.
12 */
13
14#include <linux/cache.h>
15#include <linux/clk.h>
16#include <linux/delay.h>
17#include <linux/dma-mapping.h>
18#include <linux/err.h>
19#include <linux/etherdevice.h>
20#include <linux/ethtool.h>
21#include <linux/if_vlan.h>
22#include <linux/kernel.h>
23#include <linux/list.h>
24#include <linux/module.h>
25#include <linux/net_tstamp.h>
26#include <linux/of.h>
27#include <linux/of_device.h>
28#include <linux/of_irq.h>
29#include <linux/of_mdio.h>
30#include <linux/of_net.h>
c156633f
SS		 31#include <linux/pm_runtime.h>
32#include <linux/slab.h>
33#include <linux/spinlock.h>
34
35#include "ravb.h"
36
37#define RAVB_DEF_MSG_ENABLE \
38 (NETIF_MSG_LINK | \
39 NETIF_MSG_TIMER | \
40 NETIF_MSG_RX_ERR | \
41 NETIF_MSG_TX_ERR)
42
a0d2f206 43int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value)
c156633f
SS		 44{
45 int i;
46
47 for (i = 0; i < 10000; i++) {
48 if ((ravb_read(ndev, reg) & mask) == value)
49 return 0;
50 udelay(10);
51 }
52 return -ETIMEDOUT;
53}
54
55static int ravb_config(struct net_device *ndev)
56{
57 int error;
58
59 /* Set config mode */
60 ravb_write(ndev, (ravb_read(ndev, CCC) & ~CCC_OPC) | CCC_OPC_CONFIG,
61 CCC);
62 /* Check if the operating mode is changed to the config mode */
63 error = ravb_wait(ndev, CSR, CSR_OPS, CSR_OPS_CONFIG);
64 if (error)
65 netdev_err(ndev, "failed to switch device to config mode\n");
66
67 return error;
68}
69
70static void ravb_set_duplex(struct net_device *ndev)
71{
72 struct ravb_private *priv = netdev_priv(ndev);
73 u32 ecmr = ravb_read(ndev, ECMR);
74
75 if (priv->duplex) /* Full */
76 ecmr |= ECMR_DM;
77 else /* Half */
78 ecmr &= ~ECMR_DM;
79 ravb_write(ndev, ecmr, ECMR);
80}
81
82static void ravb_set_rate(struct net_device *ndev)
83{
84 struct ravb_private *priv = netdev_priv(ndev);
85
86 switch (priv->speed) {
87 case 100: /* 100BASE */
88 ravb_write(ndev, GECMR_SPEED_100, GECMR);
89 break;
90 case 1000: /* 1000BASE */
91 ravb_write(ndev, GECMR_SPEED_1000, GECMR);
92 break;
93 default:
94 break;
95 }
96}
97
98static void ravb_set_buffer_align(struct sk_buff *skb)
99{
100 u32 reserve = (unsigned long)skb->data & (RAVB_ALIGN - 1);
101
102 if (reserve)
103 skb_reserve(skb, RAVB_ALIGN - reserve);
104}
105
106/* Get MAC address from the MAC address registers
107 *
108 * Ethernet AVB device doesn't have ROM for MAC address.
109 * This function gets the MAC address that was used by a bootloader.
110 */
111static void ravb_read_mac_address(struct net_device *ndev, const u8 *mac)
112{
113 if (mac) {
114 ether_addr_copy(ndev->dev_addr, mac);
115 } else {
116 ndev->dev_addr[0] = (ravb_read(ndev, MAHR) >> 24);
117 ndev->dev_addr[1] = (ravb_read(ndev, MAHR) >> 16) & 0xFF;
118 ndev->dev_addr[2] = (ravb_read(ndev, MAHR) >> 8) & 0xFF;
119 ndev->dev_addr[3] = (ravb_read(ndev, MAHR) >> 0) & 0xFF;
120 ndev->dev_addr[4] = (ravb_read(ndev, MALR) >> 8) & 0xFF;
121 ndev->dev_addr[5] = (ravb_read(ndev, MALR) >> 0) & 0xFF;
122 }
123}
124
125static void ravb_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set)
126{
127 struct ravb_private *priv = container_of(ctrl, struct ravb_private,
128 mdiobb);
129 u32 pir = ravb_read(priv->ndev, PIR);
130
131 if (set)
132 pir |= mask;
133 else
134 pir &= ~mask;
135 ravb_write(priv->ndev, pir, PIR);
136}
137
138/* MDC pin control */
139static void ravb_set_mdc(struct mdiobb_ctrl *ctrl, int level)
140{
141 ravb_mdio_ctrl(ctrl, PIR_MDC, level);
142}
143
144/* Data I/O pin control */
145static void ravb_set_mdio_dir(struct mdiobb_ctrl *ctrl, int output)
146{
147 ravb_mdio_ctrl(ctrl, PIR_MMD, output);
148}
149
150/* Set data bit */
151static void ravb_set_mdio_data(struct mdiobb_ctrl *ctrl, int value)
152{
153 ravb_mdio_ctrl(ctrl, PIR_MDO, value);
154}
155
156/* Get data bit */
157static int ravb_get_mdio_data(struct mdiobb_ctrl *ctrl)
158{
159 struct ravb_private *priv = container_of(ctrl, struct ravb_private,
160 mdiobb);
161
162 return (ravb_read(priv->ndev, PIR) & PIR_MDI) != 0;
163}
164
165/* MDIO bus control struct */
166static struct mdiobb_ops bb_ops = {
167 .owner = THIS_MODULE,
168 .set_mdc = ravb_set_mdc,
169 .set_mdio_dir = ravb_set_mdio_dir,
170 .set_mdio_data = ravb_set_mdio_data,
171 .get_mdio_data = ravb_get_mdio_data,
172};
173
174/* Free skb's and DMA buffers for Ethernet AVB */
175static void ravb_ring_free(struct net_device *ndev, int q)
176{
177 struct ravb_private *priv = netdev_priv(ndev);
178 int ring_size;
179 int i;
180
181 /* Free RX skb ringbuffer */
182 if (priv->rx_skb[q]) {
183 for (i = 0; i < priv->num_rx_ring[q]; i++)
184 dev_kfree_skb(priv->rx_skb[q][i]);
185 }
186 kfree(priv->rx_skb[q]);
187 priv->rx_skb[q] = NULL;
188
189 /* Free TX skb ringbuffer */
190 if (priv->tx_skb[q]) {
191 for (i = 0; i < priv->num_tx_ring[q]; i++)
192 dev_kfree_skb(priv->tx_skb[q][i]);
193 }
194 kfree(priv->tx_skb[q]);
195 priv->tx_skb[q] = NULL;
196
197 /* Free aligned TX buffers */
198 if (priv->tx_buffers[q]) {
199 for (i = 0; i < priv->num_tx_ring[q]; i++)
200 kfree(priv->tx_buffers[q][i]);
201 }
202 kfree(priv->tx_buffers[q]);
203 priv->tx_buffers[q] = NULL;
204
205 if (priv->rx_ring[q]) {
206 ring_size = sizeof(struct ravb_ex_rx_desc) *
207 (priv->num_rx_ring[q] + 1);
208 dma_free_coherent(NULL, ring_size, priv->rx_ring[q],
209 priv->rx_desc_dma[q]);
210 priv->rx_ring[q] = NULL;
211 }
212
213 if (priv->tx_ring[q]) {
214 ring_size = sizeof(struct ravb_tx_desc) *
215 (priv->num_tx_ring[q] + 1);
216 dma_free_coherent(NULL, ring_size, priv->tx_ring[q],
217 priv->tx_desc_dma[q]);
218 priv->tx_ring[q] = NULL;
219 }
220}
221
222/* Format skb and descriptor buffer for Ethernet AVB */
223static void ravb_ring_format(struct net_device *ndev, int q)
224{
225 struct ravb_private *priv = netdev_priv(ndev);
226 struct ravb_ex_rx_desc *rx_desc = NULL;
227 struct ravb_tx_desc *tx_desc = NULL;
228 struct ravb_desc *desc = NULL;
229 int rx_ring_size = sizeof(*rx_desc) * priv->num_rx_ring[q];
230 int tx_ring_size = sizeof(*tx_desc) * priv->num_tx_ring[q];
231 struct sk_buff *skb;
232 dma_addr_t dma_addr;
233 void *buffer;
234 int i;
235
236 priv->cur_rx[q] = 0;
237 priv->cur_tx[q] = 0;
238 priv->dirty_rx[q] = 0;
239 priv->dirty_tx[q] = 0;
240
241 memset(priv->rx_ring[q], 0, rx_ring_size);
242 /* Build RX ring buffer */
243 for (i = 0; i < priv->num_rx_ring[q]; i++) {
244 priv->rx_skb[q][i] = NULL;
245 skb = netdev_alloc_skb(ndev, PKT_BUF_SZ + RAVB_ALIGN - 1);
246 if (!skb)
247 break;
248 ravb_set_buffer_align(skb);
249 /* RX descriptor */
250 rx_desc = &priv->rx_ring[q][i];
251 /* The size of the buffer should be on 16-byte boundary. */
252 rx_desc->ds_cc = cpu_to_le16(ALIGN(PKT_BUF_SZ, 16));
253 dma_addr = dma_map_single(&ndev->dev, skb->data,
254 ALIGN(PKT_BUF_SZ, 16),
255 DMA_FROM_DEVICE);
256 if (dma_mapping_error(&ndev->dev, dma_addr)) {
257 dev_kfree_skb(skb);
258 break;
259 }
260 priv->rx_skb[q][i] = skb;
261 rx_desc->dptr = cpu_to_le32(dma_addr);
262 rx_desc->die_dt = DT_FEMPTY;
263 }
264 rx_desc = &priv->rx_ring[q][i];
265 rx_desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]);
266 rx_desc->die_dt = DT_LINKFIX; /* type */
267 priv->dirty_rx[q] = (u32)(i - priv->num_rx_ring[q]);
268
269 memset(priv->tx_ring[q], 0, tx_ring_size);
270 /* Build TX ring buffer */
271 for (i = 0; i < priv->num_tx_ring[q]; i++) {
272 priv->tx_skb[q][i] = NULL;
273 priv->tx_buffers[q][i] = NULL;
274 buffer = kmalloc(PKT_BUF_SZ + RAVB_ALIGN - 1, GFP_KERNEL);
275 if (!buffer)
276 break;
277 /* Aligned TX buffer */
278 priv->tx_buffers[q][i] = buffer;
279 tx_desc = &priv->tx_ring[q][i];
280 tx_desc->die_dt = DT_EEMPTY;
281 }
282 tx_desc = &priv->tx_ring[q][i];
283 tx_desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]);
284 tx_desc->die_dt = DT_LINKFIX; /* type */
285
286 /* RX descriptor base address for best effort */
287 desc = &priv->desc_bat[RX_QUEUE_OFFSET + q];
288 desc->die_dt = DT_LINKFIX; /* type */
289 desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]);
290
291 /* TX descriptor base address for best effort */
292 desc = &priv->desc_bat[q];
293 desc->die_dt = DT_LINKFIX; /* type */
294 desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]);
295}
296
297/* Init skb and descriptor buffer for Ethernet AVB */
298static int ravb_ring_init(struct net_device *ndev, int q)
299{
300 struct ravb_private *priv = netdev_priv(ndev);
301 int ring_size;
302
303 /* Allocate RX and TX skb rings */
304 priv->rx_skb[q] = kcalloc(priv->num_rx_ring[q],
305 sizeof(*priv->rx_skb[q]), GFP_KERNEL);
306 priv->tx_skb[q] = kcalloc(priv->num_tx_ring[q],
307 sizeof(*priv->tx_skb[q]), GFP_KERNEL);
308 if (!priv->rx_skb[q] || !priv->tx_skb[q])
309 goto error;
310
311 /* Allocate rings for the aligned buffers */
312 priv->tx_buffers[q] = kcalloc(priv->num_tx_ring[q],
313 sizeof(*priv->tx_buffers[q]), GFP_KERNEL);
314 if (!priv->tx_buffers[q])
315 goto error;
316
317 /* Allocate all RX descriptors. */
318 ring_size = sizeof(struct ravb_ex_rx_desc) * (priv->num_rx_ring[q] + 1);
319 priv->rx_ring[q] = dma_alloc_coherent(NULL, ring_size,
320 &priv->rx_desc_dma[q],
321 GFP_KERNEL);
322 if (!priv->rx_ring[q])
323 goto error;
324
325 priv->dirty_rx[q] = 0;
326
327 /* Allocate all TX descriptors. */
328 ring_size = sizeof(struct ravb_tx_desc) * (priv->num_tx_ring[q] + 1);
329 priv->tx_ring[q] = dma_alloc_coherent(NULL, ring_size,
330 &priv->tx_desc_dma[q],
331 GFP_KERNEL);
332 if (!priv->tx_ring[q])
333 goto error;
334
335 return 0;
336
337error:
338 ravb_ring_free(ndev, q);
339
340 return -ENOMEM;
341}
342
343/* E-MAC init function */
344static void ravb_emac_init(struct net_device *ndev)
345{
346 struct ravb_private *priv = netdev_priv(ndev);
347 u32 ecmr;
348
349 /* Receive frame limit set register */
350 ravb_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, RFLR);
351
352 /* PAUSE prohibition */
353 ecmr = ravb_read(ndev, ECMR);
354 ecmr &= ECMR_DM;
355 ecmr |= ECMR_ZPF | (priv->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE;
356 ravb_write(ndev, ecmr, ECMR);
357
358 ravb_set_rate(ndev);
359
360 /* Set MAC address */
361 ravb_write(ndev,
362 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
363 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
364 ravb_write(ndev,
365 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
366
367 ravb_write(ndev, 1, MPR);
368
369 /* E-MAC status register clear */
370 ravb_write(ndev, ECSR_ICD | ECSR_MPD, ECSR);
371
372 /* E-MAC interrupt enable register */
373 ravb_write(ndev, ECSIPR_ICDIP | ECSIPR_MPDIP | ECSIPR_LCHNGIP, ECSIPR);
374}
375
376/* Device init function for Ethernet AVB */
377static int ravb_dmac_init(struct net_device *ndev)
378{
379 int error;
380
381 /* Set CONFIG mode */
382 error = ravb_config(ndev);
383 if (error)
384 return error;
385
386 error = ravb_ring_init(ndev, RAVB_BE);
387 if (error)
388 return error;
389 error = ravb_ring_init(ndev, RAVB_NC);
390 if (error) {
391 ravb_ring_free(ndev, RAVB_BE);
392 return error;
393 }
394
395 /* Descriptor format */
396 ravb_ring_format(ndev, RAVB_BE);
397 ravb_ring_format(ndev, RAVB_NC);
398
399#if defined(__LITTLE_ENDIAN)
400 ravb_write(ndev, ravb_read(ndev, CCC) & ~CCC_BOC, CCC);
401#else
402 ravb_write(ndev, ravb_read(ndev, CCC) | CCC_BOC, CCC);
403#endif
404
405 /* Set AVB RX */
406 ravb_write(ndev, RCR_EFFS | RCR_ENCF | RCR_ETS0 | 0x18000000, RCR);
407
408 /* Set FIFO size */
409 ravb_write(ndev, TGC_TQP_AVBMODE1 | 0x00222200, TGC);
410
411 /* Timestamp enable */
412 ravb_write(ndev, TCCR_TFEN, TCCR);
413
414 /* Interrupt enable: */
415 /* Frame receive */
416 ravb_write(ndev, RIC0_FRE0 | RIC0_FRE1, RIC0);
417 /* Receive FIFO full warning */
418 ravb_write(ndev, RIC1_RFWE, RIC1);
419 /* Receive FIFO full error, descriptor empty */
420 ravb_write(ndev, RIC2_QFE0 | RIC2_QFE1 | RIC2_RFFE, RIC2);
421 /* Frame transmitted, timestamp FIFO updated */
422 ravb_write(ndev, TIC_FTE0 | TIC_FTE1 | TIC_TFUE, TIC);
423
424 /* Setting the control will start the AVB-DMAC process. */
425 ravb_write(ndev, (ravb_read(ndev, CCC) & ~CCC_OPC) | CCC_OPC_OPERATION,
426 CCC);
427
428 return 0;
429}
430
431/* Free TX skb function for AVB-IP */
432static int ravb_tx_free(struct net_device *ndev, int q)
433{
434 struct ravb_private *priv = netdev_priv(ndev);
435 struct net_device_stats *stats = &priv->stats[q];
436 struct ravb_tx_desc *desc;
437 int free_num = 0;
438 int entry = 0;
439 u32 size;
440
441 for (; priv->cur_tx[q] - priv->dirty_tx[q] > 0; priv->dirty_tx[q]++) {
442 entry = priv->dirty_tx[q] % priv->num_tx_ring[q];
443 desc = &priv->tx_ring[q][entry];
444 if (desc->die_dt != DT_FEMPTY)
445 break;
446 /* Descriptor type must be checked before all other reads */
447 dma_rmb();
448 size = le16_to_cpu(desc->ds_tagl) & TX_DS;
449 /* Free the original skb. */
450 if (priv->tx_skb[q][entry]) {
451 dma_unmap_single(&ndev->dev, le32_to_cpu(desc->dptr),
452 size, DMA_TO_DEVICE);
453 dev_kfree_skb_any(priv->tx_skb[q][entry]);
454 priv->tx_skb[q][entry] = NULL;
455 free_num++;
456 }
457 stats->tx_packets++;
458 stats->tx_bytes += size;
459 desc->die_dt = DT_EEMPTY;
460 }
461 return free_num;
462}
463
464static void ravb_get_tx_tstamp(struct net_device *ndev)
465{
466 struct ravb_private *priv = netdev_priv(ndev);
467 struct ravb_tstamp_skb *ts_skb, *ts_skb2;
468 struct skb_shared_hwtstamps shhwtstamps;
469 struct sk_buff *skb;
470 struct timespec64 ts;
471 u16 tag, tfa_tag;
472 int count;
473 u32 tfa2;
474
475 count = (ravb_read(ndev, TSR) & TSR_TFFL) >> 8;
476 while (count--) {
477 tfa2 = ravb_read(ndev, TFA2);
478 tfa_tag = (tfa2 & TFA2_TST) >> 16;
479 ts.tv_nsec = (u64)ravb_read(ndev, TFA0);
480 ts.tv_sec = ((u64)(tfa2 & TFA2_TSV) << 32) |
481 ravb_read(ndev, TFA1);
482 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
483 shhwtstamps.hwtstamp = timespec64_to_ktime(ts);
484 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list,
485 list) {
486 skb = ts_skb->skb;
487 tag = ts_skb->tag;
488 list_del(&ts_skb->list);
489 kfree(ts_skb);
490 if (tag == tfa_tag) {
491 skb_tstamp_tx(skb, &shhwtstamps);
492 break;
493 }
494 }
495 ravb_write(ndev, ravb_read(ndev, TCCR) | TCCR_TFR, TCCR);
496 }
497}
498
499/* Packet receive function for Ethernet AVB */
500static bool ravb_rx(struct net_device *ndev, int *quota, int q)
501{
502 struct ravb_private *priv = netdev_priv(ndev);
503 int entry = priv->cur_rx[q] % priv->num_rx_ring[q];
504 int boguscnt = (priv->dirty_rx[q] + priv->num_rx_ring[q]) -
505 priv->cur_rx[q];
506 struct net_device_stats *stats = &priv->stats[q];
507 struct ravb_ex_rx_desc *desc;
508 struct sk_buff *skb;
509 dma_addr_t dma_addr;
510 struct timespec64 ts;
511 u16 pkt_len = 0;
512 u8 desc_status;
513 int limit;
514
515 boguscnt = min(boguscnt, *quota);
516 limit = boguscnt;
517 desc = &priv->rx_ring[q][entry];
518 while (desc->die_dt != DT_FEMPTY) {
519 /* Descriptor type must be checked before all other reads */
520 dma_rmb();
521 desc_status = desc->msc;
522 pkt_len = le16_to_cpu(desc->ds_cc) & RX_DS;
523
524 if (--boguscnt < 0)
525 break;
526
527 if (desc_status & MSC_MC)
528 stats->multicast++;
529
530 if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF |
531 MSC_CEEF)) {
532 stats->rx_errors++;
533 if (desc_status & MSC_CRC)
534 stats->rx_crc_errors++;
535 if (desc_status & MSC_RFE)
536 stats->rx_frame_errors++;
537 if (desc_status & (MSC_RTLF | MSC_RTSF))
538 stats->rx_length_errors++;
539 if (desc_status & MSC_CEEF)
540 stats->rx_missed_errors++;
541 } else {
542 u32 get_ts = priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE;
543
544 skb = priv->rx_skb[q][entry];
545 priv->rx_skb[q][entry] = NULL;
e2370f07
SS		 546 dma_unmap_single(&ndev->dev, le32_to_cpu(desc->dptr),
547 ALIGN(PKT_BUF_SZ, 16),
548 DMA_FROM_DEVICE);
c156633f
SS		 549 get_ts &= (q == RAVB_NC) ?
550 RAVB_RXTSTAMP_TYPE_V2_L2_EVENT :
551 ~RAVB_RXTSTAMP_TYPE_V2_L2_EVENT;
552 if (get_ts) {
553 struct skb_shared_hwtstamps *shhwtstamps;
554
555 shhwtstamps = skb_hwtstamps(skb);
556 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
557 ts.tv_sec = ((u64) le16_to_cpu(desc->ts_sh) <<
558 32) | le32_to_cpu(desc->ts_sl);
559 ts.tv_nsec = le32_to_cpu(desc->ts_n);
560 shhwtstamps->hwtstamp = timespec64_to_ktime(ts);
561 }
562 skb_put(skb, pkt_len);
563 skb->protocol = eth_type_trans(skb, ndev);
564 napi_gro_receive(&priv->napi[q], skb);
565 stats->rx_packets++;
566 stats->rx_bytes += pkt_len;
567 }
568
569 entry = (++priv->cur_rx[q]) % priv->num_rx_ring[q];
570 desc = &priv->rx_ring[q][entry];
571 }
572
573 /* Refill the RX ring buffers. */
574 for (; priv->cur_rx[q] - priv->dirty_rx[q] > 0; priv->dirty_rx[q]++) {
575 entry = priv->dirty_rx[q] % priv->num_rx_ring[q];
576 desc = &priv->rx_ring[q][entry];
577 /* The size of the buffer should be on 16-byte boundary. */
578 desc->ds_cc = cpu_to_le16(ALIGN(PKT_BUF_SZ, 16));
579
580 if (!priv->rx_skb[q][entry]) {
581 skb = netdev_alloc_skb(ndev,
582 PKT_BUF_SZ + RAVB_ALIGN - 1);
583 if (!skb)
584 break; /* Better luck next round. */
585 ravb_set_buffer_align(skb);
c156633f
SS		 586 dma_addr = dma_map_single(&ndev->dev, skb->data,
587 le16_to_cpu(desc->ds_cc),
588 DMA_FROM_DEVICE);
589 skb_checksum_none_assert(skb);
590 if (dma_mapping_error(&ndev->dev, dma_addr)) {
591 dev_kfree_skb_any(skb);
592 break;
593 }
594 desc->dptr = cpu_to_le32(dma_addr);
595 priv->rx_skb[q][entry] = skb;
596 }
597 /* Descriptor type must be set after all the above writes */
598 dma_wmb();
599 desc->die_dt = DT_FEMPTY;
600 }
601
602 *quota -= limit - (++boguscnt);
603
604 return boguscnt <= 0;
605}
606
607static void ravb_rcv_snd_disable(struct net_device *ndev)
608{
609 /* Disable TX and RX */
610 ravb_write(ndev, ravb_read(ndev, ECMR) & ~(ECMR_RE | ECMR_TE), ECMR);
611}
612
613static void ravb_rcv_snd_enable(struct net_device *ndev)
614{
615 /* Enable TX and RX */
616 ravb_write(ndev, ravb_read(ndev, ECMR) | ECMR_RE | ECMR_TE, ECMR);
617}
618
619/* function for waiting dma process finished */
620static int ravb_stop_dma(struct net_device *ndev)
621{
622 int error;
623
624 /* Wait for stopping the hardware TX process */
625 error = ravb_wait(ndev, TCCR,
626 TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 0);
627 if (error)
628 return error;
629
630 error = ravb_wait(ndev, CSR, CSR_TPO0 | CSR_TPO1 | CSR_TPO2 | CSR_TPO3,
631 0);
632 if (error)
633 return error;
634
635 /* Stop the E-MAC's RX/TX processes. */
636 ravb_rcv_snd_disable(ndev);
637
638 /* Wait for stopping the RX DMA process */
639 error = ravb_wait(ndev, CSR, CSR_RPO, 0);
640 if (error)
641 return error;
642
643 /* Stop AVB-DMAC process */
644 return ravb_config(ndev);
645}
646
647/* E-MAC interrupt handler */
648static void ravb_emac_interrupt(struct net_device *ndev)
649{
650 struct ravb_private *priv = netdev_priv(ndev);
651 u32 ecsr, psr;
652
653 ecsr = ravb_read(ndev, ECSR);
654 ravb_write(ndev, ecsr, ECSR); /* clear interrupt */
655 if (ecsr & ECSR_ICD)
656 ndev->stats.tx_carrier_errors++;
657 if (ecsr & ECSR_LCHNG) {
658 /* Link changed */
659 if (priv->no_avb_link)
660 return;
661 psr = ravb_read(ndev, PSR);
662 if (priv->avb_link_active_low)
663 psr ^= PSR_LMON;
664 if (!(psr & PSR_LMON)) {
665 /* DIsable RX and TX */
666 ravb_rcv_snd_disable(ndev);
667 } else {
668 /* Enable RX and TX */
669 ravb_rcv_snd_enable(ndev);
670 }
671 }
672}
673
674/* Error interrupt handler */
675static void ravb_error_interrupt(struct net_device *ndev)
676{
677 struct ravb_private *priv = netdev_priv(ndev);
678 u32 eis, ris2;
679
680 eis = ravb_read(ndev, EIS);
681 ravb_write(ndev, ~EIS_QFS, EIS);
682 if (eis & EIS_QFS) {
683 ris2 = ravb_read(ndev, RIS2);
684 ravb_write(ndev, ~(RIS2_QFF0 | RIS2_RFFF), RIS2);
685
686 /* Receive Descriptor Empty int */
687 if (ris2 & RIS2_QFF0)
688 priv->stats[RAVB_BE].rx_over_errors++;
689
690 /* Receive Descriptor Empty int */
691 if (ris2 & RIS2_QFF1)
692 priv->stats[RAVB_NC].rx_over_errors++;
693
694 /* Receive FIFO Overflow int */
695 if (ris2 & RIS2_RFFF)
696 priv->rx_fifo_errors++;
697 }
698}
699
700static irqreturn_t ravb_interrupt(int irq, void *dev_id)
701{
702 struct net_device *ndev = dev_id;
703 struct ravb_private *priv = netdev_priv(ndev);
704 irqreturn_t result = IRQ_NONE;
705 u32 iss;
706
707 spin_lock(&priv->lock);
708 /* Get interrupt status */
709 iss = ravb_read(ndev, ISS);
710
711 /* Received and transmitted interrupts */
712 if (iss & (ISS_FRS | ISS_FTS | ISS_TFUS)) {
713 u32 ris0 = ravb_read(ndev, RIS0);
714 u32 ric0 = ravb_read(ndev, RIC0);
715 u32 tis = ravb_read(ndev, TIS);
716 u32 tic = ravb_read(ndev, TIC);
717 int q;
718
719 /* Timestamp updated */
720 if (tis & TIS_TFUF) {
721 ravb_write(ndev, ~TIS_TFUF, TIS);
722 ravb_get_tx_tstamp(ndev);
723 result = IRQ_HANDLED;
724 }
725
726 /* Network control and best effort queue RX/TX */
727 for (q = RAVB_NC; q >= RAVB_BE; q--) {
728 if (((ris0 & ric0) & BIT(q)) ||
729 ((tis & tic) & BIT(q))) {
730 if (napi_schedule_prep(&priv->napi[q])) {
731 /* Mask RX and TX interrupts */
732 ravb_write(ndev, ric0 & ~BIT(q), RIC0);
733 ravb_write(ndev, tic & ~BIT(q), TIC);
734 __napi_schedule(&priv->napi[q]);
735 } else {
736 netdev_warn(ndev,
737 "ignoring interrupt, rx status 0x%08x, rx mask 0x%08x,\n",
738 ris0, ric0);
739 netdev_warn(ndev,
740 " tx status 0x%08x, tx mask 0x%08x.\n",
741 tis, tic);
742 }
743 result = IRQ_HANDLED;
744 }
745 }
746 }
747
748 /* E-MAC status summary */
749 if (iss & ISS_MS) {
750 ravb_emac_interrupt(ndev);
751 result = IRQ_HANDLED;
752 }
753
754 /* Error status summary */
755 if (iss & ISS_ES) {
756 ravb_error_interrupt(ndev);
757 result = IRQ_HANDLED;
758 }
759
a0d2f206
SS		 760 if (iss & ISS_CGIS)
761 result = ravb_ptp_interrupt(ndev);
762
c156633f
SS		 763 mmiowb();
764 spin_unlock(&priv->lock);
765 return result;
766}
767
768static int ravb_poll(struct napi_struct *napi, int budget)
769{
770 struct net_device *ndev = napi->dev;
771 struct ravb_private *priv = netdev_priv(ndev);
772 unsigned long flags;
773 int q = napi - priv->napi;
774 int mask = BIT(q);
775 int quota = budget;
776 u32 ris0, tis;
777
778 for (;;) {
779 tis = ravb_read(ndev, TIS);
780 ris0 = ravb_read(ndev, RIS0);
781 if (!((ris0 & mask) || (tis & mask)))
782 break;
783
784 /* Processing RX Descriptor Ring */
785 if (ris0 & mask) {
786 /* Clear RX interrupt */
787 ravb_write(ndev, ~mask, RIS0);
788 if (ravb_rx(ndev, &quota, q))
789 goto out;
790 }
791 /* Processing TX Descriptor Ring */
792 if (tis & mask) {
793 spin_lock_irqsave(&priv->lock, flags);
794 /* Clear TX interrupt */
795 ravb_write(ndev, ~mask, TIS);
796 ravb_tx_free(ndev, q);
797 netif_wake_subqueue(ndev, q);
798 mmiowb();
799 spin_unlock_irqrestore(&priv->lock, flags);
800 }
801 }
802
803 napi_complete(napi);
804
805 /* Re-enable RX/TX interrupts */
806 spin_lock_irqsave(&priv->lock, flags);
807 ravb_write(ndev, ravb_read(ndev, RIC0) | mask, RIC0);
808 ravb_write(ndev, ravb_read(ndev, TIC) | mask, TIC);
809 mmiowb();
810 spin_unlock_irqrestore(&priv->lock, flags);
811
812 /* Receive error message handling */
813 priv->rx_over_errors = priv->stats[RAVB_BE].rx_over_errors;
814 priv->rx_over_errors += priv->stats[RAVB_NC].rx_over_errors;
815 if (priv->rx_over_errors != ndev->stats.rx_over_errors) {
816 ndev->stats.rx_over_errors = priv->rx_over_errors;
817 netif_err(priv, rx_err, ndev, "Receive Descriptor Empty\n");
818 }
819 if (priv->rx_fifo_errors != ndev->stats.rx_fifo_errors) {
820 ndev->stats.rx_fifo_errors = priv->rx_fifo_errors;
821 netif_err(priv, rx_err, ndev, "Receive FIFO Overflow\n");
822 }
823out:
824 return budget - quota;
825}
826
827/* PHY state control function */
828static void ravb_adjust_link(struct net_device *ndev)
829{
830 struct ravb_private *priv = netdev_priv(ndev);
831 struct phy_device *phydev = priv->phydev;
832 bool new_state = false;
833
834 if (phydev->link) {
835 if (phydev->duplex != priv->duplex) {
836 new_state = true;
837 priv->duplex = phydev->duplex;
838 ravb_set_duplex(ndev);
839 }
840
841 if (phydev->speed != priv->speed) {
842 new_state = true;
843 priv->speed = phydev->speed;
844 ravb_set_rate(ndev);
845 }
846 if (!priv->link) {
847 ravb_write(ndev, ravb_read(ndev, ECMR) & ~ECMR_TXF,
848 ECMR);
849 new_state = true;
850 priv->link = phydev->link;
851 if (priv->no_avb_link)
852 ravb_rcv_snd_enable(ndev);
853 }
854 } else if (priv->link) {
855 new_state = true;
856 priv->link = 0;
857 priv->speed = 0;
858 priv->duplex = -1;
859 if (priv->no_avb_link)
860 ravb_rcv_snd_disable(ndev);
861 }
862
863 if (new_state && netif_msg_link(priv))
864 phy_print_status(phydev);
865}
866
867/* PHY init function */
868static int ravb_phy_init(struct net_device *ndev)
869{
870 struct device_node *np = ndev->dev.parent->of_node;
871 struct ravb_private *priv = netdev_priv(ndev);
872 struct phy_device *phydev;
873 struct device_node *pn;
874
875 priv->link = 0;
876 priv->speed = 0;
877 priv->duplex = -1;
878
879 /* Try connecting to PHY */
880 pn = of_parse_phandle(np, "phy-handle", 0);
881 phydev = of_phy_connect(ndev, pn, ravb_adjust_link, 0,
882 priv->phy_interface);
883 if (!phydev) {
884 netdev_err(ndev, "failed to connect PHY\n");
885 return -ENOENT;
886 }
887
888 netdev_info(ndev, "attached PHY %d (IRQ %d) to driver %s\n",
889 phydev->addr, phydev->irq, phydev->drv->name);
890
891 priv->phydev = phydev;
892
893 return 0;
894}
895
896/* PHY control start function */
897static int ravb_phy_start(struct net_device *ndev)
898{
899 struct ravb_private *priv = netdev_priv(ndev);
900 int error;
901
902 error = ravb_phy_init(ndev);
903 if (error)
904 return error;
905
906 phy_start(priv->phydev);
907
908 return 0;
909}
910
911static int ravb_get_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
912{
913 struct ravb_private *priv = netdev_priv(ndev);
914 int error = -ENODEV;
915 unsigned long flags;
916
917 if (priv->phydev) {
918 spin_lock_irqsave(&priv->lock, flags);
919 error = phy_ethtool_gset(priv->phydev, ecmd);
920 spin_unlock_irqrestore(&priv->lock, flags);
921 }
922
923 return error;
924}
925
926static int ravb_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
927{
928 struct ravb_private *priv = netdev_priv(ndev);
929 unsigned long flags;
930 int error;
931
932 if (!priv->phydev)
933 return -ENODEV;
934
935 spin_lock_irqsave(&priv->lock, flags);
936
937 /* Disable TX and RX */
938 ravb_rcv_snd_disable(ndev);
939
940 error = phy_ethtool_sset(priv->phydev, ecmd);
941 if (error)
942 goto error_exit;
943
944 if (ecmd->duplex == DUPLEX_FULL)
945 priv->duplex = 1;
946 else
947 priv->duplex = 0;
948
949 ravb_set_duplex(ndev);
950
951error_exit:
952 mdelay(1);
953
954 /* Enable TX and RX */
955 ravb_rcv_snd_enable(ndev);
956
957 mmiowb();
958 spin_unlock_irqrestore(&priv->lock, flags);
959
960 return error;
961}
962
963static int ravb_nway_reset(struct net_device *ndev)
964{
965 struct ravb_private *priv = netdev_priv(ndev);
966 int error = -ENODEV;
967 unsigned long flags;
968
969 if (priv->phydev) {
970 spin_lock_irqsave(&priv->lock, flags);
971 error = phy_start_aneg(priv->phydev);
972 spin_unlock_irqrestore(&priv->lock, flags);
973 }
974
975 return error;
976}
977
978static u32 ravb_get_msglevel(struct net_device *ndev)
979{
980 struct ravb_private *priv = netdev_priv(ndev);
981
982 return priv->msg_enable;
983}
984
985static void ravb_set_msglevel(struct net_device *ndev, u32 value)
986{
987 struct ravb_private *priv = netdev_priv(ndev);
988
989 priv->msg_enable = value;
990}
991
992static const char ravb_gstrings_stats[][ETH_GSTRING_LEN] = {
993 "rx_queue_0_current",
994 "tx_queue_0_current",
995 "rx_queue_0_dirty",
996 "tx_queue_0_dirty",
997 "rx_queue_0_packets",
998 "tx_queue_0_packets",
999 "rx_queue_0_bytes",
1000 "tx_queue_0_bytes",
1001 "rx_queue_0_mcast_packets",
1002 "rx_queue_0_errors",
1003 "rx_queue_0_crc_errors",
1004 "rx_queue_0_frame_errors",
1005 "rx_queue_0_length_errors",
1006 "rx_queue_0_missed_errors",
1007 "rx_queue_0_over_errors",
1008
1009 "rx_queue_1_current",
1010 "tx_queue_1_current",
1011 "rx_queue_1_dirty",
1012 "tx_queue_1_dirty",
1013 "rx_queue_1_packets",
1014 "tx_queue_1_packets",
1015 "rx_queue_1_bytes",
1016 "tx_queue_1_bytes",
1017 "rx_queue_1_mcast_packets",
1018 "rx_queue_1_errors",
1019 "rx_queue_1_crc_errors",
1020 "rx_queue_1_frame_errors_",
1021 "rx_queue_1_length_errors",
1022 "rx_queue_1_missed_errors",
1023 "rx_queue_1_over_errors",
1024};
1025
1026#define RAVB_STATS_LEN ARRAY_SIZE(ravb_gstrings_stats)
1027
1028static int ravb_get_sset_count(struct net_device *netdev, int sset)
1029{
1030 switch (sset) {
1031 case ETH_SS_STATS:
1032 return RAVB_STATS_LEN;
1033 default:
1034 return -EOPNOTSUPP;
1035 }
1036}
1037
1038static void ravb_get_ethtool_stats(struct net_device *ndev,
1039 struct ethtool_stats *stats, u64 *data)
1040{
1041 struct ravb_private *priv = netdev_priv(ndev);
1042 int i = 0;
1043 int q;
1044
1045 /* Device-specific stats */
1046 for (q = RAVB_BE; q < NUM_RX_QUEUE; q++) {
1047 struct net_device_stats *stats = &priv->stats[q];
1048
1049 data[i++] = priv->cur_rx[q];
1050 data[i++] = priv->cur_tx[q];
1051 data[i++] = priv->dirty_rx[q];
1052 data[i++] = priv->dirty_tx[q];
1053 data[i++] = stats->rx_packets;
1054 data[i++] = stats->tx_packets;
1055 data[i++] = stats->rx_bytes;
1056 data[i++] = stats->tx_bytes;
1057 data[i++] = stats->multicast;
1058 data[i++] = stats->rx_errors;
1059 data[i++] = stats->rx_crc_errors;
1060 data[i++] = stats->rx_frame_errors;
1061 data[i++] = stats->rx_length_errors;
1062 data[i++] = stats->rx_missed_errors;
1063 data[i++] = stats->rx_over_errors;
1064 }
1065}
1066
1067static void ravb_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1068{
1069 switch (stringset) {
1070 case ETH_SS_STATS:
1071 memcpy(data, *ravb_gstrings_stats, sizeof(ravb_gstrings_stats));
1072 break;
1073 }
1074}
1075
1076static void ravb_get_ringparam(struct net_device *ndev,
1077 struct ethtool_ringparam *ring)
1078{
1079 struct ravb_private *priv = netdev_priv(ndev);
1080
1081 ring->rx_max_pending = BE_RX_RING_MAX;
1082 ring->tx_max_pending = BE_TX_RING_MAX;
1083 ring->rx_pending = priv->num_rx_ring[RAVB_BE];
1084 ring->tx_pending = priv->num_tx_ring[RAVB_BE];
1085}
1086
1087static int ravb_set_ringparam(struct net_device *ndev,
1088 struct ethtool_ringparam *ring)
1089{
1090 struct ravb_private *priv = netdev_priv(ndev);
1091 int error;
1092
1093 if (ring->tx_pending > BE_TX_RING_MAX ||
1094 ring->rx_pending > BE_RX_RING_MAX ||
1095 ring->tx_pending < BE_TX_RING_MIN ||
1096 ring->rx_pending < BE_RX_RING_MIN)
1097 return -EINVAL;
1098 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
1099 return -EINVAL;
1100
1101 if (netif_running(ndev)) {
1102 netif_device_detach(ndev);
a0d2f206
SS		 1103 /* Stop PTP Clock driver */
1104 ravb_ptp_stop(ndev);
c156633f
SS		 1105 /* Wait for DMA stopping */
1106 error = ravb_stop_dma(ndev);
1107 if (error) {
1108 netdev_err(ndev,
1109 "cannot set ringparam! Any AVB processes are still running?\n");
1110 return error;
1111 }
1112 synchronize_irq(ndev->irq);
1113
1114 /* Free all the skb's in the RX queue and the DMA buffers. */
1115 ravb_ring_free(ndev, RAVB_BE);
1116 ravb_ring_free(ndev, RAVB_NC);
1117 }
1118
1119 /* Set new parameters */
1120 priv->num_rx_ring[RAVB_BE] = ring->rx_pending;
1121 priv->num_tx_ring[RAVB_BE] = ring->tx_pending;
1122
1123 if (netif_running(ndev)) {
1124 error = ravb_dmac_init(ndev);
1125 if (error) {
1126 netdev_err(ndev,
1127 "%s: ravb_dmac_init() failed, error %d\n",
1128 __func__, error);
1129 return error;
1130 }
1131
1132 ravb_emac_init(ndev);
1133
a0d2f206
SS		 1134 /* Initialise PTP Clock driver */
1135 ravb_ptp_init(ndev, priv->pdev);
1136
c156633f
SS		 1137 netif_device_attach(ndev);
1138 }
1139
1140 return 0;
1141}
1142
1143static int ravb_get_ts_info(struct net_device *ndev,
1144 struct ethtool_ts_info *info)
1145{
a0d2f206
SS		 1146 struct ravb_private *priv = netdev_priv(ndev);
1147
c156633f
SS		 1148 info->so_timestamping =
1149 SOF_TIMESTAMPING_TX_SOFTWARE |
1150 SOF_TIMESTAMPING_RX_SOFTWARE |
1151 SOF_TIMESTAMPING_SOFTWARE |
1152 SOF_TIMESTAMPING_TX_HARDWARE |
1153 SOF_TIMESTAMPING_RX_HARDWARE |
1154 SOF_TIMESTAMPING_RAW_HARDWARE;
1155 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON);
1156 info->rx_filters =
1157 (1 << HWTSTAMP_FILTER_NONE) |
1158 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
1159 (1 << HWTSTAMP_FILTER_ALL);
a0d2f206 1160 info->phc_index = ptp_clock_index(priv->ptp.clock);
c156633f
SS		 1161
1162 return 0;
1163}
1164
1165static const struct ethtool_ops ravb_ethtool_ops = {
1166 .get_settings = ravb_get_settings,
1167 .set_settings = ravb_set_settings,
1168 .nway_reset = ravb_nway_reset,
1169 .get_msglevel = ravb_get_msglevel,
1170 .set_msglevel = ravb_set_msglevel,
1171 .get_link = ethtool_op_get_link,
1172 .get_strings = ravb_get_strings,
1173 .get_ethtool_stats = ravb_get_ethtool_stats,
1174 .get_sset_count = ravb_get_sset_count,
1175 .get_ringparam = ravb_get_ringparam,
1176 .set_ringparam = ravb_set_ringparam,
1177 .get_ts_info = ravb_get_ts_info,
1178};
1179
1180/* Network device open function for Ethernet AVB */
1181static int ravb_open(struct net_device *ndev)
1182{
1183 struct ravb_private *priv = netdev_priv(ndev);
1184 int error;
1185
1186 napi_enable(&priv->napi[RAVB_BE]);
1187 napi_enable(&priv->napi[RAVB_NC]);
1188
1189 error = request_irq(ndev->irq, ravb_interrupt, IRQF_SHARED, ndev->name,
1190 ndev);
1191 if (error) {
1192 netdev_err(ndev, "cannot request IRQ\n");
1193 goto out_napi_off;
1194 }
1195
1196 /* Device init */
1197 error = ravb_dmac_init(ndev);
1198 if (error)
1199 goto out_free_irq;
1200 ravb_emac_init(ndev);
1201
a0d2f206
SS		 1202 /* Initialise PTP Clock driver */
1203 ravb_ptp_init(ndev, priv->pdev);
1204
c156633f
SS		 1205 netif_tx_start_all_queues(ndev);
1206
1207 /* PHY control start */
1208 error = ravb_phy_start(ndev);
1209 if (error)
a0d2f206 1210 goto out_ptp_stop;
c156633f
SS		 1211
1212 return 0;
1213
a0d2f206
SS		 1214out_ptp_stop:
1215 /* Stop PTP Clock driver */
1216 ravb_ptp_stop(ndev);
c156633f
SS		 1217out_free_irq:
1218 free_irq(ndev->irq, ndev);
1219out_napi_off:
1220 napi_disable(&priv->napi[RAVB_NC]);
1221 napi_disable(&priv->napi[RAVB_BE]);
1222 return error;
1223}
1224
1225/* Timeout function for Ethernet AVB */
1226static void ravb_tx_timeout(struct net_device *ndev)
1227{
1228 struct ravb_private *priv = netdev_priv(ndev);
1229
1230 netif_err(priv, tx_err, ndev,
1231 "transmit timed out, status %08x, resetting...\n",
1232 ravb_read(ndev, ISS));
1233
1234 /* tx_errors count up */
1235 ndev->stats.tx_errors++;
1236
1237 schedule_work(&priv->work);
1238}
1239
1240static void ravb_tx_timeout_work(struct work_struct *work)
1241{
1242 struct ravb_private *priv = container_of(work, struct ravb_private,
1243 work);
1244 struct net_device *ndev = priv->ndev;
1245
1246 netif_tx_stop_all_queues(ndev);
1247
a0d2f206
SS		 1248 /* Stop PTP Clock driver */
1249 ravb_ptp_stop(ndev);
1250
c156633f
SS		 1251 /* Wait for DMA stopping */
1252 ravb_stop_dma(ndev);
1253
1254 ravb_ring_free(ndev, RAVB_BE);
1255 ravb_ring_free(ndev, RAVB_NC);
1256
1257 /* Device init */
1258 ravb_dmac_init(ndev);
1259 ravb_emac_init(ndev);
1260
a0d2f206
SS		 1261 /* Initialise PTP Clock driver */
1262 ravb_ptp_init(ndev, priv->pdev);
1263
c156633f
SS		 1264 netif_tx_start_all_queues(ndev);
1265}
1266
1267/* Packet transmit function for Ethernet AVB */
1268static netdev_tx_t ravb_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1269{
1270 struct ravb_private *priv = netdev_priv(ndev);
1271 struct ravb_tstamp_skb *ts_skb = NULL;
1272 u16 q = skb_get_queue_mapping(skb);
1273 struct ravb_tx_desc *desc;
1274 unsigned long flags;
1275 u32 dma_addr;
1276 void *buffer;
1277 u32 entry;
c156633f
SS		 1278
1279 spin_lock_irqsave(&priv->lock, flags);
1280 if (priv->cur_tx[q] - priv->dirty_tx[q] >= priv->num_tx_ring[q]) {
1281 netif_err(priv, tx_queued, ndev,
1282 "still transmitting with the full ring!\n");
1283 netif_stop_subqueue(ndev, q);
1284 spin_unlock_irqrestore(&priv->lock, flags);
1285 return NETDEV_TX_BUSY;
1286 }
1287 entry = priv->cur_tx[q] % priv->num_tx_ring[q];
1288 priv->tx_skb[q][entry] = skb;
1289
1290 if (skb_put_padto(skb, ETH_ZLEN))
1291 goto drop;
1292
1293 buffer = PTR_ALIGN(priv->tx_buffers[q][entry], RAVB_ALIGN);
1294 memcpy(buffer, skb->data, skb->len);
1295 desc = &priv->tx_ring[q][entry];
1296 desc->ds_tagl = cpu_to_le16(skb->len);
1297 dma_addr = dma_map_single(&ndev->dev, buffer, skb->len, DMA_TO_DEVICE);
1298 if (dma_mapping_error(&ndev->dev, dma_addr))
1299 goto drop;
1300 desc->dptr = cpu_to_le32(dma_addr);
1301
1302 /* TX timestamp required */
1303 if (q == RAVB_NC) {
1304 ts_skb = kmalloc(sizeof(*ts_skb), GFP_ATOMIC);
1305 if (!ts_skb) {
1306 dma_unmap_single(&ndev->dev, dma_addr, skb->len,
1307 DMA_TO_DEVICE);
1308 goto drop;
1309 }
1310 ts_skb->skb = skb;
1311 ts_skb->tag = priv->ts_skb_tag++;
1312 priv->ts_skb_tag &= 0x3ff;
1313 list_add_tail(&ts_skb->list, &priv->ts_skb_list);
1314
1315 /* TAG and timestamp required flag */
1316 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1317 skb_tx_timestamp(skb);
1318 desc->tagh_tsr = (ts_skb->tag >> 4) | TX_TSR;
1319 desc->ds_tagl |= le16_to_cpu(ts_skb->tag << 12);
1320 }
1321
1322 /* Descriptor type must be set after all the above writes */
1323 dma_wmb();
1324 desc->die_dt = DT_FSINGLE;
1325
06613e38 1326 ravb_write(ndev, ravb_read(ndev, TCCR) | (TCCR_TSRQ0 << q), TCCR);
c156633f
SS		 1327
1328 priv->cur_tx[q]++;
1329 if (priv->cur_tx[q] - priv->dirty_tx[q] >= priv->num_tx_ring[q] &&
1330 !ravb_tx_free(ndev, q))
1331 netif_stop_subqueue(ndev, q);
1332
1333exit:
1334 mmiowb();
1335 spin_unlock_irqrestore(&priv->lock, flags);
1336 return NETDEV_TX_OK;
1337
1338drop:
1339 dev_kfree_skb_any(skb);
1340 priv->tx_skb[q][entry] = NULL;
1341 goto exit;
1342}
1343
1344static u16 ravb_select_queue(struct net_device *ndev, struct sk_buff *skb,
1345 void *accel_priv, select_queue_fallback_t fallback)
1346{
1347 /* If skb needs TX timestamp, it is handled in network control queue */
1348 return (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) ? RAVB_NC :
1349 RAVB_BE;
1350
1351}
1352
1353static struct net_device_stats *ravb_get_stats(struct net_device *ndev)
1354{
1355 struct ravb_private *priv = netdev_priv(ndev);
1356 struct net_device_stats *nstats, *stats0, *stats1;
1357
1358 nstats = &ndev->stats;
1359 stats0 = &priv->stats[RAVB_BE];
1360 stats1 = &priv->stats[RAVB_NC];
1361
1362 nstats->tx_dropped += ravb_read(ndev, TROCR);
1363 ravb_write(ndev, 0, TROCR); /* (write clear) */
1364 nstats->collisions += ravb_read(ndev, CDCR);
1365 ravb_write(ndev, 0, CDCR); /* (write clear) */
1366 nstats->tx_carrier_errors += ravb_read(ndev, LCCR);
1367 ravb_write(ndev, 0, LCCR); /* (write clear) */
1368
1369 nstats->tx_carrier_errors += ravb_read(ndev, CERCR);
1370 ravb_write(ndev, 0, CERCR); /* (write clear) */
1371 nstats->tx_carrier_errors += ravb_read(ndev, CEECR);
1372 ravb_write(ndev, 0, CEECR); /* (write clear) */
1373
1374 nstats->rx_packets = stats0->rx_packets + stats1->rx_packets;
1375 nstats->tx_packets = stats0->tx_packets + stats1->tx_packets;
1376 nstats->rx_bytes = stats0->rx_bytes + stats1->rx_bytes;
1377 nstats->tx_bytes = stats0->tx_bytes + stats1->tx_bytes;
1378 nstats->multicast = stats0->multicast + stats1->multicast;
1379 nstats->rx_errors = stats0->rx_errors + stats1->rx_errors;
1380 nstats->rx_crc_errors = stats0->rx_crc_errors + stats1->rx_crc_errors;
1381 nstats->rx_frame_errors =
1382 stats0->rx_frame_errors + stats1->rx_frame_errors;
1383 nstats->rx_length_errors =
1384 stats0->rx_length_errors + stats1->rx_length_errors;
1385 nstats->rx_missed_errors =
1386 stats0->rx_missed_errors + stats1->rx_missed_errors;
1387 nstats->rx_over_errors =
1388 stats0->rx_over_errors + stats1->rx_over_errors;
1389
1390 return nstats;
1391}
1392
1393/* Update promiscuous bit */
1394static void ravb_set_rx_mode(struct net_device *ndev)
1395{
1396 struct ravb_private *priv = netdev_priv(ndev);
1397 unsigned long flags;
1398 u32 ecmr;
1399
1400 spin_lock_irqsave(&priv->lock, flags);
1401 ecmr = ravb_read(ndev, ECMR);
1402 if (ndev->flags & IFF_PROMISC)
1403 ecmr |= ECMR_PRM;
1404 else
1405 ecmr &= ~ECMR_PRM;
1406 ravb_write(ndev, ecmr, ECMR);
1407 mmiowb();
1408 spin_unlock_irqrestore(&priv->lock, flags);
1409}
1410
1411/* Device close function for Ethernet AVB */
1412static int ravb_close(struct net_device *ndev)
1413{
1414 struct ravb_private *priv = netdev_priv(ndev);
1415 struct ravb_tstamp_skb *ts_skb, *ts_skb2;
1416
1417 netif_tx_stop_all_queues(ndev);
1418
1419 /* Disable interrupts by clearing the interrupt masks. */
1420 ravb_write(ndev, 0, RIC0);
1421 ravb_write(ndev, 0, RIC1);
1422 ravb_write(ndev, 0, RIC2);
1423 ravb_write(ndev, 0, TIC);
1424
a0d2f206
SS		 1425 /* Stop PTP Clock driver */
1426 ravb_ptp_stop(ndev);
1427
c156633f
SS		 1428 /* Set the config mode to stop the AVB-DMAC's processes */
1429 if (ravb_stop_dma(ndev) < 0)
1430 netdev_err(ndev,
1431 "device will be stopped after h/w processes are done.\n");
1432
1433 /* Clear the timestamp list */
1434 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, list) {
1435 list_del(&ts_skb->list);
1436 kfree(ts_skb);
1437 }
1438
1439 /* PHY disconnect */
1440 if (priv->phydev) {
1441 phy_stop(priv->phydev);
1442 phy_disconnect(priv->phydev);
1443 priv->phydev = NULL;
1444 }
1445
1446 free_irq(ndev->irq, ndev);
1447
1448 napi_disable(&priv->napi[RAVB_NC]);
1449 napi_disable(&priv->napi[RAVB_BE]);
1450
1451 /* Free all the skb's in the RX queue and the DMA buffers. */
1452 ravb_ring_free(ndev, RAVB_BE);
1453 ravb_ring_free(ndev, RAVB_NC);
1454
1455 return 0;
1456}
1457
1458static int ravb_hwtstamp_get(struct net_device *ndev, struct ifreq *req)
1459{
1460 struct ravb_private *priv = netdev_priv(ndev);
1461 struct hwtstamp_config config;
1462
1463 config.flags = 0;
1464 config.tx_type = priv->tstamp_tx_ctrl ? HWTSTAMP_TX_ON :
1465 HWTSTAMP_TX_OFF;
1466 if (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE_V2_L2_EVENT)
1467 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
1468 else if (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE_ALL)
1469 config.rx_filter = HWTSTAMP_FILTER_ALL;
1470 else
1471 config.rx_filter = HWTSTAMP_FILTER_NONE;
1472
1473 return copy_to_user(req->ifr_data, &config, sizeof(config)) ?
1474 -EFAULT : 0;
1475}
1476
1477/* Control hardware time stamping */
1478static int ravb_hwtstamp_set(struct net_device *ndev, struct ifreq *req)
1479{
1480 struct ravb_private *priv = netdev_priv(ndev);
1481 struct hwtstamp_config config;
1482 u32 tstamp_rx_ctrl = RAVB_RXTSTAMP_ENABLED;
1483 u32 tstamp_tx_ctrl;
1484
1485 if (copy_from_user(&config, req->ifr_data, sizeof(config)))
1486 return -EFAULT;
1487
1488 /* Reserved for future extensions */
1489 if (config.flags)
1490 return -EINVAL;
1491
1492 switch (config.tx_type) {
1493 case HWTSTAMP_TX_OFF:
1494 tstamp_tx_ctrl = 0;
1495 break;
1496 case HWTSTAMP_TX_ON:
1497 tstamp_tx_ctrl = RAVB_TXTSTAMP_ENABLED;
1498 break;
1499 default:
1500 return -ERANGE;
1501 }
1502
1503 switch (config.rx_filter) {
1504 case HWTSTAMP_FILTER_NONE:
1505 tstamp_rx_ctrl = 0;
1506 break;
1507 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1508 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_V2_L2_EVENT;
1509 break;
1510 default:
1511 config.rx_filter = HWTSTAMP_FILTER_ALL;
1512 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_ALL;
1513 }
1514
1515 priv->tstamp_tx_ctrl = tstamp_tx_ctrl;
1516 priv->tstamp_rx_ctrl = tstamp_rx_ctrl;
1517
1518 return copy_to_user(req->ifr_data, &config, sizeof(config)) ?
1519 -EFAULT : 0;
1520}
1521
1522/* ioctl to device function */
1523static int ravb_do_ioctl(struct net_device *ndev, struct ifreq *req, int cmd)
1524{
1525 struct ravb_private *priv = netdev_priv(ndev);
1526 struct phy_device *phydev = priv->phydev;
1527
1528 if (!netif_running(ndev))
1529 return -EINVAL;
1530
1531 if (!phydev)
1532 return -ENODEV;
1533
1534 switch (cmd) {
1535 case SIOCGHWTSTAMP:
1536 return ravb_hwtstamp_get(ndev, req);
1537 case SIOCSHWTSTAMP:
1538 return ravb_hwtstamp_set(ndev, req);
1539 }
1540
1541 return phy_mii_ioctl(phydev, req, cmd);
1542}
1543
1544static const struct net_device_ops ravb_netdev_ops = {
1545 .ndo_open = ravb_open,
1546 .ndo_stop = ravb_close,
1547 .ndo_start_xmit = ravb_start_xmit,
1548 .ndo_select_queue = ravb_select_queue,
1549 .ndo_get_stats = ravb_get_stats,
1550 .ndo_set_rx_mode = ravb_set_rx_mode,
1551 .ndo_tx_timeout = ravb_tx_timeout,
1552 .ndo_do_ioctl = ravb_do_ioctl,
1553 .ndo_validate_addr = eth_validate_addr,
1554 .ndo_set_mac_address = eth_mac_addr,
1555 .ndo_change_mtu = eth_change_mtu,
1556};
1557
1558/* MDIO bus init function */
1559static int ravb_mdio_init(struct ravb_private *priv)
1560{
1561 struct platform_device *pdev = priv->pdev;
1562 struct device *dev = &pdev->dev;
1563 int error;
1564
1565 /* Bitbang init */
1566 priv->mdiobb.ops = &bb_ops;
1567
1568 /* MII controller setting */
1569 priv->mii_bus = alloc_mdio_bitbang(&priv->mdiobb);
1570 if (!priv->mii_bus)
1571 return -ENOMEM;
1572
1573 /* Hook up MII support for ethtool */
1574 priv->mii_bus->name = "ravb_mii";
1575 priv->mii_bus->parent = dev;
1576 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
1577 pdev->name, pdev->id);
1578
1579 /* Register MDIO bus */
1580 error = of_mdiobus_register(priv->mii_bus, dev->of_node);
1581 if (error)
1582 goto out_free_bus;
1583
1584 return 0;
1585
1586out_free_bus:
1587 free_mdio_bitbang(priv->mii_bus);
1588 return error;
1589}
1590
1591/* MDIO bus release function */
1592static int ravb_mdio_release(struct ravb_private *priv)
1593{
1594 /* Unregister mdio bus */
1595 mdiobus_unregister(priv->mii_bus);
1596
1597 /* Free bitbang info */
1598 free_mdio_bitbang(priv->mii_bus);
1599
1600 return 0;
1601}
1602
1603static int ravb_probe(struct platform_device *pdev)
1604{
1605 struct device_node *np = pdev->dev.of_node;
1606 struct ravb_private *priv;
1607 struct net_device *ndev;
1608 int error, irq, q;
1609 struct resource *res;
1610
1611 if (!np) {
1612 dev_err(&pdev->dev,
1613 "this driver is required to be instantiated from device tree\n");
1614 return -EINVAL;
1615 }
1616
1617 /* Get base address */
1618 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1619 if (!res) {
1620 dev_err(&pdev->dev, "invalid resource\n");
1621 return -EINVAL;
1622 }
1623
1624 ndev = alloc_etherdev_mqs(sizeof(struct ravb_private),
1625 NUM_TX_QUEUE, NUM_RX_QUEUE);
1626 if (!ndev)
1627 return -ENOMEM;
1628
1629 pm_runtime_enable(&pdev->dev);
1630 pm_runtime_get_sync(&pdev->dev);
1631
1632 /* The Ether-specific entries in the device structure. */
1633 ndev->base_addr = res->start;
1634 ndev->dma = -1;
1635 irq = platform_get_irq(pdev, 0);
1636 if (irq < 0) {
1637 error = -ENODEV;
1638 goto out_release;
1639 }
1640 ndev->irq = irq;
1641
1642 SET_NETDEV_DEV(ndev, &pdev->dev);
1643
1644 priv = netdev_priv(ndev);
1645 priv->ndev = ndev;
1646 priv->pdev = pdev;
1647 priv->num_tx_ring[RAVB_BE] = BE_TX_RING_SIZE;
1648 priv->num_rx_ring[RAVB_BE] = BE_RX_RING_SIZE;
1649 priv->num_tx_ring[RAVB_NC] = NC_TX_RING_SIZE;
1650 priv->num_rx_ring[RAVB_NC] = NC_RX_RING_SIZE;
1651 priv->addr = devm_ioremap_resource(&pdev->dev, res);
1652 if (IS_ERR(priv->addr)) {
1653 error = PTR_ERR(priv->addr);
1654 goto out_release;
1655 }
1656
1657 spin_lock_init(&priv->lock);
1658 INIT_WORK(&priv->work, ravb_tx_timeout_work);
1659
1660 priv->phy_interface = of_get_phy_mode(np);
1661
1662 priv->no_avb_link = of_property_read_bool(np, "renesas,no-ether-link");
1663 priv->avb_link_active_low =
1664 of_property_read_bool(np, "renesas,ether-link-active-low");
1665
1666 /* Set function */
1667 ndev->netdev_ops = &ravb_netdev_ops;
1668 ndev->ethtool_ops = &ravb_ethtool_ops;
1669
1670 /* Set AVB config mode */
1671 ravb_write(ndev, (ravb_read(ndev, CCC) & ~CCC_OPC) | CCC_OPC_CONFIG,
1672 CCC);
1673
1674 /* Set CSEL value */
1675 ravb_write(ndev, (ravb_read(ndev, CCC) & ~CCC_CSEL) | CCC_CSEL_HPB,
1676 CCC);
1677
1678 /* Set GTI value */
1679 ravb_write(ndev, ((1000 << 20) / 130) & GTI_TIV, GTI);
1680
1681 /* Request GTI loading */
1682 ravb_write(ndev, ravb_read(ndev, GCCR) | GCCR_LTI, GCCR);
1683
1684 /* Allocate descriptor base address table */
1685 priv->desc_bat_size = sizeof(struct ravb_desc) * DBAT_ENTRY_NUM;
1686 priv->desc_bat = dma_alloc_coherent(NULL, priv->desc_bat_size,
1687 &priv->desc_bat_dma, GFP_KERNEL);
1688 if (!priv->desc_bat) {
1689 dev_err(&ndev->dev,
1690 "Cannot allocate desc base address table (size %d bytes)\n",
1691 priv->desc_bat_size);
1692 error = -ENOMEM;
1693 goto out_release;
1694 }
1695 for (q = RAVB_BE; q < DBAT_ENTRY_NUM; q++)
1696 priv->desc_bat[q].die_dt = DT_EOS;
1697 ravb_write(ndev, priv->desc_bat_dma, DBAT);
1698
1699 /* Initialise HW timestamp list */
1700 INIT_LIST_HEAD(&priv->ts_skb_list);
1701
1702 /* Debug message level */
1703 priv->msg_enable = RAVB_DEF_MSG_ENABLE;
1704
1705 /* Read and set MAC address */
1706 ravb_read_mac_address(ndev, of_get_mac_address(np));
1707 if (!is_valid_ether_addr(ndev->dev_addr)) {
1708 dev_warn(&pdev->dev,
1709 "no valid MAC address supplied, using a random one\n");
1710 eth_hw_addr_random(ndev);
1711 }
1712
1713 /* MDIO bus init */
1714 error = ravb_mdio_init(priv);
1715 if (error) {
1716 dev_err(&ndev->dev, "failed to initialize MDIO\n");
1717 goto out_dma_free;
1718 }
1719
1720 netif_napi_add(ndev, &priv->napi[RAVB_BE], ravb_poll, 64);
1721 netif_napi_add(ndev, &priv->napi[RAVB_NC], ravb_poll, 64);
1722
1723 /* Network device register */
1724 error = register_netdev(ndev);
1725 if (error)
1726 goto out_napi_del;
1727
1728 /* Print device information */
1729 netdev_info(ndev, "Base address at %#x, %pM, IRQ %d.\n",
1730 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
1731
1732 platform_set_drvdata(pdev, ndev);
1733
1734 return 0;
1735
1736out_napi_del:
1737 netif_napi_del(&priv->napi[RAVB_NC]);
1738 netif_napi_del(&priv->napi[RAVB_BE]);
1739 ravb_mdio_release(priv);
1740out_dma_free:
1741 dma_free_coherent(NULL, priv->desc_bat_size, priv->desc_bat,
1742 priv->desc_bat_dma);
1743out_release:
1744 if (ndev)
1745 free_netdev(ndev);
1746
1747 pm_runtime_put(&pdev->dev);
1748 pm_runtime_disable(&pdev->dev);
1749 return error;
1750}
1751
1752static int ravb_remove(struct platform_device *pdev)
1753{
1754 struct net_device *ndev = platform_get_drvdata(pdev);
1755 struct ravb_private *priv = netdev_priv(ndev);
1756
1757 dma_free_coherent(NULL, priv->desc_bat_size, priv->desc_bat,
1758 priv->desc_bat_dma);
1759 /* Set reset mode */
1760 ravb_write(ndev, CCC_OPC_RESET, CCC);
1761 pm_runtime_put_sync(&pdev->dev);
1762 unregister_netdev(ndev);
1763 netif_napi_del(&priv->napi[RAVB_NC]);
1764 netif_napi_del(&priv->napi[RAVB_BE]);
1765 ravb_mdio_release(priv);
1766 pm_runtime_disable(&pdev->dev);
1767 free_netdev(ndev);
1768 platform_set_drvdata(pdev, NULL);
1769
1770 return 0;
1771}
1772
1773#ifdef CONFIG_PM
1774static int ravb_runtime_nop(struct device *dev)
1775{
1776 /* Runtime PM callback shared between ->runtime_suspend()
1777 * and ->runtime_resume(). Simply returns success.
1778 *
1779 * This driver re-initializes all registers after
1780 * pm_runtime_get_sync() anyway so there is no need
1781 * to save and restore registers here.
1782 */
1783 return 0;
1784}
1785
1786static const struct dev_pm_ops ravb_dev_pm_ops = {
1787 .runtime_suspend = ravb_runtime_nop,
1788 .runtime_resume = ravb_runtime_nop,
1789};
1790
1791#define RAVB_PM_OPS (&ravb_dev_pm_ops)
1792#else
1793#define RAVB_PM_OPS NULL
1794#endif
1795
1796static const struct of_device_id ravb_match_table[] = {
1797 { .compatible = "renesas,etheravb-r8a7790" },
1798 { .compatible = "renesas,etheravb-r8a7794" },
1799 { }
1800};
1801MODULE_DEVICE_TABLE(of, ravb_match_table);
1802
1803static struct platform_driver ravb_driver = {
1804 .probe = ravb_probe,
1805 .remove = ravb_remove,
1806 .driver = {
1807 .name = "ravb",
1808 .pm = RAVB_PM_OPS,
1809 .of_match_table = ravb_match_table,
1810 },
1811};
1812
1813module_platform_driver(ravb_driver);
1814
1815MODULE_AUTHOR("Mitsuhiro Kimura, Masaru Nagai");
1816MODULE_DESCRIPTION("Renesas Ethernet AVB driver");
1817MODULE_LICENSE("GPL v2");
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