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UBUNTU: Ubuntu-4.15.0-96.97
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / renesas / ravb_main.c
CommitLineData
c156633f
SS		 1/* Renesas Ethernet AVB device driver
2 *
3c7a3108 3 * Copyright (C) 2014-2019 Renesas Electronics Corporation
c156633f 4 * Copyright (C) 2015 Renesas Solutions Corp.
568b3ce7 5 * Copyright (C) 2015-2016 Cogent Embedded, Inc. <source@cogentembedded.com>
c156633f
SS		 6 *
7 * Based on the SuperH Ethernet driver
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms and conditions of the GNU General Public License version 2,
11 * as published by the Free Software Foundation.
12 */
13
14#include <linux/cache.h>
15#include <linux/clk.h>
16#include <linux/delay.h>
17#include <linux/dma-mapping.h>
18#include <linux/err.h>
19#include <linux/etherdevice.h>
20#include <linux/ethtool.h>
21#include <linux/if_vlan.h>
22#include <linux/kernel.h>
23#include <linux/list.h>
24#include <linux/module.h>
25#include <linux/net_tstamp.h>
26#include <linux/of.h>
27#include <linux/of_device.h>
28#include <linux/of_irq.h>
29#include <linux/of_mdio.h>
30#include <linux/of_net.h>
c156633f
SS		 31#include <linux/pm_runtime.h>
32#include <linux/slab.h>
33#include <linux/spinlock.h>
0e98f9d5 34#include <linux/sys_soc.h>
c156633f 35
b3d39a88
SH		 36#include <asm/div64.h>
37
c156633f
SS		 38#include "ravb.h"
39
40#define RAVB_DEF_MSG_ENABLE \
41 (NETIF_MSG_LINK | \
42 NETIF_MSG_TIMER | \
43 NETIF_MSG_RX_ERR | \
44 NETIF_MSG_TX_ERR)
45
f51bdc23
KM		 46static const char *ravb_rx_irqs[NUM_RX_QUEUE] = {
47 "ch0", /* RAVB_BE */
48 "ch1", /* RAVB_NC */
49};
50
51static const char *ravb_tx_irqs[NUM_TX_QUEUE] = {
52 "ch18", /* RAVB_BE */
53 "ch19", /* RAVB_NC */
54};
55
568b3ce7
SS		 56void ravb_modify(struct net_device *ndev, enum ravb_reg reg, u32 clear,
57 u32 set)
58{
59 ravb_write(ndev, (ravb_read(ndev, reg) & ~clear) | set, reg);
60}
61
a0d2f206 62int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value)
c156633f
SS		 63{
64 int i;
65
66 for (i = 0; i < 10000; i++) {
67 if ((ravb_read(ndev, reg) & mask) == value)
68 return 0;
69 udelay(10);
70 }
71 return -ETIMEDOUT;
72}
73
74static int ravb_config(struct net_device *ndev)
75{
76 int error;
77
78 /* Set config mode */
568b3ce7 79 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG);
c156633f
SS		 80 /* Check if the operating mode is changed to the config mode */
81 error = ravb_wait(ndev, CSR, CSR_OPS, CSR_OPS_CONFIG);
82 if (error)
83 netdev_err(ndev, "failed to switch device to config mode\n");
84
85 return error;
86}
87
c156633f
SS		 88static void ravb_set_rate(struct net_device *ndev)
89{
90 struct ravb_private *priv = netdev_priv(ndev);
91
92 switch (priv->speed) {
93 case 100: /* 100BASE */
94 ravb_write(ndev, GECMR_SPEED_100, GECMR);
95 break;
96 case 1000: /* 1000BASE */
97 ravb_write(ndev, GECMR_SPEED_1000, GECMR);
98 break;
c156633f
SS		 99 }
100}
101
102static void ravb_set_buffer_align(struct sk_buff *skb)
103{
104 u32 reserve = (unsigned long)skb->data & (RAVB_ALIGN - 1);
105
106 if (reserve)
107 skb_reserve(skb, RAVB_ALIGN - reserve);
108}
109
110/* Get MAC address from the MAC address registers
111 *
112 * Ethernet AVB device doesn't have ROM for MAC address.
113 * This function gets the MAC address that was used by a bootloader.
114 */
115static void ravb_read_mac_address(struct net_device *ndev, const u8 *mac)
116{
117 if (mac) {
118 ether_addr_copy(ndev->dev_addr, mac);
119 } else {
d9660638
SS		 120 u32 mahr = ravb_read(ndev, MAHR);
121 u32 malr = ravb_read(ndev, MALR);
122
123 ndev->dev_addr[0] = (mahr >> 24) & 0xFF;
124 ndev->dev_addr[1] = (mahr >> 16) & 0xFF;
125 ndev->dev_addr[2] = (mahr >> 8) & 0xFF;
126 ndev->dev_addr[3] = (mahr >> 0) & 0xFF;
127 ndev->dev_addr[4] = (malr >> 8) & 0xFF;
128 ndev->dev_addr[5] = (malr >> 0) & 0xFF;
c156633f
SS		 129 }
130}
131
132static void ravb_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set)
133{
134 struct ravb_private *priv = container_of(ctrl, struct ravb_private,
135 mdiobb);
c156633f 136
568b3ce7 137 ravb_modify(priv->ndev, PIR, mask, set ? mask : 0);
c156633f
SS		 138}
139
140/* MDC pin control */
141static void ravb_set_mdc(struct mdiobb_ctrl *ctrl, int level)
142{
143 ravb_mdio_ctrl(ctrl, PIR_MDC, level);
144}
145
146/* Data I/O pin control */
147static void ravb_set_mdio_dir(struct mdiobb_ctrl *ctrl, int output)
148{
149 ravb_mdio_ctrl(ctrl, PIR_MMD, output);
150}
151
152/* Set data bit */
153static void ravb_set_mdio_data(struct mdiobb_ctrl *ctrl, int value)
154{
155 ravb_mdio_ctrl(ctrl, PIR_MDO, value);
156}
157
158/* Get data bit */
159static int ravb_get_mdio_data(struct mdiobb_ctrl *ctrl)
160{
161 struct ravb_private *priv = container_of(ctrl, struct ravb_private,
162 mdiobb);
163
164 return (ravb_read(priv->ndev, PIR) & PIR_MDI) != 0;
165}
166
167/* MDIO bus control struct */
168static struct mdiobb_ops bb_ops = {
169 .owner = THIS_MODULE,
170 .set_mdc = ravb_set_mdc,
171 .set_mdio_dir = ravb_set_mdio_dir,
172 .set_mdio_data = ravb_set_mdio_data,
173 .get_mdio_data = ravb_get_mdio_data,
174};
175
a47b70ea
KM		 176/* Free TX skb function for AVB-IP */
177static int ravb_tx_free(struct net_device *ndev, int q, bool free_txed_only)
178{
179 struct ravb_private *priv = netdev_priv(ndev);
180 struct net_device_stats *stats = &priv->stats[q];
181 struct ravb_tx_desc *desc;
182 int free_num = 0;
183 int entry;
184 u32 size;
185
186 for (; priv->cur_tx[q] - priv->dirty_tx[q] > 0; priv->dirty_tx[q]++) {
187 bool txed;
188
189 entry = priv->dirty_tx[q] % (priv->num_tx_ring[q] *
190 NUM_TX_DESC);
191 desc = &priv->tx_ring[q][entry];
192 txed = desc->die_dt == DT_FEMPTY;
193 if (free_txed_only && !txed)
194 break;
195 /* Descriptor type must be checked before all other reads */
196 dma_rmb();
197 size = le16_to_cpu(desc->ds_tagl) & TX_DS;
198 /* Free the original skb. */
199 if (priv->tx_skb[q][entry / NUM_TX_DESC]) {
200 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
201 size, DMA_TO_DEVICE);
202 /* Last packet descriptor? */
203 if (entry % NUM_TX_DESC == NUM_TX_DESC - 1) {
204 entry /= NUM_TX_DESC;
205 dev_kfree_skb_any(priv->tx_skb[q][entry]);
206 priv->tx_skb[q][entry] = NULL;
207 if (txed)
208 stats->tx_packets++;
209 }
210 free_num++;
211 }
212 if (txed)
213 stats->tx_bytes += size;
214 desc->die_dt = DT_EEMPTY;
215 }
216 return free_num;
217}
218
c156633f
SS		 219/* Free skb's and DMA buffers for Ethernet AVB */
220static void ravb_ring_free(struct net_device *ndev, int q)
221{
222 struct ravb_private *priv = netdev_priv(ndev);
223 int ring_size;
224 int i;
225
c156633f 226 if (priv->rx_ring[q]) {
a47b70ea
KM		 227 for (i = 0; i < priv->num_rx_ring[q]; i++) {
228 struct ravb_ex_rx_desc *desc = &priv->rx_ring[q][i];
229
230 if (!dma_mapping_error(ndev->dev.parent,
231 le32_to_cpu(desc->dptr)))
232 dma_unmap_single(ndev->dev.parent,
233 le32_to_cpu(desc->dptr),
234 PKT_BUF_SZ,
235 DMA_FROM_DEVICE);
236 }
c156633f
SS		 237 ring_size = sizeof(struct ravb_ex_rx_desc) *
238 (priv->num_rx_ring[q] + 1);
e2dbb33a 239 dma_free_coherent(ndev->dev.parent, ring_size, priv->rx_ring[q],
c156633f
SS		 240 priv->rx_desc_dma[q]);
241 priv->rx_ring[q] = NULL;
242 }
243
244 if (priv->tx_ring[q]) {
a47b70ea
KM		 245 ravb_tx_free(ndev, q, false);
246
c156633f 247 ring_size = sizeof(struct ravb_tx_desc) *
2f45d190 248 (priv->num_tx_ring[q] * NUM_TX_DESC + 1);
e2dbb33a 249 dma_free_coherent(ndev->dev.parent, ring_size, priv->tx_ring[q],
c156633f
SS		 250 priv->tx_desc_dma[q]);
251 priv->tx_ring[q] = NULL;
252 }
a47b70ea 253
79514ef6
ER		 254 /* Free RX skb ringbuffer */
255 if (priv->rx_skb[q]) {
256 for (i = 0; i < priv->num_rx_ring[q]; i++)
257 dev_kfree_skb(priv->rx_skb[q][i]);
258 }
259 kfree(priv->rx_skb[q]);
260 priv->rx_skb[q] = NULL;
261
262 /* Free aligned TX buffers */
263 kfree(priv->tx_align[q]);
264 priv->tx_align[q] = NULL;
265
a47b70ea
KM		 266 /* Free TX skb ringbuffer.
267 * SKBs are freed by ravb_tx_free() call above.
268 */
269 kfree(priv->tx_skb[q]);
270 priv->tx_skb[q] = NULL;
c156633f
SS		 271}
272
273/* Format skb and descriptor buffer for Ethernet AVB */
274static void ravb_ring_format(struct net_device *ndev, int q)
275{
276 struct ravb_private *priv = netdev_priv(ndev);
aad0d51e
SS		 277 struct ravb_ex_rx_desc *rx_desc;
278 struct ravb_tx_desc *tx_desc;
279 struct ravb_desc *desc;
c156633f 280 int rx_ring_size = sizeof(*rx_desc) * priv->num_rx_ring[q];
2f45d190
SS		 281 int tx_ring_size = sizeof(*tx_desc) * priv->num_tx_ring[q] *
282 NUM_TX_DESC;
c156633f 283 dma_addr_t dma_addr;
c156633f
SS		 284 int i;
285
286 priv->cur_rx[q] = 0;
287 priv->cur_tx[q] = 0;
288 priv->dirty_rx[q] = 0;
289 priv->dirty_tx[q] = 0;
290
291 memset(priv->rx_ring[q], 0, rx_ring_size);
292 /* Build RX ring buffer */
293 for (i = 0; i < priv->num_rx_ring[q]; i++) {
c156633f
SS		 294 /* RX descriptor */
295 rx_desc = &priv->rx_ring[q][i];
094e43d5 296 rx_desc->ds_cc = cpu_to_le16(PKT_BUF_SZ);
e2dbb33a 297 dma_addr = dma_map_single(ndev->dev.parent, priv->rx_skb[q][i]->data,
094e43d5 298 PKT_BUF_SZ,
c156633f 299 DMA_FROM_DEVICE);
d8b48911
SS		 300 /* We just set the data size to 0 for a failed mapping which
301 * should prevent DMA from happening...
302 */
e2dbb33a 303 if (dma_mapping_error(ndev->dev.parent, dma_addr))
d8b48911 304 rx_desc->ds_cc = cpu_to_le16(0);
c156633f
SS		 305 rx_desc->dptr = cpu_to_le32(dma_addr);
306 rx_desc->die_dt = DT_FEMPTY;
307 }
308 rx_desc = &priv->rx_ring[q][i];
309 rx_desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]);
310 rx_desc->die_dt = DT_LINKFIX; /* type */
c156633f
SS		 311
312 memset(priv->tx_ring[q], 0, tx_ring_size);
313 /* Build TX ring buffer */
2f45d190
SS		 314 for (i = 0, tx_desc = priv->tx_ring[q]; i < priv->num_tx_ring[q];
315 i++, tx_desc++) {
316 tx_desc->die_dt = DT_EEMPTY;
317 tx_desc++;
c156633f
SS		 318 tx_desc->die_dt = DT_EEMPTY;
319 }
c156633f
SS		 320 tx_desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]);
321 tx_desc->die_dt = DT_LINKFIX; /* type */
322
323 /* RX descriptor base address for best effort */
324 desc = &priv->desc_bat[RX_QUEUE_OFFSET + q];
325 desc->die_dt = DT_LINKFIX; /* type */
326 desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]);
327
328 /* TX descriptor base address for best effort */
329 desc = &priv->desc_bat[q];
330 desc->die_dt = DT_LINKFIX; /* type */
331 desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]);
332}
333
334/* Init skb and descriptor buffer for Ethernet AVB */
335static int ravb_ring_init(struct net_device *ndev, int q)
336{
337 struct ravb_private *priv = netdev_priv(ndev);
d8b48911 338 struct sk_buff *skb;
c156633f 339 int ring_size;
d8b48911 340 int i;
c156633f
SS		 341
342 /* Allocate RX and TX skb rings */
343 priv->rx_skb[q] = kcalloc(priv->num_rx_ring[q],
344 sizeof(*priv->rx_skb[q]), GFP_KERNEL);
345 priv->tx_skb[q] = kcalloc(priv->num_tx_ring[q],
346 sizeof(*priv->tx_skb[q]), GFP_KERNEL);
347 if (!priv->rx_skb[q] || !priv->tx_skb[q])
348 goto error;
349
d8b48911
SS		 350 for (i = 0; i < priv->num_rx_ring[q]; i++) {
351 skb = netdev_alloc_skb(ndev, PKT_BUF_SZ + RAVB_ALIGN - 1);
352 if (!skb)
353 goto error;
354 ravb_set_buffer_align(skb);
355 priv->rx_skb[q][i] = skb;
356 }
357
c156633f 358 /* Allocate rings for the aligned buffers */
2f45d190
SS		 359 priv->tx_align[q] = kmalloc(DPTR_ALIGN * priv->num_tx_ring[q] +
360 DPTR_ALIGN - 1, GFP_KERNEL);
361 if (!priv->tx_align[q])
c156633f
SS		 362 goto error;
363
364 /* Allocate all RX descriptors. */
365 ring_size = sizeof(struct ravb_ex_rx_desc) * (priv->num_rx_ring[q] + 1);
e2dbb33a 366 priv->rx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size,
c156633f
SS		 367 &priv->rx_desc_dma[q],
368 GFP_KERNEL);
369 if (!priv->rx_ring[q])
370 goto error;
371
372 priv->dirty_rx[q] = 0;
373
374 /* Allocate all TX descriptors. */
2f45d190
SS		 375 ring_size = sizeof(struct ravb_tx_desc) *
376 (priv->num_tx_ring[q] * NUM_TX_DESC + 1);
e2dbb33a 377 priv->tx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size,
c156633f
SS		 378 &priv->tx_desc_dma[q],
379 GFP_KERNEL);
380 if (!priv->tx_ring[q])
381 goto error;
382
383 return 0;
384
385error:
386 ravb_ring_free(ndev, q);
387
388 return -ENOMEM;
389}
390
391/* E-MAC init function */
392static void ravb_emac_init(struct net_device *ndev)
393{
c156633f
SS		 394 /* Receive frame limit set register */
395 ravb_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, RFLR);
396
4d86d381 397 /* EMAC Mode: PAUSE prohibition; Duplex; RX Checksum; TX; RX */
8011a0e3 398 ravb_write(ndev, ECMR_ZPF | ECMR_DM |
4d86d381 399 (ndev->features & NETIF_F_RXCSUM ? ECMR_RCSC : 0) |
1c1fa821 400 ECMR_TE | ECMR_RE, ECMR);
c156633f
SS		 401
402 ravb_set_rate(ndev);
403
404 /* Set MAC address */
405 ravb_write(ndev,
406 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
407 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
408 ravb_write(ndev,
409 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
410
c156633f
SS		 411 /* E-MAC status register clear */
412 ravb_write(ndev, ECSR_ICD | ECSR_MPD, ECSR);
413
414 /* E-MAC interrupt enable register */
415 ravb_write(ndev, ECSIPR_ICDIP | ECSIPR_MPDIP | ECSIPR_LCHNGIP, ECSIPR);
416}
417
418/* Device init function for Ethernet AVB */
419static int ravb_dmac_init(struct net_device *ndev)
420{
f51bdc23 421 struct ravb_private *priv = netdev_priv(ndev);
c156633f
SS		 422 int error;
423
424 /* Set CONFIG mode */
425 error = ravb_config(ndev);
426 if (error)
427 return error;
428
429 error = ravb_ring_init(ndev, RAVB_BE);
430 if (error)
431 return error;
432 error = ravb_ring_init(ndev, RAVB_NC);
433 if (error) {
434 ravb_ring_free(ndev, RAVB_BE);
435 return error;
436 }
437
438 /* Descriptor format */
439 ravb_ring_format(ndev, RAVB_BE);
440 ravb_ring_format(ndev, RAVB_NC);
441
442#if defined(__LITTLE_ENDIAN)
568b3ce7 443 ravb_modify(ndev, CCC, CCC_BOC, 0);
c156633f 444#else
568b3ce7 445 ravb_modify(ndev, CCC, CCC_BOC, CCC_BOC);
c156633f
SS		 446#endif
447
448 /* Set AVB RX */
8d9c418b
MN		 449 ravb_write(ndev,
450 RCR_EFFS | RCR_ENCF | RCR_ETS0 | RCR_ESF | 0x18000000, RCR);
c156633f
SS		 451
452 /* Set FIFO size */
14e7854b 453 ravb_write(ndev, TGC_TQP_AVBMODE1 | 0x00112200, TGC);
c156633f
SS		 454
455 /* Timestamp enable */
456 ravb_write(ndev, TCCR_TFEN, TCCR);
457
6474de5f 458 /* Interrupt init: */
f51bdc23
KM		 459 if (priv->chip_id == RCAR_GEN3) {
460 /* Clear DIL.DPLx */
461 ravb_write(ndev, 0, DIL);
462 /* Set queue specific interrupt */
463 ravb_write(ndev, CIE_CRIE | CIE_CTIE | CIE_CL0M, CIE);
464 }
c156633f
SS		 465 /* Frame receive */
466 ravb_write(ndev, RIC0_FRE0 | RIC0_FRE1, RIC0);
6474de5f
KM		 467 /* Disable FIFO full warning */
468 ravb_write(ndev, 0, RIC1);
c156633f
SS		 469 /* Receive FIFO full error, descriptor empty */
470 ravb_write(ndev, RIC2_QFE0 | RIC2_QFE1 | RIC2_RFFE, RIC2);
471 /* Frame transmitted, timestamp FIFO updated */
472 ravb_write(ndev, TIC_FTE0 | TIC_FTE1 | TIC_TFUE, TIC);
473
474 /* Setting the control will start the AVB-DMAC process. */
568b3ce7 475 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_OPERATION);
c156633f
SS		 476
477 return 0;
478}
479
c156633f
SS		 480static void ravb_get_tx_tstamp(struct net_device *ndev)
481{
482 struct ravb_private *priv = netdev_priv(ndev);
483 struct ravb_tstamp_skb *ts_skb, *ts_skb2;
484 struct skb_shared_hwtstamps shhwtstamps;
485 struct sk_buff *skb;
486 struct timespec64 ts;
487 u16 tag, tfa_tag;
488 int count;
489 u32 tfa2;
490
491 count = (ravb_read(ndev, TSR) & TSR_TFFL) >> 8;
492 while (count--) {
493 tfa2 = ravb_read(ndev, TFA2);
494 tfa_tag = (tfa2 & TFA2_TST) >> 16;
495 ts.tv_nsec = (u64)ravb_read(ndev, TFA0);
496 ts.tv_sec = ((u64)(tfa2 & TFA2_TSV) << 32) |
497 ravb_read(ndev, TFA1);
498 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
499 shhwtstamps.hwtstamp = timespec64_to_ktime(ts);
500 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list,
501 list) {
502 skb = ts_skb->skb;
503 tag = ts_skb->tag;
504 list_del(&ts_skb->list);
505 kfree(ts_skb);
506 if (tag == tfa_tag) {
507 skb_tstamp_tx(skb, &shhwtstamps);
3c7a3108 508 dev_consume_skb_any(skb);
c156633f 509 break;
3c7a3108
TV		 510 } else {
511 dev_kfree_skb_any(skb);
c156633f
SS		 512 }
513 }
568b3ce7 514 ravb_modify(ndev, TCCR, TCCR_TFR, TCCR_TFR);
c156633f
SS		 515 }
516}
517
4d86d381
SH		 518static void ravb_rx_csum(struct sk_buff *skb)
519{
520 u8 *hw_csum;
521
e557fc8f
SH		 522 /* The hardware checksum is contained in sizeof(__sum16) (2) bytes
523 * appended to packet data
524 */
525 if (unlikely(skb->len < sizeof(__sum16)))
4d86d381 526 return;
e557fc8f 527 hw_csum = skb_tail_pointer(skb) - sizeof(__sum16);
4d86d381
SH		 528 skb->csum = csum_unfold((__force __sum16)get_unaligned_le16(hw_csum));
529 skb->ip_summed = CHECKSUM_COMPLETE;
e557fc8f 530 skb_trim(skb, skb->len - sizeof(__sum16));
4d86d381
SH		 531}
532
c156633f
SS		 533/* Packet receive function for Ethernet AVB */
534static bool ravb_rx(struct net_device *ndev, int *quota, int q)
535{
536 struct ravb_private *priv = netdev_priv(ndev);
537 int entry = priv->cur_rx[q] % priv->num_rx_ring[q];
538 int boguscnt = (priv->dirty_rx[q] + priv->num_rx_ring[q]) -
539 priv->cur_rx[q];
540 struct net_device_stats *stats = &priv->stats[q];
541 struct ravb_ex_rx_desc *desc;
542 struct sk_buff *skb;
543 dma_addr_t dma_addr;
544 struct timespec64 ts;
c156633f 545 u8 desc_status;
aad0d51e 546 u16 pkt_len;
c156633f
SS		 547 int limit;
548
549 boguscnt = min(boguscnt, *quota);
550 limit = boguscnt;
551 desc = &priv->rx_ring[q][entry];
552 while (desc->die_dt != DT_FEMPTY) {
553 /* Descriptor type must be checked before all other reads */
554 dma_rmb();
555 desc_status = desc->msc;
556 pkt_len = le16_to_cpu(desc->ds_cc) & RX_DS;
557
558 if (--boguscnt < 0)
559 break;
560
d8b48911
SS		 561 /* We use 0-byte descriptors to mark the DMA mapping errors */
562 if (!pkt_len)
563 continue;
564
c156633f
SS		 565 if (desc_status & MSC_MC)
566 stats->multicast++;
567
568 if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF |
569 MSC_CEEF)) {
570 stats->rx_errors++;
571 if (desc_status & MSC_CRC)
572 stats->rx_crc_errors++;
573 if (desc_status & MSC_RFE)
574 stats->rx_frame_errors++;
575 if (desc_status & (MSC_RTLF | MSC_RTSF))
576 stats->rx_length_errors++;
577 if (desc_status & MSC_CEEF)
578 stats->rx_missed_errors++;
579 } else {
580 u32 get_ts = priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE;
581
582 skb = priv->rx_skb[q][entry];
583 priv->rx_skb[q][entry] = NULL;
e2dbb33a 584 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
094e43d5 585 PKT_BUF_SZ,
e2370f07 586 DMA_FROM_DEVICE);
c156633f
SS		 587 get_ts &= (q == RAVB_NC) ?
588 RAVB_RXTSTAMP_TYPE_V2_L2_EVENT :
589 ~RAVB_RXTSTAMP_TYPE_V2_L2_EVENT;
590 if (get_ts) {
591 struct skb_shared_hwtstamps *shhwtstamps;
592
593 shhwtstamps = skb_hwtstamps(skb);
594 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
595 ts.tv_sec = ((u64) le16_to_cpu(desc->ts_sh) <<
596 32) | le32_to_cpu(desc->ts_sl);
597 ts.tv_nsec = le32_to_cpu(desc->ts_n);
598 shhwtstamps->hwtstamp = timespec64_to_ktime(ts);
599 }
4d86d381 600
c156633f
SS		 601 skb_put(skb, pkt_len);
602 skb->protocol = eth_type_trans(skb, ndev);
4d86d381
SH		 603 if (ndev->features & NETIF_F_RXCSUM)
604 ravb_rx_csum(skb);
c156633f
SS		 605 napi_gro_receive(&priv->napi[q], skb);
606 stats->rx_packets++;
607 stats->rx_bytes += pkt_len;
608 }
609
610 entry = (++priv->cur_rx[q]) % priv->num_rx_ring[q];
611 desc = &priv->rx_ring[q][entry];
612 }
613
614 /* Refill the RX ring buffers. */
615 for (; priv->cur_rx[q] - priv->dirty_rx[q] > 0; priv->dirty_rx[q]++) {
616 entry = priv->dirty_rx[q] % priv->num_rx_ring[q];
617 desc = &priv->rx_ring[q][entry];
094e43d5 618 desc->ds_cc = cpu_to_le16(PKT_BUF_SZ);
c156633f
SS		 619
620 if (!priv->rx_skb[q][entry]) {
621 skb = netdev_alloc_skb(ndev,
622 PKT_BUF_SZ + RAVB_ALIGN - 1);
623 if (!skb)
624 break; /* Better luck next round. */
625 ravb_set_buffer_align(skb);
e2dbb33a 626 dma_addr = dma_map_single(ndev->dev.parent, skb->data,
c156633f
SS		 627 le16_to_cpu(desc->ds_cc),
628 DMA_FROM_DEVICE);
629 skb_checksum_none_assert(skb);
d8b48911
SS		 630 /* We just set the data size to 0 for a failed mapping
631 * which should prevent DMA from happening...
632 */
e2dbb33a 633 if (dma_mapping_error(ndev->dev.parent, dma_addr))
d8b48911 634 desc->ds_cc = cpu_to_le16(0);
c156633f
SS		 635 desc->dptr = cpu_to_le32(dma_addr);
636 priv->rx_skb[q][entry] = skb;
637 }
638 /* Descriptor type must be set after all the above writes */
639 dma_wmb();
640 desc->die_dt = DT_FEMPTY;
641 }
642
643 *quota -= limit - (++boguscnt);
644
645 return boguscnt <= 0;
646}
647
648static void ravb_rcv_snd_disable(struct net_device *ndev)
649{
650 /* Disable TX and RX */
568b3ce7 651 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0);
c156633f
SS		 652}
653
654static void ravb_rcv_snd_enable(struct net_device *ndev)
655{
656 /* Enable TX and RX */
568b3ce7 657 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE);
c156633f
SS		 658}
659
660/* function for waiting dma process finished */
661static int ravb_stop_dma(struct net_device *ndev)
662{
663 int error;
664
665 /* Wait for stopping the hardware TX process */
666 error = ravb_wait(ndev, TCCR,
667 TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 0);
668 if (error)
669 return error;
670
671 error = ravb_wait(ndev, CSR, CSR_TPO0 | CSR_TPO1 | CSR_TPO2 | CSR_TPO3,
672 0);
673 if (error)
674 return error;
675
676 /* Stop the E-MAC's RX/TX processes. */
677 ravb_rcv_snd_disable(ndev);
678
679 /* Wait for stopping the RX DMA process */
680 error = ravb_wait(ndev, CSR, CSR_RPO, 0);
681 if (error)
682 return error;
683
684 /* Stop AVB-DMAC process */
685 return ravb_config(ndev);
686}
687
688/* E-MAC interrupt handler */
f51bdc23 689static void ravb_emac_interrupt_unlocked(struct net_device *ndev)
c156633f
SS		 690{
691 struct ravb_private *priv = netdev_priv(ndev);
692 u32 ecsr, psr;
693
694 ecsr = ravb_read(ndev, ECSR);
695 ravb_write(ndev, ecsr, ECSR); /* clear interrupt */
3e3d6477
NS		 696
697 if (ecsr & ECSR_MPD)
698 pm_wakeup_event(&priv->pdev->dev, 0);
c156633f
SS		 699 if (ecsr & ECSR_ICD)
700 ndev->stats.tx_carrier_errors++;
701 if (ecsr & ECSR_LCHNG) {
702 /* Link changed */
703 if (priv->no_avb_link)
704 return;
705 psr = ravb_read(ndev, PSR);
706 if (priv->avb_link_active_low)
707 psr ^= PSR_LMON;
708 if (!(psr & PSR_LMON)) {
709 /* DIsable RX and TX */
710 ravb_rcv_snd_disable(ndev);
711 } else {
712 /* Enable RX and TX */
713 ravb_rcv_snd_enable(ndev);
714 }
715 }
716}
717
f51bdc23
KM		 718static irqreturn_t ravb_emac_interrupt(int irq, void *dev_id)
719{
720 struct net_device *ndev = dev_id;
721 struct ravb_private *priv = netdev_priv(ndev);
722
723 spin_lock(&priv->lock);
724 ravb_emac_interrupt_unlocked(ndev);
725 mmiowb();
726 spin_unlock(&priv->lock);
727 return IRQ_HANDLED;
728}
729
c156633f
SS		 730/* Error interrupt handler */
731static void ravb_error_interrupt(struct net_device *ndev)
732{
733 struct ravb_private *priv = netdev_priv(ndev);
734 u32 eis, ris2;
735
736 eis = ravb_read(ndev, EIS);
009b7053 737 ravb_write(ndev, ~(EIS_QFS | EIS_RESERVED), EIS);
c156633f
SS		 738 if (eis & EIS_QFS) {
739 ris2 = ravb_read(ndev, RIS2);
009b7053
KM		 740 ravb_write(ndev, ~(RIS2_QFF0 | RIS2_RFFF | RIS2_RESERVED),
741 RIS2);
c156633f
SS		 742
743 /* Receive Descriptor Empty int */
744 if (ris2 & RIS2_QFF0)
745 priv->stats[RAVB_BE].rx_over_errors++;
746
747 /* Receive Descriptor Empty int */
748 if (ris2 & RIS2_QFF1)
749 priv->stats[RAVB_NC].rx_over_errors++;
750
751 /* Receive FIFO Overflow int */
752 if (ris2 & RIS2_RFFF)
753 priv->rx_fifo_errors++;
754 }
755}
756
f51bdc23
KM		 757static bool ravb_queue_interrupt(struct net_device *ndev, int q)
758{
759 struct ravb_private *priv = netdev_priv(ndev);
760 u32 ris0 = ravb_read(ndev, RIS0);
761 u32 ric0 = ravb_read(ndev, RIC0);
762 u32 tis = ravb_read(ndev, TIS);
763 u32 tic = ravb_read(ndev, TIC);
764
765 if (((ris0 & ric0) & BIT(q)) || ((tis & tic) & BIT(q))) {
766 if (napi_schedule_prep(&priv->napi[q])) {
767 /* Mask RX and TX interrupts */
768 if (priv->chip_id == RCAR_GEN2) {
769 ravb_write(ndev, ric0 & ~BIT(q), RIC0);
770 ravb_write(ndev, tic & ~BIT(q), TIC);
771 } else {
772 ravb_write(ndev, BIT(q), RID0);
773 ravb_write(ndev, BIT(q), TID);
774 }
775 __napi_schedule(&priv->napi[q]);
776 } else {
777 netdev_warn(ndev,
778 "ignoring interrupt, rx status 0x%08x, rx mask 0x%08x,\n",
779 ris0, ric0);
780 netdev_warn(ndev,
781 " tx status 0x%08x, tx mask 0x%08x.\n",
782 tis, tic);
783 }
784 return true;
785 }
786 return false;
787}
788
789static bool ravb_timestamp_interrupt(struct net_device *ndev)
790{
791 u32 tis = ravb_read(ndev, TIS);
792
793 if (tis & TIS_TFUF) {
009b7053 794 ravb_write(ndev, ~(TIS_TFUF | TIS_RESERVED), TIS);
f51bdc23
KM		 795 ravb_get_tx_tstamp(ndev);
796 return true;
797 }
798 return false;
799}
800
c156633f
SS		 801static irqreturn_t ravb_interrupt(int irq, void *dev_id)
802{
803 struct net_device *ndev = dev_id;
804 struct ravb_private *priv = netdev_priv(ndev);
805 irqreturn_t result = IRQ_NONE;
806 u32 iss;
807
808 spin_lock(&priv->lock);
809 /* Get interrupt status */
810 iss = ravb_read(ndev, ISS);
811
812 /* Received and transmitted interrupts */
813 if (iss & (ISS_FRS | ISS_FTS | ISS_TFUS)) {
c156633f
SS		 814 int q;
815
816 /* Timestamp updated */
f51bdc23 817 if (ravb_timestamp_interrupt(ndev))
c156633f 818 result = IRQ_HANDLED;
c156633f
SS		 819
820 /* Network control and best effort queue RX/TX */
821 for (q = RAVB_NC; q >= RAVB_BE; q--) {
f51bdc23 822 if (ravb_queue_interrupt(ndev, q))
c156633f 823 result = IRQ_HANDLED;
c156633f
SS		 824 }
825 }
826
827 /* E-MAC status summary */
828 if (iss & ISS_MS) {
f51bdc23 829 ravb_emac_interrupt_unlocked(ndev);
c156633f
SS		 830 result = IRQ_HANDLED;
831 }
832
833 /* Error status summary */
834 if (iss & ISS_ES) {
835 ravb_error_interrupt(ndev);
836 result = IRQ_HANDLED;
837 }
838
f51bdc23 839 /* gPTP interrupt status summary */
d0988a5f
SS		 840 if (iss & ISS_CGIS) {
841 ravb_ptp_interrupt(ndev);
38c848c7 842 result = IRQ_HANDLED;
d0988a5f 843 }
a0d2f206 844
c156633f
SS		 845 mmiowb();
846 spin_unlock(&priv->lock);
847 return result;
848}
849
f51bdc23
KM		 850/* Timestamp/Error/gPTP interrupt handler */
851static irqreturn_t ravb_multi_interrupt(int irq, void *dev_id)
852{
853 struct net_device *ndev = dev_id;
854 struct ravb_private *priv = netdev_priv(ndev);
855 irqreturn_t result = IRQ_NONE;
856 u32 iss;
857
858 spin_lock(&priv->lock);
859 /* Get interrupt status */
860 iss = ravb_read(ndev, ISS);
861
862 /* Timestamp updated */
863 if ((iss & ISS_TFUS) && ravb_timestamp_interrupt(ndev))
864 result = IRQ_HANDLED;
865
866 /* Error status summary */
867 if (iss & ISS_ES) {
868 ravb_error_interrupt(ndev);
869 result = IRQ_HANDLED;
870 }
871
872 /* gPTP interrupt status summary */
d0988a5f
SS		 873 if (iss & ISS_CGIS) {
874 ravb_ptp_interrupt(ndev);
f51bdc23 875 result = IRQ_HANDLED;
d0988a5f 876 }
f51bdc23
KM		 877
878 mmiowb();
879 spin_unlock(&priv->lock);
880 return result;
881}
882
883static irqreturn_t ravb_dma_interrupt(int irq, void *dev_id, int q)
884{
885 struct net_device *ndev = dev_id;
886 struct ravb_private *priv = netdev_priv(ndev);
887 irqreturn_t result = IRQ_NONE;
888
889 spin_lock(&priv->lock);
890
891 /* Network control/Best effort queue RX/TX */
892 if (ravb_queue_interrupt(ndev, q))
893 result = IRQ_HANDLED;
894
895 mmiowb();
896 spin_unlock(&priv->lock);
897 return result;
898}
899
900static irqreturn_t ravb_be_interrupt(int irq, void *dev_id)
901{
902 return ravb_dma_interrupt(irq, dev_id, RAVB_BE);
903}
904
905static irqreturn_t ravb_nc_interrupt(int irq, void *dev_id)
906{
907 return ravb_dma_interrupt(irq, dev_id, RAVB_NC);
908}
909
c156633f
SS		 910static int ravb_poll(struct napi_struct *napi, int budget)
911{
912 struct net_device *ndev = napi->dev;
913 struct ravb_private *priv = netdev_priv(ndev);
914 unsigned long flags;
915 int q = napi - priv->napi;
916 int mask = BIT(q);
917 int quota = budget;
918 u32 ris0, tis;
919
920 for (;;) {
921 tis = ravb_read(ndev, TIS);
922 ris0 = ravb_read(ndev, RIS0);
923 if (!((ris0 & mask) || (tis & mask)))
924 break;
925
926 /* Processing RX Descriptor Ring */
927 if (ris0 & mask) {
928 /* Clear RX interrupt */
009b7053 929 ravb_write(ndev, ~(mask | RIS0_RESERVED), RIS0);
c156633f
SS		 930 if (ravb_rx(ndev, &quota, q))
931 goto out;
932 }
933 /* Processing TX Descriptor Ring */
934 if (tis & mask) {
935 spin_lock_irqsave(&priv->lock, flags);
936 /* Clear TX interrupt */
009b7053 937 ravb_write(ndev, ~(mask | TIS_RESERVED), TIS);
a47b70ea 938 ravb_tx_free(ndev, q, true);
c156633f
SS		 939 netif_wake_subqueue(ndev, q);
940 mmiowb();
941 spin_unlock_irqrestore(&priv->lock, flags);
942 }
943 }
944
945 napi_complete(napi);
946
947 /* Re-enable RX/TX interrupts */
948 spin_lock_irqsave(&priv->lock, flags);
f51bdc23
KM		 949 if (priv->chip_id == RCAR_GEN2) {
950 ravb_modify(ndev, RIC0, mask, mask);
951 ravb_modify(ndev, TIC, mask, mask);
952 } else {
953 ravb_write(ndev, mask, RIE0);
954 ravb_write(ndev, mask, TIE);
955 }
c156633f
SS		 956 mmiowb();
957 spin_unlock_irqrestore(&priv->lock, flags);
958
959 /* Receive error message handling */
960 priv->rx_over_errors = priv->stats[RAVB_BE].rx_over_errors;
961 priv->rx_over_errors += priv->stats[RAVB_NC].rx_over_errors;
18a3ed59 962 if (priv->rx_over_errors != ndev->stats.rx_over_errors)
c156633f 963 ndev->stats.rx_over_errors = priv->rx_over_errors;
18a3ed59 964 if (priv->rx_fifo_errors != ndev->stats.rx_fifo_errors)
c156633f 965 ndev->stats.rx_fifo_errors = priv->rx_fifo_errors;
c156633f
SS		 966out:
967 return budget - quota;
968}
969
970/* PHY state control function */
971static void ravb_adjust_link(struct net_device *ndev)
972{
973 struct ravb_private *priv = netdev_priv(ndev);
0f635171 974 struct phy_device *phydev = ndev->phydev;
c156633f 975 bool new_state = false;
bc248ff2
VZ		 976 unsigned long flags;
977
978 spin_lock_irqsave(&priv->lock, flags);
979
980 /* Disable TX and RX right over here, if E-MAC change is ignored */
981 if (priv->no_avb_link)
982 ravb_rcv_snd_disable(ndev);
c156633f
SS		 983
984 if (phydev->link) {
c156633f
SS		 985 if (phydev->speed != priv->speed) {
986 new_state = true;
987 priv->speed = phydev->speed;
988 ravb_set_rate(ndev);
989 }
990 if (!priv->link) {
568b3ce7 991 ravb_modify(ndev, ECMR, ECMR_TXF, 0);
c156633f
SS		 992 new_state = true;
993 priv->link = phydev->link;
c156633f
SS		 994 }
995 } else if (priv->link) {
996 new_state = true;
997 priv->link = 0;
998 priv->speed = 0;
c156633f
SS		 999 }
1000
bc248ff2
VZ		 1001 /* Enable TX and RX right over here, if E-MAC change is ignored */
1002 if (priv->no_avb_link && phydev->link)
1003 ravb_rcv_snd_enable(ndev);
1004
1005 mmiowb();
1006 spin_unlock_irqrestore(&priv->lock, flags);
1007
c156633f
SS		 1008 if (new_state && netif_msg_link(priv))
1009 phy_print_status(phydev);
1010}
1011
0e98f9d5
GU		 1012static const struct soc_device_attribute r8a7795es10[] = {
1013 { .soc_id = "r8a7795", .revision = "ES1.0", },
1014 { /* sentinel */ }
1015};
1016
c156633f
SS		 1017/* PHY init function */
1018static int ravb_phy_init(struct net_device *ndev)
1019{
1020 struct device_node *np = ndev->dev.parent->of_node;
1021 struct ravb_private *priv = netdev_priv(ndev);
1022 struct phy_device *phydev;
1023 struct device_node *pn;
b4bc88a8 1024 int err;
c156633f
SS		 1025
1026 priv->link = 0;
1027 priv->speed = 0;
c156633f
SS		 1028
1029 /* Try connecting to PHY */
1030 pn = of_parse_phandle(np, "phy-handle", 0);
b4bc88a8
KM		 1031 if (!pn) {
1032 /* In the case of a fixed PHY, the DT node associated
1033 * to the PHY is the Ethernet MAC DT node.
1034 */
1035 if (of_phy_is_fixed_link(np)) {
1036 err = of_phy_register_fixed_link(np);
1037 if (err)
1038 return err;
1039 }
1040 pn = of_node_get(np);
1041 }
c156633f
SS		 1042 phydev = of_phy_connect(ndev, pn, ravb_adjust_link, 0,
1043 priv->phy_interface);
c9b1eb89 1044 of_node_put(pn);
c156633f
SS		 1045 if (!phydev) {
1046 netdev_err(ndev, "failed to connect PHY\n");
9f70eb33
JH		 1047 err = -ENOENT;
1048 goto err_deregister_fixed_link;
c156633f
SS		 1049 }
1050
0e98f9d5 1051 /* This driver only support 10/100Mbit speeds on R-Car H3 ES1.0
22d4df8f
KM		 1052 * at this time.
1053 */
0e98f9d5 1054 if (soc_device_match(r8a7795es10)) {
22d4df8f
KM		 1055 err = phy_set_max_speed(phydev, SPEED_100);
1056 if (err) {
1057 netdev_err(ndev, "failed to limit PHY to 100Mbit/s\n");
9f70eb33 1058 goto err_phy_disconnect;
22d4df8f
KM		 1059 }
1060
1061 netdev_info(ndev, "limited PHY to 100Mbit/s\n");
1062 }
1063
54499969
KM		 1064 /* 10BASE is not supported */
1065 phydev->supported &= ~PHY_10BT_FEATURES;
1066
2220943a 1067 phy_attached_info(phydev);
c156633f 1068
c156633f 1069 return 0;
9f70eb33
JH		 1070
1071err_phy_disconnect:
1072 phy_disconnect(phydev);
1073err_deregister_fixed_link:
1074 if (of_phy_is_fixed_link(np))
1075 of_phy_deregister_fixed_link(np);
1076
1077 return err;
c156633f
SS		 1078}
1079
1080/* PHY control start function */
1081static int ravb_phy_start(struct net_device *ndev)
1082{
c156633f
SS		 1083 int error;
1084
1085 error = ravb_phy_init(ndev);
1086 if (error)
1087 return error;
1088
0f635171 1089 phy_start(ndev->phydev);
c156633f
SS		 1090
1091 return 0;
1092}
1093
04462f2a
PR		 1094static int ravb_get_link_ksettings(struct net_device *ndev,
1095 struct ethtool_link_ksettings *cmd)
c156633f
SS		 1096{
1097 struct ravb_private *priv = netdev_priv(ndev);
c156633f
SS		 1098 unsigned long flags;
1099
5514174f 1100 if (!ndev->phydev)
1101 return -ENODEV;
c156633f 1102
5514174f 1103 spin_lock_irqsave(&priv->lock, flags);
1104 phy_ethtool_ksettings_get(ndev->phydev, cmd);
1105 spin_unlock_irqrestore(&priv->lock, flags);
1106
1107 return 0;
c156633f
SS		 1108}
1109
04462f2a
PR		 1110static int ravb_set_link_ksettings(struct net_device *ndev,
1111 const struct ethtool_link_ksettings *cmd)
c156633f 1112{
0f635171 1113 if (!ndev->phydev)
c156633f
SS		 1114 return -ENODEV;
1115
bc248ff2 1116 return phy_ethtool_ksettings_set(ndev->phydev, cmd);
c156633f
SS		 1117}
1118
1119static int ravb_nway_reset(struct net_device *ndev)
1120{
c156633f 1121 int error = -ENODEV;
c156633f 1122
07cb7686 1123 if (ndev->phydev)
0f635171 1124 error = phy_start_aneg(ndev->phydev);
c156633f
SS		 1125
1126 return error;
1127}
1128
1129static u32 ravb_get_msglevel(struct net_device *ndev)
1130{
1131 struct ravb_private *priv = netdev_priv(ndev);
1132
1133 return priv->msg_enable;
1134}
1135
1136static void ravb_set_msglevel(struct net_device *ndev, u32 value)
1137{
1138 struct ravb_private *priv = netdev_priv(ndev);
1139
1140 priv->msg_enable = value;
1141}
1142
1143static const char ravb_gstrings_stats[][ETH_GSTRING_LEN] = {
1144 "rx_queue_0_current",
1145 "tx_queue_0_current",
1146 "rx_queue_0_dirty",
1147 "tx_queue_0_dirty",
1148 "rx_queue_0_packets",
1149 "tx_queue_0_packets",
1150 "rx_queue_0_bytes",
1151 "tx_queue_0_bytes",
1152 "rx_queue_0_mcast_packets",
1153 "rx_queue_0_errors",
1154 "rx_queue_0_crc_errors",
1155 "rx_queue_0_frame_errors",
1156 "rx_queue_0_length_errors",
1157 "rx_queue_0_missed_errors",
1158 "rx_queue_0_over_errors",
1159
1160 "rx_queue_1_current",
1161 "tx_queue_1_current",
1162 "rx_queue_1_dirty",
1163 "tx_queue_1_dirty",
1164 "rx_queue_1_packets",
1165 "tx_queue_1_packets",
1166 "rx_queue_1_bytes",
1167 "tx_queue_1_bytes",
1168 "rx_queue_1_mcast_packets",
1169 "rx_queue_1_errors",
1170 "rx_queue_1_crc_errors",
b17c1d9a 1171 "rx_queue_1_frame_errors",
c156633f
SS		 1172 "rx_queue_1_length_errors",
1173 "rx_queue_1_missed_errors",
1174 "rx_queue_1_over_errors",
1175};
1176
1177#define RAVB_STATS_LEN ARRAY_SIZE(ravb_gstrings_stats)
1178
1179static int ravb_get_sset_count(struct net_device *netdev, int sset)
1180{
1181 switch (sset) {
1182 case ETH_SS_STATS:
1183 return RAVB_STATS_LEN;
1184 default:
1185 return -EOPNOTSUPP;
1186 }
1187}
1188
1189static void ravb_get_ethtool_stats(struct net_device *ndev,
1190 struct ethtool_stats *stats, u64 *data)
1191{
1192 struct ravb_private *priv = netdev_priv(ndev);
1193 int i = 0;
1194 int q;
1195
1196 /* Device-specific stats */
1197 for (q = RAVB_BE; q < NUM_RX_QUEUE; q++) {
1198 struct net_device_stats *stats = &priv->stats[q];
1199
1200 data[i++] = priv->cur_rx[q];
1201 data[i++] = priv->cur_tx[q];
1202 data[i++] = priv->dirty_rx[q];
1203 data[i++] = priv->dirty_tx[q];
1204 data[i++] = stats->rx_packets;
1205 data[i++] = stats->tx_packets;
1206 data[i++] = stats->rx_bytes;
1207 data[i++] = stats->tx_bytes;
1208 data[i++] = stats->multicast;
1209 data[i++] = stats->rx_errors;
1210 data[i++] = stats->rx_crc_errors;
1211 data[i++] = stats->rx_frame_errors;
1212 data[i++] = stats->rx_length_errors;
1213 data[i++] = stats->rx_missed_errors;
1214 data[i++] = stats->rx_over_errors;
1215 }
1216}
1217
1218static void ravb_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1219{
1220 switch (stringset) {
1221 case ETH_SS_STATS:
1222 memcpy(data, *ravb_gstrings_stats, sizeof(ravb_gstrings_stats));
1223 break;
1224 }
1225}
1226
1227static void ravb_get_ringparam(struct net_device *ndev,
1228 struct ethtool_ringparam *ring)
1229{
1230 struct ravb_private *priv = netdev_priv(ndev);
1231
1232 ring->rx_max_pending = BE_RX_RING_MAX;
1233 ring->tx_max_pending = BE_TX_RING_MAX;
1234 ring->rx_pending = priv->num_rx_ring[RAVB_BE];
1235 ring->tx_pending = priv->num_tx_ring[RAVB_BE];
1236}
1237
1238static int ravb_set_ringparam(struct net_device *ndev,
1239 struct ethtool_ringparam *ring)
1240{
1241 struct ravb_private *priv = netdev_priv(ndev);
1242 int error;
1243
1244 if (ring->tx_pending > BE_TX_RING_MAX ||
1245 ring->rx_pending > BE_RX_RING_MAX ||
1246 ring->tx_pending < BE_TX_RING_MIN ||
1247 ring->rx_pending < BE_RX_RING_MIN)
1248 return -EINVAL;
1249 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
1250 return -EINVAL;
1251
1252 if (netif_running(ndev)) {
1253 netif_device_detach(ndev);
a0d2f206 1254 /* Stop PTP Clock driver */
50bfd838
SS		 1255 if (priv->chip_id == RCAR_GEN2)
1256 ravb_ptp_stop(ndev);
c156633f
SS		 1257 /* Wait for DMA stopping */
1258 error = ravb_stop_dma(ndev);
1259 if (error) {
1260 netdev_err(ndev,
1261 "cannot set ringparam! Any AVB processes are still running?\n");
1262 return error;
1263 }
1264 synchronize_irq(ndev->irq);
1265
1266 /* Free all the skb's in the RX queue and the DMA buffers. */
1267 ravb_ring_free(ndev, RAVB_BE);
1268 ravb_ring_free(ndev, RAVB_NC);
1269 }
1270
1271 /* Set new parameters */
1272 priv->num_rx_ring[RAVB_BE] = ring->rx_pending;
1273 priv->num_tx_ring[RAVB_BE] = ring->tx_pending;
1274
1275 if (netif_running(ndev)) {
1276 error = ravb_dmac_init(ndev);
1277 if (error) {
1278 netdev_err(ndev,
1279 "%s: ravb_dmac_init() failed, error %d\n",
1280 __func__, error);
1281 return error;
1282 }
1283
1284 ravb_emac_init(ndev);
1285
a0d2f206 1286 /* Initialise PTP Clock driver */
50bfd838
SS		 1287 if (priv->chip_id == RCAR_GEN2)
1288 ravb_ptp_init(ndev, priv->pdev);
a0d2f206 1289
c156633f
SS		 1290 netif_device_attach(ndev);
1291 }
1292
1293 return 0;
1294}
1295
1296static int ravb_get_ts_info(struct net_device *ndev,
1297 struct ethtool_ts_info *info)
1298{
a0d2f206
SS		 1299 struct ravb_private *priv = netdev_priv(ndev);
1300
c156633f
SS		 1301 info->so_timestamping =
1302 SOF_TIMESTAMPING_TX_SOFTWARE |
1303 SOF_TIMESTAMPING_RX_SOFTWARE |
1304 SOF_TIMESTAMPING_SOFTWARE |
1305 SOF_TIMESTAMPING_TX_HARDWARE |
1306 SOF_TIMESTAMPING_RX_HARDWARE |
1307 SOF_TIMESTAMPING_RAW_HARDWARE;
1308 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON);
1309 info->rx_filters =
1310 (1 << HWTSTAMP_FILTER_NONE) |
1311 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
1312 (1 << HWTSTAMP_FILTER_ALL);
a0d2f206 1313 info->phc_index = ptp_clock_index(priv->ptp.clock);
c156633f
SS		 1314
1315 return 0;
1316}
1317
3e3d6477
NS		 1318static void ravb_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1319{
1320 struct ravb_private *priv = netdev_priv(ndev);
1321
ab104615
GU		 1322 wol->supported = WAKE_MAGIC;
1323 wol->wolopts = priv->wol_enabled ? WAKE_MAGIC : 0;
3e3d6477
NS		 1324}
1325
1326static int ravb_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1327{
1328 struct ravb_private *priv = netdev_priv(ndev);
1329
ab104615 1330 if (wol->wolopts & ~WAKE_MAGIC)
3e3d6477
NS		 1331 return -EOPNOTSUPP;
1332
1333 priv->wol_enabled = !!(wol->wolopts & WAKE_MAGIC);
1334
1335 device_set_wakeup_enable(&priv->pdev->dev, priv->wol_enabled);
1336
1337 return 0;
1338}
1339
c156633f 1340static const struct ethtool_ops ravb_ethtool_ops = {
c156633f
SS		 1341 .nway_reset = ravb_nway_reset,
1342 .get_msglevel = ravb_get_msglevel,
1343 .set_msglevel = ravb_set_msglevel,
1344 .get_link = ethtool_op_get_link,
1345 .get_strings = ravb_get_strings,
1346 .get_ethtool_stats = ravb_get_ethtool_stats,
1347 .get_sset_count = ravb_get_sset_count,
1348 .get_ringparam = ravb_get_ringparam,
1349 .set_ringparam = ravb_set_ringparam,
1350 .get_ts_info = ravb_get_ts_info,
04462f2a
PR		 1351 .get_link_ksettings = ravb_get_link_ksettings,
1352 .set_link_ksettings = ravb_set_link_ksettings,
3e3d6477
NS		 1353 .get_wol = ravb_get_wol,
1354 .set_wol = ravb_set_wol,
c156633f
SS		 1355};
1356
f51bdc23
KM		 1357static inline int ravb_hook_irq(unsigned int irq, irq_handler_t handler,
1358 struct net_device *ndev, struct device *dev,
1359 const char *ch)
1360{
1361 char *name;
1362 int error;
1363
1364 name = devm_kasprintf(dev, GFP_KERNEL, "%s:%s", ndev->name, ch);
1365 if (!name)
1366 return -ENOMEM;
1367 error = request_irq(irq, handler, 0, name, ndev);
1368 if (error)
1369 netdev_err(ndev, "cannot request IRQ %s\n", name);
1370
1371 return error;
1372}
1373
c156633f
SS		 1374/* Network device open function for Ethernet AVB */
1375static int ravb_open(struct net_device *ndev)
1376{
1377 struct ravb_private *priv = netdev_priv(ndev);
f51bdc23
KM		 1378 struct platform_device *pdev = priv->pdev;
1379 struct device *dev = &pdev->dev;
c156633f
SS		 1380 int error;
1381
1382 napi_enable(&priv->napi[RAVB_BE]);
1383 napi_enable(&priv->napi[RAVB_NC]);
1384
f51bdc23
KM		 1385 if (priv->chip_id == RCAR_GEN2) {
1386 error = request_irq(ndev->irq, ravb_interrupt, IRQF_SHARED,
1387 ndev->name, ndev);
22d4df8f
KM		 1388 if (error) {
1389 netdev_err(ndev, "cannot request IRQ\n");
f51bdc23 1390 goto out_napi_off;
22d4df8f 1391 }
f51bdc23
KM		 1392 } else {
1393 error = ravb_hook_irq(ndev->irq, ravb_multi_interrupt, ndev,
1394 dev, "ch22:multi");
1395 if (error)
1396 goto out_napi_off;
1397 error = ravb_hook_irq(priv->emac_irq, ravb_emac_interrupt, ndev,
1398 dev, "ch24:emac");
1399 if (error)
1400 goto out_free_irq;
1401 error = ravb_hook_irq(priv->rx_irqs[RAVB_BE], ravb_be_interrupt,
1402 ndev, dev, "ch0:rx_be");
1403 if (error)
1404 goto out_free_irq_emac;
1405 error = ravb_hook_irq(priv->tx_irqs[RAVB_BE], ravb_be_interrupt,
1406 ndev, dev, "ch18:tx_be");
1407 if (error)
1408 goto out_free_irq_be_rx;
1409 error = ravb_hook_irq(priv->rx_irqs[RAVB_NC], ravb_nc_interrupt,
1410 ndev, dev, "ch1:rx_nc");
1411 if (error)
1412 goto out_free_irq_be_tx;
1413 error = ravb_hook_irq(priv->tx_irqs[RAVB_NC], ravb_nc_interrupt,
1414 ndev, dev, "ch19:tx_nc");
1415 if (error)
1416 goto out_free_irq_nc_rx;
22d4df8f
KM		 1417 }
1418
c156633f
SS		 1419 /* Device init */
1420 error = ravb_dmac_init(ndev);
1421 if (error)
f51bdc23 1422 goto out_free_irq_nc_tx;
c156633f
SS		 1423 ravb_emac_init(ndev);
1424
a0d2f206 1425 /* Initialise PTP Clock driver */
f5d7837f
KM		 1426 if (priv->chip_id == RCAR_GEN2)
1427 ravb_ptp_init(ndev, priv->pdev);
a0d2f206 1428
c156633f
SS		 1429 netif_tx_start_all_queues(ndev);
1430
1431 /* PHY control start */
1432 error = ravb_phy_start(ndev);
1433 if (error)
a0d2f206 1434 goto out_ptp_stop;
c156633f
SS		 1435
1436 return 0;
1437
a0d2f206
SS		 1438out_ptp_stop:
1439 /* Stop PTP Clock driver */
f5d7837f
KM		 1440 if (priv->chip_id == RCAR_GEN2)
1441 ravb_ptp_stop(ndev);
f51bdc23
KM		 1442out_free_irq_nc_tx:
1443 if (priv->chip_id == RCAR_GEN2)
1444 goto out_free_irq;
1445 free_irq(priv->tx_irqs[RAVB_NC], ndev);
1446out_free_irq_nc_rx:
1447 free_irq(priv->rx_irqs[RAVB_NC], ndev);
1448out_free_irq_be_tx:
1449 free_irq(priv->tx_irqs[RAVB_BE], ndev);
1450out_free_irq_be_rx:
1451 free_irq(priv->rx_irqs[RAVB_BE], ndev);
1452out_free_irq_emac:
1453 free_irq(priv->emac_irq, ndev);
c156633f
SS		 1454out_free_irq:
1455 free_irq(ndev->irq, ndev);
1456out_napi_off:
1457 napi_disable(&priv->napi[RAVB_NC]);
1458 napi_disable(&priv->napi[RAVB_BE]);
1459 return error;
1460}
1461
1462/* Timeout function for Ethernet AVB */
1463static void ravb_tx_timeout(struct net_device *ndev)
1464{
1465 struct ravb_private *priv = netdev_priv(ndev);
1466
1467 netif_err(priv, tx_err, ndev,
1468 "transmit timed out, status %08x, resetting...\n",
1469 ravb_read(ndev, ISS));
1470
1471 /* tx_errors count up */
1472 ndev->stats.tx_errors++;
1473
1474 schedule_work(&priv->work);
1475}
1476
1477static void ravb_tx_timeout_work(struct work_struct *work)
1478{
1479 struct ravb_private *priv = container_of(work, struct ravb_private,
1480 work);
1481 struct net_device *ndev = priv->ndev;
1482
1483 netif_tx_stop_all_queues(ndev);
1484
a0d2f206 1485 /* Stop PTP Clock driver */
50bfd838
SS		 1486 if (priv->chip_id == RCAR_GEN2)
1487 ravb_ptp_stop(ndev);
a0d2f206 1488
c156633f
SS		 1489 /* Wait for DMA stopping */
1490 ravb_stop_dma(ndev);
1491
1492 ravb_ring_free(ndev, RAVB_BE);
1493 ravb_ring_free(ndev, RAVB_NC);
1494
1495 /* Device init */
1496 ravb_dmac_init(ndev);
1497 ravb_emac_init(ndev);
1498
a0d2f206 1499 /* Initialise PTP Clock driver */
50bfd838
SS		 1500 if (priv->chip_id == RCAR_GEN2)
1501 ravb_ptp_init(ndev, priv->pdev);
a0d2f206 1502
c156633f
SS		 1503 netif_tx_start_all_queues(ndev);
1504}
1505
1506/* Packet transmit function for Ethernet AVB */
1507static netdev_tx_t ravb_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1508{
1509 struct ravb_private *priv = netdev_priv(ndev);
c156633f 1510 u16 q = skb_get_queue_mapping(skb);
aad0d51e 1511 struct ravb_tstamp_skb *ts_skb;
c156633f
SS		 1512 struct ravb_tx_desc *desc;
1513 unsigned long flags;
1514 u32 dma_addr;
1515 void *buffer;
1516 u32 entry;
2f45d190 1517 u32 len;
c156633f
SS		 1518
1519 spin_lock_irqsave(&priv->lock, flags);
2f45d190
SS		 1520 if (priv->cur_tx[q] - priv->dirty_tx[q] > (priv->num_tx_ring[q] - 1) *
1521 NUM_TX_DESC) {
c156633f
SS		 1522 netif_err(priv, tx_queued, ndev,
1523 "still transmitting with the full ring!\n");
1524 netif_stop_subqueue(ndev, q);
1525 spin_unlock_irqrestore(&priv->lock, flags);
1526 return NETDEV_TX_BUSY;
1527 }
c156633f
SS		 1528
1529 if (skb_put_padto(skb, ETH_ZLEN))
9199cb76
DC		 1530 goto exit;
1531
1532 entry = priv->cur_tx[q] % (priv->num_tx_ring[q] * NUM_TX_DESC);
1533 priv->tx_skb[q][entry / NUM_TX_DESC] = skb;
c156633f 1534
2f45d190
SS		 1535 buffer = PTR_ALIGN(priv->tx_align[q], DPTR_ALIGN) +
1536 entry / NUM_TX_DESC * DPTR_ALIGN;
1537 len = PTR_ALIGN(skb->data, DPTR_ALIGN) - skb->data;
8ec3e8a1
MN		 1538 /* Zero length DMA descriptors are problematic as they seem to
1539 * terminate DMA transfers. Avoid them by simply using a length of
1540 * DPTR_ALIGN (4) when skb data is aligned to DPTR_ALIGN.
1541 *
1542 * As skb is guaranteed to have at least ETH_ZLEN (60) bytes of
1543 * data by the call to skb_put_padto() above this is safe with
1544 * respect to both the length of the first DMA descriptor (len)
1545 * overflowing the available data and the length of the second DMA
1546 * descriptor (skb->len - len) being negative.
1547 */
1548 if (len == 0)
1549 len = DPTR_ALIGN;
1550
2f45d190 1551 memcpy(buffer, skb->data, len);
e2dbb33a
KM		 1552 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, DMA_TO_DEVICE);
1553 if (dma_mapping_error(ndev->dev.parent, dma_addr))
c156633f 1554 goto drop;
2f45d190
SS		 1555
1556 desc = &priv->tx_ring[q][entry];
1557 desc->ds_tagl = cpu_to_le16(len);
1558 desc->dptr = cpu_to_le32(dma_addr);
1559
1560 buffer = skb->data + len;
1561 len = skb->len - len;
e2dbb33a
KM		 1562 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, DMA_TO_DEVICE);
1563 if (dma_mapping_error(ndev->dev.parent, dma_addr))
2f45d190
SS		 1564 goto unmap;
1565
1566 desc++;
1567 desc->ds_tagl = cpu_to_le16(len);
c156633f
SS		 1568 desc->dptr = cpu_to_le32(dma_addr);
1569
1570 /* TX timestamp required */
1571 if (q == RAVB_NC) {
1572 ts_skb = kmalloc(sizeof(*ts_skb), GFP_ATOMIC);
1573 if (!ts_skb) {
2f45d190 1574 desc--;
e2dbb33a 1575 dma_unmap_single(ndev->dev.parent, dma_addr, len,
c156633f 1576 DMA_TO_DEVICE);
2f45d190 1577 goto unmap;
c156633f 1578 }
3c7a3108 1579 ts_skb->skb = skb_get(skb);
c156633f
SS		 1580 ts_skb->tag = priv->ts_skb_tag++;
1581 priv->ts_skb_tag &= 0x3ff;
1582 list_add_tail(&ts_skb->list, &priv->ts_skb_list);
1583
1584 /* TAG and timestamp required flag */
1585 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
c156633f
SS		 1586 desc->tagh_tsr = (ts_skb->tag >> 4) | TX_TSR;
1587 desc->ds_tagl |= le16_to_cpu(ts_skb->tag << 12);
1588 }
1589
d7be81a5 1590 skb_tx_timestamp(skb);
c156633f
SS		 1591 /* Descriptor type must be set after all the above writes */
1592 dma_wmb();
2f45d190
SS		 1593 desc->die_dt = DT_FEND;
1594 desc--;
1595 desc->die_dt = DT_FSTART;
c156633f 1596
568b3ce7 1597 ravb_modify(ndev, TCCR, TCCR_TSRQ0 << q, TCCR_TSRQ0 << q);
c156633f 1598
2f45d190
SS		 1599 priv->cur_tx[q] += NUM_TX_DESC;
1600 if (priv->cur_tx[q] - priv->dirty_tx[q] >
a47b70ea
KM		 1601 (priv->num_tx_ring[q] - 1) * NUM_TX_DESC &&
1602 !ravb_tx_free(ndev, q, true))
c156633f
SS		 1603 netif_stop_subqueue(ndev, q);
1604
1605exit:
1606 mmiowb();
1607 spin_unlock_irqrestore(&priv->lock, flags);
1608 return NETDEV_TX_OK;
1609
2f45d190 1610unmap:
e2dbb33a 1611 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
2f45d190 1612 le16_to_cpu(desc->ds_tagl), DMA_TO_DEVICE);
c156633f
SS		 1613drop:
1614 dev_kfree_skb_any(skb);
2f45d190 1615 priv->tx_skb[q][entry / NUM_TX_DESC] = NULL;
c156633f
SS		 1616 goto exit;
1617}
1618
1619static u16 ravb_select_queue(struct net_device *ndev, struct sk_buff *skb,
1620 void *accel_priv, select_queue_fallback_t fallback)
1621{
1622 /* If skb needs TX timestamp, it is handled in network control queue */
1623 return (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) ? RAVB_NC :
1624 RAVB_BE;
1625
1626}
1627
1628static struct net_device_stats *ravb_get_stats(struct net_device *ndev)
1629{
1630 struct ravb_private *priv = netdev_priv(ndev);
1631 struct net_device_stats *nstats, *stats0, *stats1;
1632
1633 nstats = &ndev->stats;
1634 stats0 = &priv->stats[RAVB_BE];
1635 stats1 = &priv->stats[RAVB_NC];
1636
1637 nstats->tx_dropped += ravb_read(ndev, TROCR);
1638 ravb_write(ndev, 0, TROCR); /* (write clear) */
1639 nstats->collisions += ravb_read(ndev, CDCR);
1640 ravb_write(ndev, 0, CDCR); /* (write clear) */
1641 nstats->tx_carrier_errors += ravb_read(ndev, LCCR);
1642 ravb_write(ndev, 0, LCCR); /* (write clear) */
1643
1644 nstats->tx_carrier_errors += ravb_read(ndev, CERCR);
1645 ravb_write(ndev, 0, CERCR); /* (write clear) */
1646 nstats->tx_carrier_errors += ravb_read(ndev, CEECR);
1647 ravb_write(ndev, 0, CEECR); /* (write clear) */
1648
1649 nstats->rx_packets = stats0->rx_packets + stats1->rx_packets;
1650 nstats->tx_packets = stats0->tx_packets + stats1->tx_packets;
1651 nstats->rx_bytes = stats0->rx_bytes + stats1->rx_bytes;
1652 nstats->tx_bytes = stats0->tx_bytes + stats1->tx_bytes;
1653 nstats->multicast = stats0->multicast + stats1->multicast;
1654 nstats->rx_errors = stats0->rx_errors + stats1->rx_errors;
1655 nstats->rx_crc_errors = stats0->rx_crc_errors + stats1->rx_crc_errors;
1656 nstats->rx_frame_errors =
1657 stats0->rx_frame_errors + stats1->rx_frame_errors;
1658 nstats->rx_length_errors =
1659 stats0->rx_length_errors + stats1->rx_length_errors;
1660 nstats->rx_missed_errors =
1661 stats0->rx_missed_errors + stats1->rx_missed_errors;
1662 nstats->rx_over_errors =
1663 stats0->rx_over_errors + stats1->rx_over_errors;
1664
1665 return nstats;
1666}
1667
1668/* Update promiscuous bit */
1669static void ravb_set_rx_mode(struct net_device *ndev)
1670{
1671 struct ravb_private *priv = netdev_priv(ndev);
1672 unsigned long flags;
c156633f
SS		 1673
1674 spin_lock_irqsave(&priv->lock, flags);
568b3ce7
SS		 1675 ravb_modify(ndev, ECMR, ECMR_PRM,
1676 ndev->flags & IFF_PROMISC ? ECMR_PRM : 0);
c156633f
SS		 1677 mmiowb();
1678 spin_unlock_irqrestore(&priv->lock, flags);
1679}
1680
1681/* Device close function for Ethernet AVB */
1682static int ravb_close(struct net_device *ndev)
1683{
9f70eb33 1684 struct device_node *np = ndev->dev.parent->of_node;
c156633f
SS		 1685 struct ravb_private *priv = netdev_priv(ndev);
1686 struct ravb_tstamp_skb *ts_skb, *ts_skb2;
1687
1688 netif_tx_stop_all_queues(ndev);
1689
1690 /* Disable interrupts by clearing the interrupt masks. */
1691 ravb_write(ndev, 0, RIC0);
c156633f
SS		 1692 ravb_write(ndev, 0, RIC2);
1693 ravb_write(ndev, 0, TIC);
1694
a0d2f206 1695 /* Stop PTP Clock driver */
f5d7837f
KM		 1696 if (priv->chip_id == RCAR_GEN2)
1697 ravb_ptp_stop(ndev);
a0d2f206 1698
c156633f
SS		 1699 /* Set the config mode to stop the AVB-DMAC's processes */
1700 if (ravb_stop_dma(ndev) < 0)
1701 netdev_err(ndev,
1702 "device will be stopped after h/w processes are done.\n");
1703
1704 /* Clear the timestamp list */
1705 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, list) {
1706 list_del(&ts_skb->list);
3c7a3108 1707 kfree_skb(ts_skb->skb);
c156633f
SS		 1708 kfree(ts_skb);
1709 }
1710
1711 /* PHY disconnect */
0f635171
PR		 1712 if (ndev->phydev) {
1713 phy_stop(ndev->phydev);
1714 phy_disconnect(ndev->phydev);
9f70eb33
JH		 1715 if (of_phy_is_fixed_link(np))
1716 of_phy_deregister_fixed_link(np);
c156633f
SS		 1717 }
1718
ccf92824
GU		 1719 if (priv->chip_id != RCAR_GEN2) {
1720 free_irq(priv->tx_irqs[RAVB_NC], ndev);
1721 free_irq(priv->rx_irqs[RAVB_NC], ndev);
1722 free_irq(priv->tx_irqs[RAVB_BE], ndev);
1723 free_irq(priv->rx_irqs[RAVB_BE], ndev);
7fa816b9 1724 free_irq(priv->emac_irq, ndev);
ccf92824 1725 }
c156633f
SS		 1726 free_irq(ndev->irq, ndev);
1727
1728 napi_disable(&priv->napi[RAVB_NC]);
1729 napi_disable(&priv->napi[RAVB_BE]);
1730
1731 /* Free all the skb's in the RX queue and the DMA buffers. */
1732 ravb_ring_free(ndev, RAVB_BE);
1733 ravb_ring_free(ndev, RAVB_NC);
1734
1735 return 0;
1736}
1737
1738static int ravb_hwtstamp_get(struct net_device *ndev, struct ifreq *req)
1739{
1740 struct ravb_private *priv = netdev_priv(ndev);
1741 struct hwtstamp_config config;
1742
1743 config.flags = 0;
1744 config.tx_type = priv->tstamp_tx_ctrl ? HWTSTAMP_TX_ON :
1745 HWTSTAMP_TX_OFF;
1746 if (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE_V2_L2_EVENT)
1747 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
1748 else if (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE_ALL)
1749 config.rx_filter = HWTSTAMP_FILTER_ALL;
1750 else
1751 config.rx_filter = HWTSTAMP_FILTER_NONE;
1752
1753 return copy_to_user(req->ifr_data, &config, sizeof(config)) ?
1754 -EFAULT : 0;
1755}
1756
1757/* Control hardware time stamping */
1758static int ravb_hwtstamp_set(struct net_device *ndev, struct ifreq *req)
1759{
1760 struct ravb_private *priv = netdev_priv(ndev);
1761 struct hwtstamp_config config;
1762 u32 tstamp_rx_ctrl = RAVB_RXTSTAMP_ENABLED;
1763 u32 tstamp_tx_ctrl;
1764
1765 if (copy_from_user(&config, req->ifr_data, sizeof(config)))
1766 return -EFAULT;
1767
1768 /* Reserved for future extensions */
1769 if (config.flags)
1770 return -EINVAL;
1771
1772 switch (config.tx_type) {
1773 case HWTSTAMP_TX_OFF:
1774 tstamp_tx_ctrl = 0;
1775 break;
1776 case HWTSTAMP_TX_ON:
1777 tstamp_tx_ctrl = RAVB_TXTSTAMP_ENABLED;
1778 break;
1779 default:
1780 return -ERANGE;
1781 }
1782
1783 switch (config.rx_filter) {
1784 case HWTSTAMP_FILTER_NONE:
1785 tstamp_rx_ctrl = 0;
1786 break;
1787 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1788 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_V2_L2_EVENT;
1789 break;
1790 default:
1791 config.rx_filter = HWTSTAMP_FILTER_ALL;
1792 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_ALL;
1793 }
1794
1795 priv->tstamp_tx_ctrl = tstamp_tx_ctrl;
1796 priv->tstamp_rx_ctrl = tstamp_rx_ctrl;
1797
1798 return copy_to_user(req->ifr_data, &config, sizeof(config)) ?
1799 -EFAULT : 0;
1800}
1801
1802/* ioctl to device function */
1803static int ravb_do_ioctl(struct net_device *ndev, struct ifreq *req, int cmd)
1804{
0f635171 1805 struct phy_device *phydev = ndev->phydev;
c156633f
SS		 1806
1807 if (!netif_running(ndev))
1808 return -EINVAL;
1809
1810 if (!phydev)
1811 return -ENODEV;
1812
1813 switch (cmd) {
1814 case SIOCGHWTSTAMP:
1815 return ravb_hwtstamp_get(ndev, req);
1816 case SIOCSHWTSTAMP:
1817 return ravb_hwtstamp_set(ndev, req);
1818 }
1819
1820 return phy_mii_ioctl(phydev, req, cmd);
1821}
1822
4d86d381
SH		 1823static void ravb_set_rx_csum(struct net_device *ndev, bool enable)
1824{
1825 struct ravb_private *priv = netdev_priv(ndev);
1826 unsigned long flags;
1827
1828 spin_lock_irqsave(&priv->lock, flags);
1829
1830 /* Disable TX and RX */
1831 ravb_rcv_snd_disable(ndev);
1832
1833 /* Modify RX Checksum setting */
1834 ravb_modify(ndev, ECMR, ECMR_RCSC, enable ? ECMR_RCSC : 0);
1835
1836 /* Enable TX and RX */
1837 ravb_rcv_snd_enable(ndev);
1838
1839 spin_unlock_irqrestore(&priv->lock, flags);
1840}
1841
1842static int ravb_set_features(struct net_device *ndev,
1843 netdev_features_t features)
1844{
1845 netdev_features_t changed = ndev->features ^ features;
1846
1847 if (changed & NETIF_F_RXCSUM)
1848 ravb_set_rx_csum(ndev, features & NETIF_F_RXCSUM);
1849
1850 ndev->features = features;
1851
1852 return 0;
1853}
1854
c156633f
SS		 1855static const struct net_device_ops ravb_netdev_ops = {
1856 .ndo_open = ravb_open,
1857 .ndo_stop = ravb_close,
1858 .ndo_start_xmit = ravb_start_xmit,
1859 .ndo_select_queue = ravb_select_queue,
1860 .ndo_get_stats = ravb_get_stats,
1861 .ndo_set_rx_mode = ravb_set_rx_mode,
1862 .ndo_tx_timeout = ravb_tx_timeout,
1863 .ndo_do_ioctl = ravb_do_ioctl,
1864 .ndo_validate_addr = eth_validate_addr,
1865 .ndo_set_mac_address = eth_mac_addr,
4d86d381 1866 .ndo_set_features = ravb_set_features,
c156633f
SS		 1867};
1868
1869/* MDIO bus init function */
1870static int ravb_mdio_init(struct ravb_private *priv)
1871{
1872 struct platform_device *pdev = priv->pdev;
1873 struct device *dev = &pdev->dev;
1874 int error;
1875
1876 /* Bitbang init */
1877 priv->mdiobb.ops = &bb_ops;
1878
1879 /* MII controller setting */
1880 priv->mii_bus = alloc_mdio_bitbang(&priv->mdiobb);
1881 if (!priv->mii_bus)
1882 return -ENOMEM;
1883
1884 /* Hook up MII support for ethtool */
1885 priv->mii_bus->name = "ravb_mii";
1886 priv->mii_bus->parent = dev;
1887 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
1888 pdev->name, pdev->id);
1889
1890 /* Register MDIO bus */
1891 error = of_mdiobus_register(priv->mii_bus, dev->of_node);
1892 if (error)
1893 goto out_free_bus;
1894
1895 return 0;
1896
1897out_free_bus:
1898 free_mdio_bitbang(priv->mii_bus);
1899 return error;
1900}
1901
1902/* MDIO bus release function */
1903static int ravb_mdio_release(struct ravb_private *priv)
1904{
1905 /* Unregister mdio bus */
1906 mdiobus_unregister(priv->mii_bus);
1907
1908 /* Free bitbang info */
1909 free_mdio_bitbang(priv->mii_bus);
1910
1911 return 0;
1912}
1913
22d4df8f
KM		 1914static const struct of_device_id ravb_match_table[] = {
1915 { .compatible = "renesas,etheravb-r8a7790", .data = (void *)RCAR_GEN2 },
1916 { .compatible = "renesas,etheravb-r8a7794", .data = (void *)RCAR_GEN2 },
0e874361 1917 { .compatible = "renesas,etheravb-rcar-gen2", .data = (void *)RCAR_GEN2 },
22d4df8f 1918 { .compatible = "renesas,etheravb-r8a7795", .data = (void *)RCAR_GEN3 },
0e874361 1919 { .compatible = "renesas,etheravb-rcar-gen3", .data = (void *)RCAR_GEN3 },
22d4df8f
KM		 1920 { }
1921};
1922MODULE_DEVICE_TABLE(of, ravb_match_table);
1923
b3d39a88
SH		 1924static int ravb_set_gti(struct net_device *ndev)
1925{
ab104615 1926 struct ravb_private *priv = netdev_priv(ndev);
b3d39a88 1927 struct device *dev = ndev->dev.parent;
b3d39a88 1928 unsigned long rate;
b3d39a88
SH		 1929 uint64_t inc;
1930
ab104615 1931 rate = clk_get_rate(priv->clk);
a6d37131
WS		 1932 if (!rate)
1933 return -EINVAL;
1934
b3d39a88
SH		 1935 inc = 1000000000ULL << 20;
1936 do_div(inc, rate);
1937
1938 if (inc < GTI_TIV_MIN || inc > GTI_TIV_MAX) {
1939 dev_err(dev, "gti.tiv increment 0x%llx is outside the range 0x%x - 0x%x\n",
1940 inc, GTI_TIV_MIN, GTI_TIV_MAX);
1941 return -EINVAL;
1942 }
1943
1944 ravb_write(ndev, inc, GTI);
1945
1946 return 0;
1947}
1948
0184165b
NS		 1949static void ravb_set_config_mode(struct net_device *ndev)
1950{
1951 struct ravb_private *priv = netdev_priv(ndev);
1952
1953 if (priv->chip_id == RCAR_GEN2) {
1954 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG);
1955 /* Set CSEL value */
1956 ravb_modify(ndev, CCC, CCC_CSEL, CCC_CSEL_HPB);
1957 } else {
1958 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG |
1959 CCC_GAC | CCC_CSEL_HPB);
1960 }
1961}
1962
61fccb2d
KM		 1963/* Set tx and rx clock internal delay modes */
1964static void ravb_set_delay_mode(struct net_device *ndev)
1965{
1966 struct ravb_private *priv = netdev_priv(ndev);
1967 int set = 0;
1968
1969 if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
1970 priv->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID)
1971 set |= APSR_DM_RDM;
1972
1973 if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
1974 priv->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID)
1975 set |= APSR_DM_TDM;
1976
1977 ravb_modify(ndev, APSR, APSR_DM, set);
1978}
1979
c156633f
SS		 1980static int ravb_probe(struct platform_device *pdev)
1981{
1982 struct device_node *np = pdev->dev.of_node;
1983 struct ravb_private *priv;
22d4df8f 1984 enum ravb_chip_id chip_id;
c156633f
SS		 1985 struct net_device *ndev;
1986 int error, irq, q;
1987 struct resource *res;
f51bdc23 1988 int i;
c156633f
SS		 1989
1990 if (!np) {
1991 dev_err(&pdev->dev,
1992 "this driver is required to be instantiated from device tree\n");
1993 return -EINVAL;
1994 }
1995
1996 /* Get base address */
1997 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1998 if (!res) {
1999 dev_err(&pdev->dev, "invalid resource\n");
2000 return -EINVAL;
2001 }
2002
2003 ndev = alloc_etherdev_mqs(sizeof(struct ravb_private),
2004 NUM_TX_QUEUE, NUM_RX_QUEUE);
2005 if (!ndev)
2006 return -ENOMEM;
2007
4d86d381
SH		 2008 ndev->features = NETIF_F_RXCSUM;
2009 ndev->hw_features = NETIF_F_RXCSUM;
2010
c156633f
SS		 2011 pm_runtime_enable(&pdev->dev);
2012 pm_runtime_get_sync(&pdev->dev);
2013
2014 /* The Ether-specific entries in the device structure. */
2015 ndev->base_addr = res->start;
22d4df8f 2016
e8668630 2017 chip_id = (enum ravb_chip_id)of_device_get_match_data(&pdev->dev);
22d4df8f
KM		 2018
2019 if (chip_id == RCAR_GEN3)
2020 irq = platform_get_irq_byname(pdev, "ch22");
2021 else
2022 irq = platform_get_irq(pdev, 0);
c156633f 2023 if (irq < 0) {
f375339e 2024 error = irq;
c156633f
SS		 2025 goto out_release;
2026 }
2027 ndev->irq = irq;
2028
2029 SET_NETDEV_DEV(ndev, &pdev->dev);
2030
2031 priv = netdev_priv(ndev);
2032 priv->ndev = ndev;
2033 priv->pdev = pdev;
2034 priv->num_tx_ring[RAVB_BE] = BE_TX_RING_SIZE;
2035 priv->num_rx_ring[RAVB_BE] = BE_RX_RING_SIZE;
2036 priv->num_tx_ring[RAVB_NC] = NC_TX_RING_SIZE;
2037 priv->num_rx_ring[RAVB_NC] = NC_RX_RING_SIZE;
2038 priv->addr = devm_ioremap_resource(&pdev->dev, res);
2039 if (IS_ERR(priv->addr)) {
2040 error = PTR_ERR(priv->addr);
2041 goto out_release;
2042 }
2043
2044 spin_lock_init(&priv->lock);
2045 INIT_WORK(&priv->work, ravb_tx_timeout_work);
2046
2047 priv->phy_interface = of_get_phy_mode(np);
2048
2049 priv->no_avb_link = of_property_read_bool(np, "renesas,no-ether-link");
2050 priv->avb_link_active_low =
2051 of_property_read_bool(np, "renesas,ether-link-active-low");
2052
22d4df8f
KM		 2053 if (chip_id == RCAR_GEN3) {
2054 irq = platform_get_irq_byname(pdev, "ch24");
2055 if (irq < 0) {
2056 error = irq;
2057 goto out_release;
2058 }
2059 priv->emac_irq = irq;
f51bdc23
KM		 2060 for (i = 0; i < NUM_RX_QUEUE; i++) {
2061 irq = platform_get_irq_byname(pdev, ravb_rx_irqs[i]);
2062 if (irq < 0) {
2063 error = irq;
2064 goto out_release;
2065 }
2066 priv->rx_irqs[i] = irq;
2067 }
2068 for (i = 0; i < NUM_TX_QUEUE; i++) {
2069 irq = platform_get_irq_byname(pdev, ravb_tx_irqs[i]);
2070 if (irq < 0) {
2071 error = irq;
2072 goto out_release;
2073 }
2074 priv->tx_irqs[i] = irq;
2075 }
22d4df8f
KM		 2076 }
2077
2078 priv->chip_id = chip_id;
2079
3e3d6477 2080 priv->clk = devm_clk_get(&pdev->dev, NULL);
ab104615
GU		 2081 if (IS_ERR(priv->clk)) {
2082 error = PTR_ERR(priv->clk);
2083 goto out_release;
2084 }
3e3d6477 2085
c156633f
SS		 2086 /* Set function */
2087 ndev->netdev_ops = &ravb_netdev_ops;
2088 ndev->ethtool_ops = &ravb_ethtool_ops;
2089
2090 /* Set AVB config mode */
0184165b 2091 ravb_set_config_mode(ndev);
c156633f 2092
c156633f 2093 /* Set GTI value */
b3d39a88
SH		 2094 error = ravb_set_gti(ndev);
2095 if (error)
2096 goto out_release;
c156633f
SS		 2097
2098 /* Request GTI loading */
568b3ce7 2099 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI);
c156633f 2100
61fccb2d
KM		 2101 if (priv->chip_id != RCAR_GEN2)
2102 ravb_set_delay_mode(ndev);
2103
c156633f
SS		 2104 /* Allocate descriptor base address table */
2105 priv->desc_bat_size = sizeof(struct ravb_desc) * DBAT_ENTRY_NUM;
e2dbb33a 2106 priv->desc_bat = dma_alloc_coherent(ndev->dev.parent, priv->desc_bat_size,
c156633f
SS		 2107 &priv->desc_bat_dma, GFP_KERNEL);
2108 if (!priv->desc_bat) {
c4511132 2109 dev_err(&pdev->dev,
c156633f
SS		 2110 "Cannot allocate desc base address table (size %d bytes)\n",
2111 priv->desc_bat_size);
2112 error = -ENOMEM;
2113 goto out_release;
2114 }
2115 for (q = RAVB_BE; q < DBAT_ENTRY_NUM; q++)
2116 priv->desc_bat[q].die_dt = DT_EOS;
2117 ravb_write(ndev, priv->desc_bat_dma, DBAT);
2118
2119 /* Initialise HW timestamp list */
2120 INIT_LIST_HEAD(&priv->ts_skb_list);
2121
f5d7837f
KM		 2122 /* Initialise PTP Clock driver */
2123 if (chip_id != RCAR_GEN2)
2124 ravb_ptp_init(ndev, pdev);
2125
c156633f
SS		 2126 /* Debug message level */
2127 priv->msg_enable = RAVB_DEF_MSG_ENABLE;
2128
2129 /* Read and set MAC address */
2130 ravb_read_mac_address(ndev, of_get_mac_address(np));
2131 if (!is_valid_ether_addr(ndev->dev_addr)) {
2132 dev_warn(&pdev->dev,
2133 "no valid MAC address supplied, using a random one\n");
2134 eth_hw_addr_random(ndev);
2135 }
2136
2137 /* MDIO bus init */
2138 error = ravb_mdio_init(priv);
2139 if (error) {
c4511132 2140 dev_err(&pdev->dev, "failed to initialize MDIO\n");
c156633f
SS		 2141 goto out_dma_free;
2142 }
2143
2144 netif_napi_add(ndev, &priv->napi[RAVB_BE], ravb_poll, 64);
2145 netif_napi_add(ndev, &priv->napi[RAVB_NC], ravb_poll, 64);
2146
2147 /* Network device register */
2148 error = register_netdev(ndev);
2149 if (error)
2150 goto out_napi_del;
2151
ab104615 2152 device_set_wakeup_capable(&pdev->dev, 1);
3e3d6477 2153
c156633f
SS		 2154 /* Print device information */
2155 netdev_info(ndev, "Base address at %#x, %pM, IRQ %d.\n",
2156 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
2157
2158 platform_set_drvdata(pdev, ndev);
2159
2160 return 0;
2161
2162out_napi_del:
2163 netif_napi_del(&priv->napi[RAVB_NC]);
2164 netif_napi_del(&priv->napi[RAVB_BE]);
2165 ravb_mdio_release(priv);
2166out_dma_free:
e2dbb33a 2167 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat,
c156633f 2168 priv->desc_bat_dma);
f5d7837f
KM		 2169
2170 /* Stop PTP Clock driver */
2171 if (chip_id != RCAR_GEN2)
2172 ravb_ptp_stop(ndev);
c156633f
SS		 2173out_release:
2174 if (ndev)
2175 free_netdev(ndev);
2176
2177 pm_runtime_put(&pdev->dev);
2178 pm_runtime_disable(&pdev->dev);
2179 return error;
2180}
2181
2182static int ravb_remove(struct platform_device *pdev)
2183{
2184 struct net_device *ndev = platform_get_drvdata(pdev);
2185 struct ravb_private *priv = netdev_priv(ndev);
2186
f5d7837f
KM		 2187 /* Stop PTP Clock driver */
2188 if (priv->chip_id != RCAR_GEN2)
2189 ravb_ptp_stop(ndev);
2190
e2dbb33a 2191 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat,
c156633f
SS		 2192 priv->desc_bat_dma);
2193 /* Set reset mode */
2194 ravb_write(ndev, CCC_OPC_RESET, CCC);
2195 pm_runtime_put_sync(&pdev->dev);
2196 unregister_netdev(ndev);
2197 netif_napi_del(&priv->napi[RAVB_NC]);
2198 netif_napi_del(&priv->napi[RAVB_BE]);
2199 ravb_mdio_release(priv);
2200 pm_runtime_disable(&pdev->dev);
2201 free_netdev(ndev);
2202 platform_set_drvdata(pdev, NULL);
2203
2204 return 0;
2205}
2206
3e3d6477
NS		 2207static int ravb_wol_setup(struct net_device *ndev)
2208{
2209 struct ravb_private *priv = netdev_priv(ndev);
2210
2211 /* Disable interrupts by clearing the interrupt masks. */
2212 ravb_write(ndev, 0, RIC0);
2213 ravb_write(ndev, 0, RIC2);
2214 ravb_write(ndev, 0, TIC);
2215
2216 /* Only allow ECI interrupts */
2217 synchronize_irq(priv->emac_irq);
2218 napi_disable(&priv->napi[RAVB_NC]);
2219 napi_disable(&priv->napi[RAVB_BE]);
2220 ravb_write(ndev, ECSIPR_MPDIP, ECSIPR);
2221
2222 /* Enable MagicPacket */
2223 ravb_modify(ndev, ECMR, ECMR_MPDE, ECMR_MPDE);
2224
2225 /* Increased clock usage so device won't be suspended */
2226 clk_enable(priv->clk);
2227
2228 return enable_irq_wake(priv->emac_irq);
2229}
2230
2231static int ravb_wol_restore(struct net_device *ndev)
2232{
2233 struct ravb_private *priv = netdev_priv(ndev);
2234 int ret;
2235
2236 napi_enable(&priv->napi[RAVB_NC]);
2237 napi_enable(&priv->napi[RAVB_BE]);
2238
2239 /* Disable MagicPacket */
2240 ravb_modify(ndev, ECMR, ECMR_MPDE, 0);
2241
2242 ret = ravb_close(ndev);
2243 if (ret < 0)
2244 return ret;
2245
2246 /* Restore clock usage count */
2247 clk_disable(priv->clk);
2248
2249 return disable_irq_wake(priv->emac_irq);
2250}
2251
1ddcf41f 2252static int __maybe_unused ravb_suspend(struct device *dev)
0184165b
NS		 2253{
2254 struct net_device *ndev = dev_get_drvdata(dev);
3e3d6477
NS		 2255 struct ravb_private *priv = netdev_priv(ndev);
2256 int ret;
0184165b 2257
3e3d6477
NS		 2258 if (!netif_running(ndev))
2259 return 0;
2260
2261 netif_device_detach(ndev);
2262
2263 if (priv->wol_enabled)
2264 ret = ravb_wol_setup(ndev);
2265 else
0184165b 2266 ret = ravb_close(ndev);
0184165b
NS		 2267
2268 return ret;
2269}
2270
1ddcf41f 2271static int __maybe_unused ravb_resume(struct device *dev)
0184165b
NS		 2272{
2273 struct net_device *ndev = dev_get_drvdata(dev);
2274 struct ravb_private *priv = netdev_priv(ndev);
2275 int ret = 0;
2276
6b782f43
GU		 2277 /* If WoL is enabled set reset mode to rearm the WoL logic */
2278 if (priv->wol_enabled)
3e3d6477
NS		 2279 ravb_write(ndev, CCC_OPC_RESET, CCC);
2280
0184165b
NS		 2281 /* All register have been reset to default values.
2282 * Restore all registers which where setup at probe time and
2283 * reopen device if it was running before system suspended.
2284 */
2285
2286 /* Set AVB config mode */
2287 ravb_set_config_mode(ndev);
2288
2289 /* Set GTI value */
2290 ret = ravb_set_gti(ndev);
2291 if (ret)
2292 return ret;
2293
2294 /* Request GTI loading */
2295 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI);
2296
61fccb2d
KM		 2297 if (priv->chip_id != RCAR_GEN2)
2298 ravb_set_delay_mode(ndev);
2299
0184165b
NS		 2300 /* Restore descriptor base address table */
2301 ravb_write(ndev, priv->desc_bat_dma, DBAT);
2302
2303 if (netif_running(ndev)) {
3e3d6477
NS		 2304 if (priv->wol_enabled) {
2305 ret = ravb_wol_restore(ndev);
2306 if (ret)
2307 return ret;
2308 }
0184165b
NS		 2309 ret = ravb_open(ndev);
2310 if (ret < 0)
2311 return ret;
2312 netif_device_attach(ndev);
2313 }
2314
2315 return ret;
2316}
2317
1ddcf41f 2318static int __maybe_unused ravb_runtime_nop(struct device *dev)
c156633f
SS		 2319{
2320 /* Runtime PM callback shared between ->runtime_suspend()
2321 * and ->runtime_resume(). Simply returns success.
2322 *
2323 * This driver re-initializes all registers after
2324 * pm_runtime_get_sync() anyway so there is no need
2325 * to save and restore registers here.
2326 */
2327 return 0;
2328}
2329
2330static const struct dev_pm_ops ravb_dev_pm_ops = {
b89b815c 2331 SET_SYSTEM_SLEEP_PM_OPS(ravb_suspend, ravb_resume)
524c6f69 2332 SET_RUNTIME_PM_OPS(ravb_runtime_nop, ravb_runtime_nop, NULL)
c156633f
SS		 2333};
2334
c156633f
SS		 2335static struct platform_driver ravb_driver = {
2336 .probe = ravb_probe,
2337 .remove = ravb_remove,
2338 .driver = {
2339 .name = "ravb",
1ddcf41f 2340 .pm = &ravb_dev_pm_ops,
c156633f
SS		 2341 .of_match_table = ravb_match_table,
2342 },
2343};
2344
2345module_platform_driver(ravb_driver);
2346
2347MODULE_AUTHOR("Mitsuhiro Kimura, Masaru Nagai");
2348MODULE_DESCRIPTION("Renesas Ethernet AVB driver");
2349MODULE_LICENSE("GPL v2");
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