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sh_eth: fix bitbang memory leak
[mirror_ubuntu-hirsute-kernel.git] / drivers / net / ethernet / renesas / sh_eth.c
CommitLineData
86a74ff2
NI		 1/*
2 * SuperH Ethernet device driver
3 *
f0e81fec
NI		 4 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu
5 * Copyright (C) 2008-2012 Renesas Solutions Corp.
86a74ff2
NI		 6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * The full GNU General Public License is included in this distribution in
20 * the file called "COPYING".
21 */
22
86a74ff2 23#include <linux/init.h>
0654011d
YS		 24#include <linux/module.h>
25#include <linux/kernel.h>
26#include <linux/spinlock.h>
6a27cded 27#include <linux/interrupt.h>
86a74ff2
NI		 28#include <linux/dma-mapping.h>
29#include <linux/etherdevice.h>
30#include <linux/delay.h>
31#include <linux/platform_device.h>
32#include <linux/mdio-bitbang.h>
33#include <linux/netdevice.h>
34#include <linux/phy.h>
35#include <linux/cache.h>
36#include <linux/io.h>
bcd5149d 37#include <linux/pm_runtime.h>
5a0e3ad6 38#include <linux/slab.h>
dc19e4e5 39#include <linux/ethtool.h>
fdb37a7f 40#include <linux/if_vlan.h>
f0e81fec 41#include <linux/clk.h>
d4fa0e35 42#include <linux/sh_eth.h>
86a74ff2
NI		 43
44#include "sh_eth.h"
45
dc19e4e5
NI		 46#define SH_ETH_DEF_MSG_ENABLE \
47 (NETIF_MSG_LINK | \
48 NETIF_MSG_TIMER | \
49 NETIF_MSG_RX_ERR| \
50 NETIF_MSG_TX_ERR)
51
5e7a76be
NI		 52#if defined(CONFIG_CPU_SUBTYPE_SH7734) || \
53 defined(CONFIG_CPU_SUBTYPE_SH7763) || \
54 defined(CONFIG_ARCH_R8A7740)
55static void sh_eth_select_mii(struct net_device *ndev)
56{
57 u32 value = 0x0;
58 struct sh_eth_private *mdp = netdev_priv(ndev);
59
60 switch (mdp->phy_interface) {
61 case PHY_INTERFACE_MODE_GMII:
62 value = 0x2;
63 break;
64 case PHY_INTERFACE_MODE_MII:
65 value = 0x1;
66 break;
67 case PHY_INTERFACE_MODE_RMII:
68 value = 0x0;
69 break;
70 default:
71 pr_warn("PHY interface mode was not setup. Set to MII.\n");
72 value = 0x1;
73 break;
74 }
75
76 sh_eth_write(ndev, value, RMII_MII);
77}
78#endif
79
380af9e3 80/* There is CPU dependent code */
d0418bb7 81#if defined(CONFIG_CPU_SUBTYPE_SH7724) || defined(CONFIG_ARCH_R8A7779)
65ac8851
YS		 82#define SH_ETH_RESET_DEFAULT 1
83static void sh_eth_set_duplex(struct net_device *ndev)
84{
85 struct sh_eth_private *mdp = netdev_priv(ndev);
65ac8851
YS		 86
87 if (mdp->duplex) /* Full */
4a55530f 88 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
65ac8851 89 else /* Half */
4a55530f 90 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
65ac8851
YS		 91}
92
93static void sh_eth_set_rate(struct net_device *ndev)
94{
95 struct sh_eth_private *mdp = netdev_priv(ndev);
d0418bb7
PE		 96 unsigned int bits = ECMR_RTM;
97
98#if defined(CONFIG_ARCH_R8A7779)
99 bits |= ECMR_ELB;
100#endif
65ac8851
YS		 101
102 switch (mdp->speed) {
103 case 10: /* 10BASE */
d0418bb7 104 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~bits, ECMR);
65ac8851
YS		 105 break;
106 case 100:/* 100BASE */
d0418bb7 107 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | bits, ECMR);
65ac8851
YS		 108 break;
109 default:
110 break;
111 }
112}
113
114/* SH7724 */
115static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
116 .set_duplex = sh_eth_set_duplex,
117 .set_rate = sh_eth_set_rate,
118
119 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
120 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
121 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x01ff009f,
122
123 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
124 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE |
125 EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI,
126 .tx_error_check = EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE,
127
128 .apr = 1,
129 .mpr = 1,
130 .tpauser = 1,
131 .hw_swap = 1,
503914cf
MD		 132 .rpadir = 1,
133 .rpadir_value = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
65ac8851 134};
f29a3d04 135#elif defined(CONFIG_CPU_SUBTYPE_SH7757)
8fcd4961
YS		 136#define SH_ETH_HAS_BOTH_MODULES 1
137#define SH_ETH_HAS_TSU 1
5cee1d37
NI		 138static int sh_eth_check_reset(struct net_device *ndev);
139
f29a3d04
YS		 140static void sh_eth_set_duplex(struct net_device *ndev)
141{
142 struct sh_eth_private *mdp = netdev_priv(ndev);
f29a3d04
YS		 143
144 if (mdp->duplex) /* Full */
4a55530f 145 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
f29a3d04 146 else /* Half */
4a55530f 147 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
f29a3d04
YS		 148}
149
150static void sh_eth_set_rate(struct net_device *ndev)
151{
152 struct sh_eth_private *mdp = netdev_priv(ndev);
f29a3d04
YS		 153
154 switch (mdp->speed) {
155 case 10: /* 10BASE */
4a55530f 156 sh_eth_write(ndev, 0, RTRATE);
f29a3d04
YS		 157 break;
158 case 100:/* 100BASE */
4a55530f 159 sh_eth_write(ndev, 1, RTRATE);
f29a3d04
YS		 160 break;
161 default:
162 break;
163 }
164}
165
166/* SH7757 */
167static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
168 .set_duplex = sh_eth_set_duplex,
169 .set_rate = sh_eth_set_rate,
170
171 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
172 .rmcr_value = 0x00000001,
173
174 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
175 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE |
176 EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI,
177 .tx_error_check = EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE,
178
179 .apr = 1,
180 .mpr = 1,
181 .tpauser = 1,
182 .hw_swap = 1,
183 .no_ade = 1,
2e98e797
YS		 184 .rpadir = 1,
185 .rpadir_value = 2 << 16,
f29a3d04 186};
65ac8851 187
8fcd4961
YS		 188#define SH_GIGA_ETH_BASE 0xfee00000
189#define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
190#define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
191static void sh_eth_chip_reset_giga(struct net_device *ndev)
192{
193 int i;
194 unsigned long mahr[2], malr[2];
195
196 /* save MAHR and MALR */
197 for (i = 0; i < 2; i++) {
ae70644d
YS		 198 malr[i] = ioread32((void *)GIGA_MALR(i));
199 mahr[i] = ioread32((void *)GIGA_MAHR(i));
8fcd4961
YS		 200 }
201
202 /* reset device */
ae70644d 203 iowrite32(ARSTR_ARSTR, (void *)(SH_GIGA_ETH_BASE + 0x1800));
8fcd4961
YS		 204 mdelay(1);
205
206 /* restore MAHR and MALR */
207 for (i = 0; i < 2; i++) {
ae70644d
YS		 208 iowrite32(malr[i], (void *)GIGA_MALR(i));
209 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
8fcd4961
YS		 210 }
211}
212
213static int sh_eth_is_gether(struct sh_eth_private *mdp);
5cee1d37 214static int sh_eth_reset(struct net_device *ndev)
8fcd4961
YS		 215{
216 struct sh_eth_private *mdp = netdev_priv(ndev);
5cee1d37 217 int ret = 0;
8fcd4961
YS		 218
219 if (sh_eth_is_gether(mdp)) {
220 sh_eth_write(ndev, 0x03, EDSR);
221 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER,
222 EDMR);
5cee1d37
NI		 223
224 ret = sh_eth_check_reset(ndev);
225 if (ret)
226 goto out;
8fcd4961
YS		 227
228 /* Table Init */
229 sh_eth_write(ndev, 0x0, TDLAR);
230 sh_eth_write(ndev, 0x0, TDFAR);
231 sh_eth_write(ndev, 0x0, TDFXR);
232 sh_eth_write(ndev, 0x0, TDFFR);
233 sh_eth_write(ndev, 0x0, RDLAR);
234 sh_eth_write(ndev, 0x0, RDFAR);
235 sh_eth_write(ndev, 0x0, RDFXR);
236 sh_eth_write(ndev, 0x0, RDFFR);
237 } else {
238 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER,
239 EDMR);
240 mdelay(3);
241 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER,
242 EDMR);
243 }
5cee1d37
NI		 244
245out:
246 return ret;
8fcd4961
YS		 247}
248
249static void sh_eth_set_duplex_giga(struct net_device *ndev)
250{
251 struct sh_eth_private *mdp = netdev_priv(ndev);
252
253 if (mdp->duplex) /* Full */
254 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
255 else /* Half */
256 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
257}
258
259static void sh_eth_set_rate_giga(struct net_device *ndev)
260{
261 struct sh_eth_private *mdp = netdev_priv(ndev);
262
263 switch (mdp->speed) {
264 case 10: /* 10BASE */
265 sh_eth_write(ndev, 0x00000000, GECMR);
266 break;
267 case 100:/* 100BASE */
268 sh_eth_write(ndev, 0x00000010, GECMR);
269 break;
270 case 1000: /* 1000BASE */
271 sh_eth_write(ndev, 0x00000020, GECMR);
272 break;
273 default:
274 break;
275 }
276}
277
278/* SH7757(GETHERC) */
279static struct sh_eth_cpu_data sh_eth_my_cpu_data_giga = {
280 .chip_reset = sh_eth_chip_reset_giga,
281 .set_duplex = sh_eth_set_duplex_giga,
282 .set_rate = sh_eth_set_rate_giga,
283
284 .ecsr_value = ECSR_ICD | ECSR_MPD,
285 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
286 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
287
288 .tx_check = EESR_TC1 | EESR_FTC,
289 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \
290 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \
291 EESR_ECI,
292 .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \
293 EESR_TFE,
294 .fdr_value = 0x0000072f,
295 .rmcr_value = 0x00000001,
296
297 .apr = 1,
298 .mpr = 1,
299 .tpauser = 1,
300 .bculr = 1,
301 .hw_swap = 1,
302 .rpadir = 1,
303 .rpadir_value = 2 << 16,
304 .no_trimd = 1,
305 .no_ade = 1,
3acbc971 306 .tsu = 1,
8fcd4961
YS		 307};
308
309static struct sh_eth_cpu_data *sh_eth_get_cpu_data(struct sh_eth_private *mdp)
310{
311 if (sh_eth_is_gether(mdp))
312 return &sh_eth_my_cpu_data_giga;
313 else
314 return &sh_eth_my_cpu_data;
315}
316
f0e81fec 317#elif defined(CONFIG_CPU_SUBTYPE_SH7734) || defined(CONFIG_CPU_SUBTYPE_SH7763)
380af9e3 318#define SH_ETH_HAS_TSU 1
5cee1d37 319static int sh_eth_check_reset(struct net_device *ndev);
f0e81fec 320static void sh_eth_reset_hw_crc(struct net_device *ndev);
5e7a76be 321
380af9e3
YS		 322static void sh_eth_chip_reset(struct net_device *ndev)
323{
4986b996
YS		 324 struct sh_eth_private *mdp = netdev_priv(ndev);
325
380af9e3 326 /* reset device */
4986b996 327 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
380af9e3
YS		 328 mdelay(1);
329}
330
380af9e3
YS		 331static void sh_eth_set_duplex(struct net_device *ndev)
332{
333 struct sh_eth_private *mdp = netdev_priv(ndev);
380af9e3
YS		 334
335 if (mdp->duplex) /* Full */
4a55530f 336 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
380af9e3 337 else /* Half */
4a55530f 338 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
380af9e3
YS		 339}
340
341static void sh_eth_set_rate(struct net_device *ndev)
342{
343 struct sh_eth_private *mdp = netdev_priv(ndev);
380af9e3
YS		 344
345 switch (mdp->speed) {
346 case 10: /* 10BASE */
4a55530f 347 sh_eth_write(ndev, GECMR_10, GECMR);
380af9e3
YS		 348 break;
349 case 100:/* 100BASE */
4a55530f 350 sh_eth_write(ndev, GECMR_100, GECMR);
380af9e3
YS		 351 break;
352 case 1000: /* 1000BASE */
4a55530f 353 sh_eth_write(ndev, GECMR_1000, GECMR);
380af9e3
YS		 354 break;
355 default:
356 break;
357 }
358}
359
360/* sh7763 */
361static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
362 .chip_reset = sh_eth_chip_reset,
363 .set_duplex = sh_eth_set_duplex,
364 .set_rate = sh_eth_set_rate,
365
366 .ecsr_value = ECSR_ICD | ECSR_MPD,
367 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
368 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
369
370 .tx_check = EESR_TC1 | EESR_FTC,
371 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \
372 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \
373 EESR_ECI,
374 .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \
375 EESR_TFE,
376
377 .apr = 1,
378 .mpr = 1,
379 .tpauser = 1,
380 .bculr = 1,
381 .hw_swap = 1,
380af9e3
YS		 382 .no_trimd = 1,
383 .no_ade = 1,
4986b996 384 .tsu = 1,
f0e81fec
NI		 385#if defined(CONFIG_CPU_SUBTYPE_SH7734)
386 .hw_crc = 1,
5e7a76be 387 .select_mii = 1,
f0e81fec 388#endif
380af9e3
YS		 389};
390
5cee1d37 391static int sh_eth_reset(struct net_device *ndev)
5e7a76be 392{
5cee1d37 393 int ret = 0;
5e7a76be
NI		 394
395 sh_eth_write(ndev, EDSR_ENALL, EDSR);
396 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER, EDMR);
5cee1d37
NI		 397
398 ret = sh_eth_check_reset(ndev);
399 if (ret)
400 goto out;
5e7a76be
NI		 401
402 /* Table Init */
403 sh_eth_write(ndev, 0x0, TDLAR);
404 sh_eth_write(ndev, 0x0, TDFAR);
405 sh_eth_write(ndev, 0x0, TDFXR);
406 sh_eth_write(ndev, 0x0, TDFFR);
407 sh_eth_write(ndev, 0x0, RDLAR);
408 sh_eth_write(ndev, 0x0, RDFAR);
409 sh_eth_write(ndev, 0x0, RDFXR);
410 sh_eth_write(ndev, 0x0, RDFFR);
411
412 /* Reset HW CRC register */
413 sh_eth_reset_hw_crc(ndev);
414
415 /* Select MII mode */
416 if (sh_eth_my_cpu_data.select_mii)
417 sh_eth_select_mii(ndev);
5cee1d37
NI		 418out:
419 return ret;
5e7a76be
NI		 420}
421
f0e81fec
NI		 422static void sh_eth_reset_hw_crc(struct net_device *ndev)
423{
424 if (sh_eth_my_cpu_data.hw_crc)
425 sh_eth_write(ndev, 0x0, CSMR);
426}
427
73a0d907
YS		 428#elif defined(CONFIG_ARCH_R8A7740)
429#define SH_ETH_HAS_TSU 1
5cee1d37
NI		 430static int sh_eth_check_reset(struct net_device *ndev);
431
73a0d907
YS		 432static void sh_eth_chip_reset(struct net_device *ndev)
433{
434 struct sh_eth_private *mdp = netdev_priv(ndev);
73a0d907
YS		 435
436 /* reset device */
437 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
438 mdelay(1);
439
5e7a76be 440 sh_eth_select_mii(ndev);
73a0d907
YS		 441}
442
5cee1d37 443static int sh_eth_reset(struct net_device *ndev)
73a0d907 444{
5cee1d37 445 int ret = 0;
73a0d907
YS		 446
447 sh_eth_write(ndev, EDSR_ENALL, EDSR);
448 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER, EDMR);
5cee1d37
NI		 449
450 ret = sh_eth_check_reset(ndev);
451 if (ret)
452 goto out;
73a0d907
YS		 453
454 /* Table Init */
455 sh_eth_write(ndev, 0x0, TDLAR);
456 sh_eth_write(ndev, 0x0, TDFAR);
457 sh_eth_write(ndev, 0x0, TDFXR);
458 sh_eth_write(ndev, 0x0, TDFFR);
459 sh_eth_write(ndev, 0x0, RDLAR);
460 sh_eth_write(ndev, 0x0, RDFAR);
461 sh_eth_write(ndev, 0x0, RDFXR);
462 sh_eth_write(ndev, 0x0, RDFFR);
5cee1d37
NI		 463
464out:
465 return ret;
73a0d907
YS		 466}
467
468static void sh_eth_set_duplex(struct net_device *ndev)
469{
470 struct sh_eth_private *mdp = netdev_priv(ndev);
471
472 if (mdp->duplex) /* Full */
473 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
474 else /* Half */
475 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
476}
477
478static void sh_eth_set_rate(struct net_device *ndev)
479{
480 struct sh_eth_private *mdp = netdev_priv(ndev);
481
482 switch (mdp->speed) {
483 case 10: /* 10BASE */
484 sh_eth_write(ndev, GECMR_10, GECMR);
485 break;
486 case 100:/* 100BASE */
487 sh_eth_write(ndev, GECMR_100, GECMR);
488 break;
489 case 1000: /* 1000BASE */
490 sh_eth_write(ndev, GECMR_1000, GECMR);
491 break;
492 default:
493 break;
494 }
495}
496
497/* R8A7740 */
498static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
499 .chip_reset = sh_eth_chip_reset,
500 .set_duplex = sh_eth_set_duplex,
501 .set_rate = sh_eth_set_rate,
502
503 .ecsr_value = ECSR_ICD | ECSR_MPD,
504 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
505 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
506
507 .tx_check = EESR_TC1 | EESR_FTC,
508 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \
509 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \
510 EESR_ECI,
511 .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \
512 EESR_TFE,
513
514 .apr = 1,
515 .mpr = 1,
516 .tpauser = 1,
517 .bculr = 1,
518 .hw_swap = 1,
519 .no_trimd = 1,
520 .no_ade = 1,
521 .tsu = 1,
5e7a76be 522 .select_mii = 1,
73a0d907
YS		 523};
524
380af9e3
YS		 525#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
526#define SH_ETH_RESET_DEFAULT 1
527static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
528 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
529
530 .apr = 1,
531 .mpr = 1,
532 .tpauser = 1,
533 .hw_swap = 1,
534};
535#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
536#define SH_ETH_RESET_DEFAULT 1
537#define SH_ETH_HAS_TSU 1
538static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
539 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
4986b996 540 .tsu = 1,
380af9e3
YS		 541};
542#endif
543
544static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
545{
546 if (!cd->ecsr_value)
547 cd->ecsr_value = DEFAULT_ECSR_INIT;
548
549 if (!cd->ecsipr_value)
550 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
551
552 if (!cd->fcftr_value)
553 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF | \
554 DEFAULT_FIFO_F_D_RFD;
555
556 if (!cd->fdr_value)
557 cd->fdr_value = DEFAULT_FDR_INIT;
558
559 if (!cd->rmcr_value)
560 cd->rmcr_value = DEFAULT_RMCR_VALUE;
561
562 if (!cd->tx_check)
563 cd->tx_check = DEFAULT_TX_CHECK;
564
565 if (!cd->eesr_err_check)
566 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
567
568 if (!cd->tx_error_check)
569 cd->tx_error_check = DEFAULT_TX_ERROR_CHECK;
570}
571
572#if defined(SH_ETH_RESET_DEFAULT)
573/* Chip Reset */
5cee1d37 574static int sh_eth_reset(struct net_device *ndev)
380af9e3 575{
c5ed5368 576 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER, EDMR);
380af9e3 577 mdelay(3);
c5ed5368 578 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER, EDMR);
5cee1d37
NI		 579
580 return 0;
581}
582#else
583static int sh_eth_check_reset(struct net_device *ndev)
584{
585 int ret = 0;
586 int cnt = 100;
587
588 while (cnt > 0) {
589 if (!(sh_eth_read(ndev, EDMR) & 0x3))
590 break;
591 mdelay(1);
592 cnt--;
593 }
594 if (cnt < 0) {
595 printk(KERN_ERR "Device reset fail\n");
596 ret = -ETIMEDOUT;
597 }
598 return ret;
380af9e3
YS		 599}
600#endif
601
73a0d907 602#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
380af9e3
YS		 603static void sh_eth_set_receive_align(struct sk_buff *skb)
604{
605 int reserve;
606
607 reserve = SH4_SKB_RX_ALIGN - ((u32)skb->data & (SH4_SKB_RX_ALIGN - 1));
608 if (reserve)
609 skb_reserve(skb, reserve);
610}
611#else
612static void sh_eth_set_receive_align(struct sk_buff *skb)
613{
614 skb_reserve(skb, SH2_SH3_SKB_RX_ALIGN);
615}
616#endif
617
618
71557a37
YS		 619/* CPU <-> EDMAC endian convert */
620static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x)
621{
622 switch (mdp->edmac_endian) {
623 case EDMAC_LITTLE_ENDIAN:
624 return cpu_to_le32(x);
625 case EDMAC_BIG_ENDIAN:
626 return cpu_to_be32(x);
627 }
628 return x;
629}
630
631static inline __u32 edmac_to_cpu(struct sh_eth_private *mdp, u32 x)
632{
633 switch (mdp->edmac_endian) {
634 case EDMAC_LITTLE_ENDIAN:
635 return le32_to_cpu(x);
636 case EDMAC_BIG_ENDIAN:
637 return be32_to_cpu(x);
638 }
639 return x;
640}
641
86a74ff2
NI		 642/*
643 * Program the hardware MAC address from dev->dev_addr.
644 */
645static void update_mac_address(struct net_device *ndev)
646{
4a55530f
YS		 647 sh_eth_write(ndev,
648 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
649 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
650 sh_eth_write(ndev,
651 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
86a74ff2
NI		 652}
653
654/*
655 * Get MAC address from SuperH MAC address register
656 *
657 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
658 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
659 * When you want use this device, you must set MAC address in bootloader.
660 *
661 */
748031f9 662static void read_mac_address(struct net_device *ndev, unsigned char *mac)
86a74ff2 663{
748031f9
MD		 664 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
665 memcpy(ndev->dev_addr, mac, 6);
666 } else {
4a55530f
YS		 667 ndev->dev_addr[0] = (sh_eth_read(ndev, MAHR) >> 24);
668 ndev->dev_addr[1] = (sh_eth_read(ndev, MAHR) >> 16) & 0xFF;
669 ndev->dev_addr[2] = (sh_eth_read(ndev, MAHR) >> 8) & 0xFF;
670 ndev->dev_addr[3] = (sh_eth_read(ndev, MAHR) & 0xFF);
671 ndev->dev_addr[4] = (sh_eth_read(ndev, MALR) >> 8) & 0xFF;
672 ndev->dev_addr[5] = (sh_eth_read(ndev, MALR) & 0xFF);
748031f9 673 }
86a74ff2
NI		 674}
675
c5ed5368
YS		 676static int sh_eth_is_gether(struct sh_eth_private *mdp)
677{
678 if (mdp->reg_offset == sh_eth_offset_gigabit)
679 return 1;
680 else
681 return 0;
682}
683
684static unsigned long sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
685{
686 if (sh_eth_is_gether(mdp))
687 return EDTRR_TRNS_GETHER;
688 else
689 return EDTRR_TRNS_ETHER;
690}
691
86a74ff2 692struct bb_info {
ae70644d 693 void (*set_gate)(void *addr);
86a74ff2 694 struct mdiobb_ctrl ctrl;
ae70644d 695 void *addr;
86a74ff2
NI		 696 u32 mmd_msk;/* MMD */
697 u32 mdo_msk;
698 u32 mdi_msk;
699 u32 mdc_msk;
700};
701
702/* PHY bit set */
ae70644d 703static void bb_set(void *addr, u32 msk)
86a74ff2 704{
ae70644d 705 iowrite32(ioread32(addr) | msk, addr);
86a74ff2
NI		 706}
707
708/* PHY bit clear */
ae70644d 709static void bb_clr(void *addr, u32 msk)
86a74ff2 710{
ae70644d 711 iowrite32((ioread32(addr) & ~msk), addr);
86a74ff2
NI		 712}
713
714/* PHY bit read */
ae70644d 715static int bb_read(void *addr, u32 msk)
86a74ff2 716{
ae70644d 717 return (ioread32(addr) & msk) != 0;
86a74ff2
NI		 718}
719
720/* Data I/O pin control */
721static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
722{
723 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
b3017e6a
YS		 724
725 if (bitbang->set_gate)
726 bitbang->set_gate(bitbang->addr);
727
86a74ff2
NI		 728 if (bit)
729 bb_set(bitbang->addr, bitbang->mmd_msk);
730 else
731 bb_clr(bitbang->addr, bitbang->mmd_msk);
732}
733
734/* Set bit data*/
735static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
736{
737 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
738
b3017e6a
YS		 739 if (bitbang->set_gate)
740 bitbang->set_gate(bitbang->addr);
741
86a74ff2
NI		 742 if (bit)
743 bb_set(bitbang->addr, bitbang->mdo_msk);
744 else
745 bb_clr(bitbang->addr, bitbang->mdo_msk);
746}
747
748/* Get bit data*/
749static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
750{
751 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
b3017e6a
YS		 752
753 if (bitbang->set_gate)
754 bitbang->set_gate(bitbang->addr);
755
86a74ff2
NI		 756 return bb_read(bitbang->addr, bitbang->mdi_msk);
757}
758
759/* MDC pin control */
760static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
761{
762 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
763
b3017e6a
YS		 764 if (bitbang->set_gate)
765 bitbang->set_gate(bitbang->addr);
766
86a74ff2
NI		 767 if (bit)
768 bb_set(bitbang->addr, bitbang->mdc_msk);
769 else
770 bb_clr(bitbang->addr, bitbang->mdc_msk);
771}
772
773/* mdio bus control struct */
774static struct mdiobb_ops bb_ops = {
775 .owner = THIS_MODULE,
776 .set_mdc = sh_mdc_ctrl,
777 .set_mdio_dir = sh_mmd_ctrl,
778 .set_mdio_data = sh_set_mdio,
779 .get_mdio_data = sh_get_mdio,
780};
781
86a74ff2
NI		 782/* free skb and descriptor buffer */
783static void sh_eth_ring_free(struct net_device *ndev)
784{
785 struct sh_eth_private *mdp = netdev_priv(ndev);
786 int i;
787
788 /* Free Rx skb ringbuffer */
789 if (mdp->rx_skbuff) {
525b8075 790 for (i = 0; i < mdp->num_rx_ring; i++) {
86a74ff2
NI		 791 if (mdp->rx_skbuff[i])
792 dev_kfree_skb(mdp->rx_skbuff[i]);
793 }
794 }
795 kfree(mdp->rx_skbuff);
91c77550 796 mdp->rx_skbuff = NULL;
86a74ff2
NI		 797
798 /* Free Tx skb ringbuffer */
799 if (mdp->tx_skbuff) {
525b8075 800 for (i = 0; i < mdp->num_tx_ring; i++) {
86a74ff2
NI		 801 if (mdp->tx_skbuff[i])
802 dev_kfree_skb(mdp->tx_skbuff[i]);
803 }
804 }
805 kfree(mdp->tx_skbuff);
91c77550 806 mdp->tx_skbuff = NULL;
86a74ff2
NI		 807}
808
809/* format skb and descriptor buffer */
810static void sh_eth_ring_format(struct net_device *ndev)
811{
812 struct sh_eth_private *mdp = netdev_priv(ndev);
813 int i;
814 struct sk_buff *skb;
815 struct sh_eth_rxdesc *rxdesc = NULL;
816 struct sh_eth_txdesc *txdesc = NULL;
525b8075
YS		 817 int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
818 int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
86a74ff2
NI		 819
820 mdp->cur_rx = mdp->cur_tx = 0;
821 mdp->dirty_rx = mdp->dirty_tx = 0;
822
823 memset(mdp->rx_ring, 0, rx_ringsize);
824
825 /* build Rx ring buffer */
525b8075 826 for (i = 0; i < mdp->num_rx_ring; i++) {
86a74ff2
NI		 827 /* skb */
828 mdp->rx_skbuff[i] = NULL;
dae2e9f4 829 skb = netdev_alloc_skb(ndev, mdp->rx_buf_sz);
86a74ff2
NI		 830 mdp->rx_skbuff[i] = skb;
831 if (skb == NULL)
832 break;
bb7d92e3 833 dma_map_single(&ndev->dev, skb->data, mdp->rx_buf_sz,
e88aae7b 834 DMA_FROM_DEVICE);
380af9e3
YS		 835 sh_eth_set_receive_align(skb);
836
86a74ff2
NI		 837 /* RX descriptor */
838 rxdesc = &mdp->rx_ring[i];
0029d64a 839 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
71557a37 840 rxdesc->status = cpu_to_edmac(mdp, RD_RACT | RD_RFP);
86a74ff2
NI		 841
842 /* The size of the buffer is 16 byte boundary. */
0029d64a 843 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
b0ca2a21
NI		 844 /* Rx descriptor address set */
845 if (i == 0) {
4a55530f 846 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
c5ed5368
YS		 847 if (sh_eth_is_gether(mdp))
848 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
b0ca2a21 849 }
86a74ff2
NI		 850 }
851
525b8075 852 mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
86a74ff2
NI		 853
854 /* Mark the last entry as wrapping the ring. */
71557a37 855 rxdesc->status |= cpu_to_edmac(mdp, RD_RDEL);
86a74ff2
NI		 856
857 memset(mdp->tx_ring, 0, tx_ringsize);
858
859 /* build Tx ring buffer */
525b8075 860 for (i = 0; i < mdp->num_tx_ring; i++) {
86a74ff2
NI		 861 mdp->tx_skbuff[i] = NULL;
862 txdesc = &mdp->tx_ring[i];
71557a37 863 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
86a74ff2 864 txdesc->buffer_length = 0;
b0ca2a21 865 if (i == 0) {
71557a37 866 /* Tx descriptor address set */
4a55530f 867 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
c5ed5368
YS		 868 if (sh_eth_is_gether(mdp))
869 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
b0ca2a21 870 }
86a74ff2
NI		 871 }
872
71557a37 873 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
86a74ff2
NI		 874}
875
876/* Get skb and descriptor buffer */
877static int sh_eth_ring_init(struct net_device *ndev)
878{
879 struct sh_eth_private *mdp = netdev_priv(ndev);
880 int rx_ringsize, tx_ringsize, ret = 0;
881
882 /*
883 * +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
884 * card needs room to do 8 byte alignment, +2 so we can reserve
885 * the first 2 bytes, and +16 gets room for the status word from the
886 * card.
887 */
888 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
889 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
503914cf
MD		 890 if (mdp->cd->rpadir)
891 mdp->rx_buf_sz += NET_IP_ALIGN;
86a74ff2
NI		 892
893 /* Allocate RX and TX skb rings */
b2adaca9
JP		 894 mdp->rx_skbuff = kmalloc_array(mdp->num_rx_ring,
895 sizeof(*mdp->rx_skbuff), GFP_KERNEL);
86a74ff2 896 if (!mdp->rx_skbuff) {
86a74ff2
NI		 897 ret = -ENOMEM;
898 return ret;
899 }
900
b2adaca9
JP		 901 mdp->tx_skbuff = kmalloc_array(mdp->num_tx_ring,
902 sizeof(*mdp->tx_skbuff), GFP_KERNEL);
86a74ff2 903 if (!mdp->tx_skbuff) {
86a74ff2
NI		 904 ret = -ENOMEM;
905 goto skb_ring_free;
906 }
907
908 /* Allocate all Rx descriptors. */
525b8075 909 rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
86a74ff2
NI		 910 mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
911 GFP_KERNEL);
912
913 if (!mdp->rx_ring) {
380af9e3
YS		 914 dev_err(&ndev->dev, "Cannot allocate Rx Ring (size %d bytes)\n",
915 rx_ringsize);
86a74ff2
NI		 916 ret = -ENOMEM;
917 goto desc_ring_free;
918 }
919
920 mdp->dirty_rx = 0;
921
922 /* Allocate all Tx descriptors. */
525b8075 923 tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
86a74ff2
NI		 924 mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
925 GFP_KERNEL);
926 if (!mdp->tx_ring) {
380af9e3
YS		 927 dev_err(&ndev->dev, "Cannot allocate Tx Ring (size %d bytes)\n",
928 tx_ringsize);
86a74ff2
NI		 929 ret = -ENOMEM;
930 goto desc_ring_free;
931 }
932 return ret;
933
934desc_ring_free:
935 /* free DMA buffer */
936 dma_free_coherent(NULL, rx_ringsize, mdp->rx_ring, mdp->rx_desc_dma);
937
938skb_ring_free:
939 /* Free Rx and Tx skb ring buffer */
940 sh_eth_ring_free(ndev);
91c77550
YS		 941 mdp->tx_ring = NULL;
942 mdp->rx_ring = NULL;
86a74ff2
NI		 943
944 return ret;
945}
946
91c77550
YS		 947static void sh_eth_free_dma_buffer(struct sh_eth_private *mdp)
948{
949 int ringsize;
950
951 if (mdp->rx_ring) {
525b8075 952 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
91c77550
YS		 953 dma_free_coherent(NULL, ringsize, mdp->rx_ring,
954 mdp->rx_desc_dma);
955 mdp->rx_ring = NULL;
956 }
957
958 if (mdp->tx_ring) {
525b8075 959 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
91c77550
YS		 960 dma_free_coherent(NULL, ringsize, mdp->tx_ring,
961 mdp->tx_desc_dma);
962 mdp->tx_ring = NULL;
963 }
964}
965
525b8075 966static int sh_eth_dev_init(struct net_device *ndev, bool start)
86a74ff2
NI		 967{
968 int ret = 0;
969 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 970 u32 val;
971
972 /* Soft Reset */
5cee1d37
NI		 973 ret = sh_eth_reset(ndev);
974 if (ret)
975 goto out;
86a74ff2 976
b0ca2a21
NI		 977 /* Descriptor format */
978 sh_eth_ring_format(ndev);
380af9e3 979 if (mdp->cd->rpadir)
4a55530f 980 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
86a74ff2
NI		 981
982 /* all sh_eth int mask */
4a55530f 983 sh_eth_write(ndev, 0, EESIPR);
86a74ff2 984
10b9194f 985#if defined(__LITTLE_ENDIAN)
380af9e3 986 if (mdp->cd->hw_swap)
4a55530f 987 sh_eth_write(ndev, EDMR_EL, EDMR);
380af9e3 988 else
b0ca2a21 989#endif
4a55530f 990 sh_eth_write(ndev, 0, EDMR);
86a74ff2 991
b0ca2a21 992 /* FIFO size set */
4a55530f
YS		 993 sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
994 sh_eth_write(ndev, 0, TFTR);
86a74ff2 995
b0ca2a21 996 /* Frame recv control */
4a55530f 997 sh_eth_write(ndev, mdp->cd->rmcr_value, RMCR);
86a74ff2 998
2ecbb783 999 sh_eth_write(ndev, DESC_I_RINT8 | DESC_I_RINT5 | DESC_I_TINT2, TRSCER);
86a74ff2 1000
380af9e3 1001 if (mdp->cd->bculr)
4a55530f 1002 sh_eth_write(ndev, 0x800, BCULR); /* Burst sycle set */
b0ca2a21 1003
4a55530f 1004 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
86a74ff2 1005
380af9e3 1006 if (!mdp->cd->no_trimd)
4a55530f 1007 sh_eth_write(ndev, 0, TRIMD);
86a74ff2 1008
b0ca2a21 1009 /* Recv frame limit set register */
fdb37a7f
YS		 1010 sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1011 RFLR);
86a74ff2 1012
4a55530f 1013 sh_eth_write(ndev, sh_eth_read(ndev, EESR), EESR);
525b8075
YS		 1014 if (start)
1015 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
86a74ff2
NI		 1016
1017 /* PAUSE Prohibition */
4a55530f 1018 val = (sh_eth_read(ndev, ECMR) & ECMR_DM) |
86a74ff2
NI		 1019 ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE;
1020
4a55530f 1021 sh_eth_write(ndev, val, ECMR);
b0ca2a21 1022
380af9e3
YS		 1023 if (mdp->cd->set_rate)
1024 mdp->cd->set_rate(ndev);
1025
b0ca2a21 1026 /* E-MAC Status Register clear */
4a55530f 1027 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
b0ca2a21
NI		 1028
1029 /* E-MAC Interrupt Enable register */
525b8075
YS		 1030 if (start)
1031 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
86a74ff2
NI		 1032
1033 /* Set MAC address */
1034 update_mac_address(ndev);
1035
1036 /* mask reset */
380af9e3 1037 if (mdp->cd->apr)
4a55530f 1038 sh_eth_write(ndev, APR_AP, APR);
380af9e3 1039 if (mdp->cd->mpr)
4a55530f 1040 sh_eth_write(ndev, MPR_MP, MPR);
380af9e3 1041 if (mdp->cd->tpauser)
4a55530f 1042 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
b0ca2a21 1043
525b8075
YS		 1044 if (start) {
1045 /* Setting the Rx mode will start the Rx process. */
1046 sh_eth_write(ndev, EDRRR_R, EDRRR);
86a74ff2 1047
525b8075
YS		 1048 netif_start_queue(ndev);
1049 }
86a74ff2 1050
5cee1d37 1051out:
86a74ff2
NI		 1052 return ret;
1053}
1054
1055/* free Tx skb function */
1056static int sh_eth_txfree(struct net_device *ndev)
1057{
1058 struct sh_eth_private *mdp = netdev_priv(ndev);
1059 struct sh_eth_txdesc *txdesc;
1060 int freeNum = 0;
1061 int entry = 0;
1062
1063 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
525b8075 1064 entry = mdp->dirty_tx % mdp->num_tx_ring;
86a74ff2 1065 txdesc = &mdp->tx_ring[entry];
71557a37 1066 if (txdesc->status & cpu_to_edmac(mdp, TD_TACT))
86a74ff2
NI		 1067 break;
1068 /* Free the original skb. */
1069 if (mdp->tx_skbuff[entry]) {
31fcb99d
YS		 1070 dma_unmap_single(&ndev->dev, txdesc->addr,
1071 txdesc->buffer_length, DMA_TO_DEVICE);
86a74ff2
NI		 1072 dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1073 mdp->tx_skbuff[entry] = NULL;
1074 freeNum++;
1075 }
71557a37 1076 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
525b8075 1077 if (entry >= mdp->num_tx_ring - 1)
71557a37 1078 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
86a74ff2 1079
bb7d92e3
ED		 1080 ndev->stats.tx_packets++;
1081 ndev->stats.tx_bytes += txdesc->buffer_length;
86a74ff2
NI		 1082 }
1083 return freeNum;
1084}
1085
1086/* Packet receive function */
a18e08bd 1087static int sh_eth_rx(struct net_device *ndev, u32 intr_status)
86a74ff2
NI		 1088{
1089 struct sh_eth_private *mdp = netdev_priv(ndev);
1090 struct sh_eth_rxdesc *rxdesc;
1091
525b8075
YS		 1092 int entry = mdp->cur_rx % mdp->num_rx_ring;
1093 int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
86a74ff2
NI		 1094 struct sk_buff *skb;
1095 u16 pkt_len = 0;
380af9e3 1096 u32 desc_status;
86a74ff2
NI		 1097
1098 rxdesc = &mdp->rx_ring[entry];
71557a37
YS		 1099 while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) {
1100 desc_status = edmac_to_cpu(mdp, rxdesc->status);
86a74ff2
NI		 1101 pkt_len = rxdesc->frame_length;
1102
73a0d907
YS		 1103#if defined(CONFIG_ARCH_R8A7740)
1104 desc_status >>= 16;
1105#endif
1106
86a74ff2
NI		 1107 if (--boguscnt < 0)
1108 break;
1109
1110 if (!(desc_status & RDFEND))
bb7d92e3 1111 ndev->stats.rx_length_errors++;
86a74ff2
NI		 1112
1113 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1114 RD_RFS5 | RD_RFS6 | RD_RFS10)) {
bb7d92e3 1115 ndev->stats.rx_errors++;
86a74ff2 1116 if (desc_status & RD_RFS1)
bb7d92e3 1117 ndev->stats.rx_crc_errors++;
86a74ff2 1118 if (desc_status & RD_RFS2)
bb7d92e3 1119 ndev->stats.rx_frame_errors++;
86a74ff2 1120 if (desc_status & RD_RFS3)
bb7d92e3 1121 ndev->stats.rx_length_errors++;
86a74ff2 1122 if (desc_status & RD_RFS4)
bb7d92e3 1123 ndev->stats.rx_length_errors++;
86a74ff2 1124 if (desc_status & RD_RFS6)
bb7d92e3 1125 ndev->stats.rx_missed_errors++;
86a74ff2 1126 if (desc_status & RD_RFS10)
bb7d92e3 1127 ndev->stats.rx_over_errors++;
86a74ff2 1128 } else {
380af9e3
YS		 1129 if (!mdp->cd->hw_swap)
1130 sh_eth_soft_swap(
1131 phys_to_virt(ALIGN(rxdesc->addr, 4)),
1132 pkt_len + 2);
86a74ff2
NI		 1133 skb = mdp->rx_skbuff[entry];
1134 mdp->rx_skbuff[entry] = NULL;
503914cf
MD		 1135 if (mdp->cd->rpadir)
1136 skb_reserve(skb, NET_IP_ALIGN);
86a74ff2
NI		 1137 skb_put(skb, pkt_len);
1138 skb->protocol = eth_type_trans(skb, ndev);
1139 netif_rx(skb);
bb7d92e3
ED		 1140 ndev->stats.rx_packets++;
1141 ndev->stats.rx_bytes += pkt_len;
86a74ff2 1142 }
71557a37 1143 rxdesc->status |= cpu_to_edmac(mdp, RD_RACT);
525b8075 1144 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
862df497 1145 rxdesc = &mdp->rx_ring[entry];
86a74ff2
NI		 1146 }
1147
1148 /* Refill the Rx ring buffers. */
1149 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
525b8075 1150 entry = mdp->dirty_rx % mdp->num_rx_ring;
86a74ff2 1151 rxdesc = &mdp->rx_ring[entry];
b0ca2a21 1152 /* The size of the buffer is 16 byte boundary. */
0029d64a 1153 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
b0ca2a21 1154
86a74ff2 1155 if (mdp->rx_skbuff[entry] == NULL) {
dae2e9f4 1156 skb = netdev_alloc_skb(ndev, mdp->rx_buf_sz);
86a74ff2
NI		 1157 mdp->rx_skbuff[entry] = skb;
1158 if (skb == NULL)
1159 break; /* Better luck next round. */
bb7d92e3 1160 dma_map_single(&ndev->dev, skb->data, mdp->rx_buf_sz,
e88aae7b 1161 DMA_FROM_DEVICE);
380af9e3
YS		 1162 sh_eth_set_receive_align(skb);
1163
bc8acf2c 1164 skb_checksum_none_assert(skb);
0029d64a 1165 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
86a74ff2 1166 }
525b8075 1167 if (entry >= mdp->num_rx_ring - 1)
86a74ff2 1168 rxdesc->status |=
71557a37 1169 cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDEL);
86a74ff2
NI		 1170 else
1171 rxdesc->status |=
71557a37 1172 cpu_to_edmac(mdp, RD_RACT | RD_RFP);
86a74ff2
NI		 1173 }
1174
1175 /* Restart Rx engine if stopped. */
1176 /* If we don't need to check status, don't. -KDU */
79fba9f5 1177 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
a18e08bd
YS		 1178 /* fix the values for the next receiving if RDE is set */
1179 if (intr_status & EESR_RDE)
1180 mdp->cur_rx = mdp->dirty_rx =
1181 (sh_eth_read(ndev, RDFAR) -
1182 sh_eth_read(ndev, RDLAR)) >> 4;
4a55530f 1183 sh_eth_write(ndev, EDRRR_R, EDRRR);
79fba9f5 1184 }
86a74ff2
NI		 1185
1186 return 0;
1187}
1188
4a55530f 1189static void sh_eth_rcv_snd_disable(struct net_device *ndev)
dc19e4e5
NI		 1190{
1191 /* disable tx and rx */
4a55530f
YS		 1192 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) &
1193 ~(ECMR_RE | ECMR_TE), ECMR);
dc19e4e5
NI		 1194}
1195
4a55530f 1196static void sh_eth_rcv_snd_enable(struct net_device *ndev)
dc19e4e5
NI		 1197{
1198 /* enable tx and rx */
4a55530f
YS		 1199 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) |
1200 (ECMR_RE | ECMR_TE), ECMR);
dc19e4e5
NI		 1201}
1202
86a74ff2
NI		 1203/* error control function */
1204static void sh_eth_error(struct net_device *ndev, int intr_status)
1205{
1206 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2 1207 u32 felic_stat;
380af9e3
YS		 1208 u32 link_stat;
1209 u32 mask;
86a74ff2
NI		 1210
1211 if (intr_status & EESR_ECI) {
4a55530f
YS		 1212 felic_stat = sh_eth_read(ndev, ECSR);
1213 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */
86a74ff2 1214 if (felic_stat & ECSR_ICD)
bb7d92e3 1215 ndev->stats.tx_carrier_errors++;
86a74ff2
NI		 1216 if (felic_stat & ECSR_LCHNG) {
1217 /* Link Changed */
4923576b 1218 if (mdp->cd->no_psr || mdp->no_ether_link) {
380af9e3
YS		 1219 if (mdp->link == PHY_DOWN)
1220 link_stat = 0;
1221 else
1222 link_stat = PHY_ST_LINK;
1223 } else {
4a55530f 1224 link_stat = (sh_eth_read(ndev, PSR));
4923576b
YS		 1225 if (mdp->ether_link_active_low)
1226 link_stat = ~link_stat;
380af9e3 1227 }
dc19e4e5 1228 if (!(link_stat & PHY_ST_LINK))
4a55530f 1229 sh_eth_rcv_snd_disable(ndev);
dc19e4e5 1230 else {
86a74ff2 1231 /* Link Up */
4a55530f
YS		 1232 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) &
1233 ~DMAC_M_ECI, EESIPR);
86a74ff2 1234 /*clear int */
4a55530f
YS		 1235 sh_eth_write(ndev, sh_eth_read(ndev, ECSR),
1236 ECSR);
1237 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) |
1238 DMAC_M_ECI, EESIPR);
86a74ff2 1239 /* enable tx and rx */
4a55530f 1240 sh_eth_rcv_snd_enable(ndev);
86a74ff2
NI		 1241 }
1242 }
1243 }
1244
1245 if (intr_status & EESR_TWB) {
1246 /* Write buck end. unused write back interrupt */
1247 if (intr_status & EESR_TABT) /* Transmit Abort int */
bb7d92e3 1248 ndev->stats.tx_aborted_errors++;
dc19e4e5
NI		 1249 if (netif_msg_tx_err(mdp))
1250 dev_err(&ndev->dev, "Transmit Abort\n");
86a74ff2
NI		 1251 }
1252
1253 if (intr_status & EESR_RABT) {
1254 /* Receive Abort int */
1255 if (intr_status & EESR_RFRMER) {
1256 /* Receive Frame Overflow int */
bb7d92e3 1257 ndev->stats.rx_frame_errors++;
dc19e4e5
NI		 1258 if (netif_msg_rx_err(mdp))
1259 dev_err(&ndev->dev, "Receive Abort\n");
86a74ff2
NI		 1260 }
1261 }
380af9e3 1262
dc19e4e5
NI		 1263 if (intr_status & EESR_TDE) {
1264 /* Transmit Descriptor Empty int */
bb7d92e3 1265 ndev->stats.tx_fifo_errors++;
dc19e4e5
NI		 1266 if (netif_msg_tx_err(mdp))
1267 dev_err(&ndev->dev, "Transmit Descriptor Empty\n");
1268 }
1269
1270 if (intr_status & EESR_TFE) {
1271 /* FIFO under flow */
bb7d92e3 1272 ndev->stats.tx_fifo_errors++;
dc19e4e5
NI		 1273 if (netif_msg_tx_err(mdp))
1274 dev_err(&ndev->dev, "Transmit FIFO Under flow\n");
86a74ff2
NI		 1275 }
1276
1277 if (intr_status & EESR_RDE) {
1278 /* Receive Descriptor Empty int */
bb7d92e3 1279 ndev->stats.rx_over_errors++;
86a74ff2 1280
dc19e4e5
NI		 1281 if (netif_msg_rx_err(mdp))
1282 dev_err(&ndev->dev, "Receive Descriptor Empty\n");
86a74ff2 1283 }
dc19e4e5 1284
86a74ff2
NI		 1285 if (intr_status & EESR_RFE) {
1286 /* Receive FIFO Overflow int */
bb7d92e3 1287 ndev->stats.rx_fifo_errors++;
dc19e4e5
NI		 1288 if (netif_msg_rx_err(mdp))
1289 dev_err(&ndev->dev, "Receive FIFO Overflow\n");
1290 }
1291
1292 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1293 /* Address Error */
bb7d92e3 1294 ndev->stats.tx_fifo_errors++;
dc19e4e5
NI		 1295 if (netif_msg_tx_err(mdp))
1296 dev_err(&ndev->dev, "Address Error\n");
86a74ff2 1297 }
380af9e3
YS		 1298
1299 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1300 if (mdp->cd->no_ade)
1301 mask &= ~EESR_ADE;
1302 if (intr_status & mask) {
86a74ff2 1303 /* Tx error */
4a55530f 1304 u32 edtrr = sh_eth_read(ndev, EDTRR);
86a74ff2 1305 /* dmesg */
380af9e3
YS		 1306 dev_err(&ndev->dev, "TX error. status=%8.8x cur_tx=%8.8x ",
1307 intr_status, mdp->cur_tx);
1308 dev_err(&ndev->dev, "dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
86a74ff2
NI		 1309 mdp->dirty_tx, (u32) ndev->state, edtrr);
1310 /* dirty buffer free */
1311 sh_eth_txfree(ndev);
1312
1313 /* SH7712 BUG */
c5ed5368 1314 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
86a74ff2 1315 /* tx dma start */
c5ed5368 1316 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
86a74ff2
NI		 1317 }
1318 /* wakeup */
1319 netif_wake_queue(ndev);
1320 }
1321}
1322
1323static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1324{
1325 struct net_device *ndev = netdev;
1326 struct sh_eth_private *mdp = netdev_priv(ndev);
380af9e3 1327 struct sh_eth_cpu_data *cd = mdp->cd;
0e0fde3c 1328 irqreturn_t ret = IRQ_NONE;
4a55530f 1329 u32 intr_status = 0;
86a74ff2 1330
86a74ff2
NI		 1331 spin_lock(&mdp->lock);
1332
b0ca2a21 1333 /* Get interrpt stat */
4a55530f 1334 intr_status = sh_eth_read(ndev, EESR);
86a74ff2 1335 /* Clear interrupt */
0e0fde3c
NI		 1336 if (intr_status & (EESR_FRC | EESR_RMAF | EESR_RRF |
1337 EESR_RTLF | EESR_RTSF | EESR_PRE | EESR_CERF |
380af9e3 1338 cd->tx_check | cd->eesr_err_check)) {
4a55530f 1339 sh_eth_write(ndev, intr_status, EESR);
0e0fde3c
NI		 1340 ret = IRQ_HANDLED;
1341 } else
1342 goto other_irq;
86a74ff2 1343
b0ca2a21
NI		 1344 if (intr_status & (EESR_FRC | /* Frame recv*/
1345 EESR_RMAF | /* Multi cast address recv*/
1346 EESR_RRF | /* Bit frame recv */
1347 EESR_RTLF | /* Long frame recv*/
1348 EESR_RTSF | /* short frame recv */
1349 EESR_PRE | /* PHY-LSI recv error */
1350 EESR_CERF)){ /* recv frame CRC error */
a18e08bd 1351 sh_eth_rx(ndev, intr_status);
b0ca2a21 1352 }
86a74ff2 1353
b0ca2a21 1354 /* Tx Check */
380af9e3 1355 if (intr_status & cd->tx_check) {
86a74ff2
NI		 1356 sh_eth_txfree(ndev);
1357 netif_wake_queue(ndev);
1358 }
1359
380af9e3 1360 if (intr_status & cd->eesr_err_check)
86a74ff2
NI		 1361 sh_eth_error(ndev, intr_status);
1362
0e0fde3c 1363other_irq:
86a74ff2
NI		 1364 spin_unlock(&mdp->lock);
1365
0e0fde3c 1366 return ret;
86a74ff2
NI		 1367}
1368
86a74ff2
NI		 1369/* PHY state control function */
1370static void sh_eth_adjust_link(struct net_device *ndev)
1371{
1372 struct sh_eth_private *mdp = netdev_priv(ndev);
1373 struct phy_device *phydev = mdp->phydev;
86a74ff2
NI		 1374 int new_state = 0;
1375
1376 if (phydev->link != PHY_DOWN) {
1377 if (phydev->duplex != mdp->duplex) {
1378 new_state = 1;
1379 mdp->duplex = phydev->duplex;
380af9e3
YS		 1380 if (mdp->cd->set_duplex)
1381 mdp->cd->set_duplex(ndev);
86a74ff2
NI		 1382 }
1383
1384 if (phydev->speed != mdp->speed) {
1385 new_state = 1;
1386 mdp->speed = phydev->speed;
380af9e3
YS		 1387 if (mdp->cd->set_rate)
1388 mdp->cd->set_rate(ndev);
86a74ff2
NI		 1389 }
1390 if (mdp->link == PHY_DOWN) {
91a56152
YS		 1391 sh_eth_write(ndev,
1392 (sh_eth_read(ndev, ECMR) & ~ECMR_TXF), ECMR);
86a74ff2
NI		 1393 new_state = 1;
1394 mdp->link = phydev->link;
86a74ff2
NI		 1395 }
1396 } else if (mdp->link) {
1397 new_state = 1;
1398 mdp->link = PHY_DOWN;
1399 mdp->speed = 0;
1400 mdp->duplex = -1;
86a74ff2
NI		 1401 }
1402
dc19e4e5 1403 if (new_state && netif_msg_link(mdp))
86a74ff2
NI		 1404 phy_print_status(phydev);
1405}
1406
1407/* PHY init function */
1408static int sh_eth_phy_init(struct net_device *ndev)
1409{
1410 struct sh_eth_private *mdp = netdev_priv(ndev);
0a372eb9 1411 char phy_id[MII_BUS_ID_SIZE + 3];
86a74ff2
NI		 1412 struct phy_device *phydev = NULL;
1413
fb28ad35 1414 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
86a74ff2
NI		 1415 mdp->mii_bus->id , mdp->phy_id);
1416
1417 mdp->link = PHY_DOWN;
1418 mdp->speed = 0;
1419 mdp->duplex = -1;
1420
1421 /* Try connect to PHY */
c061b18d 1422 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
f9a8f83b 1423 mdp->phy_interface);
86a74ff2
NI		 1424 if (IS_ERR(phydev)) {
1425 dev_err(&ndev->dev, "phy_connect failed\n");
1426 return PTR_ERR(phydev);
1427 }
380af9e3 1428
86a74ff2 1429 dev_info(&ndev->dev, "attached phy %i to driver %s\n",
380af9e3 1430 phydev->addr, phydev->drv->name);
86a74ff2
NI		 1431
1432 mdp->phydev = phydev;
1433
1434 return 0;
1435}
1436
1437/* PHY control start function */
1438static int sh_eth_phy_start(struct net_device *ndev)
1439{
1440 struct sh_eth_private *mdp = netdev_priv(ndev);
1441 int ret;
1442
1443 ret = sh_eth_phy_init(ndev);
1444 if (ret)
1445 return ret;
1446
1447 /* reset phy - this also wakes it from PDOWN */
1448 phy_write(mdp->phydev, MII_BMCR, BMCR_RESET);
1449 phy_start(mdp->phydev);
1450
1451 return 0;
1452}
1453
dc19e4e5
NI		 1454static int sh_eth_get_settings(struct net_device *ndev,
1455 struct ethtool_cmd *ecmd)
1456{
1457 struct sh_eth_private *mdp = netdev_priv(ndev);
1458 unsigned long flags;
1459 int ret;
1460
1461 spin_lock_irqsave(&mdp->lock, flags);
1462 ret = phy_ethtool_gset(mdp->phydev, ecmd);
1463 spin_unlock_irqrestore(&mdp->lock, flags);
1464
1465 return ret;
1466}
1467
1468static int sh_eth_set_settings(struct net_device *ndev,
1469 struct ethtool_cmd *ecmd)
1470{
1471 struct sh_eth_private *mdp = netdev_priv(ndev);
1472 unsigned long flags;
1473 int ret;
dc19e4e5
NI		 1474
1475 spin_lock_irqsave(&mdp->lock, flags);
1476
1477 /* disable tx and rx */
4a55530f 1478 sh_eth_rcv_snd_disable(ndev);
dc19e4e5
NI		 1479
1480 ret = phy_ethtool_sset(mdp->phydev, ecmd);
1481 if (ret)
1482 goto error_exit;
1483
1484 if (ecmd->duplex == DUPLEX_FULL)
1485 mdp->duplex = 1;
1486 else
1487 mdp->duplex = 0;
1488
1489 if (mdp->cd->set_duplex)
1490 mdp->cd->set_duplex(ndev);
1491
1492error_exit:
1493 mdelay(1);
1494
1495 /* enable tx and rx */
4a55530f 1496 sh_eth_rcv_snd_enable(ndev);
dc19e4e5
NI		 1497
1498 spin_unlock_irqrestore(&mdp->lock, flags);
1499
1500 return ret;
1501}
1502
1503static int sh_eth_nway_reset(struct net_device *ndev)
1504{
1505 struct sh_eth_private *mdp = netdev_priv(ndev);
1506 unsigned long flags;
1507 int ret;
1508
1509 spin_lock_irqsave(&mdp->lock, flags);
1510 ret = phy_start_aneg(mdp->phydev);
1511 spin_unlock_irqrestore(&mdp->lock, flags);
1512
1513 return ret;
1514}
1515
1516static u32 sh_eth_get_msglevel(struct net_device *ndev)
1517{
1518 struct sh_eth_private *mdp = netdev_priv(ndev);
1519 return mdp->msg_enable;
1520}
1521
1522static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
1523{
1524 struct sh_eth_private *mdp = netdev_priv(ndev);
1525 mdp->msg_enable = value;
1526}
1527
1528static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
1529 "rx_current", "tx_current",
1530 "rx_dirty", "tx_dirty",
1531};
1532#define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats)
1533
1534static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
1535{
1536 switch (sset) {
1537 case ETH_SS_STATS:
1538 return SH_ETH_STATS_LEN;
1539 default:
1540 return -EOPNOTSUPP;
1541 }
1542}
1543
1544static void sh_eth_get_ethtool_stats(struct net_device *ndev,
1545 struct ethtool_stats *stats, u64 *data)
1546{
1547 struct sh_eth_private *mdp = netdev_priv(ndev);
1548 int i = 0;
1549
1550 /* device-specific stats */
1551 data[i++] = mdp->cur_rx;
1552 data[i++] = mdp->cur_tx;
1553 data[i++] = mdp->dirty_rx;
1554 data[i++] = mdp->dirty_tx;
1555}
1556
1557static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1558{
1559 switch (stringset) {
1560 case ETH_SS_STATS:
1561 memcpy(data, *sh_eth_gstrings_stats,
1562 sizeof(sh_eth_gstrings_stats));
1563 break;
1564 }
1565}
1566
525b8075
YS		 1567static void sh_eth_get_ringparam(struct net_device *ndev,
1568 struct ethtool_ringparam *ring)
1569{
1570 struct sh_eth_private *mdp = netdev_priv(ndev);
1571
1572 ring->rx_max_pending = RX_RING_MAX;
1573 ring->tx_max_pending = TX_RING_MAX;
1574 ring->rx_pending = mdp->num_rx_ring;
1575 ring->tx_pending = mdp->num_tx_ring;
1576}
1577
1578static int sh_eth_set_ringparam(struct net_device *ndev,
1579 struct ethtool_ringparam *ring)
1580{
1581 struct sh_eth_private *mdp = netdev_priv(ndev);
1582 int ret;
1583
1584 if (ring->tx_pending > TX_RING_MAX ||
1585 ring->rx_pending > RX_RING_MAX ||
1586 ring->tx_pending < TX_RING_MIN ||
1587 ring->rx_pending < RX_RING_MIN)
1588 return -EINVAL;
1589 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
1590 return -EINVAL;
1591
1592 if (netif_running(ndev)) {
1593 netif_tx_disable(ndev);
1594 /* Disable interrupts by clearing the interrupt mask. */
1595 sh_eth_write(ndev, 0x0000, EESIPR);
1596 /* Stop the chip's Tx and Rx processes. */
1597 sh_eth_write(ndev, 0, EDTRR);
1598 sh_eth_write(ndev, 0, EDRRR);
1599 synchronize_irq(ndev->irq);
1600 }
1601
1602 /* Free all the skbuffs in the Rx queue. */
1603 sh_eth_ring_free(ndev);
1604 /* Free DMA buffer */
1605 sh_eth_free_dma_buffer(mdp);
1606
1607 /* Set new parameters */
1608 mdp->num_rx_ring = ring->rx_pending;
1609 mdp->num_tx_ring = ring->tx_pending;
1610
1611 ret = sh_eth_ring_init(ndev);
1612 if (ret < 0) {
1613 dev_err(&ndev->dev, "%s: sh_eth_ring_init failed.\n", __func__);
1614 return ret;
1615 }
1616 ret = sh_eth_dev_init(ndev, false);
1617 if (ret < 0) {
1618 dev_err(&ndev->dev, "%s: sh_eth_dev_init failed.\n", __func__);
1619 return ret;
1620 }
1621
1622 if (netif_running(ndev)) {
1623 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1624 /* Setting the Rx mode will start the Rx process. */
1625 sh_eth_write(ndev, EDRRR_R, EDRRR);
1626 netif_wake_queue(ndev);
1627 }
1628
1629 return 0;
1630}
1631
9b07be4b 1632static const struct ethtool_ops sh_eth_ethtool_ops = {
dc19e4e5
NI		 1633 .get_settings = sh_eth_get_settings,
1634 .set_settings = sh_eth_set_settings,
9b07be4b 1635 .nway_reset = sh_eth_nway_reset,
dc19e4e5
NI		 1636 .get_msglevel = sh_eth_get_msglevel,
1637 .set_msglevel = sh_eth_set_msglevel,
9b07be4b 1638 .get_link = ethtool_op_get_link,
dc19e4e5
NI		 1639 .get_strings = sh_eth_get_strings,
1640 .get_ethtool_stats = sh_eth_get_ethtool_stats,
1641 .get_sset_count = sh_eth_get_sset_count,
525b8075
YS		 1642 .get_ringparam = sh_eth_get_ringparam,
1643 .set_ringparam = sh_eth_set_ringparam,
dc19e4e5
NI		 1644};
1645
86a74ff2
NI		 1646/* network device open function */
1647static int sh_eth_open(struct net_device *ndev)
1648{
1649 int ret = 0;
1650 struct sh_eth_private *mdp = netdev_priv(ndev);
1651
bcd5149d
MD		 1652 pm_runtime_get_sync(&mdp->pdev->dev);
1653
a0607fd3 1654 ret = request_irq(ndev->irq, sh_eth_interrupt,
f29a3d04 1655#if defined(CONFIG_CPU_SUBTYPE_SH7763) || \
dc19e4e5
NI		 1656 defined(CONFIG_CPU_SUBTYPE_SH7764) || \
1657 defined(CONFIG_CPU_SUBTYPE_SH7757)
0e0fde3c
NI		 1658 IRQF_SHARED,
1659#else
1660 0,
1661#endif
1662 ndev->name, ndev);
86a74ff2 1663 if (ret) {
380af9e3 1664 dev_err(&ndev->dev, "Can not assign IRQ number\n");
86a74ff2
NI		 1665 return ret;
1666 }
1667
1668 /* Descriptor set */
1669 ret = sh_eth_ring_init(ndev);
1670 if (ret)
1671 goto out_free_irq;
1672
1673 /* device init */
525b8075 1674 ret = sh_eth_dev_init(ndev, true);
86a74ff2
NI		 1675 if (ret)
1676 goto out_free_irq;
1677
1678 /* PHY control start*/
1679 ret = sh_eth_phy_start(ndev);
1680 if (ret)
1681 goto out_free_irq;
1682
86a74ff2
NI		 1683 return ret;
1684
1685out_free_irq:
1686 free_irq(ndev->irq, ndev);
bcd5149d 1687 pm_runtime_put_sync(&mdp->pdev->dev);
86a74ff2
NI		 1688 return ret;
1689}
1690
1691/* Timeout function */
1692static void sh_eth_tx_timeout(struct net_device *ndev)
1693{
1694 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 1695 struct sh_eth_rxdesc *rxdesc;
1696 int i;
1697
1698 netif_stop_queue(ndev);
1699
dc19e4e5
NI		 1700 if (netif_msg_timer(mdp))
1701 dev_err(&ndev->dev, "%s: transmit timed out, status %8.8x,"
4a55530f 1702 " resetting...\n", ndev->name, (int)sh_eth_read(ndev, EESR));
86a74ff2
NI		 1703
1704 /* tx_errors count up */
bb7d92e3 1705 ndev->stats.tx_errors++;
86a74ff2 1706
86a74ff2 1707 /* Free all the skbuffs in the Rx queue. */
525b8075 1708 for (i = 0; i < mdp->num_rx_ring; i++) {
86a74ff2
NI		 1709 rxdesc = &mdp->rx_ring[i];
1710 rxdesc->status = 0;
1711 rxdesc->addr = 0xBADF00D0;
1712 if (mdp->rx_skbuff[i])
1713 dev_kfree_skb(mdp->rx_skbuff[i]);
1714 mdp->rx_skbuff[i] = NULL;
1715 }
525b8075 1716 for (i = 0; i < mdp->num_tx_ring; i++) {
86a74ff2
NI		 1717 if (mdp->tx_skbuff[i])
1718 dev_kfree_skb(mdp->tx_skbuff[i]);
1719 mdp->tx_skbuff[i] = NULL;
1720 }
1721
1722 /* device init */
525b8075 1723 sh_eth_dev_init(ndev, true);
86a74ff2
NI		 1724}
1725
1726/* Packet transmit function */
1727static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1728{
1729 struct sh_eth_private *mdp = netdev_priv(ndev);
1730 struct sh_eth_txdesc *txdesc;
1731 u32 entry;
fb5e2f9b 1732 unsigned long flags;
86a74ff2
NI		 1733
1734 spin_lock_irqsave(&mdp->lock, flags);
525b8075 1735 if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
86a74ff2 1736 if (!sh_eth_txfree(ndev)) {
dc19e4e5
NI		 1737 if (netif_msg_tx_queued(mdp))
1738 dev_warn(&ndev->dev, "TxFD exhausted.\n");
86a74ff2
NI		 1739 netif_stop_queue(ndev);
1740 spin_unlock_irqrestore(&mdp->lock, flags);
5b548140 1741 return NETDEV_TX_BUSY;
86a74ff2
NI		 1742 }
1743 }
1744 spin_unlock_irqrestore(&mdp->lock, flags);
1745
525b8075 1746 entry = mdp->cur_tx % mdp->num_tx_ring;
86a74ff2
NI		 1747 mdp->tx_skbuff[entry] = skb;
1748 txdesc = &mdp->tx_ring[entry];
86a74ff2 1749 /* soft swap. */
380af9e3
YS		 1750 if (!mdp->cd->hw_swap)
1751 sh_eth_soft_swap(phys_to_virt(ALIGN(txdesc->addr, 4)),
1752 skb->len + 2);
31fcb99d
YS		 1753 txdesc->addr = dma_map_single(&ndev->dev, skb->data, skb->len,
1754 DMA_TO_DEVICE);
86a74ff2
NI		 1755 if (skb->len < ETHERSMALL)
1756 txdesc->buffer_length = ETHERSMALL;
1757 else
1758 txdesc->buffer_length = skb->len;
1759
525b8075 1760 if (entry >= mdp->num_tx_ring - 1)
71557a37 1761 txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE);
86a74ff2 1762 else
71557a37 1763 txdesc->status |= cpu_to_edmac(mdp, TD_TACT);
86a74ff2
NI		 1764
1765 mdp->cur_tx++;
1766
c5ed5368
YS		 1767 if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
1768 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
b0ca2a21 1769
6ed10654 1770 return NETDEV_TX_OK;
86a74ff2
NI		 1771}
1772
1773/* device close function */
1774static int sh_eth_close(struct net_device *ndev)
1775{
1776 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 1777
1778 netif_stop_queue(ndev);
1779
1780 /* Disable interrupts by clearing the interrupt mask. */
4a55530f 1781 sh_eth_write(ndev, 0x0000, EESIPR);
86a74ff2
NI		 1782
1783 /* Stop the chip's Tx and Rx processes. */
4a55530f
YS		 1784 sh_eth_write(ndev, 0, EDTRR);
1785 sh_eth_write(ndev, 0, EDRRR);
86a74ff2
NI		 1786
1787 /* PHY Disconnect */
1788 if (mdp->phydev) {
1789 phy_stop(mdp->phydev);
1790 phy_disconnect(mdp->phydev);
1791 }
1792
1793 free_irq(ndev->irq, ndev);
1794
86a74ff2
NI		 1795 /* Free all the skbuffs in the Rx queue. */
1796 sh_eth_ring_free(ndev);
1797
1798 /* free DMA buffer */
91c77550 1799 sh_eth_free_dma_buffer(mdp);
86a74ff2 1800
bcd5149d
MD		 1801 pm_runtime_put_sync(&mdp->pdev->dev);
1802
86a74ff2
NI		 1803 return 0;
1804}
1805
1806static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
1807{
1808 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2 1809
bcd5149d
MD		 1810 pm_runtime_get_sync(&mdp->pdev->dev);
1811
bb7d92e3 1812 ndev->stats.tx_dropped += sh_eth_read(ndev, TROCR);
4a55530f 1813 sh_eth_write(ndev, 0, TROCR); /* (write clear) */
bb7d92e3 1814 ndev->stats.collisions += sh_eth_read(ndev, CDCR);
4a55530f 1815 sh_eth_write(ndev, 0, CDCR); /* (write clear) */
bb7d92e3 1816 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, LCCR);
4a55530f 1817 sh_eth_write(ndev, 0, LCCR); /* (write clear) */
c5ed5368 1818 if (sh_eth_is_gether(mdp)) {
bb7d92e3 1819 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CERCR);
c5ed5368 1820 sh_eth_write(ndev, 0, CERCR); /* (write clear) */
bb7d92e3 1821 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CEECR);
c5ed5368
YS		 1822 sh_eth_write(ndev, 0, CEECR); /* (write clear) */
1823 } else {
bb7d92e3 1824 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CNDCR);
c5ed5368
YS		 1825 sh_eth_write(ndev, 0, CNDCR); /* (write clear) */
1826 }
bcd5149d
MD		 1827 pm_runtime_put_sync(&mdp->pdev->dev);
1828
bb7d92e3 1829 return &ndev->stats;
86a74ff2
NI		 1830}
1831
bb7d92e3 1832/* ioctl to device function */
86a74ff2
NI		 1833static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq,
1834 int cmd)
1835{
1836 struct sh_eth_private *mdp = netdev_priv(ndev);
1837 struct phy_device *phydev = mdp->phydev;
1838
1839 if (!netif_running(ndev))
1840 return -EINVAL;
1841
1842 if (!phydev)
1843 return -ENODEV;
1844
28b04113 1845 return phy_mii_ioctl(phydev, rq, cmd);
86a74ff2
NI		 1846}
1847
380af9e3 1848#if defined(SH_ETH_HAS_TSU)
6743fe6d
YS		 1849/* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
1850static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp,
1851 int entry)
1852{
1853 return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4);
1854}
1855
1856static u32 sh_eth_tsu_get_post_mask(int entry)
1857{
1858 return 0x0f << (28 - ((entry % 8) * 4));
1859}
1860
1861static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
1862{
1863 return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
1864}
1865
1866static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
1867 int entry)
1868{
1869 struct sh_eth_private *mdp = netdev_priv(ndev);
1870 u32 tmp;
1871 void *reg_offset;
1872
1873 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
1874 tmp = ioread32(reg_offset);
1875 iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset);
1876}
1877
1878static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
1879 int entry)
1880{
1881 struct sh_eth_private *mdp = netdev_priv(ndev);
1882 u32 post_mask, ref_mask, tmp;
1883 void *reg_offset;
1884
1885 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
1886 post_mask = sh_eth_tsu_get_post_mask(entry);
1887 ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
1888
1889 tmp = ioread32(reg_offset);
1890 iowrite32(tmp & ~post_mask, reg_offset);
1891
1892 /* If other port enables, the function returns "true" */
1893 return tmp & ref_mask;
1894}
1895
1896static int sh_eth_tsu_busy(struct net_device *ndev)
1897{
1898 int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
1899 struct sh_eth_private *mdp = netdev_priv(ndev);
1900
1901 while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
1902 udelay(10);
1903 timeout--;
1904 if (timeout <= 0) {
1905 dev_err(&ndev->dev, "%s: timeout\n", __func__);
1906 return -ETIMEDOUT;
1907 }
1908 }
1909
1910 return 0;
1911}
1912
1913static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg,
1914 const u8 *addr)
1915{
1916 u32 val;
1917
1918 val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
1919 iowrite32(val, reg);
1920 if (sh_eth_tsu_busy(ndev) < 0)
1921 return -EBUSY;
1922
1923 val = addr[4] << 8 | addr[5];
1924 iowrite32(val, reg + 4);
1925 if (sh_eth_tsu_busy(ndev) < 0)
1926 return -EBUSY;
1927
1928 return 0;
1929}
1930
1931static void sh_eth_tsu_read_entry(void *reg, u8 *addr)
1932{
1933 u32 val;
1934
1935 val = ioread32(reg);
1936 addr[0] = (val >> 24) & 0xff;
1937 addr[1] = (val >> 16) & 0xff;
1938 addr[2] = (val >> 8) & 0xff;
1939 addr[3] = val & 0xff;
1940 val = ioread32(reg + 4);
1941 addr[4] = (val >> 8) & 0xff;
1942 addr[5] = val & 0xff;
1943}
1944
1945
1946static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
1947{
1948 struct sh_eth_private *mdp = netdev_priv(ndev);
1949 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
1950 int i;
1951 u8 c_addr[ETH_ALEN];
1952
1953 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
1954 sh_eth_tsu_read_entry(reg_offset, c_addr);
1955 if (memcmp(addr, c_addr, ETH_ALEN) == 0)
1956 return i;
1957 }
1958
1959 return -ENOENT;
1960}
1961
1962static int sh_eth_tsu_find_empty(struct net_device *ndev)
1963{
1964 u8 blank[ETH_ALEN];
1965 int entry;
1966
1967 memset(blank, 0, sizeof(blank));
1968 entry = sh_eth_tsu_find_entry(ndev, blank);
1969 return (entry < 0) ? -ENOMEM : entry;
1970}
1971
1972static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
1973 int entry)
1974{
1975 struct sh_eth_private *mdp = netdev_priv(ndev);
1976 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
1977 int ret;
1978 u8 blank[ETH_ALEN];
1979
1980 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
1981 ~(1 << (31 - entry)), TSU_TEN);
1982
1983 memset(blank, 0, sizeof(blank));
1984 ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
1985 if (ret < 0)
1986 return ret;
1987 return 0;
1988}
1989
1990static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
1991{
1992 struct sh_eth_private *mdp = netdev_priv(ndev);
1993 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
1994 int i, ret;
1995
1996 if (!mdp->cd->tsu)
1997 return 0;
1998
1999 i = sh_eth_tsu_find_entry(ndev, addr);
2000 if (i < 0) {
2001 /* No entry found, create one */
2002 i = sh_eth_tsu_find_empty(ndev);
2003 if (i < 0)
2004 return -ENOMEM;
2005 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
2006 if (ret < 0)
2007 return ret;
2008
2009 /* Enable the entry */
2010 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
2011 (1 << (31 - i)), TSU_TEN);
2012 }
2013
2014 /* Entry found or created, enable POST */
2015 sh_eth_tsu_enable_cam_entry_post(ndev, i);
2016
2017 return 0;
2018}
2019
2020static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
2021{
2022 struct sh_eth_private *mdp = netdev_priv(ndev);
2023 int i, ret;
2024
2025 if (!mdp->cd->tsu)
2026 return 0;
2027
2028 i = sh_eth_tsu_find_entry(ndev, addr);
2029 if (i) {
2030 /* Entry found */
2031 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2032 goto done;
2033
2034 /* Disable the entry if both ports was disabled */
2035 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2036 if (ret < 0)
2037 return ret;
2038 }
2039done:
2040 return 0;
2041}
2042
2043static int sh_eth_tsu_purge_all(struct net_device *ndev)
2044{
2045 struct sh_eth_private *mdp = netdev_priv(ndev);
2046 int i, ret;
2047
2048 if (unlikely(!mdp->cd->tsu))
2049 return 0;
2050
2051 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
2052 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2053 continue;
2054
2055 /* Disable the entry if both ports was disabled */
2056 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2057 if (ret < 0)
2058 return ret;
2059 }
2060
2061 return 0;
2062}
2063
2064static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
2065{
2066 struct sh_eth_private *mdp = netdev_priv(ndev);
2067 u8 addr[ETH_ALEN];
2068 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2069 int i;
2070
2071 if (unlikely(!mdp->cd->tsu))
2072 return;
2073
2074 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2075 sh_eth_tsu_read_entry(reg_offset, addr);
2076 if (is_multicast_ether_addr(addr))
2077 sh_eth_tsu_del_entry(ndev, addr);
2078 }
2079}
2080
86a74ff2
NI		 2081/* Multicast reception directions set */
2082static void sh_eth_set_multicast_list(struct net_device *ndev)
2083{
6743fe6d
YS		 2084 struct sh_eth_private *mdp = netdev_priv(ndev);
2085 u32 ecmr_bits;
2086 int mcast_all = 0;
2087 unsigned long flags;
2088
2089 spin_lock_irqsave(&mdp->lock, flags);
2090 /*
2091 * Initial condition is MCT = 1, PRM = 0.
2092 * Depending on ndev->flags, set PRM or clear MCT
2093 */
2094 ecmr_bits = (sh_eth_read(ndev, ECMR) & ~ECMR_PRM) | ECMR_MCT;
2095
2096 if (!(ndev->flags & IFF_MULTICAST)) {
2097 sh_eth_tsu_purge_mcast(ndev);
2098 mcast_all = 1;
2099 }
2100 if (ndev->flags & IFF_ALLMULTI) {
2101 sh_eth_tsu_purge_mcast(ndev);
2102 ecmr_bits &= ~ECMR_MCT;
2103 mcast_all = 1;
2104 }
2105
86a74ff2 2106 if (ndev->flags & IFF_PROMISC) {
6743fe6d
YS		 2107 sh_eth_tsu_purge_all(ndev);
2108 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2109 } else if (mdp->cd->tsu) {
2110 struct netdev_hw_addr *ha;
2111 netdev_for_each_mc_addr(ha, ndev) {
2112 if (mcast_all && is_multicast_ether_addr(ha->addr))
2113 continue;
2114
2115 if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2116 if (!mcast_all) {
2117 sh_eth_tsu_purge_mcast(ndev);
2118 ecmr_bits &= ~ECMR_MCT;
2119 mcast_all = 1;
2120 }
2121 }
2122 }
86a74ff2
NI		 2123 } else {
2124 /* Normal, unicast/broadcast-only mode. */
6743fe6d 2125 ecmr_bits = (ecmr_bits & ~ECMR_PRM) | ECMR_MCT;
86a74ff2 2126 }
6743fe6d
YS		 2127
2128 /* update the ethernet mode */
2129 sh_eth_write(ndev, ecmr_bits, ECMR);
2130
2131 spin_unlock_irqrestore(&mdp->lock, flags);
86a74ff2 2132}
71cc7c37
YS		 2133
2134static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2135{
2136 if (!mdp->port)
2137 return TSU_VTAG0;
2138 else
2139 return TSU_VTAG1;
2140}
2141
2142static int sh_eth_vlan_rx_add_vid(struct net_device *ndev, u16 vid)
2143{
2144 struct sh_eth_private *mdp = netdev_priv(ndev);
2145 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2146
2147 if (unlikely(!mdp->cd->tsu))
2148 return -EPERM;
2149
2150 /* No filtering if vid = 0 */
2151 if (!vid)
2152 return 0;
2153
2154 mdp->vlan_num_ids++;
2155
2156 /*
2157 * The controller has one VLAN tag HW filter. So, if the filter is
2158 * already enabled, the driver disables it and the filte
2159 */
2160 if (mdp->vlan_num_ids > 1) {
2161 /* disable VLAN filter */
2162 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2163 return 0;
2164 }
2165
2166 sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
2167 vtag_reg_index);
2168
2169 return 0;
2170}
2171
2172static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev, u16 vid)
2173{
2174 struct sh_eth_private *mdp = netdev_priv(ndev);
2175 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2176
2177 if (unlikely(!mdp->cd->tsu))
2178 return -EPERM;
2179
2180 /* No filtering if vid = 0 */
2181 if (!vid)
2182 return 0;
2183
2184 mdp->vlan_num_ids--;
2185 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2186
2187 return 0;
2188}
4986b996 2189#endif /* SH_ETH_HAS_TSU */
86a74ff2
NI		 2190
2191/* SuperH's TSU register init function */
4a55530f 2192static void sh_eth_tsu_init(struct sh_eth_private *mdp)
86a74ff2 2193{
4a55530f
YS		 2194 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */
2195 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */
2196 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */
2197 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
2198 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
2199 sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
2200 sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
2201 sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
2202 sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
2203 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
c5ed5368
YS		 2204 if (sh_eth_is_gether(mdp)) {
2205 sh_eth_tsu_write(mdp, 0, TSU_QTAG0); /* Disable QTAG(0->1) */
2206 sh_eth_tsu_write(mdp, 0, TSU_QTAG1); /* Disable QTAG(1->0) */
2207 } else {
2208 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */
2209 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */
2210 }
4a55530f
YS		 2211 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */
2212 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */
2213 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2214 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */
2215 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */
2216 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */
2217 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */
86a74ff2
NI		 2218}
2219
2220/* MDIO bus release function */
2221static int sh_mdio_release(struct net_device *ndev)
2222{
0582b7d1 2223 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 2224 struct mii_bus *bus = dev_get_drvdata(&ndev->dev);
2225
2226 /* unregister mdio bus */
2227 mdiobus_unregister(bus);
2228
2229 /* remove mdio bus info from net_device */
2230 dev_set_drvdata(&ndev->dev, NULL);
2231
0f0b405c
DK		 2232 /* free interrupts memory */
2233 kfree(bus->irq);
2234
86a74ff2
NI		 2235 /* free bitbang info */
2236 free_mdio_bitbang(bus);
2237
0582b7d1
SS		 2238 /* free bitbang memory */
2239 kfree(mdp->bitbang);
2240
86a74ff2
NI		 2241 return 0;
2242}
2243
2244/* MDIO bus init function */
b3017e6a
YS		 2245static int sh_mdio_init(struct net_device *ndev, int id,
2246 struct sh_eth_plat_data *pd)
86a74ff2
NI		 2247{
2248 int ret, i;
2249 struct bb_info *bitbang;
2250 struct sh_eth_private *mdp = netdev_priv(ndev);
2251
2252 /* create bit control struct for PHY */
2253 bitbang = kzalloc(sizeof(struct bb_info), GFP_KERNEL);
2254 if (!bitbang) {
2255 ret = -ENOMEM;
2256 goto out;
2257 }
2258
2259 /* bitbang init */
ae70644d 2260 bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
b3017e6a 2261 bitbang->set_gate = pd->set_mdio_gate;
86a74ff2
NI		 2262 bitbang->mdi_msk = 0x08;
2263 bitbang->mdo_msk = 0x04;
2264 bitbang->mmd_msk = 0x02;/* MMD */
2265 bitbang->mdc_msk = 0x01;
2266 bitbang->ctrl.ops = &bb_ops;
2267
c2e07b3a 2268 /* MII controller setting */
0582b7d1 2269 mdp->bitbang = bitbang;
86a74ff2
NI		 2270 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
2271 if (!mdp->mii_bus) {
2272 ret = -ENOMEM;
2273 goto out_free_bitbang;
2274 }
2275
2276 /* Hook up MII support for ethtool */
2277 mdp->mii_bus->name = "sh_mii";
18ee49dd 2278 mdp->mii_bus->parent = &ndev->dev;
5278fb54 2279 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
34aa6f14 2280 mdp->pdev->name, id);
86a74ff2
NI		 2281
2282 /* PHY IRQ */
2283 mdp->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
2284 if (!mdp->mii_bus->irq) {
2285 ret = -ENOMEM;
2286 goto out_free_bus;
2287 }
2288
2289 for (i = 0; i < PHY_MAX_ADDR; i++)
2290 mdp->mii_bus->irq[i] = PHY_POLL;
2291
8f6352f2 2292 /* register mdio bus */
86a74ff2
NI		 2293 ret = mdiobus_register(mdp->mii_bus);
2294 if (ret)
2295 goto out_free_irq;
2296
2297 dev_set_drvdata(&ndev->dev, mdp->mii_bus);
2298
2299 return 0;
2300
2301out_free_irq:
2302 kfree(mdp->mii_bus->irq);
2303
2304out_free_bus:
298cf9be 2305 free_mdio_bitbang(mdp->mii_bus);
86a74ff2
NI		 2306
2307out_free_bitbang:
2308 kfree(bitbang);
2309
2310out:
2311 return ret;
2312}
2313
4a55530f
YS		 2314static const u16 *sh_eth_get_register_offset(int register_type)
2315{
2316 const u16 *reg_offset = NULL;
2317
2318 switch (register_type) {
2319 case SH_ETH_REG_GIGABIT:
2320 reg_offset = sh_eth_offset_gigabit;
2321 break;
2322 case SH_ETH_REG_FAST_SH4:
2323 reg_offset = sh_eth_offset_fast_sh4;
2324 break;
2325 case SH_ETH_REG_FAST_SH3_SH2:
2326 reg_offset = sh_eth_offset_fast_sh3_sh2;
2327 break;
2328 default:
2329 printk(KERN_ERR "Unknown register type (%d)\n", register_type);
2330 break;
2331 }
2332
2333 return reg_offset;
2334}
2335
ebf84eaa
AB		 2336static const struct net_device_ops sh_eth_netdev_ops = {
2337 .ndo_open = sh_eth_open,
2338 .ndo_stop = sh_eth_close,
2339 .ndo_start_xmit = sh_eth_start_xmit,
2340 .ndo_get_stats = sh_eth_get_stats,
380af9e3 2341#if defined(SH_ETH_HAS_TSU)
afc4b13d 2342 .ndo_set_rx_mode = sh_eth_set_multicast_list,
71cc7c37
YS		 2343 .ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid,
2344 .ndo_vlan_rx_kill_vid = sh_eth_vlan_rx_kill_vid,
380af9e3 2345#endif
ebf84eaa
AB		 2346 .ndo_tx_timeout = sh_eth_tx_timeout,
2347 .ndo_do_ioctl = sh_eth_do_ioctl,
2348 .ndo_validate_addr = eth_validate_addr,
2349 .ndo_set_mac_address = eth_mac_addr,
2350 .ndo_change_mtu = eth_change_mtu,
2351};
2352
86a74ff2
NI		 2353static int sh_eth_drv_probe(struct platform_device *pdev)
2354{
9c38657c 2355 int ret, devno = 0;
86a74ff2
NI		 2356 struct resource *res;
2357 struct net_device *ndev = NULL;
ec0d7551 2358 struct sh_eth_private *mdp = NULL;
71557a37 2359 struct sh_eth_plat_data *pd;
86a74ff2
NI		 2360
2361 /* get base addr */
2362 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2363 if (unlikely(res == NULL)) {
2364 dev_err(&pdev->dev, "invalid resource\n");
2365 ret = -EINVAL;
2366 goto out;
2367 }
2368
2369 ndev = alloc_etherdev(sizeof(struct sh_eth_private));
2370 if (!ndev) {
86a74ff2
NI		 2371 ret = -ENOMEM;
2372 goto out;
2373 }
2374
2375 /* The sh Ether-specific entries in the device structure. */
2376 ndev->base_addr = res->start;
2377 devno = pdev->id;
2378 if (devno < 0)
2379 devno = 0;
2380
2381 ndev->dma = -1;
cc3c080d 2382 ret = platform_get_irq(pdev, 0);
2383 if (ret < 0) {
86a74ff2
NI		 2384 ret = -ENODEV;
2385 goto out_release;
2386 }
cc3c080d 2387 ndev->irq = ret;
86a74ff2
NI		 2388
2389 SET_NETDEV_DEV(ndev, &pdev->dev);
2390
2391 /* Fill in the fields of the device structure with ethernet values. */
2392 ether_setup(ndev);
2393
2394 mdp = netdev_priv(ndev);
525b8075
YS		 2395 mdp->num_tx_ring = TX_RING_SIZE;
2396 mdp->num_rx_ring = RX_RING_SIZE;
ae70644d
YS		 2397 mdp->addr = ioremap(res->start, resource_size(res));
2398 if (mdp->addr == NULL) {
2399 ret = -ENOMEM;
2400 dev_err(&pdev->dev, "ioremap failed.\n");
2401 goto out_release;
2402 }
2403
86a74ff2 2404 spin_lock_init(&mdp->lock);
bcd5149d
MD		 2405 mdp->pdev = pdev;
2406 pm_runtime_enable(&pdev->dev);
2407 pm_runtime_resume(&pdev->dev);
86a74ff2 2408
71557a37 2409 pd = (struct sh_eth_plat_data *)(pdev->dev.platform_data);
86a74ff2 2410 /* get PHY ID */
71557a37 2411 mdp->phy_id = pd->phy;
e47c9052 2412 mdp->phy_interface = pd->phy_interface;
71557a37
YS		 2413 /* EDMAC endian */
2414 mdp->edmac_endian = pd->edmac_endian;
4923576b
YS		 2415 mdp->no_ether_link = pd->no_ether_link;
2416 mdp->ether_link_active_low = pd->ether_link_active_low;
4a55530f 2417 mdp->reg_offset = sh_eth_get_register_offset(pd->register_type);
86a74ff2 2418
380af9e3 2419 /* set cpu data */
8fcd4961
YS		 2420#if defined(SH_ETH_HAS_BOTH_MODULES)
2421 mdp->cd = sh_eth_get_cpu_data(mdp);
2422#else
380af9e3 2423 mdp->cd = &sh_eth_my_cpu_data;
8fcd4961 2424#endif
380af9e3
YS		 2425 sh_eth_set_default_cpu_data(mdp->cd);
2426
86a74ff2 2427 /* set function */
ebf84eaa 2428 ndev->netdev_ops = &sh_eth_netdev_ops;
dc19e4e5 2429 SET_ETHTOOL_OPS(ndev, &sh_eth_ethtool_ops);
86a74ff2
NI		 2430 ndev->watchdog_timeo = TX_TIMEOUT;
2431
dc19e4e5
NI		 2432 /* debug message level */
2433 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
86a74ff2
NI		 2434
2435 /* read and set MAC address */
748031f9 2436 read_mac_address(ndev, pd->mac_addr);
86a74ff2 2437
6ba88021
YS		 2438 /* ioremap the TSU registers */
2439 if (mdp->cd->tsu) {
2440 struct resource *rtsu;
2441 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2442 if (!rtsu) {
2443 dev_err(&pdev->dev, "Not found TSU resource\n");
043c4789 2444 ret = -ENODEV;
6ba88021
YS		 2445 goto out_release;
2446 }
2447 mdp->tsu_addr = ioremap(rtsu->start,
2448 resource_size(rtsu));
6743fe6d 2449 mdp->port = devno % 2;
71cc7c37 2450 ndev->features = NETIF_F_HW_VLAN_FILTER;
6ba88021
YS		 2451 }
2452
150647fb
YS		 2453 /* initialize first or needed device */
2454 if (!devno || pd->needs_init) {
380af9e3
YS		 2455 if (mdp->cd->chip_reset)
2456 mdp->cd->chip_reset(ndev);
86a74ff2 2457
4986b996
YS		 2458 if (mdp->cd->tsu) {
2459 /* TSU init (Init only)*/
2460 sh_eth_tsu_init(mdp);
2461 }
86a74ff2
NI		 2462 }
2463
2464 /* network device register */
2465 ret = register_netdev(ndev);
2466 if (ret)
2467 goto out_release;
2468
2469 /* mdio bus init */
b3017e6a 2470 ret = sh_mdio_init(ndev, pdev->id, pd);
86a74ff2
NI		 2471 if (ret)
2472 goto out_unregister;
2473
25985edc 2474 /* print device information */
6cd9b49d
HS		 2475 pr_info("Base address at 0x%x, %pM, IRQ %d.\n",
2476 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
86a74ff2
NI		 2477
2478 platform_set_drvdata(pdev, ndev);
2479
2480 return ret;
2481
2482out_unregister:
2483 unregister_netdev(ndev);
2484
2485out_release:
2486 /* net_dev free */
ae70644d
YS		 2487 if (mdp && mdp->addr)
2488 iounmap(mdp->addr);
ec0d7551 2489 if (mdp && mdp->tsu_addr)
4986b996 2490 iounmap(mdp->tsu_addr);
86a74ff2
NI		 2491 if (ndev)
2492 free_netdev(ndev);
2493
2494out:
2495 return ret;
2496}
2497
2498static int sh_eth_drv_remove(struct platform_device *pdev)
2499{
2500 struct net_device *ndev = platform_get_drvdata(pdev);
4986b996 2501 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2 2502
6ba88021
YS		 2503 if (mdp->cd->tsu)
2504 iounmap(mdp->tsu_addr);
86a74ff2
NI		 2505 sh_mdio_release(ndev);
2506 unregister_netdev(ndev);
bcd5149d 2507 pm_runtime_disable(&pdev->dev);
ae70644d 2508 iounmap(mdp->addr);
86a74ff2
NI		 2509 free_netdev(ndev);
2510 platform_set_drvdata(pdev, NULL);
2511
2512 return 0;
2513}
2514
bcd5149d
MD		 2515static int sh_eth_runtime_nop(struct device *dev)
2516{
2517 /*
2518 * Runtime PM callback shared between ->runtime_suspend()
2519 * and ->runtime_resume(). Simply returns success.
2520 *
2521 * This driver re-initializes all registers after
2522 * pm_runtime_get_sync() anyway so there is no need
2523 * to save and restore registers here.
2524 */
2525 return 0;
2526}
2527
2528static struct dev_pm_ops sh_eth_dev_pm_ops = {
2529 .runtime_suspend = sh_eth_runtime_nop,
2530 .runtime_resume = sh_eth_runtime_nop,
2531};
2532
86a74ff2
NI		 2533static struct platform_driver sh_eth_driver = {
2534 .probe = sh_eth_drv_probe,
2535 .remove = sh_eth_drv_remove,
2536 .driver = {
2537 .name = CARDNAME,
bcd5149d 2538 .pm = &sh_eth_dev_pm_ops,
86a74ff2
NI		 2539 },
2540};
2541
db62f684 2542module_platform_driver(sh_eth_driver);
86a74ff2
NI		 2543
2544MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
2545MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
2546MODULE_LICENSE("GPL v2");
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