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sh_eth: no need for *else* after *goto*
[mirror_ubuntu-hirsute-kernel.git] / drivers / net / ethernet / renesas / sh_eth.c
CommitLineData
128296fc 1/* SuperH Ethernet device driver
86a74ff2 2 *
966d6dbb 3 * Copyright (C) 2014 Renesas Electronics Corporation
f0e81fec 4 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu
b356e978 5 * Copyright (C) 2008-2014 Renesas Solutions Corp.
b2b14d2f 6 * Copyright (C) 2013-2016 Cogent Embedded, Inc.
702eca02 7 * Copyright (C) 2014 Codethink Limited
86a74ff2
NI		 8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms and conditions of the GNU General Public License,
11 * version 2, as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
86a74ff2
NI		 17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 */
21
0654011d
YS		 22#include <linux/module.h>
23#include <linux/kernel.h>
24#include <linux/spinlock.h>
6a27cded 25#include <linux/interrupt.h>
86a74ff2
NI		 26#include <linux/dma-mapping.h>
27#include <linux/etherdevice.h>
28#include <linux/delay.h>
29#include <linux/platform_device.h>
30#include <linux/mdio-bitbang.h>
31#include <linux/netdevice.h>
b356e978
SS		 32#include <linux/of.h>
33#include <linux/of_device.h>
34#include <linux/of_irq.h>
35#include <linux/of_net.h>
86a74ff2
NI		 36#include <linux/phy.h>
37#include <linux/cache.h>
38#include <linux/io.h>
bcd5149d 39#include <linux/pm_runtime.h>
5a0e3ad6 40#include <linux/slab.h>
dc19e4e5 41#include <linux/ethtool.h>
fdb37a7f 42#include <linux/if_vlan.h>
f0e81fec 43#include <linux/clk.h>
d4fa0e35 44#include <linux/sh_eth.h>
702eca02 45#include <linux/of_mdio.h>
86a74ff2
NI		 46
47#include "sh_eth.h"
48
dc19e4e5
NI		 49#define SH_ETH_DEF_MSG_ENABLE \
50 (NETIF_MSG_LINK | \
51 NETIF_MSG_TIMER | \
52 NETIF_MSG_RX_ERR| \
53 NETIF_MSG_TX_ERR)
54
2274d375
SS		 55#define SH_ETH_OFFSET_INVALID ((u16)~0)
56
3365711d
BH		 57#define SH_ETH_OFFSET_DEFAULTS \
58 [0 ... SH_ETH_MAX_REGISTER_OFFSET - 1] = SH_ETH_OFFSET_INVALID
59
c0013f6f 60static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
3365711d
BH		 61 SH_ETH_OFFSET_DEFAULTS,
62
c0013f6f
SS		 63 [EDSR] = 0x0000,
64 [EDMR] = 0x0400,
65 [EDTRR] = 0x0408,
66 [EDRRR] = 0x0410,
67 [EESR] = 0x0428,
68 [EESIPR] = 0x0430,
69 [TDLAR] = 0x0010,
70 [TDFAR] = 0x0014,
71 [TDFXR] = 0x0018,
72 [TDFFR] = 0x001c,
73 [RDLAR] = 0x0030,
74 [RDFAR] = 0x0034,
75 [RDFXR] = 0x0038,
76 [RDFFR] = 0x003c,
77 [TRSCER] = 0x0438,
78 [RMFCR] = 0x0440,
79 [TFTR] = 0x0448,
80 [FDR] = 0x0450,
81 [RMCR] = 0x0458,
82 [RPADIR] = 0x0460,
83 [FCFTR] = 0x0468,
84 [CSMR] = 0x04E4,
85
86 [ECMR] = 0x0500,
87 [ECSR] = 0x0510,
88 [ECSIPR] = 0x0518,
89 [PIR] = 0x0520,
90 [PSR] = 0x0528,
91 [PIPR] = 0x052c,
92 [RFLR] = 0x0508,
93 [APR] = 0x0554,
94 [MPR] = 0x0558,
95 [PFTCR] = 0x055c,
96 [PFRCR] = 0x0560,
97 [TPAUSER] = 0x0564,
98 [GECMR] = 0x05b0,
99 [BCULR] = 0x05b4,
100 [MAHR] = 0x05c0,
101 [MALR] = 0x05c8,
102 [TROCR] = 0x0700,
103 [CDCR] = 0x0708,
104 [LCCR] = 0x0710,
105 [CEFCR] = 0x0740,
106 [FRECR] = 0x0748,
107 [TSFRCR] = 0x0750,
108 [TLFRCR] = 0x0758,
109 [RFCR] = 0x0760,
110 [CERCR] = 0x0768,
111 [CEECR] = 0x0770,
112 [MAFCR] = 0x0778,
113 [RMII_MII] = 0x0790,
114
115 [ARSTR] = 0x0000,
116 [TSU_CTRST] = 0x0004,
117 [TSU_FWEN0] = 0x0010,
118 [TSU_FWEN1] = 0x0014,
119 [TSU_FCM] = 0x0018,
120 [TSU_BSYSL0] = 0x0020,
121 [TSU_BSYSL1] = 0x0024,
122 [TSU_PRISL0] = 0x0028,
123 [TSU_PRISL1] = 0x002c,
124 [TSU_FWSL0] = 0x0030,
125 [TSU_FWSL1] = 0x0034,
126 [TSU_FWSLC] = 0x0038,
127 [TSU_QTAG0] = 0x0040,
128 [TSU_QTAG1] = 0x0044,
129 [TSU_FWSR] = 0x0050,
130 [TSU_FWINMK] = 0x0054,
131 [TSU_ADQT0] = 0x0048,
132 [TSU_ADQT1] = 0x004c,
133 [TSU_VTAG0] = 0x0058,
134 [TSU_VTAG1] = 0x005c,
135 [TSU_ADSBSY] = 0x0060,
136 [TSU_TEN] = 0x0064,
137 [TSU_POST1] = 0x0070,
138 [TSU_POST2] = 0x0074,
139 [TSU_POST3] = 0x0078,
140 [TSU_POST4] = 0x007c,
141 [TSU_ADRH0] = 0x0100,
c0013f6f
SS		 142
143 [TXNLCR0] = 0x0080,
144 [TXALCR0] = 0x0084,
145 [RXNLCR0] = 0x0088,
146 [RXALCR0] = 0x008c,
147 [FWNLCR0] = 0x0090,
148 [FWALCR0] = 0x0094,
149 [TXNLCR1] = 0x00a0,
150 [TXALCR1] = 0x00a0,
151 [RXNLCR1] = 0x00a8,
152 [RXALCR1] = 0x00ac,
153 [FWNLCR1] = 0x00b0,
154 [FWALCR1] = 0x00b4,
155};
156
db893473 157static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
3365711d
BH		 158 SH_ETH_OFFSET_DEFAULTS,
159
db893473
SH		 160 [EDSR] = 0x0000,
161 [EDMR] = 0x0400,
162 [EDTRR] = 0x0408,
163 [EDRRR] = 0x0410,
164 [EESR] = 0x0428,
165 [EESIPR] = 0x0430,
166 [TDLAR] = 0x0010,
167 [TDFAR] = 0x0014,
168 [TDFXR] = 0x0018,
169 [TDFFR] = 0x001c,
170 [RDLAR] = 0x0030,
171 [RDFAR] = 0x0034,
172 [RDFXR] = 0x0038,
173 [RDFFR] = 0x003c,
174 [TRSCER] = 0x0438,
175 [RMFCR] = 0x0440,
176 [TFTR] = 0x0448,
177 [FDR] = 0x0450,
178 [RMCR] = 0x0458,
179 [RPADIR] = 0x0460,
180 [FCFTR] = 0x0468,
181 [CSMR] = 0x04E4,
182
183 [ECMR] = 0x0500,
184 [RFLR] = 0x0508,
185 [ECSR] = 0x0510,
186 [ECSIPR] = 0x0518,
187 [PIR] = 0x0520,
188 [APR] = 0x0554,
189 [MPR] = 0x0558,
190 [PFTCR] = 0x055c,
191 [PFRCR] = 0x0560,
192 [TPAUSER] = 0x0564,
193 [MAHR] = 0x05c0,
194 [MALR] = 0x05c8,
195 [CEFCR] = 0x0740,
196 [FRECR] = 0x0748,
197 [TSFRCR] = 0x0750,
198 [TLFRCR] = 0x0758,
199 [RFCR] = 0x0760,
200 [MAFCR] = 0x0778,
201
202 [ARSTR] = 0x0000,
203 [TSU_CTRST] = 0x0004,
e1487888 204 [TSU_FWSLC] = 0x0038,
db893473
SH		 205 [TSU_VTAG0] = 0x0058,
206 [TSU_ADSBSY] = 0x0060,
207 [TSU_TEN] = 0x0064,
e1487888
CB		 208 [TSU_POST1] = 0x0070,
209 [TSU_POST2] = 0x0074,
210 [TSU_POST3] = 0x0078,
211 [TSU_POST4] = 0x007c,
db893473 212 [TSU_ADRH0] = 0x0100,
db893473
SH		 213
214 [TXNLCR0] = 0x0080,
215 [TXALCR0] = 0x0084,
216 [RXNLCR0] = 0x0088,
217 [RXALCR0] = 0x008C,
218};
219
a3f109bd 220static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
3365711d
BH		 221 SH_ETH_OFFSET_DEFAULTS,
222
a3f109bd
SS		 223 [ECMR] = 0x0300,
224 [RFLR] = 0x0308,
225 [ECSR] = 0x0310,
226 [ECSIPR] = 0x0318,
227 [PIR] = 0x0320,
228 [PSR] = 0x0328,
229 [RDMLR] = 0x0340,
230 [IPGR] = 0x0350,
231 [APR] = 0x0354,
232 [MPR] = 0x0358,
233 [RFCF] = 0x0360,
234 [TPAUSER] = 0x0364,
235 [TPAUSECR] = 0x0368,
236 [MAHR] = 0x03c0,
237 [MALR] = 0x03c8,
238 [TROCR] = 0x03d0,
239 [CDCR] = 0x03d4,
240 [LCCR] = 0x03d8,
241 [CNDCR] = 0x03dc,
242 [CEFCR] = 0x03e4,
243 [FRECR] = 0x03e8,
244 [TSFRCR] = 0x03ec,
245 [TLFRCR] = 0x03f0,
246 [RFCR] = 0x03f4,
247 [MAFCR] = 0x03f8,
248
249 [EDMR] = 0x0200,
250 [EDTRR] = 0x0208,
251 [EDRRR] = 0x0210,
252 [TDLAR] = 0x0218,
253 [RDLAR] = 0x0220,
254 [EESR] = 0x0228,
255 [EESIPR] = 0x0230,
256 [TRSCER] = 0x0238,
257 [RMFCR] = 0x0240,
258 [TFTR] = 0x0248,
259 [FDR] = 0x0250,
260 [RMCR] = 0x0258,
261 [TFUCR] = 0x0264,
262 [RFOCR] = 0x0268,
55754f19 263 [RMIIMODE] = 0x026c,
a3f109bd
SS		 264 [FCFTR] = 0x0270,
265 [TRIMD] = 0x027c,
266};
267
c0013f6f 268static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
3365711d
BH		 269 SH_ETH_OFFSET_DEFAULTS,
270
c0013f6f
SS		 271 [ECMR] = 0x0100,
272 [RFLR] = 0x0108,
273 [ECSR] = 0x0110,
274 [ECSIPR] = 0x0118,
275 [PIR] = 0x0120,
276 [PSR] = 0x0128,
277 [RDMLR] = 0x0140,
278 [IPGR] = 0x0150,
279 [APR] = 0x0154,
280 [MPR] = 0x0158,
281 [TPAUSER] = 0x0164,
282 [RFCF] = 0x0160,
283 [TPAUSECR] = 0x0168,
284 [BCFRR] = 0x016c,
285 [MAHR] = 0x01c0,
286 [MALR] = 0x01c8,
287 [TROCR] = 0x01d0,
288 [CDCR] = 0x01d4,
289 [LCCR] = 0x01d8,
290 [CNDCR] = 0x01dc,
291 [CEFCR] = 0x01e4,
292 [FRECR] = 0x01e8,
293 [TSFRCR] = 0x01ec,
294 [TLFRCR] = 0x01f0,
295 [RFCR] = 0x01f4,
296 [MAFCR] = 0x01f8,
297 [RTRATE] = 0x01fc,
298
299 [EDMR] = 0x0000,
300 [EDTRR] = 0x0008,
301 [EDRRR] = 0x0010,
302 [TDLAR] = 0x0018,
303 [RDLAR] = 0x0020,
304 [EESR] = 0x0028,
305 [EESIPR] = 0x0030,
306 [TRSCER] = 0x0038,
307 [RMFCR] = 0x0040,
308 [TFTR] = 0x0048,
309 [FDR] = 0x0050,
310 [RMCR] = 0x0058,
311 [TFUCR] = 0x0064,
312 [RFOCR] = 0x0068,
313 [FCFTR] = 0x0070,
314 [RPADIR] = 0x0078,
315 [TRIMD] = 0x007c,
316 [RBWAR] = 0x00c8,
317 [RDFAR] = 0x00cc,
318 [TBRAR] = 0x00d4,
319 [TDFAR] = 0x00d8,
320};
321
322static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
3365711d
BH		 323 SH_ETH_OFFSET_DEFAULTS,
324
d8b0426a
SS		 325 [EDMR] = 0x0000,
326 [EDTRR] = 0x0004,
327 [EDRRR] = 0x0008,
328 [TDLAR] = 0x000c,
329 [RDLAR] = 0x0010,
330 [EESR] = 0x0014,
331 [EESIPR] = 0x0018,
332 [TRSCER] = 0x001c,
333 [RMFCR] = 0x0020,
334 [TFTR] = 0x0024,
335 [FDR] = 0x0028,
336 [RMCR] = 0x002c,
337 [EDOCR] = 0x0030,
338 [FCFTR] = 0x0034,
339 [RPADIR] = 0x0038,
340 [TRIMD] = 0x003c,
341 [RBWAR] = 0x0040,
342 [RDFAR] = 0x0044,
343 [TBRAR] = 0x004c,
344 [TDFAR] = 0x0050,
345
c0013f6f
SS		 346 [ECMR] = 0x0160,
347 [ECSR] = 0x0164,
348 [ECSIPR] = 0x0168,
349 [PIR] = 0x016c,
350 [MAHR] = 0x0170,
351 [MALR] = 0x0174,
352 [RFLR] = 0x0178,
353 [PSR] = 0x017c,
354 [TROCR] = 0x0180,
355 [CDCR] = 0x0184,
356 [LCCR] = 0x0188,
357 [CNDCR] = 0x018c,
358 [CEFCR] = 0x0194,
359 [FRECR] = 0x0198,
360 [TSFRCR] = 0x019c,
361 [TLFRCR] = 0x01a0,
362 [RFCR] = 0x01a4,
363 [MAFCR] = 0x01a8,
364 [IPGR] = 0x01b4,
365 [APR] = 0x01b8,
366 [MPR] = 0x01bc,
367 [TPAUSER] = 0x01c4,
368 [BCFR] = 0x01cc,
369
370 [ARSTR] = 0x0000,
371 [TSU_CTRST] = 0x0004,
372 [TSU_FWEN0] = 0x0010,
373 [TSU_FWEN1] = 0x0014,
374 [TSU_FCM] = 0x0018,
375 [TSU_BSYSL0] = 0x0020,
376 [TSU_BSYSL1] = 0x0024,
377 [TSU_PRISL0] = 0x0028,
378 [TSU_PRISL1] = 0x002c,
379 [TSU_FWSL0] = 0x0030,
380 [TSU_FWSL1] = 0x0034,
381 [TSU_FWSLC] = 0x0038,
382 [TSU_QTAGM0] = 0x0040,
383 [TSU_QTAGM1] = 0x0044,
384 [TSU_ADQT0] = 0x0048,
385 [TSU_ADQT1] = 0x004c,
386 [TSU_FWSR] = 0x0050,
387 [TSU_FWINMK] = 0x0054,
388 [TSU_ADSBSY] = 0x0060,
389 [TSU_TEN] = 0x0064,
390 [TSU_POST1] = 0x0070,
391 [TSU_POST2] = 0x0074,
392 [TSU_POST3] = 0x0078,
393 [TSU_POST4] = 0x007c,
394
395 [TXNLCR0] = 0x0080,
396 [TXALCR0] = 0x0084,
397 [RXNLCR0] = 0x0088,
398 [RXALCR0] = 0x008c,
399 [FWNLCR0] = 0x0090,
400 [FWALCR0] = 0x0094,
401 [TXNLCR1] = 0x00a0,
402 [TXALCR1] = 0x00a0,
403 [RXNLCR1] = 0x00a8,
404 [RXALCR1] = 0x00ac,
405 [FWNLCR1] = 0x00b0,
406 [FWALCR1] = 0x00b4,
407
408 [TSU_ADRH0] = 0x0100,
c0013f6f
SS		 409};
410
740c7f31
BH		 411static void sh_eth_rcv_snd_disable(struct net_device *ndev);
412static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev);
413
2274d375
SS		 414static void sh_eth_write(struct net_device *ndev, u32 data, int enum_index)
415{
416 struct sh_eth_private *mdp = netdev_priv(ndev);
417 u16 offset = mdp->reg_offset[enum_index];
418
419 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
420 return;
421
422 iowrite32(data, mdp->addr + offset);
423}
424
425static u32 sh_eth_read(struct net_device *ndev, int enum_index)
426{
427 struct sh_eth_private *mdp = netdev_priv(ndev);
428 u16 offset = mdp->reg_offset[enum_index];
429
430 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
431 return ~0U;
432
433 return ioread32(mdp->addr + offset);
434}
435
b2b14d2f
SS		 436static void sh_eth_modify(struct net_device *ndev, int enum_index, u32 clear,
437 u32 set)
438{
439 sh_eth_write(ndev, (sh_eth_read(ndev, enum_index) & ~clear) | set,
440 enum_index);
441}
442
504c8ca5 443static bool sh_eth_is_gether(struct sh_eth_private *mdp)
dabdde9e 444{
504c8ca5 445 return mdp->reg_offset == sh_eth_offset_gigabit;
dabdde9e
NI		 446}
447
db893473
SH		 448static bool sh_eth_is_rz_fast_ether(struct sh_eth_private *mdp)
449{
450 return mdp->reg_offset == sh_eth_offset_fast_rz;
451}
452
8e994402 453static void sh_eth_select_mii(struct net_device *ndev)
5e7a76be 454{
5e7a76be 455 struct sh_eth_private *mdp = netdev_priv(ndev);
4fa8c3cc 456 u32 value;
5e7a76be
NI		 457
458 switch (mdp->phy_interface) {
459 case PHY_INTERFACE_MODE_GMII:
460 value = 0x2;
461 break;
462 case PHY_INTERFACE_MODE_MII:
463 value = 0x1;
464 break;
465 case PHY_INTERFACE_MODE_RMII:
466 value = 0x0;
467 break;
468 default:
f75f14ec
SS		 469 netdev_warn(ndev,
470 "PHY interface mode was not setup. Set to MII.\n");
5e7a76be
NI		 471 value = 0x1;
472 break;
473 }
474
475 sh_eth_write(ndev, value, RMII_MII);
476}
5e7a76be 477
8e994402 478static void sh_eth_set_duplex(struct net_device *ndev)
65ac8851
YS		 479{
480 struct sh_eth_private *mdp = netdev_priv(ndev);
65ac8851 481
b2b14d2f 482 sh_eth_modify(ndev, ECMR, ECMR_DM, mdp->duplex ? ECMR_DM : 0);
65ac8851
YS		 483}
484
99f84be6
GU		 485static void sh_eth_chip_reset(struct net_device *ndev)
486{
487 struct sh_eth_private *mdp = netdev_priv(ndev);
488
489 /* reset device */
ec65cfce 490 sh_eth_tsu_write(mdp, ARSTR_ARST, ARSTR);
99f84be6
GU		 491 mdelay(1);
492}
493
a0f48be3
GU		 494static void sh_eth_set_rate_gether(struct net_device *ndev)
495{
496 struct sh_eth_private *mdp = netdev_priv(ndev);
497
498 switch (mdp->speed) {
499 case 10: /* 10BASE */
500 sh_eth_write(ndev, GECMR_10, GECMR);
501 break;
502 case 100:/* 100BASE */
503 sh_eth_write(ndev, GECMR_100, GECMR);
504 break;
505 case 1000: /* 1000BASE */
506 sh_eth_write(ndev, GECMR_1000, GECMR);
507 break;
a0f48be3
GU		 508 }
509}
510
99f84be6
GU		 511#ifdef CONFIG_OF
512/* R7S72100 */
513static struct sh_eth_cpu_data r7s72100_data = {
514 .chip_reset = sh_eth_chip_reset,
515 .set_duplex = sh_eth_set_duplex,
516
517 .register_type = SH_ETH_REG_FAST_RZ,
518
519 .ecsr_value = ECSR_ICD,
520 .ecsipr_value = ECSIPR_ICDIP,
33d446db 521 .eesipr_value = 0xe77f009f,
99f84be6
GU		 522
523 .tx_check = EESR_TC1 | EESR_FTC,
524 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
525 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
526 EESR_TDE | EESR_ECI,
527 .fdr_value = 0x0000070f,
528
529 .no_psr = 1,
530 .apr = 1,
531 .mpr = 1,
532 .tpauser = 1,
533 .hw_swap = 1,
534 .rpadir = 1,
535 .rpadir_value = 2 << 16,
536 .no_trimd = 1,
537 .no_ade = 1,
538 .hw_crc = 1,
539 .tsu = 1,
540 .shift_rd0 = 1,
541};
a0f48be3
GU		 542
543static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
544{
c66b2581 545 sh_eth_chip_reset(ndev);
a0f48be3
GU		 546
547 sh_eth_select_mii(ndev);
548}
549
550/* R8A7740 */
551static struct sh_eth_cpu_data r8a7740_data = {
552 .chip_reset = sh_eth_chip_reset_r8a7740,
553 .set_duplex = sh_eth_set_duplex,
554 .set_rate = sh_eth_set_rate_gether,
555
556 .register_type = SH_ETH_REG_GIGABIT,
557
558 .ecsr_value = ECSR_ICD | ECSR_MPD,
559 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
560 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
561
562 .tx_check = EESR_TC1 | EESR_FTC,
563 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
564 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
565 EESR_TDE | EESR_ECI,
566 .fdr_value = 0x0000070f,
567
568 .apr = 1,
569 .mpr = 1,
570 .tpauser = 1,
571 .bculr = 1,
572 .hw_swap = 1,
573 .rpadir = 1,
574 .rpadir_value = 2 << 16,
575 .no_trimd = 1,
576 .no_ade = 1,
577 .tsu = 1,
578 .select_mii = 1,
579 .shift_rd0 = 1,
580};
99f84be6 581
04b0ed2a 582/* There is CPU dependent code */
589ebdef 583static void sh_eth_set_rate_r8a777x(struct net_device *ndev)
65ac8851
YS		 584{
585 struct sh_eth_private *mdp = netdev_priv(ndev);
d0418bb7 586
a3f109bd
SS		 587 switch (mdp->speed) {
588 case 10: /* 10BASE */
b2b14d2f 589 sh_eth_modify(ndev, ECMR, ECMR_ELB, 0);
a3f109bd
SS		 590 break;
591 case 100:/* 100BASE */
b2b14d2f 592 sh_eth_modify(ndev, ECMR, ECMR_ELB, ECMR_ELB);
a3f109bd 593 break;
a3f109bd
SS		 594 }
595}
596
674853b2 597/* R8A7778/9 */
589ebdef 598static struct sh_eth_cpu_data r8a777x_data = {
a3f109bd 599 .set_duplex = sh_eth_set_duplex,
589ebdef 600 .set_rate = sh_eth_set_rate_r8a777x,
a3f109bd 601
a3153d8c
SS		 602 .register_type = SH_ETH_REG_FAST_RCAR,
603
a3f109bd
SS		 604 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
605 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
606 .eesipr_value = 0x01ff009f,
607
608 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
ca8c3585
SS		 609 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
610 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
611 EESR_ECI,
d407bc02 612 .fdr_value = 0x00000f0f,
a3f109bd
SS		 613
614 .apr = 1,
615 .mpr = 1,
616 .tpauser = 1,
617 .hw_swap = 1,
618};
a3f109bd 619
94a12b15
SS		 620/* R8A7790/1 */
621static struct sh_eth_cpu_data r8a779x_data = {
e18dbf7e
SH		 622 .set_duplex = sh_eth_set_duplex,
623 .set_rate = sh_eth_set_rate_r8a777x,
624
a3153d8c
SS		 625 .register_type = SH_ETH_REG_FAST_RCAR,
626
e18dbf7e
SH		 627 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
628 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
629 .eesipr_value = 0x01ff009f,
630
631 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
ba361cb3
LP		 632 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
633 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
634 EESR_ECI,
d407bc02 635 .fdr_value = 0x00000f0f,
e18dbf7e 636
01fbd3f5
GU		 637 .trscer_err_mask = DESC_I_RINT8,
638
e18dbf7e
SH		 639 .apr = 1,
640 .mpr = 1,
641 .tpauser = 1,
642 .hw_swap = 1,
643 .rmiimode = 1,
644};
c74a2248 645#endif /* CONFIG_OF */
e18dbf7e 646
9c3beaab 647static void sh_eth_set_rate_sh7724(struct net_device *ndev)
a3f109bd
SS		 648{
649 struct sh_eth_private *mdp = netdev_priv(ndev);
65ac8851
YS		 650
651 switch (mdp->speed) {
652 case 10: /* 10BASE */
b2b14d2f 653 sh_eth_modify(ndev, ECMR, ECMR_RTM, 0);
65ac8851
YS		 654 break;
655 case 100:/* 100BASE */
b2b14d2f 656 sh_eth_modify(ndev, ECMR, ECMR_RTM, ECMR_RTM);
65ac8851 657 break;
65ac8851
YS		 658 }
659}
660
661/* SH7724 */
9c3beaab 662static struct sh_eth_cpu_data sh7724_data = {
65ac8851 663 .set_duplex = sh_eth_set_duplex,
9c3beaab 664 .set_rate = sh_eth_set_rate_sh7724,
65ac8851 665
a3153d8c
SS		 666 .register_type = SH_ETH_REG_FAST_SH4,
667
65ac8851
YS		 668 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
669 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
a80c3de7 670 .eesipr_value = 0x01ff009f,
65ac8851
YS		 671
672 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
ca8c3585
SS		 673 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
674 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
675 EESR_ECI,
65ac8851
YS		 676
677 .apr = 1,
678 .mpr = 1,
679 .tpauser = 1,
680 .hw_swap = 1,
503914cf
MD		 681 .rpadir = 1,
682 .rpadir_value = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
65ac8851 683};
5cee1d37 684
24549e2a 685static void sh_eth_set_rate_sh7757(struct net_device *ndev)
f29a3d04
YS		 686{
687 struct sh_eth_private *mdp = netdev_priv(ndev);
f29a3d04
YS		 688
689 switch (mdp->speed) {
690 case 10: /* 10BASE */
4a55530f 691 sh_eth_write(ndev, 0, RTRATE);
f29a3d04
YS		 692 break;
693 case 100:/* 100BASE */
4a55530f 694 sh_eth_write(ndev, 1, RTRATE);
f29a3d04 695 break;
f29a3d04
YS		 696 }
697}
698
699/* SH7757 */
24549e2a
SS		 700static struct sh_eth_cpu_data sh7757_data = {
701 .set_duplex = sh_eth_set_duplex,
702 .set_rate = sh_eth_set_rate_sh7757,
f29a3d04 703
a3153d8c
SS		 704 .register_type = SH_ETH_REG_FAST_SH4,
705
f29a3d04 706 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
f29a3d04
YS		 707
708 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
ca8c3585
SS		 709 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
710 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
711 EESR_ECI,
f29a3d04 712
5b3dfd13 713 .irq_flags = IRQF_SHARED,
f29a3d04
YS		 714 .apr = 1,
715 .mpr = 1,
716 .tpauser = 1,
717 .hw_swap = 1,
718 .no_ade = 1,
2e98e797
YS		 719 .rpadir = 1,
720 .rpadir_value = 2 << 16,
6b4b4fea 721 .rtrate = 1,
f29a3d04 722};
65ac8851 723
e403d295 724#define SH_GIGA_ETH_BASE 0xfee00000UL
8fcd4961
YS		 725#define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
726#define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
727static void sh_eth_chip_reset_giga(struct net_device *ndev)
728{
0799c2d6 729 u32 mahr[2], malr[2];
79270922 730 int i;
8fcd4961
YS		 731
732 /* save MAHR and MALR */
733 for (i = 0; i < 2; i++) {
ae70644d
YS		 734 malr[i] = ioread32((void *)GIGA_MALR(i));
735 mahr[i] = ioread32((void *)GIGA_MAHR(i));
8fcd4961
YS		 736 }
737
c66b2581 738 sh_eth_chip_reset(ndev);
8fcd4961
YS		 739
740 /* restore MAHR and MALR */
741 for (i = 0; i < 2; i++) {
ae70644d
YS		 742 iowrite32(malr[i], (void *)GIGA_MALR(i));
743 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
8fcd4961
YS		 744 }
745}
746
8fcd4961
YS		 747static void sh_eth_set_rate_giga(struct net_device *ndev)
748{
749 struct sh_eth_private *mdp = netdev_priv(ndev);
750
751 switch (mdp->speed) {
752 case 10: /* 10BASE */
753 sh_eth_write(ndev, 0x00000000, GECMR);
754 break;
755 case 100:/* 100BASE */
756 sh_eth_write(ndev, 0x00000010, GECMR);
757 break;
758 case 1000: /* 1000BASE */
759 sh_eth_write(ndev, 0x00000020, GECMR);
760 break;
8fcd4961
YS		 761 }
762}
763
764/* SH7757(GETHERC) */
24549e2a 765static struct sh_eth_cpu_data sh7757_data_giga = {
8fcd4961 766 .chip_reset = sh_eth_chip_reset_giga,
04b0ed2a 767 .set_duplex = sh_eth_set_duplex,
8fcd4961
YS		 768 .set_rate = sh_eth_set_rate_giga,
769
a3153d8c
SS		 770 .register_type = SH_ETH_REG_GIGABIT,
771
8fcd4961
YS		 772 .ecsr_value = ECSR_ICD | ECSR_MPD,
773 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
774 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
775
776 .tx_check = EESR_TC1 | EESR_FTC,
ca8c3585
SS		 777 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
778 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
779 EESR_TDE | EESR_ECI,
8fcd4961 780 .fdr_value = 0x0000072f,
8fcd4961 781
5b3dfd13 782 .irq_flags = IRQF_SHARED,
8fcd4961
YS		 783 .apr = 1,
784 .mpr = 1,
785 .tpauser = 1,
786 .bculr = 1,
787 .hw_swap = 1,
788 .rpadir = 1,
789 .rpadir_value = 2 << 16,
790 .no_trimd = 1,
791 .no_ade = 1,
3acbc971 792 .tsu = 1,
8fcd4961
YS		 793};
794
f5d12767
SS		 795/* SH7734 */
796static struct sh_eth_cpu_data sh7734_data = {
380af9e3
YS		 797 .chip_reset = sh_eth_chip_reset,
798 .set_duplex = sh_eth_set_duplex,
f5d12767
SS		 799 .set_rate = sh_eth_set_rate_gether,
800
a3153d8c
SS		 801 .register_type = SH_ETH_REG_GIGABIT,
802
f5d12767
SS		 803 .ecsr_value = ECSR_ICD | ECSR_MPD,
804 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
805 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
806
807 .tx_check = EESR_TC1 | EESR_FTC,
ca8c3585
SS		 808 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
809 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
810 EESR_TDE | EESR_ECI,
f5d12767
SS		 811
812 .apr = 1,
813 .mpr = 1,
814 .tpauser = 1,
815 .bculr = 1,
816 .hw_swap = 1,
817 .no_trimd = 1,
818 .no_ade = 1,
819 .tsu = 1,
820 .hw_crc = 1,
821 .select_mii = 1,
822};
823
824/* SH7763 */
825static struct sh_eth_cpu_data sh7763_data = {
826 .chip_reset = sh_eth_chip_reset,
827 .set_duplex = sh_eth_set_duplex,
828 .set_rate = sh_eth_set_rate_gether,
380af9e3 829
a3153d8c
SS		 830 .register_type = SH_ETH_REG_GIGABIT,
831
380af9e3
YS		 832 .ecsr_value = ECSR_ICD | ECSR_MPD,
833 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
834 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
835
836 .tx_check = EESR_TC1 | EESR_FTC,
128296fc
SS		 837 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
838 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
380af9e3 839 EESR_ECI,
380af9e3
YS		 840
841 .apr = 1,
842 .mpr = 1,
843 .tpauser = 1,
844 .bculr = 1,
845 .hw_swap = 1,
380af9e3
YS		 846 .no_trimd = 1,
847 .no_ade = 1,
4986b996 848 .tsu = 1,
5b3dfd13 849 .irq_flags = IRQF_SHARED,
380af9e3
YS		 850};
851
c18a79ab 852static struct sh_eth_cpu_data sh7619_data = {
a3153d8c
SS		 853 .register_type = SH_ETH_REG_FAST_SH3_SH2,
854
380af9e3
YS		 855 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
856
857 .apr = 1,
858 .mpr = 1,
859 .tpauser = 1,
860 .hw_swap = 1,
861};
7bbe150d
SS		 862
863static struct sh_eth_cpu_data sh771x_data = {
a3153d8c
SS		 864 .register_type = SH_ETH_REG_FAST_SH3_SH2,
865
380af9e3 866 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
4986b996 867 .tsu = 1,
380af9e3 868};
380af9e3
YS		 869
870static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
871{
872 if (!cd->ecsr_value)
873 cd->ecsr_value = DEFAULT_ECSR_INIT;
874
875 if (!cd->ecsipr_value)
876 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
877
878 if (!cd->fcftr_value)
128296fc 879 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF |
380af9e3
YS		 880 DEFAULT_FIFO_F_D_RFD;
881
882 if (!cd->fdr_value)
883 cd->fdr_value = DEFAULT_FDR_INIT;
884
380af9e3
YS		 885 if (!cd->tx_check)
886 cd->tx_check = DEFAULT_TX_CHECK;
887
888 if (!cd->eesr_err_check)
889 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
b284fbe3
NI		 890
891 if (!cd->trscer_err_mask)
892 cd->trscer_err_mask = DEFAULT_TRSCER_ERR_MASK;
380af9e3
YS		 893}
894
5cee1d37
NI		 895static int sh_eth_check_reset(struct net_device *ndev)
896{
897 int ret = 0;
898 int cnt = 100;
899
900 while (cnt > 0) {
97717edc 901 if (!(sh_eth_read(ndev, EDMR) & EDMR_SRST_GETHER))
5cee1d37
NI		 902 break;
903 mdelay(1);
904 cnt--;
905 }
9f8c4265 906 if (cnt <= 0) {
f75f14ec 907 netdev_err(ndev, "Device reset failed\n");
5cee1d37
NI		 908 ret = -ETIMEDOUT;
909 }
910 return ret;
380af9e3 911}
dabdde9e
NI		 912
913static int sh_eth_reset(struct net_device *ndev)
914{
915 struct sh_eth_private *mdp = netdev_priv(ndev);
916 int ret = 0;
917
db893473 918 if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp)) {
dabdde9e 919 sh_eth_write(ndev, EDSR_ENALL, EDSR);
b2b14d2f 920 sh_eth_modify(ndev, EDMR, EDMR_SRST_GETHER, EDMR_SRST_GETHER);
dabdde9e
NI		 921
922 ret = sh_eth_check_reset(ndev);
923 if (ret)
f738a13d 924 return ret;
dabdde9e
NI		 925
926 /* Table Init */
927 sh_eth_write(ndev, 0x0, TDLAR);
928 sh_eth_write(ndev, 0x0, TDFAR);
929 sh_eth_write(ndev, 0x0, TDFXR);
930 sh_eth_write(ndev, 0x0, TDFFR);
931 sh_eth_write(ndev, 0x0, RDLAR);
932 sh_eth_write(ndev, 0x0, RDFAR);
933 sh_eth_write(ndev, 0x0, RDFXR);
934 sh_eth_write(ndev, 0x0, RDFFR);
935
936 /* Reset HW CRC register */
937 if (mdp->cd->hw_crc)
938 sh_eth_write(ndev, 0x0, CSMR);
939
940 /* Select MII mode */
941 if (mdp->cd->select_mii)
942 sh_eth_select_mii(ndev);
943 } else {
b2b14d2f 944 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, EDMR_SRST_ETHER);
dabdde9e 945 mdelay(3);
b2b14d2f 946 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, 0);
dabdde9e
NI		 947 }
948
dabdde9e
NI		 949 return ret;
950}
380af9e3 951
380af9e3
YS		 952static void sh_eth_set_receive_align(struct sk_buff *skb)
953{
4d6a949c 954 uintptr_t reserve = (uintptr_t)skb->data & (SH_ETH_RX_ALIGN - 1);
380af9e3 955
380af9e3 956 if (reserve)
4d6a949c 957 skb_reserve(skb, SH_ETH_RX_ALIGN - reserve);
380af9e3 958}
380af9e3 959
128296fc 960/* Program the hardware MAC address from dev->dev_addr. */
86a74ff2
NI		 961static void update_mac_address(struct net_device *ndev)
962{
4a55530f 963 sh_eth_write(ndev,
128296fc
SS		 964 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
965 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
4a55530f 966 sh_eth_write(ndev,
128296fc 967 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
86a74ff2
NI		 968}
969
128296fc 970/* Get MAC address from SuperH MAC address register
86a74ff2
NI		 971 *
972 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
973 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
974 * When you want use this device, you must set MAC address in bootloader.
975 *
976 */
748031f9 977static void read_mac_address(struct net_device *ndev, unsigned char *mac)
86a74ff2 978{
748031f9 979 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
d458cdf7 980 memcpy(ndev->dev_addr, mac, ETH_ALEN);
748031f9 981 } else {
37742f02
SS		 982 u32 mahr = sh_eth_read(ndev, MAHR);
983 u32 malr = sh_eth_read(ndev, MALR);
984
985 ndev->dev_addr[0] = (mahr >> 24) & 0xFF;
986 ndev->dev_addr[1] = (mahr >> 16) & 0xFF;
987 ndev->dev_addr[2] = (mahr >> 8) & 0xFF;
988 ndev->dev_addr[3] = (mahr >> 0) & 0xFF;
989 ndev->dev_addr[4] = (malr >> 8) & 0xFF;
990 ndev->dev_addr[5] = (malr >> 0) & 0xFF;
748031f9 991 }
86a74ff2
NI		 992}
993
0799c2d6 994static u32 sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
c5ed5368 995{
db893473 996 if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp))
c5ed5368
YS		 997 return EDTRR_TRNS_GETHER;
998 else
999 return EDTRR_TRNS_ETHER;
1000}
1001
86a74ff2 1002struct bb_info {
ae70644d 1003 void (*set_gate)(void *addr);
86a74ff2 1004 struct mdiobb_ctrl ctrl;
ae70644d 1005 void *addr;
86a74ff2
NI		 1006};
1007
39b4b06b 1008static void sh_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set)
86a74ff2
NI		 1009{
1010 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
78fa3c5c 1011 u32 pir;
b3017e6a
YS		 1012
1013 if (bitbang->set_gate)
1014 bitbang->set_gate(bitbang->addr);
1015
78fa3c5c 1016 pir = ioread32(bitbang->addr);
39b4b06b 1017 if (set)
78fa3c5c 1018 pir |= mask;
86a74ff2 1019 else
78fa3c5c
SS		 1020 pir &= ~mask;
1021 iowrite32(pir, bitbang->addr);
39b4b06b
SS		 1022}
1023
1024/* Data I/O pin control */
1025static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1026{
1027 sh_mdio_ctrl(ctrl, PIR_MMD, bit);
86a74ff2
NI		 1028}
1029
1030/* Set bit data*/
1031static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
1032{
39b4b06b 1033 sh_mdio_ctrl(ctrl, PIR_MDO, bit);
86a74ff2
NI		 1034}
1035
1036/* Get bit data*/
1037static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
1038{
1039 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
b3017e6a
YS		 1040
1041 if (bitbang->set_gate)
1042 bitbang->set_gate(bitbang->addr);
1043
78fa3c5c 1044 return (ioread32(bitbang->addr) & PIR_MDI) != 0;
86a74ff2
NI		 1045}
1046
1047/* MDC pin control */
1048static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1049{
39b4b06b 1050 sh_mdio_ctrl(ctrl, PIR_MDC, bit);
86a74ff2
NI		 1051}
1052
1053/* mdio bus control struct */
1054static struct mdiobb_ops bb_ops = {
1055 .owner = THIS_MODULE,
1056 .set_mdc = sh_mdc_ctrl,
1057 .set_mdio_dir = sh_mmd_ctrl,
1058 .set_mdio_data = sh_set_mdio,
1059 .get_mdio_data = sh_get_mdio,
1060};
1061
86a74ff2
NI		 1062/* free skb and descriptor buffer */
1063static void sh_eth_ring_free(struct net_device *ndev)
1064{
1065 struct sh_eth_private *mdp = netdev_priv(ndev);
8e03a5e7 1066 int ringsize, i;
86a74ff2
NI		 1067
1068 /* Free Rx skb ringbuffer */
1069 if (mdp->rx_skbuff) {
179d80af
SS		 1070 for (i = 0; i < mdp->num_rx_ring; i++)
1071 dev_kfree_skb(mdp->rx_skbuff[i]);
86a74ff2
NI		 1072 }
1073 kfree(mdp->rx_skbuff);
91c77550 1074 mdp->rx_skbuff = NULL;
86a74ff2
NI		 1075
1076 /* Free Tx skb ringbuffer */
1077 if (mdp->tx_skbuff) {
179d80af
SS		 1078 for (i = 0; i < mdp->num_tx_ring; i++)
1079 dev_kfree_skb(mdp->tx_skbuff[i]);
86a74ff2
NI		 1080 }
1081 kfree(mdp->tx_skbuff);
91c77550 1082 mdp->tx_skbuff = NULL;
8e03a5e7
SS		 1083
1084 if (mdp->rx_ring) {
1085 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1086 dma_free_coherent(NULL, ringsize, mdp->rx_ring,
1087 mdp->rx_desc_dma);
1088 mdp->rx_ring = NULL;
1089 }
1090
1091 if (mdp->tx_ring) {
1092 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1093 dma_free_coherent(NULL, ringsize, mdp->tx_ring,
1094 mdp->tx_desc_dma);
1095 mdp->tx_ring = NULL;
1096 }
86a74ff2
NI		 1097}
1098
1099/* format skb and descriptor buffer */
1100static void sh_eth_ring_format(struct net_device *ndev)
1101{
1102 struct sh_eth_private *mdp = netdev_priv(ndev);
1103 int i;
1104 struct sk_buff *skb;
1105 struct sh_eth_rxdesc *rxdesc = NULL;
1106 struct sh_eth_txdesc *txdesc = NULL;
525b8075
YS		 1107 int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
1108 int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
cb368595 1109 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
52b9fa36 1110 dma_addr_t dma_addr;
5cbf20c7 1111 u32 buf_len;
86a74ff2 1112
128296fc
SS		 1113 mdp->cur_rx = 0;
1114 mdp->cur_tx = 0;
1115 mdp->dirty_rx = 0;
1116 mdp->dirty_tx = 0;
86a74ff2
NI		 1117
1118 memset(mdp->rx_ring, 0, rx_ringsize);
1119
1120 /* build Rx ring buffer */
525b8075 1121 for (i = 0; i < mdp->num_rx_ring; i++) {
86a74ff2
NI		 1122 /* skb */
1123 mdp->rx_skbuff[i] = NULL;
4d6a949c 1124 skb = netdev_alloc_skb(ndev, skbuff_size);
86a74ff2
NI		 1125 if (skb == NULL)
1126 break;
380af9e3
YS		 1127 sh_eth_set_receive_align(skb);
1128
ab857916 1129 /* The size of the buffer is a multiple of 32 bytes. */
5cbf20c7 1130 buf_len = ALIGN(mdp->rx_buf_sz, 32);
5cbf20c7 1131 dma_addr = dma_map_single(&ndev->dev, skb->data, buf_len,
52b9fa36
BH		 1132 DMA_FROM_DEVICE);
1133 if (dma_mapping_error(&ndev->dev, dma_addr)) {
1134 kfree_skb(skb);
1135 break;
1136 }
1137 mdp->rx_skbuff[i] = skb;
d0ba9134
SS		 1138
1139 /* RX descriptor */
1140 rxdesc = &mdp->rx_ring[i];
1141 rxdesc->len = cpu_to_le32(buf_len << 16);
7cf72477
SS		 1142 rxdesc->addr = cpu_to_le32(dma_addr);
1143 rxdesc->status = cpu_to_le32(RD_RACT | RD_RFP);
86a74ff2 1144
b0ca2a21
NI		 1145 /* Rx descriptor address set */
1146 if (i == 0) {
4a55530f 1147 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
db893473
SH		 1148 if (sh_eth_is_gether(mdp) ||
1149 sh_eth_is_rz_fast_ether(mdp))
c5ed5368 1150 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
b0ca2a21 1151 }
86a74ff2
NI		 1152 }
1153
525b8075 1154 mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
86a74ff2
NI		 1155
1156 /* Mark the last entry as wrapping the ring. */
c1b7fca6
SS		 1157 if (rxdesc)
1158 rxdesc->status |= cpu_to_le32(RD_RDLE);
86a74ff2
NI		 1159
1160 memset(mdp->tx_ring, 0, tx_ringsize);
1161
1162 /* build Tx ring buffer */
525b8075 1163 for (i = 0; i < mdp->num_tx_ring; i++) {
86a74ff2
NI		 1164 mdp->tx_skbuff[i] = NULL;
1165 txdesc = &mdp->tx_ring[i];
7cf72477
SS		 1166 txdesc->status = cpu_to_le32(TD_TFP);
1167 txdesc->len = cpu_to_le32(0);
b0ca2a21 1168 if (i == 0) {
71557a37 1169 /* Tx descriptor address set */
4a55530f 1170 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
db893473
SH		 1171 if (sh_eth_is_gether(mdp) ||
1172 sh_eth_is_rz_fast_ether(mdp))
c5ed5368 1173 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
b0ca2a21 1174 }
86a74ff2
NI		 1175 }
1176
7cf72477 1177 txdesc->status |= cpu_to_le32(TD_TDLE);
86a74ff2
NI		 1178}
1179
1180/* Get skb and descriptor buffer */
1181static int sh_eth_ring_init(struct net_device *ndev)
1182{
1183 struct sh_eth_private *mdp = netdev_priv(ndev);
91d80683 1184 int rx_ringsize, tx_ringsize;
86a74ff2 1185
128296fc 1186 /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
86a74ff2
NI		 1187 * card needs room to do 8 byte alignment, +2 so we can reserve
1188 * the first 2 bytes, and +16 gets room for the status word from the
1189 * card.
1190 */
1191 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
1192 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
503914cf
MD		 1193 if (mdp->cd->rpadir)
1194 mdp->rx_buf_sz += NET_IP_ALIGN;
86a74ff2
NI		 1195
1196 /* Allocate RX and TX skb rings */
2c94e856
SS		 1197 mdp->rx_skbuff = kcalloc(mdp->num_rx_ring, sizeof(*mdp->rx_skbuff),
1198 GFP_KERNEL);
91d80683
SS		 1199 if (!mdp->rx_skbuff)
1200 return -ENOMEM;
86a74ff2 1201
2c94e856
SS		 1202 mdp->tx_skbuff = kcalloc(mdp->num_tx_ring, sizeof(*mdp->tx_skbuff),
1203 GFP_KERNEL);
91d80683 1204 if (!mdp->tx_skbuff)
8e03a5e7 1205 goto ring_free;
86a74ff2
NI		 1206
1207 /* Allocate all Rx descriptors. */
525b8075 1208 rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
86a74ff2 1209 mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
d0320f75 1210 GFP_KERNEL);
91d80683 1211 if (!mdp->rx_ring)
8e03a5e7 1212 goto ring_free;
86a74ff2
NI		 1213
1214 mdp->dirty_rx = 0;
1215
1216 /* Allocate all Tx descriptors. */
525b8075 1217 tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
86a74ff2 1218 mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
d0320f75 1219 GFP_KERNEL);
91d80683 1220 if (!mdp->tx_ring)
8e03a5e7 1221 goto ring_free;
91d80683 1222 return 0;
86a74ff2 1223
8e03a5e7
SS		 1224ring_free:
1225 /* Free Rx and Tx skb ring buffer and DMA buffer */
86a74ff2
NI		 1226 sh_eth_ring_free(ndev);
1227
91d80683 1228 return -ENOMEM;
86a74ff2
NI		 1229}
1230
f7967210 1231static int sh_eth_dev_init(struct net_device *ndev)
86a74ff2 1232{
86a74ff2 1233 struct sh_eth_private *mdp = netdev_priv(ndev);
4fa8c3cc 1234 int ret;
86a74ff2
NI		 1235
1236 /* Soft Reset */
5cee1d37
NI		 1237 ret = sh_eth_reset(ndev);
1238 if (ret)
f738a13d 1239 return ret;
86a74ff2 1240
55754f19
SH		 1241 if (mdp->cd->rmiimode)
1242 sh_eth_write(ndev, 0x1, RMIIMODE);
1243
b0ca2a21
NI		 1244 /* Descriptor format */
1245 sh_eth_ring_format(ndev);
380af9e3 1246 if (mdp->cd->rpadir)
4a55530f 1247 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
86a74ff2
NI		 1248
1249 /* all sh_eth int mask */
4a55530f 1250 sh_eth_write(ndev, 0, EESIPR);
86a74ff2 1251
10b9194f 1252#if defined(__LITTLE_ENDIAN)
380af9e3 1253 if (mdp->cd->hw_swap)
4a55530f 1254 sh_eth_write(ndev, EDMR_EL, EDMR);
380af9e3 1255 else
b0ca2a21 1256#endif
4a55530f 1257 sh_eth_write(ndev, 0, EDMR);
86a74ff2 1258
b0ca2a21 1259 /* FIFO size set */
4a55530f
YS		 1260 sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
1261 sh_eth_write(ndev, 0, TFTR);
86a74ff2 1262
530aa2d0
BD		 1263 /* Frame recv control (enable multiple-packets per rx irq) */
1264 sh_eth_write(ndev, RMCR_RNC, RMCR);
86a74ff2 1265
b284fbe3 1266 sh_eth_write(ndev, mdp->cd->trscer_err_mask, TRSCER);
86a74ff2 1267
380af9e3 1268 if (mdp->cd->bculr)
4a55530f 1269 sh_eth_write(ndev, 0x800, BCULR); /* Burst sycle set */
b0ca2a21 1270
4a55530f 1271 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
86a74ff2 1272
380af9e3 1273 if (!mdp->cd->no_trimd)
4a55530f 1274 sh_eth_write(ndev, 0, TRIMD);
86a74ff2 1275
b0ca2a21 1276 /* Recv frame limit set register */
fdb37a7f
YS		 1277 sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1278 RFLR);
86a74ff2 1279
b2b14d2f 1280 sh_eth_modify(ndev, EESR, 0, 0);
f7967210
SS		 1281 mdp->irq_enabled = true;
1282 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
86a74ff2
NI		 1283
1284 /* PAUSE Prohibition */
bffa731f
SS		 1285 sh_eth_write(ndev, ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) |
1286 ECMR_TE | ECMR_RE, ECMR);
b0ca2a21 1287
380af9e3
YS		 1288 if (mdp->cd->set_rate)
1289 mdp->cd->set_rate(ndev);
1290
b0ca2a21 1291 /* E-MAC Status Register clear */
4a55530f 1292 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
b0ca2a21
NI		 1293
1294 /* E-MAC Interrupt Enable register */
f7967210 1295 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
86a74ff2
NI		 1296
1297 /* Set MAC address */
1298 update_mac_address(ndev);
1299
1300 /* mask reset */
380af9e3 1301 if (mdp->cd->apr)
4a55530f 1302 sh_eth_write(ndev, APR_AP, APR);
380af9e3 1303 if (mdp->cd->mpr)
4a55530f 1304 sh_eth_write(ndev, MPR_MP, MPR);
380af9e3 1305 if (mdp->cd->tpauser)
4a55530f 1306 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
b0ca2a21 1307
f7967210
SS		 1308 /* Setting the Rx mode will start the Rx process. */
1309 sh_eth_write(ndev, EDRRR_R, EDRRR);
86a74ff2
NI		 1310
1311 return ret;
1312}
1313
740c7f31
BH		 1314static void sh_eth_dev_exit(struct net_device *ndev)
1315{
1316 struct sh_eth_private *mdp = netdev_priv(ndev);
1317 int i;
1318
1319 /* Deactivate all TX descriptors, so DMA should stop at next
1320 * packet boundary if it's currently running
1321 */
1322 for (i = 0; i < mdp->num_tx_ring; i++)
7cf72477 1323 mdp->tx_ring[i].status &= ~cpu_to_le32(TD_TACT);
740c7f31
BH		 1324
1325 /* Disable TX FIFO egress to MAC */
1326 sh_eth_rcv_snd_disable(ndev);
1327
1328 /* Stop RX DMA at next packet boundary */
1329 sh_eth_write(ndev, 0, EDRRR);
1330
1331 /* Aside from TX DMA, we can't tell when the hardware is
1332 * really stopped, so we need to reset to make sure.
1333 * Before doing that, wait for long enough to *probably*
1334 * finish transmitting the last packet and poll stats.
1335 */
1336 msleep(2); /* max frame time at 10 Mbps < 1250 us */
1337 sh_eth_get_stats(ndev);
1338 sh_eth_reset(ndev);
a14c7d15
GU		 1339
1340 /* Set MAC address again */
1341 update_mac_address(ndev);
740c7f31
BH		 1342}
1343
86a74ff2
NI		 1344/* free Tx skb function */
1345static int sh_eth_txfree(struct net_device *ndev)
1346{
1347 struct sh_eth_private *mdp = netdev_priv(ndev);
1348 struct sh_eth_txdesc *txdesc;
128296fc 1349 int free_num = 0;
4fa8c3cc 1350 int entry;
86a74ff2
NI		 1351
1352 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
525b8075 1353 entry = mdp->dirty_tx % mdp->num_tx_ring;
86a74ff2 1354 txdesc = &mdp->tx_ring[entry];
7cf72477 1355 if (txdesc->status & cpu_to_le32(TD_TACT))
86a74ff2 1356 break;
7d7355f5 1357 /* TACT bit must be checked before all the following reads */
f32bfb9a 1358 dma_rmb();
e5fd13f4
BH		 1359 netif_info(mdp, tx_done, ndev,
1360 "tx entry %d status 0x%08x\n",
7cf72477 1361 entry, le32_to_cpu(txdesc->status));
86a74ff2
NI		 1362 /* Free the original skb. */
1363 if (mdp->tx_skbuff[entry]) {
7cf72477
SS		 1364 dma_unmap_single(&ndev->dev, le32_to_cpu(txdesc->addr),
1365 le32_to_cpu(txdesc->len) >> 16,
5cbf20c7 1366 DMA_TO_DEVICE);
86a74ff2
NI		 1367 dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1368 mdp->tx_skbuff[entry] = NULL;
128296fc 1369 free_num++;
86a74ff2 1370 }
7cf72477 1371 txdesc->status = cpu_to_le32(TD_TFP);
525b8075 1372 if (entry >= mdp->num_tx_ring - 1)
7cf72477 1373 txdesc->status |= cpu_to_le32(TD_TDLE);
86a74ff2 1374
bb7d92e3 1375 ndev->stats.tx_packets++;
7cf72477 1376 ndev->stats.tx_bytes += le32_to_cpu(txdesc->len) >> 16;
86a74ff2 1377 }
128296fc 1378 return free_num;
86a74ff2
NI		 1379}
1380
1381/* Packet receive function */
3719109d 1382static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
86a74ff2
NI		 1383{
1384 struct sh_eth_private *mdp = netdev_priv(ndev);
1385 struct sh_eth_rxdesc *rxdesc;
1386
525b8075
YS		 1387 int entry = mdp->cur_rx % mdp->num_rx_ring;
1388 int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
319cd520 1389 int limit;
86a74ff2 1390 struct sk_buff *skb;
380af9e3 1391 u32 desc_status;
cb368595 1392 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
52b9fa36 1393 dma_addr_t dma_addr;
4fa8c3cc 1394 u16 pkt_len;
5cbf20c7 1395 u32 buf_len;
86a74ff2 1396
319cd520
MK		 1397 boguscnt = min(boguscnt, *quota);
1398 limit = boguscnt;
86a74ff2 1399 rxdesc = &mdp->rx_ring[entry];
7cf72477 1400 while (!(rxdesc->status & cpu_to_le32(RD_RACT))) {
7d7355f5 1401 /* RACT bit must be checked before all the following reads */
f32bfb9a 1402 dma_rmb();
7cf72477
SS		 1403 desc_status = le32_to_cpu(rxdesc->status);
1404 pkt_len = le32_to_cpu(rxdesc->len) & RD_RFL;
86a74ff2
NI		 1405
1406 if (--boguscnt < 0)
1407 break;
1408
e5fd13f4
BH		 1409 netif_info(mdp, rx_status, ndev,
1410 "rx entry %d status 0x%08x len %d\n",
1411 entry, desc_status, pkt_len);
1412
86a74ff2 1413 if (!(desc_status & RDFEND))
bb7d92e3 1414 ndev->stats.rx_length_errors++;
86a74ff2 1415
128296fc 1416 /* In case of almost all GETHER/ETHERs, the Receive Frame State
dd019897 1417 * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
9b4a6364
BH		 1418 * bit 0. However, in case of the R8A7740 and R7S72100
1419 * the RFS bits are from bit 25 to bit 16. So, the
db893473 1420 * driver needs right shifting by 16.
dd019897 1421 */
ac8025a6
SS		 1422 if (mdp->cd->shift_rd0)
1423 desc_status >>= 16;
dd019897 1424
248be83d 1425 skb = mdp->rx_skbuff[entry];
86a74ff2
NI		 1426 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1427 RD_RFS5 | RD_RFS6 | RD_RFS10)) {
bb7d92e3 1428 ndev->stats.rx_errors++;
86a74ff2 1429 if (desc_status & RD_RFS1)
bb7d92e3 1430 ndev->stats.rx_crc_errors++;
86a74ff2 1431 if (desc_status & RD_RFS2)
bb7d92e3 1432 ndev->stats.rx_frame_errors++;
86a74ff2 1433 if (desc_status & RD_RFS3)
bb7d92e3 1434 ndev->stats.rx_length_errors++;
86a74ff2 1435 if (desc_status & RD_RFS4)
bb7d92e3 1436 ndev->stats.rx_length_errors++;
86a74ff2 1437 if (desc_status & RD_RFS6)
bb7d92e3 1438 ndev->stats.rx_missed_errors++;
86a74ff2 1439 if (desc_status & RD_RFS10)
bb7d92e3 1440 ndev->stats.rx_over_errors++;
248be83d 1441 } else if (skb) {
7cf72477 1442 dma_addr = le32_to_cpu(rxdesc->addr);
380af9e3
YS		 1443 if (!mdp->cd->hw_swap)
1444 sh_eth_soft_swap(
1299653a 1445 phys_to_virt(ALIGN(dma_addr, 4)),
380af9e3 1446 pkt_len + 2);
86a74ff2 1447 mdp->rx_skbuff[entry] = NULL;
503914cf
MD		 1448 if (mdp->cd->rpadir)
1449 skb_reserve(skb, NET_IP_ALIGN);
1299653a 1450 dma_unmap_single(&ndev->dev, dma_addr,
ab857916 1451 ALIGN(mdp->rx_buf_sz, 32),
52b9fa36 1452 DMA_FROM_DEVICE);
86a74ff2
NI		 1453 skb_put(skb, pkt_len);
1454 skb->protocol = eth_type_trans(skb, ndev);
a8e9fd0f 1455 netif_receive_skb(skb);
bb7d92e3
ED		 1456 ndev->stats.rx_packets++;
1457 ndev->stats.rx_bytes += pkt_len;
25b77ad7
BH		 1458 if (desc_status & RD_RFS8)
1459 ndev->stats.multicast++;
86a74ff2 1460 }
525b8075 1461 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
862df497 1462 rxdesc = &mdp->rx_ring[entry];
86a74ff2
NI		 1463 }
1464
1465 /* Refill the Rx ring buffers. */
1466 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
525b8075 1467 entry = mdp->dirty_rx % mdp->num_rx_ring;
86a74ff2 1468 rxdesc = &mdp->rx_ring[entry];
ab857916 1469 /* The size of the buffer is 32 byte boundary. */
5cbf20c7 1470 buf_len = ALIGN(mdp->rx_buf_sz, 32);
7cf72477 1471 rxdesc->len = cpu_to_le32(buf_len << 16);
b0ca2a21 1472
86a74ff2 1473 if (mdp->rx_skbuff[entry] == NULL) {
4d6a949c 1474 skb = netdev_alloc_skb(ndev, skbuff_size);
86a74ff2
NI		 1475 if (skb == NULL)
1476 break; /* Better luck next round. */
380af9e3 1477 sh_eth_set_receive_align(skb);
52b9fa36 1478 dma_addr = dma_map_single(&ndev->dev, skb->data,
5cbf20c7 1479 buf_len, DMA_FROM_DEVICE);
52b9fa36
BH		 1480 if (dma_mapping_error(&ndev->dev, dma_addr)) {
1481 kfree_skb(skb);
1482 break;
1483 }
1484 mdp->rx_skbuff[entry] = skb;
380af9e3 1485
bc8acf2c 1486 skb_checksum_none_assert(skb);
7cf72477 1487 rxdesc->addr = cpu_to_le32(dma_addr);
86a74ff2 1488 }
f32bfb9a 1489 dma_wmb(); /* RACT bit must be set after all the above writes */
525b8075 1490 if (entry >= mdp->num_rx_ring - 1)
86a74ff2 1491 rxdesc->status |=
7cf72477 1492 cpu_to_le32(RD_RACT | RD_RFP | RD_RDLE);
86a74ff2 1493 else
7cf72477 1494 rxdesc->status |= cpu_to_le32(RD_RACT | RD_RFP);
86a74ff2
NI		 1495 }
1496
1497 /* Restart Rx engine if stopped. */
1498 /* If we don't need to check status, don't. -KDU */
79fba9f5 1499 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
a18e08bd 1500 /* fix the values for the next receiving if RDE is set */
3365711d
BH		 1501 if (intr_status & EESR_RDE &&
1502 mdp->reg_offset[RDFAR] != SH_ETH_OFFSET_INVALID) {
128296fc
SS		 1503 u32 count = (sh_eth_read(ndev, RDFAR) -
1504 sh_eth_read(ndev, RDLAR)) >> 4;
1505
1506 mdp->cur_rx = count;
1507 mdp->dirty_rx = count;
1508 }
4a55530f 1509 sh_eth_write(ndev, EDRRR_R, EDRRR);
79fba9f5 1510 }
86a74ff2 1511
319cd520
MK		 1512 *quota -= limit - boguscnt - 1;
1513
4f809cea 1514 return *quota <= 0;
86a74ff2
NI		 1515}
1516
4a55530f 1517static void sh_eth_rcv_snd_disable(struct net_device *ndev)
dc19e4e5
NI		 1518{
1519 /* disable tx and rx */
b2b14d2f 1520 sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0);
dc19e4e5
NI		 1521}
1522
4a55530f 1523static void sh_eth_rcv_snd_enable(struct net_device *ndev)
dc19e4e5
NI		 1524{
1525 /* enable tx and rx */
b2b14d2f 1526 sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE);
dc19e4e5
NI		 1527}
1528
86a74ff2 1529/* error control function */
0799c2d6 1530static void sh_eth_error(struct net_device *ndev, u32 intr_status)
86a74ff2
NI		 1531{
1532 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2 1533 u32 felic_stat;
380af9e3
YS		 1534 u32 link_stat;
1535 u32 mask;
86a74ff2
NI		 1536
1537 if (intr_status & EESR_ECI) {
40634699
SS		 1538 felic_stat = sh_eth_read(ndev, ECSR) &
1539 sh_eth_read(ndev, ECSIPR);
4a55530f 1540 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */
86a74ff2 1541 if (felic_stat & ECSR_ICD)
bb7d92e3 1542 ndev->stats.tx_carrier_errors++;
86a74ff2
NI		 1543 if (felic_stat & ECSR_LCHNG) {
1544 /* Link Changed */
1940f240 1545 if (mdp->cd->no_psr || mdp->no_ether_link)
1e1b812b 1546 goto ignore_link;
1940f240
SS		 1547 link_stat = sh_eth_read(ndev, PSR);
1548 if (mdp->ether_link_active_low)
1549 link_stat = ~link_stat;
128296fc 1550 if (!(link_stat & PHY_ST_LINK)) {
4a55530f 1551 sh_eth_rcv_snd_disable(ndev);
128296fc 1552 } else {
86a74ff2 1553 /* Link Up */
b2b14d2f 1554 sh_eth_modify(ndev, EESIPR, DMAC_M_ECI, 0);
128296fc 1555 /* clear int */
b2b14d2f
SS		 1556 sh_eth_modify(ndev, ECSR, 0, 0);
1557 sh_eth_modify(ndev, EESIPR, DMAC_M_ECI,
1558 DMAC_M_ECI);
86a74ff2 1559 /* enable tx and rx */
4a55530f 1560 sh_eth_rcv_snd_enable(ndev);
86a74ff2
NI		 1561 }
1562 }
1563 }
1564
1e1b812b 1565ignore_link:
86a74ff2 1566 if (intr_status & EESR_TWB) {
4eb313a7
SS		 1567 /* Unused write back interrupt */
1568 if (intr_status & EESR_TABT) { /* Transmit Abort int */
bb7d92e3 1569 ndev->stats.tx_aborted_errors++;
8d5009f6 1570 netif_err(mdp, tx_err, ndev, "Transmit Abort\n");
4eb313a7 1571 }
86a74ff2
NI		 1572 }
1573
1574 if (intr_status & EESR_RABT) {
1575 /* Receive Abort int */
1576 if (intr_status & EESR_RFRMER) {
1577 /* Receive Frame Overflow int */
bb7d92e3 1578 ndev->stats.rx_frame_errors++;
86a74ff2
NI		 1579 }
1580 }
380af9e3 1581
dc19e4e5
NI		 1582 if (intr_status & EESR_TDE) {
1583 /* Transmit Descriptor Empty int */
bb7d92e3 1584 ndev->stats.tx_fifo_errors++;
8d5009f6 1585 netif_err(mdp, tx_err, ndev, "Transmit Descriptor Empty\n");
dc19e4e5
NI		 1586 }
1587
1588 if (intr_status & EESR_TFE) {
1589 /* FIFO under flow */
bb7d92e3 1590 ndev->stats.tx_fifo_errors++;
8d5009f6 1591 netif_err(mdp, tx_err, ndev, "Transmit FIFO Under flow\n");
86a74ff2
NI		 1592 }
1593
1594 if (intr_status & EESR_RDE) {
1595 /* Receive Descriptor Empty int */
bb7d92e3 1596 ndev->stats.rx_over_errors++;
86a74ff2 1597 }
dc19e4e5 1598
86a74ff2
NI		 1599 if (intr_status & EESR_RFE) {
1600 /* Receive FIFO Overflow int */
bb7d92e3 1601 ndev->stats.rx_fifo_errors++;
dc19e4e5
NI		 1602 }
1603
1604 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1605 /* Address Error */
bb7d92e3 1606 ndev->stats.tx_fifo_errors++;
8d5009f6 1607 netif_err(mdp, tx_err, ndev, "Address Error\n");
86a74ff2 1608 }
380af9e3
YS		 1609
1610 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1611 if (mdp->cd->no_ade)
1612 mask &= ~EESR_ADE;
1613 if (intr_status & mask) {
86a74ff2 1614 /* Tx error */
4a55530f 1615 u32 edtrr = sh_eth_read(ndev, EDTRR);
090d560f 1616
86a74ff2 1617 /* dmesg */
da246855
SS		 1618 netdev_err(ndev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1619 intr_status, mdp->cur_tx, mdp->dirty_tx,
1620 (u32)ndev->state, edtrr);
86a74ff2
NI		 1621 /* dirty buffer free */
1622 sh_eth_txfree(ndev);
1623
1624 /* SH7712 BUG */
c5ed5368 1625 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
86a74ff2 1626 /* tx dma start */
c5ed5368 1627 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
86a74ff2
NI		 1628 }
1629 /* wakeup */
1630 netif_wake_queue(ndev);
1631 }
1632}
1633
1634static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1635{
1636 struct net_device *ndev = netdev;
1637 struct sh_eth_private *mdp = netdev_priv(ndev);
380af9e3 1638 struct sh_eth_cpu_data *cd = mdp->cd;
0e0fde3c 1639 irqreturn_t ret = IRQ_NONE;
0799c2d6 1640 u32 intr_status, intr_enable;
86a74ff2 1641
86a74ff2
NI		 1642 spin_lock(&mdp->lock);
1643
3893b273 1644 /* Get interrupt status */
4a55530f 1645 intr_status = sh_eth_read(ndev, EESR);
3893b273
SS		 1646 /* Mask it with the interrupt mask, forcing ECI interrupt to be always
1647 * enabled since it's the one that comes thru regardless of the mask,
1648 * and we need to fully handle it in sh_eth_error() in order to quench
1649 * it as it doesn't get cleared by just writing 1 to the ECI bit...
1650 */
3719109d
SS		 1651 intr_enable = sh_eth_read(ndev, EESIPR);
1652 intr_status &= intr_enable | DMAC_M_ECI;
1653 if (intr_status & (EESR_RX_CHECK | cd->tx_check | cd->eesr_err_check))
0e0fde3c 1654 ret = IRQ_HANDLED;
3719109d 1655 else
283e38db
BH		 1656 goto out;
1657
1658 if (!likely(mdp->irq_enabled)) {
1659 sh_eth_write(ndev, 0, EESIPR);
1660 goto out;
1661 }
86a74ff2 1662
3719109d
SS		 1663 if (intr_status & EESR_RX_CHECK) {
1664 if (napi_schedule_prep(&mdp->napi)) {
1665 /* Mask Rx interrupts */
1666 sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK,
1667 EESIPR);
1668 __napi_schedule(&mdp->napi);
1669 } else {
da246855 1670 netdev_warn(ndev,
0799c2d6 1671 "ignoring interrupt, status 0x%08x, mask 0x%08x.\n",
da246855 1672 intr_status, intr_enable);
3719109d
SS		 1673 }
1674 }
86a74ff2 1675
b0ca2a21 1676 /* Tx Check */
380af9e3 1677 if (intr_status & cd->tx_check) {
3719109d
SS		 1678 /* Clear Tx interrupts */
1679 sh_eth_write(ndev, intr_status & cd->tx_check, EESR);
1680
86a74ff2
NI		 1681 sh_eth_txfree(ndev);
1682 netif_wake_queue(ndev);
1683 }
1684
3719109d
SS		 1685 if (intr_status & cd->eesr_err_check) {
1686 /* Clear error interrupts */
1687 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR);
1688
86a74ff2 1689 sh_eth_error(ndev, intr_status);
3719109d 1690 }
86a74ff2 1691
283e38db 1692out:
86a74ff2
NI		 1693 spin_unlock(&mdp->lock);
1694
0e0fde3c 1695 return ret;
86a74ff2
NI		 1696}
1697
3719109d
SS		 1698static int sh_eth_poll(struct napi_struct *napi, int budget)
1699{
1700 struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private,
1701 napi);
1702 struct net_device *ndev = napi->dev;
1703 int quota = budget;
0799c2d6 1704 u32 intr_status;
3719109d
SS		 1705
1706 for (;;) {
1707 intr_status = sh_eth_read(ndev, EESR);
1708 if (!(intr_status & EESR_RX_CHECK))
1709 break;
1710 /* Clear Rx interrupts */
1711 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR);
1712
1713 if (sh_eth_rx(ndev, intr_status, &quota))
1714 goto out;
1715 }
1716
1717 napi_complete(napi);
1718
1719 /* Reenable Rx interrupts */
283e38db
BH		 1720 if (mdp->irq_enabled)
1721 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
3719109d
SS		 1722out:
1723 return budget - quota;
1724}
1725
86a74ff2
NI		 1726/* PHY state control function */
1727static void sh_eth_adjust_link(struct net_device *ndev)
1728{
1729 struct sh_eth_private *mdp = netdev_priv(ndev);
9fd0375a 1730 struct phy_device *phydev = ndev->phydev;
86a74ff2
NI		 1731 int new_state = 0;
1732
3340d2aa 1733 if (phydev->link) {
86a74ff2
NI		 1734 if (phydev->duplex != mdp->duplex) {
1735 new_state = 1;
1736 mdp->duplex = phydev->duplex;
380af9e3
YS		 1737 if (mdp->cd->set_duplex)
1738 mdp->cd->set_duplex(ndev);
86a74ff2
NI		 1739 }
1740
1741 if (phydev->speed != mdp->speed) {
1742 new_state = 1;
1743 mdp->speed = phydev->speed;
380af9e3
YS		 1744 if (mdp->cd->set_rate)
1745 mdp->cd->set_rate(ndev);
86a74ff2 1746 }
3340d2aa 1747 if (!mdp->link) {
b2b14d2f 1748 sh_eth_modify(ndev, ECMR, ECMR_TXF, 0);
86a74ff2
NI		 1749 new_state = 1;
1750 mdp->link = phydev->link;
1e1b812b
SS		 1751 if (mdp->cd->no_psr || mdp->no_ether_link)
1752 sh_eth_rcv_snd_enable(ndev);
86a74ff2
NI		 1753 }
1754 } else if (mdp->link) {
1755 new_state = 1;
3340d2aa 1756 mdp->link = 0;
86a74ff2
NI		 1757 mdp->speed = 0;
1758 mdp->duplex = -1;
1e1b812b
SS		 1759 if (mdp->cd->no_psr || mdp->no_ether_link)
1760 sh_eth_rcv_snd_disable(ndev);
86a74ff2
NI		 1761 }
1762
dc19e4e5 1763 if (new_state && netif_msg_link(mdp))
86a74ff2
NI		 1764 phy_print_status(phydev);
1765}
1766
1767/* PHY init function */
1768static int sh_eth_phy_init(struct net_device *ndev)
1769{
702eca02 1770 struct device_node *np = ndev->dev.parent->of_node;
86a74ff2 1771 struct sh_eth_private *mdp = netdev_priv(ndev);
4fa8c3cc 1772 struct phy_device *phydev;
86a74ff2 1773
3340d2aa 1774 mdp->link = 0;
86a74ff2
NI		 1775 mdp->speed = 0;
1776 mdp->duplex = -1;
1777
1778 /* Try connect to PHY */
702eca02
BD		 1779 if (np) {
1780 struct device_node *pn;
1781
1782 pn = of_parse_phandle(np, "phy-handle", 0);
1783 phydev = of_phy_connect(ndev, pn,
1784 sh_eth_adjust_link, 0,
1785 mdp->phy_interface);
1786
8da703dc 1787 of_node_put(pn);
702eca02
BD		 1788 if (!phydev)
1789 phydev = ERR_PTR(-ENOENT);
1790 } else {
1791 char phy_id[MII_BUS_ID_SIZE + 3];
1792
1793 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
1794 mdp->mii_bus->id, mdp->phy_id);
1795
1796 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
1797 mdp->phy_interface);
1798 }
1799
86a74ff2 1800 if (IS_ERR(phydev)) {
da246855 1801 netdev_err(ndev, "failed to connect PHY\n");
86a74ff2
NI		 1802 return PTR_ERR(phydev);
1803 }
380af9e3 1804
2220943a 1805 phy_attached_info(phydev);
86a74ff2 1806
86a74ff2
NI		 1807 return 0;
1808}
1809
1810/* PHY control start function */
1811static int sh_eth_phy_start(struct net_device *ndev)
1812{
86a74ff2
NI		 1813 int ret;
1814
1815 ret = sh_eth_phy_init(ndev);
1816 if (ret)
1817 return ret;
1818
9fd0375a 1819 phy_start(ndev->phydev);
86a74ff2
NI		 1820
1821 return 0;
1822}
1823
f08aff44
PR		 1824static int sh_eth_get_link_ksettings(struct net_device *ndev,
1825 struct ethtool_link_ksettings *cmd)
dc19e4e5
NI		 1826{
1827 struct sh_eth_private *mdp = netdev_priv(ndev);
1828 unsigned long flags;
1829 int ret;
1830
9fd0375a 1831 if (!ndev->phydev)
4f9dce23
BH		 1832 return -ENODEV;
1833
dc19e4e5 1834 spin_lock_irqsave(&mdp->lock, flags);
f08aff44 1835 ret = phy_ethtool_ksettings_get(ndev->phydev, cmd);
dc19e4e5
NI		 1836 spin_unlock_irqrestore(&mdp->lock, flags);
1837
1838 return ret;
1839}
1840
f08aff44
PR		 1841static int sh_eth_set_link_ksettings(struct net_device *ndev,
1842 const struct ethtool_link_ksettings *cmd)
dc19e4e5
NI		 1843{
1844 struct sh_eth_private *mdp = netdev_priv(ndev);
1845 unsigned long flags;
1846 int ret;
dc19e4e5 1847
9fd0375a 1848 if (!ndev->phydev)
4f9dce23
BH		 1849 return -ENODEV;
1850
dc19e4e5
NI		 1851 spin_lock_irqsave(&mdp->lock, flags);
1852
1853 /* disable tx and rx */
4a55530f 1854 sh_eth_rcv_snd_disable(ndev);
dc19e4e5 1855
f08aff44 1856 ret = phy_ethtool_ksettings_set(ndev->phydev, cmd);
dc19e4e5
NI		 1857 if (ret)
1858 goto error_exit;
1859
f08aff44 1860 if (cmd->base.duplex == DUPLEX_FULL)
dc19e4e5
NI		 1861 mdp->duplex = 1;
1862 else
1863 mdp->duplex = 0;
1864
1865 if (mdp->cd->set_duplex)
1866 mdp->cd->set_duplex(ndev);
1867
1868error_exit:
1869 mdelay(1);
1870
1871 /* enable tx and rx */
4a55530f 1872 sh_eth_rcv_snd_enable(ndev);
dc19e4e5
NI		 1873
1874 spin_unlock_irqrestore(&mdp->lock, flags);
1875
1876 return ret;
1877}
1878
6b4b4fea
BH		 1879/* If it is ever necessary to increase SH_ETH_REG_DUMP_MAX_REGS, the
1880 * version must be bumped as well. Just adding registers up to that
1881 * limit is fine, as long as the existing register indices don't
1882 * change.
1883 */
1884#define SH_ETH_REG_DUMP_VERSION 1
1885#define SH_ETH_REG_DUMP_MAX_REGS 256
1886
1887static size_t __sh_eth_get_regs(struct net_device *ndev, u32 *buf)
1888{
1889 struct sh_eth_private *mdp = netdev_priv(ndev);
1890 struct sh_eth_cpu_data *cd = mdp->cd;
1891 u32 *valid_map;
1892 size_t len;
1893
1894 BUILD_BUG_ON(SH_ETH_MAX_REGISTER_OFFSET > SH_ETH_REG_DUMP_MAX_REGS);
1895
1896 /* Dump starts with a bitmap that tells ethtool which
1897 * registers are defined for this chip.
1898 */
1899 len = DIV_ROUND_UP(SH_ETH_REG_DUMP_MAX_REGS, 32);
1900 if (buf) {
1901 valid_map = buf;
1902 buf += len;
1903 } else {
1904 valid_map = NULL;
1905 }
1906
1907 /* Add a register to the dump, if it has a defined offset.
1908 * This automatically skips most undefined registers, but for
1909 * some it is also necessary to check a capability flag in
1910 * struct sh_eth_cpu_data.
1911 */
1912#define mark_reg_valid(reg) valid_map[reg / 32] |= 1U << (reg % 32)
1913#define add_reg_from(reg, read_expr) do { \
1914 if (mdp->reg_offset[reg] != SH_ETH_OFFSET_INVALID) { \
1915 if (buf) { \
1916 mark_reg_valid(reg); \
1917 *buf++ = read_expr; \
1918 } \
1919 ++len; \
1920 } \
1921 } while (0)
1922#define add_reg(reg) add_reg_from(reg, sh_eth_read(ndev, reg))
1923#define add_tsu_reg(reg) add_reg_from(reg, sh_eth_tsu_read(mdp, reg))
1924
1925 add_reg(EDSR);
1926 add_reg(EDMR);
1927 add_reg(EDTRR);
1928 add_reg(EDRRR);
1929 add_reg(EESR);
1930 add_reg(EESIPR);
1931 add_reg(TDLAR);
1932 add_reg(TDFAR);
1933 add_reg(TDFXR);
1934 add_reg(TDFFR);
1935 add_reg(RDLAR);
1936 add_reg(RDFAR);
1937 add_reg(RDFXR);
1938 add_reg(RDFFR);
1939 add_reg(TRSCER);
1940 add_reg(RMFCR);
1941 add_reg(TFTR);
1942 add_reg(FDR);
1943 add_reg(RMCR);
1944 add_reg(TFUCR);
1945 add_reg(RFOCR);
1946 if (cd->rmiimode)
1947 add_reg(RMIIMODE);
1948 add_reg(FCFTR);
1949 if (cd->rpadir)
1950 add_reg(RPADIR);
1951 if (!cd->no_trimd)
1952 add_reg(TRIMD);
1953 add_reg(ECMR);
1954 add_reg(ECSR);
1955 add_reg(ECSIPR);
1956 add_reg(PIR);
1957 if (!cd->no_psr)
1958 add_reg(PSR);
1959 add_reg(RDMLR);
1960 add_reg(RFLR);
1961 add_reg(IPGR);
1962 if (cd->apr)
1963 add_reg(APR);
1964 if (cd->mpr)
1965 add_reg(MPR);
1966 add_reg(RFCR);
1967 add_reg(RFCF);
1968 if (cd->tpauser)
1969 add_reg(TPAUSER);
1970 add_reg(TPAUSECR);
1971 add_reg(GECMR);
1972 if (cd->bculr)
1973 add_reg(BCULR);
1974 add_reg(MAHR);
1975 add_reg(MALR);
1976 add_reg(TROCR);
1977 add_reg(CDCR);
1978 add_reg(LCCR);
1979 add_reg(CNDCR);
1980 add_reg(CEFCR);
1981 add_reg(FRECR);
1982 add_reg(TSFRCR);
1983 add_reg(TLFRCR);
1984 add_reg(CERCR);
1985 add_reg(CEECR);
1986 add_reg(MAFCR);
1987 if (cd->rtrate)
1988 add_reg(RTRATE);
1989 if (cd->hw_crc)
1990 add_reg(CSMR);
1991 if (cd->select_mii)
1992 add_reg(RMII_MII);
1993 add_reg(ARSTR);
1994 if (cd->tsu) {
1995 add_tsu_reg(TSU_CTRST);
1996 add_tsu_reg(TSU_FWEN0);
1997 add_tsu_reg(TSU_FWEN1);
1998 add_tsu_reg(TSU_FCM);
1999 add_tsu_reg(TSU_BSYSL0);
2000 add_tsu_reg(TSU_BSYSL1);
2001 add_tsu_reg(TSU_PRISL0);
2002 add_tsu_reg(TSU_PRISL1);
2003 add_tsu_reg(TSU_FWSL0);
2004 add_tsu_reg(TSU_FWSL1);
2005 add_tsu_reg(TSU_FWSLC);
2006 add_tsu_reg(TSU_QTAG0);
2007 add_tsu_reg(TSU_QTAG1);
2008 add_tsu_reg(TSU_QTAGM0);
2009 add_tsu_reg(TSU_QTAGM1);
2010 add_tsu_reg(TSU_FWSR);
2011 add_tsu_reg(TSU_FWINMK);
2012 add_tsu_reg(TSU_ADQT0);
2013 add_tsu_reg(TSU_ADQT1);
2014 add_tsu_reg(TSU_VTAG0);
2015 add_tsu_reg(TSU_VTAG1);
2016 add_tsu_reg(TSU_ADSBSY);
2017 add_tsu_reg(TSU_TEN);
2018 add_tsu_reg(TSU_POST1);
2019 add_tsu_reg(TSU_POST2);
2020 add_tsu_reg(TSU_POST3);
2021 add_tsu_reg(TSU_POST4);
2022 if (mdp->reg_offset[TSU_ADRH0] != SH_ETH_OFFSET_INVALID) {
2023 /* This is the start of a table, not just a single
2024 * register.
2025 */
2026 if (buf) {
2027 unsigned int i;
2028
2029 mark_reg_valid(TSU_ADRH0);
2030 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES * 2; i++)
2031 *buf++ = ioread32(
2032 mdp->tsu_addr +
2033 mdp->reg_offset[TSU_ADRH0] +
2034 i * 4);
2035 }
2036 len += SH_ETH_TSU_CAM_ENTRIES * 2;
2037 }
2038 }
2039
2040#undef mark_reg_valid
2041#undef add_reg_from
2042#undef add_reg
2043#undef add_tsu_reg
2044
2045 return len * 4;
2046}
2047
2048static int sh_eth_get_regs_len(struct net_device *ndev)
2049{
2050 return __sh_eth_get_regs(ndev, NULL);
2051}
2052
2053static void sh_eth_get_regs(struct net_device *ndev, struct ethtool_regs *regs,
2054 void *buf)
2055{
2056 struct sh_eth_private *mdp = netdev_priv(ndev);
2057
2058 regs->version = SH_ETH_REG_DUMP_VERSION;
2059
2060 pm_runtime_get_sync(&mdp->pdev->dev);
2061 __sh_eth_get_regs(ndev, buf);
2062 pm_runtime_put_sync(&mdp->pdev->dev);
2063}
2064
dc19e4e5
NI		 2065static int sh_eth_nway_reset(struct net_device *ndev)
2066{
2067 struct sh_eth_private *mdp = netdev_priv(ndev);
2068 unsigned long flags;
2069 int ret;
2070
9fd0375a 2071 if (!ndev->phydev)
4f9dce23
BH		 2072 return -ENODEV;
2073
dc19e4e5 2074 spin_lock_irqsave(&mdp->lock, flags);
9fd0375a 2075 ret = phy_start_aneg(ndev->phydev);
dc19e4e5
NI		 2076 spin_unlock_irqrestore(&mdp->lock, flags);
2077
2078 return ret;
2079}
2080
2081static u32 sh_eth_get_msglevel(struct net_device *ndev)
2082{
2083 struct sh_eth_private *mdp = netdev_priv(ndev);
2084 return mdp->msg_enable;
2085}
2086
2087static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
2088{
2089 struct sh_eth_private *mdp = netdev_priv(ndev);
2090 mdp->msg_enable = value;
2091}
2092
2093static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
2094 "rx_current", "tx_current",
2095 "rx_dirty", "tx_dirty",
2096};
2097#define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats)
2098
2099static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
2100{
2101 switch (sset) {
2102 case ETH_SS_STATS:
2103 return SH_ETH_STATS_LEN;
2104 default:
2105 return -EOPNOTSUPP;
2106 }
2107}
2108
2109static void sh_eth_get_ethtool_stats(struct net_device *ndev,
128296fc 2110 struct ethtool_stats *stats, u64 *data)
dc19e4e5
NI		 2111{
2112 struct sh_eth_private *mdp = netdev_priv(ndev);
2113 int i = 0;
2114
2115 /* device-specific stats */
2116 data[i++] = mdp->cur_rx;
2117 data[i++] = mdp->cur_tx;
2118 data[i++] = mdp->dirty_rx;
2119 data[i++] = mdp->dirty_tx;
2120}
2121
2122static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
2123{
2124 switch (stringset) {
2125 case ETH_SS_STATS:
2126 memcpy(data, *sh_eth_gstrings_stats,
128296fc 2127 sizeof(sh_eth_gstrings_stats));
dc19e4e5
NI		 2128 break;
2129 }
2130}
2131
525b8075
YS		 2132static void sh_eth_get_ringparam(struct net_device *ndev,
2133 struct ethtool_ringparam *ring)
2134{
2135 struct sh_eth_private *mdp = netdev_priv(ndev);
2136
2137 ring->rx_max_pending = RX_RING_MAX;
2138 ring->tx_max_pending = TX_RING_MAX;
2139 ring->rx_pending = mdp->num_rx_ring;
2140 ring->tx_pending = mdp->num_tx_ring;
2141}
2142
2143static int sh_eth_set_ringparam(struct net_device *ndev,
2144 struct ethtool_ringparam *ring)
2145{
2146 struct sh_eth_private *mdp = netdev_priv(ndev);
2147 int ret;
2148
2149 if (ring->tx_pending > TX_RING_MAX ||
2150 ring->rx_pending > RX_RING_MAX ||
2151 ring->tx_pending < TX_RING_MIN ||
2152 ring->rx_pending < RX_RING_MIN)
2153 return -EINVAL;
2154 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
2155 return -EINVAL;
2156
2157 if (netif_running(ndev)) {
bd888916 2158 netif_device_detach(ndev);
525b8075 2159 netif_tx_disable(ndev);
283e38db
BH		 2160
2161 /* Serialise with the interrupt handler and NAPI, then
2162 * disable interrupts. We have to clear the
2163 * irq_enabled flag first to ensure that interrupts
2164 * won't be re-enabled.
2165 */
2166 mdp->irq_enabled = false;
525b8075 2167 synchronize_irq(ndev->irq);
283e38db 2168 napi_synchronize(&mdp->napi);
525b8075 2169 sh_eth_write(ndev, 0x0000, EESIPR);
525b8075 2170
740c7f31 2171 sh_eth_dev_exit(ndev);
525b8075 2172
8e03a5e7 2173 /* Free all the skbuffs in the Rx queue and the DMA buffers. */
084236d8 2174 sh_eth_ring_free(ndev);
084236d8 2175 }
525b8075
YS		 2176
2177 /* Set new parameters */
2178 mdp->num_rx_ring = ring->rx_pending;
2179 mdp->num_tx_ring = ring->tx_pending;
2180
525b8075 2181 if (netif_running(ndev)) {
084236d8
BH		 2182 ret = sh_eth_ring_init(ndev);
2183 if (ret < 0) {
2184 netdev_err(ndev, "%s: sh_eth_ring_init failed.\n",
2185 __func__);
2186 return ret;
2187 }
f7967210 2188 ret = sh_eth_dev_init(ndev);
084236d8
BH		 2189 if (ret < 0) {
2190 netdev_err(ndev, "%s: sh_eth_dev_init failed.\n",
2191 __func__);
2192 return ret;
2193 }
2194
bd888916 2195 netif_device_attach(ndev);
525b8075
YS		 2196 }
2197
2198 return 0;
2199}
2200
9b07be4b 2201static const struct ethtool_ops sh_eth_ethtool_ops = {
6b4b4fea
BH		 2202 .get_regs_len = sh_eth_get_regs_len,
2203 .get_regs = sh_eth_get_regs,
9b07be4b 2204 .nway_reset = sh_eth_nway_reset,
dc19e4e5
NI		 2205 .get_msglevel = sh_eth_get_msglevel,
2206 .set_msglevel = sh_eth_set_msglevel,
9b07be4b 2207 .get_link = ethtool_op_get_link,
dc19e4e5
NI		 2208 .get_strings = sh_eth_get_strings,
2209 .get_ethtool_stats = sh_eth_get_ethtool_stats,
2210 .get_sset_count = sh_eth_get_sset_count,
525b8075
YS		 2211 .get_ringparam = sh_eth_get_ringparam,
2212 .set_ringparam = sh_eth_set_ringparam,
f08aff44
PR		 2213 .get_link_ksettings = sh_eth_get_link_ksettings,
2214 .set_link_ksettings = sh_eth_set_link_ksettings,
dc19e4e5
NI		 2215};
2216
86a74ff2
NI		 2217/* network device open function */
2218static int sh_eth_open(struct net_device *ndev)
2219{
86a74ff2 2220 struct sh_eth_private *mdp = netdev_priv(ndev);
4fa8c3cc 2221 int ret;
86a74ff2 2222
bcd5149d
MD		 2223 pm_runtime_get_sync(&mdp->pdev->dev);
2224
d2779e99
SS		 2225 napi_enable(&mdp->napi);
2226
a0607fd3 2227 ret = request_irq(ndev->irq, sh_eth_interrupt,
5b3dfd13 2228 mdp->cd->irq_flags, ndev->name, ndev);
86a74ff2 2229 if (ret) {
da246855 2230 netdev_err(ndev, "Can not assign IRQ number\n");
d2779e99 2231 goto out_napi_off;
86a74ff2
NI		 2232 }
2233
2234 /* Descriptor set */
2235 ret = sh_eth_ring_init(ndev);
2236 if (ret)
2237 goto out_free_irq;
2238
2239 /* device init */
f7967210 2240 ret = sh_eth_dev_init(ndev);
86a74ff2
NI		 2241 if (ret)
2242 goto out_free_irq;
2243
2244 /* PHY control start*/
2245 ret = sh_eth_phy_start(ndev);
2246 if (ret)
2247 goto out_free_irq;
2248
ad846aa5
SS		 2249 netif_start_queue(ndev);
2250
7fa2955f
MK		 2251 mdp->is_opened = 1;
2252
86a74ff2
NI		 2253 return ret;
2254
2255out_free_irq:
2256 free_irq(ndev->irq, ndev);
d2779e99
SS		 2257out_napi_off:
2258 napi_disable(&mdp->napi);
bcd5149d 2259 pm_runtime_put_sync(&mdp->pdev->dev);
86a74ff2
NI		 2260 return ret;
2261}
2262
2263/* Timeout function */
2264static void sh_eth_tx_timeout(struct net_device *ndev)
2265{
2266 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 2267 struct sh_eth_rxdesc *rxdesc;
2268 int i;
2269
2270 netif_stop_queue(ndev);
2271
8d5009f6
SS		 2272 netif_err(mdp, timer, ndev,
2273 "transmit timed out, status %8.8x, resetting...\n",
0799c2d6 2274 sh_eth_read(ndev, EESR));
86a74ff2
NI		 2275
2276 /* tx_errors count up */
bb7d92e3 2277 ndev->stats.tx_errors++;
86a74ff2 2278
86a74ff2 2279 /* Free all the skbuffs in the Rx queue. */
525b8075 2280 for (i = 0; i < mdp->num_rx_ring; i++) {
86a74ff2 2281 rxdesc = &mdp->rx_ring[i];
7cf72477
SS		 2282 rxdesc->status = cpu_to_le32(0);
2283 rxdesc->addr = cpu_to_le32(0xBADF00D0);
179d80af 2284 dev_kfree_skb(mdp->rx_skbuff[i]);
86a74ff2
NI		 2285 mdp->rx_skbuff[i] = NULL;
2286 }
525b8075 2287 for (i = 0; i < mdp->num_tx_ring; i++) {
179d80af 2288 dev_kfree_skb(mdp->tx_skbuff[i]);
86a74ff2
NI		 2289 mdp->tx_skbuff[i] = NULL;
2290 }
2291
2292 /* device init */
f7967210 2293 sh_eth_dev_init(ndev);
ad846aa5
SS		 2294
2295 netif_start_queue(ndev);
86a74ff2
NI		 2296}
2297
2298/* Packet transmit function */
2299static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
2300{
2301 struct sh_eth_private *mdp = netdev_priv(ndev);
2302 struct sh_eth_txdesc *txdesc;
1299653a 2303 dma_addr_t dma_addr;
86a74ff2 2304 u32 entry;
fb5e2f9b 2305 unsigned long flags;
86a74ff2
NI		 2306
2307 spin_lock_irqsave(&mdp->lock, flags);
525b8075 2308 if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
86a74ff2 2309 if (!sh_eth_txfree(ndev)) {
8d5009f6 2310 netif_warn(mdp, tx_queued, ndev, "TxFD exhausted.\n");
86a74ff2
NI		 2311 netif_stop_queue(ndev);
2312 spin_unlock_irqrestore(&mdp->lock, flags);
5b548140 2313 return NETDEV_TX_BUSY;
86a74ff2
NI		 2314 }
2315 }
2316 spin_unlock_irqrestore(&mdp->lock, flags);
2317
dacc73e0 2318 if (skb_put_padto(skb, ETH_ZLEN))
eebfb643
BH		 2319 return NETDEV_TX_OK;
2320
525b8075 2321 entry = mdp->cur_tx % mdp->num_tx_ring;
86a74ff2
NI		 2322 mdp->tx_skbuff[entry] = skb;
2323 txdesc = &mdp->tx_ring[entry];
86a74ff2 2324 /* soft swap. */
380af9e3 2325 if (!mdp->cd->hw_swap)
3e230993 2326 sh_eth_soft_swap(PTR_ALIGN(skb->data, 4), skb->len + 2);
1299653a
SS		 2327 dma_addr = dma_map_single(&ndev->dev, skb->data, skb->len,
2328 DMA_TO_DEVICE);
2329 if (dma_mapping_error(&ndev->dev, dma_addr)) {
aa3933b8
BH		 2330 kfree_skb(skb);
2331 return NETDEV_TX_OK;
2332 }
7cf72477
SS		 2333 txdesc->addr = cpu_to_le32(dma_addr);
2334 txdesc->len = cpu_to_le32(skb->len << 16);
86a74ff2 2335
f32bfb9a 2336 dma_wmb(); /* TACT bit must be set after all the above writes */
525b8075 2337 if (entry >= mdp->num_tx_ring - 1)
7cf72477 2338 txdesc->status |= cpu_to_le32(TD_TACT | TD_TDLE);
86a74ff2 2339 else
7cf72477 2340 txdesc->status |= cpu_to_le32(TD_TACT);
86a74ff2
NI		 2341
2342 mdp->cur_tx++;
2343
c5ed5368
YS		 2344 if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
2345 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
b0ca2a21 2346
6ed10654 2347 return NETDEV_TX_OK;
86a74ff2
NI		 2348}
2349
4398f9c8
BH		 2350/* The statistics registers have write-clear behaviour, which means we
2351 * will lose any increment between the read and write. We mitigate
2352 * this by only clearing when we read a non-zero value, so we will
2353 * never falsely report a total of zero.
2354 */
2355static void
2356sh_eth_update_stat(struct net_device *ndev, unsigned long *stat, int reg)
2357{
2358 u32 delta = sh_eth_read(ndev, reg);
2359
2360 if (delta) {
2361 *stat += delta;
2362 sh_eth_write(ndev, 0, reg);
2363 }
2364}
2365
7fa2955f
MK		 2366static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
2367{
2368 struct sh_eth_private *mdp = netdev_priv(ndev);
2369
2370 if (sh_eth_is_rz_fast_ether(mdp))
2371 return &ndev->stats;
2372
2373 if (!mdp->is_opened)
2374 return &ndev->stats;
2375
4398f9c8
BH		 2376 sh_eth_update_stat(ndev, &ndev->stats.tx_dropped, TROCR);
2377 sh_eth_update_stat(ndev, &ndev->stats.collisions, CDCR);
2378 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, LCCR);
7fa2955f
MK		 2379
2380 if (sh_eth_is_gether(mdp)) {
4398f9c8
BH		 2381 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2382 CERCR);
2383 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2384 CEECR);
7fa2955f 2385 } else {
4398f9c8
BH		 2386 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2387 CNDCR);
7fa2955f
MK		 2388 }
2389
2390 return &ndev->stats;
2391}
2392
86a74ff2
NI		 2393/* device close function */
2394static int sh_eth_close(struct net_device *ndev)
2395{
2396 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 2397
2398 netif_stop_queue(ndev);
2399
283e38db
BH		 2400 /* Serialise with the interrupt handler and NAPI, then disable
2401 * interrupts. We have to clear the irq_enabled flag first to
2402 * ensure that interrupts won't be re-enabled.
2403 */
2404 mdp->irq_enabled = false;
2405 synchronize_irq(ndev->irq);
2406 napi_disable(&mdp->napi);
4a55530f 2407 sh_eth_write(ndev, 0x0000, EESIPR);
86a74ff2 2408
740c7f31 2409 sh_eth_dev_exit(ndev);
86a74ff2
NI		 2410
2411 /* PHY Disconnect */
9fd0375a
PR		 2412 if (ndev->phydev) {
2413 phy_stop(ndev->phydev);
2414 phy_disconnect(ndev->phydev);
86a74ff2
NI		 2415 }
2416
2417 free_irq(ndev->irq, ndev);
2418
8e03a5e7 2419 /* Free all the skbuffs in the Rx queue and the DMA buffer. */
86a74ff2
NI		 2420 sh_eth_ring_free(ndev);
2421
bcd5149d
MD		 2422 pm_runtime_put_sync(&mdp->pdev->dev);
2423
7fa2955f 2424 mdp->is_opened = 0;
bcd5149d 2425
7fa2955f 2426 return 0;
86a74ff2
NI		 2427}
2428
bb7d92e3 2429/* ioctl to device function */
128296fc 2430static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
86a74ff2 2431{
9fd0375a 2432 struct phy_device *phydev = ndev->phydev;
86a74ff2
NI		 2433
2434 if (!netif_running(ndev))
2435 return -EINVAL;
2436
2437 if (!phydev)
2438 return -ENODEV;
2439
28b04113 2440 return phy_mii_ioctl(phydev, rq, cmd);
86a74ff2
NI		 2441}
2442
6743fe6d
YS		 2443/* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
2444static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp,
2445 int entry)
2446{
2447 return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4);
2448}
2449
2450static u32 sh_eth_tsu_get_post_mask(int entry)
2451{
2452 return 0x0f << (28 - ((entry % 8) * 4));
2453}
2454
2455static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
2456{
2457 return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
2458}
2459
2460static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
2461 int entry)
2462{
2463 struct sh_eth_private *mdp = netdev_priv(ndev);
2464 u32 tmp;
2465 void *reg_offset;
2466
2467 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2468 tmp = ioread32(reg_offset);
2469 iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset);
2470}
2471
2472static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
2473 int entry)
2474{
2475 struct sh_eth_private *mdp = netdev_priv(ndev);
2476 u32 post_mask, ref_mask, tmp;
2477 void *reg_offset;
2478
2479 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2480 post_mask = sh_eth_tsu_get_post_mask(entry);
2481 ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
2482
2483 tmp = ioread32(reg_offset);
2484 iowrite32(tmp & ~post_mask, reg_offset);
2485
2486 /* If other port enables, the function returns "true" */
2487 return tmp & ref_mask;
2488}
2489
2490static int sh_eth_tsu_busy(struct net_device *ndev)
2491{
2492 int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
2493 struct sh_eth_private *mdp = netdev_priv(ndev);
2494
2495 while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
2496 udelay(10);
2497 timeout--;
2498 if (timeout <= 0) {
da246855 2499 netdev_err(ndev, "%s: timeout\n", __func__);
6743fe6d
YS		 2500 return -ETIMEDOUT;
2501 }
2502 }
2503
2504 return 0;
2505}
2506
2507static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg,
2508 const u8 *addr)
2509{
2510 u32 val;
2511
2512 val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
2513 iowrite32(val, reg);
2514 if (sh_eth_tsu_busy(ndev) < 0)
2515 return -EBUSY;
2516
2517 val = addr[4] << 8 | addr[5];
2518 iowrite32(val, reg + 4);
2519 if (sh_eth_tsu_busy(ndev) < 0)
2520 return -EBUSY;
2521
2522 return 0;
2523}
2524
2525static void sh_eth_tsu_read_entry(void *reg, u8 *addr)
2526{
2527 u32 val;
2528
2529 val = ioread32(reg);
2530 addr[0] = (val >> 24) & 0xff;
2531 addr[1] = (val >> 16) & 0xff;
2532 addr[2] = (val >> 8) & 0xff;
2533 addr[3] = val & 0xff;
2534 val = ioread32(reg + 4);
2535 addr[4] = (val >> 8) & 0xff;
2536 addr[5] = val & 0xff;
2537}
2538
2539
2540static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
2541{
2542 struct sh_eth_private *mdp = netdev_priv(ndev);
2543 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2544 int i;
2545 u8 c_addr[ETH_ALEN];
2546
2547 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2548 sh_eth_tsu_read_entry(reg_offset, c_addr);
c4bde29c 2549 if (ether_addr_equal(addr, c_addr))
6743fe6d
YS		 2550 return i;
2551 }
2552
2553 return -ENOENT;
2554}
2555
2556static int sh_eth_tsu_find_empty(struct net_device *ndev)
2557{
2558 u8 blank[ETH_ALEN];
2559 int entry;
2560
2561 memset(blank, 0, sizeof(blank));
2562 entry = sh_eth_tsu_find_entry(ndev, blank);
2563 return (entry < 0) ? -ENOMEM : entry;
2564}
2565
2566static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
2567 int entry)
2568{
2569 struct sh_eth_private *mdp = netdev_priv(ndev);
2570 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2571 int ret;
2572 u8 blank[ETH_ALEN];
2573
2574 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
2575 ~(1 << (31 - entry)), TSU_TEN);
2576
2577 memset(blank, 0, sizeof(blank));
2578 ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
2579 if (ret < 0)
2580 return ret;
2581 return 0;
2582}
2583
2584static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
2585{
2586 struct sh_eth_private *mdp = netdev_priv(ndev);
2587 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2588 int i, ret;
2589
2590 if (!mdp->cd->tsu)
2591 return 0;
2592
2593 i = sh_eth_tsu_find_entry(ndev, addr);
2594 if (i < 0) {
2595 /* No entry found, create one */
2596 i = sh_eth_tsu_find_empty(ndev);
2597 if (i < 0)
2598 return -ENOMEM;
2599 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
2600 if (ret < 0)
2601 return ret;
2602
2603 /* Enable the entry */
2604 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
2605 (1 << (31 - i)), TSU_TEN);
2606 }
2607
2608 /* Entry found or created, enable POST */
2609 sh_eth_tsu_enable_cam_entry_post(ndev, i);
2610
2611 return 0;
2612}
2613
2614static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
2615{
2616 struct sh_eth_private *mdp = netdev_priv(ndev);
2617 int i, ret;
2618
2619 if (!mdp->cd->tsu)
2620 return 0;
2621
2622 i = sh_eth_tsu_find_entry(ndev, addr);
2623 if (i) {
2624 /* Entry found */
2625 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2626 goto done;
2627
2628 /* Disable the entry if both ports was disabled */
2629 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2630 if (ret < 0)
2631 return ret;
2632 }
2633done:
2634 return 0;
2635}
2636
2637static int sh_eth_tsu_purge_all(struct net_device *ndev)
2638{
2639 struct sh_eth_private *mdp = netdev_priv(ndev);
2640 int i, ret;
2641
b37feed7 2642 if (!mdp->cd->tsu)
6743fe6d
YS		 2643 return 0;
2644
2645 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
2646 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2647 continue;
2648
2649 /* Disable the entry if both ports was disabled */
2650 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2651 if (ret < 0)
2652 return ret;
2653 }
2654
2655 return 0;
2656}
2657
2658static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
2659{
2660 struct sh_eth_private *mdp = netdev_priv(ndev);
2661 u8 addr[ETH_ALEN];
2662 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2663 int i;
2664
b37feed7 2665 if (!mdp->cd->tsu)
6743fe6d
YS		 2666 return;
2667
2668 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2669 sh_eth_tsu_read_entry(reg_offset, addr);
2670 if (is_multicast_ether_addr(addr))
2671 sh_eth_tsu_del_entry(ndev, addr);
2672 }
2673}
2674
b37feed7
BH		 2675/* Update promiscuous flag and multicast filter */
2676static void sh_eth_set_rx_mode(struct net_device *ndev)
86a74ff2 2677{
6743fe6d
YS		 2678 struct sh_eth_private *mdp = netdev_priv(ndev);
2679 u32 ecmr_bits;
2680 int mcast_all = 0;
2681 unsigned long flags;
2682
2683 spin_lock_irqsave(&mdp->lock, flags);
128296fc 2684 /* Initial condition is MCT = 1, PRM = 0.
6743fe6d
YS		 2685 * Depending on ndev->flags, set PRM or clear MCT
2686 */
b37feed7
BH		 2687 ecmr_bits = sh_eth_read(ndev, ECMR) & ~ECMR_PRM;
2688 if (mdp->cd->tsu)
2689 ecmr_bits |= ECMR_MCT;
6743fe6d
YS		 2690
2691 if (!(ndev->flags & IFF_MULTICAST)) {
2692 sh_eth_tsu_purge_mcast(ndev);
2693 mcast_all = 1;
2694 }
2695 if (ndev->flags & IFF_ALLMULTI) {
2696 sh_eth_tsu_purge_mcast(ndev);
2697 ecmr_bits &= ~ECMR_MCT;
2698 mcast_all = 1;
2699 }
2700
86a74ff2 2701 if (ndev->flags & IFF_PROMISC) {
6743fe6d
YS		 2702 sh_eth_tsu_purge_all(ndev);
2703 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2704 } else if (mdp->cd->tsu) {
2705 struct netdev_hw_addr *ha;
2706 netdev_for_each_mc_addr(ha, ndev) {
2707 if (mcast_all && is_multicast_ether_addr(ha->addr))
2708 continue;
2709
2710 if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2711 if (!mcast_all) {
2712 sh_eth_tsu_purge_mcast(ndev);
2713 ecmr_bits &= ~ECMR_MCT;
2714 mcast_all = 1;
2715 }
2716 }
2717 }
86a74ff2 2718 }
6743fe6d
YS		 2719
2720 /* update the ethernet mode */
2721 sh_eth_write(ndev, ecmr_bits, ECMR);
2722
2723 spin_unlock_irqrestore(&mdp->lock, flags);
86a74ff2 2724}
71cc7c37
YS		 2725
2726static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2727{
2728 if (!mdp->port)
2729 return TSU_VTAG0;
2730 else
2731 return TSU_VTAG1;
2732}
2733
80d5c368
PM		 2734static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
2735 __be16 proto, u16 vid)
71cc7c37
YS		 2736{
2737 struct sh_eth_private *mdp = netdev_priv(ndev);
2738 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2739
2740 if (unlikely(!mdp->cd->tsu))
2741 return -EPERM;
2742
2743 /* No filtering if vid = 0 */
2744 if (!vid)
2745 return 0;
2746
2747 mdp->vlan_num_ids++;
2748
128296fc 2749 /* The controller has one VLAN tag HW filter. So, if the filter is
71cc7c37
YS		 2750 * already enabled, the driver disables it and the filte
2751 */
2752 if (mdp->vlan_num_ids > 1) {
2753 /* disable VLAN filter */
2754 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2755 return 0;
2756 }
2757
2758 sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
2759 vtag_reg_index);
2760
2761 return 0;
2762}
2763
80d5c368
PM		 2764static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
2765 __be16 proto, u16 vid)
71cc7c37
YS		 2766{
2767 struct sh_eth_private *mdp = netdev_priv(ndev);
2768 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2769
2770 if (unlikely(!mdp->cd->tsu))
2771 return -EPERM;
2772
2773 /* No filtering if vid = 0 */
2774 if (!vid)
2775 return 0;
2776
2777 mdp->vlan_num_ids--;
2778 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2779
2780 return 0;
2781}
86a74ff2
NI		 2782
2783/* SuperH's TSU register init function */
4a55530f 2784static void sh_eth_tsu_init(struct sh_eth_private *mdp)
86a74ff2 2785{
db893473
SH		 2786 if (sh_eth_is_rz_fast_ether(mdp)) {
2787 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
e1487888
CB		 2788 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL,
2789 TSU_FWSLC); /* Enable POST registers */
db893473
SH		 2790 return;
2791 }
2792
4a55530f
YS		 2793 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */
2794 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */
2795 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */
2796 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
2797 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
2798 sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
2799 sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
2800 sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
2801 sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
2802 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
c5ed5368
YS		 2803 if (sh_eth_is_gether(mdp)) {
2804 sh_eth_tsu_write(mdp, 0, TSU_QTAG0); /* Disable QTAG(0->1) */
2805 sh_eth_tsu_write(mdp, 0, TSU_QTAG1); /* Disable QTAG(1->0) */
2806 } else {
2807 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */
2808 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */
2809 }
4a55530f
YS		 2810 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */
2811 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */
2812 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2813 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */
2814 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */
2815 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */
2816 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */
86a74ff2
NI		 2817}
2818
2819/* MDIO bus release function */
bd920ff5 2820static int sh_mdio_release(struct sh_eth_private *mdp)
86a74ff2 2821{
86a74ff2 2822 /* unregister mdio bus */
bd920ff5 2823 mdiobus_unregister(mdp->mii_bus);
86a74ff2
NI		 2824
2825 /* free bitbang info */
bd920ff5 2826 free_mdio_bitbang(mdp->mii_bus);
86a74ff2
NI		 2827
2828 return 0;
2829}
2830
2831/* MDIO bus init function */
bd920ff5 2832static int sh_mdio_init(struct sh_eth_private *mdp,
b3017e6a 2833 struct sh_eth_plat_data *pd)
86a74ff2 2834{
e7f4dc35 2835 int ret;
86a74ff2 2836 struct bb_info *bitbang;
bd920ff5 2837 struct platform_device *pdev = mdp->pdev;
aa8d4225 2838 struct device *dev = &mdp->pdev->dev;
86a74ff2
NI		 2839
2840 /* create bit control struct for PHY */
aa8d4225 2841 bitbang = devm_kzalloc(dev, sizeof(struct bb_info), GFP_KERNEL);
f738a13d
LP		 2842 if (!bitbang)
2843 return -ENOMEM;
86a74ff2
NI		 2844
2845 /* bitbang init */
ae70644d 2846 bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
b3017e6a 2847 bitbang->set_gate = pd->set_mdio_gate;
86a74ff2
NI		 2848 bitbang->ctrl.ops = &bb_ops;
2849
c2e07b3a 2850 /* MII controller setting */
86a74ff2 2851 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
f738a13d
LP		 2852 if (!mdp->mii_bus)
2853 return -ENOMEM;
86a74ff2
NI		 2854
2855 /* Hook up MII support for ethtool */
2856 mdp->mii_bus->name = "sh_mii";
a5bd6060 2857 mdp->mii_bus->parent = dev;
5278fb54 2858 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
bd920ff5 2859 pdev->name, pdev->id);
86a74ff2 2860
bd920ff5
LP		 2861 /* register MDIO bus */
2862 if (dev->of_node) {
2863 ret = of_mdiobus_register(mdp->mii_bus, dev->of_node);
702eca02 2864 } else {
702eca02
BD		 2865 if (pd->phy_irq > 0)
2866 mdp->mii_bus->irq[pd->phy] = pd->phy_irq;
2867
2868 ret = mdiobus_register(mdp->mii_bus);
2869 }
2870
86a74ff2 2871 if (ret)
d5e07e69 2872 goto out_free_bus;
86a74ff2 2873
86a74ff2
NI		 2874 return 0;
2875
86a74ff2 2876out_free_bus:
298cf9be 2877 free_mdio_bitbang(mdp->mii_bus);
86a74ff2
NI		 2878 return ret;
2879}
2880
4a55530f
YS		 2881static const u16 *sh_eth_get_register_offset(int register_type)
2882{
2883 const u16 *reg_offset = NULL;
2884
2885 switch (register_type) {
2886 case SH_ETH_REG_GIGABIT:
2887 reg_offset = sh_eth_offset_gigabit;
2888 break;
db893473
SH		 2889 case SH_ETH_REG_FAST_RZ:
2890 reg_offset = sh_eth_offset_fast_rz;
2891 break;
a3f109bd
SS		 2892 case SH_ETH_REG_FAST_RCAR:
2893 reg_offset = sh_eth_offset_fast_rcar;
2894 break;
4a55530f
YS		 2895 case SH_ETH_REG_FAST_SH4:
2896 reg_offset = sh_eth_offset_fast_sh4;
2897 break;
2898 case SH_ETH_REG_FAST_SH3_SH2:
2899 reg_offset = sh_eth_offset_fast_sh3_sh2;
2900 break;
4a55530f
YS		 2901 }
2902
2903 return reg_offset;
2904}
2905
8f728d79 2906static const struct net_device_ops sh_eth_netdev_ops = {
ebf84eaa
AB		 2907 .ndo_open = sh_eth_open,
2908 .ndo_stop = sh_eth_close,
2909 .ndo_start_xmit = sh_eth_start_xmit,
2910 .ndo_get_stats = sh_eth_get_stats,
b37feed7 2911 .ndo_set_rx_mode = sh_eth_set_rx_mode,
ebf84eaa
AB		 2912 .ndo_tx_timeout = sh_eth_tx_timeout,
2913 .ndo_do_ioctl = sh_eth_do_ioctl,
2914 .ndo_validate_addr = eth_validate_addr,
2915 .ndo_set_mac_address = eth_mac_addr,
ebf84eaa
AB		 2916};
2917
8f728d79
SS		 2918static const struct net_device_ops sh_eth_netdev_ops_tsu = {
2919 .ndo_open = sh_eth_open,
2920 .ndo_stop = sh_eth_close,
2921 .ndo_start_xmit = sh_eth_start_xmit,
2922 .ndo_get_stats = sh_eth_get_stats,
b37feed7 2923 .ndo_set_rx_mode = sh_eth_set_rx_mode,
8f728d79
SS		 2924 .ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid,
2925 .ndo_vlan_rx_kill_vid = sh_eth_vlan_rx_kill_vid,
2926 .ndo_tx_timeout = sh_eth_tx_timeout,
2927 .ndo_do_ioctl = sh_eth_do_ioctl,
2928 .ndo_validate_addr = eth_validate_addr,
2929 .ndo_set_mac_address = eth_mac_addr,
8f728d79
SS		 2930};
2931
b356e978
SS		 2932#ifdef CONFIG_OF
2933static struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
2934{
2935 struct device_node *np = dev->of_node;
2936 struct sh_eth_plat_data *pdata;
b356e978
SS		 2937 const char *mac_addr;
2938
2939 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
2940 if (!pdata)
2941 return NULL;
2942
2943 pdata->phy_interface = of_get_phy_mode(np);
2944
b356e978
SS		 2945 mac_addr = of_get_mac_address(np);
2946 if (mac_addr)
2947 memcpy(pdata->mac_addr, mac_addr, ETH_ALEN);
2948
2949 pdata->no_ether_link =
2950 of_property_read_bool(np, "renesas,no-ether-link");
2951 pdata->ether_link_active_low =
2952 of_property_read_bool(np, "renesas,ether-link-active-low");
2953
2954 return pdata;
2955}
2956
2957static const struct of_device_id sh_eth_match_table[] = {
2958 { .compatible = "renesas,gether-r8a7740", .data = &r8a7740_data },
c099ff3c
SS		 2959 { .compatible = "renesas,ether-r8a7743", .data = &r8a779x_data },
2960 { .compatible = "renesas,ether-r8a7745", .data = &r8a779x_data },
b356e978
SS		 2961 { .compatible = "renesas,ether-r8a7778", .data = &r8a777x_data },
2962 { .compatible = "renesas,ether-r8a7779", .data = &r8a777x_data },
2963 { .compatible = "renesas,ether-r8a7790", .data = &r8a779x_data },
2964 { .compatible = "renesas,ether-r8a7791", .data = &r8a779x_data },
9488e1e5 2965 { .compatible = "renesas,ether-r8a7793", .data = &r8a779x_data },
0f76b9d8 2966 { .compatible = "renesas,ether-r8a7794", .data = &r8a779x_data },
b356e978
SS		 2967 { .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data },
2968 { }
2969};
2970MODULE_DEVICE_TABLE(of, sh_eth_match_table);
2971#else
2972static inline struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
2973{
2974 return NULL;
2975}
2976#endif
2977
86a74ff2
NI		 2978static int sh_eth_drv_probe(struct platform_device *pdev)
2979{
86a74ff2 2980 struct resource *res;
0b76b862 2981 struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev);
afe391ad 2982 const struct platform_device_id *id = platform_get_device_id(pdev);
4fa8c3cc
SS		 2983 struct sh_eth_private *mdp;
2984 struct net_device *ndev;
2985 int ret, devno;
86a74ff2
NI		 2986
2987 /* get base addr */
2988 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
86a74ff2
NI		 2989
2990 ndev = alloc_etherdev(sizeof(struct sh_eth_private));
f738a13d
LP		 2991 if (!ndev)
2992 return -ENOMEM;
86a74ff2 2993
b5893a08
BD		 2994 pm_runtime_enable(&pdev->dev);
2995 pm_runtime_get_sync(&pdev->dev);
2996
86a74ff2
NI		 2997 devno = pdev->id;
2998 if (devno < 0)
2999 devno = 0;
3000
cc3c080d 3001 ret = platform_get_irq(pdev, 0);
7a468ac6 3002 if (ret < 0)
86a74ff2 3003 goto out_release;
cc3c080d 3004 ndev->irq = ret;
86a74ff2
NI		 3005
3006 SET_NETDEV_DEV(ndev, &pdev->dev);
3007
86a74ff2 3008 mdp = netdev_priv(ndev);
525b8075
YS		 3009 mdp->num_tx_ring = TX_RING_SIZE;
3010 mdp->num_rx_ring = RX_RING_SIZE;
d5e07e69
SS		 3011 mdp->addr = devm_ioremap_resource(&pdev->dev, res);
3012 if (IS_ERR(mdp->addr)) {
3013 ret = PTR_ERR(mdp->addr);
ae70644d
YS		 3014 goto out_release;
3015 }
3016
c960804f
VB		 3017 ndev->base_addr = res->start;
3018
86a74ff2 3019 spin_lock_init(&mdp->lock);
bcd5149d 3020 mdp->pdev = pdev;
86a74ff2 3021
b356e978
SS		 3022 if (pdev->dev.of_node)
3023 pd = sh_eth_parse_dt(&pdev->dev);
3b4c5cbf
SS		 3024 if (!pd) {
3025 dev_err(&pdev->dev, "no platform data\n");
3026 ret = -EINVAL;
3027 goto out_release;
3028 }
3029
86a74ff2 3030 /* get PHY ID */
71557a37 3031 mdp->phy_id = pd->phy;
e47c9052 3032 mdp->phy_interface = pd->phy_interface;
4923576b
YS		 3033 mdp->no_ether_link = pd->no_ether_link;
3034 mdp->ether_link_active_low = pd->ether_link_active_low;
86a74ff2 3035
380af9e3 3036 /* set cpu data */
42a67c9b 3037 if (id)
b356e978 3038 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data;
42a67c9b
WS		 3039 else
3040 mdp->cd = (struct sh_eth_cpu_data *)of_device_get_match_data(&pdev->dev);
b356e978 3041
a3153d8c 3042 mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type);
264be2f5
SS		 3043 if (!mdp->reg_offset) {
3044 dev_err(&pdev->dev, "Unknown register type (%d)\n",
3045 mdp->cd->register_type);
3046 ret = -EINVAL;
3047 goto out_release;
3048 }
380af9e3
YS		 3049 sh_eth_set_default_cpu_data(mdp->cd);
3050
86a74ff2 3051 /* set function */
8f728d79
SS		 3052 if (mdp->cd->tsu)
3053 ndev->netdev_ops = &sh_eth_netdev_ops_tsu;
3054 else
3055 ndev->netdev_ops = &sh_eth_netdev_ops;
7ad24ea4 3056 ndev->ethtool_ops = &sh_eth_ethtool_ops;
86a74ff2
NI		 3057 ndev->watchdog_timeo = TX_TIMEOUT;
3058
dc19e4e5
NI		 3059 /* debug message level */
3060 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
86a74ff2
NI		 3061
3062 /* read and set MAC address */
748031f9 3063 read_mac_address(ndev, pd->mac_addr);
ff6e7228
SS		 3064 if (!is_valid_ether_addr(ndev->dev_addr)) {
3065 dev_warn(&pdev->dev,
3066 "no valid MAC address supplied, using a random one.\n");
3067 eth_hw_addr_random(ndev);
3068 }
86a74ff2 3069
6ba88021
YS		 3070 /* ioremap the TSU registers */
3071 if (mdp->cd->tsu) {
3072 struct resource *rtsu;
3073 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
d5e07e69
SS		 3074 mdp->tsu_addr = devm_ioremap_resource(&pdev->dev, rtsu);
3075 if (IS_ERR(mdp->tsu_addr)) {
3076 ret = PTR_ERR(mdp->tsu_addr);
fc0c0900
SS		 3077 goto out_release;
3078 }
6743fe6d 3079 mdp->port = devno % 2;
f646968f 3080 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER;
6ba88021
YS		 3081 }
3082
150647fb
YS		 3083 /* initialize first or needed device */
3084 if (!devno || pd->needs_init) {
380af9e3
YS		 3085 if (mdp->cd->chip_reset)
3086 mdp->cd->chip_reset(ndev);
86a74ff2 3087
4986b996
YS		 3088 if (mdp->cd->tsu) {
3089 /* TSU init (Init only)*/
3090 sh_eth_tsu_init(mdp);
3091 }
86a74ff2
NI		 3092 }
3093
966d6dbb
HN		 3094 if (mdp->cd->rmiimode)
3095 sh_eth_write(ndev, 0x1, RMIIMODE);
3096
daacf03f
LP		 3097 /* MDIO bus init */
3098 ret = sh_mdio_init(mdp, pd);
3099 if (ret) {
3100 dev_err(&ndev->dev, "failed to initialise MDIO\n");
3101 goto out_release;
3102 }
3103
3719109d
SS		 3104 netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64);
3105
86a74ff2
NI		 3106 /* network device register */
3107 ret = register_netdev(ndev);
3108 if (ret)
3719109d 3109 goto out_napi_del;
86a74ff2 3110
25985edc 3111 /* print device information */
f75f14ec
SS		 3112 netdev_info(ndev, "Base address at 0x%x, %pM, IRQ %d.\n",
3113 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
86a74ff2 3114
b5893a08 3115 pm_runtime_put(&pdev->dev);
86a74ff2
NI		 3116 platform_set_drvdata(pdev, ndev);
3117
3118 return ret;
3119
3719109d
SS		 3120out_napi_del:
3121 netif_napi_del(&mdp->napi);
daacf03f 3122 sh_mdio_release(mdp);
3719109d 3123
86a74ff2
NI		 3124out_release:
3125 /* net_dev free */
3126 if (ndev)
3127 free_netdev(ndev);
3128
b5893a08
BD		 3129 pm_runtime_put(&pdev->dev);
3130 pm_runtime_disable(&pdev->dev);
86a74ff2
NI		 3131 return ret;
3132}
3133
3134static int sh_eth_drv_remove(struct platform_device *pdev)
3135{
3136 struct net_device *ndev = platform_get_drvdata(pdev);
3719109d 3137 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2 3138
86a74ff2 3139 unregister_netdev(ndev);
3719109d 3140 netif_napi_del(&mdp->napi);
daacf03f 3141 sh_mdio_release(mdp);
bcd5149d 3142 pm_runtime_disable(&pdev->dev);
86a74ff2 3143 free_netdev(ndev);
86a74ff2
NI		 3144
3145 return 0;
3146}
3147
540ad1b8 3148#ifdef CONFIG_PM
b71af046
MU		 3149#ifdef CONFIG_PM_SLEEP
3150static int sh_eth_suspend(struct device *dev)
3151{
3152 struct net_device *ndev = dev_get_drvdata(dev);
3153 int ret = 0;
3154
3155 if (netif_running(ndev)) {
3156 netif_device_detach(ndev);
3157 ret = sh_eth_close(ndev);
3158 }
3159
3160 return ret;
3161}
3162
3163static int sh_eth_resume(struct device *dev)
3164{
3165 struct net_device *ndev = dev_get_drvdata(dev);
3166 int ret = 0;
3167
3168 if (netif_running(ndev)) {
3169 ret = sh_eth_open(ndev);
3170 if (ret < 0)
3171 return ret;
3172 netif_device_attach(ndev);
3173 }
3174
3175 return ret;
3176}
3177#endif
3178
bcd5149d
MD		 3179static int sh_eth_runtime_nop(struct device *dev)
3180{
128296fc 3181 /* Runtime PM callback shared between ->runtime_suspend()
bcd5149d
MD		 3182 * and ->runtime_resume(). Simply returns success.
3183 *
3184 * This driver re-initializes all registers after
3185 * pm_runtime_get_sync() anyway so there is no need
3186 * to save and restore registers here.
3187 */
3188 return 0;
3189}
3190
540ad1b8 3191static const struct dev_pm_ops sh_eth_dev_pm_ops = {
b71af046 3192 SET_SYSTEM_SLEEP_PM_OPS(sh_eth_suspend, sh_eth_resume)
e7d7e898 3193 SET_RUNTIME_PM_OPS(sh_eth_runtime_nop, sh_eth_runtime_nop, NULL)
bcd5149d 3194};
540ad1b8
NI		 3195#define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
3196#else
3197#define SH_ETH_PM_OPS NULL
3198#endif
bcd5149d 3199
afe391ad 3200static struct platform_device_id sh_eth_id_table[] = {
c18a79ab 3201 { "sh7619-ether", (kernel_ulong_t)&sh7619_data },
7bbe150d 3202 { "sh771x-ether", (kernel_ulong_t)&sh771x_data },
9c3beaab 3203 { "sh7724-ether", (kernel_ulong_t)&sh7724_data },
f5d12767 3204 { "sh7734-gether", (kernel_ulong_t)&sh7734_data },
24549e2a
SS		 3205 { "sh7757-ether", (kernel_ulong_t)&sh7757_data },
3206 { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga },
f5d12767 3207 { "sh7763-gether", (kernel_ulong_t)&sh7763_data },
afe391ad
SS		 3208 { }
3209};
3210MODULE_DEVICE_TABLE(platform, sh_eth_id_table);
3211
86a74ff2
NI		 3212static struct platform_driver sh_eth_driver = {
3213 .probe = sh_eth_drv_probe,
3214 .remove = sh_eth_drv_remove,
afe391ad 3215 .id_table = sh_eth_id_table,
86a74ff2
NI		 3216 .driver = {
3217 .name = CARDNAME,
540ad1b8 3218 .pm = SH_ETH_PM_OPS,
b356e978 3219 .of_match_table = of_match_ptr(sh_eth_match_table),
86a74ff2
NI		 3220 },
3221};
3222
db62f684 3223module_platform_driver(sh_eth_driver);
86a74ff2
NI		 3224
3225MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
3226MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
3227MODULE_LICENSE("GPL v2");
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