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sh_eth: remove mask fields from 'struct bb_info'
[mirror_ubuntu-zesty-kernel.git] / drivers / net / ethernet / renesas / sh_eth.c
CommitLineData
128296fc 1/* SuperH Ethernet device driver
86a74ff2 2 *
966d6dbb 3 * Copyright (C) 2014 Renesas Electronics Corporation
f0e81fec 4 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu
b356e978
SS		 5 * Copyright (C) 2008-2014 Renesas Solutions Corp.
6 * Copyright (C) 2013-2014 Cogent Embedded, Inc.
702eca02 7 * Copyright (C) 2014 Codethink Limited
86a74ff2
NI		 8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms and conditions of the GNU General Public License,
11 * version 2, as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
86a74ff2
NI		 17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 */
21
0654011d
YS		 22#include <linux/module.h>
23#include <linux/kernel.h>
24#include <linux/spinlock.h>
6a27cded 25#include <linux/interrupt.h>
86a74ff2
NI		 26#include <linux/dma-mapping.h>
27#include <linux/etherdevice.h>
28#include <linux/delay.h>
29#include <linux/platform_device.h>
30#include <linux/mdio-bitbang.h>
31#include <linux/netdevice.h>
b356e978
SS		 32#include <linux/of.h>
33#include <linux/of_device.h>
34#include <linux/of_irq.h>
35#include <linux/of_net.h>
86a74ff2
NI		 36#include <linux/phy.h>
37#include <linux/cache.h>
38#include <linux/io.h>
bcd5149d 39#include <linux/pm_runtime.h>
5a0e3ad6 40#include <linux/slab.h>
dc19e4e5 41#include <linux/ethtool.h>
fdb37a7f 42#include <linux/if_vlan.h>
f0e81fec 43#include <linux/clk.h>
d4fa0e35 44#include <linux/sh_eth.h>
702eca02 45#include <linux/of_mdio.h>
86a74ff2
NI		 46
47#include "sh_eth.h"
48
dc19e4e5
NI		 49#define SH_ETH_DEF_MSG_ENABLE \
50 (NETIF_MSG_LINK | \
51 NETIF_MSG_TIMER | \
52 NETIF_MSG_RX_ERR| \
53 NETIF_MSG_TX_ERR)
54
3365711d
BH		 55#define SH_ETH_OFFSET_DEFAULTS \
56 [0 ... SH_ETH_MAX_REGISTER_OFFSET - 1] = SH_ETH_OFFSET_INVALID
57
c0013f6f 58static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
3365711d
BH		 59 SH_ETH_OFFSET_DEFAULTS,
60
c0013f6f
SS		 61 [EDSR] = 0x0000,
62 [EDMR] = 0x0400,
63 [EDTRR] = 0x0408,
64 [EDRRR] = 0x0410,
65 [EESR] = 0x0428,
66 [EESIPR] = 0x0430,
67 [TDLAR] = 0x0010,
68 [TDFAR] = 0x0014,
69 [TDFXR] = 0x0018,
70 [TDFFR] = 0x001c,
71 [RDLAR] = 0x0030,
72 [RDFAR] = 0x0034,
73 [RDFXR] = 0x0038,
74 [RDFFR] = 0x003c,
75 [TRSCER] = 0x0438,
76 [RMFCR] = 0x0440,
77 [TFTR] = 0x0448,
78 [FDR] = 0x0450,
79 [RMCR] = 0x0458,
80 [RPADIR] = 0x0460,
81 [FCFTR] = 0x0468,
82 [CSMR] = 0x04E4,
83
84 [ECMR] = 0x0500,
85 [ECSR] = 0x0510,
86 [ECSIPR] = 0x0518,
87 [PIR] = 0x0520,
88 [PSR] = 0x0528,
89 [PIPR] = 0x052c,
90 [RFLR] = 0x0508,
91 [APR] = 0x0554,
92 [MPR] = 0x0558,
93 [PFTCR] = 0x055c,
94 [PFRCR] = 0x0560,
95 [TPAUSER] = 0x0564,
96 [GECMR] = 0x05b0,
97 [BCULR] = 0x05b4,
98 [MAHR] = 0x05c0,
99 [MALR] = 0x05c8,
100 [TROCR] = 0x0700,
101 [CDCR] = 0x0708,
102 [LCCR] = 0x0710,
103 [CEFCR] = 0x0740,
104 [FRECR] = 0x0748,
105 [TSFRCR] = 0x0750,
106 [TLFRCR] = 0x0758,
107 [RFCR] = 0x0760,
108 [CERCR] = 0x0768,
109 [CEECR] = 0x0770,
110 [MAFCR] = 0x0778,
111 [RMII_MII] = 0x0790,
112
113 [ARSTR] = 0x0000,
114 [TSU_CTRST] = 0x0004,
115 [TSU_FWEN0] = 0x0010,
116 [TSU_FWEN1] = 0x0014,
117 [TSU_FCM] = 0x0018,
118 [TSU_BSYSL0] = 0x0020,
119 [TSU_BSYSL1] = 0x0024,
120 [TSU_PRISL0] = 0x0028,
121 [TSU_PRISL1] = 0x002c,
122 [TSU_FWSL0] = 0x0030,
123 [TSU_FWSL1] = 0x0034,
124 [TSU_FWSLC] = 0x0038,
125 [TSU_QTAG0] = 0x0040,
126 [TSU_QTAG1] = 0x0044,
127 [TSU_FWSR] = 0x0050,
128 [TSU_FWINMK] = 0x0054,
129 [TSU_ADQT0] = 0x0048,
130 [TSU_ADQT1] = 0x004c,
131 [TSU_VTAG0] = 0x0058,
132 [TSU_VTAG1] = 0x005c,
133 [TSU_ADSBSY] = 0x0060,
134 [TSU_TEN] = 0x0064,
135 [TSU_POST1] = 0x0070,
136 [TSU_POST2] = 0x0074,
137 [TSU_POST3] = 0x0078,
138 [TSU_POST4] = 0x007c,
139 [TSU_ADRH0] = 0x0100,
c0013f6f
SS		 140
141 [TXNLCR0] = 0x0080,
142 [TXALCR0] = 0x0084,
143 [RXNLCR0] = 0x0088,
144 [RXALCR0] = 0x008c,
145 [FWNLCR0] = 0x0090,
146 [FWALCR0] = 0x0094,
147 [TXNLCR1] = 0x00a0,
148 [TXALCR1] = 0x00a0,
149 [RXNLCR1] = 0x00a8,
150 [RXALCR1] = 0x00ac,
151 [FWNLCR1] = 0x00b0,
152 [FWALCR1] = 0x00b4,
153};
154
db893473 155static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
3365711d
BH		 156 SH_ETH_OFFSET_DEFAULTS,
157
db893473
SH		 158 [EDSR] = 0x0000,
159 [EDMR] = 0x0400,
160 [EDTRR] = 0x0408,
161 [EDRRR] = 0x0410,
162 [EESR] = 0x0428,
163 [EESIPR] = 0x0430,
164 [TDLAR] = 0x0010,
165 [TDFAR] = 0x0014,
166 [TDFXR] = 0x0018,
167 [TDFFR] = 0x001c,
168 [RDLAR] = 0x0030,
169 [RDFAR] = 0x0034,
170 [RDFXR] = 0x0038,
171 [RDFFR] = 0x003c,
172 [TRSCER] = 0x0438,
173 [RMFCR] = 0x0440,
174 [TFTR] = 0x0448,
175 [FDR] = 0x0450,
176 [RMCR] = 0x0458,
177 [RPADIR] = 0x0460,
178 [FCFTR] = 0x0468,
179 [CSMR] = 0x04E4,
180
181 [ECMR] = 0x0500,
182 [RFLR] = 0x0508,
183 [ECSR] = 0x0510,
184 [ECSIPR] = 0x0518,
185 [PIR] = 0x0520,
186 [APR] = 0x0554,
187 [MPR] = 0x0558,
188 [PFTCR] = 0x055c,
189 [PFRCR] = 0x0560,
190 [TPAUSER] = 0x0564,
191 [MAHR] = 0x05c0,
192 [MALR] = 0x05c8,
193 [CEFCR] = 0x0740,
194 [FRECR] = 0x0748,
195 [TSFRCR] = 0x0750,
196 [TLFRCR] = 0x0758,
197 [RFCR] = 0x0760,
198 [MAFCR] = 0x0778,
199
200 [ARSTR] = 0x0000,
201 [TSU_CTRST] = 0x0004,
202 [TSU_VTAG0] = 0x0058,
203 [TSU_ADSBSY] = 0x0060,
204 [TSU_TEN] = 0x0064,
205 [TSU_ADRH0] = 0x0100,
db893473
SH		 206
207 [TXNLCR0] = 0x0080,
208 [TXALCR0] = 0x0084,
209 [RXNLCR0] = 0x0088,
210 [RXALCR0] = 0x008C,
211};
212
a3f109bd 213static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
3365711d
BH		 214 SH_ETH_OFFSET_DEFAULTS,
215
a3f109bd
SS		 216 [ECMR] = 0x0300,
217 [RFLR] = 0x0308,
218 [ECSR] = 0x0310,
219 [ECSIPR] = 0x0318,
220 [PIR] = 0x0320,
221 [PSR] = 0x0328,
222 [RDMLR] = 0x0340,
223 [IPGR] = 0x0350,
224 [APR] = 0x0354,
225 [MPR] = 0x0358,
226 [RFCF] = 0x0360,
227 [TPAUSER] = 0x0364,
228 [TPAUSECR] = 0x0368,
229 [MAHR] = 0x03c0,
230 [MALR] = 0x03c8,
231 [TROCR] = 0x03d0,
232 [CDCR] = 0x03d4,
233 [LCCR] = 0x03d8,
234 [CNDCR] = 0x03dc,
235 [CEFCR] = 0x03e4,
236 [FRECR] = 0x03e8,
237 [TSFRCR] = 0x03ec,
238 [TLFRCR] = 0x03f0,
239 [RFCR] = 0x03f4,
240 [MAFCR] = 0x03f8,
241
242 [EDMR] = 0x0200,
243 [EDTRR] = 0x0208,
244 [EDRRR] = 0x0210,
245 [TDLAR] = 0x0218,
246 [RDLAR] = 0x0220,
247 [EESR] = 0x0228,
248 [EESIPR] = 0x0230,
249 [TRSCER] = 0x0238,
250 [RMFCR] = 0x0240,
251 [TFTR] = 0x0248,
252 [FDR] = 0x0250,
253 [RMCR] = 0x0258,
254 [TFUCR] = 0x0264,
255 [RFOCR] = 0x0268,
55754f19 256 [RMIIMODE] = 0x026c,
a3f109bd
SS		 257 [FCFTR] = 0x0270,
258 [TRIMD] = 0x027c,
259};
260
c0013f6f 261static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
3365711d
BH		 262 SH_ETH_OFFSET_DEFAULTS,
263
c0013f6f
SS		 264 [ECMR] = 0x0100,
265 [RFLR] = 0x0108,
266 [ECSR] = 0x0110,
267 [ECSIPR] = 0x0118,
268 [PIR] = 0x0120,
269 [PSR] = 0x0128,
270 [RDMLR] = 0x0140,
271 [IPGR] = 0x0150,
272 [APR] = 0x0154,
273 [MPR] = 0x0158,
274 [TPAUSER] = 0x0164,
275 [RFCF] = 0x0160,
276 [TPAUSECR] = 0x0168,
277 [BCFRR] = 0x016c,
278 [MAHR] = 0x01c0,
279 [MALR] = 0x01c8,
280 [TROCR] = 0x01d0,
281 [CDCR] = 0x01d4,
282 [LCCR] = 0x01d8,
283 [CNDCR] = 0x01dc,
284 [CEFCR] = 0x01e4,
285 [FRECR] = 0x01e8,
286 [TSFRCR] = 0x01ec,
287 [TLFRCR] = 0x01f0,
288 [RFCR] = 0x01f4,
289 [MAFCR] = 0x01f8,
290 [RTRATE] = 0x01fc,
291
292 [EDMR] = 0x0000,
293 [EDTRR] = 0x0008,
294 [EDRRR] = 0x0010,
295 [TDLAR] = 0x0018,
296 [RDLAR] = 0x0020,
297 [EESR] = 0x0028,
298 [EESIPR] = 0x0030,
299 [TRSCER] = 0x0038,
300 [RMFCR] = 0x0040,
301 [TFTR] = 0x0048,
302 [FDR] = 0x0050,
303 [RMCR] = 0x0058,
304 [TFUCR] = 0x0064,
305 [RFOCR] = 0x0068,
306 [FCFTR] = 0x0070,
307 [RPADIR] = 0x0078,
308 [TRIMD] = 0x007c,
309 [RBWAR] = 0x00c8,
310 [RDFAR] = 0x00cc,
311 [TBRAR] = 0x00d4,
312 [TDFAR] = 0x00d8,
313};
314
315static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
3365711d
BH		 316 SH_ETH_OFFSET_DEFAULTS,
317
d8b0426a
SS		 318 [EDMR] = 0x0000,
319 [EDTRR] = 0x0004,
320 [EDRRR] = 0x0008,
321 [TDLAR] = 0x000c,
322 [RDLAR] = 0x0010,
323 [EESR] = 0x0014,
324 [EESIPR] = 0x0018,
325 [TRSCER] = 0x001c,
326 [RMFCR] = 0x0020,
327 [TFTR] = 0x0024,
328 [FDR] = 0x0028,
329 [RMCR] = 0x002c,
330 [EDOCR] = 0x0030,
331 [FCFTR] = 0x0034,
332 [RPADIR] = 0x0038,
333 [TRIMD] = 0x003c,
334 [RBWAR] = 0x0040,
335 [RDFAR] = 0x0044,
336 [TBRAR] = 0x004c,
337 [TDFAR] = 0x0050,
338
c0013f6f
SS		 339 [ECMR] = 0x0160,
340 [ECSR] = 0x0164,
341 [ECSIPR] = 0x0168,
342 [PIR] = 0x016c,
343 [MAHR] = 0x0170,
344 [MALR] = 0x0174,
345 [RFLR] = 0x0178,
346 [PSR] = 0x017c,
347 [TROCR] = 0x0180,
348 [CDCR] = 0x0184,
349 [LCCR] = 0x0188,
350 [CNDCR] = 0x018c,
351 [CEFCR] = 0x0194,
352 [FRECR] = 0x0198,
353 [TSFRCR] = 0x019c,
354 [TLFRCR] = 0x01a0,
355 [RFCR] = 0x01a4,
356 [MAFCR] = 0x01a8,
357 [IPGR] = 0x01b4,
358 [APR] = 0x01b8,
359 [MPR] = 0x01bc,
360 [TPAUSER] = 0x01c4,
361 [BCFR] = 0x01cc,
362
363 [ARSTR] = 0x0000,
364 [TSU_CTRST] = 0x0004,
365 [TSU_FWEN0] = 0x0010,
366 [TSU_FWEN1] = 0x0014,
367 [TSU_FCM] = 0x0018,
368 [TSU_BSYSL0] = 0x0020,
369 [TSU_BSYSL1] = 0x0024,
370 [TSU_PRISL0] = 0x0028,
371 [TSU_PRISL1] = 0x002c,
372 [TSU_FWSL0] = 0x0030,
373 [TSU_FWSL1] = 0x0034,
374 [TSU_FWSLC] = 0x0038,
375 [TSU_QTAGM0] = 0x0040,
376 [TSU_QTAGM1] = 0x0044,
377 [TSU_ADQT0] = 0x0048,
378 [TSU_ADQT1] = 0x004c,
379 [TSU_FWSR] = 0x0050,
380 [TSU_FWINMK] = 0x0054,
381 [TSU_ADSBSY] = 0x0060,
382 [TSU_TEN] = 0x0064,
383 [TSU_POST1] = 0x0070,
384 [TSU_POST2] = 0x0074,
385 [TSU_POST3] = 0x0078,
386 [TSU_POST4] = 0x007c,
387
388 [TXNLCR0] = 0x0080,
389 [TXALCR0] = 0x0084,
390 [RXNLCR0] = 0x0088,
391 [RXALCR0] = 0x008c,
392 [FWNLCR0] = 0x0090,
393 [FWALCR0] = 0x0094,
394 [TXNLCR1] = 0x00a0,
395 [TXALCR1] = 0x00a0,
396 [RXNLCR1] = 0x00a8,
397 [RXALCR1] = 0x00ac,
398 [FWNLCR1] = 0x00b0,
399 [FWALCR1] = 0x00b4,
400
401 [TSU_ADRH0] = 0x0100,
c0013f6f
SS		 402};
403
740c7f31
BH		 404static void sh_eth_rcv_snd_disable(struct net_device *ndev);
405static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev);
406
504c8ca5 407static bool sh_eth_is_gether(struct sh_eth_private *mdp)
dabdde9e 408{
504c8ca5 409 return mdp->reg_offset == sh_eth_offset_gigabit;
dabdde9e
NI		 410}
411
db893473
SH		 412static bool sh_eth_is_rz_fast_ether(struct sh_eth_private *mdp)
413{
414 return mdp->reg_offset == sh_eth_offset_fast_rz;
415}
416
8e994402 417static void sh_eth_select_mii(struct net_device *ndev)
5e7a76be
NI		 418{
419 u32 value = 0x0;
420 struct sh_eth_private *mdp = netdev_priv(ndev);
421
422 switch (mdp->phy_interface) {
423 case PHY_INTERFACE_MODE_GMII:
424 value = 0x2;
425 break;
426 case PHY_INTERFACE_MODE_MII:
427 value = 0x1;
428 break;
429 case PHY_INTERFACE_MODE_RMII:
430 value = 0x0;
431 break;
432 default:
f75f14ec
SS		 433 netdev_warn(ndev,
434 "PHY interface mode was not setup. Set to MII.\n");
5e7a76be
NI		 435 value = 0x1;
436 break;
437 }
438
439 sh_eth_write(ndev, value, RMII_MII);
440}
5e7a76be 441
8e994402 442static void sh_eth_set_duplex(struct net_device *ndev)
65ac8851
YS		 443{
444 struct sh_eth_private *mdp = netdev_priv(ndev);
65ac8851
YS		 445
446 if (mdp->duplex) /* Full */
4a55530f 447 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
65ac8851 448 else /* Half */
4a55530f 449 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
65ac8851
YS		 450}
451
99f84be6
GU		 452static void sh_eth_chip_reset(struct net_device *ndev)
453{
454 struct sh_eth_private *mdp = netdev_priv(ndev);
455
456 /* reset device */
457 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
458 mdelay(1);
459}
460
a0f48be3
GU		 461static void sh_eth_set_rate_gether(struct net_device *ndev)
462{
463 struct sh_eth_private *mdp = netdev_priv(ndev);
464
465 switch (mdp->speed) {
466 case 10: /* 10BASE */
467 sh_eth_write(ndev, GECMR_10, GECMR);
468 break;
469 case 100:/* 100BASE */
470 sh_eth_write(ndev, GECMR_100, GECMR);
471 break;
472 case 1000: /* 1000BASE */
473 sh_eth_write(ndev, GECMR_1000, GECMR);
474 break;
475 default:
476 break;
477 }
478}
479
99f84be6
GU		 480#ifdef CONFIG_OF
481/* R7S72100 */
482static struct sh_eth_cpu_data r7s72100_data = {
483 .chip_reset = sh_eth_chip_reset,
484 .set_duplex = sh_eth_set_duplex,
485
486 .register_type = SH_ETH_REG_FAST_RZ,
487
488 .ecsr_value = ECSR_ICD,
489 .ecsipr_value = ECSIPR_ICDIP,
490 .eesipr_value = 0xff7f009f,
491
492 .tx_check = EESR_TC1 | EESR_FTC,
493 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
494 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
495 EESR_TDE | EESR_ECI,
496 .fdr_value = 0x0000070f,
497
498 .no_psr = 1,
499 .apr = 1,
500 .mpr = 1,
501 .tpauser = 1,
502 .hw_swap = 1,
503 .rpadir = 1,
504 .rpadir_value = 2 << 16,
505 .no_trimd = 1,
506 .no_ade = 1,
507 .hw_crc = 1,
508 .tsu = 1,
509 .shift_rd0 = 1,
510};
a0f48be3
GU		 511
512static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
513{
514 struct sh_eth_private *mdp = netdev_priv(ndev);
515
516 /* reset device */
517 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
518 mdelay(1);
519
520 sh_eth_select_mii(ndev);
521}
522
523/* R8A7740 */
524static struct sh_eth_cpu_data r8a7740_data = {
525 .chip_reset = sh_eth_chip_reset_r8a7740,
526 .set_duplex = sh_eth_set_duplex,
527 .set_rate = sh_eth_set_rate_gether,
528
529 .register_type = SH_ETH_REG_GIGABIT,
530
531 .ecsr_value = ECSR_ICD | ECSR_MPD,
532 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
533 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
534
535 .tx_check = EESR_TC1 | EESR_FTC,
536 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
537 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
538 EESR_TDE | EESR_ECI,
539 .fdr_value = 0x0000070f,
540
541 .apr = 1,
542 .mpr = 1,
543 .tpauser = 1,
544 .bculr = 1,
545 .hw_swap = 1,
546 .rpadir = 1,
547 .rpadir_value = 2 << 16,
548 .no_trimd = 1,
549 .no_ade = 1,
550 .tsu = 1,
551 .select_mii = 1,
552 .shift_rd0 = 1,
553};
99f84be6 554
04b0ed2a 555/* There is CPU dependent code */
589ebdef 556static void sh_eth_set_rate_r8a777x(struct net_device *ndev)
65ac8851
YS		 557{
558 struct sh_eth_private *mdp = netdev_priv(ndev);
d0418bb7 559
a3f109bd
SS		 560 switch (mdp->speed) {
561 case 10: /* 10BASE */
562 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_ELB, ECMR);
563 break;
564 case 100:/* 100BASE */
565 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_ELB, ECMR);
566 break;
567 default:
568 break;
569 }
570}
571
674853b2 572/* R8A7778/9 */
589ebdef 573static struct sh_eth_cpu_data r8a777x_data = {
a3f109bd 574 .set_duplex = sh_eth_set_duplex,
589ebdef 575 .set_rate = sh_eth_set_rate_r8a777x,
a3f109bd 576
a3153d8c
SS		 577 .register_type = SH_ETH_REG_FAST_RCAR,
578
a3f109bd
SS		 579 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
580 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
581 .eesipr_value = 0x01ff009f,
582
583 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
ca8c3585
SS		 584 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
585 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
586 EESR_ECI,
d407bc02 587 .fdr_value = 0x00000f0f,
a3f109bd
SS		 588
589 .apr = 1,
590 .mpr = 1,
591 .tpauser = 1,
592 .hw_swap = 1,
593};
a3f109bd 594
94a12b15
SS		 595/* R8A7790/1 */
596static struct sh_eth_cpu_data r8a779x_data = {
e18dbf7e
SH		 597 .set_duplex = sh_eth_set_duplex,
598 .set_rate = sh_eth_set_rate_r8a777x,
599
a3153d8c
SS		 600 .register_type = SH_ETH_REG_FAST_RCAR,
601
e18dbf7e
SH		 602 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
603 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
604 .eesipr_value = 0x01ff009f,
605
606 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
ba361cb3
LP		 607 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
608 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
609 EESR_ECI,
d407bc02 610 .fdr_value = 0x00000f0f,
e18dbf7e 611
01fbd3f5
GU		 612 .trscer_err_mask = DESC_I_RINT8,
613
e18dbf7e
SH		 614 .apr = 1,
615 .mpr = 1,
616 .tpauser = 1,
617 .hw_swap = 1,
618 .rmiimode = 1,
619};
c74a2248 620#endif /* CONFIG_OF */
e18dbf7e 621
9c3beaab 622static void sh_eth_set_rate_sh7724(struct net_device *ndev)
a3f109bd
SS		 623{
624 struct sh_eth_private *mdp = netdev_priv(ndev);
65ac8851
YS		 625
626 switch (mdp->speed) {
627 case 10: /* 10BASE */
a3f109bd 628 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_RTM, ECMR);
65ac8851
YS		 629 break;
630 case 100:/* 100BASE */
a3f109bd 631 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_RTM, ECMR);
65ac8851
YS		 632 break;
633 default:
634 break;
635 }
636}
637
638/* SH7724 */
9c3beaab 639static struct sh_eth_cpu_data sh7724_data = {
65ac8851 640 .set_duplex = sh_eth_set_duplex,
9c3beaab 641 .set_rate = sh_eth_set_rate_sh7724,
65ac8851 642
a3153d8c
SS		 643 .register_type = SH_ETH_REG_FAST_SH4,
644
65ac8851
YS		 645 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
646 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
a80c3de7 647 .eesipr_value = 0x01ff009f,
65ac8851
YS		 648
649 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
ca8c3585
SS		 650 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
651 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
652 EESR_ECI,
65ac8851
YS		 653
654 .apr = 1,
655 .mpr = 1,
656 .tpauser = 1,
657 .hw_swap = 1,
503914cf
MD		 658 .rpadir = 1,
659 .rpadir_value = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
65ac8851 660};
5cee1d37 661
24549e2a 662static void sh_eth_set_rate_sh7757(struct net_device *ndev)
f29a3d04
YS		 663{
664 struct sh_eth_private *mdp = netdev_priv(ndev);
f29a3d04
YS		 665
666 switch (mdp->speed) {
667 case 10: /* 10BASE */
4a55530f 668 sh_eth_write(ndev, 0, RTRATE);
f29a3d04
YS		 669 break;
670 case 100:/* 100BASE */
4a55530f 671 sh_eth_write(ndev, 1, RTRATE);
f29a3d04
YS		 672 break;
673 default:
674 break;
675 }
676}
677
678/* SH7757 */
24549e2a
SS		 679static struct sh_eth_cpu_data sh7757_data = {
680 .set_duplex = sh_eth_set_duplex,
681 .set_rate = sh_eth_set_rate_sh7757,
f29a3d04 682
a3153d8c
SS		 683 .register_type = SH_ETH_REG_FAST_SH4,
684
f29a3d04 685 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
f29a3d04
YS		 686
687 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
ca8c3585
SS		 688 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
689 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
690 EESR_ECI,
f29a3d04 691
5b3dfd13 692 .irq_flags = IRQF_SHARED,
f29a3d04
YS		 693 .apr = 1,
694 .mpr = 1,
695 .tpauser = 1,
696 .hw_swap = 1,
697 .no_ade = 1,
2e98e797
YS		 698 .rpadir = 1,
699 .rpadir_value = 2 << 16,
6b4b4fea 700 .rtrate = 1,
f29a3d04 701};
65ac8851 702
e403d295 703#define SH_GIGA_ETH_BASE 0xfee00000UL
8fcd4961
YS		 704#define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
705#define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
706static void sh_eth_chip_reset_giga(struct net_device *ndev)
707{
708 int i;
0799c2d6 709 u32 mahr[2], malr[2];
8fcd4961
YS		 710
711 /* save MAHR and MALR */
712 for (i = 0; i < 2; i++) {
ae70644d
YS		 713 malr[i] = ioread32((void *)GIGA_MALR(i));
714 mahr[i] = ioread32((void *)GIGA_MAHR(i));
8fcd4961
YS		 715 }
716
717 /* reset device */
ae70644d 718 iowrite32(ARSTR_ARSTR, (void *)(SH_GIGA_ETH_BASE + 0x1800));
8fcd4961
YS		 719 mdelay(1);
720
721 /* restore MAHR and MALR */
722 for (i = 0; i < 2; i++) {
ae70644d
YS		 723 iowrite32(malr[i], (void *)GIGA_MALR(i));
724 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
8fcd4961
YS		 725 }
726}
727
8fcd4961
YS		 728static void sh_eth_set_rate_giga(struct net_device *ndev)
729{
730 struct sh_eth_private *mdp = netdev_priv(ndev);
731
732 switch (mdp->speed) {
733 case 10: /* 10BASE */
734 sh_eth_write(ndev, 0x00000000, GECMR);
735 break;
736 case 100:/* 100BASE */
737 sh_eth_write(ndev, 0x00000010, GECMR);
738 break;
739 case 1000: /* 1000BASE */
740 sh_eth_write(ndev, 0x00000020, GECMR);
741 break;
742 default:
743 break;
744 }
745}
746
747/* SH7757(GETHERC) */
24549e2a 748static struct sh_eth_cpu_data sh7757_data_giga = {
8fcd4961 749 .chip_reset = sh_eth_chip_reset_giga,
04b0ed2a 750 .set_duplex = sh_eth_set_duplex,
8fcd4961
YS		 751 .set_rate = sh_eth_set_rate_giga,
752
a3153d8c
SS		 753 .register_type = SH_ETH_REG_GIGABIT,
754
8fcd4961
YS		 755 .ecsr_value = ECSR_ICD | ECSR_MPD,
756 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
757 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
758
759 .tx_check = EESR_TC1 | EESR_FTC,
ca8c3585
SS		 760 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
761 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
762 EESR_TDE | EESR_ECI,
8fcd4961 763 .fdr_value = 0x0000072f,
8fcd4961 764
5b3dfd13 765 .irq_flags = IRQF_SHARED,
8fcd4961
YS		 766 .apr = 1,
767 .mpr = 1,
768 .tpauser = 1,
769 .bculr = 1,
770 .hw_swap = 1,
771 .rpadir = 1,
772 .rpadir_value = 2 << 16,
773 .no_trimd = 1,
774 .no_ade = 1,
3acbc971 775 .tsu = 1,
8fcd4961
YS		 776};
777
f5d12767
SS		 778/* SH7734 */
779static struct sh_eth_cpu_data sh7734_data = {
380af9e3
YS		 780 .chip_reset = sh_eth_chip_reset,
781 .set_duplex = sh_eth_set_duplex,
f5d12767
SS		 782 .set_rate = sh_eth_set_rate_gether,
783
a3153d8c
SS		 784 .register_type = SH_ETH_REG_GIGABIT,
785
f5d12767
SS		 786 .ecsr_value = ECSR_ICD | ECSR_MPD,
787 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
788 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
789
790 .tx_check = EESR_TC1 | EESR_FTC,
ca8c3585
SS		 791 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
792 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
793 EESR_TDE | EESR_ECI,
f5d12767
SS		 794
795 .apr = 1,
796 .mpr = 1,
797 .tpauser = 1,
798 .bculr = 1,
799 .hw_swap = 1,
800 .no_trimd = 1,
801 .no_ade = 1,
802 .tsu = 1,
803 .hw_crc = 1,
804 .select_mii = 1,
805};
806
807/* SH7763 */
808static struct sh_eth_cpu_data sh7763_data = {
809 .chip_reset = sh_eth_chip_reset,
810 .set_duplex = sh_eth_set_duplex,
811 .set_rate = sh_eth_set_rate_gether,
380af9e3 812
a3153d8c
SS		 813 .register_type = SH_ETH_REG_GIGABIT,
814
380af9e3
YS		 815 .ecsr_value = ECSR_ICD | ECSR_MPD,
816 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
817 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
818
819 .tx_check = EESR_TC1 | EESR_FTC,
128296fc
SS		 820 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
821 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
380af9e3 822 EESR_ECI,
380af9e3
YS		 823
824 .apr = 1,
825 .mpr = 1,
826 .tpauser = 1,
827 .bculr = 1,
828 .hw_swap = 1,
380af9e3
YS		 829 .no_trimd = 1,
830 .no_ade = 1,
4986b996 831 .tsu = 1,
5b3dfd13 832 .irq_flags = IRQF_SHARED,
380af9e3
YS		 833};
834
c18a79ab 835static struct sh_eth_cpu_data sh7619_data = {
a3153d8c
SS		 836 .register_type = SH_ETH_REG_FAST_SH3_SH2,
837
380af9e3
YS		 838 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
839
840 .apr = 1,
841 .mpr = 1,
842 .tpauser = 1,
843 .hw_swap = 1,
844};
7bbe150d
SS		 845
846static struct sh_eth_cpu_data sh771x_data = {
a3153d8c
SS		 847 .register_type = SH_ETH_REG_FAST_SH3_SH2,
848
380af9e3 849 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
4986b996 850 .tsu = 1,
380af9e3 851};
380af9e3
YS		 852
853static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
854{
855 if (!cd->ecsr_value)
856 cd->ecsr_value = DEFAULT_ECSR_INIT;
857
858 if (!cd->ecsipr_value)
859 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
860
861 if (!cd->fcftr_value)
128296fc 862 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF |
380af9e3
YS		 863 DEFAULT_FIFO_F_D_RFD;
864
865 if (!cd->fdr_value)
866 cd->fdr_value = DEFAULT_FDR_INIT;
867
380af9e3
YS		 868 if (!cd->tx_check)
869 cd->tx_check = DEFAULT_TX_CHECK;
870
871 if (!cd->eesr_err_check)
872 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
b284fbe3
NI		 873
874 if (!cd->trscer_err_mask)
875 cd->trscer_err_mask = DEFAULT_TRSCER_ERR_MASK;
380af9e3
YS		 876}
877
5cee1d37
NI		 878static int sh_eth_check_reset(struct net_device *ndev)
879{
880 int ret = 0;
881 int cnt = 100;
882
883 while (cnt > 0) {
884 if (!(sh_eth_read(ndev, EDMR) & 0x3))
885 break;
886 mdelay(1);
887 cnt--;
888 }
9f8c4265 889 if (cnt <= 0) {
f75f14ec 890 netdev_err(ndev, "Device reset failed\n");
5cee1d37
NI		 891 ret = -ETIMEDOUT;
892 }
893 return ret;
380af9e3 894}
dabdde9e
NI		 895
896static int sh_eth_reset(struct net_device *ndev)
897{
898 struct sh_eth_private *mdp = netdev_priv(ndev);
899 int ret = 0;
900
db893473 901 if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp)) {
dabdde9e
NI		 902 sh_eth_write(ndev, EDSR_ENALL, EDSR);
903 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER,
904 EDMR);
905
906 ret = sh_eth_check_reset(ndev);
907 if (ret)
f738a13d 908 return ret;
dabdde9e
NI		 909
910 /* Table Init */
911 sh_eth_write(ndev, 0x0, TDLAR);
912 sh_eth_write(ndev, 0x0, TDFAR);
913 sh_eth_write(ndev, 0x0, TDFXR);
914 sh_eth_write(ndev, 0x0, TDFFR);
915 sh_eth_write(ndev, 0x0, RDLAR);
916 sh_eth_write(ndev, 0x0, RDFAR);
917 sh_eth_write(ndev, 0x0, RDFXR);
918 sh_eth_write(ndev, 0x0, RDFFR);
919
920 /* Reset HW CRC register */
921 if (mdp->cd->hw_crc)
922 sh_eth_write(ndev, 0x0, CSMR);
923
924 /* Select MII mode */
925 if (mdp->cd->select_mii)
926 sh_eth_select_mii(ndev);
927 } else {
928 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER,
929 EDMR);
930 mdelay(3);
931 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER,
932 EDMR);
933 }
934
dabdde9e
NI		 935 return ret;
936}
380af9e3 937
380af9e3
YS		 938static void sh_eth_set_receive_align(struct sk_buff *skb)
939{
4d6a949c 940 uintptr_t reserve = (uintptr_t)skb->data & (SH_ETH_RX_ALIGN - 1);
380af9e3 941
380af9e3 942 if (reserve)
4d6a949c 943 skb_reserve(skb, SH_ETH_RX_ALIGN - reserve);
380af9e3 944}
380af9e3
YS		 945
946
71557a37
YS		 947/* CPU <-> EDMAC endian convert */
948static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x)
949{
950 switch (mdp->edmac_endian) {
951 case EDMAC_LITTLE_ENDIAN:
952 return cpu_to_le32(x);
953 case EDMAC_BIG_ENDIAN:
954 return cpu_to_be32(x);
955 }
956 return x;
957}
958
959static inline __u32 edmac_to_cpu(struct sh_eth_private *mdp, u32 x)
960{
961 switch (mdp->edmac_endian) {
962 case EDMAC_LITTLE_ENDIAN:
963 return le32_to_cpu(x);
964 case EDMAC_BIG_ENDIAN:
965 return be32_to_cpu(x);
966 }
967 return x;
968}
969
128296fc 970/* Program the hardware MAC address from dev->dev_addr. */
86a74ff2
NI		 971static void update_mac_address(struct net_device *ndev)
972{
4a55530f 973 sh_eth_write(ndev,
128296fc
SS		 974 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
975 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
4a55530f 976 sh_eth_write(ndev,
128296fc 977 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
86a74ff2
NI		 978}
979
128296fc 980/* Get MAC address from SuperH MAC address register
86a74ff2
NI		 981 *
982 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
983 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
984 * When you want use this device, you must set MAC address in bootloader.
985 *
986 */
748031f9 987static void read_mac_address(struct net_device *ndev, unsigned char *mac)
86a74ff2 988{
748031f9 989 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
d458cdf7 990 memcpy(ndev->dev_addr, mac, ETH_ALEN);
748031f9 991 } else {
37742f02
SS		 992 u32 mahr = sh_eth_read(ndev, MAHR);
993 u32 malr = sh_eth_read(ndev, MALR);
994
995 ndev->dev_addr[0] = (mahr >> 24) & 0xFF;
996 ndev->dev_addr[1] = (mahr >> 16) & 0xFF;
997 ndev->dev_addr[2] = (mahr >> 8) & 0xFF;
998 ndev->dev_addr[3] = (mahr >> 0) & 0xFF;
999 ndev->dev_addr[4] = (malr >> 8) & 0xFF;
1000 ndev->dev_addr[5] = (malr >> 0) & 0xFF;
748031f9 1001 }
86a74ff2
NI		 1002}
1003
0799c2d6 1004static u32 sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
c5ed5368 1005{
db893473 1006 if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp))
c5ed5368
YS		 1007 return EDTRR_TRNS_GETHER;
1008 else
1009 return EDTRR_TRNS_ETHER;
1010}
1011
86a74ff2 1012struct bb_info {
ae70644d 1013 void (*set_gate)(void *addr);
86a74ff2 1014 struct mdiobb_ctrl ctrl;
ae70644d 1015 void *addr;
86a74ff2
NI		 1016};
1017
1018/* PHY bit set */
ae70644d 1019static void bb_set(void *addr, u32 msk)
86a74ff2 1020{
ae70644d 1021 iowrite32(ioread32(addr) | msk, addr);
86a74ff2
NI		 1022}
1023
1024/* PHY bit clear */
ae70644d 1025static void bb_clr(void *addr, u32 msk)
86a74ff2 1026{
ae70644d 1027 iowrite32((ioread32(addr) & ~msk), addr);
86a74ff2
NI		 1028}
1029
1030/* PHY bit read */
ae70644d 1031static int bb_read(void *addr, u32 msk)
86a74ff2 1032{
ae70644d 1033 return (ioread32(addr) & msk) != 0;
86a74ff2
NI		 1034}
1035
1036/* Data I/O pin control */
1037static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1038{
1039 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
b3017e6a
YS		 1040
1041 if (bitbang->set_gate)
1042 bitbang->set_gate(bitbang->addr);
1043
86a74ff2 1044 if (bit)
3242e2b4 1045 bb_set(bitbang->addr, PIR_MMD);
86a74ff2 1046 else
3242e2b4 1047 bb_clr(bitbang->addr, PIR_MMD);
86a74ff2
NI		 1048}
1049
1050/* Set bit data*/
1051static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
1052{
1053 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1054
b3017e6a
YS		 1055 if (bitbang->set_gate)
1056 bitbang->set_gate(bitbang->addr);
1057
86a74ff2 1058 if (bit)
3242e2b4 1059 bb_set(bitbang->addr, PIR_MDO);
86a74ff2 1060 else
3242e2b4 1061 bb_clr(bitbang->addr, PIR_MDO);
86a74ff2
NI		 1062}
1063
1064/* Get bit data*/
1065static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
1066{
1067 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
b3017e6a
YS		 1068
1069 if (bitbang->set_gate)
1070 bitbang->set_gate(bitbang->addr);
1071
3242e2b4 1072 return bb_read(bitbang->addr, PIR_MDI);
86a74ff2
NI		 1073}
1074
1075/* MDC pin control */
1076static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1077{
1078 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1079
b3017e6a
YS		 1080 if (bitbang->set_gate)
1081 bitbang->set_gate(bitbang->addr);
1082
86a74ff2 1083 if (bit)
3242e2b4 1084 bb_set(bitbang->addr, PIR_MDC);
86a74ff2 1085 else
3242e2b4 1086 bb_clr(bitbang->addr, PIR_MDC);
86a74ff2
NI		 1087}
1088
1089/* mdio bus control struct */
1090static struct mdiobb_ops bb_ops = {
1091 .owner = THIS_MODULE,
1092 .set_mdc = sh_mdc_ctrl,
1093 .set_mdio_dir = sh_mmd_ctrl,
1094 .set_mdio_data = sh_set_mdio,
1095 .get_mdio_data = sh_get_mdio,
1096};
1097
86a74ff2
NI		 1098/* free skb and descriptor buffer */
1099static void sh_eth_ring_free(struct net_device *ndev)
1100{
1101 struct sh_eth_private *mdp = netdev_priv(ndev);
8e03a5e7 1102 int ringsize, i;
86a74ff2
NI		 1103
1104 /* Free Rx skb ringbuffer */
1105 if (mdp->rx_skbuff) {
179d80af
SS		 1106 for (i = 0; i < mdp->num_rx_ring; i++)
1107 dev_kfree_skb(mdp->rx_skbuff[i]);
86a74ff2
NI		 1108 }
1109 kfree(mdp->rx_skbuff);
91c77550 1110 mdp->rx_skbuff = NULL;
86a74ff2
NI		 1111
1112 /* Free Tx skb ringbuffer */
1113 if (mdp->tx_skbuff) {
179d80af
SS		 1114 for (i = 0; i < mdp->num_tx_ring; i++)
1115 dev_kfree_skb(mdp->tx_skbuff[i]);
86a74ff2
NI		 1116 }
1117 kfree(mdp->tx_skbuff);
91c77550 1118 mdp->tx_skbuff = NULL;
8e03a5e7
SS		 1119
1120 if (mdp->rx_ring) {
1121 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1122 dma_free_coherent(NULL, ringsize, mdp->rx_ring,
1123 mdp->rx_desc_dma);
1124 mdp->rx_ring = NULL;
1125 }
1126
1127 if (mdp->tx_ring) {
1128 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1129 dma_free_coherent(NULL, ringsize, mdp->tx_ring,
1130 mdp->tx_desc_dma);
1131 mdp->tx_ring = NULL;
1132 }
86a74ff2
NI		 1133}
1134
1135/* format skb and descriptor buffer */
1136static void sh_eth_ring_format(struct net_device *ndev)
1137{
1138 struct sh_eth_private *mdp = netdev_priv(ndev);
1139 int i;
1140 struct sk_buff *skb;
1141 struct sh_eth_rxdesc *rxdesc = NULL;
1142 struct sh_eth_txdesc *txdesc = NULL;
525b8075
YS		 1143 int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
1144 int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
cb368595 1145 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
52b9fa36 1146 dma_addr_t dma_addr;
86a74ff2 1147
128296fc
SS		 1148 mdp->cur_rx = 0;
1149 mdp->cur_tx = 0;
1150 mdp->dirty_rx = 0;
1151 mdp->dirty_tx = 0;
86a74ff2
NI		 1152
1153 memset(mdp->rx_ring, 0, rx_ringsize);
1154
1155 /* build Rx ring buffer */
525b8075 1156 for (i = 0; i < mdp->num_rx_ring; i++) {
86a74ff2
NI		 1157 /* skb */
1158 mdp->rx_skbuff[i] = NULL;
4d6a949c 1159 skb = netdev_alloc_skb(ndev, skbuff_size);
86a74ff2
NI		 1160 if (skb == NULL)
1161 break;
380af9e3
YS		 1162 sh_eth_set_receive_align(skb);
1163
86a74ff2
NI		 1164 /* RX descriptor */
1165 rxdesc = &mdp->rx_ring[i];
ab857916
SS		 1166 /* The size of the buffer is a multiple of 32 bytes. */
1167 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 32);
52b9fa36
BH		 1168 dma_addr = dma_map_single(&ndev->dev, skb->data,
1169 rxdesc->buffer_length,
1170 DMA_FROM_DEVICE);
1171 if (dma_mapping_error(&ndev->dev, dma_addr)) {
1172 kfree_skb(skb);
1173 break;
1174 }
1175 mdp->rx_skbuff[i] = skb;
1176 rxdesc->addr = dma_addr;
71557a37 1177 rxdesc->status = cpu_to_edmac(mdp, RD_RACT | RD_RFP);
86a74ff2 1178
b0ca2a21
NI		 1179 /* Rx descriptor address set */
1180 if (i == 0) {
4a55530f 1181 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
db893473
SH		 1182 if (sh_eth_is_gether(mdp) ||
1183 sh_eth_is_rz_fast_ether(mdp))
c5ed5368 1184 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
b0ca2a21 1185 }
86a74ff2
NI		 1186 }
1187
525b8075 1188 mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
86a74ff2
NI		 1189
1190 /* Mark the last entry as wrapping the ring. */
c238041f 1191 rxdesc->status |= cpu_to_edmac(mdp, RD_RDLE);
86a74ff2
NI		 1192
1193 memset(mdp->tx_ring, 0, tx_ringsize);
1194
1195 /* build Tx ring buffer */
525b8075 1196 for (i = 0; i < mdp->num_tx_ring; i++) {
86a74ff2
NI		 1197 mdp->tx_skbuff[i] = NULL;
1198 txdesc = &mdp->tx_ring[i];
71557a37 1199 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
86a74ff2 1200 txdesc->buffer_length = 0;
b0ca2a21 1201 if (i == 0) {
71557a37 1202 /* Tx descriptor address set */
4a55530f 1203 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
db893473
SH		 1204 if (sh_eth_is_gether(mdp) ||
1205 sh_eth_is_rz_fast_ether(mdp))
c5ed5368 1206 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
b0ca2a21 1207 }
86a74ff2
NI		 1208 }
1209
71557a37 1210 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
86a74ff2
NI		 1211}
1212
1213/* Get skb and descriptor buffer */
1214static int sh_eth_ring_init(struct net_device *ndev)
1215{
1216 struct sh_eth_private *mdp = netdev_priv(ndev);
91d80683 1217 int rx_ringsize, tx_ringsize;
86a74ff2 1218
128296fc 1219 /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
86a74ff2
NI		 1220 * card needs room to do 8 byte alignment, +2 so we can reserve
1221 * the first 2 bytes, and +16 gets room for the status word from the
1222 * card.
1223 */
1224 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
1225 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
503914cf
MD		 1226 if (mdp->cd->rpadir)
1227 mdp->rx_buf_sz += NET_IP_ALIGN;
86a74ff2
NI		 1228
1229 /* Allocate RX and TX skb rings */
2c94e856
SS		 1230 mdp->rx_skbuff = kcalloc(mdp->num_rx_ring, sizeof(*mdp->rx_skbuff),
1231 GFP_KERNEL);
91d80683
SS		 1232 if (!mdp->rx_skbuff)
1233 return -ENOMEM;
86a74ff2 1234
2c94e856
SS		 1235 mdp->tx_skbuff = kcalloc(mdp->num_tx_ring, sizeof(*mdp->tx_skbuff),
1236 GFP_KERNEL);
91d80683 1237 if (!mdp->tx_skbuff)
8e03a5e7 1238 goto ring_free;
86a74ff2
NI		 1239
1240 /* Allocate all Rx descriptors. */
525b8075 1241 rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
86a74ff2 1242 mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
d0320f75 1243 GFP_KERNEL);
91d80683 1244 if (!mdp->rx_ring)
8e03a5e7 1245 goto ring_free;
86a74ff2
NI		 1246
1247 mdp->dirty_rx = 0;
1248
1249 /* Allocate all Tx descriptors. */
525b8075 1250 tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
86a74ff2 1251 mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
d0320f75 1252 GFP_KERNEL);
91d80683 1253 if (!mdp->tx_ring)
8e03a5e7 1254 goto ring_free;
91d80683 1255 return 0;
86a74ff2 1256
8e03a5e7
SS		 1257ring_free:
1258 /* Free Rx and Tx skb ring buffer and DMA buffer */
86a74ff2
NI		 1259 sh_eth_ring_free(ndev);
1260
91d80683 1261 return -ENOMEM;
86a74ff2
NI		 1262}
1263
525b8075 1264static int sh_eth_dev_init(struct net_device *ndev, bool start)
86a74ff2
NI		 1265{
1266 int ret = 0;
1267 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 1268 u32 val;
1269
1270 /* Soft Reset */
5cee1d37
NI		 1271 ret = sh_eth_reset(ndev);
1272 if (ret)
f738a13d 1273 return ret;
86a74ff2 1274
55754f19
SH		 1275 if (mdp->cd->rmiimode)
1276 sh_eth_write(ndev, 0x1, RMIIMODE);
1277
b0ca2a21
NI		 1278 /* Descriptor format */
1279 sh_eth_ring_format(ndev);
380af9e3 1280 if (mdp->cd->rpadir)
4a55530f 1281 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
86a74ff2
NI		 1282
1283 /* all sh_eth int mask */
4a55530f 1284 sh_eth_write(ndev, 0, EESIPR);
86a74ff2 1285
10b9194f 1286#if defined(__LITTLE_ENDIAN)
380af9e3 1287 if (mdp->cd->hw_swap)
4a55530f 1288 sh_eth_write(ndev, EDMR_EL, EDMR);
380af9e3 1289 else
b0ca2a21 1290#endif
4a55530f 1291 sh_eth_write(ndev, 0, EDMR);
86a74ff2 1292
b0ca2a21 1293 /* FIFO size set */
4a55530f
YS		 1294 sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
1295 sh_eth_write(ndev, 0, TFTR);
86a74ff2 1296
530aa2d0
BD		 1297 /* Frame recv control (enable multiple-packets per rx irq) */
1298 sh_eth_write(ndev, RMCR_RNC, RMCR);
86a74ff2 1299
b284fbe3 1300 sh_eth_write(ndev, mdp->cd->trscer_err_mask, TRSCER);
86a74ff2 1301
380af9e3 1302 if (mdp->cd->bculr)
4a55530f 1303 sh_eth_write(ndev, 0x800, BCULR); /* Burst sycle set */
b0ca2a21 1304
4a55530f 1305 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
86a74ff2 1306
380af9e3 1307 if (!mdp->cd->no_trimd)
4a55530f 1308 sh_eth_write(ndev, 0, TRIMD);
86a74ff2 1309
b0ca2a21 1310 /* Recv frame limit set register */
fdb37a7f
YS		 1311 sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1312 RFLR);
86a74ff2 1313
4a55530f 1314 sh_eth_write(ndev, sh_eth_read(ndev, EESR), EESR);
283e38db
BH		 1315 if (start) {
1316 mdp->irq_enabled = true;
525b8075 1317 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
283e38db 1318 }
86a74ff2
NI		 1319
1320 /* PAUSE Prohibition */
4a55530f 1321 val = (sh_eth_read(ndev, ECMR) & ECMR_DM) |
86a74ff2
NI		 1322 ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE;
1323
4a55530f 1324 sh_eth_write(ndev, val, ECMR);
b0ca2a21 1325
380af9e3
YS		 1326 if (mdp->cd->set_rate)
1327 mdp->cd->set_rate(ndev);
1328
b0ca2a21 1329 /* E-MAC Status Register clear */
4a55530f 1330 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
b0ca2a21
NI		 1331
1332 /* E-MAC Interrupt Enable register */
525b8075
YS		 1333 if (start)
1334 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
86a74ff2
NI		 1335
1336 /* Set MAC address */
1337 update_mac_address(ndev);
1338
1339 /* mask reset */
380af9e3 1340 if (mdp->cd->apr)
4a55530f 1341 sh_eth_write(ndev, APR_AP, APR);
380af9e3 1342 if (mdp->cd->mpr)
4a55530f 1343 sh_eth_write(ndev, MPR_MP, MPR);
380af9e3 1344 if (mdp->cd->tpauser)
4a55530f 1345 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
b0ca2a21 1346
525b8075
YS		 1347 if (start) {
1348 /* Setting the Rx mode will start the Rx process. */
1349 sh_eth_write(ndev, EDRRR_R, EDRRR);
86a74ff2 1350
525b8075
YS		 1351 netif_start_queue(ndev);
1352 }
86a74ff2
NI		 1353
1354 return ret;
1355}
1356
740c7f31
BH		 1357static void sh_eth_dev_exit(struct net_device *ndev)
1358{
1359 struct sh_eth_private *mdp = netdev_priv(ndev);
1360 int i;
1361
1362 /* Deactivate all TX descriptors, so DMA should stop at next
1363 * packet boundary if it's currently running
1364 */
1365 for (i = 0; i < mdp->num_tx_ring; i++)
1366 mdp->tx_ring[i].status &= ~cpu_to_edmac(mdp, TD_TACT);
1367
1368 /* Disable TX FIFO egress to MAC */
1369 sh_eth_rcv_snd_disable(ndev);
1370
1371 /* Stop RX DMA at next packet boundary */
1372 sh_eth_write(ndev, 0, EDRRR);
1373
1374 /* Aside from TX DMA, we can't tell when the hardware is
1375 * really stopped, so we need to reset to make sure.
1376 * Before doing that, wait for long enough to *probably*
1377 * finish transmitting the last packet and poll stats.
1378 */
1379 msleep(2); /* max frame time at 10 Mbps < 1250 us */
1380 sh_eth_get_stats(ndev);
1381 sh_eth_reset(ndev);
a14c7d15
GU		 1382
1383 /* Set MAC address again */
1384 update_mac_address(ndev);
740c7f31
BH		 1385}
1386
86a74ff2
NI		 1387/* free Tx skb function */
1388static int sh_eth_txfree(struct net_device *ndev)
1389{
1390 struct sh_eth_private *mdp = netdev_priv(ndev);
1391 struct sh_eth_txdesc *txdesc;
128296fc 1392 int free_num = 0;
86a74ff2
NI		 1393 int entry = 0;
1394
1395 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
525b8075 1396 entry = mdp->dirty_tx % mdp->num_tx_ring;
86a74ff2 1397 txdesc = &mdp->tx_ring[entry];
71557a37 1398 if (txdesc->status & cpu_to_edmac(mdp, TD_TACT))
86a74ff2 1399 break;
7d7355f5 1400 /* TACT bit must be checked before all the following reads */
f32bfb9a 1401 dma_rmb();
e5fd13f4
BH		 1402 netif_info(mdp, tx_done, ndev,
1403 "tx entry %d status 0x%08x\n",
1404 entry, edmac_to_cpu(mdp, txdesc->status));
86a74ff2
NI		 1405 /* Free the original skb. */
1406 if (mdp->tx_skbuff[entry]) {
31fcb99d
YS		 1407 dma_unmap_single(&ndev->dev, txdesc->addr,
1408 txdesc->buffer_length, DMA_TO_DEVICE);
86a74ff2
NI		 1409 dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1410 mdp->tx_skbuff[entry] = NULL;
128296fc 1411 free_num++;
86a74ff2 1412 }
71557a37 1413 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
525b8075 1414 if (entry >= mdp->num_tx_ring - 1)
71557a37 1415 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
86a74ff2 1416
bb7d92e3
ED		 1417 ndev->stats.tx_packets++;
1418 ndev->stats.tx_bytes += txdesc->buffer_length;
86a74ff2 1419 }
128296fc 1420 return free_num;
86a74ff2
NI		 1421}
1422
1423/* Packet receive function */
3719109d 1424static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
86a74ff2
NI		 1425{
1426 struct sh_eth_private *mdp = netdev_priv(ndev);
1427 struct sh_eth_rxdesc *rxdesc;
1428
525b8075
YS		 1429 int entry = mdp->cur_rx % mdp->num_rx_ring;
1430 int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
319cd520 1431 int limit;
86a74ff2
NI		 1432 struct sk_buff *skb;
1433 u16 pkt_len = 0;
380af9e3 1434 u32 desc_status;
cb368595 1435 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
52b9fa36 1436 dma_addr_t dma_addr;
86a74ff2 1437
319cd520
MK		 1438 boguscnt = min(boguscnt, *quota);
1439 limit = boguscnt;
86a74ff2 1440 rxdesc = &mdp->rx_ring[entry];
71557a37 1441 while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) {
7d7355f5 1442 /* RACT bit must be checked before all the following reads */
f32bfb9a 1443 dma_rmb();
71557a37 1444 desc_status = edmac_to_cpu(mdp, rxdesc->status);
86a74ff2
NI		 1445 pkt_len = rxdesc->frame_length;
1446
1447 if (--boguscnt < 0)
1448 break;
1449
e5fd13f4
BH		 1450 netif_info(mdp, rx_status, ndev,
1451 "rx entry %d status 0x%08x len %d\n",
1452 entry, desc_status, pkt_len);
1453
86a74ff2 1454 if (!(desc_status & RDFEND))
bb7d92e3 1455 ndev->stats.rx_length_errors++;
86a74ff2 1456
128296fc 1457 /* In case of almost all GETHER/ETHERs, the Receive Frame State
dd019897 1458 * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
9b4a6364
BH		 1459 * bit 0. However, in case of the R8A7740 and R7S72100
1460 * the RFS bits are from bit 25 to bit 16. So, the
db893473 1461 * driver needs right shifting by 16.
dd019897 1462 */
ac8025a6
SS		 1463 if (mdp->cd->shift_rd0)
1464 desc_status >>= 16;
dd019897 1465
86a74ff2
NI		 1466 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1467 RD_RFS5 | RD_RFS6 | RD_RFS10)) {
bb7d92e3 1468 ndev->stats.rx_errors++;
86a74ff2 1469 if (desc_status & RD_RFS1)
bb7d92e3 1470 ndev->stats.rx_crc_errors++;
86a74ff2 1471 if (desc_status & RD_RFS2)
bb7d92e3 1472 ndev->stats.rx_frame_errors++;
86a74ff2 1473 if (desc_status & RD_RFS3)
bb7d92e3 1474 ndev->stats.rx_length_errors++;
86a74ff2 1475 if (desc_status & RD_RFS4)
bb7d92e3 1476 ndev->stats.rx_length_errors++;
86a74ff2 1477 if (desc_status & RD_RFS6)
bb7d92e3 1478 ndev->stats.rx_missed_errors++;
86a74ff2 1479 if (desc_status & RD_RFS10)
bb7d92e3 1480 ndev->stats.rx_over_errors++;
86a74ff2 1481 } else {
380af9e3
YS		 1482 if (!mdp->cd->hw_swap)
1483 sh_eth_soft_swap(
1484 phys_to_virt(ALIGN(rxdesc->addr, 4)),
1485 pkt_len + 2);
86a74ff2
NI		 1486 skb = mdp->rx_skbuff[entry];
1487 mdp->rx_skbuff[entry] = NULL;
503914cf
MD		 1488 if (mdp->cd->rpadir)
1489 skb_reserve(skb, NET_IP_ALIGN);
52b9fa36 1490 dma_unmap_single(&ndev->dev, rxdesc->addr,
ab857916 1491 ALIGN(mdp->rx_buf_sz, 32),
52b9fa36 1492 DMA_FROM_DEVICE);
86a74ff2
NI		 1493 skb_put(skb, pkt_len);
1494 skb->protocol = eth_type_trans(skb, ndev);
a8e9fd0f 1495 netif_receive_skb(skb);
bb7d92e3
ED		 1496 ndev->stats.rx_packets++;
1497 ndev->stats.rx_bytes += pkt_len;
25b77ad7
BH		 1498 if (desc_status & RD_RFS8)
1499 ndev->stats.multicast++;
86a74ff2 1500 }
525b8075 1501 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
862df497 1502 rxdesc = &mdp->rx_ring[entry];
86a74ff2
NI		 1503 }
1504
1505 /* Refill the Rx ring buffers. */
1506 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
525b8075 1507 entry = mdp->dirty_rx % mdp->num_rx_ring;
86a74ff2 1508 rxdesc = &mdp->rx_ring[entry];
ab857916
SS		 1509 /* The size of the buffer is 32 byte boundary. */
1510 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 32);
b0ca2a21 1511
86a74ff2 1512 if (mdp->rx_skbuff[entry] == NULL) {
4d6a949c 1513 skb = netdev_alloc_skb(ndev, skbuff_size);
86a74ff2
NI		 1514 if (skb == NULL)
1515 break; /* Better luck next round. */
380af9e3 1516 sh_eth_set_receive_align(skb);
52b9fa36
BH		 1517 dma_addr = dma_map_single(&ndev->dev, skb->data,
1518 rxdesc->buffer_length,
1519 DMA_FROM_DEVICE);
1520 if (dma_mapping_error(&ndev->dev, dma_addr)) {
1521 kfree_skb(skb);
1522 break;
1523 }
1524 mdp->rx_skbuff[entry] = skb;
380af9e3 1525
bc8acf2c 1526 skb_checksum_none_assert(skb);
52b9fa36 1527 rxdesc->addr = dma_addr;
86a74ff2 1528 }
f32bfb9a 1529 dma_wmb(); /* RACT bit must be set after all the above writes */
525b8075 1530 if (entry >= mdp->num_rx_ring - 1)
86a74ff2 1531 rxdesc->status |=
c238041f 1532 cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDLE);
86a74ff2
NI		 1533 else
1534 rxdesc->status |=
71557a37 1535 cpu_to_edmac(mdp, RD_RACT | RD_RFP);
86a74ff2
NI		 1536 }
1537
1538 /* Restart Rx engine if stopped. */
1539 /* If we don't need to check status, don't. -KDU */
79fba9f5 1540 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
a18e08bd 1541 /* fix the values for the next receiving if RDE is set */
3365711d
BH		 1542 if (intr_status & EESR_RDE &&
1543 mdp->reg_offset[RDFAR] != SH_ETH_OFFSET_INVALID) {
128296fc
SS		 1544 u32 count = (sh_eth_read(ndev, RDFAR) -
1545 sh_eth_read(ndev, RDLAR)) >> 4;
1546
1547 mdp->cur_rx = count;
1548 mdp->dirty_rx = count;
1549 }
4a55530f 1550 sh_eth_write(ndev, EDRRR_R, EDRRR);
79fba9f5 1551 }
86a74ff2 1552
319cd520
MK		 1553 *quota -= limit - boguscnt - 1;
1554
4f809cea 1555 return *quota <= 0;
86a74ff2
NI		 1556}
1557
4a55530f 1558static void sh_eth_rcv_snd_disable(struct net_device *ndev)
dc19e4e5
NI		 1559{
1560 /* disable tx and rx */
4a55530f
YS		 1561 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) &
1562 ~(ECMR_RE | ECMR_TE), ECMR);
dc19e4e5
NI		 1563}
1564
4a55530f 1565static void sh_eth_rcv_snd_enable(struct net_device *ndev)
dc19e4e5
NI		 1566{
1567 /* enable tx and rx */
4a55530f
YS		 1568 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) |
1569 (ECMR_RE | ECMR_TE), ECMR);
dc19e4e5
NI		 1570}
1571
86a74ff2 1572/* error control function */
0799c2d6 1573static void sh_eth_error(struct net_device *ndev, u32 intr_status)
86a74ff2
NI		 1574{
1575 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2 1576 u32 felic_stat;
380af9e3
YS		 1577 u32 link_stat;
1578 u32 mask;
86a74ff2
NI		 1579
1580 if (intr_status & EESR_ECI) {
4a55530f
YS		 1581 felic_stat = sh_eth_read(ndev, ECSR);
1582 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */
86a74ff2 1583 if (felic_stat & ECSR_ICD)
bb7d92e3 1584 ndev->stats.tx_carrier_errors++;
86a74ff2
NI		 1585 if (felic_stat & ECSR_LCHNG) {
1586 /* Link Changed */
4923576b 1587 if (mdp->cd->no_psr || mdp->no_ether_link) {
1e1b812b 1588 goto ignore_link;
380af9e3 1589 } else {
4a55530f 1590 link_stat = (sh_eth_read(ndev, PSR));
4923576b
YS		 1591 if (mdp->ether_link_active_low)
1592 link_stat = ~link_stat;
380af9e3 1593 }
128296fc 1594 if (!(link_stat & PHY_ST_LINK)) {
4a55530f 1595 sh_eth_rcv_snd_disable(ndev);
128296fc 1596 } else {
86a74ff2 1597 /* Link Up */
4a55530f 1598 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) &
128296fc
SS		 1599 ~DMAC_M_ECI, EESIPR);
1600 /* clear int */
4a55530f 1601 sh_eth_write(ndev, sh_eth_read(ndev, ECSR),
128296fc 1602 ECSR);
4a55530f 1603 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) |
128296fc 1604 DMAC_M_ECI, EESIPR);
86a74ff2 1605 /* enable tx and rx */
4a55530f 1606 sh_eth_rcv_snd_enable(ndev);
86a74ff2
NI		 1607 }
1608 }
1609 }
1610
1e1b812b 1611ignore_link:
86a74ff2 1612 if (intr_status & EESR_TWB) {
4eb313a7
SS		 1613 /* Unused write back interrupt */
1614 if (intr_status & EESR_TABT) { /* Transmit Abort int */
bb7d92e3 1615 ndev->stats.tx_aborted_errors++;
8d5009f6 1616 netif_err(mdp, tx_err, ndev, "Transmit Abort\n");
4eb313a7 1617 }
86a74ff2
NI		 1618 }
1619
1620 if (intr_status & EESR_RABT) {
1621 /* Receive Abort int */
1622 if (intr_status & EESR_RFRMER) {
1623 /* Receive Frame Overflow int */
bb7d92e3 1624 ndev->stats.rx_frame_errors++;
86a74ff2
NI		 1625 }
1626 }
380af9e3 1627
dc19e4e5
NI		 1628 if (intr_status & EESR_TDE) {
1629 /* Transmit Descriptor Empty int */
bb7d92e3 1630 ndev->stats.tx_fifo_errors++;
8d5009f6 1631 netif_err(mdp, tx_err, ndev, "Transmit Descriptor Empty\n");
dc19e4e5
NI		 1632 }
1633
1634 if (intr_status & EESR_TFE) {
1635 /* FIFO under flow */
bb7d92e3 1636 ndev->stats.tx_fifo_errors++;
8d5009f6 1637 netif_err(mdp, tx_err, ndev, "Transmit FIFO Under flow\n");
86a74ff2
NI		 1638 }
1639
1640 if (intr_status & EESR_RDE) {
1641 /* Receive Descriptor Empty int */
bb7d92e3 1642 ndev->stats.rx_over_errors++;
86a74ff2 1643 }
dc19e4e5 1644
86a74ff2
NI		 1645 if (intr_status & EESR_RFE) {
1646 /* Receive FIFO Overflow int */
bb7d92e3 1647 ndev->stats.rx_fifo_errors++;
dc19e4e5
NI		 1648 }
1649
1650 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1651 /* Address Error */
bb7d92e3 1652 ndev->stats.tx_fifo_errors++;
8d5009f6 1653 netif_err(mdp, tx_err, ndev, "Address Error\n");
86a74ff2 1654 }
380af9e3
YS		 1655
1656 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1657 if (mdp->cd->no_ade)
1658 mask &= ~EESR_ADE;
1659 if (intr_status & mask) {
86a74ff2 1660 /* Tx error */
4a55530f 1661 u32 edtrr = sh_eth_read(ndev, EDTRR);
090d560f 1662
86a74ff2 1663 /* dmesg */
da246855
SS		 1664 netdev_err(ndev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1665 intr_status, mdp->cur_tx, mdp->dirty_tx,
1666 (u32)ndev->state, edtrr);
86a74ff2
NI		 1667 /* dirty buffer free */
1668 sh_eth_txfree(ndev);
1669
1670 /* SH7712 BUG */
c5ed5368 1671 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
86a74ff2 1672 /* tx dma start */
c5ed5368 1673 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
86a74ff2
NI		 1674 }
1675 /* wakeup */
1676 netif_wake_queue(ndev);
1677 }
1678}
1679
1680static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1681{
1682 struct net_device *ndev = netdev;
1683 struct sh_eth_private *mdp = netdev_priv(ndev);
380af9e3 1684 struct sh_eth_cpu_data *cd = mdp->cd;
0e0fde3c 1685 irqreturn_t ret = IRQ_NONE;
0799c2d6 1686 u32 intr_status, intr_enable;
86a74ff2 1687
86a74ff2
NI		 1688 spin_lock(&mdp->lock);
1689
3893b273 1690 /* Get interrupt status */
4a55530f 1691 intr_status = sh_eth_read(ndev, EESR);
3893b273
SS		 1692 /* Mask it with the interrupt mask, forcing ECI interrupt to be always
1693 * enabled since it's the one that comes thru regardless of the mask,
1694 * and we need to fully handle it in sh_eth_error() in order to quench
1695 * it as it doesn't get cleared by just writing 1 to the ECI bit...
1696 */
3719109d
SS		 1697 intr_enable = sh_eth_read(ndev, EESIPR);
1698 intr_status &= intr_enable | DMAC_M_ECI;
1699 if (intr_status & (EESR_RX_CHECK | cd->tx_check | cd->eesr_err_check))
0e0fde3c 1700 ret = IRQ_HANDLED;
3719109d 1701 else
283e38db
BH		 1702 goto out;
1703
1704 if (!likely(mdp->irq_enabled)) {
1705 sh_eth_write(ndev, 0, EESIPR);
1706 goto out;
1707 }
86a74ff2 1708
3719109d
SS		 1709 if (intr_status & EESR_RX_CHECK) {
1710 if (napi_schedule_prep(&mdp->napi)) {
1711 /* Mask Rx interrupts */
1712 sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK,
1713 EESIPR);
1714 __napi_schedule(&mdp->napi);
1715 } else {
da246855 1716 netdev_warn(ndev,
0799c2d6 1717 "ignoring interrupt, status 0x%08x, mask 0x%08x.\n",
da246855 1718 intr_status, intr_enable);
3719109d
SS		 1719 }
1720 }
86a74ff2 1721
b0ca2a21 1722 /* Tx Check */
380af9e3 1723 if (intr_status & cd->tx_check) {
3719109d
SS		 1724 /* Clear Tx interrupts */
1725 sh_eth_write(ndev, intr_status & cd->tx_check, EESR);
1726
86a74ff2
NI		 1727 sh_eth_txfree(ndev);
1728 netif_wake_queue(ndev);
1729 }
1730
3719109d
SS		 1731 if (intr_status & cd->eesr_err_check) {
1732 /* Clear error interrupts */
1733 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR);
1734
86a74ff2 1735 sh_eth_error(ndev, intr_status);
3719109d 1736 }
86a74ff2 1737
283e38db 1738out:
86a74ff2
NI		 1739 spin_unlock(&mdp->lock);
1740
0e0fde3c 1741 return ret;
86a74ff2
NI		 1742}
1743
3719109d
SS		 1744static int sh_eth_poll(struct napi_struct *napi, int budget)
1745{
1746 struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private,
1747 napi);
1748 struct net_device *ndev = napi->dev;
1749 int quota = budget;
0799c2d6 1750 u32 intr_status;
3719109d
SS		 1751
1752 for (;;) {
1753 intr_status = sh_eth_read(ndev, EESR);
1754 if (!(intr_status & EESR_RX_CHECK))
1755 break;
1756 /* Clear Rx interrupts */
1757 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR);
1758
1759 if (sh_eth_rx(ndev, intr_status, &quota))
1760 goto out;
1761 }
1762
1763 napi_complete(napi);
1764
1765 /* Reenable Rx interrupts */
283e38db
BH		 1766 if (mdp->irq_enabled)
1767 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
3719109d
SS		 1768out:
1769 return budget - quota;
1770}
1771
86a74ff2
NI		 1772/* PHY state control function */
1773static void sh_eth_adjust_link(struct net_device *ndev)
1774{
1775 struct sh_eth_private *mdp = netdev_priv(ndev);
1776 struct phy_device *phydev = mdp->phydev;
86a74ff2
NI		 1777 int new_state = 0;
1778
3340d2aa 1779 if (phydev->link) {
86a74ff2
NI		 1780 if (phydev->duplex != mdp->duplex) {
1781 new_state = 1;
1782 mdp->duplex = phydev->duplex;
380af9e3
YS		 1783 if (mdp->cd->set_duplex)
1784 mdp->cd->set_duplex(ndev);
86a74ff2
NI		 1785 }
1786
1787 if (phydev->speed != mdp->speed) {
1788 new_state = 1;
1789 mdp->speed = phydev->speed;
380af9e3
YS		 1790 if (mdp->cd->set_rate)
1791 mdp->cd->set_rate(ndev);
86a74ff2 1792 }
3340d2aa 1793 if (!mdp->link) {
91a56152 1794 sh_eth_write(ndev,
128296fc
SS		 1795 sh_eth_read(ndev, ECMR) & ~ECMR_TXF,
1796 ECMR);
86a74ff2
NI		 1797 new_state = 1;
1798 mdp->link = phydev->link;
1e1b812b
SS		 1799 if (mdp->cd->no_psr || mdp->no_ether_link)
1800 sh_eth_rcv_snd_enable(ndev);
86a74ff2
NI		 1801 }
1802 } else if (mdp->link) {
1803 new_state = 1;
3340d2aa 1804 mdp->link = 0;
86a74ff2
NI		 1805 mdp->speed = 0;
1806 mdp->duplex = -1;
1e1b812b
SS		 1807 if (mdp->cd->no_psr || mdp->no_ether_link)
1808 sh_eth_rcv_snd_disable(ndev);
86a74ff2
NI		 1809 }
1810
dc19e4e5 1811 if (new_state && netif_msg_link(mdp))
86a74ff2
NI		 1812 phy_print_status(phydev);
1813}
1814
1815/* PHY init function */
1816static int sh_eth_phy_init(struct net_device *ndev)
1817{
702eca02 1818 struct device_node *np = ndev->dev.parent->of_node;
86a74ff2 1819 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 1820 struct phy_device *phydev = NULL;
1821
3340d2aa 1822 mdp->link = 0;
86a74ff2
NI		 1823 mdp->speed = 0;
1824 mdp->duplex = -1;
1825
1826 /* Try connect to PHY */
702eca02
BD		 1827 if (np) {
1828 struct device_node *pn;
1829
1830 pn = of_parse_phandle(np, "phy-handle", 0);
1831 phydev = of_phy_connect(ndev, pn,
1832 sh_eth_adjust_link, 0,
1833 mdp->phy_interface);
1834
1835 if (!phydev)
1836 phydev = ERR_PTR(-ENOENT);
1837 } else {
1838 char phy_id[MII_BUS_ID_SIZE + 3];
1839
1840 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
1841 mdp->mii_bus->id, mdp->phy_id);
1842
1843 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
1844 mdp->phy_interface);
1845 }
1846
86a74ff2 1847 if (IS_ERR(phydev)) {
da246855 1848 netdev_err(ndev, "failed to connect PHY\n");
86a74ff2
NI		 1849 return PTR_ERR(phydev);
1850 }
380af9e3 1851
da246855
SS		 1852 netdev_info(ndev, "attached PHY %d (IRQ %d) to driver %s\n",
1853 phydev->addr, phydev->irq, phydev->drv->name);
86a74ff2
NI		 1854
1855 mdp->phydev = phydev;
1856
1857 return 0;
1858}
1859
1860/* PHY control start function */
1861static int sh_eth_phy_start(struct net_device *ndev)
1862{
1863 struct sh_eth_private *mdp = netdev_priv(ndev);
1864 int ret;
1865
1866 ret = sh_eth_phy_init(ndev);
1867 if (ret)
1868 return ret;
1869
86a74ff2
NI		 1870 phy_start(mdp->phydev);
1871
1872 return 0;
1873}
1874
dc19e4e5 1875static int sh_eth_get_settings(struct net_device *ndev,
128296fc 1876 struct ethtool_cmd *ecmd)
dc19e4e5
NI		 1877{
1878 struct sh_eth_private *mdp = netdev_priv(ndev);
1879 unsigned long flags;
1880 int ret;
1881
4f9dce23
BH		 1882 if (!mdp->phydev)
1883 return -ENODEV;
1884
dc19e4e5
NI		 1885 spin_lock_irqsave(&mdp->lock, flags);
1886 ret = phy_ethtool_gset(mdp->phydev, ecmd);
1887 spin_unlock_irqrestore(&mdp->lock, flags);
1888
1889 return ret;
1890}
1891
1892static int sh_eth_set_settings(struct net_device *ndev,
128296fc 1893 struct ethtool_cmd *ecmd)
dc19e4e5
NI		 1894{
1895 struct sh_eth_private *mdp = netdev_priv(ndev);
1896 unsigned long flags;
1897 int ret;
dc19e4e5 1898
4f9dce23
BH		 1899 if (!mdp->phydev)
1900 return -ENODEV;
1901
dc19e4e5
NI		 1902 spin_lock_irqsave(&mdp->lock, flags);
1903
1904 /* disable tx and rx */
4a55530f 1905 sh_eth_rcv_snd_disable(ndev);
dc19e4e5
NI		 1906
1907 ret = phy_ethtool_sset(mdp->phydev, ecmd);
1908 if (ret)
1909 goto error_exit;
1910
1911 if (ecmd->duplex == DUPLEX_FULL)
1912 mdp->duplex = 1;
1913 else
1914 mdp->duplex = 0;
1915
1916 if (mdp->cd->set_duplex)
1917 mdp->cd->set_duplex(ndev);
1918
1919error_exit:
1920 mdelay(1);
1921
1922 /* enable tx and rx */
4a55530f 1923 sh_eth_rcv_snd_enable(ndev);
dc19e4e5
NI		 1924
1925 spin_unlock_irqrestore(&mdp->lock, flags);
1926
1927 return ret;
1928}
1929
6b4b4fea
BH		 1930/* If it is ever necessary to increase SH_ETH_REG_DUMP_MAX_REGS, the
1931 * version must be bumped as well. Just adding registers up to that
1932 * limit is fine, as long as the existing register indices don't
1933 * change.
1934 */
1935#define SH_ETH_REG_DUMP_VERSION 1
1936#define SH_ETH_REG_DUMP_MAX_REGS 256
1937
1938static size_t __sh_eth_get_regs(struct net_device *ndev, u32 *buf)
1939{
1940 struct sh_eth_private *mdp = netdev_priv(ndev);
1941 struct sh_eth_cpu_data *cd = mdp->cd;
1942 u32 *valid_map;
1943 size_t len;
1944
1945 BUILD_BUG_ON(SH_ETH_MAX_REGISTER_OFFSET > SH_ETH_REG_DUMP_MAX_REGS);
1946
1947 /* Dump starts with a bitmap that tells ethtool which
1948 * registers are defined for this chip.
1949 */
1950 len = DIV_ROUND_UP(SH_ETH_REG_DUMP_MAX_REGS, 32);
1951 if (buf) {
1952 valid_map = buf;
1953 buf += len;
1954 } else {
1955 valid_map = NULL;
1956 }
1957
1958 /* Add a register to the dump, if it has a defined offset.
1959 * This automatically skips most undefined registers, but for
1960 * some it is also necessary to check a capability flag in
1961 * struct sh_eth_cpu_data.
1962 */
1963#define mark_reg_valid(reg) valid_map[reg / 32] |= 1U << (reg % 32)
1964#define add_reg_from(reg, read_expr) do { \
1965 if (mdp->reg_offset[reg] != SH_ETH_OFFSET_INVALID) { \
1966 if (buf) { \
1967 mark_reg_valid(reg); \
1968 *buf++ = read_expr; \
1969 } \
1970 ++len; \
1971 } \
1972 } while (0)
1973#define add_reg(reg) add_reg_from(reg, sh_eth_read(ndev, reg))
1974#define add_tsu_reg(reg) add_reg_from(reg, sh_eth_tsu_read(mdp, reg))
1975
1976 add_reg(EDSR);
1977 add_reg(EDMR);
1978 add_reg(EDTRR);
1979 add_reg(EDRRR);
1980 add_reg(EESR);
1981 add_reg(EESIPR);
1982 add_reg(TDLAR);
1983 add_reg(TDFAR);
1984 add_reg(TDFXR);
1985 add_reg(TDFFR);
1986 add_reg(RDLAR);
1987 add_reg(RDFAR);
1988 add_reg(RDFXR);
1989 add_reg(RDFFR);
1990 add_reg(TRSCER);
1991 add_reg(RMFCR);
1992 add_reg(TFTR);
1993 add_reg(FDR);
1994 add_reg(RMCR);
1995 add_reg(TFUCR);
1996 add_reg(RFOCR);
1997 if (cd->rmiimode)
1998 add_reg(RMIIMODE);
1999 add_reg(FCFTR);
2000 if (cd->rpadir)
2001 add_reg(RPADIR);
2002 if (!cd->no_trimd)
2003 add_reg(TRIMD);
2004 add_reg(ECMR);
2005 add_reg(ECSR);
2006 add_reg(ECSIPR);
2007 add_reg(PIR);
2008 if (!cd->no_psr)
2009 add_reg(PSR);
2010 add_reg(RDMLR);
2011 add_reg(RFLR);
2012 add_reg(IPGR);
2013 if (cd->apr)
2014 add_reg(APR);
2015 if (cd->mpr)
2016 add_reg(MPR);
2017 add_reg(RFCR);
2018 add_reg(RFCF);
2019 if (cd->tpauser)
2020 add_reg(TPAUSER);
2021 add_reg(TPAUSECR);
2022 add_reg(GECMR);
2023 if (cd->bculr)
2024 add_reg(BCULR);
2025 add_reg(MAHR);
2026 add_reg(MALR);
2027 add_reg(TROCR);
2028 add_reg(CDCR);
2029 add_reg(LCCR);
2030 add_reg(CNDCR);
2031 add_reg(CEFCR);
2032 add_reg(FRECR);
2033 add_reg(TSFRCR);
2034 add_reg(TLFRCR);
2035 add_reg(CERCR);
2036 add_reg(CEECR);
2037 add_reg(MAFCR);
2038 if (cd->rtrate)
2039 add_reg(RTRATE);
2040 if (cd->hw_crc)
2041 add_reg(CSMR);
2042 if (cd->select_mii)
2043 add_reg(RMII_MII);
2044 add_reg(ARSTR);
2045 if (cd->tsu) {
2046 add_tsu_reg(TSU_CTRST);
2047 add_tsu_reg(TSU_FWEN0);
2048 add_tsu_reg(TSU_FWEN1);
2049 add_tsu_reg(TSU_FCM);
2050 add_tsu_reg(TSU_BSYSL0);
2051 add_tsu_reg(TSU_BSYSL1);
2052 add_tsu_reg(TSU_PRISL0);
2053 add_tsu_reg(TSU_PRISL1);
2054 add_tsu_reg(TSU_FWSL0);
2055 add_tsu_reg(TSU_FWSL1);
2056 add_tsu_reg(TSU_FWSLC);
2057 add_tsu_reg(TSU_QTAG0);
2058 add_tsu_reg(TSU_QTAG1);
2059 add_tsu_reg(TSU_QTAGM0);
2060 add_tsu_reg(TSU_QTAGM1);
2061 add_tsu_reg(TSU_FWSR);
2062 add_tsu_reg(TSU_FWINMK);
2063 add_tsu_reg(TSU_ADQT0);
2064 add_tsu_reg(TSU_ADQT1);
2065 add_tsu_reg(TSU_VTAG0);
2066 add_tsu_reg(TSU_VTAG1);
2067 add_tsu_reg(TSU_ADSBSY);
2068 add_tsu_reg(TSU_TEN);
2069 add_tsu_reg(TSU_POST1);
2070 add_tsu_reg(TSU_POST2);
2071 add_tsu_reg(TSU_POST3);
2072 add_tsu_reg(TSU_POST4);
2073 if (mdp->reg_offset[TSU_ADRH0] != SH_ETH_OFFSET_INVALID) {
2074 /* This is the start of a table, not just a single
2075 * register.
2076 */
2077 if (buf) {
2078 unsigned int i;
2079
2080 mark_reg_valid(TSU_ADRH0);
2081 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES * 2; i++)
2082 *buf++ = ioread32(
2083 mdp->tsu_addr +
2084 mdp->reg_offset[TSU_ADRH0] +
2085 i * 4);
2086 }
2087 len += SH_ETH_TSU_CAM_ENTRIES * 2;
2088 }
2089 }
2090
2091#undef mark_reg_valid
2092#undef add_reg_from
2093#undef add_reg
2094#undef add_tsu_reg
2095
2096 return len * 4;
2097}
2098
2099static int sh_eth_get_regs_len(struct net_device *ndev)
2100{
2101 return __sh_eth_get_regs(ndev, NULL);
2102}
2103
2104static void sh_eth_get_regs(struct net_device *ndev, struct ethtool_regs *regs,
2105 void *buf)
2106{
2107 struct sh_eth_private *mdp = netdev_priv(ndev);
2108
2109 regs->version = SH_ETH_REG_DUMP_VERSION;
2110
2111 pm_runtime_get_sync(&mdp->pdev->dev);
2112 __sh_eth_get_regs(ndev, buf);
2113 pm_runtime_put_sync(&mdp->pdev->dev);
2114}
2115
dc19e4e5
NI		 2116static int sh_eth_nway_reset(struct net_device *ndev)
2117{
2118 struct sh_eth_private *mdp = netdev_priv(ndev);
2119 unsigned long flags;
2120 int ret;
2121
4f9dce23
BH		 2122 if (!mdp->phydev)
2123 return -ENODEV;
2124
dc19e4e5
NI		 2125 spin_lock_irqsave(&mdp->lock, flags);
2126 ret = phy_start_aneg(mdp->phydev);
2127 spin_unlock_irqrestore(&mdp->lock, flags);
2128
2129 return ret;
2130}
2131
2132static u32 sh_eth_get_msglevel(struct net_device *ndev)
2133{
2134 struct sh_eth_private *mdp = netdev_priv(ndev);
2135 return mdp->msg_enable;
2136}
2137
2138static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
2139{
2140 struct sh_eth_private *mdp = netdev_priv(ndev);
2141 mdp->msg_enable = value;
2142}
2143
2144static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
2145 "rx_current", "tx_current",
2146 "rx_dirty", "tx_dirty",
2147};
2148#define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats)
2149
2150static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
2151{
2152 switch (sset) {
2153 case ETH_SS_STATS:
2154 return SH_ETH_STATS_LEN;
2155 default:
2156 return -EOPNOTSUPP;
2157 }
2158}
2159
2160static void sh_eth_get_ethtool_stats(struct net_device *ndev,
128296fc 2161 struct ethtool_stats *stats, u64 *data)
dc19e4e5
NI		 2162{
2163 struct sh_eth_private *mdp = netdev_priv(ndev);
2164 int i = 0;
2165
2166 /* device-specific stats */
2167 data[i++] = mdp->cur_rx;
2168 data[i++] = mdp->cur_tx;
2169 data[i++] = mdp->dirty_rx;
2170 data[i++] = mdp->dirty_tx;
2171}
2172
2173static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
2174{
2175 switch (stringset) {
2176 case ETH_SS_STATS:
2177 memcpy(data, *sh_eth_gstrings_stats,
128296fc 2178 sizeof(sh_eth_gstrings_stats));
dc19e4e5
NI		 2179 break;
2180 }
2181}
2182
525b8075
YS		 2183static void sh_eth_get_ringparam(struct net_device *ndev,
2184 struct ethtool_ringparam *ring)
2185{
2186 struct sh_eth_private *mdp = netdev_priv(ndev);
2187
2188 ring->rx_max_pending = RX_RING_MAX;
2189 ring->tx_max_pending = TX_RING_MAX;
2190 ring->rx_pending = mdp->num_rx_ring;
2191 ring->tx_pending = mdp->num_tx_ring;
2192}
2193
2194static int sh_eth_set_ringparam(struct net_device *ndev,
2195 struct ethtool_ringparam *ring)
2196{
2197 struct sh_eth_private *mdp = netdev_priv(ndev);
2198 int ret;
2199
2200 if (ring->tx_pending > TX_RING_MAX ||
2201 ring->rx_pending > RX_RING_MAX ||
2202 ring->tx_pending < TX_RING_MIN ||
2203 ring->rx_pending < RX_RING_MIN)
2204 return -EINVAL;
2205 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
2206 return -EINVAL;
2207
2208 if (netif_running(ndev)) {
bd888916 2209 netif_device_detach(ndev);
525b8075 2210 netif_tx_disable(ndev);
283e38db
BH		 2211
2212 /* Serialise with the interrupt handler and NAPI, then
2213 * disable interrupts. We have to clear the
2214 * irq_enabled flag first to ensure that interrupts
2215 * won't be re-enabled.
2216 */
2217 mdp->irq_enabled = false;
525b8075 2218 synchronize_irq(ndev->irq);
283e38db 2219 napi_synchronize(&mdp->napi);
525b8075 2220 sh_eth_write(ndev, 0x0000, EESIPR);
525b8075 2221
740c7f31 2222 sh_eth_dev_exit(ndev);
525b8075 2223
8e03a5e7 2224 /* Free all the skbuffs in the Rx queue and the DMA buffers. */
084236d8 2225 sh_eth_ring_free(ndev);
084236d8 2226 }
525b8075
YS		 2227
2228 /* Set new parameters */
2229 mdp->num_rx_ring = ring->rx_pending;
2230 mdp->num_tx_ring = ring->tx_pending;
2231
525b8075 2232 if (netif_running(ndev)) {
084236d8
BH		 2233 ret = sh_eth_ring_init(ndev);
2234 if (ret < 0) {
2235 netdev_err(ndev, "%s: sh_eth_ring_init failed.\n",
2236 __func__);
2237 return ret;
2238 }
2239 ret = sh_eth_dev_init(ndev, false);
2240 if (ret < 0) {
2241 netdev_err(ndev, "%s: sh_eth_dev_init failed.\n",
2242 __func__);
2243 return ret;
2244 }
2245
283e38db 2246 mdp->irq_enabled = true;
525b8075
YS		 2247 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
2248 /* Setting the Rx mode will start the Rx process. */
2249 sh_eth_write(ndev, EDRRR_R, EDRRR);
bd888916 2250 netif_device_attach(ndev);
525b8075
YS		 2251 }
2252
2253 return 0;
2254}
2255
9b07be4b 2256static const struct ethtool_ops sh_eth_ethtool_ops = {
dc19e4e5
NI		 2257 .get_settings = sh_eth_get_settings,
2258 .set_settings = sh_eth_set_settings,
6b4b4fea
BH		 2259 .get_regs_len = sh_eth_get_regs_len,
2260 .get_regs = sh_eth_get_regs,
9b07be4b 2261 .nway_reset = sh_eth_nway_reset,
dc19e4e5
NI		 2262 .get_msglevel = sh_eth_get_msglevel,
2263 .set_msglevel = sh_eth_set_msglevel,
9b07be4b 2264 .get_link = ethtool_op_get_link,
dc19e4e5
NI		 2265 .get_strings = sh_eth_get_strings,
2266 .get_ethtool_stats = sh_eth_get_ethtool_stats,
2267 .get_sset_count = sh_eth_get_sset_count,
525b8075
YS		 2268 .get_ringparam = sh_eth_get_ringparam,
2269 .set_ringparam = sh_eth_set_ringparam,
dc19e4e5
NI		 2270};
2271
86a74ff2
NI		 2272/* network device open function */
2273static int sh_eth_open(struct net_device *ndev)
2274{
2275 int ret = 0;
2276 struct sh_eth_private *mdp = netdev_priv(ndev);
2277
bcd5149d
MD		 2278 pm_runtime_get_sync(&mdp->pdev->dev);
2279
d2779e99
SS		 2280 napi_enable(&mdp->napi);
2281
a0607fd3 2282 ret = request_irq(ndev->irq, sh_eth_interrupt,
5b3dfd13 2283 mdp->cd->irq_flags, ndev->name, ndev);
86a74ff2 2284 if (ret) {
da246855 2285 netdev_err(ndev, "Can not assign IRQ number\n");
d2779e99 2286 goto out_napi_off;
86a74ff2
NI		 2287 }
2288
2289 /* Descriptor set */
2290 ret = sh_eth_ring_init(ndev);
2291 if (ret)
2292 goto out_free_irq;
2293
2294 /* device init */
525b8075 2295 ret = sh_eth_dev_init(ndev, true);
86a74ff2
NI		 2296 if (ret)
2297 goto out_free_irq;
2298
2299 /* PHY control start*/
2300 ret = sh_eth_phy_start(ndev);
2301 if (ret)
2302 goto out_free_irq;
2303
7fa2955f
MK		 2304 mdp->is_opened = 1;
2305
86a74ff2
NI		 2306 return ret;
2307
2308out_free_irq:
2309 free_irq(ndev->irq, ndev);
d2779e99
SS		 2310out_napi_off:
2311 napi_disable(&mdp->napi);
bcd5149d 2312 pm_runtime_put_sync(&mdp->pdev->dev);
86a74ff2
NI		 2313 return ret;
2314}
2315
2316/* Timeout function */
2317static void sh_eth_tx_timeout(struct net_device *ndev)
2318{
2319 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 2320 struct sh_eth_rxdesc *rxdesc;
2321 int i;
2322
2323 netif_stop_queue(ndev);
2324
8d5009f6
SS		 2325 netif_err(mdp, timer, ndev,
2326 "transmit timed out, status %8.8x, resetting...\n",
0799c2d6 2327 sh_eth_read(ndev, EESR));
86a74ff2
NI		 2328
2329 /* tx_errors count up */
bb7d92e3 2330 ndev->stats.tx_errors++;
86a74ff2 2331
86a74ff2 2332 /* Free all the skbuffs in the Rx queue. */
525b8075 2333 for (i = 0; i < mdp->num_rx_ring; i++) {
86a74ff2
NI		 2334 rxdesc = &mdp->rx_ring[i];
2335 rxdesc->status = 0;
2336 rxdesc->addr = 0xBADF00D0;
179d80af 2337 dev_kfree_skb(mdp->rx_skbuff[i]);
86a74ff2
NI		 2338 mdp->rx_skbuff[i] = NULL;
2339 }
525b8075 2340 for (i = 0; i < mdp->num_tx_ring; i++) {
179d80af 2341 dev_kfree_skb(mdp->tx_skbuff[i]);
86a74ff2
NI		 2342 mdp->tx_skbuff[i] = NULL;
2343 }
2344
2345 /* device init */
525b8075 2346 sh_eth_dev_init(ndev, true);
86a74ff2
NI		 2347}
2348
2349/* Packet transmit function */
2350static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
2351{
2352 struct sh_eth_private *mdp = netdev_priv(ndev);
2353 struct sh_eth_txdesc *txdesc;
2354 u32 entry;
fb5e2f9b 2355 unsigned long flags;
86a74ff2
NI		 2356
2357 spin_lock_irqsave(&mdp->lock, flags);
525b8075 2358 if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
86a74ff2 2359 if (!sh_eth_txfree(ndev)) {
8d5009f6 2360 netif_warn(mdp, tx_queued, ndev, "TxFD exhausted.\n");
86a74ff2
NI		 2361 netif_stop_queue(ndev);
2362 spin_unlock_irqrestore(&mdp->lock, flags);
5b548140 2363 return NETDEV_TX_BUSY;
86a74ff2
NI		 2364 }
2365 }
2366 spin_unlock_irqrestore(&mdp->lock, flags);
2367
dacc73e0 2368 if (skb_put_padto(skb, ETH_ZLEN))
eebfb643
BH		 2369 return NETDEV_TX_OK;
2370
525b8075 2371 entry = mdp->cur_tx % mdp->num_tx_ring;
86a74ff2
NI		 2372 mdp->tx_skbuff[entry] = skb;
2373 txdesc = &mdp->tx_ring[entry];
86a74ff2 2374 /* soft swap. */
380af9e3
YS		 2375 if (!mdp->cd->hw_swap)
2376 sh_eth_soft_swap(phys_to_virt(ALIGN(txdesc->addr, 4)),
2377 skb->len + 2);
31fcb99d
YS		 2378 txdesc->addr = dma_map_single(&ndev->dev, skb->data, skb->len,
2379 DMA_TO_DEVICE);
aa3933b8
BH		 2380 if (dma_mapping_error(&ndev->dev, txdesc->addr)) {
2381 kfree_skb(skb);
2382 return NETDEV_TX_OK;
2383 }
eebfb643 2384 txdesc->buffer_length = skb->len;
86a74ff2 2385
f32bfb9a 2386 dma_wmb(); /* TACT bit must be set after all the above writes */
525b8075 2387 if (entry >= mdp->num_tx_ring - 1)
71557a37 2388 txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE);
86a74ff2 2389 else
71557a37 2390 txdesc->status |= cpu_to_edmac(mdp, TD_TACT);
86a74ff2
NI		 2391
2392 mdp->cur_tx++;
2393
c5ed5368
YS		 2394 if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
2395 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
b0ca2a21 2396
6ed10654 2397 return NETDEV_TX_OK;
86a74ff2
NI		 2398}
2399
4398f9c8
BH		 2400/* The statistics registers have write-clear behaviour, which means we
2401 * will lose any increment between the read and write. We mitigate
2402 * this by only clearing when we read a non-zero value, so we will
2403 * never falsely report a total of zero.
2404 */
2405static void
2406sh_eth_update_stat(struct net_device *ndev, unsigned long *stat, int reg)
2407{
2408 u32 delta = sh_eth_read(ndev, reg);
2409
2410 if (delta) {
2411 *stat += delta;
2412 sh_eth_write(ndev, 0, reg);
2413 }
2414}
2415
7fa2955f
MK		 2416static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
2417{
2418 struct sh_eth_private *mdp = netdev_priv(ndev);
2419
2420 if (sh_eth_is_rz_fast_ether(mdp))
2421 return &ndev->stats;
2422
2423 if (!mdp->is_opened)
2424 return &ndev->stats;
2425
4398f9c8
BH		 2426 sh_eth_update_stat(ndev, &ndev->stats.tx_dropped, TROCR);
2427 sh_eth_update_stat(ndev, &ndev->stats.collisions, CDCR);
2428 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, LCCR);
7fa2955f
MK		 2429
2430 if (sh_eth_is_gether(mdp)) {
4398f9c8
BH		 2431 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2432 CERCR);
2433 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2434 CEECR);
7fa2955f 2435 } else {
4398f9c8
BH		 2436 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2437 CNDCR);
7fa2955f
MK		 2438 }
2439
2440 return &ndev->stats;
2441}
2442
86a74ff2
NI		 2443/* device close function */
2444static int sh_eth_close(struct net_device *ndev)
2445{
2446 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 2447
2448 netif_stop_queue(ndev);
2449
283e38db
BH		 2450 /* Serialise with the interrupt handler and NAPI, then disable
2451 * interrupts. We have to clear the irq_enabled flag first to
2452 * ensure that interrupts won't be re-enabled.
2453 */
2454 mdp->irq_enabled = false;
2455 synchronize_irq(ndev->irq);
2456 napi_disable(&mdp->napi);
4a55530f 2457 sh_eth_write(ndev, 0x0000, EESIPR);
86a74ff2 2458
740c7f31 2459 sh_eth_dev_exit(ndev);
86a74ff2
NI		 2460
2461 /* PHY Disconnect */
2462 if (mdp->phydev) {
2463 phy_stop(mdp->phydev);
2464 phy_disconnect(mdp->phydev);
4f9dce23 2465 mdp->phydev = NULL;
86a74ff2
NI		 2466 }
2467
2468 free_irq(ndev->irq, ndev);
2469
8e03a5e7 2470 /* Free all the skbuffs in the Rx queue and the DMA buffer. */
86a74ff2
NI		 2471 sh_eth_ring_free(ndev);
2472
bcd5149d
MD		 2473 pm_runtime_put_sync(&mdp->pdev->dev);
2474
7fa2955f 2475 mdp->is_opened = 0;
bcd5149d 2476
7fa2955f 2477 return 0;
86a74ff2
NI		 2478}
2479
bb7d92e3 2480/* ioctl to device function */
128296fc 2481static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
86a74ff2
NI		 2482{
2483 struct sh_eth_private *mdp = netdev_priv(ndev);
2484 struct phy_device *phydev = mdp->phydev;
2485
2486 if (!netif_running(ndev))
2487 return -EINVAL;
2488
2489 if (!phydev)
2490 return -ENODEV;
2491
28b04113 2492 return phy_mii_ioctl(phydev, rq, cmd);
86a74ff2
NI		 2493}
2494
6743fe6d
YS		 2495/* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
2496static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp,
2497 int entry)
2498{
2499 return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4);
2500}
2501
2502static u32 sh_eth_tsu_get_post_mask(int entry)
2503{
2504 return 0x0f << (28 - ((entry % 8) * 4));
2505}
2506
2507static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
2508{
2509 return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
2510}
2511
2512static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
2513 int entry)
2514{
2515 struct sh_eth_private *mdp = netdev_priv(ndev);
2516 u32 tmp;
2517 void *reg_offset;
2518
2519 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2520 tmp = ioread32(reg_offset);
2521 iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset);
2522}
2523
2524static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
2525 int entry)
2526{
2527 struct sh_eth_private *mdp = netdev_priv(ndev);
2528 u32 post_mask, ref_mask, tmp;
2529 void *reg_offset;
2530
2531 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2532 post_mask = sh_eth_tsu_get_post_mask(entry);
2533 ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
2534
2535 tmp = ioread32(reg_offset);
2536 iowrite32(tmp & ~post_mask, reg_offset);
2537
2538 /* If other port enables, the function returns "true" */
2539 return tmp & ref_mask;
2540}
2541
2542static int sh_eth_tsu_busy(struct net_device *ndev)
2543{
2544 int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
2545 struct sh_eth_private *mdp = netdev_priv(ndev);
2546
2547 while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
2548 udelay(10);
2549 timeout--;
2550 if (timeout <= 0) {
da246855 2551 netdev_err(ndev, "%s: timeout\n", __func__);
6743fe6d
YS		 2552 return -ETIMEDOUT;
2553 }
2554 }
2555
2556 return 0;
2557}
2558
2559static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg,
2560 const u8 *addr)
2561{
2562 u32 val;
2563
2564 val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
2565 iowrite32(val, reg);
2566 if (sh_eth_tsu_busy(ndev) < 0)
2567 return -EBUSY;
2568
2569 val = addr[4] << 8 | addr[5];
2570 iowrite32(val, reg + 4);
2571 if (sh_eth_tsu_busy(ndev) < 0)
2572 return -EBUSY;
2573
2574 return 0;
2575}
2576
2577static void sh_eth_tsu_read_entry(void *reg, u8 *addr)
2578{
2579 u32 val;
2580
2581 val = ioread32(reg);
2582 addr[0] = (val >> 24) & 0xff;
2583 addr[1] = (val >> 16) & 0xff;
2584 addr[2] = (val >> 8) & 0xff;
2585 addr[3] = val & 0xff;
2586 val = ioread32(reg + 4);
2587 addr[4] = (val >> 8) & 0xff;
2588 addr[5] = val & 0xff;
2589}
2590
2591
2592static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
2593{
2594 struct sh_eth_private *mdp = netdev_priv(ndev);
2595 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2596 int i;
2597 u8 c_addr[ETH_ALEN];
2598
2599 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2600 sh_eth_tsu_read_entry(reg_offset, c_addr);
c4bde29c 2601 if (ether_addr_equal(addr, c_addr))
6743fe6d
YS		 2602 return i;
2603 }
2604
2605 return -ENOENT;
2606}
2607
2608static int sh_eth_tsu_find_empty(struct net_device *ndev)
2609{
2610 u8 blank[ETH_ALEN];
2611 int entry;
2612
2613 memset(blank, 0, sizeof(blank));
2614 entry = sh_eth_tsu_find_entry(ndev, blank);
2615 return (entry < 0) ? -ENOMEM : entry;
2616}
2617
2618static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
2619 int entry)
2620{
2621 struct sh_eth_private *mdp = netdev_priv(ndev);
2622 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2623 int ret;
2624 u8 blank[ETH_ALEN];
2625
2626 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
2627 ~(1 << (31 - entry)), TSU_TEN);
2628
2629 memset(blank, 0, sizeof(blank));
2630 ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
2631 if (ret < 0)
2632 return ret;
2633 return 0;
2634}
2635
2636static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
2637{
2638 struct sh_eth_private *mdp = netdev_priv(ndev);
2639 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2640 int i, ret;
2641
2642 if (!mdp->cd->tsu)
2643 return 0;
2644
2645 i = sh_eth_tsu_find_entry(ndev, addr);
2646 if (i < 0) {
2647 /* No entry found, create one */
2648 i = sh_eth_tsu_find_empty(ndev);
2649 if (i < 0)
2650 return -ENOMEM;
2651 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
2652 if (ret < 0)
2653 return ret;
2654
2655 /* Enable the entry */
2656 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
2657 (1 << (31 - i)), TSU_TEN);
2658 }
2659
2660 /* Entry found or created, enable POST */
2661 sh_eth_tsu_enable_cam_entry_post(ndev, i);
2662
2663 return 0;
2664}
2665
2666static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
2667{
2668 struct sh_eth_private *mdp = netdev_priv(ndev);
2669 int i, ret;
2670
2671 if (!mdp->cd->tsu)
2672 return 0;
2673
2674 i = sh_eth_tsu_find_entry(ndev, addr);
2675 if (i) {
2676 /* Entry found */
2677 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2678 goto done;
2679
2680 /* Disable the entry if both ports was disabled */
2681 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2682 if (ret < 0)
2683 return ret;
2684 }
2685done:
2686 return 0;
2687}
2688
2689static int sh_eth_tsu_purge_all(struct net_device *ndev)
2690{
2691 struct sh_eth_private *mdp = netdev_priv(ndev);
2692 int i, ret;
2693
b37feed7 2694 if (!mdp->cd->tsu)
6743fe6d
YS		 2695 return 0;
2696
2697 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
2698 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2699 continue;
2700
2701 /* Disable the entry if both ports was disabled */
2702 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2703 if (ret < 0)
2704 return ret;
2705 }
2706
2707 return 0;
2708}
2709
2710static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
2711{
2712 struct sh_eth_private *mdp = netdev_priv(ndev);
2713 u8 addr[ETH_ALEN];
2714 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2715 int i;
2716
b37feed7 2717 if (!mdp->cd->tsu)
6743fe6d
YS		 2718 return;
2719
2720 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2721 sh_eth_tsu_read_entry(reg_offset, addr);
2722 if (is_multicast_ether_addr(addr))
2723 sh_eth_tsu_del_entry(ndev, addr);
2724 }
2725}
2726
b37feed7
BH		 2727/* Update promiscuous flag and multicast filter */
2728static void sh_eth_set_rx_mode(struct net_device *ndev)
86a74ff2 2729{
6743fe6d
YS		 2730 struct sh_eth_private *mdp = netdev_priv(ndev);
2731 u32 ecmr_bits;
2732 int mcast_all = 0;
2733 unsigned long flags;
2734
2735 spin_lock_irqsave(&mdp->lock, flags);
128296fc 2736 /* Initial condition is MCT = 1, PRM = 0.
6743fe6d
YS		 2737 * Depending on ndev->flags, set PRM or clear MCT
2738 */
b37feed7
BH		 2739 ecmr_bits = sh_eth_read(ndev, ECMR) & ~ECMR_PRM;
2740 if (mdp->cd->tsu)
2741 ecmr_bits |= ECMR_MCT;
6743fe6d
YS		 2742
2743 if (!(ndev->flags & IFF_MULTICAST)) {
2744 sh_eth_tsu_purge_mcast(ndev);
2745 mcast_all = 1;
2746 }
2747 if (ndev->flags & IFF_ALLMULTI) {
2748 sh_eth_tsu_purge_mcast(ndev);
2749 ecmr_bits &= ~ECMR_MCT;
2750 mcast_all = 1;
2751 }
2752
86a74ff2 2753 if (ndev->flags & IFF_PROMISC) {
6743fe6d
YS		 2754 sh_eth_tsu_purge_all(ndev);
2755 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2756 } else if (mdp->cd->tsu) {
2757 struct netdev_hw_addr *ha;
2758 netdev_for_each_mc_addr(ha, ndev) {
2759 if (mcast_all && is_multicast_ether_addr(ha->addr))
2760 continue;
2761
2762 if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2763 if (!mcast_all) {
2764 sh_eth_tsu_purge_mcast(ndev);
2765 ecmr_bits &= ~ECMR_MCT;
2766 mcast_all = 1;
2767 }
2768 }
2769 }
86a74ff2 2770 }
6743fe6d
YS		 2771
2772 /* update the ethernet mode */
2773 sh_eth_write(ndev, ecmr_bits, ECMR);
2774
2775 spin_unlock_irqrestore(&mdp->lock, flags);
86a74ff2 2776}
71cc7c37
YS		 2777
2778static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2779{
2780 if (!mdp->port)
2781 return TSU_VTAG0;
2782 else
2783 return TSU_VTAG1;
2784}
2785
80d5c368
PM		 2786static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
2787 __be16 proto, u16 vid)
71cc7c37
YS		 2788{
2789 struct sh_eth_private *mdp = netdev_priv(ndev);
2790 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2791
2792 if (unlikely(!mdp->cd->tsu))
2793 return -EPERM;
2794
2795 /* No filtering if vid = 0 */
2796 if (!vid)
2797 return 0;
2798
2799 mdp->vlan_num_ids++;
2800
128296fc 2801 /* The controller has one VLAN tag HW filter. So, if the filter is
71cc7c37
YS		 2802 * already enabled, the driver disables it and the filte
2803 */
2804 if (mdp->vlan_num_ids > 1) {
2805 /* disable VLAN filter */
2806 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2807 return 0;
2808 }
2809
2810 sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
2811 vtag_reg_index);
2812
2813 return 0;
2814}
2815
80d5c368
PM		 2816static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
2817 __be16 proto, u16 vid)
71cc7c37
YS		 2818{
2819 struct sh_eth_private *mdp = netdev_priv(ndev);
2820 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2821
2822 if (unlikely(!mdp->cd->tsu))
2823 return -EPERM;
2824
2825 /* No filtering if vid = 0 */
2826 if (!vid)
2827 return 0;
2828
2829 mdp->vlan_num_ids--;
2830 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2831
2832 return 0;
2833}
86a74ff2
NI		 2834
2835/* SuperH's TSU register init function */
4a55530f 2836static void sh_eth_tsu_init(struct sh_eth_private *mdp)
86a74ff2 2837{
db893473
SH		 2838 if (sh_eth_is_rz_fast_ether(mdp)) {
2839 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2840 return;
2841 }
2842
4a55530f
YS		 2843 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */
2844 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */
2845 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */
2846 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
2847 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
2848 sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
2849 sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
2850 sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
2851 sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
2852 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
c5ed5368
YS		 2853 if (sh_eth_is_gether(mdp)) {
2854 sh_eth_tsu_write(mdp, 0, TSU_QTAG0); /* Disable QTAG(0->1) */
2855 sh_eth_tsu_write(mdp, 0, TSU_QTAG1); /* Disable QTAG(1->0) */
2856 } else {
2857 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */
2858 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */
2859 }
4a55530f
YS		 2860 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */
2861 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */
2862 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2863 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */
2864 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */
2865 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */
2866 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */
86a74ff2
NI		 2867}
2868
2869/* MDIO bus release function */
bd920ff5 2870static int sh_mdio_release(struct sh_eth_private *mdp)
86a74ff2 2871{
86a74ff2 2872 /* unregister mdio bus */
bd920ff5 2873 mdiobus_unregister(mdp->mii_bus);
86a74ff2
NI		 2874
2875 /* free bitbang info */
bd920ff5 2876 free_mdio_bitbang(mdp->mii_bus);
86a74ff2
NI		 2877
2878 return 0;
2879}
2880
2881/* MDIO bus init function */
bd920ff5 2882static int sh_mdio_init(struct sh_eth_private *mdp,
b3017e6a 2883 struct sh_eth_plat_data *pd)
86a74ff2
NI		 2884{
2885 int ret, i;
2886 struct bb_info *bitbang;
bd920ff5 2887 struct platform_device *pdev = mdp->pdev;
aa8d4225 2888 struct device *dev = &mdp->pdev->dev;
86a74ff2
NI		 2889
2890 /* create bit control struct for PHY */
aa8d4225 2891 bitbang = devm_kzalloc(dev, sizeof(struct bb_info), GFP_KERNEL);
f738a13d
LP		 2892 if (!bitbang)
2893 return -ENOMEM;
86a74ff2
NI		 2894
2895 /* bitbang init */
ae70644d 2896 bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
b3017e6a 2897 bitbang->set_gate = pd->set_mdio_gate;
86a74ff2
NI		 2898 bitbang->ctrl.ops = &bb_ops;
2899
c2e07b3a 2900 /* MII controller setting */
86a74ff2 2901 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
f738a13d
LP		 2902 if (!mdp->mii_bus)
2903 return -ENOMEM;
86a74ff2
NI		 2904
2905 /* Hook up MII support for ethtool */
2906 mdp->mii_bus->name = "sh_mii";
a5bd6060 2907 mdp->mii_bus->parent = dev;
5278fb54 2908 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
bd920ff5 2909 pdev->name, pdev->id);
86a74ff2
NI		 2910
2911 /* PHY IRQ */
86b5d251
SS		 2912 mdp->mii_bus->irq = devm_kmalloc_array(dev, PHY_MAX_ADDR, sizeof(int),
2913 GFP_KERNEL);
86a74ff2
NI		 2914 if (!mdp->mii_bus->irq) {
2915 ret = -ENOMEM;
2916 goto out_free_bus;
2917 }
2918
bd920ff5
LP		 2919 /* register MDIO bus */
2920 if (dev->of_node) {
2921 ret = of_mdiobus_register(mdp->mii_bus, dev->of_node);
702eca02
BD		 2922 } else {
2923 for (i = 0; i < PHY_MAX_ADDR; i++)
2924 mdp->mii_bus->irq[i] = PHY_POLL;
2925 if (pd->phy_irq > 0)
2926 mdp->mii_bus->irq[pd->phy] = pd->phy_irq;
2927
2928 ret = mdiobus_register(mdp->mii_bus);
2929 }
2930
86a74ff2 2931 if (ret)
d5e07e69 2932 goto out_free_bus;
86a74ff2 2933
86a74ff2
NI		 2934 return 0;
2935
86a74ff2 2936out_free_bus:
298cf9be 2937 free_mdio_bitbang(mdp->mii_bus);
86a74ff2
NI		 2938 return ret;
2939}
2940
4a55530f
YS		 2941static const u16 *sh_eth_get_register_offset(int register_type)
2942{
2943 const u16 *reg_offset = NULL;
2944
2945 switch (register_type) {
2946 case SH_ETH_REG_GIGABIT:
2947 reg_offset = sh_eth_offset_gigabit;
2948 break;
db893473
SH		 2949 case SH_ETH_REG_FAST_RZ:
2950 reg_offset = sh_eth_offset_fast_rz;
2951 break;
a3f109bd
SS		 2952 case SH_ETH_REG_FAST_RCAR:
2953 reg_offset = sh_eth_offset_fast_rcar;
2954 break;
4a55530f
YS		 2955 case SH_ETH_REG_FAST_SH4:
2956 reg_offset = sh_eth_offset_fast_sh4;
2957 break;
2958 case SH_ETH_REG_FAST_SH3_SH2:
2959 reg_offset = sh_eth_offset_fast_sh3_sh2;
2960 break;
2961 default:
4a55530f
YS		 2962 break;
2963 }
2964
2965 return reg_offset;
2966}
2967
8f728d79 2968static const struct net_device_ops sh_eth_netdev_ops = {
ebf84eaa
AB		 2969 .ndo_open = sh_eth_open,
2970 .ndo_stop = sh_eth_close,
2971 .ndo_start_xmit = sh_eth_start_xmit,
2972 .ndo_get_stats = sh_eth_get_stats,
b37feed7 2973 .ndo_set_rx_mode = sh_eth_set_rx_mode,
ebf84eaa
AB		 2974 .ndo_tx_timeout = sh_eth_tx_timeout,
2975 .ndo_do_ioctl = sh_eth_do_ioctl,
2976 .ndo_validate_addr = eth_validate_addr,
2977 .ndo_set_mac_address = eth_mac_addr,
2978 .ndo_change_mtu = eth_change_mtu,
2979};
2980
8f728d79
SS		 2981static const struct net_device_ops sh_eth_netdev_ops_tsu = {
2982 .ndo_open = sh_eth_open,
2983 .ndo_stop = sh_eth_close,
2984 .ndo_start_xmit = sh_eth_start_xmit,
2985 .ndo_get_stats = sh_eth_get_stats,
b37feed7 2986 .ndo_set_rx_mode = sh_eth_set_rx_mode,
8f728d79
SS		 2987 .ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid,
2988 .ndo_vlan_rx_kill_vid = sh_eth_vlan_rx_kill_vid,
2989 .ndo_tx_timeout = sh_eth_tx_timeout,
2990 .ndo_do_ioctl = sh_eth_do_ioctl,
2991 .ndo_validate_addr = eth_validate_addr,
2992 .ndo_set_mac_address = eth_mac_addr,
2993 .ndo_change_mtu = eth_change_mtu,
2994};
2995
b356e978
SS		 2996#ifdef CONFIG_OF
2997static struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
2998{
2999 struct device_node *np = dev->of_node;
3000 struct sh_eth_plat_data *pdata;
b356e978
SS		 3001 const char *mac_addr;
3002
3003 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
3004 if (!pdata)
3005 return NULL;
3006
3007 pdata->phy_interface = of_get_phy_mode(np);
3008
b356e978
SS		 3009 mac_addr = of_get_mac_address(np);
3010 if (mac_addr)
3011 memcpy(pdata->mac_addr, mac_addr, ETH_ALEN);
3012
3013 pdata->no_ether_link =
3014 of_property_read_bool(np, "renesas,no-ether-link");
3015 pdata->ether_link_active_low =
3016 of_property_read_bool(np, "renesas,ether-link-active-low");
3017
3018 return pdata;
3019}
3020
3021static const struct of_device_id sh_eth_match_table[] = {
3022 { .compatible = "renesas,gether-r8a7740", .data = &r8a7740_data },
3023 { .compatible = "renesas,ether-r8a7778", .data = &r8a777x_data },
3024 { .compatible = "renesas,ether-r8a7779", .data = &r8a777x_data },
3025 { .compatible = "renesas,ether-r8a7790", .data = &r8a779x_data },
3026 { .compatible = "renesas,ether-r8a7791", .data = &r8a779x_data },
9488e1e5 3027 { .compatible = "renesas,ether-r8a7793", .data = &r8a779x_data },
0f76b9d8 3028 { .compatible = "renesas,ether-r8a7794", .data = &r8a779x_data },
b356e978
SS		 3029 { .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data },
3030 { }
3031};
3032MODULE_DEVICE_TABLE(of, sh_eth_match_table);
3033#else
3034static inline struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
3035{
3036 return NULL;
3037}
3038#endif
3039
86a74ff2
NI		 3040static int sh_eth_drv_probe(struct platform_device *pdev)
3041{
9c38657c 3042 int ret, devno = 0;
86a74ff2
NI		 3043 struct resource *res;
3044 struct net_device *ndev = NULL;
ec0d7551 3045 struct sh_eth_private *mdp = NULL;
0b76b862 3046 struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev);
afe391ad 3047 const struct platform_device_id *id = platform_get_device_id(pdev);
86a74ff2
NI		 3048
3049 /* get base addr */
3050 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
86a74ff2
NI		 3051
3052 ndev = alloc_etherdev(sizeof(struct sh_eth_private));
f738a13d
LP		 3053 if (!ndev)
3054 return -ENOMEM;
86a74ff2 3055
b5893a08
BD		 3056 pm_runtime_enable(&pdev->dev);
3057 pm_runtime_get_sync(&pdev->dev);
3058
86a74ff2
NI		 3059 devno = pdev->id;
3060 if (devno < 0)
3061 devno = 0;
3062
3063 ndev->dma = -1;
cc3c080d 3064 ret = platform_get_irq(pdev, 0);
7a468ac6 3065 if (ret < 0)
86a74ff2 3066 goto out_release;
cc3c080d 3067 ndev->irq = ret;
86a74ff2
NI		 3068
3069 SET_NETDEV_DEV(ndev, &pdev->dev);
3070
86a74ff2 3071 mdp = netdev_priv(ndev);
525b8075
YS		 3072 mdp->num_tx_ring = TX_RING_SIZE;
3073 mdp->num_rx_ring = RX_RING_SIZE;
d5e07e69
SS		 3074 mdp->addr = devm_ioremap_resource(&pdev->dev, res);
3075 if (IS_ERR(mdp->addr)) {
3076 ret = PTR_ERR(mdp->addr);
ae70644d
YS		 3077 goto out_release;
3078 }
3079
c960804f
VB		 3080 ndev->base_addr = res->start;
3081
86a74ff2 3082 spin_lock_init(&mdp->lock);
bcd5149d 3083 mdp->pdev = pdev;
86a74ff2 3084
b356e978
SS		 3085 if (pdev->dev.of_node)
3086 pd = sh_eth_parse_dt(&pdev->dev);
3b4c5cbf
SS		 3087 if (!pd) {
3088 dev_err(&pdev->dev, "no platform data\n");
3089 ret = -EINVAL;
3090 goto out_release;
3091 }
3092
86a74ff2 3093 /* get PHY ID */
71557a37 3094 mdp->phy_id = pd->phy;
e47c9052 3095 mdp->phy_interface = pd->phy_interface;
71557a37
YS		 3096 /* EDMAC endian */
3097 mdp->edmac_endian = pd->edmac_endian;
4923576b
YS		 3098 mdp->no_ether_link = pd->no_ether_link;
3099 mdp->ether_link_active_low = pd->ether_link_active_low;
86a74ff2 3100
380af9e3 3101 /* set cpu data */
b356e978
SS		 3102 if (id) {
3103 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data;
3104 } else {
3105 const struct of_device_id *match;
3106
3107 match = of_match_device(of_match_ptr(sh_eth_match_table),
3108 &pdev->dev);
3109 mdp->cd = (struct sh_eth_cpu_data *)match->data;
3110 }
a3153d8c 3111 mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type);
264be2f5
SS		 3112 if (!mdp->reg_offset) {
3113 dev_err(&pdev->dev, "Unknown register type (%d)\n",
3114 mdp->cd->register_type);
3115 ret = -EINVAL;
3116 goto out_release;
3117 }
380af9e3
YS		 3118 sh_eth_set_default_cpu_data(mdp->cd);
3119
86a74ff2 3120 /* set function */
8f728d79
SS		 3121 if (mdp->cd->tsu)
3122 ndev->netdev_ops = &sh_eth_netdev_ops_tsu;
3123 else
3124 ndev->netdev_ops = &sh_eth_netdev_ops;
7ad24ea4 3125 ndev->ethtool_ops = &sh_eth_ethtool_ops;
86a74ff2
NI		 3126 ndev->watchdog_timeo = TX_TIMEOUT;
3127
dc19e4e5
NI		 3128 /* debug message level */
3129 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
86a74ff2
NI		 3130
3131 /* read and set MAC address */
748031f9 3132 read_mac_address(ndev, pd->mac_addr);
ff6e7228
SS		 3133 if (!is_valid_ether_addr(ndev->dev_addr)) {
3134 dev_warn(&pdev->dev,
3135 "no valid MAC address supplied, using a random one.\n");
3136 eth_hw_addr_random(ndev);
3137 }
86a74ff2 3138
6ba88021
YS		 3139 /* ioremap the TSU registers */
3140 if (mdp->cd->tsu) {
3141 struct resource *rtsu;
3142 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
d5e07e69
SS		 3143 mdp->tsu_addr = devm_ioremap_resource(&pdev->dev, rtsu);
3144 if (IS_ERR(mdp->tsu_addr)) {
3145 ret = PTR_ERR(mdp->tsu_addr);
fc0c0900
SS		 3146 goto out_release;
3147 }
6743fe6d 3148 mdp->port = devno % 2;
f646968f 3149 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER;
6ba88021
YS		 3150 }
3151
150647fb
YS		 3152 /* initialize first or needed device */
3153 if (!devno || pd->needs_init) {
380af9e3
YS		 3154 if (mdp->cd->chip_reset)
3155 mdp->cd->chip_reset(ndev);
86a74ff2 3156
4986b996
YS		 3157 if (mdp->cd->tsu) {
3158 /* TSU init (Init only)*/
3159 sh_eth_tsu_init(mdp);
3160 }
86a74ff2
NI		 3161 }
3162
966d6dbb
HN		 3163 if (mdp->cd->rmiimode)
3164 sh_eth_write(ndev, 0x1, RMIIMODE);
3165
daacf03f
LP		 3166 /* MDIO bus init */
3167 ret = sh_mdio_init(mdp, pd);
3168 if (ret) {
3169 dev_err(&ndev->dev, "failed to initialise MDIO\n");
3170 goto out_release;
3171 }
3172
3719109d
SS		 3173 netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64);
3174
86a74ff2
NI		 3175 /* network device register */
3176 ret = register_netdev(ndev);
3177 if (ret)
3719109d 3178 goto out_napi_del;
86a74ff2 3179
25985edc 3180 /* print device information */
f75f14ec
SS		 3181 netdev_info(ndev, "Base address at 0x%x, %pM, IRQ %d.\n",
3182 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
86a74ff2 3183
b5893a08 3184 pm_runtime_put(&pdev->dev);
86a74ff2
NI		 3185 platform_set_drvdata(pdev, ndev);
3186
3187 return ret;
3188
3719109d
SS		 3189out_napi_del:
3190 netif_napi_del(&mdp->napi);
daacf03f 3191 sh_mdio_release(mdp);
3719109d 3192
86a74ff2
NI		 3193out_release:
3194 /* net_dev free */
3195 if (ndev)
3196 free_netdev(ndev);
3197
b5893a08
BD		 3198 pm_runtime_put(&pdev->dev);
3199 pm_runtime_disable(&pdev->dev);
86a74ff2
NI		 3200 return ret;
3201}
3202
3203static int sh_eth_drv_remove(struct platform_device *pdev)
3204{
3205 struct net_device *ndev = platform_get_drvdata(pdev);
3719109d 3206 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2 3207
86a74ff2 3208 unregister_netdev(ndev);
3719109d 3209 netif_napi_del(&mdp->napi);
daacf03f 3210 sh_mdio_release(mdp);
bcd5149d 3211 pm_runtime_disable(&pdev->dev);
86a74ff2 3212 free_netdev(ndev);
86a74ff2
NI		 3213
3214 return 0;
3215}
3216
540ad1b8 3217#ifdef CONFIG_PM
b71af046
MU		 3218#ifdef CONFIG_PM_SLEEP
3219static int sh_eth_suspend(struct device *dev)
3220{
3221 struct net_device *ndev = dev_get_drvdata(dev);
3222 int ret = 0;
3223
3224 if (netif_running(ndev)) {
3225 netif_device_detach(ndev);
3226 ret = sh_eth_close(ndev);
3227 }
3228
3229 return ret;
3230}
3231
3232static int sh_eth_resume(struct device *dev)
3233{
3234 struct net_device *ndev = dev_get_drvdata(dev);
3235 int ret = 0;
3236
3237 if (netif_running(ndev)) {
3238 ret = sh_eth_open(ndev);
3239 if (ret < 0)
3240 return ret;
3241 netif_device_attach(ndev);
3242 }
3243
3244 return ret;
3245}
3246#endif
3247
bcd5149d
MD		 3248static int sh_eth_runtime_nop(struct device *dev)
3249{
128296fc 3250 /* Runtime PM callback shared between ->runtime_suspend()
bcd5149d
MD		 3251 * and ->runtime_resume(). Simply returns success.
3252 *
3253 * This driver re-initializes all registers after
3254 * pm_runtime_get_sync() anyway so there is no need
3255 * to save and restore registers here.
3256 */
3257 return 0;
3258}
3259
540ad1b8 3260static const struct dev_pm_ops sh_eth_dev_pm_ops = {
b71af046 3261 SET_SYSTEM_SLEEP_PM_OPS(sh_eth_suspend, sh_eth_resume)
e7d7e898 3262 SET_RUNTIME_PM_OPS(sh_eth_runtime_nop, sh_eth_runtime_nop, NULL)
bcd5149d 3263};
540ad1b8
NI		 3264#define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
3265#else
3266#define SH_ETH_PM_OPS NULL
3267#endif
bcd5149d 3268
afe391ad 3269static struct platform_device_id sh_eth_id_table[] = {
c18a79ab 3270 { "sh7619-ether", (kernel_ulong_t)&sh7619_data },
7bbe150d 3271 { "sh771x-ether", (kernel_ulong_t)&sh771x_data },
9c3beaab 3272 { "sh7724-ether", (kernel_ulong_t)&sh7724_data },
f5d12767 3273 { "sh7734-gether", (kernel_ulong_t)&sh7734_data },
24549e2a
SS		 3274 { "sh7757-ether", (kernel_ulong_t)&sh7757_data },
3275 { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga },
f5d12767 3276 { "sh7763-gether", (kernel_ulong_t)&sh7763_data },
afe391ad
SS		 3277 { }
3278};
3279MODULE_DEVICE_TABLE(platform, sh_eth_id_table);
3280
86a74ff2
NI		 3281static struct platform_driver sh_eth_driver = {
3282 .probe = sh_eth_drv_probe,
3283 .remove = sh_eth_drv_remove,
afe391ad 3284 .id_table = sh_eth_id_table,
86a74ff2
NI		 3285 .driver = {
3286 .name = CARDNAME,
540ad1b8 3287 .pm = SH_ETH_PM_OPS,
b356e978 3288 .of_match_table = of_match_ptr(sh_eth_match_table),
86a74ff2
NI		 3289 },
3290};
3291
db62f684 3292module_platform_driver(sh_eth_driver);
86a74ff2
NI		 3293
3294MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
3295MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
3296MODULE_LICENSE("GPL v2");
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