]> git.proxmox.com Git - mirror_ubuntu-zesty-kernel.git/blame - drivers/net/ethernet/renesas/sh_eth.c
projects / mirror_ubuntu-zesty-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
sh_eth: WARN on access to a register not implemented in a particular chip
[mirror_ubuntu-zesty-kernel.git] / drivers / net / ethernet / renesas / sh_eth.c
CommitLineData
128296fc 1/* SuperH Ethernet device driver
86a74ff2 2 *
966d6dbb 3 * Copyright (C) 2014 Renesas Electronics Corporation
f0e81fec 4 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu
b356e978
SS		 5 * Copyright (C) 2008-2014 Renesas Solutions Corp.
6 * Copyright (C) 2013-2014 Cogent Embedded, Inc.
702eca02 7 * Copyright (C) 2014 Codethink Limited
86a74ff2
NI		 8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms and conditions of the GNU General Public License,
11 * version 2, as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
86a74ff2
NI		 17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 */
21
0654011d
YS		 22#include <linux/module.h>
23#include <linux/kernel.h>
24#include <linux/spinlock.h>
6a27cded 25#include <linux/interrupt.h>
86a74ff2
NI		 26#include <linux/dma-mapping.h>
27#include <linux/etherdevice.h>
28#include <linux/delay.h>
29#include <linux/platform_device.h>
30#include <linux/mdio-bitbang.h>
31#include <linux/netdevice.h>
b356e978
SS		 32#include <linux/of.h>
33#include <linux/of_device.h>
34#include <linux/of_irq.h>
35#include <linux/of_net.h>
86a74ff2
NI		 36#include <linux/phy.h>
37#include <linux/cache.h>
38#include <linux/io.h>
bcd5149d 39#include <linux/pm_runtime.h>
5a0e3ad6 40#include <linux/slab.h>
dc19e4e5 41#include <linux/ethtool.h>
fdb37a7f 42#include <linux/if_vlan.h>
f0e81fec 43#include <linux/clk.h>
d4fa0e35 44#include <linux/sh_eth.h>
702eca02 45#include <linux/of_mdio.h>
86a74ff2
NI		 46
47#include "sh_eth.h"
48
dc19e4e5
NI		 49#define SH_ETH_DEF_MSG_ENABLE \
50 (NETIF_MSG_LINK | \
51 NETIF_MSG_TIMER | \
52 NETIF_MSG_RX_ERR| \
53 NETIF_MSG_TX_ERR)
54
3365711d
BH		 55#define SH_ETH_OFFSET_DEFAULTS \
56 [0 ... SH_ETH_MAX_REGISTER_OFFSET - 1] = SH_ETH_OFFSET_INVALID
57
c0013f6f 58static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
3365711d
BH		 59 SH_ETH_OFFSET_DEFAULTS,
60
c0013f6f
SS		 61 [EDSR] = 0x0000,
62 [EDMR] = 0x0400,
63 [EDTRR] = 0x0408,
64 [EDRRR] = 0x0410,
65 [EESR] = 0x0428,
66 [EESIPR] = 0x0430,
67 [TDLAR] = 0x0010,
68 [TDFAR] = 0x0014,
69 [TDFXR] = 0x0018,
70 [TDFFR] = 0x001c,
71 [RDLAR] = 0x0030,
72 [RDFAR] = 0x0034,
73 [RDFXR] = 0x0038,
74 [RDFFR] = 0x003c,
75 [TRSCER] = 0x0438,
76 [RMFCR] = 0x0440,
77 [TFTR] = 0x0448,
78 [FDR] = 0x0450,
79 [RMCR] = 0x0458,
80 [RPADIR] = 0x0460,
81 [FCFTR] = 0x0468,
82 [CSMR] = 0x04E4,
83
84 [ECMR] = 0x0500,
85 [ECSR] = 0x0510,
86 [ECSIPR] = 0x0518,
87 [PIR] = 0x0520,
88 [PSR] = 0x0528,
89 [PIPR] = 0x052c,
90 [RFLR] = 0x0508,
91 [APR] = 0x0554,
92 [MPR] = 0x0558,
93 [PFTCR] = 0x055c,
94 [PFRCR] = 0x0560,
95 [TPAUSER] = 0x0564,
96 [GECMR] = 0x05b0,
97 [BCULR] = 0x05b4,
98 [MAHR] = 0x05c0,
99 [MALR] = 0x05c8,
100 [TROCR] = 0x0700,
101 [CDCR] = 0x0708,
102 [LCCR] = 0x0710,
103 [CEFCR] = 0x0740,
104 [FRECR] = 0x0748,
105 [TSFRCR] = 0x0750,
106 [TLFRCR] = 0x0758,
107 [RFCR] = 0x0760,
108 [CERCR] = 0x0768,
109 [CEECR] = 0x0770,
110 [MAFCR] = 0x0778,
111 [RMII_MII] = 0x0790,
112
113 [ARSTR] = 0x0000,
114 [TSU_CTRST] = 0x0004,
115 [TSU_FWEN0] = 0x0010,
116 [TSU_FWEN1] = 0x0014,
117 [TSU_FCM] = 0x0018,
118 [TSU_BSYSL0] = 0x0020,
119 [TSU_BSYSL1] = 0x0024,
120 [TSU_PRISL0] = 0x0028,
121 [TSU_PRISL1] = 0x002c,
122 [TSU_FWSL0] = 0x0030,
123 [TSU_FWSL1] = 0x0034,
124 [TSU_FWSLC] = 0x0038,
125 [TSU_QTAG0] = 0x0040,
126 [TSU_QTAG1] = 0x0044,
127 [TSU_FWSR] = 0x0050,
128 [TSU_FWINMK] = 0x0054,
129 [TSU_ADQT0] = 0x0048,
130 [TSU_ADQT1] = 0x004c,
131 [TSU_VTAG0] = 0x0058,
132 [TSU_VTAG1] = 0x005c,
133 [TSU_ADSBSY] = 0x0060,
134 [TSU_TEN] = 0x0064,
135 [TSU_POST1] = 0x0070,
136 [TSU_POST2] = 0x0074,
137 [TSU_POST3] = 0x0078,
138 [TSU_POST4] = 0x007c,
139 [TSU_ADRH0] = 0x0100,
140 [TSU_ADRL0] = 0x0104,
141 [TSU_ADRH31] = 0x01f8,
142 [TSU_ADRL31] = 0x01fc,
143
144 [TXNLCR0] = 0x0080,
145 [TXALCR0] = 0x0084,
146 [RXNLCR0] = 0x0088,
147 [RXALCR0] = 0x008c,
148 [FWNLCR0] = 0x0090,
149 [FWALCR0] = 0x0094,
150 [TXNLCR1] = 0x00a0,
151 [TXALCR1] = 0x00a0,
152 [RXNLCR1] = 0x00a8,
153 [RXALCR1] = 0x00ac,
154 [FWNLCR1] = 0x00b0,
155 [FWALCR1] = 0x00b4,
156};
157
db893473 158static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
3365711d
BH		 159 SH_ETH_OFFSET_DEFAULTS,
160
db893473
SH		 161 [EDSR] = 0x0000,
162 [EDMR] = 0x0400,
163 [EDTRR] = 0x0408,
164 [EDRRR] = 0x0410,
165 [EESR] = 0x0428,
166 [EESIPR] = 0x0430,
167 [TDLAR] = 0x0010,
168 [TDFAR] = 0x0014,
169 [TDFXR] = 0x0018,
170 [TDFFR] = 0x001c,
171 [RDLAR] = 0x0030,
172 [RDFAR] = 0x0034,
173 [RDFXR] = 0x0038,
174 [RDFFR] = 0x003c,
175 [TRSCER] = 0x0438,
176 [RMFCR] = 0x0440,
177 [TFTR] = 0x0448,
178 [FDR] = 0x0450,
179 [RMCR] = 0x0458,
180 [RPADIR] = 0x0460,
181 [FCFTR] = 0x0468,
182 [CSMR] = 0x04E4,
183
184 [ECMR] = 0x0500,
185 [RFLR] = 0x0508,
186 [ECSR] = 0x0510,
187 [ECSIPR] = 0x0518,
188 [PIR] = 0x0520,
189 [APR] = 0x0554,
190 [MPR] = 0x0558,
191 [PFTCR] = 0x055c,
192 [PFRCR] = 0x0560,
193 [TPAUSER] = 0x0564,
194 [MAHR] = 0x05c0,
195 [MALR] = 0x05c8,
196 [CEFCR] = 0x0740,
197 [FRECR] = 0x0748,
198 [TSFRCR] = 0x0750,
199 [TLFRCR] = 0x0758,
200 [RFCR] = 0x0760,
201 [MAFCR] = 0x0778,
202
203 [ARSTR] = 0x0000,
204 [TSU_CTRST] = 0x0004,
205 [TSU_VTAG0] = 0x0058,
206 [TSU_ADSBSY] = 0x0060,
207 [TSU_TEN] = 0x0064,
208 [TSU_ADRH0] = 0x0100,
209 [TSU_ADRL0] = 0x0104,
210 [TSU_ADRH31] = 0x01f8,
211 [TSU_ADRL31] = 0x01fc,
212
213 [TXNLCR0] = 0x0080,
214 [TXALCR0] = 0x0084,
215 [RXNLCR0] = 0x0088,
216 [RXALCR0] = 0x008C,
217};
218
a3f109bd 219static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
3365711d
BH		 220 SH_ETH_OFFSET_DEFAULTS,
221
a3f109bd
SS		 222 [ECMR] = 0x0300,
223 [RFLR] = 0x0308,
224 [ECSR] = 0x0310,
225 [ECSIPR] = 0x0318,
226 [PIR] = 0x0320,
227 [PSR] = 0x0328,
228 [RDMLR] = 0x0340,
229 [IPGR] = 0x0350,
230 [APR] = 0x0354,
231 [MPR] = 0x0358,
232 [RFCF] = 0x0360,
233 [TPAUSER] = 0x0364,
234 [TPAUSECR] = 0x0368,
235 [MAHR] = 0x03c0,
236 [MALR] = 0x03c8,
237 [TROCR] = 0x03d0,
238 [CDCR] = 0x03d4,
239 [LCCR] = 0x03d8,
240 [CNDCR] = 0x03dc,
241 [CEFCR] = 0x03e4,
242 [FRECR] = 0x03e8,
243 [TSFRCR] = 0x03ec,
244 [TLFRCR] = 0x03f0,
245 [RFCR] = 0x03f4,
246 [MAFCR] = 0x03f8,
247
248 [EDMR] = 0x0200,
249 [EDTRR] = 0x0208,
250 [EDRRR] = 0x0210,
251 [TDLAR] = 0x0218,
252 [RDLAR] = 0x0220,
253 [EESR] = 0x0228,
254 [EESIPR] = 0x0230,
255 [TRSCER] = 0x0238,
256 [RMFCR] = 0x0240,
257 [TFTR] = 0x0248,
258 [FDR] = 0x0250,
259 [RMCR] = 0x0258,
260 [TFUCR] = 0x0264,
261 [RFOCR] = 0x0268,
55754f19 262 [RMIIMODE] = 0x026c,
a3f109bd
SS		 263 [FCFTR] = 0x0270,
264 [TRIMD] = 0x027c,
265};
266
c0013f6f 267static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
3365711d
BH		 268 SH_ETH_OFFSET_DEFAULTS,
269
c0013f6f
SS		 270 [ECMR] = 0x0100,
271 [RFLR] = 0x0108,
272 [ECSR] = 0x0110,
273 [ECSIPR] = 0x0118,
274 [PIR] = 0x0120,
275 [PSR] = 0x0128,
276 [RDMLR] = 0x0140,
277 [IPGR] = 0x0150,
278 [APR] = 0x0154,
279 [MPR] = 0x0158,
280 [TPAUSER] = 0x0164,
281 [RFCF] = 0x0160,
282 [TPAUSECR] = 0x0168,
283 [BCFRR] = 0x016c,
284 [MAHR] = 0x01c0,
285 [MALR] = 0x01c8,
286 [TROCR] = 0x01d0,
287 [CDCR] = 0x01d4,
288 [LCCR] = 0x01d8,
289 [CNDCR] = 0x01dc,
290 [CEFCR] = 0x01e4,
291 [FRECR] = 0x01e8,
292 [TSFRCR] = 0x01ec,
293 [TLFRCR] = 0x01f0,
294 [RFCR] = 0x01f4,
295 [MAFCR] = 0x01f8,
296 [RTRATE] = 0x01fc,
297
298 [EDMR] = 0x0000,
299 [EDTRR] = 0x0008,
300 [EDRRR] = 0x0010,
301 [TDLAR] = 0x0018,
302 [RDLAR] = 0x0020,
303 [EESR] = 0x0028,
304 [EESIPR] = 0x0030,
305 [TRSCER] = 0x0038,
306 [RMFCR] = 0x0040,
307 [TFTR] = 0x0048,
308 [FDR] = 0x0050,
309 [RMCR] = 0x0058,
310 [TFUCR] = 0x0064,
311 [RFOCR] = 0x0068,
312 [FCFTR] = 0x0070,
313 [RPADIR] = 0x0078,
314 [TRIMD] = 0x007c,
315 [RBWAR] = 0x00c8,
316 [RDFAR] = 0x00cc,
317 [TBRAR] = 0x00d4,
318 [TDFAR] = 0x00d8,
319};
320
321static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
3365711d
BH		 322 SH_ETH_OFFSET_DEFAULTS,
323
d8b0426a
SS		 324 [EDMR] = 0x0000,
325 [EDTRR] = 0x0004,
326 [EDRRR] = 0x0008,
327 [TDLAR] = 0x000c,
328 [RDLAR] = 0x0010,
329 [EESR] = 0x0014,
330 [EESIPR] = 0x0018,
331 [TRSCER] = 0x001c,
332 [RMFCR] = 0x0020,
333 [TFTR] = 0x0024,
334 [FDR] = 0x0028,
335 [RMCR] = 0x002c,
336 [EDOCR] = 0x0030,
337 [FCFTR] = 0x0034,
338 [RPADIR] = 0x0038,
339 [TRIMD] = 0x003c,
340 [RBWAR] = 0x0040,
341 [RDFAR] = 0x0044,
342 [TBRAR] = 0x004c,
343 [TDFAR] = 0x0050,
344
c0013f6f
SS		 345 [ECMR] = 0x0160,
346 [ECSR] = 0x0164,
347 [ECSIPR] = 0x0168,
348 [PIR] = 0x016c,
349 [MAHR] = 0x0170,
350 [MALR] = 0x0174,
351 [RFLR] = 0x0178,
352 [PSR] = 0x017c,
353 [TROCR] = 0x0180,
354 [CDCR] = 0x0184,
355 [LCCR] = 0x0188,
356 [CNDCR] = 0x018c,
357 [CEFCR] = 0x0194,
358 [FRECR] = 0x0198,
359 [TSFRCR] = 0x019c,
360 [TLFRCR] = 0x01a0,
361 [RFCR] = 0x01a4,
362 [MAFCR] = 0x01a8,
363 [IPGR] = 0x01b4,
364 [APR] = 0x01b8,
365 [MPR] = 0x01bc,
366 [TPAUSER] = 0x01c4,
367 [BCFR] = 0x01cc,
368
369 [ARSTR] = 0x0000,
370 [TSU_CTRST] = 0x0004,
371 [TSU_FWEN0] = 0x0010,
372 [TSU_FWEN1] = 0x0014,
373 [TSU_FCM] = 0x0018,
374 [TSU_BSYSL0] = 0x0020,
375 [TSU_BSYSL1] = 0x0024,
376 [TSU_PRISL0] = 0x0028,
377 [TSU_PRISL1] = 0x002c,
378 [TSU_FWSL0] = 0x0030,
379 [TSU_FWSL1] = 0x0034,
380 [TSU_FWSLC] = 0x0038,
381 [TSU_QTAGM0] = 0x0040,
382 [TSU_QTAGM1] = 0x0044,
383 [TSU_ADQT0] = 0x0048,
384 [TSU_ADQT1] = 0x004c,
385 [TSU_FWSR] = 0x0050,
386 [TSU_FWINMK] = 0x0054,
387 [TSU_ADSBSY] = 0x0060,
388 [TSU_TEN] = 0x0064,
389 [TSU_POST1] = 0x0070,
390 [TSU_POST2] = 0x0074,
391 [TSU_POST3] = 0x0078,
392 [TSU_POST4] = 0x007c,
393
394 [TXNLCR0] = 0x0080,
395 [TXALCR0] = 0x0084,
396 [RXNLCR0] = 0x0088,
397 [RXALCR0] = 0x008c,
398 [FWNLCR0] = 0x0090,
399 [FWALCR0] = 0x0094,
400 [TXNLCR1] = 0x00a0,
401 [TXALCR1] = 0x00a0,
402 [RXNLCR1] = 0x00a8,
403 [RXALCR1] = 0x00ac,
404 [FWNLCR1] = 0x00b0,
405 [FWALCR1] = 0x00b4,
406
407 [TSU_ADRH0] = 0x0100,
408 [TSU_ADRL0] = 0x0104,
409 [TSU_ADRL31] = 0x01fc,
410};
411
740c7f31
BH		 412static void sh_eth_rcv_snd_disable(struct net_device *ndev);
413static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev);
414
504c8ca5 415static bool sh_eth_is_gether(struct sh_eth_private *mdp)
dabdde9e 416{
504c8ca5 417 return mdp->reg_offset == sh_eth_offset_gigabit;
dabdde9e
NI		 418}
419
db893473
SH		 420static bool sh_eth_is_rz_fast_ether(struct sh_eth_private *mdp)
421{
422 return mdp->reg_offset == sh_eth_offset_fast_rz;
423}
424
8e994402 425static void sh_eth_select_mii(struct net_device *ndev)
5e7a76be
NI		 426{
427 u32 value = 0x0;
428 struct sh_eth_private *mdp = netdev_priv(ndev);
429
430 switch (mdp->phy_interface) {
431 case PHY_INTERFACE_MODE_GMII:
432 value = 0x2;
433 break;
434 case PHY_INTERFACE_MODE_MII:
435 value = 0x1;
436 break;
437 case PHY_INTERFACE_MODE_RMII:
438 value = 0x0;
439 break;
440 default:
f75f14ec
SS		 441 netdev_warn(ndev,
442 "PHY interface mode was not setup. Set to MII.\n");
5e7a76be
NI		 443 value = 0x1;
444 break;
445 }
446
447 sh_eth_write(ndev, value, RMII_MII);
448}
5e7a76be 449
8e994402 450static void sh_eth_set_duplex(struct net_device *ndev)
65ac8851
YS		 451{
452 struct sh_eth_private *mdp = netdev_priv(ndev);
65ac8851
YS		 453
454 if (mdp->duplex) /* Full */
4a55530f 455 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
65ac8851 456 else /* Half */
4a55530f 457 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
65ac8851
YS		 458}
459
04b0ed2a 460/* There is CPU dependent code */
589ebdef 461static void sh_eth_set_rate_r8a777x(struct net_device *ndev)
65ac8851
YS		 462{
463 struct sh_eth_private *mdp = netdev_priv(ndev);
d0418bb7 464
a3f109bd
SS		 465 switch (mdp->speed) {
466 case 10: /* 10BASE */
467 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_ELB, ECMR);
468 break;
469 case 100:/* 100BASE */
470 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_ELB, ECMR);
471 break;
472 default:
473 break;
474 }
475}
476
674853b2 477/* R8A7778/9 */
589ebdef 478static struct sh_eth_cpu_data r8a777x_data = {
a3f109bd 479 .set_duplex = sh_eth_set_duplex,
589ebdef 480 .set_rate = sh_eth_set_rate_r8a777x,
a3f109bd 481
a3153d8c
SS		 482 .register_type = SH_ETH_REG_FAST_RCAR,
483
a3f109bd
SS		 484 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
485 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
486 .eesipr_value = 0x01ff009f,
487
488 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
ca8c3585
SS		 489 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
490 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
491 EESR_ECI,
d407bc02 492 .fdr_value = 0x00000f0f,
a3f109bd
SS		 493
494 .apr = 1,
495 .mpr = 1,
496 .tpauser = 1,
497 .hw_swap = 1,
498};
a3f109bd 499
94a12b15
SS		 500/* R8A7790/1 */
501static struct sh_eth_cpu_data r8a779x_data = {
e18dbf7e
SH		 502 .set_duplex = sh_eth_set_duplex,
503 .set_rate = sh_eth_set_rate_r8a777x,
504
a3153d8c
SS		 505 .register_type = SH_ETH_REG_FAST_RCAR,
506
e18dbf7e
SH		 507 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
508 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
509 .eesipr_value = 0x01ff009f,
510
511 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
ba361cb3
LP		 512 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
513 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
514 EESR_ECI,
d407bc02 515 .fdr_value = 0x00000f0f,
e18dbf7e 516
01fbd3f5
GU		 517 .trscer_err_mask = DESC_I_RINT8,
518
e18dbf7e
SH		 519 .apr = 1,
520 .mpr = 1,
521 .tpauser = 1,
522 .hw_swap = 1,
523 .rmiimode = 1,
524};
525
9c3beaab 526static void sh_eth_set_rate_sh7724(struct net_device *ndev)
a3f109bd
SS		 527{
528 struct sh_eth_private *mdp = netdev_priv(ndev);
65ac8851
YS		 529
530 switch (mdp->speed) {
531 case 10: /* 10BASE */
a3f109bd 532 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_RTM, ECMR);
65ac8851
YS		 533 break;
534 case 100:/* 100BASE */
a3f109bd 535 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_RTM, ECMR);
65ac8851
YS		 536 break;
537 default:
538 break;
539 }
540}
541
542/* SH7724 */
9c3beaab 543static struct sh_eth_cpu_data sh7724_data = {
65ac8851 544 .set_duplex = sh_eth_set_duplex,
9c3beaab 545 .set_rate = sh_eth_set_rate_sh7724,
65ac8851 546
a3153d8c
SS		 547 .register_type = SH_ETH_REG_FAST_SH4,
548
65ac8851
YS		 549 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
550 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
a80c3de7 551 .eesipr_value = 0x01ff009f,
65ac8851
YS		 552
553 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
ca8c3585
SS		 554 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
555 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
556 EESR_ECI,
65ac8851
YS		 557
558 .apr = 1,
559 .mpr = 1,
560 .tpauser = 1,
561 .hw_swap = 1,
503914cf
MD		 562 .rpadir = 1,
563 .rpadir_value = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
65ac8851 564};
5cee1d37 565
24549e2a 566static void sh_eth_set_rate_sh7757(struct net_device *ndev)
f29a3d04
YS		 567{
568 struct sh_eth_private *mdp = netdev_priv(ndev);
f29a3d04
YS		 569
570 switch (mdp->speed) {
571 case 10: /* 10BASE */
4a55530f 572 sh_eth_write(ndev, 0, RTRATE);
f29a3d04
YS		 573 break;
574 case 100:/* 100BASE */
4a55530f 575 sh_eth_write(ndev, 1, RTRATE);
f29a3d04
YS		 576 break;
577 default:
578 break;
579 }
580}
581
582/* SH7757 */
24549e2a
SS		 583static struct sh_eth_cpu_data sh7757_data = {
584 .set_duplex = sh_eth_set_duplex,
585 .set_rate = sh_eth_set_rate_sh7757,
f29a3d04 586
a3153d8c
SS		 587 .register_type = SH_ETH_REG_FAST_SH4,
588
f29a3d04 589 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
f29a3d04
YS		 590
591 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
ca8c3585
SS		 592 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
593 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
594 EESR_ECI,
f29a3d04 595
5b3dfd13 596 .irq_flags = IRQF_SHARED,
f29a3d04
YS		 597 .apr = 1,
598 .mpr = 1,
599 .tpauser = 1,
600 .hw_swap = 1,
601 .no_ade = 1,
2e98e797
YS		 602 .rpadir = 1,
603 .rpadir_value = 2 << 16,
f29a3d04 604};
65ac8851 605
e403d295 606#define SH_GIGA_ETH_BASE 0xfee00000UL
8fcd4961
YS		 607#define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
608#define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
609static void sh_eth_chip_reset_giga(struct net_device *ndev)
610{
611 int i;
0799c2d6 612 u32 mahr[2], malr[2];
8fcd4961
YS		 613
614 /* save MAHR and MALR */
615 for (i = 0; i < 2; i++) {
ae70644d
YS		 616 malr[i] = ioread32((void *)GIGA_MALR(i));
617 mahr[i] = ioread32((void *)GIGA_MAHR(i));
8fcd4961
YS		 618 }
619
620 /* reset device */
ae70644d 621 iowrite32(ARSTR_ARSTR, (void *)(SH_GIGA_ETH_BASE + 0x1800));
8fcd4961
YS		 622 mdelay(1);
623
624 /* restore MAHR and MALR */
625 for (i = 0; i < 2; i++) {
ae70644d
YS		 626 iowrite32(malr[i], (void *)GIGA_MALR(i));
627 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
8fcd4961
YS		 628 }
629}
630
8fcd4961
YS		 631static void sh_eth_set_rate_giga(struct net_device *ndev)
632{
633 struct sh_eth_private *mdp = netdev_priv(ndev);
634
635 switch (mdp->speed) {
636 case 10: /* 10BASE */
637 sh_eth_write(ndev, 0x00000000, GECMR);
638 break;
639 case 100:/* 100BASE */
640 sh_eth_write(ndev, 0x00000010, GECMR);
641 break;
642 case 1000: /* 1000BASE */
643 sh_eth_write(ndev, 0x00000020, GECMR);
644 break;
645 default:
646 break;
647 }
648}
649
650/* SH7757(GETHERC) */
24549e2a 651static struct sh_eth_cpu_data sh7757_data_giga = {
8fcd4961 652 .chip_reset = sh_eth_chip_reset_giga,
04b0ed2a 653 .set_duplex = sh_eth_set_duplex,
8fcd4961
YS		 654 .set_rate = sh_eth_set_rate_giga,
655
a3153d8c
SS		 656 .register_type = SH_ETH_REG_GIGABIT,
657
8fcd4961
YS		 658 .ecsr_value = ECSR_ICD | ECSR_MPD,
659 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
660 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
661
662 .tx_check = EESR_TC1 | EESR_FTC,
ca8c3585
SS		 663 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
664 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
665 EESR_TDE | EESR_ECI,
8fcd4961 666 .fdr_value = 0x0000072f,
8fcd4961 667
5b3dfd13 668 .irq_flags = IRQF_SHARED,
8fcd4961
YS		 669 .apr = 1,
670 .mpr = 1,
671 .tpauser = 1,
672 .bculr = 1,
673 .hw_swap = 1,
674 .rpadir = 1,
675 .rpadir_value = 2 << 16,
676 .no_trimd = 1,
677 .no_ade = 1,
3acbc971 678 .tsu = 1,
8fcd4961
YS		 679};
680
380af9e3
YS		 681static void sh_eth_chip_reset(struct net_device *ndev)
682{
4986b996
YS		 683 struct sh_eth_private *mdp = netdev_priv(ndev);
684
380af9e3 685 /* reset device */
4986b996 686 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
380af9e3
YS		 687 mdelay(1);
688}
689
f5d12767 690static void sh_eth_set_rate_gether(struct net_device *ndev)
380af9e3
YS		 691{
692 struct sh_eth_private *mdp = netdev_priv(ndev);
380af9e3
YS		 693
694 switch (mdp->speed) {
695 case 10: /* 10BASE */
4a55530f 696 sh_eth_write(ndev, GECMR_10, GECMR);
380af9e3
YS		 697 break;
698 case 100:/* 100BASE */
4a55530f 699 sh_eth_write(ndev, GECMR_100, GECMR);
380af9e3
YS		 700 break;
701 case 1000: /* 1000BASE */
4a55530f 702 sh_eth_write(ndev, GECMR_1000, GECMR);
380af9e3
YS		 703 break;
704 default:
705 break;
706 }
707}
708
f5d12767
SS		 709/* SH7734 */
710static struct sh_eth_cpu_data sh7734_data = {
380af9e3
YS		 711 .chip_reset = sh_eth_chip_reset,
712 .set_duplex = sh_eth_set_duplex,
f5d12767
SS		 713 .set_rate = sh_eth_set_rate_gether,
714
a3153d8c
SS		 715 .register_type = SH_ETH_REG_GIGABIT,
716
f5d12767
SS		 717 .ecsr_value = ECSR_ICD | ECSR_MPD,
718 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
719 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
720
721 .tx_check = EESR_TC1 | EESR_FTC,
ca8c3585
SS		 722 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
723 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
724 EESR_TDE | EESR_ECI,
f5d12767
SS		 725
726 .apr = 1,
727 .mpr = 1,
728 .tpauser = 1,
729 .bculr = 1,
730 .hw_swap = 1,
731 .no_trimd = 1,
732 .no_ade = 1,
733 .tsu = 1,
734 .hw_crc = 1,
735 .select_mii = 1,
736};
737
738/* SH7763 */
739static struct sh_eth_cpu_data sh7763_data = {
740 .chip_reset = sh_eth_chip_reset,
741 .set_duplex = sh_eth_set_duplex,
742 .set_rate = sh_eth_set_rate_gether,
380af9e3 743
a3153d8c
SS		 744 .register_type = SH_ETH_REG_GIGABIT,
745
380af9e3
YS		 746 .ecsr_value = ECSR_ICD | ECSR_MPD,
747 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
748 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
749
750 .tx_check = EESR_TC1 | EESR_FTC,
128296fc
SS		 751 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
752 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
380af9e3 753 EESR_ECI,
380af9e3
YS		 754
755 .apr = 1,
756 .mpr = 1,
757 .tpauser = 1,
758 .bculr = 1,
759 .hw_swap = 1,
380af9e3
YS		 760 .no_trimd = 1,
761 .no_ade = 1,
4986b996 762 .tsu = 1,
5b3dfd13 763 .irq_flags = IRQF_SHARED,
380af9e3
YS		 764};
765
e5c9b4cd 766static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
73a0d907
YS		 767{
768 struct sh_eth_private *mdp = netdev_priv(ndev);
73a0d907
YS		 769
770 /* reset device */
771 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
772 mdelay(1);
773
5e7a76be 774 sh_eth_select_mii(ndev);
73a0d907
YS		 775}
776
73a0d907 777/* R8A7740 */
e5c9b4cd
SS		 778static struct sh_eth_cpu_data r8a7740_data = {
779 .chip_reset = sh_eth_chip_reset_r8a7740,
73a0d907 780 .set_duplex = sh_eth_set_duplex,
e5c9b4cd 781 .set_rate = sh_eth_set_rate_gether,
73a0d907 782
a3153d8c
SS		 783 .register_type = SH_ETH_REG_GIGABIT,
784
73a0d907
YS		 785 .ecsr_value = ECSR_ICD | ECSR_MPD,
786 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
787 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
788
789 .tx_check = EESR_TC1 | EESR_FTC,
ca8c3585
SS		 790 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
791 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
792 EESR_TDE | EESR_ECI,
cc23528d 793 .fdr_value = 0x0000070f,
73a0d907
YS		 794
795 .apr = 1,
796 .mpr = 1,
797 .tpauser = 1,
798 .bculr = 1,
799 .hw_swap = 1,
cc23528d
SH		 800 .rpadir = 1,
801 .rpadir_value = 2 << 16,
73a0d907
YS		 802 .no_trimd = 1,
803 .no_ade = 1,
804 .tsu = 1,
5e7a76be 805 .select_mii = 1,
ac8025a6 806 .shift_rd0 = 1,
73a0d907
YS		 807};
808
db893473
SH		 809/* R7S72100 */
810static struct sh_eth_cpu_data r7s72100_data = {
811 .chip_reset = sh_eth_chip_reset,
812 .set_duplex = sh_eth_set_duplex,
813
814 .register_type = SH_ETH_REG_FAST_RZ,
815
816 .ecsr_value = ECSR_ICD,
817 .ecsipr_value = ECSIPR_ICDIP,
818 .eesipr_value = 0xff7f009f,
819
820 .tx_check = EESR_TC1 | EESR_FTC,
821 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
822 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
823 EESR_TDE | EESR_ECI,
824 .fdr_value = 0x0000070f,
db893473
SH		 825
826 .no_psr = 1,
827 .apr = 1,
828 .mpr = 1,
829 .tpauser = 1,
830 .hw_swap = 1,
831 .rpadir = 1,
832 .rpadir_value = 2 << 16,
833 .no_trimd = 1,
834 .no_ade = 1,
835 .hw_crc = 1,
836 .tsu = 1,
837 .shift_rd0 = 1,
838};
839
c18a79ab 840static struct sh_eth_cpu_data sh7619_data = {
a3153d8c
SS		 841 .register_type = SH_ETH_REG_FAST_SH3_SH2,
842
380af9e3
YS		 843 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
844
845 .apr = 1,
846 .mpr = 1,
847 .tpauser = 1,
848 .hw_swap = 1,
849};
7bbe150d
SS		 850
851static struct sh_eth_cpu_data sh771x_data = {
a3153d8c
SS		 852 .register_type = SH_ETH_REG_FAST_SH3_SH2,
853
380af9e3 854 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
4986b996 855 .tsu = 1,
380af9e3 856};
380af9e3
YS		 857
858static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
859{
860 if (!cd->ecsr_value)
861 cd->ecsr_value = DEFAULT_ECSR_INIT;
862
863 if (!cd->ecsipr_value)
864 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
865
866 if (!cd->fcftr_value)
128296fc 867 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF |
380af9e3
YS		 868 DEFAULT_FIFO_F_D_RFD;
869
870 if (!cd->fdr_value)
871 cd->fdr_value = DEFAULT_FDR_INIT;
872
380af9e3
YS		 873 if (!cd->tx_check)
874 cd->tx_check = DEFAULT_TX_CHECK;
875
876 if (!cd->eesr_err_check)
877 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
b284fbe3
NI		 878
879 if (!cd->trscer_err_mask)
880 cd->trscer_err_mask = DEFAULT_TRSCER_ERR_MASK;
380af9e3
YS		 881}
882
5cee1d37
NI		 883static int sh_eth_check_reset(struct net_device *ndev)
884{
885 int ret = 0;
886 int cnt = 100;
887
888 while (cnt > 0) {
889 if (!(sh_eth_read(ndev, EDMR) & 0x3))
890 break;
891 mdelay(1);
892 cnt--;
893 }
9f8c4265 894 if (cnt <= 0) {
f75f14ec 895 netdev_err(ndev, "Device reset failed\n");
5cee1d37
NI		 896 ret = -ETIMEDOUT;
897 }
898 return ret;
380af9e3 899}
dabdde9e
NI		 900
901static int sh_eth_reset(struct net_device *ndev)
902{
903 struct sh_eth_private *mdp = netdev_priv(ndev);
904 int ret = 0;
905
db893473 906 if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp)) {
dabdde9e
NI		 907 sh_eth_write(ndev, EDSR_ENALL, EDSR);
908 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER,
909 EDMR);
910
911 ret = sh_eth_check_reset(ndev);
912 if (ret)
f738a13d 913 return ret;
dabdde9e
NI		 914
915 /* Table Init */
916 sh_eth_write(ndev, 0x0, TDLAR);
917 sh_eth_write(ndev, 0x0, TDFAR);
918 sh_eth_write(ndev, 0x0, TDFXR);
919 sh_eth_write(ndev, 0x0, TDFFR);
920 sh_eth_write(ndev, 0x0, RDLAR);
921 sh_eth_write(ndev, 0x0, RDFAR);
922 sh_eth_write(ndev, 0x0, RDFXR);
923 sh_eth_write(ndev, 0x0, RDFFR);
924
925 /* Reset HW CRC register */
926 if (mdp->cd->hw_crc)
927 sh_eth_write(ndev, 0x0, CSMR);
928
929 /* Select MII mode */
930 if (mdp->cd->select_mii)
931 sh_eth_select_mii(ndev);
932 } else {
933 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER,
934 EDMR);
935 mdelay(3);
936 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER,
937 EDMR);
938 }
939
dabdde9e
NI		 940 return ret;
941}
380af9e3 942
380af9e3
YS		 943static void sh_eth_set_receive_align(struct sk_buff *skb)
944{
4d6a949c 945 uintptr_t reserve = (uintptr_t)skb->data & (SH_ETH_RX_ALIGN - 1);
380af9e3 946
380af9e3 947 if (reserve)
4d6a949c 948 skb_reserve(skb, SH_ETH_RX_ALIGN - reserve);
380af9e3 949}
380af9e3
YS		 950
951
71557a37
YS		 952/* CPU <-> EDMAC endian convert */
953static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x)
954{
955 switch (mdp->edmac_endian) {
956 case EDMAC_LITTLE_ENDIAN:
957 return cpu_to_le32(x);
958 case EDMAC_BIG_ENDIAN:
959 return cpu_to_be32(x);
960 }
961 return x;
962}
963
964static inline __u32 edmac_to_cpu(struct sh_eth_private *mdp, u32 x)
965{
966 switch (mdp->edmac_endian) {
967 case EDMAC_LITTLE_ENDIAN:
968 return le32_to_cpu(x);
969 case EDMAC_BIG_ENDIAN:
970 return be32_to_cpu(x);
971 }
972 return x;
973}
974
128296fc 975/* Program the hardware MAC address from dev->dev_addr. */
86a74ff2
NI		 976static void update_mac_address(struct net_device *ndev)
977{
4a55530f 978 sh_eth_write(ndev,
128296fc
SS		 979 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
980 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
4a55530f 981 sh_eth_write(ndev,
128296fc 982 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
86a74ff2
NI		 983}
984
128296fc 985/* Get MAC address from SuperH MAC address register
86a74ff2
NI		 986 *
987 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
988 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
989 * When you want use this device, you must set MAC address in bootloader.
990 *
991 */
748031f9 992static void read_mac_address(struct net_device *ndev, unsigned char *mac)
86a74ff2 993{
748031f9 994 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
d458cdf7 995 memcpy(ndev->dev_addr, mac, ETH_ALEN);
748031f9 996 } else {
4a55530f
YS		 997 ndev->dev_addr[0] = (sh_eth_read(ndev, MAHR) >> 24);
998 ndev->dev_addr[1] = (sh_eth_read(ndev, MAHR) >> 16) & 0xFF;
999 ndev->dev_addr[2] = (sh_eth_read(ndev, MAHR) >> 8) & 0xFF;
1000 ndev->dev_addr[3] = (sh_eth_read(ndev, MAHR) & 0xFF);
1001 ndev->dev_addr[4] = (sh_eth_read(ndev, MALR) >> 8) & 0xFF;
1002 ndev->dev_addr[5] = (sh_eth_read(ndev, MALR) & 0xFF);
748031f9 1003 }
86a74ff2
NI		 1004}
1005
0799c2d6 1006static u32 sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
c5ed5368 1007{
db893473 1008 if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp))
c5ed5368
YS		 1009 return EDTRR_TRNS_GETHER;
1010 else
1011 return EDTRR_TRNS_ETHER;
1012}
1013
86a74ff2 1014struct bb_info {
ae70644d 1015 void (*set_gate)(void *addr);
86a74ff2 1016 struct mdiobb_ctrl ctrl;
ae70644d 1017 void *addr;
86a74ff2
NI		 1018 u32 mmd_msk;/* MMD */
1019 u32 mdo_msk;
1020 u32 mdi_msk;
1021 u32 mdc_msk;
1022};
1023
1024/* PHY bit set */
ae70644d 1025static void bb_set(void *addr, u32 msk)
86a74ff2 1026{
ae70644d 1027 iowrite32(ioread32(addr) | msk, addr);
86a74ff2
NI		 1028}
1029
1030/* PHY bit clear */
ae70644d 1031static void bb_clr(void *addr, u32 msk)
86a74ff2 1032{
ae70644d 1033 iowrite32((ioread32(addr) & ~msk), addr);
86a74ff2
NI		 1034}
1035
1036/* PHY bit read */
ae70644d 1037static int bb_read(void *addr, u32 msk)
86a74ff2 1038{
ae70644d 1039 return (ioread32(addr) & msk) != 0;
86a74ff2
NI		 1040}
1041
1042/* Data I/O pin control */
1043static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1044{
1045 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
b3017e6a
YS		 1046
1047 if (bitbang->set_gate)
1048 bitbang->set_gate(bitbang->addr);
1049
86a74ff2
NI		 1050 if (bit)
1051 bb_set(bitbang->addr, bitbang->mmd_msk);
1052 else
1053 bb_clr(bitbang->addr, bitbang->mmd_msk);
1054}
1055
1056/* Set bit data*/
1057static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
1058{
1059 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1060
b3017e6a
YS		 1061 if (bitbang->set_gate)
1062 bitbang->set_gate(bitbang->addr);
1063
86a74ff2
NI		 1064 if (bit)
1065 bb_set(bitbang->addr, bitbang->mdo_msk);
1066 else
1067 bb_clr(bitbang->addr, bitbang->mdo_msk);
1068}
1069
1070/* Get bit data*/
1071static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
1072{
1073 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
b3017e6a
YS		 1074
1075 if (bitbang->set_gate)
1076 bitbang->set_gate(bitbang->addr);
1077
86a74ff2
NI		 1078 return bb_read(bitbang->addr, bitbang->mdi_msk);
1079}
1080
1081/* MDC pin control */
1082static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1083{
1084 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1085
b3017e6a
YS		 1086 if (bitbang->set_gate)
1087 bitbang->set_gate(bitbang->addr);
1088
86a74ff2
NI		 1089 if (bit)
1090 bb_set(bitbang->addr, bitbang->mdc_msk);
1091 else
1092 bb_clr(bitbang->addr, bitbang->mdc_msk);
1093}
1094
1095/* mdio bus control struct */
1096static struct mdiobb_ops bb_ops = {
1097 .owner = THIS_MODULE,
1098 .set_mdc = sh_mdc_ctrl,
1099 .set_mdio_dir = sh_mmd_ctrl,
1100 .set_mdio_data = sh_set_mdio,
1101 .get_mdio_data = sh_get_mdio,
1102};
1103
86a74ff2
NI		 1104/* free skb and descriptor buffer */
1105static void sh_eth_ring_free(struct net_device *ndev)
1106{
1107 struct sh_eth_private *mdp = netdev_priv(ndev);
1108 int i;
1109
1110 /* Free Rx skb ringbuffer */
1111 if (mdp->rx_skbuff) {
179d80af
SS		 1112 for (i = 0; i < mdp->num_rx_ring; i++)
1113 dev_kfree_skb(mdp->rx_skbuff[i]);
86a74ff2
NI		 1114 }
1115 kfree(mdp->rx_skbuff);
91c77550 1116 mdp->rx_skbuff = NULL;
86a74ff2
NI		 1117
1118 /* Free Tx skb ringbuffer */
1119 if (mdp->tx_skbuff) {
179d80af
SS		 1120 for (i = 0; i < mdp->num_tx_ring; i++)
1121 dev_kfree_skb(mdp->tx_skbuff[i]);
86a74ff2
NI		 1122 }
1123 kfree(mdp->tx_skbuff);
91c77550 1124 mdp->tx_skbuff = NULL;
86a74ff2
NI		 1125}
1126
1127/* format skb and descriptor buffer */
1128static void sh_eth_ring_format(struct net_device *ndev)
1129{
1130 struct sh_eth_private *mdp = netdev_priv(ndev);
1131 int i;
1132 struct sk_buff *skb;
1133 struct sh_eth_rxdesc *rxdesc = NULL;
1134 struct sh_eth_txdesc *txdesc = NULL;
525b8075
YS		 1135 int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
1136 int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
4d6a949c 1137 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN - 1;
52b9fa36 1138 dma_addr_t dma_addr;
86a74ff2 1139
128296fc
SS		 1140 mdp->cur_rx = 0;
1141 mdp->cur_tx = 0;
1142 mdp->dirty_rx = 0;
1143 mdp->dirty_tx = 0;
86a74ff2
NI		 1144
1145 memset(mdp->rx_ring, 0, rx_ringsize);
1146
1147 /* build Rx ring buffer */
525b8075 1148 for (i = 0; i < mdp->num_rx_ring; i++) {
86a74ff2
NI		 1149 /* skb */
1150 mdp->rx_skbuff[i] = NULL;
4d6a949c 1151 skb = netdev_alloc_skb(ndev, skbuff_size);
86a74ff2
NI		 1152 if (skb == NULL)
1153 break;
380af9e3
YS		 1154 sh_eth_set_receive_align(skb);
1155
86a74ff2
NI		 1156 /* RX descriptor */
1157 rxdesc = &mdp->rx_ring[i];
4d6a949c
MK		 1158 /* The size of the buffer is a multiple of 16 bytes. */
1159 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
52b9fa36
BH		 1160 dma_addr = dma_map_single(&ndev->dev, skb->data,
1161 rxdesc->buffer_length,
1162 DMA_FROM_DEVICE);
1163 if (dma_mapping_error(&ndev->dev, dma_addr)) {
1164 kfree_skb(skb);
1165 break;
1166 }
1167 mdp->rx_skbuff[i] = skb;
1168 rxdesc->addr = dma_addr;
71557a37 1169 rxdesc->status = cpu_to_edmac(mdp, RD_RACT | RD_RFP);
86a74ff2 1170
b0ca2a21
NI		 1171 /* Rx descriptor address set */
1172 if (i == 0) {
4a55530f 1173 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
db893473
SH		 1174 if (sh_eth_is_gether(mdp) ||
1175 sh_eth_is_rz_fast_ether(mdp))
c5ed5368 1176 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
b0ca2a21 1177 }
86a74ff2
NI		 1178 }
1179
525b8075 1180 mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
86a74ff2
NI		 1181
1182 /* Mark the last entry as wrapping the ring. */
71557a37 1183 rxdesc->status |= cpu_to_edmac(mdp, RD_RDEL);
86a74ff2
NI		 1184
1185 memset(mdp->tx_ring, 0, tx_ringsize);
1186
1187 /* build Tx ring buffer */
525b8075 1188 for (i = 0; i < mdp->num_tx_ring; i++) {
86a74ff2
NI		 1189 mdp->tx_skbuff[i] = NULL;
1190 txdesc = &mdp->tx_ring[i];
71557a37 1191 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
86a74ff2 1192 txdesc->buffer_length = 0;
b0ca2a21 1193 if (i == 0) {
71557a37 1194 /* Tx descriptor address set */
4a55530f 1195 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
db893473
SH		 1196 if (sh_eth_is_gether(mdp) ||
1197 sh_eth_is_rz_fast_ether(mdp))
c5ed5368 1198 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
b0ca2a21 1199 }
86a74ff2
NI		 1200 }
1201
71557a37 1202 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
86a74ff2
NI		 1203}
1204
1205/* Get skb and descriptor buffer */
1206static int sh_eth_ring_init(struct net_device *ndev)
1207{
1208 struct sh_eth_private *mdp = netdev_priv(ndev);
1209 int rx_ringsize, tx_ringsize, ret = 0;
1210
128296fc 1211 /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
86a74ff2
NI		 1212 * card needs room to do 8 byte alignment, +2 so we can reserve
1213 * the first 2 bytes, and +16 gets room for the status word from the
1214 * card.
1215 */
1216 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
1217 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
503914cf
MD		 1218 if (mdp->cd->rpadir)
1219 mdp->rx_buf_sz += NET_IP_ALIGN;
86a74ff2
NI		 1220
1221 /* Allocate RX and TX skb rings */
b2adaca9
JP		 1222 mdp->rx_skbuff = kmalloc_array(mdp->num_rx_ring,
1223 sizeof(*mdp->rx_skbuff), GFP_KERNEL);
86a74ff2 1224 if (!mdp->rx_skbuff) {
86a74ff2
NI		 1225 ret = -ENOMEM;
1226 return ret;
1227 }
1228
b2adaca9
JP		 1229 mdp->tx_skbuff = kmalloc_array(mdp->num_tx_ring,
1230 sizeof(*mdp->tx_skbuff), GFP_KERNEL);
86a74ff2 1231 if (!mdp->tx_skbuff) {
86a74ff2
NI		 1232 ret = -ENOMEM;
1233 goto skb_ring_free;
1234 }
1235
1236 /* Allocate all Rx descriptors. */
525b8075 1237 rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
86a74ff2 1238 mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
d0320f75 1239 GFP_KERNEL);
86a74ff2 1240 if (!mdp->rx_ring) {
86a74ff2
NI		 1241 ret = -ENOMEM;
1242 goto desc_ring_free;
1243 }
1244
1245 mdp->dirty_rx = 0;
1246
1247 /* Allocate all Tx descriptors. */
525b8075 1248 tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
86a74ff2 1249 mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
d0320f75 1250 GFP_KERNEL);
86a74ff2 1251 if (!mdp->tx_ring) {
86a74ff2
NI		 1252 ret = -ENOMEM;
1253 goto desc_ring_free;
1254 }
1255 return ret;
1256
1257desc_ring_free:
1258 /* free DMA buffer */
1259 dma_free_coherent(NULL, rx_ringsize, mdp->rx_ring, mdp->rx_desc_dma);
1260
1261skb_ring_free:
1262 /* Free Rx and Tx skb ring buffer */
1263 sh_eth_ring_free(ndev);
91c77550
YS		 1264 mdp->tx_ring = NULL;
1265 mdp->rx_ring = NULL;
86a74ff2
NI		 1266
1267 return ret;
1268}
1269
91c77550
YS		 1270static void sh_eth_free_dma_buffer(struct sh_eth_private *mdp)
1271{
1272 int ringsize;
1273
1274 if (mdp->rx_ring) {
525b8075 1275 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
91c77550
YS		 1276 dma_free_coherent(NULL, ringsize, mdp->rx_ring,
1277 mdp->rx_desc_dma);
1278 mdp->rx_ring = NULL;
1279 }
1280
1281 if (mdp->tx_ring) {
525b8075 1282 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
91c77550
YS		 1283 dma_free_coherent(NULL, ringsize, mdp->tx_ring,
1284 mdp->tx_desc_dma);
1285 mdp->tx_ring = NULL;
1286 }
1287}
1288
525b8075 1289static int sh_eth_dev_init(struct net_device *ndev, bool start)
86a74ff2
NI		 1290{
1291 int ret = 0;
1292 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 1293 u32 val;
1294
1295 /* Soft Reset */
5cee1d37
NI		 1296 ret = sh_eth_reset(ndev);
1297 if (ret)
f738a13d 1298 return ret;
86a74ff2 1299
55754f19
SH		 1300 if (mdp->cd->rmiimode)
1301 sh_eth_write(ndev, 0x1, RMIIMODE);
1302
b0ca2a21
NI		 1303 /* Descriptor format */
1304 sh_eth_ring_format(ndev);
380af9e3 1305 if (mdp->cd->rpadir)
4a55530f 1306 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
86a74ff2
NI		 1307
1308 /* all sh_eth int mask */
4a55530f 1309 sh_eth_write(ndev, 0, EESIPR);
86a74ff2 1310
10b9194f 1311#if defined(__LITTLE_ENDIAN)
380af9e3 1312 if (mdp->cd->hw_swap)
4a55530f 1313 sh_eth_write(ndev, EDMR_EL, EDMR);
380af9e3 1314 else
b0ca2a21 1315#endif
4a55530f 1316 sh_eth_write(ndev, 0, EDMR);
86a74ff2 1317
b0ca2a21 1318 /* FIFO size set */
4a55530f
YS		 1319 sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
1320 sh_eth_write(ndev, 0, TFTR);
86a74ff2 1321
530aa2d0
BD		 1322 /* Frame recv control (enable multiple-packets per rx irq) */
1323 sh_eth_write(ndev, RMCR_RNC, RMCR);
86a74ff2 1324
b284fbe3 1325 sh_eth_write(ndev, mdp->cd->trscer_err_mask, TRSCER);
86a74ff2 1326
380af9e3 1327 if (mdp->cd->bculr)
4a55530f 1328 sh_eth_write(ndev, 0x800, BCULR); /* Burst sycle set */
b0ca2a21 1329
4a55530f 1330 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
86a74ff2 1331
380af9e3 1332 if (!mdp->cd->no_trimd)
4a55530f 1333 sh_eth_write(ndev, 0, TRIMD);
86a74ff2 1334
b0ca2a21 1335 /* Recv frame limit set register */
fdb37a7f
YS		 1336 sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1337 RFLR);
86a74ff2 1338
4a55530f 1339 sh_eth_write(ndev, sh_eth_read(ndev, EESR), EESR);
283e38db
BH		 1340 if (start) {
1341 mdp->irq_enabled = true;
525b8075 1342 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
283e38db 1343 }
86a74ff2
NI		 1344
1345 /* PAUSE Prohibition */
4a55530f 1346 val = (sh_eth_read(ndev, ECMR) & ECMR_DM) |
86a74ff2
NI		 1347 ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE;
1348
4a55530f 1349 sh_eth_write(ndev, val, ECMR);
b0ca2a21 1350
380af9e3
YS		 1351 if (mdp->cd->set_rate)
1352 mdp->cd->set_rate(ndev);
1353
b0ca2a21 1354 /* E-MAC Status Register clear */
4a55530f 1355 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
b0ca2a21
NI		 1356
1357 /* E-MAC Interrupt Enable register */
525b8075
YS		 1358 if (start)
1359 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
86a74ff2
NI		 1360
1361 /* Set MAC address */
1362 update_mac_address(ndev);
1363
1364 /* mask reset */
380af9e3 1365 if (mdp->cd->apr)
4a55530f 1366 sh_eth_write(ndev, APR_AP, APR);
380af9e3 1367 if (mdp->cd->mpr)
4a55530f 1368 sh_eth_write(ndev, MPR_MP, MPR);
380af9e3 1369 if (mdp->cd->tpauser)
4a55530f 1370 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
b0ca2a21 1371
525b8075
YS		 1372 if (start) {
1373 /* Setting the Rx mode will start the Rx process. */
1374 sh_eth_write(ndev, EDRRR_R, EDRRR);
86a74ff2 1375
525b8075
YS		 1376 netif_start_queue(ndev);
1377 }
86a74ff2
NI		 1378
1379 return ret;
1380}
1381
740c7f31
BH		 1382static void sh_eth_dev_exit(struct net_device *ndev)
1383{
1384 struct sh_eth_private *mdp = netdev_priv(ndev);
1385 int i;
1386
1387 /* Deactivate all TX descriptors, so DMA should stop at next
1388 * packet boundary if it's currently running
1389 */
1390 for (i = 0; i < mdp->num_tx_ring; i++)
1391 mdp->tx_ring[i].status &= ~cpu_to_edmac(mdp, TD_TACT);
1392
1393 /* Disable TX FIFO egress to MAC */
1394 sh_eth_rcv_snd_disable(ndev);
1395
1396 /* Stop RX DMA at next packet boundary */
1397 sh_eth_write(ndev, 0, EDRRR);
1398
1399 /* Aside from TX DMA, we can't tell when the hardware is
1400 * really stopped, so we need to reset to make sure.
1401 * Before doing that, wait for long enough to *probably*
1402 * finish transmitting the last packet and poll stats.
1403 */
1404 msleep(2); /* max frame time at 10 Mbps < 1250 us */
1405 sh_eth_get_stats(ndev);
1406 sh_eth_reset(ndev);
a14c7d15
GU		 1407
1408 /* Set MAC address again */
1409 update_mac_address(ndev);
740c7f31
BH		 1410}
1411
86a74ff2
NI		 1412/* free Tx skb function */
1413static int sh_eth_txfree(struct net_device *ndev)
1414{
1415 struct sh_eth_private *mdp = netdev_priv(ndev);
1416 struct sh_eth_txdesc *txdesc;
128296fc 1417 int free_num = 0;
86a74ff2
NI		 1418 int entry = 0;
1419
1420 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
525b8075 1421 entry = mdp->dirty_tx % mdp->num_tx_ring;
86a74ff2 1422 txdesc = &mdp->tx_ring[entry];
71557a37 1423 if (txdesc->status & cpu_to_edmac(mdp, TD_TACT))
86a74ff2 1424 break;
7d7355f5
BH		 1425 /* TACT bit must be checked before all the following reads */
1426 rmb();
86a74ff2
NI		 1427 /* Free the original skb. */
1428 if (mdp->tx_skbuff[entry]) {
31fcb99d
YS		 1429 dma_unmap_single(&ndev->dev, txdesc->addr,
1430 txdesc->buffer_length, DMA_TO_DEVICE);
86a74ff2
NI		 1431 dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1432 mdp->tx_skbuff[entry] = NULL;
128296fc 1433 free_num++;
86a74ff2 1434 }
71557a37 1435 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
525b8075 1436 if (entry >= mdp->num_tx_ring - 1)
71557a37 1437 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
86a74ff2 1438
bb7d92e3
ED		 1439 ndev->stats.tx_packets++;
1440 ndev->stats.tx_bytes += txdesc->buffer_length;
86a74ff2 1441 }
128296fc 1442 return free_num;
86a74ff2
NI		 1443}
1444
1445/* Packet receive function */
3719109d 1446static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
86a74ff2
NI		 1447{
1448 struct sh_eth_private *mdp = netdev_priv(ndev);
1449 struct sh_eth_rxdesc *rxdesc;
1450
525b8075
YS		 1451 int entry = mdp->cur_rx % mdp->num_rx_ring;
1452 int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
319cd520 1453 int limit;
86a74ff2
NI		 1454 struct sk_buff *skb;
1455 u16 pkt_len = 0;
380af9e3 1456 u32 desc_status;
4d6a949c 1457 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN - 1;
52b9fa36 1458 dma_addr_t dma_addr;
86a74ff2 1459
319cd520
MK		 1460 boguscnt = min(boguscnt, *quota);
1461 limit = boguscnt;
86a74ff2 1462 rxdesc = &mdp->rx_ring[entry];
71557a37 1463 while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) {
7d7355f5
BH		 1464 /* RACT bit must be checked before all the following reads */
1465 rmb();
71557a37 1466 desc_status = edmac_to_cpu(mdp, rxdesc->status);
86a74ff2
NI		 1467 pkt_len = rxdesc->frame_length;
1468
1469 if (--boguscnt < 0)
1470 break;
1471
1472 if (!(desc_status & RDFEND))
bb7d92e3 1473 ndev->stats.rx_length_errors++;
86a74ff2 1474
128296fc 1475 /* In case of almost all GETHER/ETHERs, the Receive Frame State
dd019897 1476 * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
9b4a6364
BH		 1477 * bit 0. However, in case of the R8A7740 and R7S72100
1478 * the RFS bits are from bit 25 to bit 16. So, the
db893473 1479 * driver needs right shifting by 16.
dd019897 1480 */
ac8025a6
SS		 1481 if (mdp->cd->shift_rd0)
1482 desc_status >>= 16;
dd019897 1483
86a74ff2
NI		 1484 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1485 RD_RFS5 | RD_RFS6 | RD_RFS10)) {
bb7d92e3 1486 ndev->stats.rx_errors++;
86a74ff2 1487 if (desc_status & RD_RFS1)
bb7d92e3 1488 ndev->stats.rx_crc_errors++;
86a74ff2 1489 if (desc_status & RD_RFS2)
bb7d92e3 1490 ndev->stats.rx_frame_errors++;
86a74ff2 1491 if (desc_status & RD_RFS3)
bb7d92e3 1492 ndev->stats.rx_length_errors++;
86a74ff2 1493 if (desc_status & RD_RFS4)
bb7d92e3 1494 ndev->stats.rx_length_errors++;
86a74ff2 1495 if (desc_status & RD_RFS6)
bb7d92e3 1496 ndev->stats.rx_missed_errors++;
86a74ff2 1497 if (desc_status & RD_RFS10)
bb7d92e3 1498 ndev->stats.rx_over_errors++;
86a74ff2 1499 } else {
380af9e3
YS		 1500 if (!mdp->cd->hw_swap)
1501 sh_eth_soft_swap(
1502 phys_to_virt(ALIGN(rxdesc->addr, 4)),
1503 pkt_len + 2);
86a74ff2
NI		 1504 skb = mdp->rx_skbuff[entry];
1505 mdp->rx_skbuff[entry] = NULL;
503914cf
MD		 1506 if (mdp->cd->rpadir)
1507 skb_reserve(skb, NET_IP_ALIGN);
52b9fa36
BH		 1508 dma_unmap_single(&ndev->dev, rxdesc->addr,
1509 ALIGN(mdp->rx_buf_sz, 16),
1510 DMA_FROM_DEVICE);
86a74ff2
NI		 1511 skb_put(skb, pkt_len);
1512 skb->protocol = eth_type_trans(skb, ndev);
a8e9fd0f 1513 netif_receive_skb(skb);
bb7d92e3
ED		 1514 ndev->stats.rx_packets++;
1515 ndev->stats.rx_bytes += pkt_len;
25b77ad7
BH		 1516 if (desc_status & RD_RFS8)
1517 ndev->stats.multicast++;
86a74ff2 1518 }
525b8075 1519 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
862df497 1520 rxdesc = &mdp->rx_ring[entry];
86a74ff2
NI		 1521 }
1522
1523 /* Refill the Rx ring buffers. */
1524 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
525b8075 1525 entry = mdp->dirty_rx % mdp->num_rx_ring;
86a74ff2 1526 rxdesc = &mdp->rx_ring[entry];
b0ca2a21 1527 /* The size of the buffer is 16 byte boundary. */
0029d64a 1528 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
b0ca2a21 1529
86a74ff2 1530 if (mdp->rx_skbuff[entry] == NULL) {
4d6a949c 1531 skb = netdev_alloc_skb(ndev, skbuff_size);
86a74ff2
NI		 1532 if (skb == NULL)
1533 break; /* Better luck next round. */
380af9e3 1534 sh_eth_set_receive_align(skb);
52b9fa36
BH		 1535 dma_addr = dma_map_single(&ndev->dev, skb->data,
1536 rxdesc->buffer_length,
1537 DMA_FROM_DEVICE);
1538 if (dma_mapping_error(&ndev->dev, dma_addr)) {
1539 kfree_skb(skb);
1540 break;
1541 }
1542 mdp->rx_skbuff[entry] = skb;
380af9e3 1543
bc8acf2c 1544 skb_checksum_none_assert(skb);
52b9fa36 1545 rxdesc->addr = dma_addr;
86a74ff2 1546 }
7d7355f5 1547 wmb(); /* RACT bit must be set after all the above writes */
525b8075 1548 if (entry >= mdp->num_rx_ring - 1)
86a74ff2 1549 rxdesc->status |=
71557a37 1550 cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDEL);
86a74ff2
NI		 1551 else
1552 rxdesc->status |=
71557a37 1553 cpu_to_edmac(mdp, RD_RACT | RD_RFP);
86a74ff2
NI		 1554 }
1555
1556 /* Restart Rx engine if stopped. */
1557 /* If we don't need to check status, don't. -KDU */
79fba9f5 1558 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
a18e08bd 1559 /* fix the values for the next receiving if RDE is set */
3365711d
BH		 1560 if (intr_status & EESR_RDE &&
1561 mdp->reg_offset[RDFAR] != SH_ETH_OFFSET_INVALID) {
128296fc
SS		 1562 u32 count = (sh_eth_read(ndev, RDFAR) -
1563 sh_eth_read(ndev, RDLAR)) >> 4;
1564
1565 mdp->cur_rx = count;
1566 mdp->dirty_rx = count;
1567 }
4a55530f 1568 sh_eth_write(ndev, EDRRR_R, EDRRR);
79fba9f5 1569 }
86a74ff2 1570
319cd520
MK		 1571 *quota -= limit - boguscnt - 1;
1572
4f809cea 1573 return *quota <= 0;
86a74ff2
NI		 1574}
1575
4a55530f 1576static void sh_eth_rcv_snd_disable(struct net_device *ndev)
dc19e4e5
NI		 1577{
1578 /* disable tx and rx */
4a55530f
YS		 1579 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) &
1580 ~(ECMR_RE | ECMR_TE), ECMR);
dc19e4e5
NI		 1581}
1582
4a55530f 1583static void sh_eth_rcv_snd_enable(struct net_device *ndev)
dc19e4e5
NI		 1584{
1585 /* enable tx and rx */
4a55530f
YS		 1586 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) |
1587 (ECMR_RE | ECMR_TE), ECMR);
dc19e4e5
NI		 1588}
1589
86a74ff2 1590/* error control function */
0799c2d6 1591static void sh_eth_error(struct net_device *ndev, u32 intr_status)
86a74ff2
NI		 1592{
1593 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2 1594 u32 felic_stat;
380af9e3
YS		 1595 u32 link_stat;
1596 u32 mask;
86a74ff2
NI		 1597
1598 if (intr_status & EESR_ECI) {
4a55530f
YS		 1599 felic_stat = sh_eth_read(ndev, ECSR);
1600 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */
86a74ff2 1601 if (felic_stat & ECSR_ICD)
bb7d92e3 1602 ndev->stats.tx_carrier_errors++;
86a74ff2
NI		 1603 if (felic_stat & ECSR_LCHNG) {
1604 /* Link Changed */
4923576b 1605 if (mdp->cd->no_psr || mdp->no_ether_link) {
1e1b812b 1606 goto ignore_link;
380af9e3 1607 } else {
4a55530f 1608 link_stat = (sh_eth_read(ndev, PSR));
4923576b
YS		 1609 if (mdp->ether_link_active_low)
1610 link_stat = ~link_stat;
380af9e3 1611 }
128296fc 1612 if (!(link_stat & PHY_ST_LINK)) {
4a55530f 1613 sh_eth_rcv_snd_disable(ndev);
128296fc 1614 } else {
86a74ff2 1615 /* Link Up */
4a55530f 1616 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) &
128296fc
SS		 1617 ~DMAC_M_ECI, EESIPR);
1618 /* clear int */
4a55530f 1619 sh_eth_write(ndev, sh_eth_read(ndev, ECSR),
128296fc 1620 ECSR);
4a55530f 1621 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) |
128296fc 1622 DMAC_M_ECI, EESIPR);
86a74ff2 1623 /* enable tx and rx */
4a55530f 1624 sh_eth_rcv_snd_enable(ndev);
86a74ff2
NI		 1625 }
1626 }
1627 }
1628
1e1b812b 1629ignore_link:
86a74ff2 1630 if (intr_status & EESR_TWB) {
4eb313a7
SS		 1631 /* Unused write back interrupt */
1632 if (intr_status & EESR_TABT) { /* Transmit Abort int */
bb7d92e3 1633 ndev->stats.tx_aborted_errors++;
8d5009f6 1634 netif_err(mdp, tx_err, ndev, "Transmit Abort\n");
4eb313a7 1635 }
86a74ff2
NI		 1636 }
1637
1638 if (intr_status & EESR_RABT) {
1639 /* Receive Abort int */
1640 if (intr_status & EESR_RFRMER) {
1641 /* Receive Frame Overflow int */
bb7d92e3 1642 ndev->stats.rx_frame_errors++;
86a74ff2
NI		 1643 }
1644 }
380af9e3 1645
dc19e4e5
NI		 1646 if (intr_status & EESR_TDE) {
1647 /* Transmit Descriptor Empty int */
bb7d92e3 1648 ndev->stats.tx_fifo_errors++;
8d5009f6 1649 netif_err(mdp, tx_err, ndev, "Transmit Descriptor Empty\n");
dc19e4e5
NI		 1650 }
1651
1652 if (intr_status & EESR_TFE) {
1653 /* FIFO under flow */
bb7d92e3 1654 ndev->stats.tx_fifo_errors++;
8d5009f6 1655 netif_err(mdp, tx_err, ndev, "Transmit FIFO Under flow\n");
86a74ff2
NI		 1656 }
1657
1658 if (intr_status & EESR_RDE) {
1659 /* Receive Descriptor Empty int */
bb7d92e3 1660 ndev->stats.rx_over_errors++;
86a74ff2 1661 }
dc19e4e5 1662
86a74ff2
NI		 1663 if (intr_status & EESR_RFE) {
1664 /* Receive FIFO Overflow int */
bb7d92e3 1665 ndev->stats.rx_fifo_errors++;
dc19e4e5
NI		 1666 }
1667
1668 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1669 /* Address Error */
bb7d92e3 1670 ndev->stats.tx_fifo_errors++;
8d5009f6 1671 netif_err(mdp, tx_err, ndev, "Address Error\n");
86a74ff2 1672 }
380af9e3
YS		 1673
1674 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1675 if (mdp->cd->no_ade)
1676 mask &= ~EESR_ADE;
1677 if (intr_status & mask) {
86a74ff2 1678 /* Tx error */
4a55530f 1679 u32 edtrr = sh_eth_read(ndev, EDTRR);
090d560f 1680
86a74ff2 1681 /* dmesg */
da246855
SS		 1682 netdev_err(ndev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1683 intr_status, mdp->cur_tx, mdp->dirty_tx,
1684 (u32)ndev->state, edtrr);
86a74ff2
NI		 1685 /* dirty buffer free */
1686 sh_eth_txfree(ndev);
1687
1688 /* SH7712 BUG */
c5ed5368 1689 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
86a74ff2 1690 /* tx dma start */
c5ed5368 1691 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
86a74ff2
NI		 1692 }
1693 /* wakeup */
1694 netif_wake_queue(ndev);
1695 }
1696}
1697
1698static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1699{
1700 struct net_device *ndev = netdev;
1701 struct sh_eth_private *mdp = netdev_priv(ndev);
380af9e3 1702 struct sh_eth_cpu_data *cd = mdp->cd;
0e0fde3c 1703 irqreturn_t ret = IRQ_NONE;
0799c2d6 1704 u32 intr_status, intr_enable;
86a74ff2 1705
86a74ff2
NI		 1706 spin_lock(&mdp->lock);
1707
3893b273 1708 /* Get interrupt status */
4a55530f 1709 intr_status = sh_eth_read(ndev, EESR);
3893b273
SS		 1710 /* Mask it with the interrupt mask, forcing ECI interrupt to be always
1711 * enabled since it's the one that comes thru regardless of the mask,
1712 * and we need to fully handle it in sh_eth_error() in order to quench
1713 * it as it doesn't get cleared by just writing 1 to the ECI bit...
1714 */
3719109d
SS		 1715 intr_enable = sh_eth_read(ndev, EESIPR);
1716 intr_status &= intr_enable | DMAC_M_ECI;
1717 if (intr_status & (EESR_RX_CHECK | cd->tx_check | cd->eesr_err_check))
0e0fde3c 1718 ret = IRQ_HANDLED;
3719109d 1719 else
283e38db
BH		 1720 goto out;
1721
1722 if (!likely(mdp->irq_enabled)) {
1723 sh_eth_write(ndev, 0, EESIPR);
1724 goto out;
1725 }
86a74ff2 1726
3719109d
SS		 1727 if (intr_status & EESR_RX_CHECK) {
1728 if (napi_schedule_prep(&mdp->napi)) {
1729 /* Mask Rx interrupts */
1730 sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK,
1731 EESIPR);
1732 __napi_schedule(&mdp->napi);
1733 } else {
da246855 1734 netdev_warn(ndev,
0799c2d6 1735 "ignoring interrupt, status 0x%08x, mask 0x%08x.\n",
da246855 1736 intr_status, intr_enable);
3719109d
SS		 1737 }
1738 }
86a74ff2 1739
b0ca2a21 1740 /* Tx Check */
380af9e3 1741 if (intr_status & cd->tx_check) {
3719109d
SS		 1742 /* Clear Tx interrupts */
1743 sh_eth_write(ndev, intr_status & cd->tx_check, EESR);
1744
86a74ff2
NI		 1745 sh_eth_txfree(ndev);
1746 netif_wake_queue(ndev);
1747 }
1748
3719109d
SS		 1749 if (intr_status & cd->eesr_err_check) {
1750 /* Clear error interrupts */
1751 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR);
1752
86a74ff2 1753 sh_eth_error(ndev, intr_status);
3719109d 1754 }
86a74ff2 1755
283e38db 1756out:
86a74ff2
NI		 1757 spin_unlock(&mdp->lock);
1758
0e0fde3c 1759 return ret;
86a74ff2
NI		 1760}
1761
3719109d
SS		 1762static int sh_eth_poll(struct napi_struct *napi, int budget)
1763{
1764 struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private,
1765 napi);
1766 struct net_device *ndev = napi->dev;
1767 int quota = budget;
0799c2d6 1768 u32 intr_status;
3719109d
SS		 1769
1770 for (;;) {
1771 intr_status = sh_eth_read(ndev, EESR);
1772 if (!(intr_status & EESR_RX_CHECK))
1773 break;
1774 /* Clear Rx interrupts */
1775 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR);
1776
1777 if (sh_eth_rx(ndev, intr_status, &quota))
1778 goto out;
1779 }
1780
1781 napi_complete(napi);
1782
1783 /* Reenable Rx interrupts */
283e38db
BH		 1784 if (mdp->irq_enabled)
1785 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
3719109d
SS		 1786out:
1787 return budget - quota;
1788}
1789
86a74ff2
NI		 1790/* PHY state control function */
1791static void sh_eth_adjust_link(struct net_device *ndev)
1792{
1793 struct sh_eth_private *mdp = netdev_priv(ndev);
1794 struct phy_device *phydev = mdp->phydev;
86a74ff2
NI		 1795 int new_state = 0;
1796
3340d2aa 1797 if (phydev->link) {
86a74ff2
NI		 1798 if (phydev->duplex != mdp->duplex) {
1799 new_state = 1;
1800 mdp->duplex = phydev->duplex;
380af9e3
YS		 1801 if (mdp->cd->set_duplex)
1802 mdp->cd->set_duplex(ndev);
86a74ff2
NI		 1803 }
1804
1805 if (phydev->speed != mdp->speed) {
1806 new_state = 1;
1807 mdp->speed = phydev->speed;
380af9e3
YS		 1808 if (mdp->cd->set_rate)
1809 mdp->cd->set_rate(ndev);
86a74ff2 1810 }
3340d2aa 1811 if (!mdp->link) {
91a56152 1812 sh_eth_write(ndev,
128296fc
SS		 1813 sh_eth_read(ndev, ECMR) & ~ECMR_TXF,
1814 ECMR);
86a74ff2
NI		 1815 new_state = 1;
1816 mdp->link = phydev->link;
1e1b812b
SS		 1817 if (mdp->cd->no_psr || mdp->no_ether_link)
1818 sh_eth_rcv_snd_enable(ndev);
86a74ff2
NI		 1819 }
1820 } else if (mdp->link) {
1821 new_state = 1;
3340d2aa 1822 mdp->link = 0;
86a74ff2
NI		 1823 mdp->speed = 0;
1824 mdp->duplex = -1;
1e1b812b
SS		 1825 if (mdp->cd->no_psr || mdp->no_ether_link)
1826 sh_eth_rcv_snd_disable(ndev);
86a74ff2
NI		 1827 }
1828
dc19e4e5 1829 if (new_state && netif_msg_link(mdp))
86a74ff2
NI		 1830 phy_print_status(phydev);
1831}
1832
1833/* PHY init function */
1834static int sh_eth_phy_init(struct net_device *ndev)
1835{
702eca02 1836 struct device_node *np = ndev->dev.parent->of_node;
86a74ff2 1837 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 1838 struct phy_device *phydev = NULL;
1839
3340d2aa 1840 mdp->link = 0;
86a74ff2
NI		 1841 mdp->speed = 0;
1842 mdp->duplex = -1;
1843
1844 /* Try connect to PHY */
702eca02
BD		 1845 if (np) {
1846 struct device_node *pn;
1847
1848 pn = of_parse_phandle(np, "phy-handle", 0);
1849 phydev = of_phy_connect(ndev, pn,
1850 sh_eth_adjust_link, 0,
1851 mdp->phy_interface);
1852
1853 if (!phydev)
1854 phydev = ERR_PTR(-ENOENT);
1855 } else {
1856 char phy_id[MII_BUS_ID_SIZE + 3];
1857
1858 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
1859 mdp->mii_bus->id, mdp->phy_id);
1860
1861 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
1862 mdp->phy_interface);
1863 }
1864
86a74ff2 1865 if (IS_ERR(phydev)) {
da246855 1866 netdev_err(ndev, "failed to connect PHY\n");
86a74ff2
NI		 1867 return PTR_ERR(phydev);
1868 }
380af9e3 1869
da246855
SS		 1870 netdev_info(ndev, "attached PHY %d (IRQ %d) to driver %s\n",
1871 phydev->addr, phydev->irq, phydev->drv->name);
86a74ff2
NI		 1872
1873 mdp->phydev = phydev;
1874
1875 return 0;
1876}
1877
1878/* PHY control start function */
1879static int sh_eth_phy_start(struct net_device *ndev)
1880{
1881 struct sh_eth_private *mdp = netdev_priv(ndev);
1882 int ret;
1883
1884 ret = sh_eth_phy_init(ndev);
1885 if (ret)
1886 return ret;
1887
86a74ff2
NI		 1888 phy_start(mdp->phydev);
1889
1890 return 0;
1891}
1892
dc19e4e5 1893static int sh_eth_get_settings(struct net_device *ndev,
128296fc 1894 struct ethtool_cmd *ecmd)
dc19e4e5
NI		 1895{
1896 struct sh_eth_private *mdp = netdev_priv(ndev);
1897 unsigned long flags;
1898 int ret;
1899
4f9dce23
BH		 1900 if (!mdp->phydev)
1901 return -ENODEV;
1902
dc19e4e5
NI		 1903 spin_lock_irqsave(&mdp->lock, flags);
1904 ret = phy_ethtool_gset(mdp->phydev, ecmd);
1905 spin_unlock_irqrestore(&mdp->lock, flags);
1906
1907 return ret;
1908}
1909
1910static int sh_eth_set_settings(struct net_device *ndev,
128296fc 1911 struct ethtool_cmd *ecmd)
dc19e4e5
NI		 1912{
1913 struct sh_eth_private *mdp = netdev_priv(ndev);
1914 unsigned long flags;
1915 int ret;
dc19e4e5 1916
4f9dce23
BH		 1917 if (!mdp->phydev)
1918 return -ENODEV;
1919
dc19e4e5
NI		 1920 spin_lock_irqsave(&mdp->lock, flags);
1921
1922 /* disable tx and rx */
4a55530f 1923 sh_eth_rcv_snd_disable(ndev);
dc19e4e5
NI		 1924
1925 ret = phy_ethtool_sset(mdp->phydev, ecmd);
1926 if (ret)
1927 goto error_exit;
1928
1929 if (ecmd->duplex == DUPLEX_FULL)
1930 mdp->duplex = 1;
1931 else
1932 mdp->duplex = 0;
1933
1934 if (mdp->cd->set_duplex)
1935 mdp->cd->set_duplex(ndev);
1936
1937error_exit:
1938 mdelay(1);
1939
1940 /* enable tx and rx */
4a55530f 1941 sh_eth_rcv_snd_enable(ndev);
dc19e4e5
NI		 1942
1943 spin_unlock_irqrestore(&mdp->lock, flags);
1944
1945 return ret;
1946}
1947
1948static int sh_eth_nway_reset(struct net_device *ndev)
1949{
1950 struct sh_eth_private *mdp = netdev_priv(ndev);
1951 unsigned long flags;
1952 int ret;
1953
4f9dce23
BH		 1954 if (!mdp->phydev)
1955 return -ENODEV;
1956
dc19e4e5
NI		 1957 spin_lock_irqsave(&mdp->lock, flags);
1958 ret = phy_start_aneg(mdp->phydev);
1959 spin_unlock_irqrestore(&mdp->lock, flags);
1960
1961 return ret;
1962}
1963
1964static u32 sh_eth_get_msglevel(struct net_device *ndev)
1965{
1966 struct sh_eth_private *mdp = netdev_priv(ndev);
1967 return mdp->msg_enable;
1968}
1969
1970static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
1971{
1972 struct sh_eth_private *mdp = netdev_priv(ndev);
1973 mdp->msg_enable = value;
1974}
1975
1976static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
1977 "rx_current", "tx_current",
1978 "rx_dirty", "tx_dirty",
1979};
1980#define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats)
1981
1982static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
1983{
1984 switch (sset) {
1985 case ETH_SS_STATS:
1986 return SH_ETH_STATS_LEN;
1987 default:
1988 return -EOPNOTSUPP;
1989 }
1990}
1991
1992static void sh_eth_get_ethtool_stats(struct net_device *ndev,
128296fc 1993 struct ethtool_stats *stats, u64 *data)
dc19e4e5
NI		 1994{
1995 struct sh_eth_private *mdp = netdev_priv(ndev);
1996 int i = 0;
1997
1998 /* device-specific stats */
1999 data[i++] = mdp->cur_rx;
2000 data[i++] = mdp->cur_tx;
2001 data[i++] = mdp->dirty_rx;
2002 data[i++] = mdp->dirty_tx;
2003}
2004
2005static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
2006{
2007 switch (stringset) {
2008 case ETH_SS_STATS:
2009 memcpy(data, *sh_eth_gstrings_stats,
128296fc 2010 sizeof(sh_eth_gstrings_stats));
dc19e4e5
NI		 2011 break;
2012 }
2013}
2014
525b8075
YS		 2015static void sh_eth_get_ringparam(struct net_device *ndev,
2016 struct ethtool_ringparam *ring)
2017{
2018 struct sh_eth_private *mdp = netdev_priv(ndev);
2019
2020 ring->rx_max_pending = RX_RING_MAX;
2021 ring->tx_max_pending = TX_RING_MAX;
2022 ring->rx_pending = mdp->num_rx_ring;
2023 ring->tx_pending = mdp->num_tx_ring;
2024}
2025
2026static int sh_eth_set_ringparam(struct net_device *ndev,
2027 struct ethtool_ringparam *ring)
2028{
2029 struct sh_eth_private *mdp = netdev_priv(ndev);
2030 int ret;
2031
2032 if (ring->tx_pending > TX_RING_MAX ||
2033 ring->rx_pending > RX_RING_MAX ||
2034 ring->tx_pending < TX_RING_MIN ||
2035 ring->rx_pending < RX_RING_MIN)
2036 return -EINVAL;
2037 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
2038 return -EINVAL;
2039
2040 if (netif_running(ndev)) {
bd888916 2041 netif_device_detach(ndev);
525b8075 2042 netif_tx_disable(ndev);
283e38db
BH		 2043
2044 /* Serialise with the interrupt handler and NAPI, then
2045 * disable interrupts. We have to clear the
2046 * irq_enabled flag first to ensure that interrupts
2047 * won't be re-enabled.
2048 */
2049 mdp->irq_enabled = false;
525b8075 2050 synchronize_irq(ndev->irq);
283e38db 2051 napi_synchronize(&mdp->napi);
525b8075 2052 sh_eth_write(ndev, 0x0000, EESIPR);
525b8075 2053
740c7f31 2054 sh_eth_dev_exit(ndev);
525b8075 2055
084236d8
BH		 2056 /* Free all the skbuffs in the Rx queue. */
2057 sh_eth_ring_free(ndev);
2058 /* Free DMA buffer */
2059 sh_eth_free_dma_buffer(mdp);
2060 }
525b8075
YS		 2061
2062 /* Set new parameters */
2063 mdp->num_rx_ring = ring->rx_pending;
2064 mdp->num_tx_ring = ring->tx_pending;
2065
525b8075 2066 if (netif_running(ndev)) {
084236d8
BH		 2067 ret = sh_eth_ring_init(ndev);
2068 if (ret < 0) {
2069 netdev_err(ndev, "%s: sh_eth_ring_init failed.\n",
2070 __func__);
2071 return ret;
2072 }
2073 ret = sh_eth_dev_init(ndev, false);
2074 if (ret < 0) {
2075 netdev_err(ndev, "%s: sh_eth_dev_init failed.\n",
2076 __func__);
2077 return ret;
2078 }
2079
283e38db 2080 mdp->irq_enabled = true;
525b8075
YS		 2081 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
2082 /* Setting the Rx mode will start the Rx process. */
2083 sh_eth_write(ndev, EDRRR_R, EDRRR);
bd888916 2084 netif_device_attach(ndev);
525b8075
YS		 2085 }
2086
2087 return 0;
2088}
2089
9b07be4b 2090static const struct ethtool_ops sh_eth_ethtool_ops = {
dc19e4e5
NI		 2091 .get_settings = sh_eth_get_settings,
2092 .set_settings = sh_eth_set_settings,
9b07be4b 2093 .nway_reset = sh_eth_nway_reset,
dc19e4e5
NI		 2094 .get_msglevel = sh_eth_get_msglevel,
2095 .set_msglevel = sh_eth_set_msglevel,
9b07be4b 2096 .get_link = ethtool_op_get_link,
dc19e4e5
NI		 2097 .get_strings = sh_eth_get_strings,
2098 .get_ethtool_stats = sh_eth_get_ethtool_stats,
2099 .get_sset_count = sh_eth_get_sset_count,
525b8075
YS		 2100 .get_ringparam = sh_eth_get_ringparam,
2101 .set_ringparam = sh_eth_set_ringparam,
dc19e4e5
NI		 2102};
2103
86a74ff2
NI		 2104/* network device open function */
2105static int sh_eth_open(struct net_device *ndev)
2106{
2107 int ret = 0;
2108 struct sh_eth_private *mdp = netdev_priv(ndev);
2109
bcd5149d
MD		 2110 pm_runtime_get_sync(&mdp->pdev->dev);
2111
d2779e99
SS		 2112 napi_enable(&mdp->napi);
2113
a0607fd3 2114 ret = request_irq(ndev->irq, sh_eth_interrupt,
5b3dfd13 2115 mdp->cd->irq_flags, ndev->name, ndev);
86a74ff2 2116 if (ret) {
da246855 2117 netdev_err(ndev, "Can not assign IRQ number\n");
d2779e99 2118 goto out_napi_off;
86a74ff2
NI		 2119 }
2120
2121 /* Descriptor set */
2122 ret = sh_eth_ring_init(ndev);
2123 if (ret)
2124 goto out_free_irq;
2125
2126 /* device init */
525b8075 2127 ret = sh_eth_dev_init(ndev, true);
86a74ff2
NI		 2128 if (ret)
2129 goto out_free_irq;
2130
2131 /* PHY control start*/
2132 ret = sh_eth_phy_start(ndev);
2133 if (ret)
2134 goto out_free_irq;
2135
7fa2955f
MK		 2136 mdp->is_opened = 1;
2137
86a74ff2
NI		 2138 return ret;
2139
2140out_free_irq:
2141 free_irq(ndev->irq, ndev);
d2779e99
SS		 2142out_napi_off:
2143 napi_disable(&mdp->napi);
bcd5149d 2144 pm_runtime_put_sync(&mdp->pdev->dev);
86a74ff2
NI		 2145 return ret;
2146}
2147
2148/* Timeout function */
2149static void sh_eth_tx_timeout(struct net_device *ndev)
2150{
2151 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 2152 struct sh_eth_rxdesc *rxdesc;
2153 int i;
2154
2155 netif_stop_queue(ndev);
2156
8d5009f6
SS		 2157 netif_err(mdp, timer, ndev,
2158 "transmit timed out, status %8.8x, resetting...\n",
0799c2d6 2159 sh_eth_read(ndev, EESR));
86a74ff2
NI		 2160
2161 /* tx_errors count up */
bb7d92e3 2162 ndev->stats.tx_errors++;
86a74ff2 2163
86a74ff2 2164 /* Free all the skbuffs in the Rx queue. */
525b8075 2165 for (i = 0; i < mdp->num_rx_ring; i++) {
86a74ff2
NI		 2166 rxdesc = &mdp->rx_ring[i];
2167 rxdesc->status = 0;
2168 rxdesc->addr = 0xBADF00D0;
179d80af 2169 dev_kfree_skb(mdp->rx_skbuff[i]);
86a74ff2
NI		 2170 mdp->rx_skbuff[i] = NULL;
2171 }
525b8075 2172 for (i = 0; i < mdp->num_tx_ring; i++) {
179d80af 2173 dev_kfree_skb(mdp->tx_skbuff[i]);
86a74ff2
NI		 2174 mdp->tx_skbuff[i] = NULL;
2175 }
2176
2177 /* device init */
525b8075 2178 sh_eth_dev_init(ndev, true);
86a74ff2
NI		 2179}
2180
2181/* Packet transmit function */
2182static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
2183{
2184 struct sh_eth_private *mdp = netdev_priv(ndev);
2185 struct sh_eth_txdesc *txdesc;
2186 u32 entry;
fb5e2f9b 2187 unsigned long flags;
86a74ff2
NI		 2188
2189 spin_lock_irqsave(&mdp->lock, flags);
525b8075 2190 if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
86a74ff2 2191 if (!sh_eth_txfree(ndev)) {
8d5009f6 2192 netif_warn(mdp, tx_queued, ndev, "TxFD exhausted.\n");
86a74ff2
NI		 2193 netif_stop_queue(ndev);
2194 spin_unlock_irqrestore(&mdp->lock, flags);
5b548140 2195 return NETDEV_TX_BUSY;
86a74ff2
NI		 2196 }
2197 }
2198 spin_unlock_irqrestore(&mdp->lock, flags);
2199
dacc73e0 2200 if (skb_put_padto(skb, ETH_ZLEN))
eebfb643
BH		 2201 return NETDEV_TX_OK;
2202
525b8075 2203 entry = mdp->cur_tx % mdp->num_tx_ring;
86a74ff2
NI		 2204 mdp->tx_skbuff[entry] = skb;
2205 txdesc = &mdp->tx_ring[entry];
86a74ff2 2206 /* soft swap. */
380af9e3
YS		 2207 if (!mdp->cd->hw_swap)
2208 sh_eth_soft_swap(phys_to_virt(ALIGN(txdesc->addr, 4)),
2209 skb->len + 2);
31fcb99d
YS		 2210 txdesc->addr = dma_map_single(&ndev->dev, skb->data, skb->len,
2211 DMA_TO_DEVICE);
aa3933b8
BH		 2212 if (dma_mapping_error(&ndev->dev, txdesc->addr)) {
2213 kfree_skb(skb);
2214 return NETDEV_TX_OK;
2215 }
eebfb643 2216 txdesc->buffer_length = skb->len;
86a74ff2 2217
7d7355f5 2218 wmb(); /* TACT bit must be set after all the above writes */
525b8075 2219 if (entry >= mdp->num_tx_ring - 1)
71557a37 2220 txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE);
86a74ff2 2221 else
71557a37 2222 txdesc->status |= cpu_to_edmac(mdp, TD_TACT);
86a74ff2
NI		 2223
2224 mdp->cur_tx++;
2225
c5ed5368
YS		 2226 if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
2227 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
b0ca2a21 2228
6ed10654 2229 return NETDEV_TX_OK;
86a74ff2
NI		 2230}
2231
7fa2955f
MK		 2232static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
2233{
2234 struct sh_eth_private *mdp = netdev_priv(ndev);
2235
2236 if (sh_eth_is_rz_fast_ether(mdp))
2237 return &ndev->stats;
2238
2239 if (!mdp->is_opened)
2240 return &ndev->stats;
2241
2242 ndev->stats.tx_dropped += sh_eth_read(ndev, TROCR);
2243 sh_eth_write(ndev, 0, TROCR); /* (write clear) */
2244 ndev->stats.collisions += sh_eth_read(ndev, CDCR);
2245 sh_eth_write(ndev, 0, CDCR); /* (write clear) */
2246 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, LCCR);
2247 sh_eth_write(ndev, 0, LCCR); /* (write clear) */
2248
2249 if (sh_eth_is_gether(mdp)) {
2250 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CERCR);
2251 sh_eth_write(ndev, 0, CERCR); /* (write clear) */
2252 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CEECR);
2253 sh_eth_write(ndev, 0, CEECR); /* (write clear) */
2254 } else {
2255 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CNDCR);
2256 sh_eth_write(ndev, 0, CNDCR); /* (write clear) */
2257 }
2258
2259 return &ndev->stats;
2260}
2261
86a74ff2
NI		 2262/* device close function */
2263static int sh_eth_close(struct net_device *ndev)
2264{
2265 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 2266
2267 netif_stop_queue(ndev);
2268
283e38db
BH		 2269 /* Serialise with the interrupt handler and NAPI, then disable
2270 * interrupts. We have to clear the irq_enabled flag first to
2271 * ensure that interrupts won't be re-enabled.
2272 */
2273 mdp->irq_enabled = false;
2274 synchronize_irq(ndev->irq);
2275 napi_disable(&mdp->napi);
4a55530f 2276 sh_eth_write(ndev, 0x0000, EESIPR);
86a74ff2 2277
740c7f31 2278 sh_eth_dev_exit(ndev);
86a74ff2
NI		 2279
2280 /* PHY Disconnect */
2281 if (mdp->phydev) {
2282 phy_stop(mdp->phydev);
2283 phy_disconnect(mdp->phydev);
4f9dce23 2284 mdp->phydev = NULL;
86a74ff2
NI		 2285 }
2286
2287 free_irq(ndev->irq, ndev);
2288
86a74ff2
NI		 2289 /* Free all the skbuffs in the Rx queue. */
2290 sh_eth_ring_free(ndev);
2291
2292 /* free DMA buffer */
91c77550 2293 sh_eth_free_dma_buffer(mdp);
86a74ff2 2294
bcd5149d
MD		 2295 pm_runtime_put_sync(&mdp->pdev->dev);
2296
7fa2955f 2297 mdp->is_opened = 0;
bcd5149d 2298
7fa2955f 2299 return 0;
86a74ff2
NI		 2300}
2301
bb7d92e3 2302/* ioctl to device function */
128296fc 2303static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
86a74ff2
NI		 2304{
2305 struct sh_eth_private *mdp = netdev_priv(ndev);
2306 struct phy_device *phydev = mdp->phydev;
2307
2308 if (!netif_running(ndev))
2309 return -EINVAL;
2310
2311 if (!phydev)
2312 return -ENODEV;
2313
28b04113 2314 return phy_mii_ioctl(phydev, rq, cmd);
86a74ff2
NI		 2315}
2316
6743fe6d
YS		 2317/* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
2318static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp,
2319 int entry)
2320{
2321 return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4);
2322}
2323
2324static u32 sh_eth_tsu_get_post_mask(int entry)
2325{
2326 return 0x0f << (28 - ((entry % 8) * 4));
2327}
2328
2329static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
2330{
2331 return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
2332}
2333
2334static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
2335 int entry)
2336{
2337 struct sh_eth_private *mdp = netdev_priv(ndev);
2338 u32 tmp;
2339 void *reg_offset;
2340
2341 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2342 tmp = ioread32(reg_offset);
2343 iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset);
2344}
2345
2346static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
2347 int entry)
2348{
2349 struct sh_eth_private *mdp = netdev_priv(ndev);
2350 u32 post_mask, ref_mask, tmp;
2351 void *reg_offset;
2352
2353 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2354 post_mask = sh_eth_tsu_get_post_mask(entry);
2355 ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
2356
2357 tmp = ioread32(reg_offset);
2358 iowrite32(tmp & ~post_mask, reg_offset);
2359
2360 /* If other port enables, the function returns "true" */
2361 return tmp & ref_mask;
2362}
2363
2364static int sh_eth_tsu_busy(struct net_device *ndev)
2365{
2366 int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
2367 struct sh_eth_private *mdp = netdev_priv(ndev);
2368
2369 while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
2370 udelay(10);
2371 timeout--;
2372 if (timeout <= 0) {
da246855 2373 netdev_err(ndev, "%s: timeout\n", __func__);
6743fe6d
YS		 2374 return -ETIMEDOUT;
2375 }
2376 }
2377
2378 return 0;
2379}
2380
2381static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg,
2382 const u8 *addr)
2383{
2384 u32 val;
2385
2386 val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
2387 iowrite32(val, reg);
2388 if (sh_eth_tsu_busy(ndev) < 0)
2389 return -EBUSY;
2390
2391 val = addr[4] << 8 | addr[5];
2392 iowrite32(val, reg + 4);
2393 if (sh_eth_tsu_busy(ndev) < 0)
2394 return -EBUSY;
2395
2396 return 0;
2397}
2398
2399static void sh_eth_tsu_read_entry(void *reg, u8 *addr)
2400{
2401 u32 val;
2402
2403 val = ioread32(reg);
2404 addr[0] = (val >> 24) & 0xff;
2405 addr[1] = (val >> 16) & 0xff;
2406 addr[2] = (val >> 8) & 0xff;
2407 addr[3] = val & 0xff;
2408 val = ioread32(reg + 4);
2409 addr[4] = (val >> 8) & 0xff;
2410 addr[5] = val & 0xff;
2411}
2412
2413
2414static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
2415{
2416 struct sh_eth_private *mdp = netdev_priv(ndev);
2417 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2418 int i;
2419 u8 c_addr[ETH_ALEN];
2420
2421 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2422 sh_eth_tsu_read_entry(reg_offset, c_addr);
c4bde29c 2423 if (ether_addr_equal(addr, c_addr))
6743fe6d
YS		 2424 return i;
2425 }
2426
2427 return -ENOENT;
2428}
2429
2430static int sh_eth_tsu_find_empty(struct net_device *ndev)
2431{
2432 u8 blank[ETH_ALEN];
2433 int entry;
2434
2435 memset(blank, 0, sizeof(blank));
2436 entry = sh_eth_tsu_find_entry(ndev, blank);
2437 return (entry < 0) ? -ENOMEM : entry;
2438}
2439
2440static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
2441 int entry)
2442{
2443 struct sh_eth_private *mdp = netdev_priv(ndev);
2444 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2445 int ret;
2446 u8 blank[ETH_ALEN];
2447
2448 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
2449 ~(1 << (31 - entry)), TSU_TEN);
2450
2451 memset(blank, 0, sizeof(blank));
2452 ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
2453 if (ret < 0)
2454 return ret;
2455 return 0;
2456}
2457
2458static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
2459{
2460 struct sh_eth_private *mdp = netdev_priv(ndev);
2461 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2462 int i, ret;
2463
2464 if (!mdp->cd->tsu)
2465 return 0;
2466
2467 i = sh_eth_tsu_find_entry(ndev, addr);
2468 if (i < 0) {
2469 /* No entry found, create one */
2470 i = sh_eth_tsu_find_empty(ndev);
2471 if (i < 0)
2472 return -ENOMEM;
2473 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
2474 if (ret < 0)
2475 return ret;
2476
2477 /* Enable the entry */
2478 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
2479 (1 << (31 - i)), TSU_TEN);
2480 }
2481
2482 /* Entry found or created, enable POST */
2483 sh_eth_tsu_enable_cam_entry_post(ndev, i);
2484
2485 return 0;
2486}
2487
2488static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
2489{
2490 struct sh_eth_private *mdp = netdev_priv(ndev);
2491 int i, ret;
2492
2493 if (!mdp->cd->tsu)
2494 return 0;
2495
2496 i = sh_eth_tsu_find_entry(ndev, addr);
2497 if (i) {
2498 /* Entry found */
2499 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2500 goto done;
2501
2502 /* Disable the entry if both ports was disabled */
2503 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2504 if (ret < 0)
2505 return ret;
2506 }
2507done:
2508 return 0;
2509}
2510
2511static int sh_eth_tsu_purge_all(struct net_device *ndev)
2512{
2513 struct sh_eth_private *mdp = netdev_priv(ndev);
2514 int i, ret;
2515
b37feed7 2516 if (!mdp->cd->tsu)
6743fe6d
YS		 2517 return 0;
2518
2519 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
2520 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2521 continue;
2522
2523 /* Disable the entry if both ports was disabled */
2524 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2525 if (ret < 0)
2526 return ret;
2527 }
2528
2529 return 0;
2530}
2531
2532static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
2533{
2534 struct sh_eth_private *mdp = netdev_priv(ndev);
2535 u8 addr[ETH_ALEN];
2536 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2537 int i;
2538
b37feed7 2539 if (!mdp->cd->tsu)
6743fe6d
YS		 2540 return;
2541
2542 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2543 sh_eth_tsu_read_entry(reg_offset, addr);
2544 if (is_multicast_ether_addr(addr))
2545 sh_eth_tsu_del_entry(ndev, addr);
2546 }
2547}
2548
b37feed7
BH		 2549/* Update promiscuous flag and multicast filter */
2550static void sh_eth_set_rx_mode(struct net_device *ndev)
86a74ff2 2551{
6743fe6d
YS		 2552 struct sh_eth_private *mdp = netdev_priv(ndev);
2553 u32 ecmr_bits;
2554 int mcast_all = 0;
2555 unsigned long flags;
2556
2557 spin_lock_irqsave(&mdp->lock, flags);
128296fc 2558 /* Initial condition is MCT = 1, PRM = 0.
6743fe6d
YS		 2559 * Depending on ndev->flags, set PRM or clear MCT
2560 */
b37feed7
BH		 2561 ecmr_bits = sh_eth_read(ndev, ECMR) & ~ECMR_PRM;
2562 if (mdp->cd->tsu)
2563 ecmr_bits |= ECMR_MCT;
6743fe6d
YS		 2564
2565 if (!(ndev->flags & IFF_MULTICAST)) {
2566 sh_eth_tsu_purge_mcast(ndev);
2567 mcast_all = 1;
2568 }
2569 if (ndev->flags & IFF_ALLMULTI) {
2570 sh_eth_tsu_purge_mcast(ndev);
2571 ecmr_bits &= ~ECMR_MCT;
2572 mcast_all = 1;
2573 }
2574
86a74ff2 2575 if (ndev->flags & IFF_PROMISC) {
6743fe6d
YS		 2576 sh_eth_tsu_purge_all(ndev);
2577 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2578 } else if (mdp->cd->tsu) {
2579 struct netdev_hw_addr *ha;
2580 netdev_for_each_mc_addr(ha, ndev) {
2581 if (mcast_all && is_multicast_ether_addr(ha->addr))
2582 continue;
2583
2584 if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2585 if (!mcast_all) {
2586 sh_eth_tsu_purge_mcast(ndev);
2587 ecmr_bits &= ~ECMR_MCT;
2588 mcast_all = 1;
2589 }
2590 }
2591 }
86a74ff2 2592 }
6743fe6d
YS		 2593
2594 /* update the ethernet mode */
2595 sh_eth_write(ndev, ecmr_bits, ECMR);
2596
2597 spin_unlock_irqrestore(&mdp->lock, flags);
86a74ff2 2598}
71cc7c37
YS		 2599
2600static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2601{
2602 if (!mdp->port)
2603 return TSU_VTAG0;
2604 else
2605 return TSU_VTAG1;
2606}
2607
80d5c368
PM		 2608static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
2609 __be16 proto, u16 vid)
71cc7c37
YS		 2610{
2611 struct sh_eth_private *mdp = netdev_priv(ndev);
2612 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2613
2614 if (unlikely(!mdp->cd->tsu))
2615 return -EPERM;
2616
2617 /* No filtering if vid = 0 */
2618 if (!vid)
2619 return 0;
2620
2621 mdp->vlan_num_ids++;
2622
128296fc 2623 /* The controller has one VLAN tag HW filter. So, if the filter is
71cc7c37
YS		 2624 * already enabled, the driver disables it and the filte
2625 */
2626 if (mdp->vlan_num_ids > 1) {
2627 /* disable VLAN filter */
2628 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2629 return 0;
2630 }
2631
2632 sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
2633 vtag_reg_index);
2634
2635 return 0;
2636}
2637
80d5c368
PM		 2638static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
2639 __be16 proto, u16 vid)
71cc7c37
YS		 2640{
2641 struct sh_eth_private *mdp = netdev_priv(ndev);
2642 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2643
2644 if (unlikely(!mdp->cd->tsu))
2645 return -EPERM;
2646
2647 /* No filtering if vid = 0 */
2648 if (!vid)
2649 return 0;
2650
2651 mdp->vlan_num_ids--;
2652 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2653
2654 return 0;
2655}
86a74ff2
NI		 2656
2657/* SuperH's TSU register init function */
4a55530f 2658static void sh_eth_tsu_init(struct sh_eth_private *mdp)
86a74ff2 2659{
db893473
SH		 2660 if (sh_eth_is_rz_fast_ether(mdp)) {
2661 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2662 return;
2663 }
2664
4a55530f
YS		 2665 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */
2666 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */
2667 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */
2668 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
2669 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
2670 sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
2671 sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
2672 sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
2673 sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
2674 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
c5ed5368
YS		 2675 if (sh_eth_is_gether(mdp)) {
2676 sh_eth_tsu_write(mdp, 0, TSU_QTAG0); /* Disable QTAG(0->1) */
2677 sh_eth_tsu_write(mdp, 0, TSU_QTAG1); /* Disable QTAG(1->0) */
2678 } else {
2679 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */
2680 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */
2681 }
4a55530f
YS		 2682 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */
2683 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */
2684 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2685 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */
2686 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */
2687 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */
2688 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */
86a74ff2
NI		 2689}
2690
2691/* MDIO bus release function */
bd920ff5 2692static int sh_mdio_release(struct sh_eth_private *mdp)
86a74ff2 2693{
86a74ff2 2694 /* unregister mdio bus */
bd920ff5 2695 mdiobus_unregister(mdp->mii_bus);
86a74ff2
NI		 2696
2697 /* free bitbang info */
bd920ff5 2698 free_mdio_bitbang(mdp->mii_bus);
86a74ff2
NI		 2699
2700 return 0;
2701}
2702
2703/* MDIO bus init function */
bd920ff5 2704static int sh_mdio_init(struct sh_eth_private *mdp,
b3017e6a 2705 struct sh_eth_plat_data *pd)
86a74ff2
NI		 2706{
2707 int ret, i;
2708 struct bb_info *bitbang;
bd920ff5 2709 struct platform_device *pdev = mdp->pdev;
aa8d4225 2710 struct device *dev = &mdp->pdev->dev;
86a74ff2
NI		 2711
2712 /* create bit control struct for PHY */
aa8d4225 2713 bitbang = devm_kzalloc(dev, sizeof(struct bb_info), GFP_KERNEL);
f738a13d
LP		 2714 if (!bitbang)
2715 return -ENOMEM;
86a74ff2
NI		 2716
2717 /* bitbang init */
ae70644d 2718 bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
b3017e6a 2719 bitbang->set_gate = pd->set_mdio_gate;
dfed5e7f
SS		 2720 bitbang->mdi_msk = PIR_MDI;
2721 bitbang->mdo_msk = PIR_MDO;
2722 bitbang->mmd_msk = PIR_MMD;
2723 bitbang->mdc_msk = PIR_MDC;
86a74ff2
NI		 2724 bitbang->ctrl.ops = &bb_ops;
2725
c2e07b3a 2726 /* MII controller setting */
86a74ff2 2727 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
f738a13d
LP		 2728 if (!mdp->mii_bus)
2729 return -ENOMEM;
86a74ff2
NI		 2730
2731 /* Hook up MII support for ethtool */
2732 mdp->mii_bus->name = "sh_mii";
a5bd6060 2733 mdp->mii_bus->parent = dev;
5278fb54 2734 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
bd920ff5 2735 pdev->name, pdev->id);
86a74ff2
NI		 2736
2737 /* PHY IRQ */
86b5d251
SS		 2738 mdp->mii_bus->irq = devm_kmalloc_array(dev, PHY_MAX_ADDR, sizeof(int),
2739 GFP_KERNEL);
86a74ff2
NI		 2740 if (!mdp->mii_bus->irq) {
2741 ret = -ENOMEM;
2742 goto out_free_bus;
2743 }
2744
bd920ff5
LP		 2745 /* register MDIO bus */
2746 if (dev->of_node) {
2747 ret = of_mdiobus_register(mdp->mii_bus, dev->of_node);
702eca02
BD		 2748 } else {
2749 for (i = 0; i < PHY_MAX_ADDR; i++)
2750 mdp->mii_bus->irq[i] = PHY_POLL;
2751 if (pd->phy_irq > 0)
2752 mdp->mii_bus->irq[pd->phy] = pd->phy_irq;
2753
2754 ret = mdiobus_register(mdp->mii_bus);
2755 }
2756
86a74ff2 2757 if (ret)
d5e07e69 2758 goto out_free_bus;
86a74ff2 2759
86a74ff2
NI		 2760 return 0;
2761
86a74ff2 2762out_free_bus:
298cf9be 2763 free_mdio_bitbang(mdp->mii_bus);
86a74ff2
NI		 2764 return ret;
2765}
2766
4a55530f
YS		 2767static const u16 *sh_eth_get_register_offset(int register_type)
2768{
2769 const u16 *reg_offset = NULL;
2770
2771 switch (register_type) {
2772 case SH_ETH_REG_GIGABIT:
2773 reg_offset = sh_eth_offset_gigabit;
2774 break;
db893473
SH		 2775 case SH_ETH_REG_FAST_RZ:
2776 reg_offset = sh_eth_offset_fast_rz;
2777 break;
a3f109bd
SS		 2778 case SH_ETH_REG_FAST_RCAR:
2779 reg_offset = sh_eth_offset_fast_rcar;
2780 break;
4a55530f
YS		 2781 case SH_ETH_REG_FAST_SH4:
2782 reg_offset = sh_eth_offset_fast_sh4;
2783 break;
2784 case SH_ETH_REG_FAST_SH3_SH2:
2785 reg_offset = sh_eth_offset_fast_sh3_sh2;
2786 break;
2787 default:
4a55530f
YS		 2788 break;
2789 }
2790
2791 return reg_offset;
2792}
2793
8f728d79 2794static const struct net_device_ops sh_eth_netdev_ops = {
ebf84eaa
AB		 2795 .ndo_open = sh_eth_open,
2796 .ndo_stop = sh_eth_close,
2797 .ndo_start_xmit = sh_eth_start_xmit,
2798 .ndo_get_stats = sh_eth_get_stats,
b37feed7 2799 .ndo_set_rx_mode = sh_eth_set_rx_mode,
ebf84eaa
AB		 2800 .ndo_tx_timeout = sh_eth_tx_timeout,
2801 .ndo_do_ioctl = sh_eth_do_ioctl,
2802 .ndo_validate_addr = eth_validate_addr,
2803 .ndo_set_mac_address = eth_mac_addr,
2804 .ndo_change_mtu = eth_change_mtu,
2805};
2806
8f728d79
SS		 2807static const struct net_device_ops sh_eth_netdev_ops_tsu = {
2808 .ndo_open = sh_eth_open,
2809 .ndo_stop = sh_eth_close,
2810 .ndo_start_xmit = sh_eth_start_xmit,
2811 .ndo_get_stats = sh_eth_get_stats,
b37feed7 2812 .ndo_set_rx_mode = sh_eth_set_rx_mode,
8f728d79
SS		 2813 .ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid,
2814 .ndo_vlan_rx_kill_vid = sh_eth_vlan_rx_kill_vid,
2815 .ndo_tx_timeout = sh_eth_tx_timeout,
2816 .ndo_do_ioctl = sh_eth_do_ioctl,
2817 .ndo_validate_addr = eth_validate_addr,
2818 .ndo_set_mac_address = eth_mac_addr,
2819 .ndo_change_mtu = eth_change_mtu,
2820};
2821
b356e978
SS		 2822#ifdef CONFIG_OF
2823static struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
2824{
2825 struct device_node *np = dev->of_node;
2826 struct sh_eth_plat_data *pdata;
b356e978
SS		 2827 const char *mac_addr;
2828
2829 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
2830 if (!pdata)
2831 return NULL;
2832
2833 pdata->phy_interface = of_get_phy_mode(np);
2834
b356e978
SS		 2835 mac_addr = of_get_mac_address(np);
2836 if (mac_addr)
2837 memcpy(pdata->mac_addr, mac_addr, ETH_ALEN);
2838
2839 pdata->no_ether_link =
2840 of_property_read_bool(np, "renesas,no-ether-link");
2841 pdata->ether_link_active_low =
2842 of_property_read_bool(np, "renesas,ether-link-active-low");
2843
2844 return pdata;
2845}
2846
2847static const struct of_device_id sh_eth_match_table[] = {
2848 { .compatible = "renesas,gether-r8a7740", .data = &r8a7740_data },
2849 { .compatible = "renesas,ether-r8a7778", .data = &r8a777x_data },
2850 { .compatible = "renesas,ether-r8a7779", .data = &r8a777x_data },
2851 { .compatible = "renesas,ether-r8a7790", .data = &r8a779x_data },
2852 { .compatible = "renesas,ether-r8a7791", .data = &r8a779x_data },
9488e1e5 2853 { .compatible = "renesas,ether-r8a7793", .data = &r8a779x_data },
0f76b9d8 2854 { .compatible = "renesas,ether-r8a7794", .data = &r8a779x_data },
b356e978
SS		 2855 { .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data },
2856 { }
2857};
2858MODULE_DEVICE_TABLE(of, sh_eth_match_table);
2859#else
2860static inline struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
2861{
2862 return NULL;
2863}
2864#endif
2865
86a74ff2
NI		 2866static int sh_eth_drv_probe(struct platform_device *pdev)
2867{
9c38657c 2868 int ret, devno = 0;
86a74ff2
NI		 2869 struct resource *res;
2870 struct net_device *ndev = NULL;
ec0d7551 2871 struct sh_eth_private *mdp = NULL;
0b76b862 2872 struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev);
afe391ad 2873 const struct platform_device_id *id = platform_get_device_id(pdev);
86a74ff2
NI		 2874
2875 /* get base addr */
2876 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
86a74ff2
NI		 2877
2878 ndev = alloc_etherdev(sizeof(struct sh_eth_private));
f738a13d
LP		 2879 if (!ndev)
2880 return -ENOMEM;
86a74ff2 2881
b5893a08
BD		 2882 pm_runtime_enable(&pdev->dev);
2883 pm_runtime_get_sync(&pdev->dev);
2884
86a74ff2
NI		 2885 devno = pdev->id;
2886 if (devno < 0)
2887 devno = 0;
2888
2889 ndev->dma = -1;
cc3c080d 2890 ret = platform_get_irq(pdev, 0);
2891 if (ret < 0) {
86a74ff2
NI		 2892 ret = -ENODEV;
2893 goto out_release;
2894 }
cc3c080d 2895 ndev->irq = ret;
86a74ff2
NI		 2896
2897 SET_NETDEV_DEV(ndev, &pdev->dev);
2898
86a74ff2 2899 mdp = netdev_priv(ndev);
525b8075
YS		 2900 mdp->num_tx_ring = TX_RING_SIZE;
2901 mdp->num_rx_ring = RX_RING_SIZE;
d5e07e69
SS		 2902 mdp->addr = devm_ioremap_resource(&pdev->dev, res);
2903 if (IS_ERR(mdp->addr)) {
2904 ret = PTR_ERR(mdp->addr);
ae70644d
YS		 2905 goto out_release;
2906 }
2907
c960804f
VB		 2908 ndev->base_addr = res->start;
2909
86a74ff2 2910 spin_lock_init(&mdp->lock);
bcd5149d 2911 mdp->pdev = pdev;
86a74ff2 2912
b356e978
SS		 2913 if (pdev->dev.of_node)
2914 pd = sh_eth_parse_dt(&pdev->dev);
3b4c5cbf
SS		 2915 if (!pd) {
2916 dev_err(&pdev->dev, "no platform data\n");
2917 ret = -EINVAL;
2918 goto out_release;
2919 }
2920
86a74ff2 2921 /* get PHY ID */
71557a37 2922 mdp->phy_id = pd->phy;
e47c9052 2923 mdp->phy_interface = pd->phy_interface;
71557a37
YS		 2924 /* EDMAC endian */
2925 mdp->edmac_endian = pd->edmac_endian;
4923576b
YS		 2926 mdp->no_ether_link = pd->no_ether_link;
2927 mdp->ether_link_active_low = pd->ether_link_active_low;
86a74ff2 2928
380af9e3 2929 /* set cpu data */
b356e978
SS		 2930 if (id) {
2931 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data;
2932 } else {
2933 const struct of_device_id *match;
2934
2935 match = of_match_device(of_match_ptr(sh_eth_match_table),
2936 &pdev->dev);
2937 mdp->cd = (struct sh_eth_cpu_data *)match->data;
2938 }
a3153d8c 2939 mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type);
264be2f5
SS		 2940 if (!mdp->reg_offset) {
2941 dev_err(&pdev->dev, "Unknown register type (%d)\n",
2942 mdp->cd->register_type);
2943 ret = -EINVAL;
2944 goto out_release;
2945 }
380af9e3
YS		 2946 sh_eth_set_default_cpu_data(mdp->cd);
2947
86a74ff2 2948 /* set function */
8f728d79
SS		 2949 if (mdp->cd->tsu)
2950 ndev->netdev_ops = &sh_eth_netdev_ops_tsu;
2951 else
2952 ndev->netdev_ops = &sh_eth_netdev_ops;
7ad24ea4 2953 ndev->ethtool_ops = &sh_eth_ethtool_ops;
86a74ff2
NI		 2954 ndev->watchdog_timeo = TX_TIMEOUT;
2955
dc19e4e5
NI		 2956 /* debug message level */
2957 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
86a74ff2
NI		 2958
2959 /* read and set MAC address */
748031f9 2960 read_mac_address(ndev, pd->mac_addr);
ff6e7228
SS		 2961 if (!is_valid_ether_addr(ndev->dev_addr)) {
2962 dev_warn(&pdev->dev,
2963 "no valid MAC address supplied, using a random one.\n");
2964 eth_hw_addr_random(ndev);
2965 }
86a74ff2 2966
6ba88021
YS		 2967 /* ioremap the TSU registers */
2968 if (mdp->cd->tsu) {
2969 struct resource *rtsu;
2970 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
d5e07e69
SS		 2971 mdp->tsu_addr = devm_ioremap_resource(&pdev->dev, rtsu);
2972 if (IS_ERR(mdp->tsu_addr)) {
2973 ret = PTR_ERR(mdp->tsu_addr);
fc0c0900
SS		 2974 goto out_release;
2975 }
6743fe6d 2976 mdp->port = devno % 2;
f646968f 2977 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER;
6ba88021
YS		 2978 }
2979
150647fb
YS		 2980 /* initialize first or needed device */
2981 if (!devno || pd->needs_init) {
380af9e3
YS		 2982 if (mdp->cd->chip_reset)
2983 mdp->cd->chip_reset(ndev);
86a74ff2 2984
4986b996
YS		 2985 if (mdp->cd->tsu) {
2986 /* TSU init (Init only)*/
2987 sh_eth_tsu_init(mdp);
2988 }
86a74ff2
NI		 2989 }
2990
966d6dbb
HN		 2991 if (mdp->cd->rmiimode)
2992 sh_eth_write(ndev, 0x1, RMIIMODE);
2993
daacf03f
LP		 2994 /* MDIO bus init */
2995 ret = sh_mdio_init(mdp, pd);
2996 if (ret) {
2997 dev_err(&ndev->dev, "failed to initialise MDIO\n");
2998 goto out_release;
2999 }
3000
3719109d
SS		 3001 netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64);
3002
86a74ff2
NI		 3003 /* network device register */
3004 ret = register_netdev(ndev);
3005 if (ret)
3719109d 3006 goto out_napi_del;
86a74ff2 3007
25985edc 3008 /* print device information */
f75f14ec
SS		 3009 netdev_info(ndev, "Base address at 0x%x, %pM, IRQ %d.\n",
3010 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
86a74ff2 3011
b5893a08 3012 pm_runtime_put(&pdev->dev);
86a74ff2
NI		 3013 platform_set_drvdata(pdev, ndev);
3014
3015 return ret;
3016
3719109d
SS		 3017out_napi_del:
3018 netif_napi_del(&mdp->napi);
daacf03f 3019 sh_mdio_release(mdp);
3719109d 3020
86a74ff2
NI		 3021out_release:
3022 /* net_dev free */
3023 if (ndev)
3024 free_netdev(ndev);
3025
b5893a08
BD		 3026 pm_runtime_put(&pdev->dev);
3027 pm_runtime_disable(&pdev->dev);
86a74ff2
NI		 3028 return ret;
3029}
3030
3031static int sh_eth_drv_remove(struct platform_device *pdev)
3032{
3033 struct net_device *ndev = platform_get_drvdata(pdev);
3719109d 3034 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2 3035
86a74ff2 3036 unregister_netdev(ndev);
3719109d 3037 netif_napi_del(&mdp->napi);
daacf03f 3038 sh_mdio_release(mdp);
bcd5149d 3039 pm_runtime_disable(&pdev->dev);
86a74ff2 3040 free_netdev(ndev);
86a74ff2
NI		 3041
3042 return 0;
3043}
3044
540ad1b8 3045#ifdef CONFIG_PM
b71af046
MU		 3046#ifdef CONFIG_PM_SLEEP
3047static int sh_eth_suspend(struct device *dev)
3048{
3049 struct net_device *ndev = dev_get_drvdata(dev);
3050 int ret = 0;
3051
3052 if (netif_running(ndev)) {
3053 netif_device_detach(ndev);
3054 ret = sh_eth_close(ndev);
3055 }
3056
3057 return ret;
3058}
3059
3060static int sh_eth_resume(struct device *dev)
3061{
3062 struct net_device *ndev = dev_get_drvdata(dev);
3063 int ret = 0;
3064
3065 if (netif_running(ndev)) {
3066 ret = sh_eth_open(ndev);
3067 if (ret < 0)
3068 return ret;
3069 netif_device_attach(ndev);
3070 }
3071
3072 return ret;
3073}
3074#endif
3075
bcd5149d
MD		 3076static int sh_eth_runtime_nop(struct device *dev)
3077{
128296fc 3078 /* Runtime PM callback shared between ->runtime_suspend()
bcd5149d
MD		 3079 * and ->runtime_resume(). Simply returns success.
3080 *
3081 * This driver re-initializes all registers after
3082 * pm_runtime_get_sync() anyway so there is no need
3083 * to save and restore registers here.
3084 */
3085 return 0;
3086}
3087
540ad1b8 3088static const struct dev_pm_ops sh_eth_dev_pm_ops = {
b71af046 3089 SET_SYSTEM_SLEEP_PM_OPS(sh_eth_suspend, sh_eth_resume)
e7d7e898 3090 SET_RUNTIME_PM_OPS(sh_eth_runtime_nop, sh_eth_runtime_nop, NULL)
bcd5149d 3091};
540ad1b8
NI		 3092#define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
3093#else
3094#define SH_ETH_PM_OPS NULL
3095#endif
bcd5149d 3096
afe391ad 3097static struct platform_device_id sh_eth_id_table[] = {
c18a79ab 3098 { "sh7619-ether", (kernel_ulong_t)&sh7619_data },
7bbe150d 3099 { "sh771x-ether", (kernel_ulong_t)&sh771x_data },
9c3beaab 3100 { "sh7724-ether", (kernel_ulong_t)&sh7724_data },
f5d12767 3101 { "sh7734-gether", (kernel_ulong_t)&sh7734_data },
24549e2a
SS		 3102 { "sh7757-ether", (kernel_ulong_t)&sh7757_data },
3103 { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga },
f5d12767 3104 { "sh7763-gether", (kernel_ulong_t)&sh7763_data },
db893473 3105 { "r7s72100-ether", (kernel_ulong_t)&r7s72100_data },
e5c9b4cd 3106 { "r8a7740-gether", (kernel_ulong_t)&r8a7740_data },
589ebdef 3107 { "r8a777x-ether", (kernel_ulong_t)&r8a777x_data },
94a12b15
SS		 3108 { "r8a7790-ether", (kernel_ulong_t)&r8a779x_data },
3109 { "r8a7791-ether", (kernel_ulong_t)&r8a779x_data },
9488e1e5 3110 { "r8a7793-ether", (kernel_ulong_t)&r8a779x_data },
0f76b9d8 3111 { "r8a7794-ether", (kernel_ulong_t)&r8a779x_data },
afe391ad
SS		 3112 { }
3113};
3114MODULE_DEVICE_TABLE(platform, sh_eth_id_table);
3115
86a74ff2
NI		 3116static struct platform_driver sh_eth_driver = {
3117 .probe = sh_eth_drv_probe,
3118 .remove = sh_eth_drv_remove,
afe391ad 3119 .id_table = sh_eth_id_table,
86a74ff2
NI		 3120 .driver = {
3121 .name = CARDNAME,
540ad1b8 3122 .pm = SH_ETH_PM_OPS,
b356e978 3123 .of_match_table = of_match_ptr(sh_eth_match_table),
86a74ff2
NI		 3124 },
3125};
3126
db62f684 3127module_platform_driver(sh_eth_driver);
86a74ff2
NI		 3128
3129MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
3130MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
3131MODULE_LICENSE("GPL v2");
ubuntu-zesty-kernel mirror