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sh_eth: kill useless initializers
[mirror_ubuntu-zesty-kernel.git] / drivers / net / ethernet / renesas / sh_eth.c
CommitLineData
128296fc 1/* SuperH Ethernet device driver
86a74ff2 2 *
966d6dbb 3 * Copyright (C) 2014 Renesas Electronics Corporation
f0e81fec 4 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu
b356e978 5 * Copyright (C) 2008-2014 Renesas Solutions Corp.
b2b14d2f 6 * Copyright (C) 2013-2016 Cogent Embedded, Inc.
702eca02 7 * Copyright (C) 2014 Codethink Limited
86a74ff2
NI		 8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms and conditions of the GNU General Public License,
11 * version 2, as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
86a74ff2
NI		 17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 */
21
0654011d
YS		 22#include <linux/module.h>
23#include <linux/kernel.h>
24#include <linux/spinlock.h>
6a27cded 25#include <linux/interrupt.h>
86a74ff2
NI		 26#include <linux/dma-mapping.h>
27#include <linux/etherdevice.h>
28#include <linux/delay.h>
29#include <linux/platform_device.h>
30#include <linux/mdio-bitbang.h>
31#include <linux/netdevice.h>
b356e978
SS		 32#include <linux/of.h>
33#include <linux/of_device.h>
34#include <linux/of_irq.h>
35#include <linux/of_net.h>
86a74ff2
NI		 36#include <linux/phy.h>
37#include <linux/cache.h>
38#include <linux/io.h>
bcd5149d 39#include <linux/pm_runtime.h>
5a0e3ad6 40#include <linux/slab.h>
dc19e4e5 41#include <linux/ethtool.h>
fdb37a7f 42#include <linux/if_vlan.h>
f0e81fec 43#include <linux/clk.h>
d4fa0e35 44#include <linux/sh_eth.h>
702eca02 45#include <linux/of_mdio.h>
86a74ff2
NI		 46
47#include "sh_eth.h"
48
dc19e4e5
NI		 49#define SH_ETH_DEF_MSG_ENABLE \
50 (NETIF_MSG_LINK | \
51 NETIF_MSG_TIMER | \
52 NETIF_MSG_RX_ERR| \
53 NETIF_MSG_TX_ERR)
54
2274d375
SS		 55#define SH_ETH_OFFSET_INVALID ((u16)~0)
56
3365711d
BH		 57#define SH_ETH_OFFSET_DEFAULTS \
58 [0 ... SH_ETH_MAX_REGISTER_OFFSET - 1] = SH_ETH_OFFSET_INVALID
59
c0013f6f 60static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
3365711d
BH		 61 SH_ETH_OFFSET_DEFAULTS,
62
c0013f6f
SS		 63 [EDSR] = 0x0000,
64 [EDMR] = 0x0400,
65 [EDTRR] = 0x0408,
66 [EDRRR] = 0x0410,
67 [EESR] = 0x0428,
68 [EESIPR] = 0x0430,
69 [TDLAR] = 0x0010,
70 [TDFAR] = 0x0014,
71 [TDFXR] = 0x0018,
72 [TDFFR] = 0x001c,
73 [RDLAR] = 0x0030,
74 [RDFAR] = 0x0034,
75 [RDFXR] = 0x0038,
76 [RDFFR] = 0x003c,
77 [TRSCER] = 0x0438,
78 [RMFCR] = 0x0440,
79 [TFTR] = 0x0448,
80 [FDR] = 0x0450,
81 [RMCR] = 0x0458,
82 [RPADIR] = 0x0460,
83 [FCFTR] = 0x0468,
84 [CSMR] = 0x04E4,
85
86 [ECMR] = 0x0500,
87 [ECSR] = 0x0510,
88 [ECSIPR] = 0x0518,
89 [PIR] = 0x0520,
90 [PSR] = 0x0528,
91 [PIPR] = 0x052c,
92 [RFLR] = 0x0508,
93 [APR] = 0x0554,
94 [MPR] = 0x0558,
95 [PFTCR] = 0x055c,
96 [PFRCR] = 0x0560,
97 [TPAUSER] = 0x0564,
98 [GECMR] = 0x05b0,
99 [BCULR] = 0x05b4,
100 [MAHR] = 0x05c0,
101 [MALR] = 0x05c8,
102 [TROCR] = 0x0700,
103 [CDCR] = 0x0708,
104 [LCCR] = 0x0710,
105 [CEFCR] = 0x0740,
106 [FRECR] = 0x0748,
107 [TSFRCR] = 0x0750,
108 [TLFRCR] = 0x0758,
109 [RFCR] = 0x0760,
110 [CERCR] = 0x0768,
111 [CEECR] = 0x0770,
112 [MAFCR] = 0x0778,
113 [RMII_MII] = 0x0790,
114
115 [ARSTR] = 0x0000,
116 [TSU_CTRST] = 0x0004,
117 [TSU_FWEN0] = 0x0010,
118 [TSU_FWEN1] = 0x0014,
119 [TSU_FCM] = 0x0018,
120 [TSU_BSYSL0] = 0x0020,
121 [TSU_BSYSL1] = 0x0024,
122 [TSU_PRISL0] = 0x0028,
123 [TSU_PRISL1] = 0x002c,
124 [TSU_FWSL0] = 0x0030,
125 [TSU_FWSL1] = 0x0034,
126 [TSU_FWSLC] = 0x0038,
127 [TSU_QTAG0] = 0x0040,
128 [TSU_QTAG1] = 0x0044,
129 [TSU_FWSR] = 0x0050,
130 [TSU_FWINMK] = 0x0054,
131 [TSU_ADQT0] = 0x0048,
132 [TSU_ADQT1] = 0x004c,
133 [TSU_VTAG0] = 0x0058,
134 [TSU_VTAG1] = 0x005c,
135 [TSU_ADSBSY] = 0x0060,
136 [TSU_TEN] = 0x0064,
137 [TSU_POST1] = 0x0070,
138 [TSU_POST2] = 0x0074,
139 [TSU_POST3] = 0x0078,
140 [TSU_POST4] = 0x007c,
141 [TSU_ADRH0] = 0x0100,
c0013f6f
SS		 142
143 [TXNLCR0] = 0x0080,
144 [TXALCR0] = 0x0084,
145 [RXNLCR0] = 0x0088,
146 [RXALCR0] = 0x008c,
147 [FWNLCR0] = 0x0090,
148 [FWALCR0] = 0x0094,
149 [TXNLCR1] = 0x00a0,
150 [TXALCR1] = 0x00a0,
151 [RXNLCR1] = 0x00a8,
152 [RXALCR1] = 0x00ac,
153 [FWNLCR1] = 0x00b0,
154 [FWALCR1] = 0x00b4,
155};
156
db893473 157static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
3365711d
BH		 158 SH_ETH_OFFSET_DEFAULTS,
159
db893473
SH		 160 [EDSR] = 0x0000,
161 [EDMR] = 0x0400,
162 [EDTRR] = 0x0408,
163 [EDRRR] = 0x0410,
164 [EESR] = 0x0428,
165 [EESIPR] = 0x0430,
166 [TDLAR] = 0x0010,
167 [TDFAR] = 0x0014,
168 [TDFXR] = 0x0018,
169 [TDFFR] = 0x001c,
170 [RDLAR] = 0x0030,
171 [RDFAR] = 0x0034,
172 [RDFXR] = 0x0038,
173 [RDFFR] = 0x003c,
174 [TRSCER] = 0x0438,
175 [RMFCR] = 0x0440,
176 [TFTR] = 0x0448,
177 [FDR] = 0x0450,
178 [RMCR] = 0x0458,
179 [RPADIR] = 0x0460,
180 [FCFTR] = 0x0468,
181 [CSMR] = 0x04E4,
182
183 [ECMR] = 0x0500,
184 [RFLR] = 0x0508,
185 [ECSR] = 0x0510,
186 [ECSIPR] = 0x0518,
187 [PIR] = 0x0520,
188 [APR] = 0x0554,
189 [MPR] = 0x0558,
190 [PFTCR] = 0x055c,
191 [PFRCR] = 0x0560,
192 [TPAUSER] = 0x0564,
193 [MAHR] = 0x05c0,
194 [MALR] = 0x05c8,
195 [CEFCR] = 0x0740,
196 [FRECR] = 0x0748,
197 [TSFRCR] = 0x0750,
198 [TLFRCR] = 0x0758,
199 [RFCR] = 0x0760,
200 [MAFCR] = 0x0778,
201
202 [ARSTR] = 0x0000,
203 [TSU_CTRST] = 0x0004,
204 [TSU_VTAG0] = 0x0058,
205 [TSU_ADSBSY] = 0x0060,
206 [TSU_TEN] = 0x0064,
207 [TSU_ADRH0] = 0x0100,
db893473
SH		 208
209 [TXNLCR0] = 0x0080,
210 [TXALCR0] = 0x0084,
211 [RXNLCR0] = 0x0088,
212 [RXALCR0] = 0x008C,
213};
214
a3f109bd 215static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
3365711d
BH		 216 SH_ETH_OFFSET_DEFAULTS,
217
a3f109bd
SS		 218 [ECMR] = 0x0300,
219 [RFLR] = 0x0308,
220 [ECSR] = 0x0310,
221 [ECSIPR] = 0x0318,
222 [PIR] = 0x0320,
223 [PSR] = 0x0328,
224 [RDMLR] = 0x0340,
225 [IPGR] = 0x0350,
226 [APR] = 0x0354,
227 [MPR] = 0x0358,
228 [RFCF] = 0x0360,
229 [TPAUSER] = 0x0364,
230 [TPAUSECR] = 0x0368,
231 [MAHR] = 0x03c0,
232 [MALR] = 0x03c8,
233 [TROCR] = 0x03d0,
234 [CDCR] = 0x03d4,
235 [LCCR] = 0x03d8,
236 [CNDCR] = 0x03dc,
237 [CEFCR] = 0x03e4,
238 [FRECR] = 0x03e8,
239 [TSFRCR] = 0x03ec,
240 [TLFRCR] = 0x03f0,
241 [RFCR] = 0x03f4,
242 [MAFCR] = 0x03f8,
243
244 [EDMR] = 0x0200,
245 [EDTRR] = 0x0208,
246 [EDRRR] = 0x0210,
247 [TDLAR] = 0x0218,
248 [RDLAR] = 0x0220,
249 [EESR] = 0x0228,
250 [EESIPR] = 0x0230,
251 [TRSCER] = 0x0238,
252 [RMFCR] = 0x0240,
253 [TFTR] = 0x0248,
254 [FDR] = 0x0250,
255 [RMCR] = 0x0258,
256 [TFUCR] = 0x0264,
257 [RFOCR] = 0x0268,
55754f19 258 [RMIIMODE] = 0x026c,
a3f109bd
SS		 259 [FCFTR] = 0x0270,
260 [TRIMD] = 0x027c,
261};
262
c0013f6f 263static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
3365711d
BH		 264 SH_ETH_OFFSET_DEFAULTS,
265
c0013f6f
SS		 266 [ECMR] = 0x0100,
267 [RFLR] = 0x0108,
268 [ECSR] = 0x0110,
269 [ECSIPR] = 0x0118,
270 [PIR] = 0x0120,
271 [PSR] = 0x0128,
272 [RDMLR] = 0x0140,
273 [IPGR] = 0x0150,
274 [APR] = 0x0154,
275 [MPR] = 0x0158,
276 [TPAUSER] = 0x0164,
277 [RFCF] = 0x0160,
278 [TPAUSECR] = 0x0168,
279 [BCFRR] = 0x016c,
280 [MAHR] = 0x01c0,
281 [MALR] = 0x01c8,
282 [TROCR] = 0x01d0,
283 [CDCR] = 0x01d4,
284 [LCCR] = 0x01d8,
285 [CNDCR] = 0x01dc,
286 [CEFCR] = 0x01e4,
287 [FRECR] = 0x01e8,
288 [TSFRCR] = 0x01ec,
289 [TLFRCR] = 0x01f0,
290 [RFCR] = 0x01f4,
291 [MAFCR] = 0x01f8,
292 [RTRATE] = 0x01fc,
293
294 [EDMR] = 0x0000,
295 [EDTRR] = 0x0008,
296 [EDRRR] = 0x0010,
297 [TDLAR] = 0x0018,
298 [RDLAR] = 0x0020,
299 [EESR] = 0x0028,
300 [EESIPR] = 0x0030,
301 [TRSCER] = 0x0038,
302 [RMFCR] = 0x0040,
303 [TFTR] = 0x0048,
304 [FDR] = 0x0050,
305 [RMCR] = 0x0058,
306 [TFUCR] = 0x0064,
307 [RFOCR] = 0x0068,
308 [FCFTR] = 0x0070,
309 [RPADIR] = 0x0078,
310 [TRIMD] = 0x007c,
311 [RBWAR] = 0x00c8,
312 [RDFAR] = 0x00cc,
313 [TBRAR] = 0x00d4,
314 [TDFAR] = 0x00d8,
315};
316
317static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
3365711d
BH		 318 SH_ETH_OFFSET_DEFAULTS,
319
d8b0426a
SS		 320 [EDMR] = 0x0000,
321 [EDTRR] = 0x0004,
322 [EDRRR] = 0x0008,
323 [TDLAR] = 0x000c,
324 [RDLAR] = 0x0010,
325 [EESR] = 0x0014,
326 [EESIPR] = 0x0018,
327 [TRSCER] = 0x001c,
328 [RMFCR] = 0x0020,
329 [TFTR] = 0x0024,
330 [FDR] = 0x0028,
331 [RMCR] = 0x002c,
332 [EDOCR] = 0x0030,
333 [FCFTR] = 0x0034,
334 [RPADIR] = 0x0038,
335 [TRIMD] = 0x003c,
336 [RBWAR] = 0x0040,
337 [RDFAR] = 0x0044,
338 [TBRAR] = 0x004c,
339 [TDFAR] = 0x0050,
340
c0013f6f
SS		 341 [ECMR] = 0x0160,
342 [ECSR] = 0x0164,
343 [ECSIPR] = 0x0168,
344 [PIR] = 0x016c,
345 [MAHR] = 0x0170,
346 [MALR] = 0x0174,
347 [RFLR] = 0x0178,
348 [PSR] = 0x017c,
349 [TROCR] = 0x0180,
350 [CDCR] = 0x0184,
351 [LCCR] = 0x0188,
352 [CNDCR] = 0x018c,
353 [CEFCR] = 0x0194,
354 [FRECR] = 0x0198,
355 [TSFRCR] = 0x019c,
356 [TLFRCR] = 0x01a0,
357 [RFCR] = 0x01a4,
358 [MAFCR] = 0x01a8,
359 [IPGR] = 0x01b4,
360 [APR] = 0x01b8,
361 [MPR] = 0x01bc,
362 [TPAUSER] = 0x01c4,
363 [BCFR] = 0x01cc,
364
365 [ARSTR] = 0x0000,
366 [TSU_CTRST] = 0x0004,
367 [TSU_FWEN0] = 0x0010,
368 [TSU_FWEN1] = 0x0014,
369 [TSU_FCM] = 0x0018,
370 [TSU_BSYSL0] = 0x0020,
371 [TSU_BSYSL1] = 0x0024,
372 [TSU_PRISL0] = 0x0028,
373 [TSU_PRISL1] = 0x002c,
374 [TSU_FWSL0] = 0x0030,
375 [TSU_FWSL1] = 0x0034,
376 [TSU_FWSLC] = 0x0038,
377 [TSU_QTAGM0] = 0x0040,
378 [TSU_QTAGM1] = 0x0044,
379 [TSU_ADQT0] = 0x0048,
380 [TSU_ADQT1] = 0x004c,
381 [TSU_FWSR] = 0x0050,
382 [TSU_FWINMK] = 0x0054,
383 [TSU_ADSBSY] = 0x0060,
384 [TSU_TEN] = 0x0064,
385 [TSU_POST1] = 0x0070,
386 [TSU_POST2] = 0x0074,
387 [TSU_POST3] = 0x0078,
388 [TSU_POST4] = 0x007c,
389
390 [TXNLCR0] = 0x0080,
391 [TXALCR0] = 0x0084,
392 [RXNLCR0] = 0x0088,
393 [RXALCR0] = 0x008c,
394 [FWNLCR0] = 0x0090,
395 [FWALCR0] = 0x0094,
396 [TXNLCR1] = 0x00a0,
397 [TXALCR1] = 0x00a0,
398 [RXNLCR1] = 0x00a8,
399 [RXALCR1] = 0x00ac,
400 [FWNLCR1] = 0x00b0,
401 [FWALCR1] = 0x00b4,
402
403 [TSU_ADRH0] = 0x0100,
c0013f6f
SS		 404};
405
740c7f31
BH		 406static void sh_eth_rcv_snd_disable(struct net_device *ndev);
407static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev);
408
2274d375
SS		 409static void sh_eth_write(struct net_device *ndev, u32 data, int enum_index)
410{
411 struct sh_eth_private *mdp = netdev_priv(ndev);
412 u16 offset = mdp->reg_offset[enum_index];
413
414 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
415 return;
416
417 iowrite32(data, mdp->addr + offset);
418}
419
420static u32 sh_eth_read(struct net_device *ndev, int enum_index)
421{
422 struct sh_eth_private *mdp = netdev_priv(ndev);
423 u16 offset = mdp->reg_offset[enum_index];
424
425 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
426 return ~0U;
427
428 return ioread32(mdp->addr + offset);
429}
430
b2b14d2f
SS		 431static void sh_eth_modify(struct net_device *ndev, int enum_index, u32 clear,
432 u32 set)
433{
434 sh_eth_write(ndev, (sh_eth_read(ndev, enum_index) & ~clear) | set,
435 enum_index);
436}
437
504c8ca5 438static bool sh_eth_is_gether(struct sh_eth_private *mdp)
dabdde9e 439{
504c8ca5 440 return mdp->reg_offset == sh_eth_offset_gigabit;
dabdde9e
NI		 441}
442
db893473
SH		 443static bool sh_eth_is_rz_fast_ether(struct sh_eth_private *mdp)
444{
445 return mdp->reg_offset == sh_eth_offset_fast_rz;
446}
447
8e994402 448static void sh_eth_select_mii(struct net_device *ndev)
5e7a76be 449{
5e7a76be 450 struct sh_eth_private *mdp = netdev_priv(ndev);
4fa8c3cc 451 u32 value;
5e7a76be
NI		 452
453 switch (mdp->phy_interface) {
454 case PHY_INTERFACE_MODE_GMII:
455 value = 0x2;
456 break;
457 case PHY_INTERFACE_MODE_MII:
458 value = 0x1;
459 break;
460 case PHY_INTERFACE_MODE_RMII:
461 value = 0x0;
462 break;
463 default:
f75f14ec
SS		 464 netdev_warn(ndev,
465 "PHY interface mode was not setup. Set to MII.\n");
5e7a76be
NI		 466 value = 0x1;
467 break;
468 }
469
470 sh_eth_write(ndev, value, RMII_MII);
471}
5e7a76be 472
8e994402 473static void sh_eth_set_duplex(struct net_device *ndev)
65ac8851
YS		 474{
475 struct sh_eth_private *mdp = netdev_priv(ndev);
65ac8851 476
b2b14d2f 477 sh_eth_modify(ndev, ECMR, ECMR_DM, mdp->duplex ? ECMR_DM : 0);
65ac8851
YS		 478}
479
99f84be6
GU		 480static void sh_eth_chip_reset(struct net_device *ndev)
481{
482 struct sh_eth_private *mdp = netdev_priv(ndev);
483
484 /* reset device */
485 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
486 mdelay(1);
487}
488
a0f48be3
GU		 489static void sh_eth_set_rate_gether(struct net_device *ndev)
490{
491 struct sh_eth_private *mdp = netdev_priv(ndev);
492
493 switch (mdp->speed) {
494 case 10: /* 10BASE */
495 sh_eth_write(ndev, GECMR_10, GECMR);
496 break;
497 case 100:/* 100BASE */
498 sh_eth_write(ndev, GECMR_100, GECMR);
499 break;
500 case 1000: /* 1000BASE */
501 sh_eth_write(ndev, GECMR_1000, GECMR);
502 break;
a0f48be3
GU		 503 }
504}
505
99f84be6
GU		 506#ifdef CONFIG_OF
507/* R7S72100 */
508static struct sh_eth_cpu_data r7s72100_data = {
509 .chip_reset = sh_eth_chip_reset,
510 .set_duplex = sh_eth_set_duplex,
511
512 .register_type = SH_ETH_REG_FAST_RZ,
513
514 .ecsr_value = ECSR_ICD,
515 .ecsipr_value = ECSIPR_ICDIP,
516 .eesipr_value = 0xff7f009f,
517
518 .tx_check = EESR_TC1 | EESR_FTC,
519 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
520 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
521 EESR_TDE | EESR_ECI,
522 .fdr_value = 0x0000070f,
523
524 .no_psr = 1,
525 .apr = 1,
526 .mpr = 1,
527 .tpauser = 1,
528 .hw_swap = 1,
529 .rpadir = 1,
530 .rpadir_value = 2 << 16,
531 .no_trimd = 1,
532 .no_ade = 1,
533 .hw_crc = 1,
534 .tsu = 1,
535 .shift_rd0 = 1,
536};
a0f48be3
GU		 537
538static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
539{
540 struct sh_eth_private *mdp = netdev_priv(ndev);
541
542 /* reset device */
543 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
544 mdelay(1);
545
546 sh_eth_select_mii(ndev);
547}
548
549/* R8A7740 */
550static struct sh_eth_cpu_data r8a7740_data = {
551 .chip_reset = sh_eth_chip_reset_r8a7740,
552 .set_duplex = sh_eth_set_duplex,
553 .set_rate = sh_eth_set_rate_gether,
554
555 .register_type = SH_ETH_REG_GIGABIT,
556
557 .ecsr_value = ECSR_ICD | ECSR_MPD,
558 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
559 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
560
561 .tx_check = EESR_TC1 | EESR_FTC,
562 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
563 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
564 EESR_TDE | EESR_ECI,
565 .fdr_value = 0x0000070f,
566
567 .apr = 1,
568 .mpr = 1,
569 .tpauser = 1,
570 .bculr = 1,
571 .hw_swap = 1,
572 .rpadir = 1,
573 .rpadir_value = 2 << 16,
574 .no_trimd = 1,
575 .no_ade = 1,
576 .tsu = 1,
577 .select_mii = 1,
578 .shift_rd0 = 1,
579};
99f84be6 580
04b0ed2a 581/* There is CPU dependent code */
589ebdef 582static void sh_eth_set_rate_r8a777x(struct net_device *ndev)
65ac8851
YS		 583{
584 struct sh_eth_private *mdp = netdev_priv(ndev);
d0418bb7 585
a3f109bd
SS		 586 switch (mdp->speed) {
587 case 10: /* 10BASE */
b2b14d2f 588 sh_eth_modify(ndev, ECMR, ECMR_ELB, 0);
a3f109bd
SS		 589 break;
590 case 100:/* 100BASE */
b2b14d2f 591 sh_eth_modify(ndev, ECMR, ECMR_ELB, ECMR_ELB);
a3f109bd 592 break;
a3f109bd
SS		 593 }
594}
595
674853b2 596/* R8A7778/9 */
589ebdef 597static struct sh_eth_cpu_data r8a777x_data = {
a3f109bd 598 .set_duplex = sh_eth_set_duplex,
589ebdef 599 .set_rate = sh_eth_set_rate_r8a777x,
a3f109bd 600
a3153d8c
SS		 601 .register_type = SH_ETH_REG_FAST_RCAR,
602
a3f109bd
SS		 603 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
604 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
605 .eesipr_value = 0x01ff009f,
606
607 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
ca8c3585
SS		 608 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
609 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
610 EESR_ECI,
d407bc02 611 .fdr_value = 0x00000f0f,
a3f109bd
SS		 612
613 .apr = 1,
614 .mpr = 1,
615 .tpauser = 1,
616 .hw_swap = 1,
617};
a3f109bd 618
94a12b15
SS		 619/* R8A7790/1 */
620static struct sh_eth_cpu_data r8a779x_data = {
e18dbf7e
SH		 621 .set_duplex = sh_eth_set_duplex,
622 .set_rate = sh_eth_set_rate_r8a777x,
623
a3153d8c
SS		 624 .register_type = SH_ETH_REG_FAST_RCAR,
625
e18dbf7e
SH		 626 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
627 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
628 .eesipr_value = 0x01ff009f,
629
630 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
ba361cb3
LP		 631 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
632 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
633 EESR_ECI,
d407bc02 634 .fdr_value = 0x00000f0f,
e18dbf7e 635
01fbd3f5
GU		 636 .trscer_err_mask = DESC_I_RINT8,
637
e18dbf7e
SH		 638 .apr = 1,
639 .mpr = 1,
640 .tpauser = 1,
641 .hw_swap = 1,
642 .rmiimode = 1,
643};
c74a2248 644#endif /* CONFIG_OF */
e18dbf7e 645
9c3beaab 646static void sh_eth_set_rate_sh7724(struct net_device *ndev)
a3f109bd
SS		 647{
648 struct sh_eth_private *mdp = netdev_priv(ndev);
65ac8851
YS		 649
650 switch (mdp->speed) {
651 case 10: /* 10BASE */
b2b14d2f 652 sh_eth_modify(ndev, ECMR, ECMR_RTM, 0);
65ac8851
YS		 653 break;
654 case 100:/* 100BASE */
b2b14d2f 655 sh_eth_modify(ndev, ECMR, ECMR_RTM, ECMR_RTM);
65ac8851 656 break;
65ac8851
YS		 657 }
658}
659
660/* SH7724 */
9c3beaab 661static struct sh_eth_cpu_data sh7724_data = {
65ac8851 662 .set_duplex = sh_eth_set_duplex,
9c3beaab 663 .set_rate = sh_eth_set_rate_sh7724,
65ac8851 664
a3153d8c
SS		 665 .register_type = SH_ETH_REG_FAST_SH4,
666
65ac8851
YS		 667 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
668 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
a80c3de7 669 .eesipr_value = 0x01ff009f,
65ac8851
YS		 670
671 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
ca8c3585
SS		 672 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
673 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
674 EESR_ECI,
65ac8851
YS		 675
676 .apr = 1,
677 .mpr = 1,
678 .tpauser = 1,
679 .hw_swap = 1,
503914cf
MD		 680 .rpadir = 1,
681 .rpadir_value = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
65ac8851 682};
5cee1d37 683
24549e2a 684static void sh_eth_set_rate_sh7757(struct net_device *ndev)
f29a3d04
YS		 685{
686 struct sh_eth_private *mdp = netdev_priv(ndev);
f29a3d04
YS		 687
688 switch (mdp->speed) {
689 case 10: /* 10BASE */
4a55530f 690 sh_eth_write(ndev, 0, RTRATE);
f29a3d04
YS		 691 break;
692 case 100:/* 100BASE */
4a55530f 693 sh_eth_write(ndev, 1, RTRATE);
f29a3d04 694 break;
f29a3d04
YS		 695 }
696}
697
698/* SH7757 */
24549e2a
SS		 699static struct sh_eth_cpu_data sh7757_data = {
700 .set_duplex = sh_eth_set_duplex,
701 .set_rate = sh_eth_set_rate_sh7757,
f29a3d04 702
a3153d8c
SS		 703 .register_type = SH_ETH_REG_FAST_SH4,
704
f29a3d04 705 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
f29a3d04
YS		 706
707 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
ca8c3585
SS		 708 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
709 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
710 EESR_ECI,
f29a3d04 711
5b3dfd13 712 .irq_flags = IRQF_SHARED,
f29a3d04
YS		 713 .apr = 1,
714 .mpr = 1,
715 .tpauser = 1,
716 .hw_swap = 1,
717 .no_ade = 1,
2e98e797
YS		 718 .rpadir = 1,
719 .rpadir_value = 2 << 16,
6b4b4fea 720 .rtrate = 1,
f29a3d04 721};
65ac8851 722
e403d295 723#define SH_GIGA_ETH_BASE 0xfee00000UL
8fcd4961
YS		 724#define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
725#define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
726static void sh_eth_chip_reset_giga(struct net_device *ndev)
727{
728 int i;
0799c2d6 729 u32 mahr[2], malr[2];
8fcd4961
YS		 730
731 /* save MAHR and MALR */
732 for (i = 0; i < 2; i++) {
ae70644d
YS		 733 malr[i] = ioread32((void *)GIGA_MALR(i));
734 mahr[i] = ioread32((void *)GIGA_MAHR(i));
8fcd4961
YS		 735 }
736
737 /* reset device */
ae70644d 738 iowrite32(ARSTR_ARSTR, (void *)(SH_GIGA_ETH_BASE + 0x1800));
8fcd4961
YS		 739 mdelay(1);
740
741 /* restore MAHR and MALR */
742 for (i = 0; i < 2; i++) {
ae70644d
YS		 743 iowrite32(malr[i], (void *)GIGA_MALR(i));
744 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
8fcd4961
YS		 745 }
746}
747
8fcd4961
YS		 748static void sh_eth_set_rate_giga(struct net_device *ndev)
749{
750 struct sh_eth_private *mdp = netdev_priv(ndev);
751
752 switch (mdp->speed) {
753 case 10: /* 10BASE */
754 sh_eth_write(ndev, 0x00000000, GECMR);
755 break;
756 case 100:/* 100BASE */
757 sh_eth_write(ndev, 0x00000010, GECMR);
758 break;
759 case 1000: /* 1000BASE */
760 sh_eth_write(ndev, 0x00000020, GECMR);
761 break;
8fcd4961
YS		 762 }
763}
764
765/* SH7757(GETHERC) */
24549e2a 766static struct sh_eth_cpu_data sh7757_data_giga = {
8fcd4961 767 .chip_reset = sh_eth_chip_reset_giga,
04b0ed2a 768 .set_duplex = sh_eth_set_duplex,
8fcd4961
YS		 769 .set_rate = sh_eth_set_rate_giga,
770
a3153d8c
SS		 771 .register_type = SH_ETH_REG_GIGABIT,
772
8fcd4961
YS		 773 .ecsr_value = ECSR_ICD | ECSR_MPD,
774 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
775 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
776
777 .tx_check = EESR_TC1 | EESR_FTC,
ca8c3585
SS		 778 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
779 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
780 EESR_TDE | EESR_ECI,
8fcd4961 781 .fdr_value = 0x0000072f,
8fcd4961 782
5b3dfd13 783 .irq_flags = IRQF_SHARED,
8fcd4961
YS		 784 .apr = 1,
785 .mpr = 1,
786 .tpauser = 1,
787 .bculr = 1,
788 .hw_swap = 1,
789 .rpadir = 1,
790 .rpadir_value = 2 << 16,
791 .no_trimd = 1,
792 .no_ade = 1,
3acbc971 793 .tsu = 1,
8fcd4961
YS		 794};
795
f5d12767
SS		 796/* SH7734 */
797static struct sh_eth_cpu_data sh7734_data = {
380af9e3
YS		 798 .chip_reset = sh_eth_chip_reset,
799 .set_duplex = sh_eth_set_duplex,
f5d12767
SS		 800 .set_rate = sh_eth_set_rate_gether,
801
a3153d8c
SS		 802 .register_type = SH_ETH_REG_GIGABIT,
803
f5d12767
SS		 804 .ecsr_value = ECSR_ICD | ECSR_MPD,
805 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
806 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
807
808 .tx_check = EESR_TC1 | EESR_FTC,
ca8c3585
SS		 809 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
810 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
811 EESR_TDE | EESR_ECI,
f5d12767
SS		 812
813 .apr = 1,
814 .mpr = 1,
815 .tpauser = 1,
816 .bculr = 1,
817 .hw_swap = 1,
818 .no_trimd = 1,
819 .no_ade = 1,
820 .tsu = 1,
821 .hw_crc = 1,
822 .select_mii = 1,
823};
824
825/* SH7763 */
826static struct sh_eth_cpu_data sh7763_data = {
827 .chip_reset = sh_eth_chip_reset,
828 .set_duplex = sh_eth_set_duplex,
829 .set_rate = sh_eth_set_rate_gether,
380af9e3 830
a3153d8c
SS		 831 .register_type = SH_ETH_REG_GIGABIT,
832
380af9e3
YS		 833 .ecsr_value = ECSR_ICD | ECSR_MPD,
834 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
835 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
836
837 .tx_check = EESR_TC1 | EESR_FTC,
128296fc
SS		 838 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
839 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
380af9e3 840 EESR_ECI,
380af9e3
YS		 841
842 .apr = 1,
843 .mpr = 1,
844 .tpauser = 1,
845 .bculr = 1,
846 .hw_swap = 1,
380af9e3
YS		 847 .no_trimd = 1,
848 .no_ade = 1,
4986b996 849 .tsu = 1,
5b3dfd13 850 .irq_flags = IRQF_SHARED,
380af9e3
YS		 851};
852
c18a79ab 853static struct sh_eth_cpu_data sh7619_data = {
a3153d8c
SS		 854 .register_type = SH_ETH_REG_FAST_SH3_SH2,
855
380af9e3
YS		 856 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
857
858 .apr = 1,
859 .mpr = 1,
860 .tpauser = 1,
861 .hw_swap = 1,
862};
7bbe150d
SS		 863
864static struct sh_eth_cpu_data sh771x_data = {
a3153d8c
SS		 865 .register_type = SH_ETH_REG_FAST_SH3_SH2,
866
380af9e3 867 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
4986b996 868 .tsu = 1,
380af9e3 869};
380af9e3
YS		 870
871static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
872{
873 if (!cd->ecsr_value)
874 cd->ecsr_value = DEFAULT_ECSR_INIT;
875
876 if (!cd->ecsipr_value)
877 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
878
879 if (!cd->fcftr_value)
128296fc 880 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF |
380af9e3
YS		 881 DEFAULT_FIFO_F_D_RFD;
882
883 if (!cd->fdr_value)
884 cd->fdr_value = DEFAULT_FDR_INIT;
885
380af9e3
YS		 886 if (!cd->tx_check)
887 cd->tx_check = DEFAULT_TX_CHECK;
888
889 if (!cd->eesr_err_check)
890 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
b284fbe3
NI		 891
892 if (!cd->trscer_err_mask)
893 cd->trscer_err_mask = DEFAULT_TRSCER_ERR_MASK;
380af9e3
YS		 894}
895
5cee1d37
NI		 896static int sh_eth_check_reset(struct net_device *ndev)
897{
898 int ret = 0;
899 int cnt = 100;
900
901 while (cnt > 0) {
902 if (!(sh_eth_read(ndev, EDMR) & 0x3))
903 break;
904 mdelay(1);
905 cnt--;
906 }
9f8c4265 907 if (cnt <= 0) {
f75f14ec 908 netdev_err(ndev, "Device reset failed\n");
5cee1d37
NI		 909 ret = -ETIMEDOUT;
910 }
911 return ret;
380af9e3 912}
dabdde9e
NI		 913
914static int sh_eth_reset(struct net_device *ndev)
915{
916 struct sh_eth_private *mdp = netdev_priv(ndev);
917 int ret = 0;
918
db893473 919 if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp)) {
dabdde9e 920 sh_eth_write(ndev, EDSR_ENALL, EDSR);
b2b14d2f 921 sh_eth_modify(ndev, EDMR, EDMR_SRST_GETHER, EDMR_SRST_GETHER);
dabdde9e
NI		 922
923 ret = sh_eth_check_reset(ndev);
924 if (ret)
f738a13d 925 return ret;
dabdde9e
NI		 926
927 /* Table Init */
928 sh_eth_write(ndev, 0x0, TDLAR);
929 sh_eth_write(ndev, 0x0, TDFAR);
930 sh_eth_write(ndev, 0x0, TDFXR);
931 sh_eth_write(ndev, 0x0, TDFFR);
932 sh_eth_write(ndev, 0x0, RDLAR);
933 sh_eth_write(ndev, 0x0, RDFAR);
934 sh_eth_write(ndev, 0x0, RDFXR);
935 sh_eth_write(ndev, 0x0, RDFFR);
936
937 /* Reset HW CRC register */
938 if (mdp->cd->hw_crc)
939 sh_eth_write(ndev, 0x0, CSMR);
940
941 /* Select MII mode */
942 if (mdp->cd->select_mii)
943 sh_eth_select_mii(ndev);
944 } else {
b2b14d2f 945 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, EDMR_SRST_ETHER);
dabdde9e 946 mdelay(3);
b2b14d2f 947 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, 0);
dabdde9e
NI		 948 }
949
dabdde9e
NI		 950 return ret;
951}
380af9e3 952
380af9e3
YS		 953static void sh_eth_set_receive_align(struct sk_buff *skb)
954{
4d6a949c 955 uintptr_t reserve = (uintptr_t)skb->data & (SH_ETH_RX_ALIGN - 1);
380af9e3 956
380af9e3 957 if (reserve)
4d6a949c 958 skb_reserve(skb, SH_ETH_RX_ALIGN - reserve);
380af9e3 959}
380af9e3 960
128296fc 961/* Program the hardware MAC address from dev->dev_addr. */
86a74ff2
NI		 962static void update_mac_address(struct net_device *ndev)
963{
4a55530f 964 sh_eth_write(ndev,
128296fc
SS		 965 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
966 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
4a55530f 967 sh_eth_write(ndev,
128296fc 968 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
86a74ff2
NI		 969}
970
128296fc 971/* Get MAC address from SuperH MAC address register
86a74ff2
NI		 972 *
973 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
974 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
975 * When you want use this device, you must set MAC address in bootloader.
976 *
977 */
748031f9 978static void read_mac_address(struct net_device *ndev, unsigned char *mac)
86a74ff2 979{
748031f9 980 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
d458cdf7 981 memcpy(ndev->dev_addr, mac, ETH_ALEN);
748031f9 982 } else {
37742f02
SS		 983 u32 mahr = sh_eth_read(ndev, MAHR);
984 u32 malr = sh_eth_read(ndev, MALR);
985
986 ndev->dev_addr[0] = (mahr >> 24) & 0xFF;
987 ndev->dev_addr[1] = (mahr >> 16) & 0xFF;
988 ndev->dev_addr[2] = (mahr >> 8) & 0xFF;
989 ndev->dev_addr[3] = (mahr >> 0) & 0xFF;
990 ndev->dev_addr[4] = (malr >> 8) & 0xFF;
991 ndev->dev_addr[5] = (malr >> 0) & 0xFF;
748031f9 992 }
86a74ff2
NI		 993}
994
0799c2d6 995static u32 sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
c5ed5368 996{
db893473 997 if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp))
c5ed5368
YS		 998 return EDTRR_TRNS_GETHER;
999 else
1000 return EDTRR_TRNS_ETHER;
1001}
1002
86a74ff2 1003struct bb_info {
ae70644d 1004 void (*set_gate)(void *addr);
86a74ff2 1005 struct mdiobb_ctrl ctrl;
ae70644d 1006 void *addr;
86a74ff2
NI		 1007};
1008
39b4b06b 1009static void sh_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set)
86a74ff2
NI		 1010{
1011 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
78fa3c5c 1012 u32 pir;
b3017e6a
YS		 1013
1014 if (bitbang->set_gate)
1015 bitbang->set_gate(bitbang->addr);
1016
78fa3c5c 1017 pir = ioread32(bitbang->addr);
39b4b06b 1018 if (set)
78fa3c5c 1019 pir |= mask;
86a74ff2 1020 else
78fa3c5c
SS		 1021 pir &= ~mask;
1022 iowrite32(pir, bitbang->addr);
39b4b06b
SS		 1023}
1024
1025/* Data I/O pin control */
1026static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1027{
1028 sh_mdio_ctrl(ctrl, PIR_MMD, bit);
86a74ff2
NI		 1029}
1030
1031/* Set bit data*/
1032static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
1033{
39b4b06b 1034 sh_mdio_ctrl(ctrl, PIR_MDO, bit);
86a74ff2
NI		 1035}
1036
1037/* Get bit data*/
1038static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
1039{
1040 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
b3017e6a
YS		 1041
1042 if (bitbang->set_gate)
1043 bitbang->set_gate(bitbang->addr);
1044
78fa3c5c 1045 return (ioread32(bitbang->addr) & PIR_MDI) != 0;
86a74ff2
NI		 1046}
1047
1048/* MDC pin control */
1049static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1050{
39b4b06b 1051 sh_mdio_ctrl(ctrl, PIR_MDC, bit);
86a74ff2
NI		 1052}
1053
1054/* mdio bus control struct */
1055static struct mdiobb_ops bb_ops = {
1056 .owner = THIS_MODULE,
1057 .set_mdc = sh_mdc_ctrl,
1058 .set_mdio_dir = sh_mmd_ctrl,
1059 .set_mdio_data = sh_set_mdio,
1060 .get_mdio_data = sh_get_mdio,
1061};
1062
86a74ff2
NI		 1063/* free skb and descriptor buffer */
1064static void sh_eth_ring_free(struct net_device *ndev)
1065{
1066 struct sh_eth_private *mdp = netdev_priv(ndev);
8e03a5e7 1067 int ringsize, i;
86a74ff2
NI		 1068
1069 /* Free Rx skb ringbuffer */
1070 if (mdp->rx_skbuff) {
179d80af
SS		 1071 for (i = 0; i < mdp->num_rx_ring; i++)
1072 dev_kfree_skb(mdp->rx_skbuff[i]);
86a74ff2
NI		 1073 }
1074 kfree(mdp->rx_skbuff);
91c77550 1075 mdp->rx_skbuff = NULL;
86a74ff2
NI		 1076
1077 /* Free Tx skb ringbuffer */
1078 if (mdp->tx_skbuff) {
179d80af
SS		 1079 for (i = 0; i < mdp->num_tx_ring; i++)
1080 dev_kfree_skb(mdp->tx_skbuff[i]);
86a74ff2
NI		 1081 }
1082 kfree(mdp->tx_skbuff);
91c77550 1083 mdp->tx_skbuff = NULL;
8e03a5e7
SS		 1084
1085 if (mdp->rx_ring) {
1086 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1087 dma_free_coherent(NULL, ringsize, mdp->rx_ring,
1088 mdp->rx_desc_dma);
1089 mdp->rx_ring = NULL;
1090 }
1091
1092 if (mdp->tx_ring) {
1093 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1094 dma_free_coherent(NULL, ringsize, mdp->tx_ring,
1095 mdp->tx_desc_dma);
1096 mdp->tx_ring = NULL;
1097 }
86a74ff2
NI		 1098}
1099
1100/* format skb and descriptor buffer */
1101static void sh_eth_ring_format(struct net_device *ndev)
1102{
1103 struct sh_eth_private *mdp = netdev_priv(ndev);
1104 int i;
1105 struct sk_buff *skb;
1106 struct sh_eth_rxdesc *rxdesc = NULL;
1107 struct sh_eth_txdesc *txdesc = NULL;
525b8075
YS		 1108 int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
1109 int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
cb368595 1110 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
52b9fa36 1111 dma_addr_t dma_addr;
5cbf20c7 1112 u32 buf_len;
86a74ff2 1113
128296fc
SS		 1114 mdp->cur_rx = 0;
1115 mdp->cur_tx = 0;
1116 mdp->dirty_rx = 0;
1117 mdp->dirty_tx = 0;
86a74ff2
NI		 1118
1119 memset(mdp->rx_ring, 0, rx_ringsize);
1120
1121 /* build Rx ring buffer */
525b8075 1122 for (i = 0; i < mdp->num_rx_ring; i++) {
86a74ff2
NI		 1123 /* skb */
1124 mdp->rx_skbuff[i] = NULL;
4d6a949c 1125 skb = netdev_alloc_skb(ndev, skbuff_size);
86a74ff2
NI		 1126 if (skb == NULL)
1127 break;
380af9e3
YS		 1128 sh_eth_set_receive_align(skb);
1129
ab857916 1130 /* The size of the buffer is a multiple of 32 bytes. */
5cbf20c7 1131 buf_len = ALIGN(mdp->rx_buf_sz, 32);
5cbf20c7 1132 dma_addr = dma_map_single(&ndev->dev, skb->data, buf_len,
52b9fa36
BH		 1133 DMA_FROM_DEVICE);
1134 if (dma_mapping_error(&ndev->dev, dma_addr)) {
1135 kfree_skb(skb);
1136 break;
1137 }
1138 mdp->rx_skbuff[i] = skb;
d0ba9134
SS		 1139
1140 /* RX descriptor */
1141 rxdesc = &mdp->rx_ring[i];
1142 rxdesc->len = cpu_to_le32(buf_len << 16);
7cf72477
SS		 1143 rxdesc->addr = cpu_to_le32(dma_addr);
1144 rxdesc->status = cpu_to_le32(RD_RACT | RD_RFP);
86a74ff2 1145
b0ca2a21
NI		 1146 /* Rx descriptor address set */
1147 if (i == 0) {
4a55530f 1148 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
db893473
SH		 1149 if (sh_eth_is_gether(mdp) ||
1150 sh_eth_is_rz_fast_ether(mdp))
c5ed5368 1151 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
b0ca2a21 1152 }
86a74ff2
NI		 1153 }
1154
525b8075 1155 mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
86a74ff2
NI		 1156
1157 /* Mark the last entry as wrapping the ring. */
c1b7fca6
SS		 1158 if (rxdesc)
1159 rxdesc->status |= cpu_to_le32(RD_RDLE);
86a74ff2
NI		 1160
1161 memset(mdp->tx_ring, 0, tx_ringsize);
1162
1163 /* build Tx ring buffer */
525b8075 1164 for (i = 0; i < mdp->num_tx_ring; i++) {
86a74ff2
NI		 1165 mdp->tx_skbuff[i] = NULL;
1166 txdesc = &mdp->tx_ring[i];
7cf72477
SS		 1167 txdesc->status = cpu_to_le32(TD_TFP);
1168 txdesc->len = cpu_to_le32(0);
b0ca2a21 1169 if (i == 0) {
71557a37 1170 /* Tx descriptor address set */
4a55530f 1171 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
db893473
SH		 1172 if (sh_eth_is_gether(mdp) ||
1173 sh_eth_is_rz_fast_ether(mdp))
c5ed5368 1174 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
b0ca2a21 1175 }
86a74ff2
NI		 1176 }
1177
7cf72477 1178 txdesc->status |= cpu_to_le32(TD_TDLE);
86a74ff2
NI		 1179}
1180
1181/* Get skb and descriptor buffer */
1182static int sh_eth_ring_init(struct net_device *ndev)
1183{
1184 struct sh_eth_private *mdp = netdev_priv(ndev);
91d80683 1185 int rx_ringsize, tx_ringsize;
86a74ff2 1186
128296fc 1187 /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
86a74ff2
NI		 1188 * card needs room to do 8 byte alignment, +2 so we can reserve
1189 * the first 2 bytes, and +16 gets room for the status word from the
1190 * card.
1191 */
1192 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
1193 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
503914cf
MD		 1194 if (mdp->cd->rpadir)
1195 mdp->rx_buf_sz += NET_IP_ALIGN;
86a74ff2
NI		 1196
1197 /* Allocate RX and TX skb rings */
2c94e856
SS		 1198 mdp->rx_skbuff = kcalloc(mdp->num_rx_ring, sizeof(*mdp->rx_skbuff),
1199 GFP_KERNEL);
91d80683
SS		 1200 if (!mdp->rx_skbuff)
1201 return -ENOMEM;
86a74ff2 1202
2c94e856
SS		 1203 mdp->tx_skbuff = kcalloc(mdp->num_tx_ring, sizeof(*mdp->tx_skbuff),
1204 GFP_KERNEL);
91d80683 1205 if (!mdp->tx_skbuff)
8e03a5e7 1206 goto ring_free;
86a74ff2
NI		 1207
1208 /* Allocate all Rx descriptors. */
525b8075 1209 rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
86a74ff2 1210 mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
d0320f75 1211 GFP_KERNEL);
91d80683 1212 if (!mdp->rx_ring)
8e03a5e7 1213 goto ring_free;
86a74ff2
NI		 1214
1215 mdp->dirty_rx = 0;
1216
1217 /* Allocate all Tx descriptors. */
525b8075 1218 tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
86a74ff2 1219 mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
d0320f75 1220 GFP_KERNEL);
91d80683 1221 if (!mdp->tx_ring)
8e03a5e7 1222 goto ring_free;
91d80683 1223 return 0;
86a74ff2 1224
8e03a5e7
SS		 1225ring_free:
1226 /* Free Rx and Tx skb ring buffer and DMA buffer */
86a74ff2
NI		 1227 sh_eth_ring_free(ndev);
1228
91d80683 1229 return -ENOMEM;
86a74ff2
NI		 1230}
1231
525b8075 1232static int sh_eth_dev_init(struct net_device *ndev, bool start)
86a74ff2 1233{
86a74ff2 1234 struct sh_eth_private *mdp = netdev_priv(ndev);
4fa8c3cc 1235 int ret;
86a74ff2
NI		 1236
1237 /* Soft Reset */
5cee1d37
NI		 1238 ret = sh_eth_reset(ndev);
1239 if (ret)
f738a13d 1240 return ret;
86a74ff2 1241
55754f19
SH		 1242 if (mdp->cd->rmiimode)
1243 sh_eth_write(ndev, 0x1, RMIIMODE);
1244
b0ca2a21
NI		 1245 /* Descriptor format */
1246 sh_eth_ring_format(ndev);
380af9e3 1247 if (mdp->cd->rpadir)
4a55530f 1248 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
86a74ff2
NI		 1249
1250 /* all sh_eth int mask */
4a55530f 1251 sh_eth_write(ndev, 0, EESIPR);
86a74ff2 1252
10b9194f 1253#if defined(__LITTLE_ENDIAN)
380af9e3 1254 if (mdp->cd->hw_swap)
4a55530f 1255 sh_eth_write(ndev, EDMR_EL, EDMR);
380af9e3 1256 else
b0ca2a21 1257#endif
4a55530f 1258 sh_eth_write(ndev, 0, EDMR);
86a74ff2 1259
b0ca2a21 1260 /* FIFO size set */
4a55530f
YS		 1261 sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
1262 sh_eth_write(ndev, 0, TFTR);
86a74ff2 1263
530aa2d0
BD		 1264 /* Frame recv control (enable multiple-packets per rx irq) */
1265 sh_eth_write(ndev, RMCR_RNC, RMCR);
86a74ff2 1266
b284fbe3 1267 sh_eth_write(ndev, mdp->cd->trscer_err_mask, TRSCER);
86a74ff2 1268
380af9e3 1269 if (mdp->cd->bculr)
4a55530f 1270 sh_eth_write(ndev, 0x800, BCULR); /* Burst sycle set */
b0ca2a21 1271
4a55530f 1272 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
86a74ff2 1273
380af9e3 1274 if (!mdp->cd->no_trimd)
4a55530f 1275 sh_eth_write(ndev, 0, TRIMD);
86a74ff2 1276
b0ca2a21 1277 /* Recv frame limit set register */
fdb37a7f
YS		 1278 sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1279 RFLR);
86a74ff2 1280
b2b14d2f 1281 sh_eth_modify(ndev, EESR, 0, 0);
283e38db
BH		 1282 if (start) {
1283 mdp->irq_enabled = true;
525b8075 1284 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
283e38db 1285 }
86a74ff2
NI		 1286
1287 /* PAUSE Prohibition */
bffa731f
SS		 1288 sh_eth_write(ndev, ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) |
1289 ECMR_TE | ECMR_RE, ECMR);
b0ca2a21 1290
380af9e3
YS		 1291 if (mdp->cd->set_rate)
1292 mdp->cd->set_rate(ndev);
1293
b0ca2a21 1294 /* E-MAC Status Register clear */
4a55530f 1295 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
b0ca2a21
NI		 1296
1297 /* E-MAC Interrupt Enable register */
525b8075
YS		 1298 if (start)
1299 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
86a74ff2
NI		 1300
1301 /* Set MAC address */
1302 update_mac_address(ndev);
1303
1304 /* mask reset */
380af9e3 1305 if (mdp->cd->apr)
4a55530f 1306 sh_eth_write(ndev, APR_AP, APR);
380af9e3 1307 if (mdp->cd->mpr)
4a55530f 1308 sh_eth_write(ndev, MPR_MP, MPR);
380af9e3 1309 if (mdp->cd->tpauser)
4a55530f 1310 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
b0ca2a21 1311
525b8075
YS		 1312 if (start) {
1313 /* Setting the Rx mode will start the Rx process. */
1314 sh_eth_write(ndev, EDRRR_R, EDRRR);
86a74ff2 1315
525b8075
YS		 1316 netif_start_queue(ndev);
1317 }
86a74ff2
NI		 1318
1319 return ret;
1320}
1321
740c7f31
BH		 1322static void sh_eth_dev_exit(struct net_device *ndev)
1323{
1324 struct sh_eth_private *mdp = netdev_priv(ndev);
1325 int i;
1326
1327 /* Deactivate all TX descriptors, so DMA should stop at next
1328 * packet boundary if it's currently running
1329 */
1330 for (i = 0; i < mdp->num_tx_ring; i++)
7cf72477 1331 mdp->tx_ring[i].status &= ~cpu_to_le32(TD_TACT);
740c7f31
BH		 1332
1333 /* Disable TX FIFO egress to MAC */
1334 sh_eth_rcv_snd_disable(ndev);
1335
1336 /* Stop RX DMA at next packet boundary */
1337 sh_eth_write(ndev, 0, EDRRR);
1338
1339 /* Aside from TX DMA, we can't tell when the hardware is
1340 * really stopped, so we need to reset to make sure.
1341 * Before doing that, wait for long enough to *probably*
1342 * finish transmitting the last packet and poll stats.
1343 */
1344 msleep(2); /* max frame time at 10 Mbps < 1250 us */
1345 sh_eth_get_stats(ndev);
1346 sh_eth_reset(ndev);
a14c7d15
GU		 1347
1348 /* Set MAC address again */
1349 update_mac_address(ndev);
740c7f31
BH		 1350}
1351
86a74ff2
NI		 1352/* free Tx skb function */
1353static int sh_eth_txfree(struct net_device *ndev)
1354{
1355 struct sh_eth_private *mdp = netdev_priv(ndev);
1356 struct sh_eth_txdesc *txdesc;
128296fc 1357 int free_num = 0;
4fa8c3cc 1358 int entry;
86a74ff2
NI		 1359
1360 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
525b8075 1361 entry = mdp->dirty_tx % mdp->num_tx_ring;
86a74ff2 1362 txdesc = &mdp->tx_ring[entry];
7cf72477 1363 if (txdesc->status & cpu_to_le32(TD_TACT))
86a74ff2 1364 break;
7d7355f5 1365 /* TACT bit must be checked before all the following reads */
f32bfb9a 1366 dma_rmb();
e5fd13f4
BH		 1367 netif_info(mdp, tx_done, ndev,
1368 "tx entry %d status 0x%08x\n",
7cf72477 1369 entry, le32_to_cpu(txdesc->status));
86a74ff2
NI		 1370 /* Free the original skb. */
1371 if (mdp->tx_skbuff[entry]) {
7cf72477
SS		 1372 dma_unmap_single(&ndev->dev, le32_to_cpu(txdesc->addr),
1373 le32_to_cpu(txdesc->len) >> 16,
5cbf20c7 1374 DMA_TO_DEVICE);
86a74ff2
NI		 1375 dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1376 mdp->tx_skbuff[entry] = NULL;
128296fc 1377 free_num++;
86a74ff2 1378 }
7cf72477 1379 txdesc->status = cpu_to_le32(TD_TFP);
525b8075 1380 if (entry >= mdp->num_tx_ring - 1)
7cf72477 1381 txdesc->status |= cpu_to_le32(TD_TDLE);
86a74ff2 1382
bb7d92e3 1383 ndev->stats.tx_packets++;
7cf72477 1384 ndev->stats.tx_bytes += le32_to_cpu(txdesc->len) >> 16;
86a74ff2 1385 }
128296fc 1386 return free_num;
86a74ff2
NI		 1387}
1388
1389/* Packet receive function */
3719109d 1390static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
86a74ff2
NI		 1391{
1392 struct sh_eth_private *mdp = netdev_priv(ndev);
1393 struct sh_eth_rxdesc *rxdesc;
1394
525b8075
YS		 1395 int entry = mdp->cur_rx % mdp->num_rx_ring;
1396 int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
319cd520 1397 int limit;
86a74ff2 1398 struct sk_buff *skb;
380af9e3 1399 u32 desc_status;
cb368595 1400 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
52b9fa36 1401 dma_addr_t dma_addr;
4fa8c3cc 1402 u16 pkt_len;
5cbf20c7 1403 u32 buf_len;
86a74ff2 1404
319cd520
MK		 1405 boguscnt = min(boguscnt, *quota);
1406 limit = boguscnt;
86a74ff2 1407 rxdesc = &mdp->rx_ring[entry];
7cf72477 1408 while (!(rxdesc->status & cpu_to_le32(RD_RACT))) {
7d7355f5 1409 /* RACT bit must be checked before all the following reads */
f32bfb9a 1410 dma_rmb();
7cf72477
SS		 1411 desc_status = le32_to_cpu(rxdesc->status);
1412 pkt_len = le32_to_cpu(rxdesc->len) & RD_RFL;
86a74ff2
NI		 1413
1414 if (--boguscnt < 0)
1415 break;
1416
e5fd13f4
BH		 1417 netif_info(mdp, rx_status, ndev,
1418 "rx entry %d status 0x%08x len %d\n",
1419 entry, desc_status, pkt_len);
1420
86a74ff2 1421 if (!(desc_status & RDFEND))
bb7d92e3 1422 ndev->stats.rx_length_errors++;
86a74ff2 1423
128296fc 1424 /* In case of almost all GETHER/ETHERs, the Receive Frame State
dd019897 1425 * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
9b4a6364
BH		 1426 * bit 0. However, in case of the R8A7740 and R7S72100
1427 * the RFS bits are from bit 25 to bit 16. So, the
db893473 1428 * driver needs right shifting by 16.
dd019897 1429 */
ac8025a6
SS		 1430 if (mdp->cd->shift_rd0)
1431 desc_status >>= 16;
dd019897 1432
248be83d 1433 skb = mdp->rx_skbuff[entry];
86a74ff2
NI		 1434 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1435 RD_RFS5 | RD_RFS6 | RD_RFS10)) {
bb7d92e3 1436 ndev->stats.rx_errors++;
86a74ff2 1437 if (desc_status & RD_RFS1)
bb7d92e3 1438 ndev->stats.rx_crc_errors++;
86a74ff2 1439 if (desc_status & RD_RFS2)
bb7d92e3 1440 ndev->stats.rx_frame_errors++;
86a74ff2 1441 if (desc_status & RD_RFS3)
bb7d92e3 1442 ndev->stats.rx_length_errors++;
86a74ff2 1443 if (desc_status & RD_RFS4)
bb7d92e3 1444 ndev->stats.rx_length_errors++;
86a74ff2 1445 if (desc_status & RD_RFS6)
bb7d92e3 1446 ndev->stats.rx_missed_errors++;
86a74ff2 1447 if (desc_status & RD_RFS10)
bb7d92e3 1448 ndev->stats.rx_over_errors++;
248be83d 1449 } else if (skb) {
7cf72477 1450 dma_addr = le32_to_cpu(rxdesc->addr);
380af9e3
YS		 1451 if (!mdp->cd->hw_swap)
1452 sh_eth_soft_swap(
1299653a 1453 phys_to_virt(ALIGN(dma_addr, 4)),
380af9e3 1454 pkt_len + 2);
86a74ff2 1455 mdp->rx_skbuff[entry] = NULL;
503914cf
MD		 1456 if (mdp->cd->rpadir)
1457 skb_reserve(skb, NET_IP_ALIGN);
1299653a 1458 dma_unmap_single(&ndev->dev, dma_addr,
ab857916 1459 ALIGN(mdp->rx_buf_sz, 32),
52b9fa36 1460 DMA_FROM_DEVICE);
86a74ff2
NI		 1461 skb_put(skb, pkt_len);
1462 skb->protocol = eth_type_trans(skb, ndev);
a8e9fd0f 1463 netif_receive_skb(skb);
bb7d92e3
ED		 1464 ndev->stats.rx_packets++;
1465 ndev->stats.rx_bytes += pkt_len;
25b77ad7
BH		 1466 if (desc_status & RD_RFS8)
1467 ndev->stats.multicast++;
86a74ff2 1468 }
525b8075 1469 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
862df497 1470 rxdesc = &mdp->rx_ring[entry];
86a74ff2
NI		 1471 }
1472
1473 /* Refill the Rx ring buffers. */
1474 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
525b8075 1475 entry = mdp->dirty_rx % mdp->num_rx_ring;
86a74ff2 1476 rxdesc = &mdp->rx_ring[entry];
ab857916 1477 /* The size of the buffer is 32 byte boundary. */
5cbf20c7 1478 buf_len = ALIGN(mdp->rx_buf_sz, 32);
7cf72477 1479 rxdesc->len = cpu_to_le32(buf_len << 16);
b0ca2a21 1480
86a74ff2 1481 if (mdp->rx_skbuff[entry] == NULL) {
4d6a949c 1482 skb = netdev_alloc_skb(ndev, skbuff_size);
86a74ff2
NI		 1483 if (skb == NULL)
1484 break; /* Better luck next round. */
380af9e3 1485 sh_eth_set_receive_align(skb);
52b9fa36 1486 dma_addr = dma_map_single(&ndev->dev, skb->data,
5cbf20c7 1487 buf_len, DMA_FROM_DEVICE);
52b9fa36
BH		 1488 if (dma_mapping_error(&ndev->dev, dma_addr)) {
1489 kfree_skb(skb);
1490 break;
1491 }
1492 mdp->rx_skbuff[entry] = skb;
380af9e3 1493
bc8acf2c 1494 skb_checksum_none_assert(skb);
7cf72477 1495 rxdesc->addr = cpu_to_le32(dma_addr);
86a74ff2 1496 }
f32bfb9a 1497 dma_wmb(); /* RACT bit must be set after all the above writes */
525b8075 1498 if (entry >= mdp->num_rx_ring - 1)
86a74ff2 1499 rxdesc->status |=
7cf72477 1500 cpu_to_le32(RD_RACT | RD_RFP | RD_RDLE);
86a74ff2 1501 else
7cf72477 1502 rxdesc->status |= cpu_to_le32(RD_RACT | RD_RFP);
86a74ff2
NI		 1503 }
1504
1505 /* Restart Rx engine if stopped. */
1506 /* If we don't need to check status, don't. -KDU */
79fba9f5 1507 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
a18e08bd 1508 /* fix the values for the next receiving if RDE is set */
3365711d
BH		 1509 if (intr_status & EESR_RDE &&
1510 mdp->reg_offset[RDFAR] != SH_ETH_OFFSET_INVALID) {
128296fc
SS		 1511 u32 count = (sh_eth_read(ndev, RDFAR) -
1512 sh_eth_read(ndev, RDLAR)) >> 4;
1513
1514 mdp->cur_rx = count;
1515 mdp->dirty_rx = count;
1516 }
4a55530f 1517 sh_eth_write(ndev, EDRRR_R, EDRRR);
79fba9f5 1518 }
86a74ff2 1519
319cd520
MK		 1520 *quota -= limit - boguscnt - 1;
1521
4f809cea 1522 return *quota <= 0;
86a74ff2
NI		 1523}
1524
4a55530f 1525static void sh_eth_rcv_snd_disable(struct net_device *ndev)
dc19e4e5
NI		 1526{
1527 /* disable tx and rx */
b2b14d2f 1528 sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0);
dc19e4e5
NI		 1529}
1530
4a55530f 1531static void sh_eth_rcv_snd_enable(struct net_device *ndev)
dc19e4e5
NI		 1532{
1533 /* enable tx and rx */
b2b14d2f 1534 sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE);
dc19e4e5
NI		 1535}
1536
86a74ff2 1537/* error control function */
0799c2d6 1538static void sh_eth_error(struct net_device *ndev, u32 intr_status)
86a74ff2
NI		 1539{
1540 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2 1541 u32 felic_stat;
380af9e3
YS		 1542 u32 link_stat;
1543 u32 mask;
86a74ff2
NI		 1544
1545 if (intr_status & EESR_ECI) {
4a55530f
YS		 1546 felic_stat = sh_eth_read(ndev, ECSR);
1547 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */
86a74ff2 1548 if (felic_stat & ECSR_ICD)
bb7d92e3 1549 ndev->stats.tx_carrier_errors++;
86a74ff2
NI		 1550 if (felic_stat & ECSR_LCHNG) {
1551 /* Link Changed */
4923576b 1552 if (mdp->cd->no_psr || mdp->no_ether_link) {
1e1b812b 1553 goto ignore_link;
380af9e3 1554 } else {
4a55530f 1555 link_stat = (sh_eth_read(ndev, PSR));
4923576b
YS		 1556 if (mdp->ether_link_active_low)
1557 link_stat = ~link_stat;
380af9e3 1558 }
128296fc 1559 if (!(link_stat & PHY_ST_LINK)) {
4a55530f 1560 sh_eth_rcv_snd_disable(ndev);
128296fc 1561 } else {
86a74ff2 1562 /* Link Up */
b2b14d2f 1563 sh_eth_modify(ndev, EESIPR, DMAC_M_ECI, 0);
128296fc 1564 /* clear int */
b2b14d2f
SS		 1565 sh_eth_modify(ndev, ECSR, 0, 0);
1566 sh_eth_modify(ndev, EESIPR, DMAC_M_ECI,
1567 DMAC_M_ECI);
86a74ff2 1568 /* enable tx and rx */
4a55530f 1569 sh_eth_rcv_snd_enable(ndev);
86a74ff2
NI		 1570 }
1571 }
1572 }
1573
1e1b812b 1574ignore_link:
86a74ff2 1575 if (intr_status & EESR_TWB) {
4eb313a7
SS		 1576 /* Unused write back interrupt */
1577 if (intr_status & EESR_TABT) { /* Transmit Abort int */
bb7d92e3 1578 ndev->stats.tx_aborted_errors++;
8d5009f6 1579 netif_err(mdp, tx_err, ndev, "Transmit Abort\n");
4eb313a7 1580 }
86a74ff2
NI		 1581 }
1582
1583 if (intr_status & EESR_RABT) {
1584 /* Receive Abort int */
1585 if (intr_status & EESR_RFRMER) {
1586 /* Receive Frame Overflow int */
bb7d92e3 1587 ndev->stats.rx_frame_errors++;
86a74ff2
NI		 1588 }
1589 }
380af9e3 1590
dc19e4e5
NI		 1591 if (intr_status & EESR_TDE) {
1592 /* Transmit Descriptor Empty int */
bb7d92e3 1593 ndev->stats.tx_fifo_errors++;
8d5009f6 1594 netif_err(mdp, tx_err, ndev, "Transmit Descriptor Empty\n");
dc19e4e5
NI		 1595 }
1596
1597 if (intr_status & EESR_TFE) {
1598 /* FIFO under flow */
bb7d92e3 1599 ndev->stats.tx_fifo_errors++;
8d5009f6 1600 netif_err(mdp, tx_err, ndev, "Transmit FIFO Under flow\n");
86a74ff2
NI		 1601 }
1602
1603 if (intr_status & EESR_RDE) {
1604 /* Receive Descriptor Empty int */
bb7d92e3 1605 ndev->stats.rx_over_errors++;
86a74ff2 1606 }
dc19e4e5 1607
86a74ff2
NI		 1608 if (intr_status & EESR_RFE) {
1609 /* Receive FIFO Overflow int */
bb7d92e3 1610 ndev->stats.rx_fifo_errors++;
dc19e4e5
NI		 1611 }
1612
1613 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1614 /* Address Error */
bb7d92e3 1615 ndev->stats.tx_fifo_errors++;
8d5009f6 1616 netif_err(mdp, tx_err, ndev, "Address Error\n");
86a74ff2 1617 }
380af9e3
YS		 1618
1619 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1620 if (mdp->cd->no_ade)
1621 mask &= ~EESR_ADE;
1622 if (intr_status & mask) {
86a74ff2 1623 /* Tx error */
4a55530f 1624 u32 edtrr = sh_eth_read(ndev, EDTRR);
090d560f 1625
86a74ff2 1626 /* dmesg */
da246855
SS		 1627 netdev_err(ndev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1628 intr_status, mdp->cur_tx, mdp->dirty_tx,
1629 (u32)ndev->state, edtrr);
86a74ff2
NI		 1630 /* dirty buffer free */
1631 sh_eth_txfree(ndev);
1632
1633 /* SH7712 BUG */
c5ed5368 1634 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
86a74ff2 1635 /* tx dma start */
c5ed5368 1636 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
86a74ff2
NI		 1637 }
1638 /* wakeup */
1639 netif_wake_queue(ndev);
1640 }
1641}
1642
1643static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1644{
1645 struct net_device *ndev = netdev;
1646 struct sh_eth_private *mdp = netdev_priv(ndev);
380af9e3 1647 struct sh_eth_cpu_data *cd = mdp->cd;
0e0fde3c 1648 irqreturn_t ret = IRQ_NONE;
0799c2d6 1649 u32 intr_status, intr_enable;
86a74ff2 1650
86a74ff2
NI		 1651 spin_lock(&mdp->lock);
1652
3893b273 1653 /* Get interrupt status */
4a55530f 1654 intr_status = sh_eth_read(ndev, EESR);
3893b273
SS		 1655 /* Mask it with the interrupt mask, forcing ECI interrupt to be always
1656 * enabled since it's the one that comes thru regardless of the mask,
1657 * and we need to fully handle it in sh_eth_error() in order to quench
1658 * it as it doesn't get cleared by just writing 1 to the ECI bit...
1659 */
3719109d
SS		 1660 intr_enable = sh_eth_read(ndev, EESIPR);
1661 intr_status &= intr_enable | DMAC_M_ECI;
1662 if (intr_status & (EESR_RX_CHECK | cd->tx_check | cd->eesr_err_check))
0e0fde3c 1663 ret = IRQ_HANDLED;
3719109d 1664 else
283e38db
BH		 1665 goto out;
1666
1667 if (!likely(mdp->irq_enabled)) {
1668 sh_eth_write(ndev, 0, EESIPR);
1669 goto out;
1670 }
86a74ff2 1671
3719109d
SS		 1672 if (intr_status & EESR_RX_CHECK) {
1673 if (napi_schedule_prep(&mdp->napi)) {
1674 /* Mask Rx interrupts */
1675 sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK,
1676 EESIPR);
1677 __napi_schedule(&mdp->napi);
1678 } else {
da246855 1679 netdev_warn(ndev,
0799c2d6 1680 "ignoring interrupt, status 0x%08x, mask 0x%08x.\n",
da246855 1681 intr_status, intr_enable);
3719109d
SS		 1682 }
1683 }
86a74ff2 1684
b0ca2a21 1685 /* Tx Check */
380af9e3 1686 if (intr_status & cd->tx_check) {
3719109d
SS		 1687 /* Clear Tx interrupts */
1688 sh_eth_write(ndev, intr_status & cd->tx_check, EESR);
1689
86a74ff2
NI		 1690 sh_eth_txfree(ndev);
1691 netif_wake_queue(ndev);
1692 }
1693
3719109d
SS		 1694 if (intr_status & cd->eesr_err_check) {
1695 /* Clear error interrupts */
1696 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR);
1697
86a74ff2 1698 sh_eth_error(ndev, intr_status);
3719109d 1699 }
86a74ff2 1700
283e38db 1701out:
86a74ff2
NI		 1702 spin_unlock(&mdp->lock);
1703
0e0fde3c 1704 return ret;
86a74ff2
NI		 1705}
1706
3719109d
SS		 1707static int sh_eth_poll(struct napi_struct *napi, int budget)
1708{
1709 struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private,
1710 napi);
1711 struct net_device *ndev = napi->dev;
1712 int quota = budget;
0799c2d6 1713 u32 intr_status;
3719109d
SS		 1714
1715 for (;;) {
1716 intr_status = sh_eth_read(ndev, EESR);
1717 if (!(intr_status & EESR_RX_CHECK))
1718 break;
1719 /* Clear Rx interrupts */
1720 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR);
1721
1722 if (sh_eth_rx(ndev, intr_status, &quota))
1723 goto out;
1724 }
1725
1726 napi_complete(napi);
1727
1728 /* Reenable Rx interrupts */
283e38db
BH		 1729 if (mdp->irq_enabled)
1730 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
3719109d
SS		 1731out:
1732 return budget - quota;
1733}
1734
86a74ff2
NI		 1735/* PHY state control function */
1736static void sh_eth_adjust_link(struct net_device *ndev)
1737{
1738 struct sh_eth_private *mdp = netdev_priv(ndev);
1739 struct phy_device *phydev = mdp->phydev;
86a74ff2
NI		 1740 int new_state = 0;
1741
3340d2aa 1742 if (phydev->link) {
86a74ff2
NI		 1743 if (phydev->duplex != mdp->duplex) {
1744 new_state = 1;
1745 mdp->duplex = phydev->duplex;
380af9e3
YS		 1746 if (mdp->cd->set_duplex)
1747 mdp->cd->set_duplex(ndev);
86a74ff2
NI		 1748 }
1749
1750 if (phydev->speed != mdp->speed) {
1751 new_state = 1;
1752 mdp->speed = phydev->speed;
380af9e3
YS		 1753 if (mdp->cd->set_rate)
1754 mdp->cd->set_rate(ndev);
86a74ff2 1755 }
3340d2aa 1756 if (!mdp->link) {
b2b14d2f 1757 sh_eth_modify(ndev, ECMR, ECMR_TXF, 0);
86a74ff2
NI		 1758 new_state = 1;
1759 mdp->link = phydev->link;
1e1b812b
SS		 1760 if (mdp->cd->no_psr || mdp->no_ether_link)
1761 sh_eth_rcv_snd_enable(ndev);
86a74ff2
NI		 1762 }
1763 } else if (mdp->link) {
1764 new_state = 1;
3340d2aa 1765 mdp->link = 0;
86a74ff2
NI		 1766 mdp->speed = 0;
1767 mdp->duplex = -1;
1e1b812b
SS		 1768 if (mdp->cd->no_psr || mdp->no_ether_link)
1769 sh_eth_rcv_snd_disable(ndev);
86a74ff2
NI		 1770 }
1771
dc19e4e5 1772 if (new_state && netif_msg_link(mdp))
86a74ff2
NI		 1773 phy_print_status(phydev);
1774}
1775
1776/* PHY init function */
1777static int sh_eth_phy_init(struct net_device *ndev)
1778{
702eca02 1779 struct device_node *np = ndev->dev.parent->of_node;
86a74ff2 1780 struct sh_eth_private *mdp = netdev_priv(ndev);
4fa8c3cc 1781 struct phy_device *phydev;
86a74ff2 1782
3340d2aa 1783 mdp->link = 0;
86a74ff2
NI		 1784 mdp->speed = 0;
1785 mdp->duplex = -1;
1786
1787 /* Try connect to PHY */
702eca02
BD		 1788 if (np) {
1789 struct device_node *pn;
1790
1791 pn = of_parse_phandle(np, "phy-handle", 0);
1792 phydev = of_phy_connect(ndev, pn,
1793 sh_eth_adjust_link, 0,
1794 mdp->phy_interface);
1795
1796 if (!phydev)
1797 phydev = ERR_PTR(-ENOENT);
1798 } else {
1799 char phy_id[MII_BUS_ID_SIZE + 3];
1800
1801 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
1802 mdp->mii_bus->id, mdp->phy_id);
1803
1804 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
1805 mdp->phy_interface);
1806 }
1807
86a74ff2 1808 if (IS_ERR(phydev)) {
da246855 1809 netdev_err(ndev, "failed to connect PHY\n");
86a74ff2
NI		 1810 return PTR_ERR(phydev);
1811 }
380af9e3 1812
2220943a 1813 phy_attached_info(phydev);
86a74ff2
NI		 1814
1815 mdp->phydev = phydev;
1816
1817 return 0;
1818}
1819
1820/* PHY control start function */
1821static int sh_eth_phy_start(struct net_device *ndev)
1822{
1823 struct sh_eth_private *mdp = netdev_priv(ndev);
1824 int ret;
1825
1826 ret = sh_eth_phy_init(ndev);
1827 if (ret)
1828 return ret;
1829
86a74ff2
NI		 1830 phy_start(mdp->phydev);
1831
1832 return 0;
1833}
1834
dc19e4e5 1835static int sh_eth_get_settings(struct net_device *ndev,
128296fc 1836 struct ethtool_cmd *ecmd)
dc19e4e5
NI		 1837{
1838 struct sh_eth_private *mdp = netdev_priv(ndev);
1839 unsigned long flags;
1840 int ret;
1841
4f9dce23
BH		 1842 if (!mdp->phydev)
1843 return -ENODEV;
1844
dc19e4e5
NI		 1845 spin_lock_irqsave(&mdp->lock, flags);
1846 ret = phy_ethtool_gset(mdp->phydev, ecmd);
1847 spin_unlock_irqrestore(&mdp->lock, flags);
1848
1849 return ret;
1850}
1851
1852static int sh_eth_set_settings(struct net_device *ndev,
128296fc 1853 struct ethtool_cmd *ecmd)
dc19e4e5
NI		 1854{
1855 struct sh_eth_private *mdp = netdev_priv(ndev);
1856 unsigned long flags;
1857 int ret;
dc19e4e5 1858
4f9dce23
BH		 1859 if (!mdp->phydev)
1860 return -ENODEV;
1861
dc19e4e5
NI		 1862 spin_lock_irqsave(&mdp->lock, flags);
1863
1864 /* disable tx and rx */
4a55530f 1865 sh_eth_rcv_snd_disable(ndev);
dc19e4e5
NI		 1866
1867 ret = phy_ethtool_sset(mdp->phydev, ecmd);
1868 if (ret)
1869 goto error_exit;
1870
1871 if (ecmd->duplex == DUPLEX_FULL)
1872 mdp->duplex = 1;
1873 else
1874 mdp->duplex = 0;
1875
1876 if (mdp->cd->set_duplex)
1877 mdp->cd->set_duplex(ndev);
1878
1879error_exit:
1880 mdelay(1);
1881
1882 /* enable tx and rx */
4a55530f 1883 sh_eth_rcv_snd_enable(ndev);
dc19e4e5
NI		 1884
1885 spin_unlock_irqrestore(&mdp->lock, flags);
1886
1887 return ret;
1888}
1889
6b4b4fea
BH		 1890/* If it is ever necessary to increase SH_ETH_REG_DUMP_MAX_REGS, the
1891 * version must be bumped as well. Just adding registers up to that
1892 * limit is fine, as long as the existing register indices don't
1893 * change.
1894 */
1895#define SH_ETH_REG_DUMP_VERSION 1
1896#define SH_ETH_REG_DUMP_MAX_REGS 256
1897
1898static size_t __sh_eth_get_regs(struct net_device *ndev, u32 *buf)
1899{
1900 struct sh_eth_private *mdp = netdev_priv(ndev);
1901 struct sh_eth_cpu_data *cd = mdp->cd;
1902 u32 *valid_map;
1903 size_t len;
1904
1905 BUILD_BUG_ON(SH_ETH_MAX_REGISTER_OFFSET > SH_ETH_REG_DUMP_MAX_REGS);
1906
1907 /* Dump starts with a bitmap that tells ethtool which
1908 * registers are defined for this chip.
1909 */
1910 len = DIV_ROUND_UP(SH_ETH_REG_DUMP_MAX_REGS, 32);
1911 if (buf) {
1912 valid_map = buf;
1913 buf += len;
1914 } else {
1915 valid_map = NULL;
1916 }
1917
1918 /* Add a register to the dump, if it has a defined offset.
1919 * This automatically skips most undefined registers, but for
1920 * some it is also necessary to check a capability flag in
1921 * struct sh_eth_cpu_data.
1922 */
1923#define mark_reg_valid(reg) valid_map[reg / 32] |= 1U << (reg % 32)
1924#define add_reg_from(reg, read_expr) do { \
1925 if (mdp->reg_offset[reg] != SH_ETH_OFFSET_INVALID) { \
1926 if (buf) { \
1927 mark_reg_valid(reg); \
1928 *buf++ = read_expr; \
1929 } \
1930 ++len; \
1931 } \
1932 } while (0)
1933#define add_reg(reg) add_reg_from(reg, sh_eth_read(ndev, reg))
1934#define add_tsu_reg(reg) add_reg_from(reg, sh_eth_tsu_read(mdp, reg))
1935
1936 add_reg(EDSR);
1937 add_reg(EDMR);
1938 add_reg(EDTRR);
1939 add_reg(EDRRR);
1940 add_reg(EESR);
1941 add_reg(EESIPR);
1942 add_reg(TDLAR);
1943 add_reg(TDFAR);
1944 add_reg(TDFXR);
1945 add_reg(TDFFR);
1946 add_reg(RDLAR);
1947 add_reg(RDFAR);
1948 add_reg(RDFXR);
1949 add_reg(RDFFR);
1950 add_reg(TRSCER);
1951 add_reg(RMFCR);
1952 add_reg(TFTR);
1953 add_reg(FDR);
1954 add_reg(RMCR);
1955 add_reg(TFUCR);
1956 add_reg(RFOCR);
1957 if (cd->rmiimode)
1958 add_reg(RMIIMODE);
1959 add_reg(FCFTR);
1960 if (cd->rpadir)
1961 add_reg(RPADIR);
1962 if (!cd->no_trimd)
1963 add_reg(TRIMD);
1964 add_reg(ECMR);
1965 add_reg(ECSR);
1966 add_reg(ECSIPR);
1967 add_reg(PIR);
1968 if (!cd->no_psr)
1969 add_reg(PSR);
1970 add_reg(RDMLR);
1971 add_reg(RFLR);
1972 add_reg(IPGR);
1973 if (cd->apr)
1974 add_reg(APR);
1975 if (cd->mpr)
1976 add_reg(MPR);
1977 add_reg(RFCR);
1978 add_reg(RFCF);
1979 if (cd->tpauser)
1980 add_reg(TPAUSER);
1981 add_reg(TPAUSECR);
1982 add_reg(GECMR);
1983 if (cd->bculr)
1984 add_reg(BCULR);
1985 add_reg(MAHR);
1986 add_reg(MALR);
1987 add_reg(TROCR);
1988 add_reg(CDCR);
1989 add_reg(LCCR);
1990 add_reg(CNDCR);
1991 add_reg(CEFCR);
1992 add_reg(FRECR);
1993 add_reg(TSFRCR);
1994 add_reg(TLFRCR);
1995 add_reg(CERCR);
1996 add_reg(CEECR);
1997 add_reg(MAFCR);
1998 if (cd->rtrate)
1999 add_reg(RTRATE);
2000 if (cd->hw_crc)
2001 add_reg(CSMR);
2002 if (cd->select_mii)
2003 add_reg(RMII_MII);
2004 add_reg(ARSTR);
2005 if (cd->tsu) {
2006 add_tsu_reg(TSU_CTRST);
2007 add_tsu_reg(TSU_FWEN0);
2008 add_tsu_reg(TSU_FWEN1);
2009 add_tsu_reg(TSU_FCM);
2010 add_tsu_reg(TSU_BSYSL0);
2011 add_tsu_reg(TSU_BSYSL1);
2012 add_tsu_reg(TSU_PRISL0);
2013 add_tsu_reg(TSU_PRISL1);
2014 add_tsu_reg(TSU_FWSL0);
2015 add_tsu_reg(TSU_FWSL1);
2016 add_tsu_reg(TSU_FWSLC);
2017 add_tsu_reg(TSU_QTAG0);
2018 add_tsu_reg(TSU_QTAG1);
2019 add_tsu_reg(TSU_QTAGM0);
2020 add_tsu_reg(TSU_QTAGM1);
2021 add_tsu_reg(TSU_FWSR);
2022 add_tsu_reg(TSU_FWINMK);
2023 add_tsu_reg(TSU_ADQT0);
2024 add_tsu_reg(TSU_ADQT1);
2025 add_tsu_reg(TSU_VTAG0);
2026 add_tsu_reg(TSU_VTAG1);
2027 add_tsu_reg(TSU_ADSBSY);
2028 add_tsu_reg(TSU_TEN);
2029 add_tsu_reg(TSU_POST1);
2030 add_tsu_reg(TSU_POST2);
2031 add_tsu_reg(TSU_POST3);
2032 add_tsu_reg(TSU_POST4);
2033 if (mdp->reg_offset[TSU_ADRH0] != SH_ETH_OFFSET_INVALID) {
2034 /* This is the start of a table, not just a single
2035 * register.
2036 */
2037 if (buf) {
2038 unsigned int i;
2039
2040 mark_reg_valid(TSU_ADRH0);
2041 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES * 2; i++)
2042 *buf++ = ioread32(
2043 mdp->tsu_addr +
2044 mdp->reg_offset[TSU_ADRH0] +
2045 i * 4);
2046 }
2047 len += SH_ETH_TSU_CAM_ENTRIES * 2;
2048 }
2049 }
2050
2051#undef mark_reg_valid
2052#undef add_reg_from
2053#undef add_reg
2054#undef add_tsu_reg
2055
2056 return len * 4;
2057}
2058
2059static int sh_eth_get_regs_len(struct net_device *ndev)
2060{
2061 return __sh_eth_get_regs(ndev, NULL);
2062}
2063
2064static void sh_eth_get_regs(struct net_device *ndev, struct ethtool_regs *regs,
2065 void *buf)
2066{
2067 struct sh_eth_private *mdp = netdev_priv(ndev);
2068
2069 regs->version = SH_ETH_REG_DUMP_VERSION;
2070
2071 pm_runtime_get_sync(&mdp->pdev->dev);
2072 __sh_eth_get_regs(ndev, buf);
2073 pm_runtime_put_sync(&mdp->pdev->dev);
2074}
2075
dc19e4e5
NI		 2076static int sh_eth_nway_reset(struct net_device *ndev)
2077{
2078 struct sh_eth_private *mdp = netdev_priv(ndev);
2079 unsigned long flags;
2080 int ret;
2081
4f9dce23
BH		 2082 if (!mdp->phydev)
2083 return -ENODEV;
2084
dc19e4e5
NI		 2085 spin_lock_irqsave(&mdp->lock, flags);
2086 ret = phy_start_aneg(mdp->phydev);
2087 spin_unlock_irqrestore(&mdp->lock, flags);
2088
2089 return ret;
2090}
2091
2092static u32 sh_eth_get_msglevel(struct net_device *ndev)
2093{
2094 struct sh_eth_private *mdp = netdev_priv(ndev);
2095 return mdp->msg_enable;
2096}
2097
2098static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
2099{
2100 struct sh_eth_private *mdp = netdev_priv(ndev);
2101 mdp->msg_enable = value;
2102}
2103
2104static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
2105 "rx_current", "tx_current",
2106 "rx_dirty", "tx_dirty",
2107};
2108#define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats)
2109
2110static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
2111{
2112 switch (sset) {
2113 case ETH_SS_STATS:
2114 return SH_ETH_STATS_LEN;
2115 default:
2116 return -EOPNOTSUPP;
2117 }
2118}
2119
2120static void sh_eth_get_ethtool_stats(struct net_device *ndev,
128296fc 2121 struct ethtool_stats *stats, u64 *data)
dc19e4e5
NI		 2122{
2123 struct sh_eth_private *mdp = netdev_priv(ndev);
2124 int i = 0;
2125
2126 /* device-specific stats */
2127 data[i++] = mdp->cur_rx;
2128 data[i++] = mdp->cur_tx;
2129 data[i++] = mdp->dirty_rx;
2130 data[i++] = mdp->dirty_tx;
2131}
2132
2133static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
2134{
2135 switch (stringset) {
2136 case ETH_SS_STATS:
2137 memcpy(data, *sh_eth_gstrings_stats,
128296fc 2138 sizeof(sh_eth_gstrings_stats));
dc19e4e5
NI		 2139 break;
2140 }
2141}
2142
525b8075
YS		 2143static void sh_eth_get_ringparam(struct net_device *ndev,
2144 struct ethtool_ringparam *ring)
2145{
2146 struct sh_eth_private *mdp = netdev_priv(ndev);
2147
2148 ring->rx_max_pending = RX_RING_MAX;
2149 ring->tx_max_pending = TX_RING_MAX;
2150 ring->rx_pending = mdp->num_rx_ring;
2151 ring->tx_pending = mdp->num_tx_ring;
2152}
2153
2154static int sh_eth_set_ringparam(struct net_device *ndev,
2155 struct ethtool_ringparam *ring)
2156{
2157 struct sh_eth_private *mdp = netdev_priv(ndev);
2158 int ret;
2159
2160 if (ring->tx_pending > TX_RING_MAX ||
2161 ring->rx_pending > RX_RING_MAX ||
2162 ring->tx_pending < TX_RING_MIN ||
2163 ring->rx_pending < RX_RING_MIN)
2164 return -EINVAL;
2165 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
2166 return -EINVAL;
2167
2168 if (netif_running(ndev)) {
bd888916 2169 netif_device_detach(ndev);
525b8075 2170 netif_tx_disable(ndev);
283e38db
BH		 2171
2172 /* Serialise with the interrupt handler and NAPI, then
2173 * disable interrupts. We have to clear the
2174 * irq_enabled flag first to ensure that interrupts
2175 * won't be re-enabled.
2176 */
2177 mdp->irq_enabled = false;
525b8075 2178 synchronize_irq(ndev->irq);
283e38db 2179 napi_synchronize(&mdp->napi);
525b8075 2180 sh_eth_write(ndev, 0x0000, EESIPR);
525b8075 2181
740c7f31 2182 sh_eth_dev_exit(ndev);
525b8075 2183
8e03a5e7 2184 /* Free all the skbuffs in the Rx queue and the DMA buffers. */
084236d8 2185 sh_eth_ring_free(ndev);
084236d8 2186 }
525b8075
YS		 2187
2188 /* Set new parameters */
2189 mdp->num_rx_ring = ring->rx_pending;
2190 mdp->num_tx_ring = ring->tx_pending;
2191
525b8075 2192 if (netif_running(ndev)) {
084236d8
BH		 2193 ret = sh_eth_ring_init(ndev);
2194 if (ret < 0) {
2195 netdev_err(ndev, "%s: sh_eth_ring_init failed.\n",
2196 __func__);
2197 return ret;
2198 }
2199 ret = sh_eth_dev_init(ndev, false);
2200 if (ret < 0) {
2201 netdev_err(ndev, "%s: sh_eth_dev_init failed.\n",
2202 __func__);
2203 return ret;
2204 }
2205
283e38db 2206 mdp->irq_enabled = true;
525b8075
YS		 2207 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
2208 /* Setting the Rx mode will start the Rx process. */
2209 sh_eth_write(ndev, EDRRR_R, EDRRR);
bd888916 2210 netif_device_attach(ndev);
525b8075
YS		 2211 }
2212
2213 return 0;
2214}
2215
9b07be4b 2216static const struct ethtool_ops sh_eth_ethtool_ops = {
dc19e4e5
NI		 2217 .get_settings = sh_eth_get_settings,
2218 .set_settings = sh_eth_set_settings,
6b4b4fea
BH		 2219 .get_regs_len = sh_eth_get_regs_len,
2220 .get_regs = sh_eth_get_regs,
9b07be4b 2221 .nway_reset = sh_eth_nway_reset,
dc19e4e5
NI		 2222 .get_msglevel = sh_eth_get_msglevel,
2223 .set_msglevel = sh_eth_set_msglevel,
9b07be4b 2224 .get_link = ethtool_op_get_link,
dc19e4e5
NI		 2225 .get_strings = sh_eth_get_strings,
2226 .get_ethtool_stats = sh_eth_get_ethtool_stats,
2227 .get_sset_count = sh_eth_get_sset_count,
525b8075
YS		 2228 .get_ringparam = sh_eth_get_ringparam,
2229 .set_ringparam = sh_eth_set_ringparam,
dc19e4e5
NI		 2230};
2231
86a74ff2
NI		 2232/* network device open function */
2233static int sh_eth_open(struct net_device *ndev)
2234{
86a74ff2 2235 struct sh_eth_private *mdp = netdev_priv(ndev);
4fa8c3cc 2236 int ret;
86a74ff2 2237
bcd5149d
MD		 2238 pm_runtime_get_sync(&mdp->pdev->dev);
2239
d2779e99
SS		 2240 napi_enable(&mdp->napi);
2241
a0607fd3 2242 ret = request_irq(ndev->irq, sh_eth_interrupt,
5b3dfd13 2243 mdp->cd->irq_flags, ndev->name, ndev);
86a74ff2 2244 if (ret) {
da246855 2245 netdev_err(ndev, "Can not assign IRQ number\n");
d2779e99 2246 goto out_napi_off;
86a74ff2
NI		 2247 }
2248
2249 /* Descriptor set */
2250 ret = sh_eth_ring_init(ndev);
2251 if (ret)
2252 goto out_free_irq;
2253
2254 /* device init */
525b8075 2255 ret = sh_eth_dev_init(ndev, true);
86a74ff2
NI		 2256 if (ret)
2257 goto out_free_irq;
2258
2259 /* PHY control start*/
2260 ret = sh_eth_phy_start(ndev);
2261 if (ret)
2262 goto out_free_irq;
2263
7fa2955f
MK		 2264 mdp->is_opened = 1;
2265
86a74ff2
NI		 2266 return ret;
2267
2268out_free_irq:
2269 free_irq(ndev->irq, ndev);
d2779e99
SS		 2270out_napi_off:
2271 napi_disable(&mdp->napi);
bcd5149d 2272 pm_runtime_put_sync(&mdp->pdev->dev);
86a74ff2
NI		 2273 return ret;
2274}
2275
2276/* Timeout function */
2277static void sh_eth_tx_timeout(struct net_device *ndev)
2278{
2279 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 2280 struct sh_eth_rxdesc *rxdesc;
2281 int i;
2282
2283 netif_stop_queue(ndev);
2284
8d5009f6
SS		 2285 netif_err(mdp, timer, ndev,
2286 "transmit timed out, status %8.8x, resetting...\n",
0799c2d6 2287 sh_eth_read(ndev, EESR));
86a74ff2
NI		 2288
2289 /* tx_errors count up */
bb7d92e3 2290 ndev->stats.tx_errors++;
86a74ff2 2291
86a74ff2 2292 /* Free all the skbuffs in the Rx queue. */
525b8075 2293 for (i = 0; i < mdp->num_rx_ring; i++) {
86a74ff2 2294 rxdesc = &mdp->rx_ring[i];
7cf72477
SS		 2295 rxdesc->status = cpu_to_le32(0);
2296 rxdesc->addr = cpu_to_le32(0xBADF00D0);
179d80af 2297 dev_kfree_skb(mdp->rx_skbuff[i]);
86a74ff2
NI		 2298 mdp->rx_skbuff[i] = NULL;
2299 }
525b8075 2300 for (i = 0; i < mdp->num_tx_ring; i++) {
179d80af 2301 dev_kfree_skb(mdp->tx_skbuff[i]);
86a74ff2
NI		 2302 mdp->tx_skbuff[i] = NULL;
2303 }
2304
2305 /* device init */
525b8075 2306 sh_eth_dev_init(ndev, true);
86a74ff2
NI		 2307}
2308
2309/* Packet transmit function */
2310static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
2311{
2312 struct sh_eth_private *mdp = netdev_priv(ndev);
2313 struct sh_eth_txdesc *txdesc;
1299653a 2314 dma_addr_t dma_addr;
86a74ff2 2315 u32 entry;
fb5e2f9b 2316 unsigned long flags;
86a74ff2
NI		 2317
2318 spin_lock_irqsave(&mdp->lock, flags);
525b8075 2319 if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
86a74ff2 2320 if (!sh_eth_txfree(ndev)) {
8d5009f6 2321 netif_warn(mdp, tx_queued, ndev, "TxFD exhausted.\n");
86a74ff2
NI		 2322 netif_stop_queue(ndev);
2323 spin_unlock_irqrestore(&mdp->lock, flags);
5b548140 2324 return NETDEV_TX_BUSY;
86a74ff2
NI		 2325 }
2326 }
2327 spin_unlock_irqrestore(&mdp->lock, flags);
2328
dacc73e0 2329 if (skb_put_padto(skb, ETH_ZLEN))
eebfb643
BH		 2330 return NETDEV_TX_OK;
2331
525b8075 2332 entry = mdp->cur_tx % mdp->num_tx_ring;
86a74ff2
NI		 2333 mdp->tx_skbuff[entry] = skb;
2334 txdesc = &mdp->tx_ring[entry];
86a74ff2 2335 /* soft swap. */
380af9e3 2336 if (!mdp->cd->hw_swap)
3e230993 2337 sh_eth_soft_swap(PTR_ALIGN(skb->data, 4), skb->len + 2);
1299653a
SS		 2338 dma_addr = dma_map_single(&ndev->dev, skb->data, skb->len,
2339 DMA_TO_DEVICE);
2340 if (dma_mapping_error(&ndev->dev, dma_addr)) {
aa3933b8
BH		 2341 kfree_skb(skb);
2342 return NETDEV_TX_OK;
2343 }
7cf72477
SS		 2344 txdesc->addr = cpu_to_le32(dma_addr);
2345 txdesc->len = cpu_to_le32(skb->len << 16);
86a74ff2 2346
f32bfb9a 2347 dma_wmb(); /* TACT bit must be set after all the above writes */
525b8075 2348 if (entry >= mdp->num_tx_ring - 1)
7cf72477 2349 txdesc->status |= cpu_to_le32(TD_TACT | TD_TDLE);
86a74ff2 2350 else
7cf72477 2351 txdesc->status |= cpu_to_le32(TD_TACT);
86a74ff2
NI		 2352
2353 mdp->cur_tx++;
2354
c5ed5368
YS		 2355 if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
2356 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
b0ca2a21 2357
6ed10654 2358 return NETDEV_TX_OK;
86a74ff2
NI		 2359}
2360
4398f9c8
BH		 2361/* The statistics registers have write-clear behaviour, which means we
2362 * will lose any increment between the read and write. We mitigate
2363 * this by only clearing when we read a non-zero value, so we will
2364 * never falsely report a total of zero.
2365 */
2366static void
2367sh_eth_update_stat(struct net_device *ndev, unsigned long *stat, int reg)
2368{
2369 u32 delta = sh_eth_read(ndev, reg);
2370
2371 if (delta) {
2372 *stat += delta;
2373 sh_eth_write(ndev, 0, reg);
2374 }
2375}
2376
7fa2955f
MK		 2377static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
2378{
2379 struct sh_eth_private *mdp = netdev_priv(ndev);
2380
2381 if (sh_eth_is_rz_fast_ether(mdp))
2382 return &ndev->stats;
2383
2384 if (!mdp->is_opened)
2385 return &ndev->stats;
2386
4398f9c8
BH		 2387 sh_eth_update_stat(ndev, &ndev->stats.tx_dropped, TROCR);
2388 sh_eth_update_stat(ndev, &ndev->stats.collisions, CDCR);
2389 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, LCCR);
7fa2955f
MK		 2390
2391 if (sh_eth_is_gether(mdp)) {
4398f9c8
BH		 2392 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2393 CERCR);
2394 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2395 CEECR);
7fa2955f 2396 } else {
4398f9c8
BH		 2397 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2398 CNDCR);
7fa2955f
MK		 2399 }
2400
2401 return &ndev->stats;
2402}
2403
86a74ff2
NI		 2404/* device close function */
2405static int sh_eth_close(struct net_device *ndev)
2406{
2407 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 2408
2409 netif_stop_queue(ndev);
2410
283e38db
BH		 2411 /* Serialise with the interrupt handler and NAPI, then disable
2412 * interrupts. We have to clear the irq_enabled flag first to
2413 * ensure that interrupts won't be re-enabled.
2414 */
2415 mdp->irq_enabled = false;
2416 synchronize_irq(ndev->irq);
2417 napi_disable(&mdp->napi);
4a55530f 2418 sh_eth_write(ndev, 0x0000, EESIPR);
86a74ff2 2419
740c7f31 2420 sh_eth_dev_exit(ndev);
86a74ff2
NI		 2421
2422 /* PHY Disconnect */
2423 if (mdp->phydev) {
2424 phy_stop(mdp->phydev);
2425 phy_disconnect(mdp->phydev);
4f9dce23 2426 mdp->phydev = NULL;
86a74ff2
NI		 2427 }
2428
2429 free_irq(ndev->irq, ndev);
2430
8e03a5e7 2431 /* Free all the skbuffs in the Rx queue and the DMA buffer. */
86a74ff2
NI		 2432 sh_eth_ring_free(ndev);
2433
bcd5149d
MD		 2434 pm_runtime_put_sync(&mdp->pdev->dev);
2435
7fa2955f 2436 mdp->is_opened = 0;
bcd5149d 2437
7fa2955f 2438 return 0;
86a74ff2
NI		 2439}
2440
bb7d92e3 2441/* ioctl to device function */
128296fc 2442static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
86a74ff2
NI		 2443{
2444 struct sh_eth_private *mdp = netdev_priv(ndev);
2445 struct phy_device *phydev = mdp->phydev;
2446
2447 if (!netif_running(ndev))
2448 return -EINVAL;
2449
2450 if (!phydev)
2451 return -ENODEV;
2452
28b04113 2453 return phy_mii_ioctl(phydev, rq, cmd);
86a74ff2
NI		 2454}
2455
6743fe6d
YS		 2456/* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
2457static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp,
2458 int entry)
2459{
2460 return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4);
2461}
2462
2463static u32 sh_eth_tsu_get_post_mask(int entry)
2464{
2465 return 0x0f << (28 - ((entry % 8) * 4));
2466}
2467
2468static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
2469{
2470 return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
2471}
2472
2473static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
2474 int entry)
2475{
2476 struct sh_eth_private *mdp = netdev_priv(ndev);
2477 u32 tmp;
2478 void *reg_offset;
2479
2480 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2481 tmp = ioread32(reg_offset);
2482 iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset);
2483}
2484
2485static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
2486 int entry)
2487{
2488 struct sh_eth_private *mdp = netdev_priv(ndev);
2489 u32 post_mask, ref_mask, tmp;
2490 void *reg_offset;
2491
2492 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2493 post_mask = sh_eth_tsu_get_post_mask(entry);
2494 ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
2495
2496 tmp = ioread32(reg_offset);
2497 iowrite32(tmp & ~post_mask, reg_offset);
2498
2499 /* If other port enables, the function returns "true" */
2500 return tmp & ref_mask;
2501}
2502
2503static int sh_eth_tsu_busy(struct net_device *ndev)
2504{
2505 int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
2506 struct sh_eth_private *mdp = netdev_priv(ndev);
2507
2508 while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
2509 udelay(10);
2510 timeout--;
2511 if (timeout <= 0) {
da246855 2512 netdev_err(ndev, "%s: timeout\n", __func__);
6743fe6d
YS		 2513 return -ETIMEDOUT;
2514 }
2515 }
2516
2517 return 0;
2518}
2519
2520static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg,
2521 const u8 *addr)
2522{
2523 u32 val;
2524
2525 val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
2526 iowrite32(val, reg);
2527 if (sh_eth_tsu_busy(ndev) < 0)
2528 return -EBUSY;
2529
2530 val = addr[4] << 8 | addr[5];
2531 iowrite32(val, reg + 4);
2532 if (sh_eth_tsu_busy(ndev) < 0)
2533 return -EBUSY;
2534
2535 return 0;
2536}
2537
2538static void sh_eth_tsu_read_entry(void *reg, u8 *addr)
2539{
2540 u32 val;
2541
2542 val = ioread32(reg);
2543 addr[0] = (val >> 24) & 0xff;
2544 addr[1] = (val >> 16) & 0xff;
2545 addr[2] = (val >> 8) & 0xff;
2546 addr[3] = val & 0xff;
2547 val = ioread32(reg + 4);
2548 addr[4] = (val >> 8) & 0xff;
2549 addr[5] = val & 0xff;
2550}
2551
2552
2553static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
2554{
2555 struct sh_eth_private *mdp = netdev_priv(ndev);
2556 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2557 int i;
2558 u8 c_addr[ETH_ALEN];
2559
2560 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2561 sh_eth_tsu_read_entry(reg_offset, c_addr);
c4bde29c 2562 if (ether_addr_equal(addr, c_addr))
6743fe6d
YS		 2563 return i;
2564 }
2565
2566 return -ENOENT;
2567}
2568
2569static int sh_eth_tsu_find_empty(struct net_device *ndev)
2570{
2571 u8 blank[ETH_ALEN];
2572 int entry;
2573
2574 memset(blank, 0, sizeof(blank));
2575 entry = sh_eth_tsu_find_entry(ndev, blank);
2576 return (entry < 0) ? -ENOMEM : entry;
2577}
2578
2579static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
2580 int entry)
2581{
2582 struct sh_eth_private *mdp = netdev_priv(ndev);
2583 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2584 int ret;
2585 u8 blank[ETH_ALEN];
2586
2587 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
2588 ~(1 << (31 - entry)), TSU_TEN);
2589
2590 memset(blank, 0, sizeof(blank));
2591 ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
2592 if (ret < 0)
2593 return ret;
2594 return 0;
2595}
2596
2597static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
2598{
2599 struct sh_eth_private *mdp = netdev_priv(ndev);
2600 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2601 int i, ret;
2602
2603 if (!mdp->cd->tsu)
2604 return 0;
2605
2606 i = sh_eth_tsu_find_entry(ndev, addr);
2607 if (i < 0) {
2608 /* No entry found, create one */
2609 i = sh_eth_tsu_find_empty(ndev);
2610 if (i < 0)
2611 return -ENOMEM;
2612 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
2613 if (ret < 0)
2614 return ret;
2615
2616 /* Enable the entry */
2617 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
2618 (1 << (31 - i)), TSU_TEN);
2619 }
2620
2621 /* Entry found or created, enable POST */
2622 sh_eth_tsu_enable_cam_entry_post(ndev, i);
2623
2624 return 0;
2625}
2626
2627static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
2628{
2629 struct sh_eth_private *mdp = netdev_priv(ndev);
2630 int i, ret;
2631
2632 if (!mdp->cd->tsu)
2633 return 0;
2634
2635 i = sh_eth_tsu_find_entry(ndev, addr);
2636 if (i) {
2637 /* Entry found */
2638 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2639 goto done;
2640
2641 /* Disable the entry if both ports was disabled */
2642 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2643 if (ret < 0)
2644 return ret;
2645 }
2646done:
2647 return 0;
2648}
2649
2650static int sh_eth_tsu_purge_all(struct net_device *ndev)
2651{
2652 struct sh_eth_private *mdp = netdev_priv(ndev);
2653 int i, ret;
2654
b37feed7 2655 if (!mdp->cd->tsu)
6743fe6d
YS		 2656 return 0;
2657
2658 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
2659 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2660 continue;
2661
2662 /* Disable the entry if both ports was disabled */
2663 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2664 if (ret < 0)
2665 return ret;
2666 }
2667
2668 return 0;
2669}
2670
2671static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
2672{
2673 struct sh_eth_private *mdp = netdev_priv(ndev);
2674 u8 addr[ETH_ALEN];
2675 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2676 int i;
2677
b37feed7 2678 if (!mdp->cd->tsu)
6743fe6d
YS		 2679 return;
2680
2681 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2682 sh_eth_tsu_read_entry(reg_offset, addr);
2683 if (is_multicast_ether_addr(addr))
2684 sh_eth_tsu_del_entry(ndev, addr);
2685 }
2686}
2687
b37feed7
BH		 2688/* Update promiscuous flag and multicast filter */
2689static void sh_eth_set_rx_mode(struct net_device *ndev)
86a74ff2 2690{
6743fe6d
YS		 2691 struct sh_eth_private *mdp = netdev_priv(ndev);
2692 u32 ecmr_bits;
2693 int mcast_all = 0;
2694 unsigned long flags;
2695
2696 spin_lock_irqsave(&mdp->lock, flags);
128296fc 2697 /* Initial condition is MCT = 1, PRM = 0.
6743fe6d
YS		 2698 * Depending on ndev->flags, set PRM or clear MCT
2699 */
b37feed7
BH		 2700 ecmr_bits = sh_eth_read(ndev, ECMR) & ~ECMR_PRM;
2701 if (mdp->cd->tsu)
2702 ecmr_bits |= ECMR_MCT;
6743fe6d
YS		 2703
2704 if (!(ndev->flags & IFF_MULTICAST)) {
2705 sh_eth_tsu_purge_mcast(ndev);
2706 mcast_all = 1;
2707 }
2708 if (ndev->flags & IFF_ALLMULTI) {
2709 sh_eth_tsu_purge_mcast(ndev);
2710 ecmr_bits &= ~ECMR_MCT;
2711 mcast_all = 1;
2712 }
2713
86a74ff2 2714 if (ndev->flags & IFF_PROMISC) {
6743fe6d
YS		 2715 sh_eth_tsu_purge_all(ndev);
2716 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2717 } else if (mdp->cd->tsu) {
2718 struct netdev_hw_addr *ha;
2719 netdev_for_each_mc_addr(ha, ndev) {
2720 if (mcast_all && is_multicast_ether_addr(ha->addr))
2721 continue;
2722
2723 if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2724 if (!mcast_all) {
2725 sh_eth_tsu_purge_mcast(ndev);
2726 ecmr_bits &= ~ECMR_MCT;
2727 mcast_all = 1;
2728 }
2729 }
2730 }
86a74ff2 2731 }
6743fe6d
YS		 2732
2733 /* update the ethernet mode */
2734 sh_eth_write(ndev, ecmr_bits, ECMR);
2735
2736 spin_unlock_irqrestore(&mdp->lock, flags);
86a74ff2 2737}
71cc7c37
YS		 2738
2739static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2740{
2741 if (!mdp->port)
2742 return TSU_VTAG0;
2743 else
2744 return TSU_VTAG1;
2745}
2746
80d5c368
PM		 2747static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
2748 __be16 proto, u16 vid)
71cc7c37
YS		 2749{
2750 struct sh_eth_private *mdp = netdev_priv(ndev);
2751 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2752
2753 if (unlikely(!mdp->cd->tsu))
2754 return -EPERM;
2755
2756 /* No filtering if vid = 0 */
2757 if (!vid)
2758 return 0;
2759
2760 mdp->vlan_num_ids++;
2761
128296fc 2762 /* The controller has one VLAN tag HW filter. So, if the filter is
71cc7c37
YS		 2763 * already enabled, the driver disables it and the filte
2764 */
2765 if (mdp->vlan_num_ids > 1) {
2766 /* disable VLAN filter */
2767 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2768 return 0;
2769 }
2770
2771 sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
2772 vtag_reg_index);
2773
2774 return 0;
2775}
2776
80d5c368
PM		 2777static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
2778 __be16 proto, u16 vid)
71cc7c37
YS		 2779{
2780 struct sh_eth_private *mdp = netdev_priv(ndev);
2781 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2782
2783 if (unlikely(!mdp->cd->tsu))
2784 return -EPERM;
2785
2786 /* No filtering if vid = 0 */
2787 if (!vid)
2788 return 0;
2789
2790 mdp->vlan_num_ids--;
2791 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2792
2793 return 0;
2794}
86a74ff2
NI		 2795
2796/* SuperH's TSU register init function */
4a55530f 2797static void sh_eth_tsu_init(struct sh_eth_private *mdp)
86a74ff2 2798{
db893473
SH		 2799 if (sh_eth_is_rz_fast_ether(mdp)) {
2800 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2801 return;
2802 }
2803
4a55530f
YS		 2804 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */
2805 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */
2806 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */
2807 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
2808 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
2809 sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
2810 sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
2811 sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
2812 sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
2813 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
c5ed5368
YS		 2814 if (sh_eth_is_gether(mdp)) {
2815 sh_eth_tsu_write(mdp, 0, TSU_QTAG0); /* Disable QTAG(0->1) */
2816 sh_eth_tsu_write(mdp, 0, TSU_QTAG1); /* Disable QTAG(1->0) */
2817 } else {
2818 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */
2819 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */
2820 }
4a55530f
YS		 2821 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */
2822 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */
2823 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2824 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */
2825 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */
2826 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */
2827 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */
86a74ff2
NI		 2828}
2829
2830/* MDIO bus release function */
bd920ff5 2831static int sh_mdio_release(struct sh_eth_private *mdp)
86a74ff2 2832{
86a74ff2 2833 /* unregister mdio bus */
bd920ff5 2834 mdiobus_unregister(mdp->mii_bus);
86a74ff2
NI		 2835
2836 /* free bitbang info */
bd920ff5 2837 free_mdio_bitbang(mdp->mii_bus);
86a74ff2
NI		 2838
2839 return 0;
2840}
2841
2842/* MDIO bus init function */
bd920ff5 2843static int sh_mdio_init(struct sh_eth_private *mdp,
b3017e6a 2844 struct sh_eth_plat_data *pd)
86a74ff2 2845{
e7f4dc35 2846 int ret;
86a74ff2 2847 struct bb_info *bitbang;
bd920ff5 2848 struct platform_device *pdev = mdp->pdev;
aa8d4225 2849 struct device *dev = &mdp->pdev->dev;
86a74ff2
NI		 2850
2851 /* create bit control struct for PHY */
aa8d4225 2852 bitbang = devm_kzalloc(dev, sizeof(struct bb_info), GFP_KERNEL);
f738a13d
LP		 2853 if (!bitbang)
2854 return -ENOMEM;
86a74ff2
NI		 2855
2856 /* bitbang init */
ae70644d 2857 bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
b3017e6a 2858 bitbang->set_gate = pd->set_mdio_gate;
86a74ff2
NI		 2859 bitbang->ctrl.ops = &bb_ops;
2860
c2e07b3a 2861 /* MII controller setting */
86a74ff2 2862 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
f738a13d
LP		 2863 if (!mdp->mii_bus)
2864 return -ENOMEM;
86a74ff2
NI		 2865
2866 /* Hook up MII support for ethtool */
2867 mdp->mii_bus->name = "sh_mii";
a5bd6060 2868 mdp->mii_bus->parent = dev;
5278fb54 2869 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
bd920ff5 2870 pdev->name, pdev->id);
86a74ff2 2871
bd920ff5
LP		 2872 /* register MDIO bus */
2873 if (dev->of_node) {
2874 ret = of_mdiobus_register(mdp->mii_bus, dev->of_node);
702eca02 2875 } else {
702eca02
BD		 2876 if (pd->phy_irq > 0)
2877 mdp->mii_bus->irq[pd->phy] = pd->phy_irq;
2878
2879 ret = mdiobus_register(mdp->mii_bus);
2880 }
2881
86a74ff2 2882 if (ret)
d5e07e69 2883 goto out_free_bus;
86a74ff2 2884
86a74ff2
NI		 2885 return 0;
2886
86a74ff2 2887out_free_bus:
298cf9be 2888 free_mdio_bitbang(mdp->mii_bus);
86a74ff2
NI		 2889 return ret;
2890}
2891
4a55530f
YS		 2892static const u16 *sh_eth_get_register_offset(int register_type)
2893{
2894 const u16 *reg_offset = NULL;
2895
2896 switch (register_type) {
2897 case SH_ETH_REG_GIGABIT:
2898 reg_offset = sh_eth_offset_gigabit;
2899 break;
db893473
SH		 2900 case SH_ETH_REG_FAST_RZ:
2901 reg_offset = sh_eth_offset_fast_rz;
2902 break;
a3f109bd
SS		 2903 case SH_ETH_REG_FAST_RCAR:
2904 reg_offset = sh_eth_offset_fast_rcar;
2905 break;
4a55530f
YS		 2906 case SH_ETH_REG_FAST_SH4:
2907 reg_offset = sh_eth_offset_fast_sh4;
2908 break;
2909 case SH_ETH_REG_FAST_SH3_SH2:
2910 reg_offset = sh_eth_offset_fast_sh3_sh2;
2911 break;
4a55530f
YS		 2912 }
2913
2914 return reg_offset;
2915}
2916
8f728d79 2917static const struct net_device_ops sh_eth_netdev_ops = {
ebf84eaa
AB		 2918 .ndo_open = sh_eth_open,
2919 .ndo_stop = sh_eth_close,
2920 .ndo_start_xmit = sh_eth_start_xmit,
2921 .ndo_get_stats = sh_eth_get_stats,
b37feed7 2922 .ndo_set_rx_mode = sh_eth_set_rx_mode,
ebf84eaa
AB		 2923 .ndo_tx_timeout = sh_eth_tx_timeout,
2924 .ndo_do_ioctl = sh_eth_do_ioctl,
2925 .ndo_validate_addr = eth_validate_addr,
2926 .ndo_set_mac_address = eth_mac_addr,
2927 .ndo_change_mtu = eth_change_mtu,
2928};
2929
8f728d79
SS		 2930static const struct net_device_ops sh_eth_netdev_ops_tsu = {
2931 .ndo_open = sh_eth_open,
2932 .ndo_stop = sh_eth_close,
2933 .ndo_start_xmit = sh_eth_start_xmit,
2934 .ndo_get_stats = sh_eth_get_stats,
b37feed7 2935 .ndo_set_rx_mode = sh_eth_set_rx_mode,
8f728d79
SS		 2936 .ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid,
2937 .ndo_vlan_rx_kill_vid = sh_eth_vlan_rx_kill_vid,
2938 .ndo_tx_timeout = sh_eth_tx_timeout,
2939 .ndo_do_ioctl = sh_eth_do_ioctl,
2940 .ndo_validate_addr = eth_validate_addr,
2941 .ndo_set_mac_address = eth_mac_addr,
2942 .ndo_change_mtu = eth_change_mtu,
2943};
2944
b356e978
SS		 2945#ifdef CONFIG_OF
2946static struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
2947{
2948 struct device_node *np = dev->of_node;
2949 struct sh_eth_plat_data *pdata;
b356e978
SS		 2950 const char *mac_addr;
2951
2952 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
2953 if (!pdata)
2954 return NULL;
2955
2956 pdata->phy_interface = of_get_phy_mode(np);
2957
b356e978
SS		 2958 mac_addr = of_get_mac_address(np);
2959 if (mac_addr)
2960 memcpy(pdata->mac_addr, mac_addr, ETH_ALEN);
2961
2962 pdata->no_ether_link =
2963 of_property_read_bool(np, "renesas,no-ether-link");
2964 pdata->ether_link_active_low =
2965 of_property_read_bool(np, "renesas,ether-link-active-low");
2966
2967 return pdata;
2968}
2969
2970static const struct of_device_id sh_eth_match_table[] = {
2971 { .compatible = "renesas,gether-r8a7740", .data = &r8a7740_data },
2972 { .compatible = "renesas,ether-r8a7778", .data = &r8a777x_data },
2973 { .compatible = "renesas,ether-r8a7779", .data = &r8a777x_data },
2974 { .compatible = "renesas,ether-r8a7790", .data = &r8a779x_data },
2975 { .compatible = "renesas,ether-r8a7791", .data = &r8a779x_data },
9488e1e5 2976 { .compatible = "renesas,ether-r8a7793", .data = &r8a779x_data },
0f76b9d8 2977 { .compatible = "renesas,ether-r8a7794", .data = &r8a779x_data },
b356e978
SS		 2978 { .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data },
2979 { }
2980};
2981MODULE_DEVICE_TABLE(of, sh_eth_match_table);
2982#else
2983static inline struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
2984{
2985 return NULL;
2986}
2987#endif
2988
86a74ff2
NI		 2989static int sh_eth_drv_probe(struct platform_device *pdev)
2990{
86a74ff2 2991 struct resource *res;
0b76b862 2992 struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev);
afe391ad 2993 const struct platform_device_id *id = platform_get_device_id(pdev);
4fa8c3cc
SS		 2994 struct sh_eth_private *mdp;
2995 struct net_device *ndev;
2996 int ret, devno;
86a74ff2
NI		 2997
2998 /* get base addr */
2999 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
86a74ff2
NI		 3000
3001 ndev = alloc_etherdev(sizeof(struct sh_eth_private));
f738a13d
LP		 3002 if (!ndev)
3003 return -ENOMEM;
86a74ff2 3004
b5893a08
BD		 3005 pm_runtime_enable(&pdev->dev);
3006 pm_runtime_get_sync(&pdev->dev);
3007
86a74ff2
NI		 3008 devno = pdev->id;
3009 if (devno < 0)
3010 devno = 0;
3011
3012 ndev->dma = -1;
cc3c080d 3013 ret = platform_get_irq(pdev, 0);
7a468ac6 3014 if (ret < 0)
86a74ff2 3015 goto out_release;
cc3c080d 3016 ndev->irq = ret;
86a74ff2
NI		 3017
3018 SET_NETDEV_DEV(ndev, &pdev->dev);
3019
86a74ff2 3020 mdp = netdev_priv(ndev);
525b8075
YS		 3021 mdp->num_tx_ring = TX_RING_SIZE;
3022 mdp->num_rx_ring = RX_RING_SIZE;
d5e07e69
SS		 3023 mdp->addr = devm_ioremap_resource(&pdev->dev, res);
3024 if (IS_ERR(mdp->addr)) {
3025 ret = PTR_ERR(mdp->addr);
ae70644d
YS		 3026 goto out_release;
3027 }
3028
c960804f
VB		 3029 ndev->base_addr = res->start;
3030
86a74ff2 3031 spin_lock_init(&mdp->lock);
bcd5149d 3032 mdp->pdev = pdev;
86a74ff2 3033
b356e978
SS		 3034 if (pdev->dev.of_node)
3035 pd = sh_eth_parse_dt(&pdev->dev);
3b4c5cbf
SS		 3036 if (!pd) {
3037 dev_err(&pdev->dev, "no platform data\n");
3038 ret = -EINVAL;
3039 goto out_release;
3040 }
3041
86a74ff2 3042 /* get PHY ID */
71557a37 3043 mdp->phy_id = pd->phy;
e47c9052 3044 mdp->phy_interface = pd->phy_interface;
4923576b
YS		 3045 mdp->no_ether_link = pd->no_ether_link;
3046 mdp->ether_link_active_low = pd->ether_link_active_low;
86a74ff2 3047
380af9e3 3048 /* set cpu data */
42a67c9b 3049 if (id)
b356e978 3050 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data;
42a67c9b
WS		 3051 else
3052 mdp->cd = (struct sh_eth_cpu_data *)of_device_get_match_data(&pdev->dev);
b356e978 3053
a3153d8c 3054 mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type);
264be2f5
SS		 3055 if (!mdp->reg_offset) {
3056 dev_err(&pdev->dev, "Unknown register type (%d)\n",
3057 mdp->cd->register_type);
3058 ret = -EINVAL;
3059 goto out_release;
3060 }
380af9e3
YS		 3061 sh_eth_set_default_cpu_data(mdp->cd);
3062
86a74ff2 3063 /* set function */
8f728d79
SS		 3064 if (mdp->cd->tsu)
3065 ndev->netdev_ops = &sh_eth_netdev_ops_tsu;
3066 else
3067 ndev->netdev_ops = &sh_eth_netdev_ops;
7ad24ea4 3068 ndev->ethtool_ops = &sh_eth_ethtool_ops;
86a74ff2
NI		 3069 ndev->watchdog_timeo = TX_TIMEOUT;
3070
dc19e4e5
NI		 3071 /* debug message level */
3072 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
86a74ff2
NI		 3073
3074 /* read and set MAC address */
748031f9 3075 read_mac_address(ndev, pd->mac_addr);
ff6e7228
SS		 3076 if (!is_valid_ether_addr(ndev->dev_addr)) {
3077 dev_warn(&pdev->dev,
3078 "no valid MAC address supplied, using a random one.\n");
3079 eth_hw_addr_random(ndev);
3080 }
86a74ff2 3081
6ba88021
YS		 3082 /* ioremap the TSU registers */
3083 if (mdp->cd->tsu) {
3084 struct resource *rtsu;
3085 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
d5e07e69
SS		 3086 mdp->tsu_addr = devm_ioremap_resource(&pdev->dev, rtsu);
3087 if (IS_ERR(mdp->tsu_addr)) {
3088 ret = PTR_ERR(mdp->tsu_addr);
fc0c0900
SS		 3089 goto out_release;
3090 }
6743fe6d 3091 mdp->port = devno % 2;
f646968f 3092 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER;
6ba88021
YS		 3093 }
3094
150647fb
YS		 3095 /* initialize first or needed device */
3096 if (!devno || pd->needs_init) {
380af9e3
YS		 3097 if (mdp->cd->chip_reset)
3098 mdp->cd->chip_reset(ndev);
86a74ff2 3099
4986b996
YS		 3100 if (mdp->cd->tsu) {
3101 /* TSU init (Init only)*/
3102 sh_eth_tsu_init(mdp);
3103 }
86a74ff2
NI		 3104 }
3105
966d6dbb
HN		 3106 if (mdp->cd->rmiimode)
3107 sh_eth_write(ndev, 0x1, RMIIMODE);
3108
daacf03f
LP		 3109 /* MDIO bus init */
3110 ret = sh_mdio_init(mdp, pd);
3111 if (ret) {
3112 dev_err(&ndev->dev, "failed to initialise MDIO\n");
3113 goto out_release;
3114 }
3115
3719109d
SS		 3116 netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64);
3117
86a74ff2
NI		 3118 /* network device register */
3119 ret = register_netdev(ndev);
3120 if (ret)
3719109d 3121 goto out_napi_del;
86a74ff2 3122
25985edc 3123 /* print device information */
f75f14ec
SS		 3124 netdev_info(ndev, "Base address at 0x%x, %pM, IRQ %d.\n",
3125 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
86a74ff2 3126
b5893a08 3127 pm_runtime_put(&pdev->dev);
86a74ff2
NI		 3128 platform_set_drvdata(pdev, ndev);
3129
3130 return ret;
3131
3719109d
SS		 3132out_napi_del:
3133 netif_napi_del(&mdp->napi);
daacf03f 3134 sh_mdio_release(mdp);
3719109d 3135
86a74ff2
NI		 3136out_release:
3137 /* net_dev free */
3138 if (ndev)
3139 free_netdev(ndev);
3140
b5893a08
BD		 3141 pm_runtime_put(&pdev->dev);
3142 pm_runtime_disable(&pdev->dev);
86a74ff2
NI		 3143 return ret;
3144}
3145
3146static int sh_eth_drv_remove(struct platform_device *pdev)
3147{
3148 struct net_device *ndev = platform_get_drvdata(pdev);
3719109d 3149 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2 3150
86a74ff2 3151 unregister_netdev(ndev);
3719109d 3152 netif_napi_del(&mdp->napi);
daacf03f 3153 sh_mdio_release(mdp);
bcd5149d 3154 pm_runtime_disable(&pdev->dev);
86a74ff2 3155 free_netdev(ndev);
86a74ff2
NI		 3156
3157 return 0;
3158}
3159
540ad1b8 3160#ifdef CONFIG_PM
b71af046
MU		 3161#ifdef CONFIG_PM_SLEEP
3162static int sh_eth_suspend(struct device *dev)
3163{
3164 struct net_device *ndev = dev_get_drvdata(dev);
3165 int ret = 0;
3166
3167 if (netif_running(ndev)) {
3168 netif_device_detach(ndev);
3169 ret = sh_eth_close(ndev);
3170 }
3171
3172 return ret;
3173}
3174
3175static int sh_eth_resume(struct device *dev)
3176{
3177 struct net_device *ndev = dev_get_drvdata(dev);
3178 int ret = 0;
3179
3180 if (netif_running(ndev)) {
3181 ret = sh_eth_open(ndev);
3182 if (ret < 0)
3183 return ret;
3184 netif_device_attach(ndev);
3185 }
3186
3187 return ret;
3188}
3189#endif
3190
bcd5149d
MD		 3191static int sh_eth_runtime_nop(struct device *dev)
3192{
128296fc 3193 /* Runtime PM callback shared between ->runtime_suspend()
bcd5149d
MD		 3194 * and ->runtime_resume(). Simply returns success.
3195 *
3196 * This driver re-initializes all registers after
3197 * pm_runtime_get_sync() anyway so there is no need
3198 * to save and restore registers here.
3199 */
3200 return 0;
3201}
3202
540ad1b8 3203static const struct dev_pm_ops sh_eth_dev_pm_ops = {
b71af046 3204 SET_SYSTEM_SLEEP_PM_OPS(sh_eth_suspend, sh_eth_resume)
e7d7e898 3205 SET_RUNTIME_PM_OPS(sh_eth_runtime_nop, sh_eth_runtime_nop, NULL)
bcd5149d 3206};
540ad1b8
NI		 3207#define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
3208#else
3209#define SH_ETH_PM_OPS NULL
3210#endif
bcd5149d 3211
afe391ad 3212static struct platform_device_id sh_eth_id_table[] = {
c18a79ab 3213 { "sh7619-ether", (kernel_ulong_t)&sh7619_data },
7bbe150d 3214 { "sh771x-ether", (kernel_ulong_t)&sh771x_data },
9c3beaab 3215 { "sh7724-ether", (kernel_ulong_t)&sh7724_data },
f5d12767 3216 { "sh7734-gether", (kernel_ulong_t)&sh7734_data },
24549e2a
SS		 3217 { "sh7757-ether", (kernel_ulong_t)&sh7757_data },
3218 { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga },
f5d12767 3219 { "sh7763-gether", (kernel_ulong_t)&sh7763_data },
afe391ad
SS		 3220 { }
3221};
3222MODULE_DEVICE_TABLE(platform, sh_eth_id_table);
3223
86a74ff2
NI		 3224static struct platform_driver sh_eth_driver = {
3225 .probe = sh_eth_drv_probe,
3226 .remove = sh_eth_drv_remove,
afe391ad 3227 .id_table = sh_eth_id_table,
86a74ff2
NI		 3228 .driver = {
3229 .name = CARDNAME,
540ad1b8 3230 .pm = SH_ETH_PM_OPS,
b356e978 3231 .of_match_table = of_match_ptr(sh_eth_match_table),
86a74ff2
NI		 3232 },
3233};
3234
db62f684 3235module_platform_driver(sh_eth_driver);
86a74ff2
NI		 3236
3237MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
3238MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
3239MODULE_LICENSE("GPL v2");
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