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net: fix IP early demux races
[mirror_ubuntu-zesty-kernel.git] / drivers / net / ethernet / renesas / sh_eth.c
CommitLineData
128296fc 1/* SuperH Ethernet device driver
86a74ff2 2 *
966d6dbb 3 * Copyright (C) 2014 Renesas Electronics Corporation
f0e81fec 4 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu
b356e978
SS		 5 * Copyright (C) 2008-2014 Renesas Solutions Corp.
6 * Copyright (C) 2013-2014 Cogent Embedded, Inc.
702eca02 7 * Copyright (C) 2014 Codethink Limited
86a74ff2
NI		 8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms and conditions of the GNU General Public License,
11 * version 2, as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
86a74ff2
NI		 17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 */
21
0654011d
YS		 22#include <linux/module.h>
23#include <linux/kernel.h>
24#include <linux/spinlock.h>
6a27cded 25#include <linux/interrupt.h>
86a74ff2
NI		 26#include <linux/dma-mapping.h>
27#include <linux/etherdevice.h>
28#include <linux/delay.h>
29#include <linux/platform_device.h>
30#include <linux/mdio-bitbang.h>
31#include <linux/netdevice.h>
b356e978
SS		 32#include <linux/of.h>
33#include <linux/of_device.h>
34#include <linux/of_irq.h>
35#include <linux/of_net.h>
86a74ff2
NI		 36#include <linux/phy.h>
37#include <linux/cache.h>
38#include <linux/io.h>
bcd5149d 39#include <linux/pm_runtime.h>
5a0e3ad6 40#include <linux/slab.h>
dc19e4e5 41#include <linux/ethtool.h>
fdb37a7f 42#include <linux/if_vlan.h>
f0e81fec 43#include <linux/clk.h>
d4fa0e35 44#include <linux/sh_eth.h>
702eca02 45#include <linux/of_mdio.h>
86a74ff2
NI		 46
47#include "sh_eth.h"
48
dc19e4e5
NI		 49#define SH_ETH_DEF_MSG_ENABLE \
50 (NETIF_MSG_LINK | \
51 NETIF_MSG_TIMER | \
52 NETIF_MSG_RX_ERR| \
53 NETIF_MSG_TX_ERR)
54
2274d375
SS		 55#define SH_ETH_OFFSET_INVALID ((u16)~0)
56
3365711d
BH		 57#define SH_ETH_OFFSET_DEFAULTS \
58 [0 ... SH_ETH_MAX_REGISTER_OFFSET - 1] = SH_ETH_OFFSET_INVALID
59
c0013f6f 60static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
3365711d
BH		 61 SH_ETH_OFFSET_DEFAULTS,
62
c0013f6f
SS		 63 [EDSR] = 0x0000,
64 [EDMR] = 0x0400,
65 [EDTRR] = 0x0408,
66 [EDRRR] = 0x0410,
67 [EESR] = 0x0428,
68 [EESIPR] = 0x0430,
69 [TDLAR] = 0x0010,
70 [TDFAR] = 0x0014,
71 [TDFXR] = 0x0018,
72 [TDFFR] = 0x001c,
73 [RDLAR] = 0x0030,
74 [RDFAR] = 0x0034,
75 [RDFXR] = 0x0038,
76 [RDFFR] = 0x003c,
77 [TRSCER] = 0x0438,
78 [RMFCR] = 0x0440,
79 [TFTR] = 0x0448,
80 [FDR] = 0x0450,
81 [RMCR] = 0x0458,
82 [RPADIR] = 0x0460,
83 [FCFTR] = 0x0468,
84 [CSMR] = 0x04E4,
85
86 [ECMR] = 0x0500,
87 [ECSR] = 0x0510,
88 [ECSIPR] = 0x0518,
89 [PIR] = 0x0520,
90 [PSR] = 0x0528,
91 [PIPR] = 0x052c,
92 [RFLR] = 0x0508,
93 [APR] = 0x0554,
94 [MPR] = 0x0558,
95 [PFTCR] = 0x055c,
96 [PFRCR] = 0x0560,
97 [TPAUSER] = 0x0564,
98 [GECMR] = 0x05b0,
99 [BCULR] = 0x05b4,
100 [MAHR] = 0x05c0,
101 [MALR] = 0x05c8,
102 [TROCR] = 0x0700,
103 [CDCR] = 0x0708,
104 [LCCR] = 0x0710,
105 [CEFCR] = 0x0740,
106 [FRECR] = 0x0748,
107 [TSFRCR] = 0x0750,
108 [TLFRCR] = 0x0758,
109 [RFCR] = 0x0760,
110 [CERCR] = 0x0768,
111 [CEECR] = 0x0770,
112 [MAFCR] = 0x0778,
113 [RMII_MII] = 0x0790,
114
115 [ARSTR] = 0x0000,
116 [TSU_CTRST] = 0x0004,
117 [TSU_FWEN0] = 0x0010,
118 [TSU_FWEN1] = 0x0014,
119 [TSU_FCM] = 0x0018,
120 [TSU_BSYSL0] = 0x0020,
121 [TSU_BSYSL1] = 0x0024,
122 [TSU_PRISL0] = 0x0028,
123 [TSU_PRISL1] = 0x002c,
124 [TSU_FWSL0] = 0x0030,
125 [TSU_FWSL1] = 0x0034,
126 [TSU_FWSLC] = 0x0038,
127 [TSU_QTAG0] = 0x0040,
128 [TSU_QTAG1] = 0x0044,
129 [TSU_FWSR] = 0x0050,
130 [TSU_FWINMK] = 0x0054,
131 [TSU_ADQT0] = 0x0048,
132 [TSU_ADQT1] = 0x004c,
133 [TSU_VTAG0] = 0x0058,
134 [TSU_VTAG1] = 0x005c,
135 [TSU_ADSBSY] = 0x0060,
136 [TSU_TEN] = 0x0064,
137 [TSU_POST1] = 0x0070,
138 [TSU_POST2] = 0x0074,
139 [TSU_POST3] = 0x0078,
140 [TSU_POST4] = 0x007c,
141 [TSU_ADRH0] = 0x0100,
c0013f6f
SS		 142
143 [TXNLCR0] = 0x0080,
144 [TXALCR0] = 0x0084,
145 [RXNLCR0] = 0x0088,
146 [RXALCR0] = 0x008c,
147 [FWNLCR0] = 0x0090,
148 [FWALCR0] = 0x0094,
149 [TXNLCR1] = 0x00a0,
150 [TXALCR1] = 0x00a0,
151 [RXNLCR1] = 0x00a8,
152 [RXALCR1] = 0x00ac,
153 [FWNLCR1] = 0x00b0,
154 [FWALCR1] = 0x00b4,
155};
156
db893473 157static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
3365711d
BH		 158 SH_ETH_OFFSET_DEFAULTS,
159
db893473
SH		 160 [EDSR] = 0x0000,
161 [EDMR] = 0x0400,
162 [EDTRR] = 0x0408,
163 [EDRRR] = 0x0410,
164 [EESR] = 0x0428,
165 [EESIPR] = 0x0430,
166 [TDLAR] = 0x0010,
167 [TDFAR] = 0x0014,
168 [TDFXR] = 0x0018,
169 [TDFFR] = 0x001c,
170 [RDLAR] = 0x0030,
171 [RDFAR] = 0x0034,
172 [RDFXR] = 0x0038,
173 [RDFFR] = 0x003c,
174 [TRSCER] = 0x0438,
175 [RMFCR] = 0x0440,
176 [TFTR] = 0x0448,
177 [FDR] = 0x0450,
178 [RMCR] = 0x0458,
179 [RPADIR] = 0x0460,
180 [FCFTR] = 0x0468,
181 [CSMR] = 0x04E4,
182
183 [ECMR] = 0x0500,
184 [RFLR] = 0x0508,
185 [ECSR] = 0x0510,
186 [ECSIPR] = 0x0518,
187 [PIR] = 0x0520,
188 [APR] = 0x0554,
189 [MPR] = 0x0558,
190 [PFTCR] = 0x055c,
191 [PFRCR] = 0x0560,
192 [TPAUSER] = 0x0564,
193 [MAHR] = 0x05c0,
194 [MALR] = 0x05c8,
195 [CEFCR] = 0x0740,
196 [FRECR] = 0x0748,
197 [TSFRCR] = 0x0750,
198 [TLFRCR] = 0x0758,
199 [RFCR] = 0x0760,
200 [MAFCR] = 0x0778,
201
202 [ARSTR] = 0x0000,
203 [TSU_CTRST] = 0x0004,
204 [TSU_VTAG0] = 0x0058,
205 [TSU_ADSBSY] = 0x0060,
206 [TSU_TEN] = 0x0064,
207 [TSU_ADRH0] = 0x0100,
db893473
SH		 208
209 [TXNLCR0] = 0x0080,
210 [TXALCR0] = 0x0084,
211 [RXNLCR0] = 0x0088,
212 [RXALCR0] = 0x008C,
213};
214
a3f109bd 215static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
3365711d
BH		 216 SH_ETH_OFFSET_DEFAULTS,
217
a3f109bd
SS		 218 [ECMR] = 0x0300,
219 [RFLR] = 0x0308,
220 [ECSR] = 0x0310,
221 [ECSIPR] = 0x0318,
222 [PIR] = 0x0320,
223 [PSR] = 0x0328,
224 [RDMLR] = 0x0340,
225 [IPGR] = 0x0350,
226 [APR] = 0x0354,
227 [MPR] = 0x0358,
228 [RFCF] = 0x0360,
229 [TPAUSER] = 0x0364,
230 [TPAUSECR] = 0x0368,
231 [MAHR] = 0x03c0,
232 [MALR] = 0x03c8,
233 [TROCR] = 0x03d0,
234 [CDCR] = 0x03d4,
235 [LCCR] = 0x03d8,
236 [CNDCR] = 0x03dc,
237 [CEFCR] = 0x03e4,
238 [FRECR] = 0x03e8,
239 [TSFRCR] = 0x03ec,
240 [TLFRCR] = 0x03f0,
241 [RFCR] = 0x03f4,
242 [MAFCR] = 0x03f8,
243
244 [EDMR] = 0x0200,
245 [EDTRR] = 0x0208,
246 [EDRRR] = 0x0210,
247 [TDLAR] = 0x0218,
248 [RDLAR] = 0x0220,
249 [EESR] = 0x0228,
250 [EESIPR] = 0x0230,
251 [TRSCER] = 0x0238,
252 [RMFCR] = 0x0240,
253 [TFTR] = 0x0248,
254 [FDR] = 0x0250,
255 [RMCR] = 0x0258,
256 [TFUCR] = 0x0264,
257 [RFOCR] = 0x0268,
55754f19 258 [RMIIMODE] = 0x026c,
a3f109bd
SS		 259 [FCFTR] = 0x0270,
260 [TRIMD] = 0x027c,
261};
262
c0013f6f 263static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
3365711d
BH		 264 SH_ETH_OFFSET_DEFAULTS,
265
c0013f6f
SS		 266 [ECMR] = 0x0100,
267 [RFLR] = 0x0108,
268 [ECSR] = 0x0110,
269 [ECSIPR] = 0x0118,
270 [PIR] = 0x0120,
271 [PSR] = 0x0128,
272 [RDMLR] = 0x0140,
273 [IPGR] = 0x0150,
274 [APR] = 0x0154,
275 [MPR] = 0x0158,
276 [TPAUSER] = 0x0164,
277 [RFCF] = 0x0160,
278 [TPAUSECR] = 0x0168,
279 [BCFRR] = 0x016c,
280 [MAHR] = 0x01c0,
281 [MALR] = 0x01c8,
282 [TROCR] = 0x01d0,
283 [CDCR] = 0x01d4,
284 [LCCR] = 0x01d8,
285 [CNDCR] = 0x01dc,
286 [CEFCR] = 0x01e4,
287 [FRECR] = 0x01e8,
288 [TSFRCR] = 0x01ec,
289 [TLFRCR] = 0x01f0,
290 [RFCR] = 0x01f4,
291 [MAFCR] = 0x01f8,
292 [RTRATE] = 0x01fc,
293
294 [EDMR] = 0x0000,
295 [EDTRR] = 0x0008,
296 [EDRRR] = 0x0010,
297 [TDLAR] = 0x0018,
298 [RDLAR] = 0x0020,
299 [EESR] = 0x0028,
300 [EESIPR] = 0x0030,
301 [TRSCER] = 0x0038,
302 [RMFCR] = 0x0040,
303 [TFTR] = 0x0048,
304 [FDR] = 0x0050,
305 [RMCR] = 0x0058,
306 [TFUCR] = 0x0064,
307 [RFOCR] = 0x0068,
308 [FCFTR] = 0x0070,
309 [RPADIR] = 0x0078,
310 [TRIMD] = 0x007c,
311 [RBWAR] = 0x00c8,
312 [RDFAR] = 0x00cc,
313 [TBRAR] = 0x00d4,
314 [TDFAR] = 0x00d8,
315};
316
317static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
3365711d
BH		 318 SH_ETH_OFFSET_DEFAULTS,
319
d8b0426a
SS		 320 [EDMR] = 0x0000,
321 [EDTRR] = 0x0004,
322 [EDRRR] = 0x0008,
323 [TDLAR] = 0x000c,
324 [RDLAR] = 0x0010,
325 [EESR] = 0x0014,
326 [EESIPR] = 0x0018,
327 [TRSCER] = 0x001c,
328 [RMFCR] = 0x0020,
329 [TFTR] = 0x0024,
330 [FDR] = 0x0028,
331 [RMCR] = 0x002c,
332 [EDOCR] = 0x0030,
333 [FCFTR] = 0x0034,
334 [RPADIR] = 0x0038,
335 [TRIMD] = 0x003c,
336 [RBWAR] = 0x0040,
337 [RDFAR] = 0x0044,
338 [TBRAR] = 0x004c,
339 [TDFAR] = 0x0050,
340
c0013f6f
SS		 341 [ECMR] = 0x0160,
342 [ECSR] = 0x0164,
343 [ECSIPR] = 0x0168,
344 [PIR] = 0x016c,
345 [MAHR] = 0x0170,
346 [MALR] = 0x0174,
347 [RFLR] = 0x0178,
348 [PSR] = 0x017c,
349 [TROCR] = 0x0180,
350 [CDCR] = 0x0184,
351 [LCCR] = 0x0188,
352 [CNDCR] = 0x018c,
353 [CEFCR] = 0x0194,
354 [FRECR] = 0x0198,
355 [TSFRCR] = 0x019c,
356 [TLFRCR] = 0x01a0,
357 [RFCR] = 0x01a4,
358 [MAFCR] = 0x01a8,
359 [IPGR] = 0x01b4,
360 [APR] = 0x01b8,
361 [MPR] = 0x01bc,
362 [TPAUSER] = 0x01c4,
363 [BCFR] = 0x01cc,
364
365 [ARSTR] = 0x0000,
366 [TSU_CTRST] = 0x0004,
367 [TSU_FWEN0] = 0x0010,
368 [TSU_FWEN1] = 0x0014,
369 [TSU_FCM] = 0x0018,
370 [TSU_BSYSL0] = 0x0020,
371 [TSU_BSYSL1] = 0x0024,
372 [TSU_PRISL0] = 0x0028,
373 [TSU_PRISL1] = 0x002c,
374 [TSU_FWSL0] = 0x0030,
375 [TSU_FWSL1] = 0x0034,
376 [TSU_FWSLC] = 0x0038,
377 [TSU_QTAGM0] = 0x0040,
378 [TSU_QTAGM1] = 0x0044,
379 [TSU_ADQT0] = 0x0048,
380 [TSU_ADQT1] = 0x004c,
381 [TSU_FWSR] = 0x0050,
382 [TSU_FWINMK] = 0x0054,
383 [TSU_ADSBSY] = 0x0060,
384 [TSU_TEN] = 0x0064,
385 [TSU_POST1] = 0x0070,
386 [TSU_POST2] = 0x0074,
387 [TSU_POST3] = 0x0078,
388 [TSU_POST4] = 0x007c,
389
390 [TXNLCR0] = 0x0080,
391 [TXALCR0] = 0x0084,
392 [RXNLCR0] = 0x0088,
393 [RXALCR0] = 0x008c,
394 [FWNLCR0] = 0x0090,
395 [FWALCR0] = 0x0094,
396 [TXNLCR1] = 0x00a0,
397 [TXALCR1] = 0x00a0,
398 [RXNLCR1] = 0x00a8,
399 [RXALCR1] = 0x00ac,
400 [FWNLCR1] = 0x00b0,
401 [FWALCR1] = 0x00b4,
402
403 [TSU_ADRH0] = 0x0100,
c0013f6f
SS		 404};
405
740c7f31
BH		 406static void sh_eth_rcv_snd_disable(struct net_device *ndev);
407static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev);
408
2274d375
SS		 409static void sh_eth_write(struct net_device *ndev, u32 data, int enum_index)
410{
411 struct sh_eth_private *mdp = netdev_priv(ndev);
412 u16 offset = mdp->reg_offset[enum_index];
413
414 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
415 return;
416
417 iowrite32(data, mdp->addr + offset);
418}
419
420static u32 sh_eth_read(struct net_device *ndev, int enum_index)
421{
422 struct sh_eth_private *mdp = netdev_priv(ndev);
423 u16 offset = mdp->reg_offset[enum_index];
424
425 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
426 return ~0U;
427
428 return ioread32(mdp->addr + offset);
429}
430
504c8ca5 431static bool sh_eth_is_gether(struct sh_eth_private *mdp)
dabdde9e 432{
504c8ca5 433 return mdp->reg_offset == sh_eth_offset_gigabit;
dabdde9e
NI		 434}
435
db893473
SH		 436static bool sh_eth_is_rz_fast_ether(struct sh_eth_private *mdp)
437{
438 return mdp->reg_offset == sh_eth_offset_fast_rz;
439}
440
8e994402 441static void sh_eth_select_mii(struct net_device *ndev)
5e7a76be
NI		 442{
443 u32 value = 0x0;
444 struct sh_eth_private *mdp = netdev_priv(ndev);
445
446 switch (mdp->phy_interface) {
447 case PHY_INTERFACE_MODE_GMII:
448 value = 0x2;
449 break;
450 case PHY_INTERFACE_MODE_MII:
451 value = 0x1;
452 break;
453 case PHY_INTERFACE_MODE_RMII:
454 value = 0x0;
455 break;
456 default:
f75f14ec
SS		 457 netdev_warn(ndev,
458 "PHY interface mode was not setup. Set to MII.\n");
5e7a76be
NI		 459 value = 0x1;
460 break;
461 }
462
463 sh_eth_write(ndev, value, RMII_MII);
464}
5e7a76be 465
8e994402 466static void sh_eth_set_duplex(struct net_device *ndev)
65ac8851
YS		 467{
468 struct sh_eth_private *mdp = netdev_priv(ndev);
65ac8851
YS		 469
470 if (mdp->duplex) /* Full */
4a55530f 471 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
65ac8851 472 else /* Half */
4a55530f 473 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
65ac8851
YS		 474}
475
04b0ed2a 476/* There is CPU dependent code */
589ebdef 477static void sh_eth_set_rate_r8a777x(struct net_device *ndev)
65ac8851
YS		 478{
479 struct sh_eth_private *mdp = netdev_priv(ndev);
d0418bb7 480
a3f109bd
SS		 481 switch (mdp->speed) {
482 case 10: /* 10BASE */
483 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_ELB, ECMR);
484 break;
485 case 100:/* 100BASE */
486 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_ELB, ECMR);
487 break;
488 default:
489 break;
490 }
491}
492
674853b2 493/* R8A7778/9 */
589ebdef 494static struct sh_eth_cpu_data r8a777x_data = {
a3f109bd 495 .set_duplex = sh_eth_set_duplex,
589ebdef 496 .set_rate = sh_eth_set_rate_r8a777x,
a3f109bd 497
a3153d8c
SS		 498 .register_type = SH_ETH_REG_FAST_RCAR,
499
a3f109bd
SS		 500 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
501 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
502 .eesipr_value = 0x01ff009f,
503
504 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
ca8c3585
SS		 505 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
506 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
507 EESR_ECI,
d407bc02 508 .fdr_value = 0x00000f0f,
a3f109bd
SS		 509
510 .apr = 1,
511 .mpr = 1,
512 .tpauser = 1,
513 .hw_swap = 1,
514};
a3f109bd 515
94a12b15
SS		 516/* R8A7790/1 */
517static struct sh_eth_cpu_data r8a779x_data = {
e18dbf7e
SH		 518 .set_duplex = sh_eth_set_duplex,
519 .set_rate = sh_eth_set_rate_r8a777x,
520
a3153d8c
SS		 521 .register_type = SH_ETH_REG_FAST_RCAR,
522
e18dbf7e
SH		 523 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
524 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
525 .eesipr_value = 0x01ff009f,
526
527 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
ba361cb3
LP		 528 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
529 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
530 EESR_ECI,
d407bc02 531 .fdr_value = 0x00000f0f,
e18dbf7e 532
01fbd3f5
GU		 533 .trscer_err_mask = DESC_I_RINT8,
534
e18dbf7e
SH		 535 .apr = 1,
536 .mpr = 1,
537 .tpauser = 1,
538 .hw_swap = 1,
539 .rmiimode = 1,
540};
541
9c3beaab 542static void sh_eth_set_rate_sh7724(struct net_device *ndev)
a3f109bd
SS		 543{
544 struct sh_eth_private *mdp = netdev_priv(ndev);
65ac8851
YS		 545
546 switch (mdp->speed) {
547 case 10: /* 10BASE */
a3f109bd 548 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_RTM, ECMR);
65ac8851
YS		 549 break;
550 case 100:/* 100BASE */
a3f109bd 551 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_RTM, ECMR);
65ac8851
YS		 552 break;
553 default:
554 break;
555 }
556}
557
558/* SH7724 */
9c3beaab 559static struct sh_eth_cpu_data sh7724_data = {
65ac8851 560 .set_duplex = sh_eth_set_duplex,
9c3beaab 561 .set_rate = sh_eth_set_rate_sh7724,
65ac8851 562
a3153d8c
SS		 563 .register_type = SH_ETH_REG_FAST_SH4,
564
65ac8851
YS		 565 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
566 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
a80c3de7 567 .eesipr_value = 0x01ff009f,
65ac8851
YS		 568
569 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
ca8c3585
SS		 570 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
571 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
572 EESR_ECI,
65ac8851
YS		 573
574 .apr = 1,
575 .mpr = 1,
576 .tpauser = 1,
577 .hw_swap = 1,
503914cf
MD		 578 .rpadir = 1,
579 .rpadir_value = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
65ac8851 580};
5cee1d37 581
24549e2a 582static void sh_eth_set_rate_sh7757(struct net_device *ndev)
f29a3d04
YS		 583{
584 struct sh_eth_private *mdp = netdev_priv(ndev);
f29a3d04
YS		 585
586 switch (mdp->speed) {
587 case 10: /* 10BASE */
4a55530f 588 sh_eth_write(ndev, 0, RTRATE);
f29a3d04
YS		 589 break;
590 case 100:/* 100BASE */
4a55530f 591 sh_eth_write(ndev, 1, RTRATE);
f29a3d04
YS		 592 break;
593 default:
594 break;
595 }
596}
597
598/* SH7757 */
24549e2a
SS		 599static struct sh_eth_cpu_data sh7757_data = {
600 .set_duplex = sh_eth_set_duplex,
601 .set_rate = sh_eth_set_rate_sh7757,
f29a3d04 602
a3153d8c
SS		 603 .register_type = SH_ETH_REG_FAST_SH4,
604
f29a3d04 605 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
f29a3d04
YS		 606
607 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
ca8c3585
SS		 608 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
609 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
610 EESR_ECI,
f29a3d04 611
5b3dfd13 612 .irq_flags = IRQF_SHARED,
f29a3d04
YS		 613 .apr = 1,
614 .mpr = 1,
615 .tpauser = 1,
616 .hw_swap = 1,
617 .no_ade = 1,
2e98e797
YS		 618 .rpadir = 1,
619 .rpadir_value = 2 << 16,
6b4b4fea 620 .rtrate = 1,
f29a3d04 621};
65ac8851 622
e403d295 623#define SH_GIGA_ETH_BASE 0xfee00000UL
8fcd4961
YS		 624#define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
625#define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
626static void sh_eth_chip_reset_giga(struct net_device *ndev)
627{
628 int i;
0799c2d6 629 u32 mahr[2], malr[2];
8fcd4961
YS		 630
631 /* save MAHR and MALR */
632 for (i = 0; i < 2; i++) {
ae70644d
YS		 633 malr[i] = ioread32((void *)GIGA_MALR(i));
634 mahr[i] = ioread32((void *)GIGA_MAHR(i));
8fcd4961
YS		 635 }
636
637 /* reset device */
ae70644d 638 iowrite32(ARSTR_ARSTR, (void *)(SH_GIGA_ETH_BASE + 0x1800));
8fcd4961
YS		 639 mdelay(1);
640
641 /* restore MAHR and MALR */
642 for (i = 0; i < 2; i++) {
ae70644d
YS		 643 iowrite32(malr[i], (void *)GIGA_MALR(i));
644 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
8fcd4961
YS		 645 }
646}
647
8fcd4961
YS		 648static void sh_eth_set_rate_giga(struct net_device *ndev)
649{
650 struct sh_eth_private *mdp = netdev_priv(ndev);
651
652 switch (mdp->speed) {
653 case 10: /* 10BASE */
654 sh_eth_write(ndev, 0x00000000, GECMR);
655 break;
656 case 100:/* 100BASE */
657 sh_eth_write(ndev, 0x00000010, GECMR);
658 break;
659 case 1000: /* 1000BASE */
660 sh_eth_write(ndev, 0x00000020, GECMR);
661 break;
662 default:
663 break;
664 }
665}
666
667/* SH7757(GETHERC) */
24549e2a 668static struct sh_eth_cpu_data sh7757_data_giga = {
8fcd4961 669 .chip_reset = sh_eth_chip_reset_giga,
04b0ed2a 670 .set_duplex = sh_eth_set_duplex,
8fcd4961
YS		 671 .set_rate = sh_eth_set_rate_giga,
672
a3153d8c
SS		 673 .register_type = SH_ETH_REG_GIGABIT,
674
8fcd4961
YS		 675 .ecsr_value = ECSR_ICD | ECSR_MPD,
676 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
677 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
678
679 .tx_check = EESR_TC1 | EESR_FTC,
ca8c3585
SS		 680 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
681 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
682 EESR_TDE | EESR_ECI,
8fcd4961 683 .fdr_value = 0x0000072f,
8fcd4961 684
5b3dfd13 685 .irq_flags = IRQF_SHARED,
8fcd4961
YS		 686 .apr = 1,
687 .mpr = 1,
688 .tpauser = 1,
689 .bculr = 1,
690 .hw_swap = 1,
691 .rpadir = 1,
692 .rpadir_value = 2 << 16,
693 .no_trimd = 1,
694 .no_ade = 1,
3acbc971 695 .tsu = 1,
8fcd4961
YS		 696};
697
380af9e3
YS		 698static void sh_eth_chip_reset(struct net_device *ndev)
699{
4986b996
YS		 700 struct sh_eth_private *mdp = netdev_priv(ndev);
701
380af9e3 702 /* reset device */
4986b996 703 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
380af9e3
YS		 704 mdelay(1);
705}
706
f5d12767 707static void sh_eth_set_rate_gether(struct net_device *ndev)
380af9e3
YS		 708{
709 struct sh_eth_private *mdp = netdev_priv(ndev);
380af9e3
YS		 710
711 switch (mdp->speed) {
712 case 10: /* 10BASE */
4a55530f 713 sh_eth_write(ndev, GECMR_10, GECMR);
380af9e3
YS		 714 break;
715 case 100:/* 100BASE */
4a55530f 716 sh_eth_write(ndev, GECMR_100, GECMR);
380af9e3
YS		 717 break;
718 case 1000: /* 1000BASE */
4a55530f 719 sh_eth_write(ndev, GECMR_1000, GECMR);
380af9e3
YS		 720 break;
721 default:
722 break;
723 }
724}
725
f5d12767
SS		 726/* SH7734 */
727static struct sh_eth_cpu_data sh7734_data = {
380af9e3
YS		 728 .chip_reset = sh_eth_chip_reset,
729 .set_duplex = sh_eth_set_duplex,
f5d12767
SS		 730 .set_rate = sh_eth_set_rate_gether,
731
a3153d8c
SS		 732 .register_type = SH_ETH_REG_GIGABIT,
733
f5d12767
SS		 734 .ecsr_value = ECSR_ICD | ECSR_MPD,
735 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
736 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
737
738 .tx_check = EESR_TC1 | EESR_FTC,
ca8c3585
SS		 739 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
740 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
741 EESR_TDE | EESR_ECI,
f5d12767
SS		 742
743 .apr = 1,
744 .mpr = 1,
745 .tpauser = 1,
746 .bculr = 1,
747 .hw_swap = 1,
748 .no_trimd = 1,
749 .no_ade = 1,
750 .tsu = 1,
751 .hw_crc = 1,
752 .select_mii = 1,
753};
754
755/* SH7763 */
756static struct sh_eth_cpu_data sh7763_data = {
757 .chip_reset = sh_eth_chip_reset,
758 .set_duplex = sh_eth_set_duplex,
759 .set_rate = sh_eth_set_rate_gether,
380af9e3 760
a3153d8c
SS		 761 .register_type = SH_ETH_REG_GIGABIT,
762
380af9e3
YS		 763 .ecsr_value = ECSR_ICD | ECSR_MPD,
764 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
765 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
766
767 .tx_check = EESR_TC1 | EESR_FTC,
128296fc
SS		 768 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
769 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
380af9e3 770 EESR_ECI,
380af9e3
YS		 771
772 .apr = 1,
773 .mpr = 1,
774 .tpauser = 1,
775 .bculr = 1,
776 .hw_swap = 1,
380af9e3
YS		 777 .no_trimd = 1,
778 .no_ade = 1,
4986b996 779 .tsu = 1,
5b3dfd13 780 .irq_flags = IRQF_SHARED,
380af9e3
YS		 781};
782
e5c9b4cd 783static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
73a0d907
YS		 784{
785 struct sh_eth_private *mdp = netdev_priv(ndev);
73a0d907
YS		 786
787 /* reset device */
788 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
789 mdelay(1);
790
5e7a76be 791 sh_eth_select_mii(ndev);
73a0d907
YS		 792}
793
73a0d907 794/* R8A7740 */
e5c9b4cd
SS		 795static struct sh_eth_cpu_data r8a7740_data = {
796 .chip_reset = sh_eth_chip_reset_r8a7740,
73a0d907 797 .set_duplex = sh_eth_set_duplex,
e5c9b4cd 798 .set_rate = sh_eth_set_rate_gether,
73a0d907 799
a3153d8c
SS		 800 .register_type = SH_ETH_REG_GIGABIT,
801
73a0d907
YS		 802 .ecsr_value = ECSR_ICD | ECSR_MPD,
803 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
804 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
805
806 .tx_check = EESR_TC1 | EESR_FTC,
ca8c3585
SS		 807 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
808 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
809 EESR_TDE | EESR_ECI,
cc23528d 810 .fdr_value = 0x0000070f,
73a0d907
YS		 811
812 .apr = 1,
813 .mpr = 1,
814 .tpauser = 1,
815 .bculr = 1,
816 .hw_swap = 1,
cc23528d
SH		 817 .rpadir = 1,
818 .rpadir_value = 2 << 16,
73a0d907
YS		 819 .no_trimd = 1,
820 .no_ade = 1,
821 .tsu = 1,
5e7a76be 822 .select_mii = 1,
ac8025a6 823 .shift_rd0 = 1,
73a0d907
YS		 824};
825
db893473
SH		 826/* R7S72100 */
827static struct sh_eth_cpu_data r7s72100_data = {
828 .chip_reset = sh_eth_chip_reset,
829 .set_duplex = sh_eth_set_duplex,
830
831 .register_type = SH_ETH_REG_FAST_RZ,
832
833 .ecsr_value = ECSR_ICD,
834 .ecsipr_value = ECSIPR_ICDIP,
835 .eesipr_value = 0xff7f009f,
836
837 .tx_check = EESR_TC1 | EESR_FTC,
838 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
839 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
840 EESR_TDE | EESR_ECI,
841 .fdr_value = 0x0000070f,
db893473
SH		 842
843 .no_psr = 1,
844 .apr = 1,
845 .mpr = 1,
846 .tpauser = 1,
847 .hw_swap = 1,
848 .rpadir = 1,
849 .rpadir_value = 2 << 16,
850 .no_trimd = 1,
851 .no_ade = 1,
852 .hw_crc = 1,
853 .tsu = 1,
854 .shift_rd0 = 1,
855};
856
c18a79ab 857static struct sh_eth_cpu_data sh7619_data = {
a3153d8c
SS		 858 .register_type = SH_ETH_REG_FAST_SH3_SH2,
859
380af9e3
YS		 860 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
861
862 .apr = 1,
863 .mpr = 1,
864 .tpauser = 1,
865 .hw_swap = 1,
866};
7bbe150d
SS		 867
868static struct sh_eth_cpu_data sh771x_data = {
a3153d8c
SS		 869 .register_type = SH_ETH_REG_FAST_SH3_SH2,
870
380af9e3 871 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
4986b996 872 .tsu = 1,
380af9e3 873};
380af9e3
YS		 874
875static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
876{
877 if (!cd->ecsr_value)
878 cd->ecsr_value = DEFAULT_ECSR_INIT;
879
880 if (!cd->ecsipr_value)
881 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
882
883 if (!cd->fcftr_value)
128296fc 884 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF |
380af9e3
YS		 885 DEFAULT_FIFO_F_D_RFD;
886
887 if (!cd->fdr_value)
888 cd->fdr_value = DEFAULT_FDR_INIT;
889
380af9e3
YS		 890 if (!cd->tx_check)
891 cd->tx_check = DEFAULT_TX_CHECK;
892
893 if (!cd->eesr_err_check)
894 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
b284fbe3
NI		 895
896 if (!cd->trscer_err_mask)
897 cd->trscer_err_mask = DEFAULT_TRSCER_ERR_MASK;
380af9e3
YS		 898}
899
5cee1d37
NI		 900static int sh_eth_check_reset(struct net_device *ndev)
901{
902 int ret = 0;
903 int cnt = 100;
904
905 while (cnt > 0) {
906 if (!(sh_eth_read(ndev, EDMR) & 0x3))
907 break;
908 mdelay(1);
909 cnt--;
910 }
9f8c4265 911 if (cnt <= 0) {
f75f14ec 912 netdev_err(ndev, "Device reset failed\n");
5cee1d37
NI		 913 ret = -ETIMEDOUT;
914 }
915 return ret;
380af9e3 916}
dabdde9e
NI		 917
918static int sh_eth_reset(struct net_device *ndev)
919{
920 struct sh_eth_private *mdp = netdev_priv(ndev);
921 int ret = 0;
922
db893473 923 if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp)) {
dabdde9e
NI		 924 sh_eth_write(ndev, EDSR_ENALL, EDSR);
925 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER,
926 EDMR);
927
928 ret = sh_eth_check_reset(ndev);
929 if (ret)
f738a13d 930 return ret;
dabdde9e
NI		 931
932 /* Table Init */
933 sh_eth_write(ndev, 0x0, TDLAR);
934 sh_eth_write(ndev, 0x0, TDFAR);
935 sh_eth_write(ndev, 0x0, TDFXR);
936 sh_eth_write(ndev, 0x0, TDFFR);
937 sh_eth_write(ndev, 0x0, RDLAR);
938 sh_eth_write(ndev, 0x0, RDFAR);
939 sh_eth_write(ndev, 0x0, RDFXR);
940 sh_eth_write(ndev, 0x0, RDFFR);
941
942 /* Reset HW CRC register */
943 if (mdp->cd->hw_crc)
944 sh_eth_write(ndev, 0x0, CSMR);
945
946 /* Select MII mode */
947 if (mdp->cd->select_mii)
948 sh_eth_select_mii(ndev);
949 } else {
950 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER,
951 EDMR);
952 mdelay(3);
953 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER,
954 EDMR);
955 }
956
dabdde9e
NI		 957 return ret;
958}
380af9e3 959
380af9e3
YS		 960static void sh_eth_set_receive_align(struct sk_buff *skb)
961{
4d6a949c 962 uintptr_t reserve = (uintptr_t)skb->data & (SH_ETH_RX_ALIGN - 1);
380af9e3 963
380af9e3 964 if (reserve)
4d6a949c 965 skb_reserve(skb, SH_ETH_RX_ALIGN - reserve);
380af9e3 966}
380af9e3
YS		 967
968
71557a37
YS		 969/* CPU <-> EDMAC endian convert */
970static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x)
971{
972 switch (mdp->edmac_endian) {
973 case EDMAC_LITTLE_ENDIAN:
974 return cpu_to_le32(x);
975 case EDMAC_BIG_ENDIAN:
976 return cpu_to_be32(x);
977 }
978 return x;
979}
980
981static inline __u32 edmac_to_cpu(struct sh_eth_private *mdp, u32 x)
982{
983 switch (mdp->edmac_endian) {
984 case EDMAC_LITTLE_ENDIAN:
985 return le32_to_cpu(x);
986 case EDMAC_BIG_ENDIAN:
987 return be32_to_cpu(x);
988 }
989 return x;
990}
991
128296fc 992/* Program the hardware MAC address from dev->dev_addr. */
86a74ff2
NI		 993static void update_mac_address(struct net_device *ndev)
994{
4a55530f 995 sh_eth_write(ndev,
128296fc
SS		 996 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
997 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
4a55530f 998 sh_eth_write(ndev,
128296fc 999 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
86a74ff2
NI		 1000}
1001
128296fc 1002/* Get MAC address from SuperH MAC address register
86a74ff2
NI		 1003 *
1004 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
1005 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
1006 * When you want use this device, you must set MAC address in bootloader.
1007 *
1008 */
748031f9 1009static void read_mac_address(struct net_device *ndev, unsigned char *mac)
86a74ff2 1010{
748031f9 1011 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
d458cdf7 1012 memcpy(ndev->dev_addr, mac, ETH_ALEN);
748031f9 1013 } else {
4a55530f
YS		 1014 ndev->dev_addr[0] = (sh_eth_read(ndev, MAHR) >> 24);
1015 ndev->dev_addr[1] = (sh_eth_read(ndev, MAHR) >> 16) & 0xFF;
1016 ndev->dev_addr[2] = (sh_eth_read(ndev, MAHR) >> 8) & 0xFF;
1017 ndev->dev_addr[3] = (sh_eth_read(ndev, MAHR) & 0xFF);
1018 ndev->dev_addr[4] = (sh_eth_read(ndev, MALR) >> 8) & 0xFF;
1019 ndev->dev_addr[5] = (sh_eth_read(ndev, MALR) & 0xFF);
748031f9 1020 }
86a74ff2
NI		 1021}
1022
0799c2d6 1023static u32 sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
c5ed5368 1024{
db893473 1025 if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp))
c5ed5368
YS		 1026 return EDTRR_TRNS_GETHER;
1027 else
1028 return EDTRR_TRNS_ETHER;
1029}
1030
86a74ff2 1031struct bb_info {
ae70644d 1032 void (*set_gate)(void *addr);
86a74ff2 1033 struct mdiobb_ctrl ctrl;
ae70644d 1034 void *addr;
86a74ff2
NI		 1035 u32 mmd_msk;/* MMD */
1036 u32 mdo_msk;
1037 u32 mdi_msk;
1038 u32 mdc_msk;
1039};
1040
1041/* PHY bit set */
ae70644d 1042static void bb_set(void *addr, u32 msk)
86a74ff2 1043{
ae70644d 1044 iowrite32(ioread32(addr) | msk, addr);
86a74ff2
NI		 1045}
1046
1047/* PHY bit clear */
ae70644d 1048static void bb_clr(void *addr, u32 msk)
86a74ff2 1049{
ae70644d 1050 iowrite32((ioread32(addr) & ~msk), addr);
86a74ff2
NI		 1051}
1052
1053/* PHY bit read */
ae70644d 1054static int bb_read(void *addr, u32 msk)
86a74ff2 1055{
ae70644d 1056 return (ioread32(addr) & msk) != 0;
86a74ff2
NI		 1057}
1058
1059/* Data I/O pin control */
1060static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1061{
1062 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
b3017e6a
YS		 1063
1064 if (bitbang->set_gate)
1065 bitbang->set_gate(bitbang->addr);
1066
86a74ff2
NI		 1067 if (bit)
1068 bb_set(bitbang->addr, bitbang->mmd_msk);
1069 else
1070 bb_clr(bitbang->addr, bitbang->mmd_msk);
1071}
1072
1073/* Set bit data*/
1074static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
1075{
1076 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1077
b3017e6a
YS		 1078 if (bitbang->set_gate)
1079 bitbang->set_gate(bitbang->addr);
1080
86a74ff2
NI		 1081 if (bit)
1082 bb_set(bitbang->addr, bitbang->mdo_msk);
1083 else
1084 bb_clr(bitbang->addr, bitbang->mdo_msk);
1085}
1086
1087/* Get bit data*/
1088static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
1089{
1090 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
b3017e6a
YS		 1091
1092 if (bitbang->set_gate)
1093 bitbang->set_gate(bitbang->addr);
1094
86a74ff2
NI		 1095 return bb_read(bitbang->addr, bitbang->mdi_msk);
1096}
1097
1098/* MDC pin control */
1099static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1100{
1101 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1102
b3017e6a
YS		 1103 if (bitbang->set_gate)
1104 bitbang->set_gate(bitbang->addr);
1105
86a74ff2
NI		 1106 if (bit)
1107 bb_set(bitbang->addr, bitbang->mdc_msk);
1108 else
1109 bb_clr(bitbang->addr, bitbang->mdc_msk);
1110}
1111
1112/* mdio bus control struct */
1113static struct mdiobb_ops bb_ops = {
1114 .owner = THIS_MODULE,
1115 .set_mdc = sh_mdc_ctrl,
1116 .set_mdio_dir = sh_mmd_ctrl,
1117 .set_mdio_data = sh_set_mdio,
1118 .get_mdio_data = sh_get_mdio,
1119};
1120
86a74ff2
NI		 1121/* free skb and descriptor buffer */
1122static void sh_eth_ring_free(struct net_device *ndev)
1123{
1124 struct sh_eth_private *mdp = netdev_priv(ndev);
8e03a5e7 1125 int ringsize, i;
86a74ff2
NI		 1126
1127 /* Free Rx skb ringbuffer */
1128 if (mdp->rx_skbuff) {
179d80af
SS		 1129 for (i = 0; i < mdp->num_rx_ring; i++)
1130 dev_kfree_skb(mdp->rx_skbuff[i]);
86a74ff2
NI		 1131 }
1132 kfree(mdp->rx_skbuff);
91c77550 1133 mdp->rx_skbuff = NULL;
86a74ff2
NI		 1134
1135 /* Free Tx skb ringbuffer */
1136 if (mdp->tx_skbuff) {
179d80af
SS		 1137 for (i = 0; i < mdp->num_tx_ring; i++)
1138 dev_kfree_skb(mdp->tx_skbuff[i]);
86a74ff2
NI		 1139 }
1140 kfree(mdp->tx_skbuff);
91c77550 1141 mdp->tx_skbuff = NULL;
8e03a5e7
SS		 1142
1143 if (mdp->rx_ring) {
1144 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1145 dma_free_coherent(NULL, ringsize, mdp->rx_ring,
1146 mdp->rx_desc_dma);
1147 mdp->rx_ring = NULL;
1148 }
1149
1150 if (mdp->tx_ring) {
1151 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1152 dma_free_coherent(NULL, ringsize, mdp->tx_ring,
1153 mdp->tx_desc_dma);
1154 mdp->tx_ring = NULL;
1155 }
86a74ff2
NI		 1156}
1157
1158/* format skb and descriptor buffer */
1159static void sh_eth_ring_format(struct net_device *ndev)
1160{
1161 struct sh_eth_private *mdp = netdev_priv(ndev);
1162 int i;
1163 struct sk_buff *skb;
1164 struct sh_eth_rxdesc *rxdesc = NULL;
1165 struct sh_eth_txdesc *txdesc = NULL;
525b8075
YS		 1166 int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
1167 int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
cb368595 1168 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
52b9fa36 1169 dma_addr_t dma_addr;
86a74ff2 1170
128296fc
SS		 1171 mdp->cur_rx = 0;
1172 mdp->cur_tx = 0;
1173 mdp->dirty_rx = 0;
1174 mdp->dirty_tx = 0;
86a74ff2
NI		 1175
1176 memset(mdp->rx_ring, 0, rx_ringsize);
1177
1178 /* build Rx ring buffer */
525b8075 1179 for (i = 0; i < mdp->num_rx_ring; i++) {
86a74ff2
NI		 1180 /* skb */
1181 mdp->rx_skbuff[i] = NULL;
4d6a949c 1182 skb = netdev_alloc_skb(ndev, skbuff_size);
86a74ff2
NI		 1183 if (skb == NULL)
1184 break;
380af9e3
YS		 1185 sh_eth_set_receive_align(skb);
1186
86a74ff2
NI		 1187 /* RX descriptor */
1188 rxdesc = &mdp->rx_ring[i];
ab857916
SS		 1189 /* The size of the buffer is a multiple of 32 bytes. */
1190 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 32);
52b9fa36
BH		 1191 dma_addr = dma_map_single(&ndev->dev, skb->data,
1192 rxdesc->buffer_length,
1193 DMA_FROM_DEVICE);
1194 if (dma_mapping_error(&ndev->dev, dma_addr)) {
1195 kfree_skb(skb);
1196 break;
1197 }
1198 mdp->rx_skbuff[i] = skb;
1199 rxdesc->addr = dma_addr;
71557a37 1200 rxdesc->status = cpu_to_edmac(mdp, RD_RACT | RD_RFP);
86a74ff2 1201
b0ca2a21
NI		 1202 /* Rx descriptor address set */
1203 if (i == 0) {
4a55530f 1204 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
db893473
SH		 1205 if (sh_eth_is_gether(mdp) ||
1206 sh_eth_is_rz_fast_ether(mdp))
c5ed5368 1207 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
b0ca2a21 1208 }
86a74ff2
NI		 1209 }
1210
525b8075 1211 mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
86a74ff2
NI		 1212
1213 /* Mark the last entry as wrapping the ring. */
c238041f 1214 rxdesc->status |= cpu_to_edmac(mdp, RD_RDLE);
86a74ff2
NI		 1215
1216 memset(mdp->tx_ring, 0, tx_ringsize);
1217
1218 /* build Tx ring buffer */
525b8075 1219 for (i = 0; i < mdp->num_tx_ring; i++) {
86a74ff2
NI		 1220 mdp->tx_skbuff[i] = NULL;
1221 txdesc = &mdp->tx_ring[i];
71557a37 1222 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
86a74ff2 1223 txdesc->buffer_length = 0;
b0ca2a21 1224 if (i == 0) {
71557a37 1225 /* Tx descriptor address set */
4a55530f 1226 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
db893473
SH		 1227 if (sh_eth_is_gether(mdp) ||
1228 sh_eth_is_rz_fast_ether(mdp))
c5ed5368 1229 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
b0ca2a21 1230 }
86a74ff2
NI		 1231 }
1232
71557a37 1233 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
86a74ff2
NI		 1234}
1235
1236/* Get skb and descriptor buffer */
1237static int sh_eth_ring_init(struct net_device *ndev)
1238{
1239 struct sh_eth_private *mdp = netdev_priv(ndev);
91d80683 1240 int rx_ringsize, tx_ringsize;
86a74ff2 1241
128296fc 1242 /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
86a74ff2
NI		 1243 * card needs room to do 8 byte alignment, +2 so we can reserve
1244 * the first 2 bytes, and +16 gets room for the status word from the
1245 * card.
1246 */
1247 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
1248 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
503914cf
MD		 1249 if (mdp->cd->rpadir)
1250 mdp->rx_buf_sz += NET_IP_ALIGN;
86a74ff2
NI		 1251
1252 /* Allocate RX and TX skb rings */
2c94e856
SS		 1253 mdp->rx_skbuff = kcalloc(mdp->num_rx_ring, sizeof(*mdp->rx_skbuff),
1254 GFP_KERNEL);
91d80683
SS		 1255 if (!mdp->rx_skbuff)
1256 return -ENOMEM;
86a74ff2 1257
2c94e856
SS		 1258 mdp->tx_skbuff = kcalloc(mdp->num_tx_ring, sizeof(*mdp->tx_skbuff),
1259 GFP_KERNEL);
91d80683 1260 if (!mdp->tx_skbuff)
8e03a5e7 1261 goto ring_free;
86a74ff2
NI		 1262
1263 /* Allocate all Rx descriptors. */
525b8075 1264 rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
86a74ff2 1265 mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
d0320f75 1266 GFP_KERNEL);
91d80683 1267 if (!mdp->rx_ring)
8e03a5e7 1268 goto ring_free;
86a74ff2
NI		 1269
1270 mdp->dirty_rx = 0;
1271
1272 /* Allocate all Tx descriptors. */
525b8075 1273 tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
86a74ff2 1274 mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
d0320f75 1275 GFP_KERNEL);
91d80683 1276 if (!mdp->tx_ring)
8e03a5e7 1277 goto ring_free;
91d80683 1278 return 0;
86a74ff2 1279
8e03a5e7
SS		 1280ring_free:
1281 /* Free Rx and Tx skb ring buffer and DMA buffer */
86a74ff2
NI		 1282 sh_eth_ring_free(ndev);
1283
91d80683 1284 return -ENOMEM;
86a74ff2
NI		 1285}
1286
525b8075 1287static int sh_eth_dev_init(struct net_device *ndev, bool start)
86a74ff2
NI		 1288{
1289 int ret = 0;
1290 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 1291 u32 val;
1292
1293 /* Soft Reset */
5cee1d37
NI		 1294 ret = sh_eth_reset(ndev);
1295 if (ret)
f738a13d 1296 return ret;
86a74ff2 1297
55754f19
SH		 1298 if (mdp->cd->rmiimode)
1299 sh_eth_write(ndev, 0x1, RMIIMODE);
1300
b0ca2a21
NI		 1301 /* Descriptor format */
1302 sh_eth_ring_format(ndev);
380af9e3 1303 if (mdp->cd->rpadir)
4a55530f 1304 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
86a74ff2
NI		 1305
1306 /* all sh_eth int mask */
4a55530f 1307 sh_eth_write(ndev, 0, EESIPR);
86a74ff2 1308
10b9194f 1309#if defined(__LITTLE_ENDIAN)
380af9e3 1310 if (mdp->cd->hw_swap)
4a55530f 1311 sh_eth_write(ndev, EDMR_EL, EDMR);
380af9e3 1312 else
b0ca2a21 1313#endif
4a55530f 1314 sh_eth_write(ndev, 0, EDMR);
86a74ff2 1315
b0ca2a21 1316 /* FIFO size set */
4a55530f
YS		 1317 sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
1318 sh_eth_write(ndev, 0, TFTR);
86a74ff2 1319
530aa2d0
BD		 1320 /* Frame recv control (enable multiple-packets per rx irq) */
1321 sh_eth_write(ndev, RMCR_RNC, RMCR);
86a74ff2 1322
b284fbe3 1323 sh_eth_write(ndev, mdp->cd->trscer_err_mask, TRSCER);
86a74ff2 1324
380af9e3 1325 if (mdp->cd->bculr)
4a55530f 1326 sh_eth_write(ndev, 0x800, BCULR); /* Burst sycle set */
b0ca2a21 1327
4a55530f 1328 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
86a74ff2 1329
380af9e3 1330 if (!mdp->cd->no_trimd)
4a55530f 1331 sh_eth_write(ndev, 0, TRIMD);
86a74ff2 1332
b0ca2a21 1333 /* Recv frame limit set register */
fdb37a7f
YS		 1334 sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1335 RFLR);
86a74ff2 1336
4a55530f 1337 sh_eth_write(ndev, sh_eth_read(ndev, EESR), EESR);
283e38db
BH		 1338 if (start) {
1339 mdp->irq_enabled = true;
525b8075 1340 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
283e38db 1341 }
86a74ff2
NI		 1342
1343 /* PAUSE Prohibition */
4a55530f 1344 val = (sh_eth_read(ndev, ECMR) & ECMR_DM) |
86a74ff2
NI		 1345 ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE;
1346
4a55530f 1347 sh_eth_write(ndev, val, ECMR);
b0ca2a21 1348
380af9e3
YS		 1349 if (mdp->cd->set_rate)
1350 mdp->cd->set_rate(ndev);
1351
b0ca2a21 1352 /* E-MAC Status Register clear */
4a55530f 1353 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
b0ca2a21
NI		 1354
1355 /* E-MAC Interrupt Enable register */
525b8075
YS		 1356 if (start)
1357 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
86a74ff2
NI		 1358
1359 /* Set MAC address */
1360 update_mac_address(ndev);
1361
1362 /* mask reset */
380af9e3 1363 if (mdp->cd->apr)
4a55530f 1364 sh_eth_write(ndev, APR_AP, APR);
380af9e3 1365 if (mdp->cd->mpr)
4a55530f 1366 sh_eth_write(ndev, MPR_MP, MPR);
380af9e3 1367 if (mdp->cd->tpauser)
4a55530f 1368 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
b0ca2a21 1369
525b8075
YS		 1370 if (start) {
1371 /* Setting the Rx mode will start the Rx process. */
1372 sh_eth_write(ndev, EDRRR_R, EDRRR);
86a74ff2 1373
525b8075
YS		 1374 netif_start_queue(ndev);
1375 }
86a74ff2
NI		 1376
1377 return ret;
1378}
1379
740c7f31
BH		 1380static void sh_eth_dev_exit(struct net_device *ndev)
1381{
1382 struct sh_eth_private *mdp = netdev_priv(ndev);
1383 int i;
1384
1385 /* Deactivate all TX descriptors, so DMA should stop at next
1386 * packet boundary if it's currently running
1387 */
1388 for (i = 0; i < mdp->num_tx_ring; i++)
1389 mdp->tx_ring[i].status &= ~cpu_to_edmac(mdp, TD_TACT);
1390
1391 /* Disable TX FIFO egress to MAC */
1392 sh_eth_rcv_snd_disable(ndev);
1393
1394 /* Stop RX DMA at next packet boundary */
1395 sh_eth_write(ndev, 0, EDRRR);
1396
1397 /* Aside from TX DMA, we can't tell when the hardware is
1398 * really stopped, so we need to reset to make sure.
1399 * Before doing that, wait for long enough to *probably*
1400 * finish transmitting the last packet and poll stats.
1401 */
1402 msleep(2); /* max frame time at 10 Mbps < 1250 us */
1403 sh_eth_get_stats(ndev);
1404 sh_eth_reset(ndev);
a14c7d15
GU		 1405
1406 /* Set MAC address again */
1407 update_mac_address(ndev);
740c7f31
BH		 1408}
1409
86a74ff2
NI		 1410/* free Tx skb function */
1411static int sh_eth_txfree(struct net_device *ndev)
1412{
1413 struct sh_eth_private *mdp = netdev_priv(ndev);
1414 struct sh_eth_txdesc *txdesc;
128296fc 1415 int free_num = 0;
86a74ff2
NI		 1416 int entry = 0;
1417
1418 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
525b8075 1419 entry = mdp->dirty_tx % mdp->num_tx_ring;
86a74ff2 1420 txdesc = &mdp->tx_ring[entry];
71557a37 1421 if (txdesc->status & cpu_to_edmac(mdp, TD_TACT))
86a74ff2 1422 break;
7d7355f5 1423 /* TACT bit must be checked before all the following reads */
f32bfb9a 1424 dma_rmb();
e5fd13f4
BH		 1425 netif_info(mdp, tx_done, ndev,
1426 "tx entry %d status 0x%08x\n",
1427 entry, edmac_to_cpu(mdp, txdesc->status));
86a74ff2
NI		 1428 /* Free the original skb. */
1429 if (mdp->tx_skbuff[entry]) {
31fcb99d
YS		 1430 dma_unmap_single(&ndev->dev, txdesc->addr,
1431 txdesc->buffer_length, DMA_TO_DEVICE);
86a74ff2
NI		 1432 dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1433 mdp->tx_skbuff[entry] = NULL;
128296fc 1434 free_num++;
86a74ff2 1435 }
71557a37 1436 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
525b8075 1437 if (entry >= mdp->num_tx_ring - 1)
71557a37 1438 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
86a74ff2 1439
bb7d92e3
ED		 1440 ndev->stats.tx_packets++;
1441 ndev->stats.tx_bytes += txdesc->buffer_length;
86a74ff2 1442 }
128296fc 1443 return free_num;
86a74ff2
NI		 1444}
1445
1446/* Packet receive function */
3719109d 1447static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
86a74ff2
NI		 1448{
1449 struct sh_eth_private *mdp = netdev_priv(ndev);
1450 struct sh_eth_rxdesc *rxdesc;
1451
525b8075
YS		 1452 int entry = mdp->cur_rx % mdp->num_rx_ring;
1453 int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
319cd520 1454 int limit;
86a74ff2
NI		 1455 struct sk_buff *skb;
1456 u16 pkt_len = 0;
380af9e3 1457 u32 desc_status;
cb368595 1458 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
52b9fa36 1459 dma_addr_t dma_addr;
86a74ff2 1460
319cd520
MK		 1461 boguscnt = min(boguscnt, *quota);
1462 limit = boguscnt;
86a74ff2 1463 rxdesc = &mdp->rx_ring[entry];
71557a37 1464 while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) {
7d7355f5 1465 /* RACT bit must be checked before all the following reads */
f32bfb9a 1466 dma_rmb();
71557a37 1467 desc_status = edmac_to_cpu(mdp, rxdesc->status);
86a74ff2
NI		 1468 pkt_len = rxdesc->frame_length;
1469
1470 if (--boguscnt < 0)
1471 break;
1472
e5fd13f4
BH		 1473 netif_info(mdp, rx_status, ndev,
1474 "rx entry %d status 0x%08x len %d\n",
1475 entry, desc_status, pkt_len);
1476
86a74ff2 1477 if (!(desc_status & RDFEND))
bb7d92e3 1478 ndev->stats.rx_length_errors++;
86a74ff2 1479
128296fc 1480 /* In case of almost all GETHER/ETHERs, the Receive Frame State
dd019897 1481 * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
9b4a6364
BH		 1482 * bit 0. However, in case of the R8A7740 and R7S72100
1483 * the RFS bits are from bit 25 to bit 16. So, the
db893473 1484 * driver needs right shifting by 16.
dd019897 1485 */
ac8025a6
SS		 1486 if (mdp->cd->shift_rd0)
1487 desc_status >>= 16;
dd019897 1488
248be83d 1489 skb = mdp->rx_skbuff[entry];
86a74ff2
NI		 1490 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1491 RD_RFS5 | RD_RFS6 | RD_RFS10)) {
bb7d92e3 1492 ndev->stats.rx_errors++;
86a74ff2 1493 if (desc_status & RD_RFS1)
bb7d92e3 1494 ndev->stats.rx_crc_errors++;
86a74ff2 1495 if (desc_status & RD_RFS2)
bb7d92e3 1496 ndev->stats.rx_frame_errors++;
86a74ff2 1497 if (desc_status & RD_RFS3)
bb7d92e3 1498 ndev->stats.rx_length_errors++;
86a74ff2 1499 if (desc_status & RD_RFS4)
bb7d92e3 1500 ndev->stats.rx_length_errors++;
86a74ff2 1501 if (desc_status & RD_RFS6)
bb7d92e3 1502 ndev->stats.rx_missed_errors++;
86a74ff2 1503 if (desc_status & RD_RFS10)
bb7d92e3 1504 ndev->stats.rx_over_errors++;
248be83d 1505 } else if (skb) {
380af9e3
YS		 1506 if (!mdp->cd->hw_swap)
1507 sh_eth_soft_swap(
1508 phys_to_virt(ALIGN(rxdesc->addr, 4)),
1509 pkt_len + 2);
86a74ff2 1510 mdp->rx_skbuff[entry] = NULL;
503914cf
MD		 1511 if (mdp->cd->rpadir)
1512 skb_reserve(skb, NET_IP_ALIGN);
52b9fa36 1513 dma_unmap_single(&ndev->dev, rxdesc->addr,
ab857916 1514 ALIGN(mdp->rx_buf_sz, 32),
52b9fa36 1515 DMA_FROM_DEVICE);
86a74ff2
NI		 1516 skb_put(skb, pkt_len);
1517 skb->protocol = eth_type_trans(skb, ndev);
a8e9fd0f 1518 netif_receive_skb(skb);
bb7d92e3
ED		 1519 ndev->stats.rx_packets++;
1520 ndev->stats.rx_bytes += pkt_len;
25b77ad7
BH		 1521 if (desc_status & RD_RFS8)
1522 ndev->stats.multicast++;
86a74ff2 1523 }
525b8075 1524 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
862df497 1525 rxdesc = &mdp->rx_ring[entry];
86a74ff2
NI		 1526 }
1527
1528 /* Refill the Rx ring buffers. */
1529 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
525b8075 1530 entry = mdp->dirty_rx % mdp->num_rx_ring;
86a74ff2 1531 rxdesc = &mdp->rx_ring[entry];
ab857916
SS		 1532 /* The size of the buffer is 32 byte boundary. */
1533 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 32);
b0ca2a21 1534
86a74ff2 1535 if (mdp->rx_skbuff[entry] == NULL) {
4d6a949c 1536 skb = netdev_alloc_skb(ndev, skbuff_size);
86a74ff2
NI		 1537 if (skb == NULL)
1538 break; /* Better luck next round. */
380af9e3 1539 sh_eth_set_receive_align(skb);
52b9fa36
BH		 1540 dma_addr = dma_map_single(&ndev->dev, skb->data,
1541 rxdesc->buffer_length,
1542 DMA_FROM_DEVICE);
1543 if (dma_mapping_error(&ndev->dev, dma_addr)) {
1544 kfree_skb(skb);
1545 break;
1546 }
1547 mdp->rx_skbuff[entry] = skb;
380af9e3 1548
bc8acf2c 1549 skb_checksum_none_assert(skb);
52b9fa36 1550 rxdesc->addr = dma_addr;
86a74ff2 1551 }
f32bfb9a 1552 dma_wmb(); /* RACT bit must be set after all the above writes */
525b8075 1553 if (entry >= mdp->num_rx_ring - 1)
86a74ff2 1554 rxdesc->status |=
c238041f 1555 cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDLE);
86a74ff2
NI		 1556 else
1557 rxdesc->status |=
71557a37 1558 cpu_to_edmac(mdp, RD_RACT | RD_RFP);
86a74ff2
NI		 1559 }
1560
1561 /* Restart Rx engine if stopped. */
1562 /* If we don't need to check status, don't. -KDU */
79fba9f5 1563 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
a18e08bd 1564 /* fix the values for the next receiving if RDE is set */
3365711d
BH		 1565 if (intr_status & EESR_RDE &&
1566 mdp->reg_offset[RDFAR] != SH_ETH_OFFSET_INVALID) {
128296fc
SS		 1567 u32 count = (sh_eth_read(ndev, RDFAR) -
1568 sh_eth_read(ndev, RDLAR)) >> 4;
1569
1570 mdp->cur_rx = count;
1571 mdp->dirty_rx = count;
1572 }
4a55530f 1573 sh_eth_write(ndev, EDRRR_R, EDRRR);
79fba9f5 1574 }
86a74ff2 1575
319cd520
MK		 1576 *quota -= limit - boguscnt - 1;
1577
4f809cea 1578 return *quota <= 0;
86a74ff2
NI		 1579}
1580
4a55530f 1581static void sh_eth_rcv_snd_disable(struct net_device *ndev)
dc19e4e5
NI		 1582{
1583 /* disable tx and rx */
4a55530f
YS		 1584 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) &
1585 ~(ECMR_RE | ECMR_TE), ECMR);
dc19e4e5
NI		 1586}
1587
4a55530f 1588static void sh_eth_rcv_snd_enable(struct net_device *ndev)
dc19e4e5
NI		 1589{
1590 /* enable tx and rx */
4a55530f
YS		 1591 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) |
1592 (ECMR_RE | ECMR_TE), ECMR);
dc19e4e5
NI		 1593}
1594
86a74ff2 1595/* error control function */
0799c2d6 1596static void sh_eth_error(struct net_device *ndev, u32 intr_status)
86a74ff2
NI		 1597{
1598 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2 1599 u32 felic_stat;
380af9e3
YS		 1600 u32 link_stat;
1601 u32 mask;
86a74ff2
NI		 1602
1603 if (intr_status & EESR_ECI) {
4a55530f
YS		 1604 felic_stat = sh_eth_read(ndev, ECSR);
1605 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */
86a74ff2 1606 if (felic_stat & ECSR_ICD)
bb7d92e3 1607 ndev->stats.tx_carrier_errors++;
86a74ff2
NI		 1608 if (felic_stat & ECSR_LCHNG) {
1609 /* Link Changed */
4923576b 1610 if (mdp->cd->no_psr || mdp->no_ether_link) {
1e1b812b 1611 goto ignore_link;
380af9e3 1612 } else {
4a55530f 1613 link_stat = (sh_eth_read(ndev, PSR));
4923576b
YS		 1614 if (mdp->ether_link_active_low)
1615 link_stat = ~link_stat;
380af9e3 1616 }
128296fc 1617 if (!(link_stat & PHY_ST_LINK)) {
4a55530f 1618 sh_eth_rcv_snd_disable(ndev);
128296fc 1619 } else {
86a74ff2 1620 /* Link Up */
4a55530f 1621 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) &
128296fc
SS		 1622 ~DMAC_M_ECI, EESIPR);
1623 /* clear int */
4a55530f 1624 sh_eth_write(ndev, sh_eth_read(ndev, ECSR),
128296fc 1625 ECSR);
4a55530f 1626 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) |
128296fc 1627 DMAC_M_ECI, EESIPR);
86a74ff2 1628 /* enable tx and rx */
4a55530f 1629 sh_eth_rcv_snd_enable(ndev);
86a74ff2
NI		 1630 }
1631 }
1632 }
1633
1e1b812b 1634ignore_link:
86a74ff2 1635 if (intr_status & EESR_TWB) {
4eb313a7
SS		 1636 /* Unused write back interrupt */
1637 if (intr_status & EESR_TABT) { /* Transmit Abort int */
bb7d92e3 1638 ndev->stats.tx_aborted_errors++;
8d5009f6 1639 netif_err(mdp, tx_err, ndev, "Transmit Abort\n");
4eb313a7 1640 }
86a74ff2
NI		 1641 }
1642
1643 if (intr_status & EESR_RABT) {
1644 /* Receive Abort int */
1645 if (intr_status & EESR_RFRMER) {
1646 /* Receive Frame Overflow int */
bb7d92e3 1647 ndev->stats.rx_frame_errors++;
86a74ff2
NI		 1648 }
1649 }
380af9e3 1650
dc19e4e5
NI		 1651 if (intr_status & EESR_TDE) {
1652 /* Transmit Descriptor Empty int */
bb7d92e3 1653 ndev->stats.tx_fifo_errors++;
8d5009f6 1654 netif_err(mdp, tx_err, ndev, "Transmit Descriptor Empty\n");
dc19e4e5
NI		 1655 }
1656
1657 if (intr_status & EESR_TFE) {
1658 /* FIFO under flow */
bb7d92e3 1659 ndev->stats.tx_fifo_errors++;
8d5009f6 1660 netif_err(mdp, tx_err, ndev, "Transmit FIFO Under flow\n");
86a74ff2
NI		 1661 }
1662
1663 if (intr_status & EESR_RDE) {
1664 /* Receive Descriptor Empty int */
bb7d92e3 1665 ndev->stats.rx_over_errors++;
86a74ff2 1666 }
dc19e4e5 1667
86a74ff2
NI		 1668 if (intr_status & EESR_RFE) {
1669 /* Receive FIFO Overflow int */
bb7d92e3 1670 ndev->stats.rx_fifo_errors++;
dc19e4e5
NI		 1671 }
1672
1673 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1674 /* Address Error */
bb7d92e3 1675 ndev->stats.tx_fifo_errors++;
8d5009f6 1676 netif_err(mdp, tx_err, ndev, "Address Error\n");
86a74ff2 1677 }
380af9e3
YS		 1678
1679 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1680 if (mdp->cd->no_ade)
1681 mask &= ~EESR_ADE;
1682 if (intr_status & mask) {
86a74ff2 1683 /* Tx error */
4a55530f 1684 u32 edtrr = sh_eth_read(ndev, EDTRR);
090d560f 1685
86a74ff2 1686 /* dmesg */
da246855
SS		 1687 netdev_err(ndev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1688 intr_status, mdp->cur_tx, mdp->dirty_tx,
1689 (u32)ndev->state, edtrr);
86a74ff2
NI		 1690 /* dirty buffer free */
1691 sh_eth_txfree(ndev);
1692
1693 /* SH7712 BUG */
c5ed5368 1694 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
86a74ff2 1695 /* tx dma start */
c5ed5368 1696 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
86a74ff2
NI		 1697 }
1698 /* wakeup */
1699 netif_wake_queue(ndev);
1700 }
1701}
1702
1703static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1704{
1705 struct net_device *ndev = netdev;
1706 struct sh_eth_private *mdp = netdev_priv(ndev);
380af9e3 1707 struct sh_eth_cpu_data *cd = mdp->cd;
0e0fde3c 1708 irqreturn_t ret = IRQ_NONE;
0799c2d6 1709 u32 intr_status, intr_enable;
86a74ff2 1710
86a74ff2
NI		 1711 spin_lock(&mdp->lock);
1712
3893b273 1713 /* Get interrupt status */
4a55530f 1714 intr_status = sh_eth_read(ndev, EESR);
3893b273
SS		 1715 /* Mask it with the interrupt mask, forcing ECI interrupt to be always
1716 * enabled since it's the one that comes thru regardless of the mask,
1717 * and we need to fully handle it in sh_eth_error() in order to quench
1718 * it as it doesn't get cleared by just writing 1 to the ECI bit...
1719 */
3719109d
SS		 1720 intr_enable = sh_eth_read(ndev, EESIPR);
1721 intr_status &= intr_enable | DMAC_M_ECI;
1722 if (intr_status & (EESR_RX_CHECK | cd->tx_check | cd->eesr_err_check))
0e0fde3c 1723 ret = IRQ_HANDLED;
3719109d 1724 else
283e38db
BH		 1725 goto out;
1726
1727 if (!likely(mdp->irq_enabled)) {
1728 sh_eth_write(ndev, 0, EESIPR);
1729 goto out;
1730 }
86a74ff2 1731
3719109d
SS		 1732 if (intr_status & EESR_RX_CHECK) {
1733 if (napi_schedule_prep(&mdp->napi)) {
1734 /* Mask Rx interrupts */
1735 sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK,
1736 EESIPR);
1737 __napi_schedule(&mdp->napi);
1738 } else {
da246855 1739 netdev_warn(ndev,
0799c2d6 1740 "ignoring interrupt, status 0x%08x, mask 0x%08x.\n",
da246855 1741 intr_status, intr_enable);
3719109d
SS		 1742 }
1743 }
86a74ff2 1744
b0ca2a21 1745 /* Tx Check */
380af9e3 1746 if (intr_status & cd->tx_check) {
3719109d
SS		 1747 /* Clear Tx interrupts */
1748 sh_eth_write(ndev, intr_status & cd->tx_check, EESR);
1749
86a74ff2
NI		 1750 sh_eth_txfree(ndev);
1751 netif_wake_queue(ndev);
1752 }
1753
3719109d
SS		 1754 if (intr_status & cd->eesr_err_check) {
1755 /* Clear error interrupts */
1756 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR);
1757
86a74ff2 1758 sh_eth_error(ndev, intr_status);
3719109d 1759 }
86a74ff2 1760
283e38db 1761out:
86a74ff2
NI		 1762 spin_unlock(&mdp->lock);
1763
0e0fde3c 1764 return ret;
86a74ff2
NI		 1765}
1766
3719109d
SS		 1767static int sh_eth_poll(struct napi_struct *napi, int budget)
1768{
1769 struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private,
1770 napi);
1771 struct net_device *ndev = napi->dev;
1772 int quota = budget;
0799c2d6 1773 u32 intr_status;
3719109d
SS		 1774
1775 for (;;) {
1776 intr_status = sh_eth_read(ndev, EESR);
1777 if (!(intr_status & EESR_RX_CHECK))
1778 break;
1779 /* Clear Rx interrupts */
1780 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR);
1781
1782 if (sh_eth_rx(ndev, intr_status, &quota))
1783 goto out;
1784 }
1785
1786 napi_complete(napi);
1787
1788 /* Reenable Rx interrupts */
283e38db
BH		 1789 if (mdp->irq_enabled)
1790 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
3719109d
SS		 1791out:
1792 return budget - quota;
1793}
1794
86a74ff2
NI		 1795/* PHY state control function */
1796static void sh_eth_adjust_link(struct net_device *ndev)
1797{
1798 struct sh_eth_private *mdp = netdev_priv(ndev);
1799 struct phy_device *phydev = mdp->phydev;
86a74ff2
NI		 1800 int new_state = 0;
1801
3340d2aa 1802 if (phydev->link) {
86a74ff2
NI		 1803 if (phydev->duplex != mdp->duplex) {
1804 new_state = 1;
1805 mdp->duplex = phydev->duplex;
380af9e3
YS		 1806 if (mdp->cd->set_duplex)
1807 mdp->cd->set_duplex(ndev);
86a74ff2
NI		 1808 }
1809
1810 if (phydev->speed != mdp->speed) {
1811 new_state = 1;
1812 mdp->speed = phydev->speed;
380af9e3
YS		 1813 if (mdp->cd->set_rate)
1814 mdp->cd->set_rate(ndev);
86a74ff2 1815 }
3340d2aa 1816 if (!mdp->link) {
91a56152 1817 sh_eth_write(ndev,
128296fc
SS		 1818 sh_eth_read(ndev, ECMR) & ~ECMR_TXF,
1819 ECMR);
86a74ff2
NI		 1820 new_state = 1;
1821 mdp->link = phydev->link;
1e1b812b
SS		 1822 if (mdp->cd->no_psr || mdp->no_ether_link)
1823 sh_eth_rcv_snd_enable(ndev);
86a74ff2
NI		 1824 }
1825 } else if (mdp->link) {
1826 new_state = 1;
3340d2aa 1827 mdp->link = 0;
86a74ff2
NI		 1828 mdp->speed = 0;
1829 mdp->duplex = -1;
1e1b812b
SS		 1830 if (mdp->cd->no_psr || mdp->no_ether_link)
1831 sh_eth_rcv_snd_disable(ndev);
86a74ff2
NI		 1832 }
1833
dc19e4e5 1834 if (new_state && netif_msg_link(mdp))
86a74ff2
NI		 1835 phy_print_status(phydev);
1836}
1837
1838/* PHY init function */
1839static int sh_eth_phy_init(struct net_device *ndev)
1840{
702eca02 1841 struct device_node *np = ndev->dev.parent->of_node;
86a74ff2 1842 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 1843 struct phy_device *phydev = NULL;
1844
3340d2aa 1845 mdp->link = 0;
86a74ff2
NI		 1846 mdp->speed = 0;
1847 mdp->duplex = -1;
1848
1849 /* Try connect to PHY */
702eca02
BD		 1850 if (np) {
1851 struct device_node *pn;
1852
1853 pn = of_parse_phandle(np, "phy-handle", 0);
1854 phydev = of_phy_connect(ndev, pn,
1855 sh_eth_adjust_link, 0,
1856 mdp->phy_interface);
1857
1858 if (!phydev)
1859 phydev = ERR_PTR(-ENOENT);
1860 } else {
1861 char phy_id[MII_BUS_ID_SIZE + 3];
1862
1863 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
1864 mdp->mii_bus->id, mdp->phy_id);
1865
1866 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
1867 mdp->phy_interface);
1868 }
1869
86a74ff2 1870 if (IS_ERR(phydev)) {
da246855 1871 netdev_err(ndev, "failed to connect PHY\n");
86a74ff2
NI		 1872 return PTR_ERR(phydev);
1873 }
380af9e3 1874
da246855
SS		 1875 netdev_info(ndev, "attached PHY %d (IRQ %d) to driver %s\n",
1876 phydev->addr, phydev->irq, phydev->drv->name);
86a74ff2
NI		 1877
1878 mdp->phydev = phydev;
1879
1880 return 0;
1881}
1882
1883/* PHY control start function */
1884static int sh_eth_phy_start(struct net_device *ndev)
1885{
1886 struct sh_eth_private *mdp = netdev_priv(ndev);
1887 int ret;
1888
1889 ret = sh_eth_phy_init(ndev);
1890 if (ret)
1891 return ret;
1892
86a74ff2
NI		 1893 phy_start(mdp->phydev);
1894
1895 return 0;
1896}
1897
dc19e4e5 1898static int sh_eth_get_settings(struct net_device *ndev,
128296fc 1899 struct ethtool_cmd *ecmd)
dc19e4e5
NI		 1900{
1901 struct sh_eth_private *mdp = netdev_priv(ndev);
1902 unsigned long flags;
1903 int ret;
1904
4f9dce23
BH		 1905 if (!mdp->phydev)
1906 return -ENODEV;
1907
dc19e4e5
NI		 1908 spin_lock_irqsave(&mdp->lock, flags);
1909 ret = phy_ethtool_gset(mdp->phydev, ecmd);
1910 spin_unlock_irqrestore(&mdp->lock, flags);
1911
1912 return ret;
1913}
1914
1915static int sh_eth_set_settings(struct net_device *ndev,
128296fc 1916 struct ethtool_cmd *ecmd)
dc19e4e5
NI		 1917{
1918 struct sh_eth_private *mdp = netdev_priv(ndev);
1919 unsigned long flags;
1920 int ret;
dc19e4e5 1921
4f9dce23
BH		 1922 if (!mdp->phydev)
1923 return -ENODEV;
1924
dc19e4e5
NI		 1925 spin_lock_irqsave(&mdp->lock, flags);
1926
1927 /* disable tx and rx */
4a55530f 1928 sh_eth_rcv_snd_disable(ndev);
dc19e4e5
NI		 1929
1930 ret = phy_ethtool_sset(mdp->phydev, ecmd);
1931 if (ret)
1932 goto error_exit;
1933
1934 if (ecmd->duplex == DUPLEX_FULL)
1935 mdp->duplex = 1;
1936 else
1937 mdp->duplex = 0;
1938
1939 if (mdp->cd->set_duplex)
1940 mdp->cd->set_duplex(ndev);
1941
1942error_exit:
1943 mdelay(1);
1944
1945 /* enable tx and rx */
4a55530f 1946 sh_eth_rcv_snd_enable(ndev);
dc19e4e5
NI		 1947
1948 spin_unlock_irqrestore(&mdp->lock, flags);
1949
1950 return ret;
1951}
1952
6b4b4fea
BH		 1953/* If it is ever necessary to increase SH_ETH_REG_DUMP_MAX_REGS, the
1954 * version must be bumped as well. Just adding registers up to that
1955 * limit is fine, as long as the existing register indices don't
1956 * change.
1957 */
1958#define SH_ETH_REG_DUMP_VERSION 1
1959#define SH_ETH_REG_DUMP_MAX_REGS 256
1960
1961static size_t __sh_eth_get_regs(struct net_device *ndev, u32 *buf)
1962{
1963 struct sh_eth_private *mdp = netdev_priv(ndev);
1964 struct sh_eth_cpu_data *cd = mdp->cd;
1965 u32 *valid_map;
1966 size_t len;
1967
1968 BUILD_BUG_ON(SH_ETH_MAX_REGISTER_OFFSET > SH_ETH_REG_DUMP_MAX_REGS);
1969
1970 /* Dump starts with a bitmap that tells ethtool which
1971 * registers are defined for this chip.
1972 */
1973 len = DIV_ROUND_UP(SH_ETH_REG_DUMP_MAX_REGS, 32);
1974 if (buf) {
1975 valid_map = buf;
1976 buf += len;
1977 } else {
1978 valid_map = NULL;
1979 }
1980
1981 /* Add a register to the dump, if it has a defined offset.
1982 * This automatically skips most undefined registers, but for
1983 * some it is also necessary to check a capability flag in
1984 * struct sh_eth_cpu_data.
1985 */
1986#define mark_reg_valid(reg) valid_map[reg / 32] |= 1U << (reg % 32)
1987#define add_reg_from(reg, read_expr) do { \
1988 if (mdp->reg_offset[reg] != SH_ETH_OFFSET_INVALID) { \
1989 if (buf) { \
1990 mark_reg_valid(reg); \
1991 *buf++ = read_expr; \
1992 } \
1993 ++len; \
1994 } \
1995 } while (0)
1996#define add_reg(reg) add_reg_from(reg, sh_eth_read(ndev, reg))
1997#define add_tsu_reg(reg) add_reg_from(reg, sh_eth_tsu_read(mdp, reg))
1998
1999 add_reg(EDSR);
2000 add_reg(EDMR);
2001 add_reg(EDTRR);
2002 add_reg(EDRRR);
2003 add_reg(EESR);
2004 add_reg(EESIPR);
2005 add_reg(TDLAR);
2006 add_reg(TDFAR);
2007 add_reg(TDFXR);
2008 add_reg(TDFFR);
2009 add_reg(RDLAR);
2010 add_reg(RDFAR);
2011 add_reg(RDFXR);
2012 add_reg(RDFFR);
2013 add_reg(TRSCER);
2014 add_reg(RMFCR);
2015 add_reg(TFTR);
2016 add_reg(FDR);
2017 add_reg(RMCR);
2018 add_reg(TFUCR);
2019 add_reg(RFOCR);
2020 if (cd->rmiimode)
2021 add_reg(RMIIMODE);
2022 add_reg(FCFTR);
2023 if (cd->rpadir)
2024 add_reg(RPADIR);
2025 if (!cd->no_trimd)
2026 add_reg(TRIMD);
2027 add_reg(ECMR);
2028 add_reg(ECSR);
2029 add_reg(ECSIPR);
2030 add_reg(PIR);
2031 if (!cd->no_psr)
2032 add_reg(PSR);
2033 add_reg(RDMLR);
2034 add_reg(RFLR);
2035 add_reg(IPGR);
2036 if (cd->apr)
2037 add_reg(APR);
2038 if (cd->mpr)
2039 add_reg(MPR);
2040 add_reg(RFCR);
2041 add_reg(RFCF);
2042 if (cd->tpauser)
2043 add_reg(TPAUSER);
2044 add_reg(TPAUSECR);
2045 add_reg(GECMR);
2046 if (cd->bculr)
2047 add_reg(BCULR);
2048 add_reg(MAHR);
2049 add_reg(MALR);
2050 add_reg(TROCR);
2051 add_reg(CDCR);
2052 add_reg(LCCR);
2053 add_reg(CNDCR);
2054 add_reg(CEFCR);
2055 add_reg(FRECR);
2056 add_reg(TSFRCR);
2057 add_reg(TLFRCR);
2058 add_reg(CERCR);
2059 add_reg(CEECR);
2060 add_reg(MAFCR);
2061 if (cd->rtrate)
2062 add_reg(RTRATE);
2063 if (cd->hw_crc)
2064 add_reg(CSMR);
2065 if (cd->select_mii)
2066 add_reg(RMII_MII);
2067 add_reg(ARSTR);
2068 if (cd->tsu) {
2069 add_tsu_reg(TSU_CTRST);
2070 add_tsu_reg(TSU_FWEN0);
2071 add_tsu_reg(TSU_FWEN1);
2072 add_tsu_reg(TSU_FCM);
2073 add_tsu_reg(TSU_BSYSL0);
2074 add_tsu_reg(TSU_BSYSL1);
2075 add_tsu_reg(TSU_PRISL0);
2076 add_tsu_reg(TSU_PRISL1);
2077 add_tsu_reg(TSU_FWSL0);
2078 add_tsu_reg(TSU_FWSL1);
2079 add_tsu_reg(TSU_FWSLC);
2080 add_tsu_reg(TSU_QTAG0);
2081 add_tsu_reg(TSU_QTAG1);
2082 add_tsu_reg(TSU_QTAGM0);
2083 add_tsu_reg(TSU_QTAGM1);
2084 add_tsu_reg(TSU_FWSR);
2085 add_tsu_reg(TSU_FWINMK);
2086 add_tsu_reg(TSU_ADQT0);
2087 add_tsu_reg(TSU_ADQT1);
2088 add_tsu_reg(TSU_VTAG0);
2089 add_tsu_reg(TSU_VTAG1);
2090 add_tsu_reg(TSU_ADSBSY);
2091 add_tsu_reg(TSU_TEN);
2092 add_tsu_reg(TSU_POST1);
2093 add_tsu_reg(TSU_POST2);
2094 add_tsu_reg(TSU_POST3);
2095 add_tsu_reg(TSU_POST4);
2096 if (mdp->reg_offset[TSU_ADRH0] != SH_ETH_OFFSET_INVALID) {
2097 /* This is the start of a table, not just a single
2098 * register.
2099 */
2100 if (buf) {
2101 unsigned int i;
2102
2103 mark_reg_valid(TSU_ADRH0);
2104 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES * 2; i++)
2105 *buf++ = ioread32(
2106 mdp->tsu_addr +
2107 mdp->reg_offset[TSU_ADRH0] +
2108 i * 4);
2109 }
2110 len += SH_ETH_TSU_CAM_ENTRIES * 2;
2111 }
2112 }
2113
2114#undef mark_reg_valid
2115#undef add_reg_from
2116#undef add_reg
2117#undef add_tsu_reg
2118
2119 return len * 4;
2120}
2121
2122static int sh_eth_get_regs_len(struct net_device *ndev)
2123{
2124 return __sh_eth_get_regs(ndev, NULL);
2125}
2126
2127static void sh_eth_get_regs(struct net_device *ndev, struct ethtool_regs *regs,
2128 void *buf)
2129{
2130 struct sh_eth_private *mdp = netdev_priv(ndev);
2131
2132 regs->version = SH_ETH_REG_DUMP_VERSION;
2133
2134 pm_runtime_get_sync(&mdp->pdev->dev);
2135 __sh_eth_get_regs(ndev, buf);
2136 pm_runtime_put_sync(&mdp->pdev->dev);
2137}
2138
dc19e4e5
NI		 2139static int sh_eth_nway_reset(struct net_device *ndev)
2140{
2141 struct sh_eth_private *mdp = netdev_priv(ndev);
2142 unsigned long flags;
2143 int ret;
2144
4f9dce23
BH		 2145 if (!mdp->phydev)
2146 return -ENODEV;
2147
dc19e4e5
NI		 2148 spin_lock_irqsave(&mdp->lock, flags);
2149 ret = phy_start_aneg(mdp->phydev);
2150 spin_unlock_irqrestore(&mdp->lock, flags);
2151
2152 return ret;
2153}
2154
2155static u32 sh_eth_get_msglevel(struct net_device *ndev)
2156{
2157 struct sh_eth_private *mdp = netdev_priv(ndev);
2158 return mdp->msg_enable;
2159}
2160
2161static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
2162{
2163 struct sh_eth_private *mdp = netdev_priv(ndev);
2164 mdp->msg_enable = value;
2165}
2166
2167static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
2168 "rx_current", "tx_current",
2169 "rx_dirty", "tx_dirty",
2170};
2171#define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats)
2172
2173static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
2174{
2175 switch (sset) {
2176 case ETH_SS_STATS:
2177 return SH_ETH_STATS_LEN;
2178 default:
2179 return -EOPNOTSUPP;
2180 }
2181}
2182
2183static void sh_eth_get_ethtool_stats(struct net_device *ndev,
128296fc 2184 struct ethtool_stats *stats, u64 *data)
dc19e4e5
NI		 2185{
2186 struct sh_eth_private *mdp = netdev_priv(ndev);
2187 int i = 0;
2188
2189 /* device-specific stats */
2190 data[i++] = mdp->cur_rx;
2191 data[i++] = mdp->cur_tx;
2192 data[i++] = mdp->dirty_rx;
2193 data[i++] = mdp->dirty_tx;
2194}
2195
2196static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
2197{
2198 switch (stringset) {
2199 case ETH_SS_STATS:
2200 memcpy(data, *sh_eth_gstrings_stats,
128296fc 2201 sizeof(sh_eth_gstrings_stats));
dc19e4e5
NI		 2202 break;
2203 }
2204}
2205
525b8075
YS		 2206static void sh_eth_get_ringparam(struct net_device *ndev,
2207 struct ethtool_ringparam *ring)
2208{
2209 struct sh_eth_private *mdp = netdev_priv(ndev);
2210
2211 ring->rx_max_pending = RX_RING_MAX;
2212 ring->tx_max_pending = TX_RING_MAX;
2213 ring->rx_pending = mdp->num_rx_ring;
2214 ring->tx_pending = mdp->num_tx_ring;
2215}
2216
2217static int sh_eth_set_ringparam(struct net_device *ndev,
2218 struct ethtool_ringparam *ring)
2219{
2220 struct sh_eth_private *mdp = netdev_priv(ndev);
2221 int ret;
2222
2223 if (ring->tx_pending > TX_RING_MAX ||
2224 ring->rx_pending > RX_RING_MAX ||
2225 ring->tx_pending < TX_RING_MIN ||
2226 ring->rx_pending < RX_RING_MIN)
2227 return -EINVAL;
2228 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
2229 return -EINVAL;
2230
2231 if (netif_running(ndev)) {
bd888916 2232 netif_device_detach(ndev);
525b8075 2233 netif_tx_disable(ndev);
283e38db
BH		 2234
2235 /* Serialise with the interrupt handler and NAPI, then
2236 * disable interrupts. We have to clear the
2237 * irq_enabled flag first to ensure that interrupts
2238 * won't be re-enabled.
2239 */
2240 mdp->irq_enabled = false;
525b8075 2241 synchronize_irq(ndev->irq);
283e38db 2242 napi_synchronize(&mdp->napi);
525b8075 2243 sh_eth_write(ndev, 0x0000, EESIPR);
525b8075 2244
740c7f31 2245 sh_eth_dev_exit(ndev);
525b8075 2246
8e03a5e7 2247 /* Free all the skbuffs in the Rx queue and the DMA buffers. */
084236d8 2248 sh_eth_ring_free(ndev);
084236d8 2249 }
525b8075
YS		 2250
2251 /* Set new parameters */
2252 mdp->num_rx_ring = ring->rx_pending;
2253 mdp->num_tx_ring = ring->tx_pending;
2254
525b8075 2255 if (netif_running(ndev)) {
084236d8
BH		 2256 ret = sh_eth_ring_init(ndev);
2257 if (ret < 0) {
2258 netdev_err(ndev, "%s: sh_eth_ring_init failed.\n",
2259 __func__);
2260 return ret;
2261 }
2262 ret = sh_eth_dev_init(ndev, false);
2263 if (ret < 0) {
2264 netdev_err(ndev, "%s: sh_eth_dev_init failed.\n",
2265 __func__);
2266 return ret;
2267 }
2268
283e38db 2269 mdp->irq_enabled = true;
525b8075
YS		 2270 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
2271 /* Setting the Rx mode will start the Rx process. */
2272 sh_eth_write(ndev, EDRRR_R, EDRRR);
bd888916 2273 netif_device_attach(ndev);
525b8075
YS		 2274 }
2275
2276 return 0;
2277}
2278
9b07be4b 2279static const struct ethtool_ops sh_eth_ethtool_ops = {
dc19e4e5
NI		 2280 .get_settings = sh_eth_get_settings,
2281 .set_settings = sh_eth_set_settings,
6b4b4fea
BH		 2282 .get_regs_len = sh_eth_get_regs_len,
2283 .get_regs = sh_eth_get_regs,
9b07be4b 2284 .nway_reset = sh_eth_nway_reset,
dc19e4e5
NI		 2285 .get_msglevel = sh_eth_get_msglevel,
2286 .set_msglevel = sh_eth_set_msglevel,
9b07be4b 2287 .get_link = ethtool_op_get_link,
dc19e4e5
NI		 2288 .get_strings = sh_eth_get_strings,
2289 .get_ethtool_stats = sh_eth_get_ethtool_stats,
2290 .get_sset_count = sh_eth_get_sset_count,
525b8075
YS		 2291 .get_ringparam = sh_eth_get_ringparam,
2292 .set_ringparam = sh_eth_set_ringparam,
dc19e4e5
NI		 2293};
2294
86a74ff2
NI		 2295/* network device open function */
2296static int sh_eth_open(struct net_device *ndev)
2297{
2298 int ret = 0;
2299 struct sh_eth_private *mdp = netdev_priv(ndev);
2300
bcd5149d
MD		 2301 pm_runtime_get_sync(&mdp->pdev->dev);
2302
d2779e99
SS		 2303 napi_enable(&mdp->napi);
2304
a0607fd3 2305 ret = request_irq(ndev->irq, sh_eth_interrupt,
5b3dfd13 2306 mdp->cd->irq_flags, ndev->name, ndev);
86a74ff2 2307 if (ret) {
da246855 2308 netdev_err(ndev, "Can not assign IRQ number\n");
d2779e99 2309 goto out_napi_off;
86a74ff2
NI		 2310 }
2311
2312 /* Descriptor set */
2313 ret = sh_eth_ring_init(ndev);
2314 if (ret)
2315 goto out_free_irq;
2316
2317 /* device init */
525b8075 2318 ret = sh_eth_dev_init(ndev, true);
86a74ff2
NI		 2319 if (ret)
2320 goto out_free_irq;
2321
2322 /* PHY control start*/
2323 ret = sh_eth_phy_start(ndev);
2324 if (ret)
2325 goto out_free_irq;
2326
7fa2955f
MK		 2327 mdp->is_opened = 1;
2328
86a74ff2
NI		 2329 return ret;
2330
2331out_free_irq:
2332 free_irq(ndev->irq, ndev);
d2779e99
SS		 2333out_napi_off:
2334 napi_disable(&mdp->napi);
bcd5149d 2335 pm_runtime_put_sync(&mdp->pdev->dev);
86a74ff2
NI		 2336 return ret;
2337}
2338
2339/* Timeout function */
2340static void sh_eth_tx_timeout(struct net_device *ndev)
2341{
2342 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 2343 struct sh_eth_rxdesc *rxdesc;
2344 int i;
2345
2346 netif_stop_queue(ndev);
2347
8d5009f6
SS		 2348 netif_err(mdp, timer, ndev,
2349 "transmit timed out, status %8.8x, resetting...\n",
0799c2d6 2350 sh_eth_read(ndev, EESR));
86a74ff2
NI		 2351
2352 /* tx_errors count up */
bb7d92e3 2353 ndev->stats.tx_errors++;
86a74ff2 2354
86a74ff2 2355 /* Free all the skbuffs in the Rx queue. */
525b8075 2356 for (i = 0; i < mdp->num_rx_ring; i++) {
86a74ff2
NI		 2357 rxdesc = &mdp->rx_ring[i];
2358 rxdesc->status = 0;
2359 rxdesc->addr = 0xBADF00D0;
179d80af 2360 dev_kfree_skb(mdp->rx_skbuff[i]);
86a74ff2
NI		 2361 mdp->rx_skbuff[i] = NULL;
2362 }
525b8075 2363 for (i = 0; i < mdp->num_tx_ring; i++) {
179d80af 2364 dev_kfree_skb(mdp->tx_skbuff[i]);
86a74ff2
NI		 2365 mdp->tx_skbuff[i] = NULL;
2366 }
2367
2368 /* device init */
525b8075 2369 sh_eth_dev_init(ndev, true);
86a74ff2
NI		 2370}
2371
2372/* Packet transmit function */
2373static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
2374{
2375 struct sh_eth_private *mdp = netdev_priv(ndev);
2376 struct sh_eth_txdesc *txdesc;
2377 u32 entry;
fb5e2f9b 2378 unsigned long flags;
86a74ff2
NI		 2379
2380 spin_lock_irqsave(&mdp->lock, flags);
525b8075 2381 if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
86a74ff2 2382 if (!sh_eth_txfree(ndev)) {
8d5009f6 2383 netif_warn(mdp, tx_queued, ndev, "TxFD exhausted.\n");
86a74ff2
NI		 2384 netif_stop_queue(ndev);
2385 spin_unlock_irqrestore(&mdp->lock, flags);
5b548140 2386 return NETDEV_TX_BUSY;
86a74ff2
NI		 2387 }
2388 }
2389 spin_unlock_irqrestore(&mdp->lock, flags);
2390
dacc73e0 2391 if (skb_put_padto(skb, ETH_ZLEN))
eebfb643
BH		 2392 return NETDEV_TX_OK;
2393
525b8075 2394 entry = mdp->cur_tx % mdp->num_tx_ring;
86a74ff2
NI		 2395 mdp->tx_skbuff[entry] = skb;
2396 txdesc = &mdp->tx_ring[entry];
86a74ff2 2397 /* soft swap. */
380af9e3
YS		 2398 if (!mdp->cd->hw_swap)
2399 sh_eth_soft_swap(phys_to_virt(ALIGN(txdesc->addr, 4)),
2400 skb->len + 2);
31fcb99d
YS		 2401 txdesc->addr = dma_map_single(&ndev->dev, skb->data, skb->len,
2402 DMA_TO_DEVICE);
aa3933b8
BH		 2403 if (dma_mapping_error(&ndev->dev, txdesc->addr)) {
2404 kfree_skb(skb);
2405 return NETDEV_TX_OK;
2406 }
eebfb643 2407 txdesc->buffer_length = skb->len;
86a74ff2 2408
f32bfb9a 2409 dma_wmb(); /* TACT bit must be set after all the above writes */
525b8075 2410 if (entry >= mdp->num_tx_ring - 1)
71557a37 2411 txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE);
86a74ff2 2412 else
71557a37 2413 txdesc->status |= cpu_to_edmac(mdp, TD_TACT);
86a74ff2
NI		 2414
2415 mdp->cur_tx++;
2416
c5ed5368
YS		 2417 if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
2418 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
b0ca2a21 2419
6ed10654 2420 return NETDEV_TX_OK;
86a74ff2
NI		 2421}
2422
4398f9c8
BH		 2423/* The statistics registers have write-clear behaviour, which means we
2424 * will lose any increment between the read and write. We mitigate
2425 * this by only clearing when we read a non-zero value, so we will
2426 * never falsely report a total of zero.
2427 */
2428static void
2429sh_eth_update_stat(struct net_device *ndev, unsigned long *stat, int reg)
2430{
2431 u32 delta = sh_eth_read(ndev, reg);
2432
2433 if (delta) {
2434 *stat += delta;
2435 sh_eth_write(ndev, 0, reg);
2436 }
2437}
2438
7fa2955f
MK		 2439static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
2440{
2441 struct sh_eth_private *mdp = netdev_priv(ndev);
2442
2443 if (sh_eth_is_rz_fast_ether(mdp))
2444 return &ndev->stats;
2445
2446 if (!mdp->is_opened)
2447 return &ndev->stats;
2448
4398f9c8
BH		 2449 sh_eth_update_stat(ndev, &ndev->stats.tx_dropped, TROCR);
2450 sh_eth_update_stat(ndev, &ndev->stats.collisions, CDCR);
2451 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, LCCR);
7fa2955f
MK		 2452
2453 if (sh_eth_is_gether(mdp)) {
4398f9c8
BH		 2454 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2455 CERCR);
2456 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2457 CEECR);
7fa2955f 2458 } else {
4398f9c8
BH		 2459 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2460 CNDCR);
7fa2955f
MK		 2461 }
2462
2463 return &ndev->stats;
2464}
2465
86a74ff2
NI		 2466/* device close function */
2467static int sh_eth_close(struct net_device *ndev)
2468{
2469 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 2470
2471 netif_stop_queue(ndev);
2472
283e38db
BH		 2473 /* Serialise with the interrupt handler and NAPI, then disable
2474 * interrupts. We have to clear the irq_enabled flag first to
2475 * ensure that interrupts won't be re-enabled.
2476 */
2477 mdp->irq_enabled = false;
2478 synchronize_irq(ndev->irq);
2479 napi_disable(&mdp->napi);
4a55530f 2480 sh_eth_write(ndev, 0x0000, EESIPR);
86a74ff2 2481
740c7f31 2482 sh_eth_dev_exit(ndev);
86a74ff2
NI		 2483
2484 /* PHY Disconnect */
2485 if (mdp->phydev) {
2486 phy_stop(mdp->phydev);
2487 phy_disconnect(mdp->phydev);
4f9dce23 2488 mdp->phydev = NULL;
86a74ff2
NI		 2489 }
2490
2491 free_irq(ndev->irq, ndev);
2492
8e03a5e7 2493 /* Free all the skbuffs in the Rx queue and the DMA buffer. */
86a74ff2
NI		 2494 sh_eth_ring_free(ndev);
2495
bcd5149d
MD		 2496 pm_runtime_put_sync(&mdp->pdev->dev);
2497
7fa2955f 2498 mdp->is_opened = 0;
bcd5149d 2499
7fa2955f 2500 return 0;
86a74ff2
NI		 2501}
2502
bb7d92e3 2503/* ioctl to device function */
128296fc 2504static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
86a74ff2
NI		 2505{
2506 struct sh_eth_private *mdp = netdev_priv(ndev);
2507 struct phy_device *phydev = mdp->phydev;
2508
2509 if (!netif_running(ndev))
2510 return -EINVAL;
2511
2512 if (!phydev)
2513 return -ENODEV;
2514
28b04113 2515 return phy_mii_ioctl(phydev, rq, cmd);
86a74ff2
NI		 2516}
2517
6743fe6d
YS		 2518/* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
2519static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp,
2520 int entry)
2521{
2522 return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4);
2523}
2524
2525static u32 sh_eth_tsu_get_post_mask(int entry)
2526{
2527 return 0x0f << (28 - ((entry % 8) * 4));
2528}
2529
2530static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
2531{
2532 return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
2533}
2534
2535static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
2536 int entry)
2537{
2538 struct sh_eth_private *mdp = netdev_priv(ndev);
2539 u32 tmp;
2540 void *reg_offset;
2541
2542 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2543 tmp = ioread32(reg_offset);
2544 iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset);
2545}
2546
2547static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
2548 int entry)
2549{
2550 struct sh_eth_private *mdp = netdev_priv(ndev);
2551 u32 post_mask, ref_mask, tmp;
2552 void *reg_offset;
2553
2554 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2555 post_mask = sh_eth_tsu_get_post_mask(entry);
2556 ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
2557
2558 tmp = ioread32(reg_offset);
2559 iowrite32(tmp & ~post_mask, reg_offset);
2560
2561 /* If other port enables, the function returns "true" */
2562 return tmp & ref_mask;
2563}
2564
2565static int sh_eth_tsu_busy(struct net_device *ndev)
2566{
2567 int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
2568 struct sh_eth_private *mdp = netdev_priv(ndev);
2569
2570 while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
2571 udelay(10);
2572 timeout--;
2573 if (timeout <= 0) {
da246855 2574 netdev_err(ndev, "%s: timeout\n", __func__);
6743fe6d
YS		 2575 return -ETIMEDOUT;
2576 }
2577 }
2578
2579 return 0;
2580}
2581
2582static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg,
2583 const u8 *addr)
2584{
2585 u32 val;
2586
2587 val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
2588 iowrite32(val, reg);
2589 if (sh_eth_tsu_busy(ndev) < 0)
2590 return -EBUSY;
2591
2592 val = addr[4] << 8 | addr[5];
2593 iowrite32(val, reg + 4);
2594 if (sh_eth_tsu_busy(ndev) < 0)
2595 return -EBUSY;
2596
2597 return 0;
2598}
2599
2600static void sh_eth_tsu_read_entry(void *reg, u8 *addr)
2601{
2602 u32 val;
2603
2604 val = ioread32(reg);
2605 addr[0] = (val >> 24) & 0xff;
2606 addr[1] = (val >> 16) & 0xff;
2607 addr[2] = (val >> 8) & 0xff;
2608 addr[3] = val & 0xff;
2609 val = ioread32(reg + 4);
2610 addr[4] = (val >> 8) & 0xff;
2611 addr[5] = val & 0xff;
2612}
2613
2614
2615static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
2616{
2617 struct sh_eth_private *mdp = netdev_priv(ndev);
2618 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2619 int i;
2620 u8 c_addr[ETH_ALEN];
2621
2622 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2623 sh_eth_tsu_read_entry(reg_offset, c_addr);
c4bde29c 2624 if (ether_addr_equal(addr, c_addr))
6743fe6d
YS		 2625 return i;
2626 }
2627
2628 return -ENOENT;
2629}
2630
2631static int sh_eth_tsu_find_empty(struct net_device *ndev)
2632{
2633 u8 blank[ETH_ALEN];
2634 int entry;
2635
2636 memset(blank, 0, sizeof(blank));
2637 entry = sh_eth_tsu_find_entry(ndev, blank);
2638 return (entry < 0) ? -ENOMEM : entry;
2639}
2640
2641static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
2642 int entry)
2643{
2644 struct sh_eth_private *mdp = netdev_priv(ndev);
2645 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2646 int ret;
2647 u8 blank[ETH_ALEN];
2648
2649 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
2650 ~(1 << (31 - entry)), TSU_TEN);
2651
2652 memset(blank, 0, sizeof(blank));
2653 ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
2654 if (ret < 0)
2655 return ret;
2656 return 0;
2657}
2658
2659static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
2660{
2661 struct sh_eth_private *mdp = netdev_priv(ndev);
2662 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2663 int i, ret;
2664
2665 if (!mdp->cd->tsu)
2666 return 0;
2667
2668 i = sh_eth_tsu_find_entry(ndev, addr);
2669 if (i < 0) {
2670 /* No entry found, create one */
2671 i = sh_eth_tsu_find_empty(ndev);
2672 if (i < 0)
2673 return -ENOMEM;
2674 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
2675 if (ret < 0)
2676 return ret;
2677
2678 /* Enable the entry */
2679 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
2680 (1 << (31 - i)), TSU_TEN);
2681 }
2682
2683 /* Entry found or created, enable POST */
2684 sh_eth_tsu_enable_cam_entry_post(ndev, i);
2685
2686 return 0;
2687}
2688
2689static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
2690{
2691 struct sh_eth_private *mdp = netdev_priv(ndev);
2692 int i, ret;
2693
2694 if (!mdp->cd->tsu)
2695 return 0;
2696
2697 i = sh_eth_tsu_find_entry(ndev, addr);
2698 if (i) {
2699 /* Entry found */
2700 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2701 goto done;
2702
2703 /* Disable the entry if both ports was disabled */
2704 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2705 if (ret < 0)
2706 return ret;
2707 }
2708done:
2709 return 0;
2710}
2711
2712static int sh_eth_tsu_purge_all(struct net_device *ndev)
2713{
2714 struct sh_eth_private *mdp = netdev_priv(ndev);
2715 int i, ret;
2716
b37feed7 2717 if (!mdp->cd->tsu)
6743fe6d
YS		 2718 return 0;
2719
2720 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
2721 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2722 continue;
2723
2724 /* Disable the entry if both ports was disabled */
2725 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2726 if (ret < 0)
2727 return ret;
2728 }
2729
2730 return 0;
2731}
2732
2733static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
2734{
2735 struct sh_eth_private *mdp = netdev_priv(ndev);
2736 u8 addr[ETH_ALEN];
2737 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2738 int i;
2739
b37feed7 2740 if (!mdp->cd->tsu)
6743fe6d
YS		 2741 return;
2742
2743 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2744 sh_eth_tsu_read_entry(reg_offset, addr);
2745 if (is_multicast_ether_addr(addr))
2746 sh_eth_tsu_del_entry(ndev, addr);
2747 }
2748}
2749
b37feed7
BH		 2750/* Update promiscuous flag and multicast filter */
2751static void sh_eth_set_rx_mode(struct net_device *ndev)
86a74ff2 2752{
6743fe6d
YS		 2753 struct sh_eth_private *mdp = netdev_priv(ndev);
2754 u32 ecmr_bits;
2755 int mcast_all = 0;
2756 unsigned long flags;
2757
2758 spin_lock_irqsave(&mdp->lock, flags);
128296fc 2759 /* Initial condition is MCT = 1, PRM = 0.
6743fe6d
YS		 2760 * Depending on ndev->flags, set PRM or clear MCT
2761 */
b37feed7
BH		 2762 ecmr_bits = sh_eth_read(ndev, ECMR) & ~ECMR_PRM;
2763 if (mdp->cd->tsu)
2764 ecmr_bits |= ECMR_MCT;
6743fe6d
YS		 2765
2766 if (!(ndev->flags & IFF_MULTICAST)) {
2767 sh_eth_tsu_purge_mcast(ndev);
2768 mcast_all = 1;
2769 }
2770 if (ndev->flags & IFF_ALLMULTI) {
2771 sh_eth_tsu_purge_mcast(ndev);
2772 ecmr_bits &= ~ECMR_MCT;
2773 mcast_all = 1;
2774 }
2775
86a74ff2 2776 if (ndev->flags & IFF_PROMISC) {
6743fe6d
YS		 2777 sh_eth_tsu_purge_all(ndev);
2778 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2779 } else if (mdp->cd->tsu) {
2780 struct netdev_hw_addr *ha;
2781 netdev_for_each_mc_addr(ha, ndev) {
2782 if (mcast_all && is_multicast_ether_addr(ha->addr))
2783 continue;
2784
2785 if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2786 if (!mcast_all) {
2787 sh_eth_tsu_purge_mcast(ndev);
2788 ecmr_bits &= ~ECMR_MCT;
2789 mcast_all = 1;
2790 }
2791 }
2792 }
86a74ff2 2793 }
6743fe6d
YS		 2794
2795 /* update the ethernet mode */
2796 sh_eth_write(ndev, ecmr_bits, ECMR);
2797
2798 spin_unlock_irqrestore(&mdp->lock, flags);
86a74ff2 2799}
71cc7c37
YS		 2800
2801static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2802{
2803 if (!mdp->port)
2804 return TSU_VTAG0;
2805 else
2806 return TSU_VTAG1;
2807}
2808
80d5c368
PM		 2809static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
2810 __be16 proto, u16 vid)
71cc7c37
YS		 2811{
2812 struct sh_eth_private *mdp = netdev_priv(ndev);
2813 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2814
2815 if (unlikely(!mdp->cd->tsu))
2816 return -EPERM;
2817
2818 /* No filtering if vid = 0 */
2819 if (!vid)
2820 return 0;
2821
2822 mdp->vlan_num_ids++;
2823
128296fc 2824 /* The controller has one VLAN tag HW filter. So, if the filter is
71cc7c37
YS		 2825 * already enabled, the driver disables it and the filte
2826 */
2827 if (mdp->vlan_num_ids > 1) {
2828 /* disable VLAN filter */
2829 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2830 return 0;
2831 }
2832
2833 sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
2834 vtag_reg_index);
2835
2836 return 0;
2837}
2838
80d5c368
PM		 2839static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
2840 __be16 proto, u16 vid)
71cc7c37
YS		 2841{
2842 struct sh_eth_private *mdp = netdev_priv(ndev);
2843 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2844
2845 if (unlikely(!mdp->cd->tsu))
2846 return -EPERM;
2847
2848 /* No filtering if vid = 0 */
2849 if (!vid)
2850 return 0;
2851
2852 mdp->vlan_num_ids--;
2853 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2854
2855 return 0;
2856}
86a74ff2
NI		 2857
2858/* SuperH's TSU register init function */
4a55530f 2859static void sh_eth_tsu_init(struct sh_eth_private *mdp)
86a74ff2 2860{
db893473
SH		 2861 if (sh_eth_is_rz_fast_ether(mdp)) {
2862 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2863 return;
2864 }
2865
4a55530f
YS		 2866 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */
2867 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */
2868 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */
2869 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
2870 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
2871 sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
2872 sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
2873 sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
2874 sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
2875 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
c5ed5368
YS		 2876 if (sh_eth_is_gether(mdp)) {
2877 sh_eth_tsu_write(mdp, 0, TSU_QTAG0); /* Disable QTAG(0->1) */
2878 sh_eth_tsu_write(mdp, 0, TSU_QTAG1); /* Disable QTAG(1->0) */
2879 } else {
2880 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */
2881 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */
2882 }
4a55530f
YS		 2883 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */
2884 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */
2885 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2886 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */
2887 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */
2888 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */
2889 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */
86a74ff2
NI		 2890}
2891
2892/* MDIO bus release function */
bd920ff5 2893static int sh_mdio_release(struct sh_eth_private *mdp)
86a74ff2 2894{
86a74ff2 2895 /* unregister mdio bus */
bd920ff5 2896 mdiobus_unregister(mdp->mii_bus);
86a74ff2
NI		 2897
2898 /* free bitbang info */
bd920ff5 2899 free_mdio_bitbang(mdp->mii_bus);
86a74ff2
NI		 2900
2901 return 0;
2902}
2903
2904/* MDIO bus init function */
bd920ff5 2905static int sh_mdio_init(struct sh_eth_private *mdp,
b3017e6a 2906 struct sh_eth_plat_data *pd)
86a74ff2
NI		 2907{
2908 int ret, i;
2909 struct bb_info *bitbang;
bd920ff5 2910 struct platform_device *pdev = mdp->pdev;
aa8d4225 2911 struct device *dev = &mdp->pdev->dev;
86a74ff2
NI		 2912
2913 /* create bit control struct for PHY */
aa8d4225 2914 bitbang = devm_kzalloc(dev, sizeof(struct bb_info), GFP_KERNEL);
f738a13d
LP		 2915 if (!bitbang)
2916 return -ENOMEM;
86a74ff2
NI		 2917
2918 /* bitbang init */
ae70644d 2919 bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
b3017e6a 2920 bitbang->set_gate = pd->set_mdio_gate;
dfed5e7f
SS		 2921 bitbang->mdi_msk = PIR_MDI;
2922 bitbang->mdo_msk = PIR_MDO;
2923 bitbang->mmd_msk = PIR_MMD;
2924 bitbang->mdc_msk = PIR_MDC;
86a74ff2
NI		 2925 bitbang->ctrl.ops = &bb_ops;
2926
c2e07b3a 2927 /* MII controller setting */
86a74ff2 2928 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
f738a13d
LP		 2929 if (!mdp->mii_bus)
2930 return -ENOMEM;
86a74ff2
NI		 2931
2932 /* Hook up MII support for ethtool */
2933 mdp->mii_bus->name = "sh_mii";
a5bd6060 2934 mdp->mii_bus->parent = dev;
5278fb54 2935 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
bd920ff5 2936 pdev->name, pdev->id);
86a74ff2
NI		 2937
2938 /* PHY IRQ */
86b5d251
SS		 2939 mdp->mii_bus->irq = devm_kmalloc_array(dev, PHY_MAX_ADDR, sizeof(int),
2940 GFP_KERNEL);
86a74ff2
NI		 2941 if (!mdp->mii_bus->irq) {
2942 ret = -ENOMEM;
2943 goto out_free_bus;
2944 }
2945
bd920ff5
LP		 2946 /* register MDIO bus */
2947 if (dev->of_node) {
2948 ret = of_mdiobus_register(mdp->mii_bus, dev->of_node);
702eca02
BD		 2949 } else {
2950 for (i = 0; i < PHY_MAX_ADDR; i++)
2951 mdp->mii_bus->irq[i] = PHY_POLL;
2952 if (pd->phy_irq > 0)
2953 mdp->mii_bus->irq[pd->phy] = pd->phy_irq;
2954
2955 ret = mdiobus_register(mdp->mii_bus);
2956 }
2957
86a74ff2 2958 if (ret)
d5e07e69 2959 goto out_free_bus;
86a74ff2 2960
86a74ff2
NI		 2961 return 0;
2962
86a74ff2 2963out_free_bus:
298cf9be 2964 free_mdio_bitbang(mdp->mii_bus);
86a74ff2
NI		 2965 return ret;
2966}
2967
4a55530f
YS		 2968static const u16 *sh_eth_get_register_offset(int register_type)
2969{
2970 const u16 *reg_offset = NULL;
2971
2972 switch (register_type) {
2973 case SH_ETH_REG_GIGABIT:
2974 reg_offset = sh_eth_offset_gigabit;
2975 break;
db893473
SH		 2976 case SH_ETH_REG_FAST_RZ:
2977 reg_offset = sh_eth_offset_fast_rz;
2978 break;
a3f109bd
SS		 2979 case SH_ETH_REG_FAST_RCAR:
2980 reg_offset = sh_eth_offset_fast_rcar;
2981 break;
4a55530f
YS		 2982 case SH_ETH_REG_FAST_SH4:
2983 reg_offset = sh_eth_offset_fast_sh4;
2984 break;
2985 case SH_ETH_REG_FAST_SH3_SH2:
2986 reg_offset = sh_eth_offset_fast_sh3_sh2;
2987 break;
2988 default:
4a55530f
YS		 2989 break;
2990 }
2991
2992 return reg_offset;
2993}
2994
8f728d79 2995static const struct net_device_ops sh_eth_netdev_ops = {
ebf84eaa
AB		 2996 .ndo_open = sh_eth_open,
2997 .ndo_stop = sh_eth_close,
2998 .ndo_start_xmit = sh_eth_start_xmit,
2999 .ndo_get_stats = sh_eth_get_stats,
b37feed7 3000 .ndo_set_rx_mode = sh_eth_set_rx_mode,
ebf84eaa
AB		 3001 .ndo_tx_timeout = sh_eth_tx_timeout,
3002 .ndo_do_ioctl = sh_eth_do_ioctl,
3003 .ndo_validate_addr = eth_validate_addr,
3004 .ndo_set_mac_address = eth_mac_addr,
3005 .ndo_change_mtu = eth_change_mtu,
3006};
3007
8f728d79
SS		 3008static const struct net_device_ops sh_eth_netdev_ops_tsu = {
3009 .ndo_open = sh_eth_open,
3010 .ndo_stop = sh_eth_close,
3011 .ndo_start_xmit = sh_eth_start_xmit,
3012 .ndo_get_stats = sh_eth_get_stats,
b37feed7 3013 .ndo_set_rx_mode = sh_eth_set_rx_mode,
8f728d79
SS		 3014 .ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid,
3015 .ndo_vlan_rx_kill_vid = sh_eth_vlan_rx_kill_vid,
3016 .ndo_tx_timeout = sh_eth_tx_timeout,
3017 .ndo_do_ioctl = sh_eth_do_ioctl,
3018 .ndo_validate_addr = eth_validate_addr,
3019 .ndo_set_mac_address = eth_mac_addr,
3020 .ndo_change_mtu = eth_change_mtu,
3021};
3022
b356e978
SS		 3023#ifdef CONFIG_OF
3024static struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
3025{
3026 struct device_node *np = dev->of_node;
3027 struct sh_eth_plat_data *pdata;
b356e978
SS		 3028 const char *mac_addr;
3029
3030 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
3031 if (!pdata)
3032 return NULL;
3033
3034 pdata->phy_interface = of_get_phy_mode(np);
3035
b356e978
SS		 3036 mac_addr = of_get_mac_address(np);
3037 if (mac_addr)
3038 memcpy(pdata->mac_addr, mac_addr, ETH_ALEN);
3039
3040 pdata->no_ether_link =
3041 of_property_read_bool(np, "renesas,no-ether-link");
3042 pdata->ether_link_active_low =
3043 of_property_read_bool(np, "renesas,ether-link-active-low");
3044
3045 return pdata;
3046}
3047
3048static const struct of_device_id sh_eth_match_table[] = {
3049 { .compatible = "renesas,gether-r8a7740", .data = &r8a7740_data },
3050 { .compatible = "renesas,ether-r8a7778", .data = &r8a777x_data },
3051 { .compatible = "renesas,ether-r8a7779", .data = &r8a777x_data },
3052 { .compatible = "renesas,ether-r8a7790", .data = &r8a779x_data },
3053 { .compatible = "renesas,ether-r8a7791", .data = &r8a779x_data },
9488e1e5 3054 { .compatible = "renesas,ether-r8a7793", .data = &r8a779x_data },
0f76b9d8 3055 { .compatible = "renesas,ether-r8a7794", .data = &r8a779x_data },
b356e978
SS		 3056 { .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data },
3057 { }
3058};
3059MODULE_DEVICE_TABLE(of, sh_eth_match_table);
3060#else
3061static inline struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
3062{
3063 return NULL;
3064}
3065#endif
3066
86a74ff2
NI		 3067static int sh_eth_drv_probe(struct platform_device *pdev)
3068{
9c38657c 3069 int ret, devno = 0;
86a74ff2
NI		 3070 struct resource *res;
3071 struct net_device *ndev = NULL;
ec0d7551 3072 struct sh_eth_private *mdp = NULL;
0b76b862 3073 struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev);
afe391ad 3074 const struct platform_device_id *id = platform_get_device_id(pdev);
86a74ff2
NI		 3075
3076 /* get base addr */
3077 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
86a74ff2
NI		 3078
3079 ndev = alloc_etherdev(sizeof(struct sh_eth_private));
f738a13d
LP		 3080 if (!ndev)
3081 return -ENOMEM;
86a74ff2 3082
b5893a08
BD		 3083 pm_runtime_enable(&pdev->dev);
3084 pm_runtime_get_sync(&pdev->dev);
3085
86a74ff2
NI		 3086 devno = pdev->id;
3087 if (devno < 0)
3088 devno = 0;
3089
3090 ndev->dma = -1;
cc3c080d 3091 ret = platform_get_irq(pdev, 0);
7a468ac6 3092 if (ret < 0)
86a74ff2 3093 goto out_release;
cc3c080d 3094 ndev->irq = ret;
86a74ff2
NI		 3095
3096 SET_NETDEV_DEV(ndev, &pdev->dev);
3097
86a74ff2 3098 mdp = netdev_priv(ndev);
525b8075
YS		 3099 mdp->num_tx_ring = TX_RING_SIZE;
3100 mdp->num_rx_ring = RX_RING_SIZE;
d5e07e69
SS		 3101 mdp->addr = devm_ioremap_resource(&pdev->dev, res);
3102 if (IS_ERR(mdp->addr)) {
3103 ret = PTR_ERR(mdp->addr);
ae70644d
YS		 3104 goto out_release;
3105 }
3106
c960804f
VB		 3107 ndev->base_addr = res->start;
3108
86a74ff2 3109 spin_lock_init(&mdp->lock);
bcd5149d 3110 mdp->pdev = pdev;
86a74ff2 3111
b356e978
SS		 3112 if (pdev->dev.of_node)
3113 pd = sh_eth_parse_dt(&pdev->dev);
3b4c5cbf
SS		 3114 if (!pd) {
3115 dev_err(&pdev->dev, "no platform data\n");
3116 ret = -EINVAL;
3117 goto out_release;
3118 }
3119
86a74ff2 3120 /* get PHY ID */
71557a37 3121 mdp->phy_id = pd->phy;
e47c9052 3122 mdp->phy_interface = pd->phy_interface;
71557a37
YS		 3123 /* EDMAC endian */
3124 mdp->edmac_endian = pd->edmac_endian;
4923576b
YS		 3125 mdp->no_ether_link = pd->no_ether_link;
3126 mdp->ether_link_active_low = pd->ether_link_active_low;
86a74ff2 3127
380af9e3 3128 /* set cpu data */
b356e978
SS		 3129 if (id) {
3130 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data;
3131 } else {
3132 const struct of_device_id *match;
3133
3134 match = of_match_device(of_match_ptr(sh_eth_match_table),
3135 &pdev->dev);
3136 mdp->cd = (struct sh_eth_cpu_data *)match->data;
3137 }
a3153d8c 3138 mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type);
264be2f5
SS		 3139 if (!mdp->reg_offset) {
3140 dev_err(&pdev->dev, "Unknown register type (%d)\n",
3141 mdp->cd->register_type);
3142 ret = -EINVAL;
3143 goto out_release;
3144 }
380af9e3
YS		 3145 sh_eth_set_default_cpu_data(mdp->cd);
3146
86a74ff2 3147 /* set function */
8f728d79
SS		 3148 if (mdp->cd->tsu)
3149 ndev->netdev_ops = &sh_eth_netdev_ops_tsu;
3150 else
3151 ndev->netdev_ops = &sh_eth_netdev_ops;
7ad24ea4 3152 ndev->ethtool_ops = &sh_eth_ethtool_ops;
86a74ff2
NI		 3153 ndev->watchdog_timeo = TX_TIMEOUT;
3154
dc19e4e5
NI		 3155 /* debug message level */
3156 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
86a74ff2
NI		 3157
3158 /* read and set MAC address */
748031f9 3159 read_mac_address(ndev, pd->mac_addr);
ff6e7228
SS		 3160 if (!is_valid_ether_addr(ndev->dev_addr)) {
3161 dev_warn(&pdev->dev,
3162 "no valid MAC address supplied, using a random one.\n");
3163 eth_hw_addr_random(ndev);
3164 }
86a74ff2 3165
6ba88021
YS		 3166 /* ioremap the TSU registers */
3167 if (mdp->cd->tsu) {
3168 struct resource *rtsu;
3169 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
d5e07e69
SS		 3170 mdp->tsu_addr = devm_ioremap_resource(&pdev->dev, rtsu);
3171 if (IS_ERR(mdp->tsu_addr)) {
3172 ret = PTR_ERR(mdp->tsu_addr);
fc0c0900
SS		 3173 goto out_release;
3174 }
6743fe6d 3175 mdp->port = devno % 2;
f646968f 3176 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER;
6ba88021
YS		 3177 }
3178
150647fb
YS		 3179 /* initialize first or needed device */
3180 if (!devno || pd->needs_init) {
380af9e3
YS		 3181 if (mdp->cd->chip_reset)
3182 mdp->cd->chip_reset(ndev);
86a74ff2 3183
4986b996
YS		 3184 if (mdp->cd->tsu) {
3185 /* TSU init (Init only)*/
3186 sh_eth_tsu_init(mdp);
3187 }
86a74ff2
NI		 3188 }
3189
966d6dbb
HN		 3190 if (mdp->cd->rmiimode)
3191 sh_eth_write(ndev, 0x1, RMIIMODE);
3192
daacf03f
LP		 3193 /* MDIO bus init */
3194 ret = sh_mdio_init(mdp, pd);
3195 if (ret) {
3196 dev_err(&ndev->dev, "failed to initialise MDIO\n");
3197 goto out_release;
3198 }
3199
3719109d
SS		 3200 netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64);
3201
86a74ff2
NI		 3202 /* network device register */
3203 ret = register_netdev(ndev);
3204 if (ret)
3719109d 3205 goto out_napi_del;
86a74ff2 3206
25985edc 3207 /* print device information */
f75f14ec
SS		 3208 netdev_info(ndev, "Base address at 0x%x, %pM, IRQ %d.\n",
3209 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
86a74ff2 3210
b5893a08 3211 pm_runtime_put(&pdev->dev);
86a74ff2
NI		 3212 platform_set_drvdata(pdev, ndev);
3213
3214 return ret;
3215
3719109d
SS		 3216out_napi_del:
3217 netif_napi_del(&mdp->napi);
daacf03f 3218 sh_mdio_release(mdp);
3719109d 3219
86a74ff2
NI		 3220out_release:
3221 /* net_dev free */
3222 if (ndev)
3223 free_netdev(ndev);
3224
b5893a08
BD		 3225 pm_runtime_put(&pdev->dev);
3226 pm_runtime_disable(&pdev->dev);
86a74ff2
NI		 3227 return ret;
3228}
3229
3230static int sh_eth_drv_remove(struct platform_device *pdev)
3231{
3232 struct net_device *ndev = platform_get_drvdata(pdev);
3719109d 3233 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2 3234
86a74ff2 3235 unregister_netdev(ndev);
3719109d 3236 netif_napi_del(&mdp->napi);
daacf03f 3237 sh_mdio_release(mdp);
bcd5149d 3238 pm_runtime_disable(&pdev->dev);
86a74ff2 3239 free_netdev(ndev);
86a74ff2
NI		 3240
3241 return 0;
3242}
3243
540ad1b8 3244#ifdef CONFIG_PM
b71af046
MU		 3245#ifdef CONFIG_PM_SLEEP
3246static int sh_eth_suspend(struct device *dev)
3247{
3248 struct net_device *ndev = dev_get_drvdata(dev);
3249 int ret = 0;
3250
3251 if (netif_running(ndev)) {
3252 netif_device_detach(ndev);
3253 ret = sh_eth_close(ndev);
3254 }
3255
3256 return ret;
3257}
3258
3259static int sh_eth_resume(struct device *dev)
3260{
3261 struct net_device *ndev = dev_get_drvdata(dev);
3262 int ret = 0;
3263
3264 if (netif_running(ndev)) {
3265 ret = sh_eth_open(ndev);
3266 if (ret < 0)
3267 return ret;
3268 netif_device_attach(ndev);
3269 }
3270
3271 return ret;
3272}
3273#endif
3274
bcd5149d
MD		 3275static int sh_eth_runtime_nop(struct device *dev)
3276{
128296fc 3277 /* Runtime PM callback shared between ->runtime_suspend()
bcd5149d
MD		 3278 * and ->runtime_resume(). Simply returns success.
3279 *
3280 * This driver re-initializes all registers after
3281 * pm_runtime_get_sync() anyway so there is no need
3282 * to save and restore registers here.
3283 */
3284 return 0;
3285}
3286
540ad1b8 3287static const struct dev_pm_ops sh_eth_dev_pm_ops = {
b71af046 3288 SET_SYSTEM_SLEEP_PM_OPS(sh_eth_suspend, sh_eth_resume)
e7d7e898 3289 SET_RUNTIME_PM_OPS(sh_eth_runtime_nop, sh_eth_runtime_nop, NULL)
bcd5149d 3290};
540ad1b8
NI		 3291#define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
3292#else
3293#define SH_ETH_PM_OPS NULL
3294#endif
bcd5149d 3295
afe391ad 3296static struct platform_device_id sh_eth_id_table[] = {
c18a79ab 3297 { "sh7619-ether", (kernel_ulong_t)&sh7619_data },
7bbe150d 3298 { "sh771x-ether", (kernel_ulong_t)&sh771x_data },
9c3beaab 3299 { "sh7724-ether", (kernel_ulong_t)&sh7724_data },
f5d12767 3300 { "sh7734-gether", (kernel_ulong_t)&sh7734_data },
24549e2a
SS		 3301 { "sh7757-ether", (kernel_ulong_t)&sh7757_data },
3302 { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga },
f5d12767 3303 { "sh7763-gether", (kernel_ulong_t)&sh7763_data },
db893473 3304 { "r7s72100-ether", (kernel_ulong_t)&r7s72100_data },
e5c9b4cd 3305 { "r8a7740-gether", (kernel_ulong_t)&r8a7740_data },
589ebdef 3306 { "r8a777x-ether", (kernel_ulong_t)&r8a777x_data },
94a12b15
SS		 3307 { "r8a7790-ether", (kernel_ulong_t)&r8a779x_data },
3308 { "r8a7791-ether", (kernel_ulong_t)&r8a779x_data },
9488e1e5 3309 { "r8a7793-ether", (kernel_ulong_t)&r8a779x_data },
0f76b9d8 3310 { "r8a7794-ether", (kernel_ulong_t)&r8a779x_data },
afe391ad
SS		 3311 { }
3312};
3313MODULE_DEVICE_TABLE(platform, sh_eth_id_table);
3314
86a74ff2
NI		 3315static struct platform_driver sh_eth_driver = {
3316 .probe = sh_eth_drv_probe,
3317 .remove = sh_eth_drv_remove,
afe391ad 3318 .id_table = sh_eth_id_table,
86a74ff2
NI		 3319 .driver = {
3320 .name = CARDNAME,
540ad1b8 3321 .pm = SH_ETH_PM_OPS,
b356e978 3322 .of_match_table = of_match_ptr(sh_eth_match_table),
86a74ff2
NI		 3323 },
3324};
3325
db62f684 3326module_platform_driver(sh_eth_driver);
86a74ff2
NI		 3327
3328MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
3329MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
3330MODULE_LICENSE("GPL v2");
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