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ieee802154: dgram: cleanup set of broadcast panid
[mirror_ubuntu-jammy-kernel.git] / drivers / net / ethernet / renesas / sh_eth.c
CommitLineData
128296fc 1/* SuperH Ethernet device driver
86a74ff2 2 *
f0e81fec 3 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu
b356e978
SS		 4 * Copyright (C) 2008-2014 Renesas Solutions Corp.
5 * Copyright (C) 2013-2014 Cogent Embedded, Inc.
702eca02 6 * Copyright (C) 2014 Codethink Limited
86a74ff2
NI		 7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
86a74ff2
NI		 16 *
17 * The full GNU General Public License is included in this distribution in
18 * the file called "COPYING".
19 */
20
0654011d
YS		 21#include <linux/module.h>
22#include <linux/kernel.h>
23#include <linux/spinlock.h>
6a27cded 24#include <linux/interrupt.h>
86a74ff2
NI		 25#include <linux/dma-mapping.h>
26#include <linux/etherdevice.h>
27#include <linux/delay.h>
28#include <linux/platform_device.h>
29#include <linux/mdio-bitbang.h>
30#include <linux/netdevice.h>
b356e978
SS		 31#include <linux/of.h>
32#include <linux/of_device.h>
33#include <linux/of_irq.h>
34#include <linux/of_net.h>
86a74ff2
NI		 35#include <linux/phy.h>
36#include <linux/cache.h>
37#include <linux/io.h>
bcd5149d 38#include <linux/pm_runtime.h>
5a0e3ad6 39#include <linux/slab.h>
dc19e4e5 40#include <linux/ethtool.h>
fdb37a7f 41#include <linux/if_vlan.h>
f0e81fec 42#include <linux/clk.h>
d4fa0e35 43#include <linux/sh_eth.h>
702eca02 44#include <linux/of_mdio.h>
86a74ff2
NI		 45
46#include "sh_eth.h"
47
dc19e4e5
NI		 48#define SH_ETH_DEF_MSG_ENABLE \
49 (NETIF_MSG_LINK | \
50 NETIF_MSG_TIMER | \
51 NETIF_MSG_RX_ERR| \
52 NETIF_MSG_TX_ERR)
53
c0013f6f
SS		 54static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
55 [EDSR] = 0x0000,
56 [EDMR] = 0x0400,
57 [EDTRR] = 0x0408,
58 [EDRRR] = 0x0410,
59 [EESR] = 0x0428,
60 [EESIPR] = 0x0430,
61 [TDLAR] = 0x0010,
62 [TDFAR] = 0x0014,
63 [TDFXR] = 0x0018,
64 [TDFFR] = 0x001c,
65 [RDLAR] = 0x0030,
66 [RDFAR] = 0x0034,
67 [RDFXR] = 0x0038,
68 [RDFFR] = 0x003c,
69 [TRSCER] = 0x0438,
70 [RMFCR] = 0x0440,
71 [TFTR] = 0x0448,
72 [FDR] = 0x0450,
73 [RMCR] = 0x0458,
74 [RPADIR] = 0x0460,
75 [FCFTR] = 0x0468,
76 [CSMR] = 0x04E4,
77
78 [ECMR] = 0x0500,
79 [ECSR] = 0x0510,
80 [ECSIPR] = 0x0518,
81 [PIR] = 0x0520,
82 [PSR] = 0x0528,
83 [PIPR] = 0x052c,
84 [RFLR] = 0x0508,
85 [APR] = 0x0554,
86 [MPR] = 0x0558,
87 [PFTCR] = 0x055c,
88 [PFRCR] = 0x0560,
89 [TPAUSER] = 0x0564,
90 [GECMR] = 0x05b0,
91 [BCULR] = 0x05b4,
92 [MAHR] = 0x05c0,
93 [MALR] = 0x05c8,
94 [TROCR] = 0x0700,
95 [CDCR] = 0x0708,
96 [LCCR] = 0x0710,
97 [CEFCR] = 0x0740,
98 [FRECR] = 0x0748,
99 [TSFRCR] = 0x0750,
100 [TLFRCR] = 0x0758,
101 [RFCR] = 0x0760,
102 [CERCR] = 0x0768,
103 [CEECR] = 0x0770,
104 [MAFCR] = 0x0778,
105 [RMII_MII] = 0x0790,
106
107 [ARSTR] = 0x0000,
108 [TSU_CTRST] = 0x0004,
109 [TSU_FWEN0] = 0x0010,
110 [TSU_FWEN1] = 0x0014,
111 [TSU_FCM] = 0x0018,
112 [TSU_BSYSL0] = 0x0020,
113 [TSU_BSYSL1] = 0x0024,
114 [TSU_PRISL0] = 0x0028,
115 [TSU_PRISL1] = 0x002c,
116 [TSU_FWSL0] = 0x0030,
117 [TSU_FWSL1] = 0x0034,
118 [TSU_FWSLC] = 0x0038,
119 [TSU_QTAG0] = 0x0040,
120 [TSU_QTAG1] = 0x0044,
121 [TSU_FWSR] = 0x0050,
122 [TSU_FWINMK] = 0x0054,
123 [TSU_ADQT0] = 0x0048,
124 [TSU_ADQT1] = 0x004c,
125 [TSU_VTAG0] = 0x0058,
126 [TSU_VTAG1] = 0x005c,
127 [TSU_ADSBSY] = 0x0060,
128 [TSU_TEN] = 0x0064,
129 [TSU_POST1] = 0x0070,
130 [TSU_POST2] = 0x0074,
131 [TSU_POST3] = 0x0078,
132 [TSU_POST4] = 0x007c,
133 [TSU_ADRH0] = 0x0100,
134 [TSU_ADRL0] = 0x0104,
135 [TSU_ADRH31] = 0x01f8,
136 [TSU_ADRL31] = 0x01fc,
137
138 [TXNLCR0] = 0x0080,
139 [TXALCR0] = 0x0084,
140 [RXNLCR0] = 0x0088,
141 [RXALCR0] = 0x008c,
142 [FWNLCR0] = 0x0090,
143 [FWALCR0] = 0x0094,
144 [TXNLCR1] = 0x00a0,
145 [TXALCR1] = 0x00a0,
146 [RXNLCR1] = 0x00a8,
147 [RXALCR1] = 0x00ac,
148 [FWNLCR1] = 0x00b0,
149 [FWALCR1] = 0x00b4,
150};
151
db893473
SH		 152static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
153 [EDSR] = 0x0000,
154 [EDMR] = 0x0400,
155 [EDTRR] = 0x0408,
156 [EDRRR] = 0x0410,
157 [EESR] = 0x0428,
158 [EESIPR] = 0x0430,
159 [TDLAR] = 0x0010,
160 [TDFAR] = 0x0014,
161 [TDFXR] = 0x0018,
162 [TDFFR] = 0x001c,
163 [RDLAR] = 0x0030,
164 [RDFAR] = 0x0034,
165 [RDFXR] = 0x0038,
166 [RDFFR] = 0x003c,
167 [TRSCER] = 0x0438,
168 [RMFCR] = 0x0440,
169 [TFTR] = 0x0448,
170 [FDR] = 0x0450,
171 [RMCR] = 0x0458,
172 [RPADIR] = 0x0460,
173 [FCFTR] = 0x0468,
174 [CSMR] = 0x04E4,
175
176 [ECMR] = 0x0500,
177 [RFLR] = 0x0508,
178 [ECSR] = 0x0510,
179 [ECSIPR] = 0x0518,
180 [PIR] = 0x0520,
181 [APR] = 0x0554,
182 [MPR] = 0x0558,
183 [PFTCR] = 0x055c,
184 [PFRCR] = 0x0560,
185 [TPAUSER] = 0x0564,
186 [MAHR] = 0x05c0,
187 [MALR] = 0x05c8,
188 [CEFCR] = 0x0740,
189 [FRECR] = 0x0748,
190 [TSFRCR] = 0x0750,
191 [TLFRCR] = 0x0758,
192 [RFCR] = 0x0760,
193 [MAFCR] = 0x0778,
194
195 [ARSTR] = 0x0000,
196 [TSU_CTRST] = 0x0004,
197 [TSU_VTAG0] = 0x0058,
198 [TSU_ADSBSY] = 0x0060,
199 [TSU_TEN] = 0x0064,
200 [TSU_ADRH0] = 0x0100,
201 [TSU_ADRL0] = 0x0104,
202 [TSU_ADRH31] = 0x01f8,
203 [TSU_ADRL31] = 0x01fc,
204
205 [TXNLCR0] = 0x0080,
206 [TXALCR0] = 0x0084,
207 [RXNLCR0] = 0x0088,
208 [RXALCR0] = 0x008C,
209};
210
a3f109bd
SS		 211static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
212 [ECMR] = 0x0300,
213 [RFLR] = 0x0308,
214 [ECSR] = 0x0310,
215 [ECSIPR] = 0x0318,
216 [PIR] = 0x0320,
217 [PSR] = 0x0328,
218 [RDMLR] = 0x0340,
219 [IPGR] = 0x0350,
220 [APR] = 0x0354,
221 [MPR] = 0x0358,
222 [RFCF] = 0x0360,
223 [TPAUSER] = 0x0364,
224 [TPAUSECR] = 0x0368,
225 [MAHR] = 0x03c0,
226 [MALR] = 0x03c8,
227 [TROCR] = 0x03d0,
228 [CDCR] = 0x03d4,
229 [LCCR] = 0x03d8,
230 [CNDCR] = 0x03dc,
231 [CEFCR] = 0x03e4,
232 [FRECR] = 0x03e8,
233 [TSFRCR] = 0x03ec,
234 [TLFRCR] = 0x03f0,
235 [RFCR] = 0x03f4,
236 [MAFCR] = 0x03f8,
237
238 [EDMR] = 0x0200,
239 [EDTRR] = 0x0208,
240 [EDRRR] = 0x0210,
241 [TDLAR] = 0x0218,
242 [RDLAR] = 0x0220,
243 [EESR] = 0x0228,
244 [EESIPR] = 0x0230,
245 [TRSCER] = 0x0238,
246 [RMFCR] = 0x0240,
247 [TFTR] = 0x0248,
248 [FDR] = 0x0250,
249 [RMCR] = 0x0258,
250 [TFUCR] = 0x0264,
251 [RFOCR] = 0x0268,
55754f19 252 [RMIIMODE] = 0x026c,
a3f109bd
SS		 253 [FCFTR] = 0x0270,
254 [TRIMD] = 0x027c,
255};
256
c0013f6f
SS		 257static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
258 [ECMR] = 0x0100,
259 [RFLR] = 0x0108,
260 [ECSR] = 0x0110,
261 [ECSIPR] = 0x0118,
262 [PIR] = 0x0120,
263 [PSR] = 0x0128,
264 [RDMLR] = 0x0140,
265 [IPGR] = 0x0150,
266 [APR] = 0x0154,
267 [MPR] = 0x0158,
268 [TPAUSER] = 0x0164,
269 [RFCF] = 0x0160,
270 [TPAUSECR] = 0x0168,
271 [BCFRR] = 0x016c,
272 [MAHR] = 0x01c0,
273 [MALR] = 0x01c8,
274 [TROCR] = 0x01d0,
275 [CDCR] = 0x01d4,
276 [LCCR] = 0x01d8,
277 [CNDCR] = 0x01dc,
278 [CEFCR] = 0x01e4,
279 [FRECR] = 0x01e8,
280 [TSFRCR] = 0x01ec,
281 [TLFRCR] = 0x01f0,
282 [RFCR] = 0x01f4,
283 [MAFCR] = 0x01f8,
284 [RTRATE] = 0x01fc,
285
286 [EDMR] = 0x0000,
287 [EDTRR] = 0x0008,
288 [EDRRR] = 0x0010,
289 [TDLAR] = 0x0018,
290 [RDLAR] = 0x0020,
291 [EESR] = 0x0028,
292 [EESIPR] = 0x0030,
293 [TRSCER] = 0x0038,
294 [RMFCR] = 0x0040,
295 [TFTR] = 0x0048,
296 [FDR] = 0x0050,
297 [RMCR] = 0x0058,
298 [TFUCR] = 0x0064,
299 [RFOCR] = 0x0068,
300 [FCFTR] = 0x0070,
301 [RPADIR] = 0x0078,
302 [TRIMD] = 0x007c,
303 [RBWAR] = 0x00c8,
304 [RDFAR] = 0x00cc,
305 [TBRAR] = 0x00d4,
306 [TDFAR] = 0x00d8,
307};
308
309static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
310 [ECMR] = 0x0160,
311 [ECSR] = 0x0164,
312 [ECSIPR] = 0x0168,
313 [PIR] = 0x016c,
314 [MAHR] = 0x0170,
315 [MALR] = 0x0174,
316 [RFLR] = 0x0178,
317 [PSR] = 0x017c,
318 [TROCR] = 0x0180,
319 [CDCR] = 0x0184,
320 [LCCR] = 0x0188,
321 [CNDCR] = 0x018c,
322 [CEFCR] = 0x0194,
323 [FRECR] = 0x0198,
324 [TSFRCR] = 0x019c,
325 [TLFRCR] = 0x01a0,
326 [RFCR] = 0x01a4,
327 [MAFCR] = 0x01a8,
328 [IPGR] = 0x01b4,
329 [APR] = 0x01b8,
330 [MPR] = 0x01bc,
331 [TPAUSER] = 0x01c4,
332 [BCFR] = 0x01cc,
333
334 [ARSTR] = 0x0000,
335 [TSU_CTRST] = 0x0004,
336 [TSU_FWEN0] = 0x0010,
337 [TSU_FWEN1] = 0x0014,
338 [TSU_FCM] = 0x0018,
339 [TSU_BSYSL0] = 0x0020,
340 [TSU_BSYSL1] = 0x0024,
341 [TSU_PRISL0] = 0x0028,
342 [TSU_PRISL1] = 0x002c,
343 [TSU_FWSL0] = 0x0030,
344 [TSU_FWSL1] = 0x0034,
345 [TSU_FWSLC] = 0x0038,
346 [TSU_QTAGM0] = 0x0040,
347 [TSU_QTAGM1] = 0x0044,
348 [TSU_ADQT0] = 0x0048,
349 [TSU_ADQT1] = 0x004c,
350 [TSU_FWSR] = 0x0050,
351 [TSU_FWINMK] = 0x0054,
352 [TSU_ADSBSY] = 0x0060,
353 [TSU_TEN] = 0x0064,
354 [TSU_POST1] = 0x0070,
355 [TSU_POST2] = 0x0074,
356 [TSU_POST3] = 0x0078,
357 [TSU_POST4] = 0x007c,
358
359 [TXNLCR0] = 0x0080,
360 [TXALCR0] = 0x0084,
361 [RXNLCR0] = 0x0088,
362 [RXALCR0] = 0x008c,
363 [FWNLCR0] = 0x0090,
364 [FWALCR0] = 0x0094,
365 [TXNLCR1] = 0x00a0,
366 [TXALCR1] = 0x00a0,
367 [RXNLCR1] = 0x00a8,
368 [RXALCR1] = 0x00ac,
369 [FWNLCR1] = 0x00b0,
370 [FWALCR1] = 0x00b4,
371
372 [TSU_ADRH0] = 0x0100,
373 [TSU_ADRL0] = 0x0104,
374 [TSU_ADRL31] = 0x01fc,
375};
376
504c8ca5 377static bool sh_eth_is_gether(struct sh_eth_private *mdp)
dabdde9e 378{
504c8ca5 379 return mdp->reg_offset == sh_eth_offset_gigabit;
dabdde9e
NI		 380}
381
db893473
SH		 382static bool sh_eth_is_rz_fast_ether(struct sh_eth_private *mdp)
383{
384 return mdp->reg_offset == sh_eth_offset_fast_rz;
385}
386
8e994402 387static void sh_eth_select_mii(struct net_device *ndev)
5e7a76be
NI		 388{
389 u32 value = 0x0;
390 struct sh_eth_private *mdp = netdev_priv(ndev);
391
392 switch (mdp->phy_interface) {
393 case PHY_INTERFACE_MODE_GMII:
394 value = 0x2;
395 break;
396 case PHY_INTERFACE_MODE_MII:
397 value = 0x1;
398 break;
399 case PHY_INTERFACE_MODE_RMII:
400 value = 0x0;
401 break;
402 default:
f75f14ec
SS		 403 netdev_warn(ndev,
404 "PHY interface mode was not setup. Set to MII.\n");
5e7a76be
NI		 405 value = 0x1;
406 break;
407 }
408
409 sh_eth_write(ndev, value, RMII_MII);
410}
5e7a76be 411
8e994402 412static void sh_eth_set_duplex(struct net_device *ndev)
65ac8851
YS		 413{
414 struct sh_eth_private *mdp = netdev_priv(ndev);
65ac8851
YS		 415
416 if (mdp->duplex) /* Full */
4a55530f 417 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
65ac8851 418 else /* Half */
4a55530f 419 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
65ac8851
YS		 420}
421
04b0ed2a 422/* There is CPU dependent code */
589ebdef 423static void sh_eth_set_rate_r8a777x(struct net_device *ndev)
65ac8851
YS		 424{
425 struct sh_eth_private *mdp = netdev_priv(ndev);
d0418bb7 426
a3f109bd
SS		 427 switch (mdp->speed) {
428 case 10: /* 10BASE */
429 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_ELB, ECMR);
430 break;
431 case 100:/* 100BASE */
432 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_ELB, ECMR);
433 break;
434 default:
435 break;
436 }
437}
438
674853b2 439/* R8A7778/9 */
589ebdef 440static struct sh_eth_cpu_data r8a777x_data = {
a3f109bd 441 .set_duplex = sh_eth_set_duplex,
589ebdef 442 .set_rate = sh_eth_set_rate_r8a777x,
a3f109bd 443
a3153d8c
SS		 444 .register_type = SH_ETH_REG_FAST_RCAR,
445
a3f109bd
SS		 446 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
447 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
448 .eesipr_value = 0x01ff009f,
449
450 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
ca8c3585
SS		 451 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
452 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
453 EESR_ECI,
a3f109bd
SS		 454
455 .apr = 1,
456 .mpr = 1,
457 .tpauser = 1,
458 .hw_swap = 1,
459};
a3f109bd 460
94a12b15
SS		 461/* R8A7790/1 */
462static struct sh_eth_cpu_data r8a779x_data = {
e18dbf7e
SH		 463 .set_duplex = sh_eth_set_duplex,
464 .set_rate = sh_eth_set_rate_r8a777x,
465
a3153d8c
SS		 466 .register_type = SH_ETH_REG_FAST_RCAR,
467
e18dbf7e
SH		 468 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
469 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
470 .eesipr_value = 0x01ff009f,
471
472 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
ba361cb3
LP		 473 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
474 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
475 EESR_ECI,
e18dbf7e
SH		 476
477 .apr = 1,
478 .mpr = 1,
479 .tpauser = 1,
480 .hw_swap = 1,
481 .rmiimode = 1,
fd9af07c 482 .shift_rd0 = 1,
e18dbf7e
SH		 483};
484
9c3beaab 485static void sh_eth_set_rate_sh7724(struct net_device *ndev)
a3f109bd
SS		 486{
487 struct sh_eth_private *mdp = netdev_priv(ndev);
65ac8851
YS		 488
489 switch (mdp->speed) {
490 case 10: /* 10BASE */
a3f109bd 491 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_RTM, ECMR);
65ac8851
YS		 492 break;
493 case 100:/* 100BASE */
a3f109bd 494 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_RTM, ECMR);
65ac8851
YS		 495 break;
496 default:
497 break;
498 }
499}
500
501/* SH7724 */
9c3beaab 502static struct sh_eth_cpu_data sh7724_data = {
65ac8851 503 .set_duplex = sh_eth_set_duplex,
9c3beaab 504 .set_rate = sh_eth_set_rate_sh7724,
65ac8851 505
a3153d8c
SS		 506 .register_type = SH_ETH_REG_FAST_SH4,
507
65ac8851
YS		 508 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
509 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
a80c3de7 510 .eesipr_value = 0x01ff009f,
65ac8851
YS		 511
512 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
ca8c3585
SS		 513 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
514 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
515 EESR_ECI,
65ac8851
YS		 516
517 .apr = 1,
518 .mpr = 1,
519 .tpauser = 1,
520 .hw_swap = 1,
503914cf
MD		 521 .rpadir = 1,
522 .rpadir_value = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
65ac8851 523};
5cee1d37 524
24549e2a 525static void sh_eth_set_rate_sh7757(struct net_device *ndev)
f29a3d04
YS		 526{
527 struct sh_eth_private *mdp = netdev_priv(ndev);
f29a3d04
YS		 528
529 switch (mdp->speed) {
530 case 10: /* 10BASE */
4a55530f 531 sh_eth_write(ndev, 0, RTRATE);
f29a3d04
YS		 532 break;
533 case 100:/* 100BASE */
4a55530f 534 sh_eth_write(ndev, 1, RTRATE);
f29a3d04
YS		 535 break;
536 default:
537 break;
538 }
539}
540
541/* SH7757 */
24549e2a
SS		 542static struct sh_eth_cpu_data sh7757_data = {
543 .set_duplex = sh_eth_set_duplex,
544 .set_rate = sh_eth_set_rate_sh7757,
f29a3d04 545
a3153d8c
SS		 546 .register_type = SH_ETH_REG_FAST_SH4,
547
f29a3d04 548 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
305a3388 549 .rmcr_value = RMCR_RNC,
f29a3d04
YS		 550
551 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
ca8c3585
SS		 552 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
553 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
554 EESR_ECI,
f29a3d04 555
5b3dfd13 556 .irq_flags = IRQF_SHARED,
f29a3d04
YS		 557 .apr = 1,
558 .mpr = 1,
559 .tpauser = 1,
560 .hw_swap = 1,
561 .no_ade = 1,
2e98e797
YS		 562 .rpadir = 1,
563 .rpadir_value = 2 << 16,
f29a3d04 564};
65ac8851 565
e403d295 566#define SH_GIGA_ETH_BASE 0xfee00000UL
8fcd4961
YS		 567#define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
568#define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
569static void sh_eth_chip_reset_giga(struct net_device *ndev)
570{
571 int i;
572 unsigned long mahr[2], malr[2];
573
574 /* save MAHR and MALR */
575 for (i = 0; i < 2; i++) {
ae70644d
YS		 576 malr[i] = ioread32((void *)GIGA_MALR(i));
577 mahr[i] = ioread32((void *)GIGA_MAHR(i));
8fcd4961
YS		 578 }
579
580 /* reset device */
ae70644d 581 iowrite32(ARSTR_ARSTR, (void *)(SH_GIGA_ETH_BASE + 0x1800));
8fcd4961
YS		 582 mdelay(1);
583
584 /* restore MAHR and MALR */
585 for (i = 0; i < 2; i++) {
ae70644d
YS		 586 iowrite32(malr[i], (void *)GIGA_MALR(i));
587 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
8fcd4961
YS		 588 }
589}
590
8fcd4961
YS		 591static void sh_eth_set_rate_giga(struct net_device *ndev)
592{
593 struct sh_eth_private *mdp = netdev_priv(ndev);
594
595 switch (mdp->speed) {
596 case 10: /* 10BASE */
597 sh_eth_write(ndev, 0x00000000, GECMR);
598 break;
599 case 100:/* 100BASE */
600 sh_eth_write(ndev, 0x00000010, GECMR);
601 break;
602 case 1000: /* 1000BASE */
603 sh_eth_write(ndev, 0x00000020, GECMR);
604 break;
605 default:
606 break;
607 }
608}
609
610/* SH7757(GETHERC) */
24549e2a 611static struct sh_eth_cpu_data sh7757_data_giga = {
8fcd4961 612 .chip_reset = sh_eth_chip_reset_giga,
04b0ed2a 613 .set_duplex = sh_eth_set_duplex,
8fcd4961
YS		 614 .set_rate = sh_eth_set_rate_giga,
615
a3153d8c
SS		 616 .register_type = SH_ETH_REG_GIGABIT,
617
8fcd4961
YS		 618 .ecsr_value = ECSR_ICD | ECSR_MPD,
619 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
620 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
621
622 .tx_check = EESR_TC1 | EESR_FTC,
ca8c3585
SS		 623 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
624 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
625 EESR_TDE | EESR_ECI,
8fcd4961 626 .fdr_value = 0x0000072f,
305a3388 627 .rmcr_value = RMCR_RNC,
8fcd4961 628
5b3dfd13 629 .irq_flags = IRQF_SHARED,
8fcd4961
YS		 630 .apr = 1,
631 .mpr = 1,
632 .tpauser = 1,
633 .bculr = 1,
634 .hw_swap = 1,
635 .rpadir = 1,
636 .rpadir_value = 2 << 16,
637 .no_trimd = 1,
638 .no_ade = 1,
3acbc971 639 .tsu = 1,
8fcd4961
YS		 640};
641
380af9e3
YS		 642static void sh_eth_chip_reset(struct net_device *ndev)
643{
4986b996
YS		 644 struct sh_eth_private *mdp = netdev_priv(ndev);
645
380af9e3 646 /* reset device */
4986b996 647 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
380af9e3
YS		 648 mdelay(1);
649}
650
f5d12767 651static void sh_eth_set_rate_gether(struct net_device *ndev)
380af9e3
YS		 652{
653 struct sh_eth_private *mdp = netdev_priv(ndev);
380af9e3
YS		 654
655 switch (mdp->speed) {
656 case 10: /* 10BASE */
4a55530f 657 sh_eth_write(ndev, GECMR_10, GECMR);
380af9e3
YS		 658 break;
659 case 100:/* 100BASE */
4a55530f 660 sh_eth_write(ndev, GECMR_100, GECMR);
380af9e3
YS		 661 break;
662 case 1000: /* 1000BASE */
4a55530f 663 sh_eth_write(ndev, GECMR_1000, GECMR);
380af9e3
YS		 664 break;
665 default:
666 break;
667 }
668}
669
f5d12767
SS		 670/* SH7734 */
671static struct sh_eth_cpu_data sh7734_data = {
380af9e3
YS		 672 .chip_reset = sh_eth_chip_reset,
673 .set_duplex = sh_eth_set_duplex,
f5d12767
SS		 674 .set_rate = sh_eth_set_rate_gether,
675
a3153d8c
SS		 676 .register_type = SH_ETH_REG_GIGABIT,
677
f5d12767
SS		 678 .ecsr_value = ECSR_ICD | ECSR_MPD,
679 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
680 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
681
682 .tx_check = EESR_TC1 | EESR_FTC,
ca8c3585
SS		 683 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
684 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
685 EESR_TDE | EESR_ECI,
f5d12767
SS		 686
687 .apr = 1,
688 .mpr = 1,
689 .tpauser = 1,
690 .bculr = 1,
691 .hw_swap = 1,
692 .no_trimd = 1,
693 .no_ade = 1,
694 .tsu = 1,
695 .hw_crc = 1,
696 .select_mii = 1,
697};
698
699/* SH7763 */
700static struct sh_eth_cpu_data sh7763_data = {
701 .chip_reset = sh_eth_chip_reset,
702 .set_duplex = sh_eth_set_duplex,
703 .set_rate = sh_eth_set_rate_gether,
380af9e3 704
a3153d8c
SS		 705 .register_type = SH_ETH_REG_GIGABIT,
706
380af9e3
YS		 707 .ecsr_value = ECSR_ICD | ECSR_MPD,
708 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
709 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
710
711 .tx_check = EESR_TC1 | EESR_FTC,
128296fc
SS		 712 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
713 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
380af9e3 714 EESR_ECI,
380af9e3
YS		 715
716 .apr = 1,
717 .mpr = 1,
718 .tpauser = 1,
719 .bculr = 1,
720 .hw_swap = 1,
380af9e3
YS		 721 .no_trimd = 1,
722 .no_ade = 1,
4986b996 723 .tsu = 1,
5b3dfd13 724 .irq_flags = IRQF_SHARED,
380af9e3
YS		 725};
726
e5c9b4cd 727static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
73a0d907
YS		 728{
729 struct sh_eth_private *mdp = netdev_priv(ndev);
73a0d907
YS		 730
731 /* reset device */
732 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
733 mdelay(1);
734
5e7a76be 735 sh_eth_select_mii(ndev);
73a0d907
YS		 736}
737
73a0d907 738/* R8A7740 */
e5c9b4cd
SS		 739static struct sh_eth_cpu_data r8a7740_data = {
740 .chip_reset = sh_eth_chip_reset_r8a7740,
73a0d907 741 .set_duplex = sh_eth_set_duplex,
e5c9b4cd 742 .set_rate = sh_eth_set_rate_gether,
73a0d907 743
a3153d8c
SS		 744 .register_type = SH_ETH_REG_GIGABIT,
745
73a0d907
YS		 746 .ecsr_value = ECSR_ICD | ECSR_MPD,
747 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
748 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
749
750 .tx_check = EESR_TC1 | EESR_FTC,
ca8c3585
SS		 751 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
752 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
753 EESR_TDE | EESR_ECI,
cc23528d 754 .fdr_value = 0x0000070f,
305a3388 755 .rmcr_value = RMCR_RNC,
73a0d907
YS		 756
757 .apr = 1,
758 .mpr = 1,
759 .tpauser = 1,
760 .bculr = 1,
761 .hw_swap = 1,
cc23528d
SH		 762 .rpadir = 1,
763 .rpadir_value = 2 << 16,
73a0d907
YS		 764 .no_trimd = 1,
765 .no_ade = 1,
766 .tsu = 1,
5e7a76be 767 .select_mii = 1,
ac8025a6 768 .shift_rd0 = 1,
73a0d907
YS		 769};
770
db893473
SH		 771/* R7S72100 */
772static struct sh_eth_cpu_data r7s72100_data = {
773 .chip_reset = sh_eth_chip_reset,
774 .set_duplex = sh_eth_set_duplex,
775
776 .register_type = SH_ETH_REG_FAST_RZ,
777
778 .ecsr_value = ECSR_ICD,
779 .ecsipr_value = ECSIPR_ICDIP,
780 .eesipr_value = 0xff7f009f,
781
782 .tx_check = EESR_TC1 | EESR_FTC,
783 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
784 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
785 EESR_TDE | EESR_ECI,
786 .fdr_value = 0x0000070f,
787 .rmcr_value = RMCR_RNC,
788
789 .no_psr = 1,
790 .apr = 1,
791 .mpr = 1,
792 .tpauser = 1,
793 .hw_swap = 1,
794 .rpadir = 1,
795 .rpadir_value = 2 << 16,
796 .no_trimd = 1,
797 .no_ade = 1,
798 .hw_crc = 1,
799 .tsu = 1,
800 .shift_rd0 = 1,
801};
802
c18a79ab 803static struct sh_eth_cpu_data sh7619_data = {
a3153d8c
SS		 804 .register_type = SH_ETH_REG_FAST_SH3_SH2,
805
380af9e3
YS		 806 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
807
808 .apr = 1,
809 .mpr = 1,
810 .tpauser = 1,
811 .hw_swap = 1,
812};
7bbe150d
SS		 813
814static struct sh_eth_cpu_data sh771x_data = {
a3153d8c
SS		 815 .register_type = SH_ETH_REG_FAST_SH3_SH2,
816
380af9e3 817 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
4986b996 818 .tsu = 1,
380af9e3 819};
380af9e3
YS		 820
821static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
822{
823 if (!cd->ecsr_value)
824 cd->ecsr_value = DEFAULT_ECSR_INIT;
825
826 if (!cd->ecsipr_value)
827 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
828
829 if (!cd->fcftr_value)
128296fc 830 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF |
380af9e3
YS		 831 DEFAULT_FIFO_F_D_RFD;
832
833 if (!cd->fdr_value)
834 cd->fdr_value = DEFAULT_FDR_INIT;
835
836 if (!cd->rmcr_value)
837 cd->rmcr_value = DEFAULT_RMCR_VALUE;
838
839 if (!cd->tx_check)
840 cd->tx_check = DEFAULT_TX_CHECK;
841
842 if (!cd->eesr_err_check)
843 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
380af9e3
YS		 844}
845
5cee1d37
NI		 846static int sh_eth_check_reset(struct net_device *ndev)
847{
848 int ret = 0;
849 int cnt = 100;
850
851 while (cnt > 0) {
852 if (!(sh_eth_read(ndev, EDMR) & 0x3))
853 break;
854 mdelay(1);
855 cnt--;
856 }
9f8c4265 857 if (cnt <= 0) {
f75f14ec 858 netdev_err(ndev, "Device reset failed\n");
5cee1d37
NI		 859 ret = -ETIMEDOUT;
860 }
861 return ret;
380af9e3 862}
dabdde9e
NI		 863
864static int sh_eth_reset(struct net_device *ndev)
865{
866 struct sh_eth_private *mdp = netdev_priv(ndev);
867 int ret = 0;
868
db893473 869 if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp)) {
dabdde9e
NI		 870 sh_eth_write(ndev, EDSR_ENALL, EDSR);
871 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER,
872 EDMR);
873
874 ret = sh_eth_check_reset(ndev);
875 if (ret)
876 goto out;
877
878 /* Table Init */
879 sh_eth_write(ndev, 0x0, TDLAR);
880 sh_eth_write(ndev, 0x0, TDFAR);
881 sh_eth_write(ndev, 0x0, TDFXR);
882 sh_eth_write(ndev, 0x0, TDFFR);
883 sh_eth_write(ndev, 0x0, RDLAR);
884 sh_eth_write(ndev, 0x0, RDFAR);
885 sh_eth_write(ndev, 0x0, RDFXR);
886 sh_eth_write(ndev, 0x0, RDFFR);
887
888 /* Reset HW CRC register */
889 if (mdp->cd->hw_crc)
890 sh_eth_write(ndev, 0x0, CSMR);
891
892 /* Select MII mode */
893 if (mdp->cd->select_mii)
894 sh_eth_select_mii(ndev);
895 } else {
896 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER,
897 EDMR);
898 mdelay(3);
899 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER,
900 EDMR);
901 }
902
903out:
904 return ret;
905}
380af9e3 906
73a0d907 907#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
380af9e3
YS		 908static void sh_eth_set_receive_align(struct sk_buff *skb)
909{
910 int reserve;
911
912 reserve = SH4_SKB_RX_ALIGN - ((u32)skb->data & (SH4_SKB_RX_ALIGN - 1));
913 if (reserve)
914 skb_reserve(skb, reserve);
915}
916#else
917static void sh_eth_set_receive_align(struct sk_buff *skb)
918{
919 skb_reserve(skb, SH2_SH3_SKB_RX_ALIGN);
920}
921#endif
922
923
71557a37
YS		 924/* CPU <-> EDMAC endian convert */
925static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x)
926{
927 switch (mdp->edmac_endian) {
928 case EDMAC_LITTLE_ENDIAN:
929 return cpu_to_le32(x);
930 case EDMAC_BIG_ENDIAN:
931 return cpu_to_be32(x);
932 }
933 return x;
934}
935
936static inline __u32 edmac_to_cpu(struct sh_eth_private *mdp, u32 x)
937{
938 switch (mdp->edmac_endian) {
939 case EDMAC_LITTLE_ENDIAN:
940 return le32_to_cpu(x);
941 case EDMAC_BIG_ENDIAN:
942 return be32_to_cpu(x);
943 }
944 return x;
945}
946
128296fc 947/* Program the hardware MAC address from dev->dev_addr. */
86a74ff2
NI		 948static void update_mac_address(struct net_device *ndev)
949{
4a55530f 950 sh_eth_write(ndev,
128296fc
SS		 951 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
952 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
4a55530f 953 sh_eth_write(ndev,
128296fc 954 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
86a74ff2
NI		 955}
956
128296fc 957/* Get MAC address from SuperH MAC address register
86a74ff2
NI		 958 *
959 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
960 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
961 * When you want use this device, you must set MAC address in bootloader.
962 *
963 */
748031f9 964static void read_mac_address(struct net_device *ndev, unsigned char *mac)
86a74ff2 965{
748031f9 966 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
d458cdf7 967 memcpy(ndev->dev_addr, mac, ETH_ALEN);
748031f9 968 } else {
4a55530f
YS		 969 ndev->dev_addr[0] = (sh_eth_read(ndev, MAHR) >> 24);
970 ndev->dev_addr[1] = (sh_eth_read(ndev, MAHR) >> 16) & 0xFF;
971 ndev->dev_addr[2] = (sh_eth_read(ndev, MAHR) >> 8) & 0xFF;
972 ndev->dev_addr[3] = (sh_eth_read(ndev, MAHR) & 0xFF);
973 ndev->dev_addr[4] = (sh_eth_read(ndev, MALR) >> 8) & 0xFF;
974 ndev->dev_addr[5] = (sh_eth_read(ndev, MALR) & 0xFF);
748031f9 975 }
86a74ff2
NI		 976}
977
c5ed5368
YS		 978static unsigned long sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
979{
db893473 980 if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp))
c5ed5368
YS		 981 return EDTRR_TRNS_GETHER;
982 else
983 return EDTRR_TRNS_ETHER;
984}
985
86a74ff2 986struct bb_info {
ae70644d 987 void (*set_gate)(void *addr);
86a74ff2 988 struct mdiobb_ctrl ctrl;
ae70644d 989 void *addr;
86a74ff2
NI		 990 u32 mmd_msk;/* MMD */
991 u32 mdo_msk;
992 u32 mdi_msk;
993 u32 mdc_msk;
994};
995
996/* PHY bit set */
ae70644d 997static void bb_set(void *addr, u32 msk)
86a74ff2 998{
ae70644d 999 iowrite32(ioread32(addr) | msk, addr);
86a74ff2
NI		 1000}
1001
1002/* PHY bit clear */
ae70644d 1003static void bb_clr(void *addr, u32 msk)
86a74ff2 1004{
ae70644d 1005 iowrite32((ioread32(addr) & ~msk), addr);
86a74ff2
NI		 1006}
1007
1008/* PHY bit read */
ae70644d 1009static int bb_read(void *addr, u32 msk)
86a74ff2 1010{
ae70644d 1011 return (ioread32(addr) & msk) != 0;
86a74ff2
NI		 1012}
1013
1014/* Data I/O pin control */
1015static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1016{
1017 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
b3017e6a
YS		 1018
1019 if (bitbang->set_gate)
1020 bitbang->set_gate(bitbang->addr);
1021
86a74ff2
NI		 1022 if (bit)
1023 bb_set(bitbang->addr, bitbang->mmd_msk);
1024 else
1025 bb_clr(bitbang->addr, bitbang->mmd_msk);
1026}
1027
1028/* Set bit data*/
1029static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
1030{
1031 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1032
b3017e6a
YS		 1033 if (bitbang->set_gate)
1034 bitbang->set_gate(bitbang->addr);
1035
86a74ff2
NI		 1036 if (bit)
1037 bb_set(bitbang->addr, bitbang->mdo_msk);
1038 else
1039 bb_clr(bitbang->addr, bitbang->mdo_msk);
1040}
1041
1042/* Get bit data*/
1043static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
1044{
1045 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
b3017e6a
YS		 1046
1047 if (bitbang->set_gate)
1048 bitbang->set_gate(bitbang->addr);
1049
86a74ff2
NI		 1050 return bb_read(bitbang->addr, bitbang->mdi_msk);
1051}
1052
1053/* MDC pin control */
1054static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1055{
1056 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1057
b3017e6a
YS		 1058 if (bitbang->set_gate)
1059 bitbang->set_gate(bitbang->addr);
1060
86a74ff2
NI		 1061 if (bit)
1062 bb_set(bitbang->addr, bitbang->mdc_msk);
1063 else
1064 bb_clr(bitbang->addr, bitbang->mdc_msk);
1065}
1066
1067/* mdio bus control struct */
1068static struct mdiobb_ops bb_ops = {
1069 .owner = THIS_MODULE,
1070 .set_mdc = sh_mdc_ctrl,
1071 .set_mdio_dir = sh_mmd_ctrl,
1072 .set_mdio_data = sh_set_mdio,
1073 .get_mdio_data = sh_get_mdio,
1074};
1075
86a74ff2
NI		 1076/* free skb and descriptor buffer */
1077static void sh_eth_ring_free(struct net_device *ndev)
1078{
1079 struct sh_eth_private *mdp = netdev_priv(ndev);
1080 int i;
1081
1082 /* Free Rx skb ringbuffer */
1083 if (mdp->rx_skbuff) {
525b8075 1084 for (i = 0; i < mdp->num_rx_ring; i++) {
86a74ff2
NI		 1085 if (mdp->rx_skbuff[i])
1086 dev_kfree_skb(mdp->rx_skbuff[i]);
1087 }
1088 }
1089 kfree(mdp->rx_skbuff);
91c77550 1090 mdp->rx_skbuff = NULL;
86a74ff2
NI		 1091
1092 /* Free Tx skb ringbuffer */
1093 if (mdp->tx_skbuff) {
525b8075 1094 for (i = 0; i < mdp->num_tx_ring; i++) {
86a74ff2
NI		 1095 if (mdp->tx_skbuff[i])
1096 dev_kfree_skb(mdp->tx_skbuff[i]);
1097 }
1098 }
1099 kfree(mdp->tx_skbuff);
91c77550 1100 mdp->tx_skbuff = NULL;
86a74ff2
NI		 1101}
1102
1103/* format skb and descriptor buffer */
1104static void sh_eth_ring_format(struct net_device *ndev)
1105{
1106 struct sh_eth_private *mdp = netdev_priv(ndev);
1107 int i;
1108 struct sk_buff *skb;
1109 struct sh_eth_rxdesc *rxdesc = NULL;
1110 struct sh_eth_txdesc *txdesc = NULL;
525b8075
YS		 1111 int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
1112 int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
86a74ff2 1113
128296fc
SS		 1114 mdp->cur_rx = 0;
1115 mdp->cur_tx = 0;
1116 mdp->dirty_rx = 0;
1117 mdp->dirty_tx = 0;
86a74ff2
NI		 1118
1119 memset(mdp->rx_ring, 0, rx_ringsize);
1120
1121 /* build Rx ring buffer */
525b8075 1122 for (i = 0; i < mdp->num_rx_ring; i++) {
86a74ff2
NI		 1123 /* skb */
1124 mdp->rx_skbuff[i] = NULL;
dae2e9f4 1125 skb = netdev_alloc_skb(ndev, mdp->rx_buf_sz);
86a74ff2
NI		 1126 mdp->rx_skbuff[i] = skb;
1127 if (skb == NULL)
1128 break;
bb7d92e3 1129 dma_map_single(&ndev->dev, skb->data, mdp->rx_buf_sz,
128296fc 1130 DMA_FROM_DEVICE);
380af9e3
YS		 1131 sh_eth_set_receive_align(skb);
1132
86a74ff2
NI		 1133 /* RX descriptor */
1134 rxdesc = &mdp->rx_ring[i];
0029d64a 1135 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
71557a37 1136 rxdesc->status = cpu_to_edmac(mdp, RD_RACT | RD_RFP);
86a74ff2
NI		 1137
1138 /* The size of the buffer is 16 byte boundary. */
0029d64a 1139 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
b0ca2a21
NI		 1140 /* Rx descriptor address set */
1141 if (i == 0) {
4a55530f 1142 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
db893473
SH		 1143 if (sh_eth_is_gether(mdp) ||
1144 sh_eth_is_rz_fast_ether(mdp))
c5ed5368 1145 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
b0ca2a21 1146 }
86a74ff2
NI		 1147 }
1148
525b8075 1149 mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
86a74ff2
NI		 1150
1151 /* Mark the last entry as wrapping the ring. */
71557a37 1152 rxdesc->status |= cpu_to_edmac(mdp, RD_RDEL);
86a74ff2
NI		 1153
1154 memset(mdp->tx_ring, 0, tx_ringsize);
1155
1156 /* build Tx ring buffer */
525b8075 1157 for (i = 0; i < mdp->num_tx_ring; i++) {
86a74ff2
NI		 1158 mdp->tx_skbuff[i] = NULL;
1159 txdesc = &mdp->tx_ring[i];
71557a37 1160 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
86a74ff2 1161 txdesc->buffer_length = 0;
b0ca2a21 1162 if (i == 0) {
71557a37 1163 /* Tx descriptor address set */
4a55530f 1164 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
db893473
SH		 1165 if (sh_eth_is_gether(mdp) ||
1166 sh_eth_is_rz_fast_ether(mdp))
c5ed5368 1167 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
b0ca2a21 1168 }
86a74ff2
NI		 1169 }
1170
71557a37 1171 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
86a74ff2
NI		 1172}
1173
1174/* Get skb and descriptor buffer */
1175static int sh_eth_ring_init(struct net_device *ndev)
1176{
1177 struct sh_eth_private *mdp = netdev_priv(ndev);
1178 int rx_ringsize, tx_ringsize, ret = 0;
1179
128296fc 1180 /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
86a74ff2
NI		 1181 * card needs room to do 8 byte alignment, +2 so we can reserve
1182 * the first 2 bytes, and +16 gets room for the status word from the
1183 * card.
1184 */
1185 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
1186 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
503914cf
MD		 1187 if (mdp->cd->rpadir)
1188 mdp->rx_buf_sz += NET_IP_ALIGN;
86a74ff2
NI		 1189
1190 /* Allocate RX and TX skb rings */
b2adaca9
JP		 1191 mdp->rx_skbuff = kmalloc_array(mdp->num_rx_ring,
1192 sizeof(*mdp->rx_skbuff), GFP_KERNEL);
86a74ff2 1193 if (!mdp->rx_skbuff) {
86a74ff2
NI		 1194 ret = -ENOMEM;
1195 return ret;
1196 }
1197
b2adaca9
JP		 1198 mdp->tx_skbuff = kmalloc_array(mdp->num_tx_ring,
1199 sizeof(*mdp->tx_skbuff), GFP_KERNEL);
86a74ff2 1200 if (!mdp->tx_skbuff) {
86a74ff2
NI		 1201 ret = -ENOMEM;
1202 goto skb_ring_free;
1203 }
1204
1205 /* Allocate all Rx descriptors. */
525b8075 1206 rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
86a74ff2 1207 mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
d0320f75 1208 GFP_KERNEL);
86a74ff2 1209 if (!mdp->rx_ring) {
86a74ff2
NI		 1210 ret = -ENOMEM;
1211 goto desc_ring_free;
1212 }
1213
1214 mdp->dirty_rx = 0;
1215
1216 /* Allocate all Tx descriptors. */
525b8075 1217 tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
86a74ff2 1218 mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
d0320f75 1219 GFP_KERNEL);
86a74ff2 1220 if (!mdp->tx_ring) {
86a74ff2
NI		 1221 ret = -ENOMEM;
1222 goto desc_ring_free;
1223 }
1224 return ret;
1225
1226desc_ring_free:
1227 /* free DMA buffer */
1228 dma_free_coherent(NULL, rx_ringsize, mdp->rx_ring, mdp->rx_desc_dma);
1229
1230skb_ring_free:
1231 /* Free Rx and Tx skb ring buffer */
1232 sh_eth_ring_free(ndev);
91c77550
YS		 1233 mdp->tx_ring = NULL;
1234 mdp->rx_ring = NULL;
86a74ff2
NI		 1235
1236 return ret;
1237}
1238
91c77550
YS		 1239static void sh_eth_free_dma_buffer(struct sh_eth_private *mdp)
1240{
1241 int ringsize;
1242
1243 if (mdp->rx_ring) {
525b8075 1244 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
91c77550
YS		 1245 dma_free_coherent(NULL, ringsize, mdp->rx_ring,
1246 mdp->rx_desc_dma);
1247 mdp->rx_ring = NULL;
1248 }
1249
1250 if (mdp->tx_ring) {
525b8075 1251 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
91c77550
YS		 1252 dma_free_coherent(NULL, ringsize, mdp->tx_ring,
1253 mdp->tx_desc_dma);
1254 mdp->tx_ring = NULL;
1255 }
1256}
1257
525b8075 1258static int sh_eth_dev_init(struct net_device *ndev, bool start)
86a74ff2
NI		 1259{
1260 int ret = 0;
1261 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 1262 u32 val;
1263
1264 /* Soft Reset */
5cee1d37
NI		 1265 ret = sh_eth_reset(ndev);
1266 if (ret)
1267 goto out;
86a74ff2 1268
55754f19
SH		 1269 if (mdp->cd->rmiimode)
1270 sh_eth_write(ndev, 0x1, RMIIMODE);
1271
b0ca2a21
NI		 1272 /* Descriptor format */
1273 sh_eth_ring_format(ndev);
380af9e3 1274 if (mdp->cd->rpadir)
4a55530f 1275 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
86a74ff2
NI		 1276
1277 /* all sh_eth int mask */
4a55530f 1278 sh_eth_write(ndev, 0, EESIPR);
86a74ff2 1279
10b9194f 1280#if defined(__LITTLE_ENDIAN)
380af9e3 1281 if (mdp->cd->hw_swap)
4a55530f 1282 sh_eth_write(ndev, EDMR_EL, EDMR);
380af9e3 1283 else
b0ca2a21 1284#endif
4a55530f 1285 sh_eth_write(ndev, 0, EDMR);
86a74ff2 1286
b0ca2a21 1287 /* FIFO size set */
4a55530f
YS		 1288 sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
1289 sh_eth_write(ndev, 0, TFTR);
86a74ff2 1290
b0ca2a21 1291 /* Frame recv control */
4a55530f 1292 sh_eth_write(ndev, mdp->cd->rmcr_value, RMCR);
86a74ff2 1293
2ecbb783 1294 sh_eth_write(ndev, DESC_I_RINT8 | DESC_I_RINT5 | DESC_I_TINT2, TRSCER);
86a74ff2 1295
380af9e3 1296 if (mdp->cd->bculr)
4a55530f 1297 sh_eth_write(ndev, 0x800, BCULR); /* Burst sycle set */
b0ca2a21 1298
4a55530f 1299 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
86a74ff2 1300
380af9e3 1301 if (!mdp->cd->no_trimd)
4a55530f 1302 sh_eth_write(ndev, 0, TRIMD);
86a74ff2 1303
b0ca2a21 1304 /* Recv frame limit set register */
fdb37a7f
YS		 1305 sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1306 RFLR);
86a74ff2 1307
4a55530f 1308 sh_eth_write(ndev, sh_eth_read(ndev, EESR), EESR);
525b8075
YS		 1309 if (start)
1310 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
86a74ff2
NI		 1311
1312 /* PAUSE Prohibition */
4a55530f 1313 val = (sh_eth_read(ndev, ECMR) & ECMR_DM) |
86a74ff2
NI		 1314 ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE;
1315
4a55530f 1316 sh_eth_write(ndev, val, ECMR);
b0ca2a21 1317
380af9e3
YS		 1318 if (mdp->cd->set_rate)
1319 mdp->cd->set_rate(ndev);
1320
b0ca2a21 1321 /* E-MAC Status Register clear */
4a55530f 1322 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
b0ca2a21
NI		 1323
1324 /* E-MAC Interrupt Enable register */
525b8075
YS		 1325 if (start)
1326 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
86a74ff2
NI		 1327
1328 /* Set MAC address */
1329 update_mac_address(ndev);
1330
1331 /* mask reset */
380af9e3 1332 if (mdp->cd->apr)
4a55530f 1333 sh_eth_write(ndev, APR_AP, APR);
380af9e3 1334 if (mdp->cd->mpr)
4a55530f 1335 sh_eth_write(ndev, MPR_MP, MPR);
380af9e3 1336 if (mdp->cd->tpauser)
4a55530f 1337 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
b0ca2a21 1338
525b8075
YS		 1339 if (start) {
1340 /* Setting the Rx mode will start the Rx process. */
1341 sh_eth_write(ndev, EDRRR_R, EDRRR);
86a74ff2 1342
525b8075
YS		 1343 netif_start_queue(ndev);
1344 }
86a74ff2 1345
5cee1d37 1346out:
86a74ff2
NI		 1347 return ret;
1348}
1349
1350/* free Tx skb function */
1351static int sh_eth_txfree(struct net_device *ndev)
1352{
1353 struct sh_eth_private *mdp = netdev_priv(ndev);
1354 struct sh_eth_txdesc *txdesc;
128296fc 1355 int free_num = 0;
86a74ff2
NI		 1356 int entry = 0;
1357
1358 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
525b8075 1359 entry = mdp->dirty_tx % mdp->num_tx_ring;
86a74ff2 1360 txdesc = &mdp->tx_ring[entry];
71557a37 1361 if (txdesc->status & cpu_to_edmac(mdp, TD_TACT))
86a74ff2
NI		 1362 break;
1363 /* Free the original skb. */
1364 if (mdp->tx_skbuff[entry]) {
31fcb99d
YS		 1365 dma_unmap_single(&ndev->dev, txdesc->addr,
1366 txdesc->buffer_length, DMA_TO_DEVICE);
86a74ff2
NI		 1367 dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1368 mdp->tx_skbuff[entry] = NULL;
128296fc 1369 free_num++;
86a74ff2 1370 }
71557a37 1371 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
525b8075 1372 if (entry >= mdp->num_tx_ring - 1)
71557a37 1373 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
86a74ff2 1374
bb7d92e3
ED		 1375 ndev->stats.tx_packets++;
1376 ndev->stats.tx_bytes += txdesc->buffer_length;
86a74ff2 1377 }
128296fc 1378 return free_num;
86a74ff2
NI		 1379}
1380
1381/* Packet receive function */
3719109d 1382static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
86a74ff2
NI		 1383{
1384 struct sh_eth_private *mdp = netdev_priv(ndev);
1385 struct sh_eth_rxdesc *rxdesc;
1386
525b8075
YS		 1387 int entry = mdp->cur_rx % mdp->num_rx_ring;
1388 int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
86a74ff2 1389 struct sk_buff *skb;
3719109d 1390 int exceeded = 0;
86a74ff2 1391 u16 pkt_len = 0;
380af9e3 1392 u32 desc_status;
86a74ff2
NI		 1393
1394 rxdesc = &mdp->rx_ring[entry];
71557a37
YS		 1395 while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) {
1396 desc_status = edmac_to_cpu(mdp, rxdesc->status);
86a74ff2
NI		 1397 pkt_len = rxdesc->frame_length;
1398
1399 if (--boguscnt < 0)
1400 break;
1401
3719109d
SS		 1402 if (*quota <= 0) {
1403 exceeded = 1;
1404 break;
1405 }
1406 (*quota)--;
1407
86a74ff2 1408 if (!(desc_status & RDFEND))
bb7d92e3 1409 ndev->stats.rx_length_errors++;
86a74ff2 1410
128296fc 1411 /* In case of almost all GETHER/ETHERs, the Receive Frame State
dd019897 1412 * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
db893473
SH		 1413 * bit 0. However, in case of the R8A7740, R8A779x, and
1414 * R7S72100 the RFS bits are from bit 25 to bit 16. So, the
1415 * driver needs right shifting by 16.
dd019897 1416 */
ac8025a6
SS		 1417 if (mdp->cd->shift_rd0)
1418 desc_status >>= 16;
dd019897 1419
86a74ff2
NI		 1420 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1421 RD_RFS5 | RD_RFS6 | RD_RFS10)) {
bb7d92e3 1422 ndev->stats.rx_errors++;
86a74ff2 1423 if (desc_status & RD_RFS1)
bb7d92e3 1424 ndev->stats.rx_crc_errors++;
86a74ff2 1425 if (desc_status & RD_RFS2)
bb7d92e3 1426 ndev->stats.rx_frame_errors++;
86a74ff2 1427 if (desc_status & RD_RFS3)
bb7d92e3 1428 ndev->stats.rx_length_errors++;
86a74ff2 1429 if (desc_status & RD_RFS4)
bb7d92e3 1430 ndev->stats.rx_length_errors++;
86a74ff2 1431 if (desc_status & RD_RFS6)
bb7d92e3 1432 ndev->stats.rx_missed_errors++;
86a74ff2 1433 if (desc_status & RD_RFS10)
bb7d92e3 1434 ndev->stats.rx_over_errors++;
86a74ff2 1435 } else {
380af9e3
YS		 1436 if (!mdp->cd->hw_swap)
1437 sh_eth_soft_swap(
1438 phys_to_virt(ALIGN(rxdesc->addr, 4)),
1439 pkt_len + 2);
86a74ff2
NI		 1440 skb = mdp->rx_skbuff[entry];
1441 mdp->rx_skbuff[entry] = NULL;
503914cf
MD		 1442 if (mdp->cd->rpadir)
1443 skb_reserve(skb, NET_IP_ALIGN);
7db8e0c1
KA		 1444 dma_sync_single_for_cpu(&ndev->dev, rxdesc->addr,
1445 mdp->rx_buf_sz,
1446 DMA_FROM_DEVICE);
86a74ff2
NI		 1447 skb_put(skb, pkt_len);
1448 skb->protocol = eth_type_trans(skb, ndev);
a8e9fd0f 1449 netif_receive_skb(skb);
bb7d92e3
ED		 1450 ndev->stats.rx_packets++;
1451 ndev->stats.rx_bytes += pkt_len;
86a74ff2 1452 }
71557a37 1453 rxdesc->status |= cpu_to_edmac(mdp, RD_RACT);
525b8075 1454 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
862df497 1455 rxdesc = &mdp->rx_ring[entry];
86a74ff2
NI		 1456 }
1457
1458 /* Refill the Rx ring buffers. */
1459 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
525b8075 1460 entry = mdp->dirty_rx % mdp->num_rx_ring;
86a74ff2 1461 rxdesc = &mdp->rx_ring[entry];
b0ca2a21 1462 /* The size of the buffer is 16 byte boundary. */
0029d64a 1463 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
b0ca2a21 1464
86a74ff2 1465 if (mdp->rx_skbuff[entry] == NULL) {
dae2e9f4 1466 skb = netdev_alloc_skb(ndev, mdp->rx_buf_sz);
86a74ff2
NI		 1467 mdp->rx_skbuff[entry] = skb;
1468 if (skb == NULL)
1469 break; /* Better luck next round. */
bb7d92e3 1470 dma_map_single(&ndev->dev, skb->data, mdp->rx_buf_sz,
128296fc 1471 DMA_FROM_DEVICE);
380af9e3
YS		 1472 sh_eth_set_receive_align(skb);
1473
bc8acf2c 1474 skb_checksum_none_assert(skb);
0029d64a 1475 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
86a74ff2 1476 }
525b8075 1477 if (entry >= mdp->num_rx_ring - 1)
86a74ff2 1478 rxdesc->status |=
71557a37 1479 cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDEL);
86a74ff2
NI		 1480 else
1481 rxdesc->status |=
71557a37 1482 cpu_to_edmac(mdp, RD_RACT | RD_RFP);
86a74ff2
NI		 1483 }
1484
1485 /* Restart Rx engine if stopped. */
1486 /* If we don't need to check status, don't. -KDU */
79fba9f5 1487 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
a18e08bd 1488 /* fix the values for the next receiving if RDE is set */
128296fc
SS		 1489 if (intr_status & EESR_RDE) {
1490 u32 count = (sh_eth_read(ndev, RDFAR) -
1491 sh_eth_read(ndev, RDLAR)) >> 4;
1492
1493 mdp->cur_rx = count;
1494 mdp->dirty_rx = count;
1495 }
4a55530f 1496 sh_eth_write(ndev, EDRRR_R, EDRRR);
79fba9f5 1497 }
86a74ff2 1498
3719109d 1499 return exceeded;
86a74ff2
NI		 1500}
1501
4a55530f 1502static void sh_eth_rcv_snd_disable(struct net_device *ndev)
dc19e4e5
NI		 1503{
1504 /* disable tx and rx */
4a55530f
YS		 1505 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) &
1506 ~(ECMR_RE | ECMR_TE), ECMR);
dc19e4e5
NI		 1507}
1508
4a55530f 1509static void sh_eth_rcv_snd_enable(struct net_device *ndev)
dc19e4e5
NI		 1510{
1511 /* enable tx and rx */
4a55530f
YS		 1512 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) |
1513 (ECMR_RE | ECMR_TE), ECMR);
dc19e4e5
NI		 1514}
1515
86a74ff2
NI		 1516/* error control function */
1517static void sh_eth_error(struct net_device *ndev, int intr_status)
1518{
1519 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2 1520 u32 felic_stat;
380af9e3
YS		 1521 u32 link_stat;
1522 u32 mask;
86a74ff2
NI		 1523
1524 if (intr_status & EESR_ECI) {
4a55530f
YS		 1525 felic_stat = sh_eth_read(ndev, ECSR);
1526 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */
86a74ff2 1527 if (felic_stat & ECSR_ICD)
bb7d92e3 1528 ndev->stats.tx_carrier_errors++;
86a74ff2
NI		 1529 if (felic_stat & ECSR_LCHNG) {
1530 /* Link Changed */
4923576b 1531 if (mdp->cd->no_psr || mdp->no_ether_link) {
1e1b812b 1532 goto ignore_link;
380af9e3 1533 } else {
4a55530f 1534 link_stat = (sh_eth_read(ndev, PSR));
4923576b
YS		 1535 if (mdp->ether_link_active_low)
1536 link_stat = ~link_stat;
380af9e3 1537 }
128296fc 1538 if (!(link_stat & PHY_ST_LINK)) {
4a55530f 1539 sh_eth_rcv_snd_disable(ndev);
128296fc 1540 } else {
86a74ff2 1541 /* Link Up */
4a55530f 1542 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) &
128296fc
SS		 1543 ~DMAC_M_ECI, EESIPR);
1544 /* clear int */
4a55530f 1545 sh_eth_write(ndev, sh_eth_read(ndev, ECSR),
128296fc 1546 ECSR);
4a55530f 1547 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) |
128296fc 1548 DMAC_M_ECI, EESIPR);
86a74ff2 1549 /* enable tx and rx */
4a55530f 1550 sh_eth_rcv_snd_enable(ndev);
86a74ff2
NI		 1551 }
1552 }
1553 }
1554
1e1b812b 1555ignore_link:
86a74ff2 1556 if (intr_status & EESR_TWB) {
4eb313a7
SS		 1557 /* Unused write back interrupt */
1558 if (intr_status & EESR_TABT) { /* Transmit Abort int */
bb7d92e3 1559 ndev->stats.tx_aborted_errors++;
8d5009f6 1560 netif_err(mdp, tx_err, ndev, "Transmit Abort\n");
4eb313a7 1561 }
86a74ff2
NI		 1562 }
1563
1564 if (intr_status & EESR_RABT) {
1565 /* Receive Abort int */
1566 if (intr_status & EESR_RFRMER) {
1567 /* Receive Frame Overflow int */
bb7d92e3 1568 ndev->stats.rx_frame_errors++;
8d5009f6 1569 netif_err(mdp, rx_err, ndev, "Receive Abort\n");
86a74ff2
NI		 1570 }
1571 }
380af9e3 1572
dc19e4e5
NI		 1573 if (intr_status & EESR_TDE) {
1574 /* Transmit Descriptor Empty int */
bb7d92e3 1575 ndev->stats.tx_fifo_errors++;
8d5009f6 1576 netif_err(mdp, tx_err, ndev, "Transmit Descriptor Empty\n");
dc19e4e5
NI		 1577 }
1578
1579 if (intr_status & EESR_TFE) {
1580 /* FIFO under flow */
bb7d92e3 1581 ndev->stats.tx_fifo_errors++;
8d5009f6 1582 netif_err(mdp, tx_err, ndev, "Transmit FIFO Under flow\n");
86a74ff2
NI		 1583 }
1584
1585 if (intr_status & EESR_RDE) {
1586 /* Receive Descriptor Empty int */
bb7d92e3 1587 ndev->stats.rx_over_errors++;
8d5009f6 1588 netif_err(mdp, rx_err, ndev, "Receive Descriptor Empty\n");
86a74ff2 1589 }
dc19e4e5 1590
86a74ff2
NI		 1591 if (intr_status & EESR_RFE) {
1592 /* Receive FIFO Overflow int */
bb7d92e3 1593 ndev->stats.rx_fifo_errors++;
8d5009f6 1594 netif_err(mdp, rx_err, ndev, "Receive FIFO Overflow\n");
dc19e4e5
NI		 1595 }
1596
1597 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1598 /* Address Error */
bb7d92e3 1599 ndev->stats.tx_fifo_errors++;
8d5009f6 1600 netif_err(mdp, tx_err, ndev, "Address Error\n");
86a74ff2 1601 }
380af9e3
YS		 1602
1603 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1604 if (mdp->cd->no_ade)
1605 mask &= ~EESR_ADE;
1606 if (intr_status & mask) {
86a74ff2 1607 /* Tx error */
4a55530f 1608 u32 edtrr = sh_eth_read(ndev, EDTRR);
090d560f 1609
86a74ff2 1610 /* dmesg */
da246855
SS		 1611 netdev_err(ndev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1612 intr_status, mdp->cur_tx, mdp->dirty_tx,
1613 (u32)ndev->state, edtrr);
86a74ff2
NI		 1614 /* dirty buffer free */
1615 sh_eth_txfree(ndev);
1616
1617 /* SH7712 BUG */
c5ed5368 1618 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
86a74ff2 1619 /* tx dma start */
c5ed5368 1620 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
86a74ff2
NI		 1621 }
1622 /* wakeup */
1623 netif_wake_queue(ndev);
1624 }
1625}
1626
1627static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1628{
1629 struct net_device *ndev = netdev;
1630 struct sh_eth_private *mdp = netdev_priv(ndev);
380af9e3 1631 struct sh_eth_cpu_data *cd = mdp->cd;
0e0fde3c 1632 irqreturn_t ret = IRQ_NONE;
3719109d 1633 unsigned long intr_status, intr_enable;
86a74ff2 1634
86a74ff2
NI		 1635 spin_lock(&mdp->lock);
1636
3893b273 1637 /* Get interrupt status */
4a55530f 1638 intr_status = sh_eth_read(ndev, EESR);
3893b273
SS		 1639 /* Mask it with the interrupt mask, forcing ECI interrupt to be always
1640 * enabled since it's the one that comes thru regardless of the mask,
1641 * and we need to fully handle it in sh_eth_error() in order to quench
1642 * it as it doesn't get cleared by just writing 1 to the ECI bit...
1643 */
3719109d
SS		 1644 intr_enable = sh_eth_read(ndev, EESIPR);
1645 intr_status &= intr_enable | DMAC_M_ECI;
1646 if (intr_status & (EESR_RX_CHECK | cd->tx_check | cd->eesr_err_check))
0e0fde3c 1647 ret = IRQ_HANDLED;
3719109d 1648 else
0e0fde3c 1649 goto other_irq;
86a74ff2 1650
3719109d
SS		 1651 if (intr_status & EESR_RX_CHECK) {
1652 if (napi_schedule_prep(&mdp->napi)) {
1653 /* Mask Rx interrupts */
1654 sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK,
1655 EESIPR);
1656 __napi_schedule(&mdp->napi);
1657 } else {
da246855
SS		 1658 netdev_warn(ndev,
1659 "ignoring interrupt, status 0x%08lx, mask 0x%08lx.\n",
1660 intr_status, intr_enable);
3719109d
SS		 1661 }
1662 }
86a74ff2 1663
b0ca2a21 1664 /* Tx Check */
380af9e3 1665 if (intr_status & cd->tx_check) {
3719109d
SS		 1666 /* Clear Tx interrupts */
1667 sh_eth_write(ndev, intr_status & cd->tx_check, EESR);
1668
86a74ff2
NI		 1669 sh_eth_txfree(ndev);
1670 netif_wake_queue(ndev);
1671 }
1672
3719109d
SS		 1673 if (intr_status & cd->eesr_err_check) {
1674 /* Clear error interrupts */
1675 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR);
1676
86a74ff2 1677 sh_eth_error(ndev, intr_status);
3719109d 1678 }
86a74ff2 1679
0e0fde3c 1680other_irq:
86a74ff2
NI		 1681 spin_unlock(&mdp->lock);
1682
0e0fde3c 1683 return ret;
86a74ff2
NI		 1684}
1685
3719109d
SS		 1686static int sh_eth_poll(struct napi_struct *napi, int budget)
1687{
1688 struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private,
1689 napi);
1690 struct net_device *ndev = napi->dev;
1691 int quota = budget;
1692 unsigned long intr_status;
1693
1694 for (;;) {
1695 intr_status = sh_eth_read(ndev, EESR);
1696 if (!(intr_status & EESR_RX_CHECK))
1697 break;
1698 /* Clear Rx interrupts */
1699 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR);
1700
1701 if (sh_eth_rx(ndev, intr_status, &quota))
1702 goto out;
1703 }
1704
1705 napi_complete(napi);
1706
1707 /* Reenable Rx interrupts */
1708 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1709out:
1710 return budget - quota;
1711}
1712
86a74ff2
NI		 1713/* PHY state control function */
1714static void sh_eth_adjust_link(struct net_device *ndev)
1715{
1716 struct sh_eth_private *mdp = netdev_priv(ndev);
1717 struct phy_device *phydev = mdp->phydev;
86a74ff2
NI		 1718 int new_state = 0;
1719
3340d2aa 1720 if (phydev->link) {
86a74ff2
NI		 1721 if (phydev->duplex != mdp->duplex) {
1722 new_state = 1;
1723 mdp->duplex = phydev->duplex;
380af9e3
YS		 1724 if (mdp->cd->set_duplex)
1725 mdp->cd->set_duplex(ndev);
86a74ff2
NI		 1726 }
1727
1728 if (phydev->speed != mdp->speed) {
1729 new_state = 1;
1730 mdp->speed = phydev->speed;
380af9e3
YS		 1731 if (mdp->cd->set_rate)
1732 mdp->cd->set_rate(ndev);
86a74ff2 1733 }
3340d2aa 1734 if (!mdp->link) {
91a56152 1735 sh_eth_write(ndev,
128296fc
SS		 1736 sh_eth_read(ndev, ECMR) & ~ECMR_TXF,
1737 ECMR);
86a74ff2
NI		 1738 new_state = 1;
1739 mdp->link = phydev->link;
1e1b812b
SS		 1740 if (mdp->cd->no_psr || mdp->no_ether_link)
1741 sh_eth_rcv_snd_enable(ndev);
86a74ff2
NI		 1742 }
1743 } else if (mdp->link) {
1744 new_state = 1;
3340d2aa 1745 mdp->link = 0;
86a74ff2
NI		 1746 mdp->speed = 0;
1747 mdp->duplex = -1;
1e1b812b
SS		 1748 if (mdp->cd->no_psr || mdp->no_ether_link)
1749 sh_eth_rcv_snd_disable(ndev);
86a74ff2
NI		 1750 }
1751
dc19e4e5 1752 if (new_state && netif_msg_link(mdp))
86a74ff2
NI		 1753 phy_print_status(phydev);
1754}
1755
1756/* PHY init function */
1757static int sh_eth_phy_init(struct net_device *ndev)
1758{
702eca02 1759 struct device_node *np = ndev->dev.parent->of_node;
86a74ff2 1760 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 1761 struct phy_device *phydev = NULL;
1762
3340d2aa 1763 mdp->link = 0;
86a74ff2
NI		 1764 mdp->speed = 0;
1765 mdp->duplex = -1;
1766
1767 /* Try connect to PHY */
702eca02
BD		 1768 if (np) {
1769 struct device_node *pn;
1770
1771 pn = of_parse_phandle(np, "phy-handle", 0);
1772 phydev = of_phy_connect(ndev, pn,
1773 sh_eth_adjust_link, 0,
1774 mdp->phy_interface);
1775
1776 if (!phydev)
1777 phydev = ERR_PTR(-ENOENT);
1778 } else {
1779 char phy_id[MII_BUS_ID_SIZE + 3];
1780
1781 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
1782 mdp->mii_bus->id, mdp->phy_id);
1783
1784 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
1785 mdp->phy_interface);
1786 }
1787
86a74ff2 1788 if (IS_ERR(phydev)) {
da246855 1789 netdev_err(ndev, "failed to connect PHY\n");
86a74ff2
NI		 1790 return PTR_ERR(phydev);
1791 }
380af9e3 1792
da246855
SS		 1793 netdev_info(ndev, "attached PHY %d (IRQ %d) to driver %s\n",
1794 phydev->addr, phydev->irq, phydev->drv->name);
86a74ff2
NI		 1795
1796 mdp->phydev = phydev;
1797
1798 return 0;
1799}
1800
1801/* PHY control start function */
1802static int sh_eth_phy_start(struct net_device *ndev)
1803{
1804 struct sh_eth_private *mdp = netdev_priv(ndev);
1805 int ret;
1806
1807 ret = sh_eth_phy_init(ndev);
1808 if (ret)
1809 return ret;
1810
86a74ff2
NI		 1811 phy_start(mdp->phydev);
1812
1813 return 0;
1814}
1815
dc19e4e5 1816static int sh_eth_get_settings(struct net_device *ndev,
128296fc 1817 struct ethtool_cmd *ecmd)
dc19e4e5
NI		 1818{
1819 struct sh_eth_private *mdp = netdev_priv(ndev);
1820 unsigned long flags;
1821 int ret;
1822
1823 spin_lock_irqsave(&mdp->lock, flags);
1824 ret = phy_ethtool_gset(mdp->phydev, ecmd);
1825 spin_unlock_irqrestore(&mdp->lock, flags);
1826
1827 return ret;
1828}
1829
1830static int sh_eth_set_settings(struct net_device *ndev,
128296fc 1831 struct ethtool_cmd *ecmd)
dc19e4e5
NI		 1832{
1833 struct sh_eth_private *mdp = netdev_priv(ndev);
1834 unsigned long flags;
1835 int ret;
dc19e4e5
NI		 1836
1837 spin_lock_irqsave(&mdp->lock, flags);
1838
1839 /* disable tx and rx */
4a55530f 1840 sh_eth_rcv_snd_disable(ndev);
dc19e4e5
NI		 1841
1842 ret = phy_ethtool_sset(mdp->phydev, ecmd);
1843 if (ret)
1844 goto error_exit;
1845
1846 if (ecmd->duplex == DUPLEX_FULL)
1847 mdp->duplex = 1;
1848 else
1849 mdp->duplex = 0;
1850
1851 if (mdp->cd->set_duplex)
1852 mdp->cd->set_duplex(ndev);
1853
1854error_exit:
1855 mdelay(1);
1856
1857 /* enable tx and rx */
4a55530f 1858 sh_eth_rcv_snd_enable(ndev);
dc19e4e5
NI		 1859
1860 spin_unlock_irqrestore(&mdp->lock, flags);
1861
1862 return ret;
1863}
1864
1865static int sh_eth_nway_reset(struct net_device *ndev)
1866{
1867 struct sh_eth_private *mdp = netdev_priv(ndev);
1868 unsigned long flags;
1869 int ret;
1870
1871 spin_lock_irqsave(&mdp->lock, flags);
1872 ret = phy_start_aneg(mdp->phydev);
1873 spin_unlock_irqrestore(&mdp->lock, flags);
1874
1875 return ret;
1876}
1877
1878static u32 sh_eth_get_msglevel(struct net_device *ndev)
1879{
1880 struct sh_eth_private *mdp = netdev_priv(ndev);
1881 return mdp->msg_enable;
1882}
1883
1884static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
1885{
1886 struct sh_eth_private *mdp = netdev_priv(ndev);
1887 mdp->msg_enable = value;
1888}
1889
1890static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
1891 "rx_current", "tx_current",
1892 "rx_dirty", "tx_dirty",
1893};
1894#define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats)
1895
1896static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
1897{
1898 switch (sset) {
1899 case ETH_SS_STATS:
1900 return SH_ETH_STATS_LEN;
1901 default:
1902 return -EOPNOTSUPP;
1903 }
1904}
1905
1906static void sh_eth_get_ethtool_stats(struct net_device *ndev,
128296fc 1907 struct ethtool_stats *stats, u64 *data)
dc19e4e5
NI		 1908{
1909 struct sh_eth_private *mdp = netdev_priv(ndev);
1910 int i = 0;
1911
1912 /* device-specific stats */
1913 data[i++] = mdp->cur_rx;
1914 data[i++] = mdp->cur_tx;
1915 data[i++] = mdp->dirty_rx;
1916 data[i++] = mdp->dirty_tx;
1917}
1918
1919static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1920{
1921 switch (stringset) {
1922 case ETH_SS_STATS:
1923 memcpy(data, *sh_eth_gstrings_stats,
128296fc 1924 sizeof(sh_eth_gstrings_stats));
dc19e4e5
NI		 1925 break;
1926 }
1927}
1928
525b8075
YS		 1929static void sh_eth_get_ringparam(struct net_device *ndev,
1930 struct ethtool_ringparam *ring)
1931{
1932 struct sh_eth_private *mdp = netdev_priv(ndev);
1933
1934 ring->rx_max_pending = RX_RING_MAX;
1935 ring->tx_max_pending = TX_RING_MAX;
1936 ring->rx_pending = mdp->num_rx_ring;
1937 ring->tx_pending = mdp->num_tx_ring;
1938}
1939
1940static int sh_eth_set_ringparam(struct net_device *ndev,
1941 struct ethtool_ringparam *ring)
1942{
1943 struct sh_eth_private *mdp = netdev_priv(ndev);
1944 int ret;
1945
1946 if (ring->tx_pending > TX_RING_MAX ||
1947 ring->rx_pending > RX_RING_MAX ||
1948 ring->tx_pending < TX_RING_MIN ||
1949 ring->rx_pending < RX_RING_MIN)
1950 return -EINVAL;
1951 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
1952 return -EINVAL;
1953
1954 if (netif_running(ndev)) {
1955 netif_tx_disable(ndev);
1956 /* Disable interrupts by clearing the interrupt mask. */
1957 sh_eth_write(ndev, 0x0000, EESIPR);
1958 /* Stop the chip's Tx and Rx processes. */
1959 sh_eth_write(ndev, 0, EDTRR);
1960 sh_eth_write(ndev, 0, EDRRR);
1961 synchronize_irq(ndev->irq);
1962 }
1963
1964 /* Free all the skbuffs in the Rx queue. */
1965 sh_eth_ring_free(ndev);
1966 /* Free DMA buffer */
1967 sh_eth_free_dma_buffer(mdp);
1968
1969 /* Set new parameters */
1970 mdp->num_rx_ring = ring->rx_pending;
1971 mdp->num_tx_ring = ring->tx_pending;
1972
1973 ret = sh_eth_ring_init(ndev);
1974 if (ret < 0) {
da246855 1975 netdev_err(ndev, "%s: sh_eth_ring_init failed.\n", __func__);
525b8075
YS		 1976 return ret;
1977 }
1978 ret = sh_eth_dev_init(ndev, false);
1979 if (ret < 0) {
da246855 1980 netdev_err(ndev, "%s: sh_eth_dev_init failed.\n", __func__);
525b8075
YS		 1981 return ret;
1982 }
1983
1984 if (netif_running(ndev)) {
1985 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1986 /* Setting the Rx mode will start the Rx process. */
1987 sh_eth_write(ndev, EDRRR_R, EDRRR);
1988 netif_wake_queue(ndev);
1989 }
1990
1991 return 0;
1992}
1993
9b07be4b 1994static const struct ethtool_ops sh_eth_ethtool_ops = {
dc19e4e5
NI		 1995 .get_settings = sh_eth_get_settings,
1996 .set_settings = sh_eth_set_settings,
9b07be4b 1997 .nway_reset = sh_eth_nway_reset,
dc19e4e5
NI		 1998 .get_msglevel = sh_eth_get_msglevel,
1999 .set_msglevel = sh_eth_set_msglevel,
9b07be4b 2000 .get_link = ethtool_op_get_link,
dc19e4e5
NI		 2001 .get_strings = sh_eth_get_strings,
2002 .get_ethtool_stats = sh_eth_get_ethtool_stats,
2003 .get_sset_count = sh_eth_get_sset_count,
525b8075
YS		 2004 .get_ringparam = sh_eth_get_ringparam,
2005 .set_ringparam = sh_eth_set_ringparam,
dc19e4e5
NI		 2006};
2007
86a74ff2
NI		 2008/* network device open function */
2009static int sh_eth_open(struct net_device *ndev)
2010{
2011 int ret = 0;
2012 struct sh_eth_private *mdp = netdev_priv(ndev);
2013
bcd5149d
MD		 2014 pm_runtime_get_sync(&mdp->pdev->dev);
2015
d2779e99
SS		 2016 napi_enable(&mdp->napi);
2017
a0607fd3 2018 ret = request_irq(ndev->irq, sh_eth_interrupt,
5b3dfd13 2019 mdp->cd->irq_flags, ndev->name, ndev);
86a74ff2 2020 if (ret) {
da246855 2021 netdev_err(ndev, "Can not assign IRQ number\n");
d2779e99 2022 goto out_napi_off;
86a74ff2
NI		 2023 }
2024
2025 /* Descriptor set */
2026 ret = sh_eth_ring_init(ndev);
2027 if (ret)
2028 goto out_free_irq;
2029
2030 /* device init */
525b8075 2031 ret = sh_eth_dev_init(ndev, true);
86a74ff2
NI		 2032 if (ret)
2033 goto out_free_irq;
2034
2035 /* PHY control start*/
2036 ret = sh_eth_phy_start(ndev);
2037 if (ret)
2038 goto out_free_irq;
2039
86a74ff2
NI		 2040 return ret;
2041
2042out_free_irq:
2043 free_irq(ndev->irq, ndev);
d2779e99
SS		 2044out_napi_off:
2045 napi_disable(&mdp->napi);
bcd5149d 2046 pm_runtime_put_sync(&mdp->pdev->dev);
86a74ff2
NI		 2047 return ret;
2048}
2049
2050/* Timeout function */
2051static void sh_eth_tx_timeout(struct net_device *ndev)
2052{
2053 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 2054 struct sh_eth_rxdesc *rxdesc;
2055 int i;
2056
2057 netif_stop_queue(ndev);
2058
8d5009f6
SS		 2059 netif_err(mdp, timer, ndev,
2060 "transmit timed out, status %8.8x, resetting...\n",
2061 (int)sh_eth_read(ndev, EESR));
86a74ff2
NI		 2062
2063 /* tx_errors count up */
bb7d92e3 2064 ndev->stats.tx_errors++;
86a74ff2 2065
86a74ff2 2066 /* Free all the skbuffs in the Rx queue. */
525b8075 2067 for (i = 0; i < mdp->num_rx_ring; i++) {
86a74ff2
NI		 2068 rxdesc = &mdp->rx_ring[i];
2069 rxdesc->status = 0;
2070 rxdesc->addr = 0xBADF00D0;
2071 if (mdp->rx_skbuff[i])
2072 dev_kfree_skb(mdp->rx_skbuff[i]);
2073 mdp->rx_skbuff[i] = NULL;
2074 }
525b8075 2075 for (i = 0; i < mdp->num_tx_ring; i++) {
86a74ff2
NI		 2076 if (mdp->tx_skbuff[i])
2077 dev_kfree_skb(mdp->tx_skbuff[i]);
2078 mdp->tx_skbuff[i] = NULL;
2079 }
2080
2081 /* device init */
525b8075 2082 sh_eth_dev_init(ndev, true);
86a74ff2
NI		 2083}
2084
2085/* Packet transmit function */
2086static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
2087{
2088 struct sh_eth_private *mdp = netdev_priv(ndev);
2089 struct sh_eth_txdesc *txdesc;
2090 u32 entry;
fb5e2f9b 2091 unsigned long flags;
86a74ff2
NI		 2092
2093 spin_lock_irqsave(&mdp->lock, flags);
525b8075 2094 if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
86a74ff2 2095 if (!sh_eth_txfree(ndev)) {
8d5009f6 2096 netif_warn(mdp, tx_queued, ndev, "TxFD exhausted.\n");
86a74ff2
NI		 2097 netif_stop_queue(ndev);
2098 spin_unlock_irqrestore(&mdp->lock, flags);
5b548140 2099 return NETDEV_TX_BUSY;
86a74ff2
NI		 2100 }
2101 }
2102 spin_unlock_irqrestore(&mdp->lock, flags);
2103
525b8075 2104 entry = mdp->cur_tx % mdp->num_tx_ring;
86a74ff2
NI		 2105 mdp->tx_skbuff[entry] = skb;
2106 txdesc = &mdp->tx_ring[entry];
86a74ff2 2107 /* soft swap. */
380af9e3
YS		 2108 if (!mdp->cd->hw_swap)
2109 sh_eth_soft_swap(phys_to_virt(ALIGN(txdesc->addr, 4)),
2110 skb->len + 2);
31fcb99d
YS		 2111 txdesc->addr = dma_map_single(&ndev->dev, skb->data, skb->len,
2112 DMA_TO_DEVICE);
730c8c69
SS		 2113 if (skb->len < ETH_ZLEN)
2114 txdesc->buffer_length = ETH_ZLEN;
86a74ff2
NI		 2115 else
2116 txdesc->buffer_length = skb->len;
2117
525b8075 2118 if (entry >= mdp->num_tx_ring - 1)
71557a37 2119 txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE);
86a74ff2 2120 else
71557a37 2121 txdesc->status |= cpu_to_edmac(mdp, TD_TACT);
86a74ff2
NI		 2122
2123 mdp->cur_tx++;
2124
c5ed5368
YS		 2125 if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
2126 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
b0ca2a21 2127
6ed10654 2128 return NETDEV_TX_OK;
86a74ff2
NI		 2129}
2130
2131/* device close function */
2132static int sh_eth_close(struct net_device *ndev)
2133{
2134 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 2135
2136 netif_stop_queue(ndev);
2137
2138 /* Disable interrupts by clearing the interrupt mask. */
4a55530f 2139 sh_eth_write(ndev, 0x0000, EESIPR);
86a74ff2
NI		 2140
2141 /* Stop the chip's Tx and Rx processes. */
4a55530f
YS		 2142 sh_eth_write(ndev, 0, EDTRR);
2143 sh_eth_write(ndev, 0, EDRRR);
86a74ff2
NI		 2144
2145 /* PHY Disconnect */
2146 if (mdp->phydev) {
2147 phy_stop(mdp->phydev);
2148 phy_disconnect(mdp->phydev);
2149 }
2150
2151 free_irq(ndev->irq, ndev);
2152
d2779e99
SS		 2153 napi_disable(&mdp->napi);
2154
86a74ff2
NI		 2155 /* Free all the skbuffs in the Rx queue. */
2156 sh_eth_ring_free(ndev);
2157
2158 /* free DMA buffer */
91c77550 2159 sh_eth_free_dma_buffer(mdp);
86a74ff2 2160
bcd5149d
MD		 2161 pm_runtime_put_sync(&mdp->pdev->dev);
2162
86a74ff2
NI		 2163 return 0;
2164}
2165
2166static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
2167{
2168 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2 2169
db893473
SH		 2170 if (sh_eth_is_rz_fast_ether(mdp))
2171 return &ndev->stats;
2172
bcd5149d
MD		 2173 pm_runtime_get_sync(&mdp->pdev->dev);
2174
bb7d92e3 2175 ndev->stats.tx_dropped += sh_eth_read(ndev, TROCR);
4a55530f 2176 sh_eth_write(ndev, 0, TROCR); /* (write clear) */
bb7d92e3 2177 ndev->stats.collisions += sh_eth_read(ndev, CDCR);
4a55530f 2178 sh_eth_write(ndev, 0, CDCR); /* (write clear) */
bb7d92e3 2179 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, LCCR);
4a55530f 2180 sh_eth_write(ndev, 0, LCCR); /* (write clear) */
c5ed5368 2181 if (sh_eth_is_gether(mdp)) {
bb7d92e3 2182 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CERCR);
c5ed5368 2183 sh_eth_write(ndev, 0, CERCR); /* (write clear) */
bb7d92e3 2184 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CEECR);
c5ed5368
YS		 2185 sh_eth_write(ndev, 0, CEECR); /* (write clear) */
2186 } else {
bb7d92e3 2187 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CNDCR);
c5ed5368
YS		 2188 sh_eth_write(ndev, 0, CNDCR); /* (write clear) */
2189 }
bcd5149d
MD		 2190 pm_runtime_put_sync(&mdp->pdev->dev);
2191
bb7d92e3 2192 return &ndev->stats;
86a74ff2
NI		 2193}
2194
bb7d92e3 2195/* ioctl to device function */
128296fc 2196static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
86a74ff2
NI		 2197{
2198 struct sh_eth_private *mdp = netdev_priv(ndev);
2199 struct phy_device *phydev = mdp->phydev;
2200
2201 if (!netif_running(ndev))
2202 return -EINVAL;
2203
2204 if (!phydev)
2205 return -ENODEV;
2206
28b04113 2207 return phy_mii_ioctl(phydev, rq, cmd);
86a74ff2
NI		 2208}
2209
6743fe6d
YS		 2210/* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
2211static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp,
2212 int entry)
2213{
2214 return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4);
2215}
2216
2217static u32 sh_eth_tsu_get_post_mask(int entry)
2218{
2219 return 0x0f << (28 - ((entry % 8) * 4));
2220}
2221
2222static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
2223{
2224 return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
2225}
2226
2227static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
2228 int entry)
2229{
2230 struct sh_eth_private *mdp = netdev_priv(ndev);
2231 u32 tmp;
2232 void *reg_offset;
2233
2234 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2235 tmp = ioread32(reg_offset);
2236 iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset);
2237}
2238
2239static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
2240 int entry)
2241{
2242 struct sh_eth_private *mdp = netdev_priv(ndev);
2243 u32 post_mask, ref_mask, tmp;
2244 void *reg_offset;
2245
2246 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2247 post_mask = sh_eth_tsu_get_post_mask(entry);
2248 ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
2249
2250 tmp = ioread32(reg_offset);
2251 iowrite32(tmp & ~post_mask, reg_offset);
2252
2253 /* If other port enables, the function returns "true" */
2254 return tmp & ref_mask;
2255}
2256
2257static int sh_eth_tsu_busy(struct net_device *ndev)
2258{
2259 int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
2260 struct sh_eth_private *mdp = netdev_priv(ndev);
2261
2262 while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
2263 udelay(10);
2264 timeout--;
2265 if (timeout <= 0) {
da246855 2266 netdev_err(ndev, "%s: timeout\n", __func__);
6743fe6d
YS		 2267 return -ETIMEDOUT;
2268 }
2269 }
2270
2271 return 0;
2272}
2273
2274static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg,
2275 const u8 *addr)
2276{
2277 u32 val;
2278
2279 val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
2280 iowrite32(val, reg);
2281 if (sh_eth_tsu_busy(ndev) < 0)
2282 return -EBUSY;
2283
2284 val = addr[4] << 8 | addr[5];
2285 iowrite32(val, reg + 4);
2286 if (sh_eth_tsu_busy(ndev) < 0)
2287 return -EBUSY;
2288
2289 return 0;
2290}
2291
2292static void sh_eth_tsu_read_entry(void *reg, u8 *addr)
2293{
2294 u32 val;
2295
2296 val = ioread32(reg);
2297 addr[0] = (val >> 24) & 0xff;
2298 addr[1] = (val >> 16) & 0xff;
2299 addr[2] = (val >> 8) & 0xff;
2300 addr[3] = val & 0xff;
2301 val = ioread32(reg + 4);
2302 addr[4] = (val >> 8) & 0xff;
2303 addr[5] = val & 0xff;
2304}
2305
2306
2307static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
2308{
2309 struct sh_eth_private *mdp = netdev_priv(ndev);
2310 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2311 int i;
2312 u8 c_addr[ETH_ALEN];
2313
2314 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2315 sh_eth_tsu_read_entry(reg_offset, c_addr);
c4bde29c 2316 if (ether_addr_equal(addr, c_addr))
6743fe6d
YS		 2317 return i;
2318 }
2319
2320 return -ENOENT;
2321}
2322
2323static int sh_eth_tsu_find_empty(struct net_device *ndev)
2324{
2325 u8 blank[ETH_ALEN];
2326 int entry;
2327
2328 memset(blank, 0, sizeof(blank));
2329 entry = sh_eth_tsu_find_entry(ndev, blank);
2330 return (entry < 0) ? -ENOMEM : entry;
2331}
2332
2333static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
2334 int entry)
2335{
2336 struct sh_eth_private *mdp = netdev_priv(ndev);
2337 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2338 int ret;
2339 u8 blank[ETH_ALEN];
2340
2341 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
2342 ~(1 << (31 - entry)), TSU_TEN);
2343
2344 memset(blank, 0, sizeof(blank));
2345 ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
2346 if (ret < 0)
2347 return ret;
2348 return 0;
2349}
2350
2351static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
2352{
2353 struct sh_eth_private *mdp = netdev_priv(ndev);
2354 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2355 int i, ret;
2356
2357 if (!mdp->cd->tsu)
2358 return 0;
2359
2360 i = sh_eth_tsu_find_entry(ndev, addr);
2361 if (i < 0) {
2362 /* No entry found, create one */
2363 i = sh_eth_tsu_find_empty(ndev);
2364 if (i < 0)
2365 return -ENOMEM;
2366 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
2367 if (ret < 0)
2368 return ret;
2369
2370 /* Enable the entry */
2371 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
2372 (1 << (31 - i)), TSU_TEN);
2373 }
2374
2375 /* Entry found or created, enable POST */
2376 sh_eth_tsu_enable_cam_entry_post(ndev, i);
2377
2378 return 0;
2379}
2380
2381static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
2382{
2383 struct sh_eth_private *mdp = netdev_priv(ndev);
2384 int i, ret;
2385
2386 if (!mdp->cd->tsu)
2387 return 0;
2388
2389 i = sh_eth_tsu_find_entry(ndev, addr);
2390 if (i) {
2391 /* Entry found */
2392 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2393 goto done;
2394
2395 /* Disable the entry if both ports was disabled */
2396 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2397 if (ret < 0)
2398 return ret;
2399 }
2400done:
2401 return 0;
2402}
2403
2404static int sh_eth_tsu_purge_all(struct net_device *ndev)
2405{
2406 struct sh_eth_private *mdp = netdev_priv(ndev);
2407 int i, ret;
2408
2409 if (unlikely(!mdp->cd->tsu))
2410 return 0;
2411
2412 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
2413 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2414 continue;
2415
2416 /* Disable the entry if both ports was disabled */
2417 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2418 if (ret < 0)
2419 return ret;
2420 }
2421
2422 return 0;
2423}
2424
2425static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
2426{
2427 struct sh_eth_private *mdp = netdev_priv(ndev);
2428 u8 addr[ETH_ALEN];
2429 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2430 int i;
2431
2432 if (unlikely(!mdp->cd->tsu))
2433 return;
2434
2435 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2436 sh_eth_tsu_read_entry(reg_offset, addr);
2437 if (is_multicast_ether_addr(addr))
2438 sh_eth_tsu_del_entry(ndev, addr);
2439 }
2440}
2441
86a74ff2
NI		 2442/* Multicast reception directions set */
2443static void sh_eth_set_multicast_list(struct net_device *ndev)
2444{
6743fe6d
YS		 2445 struct sh_eth_private *mdp = netdev_priv(ndev);
2446 u32 ecmr_bits;
2447 int mcast_all = 0;
2448 unsigned long flags;
2449
2450 spin_lock_irqsave(&mdp->lock, flags);
128296fc 2451 /* Initial condition is MCT = 1, PRM = 0.
6743fe6d
YS		 2452 * Depending on ndev->flags, set PRM or clear MCT
2453 */
2454 ecmr_bits = (sh_eth_read(ndev, ECMR) & ~ECMR_PRM) | ECMR_MCT;
2455
2456 if (!(ndev->flags & IFF_MULTICAST)) {
2457 sh_eth_tsu_purge_mcast(ndev);
2458 mcast_all = 1;
2459 }
2460 if (ndev->flags & IFF_ALLMULTI) {
2461 sh_eth_tsu_purge_mcast(ndev);
2462 ecmr_bits &= ~ECMR_MCT;
2463 mcast_all = 1;
2464 }
2465
86a74ff2 2466 if (ndev->flags & IFF_PROMISC) {
6743fe6d
YS		 2467 sh_eth_tsu_purge_all(ndev);
2468 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2469 } else if (mdp->cd->tsu) {
2470 struct netdev_hw_addr *ha;
2471 netdev_for_each_mc_addr(ha, ndev) {
2472 if (mcast_all && is_multicast_ether_addr(ha->addr))
2473 continue;
2474
2475 if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2476 if (!mcast_all) {
2477 sh_eth_tsu_purge_mcast(ndev);
2478 ecmr_bits &= ~ECMR_MCT;
2479 mcast_all = 1;
2480 }
2481 }
2482 }
86a74ff2
NI		 2483 } else {
2484 /* Normal, unicast/broadcast-only mode. */
6743fe6d 2485 ecmr_bits = (ecmr_bits & ~ECMR_PRM) | ECMR_MCT;
86a74ff2 2486 }
6743fe6d
YS		 2487
2488 /* update the ethernet mode */
2489 sh_eth_write(ndev, ecmr_bits, ECMR);
2490
2491 spin_unlock_irqrestore(&mdp->lock, flags);
86a74ff2 2492}
71cc7c37
YS		 2493
2494static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2495{
2496 if (!mdp->port)
2497 return TSU_VTAG0;
2498 else
2499 return TSU_VTAG1;
2500}
2501
80d5c368
PM		 2502static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
2503 __be16 proto, u16 vid)
71cc7c37
YS		 2504{
2505 struct sh_eth_private *mdp = netdev_priv(ndev);
2506 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2507
2508 if (unlikely(!mdp->cd->tsu))
2509 return -EPERM;
2510
2511 /* No filtering if vid = 0 */
2512 if (!vid)
2513 return 0;
2514
2515 mdp->vlan_num_ids++;
2516
128296fc 2517 /* The controller has one VLAN tag HW filter. So, if the filter is
71cc7c37
YS		 2518 * already enabled, the driver disables it and the filte
2519 */
2520 if (mdp->vlan_num_ids > 1) {
2521 /* disable VLAN filter */
2522 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2523 return 0;
2524 }
2525
2526 sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
2527 vtag_reg_index);
2528
2529 return 0;
2530}
2531
80d5c368
PM		 2532static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
2533 __be16 proto, u16 vid)
71cc7c37
YS		 2534{
2535 struct sh_eth_private *mdp = netdev_priv(ndev);
2536 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2537
2538 if (unlikely(!mdp->cd->tsu))
2539 return -EPERM;
2540
2541 /* No filtering if vid = 0 */
2542 if (!vid)
2543 return 0;
2544
2545 mdp->vlan_num_ids--;
2546 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2547
2548 return 0;
2549}
86a74ff2
NI		 2550
2551/* SuperH's TSU register init function */
4a55530f 2552static void sh_eth_tsu_init(struct sh_eth_private *mdp)
86a74ff2 2553{
db893473
SH		 2554 if (sh_eth_is_rz_fast_ether(mdp)) {
2555 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2556 return;
2557 }
2558
4a55530f
YS		 2559 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */
2560 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */
2561 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */
2562 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
2563 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
2564 sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
2565 sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
2566 sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
2567 sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
2568 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
c5ed5368
YS		 2569 if (sh_eth_is_gether(mdp)) {
2570 sh_eth_tsu_write(mdp, 0, TSU_QTAG0); /* Disable QTAG(0->1) */
2571 sh_eth_tsu_write(mdp, 0, TSU_QTAG1); /* Disable QTAG(1->0) */
2572 } else {
2573 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */
2574 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */
2575 }
4a55530f
YS		 2576 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */
2577 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */
2578 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2579 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */
2580 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */
2581 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */
2582 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */
86a74ff2
NI		 2583}
2584
2585/* MDIO bus release function */
2586static int sh_mdio_release(struct net_device *ndev)
2587{
2588 struct mii_bus *bus = dev_get_drvdata(&ndev->dev);
2589
2590 /* unregister mdio bus */
2591 mdiobus_unregister(bus);
2592
2593 /* remove mdio bus info from net_device */
2594 dev_set_drvdata(&ndev->dev, NULL);
2595
2596 /* free bitbang info */
2597 free_mdio_bitbang(bus);
2598
2599 return 0;
2600}
2601
2602/* MDIO bus init function */
b3017e6a
YS		 2603static int sh_mdio_init(struct net_device *ndev, int id,
2604 struct sh_eth_plat_data *pd)
86a74ff2
NI		 2605{
2606 int ret, i;
2607 struct bb_info *bitbang;
2608 struct sh_eth_private *mdp = netdev_priv(ndev);
2609
2610 /* create bit control struct for PHY */
d5e07e69
SS		 2611 bitbang = devm_kzalloc(&ndev->dev, sizeof(struct bb_info),
2612 GFP_KERNEL);
86a74ff2
NI		 2613 if (!bitbang) {
2614 ret = -ENOMEM;
2615 goto out;
2616 }
2617
2618 /* bitbang init */
ae70644d 2619 bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
b3017e6a 2620 bitbang->set_gate = pd->set_mdio_gate;
dfed5e7f
SS		 2621 bitbang->mdi_msk = PIR_MDI;
2622 bitbang->mdo_msk = PIR_MDO;
2623 bitbang->mmd_msk = PIR_MMD;
2624 bitbang->mdc_msk = PIR_MDC;
86a74ff2
NI		 2625 bitbang->ctrl.ops = &bb_ops;
2626
c2e07b3a 2627 /* MII controller setting */
86a74ff2
NI		 2628 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
2629 if (!mdp->mii_bus) {
2630 ret = -ENOMEM;
d5e07e69 2631 goto out;
86a74ff2
NI		 2632 }
2633
2634 /* Hook up MII support for ethtool */
2635 mdp->mii_bus->name = "sh_mii";
18ee49dd 2636 mdp->mii_bus->parent = &ndev->dev;
5278fb54 2637 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
128296fc 2638 mdp->pdev->name, id);
86a74ff2
NI		 2639
2640 /* PHY IRQ */
d5e07e69
SS		 2641 mdp->mii_bus->irq = devm_kzalloc(&ndev->dev,
2642 sizeof(int) * PHY_MAX_ADDR,
2643 GFP_KERNEL);
86a74ff2
NI		 2644 if (!mdp->mii_bus->irq) {
2645 ret = -ENOMEM;
2646 goto out_free_bus;
2647 }
2648
8f6352f2 2649 /* register mdio bus */
702eca02
BD		 2650 if (ndev->dev.parent->of_node) {
2651 ret = of_mdiobus_register(mdp->mii_bus,
2652 ndev->dev.parent->of_node);
2653 } else {
2654 for (i = 0; i < PHY_MAX_ADDR; i++)
2655 mdp->mii_bus->irq[i] = PHY_POLL;
2656 if (pd->phy_irq > 0)
2657 mdp->mii_bus->irq[pd->phy] = pd->phy_irq;
2658
2659 ret = mdiobus_register(mdp->mii_bus);
2660 }
2661
86a74ff2 2662 if (ret)
d5e07e69 2663 goto out_free_bus;
86a74ff2
NI		 2664
2665 dev_set_drvdata(&ndev->dev, mdp->mii_bus);
2666
2667 return 0;
2668
86a74ff2 2669out_free_bus:
298cf9be 2670 free_mdio_bitbang(mdp->mii_bus);
86a74ff2 2671
86a74ff2
NI		 2672out:
2673 return ret;
2674}
2675
4a55530f
YS		 2676static const u16 *sh_eth_get_register_offset(int register_type)
2677{
2678 const u16 *reg_offset = NULL;
2679
2680 switch (register_type) {
2681 case SH_ETH_REG_GIGABIT:
2682 reg_offset = sh_eth_offset_gigabit;
2683 break;
db893473
SH		 2684 case SH_ETH_REG_FAST_RZ:
2685 reg_offset = sh_eth_offset_fast_rz;
2686 break;
a3f109bd
SS		 2687 case SH_ETH_REG_FAST_RCAR:
2688 reg_offset = sh_eth_offset_fast_rcar;
2689 break;
4a55530f
YS		 2690 case SH_ETH_REG_FAST_SH4:
2691 reg_offset = sh_eth_offset_fast_sh4;
2692 break;
2693 case SH_ETH_REG_FAST_SH3_SH2:
2694 reg_offset = sh_eth_offset_fast_sh3_sh2;
2695 break;
2696 default:
4a55530f
YS		 2697 break;
2698 }
2699
2700 return reg_offset;
2701}
2702
8f728d79 2703static const struct net_device_ops sh_eth_netdev_ops = {
ebf84eaa
AB		 2704 .ndo_open = sh_eth_open,
2705 .ndo_stop = sh_eth_close,
2706 .ndo_start_xmit = sh_eth_start_xmit,
2707 .ndo_get_stats = sh_eth_get_stats,
ebf84eaa
AB		 2708 .ndo_tx_timeout = sh_eth_tx_timeout,
2709 .ndo_do_ioctl = sh_eth_do_ioctl,
2710 .ndo_validate_addr = eth_validate_addr,
2711 .ndo_set_mac_address = eth_mac_addr,
2712 .ndo_change_mtu = eth_change_mtu,
2713};
2714
8f728d79
SS		 2715static const struct net_device_ops sh_eth_netdev_ops_tsu = {
2716 .ndo_open = sh_eth_open,
2717 .ndo_stop = sh_eth_close,
2718 .ndo_start_xmit = sh_eth_start_xmit,
2719 .ndo_get_stats = sh_eth_get_stats,
2720 .ndo_set_rx_mode = sh_eth_set_multicast_list,
2721 .ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid,
2722 .ndo_vlan_rx_kill_vid = sh_eth_vlan_rx_kill_vid,
2723 .ndo_tx_timeout = sh_eth_tx_timeout,
2724 .ndo_do_ioctl = sh_eth_do_ioctl,
2725 .ndo_validate_addr = eth_validate_addr,
2726 .ndo_set_mac_address = eth_mac_addr,
2727 .ndo_change_mtu = eth_change_mtu,
2728};
2729
b356e978
SS		 2730#ifdef CONFIG_OF
2731static struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
2732{
2733 struct device_node *np = dev->of_node;
2734 struct sh_eth_plat_data *pdata;
b356e978
SS		 2735 const char *mac_addr;
2736
2737 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
2738 if (!pdata)
2739 return NULL;
2740
2741 pdata->phy_interface = of_get_phy_mode(np);
2742
b356e978
SS		 2743 mac_addr = of_get_mac_address(np);
2744 if (mac_addr)
2745 memcpy(pdata->mac_addr, mac_addr, ETH_ALEN);
2746
2747 pdata->no_ether_link =
2748 of_property_read_bool(np, "renesas,no-ether-link");
2749 pdata->ether_link_active_low =
2750 of_property_read_bool(np, "renesas,ether-link-active-low");
2751
2752 return pdata;
2753}
2754
2755static const struct of_device_id sh_eth_match_table[] = {
2756 { .compatible = "renesas,gether-r8a7740", .data = &r8a7740_data },
2757 { .compatible = "renesas,ether-r8a7778", .data = &r8a777x_data },
2758 { .compatible = "renesas,ether-r8a7779", .data = &r8a777x_data },
2759 { .compatible = "renesas,ether-r8a7790", .data = &r8a779x_data },
2760 { .compatible = "renesas,ether-r8a7791", .data = &r8a779x_data },
2761 { .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data },
2762 { }
2763};
2764MODULE_DEVICE_TABLE(of, sh_eth_match_table);
2765#else
2766static inline struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
2767{
2768 return NULL;
2769}
2770#endif
2771
86a74ff2
NI		 2772static int sh_eth_drv_probe(struct platform_device *pdev)
2773{
9c38657c 2774 int ret, devno = 0;
86a74ff2
NI		 2775 struct resource *res;
2776 struct net_device *ndev = NULL;
ec0d7551 2777 struct sh_eth_private *mdp = NULL;
0b76b862 2778 struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev);
afe391ad 2779 const struct platform_device_id *id = platform_get_device_id(pdev);
86a74ff2
NI		 2780
2781 /* get base addr */
2782 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2783 if (unlikely(res == NULL)) {
2784 dev_err(&pdev->dev, "invalid resource\n");
2785 ret = -EINVAL;
2786 goto out;
2787 }
2788
2789 ndev = alloc_etherdev(sizeof(struct sh_eth_private));
2790 if (!ndev) {
86a74ff2
NI		 2791 ret = -ENOMEM;
2792 goto out;
2793 }
2794
2795 /* The sh Ether-specific entries in the device structure. */
2796 ndev->base_addr = res->start;
2797 devno = pdev->id;
2798 if (devno < 0)
2799 devno = 0;
2800
2801 ndev->dma = -1;
cc3c080d 2802 ret = platform_get_irq(pdev, 0);
2803 if (ret < 0) {
86a74ff2
NI		 2804 ret = -ENODEV;
2805 goto out_release;
2806 }
cc3c080d 2807 ndev->irq = ret;
86a74ff2
NI		 2808
2809 SET_NETDEV_DEV(ndev, &pdev->dev);
2810
86a74ff2 2811 mdp = netdev_priv(ndev);
525b8075
YS		 2812 mdp->num_tx_ring = TX_RING_SIZE;
2813 mdp->num_rx_ring = RX_RING_SIZE;
d5e07e69
SS		 2814 mdp->addr = devm_ioremap_resource(&pdev->dev, res);
2815 if (IS_ERR(mdp->addr)) {
2816 ret = PTR_ERR(mdp->addr);
ae70644d
YS		 2817 goto out_release;
2818 }
2819
86a74ff2 2820 spin_lock_init(&mdp->lock);
bcd5149d
MD		 2821 mdp->pdev = pdev;
2822 pm_runtime_enable(&pdev->dev);
2823 pm_runtime_resume(&pdev->dev);
86a74ff2 2824
b356e978
SS		 2825 if (pdev->dev.of_node)
2826 pd = sh_eth_parse_dt(&pdev->dev);
3b4c5cbf
SS		 2827 if (!pd) {
2828 dev_err(&pdev->dev, "no platform data\n");
2829 ret = -EINVAL;
2830 goto out_release;
2831 }
2832
86a74ff2 2833 /* get PHY ID */
71557a37 2834 mdp->phy_id = pd->phy;
e47c9052 2835 mdp->phy_interface = pd->phy_interface;
71557a37
YS		 2836 /* EDMAC endian */
2837 mdp->edmac_endian = pd->edmac_endian;
4923576b
YS		 2838 mdp->no_ether_link = pd->no_ether_link;
2839 mdp->ether_link_active_low = pd->ether_link_active_low;
86a74ff2 2840
380af9e3 2841 /* set cpu data */
b356e978
SS		 2842 if (id) {
2843 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data;
2844 } else {
2845 const struct of_device_id *match;
2846
2847 match = of_match_device(of_match_ptr(sh_eth_match_table),
2848 &pdev->dev);
2849 mdp->cd = (struct sh_eth_cpu_data *)match->data;
2850 }
a3153d8c 2851 mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type);
264be2f5
SS		 2852 if (!mdp->reg_offset) {
2853 dev_err(&pdev->dev, "Unknown register type (%d)\n",
2854 mdp->cd->register_type);
2855 ret = -EINVAL;
2856 goto out_release;
2857 }
380af9e3
YS		 2858 sh_eth_set_default_cpu_data(mdp->cd);
2859
86a74ff2 2860 /* set function */
8f728d79
SS		 2861 if (mdp->cd->tsu)
2862 ndev->netdev_ops = &sh_eth_netdev_ops_tsu;
2863 else
2864 ndev->netdev_ops = &sh_eth_netdev_ops;
dc19e4e5 2865 SET_ETHTOOL_OPS(ndev, &sh_eth_ethtool_ops);
86a74ff2
NI		 2866 ndev->watchdog_timeo = TX_TIMEOUT;
2867
dc19e4e5
NI		 2868 /* debug message level */
2869 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
86a74ff2
NI		 2870
2871 /* read and set MAC address */
748031f9 2872 read_mac_address(ndev, pd->mac_addr);
ff6e7228
SS		 2873 if (!is_valid_ether_addr(ndev->dev_addr)) {
2874 dev_warn(&pdev->dev,
2875 "no valid MAC address supplied, using a random one.\n");
2876 eth_hw_addr_random(ndev);
2877 }
86a74ff2 2878
6ba88021
YS		 2879 /* ioremap the TSU registers */
2880 if (mdp->cd->tsu) {
2881 struct resource *rtsu;
2882 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
d5e07e69
SS		 2883 mdp->tsu_addr = devm_ioremap_resource(&pdev->dev, rtsu);
2884 if (IS_ERR(mdp->tsu_addr)) {
2885 ret = PTR_ERR(mdp->tsu_addr);
fc0c0900
SS		 2886 goto out_release;
2887 }
6743fe6d 2888 mdp->port = devno % 2;
f646968f 2889 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER;
6ba88021
YS		 2890 }
2891
150647fb
YS		 2892 /* initialize first or needed device */
2893 if (!devno || pd->needs_init) {
380af9e3
YS		 2894 if (mdp->cd->chip_reset)
2895 mdp->cd->chip_reset(ndev);
86a74ff2 2896
4986b996
YS		 2897 if (mdp->cd->tsu) {
2898 /* TSU init (Init only)*/
2899 sh_eth_tsu_init(mdp);
2900 }
86a74ff2
NI		 2901 }
2902
3719109d
SS		 2903 netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64);
2904
86a74ff2
NI		 2905 /* network device register */
2906 ret = register_netdev(ndev);
2907 if (ret)
3719109d 2908 goto out_napi_del;
86a74ff2
NI		 2909
2910 /* mdio bus init */
b3017e6a 2911 ret = sh_mdio_init(ndev, pdev->id, pd);
702eca02
BD		 2912 if (ret) {
2913 dev_err(&ndev->dev, "failed to initialise MDIO\n");
86a74ff2 2914 goto out_unregister;
702eca02 2915 }
86a74ff2 2916
25985edc 2917 /* print device information */
f75f14ec
SS		 2918 netdev_info(ndev, "Base address at 0x%x, %pM, IRQ %d.\n",
2919 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
86a74ff2
NI		 2920
2921 platform_set_drvdata(pdev, ndev);
2922
2923 return ret;
2924
2925out_unregister:
2926 unregister_netdev(ndev);
2927
3719109d
SS		 2928out_napi_del:
2929 netif_napi_del(&mdp->napi);
2930
86a74ff2
NI		 2931out_release:
2932 /* net_dev free */
2933 if (ndev)
2934 free_netdev(ndev);
2935
2936out:
2937 return ret;
2938}
2939
2940static int sh_eth_drv_remove(struct platform_device *pdev)
2941{
2942 struct net_device *ndev = platform_get_drvdata(pdev);
3719109d 2943 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 2944
2945 sh_mdio_release(ndev);
2946 unregister_netdev(ndev);
3719109d 2947 netif_napi_del(&mdp->napi);
bcd5149d 2948 pm_runtime_disable(&pdev->dev);
86a74ff2 2949 free_netdev(ndev);
86a74ff2
NI		 2950
2951 return 0;
2952}
2953
540ad1b8 2954#ifdef CONFIG_PM
bcd5149d
MD		 2955static int sh_eth_runtime_nop(struct device *dev)
2956{
128296fc 2957 /* Runtime PM callback shared between ->runtime_suspend()
bcd5149d
MD		 2958 * and ->runtime_resume(). Simply returns success.
2959 *
2960 * This driver re-initializes all registers after
2961 * pm_runtime_get_sync() anyway so there is no need
2962 * to save and restore registers here.
2963 */
2964 return 0;
2965}
2966
540ad1b8 2967static const struct dev_pm_ops sh_eth_dev_pm_ops = {
bcd5149d
MD		 2968 .runtime_suspend = sh_eth_runtime_nop,
2969 .runtime_resume = sh_eth_runtime_nop,
2970};
540ad1b8
NI		 2971#define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
2972#else
2973#define SH_ETH_PM_OPS NULL
2974#endif
bcd5149d 2975
afe391ad 2976static struct platform_device_id sh_eth_id_table[] = {
c18a79ab 2977 { "sh7619-ether", (kernel_ulong_t)&sh7619_data },
7bbe150d 2978 { "sh771x-ether", (kernel_ulong_t)&sh771x_data },
9c3beaab 2979 { "sh7724-ether", (kernel_ulong_t)&sh7724_data },
f5d12767 2980 { "sh7734-gether", (kernel_ulong_t)&sh7734_data },
24549e2a
SS		 2981 { "sh7757-ether", (kernel_ulong_t)&sh7757_data },
2982 { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga },
f5d12767 2983 { "sh7763-gether", (kernel_ulong_t)&sh7763_data },
db893473 2984 { "r7s72100-ether", (kernel_ulong_t)&r7s72100_data },
e5c9b4cd 2985 { "r8a7740-gether", (kernel_ulong_t)&r8a7740_data },
589ebdef 2986 { "r8a777x-ether", (kernel_ulong_t)&r8a777x_data },
94a12b15
SS		 2987 { "r8a7790-ether", (kernel_ulong_t)&r8a779x_data },
2988 { "r8a7791-ether", (kernel_ulong_t)&r8a779x_data },
afe391ad
SS		 2989 { }
2990};
2991MODULE_DEVICE_TABLE(platform, sh_eth_id_table);
2992
86a74ff2
NI		 2993static struct platform_driver sh_eth_driver = {
2994 .probe = sh_eth_drv_probe,
2995 .remove = sh_eth_drv_remove,
afe391ad 2996 .id_table = sh_eth_id_table,
86a74ff2
NI		 2997 .driver = {
2998 .name = CARDNAME,
540ad1b8 2999 .pm = SH_ETH_PM_OPS,
b356e978 3000 .of_match_table = of_match_ptr(sh_eth_match_table),
86a74ff2
NI		 3001 },
3002};
3003
db62f684 3004module_platform_driver(sh_eth_driver);
86a74ff2
NI		 3005
3006MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
3007MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
3008MODULE_LICENSE("GPL v2");
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