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net: bridge: fdb: eliminate extra port state tests from fast-path
[mirror_ubuntu-hirsute-kernel.git] / drivers / net / ethernet / renesas / sh_eth.c
CommitLineData
00e1cae7 1// SPDX-License-Identifier: GPL-2.0
128296fc 2/* SuperH Ethernet device driver
86a74ff2 3 *
9b39f05c 4 * Copyright (C) 2014 Renesas Electronics Corporation
f0e81fec 5 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu
b356e978 6 * Copyright (C) 2008-2014 Renesas Solutions Corp.
9b39f05c 7 * Copyright (C) 2013-2017 Cogent Embedded, Inc.
702eca02 8 * Copyright (C) 2014 Codethink Limited
86a74ff2
NI		 9 */
10
0654011d
YS		 11#include <linux/module.h>
12#include <linux/kernel.h>
13#include <linux/spinlock.h>
6a27cded 14#include <linux/interrupt.h>
86a74ff2
NI		 15#include <linux/dma-mapping.h>
16#include <linux/etherdevice.h>
17#include <linux/delay.h>
18#include <linux/platform_device.h>
19#include <linux/mdio-bitbang.h>
20#include <linux/netdevice.h>
b356e978
SS		 21#include <linux/of.h>
22#include <linux/of_device.h>
23#include <linux/of_irq.h>
24#include <linux/of_net.h>
86a74ff2
NI		 25#include <linux/phy.h>
26#include <linux/cache.h>
27#include <linux/io.h>
bcd5149d 28#include <linux/pm_runtime.h>
5a0e3ad6 29#include <linux/slab.h>
dc19e4e5 30#include <linux/ethtool.h>
fdb37a7f 31#include <linux/if_vlan.h>
d4fa0e35 32#include <linux/sh_eth.h>
702eca02 33#include <linux/of_mdio.h>
86a74ff2
NI		 34
35#include "sh_eth.h"
36
dc19e4e5
NI		 37#define SH_ETH_DEF_MSG_ENABLE \
38 (NETIF_MSG_LINK | \
39 NETIF_MSG_TIMER | \
40 NETIF_MSG_RX_ERR| \
41 NETIF_MSG_TX_ERR)
42
2274d375
SS		 43#define SH_ETH_OFFSET_INVALID ((u16)~0)
44
3365711d
BH		 45#define SH_ETH_OFFSET_DEFAULTS \
46 [0 ... SH_ETH_MAX_REGISTER_OFFSET - 1] = SH_ETH_OFFSET_INVALID
47
c0013f6f 48static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
3365711d
BH		 49 SH_ETH_OFFSET_DEFAULTS,
50
c0013f6f
SS		 51 [EDSR] = 0x0000,
52 [EDMR] = 0x0400,
53 [EDTRR] = 0x0408,
54 [EDRRR] = 0x0410,
55 [EESR] = 0x0428,
56 [EESIPR] = 0x0430,
57 [TDLAR] = 0x0010,
58 [TDFAR] = 0x0014,
59 [TDFXR] = 0x0018,
60 [TDFFR] = 0x001c,
61 [RDLAR] = 0x0030,
62 [RDFAR] = 0x0034,
63 [RDFXR] = 0x0038,
64 [RDFFR] = 0x003c,
65 [TRSCER] = 0x0438,
66 [RMFCR] = 0x0440,
67 [TFTR] = 0x0448,
68 [FDR] = 0x0450,
69 [RMCR] = 0x0458,
70 [RPADIR] = 0x0460,
71 [FCFTR] = 0x0468,
72 [CSMR] = 0x04E4,
73
74 [ECMR] = 0x0500,
75 [ECSR] = 0x0510,
76 [ECSIPR] = 0x0518,
77 [PIR] = 0x0520,
78 [PSR] = 0x0528,
79 [PIPR] = 0x052c,
80 [RFLR] = 0x0508,
81 [APR] = 0x0554,
82 [MPR] = 0x0558,
83 [PFTCR] = 0x055c,
84 [PFRCR] = 0x0560,
85 [TPAUSER] = 0x0564,
86 [GECMR] = 0x05b0,
87 [BCULR] = 0x05b4,
88 [MAHR] = 0x05c0,
89 [MALR] = 0x05c8,
90 [TROCR] = 0x0700,
91 [CDCR] = 0x0708,
92 [LCCR] = 0x0710,
93 [CEFCR] = 0x0740,
94 [FRECR] = 0x0748,
95 [TSFRCR] = 0x0750,
96 [TLFRCR] = 0x0758,
97 [RFCR] = 0x0760,
98 [CERCR] = 0x0768,
99 [CEECR] = 0x0770,
100 [MAFCR] = 0x0778,
101 [RMII_MII] = 0x0790,
102
103 [ARSTR] = 0x0000,
104 [TSU_CTRST] = 0x0004,
105 [TSU_FWEN0] = 0x0010,
106 [TSU_FWEN1] = 0x0014,
107 [TSU_FCM] = 0x0018,
108 [TSU_BSYSL0] = 0x0020,
109 [TSU_BSYSL1] = 0x0024,
110 [TSU_PRISL0] = 0x0028,
111 [TSU_PRISL1] = 0x002c,
112 [TSU_FWSL0] = 0x0030,
113 [TSU_FWSL1] = 0x0034,
114 [TSU_FWSLC] = 0x0038,
4869a147
SS		 115 [TSU_QTAGM0] = 0x0040,
116 [TSU_QTAGM1] = 0x0044,
c0013f6f
SS		 117 [TSU_FWSR] = 0x0050,
118 [TSU_FWINMK] = 0x0054,
119 [TSU_ADQT0] = 0x0048,
120 [TSU_ADQT1] = 0x004c,
121 [TSU_VTAG0] = 0x0058,
122 [TSU_VTAG1] = 0x005c,
123 [TSU_ADSBSY] = 0x0060,
124 [TSU_TEN] = 0x0064,
125 [TSU_POST1] = 0x0070,
126 [TSU_POST2] = 0x0074,
127 [TSU_POST3] = 0x0078,
128 [TSU_POST4] = 0x007c,
129 [TSU_ADRH0] = 0x0100,
c0013f6f
SS		 130
131 [TXNLCR0] = 0x0080,
132 [TXALCR0] = 0x0084,
133 [RXNLCR0] = 0x0088,
134 [RXALCR0] = 0x008c,
135 [FWNLCR0] = 0x0090,
136 [FWALCR0] = 0x0094,
137 [TXNLCR1] = 0x00a0,
50f3d740 138 [TXALCR1] = 0x00a4,
c0013f6f
SS		 139 [RXNLCR1] = 0x00a8,
140 [RXALCR1] = 0x00ac,
141 [FWNLCR1] = 0x00b0,
142 [FWALCR1] = 0x00b4,
143};
144
db893473 145static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
3365711d
BH		 146 SH_ETH_OFFSET_DEFAULTS,
147
db893473
SH		 148 [EDSR] = 0x0000,
149 [EDMR] = 0x0400,
150 [EDTRR] = 0x0408,
151 [EDRRR] = 0x0410,
152 [EESR] = 0x0428,
153 [EESIPR] = 0x0430,
154 [TDLAR] = 0x0010,
155 [TDFAR] = 0x0014,
156 [TDFXR] = 0x0018,
157 [TDFFR] = 0x001c,
158 [RDLAR] = 0x0030,
159 [RDFAR] = 0x0034,
160 [RDFXR] = 0x0038,
161 [RDFFR] = 0x003c,
162 [TRSCER] = 0x0438,
163 [RMFCR] = 0x0440,
164 [TFTR] = 0x0448,
165 [FDR] = 0x0450,
166 [RMCR] = 0x0458,
167 [RPADIR] = 0x0460,
168 [FCFTR] = 0x0468,
169 [CSMR] = 0x04E4,
170
171 [ECMR] = 0x0500,
172 [RFLR] = 0x0508,
173 [ECSR] = 0x0510,
174 [ECSIPR] = 0x0518,
175 [PIR] = 0x0520,
176 [APR] = 0x0554,
177 [MPR] = 0x0558,
178 [PFTCR] = 0x055c,
179 [PFRCR] = 0x0560,
180 [TPAUSER] = 0x0564,
181 [MAHR] = 0x05c0,
182 [MALR] = 0x05c8,
183 [CEFCR] = 0x0740,
184 [FRECR] = 0x0748,
185 [TSFRCR] = 0x0750,
186 [TLFRCR] = 0x0758,
187 [RFCR] = 0x0760,
188 [MAFCR] = 0x0778,
189
190 [ARSTR] = 0x0000,
191 [TSU_CTRST] = 0x0004,
e1487888 192 [TSU_FWSLC] = 0x0038,
db893473
SH		 193 [TSU_VTAG0] = 0x0058,
194 [TSU_ADSBSY] = 0x0060,
195 [TSU_TEN] = 0x0064,
e1487888
CB		 196 [TSU_POST1] = 0x0070,
197 [TSU_POST2] = 0x0074,
198 [TSU_POST3] = 0x0078,
199 [TSU_POST4] = 0x007c,
db893473 200 [TSU_ADRH0] = 0x0100,
db893473
SH		 201
202 [TXNLCR0] = 0x0080,
203 [TXALCR0] = 0x0084,
204 [RXNLCR0] = 0x0088,
205 [RXALCR0] = 0x008C,
206};
207
a3f109bd 208static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
3365711d
BH		 209 SH_ETH_OFFSET_DEFAULTS,
210
a3f109bd
SS		 211 [ECMR] = 0x0300,
212 [RFLR] = 0x0308,
213 [ECSR] = 0x0310,
214 [ECSIPR] = 0x0318,
215 [PIR] = 0x0320,
216 [PSR] = 0x0328,
217 [RDMLR] = 0x0340,
218 [IPGR] = 0x0350,
219 [APR] = 0x0354,
220 [MPR] = 0x0358,
221 [RFCF] = 0x0360,
222 [TPAUSER] = 0x0364,
223 [TPAUSECR] = 0x0368,
224 [MAHR] = 0x03c0,
225 [MALR] = 0x03c8,
226 [TROCR] = 0x03d0,
227 [CDCR] = 0x03d4,
228 [LCCR] = 0x03d8,
229 [CNDCR] = 0x03dc,
230 [CEFCR] = 0x03e4,
231 [FRECR] = 0x03e8,
232 [TSFRCR] = 0x03ec,
233 [TLFRCR] = 0x03f0,
234 [RFCR] = 0x03f4,
235 [MAFCR] = 0x03f8,
236
237 [EDMR] = 0x0200,
238 [EDTRR] = 0x0208,
239 [EDRRR] = 0x0210,
240 [TDLAR] = 0x0218,
241 [RDLAR] = 0x0220,
242 [EESR] = 0x0228,
243 [EESIPR] = 0x0230,
244 [TRSCER] = 0x0238,
245 [RMFCR] = 0x0240,
246 [TFTR] = 0x0248,
247 [FDR] = 0x0250,
248 [RMCR] = 0x0258,
249 [TFUCR] = 0x0264,
250 [RFOCR] = 0x0268,
55754f19 251 [RMIIMODE] = 0x026c,
a3f109bd
SS		 252 [FCFTR] = 0x0270,
253 [TRIMD] = 0x027c,
254};
255
c0013f6f 256static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
3365711d
BH		 257 SH_ETH_OFFSET_DEFAULTS,
258
c0013f6f
SS		 259 [ECMR] = 0x0100,
260 [RFLR] = 0x0108,
261 [ECSR] = 0x0110,
262 [ECSIPR] = 0x0118,
263 [PIR] = 0x0120,
264 [PSR] = 0x0128,
265 [RDMLR] = 0x0140,
266 [IPGR] = 0x0150,
267 [APR] = 0x0154,
268 [MPR] = 0x0158,
269 [TPAUSER] = 0x0164,
270 [RFCF] = 0x0160,
271 [TPAUSECR] = 0x0168,
272 [BCFRR] = 0x016c,
273 [MAHR] = 0x01c0,
274 [MALR] = 0x01c8,
275 [TROCR] = 0x01d0,
276 [CDCR] = 0x01d4,
277 [LCCR] = 0x01d8,
278 [CNDCR] = 0x01dc,
279 [CEFCR] = 0x01e4,
280 [FRECR] = 0x01e8,
281 [TSFRCR] = 0x01ec,
282 [TLFRCR] = 0x01f0,
283 [RFCR] = 0x01f4,
284 [MAFCR] = 0x01f8,
285 [RTRATE] = 0x01fc,
286
287 [EDMR] = 0x0000,
288 [EDTRR] = 0x0008,
289 [EDRRR] = 0x0010,
290 [TDLAR] = 0x0018,
291 [RDLAR] = 0x0020,
292 [EESR] = 0x0028,
293 [EESIPR] = 0x0030,
294 [TRSCER] = 0x0038,
295 [RMFCR] = 0x0040,
296 [TFTR] = 0x0048,
297 [FDR] = 0x0050,
298 [RMCR] = 0x0058,
299 [TFUCR] = 0x0064,
300 [RFOCR] = 0x0068,
301 [FCFTR] = 0x0070,
302 [RPADIR] = 0x0078,
303 [TRIMD] = 0x007c,
304 [RBWAR] = 0x00c8,
305 [RDFAR] = 0x00cc,
306 [TBRAR] = 0x00d4,
307 [TDFAR] = 0x00d8,
308};
309
310static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
3365711d
BH		 311 SH_ETH_OFFSET_DEFAULTS,
312
d8b0426a
SS		 313 [EDMR] = 0x0000,
314 [EDTRR] = 0x0004,
315 [EDRRR] = 0x0008,
316 [TDLAR] = 0x000c,
317 [RDLAR] = 0x0010,
318 [EESR] = 0x0014,
319 [EESIPR] = 0x0018,
320 [TRSCER] = 0x001c,
321 [RMFCR] = 0x0020,
322 [TFTR] = 0x0024,
323 [FDR] = 0x0028,
324 [RMCR] = 0x002c,
325 [EDOCR] = 0x0030,
326 [FCFTR] = 0x0034,
327 [RPADIR] = 0x0038,
328 [TRIMD] = 0x003c,
329 [RBWAR] = 0x0040,
330 [RDFAR] = 0x0044,
331 [TBRAR] = 0x004c,
332 [TDFAR] = 0x0050,
333
c0013f6f
SS		 334 [ECMR] = 0x0160,
335 [ECSR] = 0x0164,
336 [ECSIPR] = 0x0168,
337 [PIR] = 0x016c,
338 [MAHR] = 0x0170,
339 [MALR] = 0x0174,
340 [RFLR] = 0x0178,
341 [PSR] = 0x017c,
342 [TROCR] = 0x0180,
343 [CDCR] = 0x0184,
344 [LCCR] = 0x0188,
345 [CNDCR] = 0x018c,
346 [CEFCR] = 0x0194,
347 [FRECR] = 0x0198,
348 [TSFRCR] = 0x019c,
349 [TLFRCR] = 0x01a0,
350 [RFCR] = 0x01a4,
351 [MAFCR] = 0x01a8,
352 [IPGR] = 0x01b4,
353 [APR] = 0x01b8,
354 [MPR] = 0x01bc,
355 [TPAUSER] = 0x01c4,
356 [BCFR] = 0x01cc,
357
358 [ARSTR] = 0x0000,
359 [TSU_CTRST] = 0x0004,
360 [TSU_FWEN0] = 0x0010,
361 [TSU_FWEN1] = 0x0014,
362 [TSU_FCM] = 0x0018,
363 [TSU_BSYSL0] = 0x0020,
364 [TSU_BSYSL1] = 0x0024,
365 [TSU_PRISL0] = 0x0028,
366 [TSU_PRISL1] = 0x002c,
367 [TSU_FWSL0] = 0x0030,
368 [TSU_FWSL1] = 0x0034,
369 [TSU_FWSLC] = 0x0038,
370 [TSU_QTAGM0] = 0x0040,
371 [TSU_QTAGM1] = 0x0044,
372 [TSU_ADQT0] = 0x0048,
373 [TSU_ADQT1] = 0x004c,
374 [TSU_FWSR] = 0x0050,
375 [TSU_FWINMK] = 0x0054,
376 [TSU_ADSBSY] = 0x0060,
377 [TSU_TEN] = 0x0064,
378 [TSU_POST1] = 0x0070,
379 [TSU_POST2] = 0x0074,
380 [TSU_POST3] = 0x0078,
381 [TSU_POST4] = 0x007c,
382
383 [TXNLCR0] = 0x0080,
384 [TXALCR0] = 0x0084,
385 [RXNLCR0] = 0x0088,
386 [RXALCR0] = 0x008c,
387 [FWNLCR0] = 0x0090,
388 [FWALCR0] = 0x0094,
389 [TXNLCR1] = 0x00a0,
50f3d740 390 [TXALCR1] = 0x00a4,
c0013f6f
SS		 391 [RXNLCR1] = 0x00a8,
392 [RXALCR1] = 0x00ac,
393 [FWNLCR1] = 0x00b0,
394 [FWALCR1] = 0x00b4,
395
396 [TSU_ADRH0] = 0x0100,
c0013f6f
SS		 397};
398
740c7f31
BH		 399static void sh_eth_rcv_snd_disable(struct net_device *ndev);
400static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev);
401
2274d375
SS		 402static void sh_eth_write(struct net_device *ndev, u32 data, int enum_index)
403{
404 struct sh_eth_private *mdp = netdev_priv(ndev);
405 u16 offset = mdp->reg_offset[enum_index];
406
407 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
408 return;
409
410 iowrite32(data, mdp->addr + offset);
411}
412
413static u32 sh_eth_read(struct net_device *ndev, int enum_index)
414{
415 struct sh_eth_private *mdp = netdev_priv(ndev);
416 u16 offset = mdp->reg_offset[enum_index];
417
418 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
419 return ~0U;
420
421 return ioread32(mdp->addr + offset);
422}
423
b2b14d2f
SS		 424static void sh_eth_modify(struct net_device *ndev, int enum_index, u32 clear,
425 u32 set)
426{
427 sh_eth_write(ndev, (sh_eth_read(ndev, enum_index) & ~clear) | set,
428 enum_index);
429}
430
41414f0a 431static u16 sh_eth_tsu_get_offset(struct sh_eth_private *mdp, int enum_index)
388c4bb4 432{
41414f0a 433 return mdp->reg_offset[enum_index];
388c4bb4
SS		 434}
435
55ea8743
SS		 436static void sh_eth_tsu_write(struct sh_eth_private *mdp, u32 data,
437 int enum_index)
438{
ecbecb0a 439 u16 offset = sh_eth_tsu_get_offset(mdp, enum_index);
627a0d20
SS		 440
441 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
442 return;
443
444 iowrite32(data, mdp->tsu_addr + offset);
55ea8743
SS		 445}
446
447static u32 sh_eth_tsu_read(struct sh_eth_private *mdp, int enum_index)
448{
ecbecb0a 449 u16 offset = sh_eth_tsu_get_offset(mdp, enum_index);
627a0d20
SS		 450
451 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
452 return ~0U;
453
454 return ioread32(mdp->tsu_addr + offset);
55ea8743
SS		 455}
456
bb2fa4e8
SS		 457static void sh_eth_soft_swap(char *src, int len)
458{
459#ifdef __LITTLE_ENDIAN
460 u32 *p = (u32 *)src;
1100149a 461 u32 *maxp = p + DIV_ROUND_UP(len, sizeof(u32));
bb2fa4e8
SS		 462
463 for (; p < maxp; p++)
464 *p = swab32(*p);
465#endif
466}
467
8e994402 468static void sh_eth_select_mii(struct net_device *ndev)
5e7a76be 469{
5e7a76be 470 struct sh_eth_private *mdp = netdev_priv(ndev);
4fa8c3cc 471 u32 value;
5e7a76be
NI		 472
473 switch (mdp->phy_interface) {
230c1846
SS		 474 case PHY_INTERFACE_MODE_RGMII ... PHY_INTERFACE_MODE_RGMII_TXID:
475 value = 0x3;
476 break;
5e7a76be
NI		 477 case PHY_INTERFACE_MODE_GMII:
478 value = 0x2;
479 break;
480 case PHY_INTERFACE_MODE_MII:
481 value = 0x1;
482 break;
483 case PHY_INTERFACE_MODE_RMII:
484 value = 0x0;
485 break;
486 default:
f75f14ec
SS		 487 netdev_warn(ndev,
488 "PHY interface mode was not setup. Set to MII.\n");
5e7a76be
NI		 489 value = 0x1;
490 break;
491 }
492
493 sh_eth_write(ndev, value, RMII_MII);
494}
5e7a76be 495
8e994402 496static void sh_eth_set_duplex(struct net_device *ndev)
65ac8851
YS		 497{
498 struct sh_eth_private *mdp = netdev_priv(ndev);
65ac8851 499
b2b14d2f 500 sh_eth_modify(ndev, ECMR, ECMR_DM, mdp->duplex ? ECMR_DM : 0);
65ac8851
YS		 501}
502
99f84be6
GU		 503static void sh_eth_chip_reset(struct net_device *ndev)
504{
505 struct sh_eth_private *mdp = netdev_priv(ndev);
506
507 /* reset device */
ec65cfce 508 sh_eth_tsu_write(mdp, ARSTR_ARST, ARSTR);
99f84be6
GU		 509 mdelay(1);
510}
511
4ceedeb1
SS		 512static int sh_eth_soft_reset(struct net_device *ndev)
513{
514 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, EDMR_SRST_ETHER);
515 mdelay(3);
516 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, 0);
517
518 return 0;
519}
520
521static int sh_eth_check_soft_reset(struct net_device *ndev)
522{
523 int cnt;
524
525 for (cnt = 100; cnt > 0; cnt--) {
526 if (!(sh_eth_read(ndev, EDMR) & EDMR_SRST_GETHER))
527 return 0;
528 mdelay(1);
529 }
530
531 netdev_err(ndev, "Device reset failed\n");
532 return -ETIMEDOUT;
533}
534
535static int sh_eth_soft_reset_gether(struct net_device *ndev)
536{
537 struct sh_eth_private *mdp = netdev_priv(ndev);
538 int ret;
539
540 sh_eth_write(ndev, EDSR_ENALL, EDSR);
541 sh_eth_modify(ndev, EDMR, EDMR_SRST_GETHER, EDMR_SRST_GETHER);
542
543 ret = sh_eth_check_soft_reset(ndev);
544 if (ret)
545 return ret;
546
547 /* Table Init */
548 sh_eth_write(ndev, 0, TDLAR);
549 sh_eth_write(ndev, 0, TDFAR);
550 sh_eth_write(ndev, 0, TDFXR);
551 sh_eth_write(ndev, 0, TDFFR);
552 sh_eth_write(ndev, 0, RDLAR);
553 sh_eth_write(ndev, 0, RDFAR);
554 sh_eth_write(ndev, 0, RDFXR);
555 sh_eth_write(ndev, 0, RDFFR);
556
557 /* Reset HW CRC register */
2c2ab5af 558 if (mdp->cd->csmr)
4ceedeb1
SS		 559 sh_eth_write(ndev, 0, CSMR);
560
561 /* Select MII mode */
562 if (mdp->cd->select_mii)
563 sh_eth_select_mii(ndev);
564
565 return ret;
566}
567
a0f48be3
GU		 568static void sh_eth_set_rate_gether(struct net_device *ndev)
569{
570 struct sh_eth_private *mdp = netdev_priv(ndev);
571
572 switch (mdp->speed) {
573 case 10: /* 10BASE */
574 sh_eth_write(ndev, GECMR_10, GECMR);
575 break;
576 case 100:/* 100BASE */
577 sh_eth_write(ndev, GECMR_100, GECMR);
578 break;
579 case 1000: /* 1000BASE */
580 sh_eth_write(ndev, GECMR_1000, GECMR);
581 break;
a0f48be3
GU		 582 }
583}
584
99f84be6
GU		 585#ifdef CONFIG_OF
586/* R7S72100 */
587static struct sh_eth_cpu_data r7s72100_data = {
4ceedeb1
SS		 588 .soft_reset = sh_eth_soft_reset_gether,
589
99f84be6
GU		 590 .chip_reset = sh_eth_chip_reset,
591 .set_duplex = sh_eth_set_duplex,
592
593 .register_type = SH_ETH_REG_FAST_RZ,
594
3e416992 595 .edtrr_trns = EDTRR_TRNS_GETHER,
99f84be6
GU		 596 .ecsr_value = ECSR_ICD,
597 .ecsipr_value = ECSIPR_ICDIP,
2b2d3eb4
SS		 598 .eesipr_value = EESIPR_TWB1IP | EESIPR_TWBIP | EESIPR_TC1IP |
599 EESIPR_TABTIP | EESIPR_RABTIP | EESIPR_RFCOFIP |
600 EESIPR_ECIIP |
601 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
602 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
603 EESIPR_RMAFIP | EESIPR_RRFIP |
604 EESIPR_RTLFIP | EESIPR_RTSFIP |
605 EESIPR_PREIP | EESIPR_CERFIP,
99f84be6
GU		 606
607 .tx_check = EESR_TC1 | EESR_FTC,
608 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
609 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
9b39f05c 610 EESR_TDE,
99f84be6
GU		 611 .fdr_value = 0x0000070f,
612
613 .no_psr = 1,
614 .apr = 1,
615 .mpr = 1,
616 .tpauser = 1,
617 .hw_swap = 1,
618 .rpadir = 1,
99f84be6
GU		 619 .no_trimd = 1,
620 .no_ade = 1,
246e30cc 621 .xdfar_rw = 1,
2c2ab5af 622 .csmr = 1,
48132cd0 623 .rx_csum = 1,
99f84be6 624 .tsu = 1,
ce9134df 625 .no_tx_cntrs = 1,
99f84be6 626};
a0f48be3
GU		 627
628static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
629{
c66b2581 630 sh_eth_chip_reset(ndev);
a0f48be3
GU		 631
632 sh_eth_select_mii(ndev);
633}
634
635/* R8A7740 */
636static struct sh_eth_cpu_data r8a7740_data = {
4ceedeb1
SS		 637 .soft_reset = sh_eth_soft_reset_gether,
638
a0f48be3
GU		 639 .chip_reset = sh_eth_chip_reset_r8a7740,
640 .set_duplex = sh_eth_set_duplex,
641 .set_rate = sh_eth_set_rate_gether,
642
643 .register_type = SH_ETH_REG_GIGABIT,
644
3e416992 645 .edtrr_trns = EDTRR_TRNS_GETHER,
a0f48be3
GU		 646 .ecsr_value = ECSR_ICD | ECSR_MPD,
647 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
2b2d3eb4
SS		 648 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
649 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
650 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
651 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
652 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
653 EESIPR_CEEFIP | EESIPR_CELFIP |
654 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
655 EESIPR_PREIP | EESIPR_CERFIP,
a0f48be3
GU		 656
657 .tx_check = EESR_TC1 | EESR_FTC,
658 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
659 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
9b39f05c 660 EESR_TDE,
a0f48be3
GU		 661 .fdr_value = 0x0000070f,
662
663 .apr = 1,
664 .mpr = 1,
665 .tpauser = 1,
666 .bculr = 1,
667 .hw_swap = 1,
668 .rpadir = 1,
a0f48be3
GU		 669 .no_trimd = 1,
670 .no_ade = 1,
246e30cc 671 .xdfar_rw = 1,
2c2ab5af 672 .csmr = 1,
040c16fd 673 .rx_csum = 1,
a0f48be3
GU		 674 .tsu = 1,
675 .select_mii = 1,
33017e24 676 .magic = 1,
4c1d4585 677 .cexcr = 1,
a0f48be3 678};
99f84be6 679
04b0ed2a 680/* There is CPU dependent code */
6c4b2f7e 681static void sh_eth_set_rate_rcar(struct net_device *ndev)
65ac8851
YS		 682{
683 struct sh_eth_private *mdp = netdev_priv(ndev);
d0418bb7 684
a3f109bd
SS		 685 switch (mdp->speed) {
686 case 10: /* 10BASE */
b2b14d2f 687 sh_eth_modify(ndev, ECMR, ECMR_ELB, 0);
a3f109bd
SS		 688 break;
689 case 100:/* 100BASE */
b2b14d2f 690 sh_eth_modify(ndev, ECMR, ECMR_ELB, ECMR_ELB);
a3f109bd 691 break;
a3f109bd
SS		 692 }
693}
694
6c4b2f7e
SH		 695/* R-Car Gen1 */
696static struct sh_eth_cpu_data rcar_gen1_data = {
4ceedeb1
SS		 697 .soft_reset = sh_eth_soft_reset,
698
a3f109bd 699 .set_duplex = sh_eth_set_duplex,
6c4b2f7e 700 .set_rate = sh_eth_set_rate_rcar,
a3f109bd 701
a3153d8c
SS		 702 .register_type = SH_ETH_REG_FAST_RCAR,
703
3e416992 704 .edtrr_trns = EDTRR_TRNS_ETHER,
a3f109bd
SS		 705 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
706 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
2b2d3eb4
SS		 707 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP |
708 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
709 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
710 EESIPR_RMAFIP | EESIPR_RRFIP |
711 EESIPR_RTLFIP | EESIPR_RTSFIP |
712 EESIPR_PREIP | EESIPR_CERFIP,
a3f109bd 713
27164491 714 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO,
ca8c3585 715 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
9b39f05c 716 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
d407bc02 717 .fdr_value = 0x00000f0f,
a3f109bd
SS		 718
719 .apr = 1,
720 .mpr = 1,
721 .tpauser = 1,
722 .hw_swap = 1,
6e80e55b 723 .no_xdfar = 1,
a3f109bd 724};
a3f109bd 725
6c4b2f7e
SH		 726/* R-Car Gen2 and RZ/G1 */
727static struct sh_eth_cpu_data rcar_gen2_data = {
4ceedeb1
SS		 728 .soft_reset = sh_eth_soft_reset,
729
e18dbf7e 730 .set_duplex = sh_eth_set_duplex,
6c4b2f7e 731 .set_rate = sh_eth_set_rate_rcar,
e18dbf7e 732
a3153d8c
SS		 733 .register_type = SH_ETH_REG_FAST_RCAR,
734
3e416992 735 .edtrr_trns = EDTRR_TRNS_ETHER,
e410d86d
NS		 736 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD | ECSR_MPD,
737 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP |
738 ECSIPR_MPDIP,
2b2d3eb4
SS		 739 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP |
740 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
741 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
742 EESIPR_RMAFIP | EESIPR_RRFIP |
743 EESIPR_RTLFIP | EESIPR_RTSFIP |
744 EESIPR_PREIP | EESIPR_CERFIP,
e18dbf7e 745
27164491 746 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO,
ba361cb3 747 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
9b39f05c 748 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
d407bc02 749 .fdr_value = 0x00000f0f,
e18dbf7e 750
01fbd3f5
GU		 751 .trscer_err_mask = DESC_I_RINT8,
752
e18dbf7e
SH		 753 .apr = 1,
754 .mpr = 1,
755 .tpauser = 1,
756 .hw_swap = 1,
6e80e55b 757 .no_xdfar = 1,
e18dbf7e 758 .rmiimode = 1,
e410d86d 759 .magic = 1,
e18dbf7e 760};
3eb9c2ad
SS		 761
762/* R8A77980 */
763static struct sh_eth_cpu_data r8a77980_data = {
764 .soft_reset = sh_eth_soft_reset_gether,
765
766 .set_duplex = sh_eth_set_duplex,
767 .set_rate = sh_eth_set_rate_gether,
768
769 .register_type = SH_ETH_REG_GIGABIT,
770
771 .edtrr_trns = EDTRR_TRNS_GETHER,
772 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD | ECSR_MPD,
773 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP |
774 ECSIPR_MPDIP,
775 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
776 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
777 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
778 EESIPR_RMAFIP | EESIPR_RRFIP |
779 EESIPR_RTLFIP | EESIPR_RTSFIP |
780 EESIPR_PREIP | EESIPR_CERFIP,
781
27164491 782 .tx_check = EESR_FTC | EESR_CD | EESR_TRO,
3eb9c2ad
SS		 783 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
784 EESR_RFE | EESR_RDE | EESR_RFRMER |
785 EESR_TFE | EESR_TDE | EESR_ECI,
786 .fdr_value = 0x0000070f,
787
788 .apr = 1,
789 .mpr = 1,
790 .tpauser = 1,
791 .bculr = 1,
792 .hw_swap = 1,
793 .nbst = 1,
794 .rpadir = 1,
3eb9c2ad
SS		 795 .no_trimd = 1,
796 .no_ade = 1,
797 .xdfar_rw = 1,
2c2ab5af 798 .csmr = 1,
0da843ad 799 .rx_csum = 1,
3eb9c2ad
SS		 800 .select_mii = 1,
801 .magic = 1,
802 .cexcr = 1,
803};
6e0bb04d
CB		 804
805/* R7S9210 */
806static struct sh_eth_cpu_data r7s9210_data = {
807 .soft_reset = sh_eth_soft_reset,
808
809 .set_duplex = sh_eth_set_duplex,
810 .set_rate = sh_eth_set_rate_rcar,
811
812 .register_type = SH_ETH_REG_FAST_SH4,
813
814 .edtrr_trns = EDTRR_TRNS_ETHER,
815 .ecsr_value = ECSR_ICD,
816 .ecsipr_value = ECSIPR_ICDIP,
817 .eesipr_value = EESIPR_TWBIP | EESIPR_TABTIP | EESIPR_RABTIP |
818 EESIPR_RFCOFIP | EESIPR_ECIIP | EESIPR_FTCIP |
819 EESIPR_TDEIP | EESIPR_TFUFIP | EESIPR_FRIP |
820 EESIPR_RDEIP | EESIPR_RFOFIP | EESIPR_CNDIP |
821 EESIPR_DLCIP | EESIPR_CDIP | EESIPR_TROIP |
822 EESIPR_RMAFIP | EESIPR_RRFIP | EESIPR_RTLFIP |
823 EESIPR_RTSFIP | EESIPR_PREIP | EESIPR_CERFIP,
824
825 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO,
826 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
827 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
828
829 .fdr_value = 0x0000070f,
830
831 .apr = 1,
832 .mpr = 1,
833 .tpauser = 1,
834 .hw_swap = 1,
835 .rpadir = 1,
836 .no_ade = 1,
837 .xdfar_rw = 1,
838};
c74a2248 839#endif /* CONFIG_OF */
e18dbf7e 840
9c3beaab 841static void sh_eth_set_rate_sh7724(struct net_device *ndev)
a3f109bd
SS		 842{
843 struct sh_eth_private *mdp = netdev_priv(ndev);
65ac8851
YS		 844
845 switch (mdp->speed) {
846 case 10: /* 10BASE */
b2b14d2f 847 sh_eth_modify(ndev, ECMR, ECMR_RTM, 0);
65ac8851
YS		 848 break;
849 case 100:/* 100BASE */
b2b14d2f 850 sh_eth_modify(ndev, ECMR, ECMR_RTM, ECMR_RTM);
65ac8851 851 break;
65ac8851
YS		 852 }
853}
854
855/* SH7724 */
9c3beaab 856static struct sh_eth_cpu_data sh7724_data = {
4ceedeb1
SS		 857 .soft_reset = sh_eth_soft_reset,
858
65ac8851 859 .set_duplex = sh_eth_set_duplex,
9c3beaab 860 .set_rate = sh_eth_set_rate_sh7724,
65ac8851 861
a3153d8c
SS		 862 .register_type = SH_ETH_REG_FAST_SH4,
863
3e416992 864 .edtrr_trns = EDTRR_TRNS_ETHER,
65ac8851
YS		 865 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
866 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
2b2d3eb4
SS		 867 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP |
868 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
869 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
870 EESIPR_RMAFIP | EESIPR_RRFIP |
871 EESIPR_RTLFIP | EESIPR_RTSFIP |
872 EESIPR_PREIP | EESIPR_CERFIP,
65ac8851 873
27164491 874 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO,
ca8c3585 875 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
9b39f05c 876 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
65ac8851
YS		 877
878 .apr = 1,
879 .mpr = 1,
880 .tpauser = 1,
881 .hw_swap = 1,
503914cf 882 .rpadir = 1,
65ac8851 883};
5cee1d37 884
24549e2a 885static void sh_eth_set_rate_sh7757(struct net_device *ndev)
f29a3d04
YS		 886{
887 struct sh_eth_private *mdp = netdev_priv(ndev);
f29a3d04
YS		 888
889 switch (mdp->speed) {
890 case 10: /* 10BASE */
4a55530f 891 sh_eth_write(ndev, 0, RTRATE);
f29a3d04
YS		 892 break;
893 case 100:/* 100BASE */
4a55530f 894 sh_eth_write(ndev, 1, RTRATE);
f29a3d04 895 break;
f29a3d04
YS		 896 }
897}
898
899/* SH7757 */
24549e2a 900static struct sh_eth_cpu_data sh7757_data = {
4ceedeb1
SS		 901 .soft_reset = sh_eth_soft_reset,
902
24549e2a
SS		 903 .set_duplex = sh_eth_set_duplex,
904 .set_rate = sh_eth_set_rate_sh7757,
f29a3d04 905
a3153d8c
SS		 906 .register_type = SH_ETH_REG_FAST_SH4,
907
3e416992 908 .edtrr_trns = EDTRR_TRNS_ETHER,
2b2d3eb4
SS		 909 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
910 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
911 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
912 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
913 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
914 EESIPR_CEEFIP | EESIPR_CELFIP |
915 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
916 EESIPR_PREIP | EESIPR_CERFIP,
f29a3d04 917
27164491 918 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO,
ca8c3585 919 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
9b39f05c 920 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
f29a3d04 921
5b3dfd13 922 .irq_flags = IRQF_SHARED,
f29a3d04
YS		 923 .apr = 1,
924 .mpr = 1,
925 .tpauser = 1,
926 .hw_swap = 1,
927 .no_ade = 1,
2e98e797 928 .rpadir = 1,
6b4b4fea 929 .rtrate = 1,
a94cf2a6 930 .dual_port = 1,
f29a3d04 931};
65ac8851 932
e403d295 933#define SH_GIGA_ETH_BASE 0xfee00000UL
8fcd4961
YS		 934#define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
935#define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
936static void sh_eth_chip_reset_giga(struct net_device *ndev)
937{
0799c2d6 938 u32 mahr[2], malr[2];
79270922 939 int i;
8fcd4961
YS		 940
941 /* save MAHR and MALR */
942 for (i = 0; i < 2; i++) {
ae70644d
YS		 943 malr[i] = ioread32((void *)GIGA_MALR(i));
944 mahr[i] = ioread32((void *)GIGA_MAHR(i));
8fcd4961
YS		 945 }
946
c66b2581 947 sh_eth_chip_reset(ndev);
8fcd4961
YS		 948
949 /* restore MAHR and MALR */
950 for (i = 0; i < 2; i++) {
ae70644d
YS		 951 iowrite32(malr[i], (void *)GIGA_MALR(i));
952 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
8fcd4961
YS		 953 }
954}
955
8fcd4961
YS		 956static void sh_eth_set_rate_giga(struct net_device *ndev)
957{
958 struct sh_eth_private *mdp = netdev_priv(ndev);
959
960 switch (mdp->speed) {
961 case 10: /* 10BASE */
962 sh_eth_write(ndev, 0x00000000, GECMR);
963 break;
964 case 100:/* 100BASE */
965 sh_eth_write(ndev, 0x00000010, GECMR);
966 break;
967 case 1000: /* 1000BASE */
968 sh_eth_write(ndev, 0x00000020, GECMR);
969 break;
8fcd4961
YS		 970 }
971}
972
973/* SH7757(GETHERC) */
24549e2a 974static struct sh_eth_cpu_data sh7757_data_giga = {
4ceedeb1
SS		 975 .soft_reset = sh_eth_soft_reset_gether,
976
8fcd4961 977 .chip_reset = sh_eth_chip_reset_giga,
04b0ed2a 978 .set_duplex = sh_eth_set_duplex,
8fcd4961
YS		 979 .set_rate = sh_eth_set_rate_giga,
980
a3153d8c
SS		 981 .register_type = SH_ETH_REG_GIGABIT,
982
3e416992 983 .edtrr_trns = EDTRR_TRNS_GETHER,
8fcd4961
YS		 984 .ecsr_value = ECSR_ICD | ECSR_MPD,
985 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
2b2d3eb4
SS		 986 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
987 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
988 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
989 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
990 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
991 EESIPR_CEEFIP | EESIPR_CELFIP |
992 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
993 EESIPR_PREIP | EESIPR_CERFIP,
8fcd4961
YS		 994
995 .tx_check = EESR_TC1 | EESR_FTC,
ca8c3585
SS		 996 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
997 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
9b39f05c 998 EESR_TDE,
8fcd4961 999 .fdr_value = 0x0000072f,
8fcd4961 1000
5b3dfd13 1001 .irq_flags = IRQF_SHARED,
8fcd4961
YS		 1002 .apr = 1,
1003 .mpr = 1,
1004 .tpauser = 1,
1005 .bculr = 1,
1006 .hw_swap = 1,
1007 .rpadir = 1,
8fcd4961
YS		 1008 .no_trimd = 1,
1009 .no_ade = 1,
246e30cc 1010 .xdfar_rw = 1,
3acbc971 1011 .tsu = 1,
4c1d4585 1012 .cexcr = 1,
a94cf2a6 1013 .dual_port = 1,
8fcd4961
YS		 1014};
1015
f5d12767
SS		 1016/* SH7734 */
1017static struct sh_eth_cpu_data sh7734_data = {
4ceedeb1
SS		 1018 .soft_reset = sh_eth_soft_reset_gether,
1019
380af9e3
YS		 1020 .chip_reset = sh_eth_chip_reset,
1021 .set_duplex = sh_eth_set_duplex,
f5d12767
SS		 1022 .set_rate = sh_eth_set_rate_gether,
1023
a3153d8c
SS		 1024 .register_type = SH_ETH_REG_GIGABIT,
1025
3e416992 1026 .edtrr_trns = EDTRR_TRNS_GETHER,
f5d12767
SS		 1027 .ecsr_value = ECSR_ICD | ECSR_MPD,
1028 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
2b2d3eb4
SS		 1029 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
1030 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
1031 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
1032 EESIPR_DLCIP | EESIPR_CDIP | EESIPR_TROIP |
1033 EESIPR_RMAFIP | EESIPR_CEEFIP | EESIPR_CELFIP |
1034 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
1035 EESIPR_PREIP | EESIPR_CERFIP,
f5d12767
SS		 1036
1037 .tx_check = EESR_TC1 | EESR_FTC,
ca8c3585
SS		 1038 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
1039 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
9b39f05c 1040 EESR_TDE,
f5d12767
SS		 1041
1042 .apr = 1,
1043 .mpr = 1,
1044 .tpauser = 1,
1045 .bculr = 1,
1046 .hw_swap = 1,
1047 .no_trimd = 1,
1048 .no_ade = 1,
246e30cc 1049 .xdfar_rw = 1,
f5d12767 1050 .tsu = 1,
2c2ab5af 1051 .csmr = 1,
06240e1b 1052 .rx_csum = 1,
f5d12767 1053 .select_mii = 1,
159c2a90 1054 .magic = 1,
4c1d4585 1055 .cexcr = 1,
f5d12767
SS		 1056};
1057
1058/* SH7763 */
1059static struct sh_eth_cpu_data sh7763_data = {
4ceedeb1
SS		 1060 .soft_reset = sh_eth_soft_reset_gether,
1061
f5d12767
SS		 1062 .chip_reset = sh_eth_chip_reset,
1063 .set_duplex = sh_eth_set_duplex,
1064 .set_rate = sh_eth_set_rate_gether,
380af9e3 1065
a3153d8c
SS		 1066 .register_type = SH_ETH_REG_GIGABIT,
1067
3e416992 1068 .edtrr_trns = EDTRR_TRNS_GETHER,
380af9e3
YS		 1069 .ecsr_value = ECSR_ICD | ECSR_MPD,
1070 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
2b2d3eb4
SS		 1071 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
1072 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
1073 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
1074 EESIPR_DLCIP | EESIPR_CDIP | EESIPR_TROIP |
1075 EESIPR_RMAFIP | EESIPR_CEEFIP | EESIPR_CELFIP |
1076 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
1077 EESIPR_PREIP | EESIPR_CERFIP,
380af9e3
YS		 1078
1079 .tx_check = EESR_TC1 | EESR_FTC,
128296fc 1080 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
9b39f05c 1081 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
380af9e3
YS		 1082
1083 .apr = 1,
1084 .mpr = 1,
1085 .tpauser = 1,
1086 .bculr = 1,
1087 .hw_swap = 1,
380af9e3
YS		 1088 .no_trimd = 1,
1089 .no_ade = 1,
246e30cc 1090 .xdfar_rw = 1,
4986b996 1091 .tsu = 1,
5b3dfd13 1092 .irq_flags = IRQF_SHARED,
267e1d5c 1093 .magic = 1,
4c1d4585 1094 .cexcr = 1,
997feb11 1095 .rx_csum = 1,
a94cf2a6 1096 .dual_port = 1,
380af9e3
YS		 1097};
1098
c18a79ab 1099static struct sh_eth_cpu_data sh7619_data = {
4ceedeb1
SS		 1100 .soft_reset = sh_eth_soft_reset,
1101
a3153d8c
SS		 1102 .register_type = SH_ETH_REG_FAST_SH3_SH2,
1103
3e416992 1104 .edtrr_trns = EDTRR_TRNS_ETHER,
2b2d3eb4
SS		 1105 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
1106 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
1107 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
1108 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
1109 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
1110 EESIPR_CEEFIP | EESIPR_CELFIP |
1111 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
1112 EESIPR_PREIP | EESIPR_CERFIP,
380af9e3
YS		 1113
1114 .apr = 1,
1115 .mpr = 1,
1116 .tpauser = 1,
1117 .hw_swap = 1,
1118};
7bbe150d
SS		 1119
1120static struct sh_eth_cpu_data sh771x_data = {
4ceedeb1
SS		 1121 .soft_reset = sh_eth_soft_reset,
1122
a3153d8c
SS		 1123 .register_type = SH_ETH_REG_FAST_SH3_SH2,
1124
3e416992 1125 .edtrr_trns = EDTRR_TRNS_ETHER,
2b2d3eb4
SS		 1126 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
1127 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
1128 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
1129 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
1130 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
1131 EESIPR_CEEFIP | EESIPR_CELFIP |
1132 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
1133 EESIPR_PREIP | EESIPR_CERFIP,
4986b996 1134 .tsu = 1,
a94cf2a6 1135 .dual_port = 1,
380af9e3 1136};
380af9e3
YS		 1137
1138static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
1139{
1140 if (!cd->ecsr_value)
1141 cd->ecsr_value = DEFAULT_ECSR_INIT;
1142
1143 if (!cd->ecsipr_value)
1144 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
1145
1146 if (!cd->fcftr_value)
128296fc 1147 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF |
380af9e3
YS		 1148 DEFAULT_FIFO_F_D_RFD;
1149
1150 if (!cd->fdr_value)
1151 cd->fdr_value = DEFAULT_FDR_INIT;
1152
380af9e3
YS		 1153 if (!cd->tx_check)
1154 cd->tx_check = DEFAULT_TX_CHECK;
1155
1156 if (!cd->eesr_err_check)
1157 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
b284fbe3
NI		 1158
1159 if (!cd->trscer_err_mask)
1160 cd->trscer_err_mask = DEFAULT_TRSCER_ERR_MASK;
380af9e3
YS		 1161}
1162
380af9e3
YS		 1163static void sh_eth_set_receive_align(struct sk_buff *skb)
1164{
4d6a949c 1165 uintptr_t reserve = (uintptr_t)skb->data & (SH_ETH_RX_ALIGN - 1);
380af9e3 1166
380af9e3 1167 if (reserve)
4d6a949c 1168 skb_reserve(skb, SH_ETH_RX_ALIGN - reserve);
380af9e3 1169}
380af9e3 1170
128296fc 1171/* Program the hardware MAC address from dev->dev_addr. */
86a74ff2
NI		 1172static void update_mac_address(struct net_device *ndev)
1173{
4a55530f 1174 sh_eth_write(ndev,
128296fc
SS		 1175 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
1176 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
4a55530f 1177 sh_eth_write(ndev,
128296fc 1178 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
86a74ff2
NI		 1179}
1180
128296fc 1181/* Get MAC address from SuperH MAC address register
86a74ff2
NI		 1182 *
1183 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
1184 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
1185 * When you want use this device, you must set MAC address in bootloader.
1186 *
1187 */
748031f9 1188static void read_mac_address(struct net_device *ndev, unsigned char *mac)
86a74ff2 1189{
748031f9 1190 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
d458cdf7 1191 memcpy(ndev->dev_addr, mac, ETH_ALEN);
748031f9 1192 } else {
37742f02
SS		 1193 u32 mahr = sh_eth_read(ndev, MAHR);
1194 u32 malr = sh_eth_read(ndev, MALR);
1195
1196 ndev->dev_addr[0] = (mahr >> 24) & 0xFF;
1197 ndev->dev_addr[1] = (mahr >> 16) & 0xFF;
1198 ndev->dev_addr[2] = (mahr >> 8) & 0xFF;
1199 ndev->dev_addr[3] = (mahr >> 0) & 0xFF;
1200 ndev->dev_addr[4] = (malr >> 8) & 0xFF;
1201 ndev->dev_addr[5] = (malr >> 0) & 0xFF;
748031f9 1202 }
86a74ff2
NI		 1203}
1204
1205struct bb_info {
ae70644d 1206 void (*set_gate)(void *addr);
86a74ff2 1207 struct mdiobb_ctrl ctrl;
ae70644d 1208 void *addr;
86a74ff2
NI		 1209};
1210
39b4b06b 1211static void sh_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set)
86a74ff2
NI		 1212{
1213 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
78fa3c5c 1214 u32 pir;
b3017e6a
YS		 1215
1216 if (bitbang->set_gate)
1217 bitbang->set_gate(bitbang->addr);
1218
78fa3c5c 1219 pir = ioread32(bitbang->addr);
39b4b06b 1220 if (set)
78fa3c5c 1221 pir |= mask;
86a74ff2 1222 else
78fa3c5c
SS		 1223 pir &= ~mask;
1224 iowrite32(pir, bitbang->addr);
39b4b06b
SS		 1225}
1226
1227/* Data I/O pin control */
1228static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1229{
1230 sh_mdio_ctrl(ctrl, PIR_MMD, bit);
86a74ff2
NI		 1231}
1232
1233/* Set bit data*/
1234static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
1235{
39b4b06b 1236 sh_mdio_ctrl(ctrl, PIR_MDO, bit);
86a74ff2
NI		 1237}
1238
1239/* Get bit data*/
1240static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
1241{
1242 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
b3017e6a
YS		 1243
1244 if (bitbang->set_gate)
1245 bitbang->set_gate(bitbang->addr);
1246
78fa3c5c 1247 return (ioread32(bitbang->addr) & PIR_MDI) != 0;
86a74ff2
NI		 1248}
1249
1250/* MDC pin control */
1251static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1252{
39b4b06b 1253 sh_mdio_ctrl(ctrl, PIR_MDC, bit);
86a74ff2
NI		 1254}
1255
1256/* mdio bus control struct */
1257static struct mdiobb_ops bb_ops = {
1258 .owner = THIS_MODULE,
1259 .set_mdc = sh_mdc_ctrl,
1260 .set_mdio_dir = sh_mmd_ctrl,
1261 .set_mdio_data = sh_set_mdio,
1262 .get_mdio_data = sh_get_mdio,
1263};
1264
1debdc8f
SS		 1265/* free Tx skb function */
1266static int sh_eth_tx_free(struct net_device *ndev, bool sent_only)
1267{
1268 struct sh_eth_private *mdp = netdev_priv(ndev);
1269 struct sh_eth_txdesc *txdesc;
1270 int free_num = 0;
1271 int entry;
1272 bool sent;
1273
1274 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
1275 entry = mdp->dirty_tx % mdp->num_tx_ring;
1276 txdesc = &mdp->tx_ring[entry];
1277 sent = !(txdesc->status & cpu_to_le32(TD_TACT));
1278 if (sent_only && !sent)
1279 break;
1280 /* TACT bit must be checked before all the following reads */
1281 dma_rmb();
1282 netif_info(mdp, tx_done, ndev,
1283 "tx entry %d status 0x%08x\n",
1284 entry, le32_to_cpu(txdesc->status));
1285 /* Free the original skb. */
1286 if (mdp->tx_skbuff[entry]) {
22c1aed4
TP		 1287 dma_unmap_single(&mdp->pdev->dev,
1288 le32_to_cpu(txdesc->addr),
1debdc8f
SS		 1289 le32_to_cpu(txdesc->len) >> 16,
1290 DMA_TO_DEVICE);
1291 dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1292 mdp->tx_skbuff[entry] = NULL;
1293 free_num++;
1294 }
1295 txdesc->status = cpu_to_le32(TD_TFP);
1296 if (entry >= mdp->num_tx_ring - 1)
1297 txdesc->status |= cpu_to_le32(TD_TDLE);
1298
1299 if (sent) {
1300 ndev->stats.tx_packets++;
1301 ndev->stats.tx_bytes += le32_to_cpu(txdesc->len) >> 16;
1302 }
1303 }
1304 return free_num;
1305}
1306
86a74ff2
NI		 1307/* free skb and descriptor buffer */
1308static void sh_eth_ring_free(struct net_device *ndev)
1309{
1310 struct sh_eth_private *mdp = netdev_priv(ndev);
8e03a5e7 1311 int ringsize, i;
86a74ff2 1312
1debdc8f
SS		 1313 if (mdp->rx_ring) {
1314 for (i = 0; i < mdp->num_rx_ring; i++) {
1315 if (mdp->rx_skbuff[i]) {
1316 struct sh_eth_rxdesc *rxdesc = &mdp->rx_ring[i];
1317
22c1aed4 1318 dma_unmap_single(&mdp->pdev->dev,
1debdc8f
SS		 1319 le32_to_cpu(rxdesc->addr),
1320 ALIGN(mdp->rx_buf_sz, 32),
1321 DMA_FROM_DEVICE);
1322 }
1323 }
1324 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
573500db 1325 dma_free_coherent(&mdp->pdev->dev, ringsize, mdp->rx_ring,
1debdc8f
SS		 1326 mdp->rx_desc_dma);
1327 mdp->rx_ring = NULL;
1328 }
1329
86a74ff2
NI		 1330 /* Free Rx skb ringbuffer */
1331 if (mdp->rx_skbuff) {
179d80af
SS		 1332 for (i = 0; i < mdp->num_rx_ring; i++)
1333 dev_kfree_skb(mdp->rx_skbuff[i]);
86a74ff2
NI		 1334 }
1335 kfree(mdp->rx_skbuff);
91c77550 1336 mdp->rx_skbuff = NULL;
86a74ff2 1337
8e03a5e7 1338 if (mdp->tx_ring) {
1debdc8f
SS		 1339 sh_eth_tx_free(ndev, false);
1340
8e03a5e7 1341 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
573500db 1342 dma_free_coherent(&mdp->pdev->dev, ringsize, mdp->tx_ring,
8e03a5e7
SS		 1343 mdp->tx_desc_dma);
1344 mdp->tx_ring = NULL;
1345 }
1debdc8f
SS		 1346
1347 /* Free Tx skb ringbuffer */
1348 kfree(mdp->tx_skbuff);
1349 mdp->tx_skbuff = NULL;
86a74ff2
NI		 1350}
1351
1352/* format skb and descriptor buffer */
1353static void sh_eth_ring_format(struct net_device *ndev)
1354{
1355 struct sh_eth_private *mdp = netdev_priv(ndev);
1356 int i;
1357 struct sk_buff *skb;
1358 struct sh_eth_rxdesc *rxdesc = NULL;
1359 struct sh_eth_txdesc *txdesc = NULL;
525b8075
YS		 1360 int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
1361 int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
cb368595 1362 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
52b9fa36 1363 dma_addr_t dma_addr;
5cbf20c7 1364 u32 buf_len;
86a74ff2 1365
128296fc
SS		 1366 mdp->cur_rx = 0;
1367 mdp->cur_tx = 0;
1368 mdp->dirty_rx = 0;
1369 mdp->dirty_tx = 0;
86a74ff2
NI		 1370
1371 memset(mdp->rx_ring, 0, rx_ringsize);
1372
1373 /* build Rx ring buffer */
525b8075 1374 for (i = 0; i < mdp->num_rx_ring; i++) {
86a74ff2
NI		 1375 /* skb */
1376 mdp->rx_skbuff[i] = NULL;
4d6a949c 1377 skb = netdev_alloc_skb(ndev, skbuff_size);
86a74ff2
NI		 1378 if (skb == NULL)
1379 break;
380af9e3
YS		 1380 sh_eth_set_receive_align(skb);
1381
ab857916 1382 /* The size of the buffer is a multiple of 32 bytes. */
5cbf20c7 1383 buf_len = ALIGN(mdp->rx_buf_sz, 32);
22c1aed4 1384 dma_addr = dma_map_single(&mdp->pdev->dev, skb->data, buf_len,
52b9fa36 1385 DMA_FROM_DEVICE);
22c1aed4 1386 if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) {
52b9fa36
BH		 1387 kfree_skb(skb);
1388 break;
1389 }
1390 mdp->rx_skbuff[i] = skb;
d0ba9134
SS		 1391
1392 /* RX descriptor */
1393 rxdesc = &mdp->rx_ring[i];
1394 rxdesc->len = cpu_to_le32(buf_len << 16);
7cf72477
SS		 1395 rxdesc->addr = cpu_to_le32(dma_addr);
1396 rxdesc->status = cpu_to_le32(RD_RACT | RD_RFP);
86a74ff2 1397
b0ca2a21
NI		 1398 /* Rx descriptor address set */
1399 if (i == 0) {
4a55530f 1400 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
246e30cc 1401 if (mdp->cd->xdfar_rw)
c5ed5368 1402 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
b0ca2a21 1403 }
86a74ff2
NI		 1404 }
1405
525b8075 1406 mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
86a74ff2
NI		 1407
1408 /* Mark the last entry as wrapping the ring. */
c1b7fca6
SS		 1409 if (rxdesc)
1410 rxdesc->status |= cpu_to_le32(RD_RDLE);
86a74ff2
NI		 1411
1412 memset(mdp->tx_ring, 0, tx_ringsize);
1413
1414 /* build Tx ring buffer */
525b8075 1415 for (i = 0; i < mdp->num_tx_ring; i++) {
86a74ff2
NI		 1416 mdp->tx_skbuff[i] = NULL;
1417 txdesc = &mdp->tx_ring[i];
7cf72477
SS		 1418 txdesc->status = cpu_to_le32(TD_TFP);
1419 txdesc->len = cpu_to_le32(0);
b0ca2a21 1420 if (i == 0) {
71557a37 1421 /* Tx descriptor address set */
4a55530f 1422 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
246e30cc 1423 if (mdp->cd->xdfar_rw)
c5ed5368 1424 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
b0ca2a21 1425 }
86a74ff2
NI		 1426 }
1427
7cf72477 1428 txdesc->status |= cpu_to_le32(TD_TDLE);
86a74ff2
NI		 1429}
1430
1431/* Get skb and descriptor buffer */
1432static int sh_eth_ring_init(struct net_device *ndev)
1433{
1434 struct sh_eth_private *mdp = netdev_priv(ndev);
91d80683 1435 int rx_ringsize, tx_ringsize;
86a74ff2 1436
128296fc 1437 /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
86a74ff2
NI		 1438 * card needs room to do 8 byte alignment, +2 so we can reserve
1439 * the first 2 bytes, and +16 gets room for the status word from the
1440 * card.
1441 */
1442 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
1443 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
503914cf
MD		 1444 if (mdp->cd->rpadir)
1445 mdp->rx_buf_sz += NET_IP_ALIGN;
86a74ff2
NI		 1446
1447 /* Allocate RX and TX skb rings */
2c94e856
SS		 1448 mdp->rx_skbuff = kcalloc(mdp->num_rx_ring, sizeof(*mdp->rx_skbuff),
1449 GFP_KERNEL);
91d80683
SS		 1450 if (!mdp->rx_skbuff)
1451 return -ENOMEM;
86a74ff2 1452
2c94e856
SS		 1453 mdp->tx_skbuff = kcalloc(mdp->num_tx_ring, sizeof(*mdp->tx_skbuff),
1454 GFP_KERNEL);
91d80683 1455 if (!mdp->tx_skbuff)
8e03a5e7 1456 goto ring_free;
86a74ff2
NI		 1457
1458 /* Allocate all Rx descriptors. */
525b8075 1459 rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
573500db
TP		 1460 mdp->rx_ring = dma_alloc_coherent(&mdp->pdev->dev, rx_ringsize,
1461 &mdp->rx_desc_dma, GFP_KERNEL);
91d80683 1462 if (!mdp->rx_ring)
8e03a5e7 1463 goto ring_free;
86a74ff2
NI		 1464
1465 mdp->dirty_rx = 0;
1466
1467 /* Allocate all Tx descriptors. */
525b8075 1468 tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
573500db
TP		 1469 mdp->tx_ring = dma_alloc_coherent(&mdp->pdev->dev, tx_ringsize,
1470 &mdp->tx_desc_dma, GFP_KERNEL);
91d80683 1471 if (!mdp->tx_ring)
8e03a5e7 1472 goto ring_free;
91d80683 1473 return 0;
86a74ff2 1474
8e03a5e7
SS		 1475ring_free:
1476 /* Free Rx and Tx skb ring buffer and DMA buffer */
86a74ff2
NI		 1477 sh_eth_ring_free(ndev);
1478
91d80683 1479 return -ENOMEM;
86a74ff2
NI		 1480}
1481
f7967210 1482static int sh_eth_dev_init(struct net_device *ndev)
86a74ff2 1483{
86a74ff2 1484 struct sh_eth_private *mdp = netdev_priv(ndev);
4fa8c3cc 1485 int ret;
86a74ff2
NI		 1486
1487 /* Soft Reset */
4ceedeb1 1488 ret = mdp->cd->soft_reset(ndev);
5cee1d37 1489 if (ret)
f738a13d 1490 return ret;
86a74ff2 1491
55754f19
SH		 1492 if (mdp->cd->rmiimode)
1493 sh_eth_write(ndev, 0x1, RMIIMODE);
1494
b0ca2a21
NI		 1495 /* Descriptor format */
1496 sh_eth_ring_format(ndev);
380af9e3 1497 if (mdp->cd->rpadir)
470103dc 1498 sh_eth_write(ndev, NET_IP_ALIGN << 16, RPADIR);
86a74ff2
NI		 1499
1500 /* all sh_eth int mask */
4a55530f 1501 sh_eth_write(ndev, 0, EESIPR);
86a74ff2 1502
10b9194f 1503#if defined(__LITTLE_ENDIAN)
380af9e3 1504 if (mdp->cd->hw_swap)
4a55530f 1505 sh_eth_write(ndev, EDMR_EL, EDMR);
380af9e3 1506 else
b0ca2a21 1507#endif
4a55530f 1508 sh_eth_write(ndev, 0, EDMR);
86a74ff2 1509
b0ca2a21 1510 /* FIFO size set */
4a55530f
YS		 1511 sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
1512 sh_eth_write(ndev, 0, TFTR);
86a74ff2 1513
530aa2d0
BD		 1514 /* Frame recv control (enable multiple-packets per rx irq) */
1515 sh_eth_write(ndev, RMCR_RNC, RMCR);
86a74ff2 1516
b284fbe3 1517 sh_eth_write(ndev, mdp->cd->trscer_err_mask, TRSCER);
86a74ff2 1518
93f0fa75
SS		 1519 /* DMA transfer burst mode */
1520 if (mdp->cd->nbst)
1521 sh_eth_modify(ndev, EDMR, EDMR_NBST, EDMR_NBST);
1522
6b14787a 1523 /* Burst cycle count upper-limit */
380af9e3 1524 if (mdp->cd->bculr)
6b14787a 1525 sh_eth_write(ndev, 0x800, BCULR);
b0ca2a21 1526
4a55530f 1527 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
86a74ff2 1528
380af9e3 1529 if (!mdp->cd->no_trimd)
4a55530f 1530 sh_eth_write(ndev, 0, TRIMD);
86a74ff2 1531
b0ca2a21 1532 /* Recv frame limit set register */
fdb37a7f
YS		 1533 sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1534 RFLR);
86a74ff2 1535
b2b14d2f 1536 sh_eth_modify(ndev, EESR, 0, 0);
f7967210
SS		 1537 mdp->irq_enabled = true;
1538 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
86a74ff2 1539
f8e022db 1540 /* EMAC Mode: PAUSE prohibition; Duplex; RX Checksum; TX; RX */
bffa731f 1541 sh_eth_write(ndev, ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) |
f8e022db 1542 (ndev->features & NETIF_F_RXCSUM ? ECMR_RCSC : 0) |
bffa731f 1543 ECMR_TE | ECMR_RE, ECMR);
b0ca2a21 1544
380af9e3
YS		 1545 if (mdp->cd->set_rate)
1546 mdp->cd->set_rate(ndev);
1547
b0ca2a21 1548 /* E-MAC Status Register clear */
4a55530f 1549 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
b0ca2a21
NI		 1550
1551 /* E-MAC Interrupt Enable register */
f7967210 1552 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
86a74ff2
NI		 1553
1554 /* Set MAC address */
1555 update_mac_address(ndev);
1556
1557 /* mask reset */
380af9e3 1558 if (mdp->cd->apr)
782e85c5 1559 sh_eth_write(ndev, 1, APR);
380af9e3 1560 if (mdp->cd->mpr)
782e85c5 1561 sh_eth_write(ndev, 1, MPR);
380af9e3 1562 if (mdp->cd->tpauser)
4a55530f 1563 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
b0ca2a21 1564
f7967210
SS		 1565 /* Setting the Rx mode will start the Rx process. */
1566 sh_eth_write(ndev, EDRRR_R, EDRRR);
86a74ff2
NI		 1567
1568 return ret;
1569}
1570
740c7f31
BH		 1571static void sh_eth_dev_exit(struct net_device *ndev)
1572{
1573 struct sh_eth_private *mdp = netdev_priv(ndev);
1574 int i;
1575
1576 /* Deactivate all TX descriptors, so DMA should stop at next
1577 * packet boundary if it's currently running
1578 */
1579 for (i = 0; i < mdp->num_tx_ring; i++)
7cf72477 1580 mdp->tx_ring[i].status &= ~cpu_to_le32(TD_TACT);
740c7f31
BH		 1581
1582 /* Disable TX FIFO egress to MAC */
1583 sh_eth_rcv_snd_disable(ndev);
1584
1585 /* Stop RX DMA at next packet boundary */
1586 sh_eth_write(ndev, 0, EDRRR);
1587
1588 /* Aside from TX DMA, we can't tell when the hardware is
1589 * really stopped, so we need to reset to make sure.
1590 * Before doing that, wait for long enough to *probably*
1591 * finish transmitting the last packet and poll stats.
1592 */
1593 msleep(2); /* max frame time at 10 Mbps < 1250 us */
1594 sh_eth_get_stats(ndev);
4ceedeb1 1595 mdp->cd->soft_reset(ndev);
a14c7d15 1596
315ca92d
YS		 1597 /* Set the RMII mode again if required */
1598 if (mdp->cd->rmiimode)
1599 sh_eth_write(ndev, 0x1, RMIIMODE);
1600
a14c7d15
GU		 1601 /* Set MAC address again */
1602 update_mac_address(ndev);
740c7f31
BH		 1603}
1604
f8e022db
SS		 1605static void sh_eth_rx_csum(struct sk_buff *skb)
1606{
1607 u8 *hw_csum;
1608
1609 /* The hardware checksum is 2 bytes appended to packet data */
1610 if (unlikely(skb->len < sizeof(__sum16)))
1611 return;
1612 hw_csum = skb_tail_pointer(skb) - sizeof(__sum16);
1613 skb->csum = csum_unfold((__force __sum16)get_unaligned_le16(hw_csum));
1614 skb->ip_summed = CHECKSUM_COMPLETE;
1615 skb_trim(skb, skb->len - sizeof(__sum16));
1616}
1617
86a74ff2 1618/* Packet receive function */
3719109d 1619static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
86a74ff2
NI		 1620{
1621 struct sh_eth_private *mdp = netdev_priv(ndev);
1622 struct sh_eth_rxdesc *rxdesc;
1623
525b8075
YS		 1624 int entry = mdp->cur_rx % mdp->num_rx_ring;
1625 int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
319cd520 1626 int limit;
86a74ff2 1627 struct sk_buff *skb;
380af9e3 1628 u32 desc_status;
cb368595 1629 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
52b9fa36 1630 dma_addr_t dma_addr;
4fa8c3cc 1631 u16 pkt_len;
5cbf20c7 1632 u32 buf_len;
86a74ff2 1633
319cd520
MK		 1634 boguscnt = min(boguscnt, *quota);
1635 limit = boguscnt;
86a74ff2 1636 rxdesc = &mdp->rx_ring[entry];
7cf72477 1637 while (!(rxdesc->status & cpu_to_le32(RD_RACT))) {
7d7355f5 1638 /* RACT bit must be checked before all the following reads */
f32bfb9a 1639 dma_rmb();
7cf72477
SS		 1640 desc_status = le32_to_cpu(rxdesc->status);
1641 pkt_len = le32_to_cpu(rxdesc->len) & RD_RFL;
86a74ff2
NI		 1642
1643 if (--boguscnt < 0)
1644 break;
1645
e5fd13f4
BH		 1646 netif_info(mdp, rx_status, ndev,
1647 "rx entry %d status 0x%08x len %d\n",
1648 entry, desc_status, pkt_len);
1649
86a74ff2 1650 if (!(desc_status & RDFEND))
bb7d92e3 1651 ndev->stats.rx_length_errors++;
86a74ff2 1652
128296fc 1653 /* In case of almost all GETHER/ETHERs, the Receive Frame State
dd019897 1654 * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
9b4a6364
BH		 1655 * bit 0. However, in case of the R8A7740 and R7S72100
1656 * the RFS bits are from bit 25 to bit 16. So, the
db893473 1657 * driver needs right shifting by 16.
dd019897 1658 */
2c2ab5af 1659 if (mdp->cd->csmr)
ac8025a6 1660 desc_status >>= 16;
dd019897 1661
248be83d 1662 skb = mdp->rx_skbuff[entry];
86a74ff2
NI		 1663 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1664 RD_RFS5 | RD_RFS6 | RD_RFS10)) {
bb7d92e3 1665 ndev->stats.rx_errors++;
86a74ff2 1666 if (desc_status & RD_RFS1)
bb7d92e3 1667 ndev->stats.rx_crc_errors++;
86a74ff2 1668 if (desc_status & RD_RFS2)
bb7d92e3 1669 ndev->stats.rx_frame_errors++;
86a74ff2 1670 if (desc_status & RD_RFS3)
bb7d92e3 1671 ndev->stats.rx_length_errors++;
86a74ff2 1672 if (desc_status & RD_RFS4)
bb7d92e3 1673 ndev->stats.rx_length_errors++;
86a74ff2 1674 if (desc_status & RD_RFS6)
bb7d92e3 1675 ndev->stats.rx_missed_errors++;
86a74ff2 1676 if (desc_status & RD_RFS10)
bb7d92e3 1677 ndev->stats.rx_over_errors++;
248be83d 1678 } else if (skb) {
7cf72477 1679 dma_addr = le32_to_cpu(rxdesc->addr);
380af9e3
YS		 1680 if (!mdp->cd->hw_swap)
1681 sh_eth_soft_swap(
1299653a 1682 phys_to_virt(ALIGN(dma_addr, 4)),
380af9e3 1683 pkt_len + 2);
86a74ff2 1684 mdp->rx_skbuff[entry] = NULL;
503914cf
MD		 1685 if (mdp->cd->rpadir)
1686 skb_reserve(skb, NET_IP_ALIGN);
22c1aed4 1687 dma_unmap_single(&mdp->pdev->dev, dma_addr,
ab857916 1688 ALIGN(mdp->rx_buf_sz, 32),
52b9fa36 1689 DMA_FROM_DEVICE);
86a74ff2
NI		 1690 skb_put(skb, pkt_len);
1691 skb->protocol = eth_type_trans(skb, ndev);
f8e022db
SS		 1692 if (ndev->features & NETIF_F_RXCSUM)
1693 sh_eth_rx_csum(skb);
a8e9fd0f 1694 netif_receive_skb(skb);
bb7d92e3
ED		 1695 ndev->stats.rx_packets++;
1696 ndev->stats.rx_bytes += pkt_len;
25b77ad7
BH		 1697 if (desc_status & RD_RFS8)
1698 ndev->stats.multicast++;
86a74ff2 1699 }
525b8075 1700 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
862df497 1701 rxdesc = &mdp->rx_ring[entry];
86a74ff2
NI		 1702 }
1703
1704 /* Refill the Rx ring buffers. */
1705 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
525b8075 1706 entry = mdp->dirty_rx % mdp->num_rx_ring;
86a74ff2 1707 rxdesc = &mdp->rx_ring[entry];
ab857916 1708 /* The size of the buffer is 32 byte boundary. */
5cbf20c7 1709 buf_len = ALIGN(mdp->rx_buf_sz, 32);
7cf72477 1710 rxdesc->len = cpu_to_le32(buf_len << 16);
b0ca2a21 1711
86a74ff2 1712 if (mdp->rx_skbuff[entry] == NULL) {
4d6a949c 1713 skb = netdev_alloc_skb(ndev, skbuff_size);
86a74ff2
NI		 1714 if (skb == NULL)
1715 break; /* Better luck next round. */
380af9e3 1716 sh_eth_set_receive_align(skb);
22c1aed4 1717 dma_addr = dma_map_single(&mdp->pdev->dev, skb->data,
5cbf20c7 1718 buf_len, DMA_FROM_DEVICE);
22c1aed4 1719 if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) {
52b9fa36
BH		 1720 kfree_skb(skb);
1721 break;
1722 }
1723 mdp->rx_skbuff[entry] = skb;
380af9e3 1724
bc8acf2c 1725 skb_checksum_none_assert(skb);
7cf72477 1726 rxdesc->addr = cpu_to_le32(dma_addr);
86a74ff2 1727 }
f32bfb9a 1728 dma_wmb(); /* RACT bit must be set after all the above writes */
525b8075 1729 if (entry >= mdp->num_rx_ring - 1)
86a74ff2 1730 rxdesc->status |=
7cf72477 1731 cpu_to_le32(RD_RACT | RD_RFP | RD_RDLE);
86a74ff2 1732 else
7cf72477 1733 rxdesc->status |= cpu_to_le32(RD_RACT | RD_RFP);
86a74ff2
NI		 1734 }
1735
1736 /* Restart Rx engine if stopped. */
1737 /* If we don't need to check status, don't. -KDU */
79fba9f5 1738 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
a18e08bd 1739 /* fix the values for the next receiving if RDE is set */
6e80e55b 1740 if (intr_status & EESR_RDE && !mdp->cd->no_xdfar) {
128296fc
SS		 1741 u32 count = (sh_eth_read(ndev, RDFAR) -
1742 sh_eth_read(ndev, RDLAR)) >> 4;
1743
1744 mdp->cur_rx = count;
1745 mdp->dirty_rx = count;
1746 }
4a55530f 1747 sh_eth_write(ndev, EDRRR_R, EDRRR);
79fba9f5 1748 }
86a74ff2 1749
319cd520
MK		 1750 *quota -= limit - boguscnt - 1;
1751
4f809cea 1752 return *quota <= 0;
86a74ff2
NI		 1753}
1754
4a55530f 1755static void sh_eth_rcv_snd_disable(struct net_device *ndev)
dc19e4e5
NI		 1756{
1757 /* disable tx and rx */
b2b14d2f 1758 sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0);
dc19e4e5
NI		 1759}
1760
4a55530f 1761static void sh_eth_rcv_snd_enable(struct net_device *ndev)
dc19e4e5
NI		 1762{
1763 /* enable tx and rx */
b2b14d2f 1764 sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE);
dc19e4e5
NI		 1765}
1766
9b39f05c
SS		 1767/* E-MAC interrupt handler */
1768static void sh_eth_emac_interrupt(struct net_device *ndev)
86a74ff2
NI		 1769{
1770 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2 1771 u32 felic_stat;
380af9e3 1772 u32 link_stat;
86a74ff2 1773
9b39f05c
SS		 1774 felic_stat = sh_eth_read(ndev, ECSR) & sh_eth_read(ndev, ECSIPR);
1775 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */
1776 if (felic_stat & ECSR_ICD)
1777 ndev->stats.tx_carrier_errors++;
0cf45a3b
NS		 1778 if (felic_stat & ECSR_MPD)
1779 pm_wakeup_event(&mdp->pdev->dev, 0);
9b39f05c
SS		 1780 if (felic_stat & ECSR_LCHNG) {
1781 /* Link Changed */
1782 if (mdp->cd->no_psr || mdp->no_ether_link)
1783 return;
1784 link_stat = sh_eth_read(ndev, PSR);
1785 if (mdp->ether_link_active_low)
1786 link_stat = ~link_stat;
1787 if (!(link_stat & PHY_ST_LINK)) {
1788 sh_eth_rcv_snd_disable(ndev);
1789 } else {
1790 /* Link Up */
1a0bee6c 1791 sh_eth_modify(ndev, EESIPR, EESIPR_ECIIP, 0);
9b39f05c
SS		 1792 /* clear int */
1793 sh_eth_modify(ndev, ECSR, 0, 0);
1a0bee6c 1794 sh_eth_modify(ndev, EESIPR, EESIPR_ECIIP, EESIPR_ECIIP);
9b39f05c
SS		 1795 /* enable tx and rx */
1796 sh_eth_rcv_snd_enable(ndev);
86a74ff2
NI		 1797 }
1798 }
9b39f05c
SS		 1799}
1800
1801/* error control function */
1802static void sh_eth_error(struct net_device *ndev, u32 intr_status)
1803{
1804 struct sh_eth_private *mdp = netdev_priv(ndev);
1805 u32 mask;
86a74ff2
NI		 1806
1807 if (intr_status & EESR_TWB) {
4eb313a7
SS		 1808 /* Unused write back interrupt */
1809 if (intr_status & EESR_TABT) { /* Transmit Abort int */
bb7d92e3 1810 ndev->stats.tx_aborted_errors++;
8d5009f6 1811 netif_err(mdp, tx_err, ndev, "Transmit Abort\n");
4eb313a7 1812 }
86a74ff2
NI		 1813 }
1814
1815 if (intr_status & EESR_RABT) {
1816 /* Receive Abort int */
1817 if (intr_status & EESR_RFRMER) {
1818 /* Receive Frame Overflow int */
bb7d92e3 1819 ndev->stats.rx_frame_errors++;
86a74ff2
NI		 1820 }
1821 }
380af9e3 1822
dc19e4e5
NI		 1823 if (intr_status & EESR_TDE) {
1824 /* Transmit Descriptor Empty int */
bb7d92e3 1825 ndev->stats.tx_fifo_errors++;
8d5009f6 1826 netif_err(mdp, tx_err, ndev, "Transmit Descriptor Empty\n");
dc19e4e5
NI		 1827 }
1828
1829 if (intr_status & EESR_TFE) {
1830 /* FIFO under flow */
bb7d92e3 1831 ndev->stats.tx_fifo_errors++;
8d5009f6 1832 netif_err(mdp, tx_err, ndev, "Transmit FIFO Under flow\n");
86a74ff2
NI		 1833 }
1834
1835 if (intr_status & EESR_RDE) {
1836 /* Receive Descriptor Empty int */
bb7d92e3 1837 ndev->stats.rx_over_errors++;
86a74ff2 1838 }
dc19e4e5 1839
86a74ff2
NI		 1840 if (intr_status & EESR_RFE) {
1841 /* Receive FIFO Overflow int */
bb7d92e3 1842 ndev->stats.rx_fifo_errors++;
dc19e4e5
NI		 1843 }
1844
1845 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1846 /* Address Error */
bb7d92e3 1847 ndev->stats.tx_fifo_errors++;
8d5009f6 1848 netif_err(mdp, tx_err, ndev, "Address Error\n");
86a74ff2 1849 }
380af9e3
YS		 1850
1851 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1852 if (mdp->cd->no_ade)
1853 mask &= ~EESR_ADE;
1854 if (intr_status & mask) {
86a74ff2 1855 /* Tx error */
4a55530f 1856 u32 edtrr = sh_eth_read(ndev, EDTRR);
090d560f 1857
86a74ff2 1858 /* dmesg */
da246855
SS		 1859 netdev_err(ndev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1860 intr_status, mdp->cur_tx, mdp->dirty_tx,
1861 (u32)ndev->state, edtrr);
86a74ff2 1862 /* dirty buffer free */
1debdc8f 1863 sh_eth_tx_free(ndev, true);
86a74ff2
NI		 1864
1865 /* SH7712 BUG */
3e416992 1866 if (edtrr ^ mdp->cd->edtrr_trns) {
86a74ff2 1867 /* tx dma start */
3e416992 1868 sh_eth_write(ndev, mdp->cd->edtrr_trns, EDTRR);
86a74ff2
NI		 1869 }
1870 /* wakeup */
1871 netif_wake_queue(ndev);
1872 }
1873}
1874
1875static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1876{
1877 struct net_device *ndev = netdev;
1878 struct sh_eth_private *mdp = netdev_priv(ndev);
380af9e3 1879 struct sh_eth_cpu_data *cd = mdp->cd;
0e0fde3c 1880 irqreturn_t ret = IRQ_NONE;
0799c2d6 1881 u32 intr_status, intr_enable;
86a74ff2 1882
86a74ff2
NI		 1883 spin_lock(&mdp->lock);
1884
3893b273 1885 /* Get interrupt status */
4a55530f 1886 intr_status = sh_eth_read(ndev, EESR);
9b39f05c
SS		 1887 /* Mask it with the interrupt mask, forcing ECI interrupt to be always
1888 * enabled since it's the one that comes thru regardless of the mask,
1889 * and we need to fully handle it in sh_eth_emac_interrupt() in order
1890 * to quench it as it doesn't get cleared by just writing 1 to the ECI
1891 * bit...
3893b273 1892 */
3719109d 1893 intr_enable = sh_eth_read(ndev, EESIPR);
1a0bee6c 1894 intr_status &= intr_enable | EESIPR_ECIIP;
9b39f05c
SS		 1895 if (intr_status & (EESR_RX_CHECK | cd->tx_check | EESR_ECI |
1896 cd->eesr_err_check))
0e0fde3c 1897 ret = IRQ_HANDLED;
3719109d 1898 else
283e38db
BH		 1899 goto out;
1900
2344ef3c 1901 if (unlikely(!mdp->irq_enabled)) {
283e38db
BH		 1902 sh_eth_write(ndev, 0, EESIPR);
1903 goto out;
1904 }
86a74ff2 1905
3719109d
SS		 1906 if (intr_status & EESR_RX_CHECK) {
1907 if (napi_schedule_prep(&mdp->napi)) {
1908 /* Mask Rx interrupts */
1909 sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK,
1910 EESIPR);
1911 __napi_schedule(&mdp->napi);
1912 } else {
da246855 1913 netdev_warn(ndev,
0799c2d6 1914 "ignoring interrupt, status 0x%08x, mask 0x%08x.\n",
da246855 1915 intr_status, intr_enable);
3719109d
SS		 1916 }
1917 }
86a74ff2 1918
b0ca2a21 1919 /* Tx Check */
380af9e3 1920 if (intr_status & cd->tx_check) {
3719109d
SS		 1921 /* Clear Tx interrupts */
1922 sh_eth_write(ndev, intr_status & cd->tx_check, EESR);
1923
1debdc8f 1924 sh_eth_tx_free(ndev, true);
86a74ff2
NI		 1925 netif_wake_queue(ndev);
1926 }
1927
9b39f05c
SS		 1928 /* E-MAC interrupt */
1929 if (intr_status & EESR_ECI)
1930 sh_eth_emac_interrupt(ndev);
1931
3719109d
SS		 1932 if (intr_status & cd->eesr_err_check) {
1933 /* Clear error interrupts */
1934 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR);
1935
86a74ff2 1936 sh_eth_error(ndev, intr_status);
3719109d 1937 }
86a74ff2 1938
283e38db 1939out:
86a74ff2
NI		 1940 spin_unlock(&mdp->lock);
1941
0e0fde3c 1942 return ret;
86a74ff2
NI		 1943}
1944
3719109d
SS		 1945static int sh_eth_poll(struct napi_struct *napi, int budget)
1946{
1947 struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private,
1948 napi);
1949 struct net_device *ndev = napi->dev;
1950 int quota = budget;
0799c2d6 1951 u32 intr_status;
3719109d
SS		 1952
1953 for (;;) {
1954 intr_status = sh_eth_read(ndev, EESR);
1955 if (!(intr_status & EESR_RX_CHECK))
1956 break;
1957 /* Clear Rx interrupts */
1958 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR);
1959
1960 if (sh_eth_rx(ndev, intr_status, &quota))
1961 goto out;
1962 }
1963
1964 napi_complete(napi);
1965
1966 /* Reenable Rx interrupts */
283e38db
BH		 1967 if (mdp->irq_enabled)
1968 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
3719109d
SS		 1969out:
1970 return budget - quota;
1971}
1972
86a74ff2
NI		 1973/* PHY state control function */
1974static void sh_eth_adjust_link(struct net_device *ndev)
1975{
1976 struct sh_eth_private *mdp = netdev_priv(ndev);
9fd0375a 1977 struct phy_device *phydev = ndev->phydev;
5cb3f52a 1978 unsigned long flags;
86a74ff2
NI		 1979 int new_state = 0;
1980
5cb3f52a
VZ		 1981 spin_lock_irqsave(&mdp->lock, flags);
1982
1983 /* Disable TX and RX right over here, if E-MAC change is ignored */
1984 if (mdp->cd->no_psr || mdp->no_ether_link)
1985 sh_eth_rcv_snd_disable(ndev);
1986
3340d2aa 1987 if (phydev->link) {
86a74ff2
NI		 1988 if (phydev->duplex != mdp->duplex) {
1989 new_state = 1;
1990 mdp->duplex = phydev->duplex;
380af9e3
YS		 1991 if (mdp->cd->set_duplex)
1992 mdp->cd->set_duplex(ndev);
86a74ff2
NI		 1993 }
1994
1995 if (phydev->speed != mdp->speed) {
1996 new_state = 1;
1997 mdp->speed = phydev->speed;
380af9e3
YS		 1998 if (mdp->cd->set_rate)
1999 mdp->cd->set_rate(ndev);
86a74ff2 2000 }
3340d2aa 2001 if (!mdp->link) {
b2b14d2f 2002 sh_eth_modify(ndev, ECMR, ECMR_TXF, 0);
86a74ff2
NI		 2003 new_state = 1;
2004 mdp->link = phydev->link;
86a74ff2
NI		 2005 }
2006 } else if (mdp->link) {
2007 new_state = 1;
3340d2aa 2008 mdp->link = 0;
86a74ff2
NI		 2009 mdp->speed = 0;
2010 mdp->duplex = -1;
86a74ff2
NI		 2011 }
2012
5cb3f52a
VZ		 2013 /* Enable TX and RX right over here, if E-MAC change is ignored */
2014 if ((mdp->cd->no_psr || mdp->no_ether_link) && phydev->link)
2015 sh_eth_rcv_snd_enable(ndev);
2016
5cb3f52a
VZ		 2017 spin_unlock_irqrestore(&mdp->lock, flags);
2018
dc19e4e5 2019 if (new_state && netif_msg_link(mdp))
86a74ff2
NI		 2020 phy_print_status(phydev);
2021}
2022
2023/* PHY init function */
2024static int sh_eth_phy_init(struct net_device *ndev)
2025{
702eca02 2026 struct device_node *np = ndev->dev.parent->of_node;
86a74ff2 2027 struct sh_eth_private *mdp = netdev_priv(ndev);
4fa8c3cc 2028 struct phy_device *phydev;
86a74ff2 2029
3340d2aa 2030 mdp->link = 0;
86a74ff2
NI		 2031 mdp->speed = 0;
2032 mdp->duplex = -1;
2033
2034 /* Try connect to PHY */
702eca02
BD		 2035 if (np) {
2036 struct device_node *pn;
2037
2038 pn = of_parse_phandle(np, "phy-handle", 0);
2039 phydev = of_phy_connect(ndev, pn,
2040 sh_eth_adjust_link, 0,
2041 mdp->phy_interface);
2042
8da703dc 2043 of_node_put(pn);
702eca02
BD		 2044 if (!phydev)
2045 phydev = ERR_PTR(-ENOENT);
2046 } else {
2047 char phy_id[MII_BUS_ID_SIZE + 3];
2048
2049 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
2050 mdp->mii_bus->id, mdp->phy_id);
2051
2052 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
2053 mdp->phy_interface);
2054 }
2055
86a74ff2 2056 if (IS_ERR(phydev)) {
da246855 2057 netdev_err(ndev, "failed to connect PHY\n");
86a74ff2
NI		 2058 return PTR_ERR(phydev);
2059 }
380af9e3 2060
2aab6b40
TP		 2061 /* mask with MAC supported features */
2062 if (mdp->cd->register_type != SH_ETH_REG_GIGABIT) {
2063 int err = phy_set_max_speed(phydev, SPEED_100);
2064 if (err) {
2065 netdev_err(ndev, "failed to limit PHY to 100 Mbit/s\n");
2066 phy_disconnect(phydev);
2067 return err;
2068 }
2069 }
2070
2220943a 2071 phy_attached_info(phydev);
86a74ff2 2072
86a74ff2
NI		 2073 return 0;
2074}
2075
2076/* PHY control start function */
2077static int sh_eth_phy_start(struct net_device *ndev)
2078{
86a74ff2
NI		 2079 int ret;
2080
2081 ret = sh_eth_phy_init(ndev);
2082 if (ret)
2083 return ret;
2084
9fd0375a 2085 phy_start(ndev->phydev);
86a74ff2
NI		 2086
2087 return 0;
2088}
2089
6b4b4fea
BH		 2090/* If it is ever necessary to increase SH_ETH_REG_DUMP_MAX_REGS, the
2091 * version must be bumped as well. Just adding registers up to that
2092 * limit is fine, as long as the existing register indices don't
2093 * change.
2094 */
2095#define SH_ETH_REG_DUMP_VERSION 1
2096#define SH_ETH_REG_DUMP_MAX_REGS 256
2097
2098static size_t __sh_eth_get_regs(struct net_device *ndev, u32 *buf)
2099{
2100 struct sh_eth_private *mdp = netdev_priv(ndev);
2101 struct sh_eth_cpu_data *cd = mdp->cd;
2102 u32 *valid_map;
2103 size_t len;
2104
2105 BUILD_BUG_ON(SH_ETH_MAX_REGISTER_OFFSET > SH_ETH_REG_DUMP_MAX_REGS);
2106
2107 /* Dump starts with a bitmap that tells ethtool which
2108 * registers are defined for this chip.
2109 */
2110 len = DIV_ROUND_UP(SH_ETH_REG_DUMP_MAX_REGS, 32);
2111 if (buf) {
2112 valid_map = buf;
2113 buf += len;
2114 } else {
2115 valid_map = NULL;
2116 }
2117
2118 /* Add a register to the dump, if it has a defined offset.
2119 * This automatically skips most undefined registers, but for
2120 * some it is also necessary to check a capability flag in
2121 * struct sh_eth_cpu_data.
2122 */
2123#define mark_reg_valid(reg) valid_map[reg / 32] |= 1U << (reg % 32)
2124#define add_reg_from(reg, read_expr) do { \
2125 if (mdp->reg_offset[reg] != SH_ETH_OFFSET_INVALID) { \
2126 if (buf) { \
2127 mark_reg_valid(reg); \
2128 *buf++ = read_expr; \
2129 } \
2130 ++len; \
2131 } \
2132 } while (0)
2133#define add_reg(reg) add_reg_from(reg, sh_eth_read(ndev, reg))
2134#define add_tsu_reg(reg) add_reg_from(reg, sh_eth_tsu_read(mdp, reg))
2135
2136 add_reg(EDSR);
2137 add_reg(EDMR);
2138 add_reg(EDTRR);
2139 add_reg(EDRRR);
2140 add_reg(EESR);
2141 add_reg(EESIPR);
2142 add_reg(TDLAR);
2143 add_reg(TDFAR);
2144 add_reg(TDFXR);
2145 add_reg(TDFFR);
2146 add_reg(RDLAR);
2147 add_reg(RDFAR);
2148 add_reg(RDFXR);
2149 add_reg(RDFFR);
2150 add_reg(TRSCER);
2151 add_reg(RMFCR);
2152 add_reg(TFTR);
2153 add_reg(FDR);
2154 add_reg(RMCR);
2155 add_reg(TFUCR);
2156 add_reg(RFOCR);
2157 if (cd->rmiimode)
2158 add_reg(RMIIMODE);
2159 add_reg(FCFTR);
2160 if (cd->rpadir)
2161 add_reg(RPADIR);
2162 if (!cd->no_trimd)
2163 add_reg(TRIMD);
2164 add_reg(ECMR);
2165 add_reg(ECSR);
2166 add_reg(ECSIPR);
2167 add_reg(PIR);
2168 if (!cd->no_psr)
2169 add_reg(PSR);
2170 add_reg(RDMLR);
2171 add_reg(RFLR);
2172 add_reg(IPGR);
2173 if (cd->apr)
2174 add_reg(APR);
2175 if (cd->mpr)
2176 add_reg(MPR);
2177 add_reg(RFCR);
2178 add_reg(RFCF);
2179 if (cd->tpauser)
2180 add_reg(TPAUSER);
2181 add_reg(TPAUSECR);
2182 add_reg(GECMR);
2183 if (cd->bculr)
2184 add_reg(BCULR);
2185 add_reg(MAHR);
2186 add_reg(MALR);
2187 add_reg(TROCR);
2188 add_reg(CDCR);
2189 add_reg(LCCR);
2190 add_reg(CNDCR);
2191 add_reg(CEFCR);
2192 add_reg(FRECR);
2193 add_reg(TSFRCR);
2194 add_reg(TLFRCR);
2195 add_reg(CERCR);
2196 add_reg(CEECR);
2197 add_reg(MAFCR);
2198 if (cd->rtrate)
2199 add_reg(RTRATE);
2c2ab5af 2200 if (cd->csmr)
6b4b4fea
BH		 2201 add_reg(CSMR);
2202 if (cd->select_mii)
2203 add_reg(RMII_MII);
6b4b4fea 2204 if (cd->tsu) {
17d0fb0c 2205 add_tsu_reg(ARSTR);
6b4b4fea
BH		 2206 add_tsu_reg(TSU_CTRST);
2207 add_tsu_reg(TSU_FWEN0);
2208 add_tsu_reg(TSU_FWEN1);
2209 add_tsu_reg(TSU_FCM);
2210 add_tsu_reg(TSU_BSYSL0);
2211 add_tsu_reg(TSU_BSYSL1);
2212 add_tsu_reg(TSU_PRISL0);
2213 add_tsu_reg(TSU_PRISL1);
2214 add_tsu_reg(TSU_FWSL0);
2215 add_tsu_reg(TSU_FWSL1);
2216 add_tsu_reg(TSU_FWSLC);
6b4b4fea
BH		 2217 add_tsu_reg(TSU_QTAGM0);
2218 add_tsu_reg(TSU_QTAGM1);
2219 add_tsu_reg(TSU_FWSR);
2220 add_tsu_reg(TSU_FWINMK);
2221 add_tsu_reg(TSU_ADQT0);
2222 add_tsu_reg(TSU_ADQT1);
2223 add_tsu_reg(TSU_VTAG0);
2224 add_tsu_reg(TSU_VTAG1);
2225 add_tsu_reg(TSU_ADSBSY);
2226 add_tsu_reg(TSU_TEN);
2227 add_tsu_reg(TSU_POST1);
2228 add_tsu_reg(TSU_POST2);
2229 add_tsu_reg(TSU_POST3);
2230 add_tsu_reg(TSU_POST4);
e14549a5
SS		 2231 /* This is the start of a table, not just a single register. */
2232 if (buf) {
2233 unsigned int i;
2234
2235 mark_reg_valid(TSU_ADRH0);
2236 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES * 2; i++)
2237 *buf++ = ioread32(mdp->tsu_addr +
2238 mdp->reg_offset[TSU_ADRH0] +
2239 i * 4);
6b4b4fea 2240 }
e14549a5 2241 len += SH_ETH_TSU_CAM_ENTRIES * 2;
6b4b4fea
BH		 2242 }
2243
2244#undef mark_reg_valid
2245#undef add_reg_from
2246#undef add_reg
2247#undef add_tsu_reg
2248
2249 return len * 4;
2250}
2251
2252static int sh_eth_get_regs_len(struct net_device *ndev)
2253{
2254 return __sh_eth_get_regs(ndev, NULL);
2255}
2256
2257static void sh_eth_get_regs(struct net_device *ndev, struct ethtool_regs *regs,
2258 void *buf)
2259{
2260 struct sh_eth_private *mdp = netdev_priv(ndev);
2261
2262 regs->version = SH_ETH_REG_DUMP_VERSION;
2263
2264 pm_runtime_get_sync(&mdp->pdev->dev);
2265 __sh_eth_get_regs(ndev, buf);
2266 pm_runtime_put_sync(&mdp->pdev->dev);
2267}
2268
dc19e4e5
NI		 2269static u32 sh_eth_get_msglevel(struct net_device *ndev)
2270{
2271 struct sh_eth_private *mdp = netdev_priv(ndev);
2272 return mdp->msg_enable;
2273}
2274
2275static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
2276{
2277 struct sh_eth_private *mdp = netdev_priv(ndev);
2278 mdp->msg_enable = value;
2279}
2280
2281static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
2282 "rx_current", "tx_current",
2283 "rx_dirty", "tx_dirty",
2284};
2285#define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats)
2286
2287static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
2288{
2289 switch (sset) {
2290 case ETH_SS_STATS:
2291 return SH_ETH_STATS_LEN;
2292 default:
2293 return -EOPNOTSUPP;
2294 }
2295}
2296
2297static void sh_eth_get_ethtool_stats(struct net_device *ndev,
128296fc 2298 struct ethtool_stats *stats, u64 *data)
dc19e4e5
NI		 2299{
2300 struct sh_eth_private *mdp = netdev_priv(ndev);
2301 int i = 0;
2302
2303 /* device-specific stats */
2304 data[i++] = mdp->cur_rx;
2305 data[i++] = mdp->cur_tx;
2306 data[i++] = mdp->dirty_rx;
2307 data[i++] = mdp->dirty_tx;
2308}
2309
2310static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
2311{
2312 switch (stringset) {
2313 case ETH_SS_STATS:
2314 memcpy(data, *sh_eth_gstrings_stats,
128296fc 2315 sizeof(sh_eth_gstrings_stats));
dc19e4e5
NI		 2316 break;
2317 }
2318}
2319
525b8075
YS		 2320static void sh_eth_get_ringparam(struct net_device *ndev,
2321 struct ethtool_ringparam *ring)
2322{
2323 struct sh_eth_private *mdp = netdev_priv(ndev);
2324
2325 ring->rx_max_pending = RX_RING_MAX;
2326 ring->tx_max_pending = TX_RING_MAX;
2327 ring->rx_pending = mdp->num_rx_ring;
2328 ring->tx_pending = mdp->num_tx_ring;
2329}
2330
2331static int sh_eth_set_ringparam(struct net_device *ndev,
2332 struct ethtool_ringparam *ring)
2333{
2334 struct sh_eth_private *mdp = netdev_priv(ndev);
2335 int ret;
2336
2337 if (ring->tx_pending > TX_RING_MAX ||
2338 ring->rx_pending > RX_RING_MAX ||
2339 ring->tx_pending < TX_RING_MIN ||
2340 ring->rx_pending < RX_RING_MIN)
2341 return -EINVAL;
2342 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
2343 return -EINVAL;
2344
2345 if (netif_running(ndev)) {
bd888916 2346 netif_device_detach(ndev);
525b8075 2347 netif_tx_disable(ndev);
283e38db
BH		 2348
2349 /* Serialise with the interrupt handler and NAPI, then
2350 * disable interrupts. We have to clear the
2351 * irq_enabled flag first to ensure that interrupts
2352 * won't be re-enabled.
2353 */
2354 mdp->irq_enabled = false;
525b8075 2355 synchronize_irq(ndev->irq);
283e38db 2356 napi_synchronize(&mdp->napi);
525b8075 2357 sh_eth_write(ndev, 0x0000, EESIPR);
525b8075 2358
740c7f31 2359 sh_eth_dev_exit(ndev);
525b8075 2360
8e03a5e7 2361 /* Free all the skbuffs in the Rx queue and the DMA buffers. */
084236d8 2362 sh_eth_ring_free(ndev);
084236d8 2363 }
525b8075
YS		 2364
2365 /* Set new parameters */
2366 mdp->num_rx_ring = ring->rx_pending;
2367 mdp->num_tx_ring = ring->tx_pending;
2368
525b8075 2369 if (netif_running(ndev)) {
084236d8
BH		 2370 ret = sh_eth_ring_init(ndev);
2371 if (ret < 0) {
2372 netdev_err(ndev, "%s: sh_eth_ring_init failed.\n",
2373 __func__);
2374 return ret;
2375 }
f7967210 2376 ret = sh_eth_dev_init(ndev);
084236d8
BH		 2377 if (ret < 0) {
2378 netdev_err(ndev, "%s: sh_eth_dev_init failed.\n",
2379 __func__);
2380 return ret;
2381 }
2382
bd888916 2383 netif_device_attach(ndev);
525b8075
YS		 2384 }
2385
2386 return 0;
2387}
2388
d8981d02
NS		 2389static void sh_eth_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2390{
2391 struct sh_eth_private *mdp = netdev_priv(ndev);
2392
2393 wol->supported = 0;
2394 wol->wolopts = 0;
2395
b4580c95 2396 if (mdp->cd->magic) {
d8981d02
NS		 2397 wol->supported = WAKE_MAGIC;
2398 wol->wolopts = mdp->wol_enabled ? WAKE_MAGIC : 0;
2399 }
2400}
2401
2402static int sh_eth_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2403{
2404 struct sh_eth_private *mdp = netdev_priv(ndev);
2405
b4580c95 2406 if (!mdp->cd->magic || wol->wolopts & ~WAKE_MAGIC)
d8981d02
NS		 2407 return -EOPNOTSUPP;
2408
2409 mdp->wol_enabled = !!(wol->wolopts & WAKE_MAGIC);
2410
2411 device_set_wakeup_enable(&mdp->pdev->dev, mdp->wol_enabled);
2412
2413 return 0;
2414}
2415
9b07be4b 2416static const struct ethtool_ops sh_eth_ethtool_ops = {
6b4b4fea
BH		 2417 .get_regs_len = sh_eth_get_regs_len,
2418 .get_regs = sh_eth_get_regs,
4c10628a 2419 .nway_reset = phy_ethtool_nway_reset,
dc19e4e5
NI		 2420 .get_msglevel = sh_eth_get_msglevel,
2421 .set_msglevel = sh_eth_set_msglevel,
9b07be4b 2422 .get_link = ethtool_op_get_link,
dc19e4e5
NI		 2423 .get_strings = sh_eth_get_strings,
2424 .get_ethtool_stats = sh_eth_get_ethtool_stats,
2425 .get_sset_count = sh_eth_get_sset_count,
525b8075
YS		 2426 .get_ringparam = sh_eth_get_ringparam,
2427 .set_ringparam = sh_eth_set_ringparam,
45abbd43 2428 .get_link_ksettings = phy_ethtool_get_link_ksettings,
6783f50e 2429 .set_link_ksettings = phy_ethtool_set_link_ksettings,
d8981d02
NS		 2430 .get_wol = sh_eth_get_wol,
2431 .set_wol = sh_eth_set_wol,
dc19e4e5
NI		 2432};
2433
86a74ff2
NI		 2434/* network device open function */
2435static int sh_eth_open(struct net_device *ndev)
2436{
86a74ff2 2437 struct sh_eth_private *mdp = netdev_priv(ndev);
4fa8c3cc 2438 int ret;
86a74ff2 2439
bcd5149d
MD		 2440 pm_runtime_get_sync(&mdp->pdev->dev);
2441
d2779e99
SS		 2442 napi_enable(&mdp->napi);
2443
a0607fd3 2444 ret = request_irq(ndev->irq, sh_eth_interrupt,
5b3dfd13 2445 mdp->cd->irq_flags, ndev->name, ndev);
86a74ff2 2446 if (ret) {
da246855 2447 netdev_err(ndev, "Can not assign IRQ number\n");
d2779e99 2448 goto out_napi_off;
86a74ff2
NI		 2449 }
2450
2451 /* Descriptor set */
2452 ret = sh_eth_ring_init(ndev);
2453 if (ret)
2454 goto out_free_irq;
2455
2456 /* device init */
f7967210 2457 ret = sh_eth_dev_init(ndev);
86a74ff2
NI		 2458 if (ret)
2459 goto out_free_irq;
2460
2461 /* PHY control start*/
2462 ret = sh_eth_phy_start(ndev);
2463 if (ret)
2464 goto out_free_irq;
2465
ad846aa5
SS		 2466 netif_start_queue(ndev);
2467
7fa2955f
MK		 2468 mdp->is_opened = 1;
2469
86a74ff2
NI		 2470 return ret;
2471
2472out_free_irq:
2473 free_irq(ndev->irq, ndev);
d2779e99
SS		 2474out_napi_off:
2475 napi_disable(&mdp->napi);
bcd5149d 2476 pm_runtime_put_sync(&mdp->pdev->dev);
86a74ff2
NI		 2477 return ret;
2478}
2479
2480/* Timeout function */
2481static void sh_eth_tx_timeout(struct net_device *ndev)
2482{
2483 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 2484 struct sh_eth_rxdesc *rxdesc;
2485 int i;
2486
2487 netif_stop_queue(ndev);
2488
8d5009f6
SS		 2489 netif_err(mdp, timer, ndev,
2490 "transmit timed out, status %8.8x, resetting...\n",
0799c2d6 2491 sh_eth_read(ndev, EESR));
86a74ff2
NI		 2492
2493 /* tx_errors count up */
bb7d92e3 2494 ndev->stats.tx_errors++;
86a74ff2 2495
86a74ff2 2496 /* Free all the skbuffs in the Rx queue. */
525b8075 2497 for (i = 0; i < mdp->num_rx_ring; i++) {
86a74ff2 2498 rxdesc = &mdp->rx_ring[i];
7cf72477
SS		 2499 rxdesc->status = cpu_to_le32(0);
2500 rxdesc->addr = cpu_to_le32(0xBADF00D0);
179d80af 2501 dev_kfree_skb(mdp->rx_skbuff[i]);
86a74ff2
NI		 2502 mdp->rx_skbuff[i] = NULL;
2503 }
525b8075 2504 for (i = 0; i < mdp->num_tx_ring; i++) {
179d80af 2505 dev_kfree_skb(mdp->tx_skbuff[i]);
86a74ff2
NI		 2506 mdp->tx_skbuff[i] = NULL;
2507 }
2508
2509 /* device init */
f7967210 2510 sh_eth_dev_init(ndev);
ad846aa5
SS		 2511
2512 netif_start_queue(ndev);
86a74ff2
NI		 2513}
2514
2515/* Packet transmit function */
2516static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
2517{
2518 struct sh_eth_private *mdp = netdev_priv(ndev);
2519 struct sh_eth_txdesc *txdesc;
1299653a 2520 dma_addr_t dma_addr;
86a74ff2 2521 u32 entry;
fb5e2f9b 2522 unsigned long flags;
86a74ff2
NI		 2523
2524 spin_lock_irqsave(&mdp->lock, flags);
525b8075 2525 if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
1debdc8f 2526 if (!sh_eth_tx_free(ndev, true)) {
8d5009f6 2527 netif_warn(mdp, tx_queued, ndev, "TxFD exhausted.\n");
86a74ff2
NI		 2528 netif_stop_queue(ndev);
2529 spin_unlock_irqrestore(&mdp->lock, flags);
5b548140 2530 return NETDEV_TX_BUSY;
86a74ff2
NI		 2531 }
2532 }
2533 spin_unlock_irqrestore(&mdp->lock, flags);
2534
dacc73e0 2535 if (skb_put_padto(skb, ETH_ZLEN))
eebfb643
BH		 2536 return NETDEV_TX_OK;
2537
525b8075 2538 entry = mdp->cur_tx % mdp->num_tx_ring;
86a74ff2
NI		 2539 mdp->tx_skbuff[entry] = skb;
2540 txdesc = &mdp->tx_ring[entry];
86a74ff2 2541 /* soft swap. */
380af9e3 2542 if (!mdp->cd->hw_swap)
3e230993 2543 sh_eth_soft_swap(PTR_ALIGN(skb->data, 4), skb->len + 2);
22c1aed4 2544 dma_addr = dma_map_single(&mdp->pdev->dev, skb->data, skb->len,
1299653a 2545 DMA_TO_DEVICE);
22c1aed4 2546 if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) {
aa3933b8
BH		 2547 kfree_skb(skb);
2548 return NETDEV_TX_OK;
2549 }
7cf72477
SS		 2550 txdesc->addr = cpu_to_le32(dma_addr);
2551 txdesc->len = cpu_to_le32(skb->len << 16);
86a74ff2 2552
f32bfb9a 2553 dma_wmb(); /* TACT bit must be set after all the above writes */
525b8075 2554 if (entry >= mdp->num_tx_ring - 1)
7cf72477 2555 txdesc->status |= cpu_to_le32(TD_TACT | TD_TDLE);
86a74ff2 2556 else
7cf72477 2557 txdesc->status |= cpu_to_le32(TD_TACT);
86a74ff2
NI		 2558
2559 mdp->cur_tx++;
2560
3e416992
SS		 2561 if (!(sh_eth_read(ndev, EDTRR) & mdp->cd->edtrr_trns))
2562 sh_eth_write(ndev, mdp->cd->edtrr_trns, EDTRR);
b0ca2a21 2563
6ed10654 2564 return NETDEV_TX_OK;
86a74ff2
NI		 2565}
2566
4398f9c8
BH		 2567/* The statistics registers have write-clear behaviour, which means we
2568 * will lose any increment between the read and write. We mitigate
2569 * this by only clearing when we read a non-zero value, so we will
2570 * never falsely report a total of zero.
2571 */
2572static void
2573sh_eth_update_stat(struct net_device *ndev, unsigned long *stat, int reg)
2574{
2575 u32 delta = sh_eth_read(ndev, reg);
2576
2577 if (delta) {
2578 *stat += delta;
2579 sh_eth_write(ndev, 0, reg);
2580 }
2581}
2582
7fa2955f
MK		 2583static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
2584{
2585 struct sh_eth_private *mdp = netdev_priv(ndev);
2586
ce9134df 2587 if (mdp->cd->no_tx_cntrs)
7fa2955f
MK		 2588 return &ndev->stats;
2589
2590 if (!mdp->is_opened)
2591 return &ndev->stats;
2592
4398f9c8
BH		 2593 sh_eth_update_stat(ndev, &ndev->stats.tx_dropped, TROCR);
2594 sh_eth_update_stat(ndev, &ndev->stats.collisions, CDCR);
2595 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, LCCR);
7fa2955f 2596
4c1d4585 2597 if (mdp->cd->cexcr) {
4398f9c8
BH		 2598 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2599 CERCR);
2600 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2601 CEECR);
7fa2955f 2602 } else {
4398f9c8
BH		 2603 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2604 CNDCR);
7fa2955f
MK		 2605 }
2606
2607 return &ndev->stats;
2608}
2609
86a74ff2
NI		 2610/* device close function */
2611static int sh_eth_close(struct net_device *ndev)
2612{
2613 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 2614
2615 netif_stop_queue(ndev);
2616
283e38db
BH		 2617 /* Serialise with the interrupt handler and NAPI, then disable
2618 * interrupts. We have to clear the irq_enabled flag first to
2619 * ensure that interrupts won't be re-enabled.
2620 */
2621 mdp->irq_enabled = false;
2622 synchronize_irq(ndev->irq);
2623 napi_disable(&mdp->napi);
4a55530f 2624 sh_eth_write(ndev, 0x0000, EESIPR);
86a74ff2 2625
740c7f31 2626 sh_eth_dev_exit(ndev);
86a74ff2
NI		 2627
2628 /* PHY Disconnect */
9fd0375a
PR		 2629 if (ndev->phydev) {
2630 phy_stop(ndev->phydev);
2631 phy_disconnect(ndev->phydev);
86a74ff2
NI		 2632 }
2633
2634 free_irq(ndev->irq, ndev);
2635
8e03a5e7 2636 /* Free all the skbuffs in the Rx queue and the DMA buffer. */
86a74ff2
NI		 2637 sh_eth_ring_free(ndev);
2638
bcd5149d
MD		 2639 pm_runtime_put_sync(&mdp->pdev->dev);
2640
7fa2955f 2641 mdp->is_opened = 0;
bcd5149d 2642
7fa2955f 2643 return 0;
86a74ff2
NI		 2644}
2645
bb7d92e3 2646/* ioctl to device function */
128296fc 2647static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
86a74ff2 2648{
9fd0375a 2649 struct phy_device *phydev = ndev->phydev;
86a74ff2
NI		 2650
2651 if (!netif_running(ndev))
2652 return -EINVAL;
2653
2654 if (!phydev)
2655 return -ENODEV;
2656
28b04113 2657 return phy_mii_ioctl(phydev, rq, cmd);
86a74ff2
NI		 2658}
2659
78d61022
NS		 2660static int sh_eth_change_mtu(struct net_device *ndev, int new_mtu)
2661{
2662 if (netif_running(ndev))
2663 return -EBUSY;
2664
2665 ndev->mtu = new_mtu;
2666 netdev_update_features(ndev);
2667
2668 return 0;
2669}
2670
6743fe6d 2671/* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
6743fe6d
YS		 2672static u32 sh_eth_tsu_get_post_mask(int entry)
2673{
2674 return 0x0f << (28 - ((entry % 8) * 4));
2675}
2676
2677static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
2678{
2679 return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
2680}
2681
2682static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
2683 int entry)
2684{
2685 struct sh_eth_private *mdp = netdev_priv(ndev);
77cb065f 2686 int reg = TSU_POST1 + entry / 8;
6743fe6d 2687 u32 tmp;
6743fe6d 2688
77cb065f
SS		 2689 tmp = sh_eth_tsu_read(mdp, reg);
2690 sh_eth_tsu_write(mdp, tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg);
6743fe6d
YS		 2691}
2692
2693static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
2694 int entry)
2695{
2696 struct sh_eth_private *mdp = netdev_priv(ndev);
77cb065f 2697 int reg = TSU_POST1 + entry / 8;
6743fe6d 2698 u32 post_mask, ref_mask, tmp;
6743fe6d 2699
6743fe6d
YS		 2700 post_mask = sh_eth_tsu_get_post_mask(entry);
2701 ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
2702
77cb065f
SS		 2703 tmp = sh_eth_tsu_read(mdp, reg);
2704 sh_eth_tsu_write(mdp, tmp & ~post_mask, reg);
6743fe6d
YS		 2705
2706 /* If other port enables, the function returns "true" */
2707 return tmp & ref_mask;
2708}
2709
2710static int sh_eth_tsu_busy(struct net_device *ndev)
2711{
2712 int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
2713 struct sh_eth_private *mdp = netdev_priv(ndev);
2714
2715 while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
2716 udelay(10);
2717 timeout--;
2718 if (timeout <= 0) {
da246855 2719 netdev_err(ndev, "%s: timeout\n", __func__);
6743fe6d
YS		 2720 return -ETIMEDOUT;
2721 }
2722 }
2723
2724 return 0;
2725}
2726
7a54c867 2727static int sh_eth_tsu_write_entry(struct net_device *ndev, u16 offset,
6743fe6d
YS		 2728 const u8 *addr)
2729{
7a54c867 2730 struct sh_eth_private *mdp = netdev_priv(ndev);
6743fe6d
YS		 2731 u32 val;
2732
2733 val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
7a54c867 2734 iowrite32(val, mdp->tsu_addr + offset);
6743fe6d
YS		 2735 if (sh_eth_tsu_busy(ndev) < 0)
2736 return -EBUSY;
2737
2738 val = addr[4] << 8 | addr[5];
7a54c867 2739 iowrite32(val, mdp->tsu_addr + offset + 4);
6743fe6d
YS		 2740 if (sh_eth_tsu_busy(ndev) < 0)
2741 return -EBUSY;
2742
2743 return 0;
2744}
2745
51459d4c 2746static void sh_eth_tsu_read_entry(struct net_device *ndev, u16 offset, u8 *addr)
6743fe6d 2747{
51459d4c 2748 struct sh_eth_private *mdp = netdev_priv(ndev);
6743fe6d
YS		 2749 u32 val;
2750
51459d4c 2751 val = ioread32(mdp->tsu_addr + offset);
6743fe6d
YS		 2752 addr[0] = (val >> 24) & 0xff;
2753 addr[1] = (val >> 16) & 0xff;
2754 addr[2] = (val >> 8) & 0xff;
2755 addr[3] = val & 0xff;
51459d4c 2756 val = ioread32(mdp->tsu_addr + offset + 4);
6743fe6d
YS		 2757 addr[4] = (val >> 8) & 0xff;
2758 addr[5] = val & 0xff;
2759}
2760
2761
2762static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
2763{
2764 struct sh_eth_private *mdp = netdev_priv(ndev);
41414f0a 2765 u16 reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
6743fe6d
YS		 2766 int i;
2767 u8 c_addr[ETH_ALEN];
2768
2769 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
51459d4c 2770 sh_eth_tsu_read_entry(ndev, reg_offset, c_addr);
c4bde29c 2771 if (ether_addr_equal(addr, c_addr))
6743fe6d
YS		 2772 return i;
2773 }
2774
2775 return -ENOENT;
2776}
2777
2778static int sh_eth_tsu_find_empty(struct net_device *ndev)
2779{
2780 u8 blank[ETH_ALEN];
2781 int entry;
2782
2783 memset(blank, 0, sizeof(blank));
2784 entry = sh_eth_tsu_find_entry(ndev, blank);
2785 return (entry < 0) ? -ENOMEM : entry;
2786}
2787
2788static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
2789 int entry)
2790{
2791 struct sh_eth_private *mdp = netdev_priv(ndev);
41414f0a 2792 u16 reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
6743fe6d
YS		 2793 int ret;
2794 u8 blank[ETH_ALEN];
2795
2796 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
2797 ~(1 << (31 - entry)), TSU_TEN);
2798
2799 memset(blank, 0, sizeof(blank));
7a54c867 2800 ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
6743fe6d
YS		 2801 if (ret < 0)
2802 return ret;
2803 return 0;
2804}
2805
2806static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
2807{
2808 struct sh_eth_private *mdp = netdev_priv(ndev);
41414f0a 2809 u16 reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
6743fe6d
YS		 2810 int i, ret;
2811
2812 if (!mdp->cd->tsu)
2813 return 0;
2814
2815 i = sh_eth_tsu_find_entry(ndev, addr);
2816 if (i < 0) {
2817 /* No entry found, create one */
2818 i = sh_eth_tsu_find_empty(ndev);
2819 if (i < 0)
2820 return -ENOMEM;
7a54c867 2821 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
6743fe6d
YS		 2822 if (ret < 0)
2823 return ret;
2824
2825 /* Enable the entry */
2826 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
2827 (1 << (31 - i)), TSU_TEN);
2828 }
2829
2830 /* Entry found or created, enable POST */
2831 sh_eth_tsu_enable_cam_entry_post(ndev, i);
2832
2833 return 0;
2834}
2835
2836static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
2837{
2838 struct sh_eth_private *mdp = netdev_priv(ndev);
2839 int i, ret;
2840
2841 if (!mdp->cd->tsu)
2842 return 0;
2843
2844 i = sh_eth_tsu_find_entry(ndev, addr);
2845 if (i) {
2846 /* Entry found */
2847 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2848 goto done;
2849
2850 /* Disable the entry if both ports was disabled */
2851 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2852 if (ret < 0)
2853 return ret;
2854 }
2855done:
2856 return 0;
2857}
2858
2859static int sh_eth_tsu_purge_all(struct net_device *ndev)
2860{
2861 struct sh_eth_private *mdp = netdev_priv(ndev);
2862 int i, ret;
2863
b37feed7 2864 if (!mdp->cd->tsu)
6743fe6d
YS		 2865 return 0;
2866
2867 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
2868 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2869 continue;
2870
2871 /* Disable the entry if both ports was disabled */
2872 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2873 if (ret < 0)
2874 return ret;
2875 }
2876
2877 return 0;
2878}
2879
2880static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
2881{
2882 struct sh_eth_private *mdp = netdev_priv(ndev);
41414f0a 2883 u16 reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
6743fe6d 2884 u8 addr[ETH_ALEN];
6743fe6d
YS		 2885 int i;
2886
b37feed7 2887 if (!mdp->cd->tsu)
6743fe6d
YS		 2888 return;
2889
2890 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
51459d4c 2891 sh_eth_tsu_read_entry(ndev, reg_offset, addr);
6743fe6d
YS		 2892 if (is_multicast_ether_addr(addr))
2893 sh_eth_tsu_del_entry(ndev, addr);
2894 }
2895}
2896
b37feed7
BH		 2897/* Update promiscuous flag and multicast filter */
2898static void sh_eth_set_rx_mode(struct net_device *ndev)
86a74ff2 2899{
6743fe6d
YS		 2900 struct sh_eth_private *mdp = netdev_priv(ndev);
2901 u32 ecmr_bits;
2902 int mcast_all = 0;
2903 unsigned long flags;
2904
2905 spin_lock_irqsave(&mdp->lock, flags);
128296fc 2906 /* Initial condition is MCT = 1, PRM = 0.
6743fe6d
YS		 2907 * Depending on ndev->flags, set PRM or clear MCT
2908 */
b37feed7
BH		 2909 ecmr_bits = sh_eth_read(ndev, ECMR) & ~ECMR_PRM;
2910 if (mdp->cd->tsu)
2911 ecmr_bits |= ECMR_MCT;
6743fe6d
YS		 2912
2913 if (!(ndev->flags & IFF_MULTICAST)) {
2914 sh_eth_tsu_purge_mcast(ndev);
2915 mcast_all = 1;
2916 }
2917 if (ndev->flags & IFF_ALLMULTI) {
2918 sh_eth_tsu_purge_mcast(ndev);
2919 ecmr_bits &= ~ECMR_MCT;
2920 mcast_all = 1;
2921 }
2922
86a74ff2 2923 if (ndev->flags & IFF_PROMISC) {
6743fe6d
YS		 2924 sh_eth_tsu_purge_all(ndev);
2925 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2926 } else if (mdp->cd->tsu) {
2927 struct netdev_hw_addr *ha;
2928 netdev_for_each_mc_addr(ha, ndev) {
2929 if (mcast_all && is_multicast_ether_addr(ha->addr))
2930 continue;
2931
2932 if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2933 if (!mcast_all) {
2934 sh_eth_tsu_purge_mcast(ndev);
2935 ecmr_bits &= ~ECMR_MCT;
2936 mcast_all = 1;
2937 }
2938 }
2939 }
86a74ff2 2940 }
6743fe6d
YS		 2941
2942 /* update the ethernet mode */
2943 sh_eth_write(ndev, ecmr_bits, ECMR);
2944
2945 spin_unlock_irqrestore(&mdp->lock, flags);
86a74ff2 2946}
71cc7c37 2947
f8e022db
SS		 2948static void sh_eth_set_rx_csum(struct net_device *ndev, bool enable)
2949{
2950 struct sh_eth_private *mdp = netdev_priv(ndev);
2951 unsigned long flags;
2952
2953 spin_lock_irqsave(&mdp->lock, flags);
2954
2955 /* Disable TX and RX */
2956 sh_eth_rcv_snd_disable(ndev);
2957
2958 /* Modify RX Checksum setting */
2959 sh_eth_modify(ndev, ECMR, ECMR_RCSC, enable ? ECMR_RCSC : 0);
2960
2961 /* Enable TX and RX */
2962 sh_eth_rcv_snd_enable(ndev);
2963
2964 spin_unlock_irqrestore(&mdp->lock, flags);
2965}
2966
2967static int sh_eth_set_features(struct net_device *ndev,
2968 netdev_features_t features)
2969{
2970 netdev_features_t changed = ndev->features ^ features;
2971 struct sh_eth_private *mdp = netdev_priv(ndev);
2972
2973 if (changed & NETIF_F_RXCSUM && mdp->cd->rx_csum)
2974 sh_eth_set_rx_csum(ndev, features & NETIF_F_RXCSUM);
2975
2976 ndev->features = features;
2977
2978 return 0;
2979}
2980
71cc7c37
YS		 2981static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2982{
2983 if (!mdp->port)
2984 return TSU_VTAG0;
2985 else
2986 return TSU_VTAG1;
2987}
2988
80d5c368
PM		 2989static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
2990 __be16 proto, u16 vid)
71cc7c37
YS		 2991{
2992 struct sh_eth_private *mdp = netdev_priv(ndev);
2993 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2994
2995 if (unlikely(!mdp->cd->tsu))
2996 return -EPERM;
2997
2998 /* No filtering if vid = 0 */
2999 if (!vid)
3000 return 0;
3001
3002 mdp->vlan_num_ids++;
3003
128296fc 3004 /* The controller has one VLAN tag HW filter. So, if the filter is
71cc7c37
YS		 3005 * already enabled, the driver disables it and the filte
3006 */
3007 if (mdp->vlan_num_ids > 1) {
3008 /* disable VLAN filter */
3009 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
3010 return 0;
3011 }
3012
3013 sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
3014 vtag_reg_index);
3015
3016 return 0;
3017}
3018
80d5c368
PM		 3019static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
3020 __be16 proto, u16 vid)
71cc7c37
YS		 3021{
3022 struct sh_eth_private *mdp = netdev_priv(ndev);
3023 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
3024
3025 if (unlikely(!mdp->cd->tsu))
3026 return -EPERM;
3027
3028 /* No filtering if vid = 0 */
3029 if (!vid)
3030 return 0;
3031
3032 mdp->vlan_num_ids--;
3033 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
3034
3035 return 0;
3036}
86a74ff2
NI		 3037
3038/* SuperH's TSU register init function */
4a55530f 3039static void sh_eth_tsu_init(struct sh_eth_private *mdp)
86a74ff2 3040{
a94cf2a6 3041 if (!mdp->cd->dual_port) {
db893473 3042 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
e1487888
CB		 3043 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL,
3044 TSU_FWSLC); /* Enable POST registers */
db893473
SH		 3045 return;
3046 }
3047
4a55530f
YS		 3048 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */
3049 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */
3050 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */
3051 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
3052 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
3053 sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
3054 sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
3055 sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
3056 sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
3057 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
4869a147
SS		 3058 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */
3059 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */
4a55530f
YS		 3060 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */
3061 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */
3062 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
3063 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */
3064 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */
3065 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */
3066 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */
86a74ff2
NI		 3067}
3068
3069/* MDIO bus release function */
bd920ff5 3070static int sh_mdio_release(struct sh_eth_private *mdp)
86a74ff2 3071{
86a74ff2 3072 /* unregister mdio bus */
bd920ff5 3073 mdiobus_unregister(mdp->mii_bus);
86a74ff2
NI		 3074
3075 /* free bitbang info */
bd920ff5 3076 free_mdio_bitbang(mdp->mii_bus);
86a74ff2
NI		 3077
3078 return 0;
3079}
3080
3081/* MDIO bus init function */
bd920ff5 3082static int sh_mdio_init(struct sh_eth_private *mdp,
b3017e6a 3083 struct sh_eth_plat_data *pd)
86a74ff2 3084{
e7f4dc35 3085 int ret;
86a74ff2 3086 struct bb_info *bitbang;
bd920ff5 3087 struct platform_device *pdev = mdp->pdev;
aa8d4225 3088 struct device *dev = &mdp->pdev->dev;
86a74ff2
NI		 3089
3090 /* create bit control struct for PHY */
aa8d4225 3091 bitbang = devm_kzalloc(dev, sizeof(struct bb_info), GFP_KERNEL);
f738a13d
LP		 3092 if (!bitbang)
3093 return -ENOMEM;
86a74ff2
NI		 3094
3095 /* bitbang init */
ae70644d 3096 bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
b3017e6a 3097 bitbang->set_gate = pd->set_mdio_gate;
86a74ff2
NI		 3098 bitbang->ctrl.ops = &bb_ops;
3099
c2e07b3a 3100 /* MII controller setting */
86a74ff2 3101 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
f738a13d
LP		 3102 if (!mdp->mii_bus)
3103 return -ENOMEM;
86a74ff2
NI		 3104
3105 /* Hook up MII support for ethtool */
3106 mdp->mii_bus->name = "sh_mii";
a5bd6060 3107 mdp->mii_bus->parent = dev;
5278fb54 3108 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
bd920ff5 3109 pdev->name, pdev->id);
86a74ff2 3110
bd920ff5 3111 /* register MDIO bus */
00e798c7
FF		 3112 if (pd->phy_irq > 0)
3113 mdp->mii_bus->irq[pd->phy] = pd->phy_irq;
702eca02 3114
00e798c7 3115 ret = of_mdiobus_register(mdp->mii_bus, dev->of_node);
86a74ff2 3116 if (ret)
d5e07e69 3117 goto out_free_bus;
86a74ff2 3118
86a74ff2
NI		 3119 return 0;
3120
86a74ff2 3121out_free_bus:
298cf9be 3122 free_mdio_bitbang(mdp->mii_bus);
86a74ff2
NI		 3123 return ret;
3124}
3125
4a55530f
YS		 3126static const u16 *sh_eth_get_register_offset(int register_type)
3127{
3128 const u16 *reg_offset = NULL;
3129
3130 switch (register_type) {
3131 case SH_ETH_REG_GIGABIT:
3132 reg_offset = sh_eth_offset_gigabit;
3133 break;
db893473
SH		 3134 case SH_ETH_REG_FAST_RZ:
3135 reg_offset = sh_eth_offset_fast_rz;
3136 break;
a3f109bd
SS		 3137 case SH_ETH_REG_FAST_RCAR:
3138 reg_offset = sh_eth_offset_fast_rcar;
3139 break;
4a55530f
YS		 3140 case SH_ETH_REG_FAST_SH4:
3141 reg_offset = sh_eth_offset_fast_sh4;
3142 break;
3143 case SH_ETH_REG_FAST_SH3_SH2:
3144 reg_offset = sh_eth_offset_fast_sh3_sh2;
3145 break;
4a55530f
YS		 3146 }
3147
3148 return reg_offset;
3149}
3150
8f728d79 3151static const struct net_device_ops sh_eth_netdev_ops = {
ebf84eaa
AB		 3152 .ndo_open = sh_eth_open,
3153 .ndo_stop = sh_eth_close,
3154 .ndo_start_xmit = sh_eth_start_xmit,
3155 .ndo_get_stats = sh_eth_get_stats,
b37feed7 3156 .ndo_set_rx_mode = sh_eth_set_rx_mode,
ebf84eaa
AB		 3157 .ndo_tx_timeout = sh_eth_tx_timeout,
3158 .ndo_do_ioctl = sh_eth_do_ioctl,
78d61022 3159 .ndo_change_mtu = sh_eth_change_mtu,
ebf84eaa
AB		 3160 .ndo_validate_addr = eth_validate_addr,
3161 .ndo_set_mac_address = eth_mac_addr,
f8e022db 3162 .ndo_set_features = sh_eth_set_features,
ebf84eaa
AB		 3163};
3164
8f728d79
SS		 3165static const struct net_device_ops sh_eth_netdev_ops_tsu = {
3166 .ndo_open = sh_eth_open,
3167 .ndo_stop = sh_eth_close,
3168 .ndo_start_xmit = sh_eth_start_xmit,
3169 .ndo_get_stats = sh_eth_get_stats,
b37feed7 3170 .ndo_set_rx_mode = sh_eth_set_rx_mode,
8f728d79
SS		 3171 .ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid,
3172 .ndo_vlan_rx_kill_vid = sh_eth_vlan_rx_kill_vid,
3173 .ndo_tx_timeout = sh_eth_tx_timeout,
3174 .ndo_do_ioctl = sh_eth_do_ioctl,
78d61022 3175 .ndo_change_mtu = sh_eth_change_mtu,
8f728d79
SS		 3176 .ndo_validate_addr = eth_validate_addr,
3177 .ndo_set_mac_address = eth_mac_addr,
f8e022db 3178 .ndo_set_features = sh_eth_set_features,
8f728d79
SS		 3179};
3180
b356e978
SS		 3181#ifdef CONFIG_OF
3182static struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
3183{
3184 struct device_node *np = dev->of_node;
3185 struct sh_eth_plat_data *pdata;
b356e978 3186 const char *mac_addr;
035a14e7 3187 int ret;
b356e978
SS		 3188
3189 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
3190 if (!pdata)
3191 return NULL;
3192
035a14e7
KL		 3193 ret = of_get_phy_mode(np);
3194 if (ret < 0)
3195 return NULL;
3196 pdata->phy_interface = ret;
b356e978 3197
b356e978 3198 mac_addr = of_get_mac_address(np);
a51645f7 3199 if (!IS_ERR(mac_addr))
2d2924af 3200 ether_addr_copy(pdata->mac_addr, mac_addr);
b356e978
SS		 3201
3202 pdata->no_ether_link =
3203 of_property_read_bool(np, "renesas,no-ether-link");
3204 pdata->ether_link_active_low =
3205 of_property_read_bool(np, "renesas,ether-link-active-low");
3206
3207 return pdata;
3208}
3209
3210static const struct of_device_id sh_eth_match_table[] = {
3211 { .compatible = "renesas,gether-r8a7740", .data = &r8a7740_data },
6c4b2f7e
SH		 3212 { .compatible = "renesas,ether-r8a7743", .data = &rcar_gen2_data },
3213 { .compatible = "renesas,ether-r8a7745", .data = &rcar_gen2_data },
3214 { .compatible = "renesas,ether-r8a7778", .data = &rcar_gen1_data },
3215 { .compatible = "renesas,ether-r8a7779", .data = &rcar_gen1_data },
3216 { .compatible = "renesas,ether-r8a7790", .data = &rcar_gen2_data },
3217 { .compatible = "renesas,ether-r8a7791", .data = &rcar_gen2_data },
3218 { .compatible = "renesas,ether-r8a7793", .data = &rcar_gen2_data },
3219 { .compatible = "renesas,ether-r8a7794", .data = &rcar_gen2_data },
3eb9c2ad 3220 { .compatible = "renesas,gether-r8a77980", .data = &r8a77980_data },
b356e978 3221 { .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data },
6e0bb04d 3222 { .compatible = "renesas,ether-r7s9210", .data = &r7s9210_data },
b4804e0c
SH		 3223 { .compatible = "renesas,rcar-gen1-ether", .data = &rcar_gen1_data },
3224 { .compatible = "renesas,rcar-gen2-ether", .data = &rcar_gen2_data },
b356e978
SS		 3225 { }
3226};
3227MODULE_DEVICE_TABLE(of, sh_eth_match_table);
3228#else
3229static inline struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
3230{
3231 return NULL;
3232}
3233#endif
3234
86a74ff2
NI		 3235static int sh_eth_drv_probe(struct platform_device *pdev)
3236{
86a74ff2 3237 struct resource *res;
0b76b862 3238 struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev);
afe391ad 3239 const struct platform_device_id *id = platform_get_device_id(pdev);
4fa8c3cc
SS		 3240 struct sh_eth_private *mdp;
3241 struct net_device *ndev;
9662ec19 3242 int ret;
86a74ff2
NI		 3243
3244 /* get base addr */
3245 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
86a74ff2
NI		 3246
3247 ndev = alloc_etherdev(sizeof(struct sh_eth_private));
f738a13d
LP		 3248 if (!ndev)
3249 return -ENOMEM;
86a74ff2 3250
b5893a08
BD		 3251 pm_runtime_enable(&pdev->dev);
3252 pm_runtime_get_sync(&pdev->dev);
3253
cc3c080d 3254 ret = platform_get_irq(pdev, 0);
7a468ac6 3255 if (ret < 0)
86a74ff2 3256 goto out_release;
cc3c080d 3257 ndev->irq = ret;
86a74ff2
NI		 3258
3259 SET_NETDEV_DEV(ndev, &pdev->dev);
3260
86a74ff2 3261 mdp = netdev_priv(ndev);
525b8075
YS		 3262 mdp->num_tx_ring = TX_RING_SIZE;
3263 mdp->num_rx_ring = RX_RING_SIZE;
d5e07e69
SS		 3264 mdp->addr = devm_ioremap_resource(&pdev->dev, res);
3265 if (IS_ERR(mdp->addr)) {
3266 ret = PTR_ERR(mdp->addr);
ae70644d
YS		 3267 goto out_release;
3268 }
3269
c960804f
VB		 3270 ndev->base_addr = res->start;
3271
86a74ff2 3272 spin_lock_init(&mdp->lock);
bcd5149d 3273 mdp->pdev = pdev;
86a74ff2 3274
b356e978
SS		 3275 if (pdev->dev.of_node)
3276 pd = sh_eth_parse_dt(&pdev->dev);
3b4c5cbf
SS		 3277 if (!pd) {
3278 dev_err(&pdev->dev, "no platform data\n");
3279 ret = -EINVAL;
3280 goto out_release;
3281 }
3282
86a74ff2 3283 /* get PHY ID */
71557a37 3284 mdp->phy_id = pd->phy;
e47c9052 3285 mdp->phy_interface = pd->phy_interface;
4923576b
YS		 3286 mdp->no_ether_link = pd->no_ether_link;
3287 mdp->ether_link_active_low = pd->ether_link_active_low;
86a74ff2 3288
380af9e3 3289 /* set cpu data */
42a67c9b 3290 if (id)
b356e978 3291 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data;
42a67c9b
WS		 3292 else
3293 mdp->cd = (struct sh_eth_cpu_data *)of_device_get_match_data(&pdev->dev);
b356e978 3294
a3153d8c 3295 mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type);
264be2f5
SS		 3296 if (!mdp->reg_offset) {
3297 dev_err(&pdev->dev, "Unknown register type (%d)\n",
3298 mdp->cd->register_type);
3299 ret = -EINVAL;
3300 goto out_release;
3301 }
380af9e3
YS		 3302 sh_eth_set_default_cpu_data(mdp->cd);
3303
78d61022
NS		 3304 /* User's manual states max MTU should be 2048 but due to the
3305 * alignment calculations in sh_eth_ring_init() the practical
3306 * MTU is a bit less. Maybe this can be optimized some more.
3307 */
3308 ndev->max_mtu = 2000 - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN);
3309 ndev->min_mtu = ETH_MIN_MTU;
3310
f8e022db
SS		 3311 if (mdp->cd->rx_csum) {
3312 ndev->features = NETIF_F_RXCSUM;
3313 ndev->hw_features = NETIF_F_RXCSUM;
3314 }
3315
86a74ff2 3316 /* set function */
8f728d79
SS		 3317 if (mdp->cd->tsu)
3318 ndev->netdev_ops = &sh_eth_netdev_ops_tsu;
3319 else
3320 ndev->netdev_ops = &sh_eth_netdev_ops;
7ad24ea4 3321 ndev->ethtool_ops = &sh_eth_ethtool_ops;
86a74ff2
NI		 3322 ndev->watchdog_timeo = TX_TIMEOUT;
3323
dc19e4e5
NI		 3324 /* debug message level */
3325 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
86a74ff2
NI		 3326
3327 /* read and set MAC address */
748031f9 3328 read_mac_address(ndev, pd->mac_addr);
ff6e7228
SS		 3329 if (!is_valid_ether_addr(ndev->dev_addr)) {
3330 dev_warn(&pdev->dev,
3331 "no valid MAC address supplied, using a random one.\n");
3332 eth_hw_addr_random(ndev);
3333 }
86a74ff2 3334
6ba88021 3335 if (mdp->cd->tsu) {
9662ec19 3336 int port = pdev->id < 0 ? 0 : pdev->id % 2;
6ba88021 3337 struct resource *rtsu;
dfe8266b 3338
6ba88021 3339 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
dfe8266b
SS		 3340 if (!rtsu) {
3341 dev_err(&pdev->dev, "no TSU resource\n");
3342 ret = -ENODEV;
3343 goto out_release;
3344 }
3345 /* We can only request the TSU region for the first port
3346 * of the two sharing this TSU for the probe to succeed...
3347 */
9662ec19 3348 if (port == 0 &&
dfe8266b
SS		 3349 !devm_request_mem_region(&pdev->dev, rtsu->start,
3350 resource_size(rtsu),
3351 dev_name(&pdev->dev))) {
3352 dev_err(&pdev->dev, "can't request TSU resource.\n");
3353 ret = -EBUSY;
3354 goto out_release;
3355 }
3e14c969 3356 /* ioremap the TSU registers */
dfe8266b
SS		 3357 mdp->tsu_addr = devm_ioremap(&pdev->dev, rtsu->start,
3358 resource_size(rtsu));
3359 if (!mdp->tsu_addr) {
3360 dev_err(&pdev->dev, "TSU region ioremap() failed.\n");
3361 ret = -ENOMEM;
fc0c0900
SS		 3362 goto out_release;
3363 }
9662ec19 3364 mdp->port = port;
f8e022db 3365 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
6ba88021 3366
3e14c969 3367 /* Need to init only the first port of the two sharing a TSU */
9662ec19 3368 if (port == 0) {
3e14c969
SS		 3369 if (mdp->cd->chip_reset)
3370 mdp->cd->chip_reset(ndev);
86a74ff2 3371
4986b996
YS		 3372 /* TSU init (Init only)*/
3373 sh_eth_tsu_init(mdp);
3374 }
86a74ff2
NI		 3375 }
3376
966d6dbb
HN		 3377 if (mdp->cd->rmiimode)
3378 sh_eth_write(ndev, 0x1, RMIIMODE);
3379
daacf03f
LP		 3380 /* MDIO bus init */
3381 ret = sh_mdio_init(mdp, pd);
3382 if (ret) {
b7ce520e
GU		 3383 if (ret != -EPROBE_DEFER)
3384 dev_err(&pdev->dev, "MDIO init failed: %d\n", ret);
daacf03f
LP		 3385 goto out_release;
3386 }
3387
3719109d
SS		 3388 netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64);
3389
86a74ff2
NI		 3390 /* network device register */
3391 ret = register_netdev(ndev);
3392 if (ret)
3719109d 3393 goto out_napi_del;
86a74ff2 3394
b4580c95 3395 if (mdp->cd->magic)
d8981d02
NS		 3396 device_set_wakeup_capable(&pdev->dev, 1);
3397
25985edc 3398 /* print device information */
f75f14ec
SS		 3399 netdev_info(ndev, "Base address at 0x%x, %pM, IRQ %d.\n",
3400 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
86a74ff2 3401
b5893a08 3402 pm_runtime_put(&pdev->dev);
86a74ff2
NI		 3403 platform_set_drvdata(pdev, ndev);
3404
3405 return ret;
3406
3719109d
SS		 3407out_napi_del:
3408 netif_napi_del(&mdp->napi);
daacf03f 3409 sh_mdio_release(mdp);
3719109d 3410
86a74ff2
NI		 3411out_release:
3412 /* net_dev free */
4282fc47 3413 free_netdev(ndev);
86a74ff2 3414
b5893a08
BD		 3415 pm_runtime_put(&pdev->dev);
3416 pm_runtime_disable(&pdev->dev);
86a74ff2
NI		 3417 return ret;
3418}
3419
3420static int sh_eth_drv_remove(struct platform_device *pdev)
3421{
3422 struct net_device *ndev = platform_get_drvdata(pdev);
3719109d 3423 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2 3424
86a74ff2 3425 unregister_netdev(ndev);
3719109d 3426 netif_napi_del(&mdp->napi);
daacf03f 3427 sh_mdio_release(mdp);
bcd5149d 3428 pm_runtime_disable(&pdev->dev);
86a74ff2 3429 free_netdev(ndev);
86a74ff2
NI		 3430
3431 return 0;
3432}
3433
540ad1b8 3434#ifdef CONFIG_PM
b71af046 3435#ifdef CONFIG_PM_SLEEP
d8981d02
NS		 3436static int sh_eth_wol_setup(struct net_device *ndev)
3437{
3438 struct sh_eth_private *mdp = netdev_priv(ndev);
3439
3440 /* Only allow ECI interrupts */
3441 synchronize_irq(ndev->irq);
3442 napi_disable(&mdp->napi);
1a0bee6c 3443 sh_eth_write(ndev, EESIPR_ECIIP, EESIPR);
d8981d02
NS		 3444
3445 /* Enable MagicPacket */
5e2ed132 3446 sh_eth_modify(ndev, ECMR, ECMR_MPDE, ECMR_MPDE);
d8981d02 3447
d8981d02
NS		 3448 return enable_irq_wake(ndev->irq);
3449}
3450
3451static int sh_eth_wol_restore(struct net_device *ndev)
3452{
3453 struct sh_eth_private *mdp = netdev_priv(ndev);
3454 int ret;
3455
3456 napi_enable(&mdp->napi);
3457
3458 /* Disable MagicPacket */
3459 sh_eth_modify(ndev, ECMR, ECMR_MPDE, 0);
3460
3461 /* The device needs to be reset to restore MagicPacket logic
3462 * for next wakeup. If we close and open the device it will
3463 * both be reset and all registers restored. This is what
3464 * happens during suspend and resume without WoL enabled.
3465 */
3466 ret = sh_eth_close(ndev);
3467 if (ret < 0)
3468 return ret;
3469 ret = sh_eth_open(ndev);
3470 if (ret < 0)
3471 return ret;
3472
d8981d02
NS		 3473 return disable_irq_wake(ndev->irq);
3474}
3475
b71af046
MU		 3476static int sh_eth_suspend(struct device *dev)
3477{
3478 struct net_device *ndev = dev_get_drvdata(dev);
d8981d02 3479 struct sh_eth_private *mdp = netdev_priv(ndev);
b71af046
MU		 3480 int ret = 0;
3481
d8981d02
NS		 3482 if (!netif_running(ndev))
3483 return 0;
3484
3485 netif_device_detach(ndev);
3486
3487 if (mdp->wol_enabled)
3488 ret = sh_eth_wol_setup(ndev);
3489 else
b71af046 3490 ret = sh_eth_close(ndev);
b71af046
MU		 3491
3492 return ret;
3493}
3494
3495static int sh_eth_resume(struct device *dev)
3496{
3497 struct net_device *ndev = dev_get_drvdata(dev);
d8981d02 3498 struct sh_eth_private *mdp = netdev_priv(ndev);
b71af046
MU		 3499 int ret = 0;
3500
d8981d02
NS		 3501 if (!netif_running(ndev))
3502 return 0;
3503
3504 if (mdp->wol_enabled)
3505 ret = sh_eth_wol_restore(ndev);
3506 else
b71af046 3507 ret = sh_eth_open(ndev);
d8981d02
NS		 3508
3509 if (ret < 0)
3510 return ret;
3511
3512 netif_device_attach(ndev);
b71af046
MU		 3513
3514 return ret;
3515}
3516#endif
3517
bcd5149d
MD		 3518static int sh_eth_runtime_nop(struct device *dev)
3519{
128296fc 3520 /* Runtime PM callback shared between ->runtime_suspend()
bcd5149d
MD		 3521 * and ->runtime_resume(). Simply returns success.
3522 *
3523 * This driver re-initializes all registers after
3524 * pm_runtime_get_sync() anyway so there is no need
3525 * to save and restore registers here.
3526 */
3527 return 0;
3528}
3529
540ad1b8 3530static const struct dev_pm_ops sh_eth_dev_pm_ops = {
b71af046 3531 SET_SYSTEM_SLEEP_PM_OPS(sh_eth_suspend, sh_eth_resume)
e7d7e898 3532 SET_RUNTIME_PM_OPS(sh_eth_runtime_nop, sh_eth_runtime_nop, NULL)
bcd5149d 3533};
540ad1b8
NI		 3534#define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
3535#else
3536#define SH_ETH_PM_OPS NULL
3537#endif
bcd5149d 3538
ef00df85 3539static const struct platform_device_id sh_eth_id_table[] = {
c18a79ab 3540 { "sh7619-ether", (kernel_ulong_t)&sh7619_data },
7bbe150d 3541 { "sh771x-ether", (kernel_ulong_t)&sh771x_data },
9c3beaab 3542 { "sh7724-ether", (kernel_ulong_t)&sh7724_data },
f5d12767 3543 { "sh7734-gether", (kernel_ulong_t)&sh7734_data },
24549e2a
SS		 3544 { "sh7757-ether", (kernel_ulong_t)&sh7757_data },
3545 { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga },
f5d12767 3546 { "sh7763-gether", (kernel_ulong_t)&sh7763_data },
afe391ad
SS		 3547 { }
3548};
3549MODULE_DEVICE_TABLE(platform, sh_eth_id_table);
3550
86a74ff2
NI		 3551static struct platform_driver sh_eth_driver = {
3552 .probe = sh_eth_drv_probe,
3553 .remove = sh_eth_drv_remove,
afe391ad 3554 .id_table = sh_eth_id_table,
86a74ff2
NI		 3555 .driver = {
3556 .name = CARDNAME,
540ad1b8 3557 .pm = SH_ETH_PM_OPS,
b356e978 3558 .of_match_table = of_match_ptr(sh_eth_match_table),
86a74ff2
NI		 3559 },
3560};
3561
db62f684 3562module_platform_driver(sh_eth_driver);
86a74ff2
NI		 3563
3564MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
3565MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
3566MODULE_LICENSE("GPL v2");
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