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Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/jkirsher/net...
[mirror_ubuntu-jammy-kernel.git] / drivers / net / ethernet / renesas / sh_eth.c
CommitLineData
86a74ff2
NI		 1/*
2 * SuperH Ethernet device driver
3 *
f0e81fec 4 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu
a3f109bd
SS		 5 * Copyright (C) 2008-2013 Renesas Solutions Corp.
6 * Copyright (C) 2013 Cogent Embedded, Inc.
86a74ff2
NI		 7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 * You should have received a copy of the GNU General Public License along with
17 * this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * The full GNU General Public License is included in this distribution in
21 * the file called "COPYING".
22 */
23
86a74ff2 24#include <linux/init.h>
0654011d
YS		 25#include <linux/module.h>
26#include <linux/kernel.h>
27#include <linux/spinlock.h>
6a27cded 28#include <linux/interrupt.h>
86a74ff2
NI		 29#include <linux/dma-mapping.h>
30#include <linux/etherdevice.h>
31#include <linux/delay.h>
32#include <linux/platform_device.h>
33#include <linux/mdio-bitbang.h>
34#include <linux/netdevice.h>
35#include <linux/phy.h>
36#include <linux/cache.h>
37#include <linux/io.h>
bcd5149d 38#include <linux/pm_runtime.h>
5a0e3ad6 39#include <linux/slab.h>
dc19e4e5 40#include <linux/ethtool.h>
fdb37a7f 41#include <linux/if_vlan.h>
f0e81fec 42#include <linux/clk.h>
d4fa0e35 43#include <linux/sh_eth.h>
86a74ff2
NI		 44
45#include "sh_eth.h"
46
dc19e4e5
NI		 47#define SH_ETH_DEF_MSG_ENABLE \
48 (NETIF_MSG_LINK | \
49 NETIF_MSG_TIMER | \
50 NETIF_MSG_RX_ERR| \
51 NETIF_MSG_TX_ERR)
52
c0013f6f
SS		 53static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
54 [EDSR] = 0x0000,
55 [EDMR] = 0x0400,
56 [EDTRR] = 0x0408,
57 [EDRRR] = 0x0410,
58 [EESR] = 0x0428,
59 [EESIPR] = 0x0430,
60 [TDLAR] = 0x0010,
61 [TDFAR] = 0x0014,
62 [TDFXR] = 0x0018,
63 [TDFFR] = 0x001c,
64 [RDLAR] = 0x0030,
65 [RDFAR] = 0x0034,
66 [RDFXR] = 0x0038,
67 [RDFFR] = 0x003c,
68 [TRSCER] = 0x0438,
69 [RMFCR] = 0x0440,
70 [TFTR] = 0x0448,
71 [FDR] = 0x0450,
72 [RMCR] = 0x0458,
73 [RPADIR] = 0x0460,
74 [FCFTR] = 0x0468,
75 [CSMR] = 0x04E4,
76
77 [ECMR] = 0x0500,
78 [ECSR] = 0x0510,
79 [ECSIPR] = 0x0518,
80 [PIR] = 0x0520,
81 [PSR] = 0x0528,
82 [PIPR] = 0x052c,
83 [RFLR] = 0x0508,
84 [APR] = 0x0554,
85 [MPR] = 0x0558,
86 [PFTCR] = 0x055c,
87 [PFRCR] = 0x0560,
88 [TPAUSER] = 0x0564,
89 [GECMR] = 0x05b0,
90 [BCULR] = 0x05b4,
91 [MAHR] = 0x05c0,
92 [MALR] = 0x05c8,
93 [TROCR] = 0x0700,
94 [CDCR] = 0x0708,
95 [LCCR] = 0x0710,
96 [CEFCR] = 0x0740,
97 [FRECR] = 0x0748,
98 [TSFRCR] = 0x0750,
99 [TLFRCR] = 0x0758,
100 [RFCR] = 0x0760,
101 [CERCR] = 0x0768,
102 [CEECR] = 0x0770,
103 [MAFCR] = 0x0778,
104 [RMII_MII] = 0x0790,
105
106 [ARSTR] = 0x0000,
107 [TSU_CTRST] = 0x0004,
108 [TSU_FWEN0] = 0x0010,
109 [TSU_FWEN1] = 0x0014,
110 [TSU_FCM] = 0x0018,
111 [TSU_BSYSL0] = 0x0020,
112 [TSU_BSYSL1] = 0x0024,
113 [TSU_PRISL0] = 0x0028,
114 [TSU_PRISL1] = 0x002c,
115 [TSU_FWSL0] = 0x0030,
116 [TSU_FWSL1] = 0x0034,
117 [TSU_FWSLC] = 0x0038,
118 [TSU_QTAG0] = 0x0040,
119 [TSU_QTAG1] = 0x0044,
120 [TSU_FWSR] = 0x0050,
121 [TSU_FWINMK] = 0x0054,
122 [TSU_ADQT0] = 0x0048,
123 [TSU_ADQT1] = 0x004c,
124 [TSU_VTAG0] = 0x0058,
125 [TSU_VTAG1] = 0x005c,
126 [TSU_ADSBSY] = 0x0060,
127 [TSU_TEN] = 0x0064,
128 [TSU_POST1] = 0x0070,
129 [TSU_POST2] = 0x0074,
130 [TSU_POST3] = 0x0078,
131 [TSU_POST4] = 0x007c,
132 [TSU_ADRH0] = 0x0100,
133 [TSU_ADRL0] = 0x0104,
134 [TSU_ADRH31] = 0x01f8,
135 [TSU_ADRL31] = 0x01fc,
136
137 [TXNLCR0] = 0x0080,
138 [TXALCR0] = 0x0084,
139 [RXNLCR0] = 0x0088,
140 [RXALCR0] = 0x008c,
141 [FWNLCR0] = 0x0090,
142 [FWALCR0] = 0x0094,
143 [TXNLCR1] = 0x00a0,
144 [TXALCR1] = 0x00a0,
145 [RXNLCR1] = 0x00a8,
146 [RXALCR1] = 0x00ac,
147 [FWNLCR1] = 0x00b0,
148 [FWALCR1] = 0x00b4,
149};
150
a3f109bd
SS		 151static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
152 [ECMR] = 0x0300,
153 [RFLR] = 0x0308,
154 [ECSR] = 0x0310,
155 [ECSIPR] = 0x0318,
156 [PIR] = 0x0320,
157 [PSR] = 0x0328,
158 [RDMLR] = 0x0340,
159 [IPGR] = 0x0350,
160 [APR] = 0x0354,
161 [MPR] = 0x0358,
162 [RFCF] = 0x0360,
163 [TPAUSER] = 0x0364,
164 [TPAUSECR] = 0x0368,
165 [MAHR] = 0x03c0,
166 [MALR] = 0x03c8,
167 [TROCR] = 0x03d0,
168 [CDCR] = 0x03d4,
169 [LCCR] = 0x03d8,
170 [CNDCR] = 0x03dc,
171 [CEFCR] = 0x03e4,
172 [FRECR] = 0x03e8,
173 [TSFRCR] = 0x03ec,
174 [TLFRCR] = 0x03f0,
175 [RFCR] = 0x03f4,
176 [MAFCR] = 0x03f8,
177
178 [EDMR] = 0x0200,
179 [EDTRR] = 0x0208,
180 [EDRRR] = 0x0210,
181 [TDLAR] = 0x0218,
182 [RDLAR] = 0x0220,
183 [EESR] = 0x0228,
184 [EESIPR] = 0x0230,
185 [TRSCER] = 0x0238,
186 [RMFCR] = 0x0240,
187 [TFTR] = 0x0248,
188 [FDR] = 0x0250,
189 [RMCR] = 0x0258,
190 [TFUCR] = 0x0264,
191 [RFOCR] = 0x0268,
55754f19 192 [RMIIMODE] = 0x026c,
a3f109bd
SS		 193 [FCFTR] = 0x0270,
194 [TRIMD] = 0x027c,
195};
196
c0013f6f
SS		 197static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
198 [ECMR] = 0x0100,
199 [RFLR] = 0x0108,
200 [ECSR] = 0x0110,
201 [ECSIPR] = 0x0118,
202 [PIR] = 0x0120,
203 [PSR] = 0x0128,
204 [RDMLR] = 0x0140,
205 [IPGR] = 0x0150,
206 [APR] = 0x0154,
207 [MPR] = 0x0158,
208 [TPAUSER] = 0x0164,
209 [RFCF] = 0x0160,
210 [TPAUSECR] = 0x0168,
211 [BCFRR] = 0x016c,
212 [MAHR] = 0x01c0,
213 [MALR] = 0x01c8,
214 [TROCR] = 0x01d0,
215 [CDCR] = 0x01d4,
216 [LCCR] = 0x01d8,
217 [CNDCR] = 0x01dc,
218 [CEFCR] = 0x01e4,
219 [FRECR] = 0x01e8,
220 [TSFRCR] = 0x01ec,
221 [TLFRCR] = 0x01f0,
222 [RFCR] = 0x01f4,
223 [MAFCR] = 0x01f8,
224 [RTRATE] = 0x01fc,
225
226 [EDMR] = 0x0000,
227 [EDTRR] = 0x0008,
228 [EDRRR] = 0x0010,
229 [TDLAR] = 0x0018,
230 [RDLAR] = 0x0020,
231 [EESR] = 0x0028,
232 [EESIPR] = 0x0030,
233 [TRSCER] = 0x0038,
234 [RMFCR] = 0x0040,
235 [TFTR] = 0x0048,
236 [FDR] = 0x0050,
237 [RMCR] = 0x0058,
238 [TFUCR] = 0x0064,
239 [RFOCR] = 0x0068,
240 [FCFTR] = 0x0070,
241 [RPADIR] = 0x0078,
242 [TRIMD] = 0x007c,
243 [RBWAR] = 0x00c8,
244 [RDFAR] = 0x00cc,
245 [TBRAR] = 0x00d4,
246 [TDFAR] = 0x00d8,
247};
248
249static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
250 [ECMR] = 0x0160,
251 [ECSR] = 0x0164,
252 [ECSIPR] = 0x0168,
253 [PIR] = 0x016c,
254 [MAHR] = 0x0170,
255 [MALR] = 0x0174,
256 [RFLR] = 0x0178,
257 [PSR] = 0x017c,
258 [TROCR] = 0x0180,
259 [CDCR] = 0x0184,
260 [LCCR] = 0x0188,
261 [CNDCR] = 0x018c,
262 [CEFCR] = 0x0194,
263 [FRECR] = 0x0198,
264 [TSFRCR] = 0x019c,
265 [TLFRCR] = 0x01a0,
266 [RFCR] = 0x01a4,
267 [MAFCR] = 0x01a8,
268 [IPGR] = 0x01b4,
269 [APR] = 0x01b8,
270 [MPR] = 0x01bc,
271 [TPAUSER] = 0x01c4,
272 [BCFR] = 0x01cc,
273
274 [ARSTR] = 0x0000,
275 [TSU_CTRST] = 0x0004,
276 [TSU_FWEN0] = 0x0010,
277 [TSU_FWEN1] = 0x0014,
278 [TSU_FCM] = 0x0018,
279 [TSU_BSYSL0] = 0x0020,
280 [TSU_BSYSL1] = 0x0024,
281 [TSU_PRISL0] = 0x0028,
282 [TSU_PRISL1] = 0x002c,
283 [TSU_FWSL0] = 0x0030,
284 [TSU_FWSL1] = 0x0034,
285 [TSU_FWSLC] = 0x0038,
286 [TSU_QTAGM0] = 0x0040,
287 [TSU_QTAGM1] = 0x0044,
288 [TSU_ADQT0] = 0x0048,
289 [TSU_ADQT1] = 0x004c,
290 [TSU_FWSR] = 0x0050,
291 [TSU_FWINMK] = 0x0054,
292 [TSU_ADSBSY] = 0x0060,
293 [TSU_TEN] = 0x0064,
294 [TSU_POST1] = 0x0070,
295 [TSU_POST2] = 0x0074,
296 [TSU_POST3] = 0x0078,
297 [TSU_POST4] = 0x007c,
298
299 [TXNLCR0] = 0x0080,
300 [TXALCR0] = 0x0084,
301 [RXNLCR0] = 0x0088,
302 [RXALCR0] = 0x008c,
303 [FWNLCR0] = 0x0090,
304 [FWALCR0] = 0x0094,
305 [TXNLCR1] = 0x00a0,
306 [TXALCR1] = 0x00a0,
307 [RXNLCR1] = 0x00a8,
308 [RXALCR1] = 0x00ac,
309 [FWNLCR1] = 0x00b0,
310 [FWALCR1] = 0x00b4,
311
312 [TSU_ADRH0] = 0x0100,
313 [TSU_ADRL0] = 0x0104,
314 [TSU_ADRL31] = 0x01fc,
315};
316
dabdde9e
NI		 317static int sh_eth_is_gether(struct sh_eth_private *mdp)
318{
319 if (mdp->reg_offset == sh_eth_offset_gigabit)
320 return 1;
321 else
322 return 0;
323}
324
8e994402 325static void sh_eth_select_mii(struct net_device *ndev)
5e7a76be
NI		 326{
327 u32 value = 0x0;
328 struct sh_eth_private *mdp = netdev_priv(ndev);
329
330 switch (mdp->phy_interface) {
331 case PHY_INTERFACE_MODE_GMII:
332 value = 0x2;
333 break;
334 case PHY_INTERFACE_MODE_MII:
335 value = 0x1;
336 break;
337 case PHY_INTERFACE_MODE_RMII:
338 value = 0x0;
339 break;
340 default:
341 pr_warn("PHY interface mode was not setup. Set to MII.\n");
342 value = 0x1;
343 break;
344 }
345
346 sh_eth_write(ndev, value, RMII_MII);
347}
5e7a76be 348
8e994402 349static void sh_eth_set_duplex(struct net_device *ndev)
65ac8851
YS		 350{
351 struct sh_eth_private *mdp = netdev_priv(ndev);
65ac8851
YS		 352
353 if (mdp->duplex) /* Full */
4a55530f 354 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
65ac8851 355 else /* Half */
4a55530f 356 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
65ac8851
YS		 357}
358
04b0ed2a 359/* There is CPU dependent code */
589ebdef 360static void sh_eth_set_rate_r8a777x(struct net_device *ndev)
65ac8851
YS		 361{
362 struct sh_eth_private *mdp = netdev_priv(ndev);
d0418bb7 363
a3f109bd
SS		 364 switch (mdp->speed) {
365 case 10: /* 10BASE */
366 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_ELB, ECMR);
367 break;
368 case 100:/* 100BASE */
369 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_ELB, ECMR);
370 break;
371 default:
372 break;
373 }
374}
375
674853b2 376/* R8A7778/9 */
589ebdef 377static struct sh_eth_cpu_data r8a777x_data = {
a3f109bd 378 .set_duplex = sh_eth_set_duplex,
589ebdef 379 .set_rate = sh_eth_set_rate_r8a777x,
a3f109bd
SS		 380
381 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
382 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
383 .eesipr_value = 0x01ff009f,
384
385 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
ca8c3585
SS		 386 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
387 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
388 EESR_ECI,
a3f109bd
SS		 389
390 .apr = 1,
391 .mpr = 1,
392 .tpauser = 1,
393 .hw_swap = 1,
394};
a3f109bd 395
e18dbf7e
SH		 396/* R8A7790 */
397static struct sh_eth_cpu_data r8a7790_data = {
398 .set_duplex = sh_eth_set_duplex,
399 .set_rate = sh_eth_set_rate_r8a777x,
400
401 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
402 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
403 .eesipr_value = 0x01ff009f,
404
405 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
406 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE |
407 EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI,
408
409 .apr = 1,
410 .mpr = 1,
411 .tpauser = 1,
412 .hw_swap = 1,
413 .rmiimode = 1,
414};
415
9c3beaab 416static void sh_eth_set_rate_sh7724(struct net_device *ndev)
a3f109bd
SS		 417{
418 struct sh_eth_private *mdp = netdev_priv(ndev);
65ac8851
YS		 419
420 switch (mdp->speed) {
421 case 10: /* 10BASE */
a3f109bd 422 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_RTM, ECMR);
65ac8851
YS		 423 break;
424 case 100:/* 100BASE */
a3f109bd 425 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_RTM, ECMR);
65ac8851
YS		 426 break;
427 default:
428 break;
429 }
430}
431
432/* SH7724 */
9c3beaab 433static struct sh_eth_cpu_data sh7724_data = {
65ac8851 434 .set_duplex = sh_eth_set_duplex,
9c3beaab 435 .set_rate = sh_eth_set_rate_sh7724,
65ac8851
YS		 436
437 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
438 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
a80c3de7 439 .eesipr_value = 0x01ff009f,
65ac8851
YS		 440
441 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
ca8c3585
SS		 442 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
443 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
444 EESR_ECI,
65ac8851
YS		 445
446 .apr = 1,
447 .mpr = 1,
448 .tpauser = 1,
449 .hw_swap = 1,
503914cf
MD		 450 .rpadir = 1,
451 .rpadir_value = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
65ac8851 452};
5cee1d37 453
24549e2a 454static void sh_eth_set_rate_sh7757(struct net_device *ndev)
f29a3d04
YS		 455{
456 struct sh_eth_private *mdp = netdev_priv(ndev);
f29a3d04
YS		 457
458 switch (mdp->speed) {
459 case 10: /* 10BASE */
4a55530f 460 sh_eth_write(ndev, 0, RTRATE);
f29a3d04
YS		 461 break;
462 case 100:/* 100BASE */
4a55530f 463 sh_eth_write(ndev, 1, RTRATE);
f29a3d04
YS		 464 break;
465 default:
466 break;
467 }
468}
469
470/* SH7757 */
24549e2a
SS		 471static struct sh_eth_cpu_data sh7757_data = {
472 .set_duplex = sh_eth_set_duplex,
473 .set_rate = sh_eth_set_rate_sh7757,
f29a3d04
YS		 474
475 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
476 .rmcr_value = 0x00000001,
477
478 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
ca8c3585
SS		 479 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
480 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
481 EESR_ECI,
f29a3d04 482
5b3dfd13 483 .irq_flags = IRQF_SHARED,
f29a3d04
YS		 484 .apr = 1,
485 .mpr = 1,
486 .tpauser = 1,
487 .hw_swap = 1,
488 .no_ade = 1,
2e98e797
YS		 489 .rpadir = 1,
490 .rpadir_value = 2 << 16,
f29a3d04 491};
65ac8851 492
e403d295 493#define SH_GIGA_ETH_BASE 0xfee00000UL
8fcd4961
YS		 494#define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
495#define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
496static void sh_eth_chip_reset_giga(struct net_device *ndev)
497{
498 int i;
499 unsigned long mahr[2], malr[2];
500
501 /* save MAHR and MALR */
502 for (i = 0; i < 2; i++) {
ae70644d
YS		 503 malr[i] = ioread32((void *)GIGA_MALR(i));
504 mahr[i] = ioread32((void *)GIGA_MAHR(i));
8fcd4961
YS		 505 }
506
507 /* reset device */
ae70644d 508 iowrite32(ARSTR_ARSTR, (void *)(SH_GIGA_ETH_BASE + 0x1800));
8fcd4961
YS		 509 mdelay(1);
510
511 /* restore MAHR and MALR */
512 for (i = 0; i < 2; i++) {
ae70644d
YS		 513 iowrite32(malr[i], (void *)GIGA_MALR(i));
514 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
8fcd4961
YS		 515 }
516}
517
8fcd4961
YS		 518static void sh_eth_set_rate_giga(struct net_device *ndev)
519{
520 struct sh_eth_private *mdp = netdev_priv(ndev);
521
522 switch (mdp->speed) {
523 case 10: /* 10BASE */
524 sh_eth_write(ndev, 0x00000000, GECMR);
525 break;
526 case 100:/* 100BASE */
527 sh_eth_write(ndev, 0x00000010, GECMR);
528 break;
529 case 1000: /* 1000BASE */
530 sh_eth_write(ndev, 0x00000020, GECMR);
531 break;
532 default:
533 break;
534 }
535}
536
537/* SH7757(GETHERC) */
24549e2a 538static struct sh_eth_cpu_data sh7757_data_giga = {
8fcd4961 539 .chip_reset = sh_eth_chip_reset_giga,
04b0ed2a 540 .set_duplex = sh_eth_set_duplex,
8fcd4961
YS		 541 .set_rate = sh_eth_set_rate_giga,
542
543 .ecsr_value = ECSR_ICD | ECSR_MPD,
544 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
545 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
546
547 .tx_check = EESR_TC1 | EESR_FTC,
ca8c3585
SS		 548 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
549 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
550 EESR_TDE | EESR_ECI,
8fcd4961
YS		 551 .fdr_value = 0x0000072f,
552 .rmcr_value = 0x00000001,
553
5b3dfd13 554 .irq_flags = IRQF_SHARED,
8fcd4961
YS		 555 .apr = 1,
556 .mpr = 1,
557 .tpauser = 1,
558 .bculr = 1,
559 .hw_swap = 1,
560 .rpadir = 1,
561 .rpadir_value = 2 << 16,
562 .no_trimd = 1,
563 .no_ade = 1,
3acbc971 564 .tsu = 1,
8fcd4961
YS		 565};
566
380af9e3
YS		 567static void sh_eth_chip_reset(struct net_device *ndev)
568{
4986b996
YS		 569 struct sh_eth_private *mdp = netdev_priv(ndev);
570
380af9e3 571 /* reset device */
4986b996 572 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
380af9e3
YS		 573 mdelay(1);
574}
575
f5d12767 576static void sh_eth_set_rate_gether(struct net_device *ndev)
380af9e3
YS		 577{
578 struct sh_eth_private *mdp = netdev_priv(ndev);
380af9e3
YS		 579
580 switch (mdp->speed) {
581 case 10: /* 10BASE */
4a55530f 582 sh_eth_write(ndev, GECMR_10, GECMR);
380af9e3
YS		 583 break;
584 case 100:/* 100BASE */
4a55530f 585 sh_eth_write(ndev, GECMR_100, GECMR);
380af9e3
YS		 586 break;
587 case 1000: /* 1000BASE */
4a55530f 588 sh_eth_write(ndev, GECMR_1000, GECMR);
380af9e3
YS		 589 break;
590 default:
591 break;
592 }
593}
594
f5d12767
SS		 595/* SH7734 */
596static struct sh_eth_cpu_data sh7734_data = {
380af9e3
YS		 597 .chip_reset = sh_eth_chip_reset,
598 .set_duplex = sh_eth_set_duplex,
f5d12767
SS		 599 .set_rate = sh_eth_set_rate_gether,
600
601 .ecsr_value = ECSR_ICD | ECSR_MPD,
602 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
603 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
604
605 .tx_check = EESR_TC1 | EESR_FTC,
ca8c3585
SS		 606 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
607 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
608 EESR_TDE | EESR_ECI,
f5d12767
SS		 609
610 .apr = 1,
611 .mpr = 1,
612 .tpauser = 1,
613 .bculr = 1,
614 .hw_swap = 1,
615 .no_trimd = 1,
616 .no_ade = 1,
617 .tsu = 1,
618 .hw_crc = 1,
619 .select_mii = 1,
620};
621
622/* SH7763 */
623static struct sh_eth_cpu_data sh7763_data = {
624 .chip_reset = sh_eth_chip_reset,
625 .set_duplex = sh_eth_set_duplex,
626 .set_rate = sh_eth_set_rate_gether,
380af9e3
YS		 627
628 .ecsr_value = ECSR_ICD | ECSR_MPD,
629 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
630 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
631
632 .tx_check = EESR_TC1 | EESR_FTC,
633 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \
634 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \
635 EESR_ECI,
380af9e3
YS		 636
637 .apr = 1,
638 .mpr = 1,
639 .tpauser = 1,
640 .bculr = 1,
641 .hw_swap = 1,
380af9e3
YS		 642 .no_trimd = 1,
643 .no_ade = 1,
4986b996 644 .tsu = 1,
5b3dfd13 645 .irq_flags = IRQF_SHARED,
380af9e3
YS		 646};
647
e5c9b4cd 648static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
73a0d907
YS		 649{
650 struct sh_eth_private *mdp = netdev_priv(ndev);
73a0d907
YS		 651
652 /* reset device */
653 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
654 mdelay(1);
655
5e7a76be 656 sh_eth_select_mii(ndev);
73a0d907
YS		 657}
658
73a0d907 659/* R8A7740 */
e5c9b4cd
SS		 660static struct sh_eth_cpu_data r8a7740_data = {
661 .chip_reset = sh_eth_chip_reset_r8a7740,
73a0d907 662 .set_duplex = sh_eth_set_duplex,
e5c9b4cd 663 .set_rate = sh_eth_set_rate_gether,
73a0d907
YS		 664
665 .ecsr_value = ECSR_ICD | ECSR_MPD,
666 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
667 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
668
669 .tx_check = EESR_TC1 | EESR_FTC,
ca8c3585
SS		 670 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
671 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
672 EESR_TDE | EESR_ECI,
73a0d907
YS		 673
674 .apr = 1,
675 .mpr = 1,
676 .tpauser = 1,
677 .bculr = 1,
678 .hw_swap = 1,
679 .no_trimd = 1,
680 .no_ade = 1,
681 .tsu = 1,
5e7a76be 682 .select_mii = 1,
ac8025a6 683 .shift_rd0 = 1,
73a0d907
YS		 684};
685
c18a79ab 686static struct sh_eth_cpu_data sh7619_data = {
380af9e3
YS		 687 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
688
689 .apr = 1,
690 .mpr = 1,
691 .tpauser = 1,
692 .hw_swap = 1,
693};
7bbe150d
SS		 694
695static struct sh_eth_cpu_data sh771x_data = {
380af9e3 696 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
4986b996 697 .tsu = 1,
380af9e3 698};
380af9e3
YS		 699
700static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
701{
702 if (!cd->ecsr_value)
703 cd->ecsr_value = DEFAULT_ECSR_INIT;
704
705 if (!cd->ecsipr_value)
706 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
707
708 if (!cd->fcftr_value)
709 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF | \
710 DEFAULT_FIFO_F_D_RFD;
711
712 if (!cd->fdr_value)
713 cd->fdr_value = DEFAULT_FDR_INIT;
714
715 if (!cd->rmcr_value)
716 cd->rmcr_value = DEFAULT_RMCR_VALUE;
717
718 if (!cd->tx_check)
719 cd->tx_check = DEFAULT_TX_CHECK;
720
721 if (!cd->eesr_err_check)
722 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
380af9e3
YS		 723}
724
5cee1d37
NI		 725static int sh_eth_check_reset(struct net_device *ndev)
726{
727 int ret = 0;
728 int cnt = 100;
729
730 while (cnt > 0) {
731 if (!(sh_eth_read(ndev, EDMR) & 0x3))
732 break;
733 mdelay(1);
734 cnt--;
735 }
9f8c4265
SS		 736 if (cnt <= 0) {
737 pr_err("Device reset failed\n");
5cee1d37
NI		 738 ret = -ETIMEDOUT;
739 }
740 return ret;
380af9e3 741}
dabdde9e
NI		 742
743static int sh_eth_reset(struct net_device *ndev)
744{
745 struct sh_eth_private *mdp = netdev_priv(ndev);
746 int ret = 0;
747
748 if (sh_eth_is_gether(mdp)) {
749 sh_eth_write(ndev, EDSR_ENALL, EDSR);
750 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER,
751 EDMR);
752
753 ret = sh_eth_check_reset(ndev);
754 if (ret)
755 goto out;
756
757 /* Table Init */
758 sh_eth_write(ndev, 0x0, TDLAR);
759 sh_eth_write(ndev, 0x0, TDFAR);
760 sh_eth_write(ndev, 0x0, TDFXR);
761 sh_eth_write(ndev, 0x0, TDFFR);
762 sh_eth_write(ndev, 0x0, RDLAR);
763 sh_eth_write(ndev, 0x0, RDFAR);
764 sh_eth_write(ndev, 0x0, RDFXR);
765 sh_eth_write(ndev, 0x0, RDFFR);
766
767 /* Reset HW CRC register */
768 if (mdp->cd->hw_crc)
769 sh_eth_write(ndev, 0x0, CSMR);
770
771 /* Select MII mode */
772 if (mdp->cd->select_mii)
773 sh_eth_select_mii(ndev);
774 } else {
775 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER,
776 EDMR);
777 mdelay(3);
778 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER,
779 EDMR);
780 }
781
782out:
783 return ret;
784}
380af9e3 785
73a0d907 786#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
380af9e3
YS		 787static void sh_eth_set_receive_align(struct sk_buff *skb)
788{
789 int reserve;
790
791 reserve = SH4_SKB_RX_ALIGN - ((u32)skb->data & (SH4_SKB_RX_ALIGN - 1));
792 if (reserve)
793 skb_reserve(skb, reserve);
794}
795#else
796static void sh_eth_set_receive_align(struct sk_buff *skb)
797{
798 skb_reserve(skb, SH2_SH3_SKB_RX_ALIGN);
799}
800#endif
801
802
71557a37
YS		 803/* CPU <-> EDMAC endian convert */
804static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x)
805{
806 switch (mdp->edmac_endian) {
807 case EDMAC_LITTLE_ENDIAN:
808 return cpu_to_le32(x);
809 case EDMAC_BIG_ENDIAN:
810 return cpu_to_be32(x);
811 }
812 return x;
813}
814
815static inline __u32 edmac_to_cpu(struct sh_eth_private *mdp, u32 x)
816{
817 switch (mdp->edmac_endian) {
818 case EDMAC_LITTLE_ENDIAN:
819 return le32_to_cpu(x);
820 case EDMAC_BIG_ENDIAN:
821 return be32_to_cpu(x);
822 }
823 return x;
824}
825
86a74ff2
NI		 826/*
827 * Program the hardware MAC address from dev->dev_addr.
828 */
829static void update_mac_address(struct net_device *ndev)
830{
4a55530f
YS		 831 sh_eth_write(ndev,
832 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
833 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
834 sh_eth_write(ndev,
835 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
86a74ff2
NI		 836}
837
838/*
839 * Get MAC address from SuperH MAC address register
840 *
841 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
842 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
843 * When you want use this device, you must set MAC address in bootloader.
844 *
845 */
748031f9 846static void read_mac_address(struct net_device *ndev, unsigned char *mac)
86a74ff2 847{
748031f9
MD		 848 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
849 memcpy(ndev->dev_addr, mac, 6);
850 } else {
4a55530f
YS		 851 ndev->dev_addr[0] = (sh_eth_read(ndev, MAHR) >> 24);
852 ndev->dev_addr[1] = (sh_eth_read(ndev, MAHR) >> 16) & 0xFF;
853 ndev->dev_addr[2] = (sh_eth_read(ndev, MAHR) >> 8) & 0xFF;
854 ndev->dev_addr[3] = (sh_eth_read(ndev, MAHR) & 0xFF);
855 ndev->dev_addr[4] = (sh_eth_read(ndev, MALR) >> 8) & 0xFF;
856 ndev->dev_addr[5] = (sh_eth_read(ndev, MALR) & 0xFF);
748031f9 857 }
86a74ff2
NI		 858}
859
c5ed5368
YS		 860static unsigned long sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
861{
862 if (sh_eth_is_gether(mdp))
863 return EDTRR_TRNS_GETHER;
864 else
865 return EDTRR_TRNS_ETHER;
866}
867
86a74ff2 868struct bb_info {
ae70644d 869 void (*set_gate)(void *addr);
86a74ff2 870 struct mdiobb_ctrl ctrl;
ae70644d 871 void *addr;
86a74ff2
NI		 872 u32 mmd_msk;/* MMD */
873 u32 mdo_msk;
874 u32 mdi_msk;
875 u32 mdc_msk;
876};
877
878/* PHY bit set */
ae70644d 879static void bb_set(void *addr, u32 msk)
86a74ff2 880{
ae70644d 881 iowrite32(ioread32(addr) | msk, addr);
86a74ff2
NI		 882}
883
884/* PHY bit clear */
ae70644d 885static void bb_clr(void *addr, u32 msk)
86a74ff2 886{
ae70644d 887 iowrite32((ioread32(addr) & ~msk), addr);
86a74ff2
NI		 888}
889
890/* PHY bit read */
ae70644d 891static int bb_read(void *addr, u32 msk)
86a74ff2 892{
ae70644d 893 return (ioread32(addr) & msk) != 0;
86a74ff2
NI		 894}
895
896/* Data I/O pin control */
897static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
898{
899 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
b3017e6a
YS		 900
901 if (bitbang->set_gate)
902 bitbang->set_gate(bitbang->addr);
903
86a74ff2
NI		 904 if (bit)
905 bb_set(bitbang->addr, bitbang->mmd_msk);
906 else
907 bb_clr(bitbang->addr, bitbang->mmd_msk);
908}
909
910/* Set bit data*/
911static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
912{
913 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
914
b3017e6a
YS		 915 if (bitbang->set_gate)
916 bitbang->set_gate(bitbang->addr);
917
86a74ff2
NI		 918 if (bit)
919 bb_set(bitbang->addr, bitbang->mdo_msk);
920 else
921 bb_clr(bitbang->addr, bitbang->mdo_msk);
922}
923
924/* Get bit data*/
925static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
926{
927 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
b3017e6a
YS		 928
929 if (bitbang->set_gate)
930 bitbang->set_gate(bitbang->addr);
931
86a74ff2
NI		 932 return bb_read(bitbang->addr, bitbang->mdi_msk);
933}
934
935/* MDC pin control */
936static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
937{
938 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
939
b3017e6a
YS		 940 if (bitbang->set_gate)
941 bitbang->set_gate(bitbang->addr);
942
86a74ff2
NI		 943 if (bit)
944 bb_set(bitbang->addr, bitbang->mdc_msk);
945 else
946 bb_clr(bitbang->addr, bitbang->mdc_msk);
947}
948
949/* mdio bus control struct */
950static struct mdiobb_ops bb_ops = {
951 .owner = THIS_MODULE,
952 .set_mdc = sh_mdc_ctrl,
953 .set_mdio_dir = sh_mmd_ctrl,
954 .set_mdio_data = sh_set_mdio,
955 .get_mdio_data = sh_get_mdio,
956};
957
86a74ff2
NI		 958/* free skb and descriptor buffer */
959static void sh_eth_ring_free(struct net_device *ndev)
960{
961 struct sh_eth_private *mdp = netdev_priv(ndev);
962 int i;
963
964 /* Free Rx skb ringbuffer */
965 if (mdp->rx_skbuff) {
525b8075 966 for (i = 0; i < mdp->num_rx_ring; i++) {
86a74ff2
NI		 967 if (mdp->rx_skbuff[i])
968 dev_kfree_skb(mdp->rx_skbuff[i]);
969 }
970 }
971 kfree(mdp->rx_skbuff);
91c77550 972 mdp->rx_skbuff = NULL;
86a74ff2
NI		 973
974 /* Free Tx skb ringbuffer */
975 if (mdp->tx_skbuff) {
525b8075 976 for (i = 0; i < mdp->num_tx_ring; i++) {
86a74ff2
NI		 977 if (mdp->tx_skbuff[i])
978 dev_kfree_skb(mdp->tx_skbuff[i]);
979 }
980 }
981 kfree(mdp->tx_skbuff);
91c77550 982 mdp->tx_skbuff = NULL;
86a74ff2
NI		 983}
984
985/* format skb and descriptor buffer */
986static void sh_eth_ring_format(struct net_device *ndev)
987{
988 struct sh_eth_private *mdp = netdev_priv(ndev);
989 int i;
990 struct sk_buff *skb;
991 struct sh_eth_rxdesc *rxdesc = NULL;
992 struct sh_eth_txdesc *txdesc = NULL;
525b8075
YS		 993 int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
994 int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
86a74ff2
NI		 995
996 mdp->cur_rx = mdp->cur_tx = 0;
997 mdp->dirty_rx = mdp->dirty_tx = 0;
998
999 memset(mdp->rx_ring, 0, rx_ringsize);
1000
1001 /* build Rx ring buffer */
525b8075 1002 for (i = 0; i < mdp->num_rx_ring; i++) {
86a74ff2
NI		 1003 /* skb */
1004 mdp->rx_skbuff[i] = NULL;
dae2e9f4 1005 skb = netdev_alloc_skb(ndev, mdp->rx_buf_sz);
86a74ff2
NI		 1006 mdp->rx_skbuff[i] = skb;
1007 if (skb == NULL)
1008 break;
bb7d92e3 1009 dma_map_single(&ndev->dev, skb->data, mdp->rx_buf_sz,
e88aae7b 1010 DMA_FROM_DEVICE);
380af9e3
YS		 1011 sh_eth_set_receive_align(skb);
1012
86a74ff2
NI		 1013 /* RX descriptor */
1014 rxdesc = &mdp->rx_ring[i];
0029d64a 1015 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
71557a37 1016 rxdesc->status = cpu_to_edmac(mdp, RD_RACT | RD_RFP);
86a74ff2
NI		 1017
1018 /* The size of the buffer is 16 byte boundary. */
0029d64a 1019 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
b0ca2a21
NI		 1020 /* Rx descriptor address set */
1021 if (i == 0) {
4a55530f 1022 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
c5ed5368
YS		 1023 if (sh_eth_is_gether(mdp))
1024 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
b0ca2a21 1025 }
86a74ff2
NI		 1026 }
1027
525b8075 1028 mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
86a74ff2
NI		 1029
1030 /* Mark the last entry as wrapping the ring. */
71557a37 1031 rxdesc->status |= cpu_to_edmac(mdp, RD_RDEL);
86a74ff2
NI		 1032
1033 memset(mdp->tx_ring, 0, tx_ringsize);
1034
1035 /* build Tx ring buffer */
525b8075 1036 for (i = 0; i < mdp->num_tx_ring; i++) {
86a74ff2
NI		 1037 mdp->tx_skbuff[i] = NULL;
1038 txdesc = &mdp->tx_ring[i];
71557a37 1039 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
86a74ff2 1040 txdesc->buffer_length = 0;
b0ca2a21 1041 if (i == 0) {
71557a37 1042 /* Tx descriptor address set */
4a55530f 1043 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
c5ed5368
YS		 1044 if (sh_eth_is_gether(mdp))
1045 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
b0ca2a21 1046 }
86a74ff2
NI		 1047 }
1048
71557a37 1049 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
86a74ff2
NI		 1050}
1051
1052/* Get skb and descriptor buffer */
1053static int sh_eth_ring_init(struct net_device *ndev)
1054{
1055 struct sh_eth_private *mdp = netdev_priv(ndev);
1056 int rx_ringsize, tx_ringsize, ret = 0;
1057
1058 /*
1059 * +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
1060 * card needs room to do 8 byte alignment, +2 so we can reserve
1061 * the first 2 bytes, and +16 gets room for the status word from the
1062 * card.
1063 */
1064 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
1065 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
503914cf
MD		 1066 if (mdp->cd->rpadir)
1067 mdp->rx_buf_sz += NET_IP_ALIGN;
86a74ff2
NI		 1068
1069 /* Allocate RX and TX skb rings */
b2adaca9
JP		 1070 mdp->rx_skbuff = kmalloc_array(mdp->num_rx_ring,
1071 sizeof(*mdp->rx_skbuff), GFP_KERNEL);
86a74ff2 1072 if (!mdp->rx_skbuff) {
86a74ff2
NI		 1073 ret = -ENOMEM;
1074 return ret;
1075 }
1076
b2adaca9
JP		 1077 mdp->tx_skbuff = kmalloc_array(mdp->num_tx_ring,
1078 sizeof(*mdp->tx_skbuff), GFP_KERNEL);
86a74ff2 1079 if (!mdp->tx_skbuff) {
86a74ff2
NI		 1080 ret = -ENOMEM;
1081 goto skb_ring_free;
1082 }
1083
1084 /* Allocate all Rx descriptors. */
525b8075 1085 rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
86a74ff2 1086 mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
d0320f75 1087 GFP_KERNEL);
86a74ff2 1088 if (!mdp->rx_ring) {
86a74ff2
NI		 1089 ret = -ENOMEM;
1090 goto desc_ring_free;
1091 }
1092
1093 mdp->dirty_rx = 0;
1094
1095 /* Allocate all Tx descriptors. */
525b8075 1096 tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
86a74ff2 1097 mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
d0320f75 1098 GFP_KERNEL);
86a74ff2 1099 if (!mdp->tx_ring) {
86a74ff2
NI		 1100 ret = -ENOMEM;
1101 goto desc_ring_free;
1102 }
1103 return ret;
1104
1105desc_ring_free:
1106 /* free DMA buffer */
1107 dma_free_coherent(NULL, rx_ringsize, mdp->rx_ring, mdp->rx_desc_dma);
1108
1109skb_ring_free:
1110 /* Free Rx and Tx skb ring buffer */
1111 sh_eth_ring_free(ndev);
91c77550
YS		 1112 mdp->tx_ring = NULL;
1113 mdp->rx_ring = NULL;
86a74ff2
NI		 1114
1115 return ret;
1116}
1117
91c77550
YS		 1118static void sh_eth_free_dma_buffer(struct sh_eth_private *mdp)
1119{
1120 int ringsize;
1121
1122 if (mdp->rx_ring) {
525b8075 1123 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
91c77550
YS		 1124 dma_free_coherent(NULL, ringsize, mdp->rx_ring,
1125 mdp->rx_desc_dma);
1126 mdp->rx_ring = NULL;
1127 }
1128
1129 if (mdp->tx_ring) {
525b8075 1130 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
91c77550
YS		 1131 dma_free_coherent(NULL, ringsize, mdp->tx_ring,
1132 mdp->tx_desc_dma);
1133 mdp->tx_ring = NULL;
1134 }
1135}
1136
525b8075 1137static int sh_eth_dev_init(struct net_device *ndev, bool start)
86a74ff2
NI		 1138{
1139 int ret = 0;
1140 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 1141 u32 val;
1142
1143 /* Soft Reset */
5cee1d37
NI		 1144 ret = sh_eth_reset(ndev);
1145 if (ret)
1146 goto out;
86a74ff2 1147
55754f19
SH		 1148 if (mdp->cd->rmiimode)
1149 sh_eth_write(ndev, 0x1, RMIIMODE);
1150
b0ca2a21
NI		 1151 /* Descriptor format */
1152 sh_eth_ring_format(ndev);
380af9e3 1153 if (mdp->cd->rpadir)
4a55530f 1154 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
86a74ff2
NI		 1155
1156 /* all sh_eth int mask */
4a55530f 1157 sh_eth_write(ndev, 0, EESIPR);
86a74ff2 1158
10b9194f 1159#if defined(__LITTLE_ENDIAN)
380af9e3 1160 if (mdp->cd->hw_swap)
4a55530f 1161 sh_eth_write(ndev, EDMR_EL, EDMR);
380af9e3 1162 else
b0ca2a21 1163#endif
4a55530f 1164 sh_eth_write(ndev, 0, EDMR);
86a74ff2 1165
b0ca2a21 1166 /* FIFO size set */
4a55530f
YS		 1167 sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
1168 sh_eth_write(ndev, 0, TFTR);
86a74ff2 1169
b0ca2a21 1170 /* Frame recv control */
4a55530f 1171 sh_eth_write(ndev, mdp->cd->rmcr_value, RMCR);
86a74ff2 1172
2ecbb783 1173 sh_eth_write(ndev, DESC_I_RINT8 | DESC_I_RINT5 | DESC_I_TINT2, TRSCER);
86a74ff2 1174
380af9e3 1175 if (mdp->cd->bculr)
4a55530f 1176 sh_eth_write(ndev, 0x800, BCULR); /* Burst sycle set */
b0ca2a21 1177
4a55530f 1178 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
86a74ff2 1179
380af9e3 1180 if (!mdp->cd->no_trimd)
4a55530f 1181 sh_eth_write(ndev, 0, TRIMD);
86a74ff2 1182
b0ca2a21 1183 /* Recv frame limit set register */
fdb37a7f
YS		 1184 sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1185 RFLR);
86a74ff2 1186
4a55530f 1187 sh_eth_write(ndev, sh_eth_read(ndev, EESR), EESR);
525b8075
YS		 1188 if (start)
1189 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
86a74ff2
NI		 1190
1191 /* PAUSE Prohibition */
4a55530f 1192 val = (sh_eth_read(ndev, ECMR) & ECMR_DM) |
86a74ff2
NI		 1193 ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE;
1194
4a55530f 1195 sh_eth_write(ndev, val, ECMR);
b0ca2a21 1196
380af9e3
YS		 1197 if (mdp->cd->set_rate)
1198 mdp->cd->set_rate(ndev);
1199
b0ca2a21 1200 /* E-MAC Status Register clear */
4a55530f 1201 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
b0ca2a21
NI		 1202
1203 /* E-MAC Interrupt Enable register */
525b8075
YS		 1204 if (start)
1205 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
86a74ff2
NI		 1206
1207 /* Set MAC address */
1208 update_mac_address(ndev);
1209
1210 /* mask reset */
380af9e3 1211 if (mdp->cd->apr)
4a55530f 1212 sh_eth_write(ndev, APR_AP, APR);
380af9e3 1213 if (mdp->cd->mpr)
4a55530f 1214 sh_eth_write(ndev, MPR_MP, MPR);
380af9e3 1215 if (mdp->cd->tpauser)
4a55530f 1216 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
b0ca2a21 1217
525b8075
YS		 1218 if (start) {
1219 /* Setting the Rx mode will start the Rx process. */
1220 sh_eth_write(ndev, EDRRR_R, EDRRR);
86a74ff2 1221
525b8075
YS		 1222 netif_start_queue(ndev);
1223 }
86a74ff2 1224
5cee1d37 1225out:
86a74ff2
NI		 1226 return ret;
1227}
1228
1229/* free Tx skb function */
1230static int sh_eth_txfree(struct net_device *ndev)
1231{
1232 struct sh_eth_private *mdp = netdev_priv(ndev);
1233 struct sh_eth_txdesc *txdesc;
1234 int freeNum = 0;
1235 int entry = 0;
1236
1237 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
525b8075 1238 entry = mdp->dirty_tx % mdp->num_tx_ring;
86a74ff2 1239 txdesc = &mdp->tx_ring[entry];
71557a37 1240 if (txdesc->status & cpu_to_edmac(mdp, TD_TACT))
86a74ff2
NI		 1241 break;
1242 /* Free the original skb. */
1243 if (mdp->tx_skbuff[entry]) {
31fcb99d
YS		 1244 dma_unmap_single(&ndev->dev, txdesc->addr,
1245 txdesc->buffer_length, DMA_TO_DEVICE);
86a74ff2
NI		 1246 dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1247 mdp->tx_skbuff[entry] = NULL;
1248 freeNum++;
1249 }
71557a37 1250 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
525b8075 1251 if (entry >= mdp->num_tx_ring - 1)
71557a37 1252 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
86a74ff2 1253
bb7d92e3
ED		 1254 ndev->stats.tx_packets++;
1255 ndev->stats.tx_bytes += txdesc->buffer_length;
86a74ff2
NI		 1256 }
1257 return freeNum;
1258}
1259
1260/* Packet receive function */
3719109d 1261static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
86a74ff2
NI		 1262{
1263 struct sh_eth_private *mdp = netdev_priv(ndev);
1264 struct sh_eth_rxdesc *rxdesc;
1265
525b8075
YS		 1266 int entry = mdp->cur_rx % mdp->num_rx_ring;
1267 int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
86a74ff2 1268 struct sk_buff *skb;
3719109d 1269 int exceeded = 0;
86a74ff2 1270 u16 pkt_len = 0;
380af9e3 1271 u32 desc_status;
86a74ff2
NI		 1272
1273 rxdesc = &mdp->rx_ring[entry];
71557a37
YS		 1274 while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) {
1275 desc_status = edmac_to_cpu(mdp, rxdesc->status);
86a74ff2
NI		 1276 pkt_len = rxdesc->frame_length;
1277
1278 if (--boguscnt < 0)
1279 break;
1280
3719109d
SS		 1281 if (*quota <= 0) {
1282 exceeded = 1;
1283 break;
1284 }
1285 (*quota)--;
1286
86a74ff2 1287 if (!(desc_status & RDFEND))
bb7d92e3 1288 ndev->stats.rx_length_errors++;
86a74ff2 1289
dd019897
YS		 1290 /*
1291 * In case of almost all GETHER/ETHERs, the Receive Frame State
1292 * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
1293 * bit 0. However, in case of the R8A7740's GETHER, the RFS
1294 * bits are from bit 25 to bit 16. So, the driver needs right
1295 * shifting by 16.
1296 */
ac8025a6
SS		 1297 if (mdp->cd->shift_rd0)
1298 desc_status >>= 16;
dd019897 1299
86a74ff2
NI		 1300 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1301 RD_RFS5 | RD_RFS6 | RD_RFS10)) {
bb7d92e3 1302 ndev->stats.rx_errors++;
86a74ff2 1303 if (desc_status & RD_RFS1)
bb7d92e3 1304 ndev->stats.rx_crc_errors++;
86a74ff2 1305 if (desc_status & RD_RFS2)
bb7d92e3 1306 ndev->stats.rx_frame_errors++;
86a74ff2 1307 if (desc_status & RD_RFS3)
bb7d92e3 1308 ndev->stats.rx_length_errors++;
86a74ff2 1309 if (desc_status & RD_RFS4)
bb7d92e3 1310 ndev->stats.rx_length_errors++;
86a74ff2 1311 if (desc_status & RD_RFS6)
bb7d92e3 1312 ndev->stats.rx_missed_errors++;
86a74ff2 1313 if (desc_status & RD_RFS10)
bb7d92e3 1314 ndev->stats.rx_over_errors++;
86a74ff2 1315 } else {
380af9e3
YS		 1316 if (!mdp->cd->hw_swap)
1317 sh_eth_soft_swap(
1318 phys_to_virt(ALIGN(rxdesc->addr, 4)),
1319 pkt_len + 2);
86a74ff2
NI		 1320 skb = mdp->rx_skbuff[entry];
1321 mdp->rx_skbuff[entry] = NULL;
503914cf
MD		 1322 if (mdp->cd->rpadir)
1323 skb_reserve(skb, NET_IP_ALIGN);
86a74ff2
NI		 1324 skb_put(skb, pkt_len);
1325 skb->protocol = eth_type_trans(skb, ndev);
1326 netif_rx(skb);
bb7d92e3
ED		 1327 ndev->stats.rx_packets++;
1328 ndev->stats.rx_bytes += pkt_len;
86a74ff2 1329 }
71557a37 1330 rxdesc->status |= cpu_to_edmac(mdp, RD_RACT);
525b8075 1331 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
862df497 1332 rxdesc = &mdp->rx_ring[entry];
86a74ff2
NI		 1333 }
1334
1335 /* Refill the Rx ring buffers. */
1336 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
525b8075 1337 entry = mdp->dirty_rx % mdp->num_rx_ring;
86a74ff2 1338 rxdesc = &mdp->rx_ring[entry];
b0ca2a21 1339 /* The size of the buffer is 16 byte boundary. */
0029d64a 1340 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
b0ca2a21 1341
86a74ff2 1342 if (mdp->rx_skbuff[entry] == NULL) {
dae2e9f4 1343 skb = netdev_alloc_skb(ndev, mdp->rx_buf_sz);
86a74ff2
NI		 1344 mdp->rx_skbuff[entry] = skb;
1345 if (skb == NULL)
1346 break; /* Better luck next round. */
bb7d92e3 1347 dma_map_single(&ndev->dev, skb->data, mdp->rx_buf_sz,
e88aae7b 1348 DMA_FROM_DEVICE);
380af9e3
YS		 1349 sh_eth_set_receive_align(skb);
1350
bc8acf2c 1351 skb_checksum_none_assert(skb);
0029d64a 1352 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
86a74ff2 1353 }
525b8075 1354 if (entry >= mdp->num_rx_ring - 1)
86a74ff2 1355 rxdesc->status |=
71557a37 1356 cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDEL);
86a74ff2
NI		 1357 else
1358 rxdesc->status |=
71557a37 1359 cpu_to_edmac(mdp, RD_RACT | RD_RFP);
86a74ff2
NI		 1360 }
1361
1362 /* Restart Rx engine if stopped. */
1363 /* If we don't need to check status, don't. -KDU */
79fba9f5 1364 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
a18e08bd
YS		 1365 /* fix the values for the next receiving if RDE is set */
1366 if (intr_status & EESR_RDE)
1367 mdp->cur_rx = mdp->dirty_rx =
1368 (sh_eth_read(ndev, RDFAR) -
1369 sh_eth_read(ndev, RDLAR)) >> 4;
4a55530f 1370 sh_eth_write(ndev, EDRRR_R, EDRRR);
79fba9f5 1371 }
86a74ff2 1372
3719109d 1373 return exceeded;
86a74ff2
NI		 1374}
1375
4a55530f 1376static void sh_eth_rcv_snd_disable(struct net_device *ndev)
dc19e4e5
NI		 1377{
1378 /* disable tx and rx */
4a55530f
YS		 1379 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) &
1380 ~(ECMR_RE | ECMR_TE), ECMR);
dc19e4e5
NI		 1381}
1382
4a55530f 1383static void sh_eth_rcv_snd_enable(struct net_device *ndev)
dc19e4e5
NI		 1384{
1385 /* enable tx and rx */
4a55530f
YS		 1386 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) |
1387 (ECMR_RE | ECMR_TE), ECMR);
dc19e4e5
NI		 1388}
1389
86a74ff2
NI		 1390/* error control function */
1391static void sh_eth_error(struct net_device *ndev, int intr_status)
1392{
1393 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2 1394 u32 felic_stat;
380af9e3
YS		 1395 u32 link_stat;
1396 u32 mask;
86a74ff2
NI		 1397
1398 if (intr_status & EESR_ECI) {
4a55530f
YS		 1399 felic_stat = sh_eth_read(ndev, ECSR);
1400 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */
86a74ff2 1401 if (felic_stat & ECSR_ICD)
bb7d92e3 1402 ndev->stats.tx_carrier_errors++;
86a74ff2
NI		 1403 if (felic_stat & ECSR_LCHNG) {
1404 /* Link Changed */
4923576b 1405 if (mdp->cd->no_psr || mdp->no_ether_link) {
1e1b812b 1406 goto ignore_link;
380af9e3 1407 } else {
4a55530f 1408 link_stat = (sh_eth_read(ndev, PSR));
4923576b
YS		 1409 if (mdp->ether_link_active_low)
1410 link_stat = ~link_stat;
380af9e3 1411 }
dc19e4e5 1412 if (!(link_stat & PHY_ST_LINK))
4a55530f 1413 sh_eth_rcv_snd_disable(ndev);
dc19e4e5 1414 else {
86a74ff2 1415 /* Link Up */
4a55530f
YS		 1416 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) &
1417 ~DMAC_M_ECI, EESIPR);
86a74ff2 1418 /*clear int */
4a55530f
YS		 1419 sh_eth_write(ndev, sh_eth_read(ndev, ECSR),
1420 ECSR);
1421 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) |
1422 DMAC_M_ECI, EESIPR);
86a74ff2 1423 /* enable tx and rx */
4a55530f 1424 sh_eth_rcv_snd_enable(ndev);
86a74ff2
NI		 1425 }
1426 }
1427 }
1428
1e1b812b 1429ignore_link:
86a74ff2 1430 if (intr_status & EESR_TWB) {
4eb313a7
SS		 1431 /* Unused write back interrupt */
1432 if (intr_status & EESR_TABT) { /* Transmit Abort int */
bb7d92e3 1433 ndev->stats.tx_aborted_errors++;
dc19e4e5
NI		 1434 if (netif_msg_tx_err(mdp))
1435 dev_err(&ndev->dev, "Transmit Abort\n");
4eb313a7 1436 }
86a74ff2
NI		 1437 }
1438
1439 if (intr_status & EESR_RABT) {
1440 /* Receive Abort int */
1441 if (intr_status & EESR_RFRMER) {
1442 /* Receive Frame Overflow int */
bb7d92e3 1443 ndev->stats.rx_frame_errors++;
dc19e4e5
NI		 1444 if (netif_msg_rx_err(mdp))
1445 dev_err(&ndev->dev, "Receive Abort\n");
86a74ff2
NI		 1446 }
1447 }
380af9e3 1448
dc19e4e5
NI		 1449 if (intr_status & EESR_TDE) {
1450 /* Transmit Descriptor Empty int */
bb7d92e3 1451 ndev->stats.tx_fifo_errors++;
dc19e4e5
NI		 1452 if (netif_msg_tx_err(mdp))
1453 dev_err(&ndev->dev, "Transmit Descriptor Empty\n");
1454 }
1455
1456 if (intr_status & EESR_TFE) {
1457 /* FIFO under flow */
bb7d92e3 1458 ndev->stats.tx_fifo_errors++;
dc19e4e5
NI		 1459 if (netif_msg_tx_err(mdp))
1460 dev_err(&ndev->dev, "Transmit FIFO Under flow\n");
86a74ff2
NI		 1461 }
1462
1463 if (intr_status & EESR_RDE) {
1464 /* Receive Descriptor Empty int */
bb7d92e3 1465 ndev->stats.rx_over_errors++;
86a74ff2 1466
dc19e4e5
NI		 1467 if (netif_msg_rx_err(mdp))
1468 dev_err(&ndev->dev, "Receive Descriptor Empty\n");
86a74ff2 1469 }
dc19e4e5 1470
86a74ff2
NI		 1471 if (intr_status & EESR_RFE) {
1472 /* Receive FIFO Overflow int */
bb7d92e3 1473 ndev->stats.rx_fifo_errors++;
dc19e4e5
NI		 1474 if (netif_msg_rx_err(mdp))
1475 dev_err(&ndev->dev, "Receive FIFO Overflow\n");
1476 }
1477
1478 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1479 /* Address Error */
bb7d92e3 1480 ndev->stats.tx_fifo_errors++;
dc19e4e5
NI		 1481 if (netif_msg_tx_err(mdp))
1482 dev_err(&ndev->dev, "Address Error\n");
86a74ff2 1483 }
380af9e3
YS		 1484
1485 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1486 if (mdp->cd->no_ade)
1487 mask &= ~EESR_ADE;
1488 if (intr_status & mask) {
86a74ff2 1489 /* Tx error */
4a55530f 1490 u32 edtrr = sh_eth_read(ndev, EDTRR);
86a74ff2 1491 /* dmesg */
380af9e3
YS		 1492 dev_err(&ndev->dev, "TX error. status=%8.8x cur_tx=%8.8x ",
1493 intr_status, mdp->cur_tx);
1494 dev_err(&ndev->dev, "dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
86a74ff2
NI		 1495 mdp->dirty_tx, (u32) ndev->state, edtrr);
1496 /* dirty buffer free */
1497 sh_eth_txfree(ndev);
1498
1499 /* SH7712 BUG */
c5ed5368 1500 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
86a74ff2 1501 /* tx dma start */
c5ed5368 1502 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
86a74ff2
NI		 1503 }
1504 /* wakeup */
1505 netif_wake_queue(ndev);
1506 }
1507}
1508
1509static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1510{
1511 struct net_device *ndev = netdev;
1512 struct sh_eth_private *mdp = netdev_priv(ndev);
380af9e3 1513 struct sh_eth_cpu_data *cd = mdp->cd;
0e0fde3c 1514 irqreturn_t ret = IRQ_NONE;
3719109d 1515 unsigned long intr_status, intr_enable;
86a74ff2 1516
86a74ff2
NI		 1517 spin_lock(&mdp->lock);
1518
3893b273 1519 /* Get interrupt status */
4a55530f 1520 intr_status = sh_eth_read(ndev, EESR);
3893b273
SS		 1521 /* Mask it with the interrupt mask, forcing ECI interrupt to be always
1522 * enabled since it's the one that comes thru regardless of the mask,
1523 * and we need to fully handle it in sh_eth_error() in order to quench
1524 * it as it doesn't get cleared by just writing 1 to the ECI bit...
1525 */
3719109d
SS		 1526 intr_enable = sh_eth_read(ndev, EESIPR);
1527 intr_status &= intr_enable | DMAC_M_ECI;
1528 if (intr_status & (EESR_RX_CHECK | cd->tx_check | cd->eesr_err_check))
0e0fde3c 1529 ret = IRQ_HANDLED;
3719109d 1530 else
0e0fde3c 1531 goto other_irq;
86a74ff2 1532
3719109d
SS		 1533 if (intr_status & EESR_RX_CHECK) {
1534 if (napi_schedule_prep(&mdp->napi)) {
1535 /* Mask Rx interrupts */
1536 sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK,
1537 EESIPR);
1538 __napi_schedule(&mdp->napi);
1539 } else {
1540 dev_warn(&ndev->dev,
1541 "ignoring interrupt, status 0x%08lx, mask 0x%08lx.\n",
1542 intr_status, intr_enable);
1543 }
1544 }
86a74ff2 1545
b0ca2a21 1546 /* Tx Check */
380af9e3 1547 if (intr_status & cd->tx_check) {
3719109d
SS		 1548 /* Clear Tx interrupts */
1549 sh_eth_write(ndev, intr_status & cd->tx_check, EESR);
1550
86a74ff2
NI		 1551 sh_eth_txfree(ndev);
1552 netif_wake_queue(ndev);
1553 }
1554
3719109d
SS		 1555 if (intr_status & cd->eesr_err_check) {
1556 /* Clear error interrupts */
1557 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR);
1558
86a74ff2 1559 sh_eth_error(ndev, intr_status);
3719109d 1560 }
86a74ff2 1561
0e0fde3c 1562other_irq:
86a74ff2
NI		 1563 spin_unlock(&mdp->lock);
1564
0e0fde3c 1565 return ret;
86a74ff2
NI		 1566}
1567
3719109d
SS		 1568static int sh_eth_poll(struct napi_struct *napi, int budget)
1569{
1570 struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private,
1571 napi);
1572 struct net_device *ndev = napi->dev;
1573 int quota = budget;
1574 unsigned long intr_status;
1575
1576 for (;;) {
1577 intr_status = sh_eth_read(ndev, EESR);
1578 if (!(intr_status & EESR_RX_CHECK))
1579 break;
1580 /* Clear Rx interrupts */
1581 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR);
1582
1583 if (sh_eth_rx(ndev, intr_status, &quota))
1584 goto out;
1585 }
1586
1587 napi_complete(napi);
1588
1589 /* Reenable Rx interrupts */
1590 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1591out:
1592 return budget - quota;
1593}
1594
86a74ff2
NI		 1595/* PHY state control function */
1596static void sh_eth_adjust_link(struct net_device *ndev)
1597{
1598 struct sh_eth_private *mdp = netdev_priv(ndev);
1599 struct phy_device *phydev = mdp->phydev;
86a74ff2
NI		 1600 int new_state = 0;
1601
3340d2aa 1602 if (phydev->link) {
86a74ff2
NI		 1603 if (phydev->duplex != mdp->duplex) {
1604 new_state = 1;
1605 mdp->duplex = phydev->duplex;
380af9e3
YS		 1606 if (mdp->cd->set_duplex)
1607 mdp->cd->set_duplex(ndev);
86a74ff2
NI		 1608 }
1609
1610 if (phydev->speed != mdp->speed) {
1611 new_state = 1;
1612 mdp->speed = phydev->speed;
380af9e3
YS		 1613 if (mdp->cd->set_rate)
1614 mdp->cd->set_rate(ndev);
86a74ff2 1615 }
3340d2aa 1616 if (!mdp->link) {
91a56152
YS		 1617 sh_eth_write(ndev,
1618 (sh_eth_read(ndev, ECMR) & ~ECMR_TXF), ECMR);
86a74ff2
NI		 1619 new_state = 1;
1620 mdp->link = phydev->link;
1e1b812b
SS		 1621 if (mdp->cd->no_psr || mdp->no_ether_link)
1622 sh_eth_rcv_snd_enable(ndev);
86a74ff2
NI		 1623 }
1624 } else if (mdp->link) {
1625 new_state = 1;
3340d2aa 1626 mdp->link = 0;
86a74ff2
NI		 1627 mdp->speed = 0;
1628 mdp->duplex = -1;
1e1b812b
SS		 1629 if (mdp->cd->no_psr || mdp->no_ether_link)
1630 sh_eth_rcv_snd_disable(ndev);
86a74ff2
NI		 1631 }
1632
dc19e4e5 1633 if (new_state && netif_msg_link(mdp))
86a74ff2
NI		 1634 phy_print_status(phydev);
1635}
1636
1637/* PHY init function */
1638static int sh_eth_phy_init(struct net_device *ndev)
1639{
1640 struct sh_eth_private *mdp = netdev_priv(ndev);
0a372eb9 1641 char phy_id[MII_BUS_ID_SIZE + 3];
86a74ff2
NI		 1642 struct phy_device *phydev = NULL;
1643
fb28ad35 1644 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
86a74ff2
NI		 1645 mdp->mii_bus->id , mdp->phy_id);
1646
3340d2aa 1647 mdp->link = 0;
86a74ff2
NI		 1648 mdp->speed = 0;
1649 mdp->duplex = -1;
1650
1651 /* Try connect to PHY */
c061b18d 1652 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
f9a8f83b 1653 mdp->phy_interface);
86a74ff2
NI		 1654 if (IS_ERR(phydev)) {
1655 dev_err(&ndev->dev, "phy_connect failed\n");
1656 return PTR_ERR(phydev);
1657 }
380af9e3 1658
86a74ff2 1659 dev_info(&ndev->dev, "attached phy %i to driver %s\n",
380af9e3 1660 phydev->addr, phydev->drv->name);
86a74ff2
NI		 1661
1662 mdp->phydev = phydev;
1663
1664 return 0;
1665}
1666
1667/* PHY control start function */
1668static int sh_eth_phy_start(struct net_device *ndev)
1669{
1670 struct sh_eth_private *mdp = netdev_priv(ndev);
1671 int ret;
1672
1673 ret = sh_eth_phy_init(ndev);
1674 if (ret)
1675 return ret;
1676
1677 /* reset phy - this also wakes it from PDOWN */
1678 phy_write(mdp->phydev, MII_BMCR, BMCR_RESET);
1679 phy_start(mdp->phydev);
1680
1681 return 0;
1682}
1683
dc19e4e5
NI		 1684static int sh_eth_get_settings(struct net_device *ndev,
1685 struct ethtool_cmd *ecmd)
1686{
1687 struct sh_eth_private *mdp = netdev_priv(ndev);
1688 unsigned long flags;
1689 int ret;
1690
1691 spin_lock_irqsave(&mdp->lock, flags);
1692 ret = phy_ethtool_gset(mdp->phydev, ecmd);
1693 spin_unlock_irqrestore(&mdp->lock, flags);
1694
1695 return ret;
1696}
1697
1698static int sh_eth_set_settings(struct net_device *ndev,
1699 struct ethtool_cmd *ecmd)
1700{
1701 struct sh_eth_private *mdp = netdev_priv(ndev);
1702 unsigned long flags;
1703 int ret;
dc19e4e5
NI		 1704
1705 spin_lock_irqsave(&mdp->lock, flags);
1706
1707 /* disable tx and rx */
4a55530f 1708 sh_eth_rcv_snd_disable(ndev);
dc19e4e5
NI		 1709
1710 ret = phy_ethtool_sset(mdp->phydev, ecmd);
1711 if (ret)
1712 goto error_exit;
1713
1714 if (ecmd->duplex == DUPLEX_FULL)
1715 mdp->duplex = 1;
1716 else
1717 mdp->duplex = 0;
1718
1719 if (mdp->cd->set_duplex)
1720 mdp->cd->set_duplex(ndev);
1721
1722error_exit:
1723 mdelay(1);
1724
1725 /* enable tx and rx */
4a55530f 1726 sh_eth_rcv_snd_enable(ndev);
dc19e4e5
NI		 1727
1728 spin_unlock_irqrestore(&mdp->lock, flags);
1729
1730 return ret;
1731}
1732
1733static int sh_eth_nway_reset(struct net_device *ndev)
1734{
1735 struct sh_eth_private *mdp = netdev_priv(ndev);
1736 unsigned long flags;
1737 int ret;
1738
1739 spin_lock_irqsave(&mdp->lock, flags);
1740 ret = phy_start_aneg(mdp->phydev);
1741 spin_unlock_irqrestore(&mdp->lock, flags);
1742
1743 return ret;
1744}
1745
1746static u32 sh_eth_get_msglevel(struct net_device *ndev)
1747{
1748 struct sh_eth_private *mdp = netdev_priv(ndev);
1749 return mdp->msg_enable;
1750}
1751
1752static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
1753{
1754 struct sh_eth_private *mdp = netdev_priv(ndev);
1755 mdp->msg_enable = value;
1756}
1757
1758static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
1759 "rx_current", "tx_current",
1760 "rx_dirty", "tx_dirty",
1761};
1762#define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats)
1763
1764static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
1765{
1766 switch (sset) {
1767 case ETH_SS_STATS:
1768 return SH_ETH_STATS_LEN;
1769 default:
1770 return -EOPNOTSUPP;
1771 }
1772}
1773
1774static void sh_eth_get_ethtool_stats(struct net_device *ndev,
1775 struct ethtool_stats *stats, u64 *data)
1776{
1777 struct sh_eth_private *mdp = netdev_priv(ndev);
1778 int i = 0;
1779
1780 /* device-specific stats */
1781 data[i++] = mdp->cur_rx;
1782 data[i++] = mdp->cur_tx;
1783 data[i++] = mdp->dirty_rx;
1784 data[i++] = mdp->dirty_tx;
1785}
1786
1787static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1788{
1789 switch (stringset) {
1790 case ETH_SS_STATS:
1791 memcpy(data, *sh_eth_gstrings_stats,
1792 sizeof(sh_eth_gstrings_stats));
1793 break;
1794 }
1795}
1796
525b8075
YS		 1797static void sh_eth_get_ringparam(struct net_device *ndev,
1798 struct ethtool_ringparam *ring)
1799{
1800 struct sh_eth_private *mdp = netdev_priv(ndev);
1801
1802 ring->rx_max_pending = RX_RING_MAX;
1803 ring->tx_max_pending = TX_RING_MAX;
1804 ring->rx_pending = mdp->num_rx_ring;
1805 ring->tx_pending = mdp->num_tx_ring;
1806}
1807
1808static int sh_eth_set_ringparam(struct net_device *ndev,
1809 struct ethtool_ringparam *ring)
1810{
1811 struct sh_eth_private *mdp = netdev_priv(ndev);
1812 int ret;
1813
1814 if (ring->tx_pending > TX_RING_MAX ||
1815 ring->rx_pending > RX_RING_MAX ||
1816 ring->tx_pending < TX_RING_MIN ||
1817 ring->rx_pending < RX_RING_MIN)
1818 return -EINVAL;
1819 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
1820 return -EINVAL;
1821
1822 if (netif_running(ndev)) {
1823 netif_tx_disable(ndev);
1824 /* Disable interrupts by clearing the interrupt mask. */
1825 sh_eth_write(ndev, 0x0000, EESIPR);
1826 /* Stop the chip's Tx and Rx processes. */
1827 sh_eth_write(ndev, 0, EDTRR);
1828 sh_eth_write(ndev, 0, EDRRR);
1829 synchronize_irq(ndev->irq);
1830 }
1831
1832 /* Free all the skbuffs in the Rx queue. */
1833 sh_eth_ring_free(ndev);
1834 /* Free DMA buffer */
1835 sh_eth_free_dma_buffer(mdp);
1836
1837 /* Set new parameters */
1838 mdp->num_rx_ring = ring->rx_pending;
1839 mdp->num_tx_ring = ring->tx_pending;
1840
1841 ret = sh_eth_ring_init(ndev);
1842 if (ret < 0) {
1843 dev_err(&ndev->dev, "%s: sh_eth_ring_init failed.\n", __func__);
1844 return ret;
1845 }
1846 ret = sh_eth_dev_init(ndev, false);
1847 if (ret < 0) {
1848 dev_err(&ndev->dev, "%s: sh_eth_dev_init failed.\n", __func__);
1849 return ret;
1850 }
1851
1852 if (netif_running(ndev)) {
1853 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1854 /* Setting the Rx mode will start the Rx process. */
1855 sh_eth_write(ndev, EDRRR_R, EDRRR);
1856 netif_wake_queue(ndev);
1857 }
1858
1859 return 0;
1860}
1861
9b07be4b 1862static const struct ethtool_ops sh_eth_ethtool_ops = {
dc19e4e5
NI		 1863 .get_settings = sh_eth_get_settings,
1864 .set_settings = sh_eth_set_settings,
9b07be4b 1865 .nway_reset = sh_eth_nway_reset,
dc19e4e5
NI		 1866 .get_msglevel = sh_eth_get_msglevel,
1867 .set_msglevel = sh_eth_set_msglevel,
9b07be4b 1868 .get_link = ethtool_op_get_link,
dc19e4e5
NI		 1869 .get_strings = sh_eth_get_strings,
1870 .get_ethtool_stats = sh_eth_get_ethtool_stats,
1871 .get_sset_count = sh_eth_get_sset_count,
525b8075
YS		 1872 .get_ringparam = sh_eth_get_ringparam,
1873 .set_ringparam = sh_eth_set_ringparam,
dc19e4e5
NI		 1874};
1875
86a74ff2
NI		 1876/* network device open function */
1877static int sh_eth_open(struct net_device *ndev)
1878{
1879 int ret = 0;
1880 struct sh_eth_private *mdp = netdev_priv(ndev);
1881
bcd5149d
MD		 1882 pm_runtime_get_sync(&mdp->pdev->dev);
1883
a0607fd3 1884 ret = request_irq(ndev->irq, sh_eth_interrupt,
5b3dfd13 1885 mdp->cd->irq_flags, ndev->name, ndev);
86a74ff2 1886 if (ret) {
380af9e3 1887 dev_err(&ndev->dev, "Can not assign IRQ number\n");
86a74ff2
NI		 1888 return ret;
1889 }
1890
1891 /* Descriptor set */
1892 ret = sh_eth_ring_init(ndev);
1893 if (ret)
1894 goto out_free_irq;
1895
1896 /* device init */
525b8075 1897 ret = sh_eth_dev_init(ndev, true);
86a74ff2
NI		 1898 if (ret)
1899 goto out_free_irq;
1900
1901 /* PHY control start*/
1902 ret = sh_eth_phy_start(ndev);
1903 if (ret)
1904 goto out_free_irq;
1905
3719109d
SS		 1906 napi_enable(&mdp->napi);
1907
86a74ff2
NI		 1908 return ret;
1909
1910out_free_irq:
1911 free_irq(ndev->irq, ndev);
bcd5149d 1912 pm_runtime_put_sync(&mdp->pdev->dev);
86a74ff2
NI		 1913 return ret;
1914}
1915
1916/* Timeout function */
1917static void sh_eth_tx_timeout(struct net_device *ndev)
1918{
1919 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 1920 struct sh_eth_rxdesc *rxdesc;
1921 int i;
1922
1923 netif_stop_queue(ndev);
1924
dc19e4e5
NI		 1925 if (netif_msg_timer(mdp))
1926 dev_err(&ndev->dev, "%s: transmit timed out, status %8.8x,"
4a55530f 1927 " resetting...\n", ndev->name, (int)sh_eth_read(ndev, EESR));
86a74ff2
NI		 1928
1929 /* tx_errors count up */
bb7d92e3 1930 ndev->stats.tx_errors++;
86a74ff2 1931
86a74ff2 1932 /* Free all the skbuffs in the Rx queue. */
525b8075 1933 for (i = 0; i < mdp->num_rx_ring; i++) {
86a74ff2
NI		 1934 rxdesc = &mdp->rx_ring[i];
1935 rxdesc->status = 0;
1936 rxdesc->addr = 0xBADF00D0;
1937 if (mdp->rx_skbuff[i])
1938 dev_kfree_skb(mdp->rx_skbuff[i]);
1939 mdp->rx_skbuff[i] = NULL;
1940 }
525b8075 1941 for (i = 0; i < mdp->num_tx_ring; i++) {
86a74ff2
NI		 1942 if (mdp->tx_skbuff[i])
1943 dev_kfree_skb(mdp->tx_skbuff[i]);
1944 mdp->tx_skbuff[i] = NULL;
1945 }
1946
1947 /* device init */
525b8075 1948 sh_eth_dev_init(ndev, true);
86a74ff2
NI		 1949}
1950
1951/* Packet transmit function */
1952static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1953{
1954 struct sh_eth_private *mdp = netdev_priv(ndev);
1955 struct sh_eth_txdesc *txdesc;
1956 u32 entry;
fb5e2f9b 1957 unsigned long flags;
86a74ff2
NI		 1958
1959 spin_lock_irqsave(&mdp->lock, flags);
525b8075 1960 if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
86a74ff2 1961 if (!sh_eth_txfree(ndev)) {
dc19e4e5
NI		 1962 if (netif_msg_tx_queued(mdp))
1963 dev_warn(&ndev->dev, "TxFD exhausted.\n");
86a74ff2
NI		 1964 netif_stop_queue(ndev);
1965 spin_unlock_irqrestore(&mdp->lock, flags);
5b548140 1966 return NETDEV_TX_BUSY;
86a74ff2
NI		 1967 }
1968 }
1969 spin_unlock_irqrestore(&mdp->lock, flags);
1970
525b8075 1971 entry = mdp->cur_tx % mdp->num_tx_ring;
86a74ff2
NI		 1972 mdp->tx_skbuff[entry] = skb;
1973 txdesc = &mdp->tx_ring[entry];
86a74ff2 1974 /* soft swap. */
380af9e3
YS		 1975 if (!mdp->cd->hw_swap)
1976 sh_eth_soft_swap(phys_to_virt(ALIGN(txdesc->addr, 4)),
1977 skb->len + 2);
31fcb99d
YS		 1978 txdesc->addr = dma_map_single(&ndev->dev, skb->data, skb->len,
1979 DMA_TO_DEVICE);
86a74ff2
NI		 1980 if (skb->len < ETHERSMALL)
1981 txdesc->buffer_length = ETHERSMALL;
1982 else
1983 txdesc->buffer_length = skb->len;
1984
525b8075 1985 if (entry >= mdp->num_tx_ring - 1)
71557a37 1986 txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE);
86a74ff2 1987 else
71557a37 1988 txdesc->status |= cpu_to_edmac(mdp, TD_TACT);
86a74ff2
NI		 1989
1990 mdp->cur_tx++;
1991
c5ed5368
YS		 1992 if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
1993 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
b0ca2a21 1994
6ed10654 1995 return NETDEV_TX_OK;
86a74ff2
NI		 1996}
1997
1998/* device close function */
1999static int sh_eth_close(struct net_device *ndev)
2000{
2001 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2 2002
3719109d
SS		 2003 napi_disable(&mdp->napi);
2004
86a74ff2
NI		 2005 netif_stop_queue(ndev);
2006
2007 /* Disable interrupts by clearing the interrupt mask. */
4a55530f 2008 sh_eth_write(ndev, 0x0000, EESIPR);
86a74ff2
NI		 2009
2010 /* Stop the chip's Tx and Rx processes. */
4a55530f
YS		 2011 sh_eth_write(ndev, 0, EDTRR);
2012 sh_eth_write(ndev, 0, EDRRR);
86a74ff2
NI		 2013
2014 /* PHY Disconnect */
2015 if (mdp->phydev) {
2016 phy_stop(mdp->phydev);
2017 phy_disconnect(mdp->phydev);
2018 }
2019
2020 free_irq(ndev->irq, ndev);
2021
86a74ff2
NI		 2022 /* Free all the skbuffs in the Rx queue. */
2023 sh_eth_ring_free(ndev);
2024
2025 /* free DMA buffer */
91c77550 2026 sh_eth_free_dma_buffer(mdp);
86a74ff2 2027
bcd5149d
MD		 2028 pm_runtime_put_sync(&mdp->pdev->dev);
2029
86a74ff2
NI		 2030 return 0;
2031}
2032
2033static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
2034{
2035 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2 2036
bcd5149d
MD		 2037 pm_runtime_get_sync(&mdp->pdev->dev);
2038
bb7d92e3 2039 ndev->stats.tx_dropped += sh_eth_read(ndev, TROCR);
4a55530f 2040 sh_eth_write(ndev, 0, TROCR); /* (write clear) */
bb7d92e3 2041 ndev->stats.collisions += sh_eth_read(ndev, CDCR);
4a55530f 2042 sh_eth_write(ndev, 0, CDCR); /* (write clear) */
bb7d92e3 2043 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, LCCR);
4a55530f 2044 sh_eth_write(ndev, 0, LCCR); /* (write clear) */
c5ed5368 2045 if (sh_eth_is_gether(mdp)) {
bb7d92e3 2046 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CERCR);
c5ed5368 2047 sh_eth_write(ndev, 0, CERCR); /* (write clear) */
bb7d92e3 2048 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CEECR);
c5ed5368
YS		 2049 sh_eth_write(ndev, 0, CEECR); /* (write clear) */
2050 } else {
bb7d92e3 2051 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CNDCR);
c5ed5368
YS		 2052 sh_eth_write(ndev, 0, CNDCR); /* (write clear) */
2053 }
bcd5149d
MD		 2054 pm_runtime_put_sync(&mdp->pdev->dev);
2055
bb7d92e3 2056 return &ndev->stats;
86a74ff2
NI		 2057}
2058
bb7d92e3 2059/* ioctl to device function */
86a74ff2
NI		 2060static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq,
2061 int cmd)
2062{
2063 struct sh_eth_private *mdp = netdev_priv(ndev);
2064 struct phy_device *phydev = mdp->phydev;
2065
2066 if (!netif_running(ndev))
2067 return -EINVAL;
2068
2069 if (!phydev)
2070 return -ENODEV;
2071
28b04113 2072 return phy_mii_ioctl(phydev, rq, cmd);
86a74ff2
NI		 2073}
2074
6743fe6d
YS		 2075/* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
2076static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp,
2077 int entry)
2078{
2079 return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4);
2080}
2081
2082static u32 sh_eth_tsu_get_post_mask(int entry)
2083{
2084 return 0x0f << (28 - ((entry % 8) * 4));
2085}
2086
2087static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
2088{
2089 return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
2090}
2091
2092static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
2093 int entry)
2094{
2095 struct sh_eth_private *mdp = netdev_priv(ndev);
2096 u32 tmp;
2097 void *reg_offset;
2098
2099 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2100 tmp = ioread32(reg_offset);
2101 iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset);
2102}
2103
2104static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
2105 int entry)
2106{
2107 struct sh_eth_private *mdp = netdev_priv(ndev);
2108 u32 post_mask, ref_mask, tmp;
2109 void *reg_offset;
2110
2111 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2112 post_mask = sh_eth_tsu_get_post_mask(entry);
2113 ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
2114
2115 tmp = ioread32(reg_offset);
2116 iowrite32(tmp & ~post_mask, reg_offset);
2117
2118 /* If other port enables, the function returns "true" */
2119 return tmp & ref_mask;
2120}
2121
2122static int sh_eth_tsu_busy(struct net_device *ndev)
2123{
2124 int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
2125 struct sh_eth_private *mdp = netdev_priv(ndev);
2126
2127 while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
2128 udelay(10);
2129 timeout--;
2130 if (timeout <= 0) {
2131 dev_err(&ndev->dev, "%s: timeout\n", __func__);
2132 return -ETIMEDOUT;
2133 }
2134 }
2135
2136 return 0;
2137}
2138
2139static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg,
2140 const u8 *addr)
2141{
2142 u32 val;
2143
2144 val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
2145 iowrite32(val, reg);
2146 if (sh_eth_tsu_busy(ndev) < 0)
2147 return -EBUSY;
2148
2149 val = addr[4] << 8 | addr[5];
2150 iowrite32(val, reg + 4);
2151 if (sh_eth_tsu_busy(ndev) < 0)
2152 return -EBUSY;
2153
2154 return 0;
2155}
2156
2157static void sh_eth_tsu_read_entry(void *reg, u8 *addr)
2158{
2159 u32 val;
2160
2161 val = ioread32(reg);
2162 addr[0] = (val >> 24) & 0xff;
2163 addr[1] = (val >> 16) & 0xff;
2164 addr[2] = (val >> 8) & 0xff;
2165 addr[3] = val & 0xff;
2166 val = ioread32(reg + 4);
2167 addr[4] = (val >> 8) & 0xff;
2168 addr[5] = val & 0xff;
2169}
2170
2171
2172static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
2173{
2174 struct sh_eth_private *mdp = netdev_priv(ndev);
2175 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2176 int i;
2177 u8 c_addr[ETH_ALEN];
2178
2179 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2180 sh_eth_tsu_read_entry(reg_offset, c_addr);
2181 if (memcmp(addr, c_addr, ETH_ALEN) == 0)
2182 return i;
2183 }
2184
2185 return -ENOENT;
2186}
2187
2188static int sh_eth_tsu_find_empty(struct net_device *ndev)
2189{
2190 u8 blank[ETH_ALEN];
2191 int entry;
2192
2193 memset(blank, 0, sizeof(blank));
2194 entry = sh_eth_tsu_find_entry(ndev, blank);
2195 return (entry < 0) ? -ENOMEM : entry;
2196}
2197
2198static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
2199 int entry)
2200{
2201 struct sh_eth_private *mdp = netdev_priv(ndev);
2202 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2203 int ret;
2204 u8 blank[ETH_ALEN];
2205
2206 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
2207 ~(1 << (31 - entry)), TSU_TEN);
2208
2209 memset(blank, 0, sizeof(blank));
2210 ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
2211 if (ret < 0)
2212 return ret;
2213 return 0;
2214}
2215
2216static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
2217{
2218 struct sh_eth_private *mdp = netdev_priv(ndev);
2219 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2220 int i, ret;
2221
2222 if (!mdp->cd->tsu)
2223 return 0;
2224
2225 i = sh_eth_tsu_find_entry(ndev, addr);
2226 if (i < 0) {
2227 /* No entry found, create one */
2228 i = sh_eth_tsu_find_empty(ndev);
2229 if (i < 0)
2230 return -ENOMEM;
2231 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
2232 if (ret < 0)
2233 return ret;
2234
2235 /* Enable the entry */
2236 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
2237 (1 << (31 - i)), TSU_TEN);
2238 }
2239
2240 /* Entry found or created, enable POST */
2241 sh_eth_tsu_enable_cam_entry_post(ndev, i);
2242
2243 return 0;
2244}
2245
2246static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
2247{
2248 struct sh_eth_private *mdp = netdev_priv(ndev);
2249 int i, ret;
2250
2251 if (!mdp->cd->tsu)
2252 return 0;
2253
2254 i = sh_eth_tsu_find_entry(ndev, addr);
2255 if (i) {
2256 /* Entry found */
2257 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2258 goto done;
2259
2260 /* Disable the entry if both ports was disabled */
2261 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2262 if (ret < 0)
2263 return ret;
2264 }
2265done:
2266 return 0;
2267}
2268
2269static int sh_eth_tsu_purge_all(struct net_device *ndev)
2270{
2271 struct sh_eth_private *mdp = netdev_priv(ndev);
2272 int i, ret;
2273
2274 if (unlikely(!mdp->cd->tsu))
2275 return 0;
2276
2277 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
2278 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2279 continue;
2280
2281 /* Disable the entry if both ports was disabled */
2282 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2283 if (ret < 0)
2284 return ret;
2285 }
2286
2287 return 0;
2288}
2289
2290static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
2291{
2292 struct sh_eth_private *mdp = netdev_priv(ndev);
2293 u8 addr[ETH_ALEN];
2294 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2295 int i;
2296
2297 if (unlikely(!mdp->cd->tsu))
2298 return;
2299
2300 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2301 sh_eth_tsu_read_entry(reg_offset, addr);
2302 if (is_multicast_ether_addr(addr))
2303 sh_eth_tsu_del_entry(ndev, addr);
2304 }
2305}
2306
86a74ff2
NI		 2307/* Multicast reception directions set */
2308static void sh_eth_set_multicast_list(struct net_device *ndev)
2309{
6743fe6d
YS		 2310 struct sh_eth_private *mdp = netdev_priv(ndev);
2311 u32 ecmr_bits;
2312 int mcast_all = 0;
2313 unsigned long flags;
2314
2315 spin_lock_irqsave(&mdp->lock, flags);
2316 /*
2317 * Initial condition is MCT = 1, PRM = 0.
2318 * Depending on ndev->flags, set PRM or clear MCT
2319 */
2320 ecmr_bits = (sh_eth_read(ndev, ECMR) & ~ECMR_PRM) | ECMR_MCT;
2321
2322 if (!(ndev->flags & IFF_MULTICAST)) {
2323 sh_eth_tsu_purge_mcast(ndev);
2324 mcast_all = 1;
2325 }
2326 if (ndev->flags & IFF_ALLMULTI) {
2327 sh_eth_tsu_purge_mcast(ndev);
2328 ecmr_bits &= ~ECMR_MCT;
2329 mcast_all = 1;
2330 }
2331
86a74ff2 2332 if (ndev->flags & IFF_PROMISC) {
6743fe6d
YS		 2333 sh_eth_tsu_purge_all(ndev);
2334 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2335 } else if (mdp->cd->tsu) {
2336 struct netdev_hw_addr *ha;
2337 netdev_for_each_mc_addr(ha, ndev) {
2338 if (mcast_all && is_multicast_ether_addr(ha->addr))
2339 continue;
2340
2341 if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2342 if (!mcast_all) {
2343 sh_eth_tsu_purge_mcast(ndev);
2344 ecmr_bits &= ~ECMR_MCT;
2345 mcast_all = 1;
2346 }
2347 }
2348 }
86a74ff2
NI		 2349 } else {
2350 /* Normal, unicast/broadcast-only mode. */
6743fe6d 2351 ecmr_bits = (ecmr_bits & ~ECMR_PRM) | ECMR_MCT;
86a74ff2 2352 }
6743fe6d
YS		 2353
2354 /* update the ethernet mode */
2355 sh_eth_write(ndev, ecmr_bits, ECMR);
2356
2357 spin_unlock_irqrestore(&mdp->lock, flags);
86a74ff2 2358}
71cc7c37
YS		 2359
2360static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2361{
2362 if (!mdp->port)
2363 return TSU_VTAG0;
2364 else
2365 return TSU_VTAG1;
2366}
2367
80d5c368
PM		 2368static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
2369 __be16 proto, u16 vid)
71cc7c37
YS		 2370{
2371 struct sh_eth_private *mdp = netdev_priv(ndev);
2372 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2373
2374 if (unlikely(!mdp->cd->tsu))
2375 return -EPERM;
2376
2377 /* No filtering if vid = 0 */
2378 if (!vid)
2379 return 0;
2380
2381 mdp->vlan_num_ids++;
2382
2383 /*
2384 * The controller has one VLAN tag HW filter. So, if the filter is
2385 * already enabled, the driver disables it and the filte
2386 */
2387 if (mdp->vlan_num_ids > 1) {
2388 /* disable VLAN filter */
2389 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2390 return 0;
2391 }
2392
2393 sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
2394 vtag_reg_index);
2395
2396 return 0;
2397}
2398
80d5c368
PM		 2399static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
2400 __be16 proto, u16 vid)
71cc7c37
YS		 2401{
2402 struct sh_eth_private *mdp = netdev_priv(ndev);
2403 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2404
2405 if (unlikely(!mdp->cd->tsu))
2406 return -EPERM;
2407
2408 /* No filtering if vid = 0 */
2409 if (!vid)
2410 return 0;
2411
2412 mdp->vlan_num_ids--;
2413 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2414
2415 return 0;
2416}
86a74ff2
NI		 2417
2418/* SuperH's TSU register init function */
4a55530f 2419static void sh_eth_tsu_init(struct sh_eth_private *mdp)
86a74ff2 2420{
4a55530f
YS		 2421 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */
2422 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */
2423 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */
2424 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
2425 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
2426 sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
2427 sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
2428 sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
2429 sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
2430 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
c5ed5368
YS		 2431 if (sh_eth_is_gether(mdp)) {
2432 sh_eth_tsu_write(mdp, 0, TSU_QTAG0); /* Disable QTAG(0->1) */
2433 sh_eth_tsu_write(mdp, 0, TSU_QTAG1); /* Disable QTAG(1->0) */
2434 } else {
2435 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */
2436 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */
2437 }
4a55530f
YS		 2438 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */
2439 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */
2440 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2441 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */
2442 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */
2443 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */
2444 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */
86a74ff2
NI		 2445}
2446
2447/* MDIO bus release function */
2448static int sh_mdio_release(struct net_device *ndev)
2449{
2450 struct mii_bus *bus = dev_get_drvdata(&ndev->dev);
2451
2452 /* unregister mdio bus */
2453 mdiobus_unregister(bus);
2454
2455 /* remove mdio bus info from net_device */
2456 dev_set_drvdata(&ndev->dev, NULL);
2457
2458 /* free bitbang info */
2459 free_mdio_bitbang(bus);
2460
2461 return 0;
2462}
2463
2464/* MDIO bus init function */
b3017e6a
YS		 2465static int sh_mdio_init(struct net_device *ndev, int id,
2466 struct sh_eth_plat_data *pd)
86a74ff2
NI		 2467{
2468 int ret, i;
2469 struct bb_info *bitbang;
2470 struct sh_eth_private *mdp = netdev_priv(ndev);
2471
2472 /* create bit control struct for PHY */
d5e07e69
SS		 2473 bitbang = devm_kzalloc(&ndev->dev, sizeof(struct bb_info),
2474 GFP_KERNEL);
86a74ff2
NI		 2475 if (!bitbang) {
2476 ret = -ENOMEM;
2477 goto out;
2478 }
2479
2480 /* bitbang init */
ae70644d 2481 bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
b3017e6a 2482 bitbang->set_gate = pd->set_mdio_gate;
dfed5e7f
SS		 2483 bitbang->mdi_msk = PIR_MDI;
2484 bitbang->mdo_msk = PIR_MDO;
2485 bitbang->mmd_msk = PIR_MMD;
2486 bitbang->mdc_msk = PIR_MDC;
86a74ff2
NI		 2487 bitbang->ctrl.ops = &bb_ops;
2488
c2e07b3a 2489 /* MII controller setting */
86a74ff2
NI		 2490 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
2491 if (!mdp->mii_bus) {
2492 ret = -ENOMEM;
d5e07e69 2493 goto out;
86a74ff2
NI		 2494 }
2495
2496 /* Hook up MII support for ethtool */
2497 mdp->mii_bus->name = "sh_mii";
18ee49dd 2498 mdp->mii_bus->parent = &ndev->dev;
5278fb54 2499 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
34aa6f14 2500 mdp->pdev->name, id);
86a74ff2
NI		 2501
2502 /* PHY IRQ */
d5e07e69
SS		 2503 mdp->mii_bus->irq = devm_kzalloc(&ndev->dev,
2504 sizeof(int) * PHY_MAX_ADDR,
2505 GFP_KERNEL);
86a74ff2
NI		 2506 if (!mdp->mii_bus->irq) {
2507 ret = -ENOMEM;
2508 goto out_free_bus;
2509 }
2510
2511 for (i = 0; i < PHY_MAX_ADDR; i++)
2512 mdp->mii_bus->irq[i] = PHY_POLL;
2513
8f6352f2 2514 /* register mdio bus */
86a74ff2
NI		 2515 ret = mdiobus_register(mdp->mii_bus);
2516 if (ret)
d5e07e69 2517 goto out_free_bus;
86a74ff2
NI		 2518
2519 dev_set_drvdata(&ndev->dev, mdp->mii_bus);
2520
2521 return 0;
2522
86a74ff2 2523out_free_bus:
298cf9be 2524 free_mdio_bitbang(mdp->mii_bus);
86a74ff2 2525
86a74ff2
NI		 2526out:
2527 return ret;
2528}
2529
4a55530f
YS		 2530static const u16 *sh_eth_get_register_offset(int register_type)
2531{
2532 const u16 *reg_offset = NULL;
2533
2534 switch (register_type) {
2535 case SH_ETH_REG_GIGABIT:
2536 reg_offset = sh_eth_offset_gigabit;
2537 break;
a3f109bd
SS		 2538 case SH_ETH_REG_FAST_RCAR:
2539 reg_offset = sh_eth_offset_fast_rcar;
2540 break;
4a55530f
YS		 2541 case SH_ETH_REG_FAST_SH4:
2542 reg_offset = sh_eth_offset_fast_sh4;
2543 break;
2544 case SH_ETH_REG_FAST_SH3_SH2:
2545 reg_offset = sh_eth_offset_fast_sh3_sh2;
2546 break;
2547 default:
14c3326a 2548 pr_err("Unknown register type (%d)\n", register_type);
4a55530f
YS		 2549 break;
2550 }
2551
2552 return reg_offset;
2553}
2554
8f728d79 2555static const struct net_device_ops sh_eth_netdev_ops = {
ebf84eaa
AB		 2556 .ndo_open = sh_eth_open,
2557 .ndo_stop = sh_eth_close,
2558 .ndo_start_xmit = sh_eth_start_xmit,
2559 .ndo_get_stats = sh_eth_get_stats,
ebf84eaa
AB		 2560 .ndo_tx_timeout = sh_eth_tx_timeout,
2561 .ndo_do_ioctl = sh_eth_do_ioctl,
2562 .ndo_validate_addr = eth_validate_addr,
2563 .ndo_set_mac_address = eth_mac_addr,
2564 .ndo_change_mtu = eth_change_mtu,
2565};
2566
8f728d79
SS		 2567static const struct net_device_ops sh_eth_netdev_ops_tsu = {
2568 .ndo_open = sh_eth_open,
2569 .ndo_stop = sh_eth_close,
2570 .ndo_start_xmit = sh_eth_start_xmit,
2571 .ndo_get_stats = sh_eth_get_stats,
2572 .ndo_set_rx_mode = sh_eth_set_multicast_list,
2573 .ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid,
2574 .ndo_vlan_rx_kill_vid = sh_eth_vlan_rx_kill_vid,
2575 .ndo_tx_timeout = sh_eth_tx_timeout,
2576 .ndo_do_ioctl = sh_eth_do_ioctl,
2577 .ndo_validate_addr = eth_validate_addr,
2578 .ndo_set_mac_address = eth_mac_addr,
2579 .ndo_change_mtu = eth_change_mtu,
2580};
2581
86a74ff2
NI		 2582static int sh_eth_drv_probe(struct platform_device *pdev)
2583{
9c38657c 2584 int ret, devno = 0;
86a74ff2
NI		 2585 struct resource *res;
2586 struct net_device *ndev = NULL;
ec0d7551 2587 struct sh_eth_private *mdp = NULL;
564044b0 2588 struct sh_eth_plat_data *pd = pdev->dev.platform_data;
afe391ad 2589 const struct platform_device_id *id = platform_get_device_id(pdev);
86a74ff2
NI		 2590
2591 /* get base addr */
2592 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2593 if (unlikely(res == NULL)) {
2594 dev_err(&pdev->dev, "invalid resource\n");
2595 ret = -EINVAL;
2596 goto out;
2597 }
2598
2599 ndev = alloc_etherdev(sizeof(struct sh_eth_private));
2600 if (!ndev) {
86a74ff2
NI		 2601 ret = -ENOMEM;
2602 goto out;
2603 }
2604
2605 /* The sh Ether-specific entries in the device structure. */
2606 ndev->base_addr = res->start;
2607 devno = pdev->id;
2608 if (devno < 0)
2609 devno = 0;
2610
2611 ndev->dma = -1;
cc3c080d 2612 ret = platform_get_irq(pdev, 0);
2613 if (ret < 0) {
86a74ff2
NI		 2614 ret = -ENODEV;
2615 goto out_release;
2616 }
cc3c080d 2617 ndev->irq = ret;
86a74ff2
NI		 2618
2619 SET_NETDEV_DEV(ndev, &pdev->dev);
2620
2621 /* Fill in the fields of the device structure with ethernet values. */
2622 ether_setup(ndev);
2623
2624 mdp = netdev_priv(ndev);
525b8075
YS		 2625 mdp->num_tx_ring = TX_RING_SIZE;
2626 mdp->num_rx_ring = RX_RING_SIZE;
d5e07e69
SS		 2627 mdp->addr = devm_ioremap_resource(&pdev->dev, res);
2628 if (IS_ERR(mdp->addr)) {
2629 ret = PTR_ERR(mdp->addr);
ae70644d
YS		 2630 goto out_release;
2631 }
2632
86a74ff2 2633 spin_lock_init(&mdp->lock);
bcd5149d
MD		 2634 mdp->pdev = pdev;
2635 pm_runtime_enable(&pdev->dev);
2636 pm_runtime_resume(&pdev->dev);
86a74ff2
NI		 2637
2638 /* get PHY ID */
71557a37 2639 mdp->phy_id = pd->phy;
e47c9052 2640 mdp->phy_interface = pd->phy_interface;
71557a37
YS		 2641 /* EDMAC endian */
2642 mdp->edmac_endian = pd->edmac_endian;
4923576b
YS		 2643 mdp->no_ether_link = pd->no_ether_link;
2644 mdp->ether_link_active_low = pd->ether_link_active_low;
4a55530f 2645 mdp->reg_offset = sh_eth_get_register_offset(pd->register_type);
86a74ff2 2646
380af9e3 2647 /* set cpu data */
589ebdef 2648 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data;
380af9e3
YS		 2649 sh_eth_set_default_cpu_data(mdp->cd);
2650
86a74ff2 2651 /* set function */
8f728d79
SS		 2652 if (mdp->cd->tsu)
2653 ndev->netdev_ops = &sh_eth_netdev_ops_tsu;
2654 else
2655 ndev->netdev_ops = &sh_eth_netdev_ops;
dc19e4e5 2656 SET_ETHTOOL_OPS(ndev, &sh_eth_ethtool_ops);
86a74ff2
NI		 2657 ndev->watchdog_timeo = TX_TIMEOUT;
2658
dc19e4e5
NI		 2659 /* debug message level */
2660 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
86a74ff2
NI		 2661
2662 /* read and set MAC address */
748031f9 2663 read_mac_address(ndev, pd->mac_addr);
ff6e7228
SS		 2664 if (!is_valid_ether_addr(ndev->dev_addr)) {
2665 dev_warn(&pdev->dev,
2666 "no valid MAC address supplied, using a random one.\n");
2667 eth_hw_addr_random(ndev);
2668 }
86a74ff2 2669
6ba88021
YS		 2670 /* ioremap the TSU registers */
2671 if (mdp->cd->tsu) {
2672 struct resource *rtsu;
2673 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
d5e07e69
SS		 2674 mdp->tsu_addr = devm_ioremap_resource(&pdev->dev, rtsu);
2675 if (IS_ERR(mdp->tsu_addr)) {
2676 ret = PTR_ERR(mdp->tsu_addr);
fc0c0900
SS		 2677 goto out_release;
2678 }
6743fe6d 2679 mdp->port = devno % 2;
f646968f 2680 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER;
6ba88021
YS		 2681 }
2682
150647fb
YS		 2683 /* initialize first or needed device */
2684 if (!devno || pd->needs_init) {
380af9e3
YS		 2685 if (mdp->cd->chip_reset)
2686 mdp->cd->chip_reset(ndev);
86a74ff2 2687
4986b996
YS		 2688 if (mdp->cd->tsu) {
2689 /* TSU init (Init only)*/
2690 sh_eth_tsu_init(mdp);
2691 }
86a74ff2
NI		 2692 }
2693
3719109d
SS		 2694 netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64);
2695
86a74ff2
NI		 2696 /* network device register */
2697 ret = register_netdev(ndev);
2698 if (ret)
3719109d 2699 goto out_napi_del;
86a74ff2
NI		 2700
2701 /* mdio bus init */
b3017e6a 2702 ret = sh_mdio_init(ndev, pdev->id, pd);
86a74ff2
NI		 2703 if (ret)
2704 goto out_unregister;
2705
25985edc 2706 /* print device information */
6cd9b49d
HS		 2707 pr_info("Base address at 0x%x, %pM, IRQ %d.\n",
2708 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
86a74ff2
NI		 2709
2710 platform_set_drvdata(pdev, ndev);
2711
2712 return ret;
2713
2714out_unregister:
2715 unregister_netdev(ndev);
2716
3719109d
SS		 2717out_napi_del:
2718 netif_napi_del(&mdp->napi);
2719
86a74ff2
NI		 2720out_release:
2721 /* net_dev free */
2722 if (ndev)
2723 free_netdev(ndev);
2724
2725out:
2726 return ret;
2727}
2728
2729static int sh_eth_drv_remove(struct platform_device *pdev)
2730{
2731 struct net_device *ndev = platform_get_drvdata(pdev);
3719109d 2732 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 2733
2734 sh_mdio_release(ndev);
2735 unregister_netdev(ndev);
3719109d 2736 netif_napi_del(&mdp->napi);
bcd5149d 2737 pm_runtime_disable(&pdev->dev);
86a74ff2 2738 free_netdev(ndev);
86a74ff2
NI		 2739
2740 return 0;
2741}
2742
540ad1b8 2743#ifdef CONFIG_PM
bcd5149d
MD		 2744static int sh_eth_runtime_nop(struct device *dev)
2745{
2746 /*
2747 * Runtime PM callback shared between ->runtime_suspend()
2748 * and ->runtime_resume(). Simply returns success.
2749 *
2750 * This driver re-initializes all registers after
2751 * pm_runtime_get_sync() anyway so there is no need
2752 * to save and restore registers here.
2753 */
2754 return 0;
2755}
2756
540ad1b8 2757static const struct dev_pm_ops sh_eth_dev_pm_ops = {
bcd5149d
MD		 2758 .runtime_suspend = sh_eth_runtime_nop,
2759 .runtime_resume = sh_eth_runtime_nop,
2760};
540ad1b8
NI		 2761#define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
2762#else
2763#define SH_ETH_PM_OPS NULL
2764#endif
bcd5149d 2765
afe391ad 2766static struct platform_device_id sh_eth_id_table[] = {
c18a79ab 2767 { "sh7619-ether", (kernel_ulong_t)&sh7619_data },
7bbe150d 2768 { "sh771x-ether", (kernel_ulong_t)&sh771x_data },
9c3beaab 2769 { "sh7724-ether", (kernel_ulong_t)&sh7724_data },
f5d12767 2770 { "sh7734-gether", (kernel_ulong_t)&sh7734_data },
24549e2a
SS		 2771 { "sh7757-ether", (kernel_ulong_t)&sh7757_data },
2772 { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga },
f5d12767 2773 { "sh7763-gether", (kernel_ulong_t)&sh7763_data },
e5c9b4cd 2774 { "r8a7740-gether", (kernel_ulong_t)&r8a7740_data },
589ebdef 2775 { "r8a777x-ether", (kernel_ulong_t)&r8a777x_data },
e18dbf7e 2776 { "r8a7790-ether", (kernel_ulong_t)&r8a7790_data },
afe391ad
SS		 2777 { }
2778};
2779MODULE_DEVICE_TABLE(platform, sh_eth_id_table);
2780
86a74ff2
NI		 2781static struct platform_driver sh_eth_driver = {
2782 .probe = sh_eth_drv_probe,
2783 .remove = sh_eth_drv_remove,
afe391ad 2784 .id_table = sh_eth_id_table,
86a74ff2
NI		 2785 .driver = {
2786 .name = CARDNAME,
540ad1b8 2787 .pm = SH_ETH_PM_OPS,
86a74ff2
NI		 2788 },
2789};
2790
db62f684 2791module_platform_driver(sh_eth_driver);
86a74ff2
NI		 2792
2793MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
2794MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
2795MODULE_LICENSE("GPL v2");
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