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vti: get rid of nf mark rule in prerouting
[mirror_ubuntu-zesty-kernel.git] / drivers / net / ethernet / renesas / sh_eth.c
CommitLineData
86a74ff2
NI		 1/*
2 * SuperH Ethernet device driver
3 *
f0e81fec 4 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu
a3f109bd
SS		 5 * Copyright (C) 2008-2013 Renesas Solutions Corp.
6 * Copyright (C) 2013 Cogent Embedded, Inc.
86a74ff2
NI		 7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 * You should have received a copy of the GNU General Public License along with
17 * this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * The full GNU General Public License is included in this distribution in
21 * the file called "COPYING".
22 */
23
86a74ff2 24#include <linux/init.h>
0654011d
YS		 25#include <linux/module.h>
26#include <linux/kernel.h>
27#include <linux/spinlock.h>
6a27cded 28#include <linux/interrupt.h>
86a74ff2
NI		 29#include <linux/dma-mapping.h>
30#include <linux/etherdevice.h>
31#include <linux/delay.h>
32#include <linux/platform_device.h>
33#include <linux/mdio-bitbang.h>
34#include <linux/netdevice.h>
35#include <linux/phy.h>
36#include <linux/cache.h>
37#include <linux/io.h>
bcd5149d 38#include <linux/pm_runtime.h>
5a0e3ad6 39#include <linux/slab.h>
dc19e4e5 40#include <linux/ethtool.h>
fdb37a7f 41#include <linux/if_vlan.h>
f0e81fec 42#include <linux/clk.h>
d4fa0e35 43#include <linux/sh_eth.h>
86a74ff2
NI		 44
45#include "sh_eth.h"
46
dc19e4e5
NI		 47#define SH_ETH_DEF_MSG_ENABLE \
48 (NETIF_MSG_LINK | \
49 NETIF_MSG_TIMER | \
50 NETIF_MSG_RX_ERR| \
51 NETIF_MSG_TX_ERR)
52
c0013f6f
SS		 53static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
54 [EDSR] = 0x0000,
55 [EDMR] = 0x0400,
56 [EDTRR] = 0x0408,
57 [EDRRR] = 0x0410,
58 [EESR] = 0x0428,
59 [EESIPR] = 0x0430,
60 [TDLAR] = 0x0010,
61 [TDFAR] = 0x0014,
62 [TDFXR] = 0x0018,
63 [TDFFR] = 0x001c,
64 [RDLAR] = 0x0030,
65 [RDFAR] = 0x0034,
66 [RDFXR] = 0x0038,
67 [RDFFR] = 0x003c,
68 [TRSCER] = 0x0438,
69 [RMFCR] = 0x0440,
70 [TFTR] = 0x0448,
71 [FDR] = 0x0450,
72 [RMCR] = 0x0458,
73 [RPADIR] = 0x0460,
74 [FCFTR] = 0x0468,
75 [CSMR] = 0x04E4,
76
77 [ECMR] = 0x0500,
78 [ECSR] = 0x0510,
79 [ECSIPR] = 0x0518,
80 [PIR] = 0x0520,
81 [PSR] = 0x0528,
82 [PIPR] = 0x052c,
83 [RFLR] = 0x0508,
84 [APR] = 0x0554,
85 [MPR] = 0x0558,
86 [PFTCR] = 0x055c,
87 [PFRCR] = 0x0560,
88 [TPAUSER] = 0x0564,
89 [GECMR] = 0x05b0,
90 [BCULR] = 0x05b4,
91 [MAHR] = 0x05c0,
92 [MALR] = 0x05c8,
93 [TROCR] = 0x0700,
94 [CDCR] = 0x0708,
95 [LCCR] = 0x0710,
96 [CEFCR] = 0x0740,
97 [FRECR] = 0x0748,
98 [TSFRCR] = 0x0750,
99 [TLFRCR] = 0x0758,
100 [RFCR] = 0x0760,
101 [CERCR] = 0x0768,
102 [CEECR] = 0x0770,
103 [MAFCR] = 0x0778,
104 [RMII_MII] = 0x0790,
105
106 [ARSTR] = 0x0000,
107 [TSU_CTRST] = 0x0004,
108 [TSU_FWEN0] = 0x0010,
109 [TSU_FWEN1] = 0x0014,
110 [TSU_FCM] = 0x0018,
111 [TSU_BSYSL0] = 0x0020,
112 [TSU_BSYSL1] = 0x0024,
113 [TSU_PRISL0] = 0x0028,
114 [TSU_PRISL1] = 0x002c,
115 [TSU_FWSL0] = 0x0030,
116 [TSU_FWSL1] = 0x0034,
117 [TSU_FWSLC] = 0x0038,
118 [TSU_QTAG0] = 0x0040,
119 [TSU_QTAG1] = 0x0044,
120 [TSU_FWSR] = 0x0050,
121 [TSU_FWINMK] = 0x0054,
122 [TSU_ADQT0] = 0x0048,
123 [TSU_ADQT1] = 0x004c,
124 [TSU_VTAG0] = 0x0058,
125 [TSU_VTAG1] = 0x005c,
126 [TSU_ADSBSY] = 0x0060,
127 [TSU_TEN] = 0x0064,
128 [TSU_POST1] = 0x0070,
129 [TSU_POST2] = 0x0074,
130 [TSU_POST3] = 0x0078,
131 [TSU_POST4] = 0x007c,
132 [TSU_ADRH0] = 0x0100,
133 [TSU_ADRL0] = 0x0104,
134 [TSU_ADRH31] = 0x01f8,
135 [TSU_ADRL31] = 0x01fc,
136
137 [TXNLCR0] = 0x0080,
138 [TXALCR0] = 0x0084,
139 [RXNLCR0] = 0x0088,
140 [RXALCR0] = 0x008c,
141 [FWNLCR0] = 0x0090,
142 [FWALCR0] = 0x0094,
143 [TXNLCR1] = 0x00a0,
144 [TXALCR1] = 0x00a0,
145 [RXNLCR1] = 0x00a8,
146 [RXALCR1] = 0x00ac,
147 [FWNLCR1] = 0x00b0,
148 [FWALCR1] = 0x00b4,
149};
150
a3f109bd
SS		 151static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
152 [ECMR] = 0x0300,
153 [RFLR] = 0x0308,
154 [ECSR] = 0x0310,
155 [ECSIPR] = 0x0318,
156 [PIR] = 0x0320,
157 [PSR] = 0x0328,
158 [RDMLR] = 0x0340,
159 [IPGR] = 0x0350,
160 [APR] = 0x0354,
161 [MPR] = 0x0358,
162 [RFCF] = 0x0360,
163 [TPAUSER] = 0x0364,
164 [TPAUSECR] = 0x0368,
165 [MAHR] = 0x03c0,
166 [MALR] = 0x03c8,
167 [TROCR] = 0x03d0,
168 [CDCR] = 0x03d4,
169 [LCCR] = 0x03d8,
170 [CNDCR] = 0x03dc,
171 [CEFCR] = 0x03e4,
172 [FRECR] = 0x03e8,
173 [TSFRCR] = 0x03ec,
174 [TLFRCR] = 0x03f0,
175 [RFCR] = 0x03f4,
176 [MAFCR] = 0x03f8,
177
178 [EDMR] = 0x0200,
179 [EDTRR] = 0x0208,
180 [EDRRR] = 0x0210,
181 [TDLAR] = 0x0218,
182 [RDLAR] = 0x0220,
183 [EESR] = 0x0228,
184 [EESIPR] = 0x0230,
185 [TRSCER] = 0x0238,
186 [RMFCR] = 0x0240,
187 [TFTR] = 0x0248,
188 [FDR] = 0x0250,
189 [RMCR] = 0x0258,
190 [TFUCR] = 0x0264,
191 [RFOCR] = 0x0268,
55754f19 192 [RMIIMODE] = 0x026c,
a3f109bd
SS		 193 [FCFTR] = 0x0270,
194 [TRIMD] = 0x027c,
195};
196
c0013f6f
SS		 197static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
198 [ECMR] = 0x0100,
199 [RFLR] = 0x0108,
200 [ECSR] = 0x0110,
201 [ECSIPR] = 0x0118,
202 [PIR] = 0x0120,
203 [PSR] = 0x0128,
204 [RDMLR] = 0x0140,
205 [IPGR] = 0x0150,
206 [APR] = 0x0154,
207 [MPR] = 0x0158,
208 [TPAUSER] = 0x0164,
209 [RFCF] = 0x0160,
210 [TPAUSECR] = 0x0168,
211 [BCFRR] = 0x016c,
212 [MAHR] = 0x01c0,
213 [MALR] = 0x01c8,
214 [TROCR] = 0x01d0,
215 [CDCR] = 0x01d4,
216 [LCCR] = 0x01d8,
217 [CNDCR] = 0x01dc,
218 [CEFCR] = 0x01e4,
219 [FRECR] = 0x01e8,
220 [TSFRCR] = 0x01ec,
221 [TLFRCR] = 0x01f0,
222 [RFCR] = 0x01f4,
223 [MAFCR] = 0x01f8,
224 [RTRATE] = 0x01fc,
225
226 [EDMR] = 0x0000,
227 [EDTRR] = 0x0008,
228 [EDRRR] = 0x0010,
229 [TDLAR] = 0x0018,
230 [RDLAR] = 0x0020,
231 [EESR] = 0x0028,
232 [EESIPR] = 0x0030,
233 [TRSCER] = 0x0038,
234 [RMFCR] = 0x0040,
235 [TFTR] = 0x0048,
236 [FDR] = 0x0050,
237 [RMCR] = 0x0058,
238 [TFUCR] = 0x0064,
239 [RFOCR] = 0x0068,
240 [FCFTR] = 0x0070,
241 [RPADIR] = 0x0078,
242 [TRIMD] = 0x007c,
243 [RBWAR] = 0x00c8,
244 [RDFAR] = 0x00cc,
245 [TBRAR] = 0x00d4,
246 [TDFAR] = 0x00d8,
247};
248
249static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
250 [ECMR] = 0x0160,
251 [ECSR] = 0x0164,
252 [ECSIPR] = 0x0168,
253 [PIR] = 0x016c,
254 [MAHR] = 0x0170,
255 [MALR] = 0x0174,
256 [RFLR] = 0x0178,
257 [PSR] = 0x017c,
258 [TROCR] = 0x0180,
259 [CDCR] = 0x0184,
260 [LCCR] = 0x0188,
261 [CNDCR] = 0x018c,
262 [CEFCR] = 0x0194,
263 [FRECR] = 0x0198,
264 [TSFRCR] = 0x019c,
265 [TLFRCR] = 0x01a0,
266 [RFCR] = 0x01a4,
267 [MAFCR] = 0x01a8,
268 [IPGR] = 0x01b4,
269 [APR] = 0x01b8,
270 [MPR] = 0x01bc,
271 [TPAUSER] = 0x01c4,
272 [BCFR] = 0x01cc,
273
274 [ARSTR] = 0x0000,
275 [TSU_CTRST] = 0x0004,
276 [TSU_FWEN0] = 0x0010,
277 [TSU_FWEN1] = 0x0014,
278 [TSU_FCM] = 0x0018,
279 [TSU_BSYSL0] = 0x0020,
280 [TSU_BSYSL1] = 0x0024,
281 [TSU_PRISL0] = 0x0028,
282 [TSU_PRISL1] = 0x002c,
283 [TSU_FWSL0] = 0x0030,
284 [TSU_FWSL1] = 0x0034,
285 [TSU_FWSLC] = 0x0038,
286 [TSU_QTAGM0] = 0x0040,
287 [TSU_QTAGM1] = 0x0044,
288 [TSU_ADQT0] = 0x0048,
289 [TSU_ADQT1] = 0x004c,
290 [TSU_FWSR] = 0x0050,
291 [TSU_FWINMK] = 0x0054,
292 [TSU_ADSBSY] = 0x0060,
293 [TSU_TEN] = 0x0064,
294 [TSU_POST1] = 0x0070,
295 [TSU_POST2] = 0x0074,
296 [TSU_POST3] = 0x0078,
297 [TSU_POST4] = 0x007c,
298
299 [TXNLCR0] = 0x0080,
300 [TXALCR0] = 0x0084,
301 [RXNLCR0] = 0x0088,
302 [RXALCR0] = 0x008c,
303 [FWNLCR0] = 0x0090,
304 [FWALCR0] = 0x0094,
305 [TXNLCR1] = 0x00a0,
306 [TXALCR1] = 0x00a0,
307 [RXNLCR1] = 0x00a8,
308 [RXALCR1] = 0x00ac,
309 [FWNLCR1] = 0x00b0,
310 [FWALCR1] = 0x00b4,
311
312 [TSU_ADRH0] = 0x0100,
313 [TSU_ADRL0] = 0x0104,
314 [TSU_ADRL31] = 0x01fc,
315};
316
dabdde9e
NI		 317static int sh_eth_is_gether(struct sh_eth_private *mdp)
318{
319 if (mdp->reg_offset == sh_eth_offset_gigabit)
320 return 1;
321 else
322 return 0;
323}
324
8e994402 325static void sh_eth_select_mii(struct net_device *ndev)
5e7a76be
NI		 326{
327 u32 value = 0x0;
328 struct sh_eth_private *mdp = netdev_priv(ndev);
329
330 switch (mdp->phy_interface) {
331 case PHY_INTERFACE_MODE_GMII:
332 value = 0x2;
333 break;
334 case PHY_INTERFACE_MODE_MII:
335 value = 0x1;
336 break;
337 case PHY_INTERFACE_MODE_RMII:
338 value = 0x0;
339 break;
340 default:
341 pr_warn("PHY interface mode was not setup. Set to MII.\n");
342 value = 0x1;
343 break;
344 }
345
346 sh_eth_write(ndev, value, RMII_MII);
347}
5e7a76be 348
8e994402 349static void sh_eth_set_duplex(struct net_device *ndev)
65ac8851
YS		 350{
351 struct sh_eth_private *mdp = netdev_priv(ndev);
65ac8851
YS		 352
353 if (mdp->duplex) /* Full */
4a55530f 354 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
65ac8851 355 else /* Half */
4a55530f 356 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
65ac8851
YS		 357}
358
04b0ed2a 359/* There is CPU dependent code */
589ebdef 360static void sh_eth_set_rate_r8a777x(struct net_device *ndev)
65ac8851
YS		 361{
362 struct sh_eth_private *mdp = netdev_priv(ndev);
d0418bb7 363
a3f109bd
SS		 364 switch (mdp->speed) {
365 case 10: /* 10BASE */
366 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_ELB, ECMR);
367 break;
368 case 100:/* 100BASE */
369 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_ELB, ECMR);
370 break;
371 default:
372 break;
373 }
374}
375
674853b2 376/* R8A7778/9 */
589ebdef 377static struct sh_eth_cpu_data r8a777x_data = {
a3f109bd 378 .set_duplex = sh_eth_set_duplex,
589ebdef 379 .set_rate = sh_eth_set_rate_r8a777x,
a3f109bd 380
a3153d8c
SS		 381 .register_type = SH_ETH_REG_FAST_RCAR,
382
a3f109bd
SS		 383 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
384 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
385 .eesipr_value = 0x01ff009f,
386
387 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
ca8c3585
SS		 388 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
389 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
390 EESR_ECI,
a3f109bd
SS		 391
392 .apr = 1,
393 .mpr = 1,
394 .tpauser = 1,
395 .hw_swap = 1,
396};
a3f109bd 397
e18dbf7e
SH		 398/* R8A7790 */
399static struct sh_eth_cpu_data r8a7790_data = {
400 .set_duplex = sh_eth_set_duplex,
401 .set_rate = sh_eth_set_rate_r8a777x,
402
a3153d8c
SS		 403 .register_type = SH_ETH_REG_FAST_RCAR,
404
e18dbf7e
SH		 405 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
406 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
407 .eesipr_value = 0x01ff009f,
408
409 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
ba361cb3
LP		 410 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
411 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
412 EESR_ECI,
e18dbf7e
SH		 413
414 .apr = 1,
415 .mpr = 1,
416 .tpauser = 1,
417 .hw_swap = 1,
418 .rmiimode = 1,
fd9af07c 419 .shift_rd0 = 1,
e18dbf7e
SH		 420};
421
9c3beaab 422static void sh_eth_set_rate_sh7724(struct net_device *ndev)
a3f109bd
SS		 423{
424 struct sh_eth_private *mdp = netdev_priv(ndev);
65ac8851
YS		 425
426 switch (mdp->speed) {
427 case 10: /* 10BASE */
a3f109bd 428 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_RTM, ECMR);
65ac8851
YS		 429 break;
430 case 100:/* 100BASE */
a3f109bd 431 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_RTM, ECMR);
65ac8851
YS		 432 break;
433 default:
434 break;
435 }
436}
437
438/* SH7724 */
9c3beaab 439static struct sh_eth_cpu_data sh7724_data = {
65ac8851 440 .set_duplex = sh_eth_set_duplex,
9c3beaab 441 .set_rate = sh_eth_set_rate_sh7724,
65ac8851 442
a3153d8c
SS		 443 .register_type = SH_ETH_REG_FAST_SH4,
444
65ac8851
YS		 445 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
446 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
a80c3de7 447 .eesipr_value = 0x01ff009f,
65ac8851
YS		 448
449 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
ca8c3585
SS		 450 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
451 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
452 EESR_ECI,
65ac8851
YS		 453
454 .apr = 1,
455 .mpr = 1,
456 .tpauser = 1,
457 .hw_swap = 1,
503914cf
MD		 458 .rpadir = 1,
459 .rpadir_value = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
65ac8851 460};
5cee1d37 461
24549e2a 462static void sh_eth_set_rate_sh7757(struct net_device *ndev)
f29a3d04
YS		 463{
464 struct sh_eth_private *mdp = netdev_priv(ndev);
f29a3d04
YS		 465
466 switch (mdp->speed) {
467 case 10: /* 10BASE */
4a55530f 468 sh_eth_write(ndev, 0, RTRATE);
f29a3d04
YS		 469 break;
470 case 100:/* 100BASE */
4a55530f 471 sh_eth_write(ndev, 1, RTRATE);
f29a3d04
YS		 472 break;
473 default:
474 break;
475 }
476}
477
478/* SH7757 */
24549e2a
SS		 479static struct sh_eth_cpu_data sh7757_data = {
480 .set_duplex = sh_eth_set_duplex,
481 .set_rate = sh_eth_set_rate_sh7757,
f29a3d04 482
a3153d8c
SS		 483 .register_type = SH_ETH_REG_FAST_SH4,
484
f29a3d04
YS		 485 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
486 .rmcr_value = 0x00000001,
487
488 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
ca8c3585
SS		 489 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
490 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
491 EESR_ECI,
f29a3d04 492
5b3dfd13 493 .irq_flags = IRQF_SHARED,
f29a3d04
YS		 494 .apr = 1,
495 .mpr = 1,
496 .tpauser = 1,
497 .hw_swap = 1,
498 .no_ade = 1,
2e98e797
YS		 499 .rpadir = 1,
500 .rpadir_value = 2 << 16,
f29a3d04 501};
65ac8851 502
e403d295 503#define SH_GIGA_ETH_BASE 0xfee00000UL
8fcd4961
YS		 504#define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
505#define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
506static void sh_eth_chip_reset_giga(struct net_device *ndev)
507{
508 int i;
509 unsigned long mahr[2], malr[2];
510
511 /* save MAHR and MALR */
512 for (i = 0; i < 2; i++) {
ae70644d
YS		 513 malr[i] = ioread32((void *)GIGA_MALR(i));
514 mahr[i] = ioread32((void *)GIGA_MAHR(i));
8fcd4961
YS		 515 }
516
517 /* reset device */
ae70644d 518 iowrite32(ARSTR_ARSTR, (void *)(SH_GIGA_ETH_BASE + 0x1800));
8fcd4961
YS		 519 mdelay(1);
520
521 /* restore MAHR and MALR */
522 for (i = 0; i < 2; i++) {
ae70644d
YS		 523 iowrite32(malr[i], (void *)GIGA_MALR(i));
524 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
8fcd4961
YS		 525 }
526}
527
8fcd4961
YS		 528static void sh_eth_set_rate_giga(struct net_device *ndev)
529{
530 struct sh_eth_private *mdp = netdev_priv(ndev);
531
532 switch (mdp->speed) {
533 case 10: /* 10BASE */
534 sh_eth_write(ndev, 0x00000000, GECMR);
535 break;
536 case 100:/* 100BASE */
537 sh_eth_write(ndev, 0x00000010, GECMR);
538 break;
539 case 1000: /* 1000BASE */
540 sh_eth_write(ndev, 0x00000020, GECMR);
541 break;
542 default:
543 break;
544 }
545}
546
547/* SH7757(GETHERC) */
24549e2a 548static struct sh_eth_cpu_data sh7757_data_giga = {
8fcd4961 549 .chip_reset = sh_eth_chip_reset_giga,
04b0ed2a 550 .set_duplex = sh_eth_set_duplex,
8fcd4961
YS		 551 .set_rate = sh_eth_set_rate_giga,
552
a3153d8c
SS		 553 .register_type = SH_ETH_REG_GIGABIT,
554
8fcd4961
YS		 555 .ecsr_value = ECSR_ICD | ECSR_MPD,
556 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
557 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
558
559 .tx_check = EESR_TC1 | EESR_FTC,
ca8c3585
SS		 560 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
561 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
562 EESR_TDE | EESR_ECI,
8fcd4961
YS		 563 .fdr_value = 0x0000072f,
564 .rmcr_value = 0x00000001,
565
5b3dfd13 566 .irq_flags = IRQF_SHARED,
8fcd4961
YS		 567 .apr = 1,
568 .mpr = 1,
569 .tpauser = 1,
570 .bculr = 1,
571 .hw_swap = 1,
572 .rpadir = 1,
573 .rpadir_value = 2 << 16,
574 .no_trimd = 1,
575 .no_ade = 1,
3acbc971 576 .tsu = 1,
8fcd4961
YS		 577};
578
380af9e3
YS		 579static void sh_eth_chip_reset(struct net_device *ndev)
580{
4986b996
YS		 581 struct sh_eth_private *mdp = netdev_priv(ndev);
582
380af9e3 583 /* reset device */
4986b996 584 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
380af9e3
YS		 585 mdelay(1);
586}
587
f5d12767 588static void sh_eth_set_rate_gether(struct net_device *ndev)
380af9e3
YS		 589{
590 struct sh_eth_private *mdp = netdev_priv(ndev);
380af9e3
YS		 591
592 switch (mdp->speed) {
593 case 10: /* 10BASE */
4a55530f 594 sh_eth_write(ndev, GECMR_10, GECMR);
380af9e3
YS		 595 break;
596 case 100:/* 100BASE */
4a55530f 597 sh_eth_write(ndev, GECMR_100, GECMR);
380af9e3
YS		 598 break;
599 case 1000: /* 1000BASE */
4a55530f 600 sh_eth_write(ndev, GECMR_1000, GECMR);
380af9e3
YS		 601 break;
602 default:
603 break;
604 }
605}
606
f5d12767
SS		 607/* SH7734 */
608static struct sh_eth_cpu_data sh7734_data = {
380af9e3
YS		 609 .chip_reset = sh_eth_chip_reset,
610 .set_duplex = sh_eth_set_duplex,
f5d12767
SS		 611 .set_rate = sh_eth_set_rate_gether,
612
a3153d8c
SS		 613 .register_type = SH_ETH_REG_GIGABIT,
614
f5d12767
SS		 615 .ecsr_value = ECSR_ICD | ECSR_MPD,
616 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
617 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
618
619 .tx_check = EESR_TC1 | EESR_FTC,
ca8c3585
SS		 620 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
621 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
622 EESR_TDE | EESR_ECI,
2c6221e4
NHK		 623 .fdr_value = 0x0000070f,
624 .rmcr_value = 0x00000001,
f5d12767
SS		 625
626 .apr = 1,
627 .mpr = 1,
628 .tpauser = 1,
629 .bculr = 1,
630 .hw_swap = 1,
2c6221e4
NHK		 631 .rpadir = 1,
632 .rpadir_value = 2 << 16,
f5d12767
SS		 633 .no_trimd = 1,
634 .no_ade = 1,
635 .tsu = 1,
636 .hw_crc = 1,
637 .select_mii = 1,
638};
639
640/* SH7763 */
641static struct sh_eth_cpu_data sh7763_data = {
642 .chip_reset = sh_eth_chip_reset,
643 .set_duplex = sh_eth_set_duplex,
644 .set_rate = sh_eth_set_rate_gether,
380af9e3 645
a3153d8c
SS		 646 .register_type = SH_ETH_REG_GIGABIT,
647
380af9e3
YS		 648 .ecsr_value = ECSR_ICD | ECSR_MPD,
649 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
650 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
651
652 .tx_check = EESR_TC1 | EESR_FTC,
653 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \
654 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \
655 EESR_ECI,
380af9e3
YS		 656
657 .apr = 1,
658 .mpr = 1,
659 .tpauser = 1,
660 .bculr = 1,
661 .hw_swap = 1,
380af9e3
YS		 662 .no_trimd = 1,
663 .no_ade = 1,
4986b996 664 .tsu = 1,
5b3dfd13 665 .irq_flags = IRQF_SHARED,
380af9e3
YS		 666};
667
e5c9b4cd 668static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
73a0d907
YS		 669{
670 struct sh_eth_private *mdp = netdev_priv(ndev);
73a0d907
YS		 671
672 /* reset device */
673 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
674 mdelay(1);
675
5e7a76be 676 sh_eth_select_mii(ndev);
73a0d907
YS		 677}
678
73a0d907 679/* R8A7740 */
e5c9b4cd
SS		 680static struct sh_eth_cpu_data r8a7740_data = {
681 .chip_reset = sh_eth_chip_reset_r8a7740,
73a0d907 682 .set_duplex = sh_eth_set_duplex,
e5c9b4cd 683 .set_rate = sh_eth_set_rate_gether,
73a0d907 684
a3153d8c
SS		 685 .register_type = SH_ETH_REG_GIGABIT,
686
73a0d907
YS		 687 .ecsr_value = ECSR_ICD | ECSR_MPD,
688 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
689 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
690
691 .tx_check = EESR_TC1 | EESR_FTC,
ca8c3585
SS		 692 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
693 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
694 EESR_TDE | EESR_ECI,
73a0d907
YS		 695
696 .apr = 1,
697 .mpr = 1,
698 .tpauser = 1,
699 .bculr = 1,
700 .hw_swap = 1,
701 .no_trimd = 1,
702 .no_ade = 1,
703 .tsu = 1,
5e7a76be 704 .select_mii = 1,
ac8025a6 705 .shift_rd0 = 1,
73a0d907
YS		 706};
707
c18a79ab 708static struct sh_eth_cpu_data sh7619_data = {
a3153d8c
SS		 709 .register_type = SH_ETH_REG_FAST_SH3_SH2,
710
380af9e3
YS		 711 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
712
713 .apr = 1,
714 .mpr = 1,
715 .tpauser = 1,
716 .hw_swap = 1,
717};
7bbe150d
SS		 718
719static struct sh_eth_cpu_data sh771x_data = {
a3153d8c
SS		 720 .register_type = SH_ETH_REG_FAST_SH3_SH2,
721
380af9e3 722 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
4986b996 723 .tsu = 1,
380af9e3 724};
380af9e3
YS		 725
726static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
727{
728 if (!cd->ecsr_value)
729 cd->ecsr_value = DEFAULT_ECSR_INIT;
730
731 if (!cd->ecsipr_value)
732 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
733
734 if (!cd->fcftr_value)
735 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF | \
736 DEFAULT_FIFO_F_D_RFD;
737
738 if (!cd->fdr_value)
739 cd->fdr_value = DEFAULT_FDR_INIT;
740
741 if (!cd->rmcr_value)
742 cd->rmcr_value = DEFAULT_RMCR_VALUE;
743
744 if (!cd->tx_check)
745 cd->tx_check = DEFAULT_TX_CHECK;
746
747 if (!cd->eesr_err_check)
748 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
380af9e3
YS		 749}
750
5cee1d37
NI		 751static int sh_eth_check_reset(struct net_device *ndev)
752{
753 int ret = 0;
754 int cnt = 100;
755
756 while (cnt > 0) {
757 if (!(sh_eth_read(ndev, EDMR) & 0x3))
758 break;
759 mdelay(1);
760 cnt--;
761 }
9f8c4265
SS		 762 if (cnt <= 0) {
763 pr_err("Device reset failed\n");
5cee1d37
NI		 764 ret = -ETIMEDOUT;
765 }
766 return ret;
380af9e3 767}
dabdde9e
NI		 768
769static int sh_eth_reset(struct net_device *ndev)
770{
771 struct sh_eth_private *mdp = netdev_priv(ndev);
772 int ret = 0;
773
774 if (sh_eth_is_gether(mdp)) {
775 sh_eth_write(ndev, EDSR_ENALL, EDSR);
776 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER,
777 EDMR);
778
779 ret = sh_eth_check_reset(ndev);
780 if (ret)
781 goto out;
782
783 /* Table Init */
784 sh_eth_write(ndev, 0x0, TDLAR);
785 sh_eth_write(ndev, 0x0, TDFAR);
786 sh_eth_write(ndev, 0x0, TDFXR);
787 sh_eth_write(ndev, 0x0, TDFFR);
788 sh_eth_write(ndev, 0x0, RDLAR);
789 sh_eth_write(ndev, 0x0, RDFAR);
790 sh_eth_write(ndev, 0x0, RDFXR);
791 sh_eth_write(ndev, 0x0, RDFFR);
792
793 /* Reset HW CRC register */
794 if (mdp->cd->hw_crc)
795 sh_eth_write(ndev, 0x0, CSMR);
796
797 /* Select MII mode */
798 if (mdp->cd->select_mii)
799 sh_eth_select_mii(ndev);
800 } else {
801 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER,
802 EDMR);
803 mdelay(3);
804 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER,
805 EDMR);
806 }
807
808out:
809 return ret;
810}
380af9e3 811
73a0d907 812#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
380af9e3
YS		 813static void sh_eth_set_receive_align(struct sk_buff *skb)
814{
815 int reserve;
816
817 reserve = SH4_SKB_RX_ALIGN - ((u32)skb->data & (SH4_SKB_RX_ALIGN - 1));
818 if (reserve)
819 skb_reserve(skb, reserve);
820}
821#else
822static void sh_eth_set_receive_align(struct sk_buff *skb)
823{
824 skb_reserve(skb, SH2_SH3_SKB_RX_ALIGN);
825}
826#endif
827
828
71557a37
YS		 829/* CPU <-> EDMAC endian convert */
830static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x)
831{
832 switch (mdp->edmac_endian) {
833 case EDMAC_LITTLE_ENDIAN:
834 return cpu_to_le32(x);
835 case EDMAC_BIG_ENDIAN:
836 return cpu_to_be32(x);
837 }
838 return x;
839}
840
841static inline __u32 edmac_to_cpu(struct sh_eth_private *mdp, u32 x)
842{
843 switch (mdp->edmac_endian) {
844 case EDMAC_LITTLE_ENDIAN:
845 return le32_to_cpu(x);
846 case EDMAC_BIG_ENDIAN:
847 return be32_to_cpu(x);
848 }
849 return x;
850}
851
86a74ff2
NI		 852/*
853 * Program the hardware MAC address from dev->dev_addr.
854 */
855static void update_mac_address(struct net_device *ndev)
856{
4a55530f
YS		 857 sh_eth_write(ndev,
858 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
859 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
860 sh_eth_write(ndev,
861 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
86a74ff2
NI		 862}
863
864/*
865 * Get MAC address from SuperH MAC address register
866 *
867 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
868 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
869 * When you want use this device, you must set MAC address in bootloader.
870 *
871 */
748031f9 872static void read_mac_address(struct net_device *ndev, unsigned char *mac)
86a74ff2 873{
748031f9
MD		 874 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
875 memcpy(ndev->dev_addr, mac, 6);
876 } else {
4a55530f
YS		 877 ndev->dev_addr[0] = (sh_eth_read(ndev, MAHR) >> 24);
878 ndev->dev_addr[1] = (sh_eth_read(ndev, MAHR) >> 16) & 0xFF;
879 ndev->dev_addr[2] = (sh_eth_read(ndev, MAHR) >> 8) & 0xFF;
880 ndev->dev_addr[3] = (sh_eth_read(ndev, MAHR) & 0xFF);
881 ndev->dev_addr[4] = (sh_eth_read(ndev, MALR) >> 8) & 0xFF;
882 ndev->dev_addr[5] = (sh_eth_read(ndev, MALR) & 0xFF);
748031f9 883 }
86a74ff2
NI		 884}
885
c5ed5368
YS		 886static unsigned long sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
887{
888 if (sh_eth_is_gether(mdp))
889 return EDTRR_TRNS_GETHER;
890 else
891 return EDTRR_TRNS_ETHER;
892}
893
86a74ff2 894struct bb_info {
ae70644d 895 void (*set_gate)(void *addr);
86a74ff2 896 struct mdiobb_ctrl ctrl;
ae70644d 897 void *addr;
86a74ff2
NI		 898 u32 mmd_msk;/* MMD */
899 u32 mdo_msk;
900 u32 mdi_msk;
901 u32 mdc_msk;
902};
903
904/* PHY bit set */
ae70644d 905static void bb_set(void *addr, u32 msk)
86a74ff2 906{
ae70644d 907 iowrite32(ioread32(addr) | msk, addr);
86a74ff2
NI		 908}
909
910/* PHY bit clear */
ae70644d 911static void bb_clr(void *addr, u32 msk)
86a74ff2 912{
ae70644d 913 iowrite32((ioread32(addr) & ~msk), addr);
86a74ff2
NI		 914}
915
916/* PHY bit read */
ae70644d 917static int bb_read(void *addr, u32 msk)
86a74ff2 918{
ae70644d 919 return (ioread32(addr) & msk) != 0;
86a74ff2
NI		 920}
921
922/* Data I/O pin control */
923static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
924{
925 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
b3017e6a
YS		 926
927 if (bitbang->set_gate)
928 bitbang->set_gate(bitbang->addr);
929
86a74ff2
NI		 930 if (bit)
931 bb_set(bitbang->addr, bitbang->mmd_msk);
932 else
933 bb_clr(bitbang->addr, bitbang->mmd_msk);
934}
935
936/* Set bit data*/
937static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
938{
939 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
940
b3017e6a
YS		 941 if (bitbang->set_gate)
942 bitbang->set_gate(bitbang->addr);
943
86a74ff2
NI		 944 if (bit)
945 bb_set(bitbang->addr, bitbang->mdo_msk);
946 else
947 bb_clr(bitbang->addr, bitbang->mdo_msk);
948}
949
950/* Get bit data*/
951static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
952{
953 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
b3017e6a
YS		 954
955 if (bitbang->set_gate)
956 bitbang->set_gate(bitbang->addr);
957
86a74ff2
NI		 958 return bb_read(bitbang->addr, bitbang->mdi_msk);
959}
960
961/* MDC pin control */
962static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
963{
964 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
965
b3017e6a
YS		 966 if (bitbang->set_gate)
967 bitbang->set_gate(bitbang->addr);
968
86a74ff2
NI		 969 if (bit)
970 bb_set(bitbang->addr, bitbang->mdc_msk);
971 else
972 bb_clr(bitbang->addr, bitbang->mdc_msk);
973}
974
975/* mdio bus control struct */
976static struct mdiobb_ops bb_ops = {
977 .owner = THIS_MODULE,
978 .set_mdc = sh_mdc_ctrl,
979 .set_mdio_dir = sh_mmd_ctrl,
980 .set_mdio_data = sh_set_mdio,
981 .get_mdio_data = sh_get_mdio,
982};
983
86a74ff2
NI		 984/* free skb and descriptor buffer */
985static void sh_eth_ring_free(struct net_device *ndev)
986{
987 struct sh_eth_private *mdp = netdev_priv(ndev);
988 int i;
989
990 /* Free Rx skb ringbuffer */
991 if (mdp->rx_skbuff) {
525b8075 992 for (i = 0; i < mdp->num_rx_ring; i++) {
86a74ff2
NI		 993 if (mdp->rx_skbuff[i])
994 dev_kfree_skb(mdp->rx_skbuff[i]);
995 }
996 }
997 kfree(mdp->rx_skbuff);
91c77550 998 mdp->rx_skbuff = NULL;
86a74ff2
NI		 999
1000 /* Free Tx skb ringbuffer */
1001 if (mdp->tx_skbuff) {
525b8075 1002 for (i = 0; i < mdp->num_tx_ring; i++) {
86a74ff2
NI		 1003 if (mdp->tx_skbuff[i])
1004 dev_kfree_skb(mdp->tx_skbuff[i]);
1005 }
1006 }
1007 kfree(mdp->tx_skbuff);
91c77550 1008 mdp->tx_skbuff = NULL;
86a74ff2
NI		 1009}
1010
1011/* format skb and descriptor buffer */
1012static void sh_eth_ring_format(struct net_device *ndev)
1013{
1014 struct sh_eth_private *mdp = netdev_priv(ndev);
1015 int i;
1016 struct sk_buff *skb;
1017 struct sh_eth_rxdesc *rxdesc = NULL;
1018 struct sh_eth_txdesc *txdesc = NULL;
525b8075
YS		 1019 int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
1020 int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
86a74ff2
NI		 1021
1022 mdp->cur_rx = mdp->cur_tx = 0;
1023 mdp->dirty_rx = mdp->dirty_tx = 0;
1024
1025 memset(mdp->rx_ring, 0, rx_ringsize);
1026
1027 /* build Rx ring buffer */
525b8075 1028 for (i = 0; i < mdp->num_rx_ring; i++) {
86a74ff2
NI		 1029 /* skb */
1030 mdp->rx_skbuff[i] = NULL;
dae2e9f4 1031 skb = netdev_alloc_skb(ndev, mdp->rx_buf_sz);
86a74ff2
NI		 1032 mdp->rx_skbuff[i] = skb;
1033 if (skb == NULL)
1034 break;
bb7d92e3 1035 dma_map_single(&ndev->dev, skb->data, mdp->rx_buf_sz,
e88aae7b 1036 DMA_FROM_DEVICE);
380af9e3
YS		 1037 sh_eth_set_receive_align(skb);
1038
86a74ff2
NI		 1039 /* RX descriptor */
1040 rxdesc = &mdp->rx_ring[i];
0029d64a 1041 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
71557a37 1042 rxdesc->status = cpu_to_edmac(mdp, RD_RACT | RD_RFP);
86a74ff2
NI		 1043
1044 /* The size of the buffer is 16 byte boundary. */
0029d64a 1045 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
b0ca2a21
NI		 1046 /* Rx descriptor address set */
1047 if (i == 0) {
4a55530f 1048 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
c5ed5368
YS		 1049 if (sh_eth_is_gether(mdp))
1050 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
b0ca2a21 1051 }
86a74ff2
NI		 1052 }
1053
525b8075 1054 mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
86a74ff2
NI		 1055
1056 /* Mark the last entry as wrapping the ring. */
71557a37 1057 rxdesc->status |= cpu_to_edmac(mdp, RD_RDEL);
86a74ff2
NI		 1058
1059 memset(mdp->tx_ring, 0, tx_ringsize);
1060
1061 /* build Tx ring buffer */
525b8075 1062 for (i = 0; i < mdp->num_tx_ring; i++) {
86a74ff2
NI		 1063 mdp->tx_skbuff[i] = NULL;
1064 txdesc = &mdp->tx_ring[i];
71557a37 1065 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
86a74ff2 1066 txdesc->buffer_length = 0;
b0ca2a21 1067 if (i == 0) {
71557a37 1068 /* Tx descriptor address set */
4a55530f 1069 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
c5ed5368
YS		 1070 if (sh_eth_is_gether(mdp))
1071 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
b0ca2a21 1072 }
86a74ff2
NI		 1073 }
1074
71557a37 1075 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
86a74ff2
NI		 1076}
1077
1078/* Get skb and descriptor buffer */
1079static int sh_eth_ring_init(struct net_device *ndev)
1080{
1081 struct sh_eth_private *mdp = netdev_priv(ndev);
1082 int rx_ringsize, tx_ringsize, ret = 0;
1083
1084 /*
1085 * +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
1086 * card needs room to do 8 byte alignment, +2 so we can reserve
1087 * the first 2 bytes, and +16 gets room for the status word from the
1088 * card.
1089 */
1090 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
1091 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
503914cf
MD		 1092 if (mdp->cd->rpadir)
1093 mdp->rx_buf_sz += NET_IP_ALIGN;
86a74ff2
NI		 1094
1095 /* Allocate RX and TX skb rings */
b2adaca9
JP		 1096 mdp->rx_skbuff = kmalloc_array(mdp->num_rx_ring,
1097 sizeof(*mdp->rx_skbuff), GFP_KERNEL);
86a74ff2 1098 if (!mdp->rx_skbuff) {
86a74ff2
NI		 1099 ret = -ENOMEM;
1100 return ret;
1101 }
1102
b2adaca9
JP		 1103 mdp->tx_skbuff = kmalloc_array(mdp->num_tx_ring,
1104 sizeof(*mdp->tx_skbuff), GFP_KERNEL);
86a74ff2 1105 if (!mdp->tx_skbuff) {
86a74ff2
NI		 1106 ret = -ENOMEM;
1107 goto skb_ring_free;
1108 }
1109
1110 /* Allocate all Rx descriptors. */
525b8075 1111 rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
86a74ff2 1112 mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
d0320f75 1113 GFP_KERNEL);
86a74ff2 1114 if (!mdp->rx_ring) {
86a74ff2
NI		 1115 ret = -ENOMEM;
1116 goto desc_ring_free;
1117 }
1118
1119 mdp->dirty_rx = 0;
1120
1121 /* Allocate all Tx descriptors. */
525b8075 1122 tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
86a74ff2 1123 mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
d0320f75 1124 GFP_KERNEL);
86a74ff2 1125 if (!mdp->tx_ring) {
86a74ff2
NI		 1126 ret = -ENOMEM;
1127 goto desc_ring_free;
1128 }
1129 return ret;
1130
1131desc_ring_free:
1132 /* free DMA buffer */
1133 dma_free_coherent(NULL, rx_ringsize, mdp->rx_ring, mdp->rx_desc_dma);
1134
1135skb_ring_free:
1136 /* Free Rx and Tx skb ring buffer */
1137 sh_eth_ring_free(ndev);
91c77550
YS		 1138 mdp->tx_ring = NULL;
1139 mdp->rx_ring = NULL;
86a74ff2
NI		 1140
1141 return ret;
1142}
1143
91c77550
YS		 1144static void sh_eth_free_dma_buffer(struct sh_eth_private *mdp)
1145{
1146 int ringsize;
1147
1148 if (mdp->rx_ring) {
525b8075 1149 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
91c77550
YS		 1150 dma_free_coherent(NULL, ringsize, mdp->rx_ring,
1151 mdp->rx_desc_dma);
1152 mdp->rx_ring = NULL;
1153 }
1154
1155 if (mdp->tx_ring) {
525b8075 1156 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
91c77550
YS		 1157 dma_free_coherent(NULL, ringsize, mdp->tx_ring,
1158 mdp->tx_desc_dma);
1159 mdp->tx_ring = NULL;
1160 }
1161}
1162
525b8075 1163static int sh_eth_dev_init(struct net_device *ndev, bool start)
86a74ff2
NI		 1164{
1165 int ret = 0;
1166 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 1167 u32 val;
1168
1169 /* Soft Reset */
5cee1d37
NI		 1170 ret = sh_eth_reset(ndev);
1171 if (ret)
1172 goto out;
86a74ff2 1173
55754f19
SH		 1174 if (mdp->cd->rmiimode)
1175 sh_eth_write(ndev, 0x1, RMIIMODE);
1176
b0ca2a21
NI		 1177 /* Descriptor format */
1178 sh_eth_ring_format(ndev);
380af9e3 1179 if (mdp->cd->rpadir)
4a55530f 1180 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
86a74ff2
NI		 1181
1182 /* all sh_eth int mask */
4a55530f 1183 sh_eth_write(ndev, 0, EESIPR);
86a74ff2 1184
10b9194f 1185#if defined(__LITTLE_ENDIAN)
380af9e3 1186 if (mdp->cd->hw_swap)
4a55530f 1187 sh_eth_write(ndev, EDMR_EL, EDMR);
380af9e3 1188 else
b0ca2a21 1189#endif
4a55530f 1190 sh_eth_write(ndev, 0, EDMR);
86a74ff2 1191
b0ca2a21 1192 /* FIFO size set */
4a55530f
YS		 1193 sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
1194 sh_eth_write(ndev, 0, TFTR);
86a74ff2 1195
b0ca2a21 1196 /* Frame recv control */
4a55530f 1197 sh_eth_write(ndev, mdp->cd->rmcr_value, RMCR);
86a74ff2 1198
2ecbb783 1199 sh_eth_write(ndev, DESC_I_RINT8 | DESC_I_RINT5 | DESC_I_TINT2, TRSCER);
86a74ff2 1200
380af9e3 1201 if (mdp->cd->bculr)
4a55530f 1202 sh_eth_write(ndev, 0x800, BCULR); /* Burst sycle set */
b0ca2a21 1203
4a55530f 1204 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
86a74ff2 1205
380af9e3 1206 if (!mdp->cd->no_trimd)
4a55530f 1207 sh_eth_write(ndev, 0, TRIMD);
86a74ff2 1208
b0ca2a21 1209 /* Recv frame limit set register */
fdb37a7f
YS		 1210 sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1211 RFLR);
86a74ff2 1212
4a55530f 1213 sh_eth_write(ndev, sh_eth_read(ndev, EESR), EESR);
525b8075
YS		 1214 if (start)
1215 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
86a74ff2
NI		 1216
1217 /* PAUSE Prohibition */
4a55530f 1218 val = (sh_eth_read(ndev, ECMR) & ECMR_DM) |
86a74ff2
NI		 1219 ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE;
1220
4a55530f 1221 sh_eth_write(ndev, val, ECMR);
b0ca2a21 1222
380af9e3
YS		 1223 if (mdp->cd->set_rate)
1224 mdp->cd->set_rate(ndev);
1225
b0ca2a21 1226 /* E-MAC Status Register clear */
4a55530f 1227 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
b0ca2a21
NI		 1228
1229 /* E-MAC Interrupt Enable register */
525b8075
YS		 1230 if (start)
1231 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
86a74ff2
NI		 1232
1233 /* Set MAC address */
1234 update_mac_address(ndev);
1235
1236 /* mask reset */
380af9e3 1237 if (mdp->cd->apr)
4a55530f 1238 sh_eth_write(ndev, APR_AP, APR);
380af9e3 1239 if (mdp->cd->mpr)
4a55530f 1240 sh_eth_write(ndev, MPR_MP, MPR);
380af9e3 1241 if (mdp->cd->tpauser)
4a55530f 1242 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
b0ca2a21 1243
525b8075
YS		 1244 if (start) {
1245 /* Setting the Rx mode will start the Rx process. */
1246 sh_eth_write(ndev, EDRRR_R, EDRRR);
86a74ff2 1247
525b8075
YS		 1248 netif_start_queue(ndev);
1249 }
86a74ff2 1250
5cee1d37 1251out:
86a74ff2
NI		 1252 return ret;
1253}
1254
1255/* free Tx skb function */
1256static int sh_eth_txfree(struct net_device *ndev)
1257{
1258 struct sh_eth_private *mdp = netdev_priv(ndev);
1259 struct sh_eth_txdesc *txdesc;
1260 int freeNum = 0;
1261 int entry = 0;
1262
1263 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
525b8075 1264 entry = mdp->dirty_tx % mdp->num_tx_ring;
86a74ff2 1265 txdesc = &mdp->tx_ring[entry];
71557a37 1266 if (txdesc->status & cpu_to_edmac(mdp, TD_TACT))
86a74ff2
NI		 1267 break;
1268 /* Free the original skb. */
1269 if (mdp->tx_skbuff[entry]) {
31fcb99d
YS		 1270 dma_unmap_single(&ndev->dev, txdesc->addr,
1271 txdesc->buffer_length, DMA_TO_DEVICE);
86a74ff2
NI		 1272 dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1273 mdp->tx_skbuff[entry] = NULL;
1274 freeNum++;
1275 }
71557a37 1276 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
525b8075 1277 if (entry >= mdp->num_tx_ring - 1)
71557a37 1278 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
86a74ff2 1279
bb7d92e3
ED		 1280 ndev->stats.tx_packets++;
1281 ndev->stats.tx_bytes += txdesc->buffer_length;
86a74ff2
NI		 1282 }
1283 return freeNum;
1284}
1285
1286/* Packet receive function */
3719109d 1287static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
86a74ff2
NI		 1288{
1289 struct sh_eth_private *mdp = netdev_priv(ndev);
1290 struct sh_eth_rxdesc *rxdesc;
1291
525b8075
YS		 1292 int entry = mdp->cur_rx % mdp->num_rx_ring;
1293 int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
86a74ff2 1294 struct sk_buff *skb;
3719109d 1295 int exceeded = 0;
86a74ff2 1296 u16 pkt_len = 0;
380af9e3 1297 u32 desc_status;
86a74ff2
NI		 1298
1299 rxdesc = &mdp->rx_ring[entry];
71557a37
YS		 1300 while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) {
1301 desc_status = edmac_to_cpu(mdp, rxdesc->status);
86a74ff2
NI		 1302 pkt_len = rxdesc->frame_length;
1303
1304 if (--boguscnt < 0)
1305 break;
1306
3719109d
SS		 1307 if (*quota <= 0) {
1308 exceeded = 1;
1309 break;
1310 }
1311 (*quota)--;
1312
86a74ff2 1313 if (!(desc_status & RDFEND))
bb7d92e3 1314 ndev->stats.rx_length_errors++;
86a74ff2 1315
dd019897
YS		 1316 /*
1317 * In case of almost all GETHER/ETHERs, the Receive Frame State
1318 * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
1319 * bit 0. However, in case of the R8A7740's GETHER, the RFS
1320 * bits are from bit 25 to bit 16. So, the driver needs right
1321 * shifting by 16.
1322 */
ac8025a6
SS		 1323 if (mdp->cd->shift_rd0)
1324 desc_status >>= 16;
dd019897 1325
86a74ff2
NI		 1326 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1327 RD_RFS5 | RD_RFS6 | RD_RFS10)) {
bb7d92e3 1328 ndev->stats.rx_errors++;
86a74ff2 1329 if (desc_status & RD_RFS1)
bb7d92e3 1330 ndev->stats.rx_crc_errors++;
86a74ff2 1331 if (desc_status & RD_RFS2)
bb7d92e3 1332 ndev->stats.rx_frame_errors++;
86a74ff2 1333 if (desc_status & RD_RFS3)
bb7d92e3 1334 ndev->stats.rx_length_errors++;
86a74ff2 1335 if (desc_status & RD_RFS4)
bb7d92e3 1336 ndev->stats.rx_length_errors++;
86a74ff2 1337 if (desc_status & RD_RFS6)
bb7d92e3 1338 ndev->stats.rx_missed_errors++;
86a74ff2 1339 if (desc_status & RD_RFS10)
bb7d92e3 1340 ndev->stats.rx_over_errors++;
86a74ff2 1341 } else {
380af9e3
YS		 1342 if (!mdp->cd->hw_swap)
1343 sh_eth_soft_swap(
1344 phys_to_virt(ALIGN(rxdesc->addr, 4)),
1345 pkt_len + 2);
86a74ff2
NI		 1346 skb = mdp->rx_skbuff[entry];
1347 mdp->rx_skbuff[entry] = NULL;
503914cf
MD		 1348 if (mdp->cd->rpadir)
1349 skb_reserve(skb, NET_IP_ALIGN);
7db8e0c1
KA		 1350 dma_sync_single_for_cpu(&ndev->dev, rxdesc->addr,
1351 mdp->rx_buf_sz,
1352 DMA_FROM_DEVICE);
86a74ff2
NI		 1353 skb_put(skb, pkt_len);
1354 skb->protocol = eth_type_trans(skb, ndev);
a8e9fd0f 1355 netif_receive_skb(skb);
bb7d92e3
ED		 1356 ndev->stats.rx_packets++;
1357 ndev->stats.rx_bytes += pkt_len;
86a74ff2 1358 }
71557a37 1359 rxdesc->status |= cpu_to_edmac(mdp, RD_RACT);
525b8075 1360 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
862df497 1361 rxdesc = &mdp->rx_ring[entry];
86a74ff2
NI		 1362 }
1363
1364 /* Refill the Rx ring buffers. */
1365 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
525b8075 1366 entry = mdp->dirty_rx % mdp->num_rx_ring;
86a74ff2 1367 rxdesc = &mdp->rx_ring[entry];
b0ca2a21 1368 /* The size of the buffer is 16 byte boundary. */
0029d64a 1369 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
b0ca2a21 1370
86a74ff2 1371 if (mdp->rx_skbuff[entry] == NULL) {
dae2e9f4 1372 skb = netdev_alloc_skb(ndev, mdp->rx_buf_sz);
86a74ff2
NI		 1373 mdp->rx_skbuff[entry] = skb;
1374 if (skb == NULL)
1375 break; /* Better luck next round. */
bb7d92e3 1376 dma_map_single(&ndev->dev, skb->data, mdp->rx_buf_sz,
e88aae7b 1377 DMA_FROM_DEVICE);
380af9e3
YS		 1378 sh_eth_set_receive_align(skb);
1379
bc8acf2c 1380 skb_checksum_none_assert(skb);
0029d64a 1381 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
86a74ff2 1382 }
525b8075 1383 if (entry >= mdp->num_rx_ring - 1)
86a74ff2 1384 rxdesc->status |=
71557a37 1385 cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDEL);
86a74ff2
NI		 1386 else
1387 rxdesc->status |=
71557a37 1388 cpu_to_edmac(mdp, RD_RACT | RD_RFP);
86a74ff2
NI		 1389 }
1390
1391 /* Restart Rx engine if stopped. */
1392 /* If we don't need to check status, don't. -KDU */
79fba9f5 1393 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
a18e08bd
YS		 1394 /* fix the values for the next receiving if RDE is set */
1395 if (intr_status & EESR_RDE)
1396 mdp->cur_rx = mdp->dirty_rx =
1397 (sh_eth_read(ndev, RDFAR) -
1398 sh_eth_read(ndev, RDLAR)) >> 4;
4a55530f 1399 sh_eth_write(ndev, EDRRR_R, EDRRR);
79fba9f5 1400 }
86a74ff2 1401
3719109d 1402 return exceeded;
86a74ff2
NI		 1403}
1404
4a55530f 1405static void sh_eth_rcv_snd_disable(struct net_device *ndev)
dc19e4e5
NI		 1406{
1407 /* disable tx and rx */
4a55530f
YS		 1408 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) &
1409 ~(ECMR_RE | ECMR_TE), ECMR);
dc19e4e5
NI		 1410}
1411
4a55530f 1412static void sh_eth_rcv_snd_enable(struct net_device *ndev)
dc19e4e5
NI		 1413{
1414 /* enable tx and rx */
4a55530f
YS		 1415 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) |
1416 (ECMR_RE | ECMR_TE), ECMR);
dc19e4e5
NI		 1417}
1418
86a74ff2
NI		 1419/* error control function */
1420static void sh_eth_error(struct net_device *ndev, int intr_status)
1421{
1422 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2 1423 u32 felic_stat;
380af9e3
YS		 1424 u32 link_stat;
1425 u32 mask;
86a74ff2
NI		 1426
1427 if (intr_status & EESR_ECI) {
4a55530f
YS		 1428 felic_stat = sh_eth_read(ndev, ECSR);
1429 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */
86a74ff2 1430 if (felic_stat & ECSR_ICD)
bb7d92e3 1431 ndev->stats.tx_carrier_errors++;
86a74ff2
NI		 1432 if (felic_stat & ECSR_LCHNG) {
1433 /* Link Changed */
4923576b 1434 if (mdp->cd->no_psr || mdp->no_ether_link) {
1e1b812b 1435 goto ignore_link;
380af9e3 1436 } else {
4a55530f 1437 link_stat = (sh_eth_read(ndev, PSR));
4923576b
YS		 1438 if (mdp->ether_link_active_low)
1439 link_stat = ~link_stat;
380af9e3 1440 }
dc19e4e5 1441 if (!(link_stat & PHY_ST_LINK))
4a55530f 1442 sh_eth_rcv_snd_disable(ndev);
dc19e4e5 1443 else {
86a74ff2 1444 /* Link Up */
4a55530f
YS		 1445 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) &
1446 ~DMAC_M_ECI, EESIPR);
86a74ff2 1447 /*clear int */
4a55530f
YS		 1448 sh_eth_write(ndev, sh_eth_read(ndev, ECSR),
1449 ECSR);
1450 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) |
1451 DMAC_M_ECI, EESIPR);
86a74ff2 1452 /* enable tx and rx */
4a55530f 1453 sh_eth_rcv_snd_enable(ndev);
86a74ff2
NI		 1454 }
1455 }
1456 }
1457
1e1b812b 1458ignore_link:
86a74ff2 1459 if (intr_status & EESR_TWB) {
4eb313a7
SS		 1460 /* Unused write back interrupt */
1461 if (intr_status & EESR_TABT) { /* Transmit Abort int */
bb7d92e3 1462 ndev->stats.tx_aborted_errors++;
dc19e4e5
NI		 1463 if (netif_msg_tx_err(mdp))
1464 dev_err(&ndev->dev, "Transmit Abort\n");
4eb313a7 1465 }
86a74ff2
NI		 1466 }
1467
1468 if (intr_status & EESR_RABT) {
1469 /* Receive Abort int */
1470 if (intr_status & EESR_RFRMER) {
1471 /* Receive Frame Overflow int */
bb7d92e3 1472 ndev->stats.rx_frame_errors++;
dc19e4e5
NI		 1473 if (netif_msg_rx_err(mdp))
1474 dev_err(&ndev->dev, "Receive Abort\n");
86a74ff2
NI		 1475 }
1476 }
380af9e3 1477
dc19e4e5
NI		 1478 if (intr_status & EESR_TDE) {
1479 /* Transmit Descriptor Empty int */
bb7d92e3 1480 ndev->stats.tx_fifo_errors++;
dc19e4e5
NI		 1481 if (netif_msg_tx_err(mdp))
1482 dev_err(&ndev->dev, "Transmit Descriptor Empty\n");
1483 }
1484
1485 if (intr_status & EESR_TFE) {
1486 /* FIFO under flow */
bb7d92e3 1487 ndev->stats.tx_fifo_errors++;
dc19e4e5
NI		 1488 if (netif_msg_tx_err(mdp))
1489 dev_err(&ndev->dev, "Transmit FIFO Under flow\n");
86a74ff2
NI		 1490 }
1491
1492 if (intr_status & EESR_RDE) {
1493 /* Receive Descriptor Empty int */
bb7d92e3 1494 ndev->stats.rx_over_errors++;
86a74ff2 1495
dc19e4e5
NI		 1496 if (netif_msg_rx_err(mdp))
1497 dev_err(&ndev->dev, "Receive Descriptor Empty\n");
86a74ff2 1498 }
dc19e4e5 1499
86a74ff2
NI		 1500 if (intr_status & EESR_RFE) {
1501 /* Receive FIFO Overflow int */
bb7d92e3 1502 ndev->stats.rx_fifo_errors++;
dc19e4e5
NI		 1503 if (netif_msg_rx_err(mdp))
1504 dev_err(&ndev->dev, "Receive FIFO Overflow\n");
1505 }
1506
1507 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1508 /* Address Error */
bb7d92e3 1509 ndev->stats.tx_fifo_errors++;
dc19e4e5
NI		 1510 if (netif_msg_tx_err(mdp))
1511 dev_err(&ndev->dev, "Address Error\n");
86a74ff2 1512 }
380af9e3
YS		 1513
1514 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1515 if (mdp->cd->no_ade)
1516 mask &= ~EESR_ADE;
1517 if (intr_status & mask) {
86a74ff2 1518 /* Tx error */
4a55530f 1519 u32 edtrr = sh_eth_read(ndev, EDTRR);
86a74ff2 1520 /* dmesg */
380af9e3
YS		 1521 dev_err(&ndev->dev, "TX error. status=%8.8x cur_tx=%8.8x ",
1522 intr_status, mdp->cur_tx);
1523 dev_err(&ndev->dev, "dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
86a74ff2
NI		 1524 mdp->dirty_tx, (u32) ndev->state, edtrr);
1525 /* dirty buffer free */
1526 sh_eth_txfree(ndev);
1527
1528 /* SH7712 BUG */
c5ed5368 1529 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
86a74ff2 1530 /* tx dma start */
c5ed5368 1531 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
86a74ff2
NI		 1532 }
1533 /* wakeup */
1534 netif_wake_queue(ndev);
1535 }
1536}
1537
1538static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1539{
1540 struct net_device *ndev = netdev;
1541 struct sh_eth_private *mdp = netdev_priv(ndev);
380af9e3 1542 struct sh_eth_cpu_data *cd = mdp->cd;
0e0fde3c 1543 irqreturn_t ret = IRQ_NONE;
3719109d 1544 unsigned long intr_status, intr_enable;
86a74ff2 1545
86a74ff2
NI		 1546 spin_lock(&mdp->lock);
1547
3893b273 1548 /* Get interrupt status */
4a55530f 1549 intr_status = sh_eth_read(ndev, EESR);
3893b273
SS		 1550 /* Mask it with the interrupt mask, forcing ECI interrupt to be always
1551 * enabled since it's the one that comes thru regardless of the mask,
1552 * and we need to fully handle it in sh_eth_error() in order to quench
1553 * it as it doesn't get cleared by just writing 1 to the ECI bit...
1554 */
3719109d
SS		 1555 intr_enable = sh_eth_read(ndev, EESIPR);
1556 intr_status &= intr_enable | DMAC_M_ECI;
1557 if (intr_status & (EESR_RX_CHECK | cd->tx_check | cd->eesr_err_check))
0e0fde3c 1558 ret = IRQ_HANDLED;
3719109d 1559 else
0e0fde3c 1560 goto other_irq;
86a74ff2 1561
3719109d
SS		 1562 if (intr_status & EESR_RX_CHECK) {
1563 if (napi_schedule_prep(&mdp->napi)) {
1564 /* Mask Rx interrupts */
1565 sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK,
1566 EESIPR);
1567 __napi_schedule(&mdp->napi);
1568 } else {
1569 dev_warn(&ndev->dev,
1570 "ignoring interrupt, status 0x%08lx, mask 0x%08lx.\n",
1571 intr_status, intr_enable);
1572 }
1573 }
86a74ff2 1574
b0ca2a21 1575 /* Tx Check */
380af9e3 1576 if (intr_status & cd->tx_check) {
3719109d
SS		 1577 /* Clear Tx interrupts */
1578 sh_eth_write(ndev, intr_status & cd->tx_check, EESR);
1579
86a74ff2
NI		 1580 sh_eth_txfree(ndev);
1581 netif_wake_queue(ndev);
1582 }
1583
3719109d
SS		 1584 if (intr_status & cd->eesr_err_check) {
1585 /* Clear error interrupts */
1586 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR);
1587
86a74ff2 1588 sh_eth_error(ndev, intr_status);
3719109d 1589 }
86a74ff2 1590
0e0fde3c 1591other_irq:
86a74ff2
NI		 1592 spin_unlock(&mdp->lock);
1593
0e0fde3c 1594 return ret;
86a74ff2
NI		 1595}
1596
3719109d
SS		 1597static int sh_eth_poll(struct napi_struct *napi, int budget)
1598{
1599 struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private,
1600 napi);
1601 struct net_device *ndev = napi->dev;
1602 int quota = budget;
1603 unsigned long intr_status;
1604
1605 for (;;) {
1606 intr_status = sh_eth_read(ndev, EESR);
1607 if (!(intr_status & EESR_RX_CHECK))
1608 break;
1609 /* Clear Rx interrupts */
1610 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR);
1611
1612 if (sh_eth_rx(ndev, intr_status, &quota))
1613 goto out;
1614 }
1615
1616 napi_complete(napi);
1617
1618 /* Reenable Rx interrupts */
1619 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1620out:
1621 return budget - quota;
1622}
1623
86a74ff2
NI		 1624/* PHY state control function */
1625static void sh_eth_adjust_link(struct net_device *ndev)
1626{
1627 struct sh_eth_private *mdp = netdev_priv(ndev);
1628 struct phy_device *phydev = mdp->phydev;
86a74ff2
NI		 1629 int new_state = 0;
1630
3340d2aa 1631 if (phydev->link) {
86a74ff2
NI		 1632 if (phydev->duplex != mdp->duplex) {
1633 new_state = 1;
1634 mdp->duplex = phydev->duplex;
380af9e3
YS		 1635 if (mdp->cd->set_duplex)
1636 mdp->cd->set_duplex(ndev);
86a74ff2
NI		 1637 }
1638
1639 if (phydev->speed != mdp->speed) {
1640 new_state = 1;
1641 mdp->speed = phydev->speed;
380af9e3
YS		 1642 if (mdp->cd->set_rate)
1643 mdp->cd->set_rate(ndev);
86a74ff2 1644 }
3340d2aa 1645 if (!mdp->link) {
91a56152
YS		 1646 sh_eth_write(ndev,
1647 (sh_eth_read(ndev, ECMR) & ~ECMR_TXF), ECMR);
86a74ff2
NI		 1648 new_state = 1;
1649 mdp->link = phydev->link;
1e1b812b
SS		 1650 if (mdp->cd->no_psr || mdp->no_ether_link)
1651 sh_eth_rcv_snd_enable(ndev);
86a74ff2
NI		 1652 }
1653 } else if (mdp->link) {
1654 new_state = 1;
3340d2aa 1655 mdp->link = 0;
86a74ff2
NI		 1656 mdp->speed = 0;
1657 mdp->duplex = -1;
1e1b812b
SS		 1658 if (mdp->cd->no_psr || mdp->no_ether_link)
1659 sh_eth_rcv_snd_disable(ndev);
86a74ff2
NI		 1660 }
1661
dc19e4e5 1662 if (new_state && netif_msg_link(mdp))
86a74ff2
NI		 1663 phy_print_status(phydev);
1664}
1665
1666/* PHY init function */
1667static int sh_eth_phy_init(struct net_device *ndev)
1668{
1669 struct sh_eth_private *mdp = netdev_priv(ndev);
0a372eb9 1670 char phy_id[MII_BUS_ID_SIZE + 3];
86a74ff2
NI		 1671 struct phy_device *phydev = NULL;
1672
fb28ad35 1673 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
86a74ff2
NI		 1674 mdp->mii_bus->id , mdp->phy_id);
1675
3340d2aa 1676 mdp->link = 0;
86a74ff2
NI		 1677 mdp->speed = 0;
1678 mdp->duplex = -1;
1679
1680 /* Try connect to PHY */
c061b18d 1681 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
f9a8f83b 1682 mdp->phy_interface);
86a74ff2
NI		 1683 if (IS_ERR(phydev)) {
1684 dev_err(&ndev->dev, "phy_connect failed\n");
1685 return PTR_ERR(phydev);
1686 }
380af9e3 1687
86a74ff2 1688 dev_info(&ndev->dev, "attached phy %i to driver %s\n",
380af9e3 1689 phydev->addr, phydev->drv->name);
86a74ff2
NI		 1690
1691 mdp->phydev = phydev;
1692
1693 return 0;
1694}
1695
1696/* PHY control start function */
1697static int sh_eth_phy_start(struct net_device *ndev)
1698{
1699 struct sh_eth_private *mdp = netdev_priv(ndev);
1700 int ret;
1701
1702 ret = sh_eth_phy_init(ndev);
1703 if (ret)
1704 return ret;
1705
1706 /* reset phy - this also wakes it from PDOWN */
1707 phy_write(mdp->phydev, MII_BMCR, BMCR_RESET);
1708 phy_start(mdp->phydev);
1709
1710 return 0;
1711}
1712
dc19e4e5
NI		 1713static int sh_eth_get_settings(struct net_device *ndev,
1714 struct ethtool_cmd *ecmd)
1715{
1716 struct sh_eth_private *mdp = netdev_priv(ndev);
1717 unsigned long flags;
1718 int ret;
1719
1720 spin_lock_irqsave(&mdp->lock, flags);
1721 ret = phy_ethtool_gset(mdp->phydev, ecmd);
1722 spin_unlock_irqrestore(&mdp->lock, flags);
1723
1724 return ret;
1725}
1726
1727static int sh_eth_set_settings(struct net_device *ndev,
1728 struct ethtool_cmd *ecmd)
1729{
1730 struct sh_eth_private *mdp = netdev_priv(ndev);
1731 unsigned long flags;
1732 int ret;
dc19e4e5
NI		 1733
1734 spin_lock_irqsave(&mdp->lock, flags);
1735
1736 /* disable tx and rx */
4a55530f 1737 sh_eth_rcv_snd_disable(ndev);
dc19e4e5
NI		 1738
1739 ret = phy_ethtool_sset(mdp->phydev, ecmd);
1740 if (ret)
1741 goto error_exit;
1742
1743 if (ecmd->duplex == DUPLEX_FULL)
1744 mdp->duplex = 1;
1745 else
1746 mdp->duplex = 0;
1747
1748 if (mdp->cd->set_duplex)
1749 mdp->cd->set_duplex(ndev);
1750
1751error_exit:
1752 mdelay(1);
1753
1754 /* enable tx and rx */
4a55530f 1755 sh_eth_rcv_snd_enable(ndev);
dc19e4e5
NI		 1756
1757 spin_unlock_irqrestore(&mdp->lock, flags);
1758
1759 return ret;
1760}
1761
1762static int sh_eth_nway_reset(struct net_device *ndev)
1763{
1764 struct sh_eth_private *mdp = netdev_priv(ndev);
1765 unsigned long flags;
1766 int ret;
1767
1768 spin_lock_irqsave(&mdp->lock, flags);
1769 ret = phy_start_aneg(mdp->phydev);
1770 spin_unlock_irqrestore(&mdp->lock, flags);
1771
1772 return ret;
1773}
1774
1775static u32 sh_eth_get_msglevel(struct net_device *ndev)
1776{
1777 struct sh_eth_private *mdp = netdev_priv(ndev);
1778 return mdp->msg_enable;
1779}
1780
1781static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
1782{
1783 struct sh_eth_private *mdp = netdev_priv(ndev);
1784 mdp->msg_enable = value;
1785}
1786
1787static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
1788 "rx_current", "tx_current",
1789 "rx_dirty", "tx_dirty",
1790};
1791#define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats)
1792
1793static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
1794{
1795 switch (sset) {
1796 case ETH_SS_STATS:
1797 return SH_ETH_STATS_LEN;
1798 default:
1799 return -EOPNOTSUPP;
1800 }
1801}
1802
1803static void sh_eth_get_ethtool_stats(struct net_device *ndev,
1804 struct ethtool_stats *stats, u64 *data)
1805{
1806 struct sh_eth_private *mdp = netdev_priv(ndev);
1807 int i = 0;
1808
1809 /* device-specific stats */
1810 data[i++] = mdp->cur_rx;
1811 data[i++] = mdp->cur_tx;
1812 data[i++] = mdp->dirty_rx;
1813 data[i++] = mdp->dirty_tx;
1814}
1815
1816static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1817{
1818 switch (stringset) {
1819 case ETH_SS_STATS:
1820 memcpy(data, *sh_eth_gstrings_stats,
1821 sizeof(sh_eth_gstrings_stats));
1822 break;
1823 }
1824}
1825
525b8075
YS		 1826static void sh_eth_get_ringparam(struct net_device *ndev,
1827 struct ethtool_ringparam *ring)
1828{
1829 struct sh_eth_private *mdp = netdev_priv(ndev);
1830
1831 ring->rx_max_pending = RX_RING_MAX;
1832 ring->tx_max_pending = TX_RING_MAX;
1833 ring->rx_pending = mdp->num_rx_ring;
1834 ring->tx_pending = mdp->num_tx_ring;
1835}
1836
1837static int sh_eth_set_ringparam(struct net_device *ndev,
1838 struct ethtool_ringparam *ring)
1839{
1840 struct sh_eth_private *mdp = netdev_priv(ndev);
1841 int ret;
1842
1843 if (ring->tx_pending > TX_RING_MAX ||
1844 ring->rx_pending > RX_RING_MAX ||
1845 ring->tx_pending < TX_RING_MIN ||
1846 ring->rx_pending < RX_RING_MIN)
1847 return -EINVAL;
1848 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
1849 return -EINVAL;
1850
1851 if (netif_running(ndev)) {
1852 netif_tx_disable(ndev);
1853 /* Disable interrupts by clearing the interrupt mask. */
1854 sh_eth_write(ndev, 0x0000, EESIPR);
1855 /* Stop the chip's Tx and Rx processes. */
1856 sh_eth_write(ndev, 0, EDTRR);
1857 sh_eth_write(ndev, 0, EDRRR);
1858 synchronize_irq(ndev->irq);
1859 }
1860
1861 /* Free all the skbuffs in the Rx queue. */
1862 sh_eth_ring_free(ndev);
1863 /* Free DMA buffer */
1864 sh_eth_free_dma_buffer(mdp);
1865
1866 /* Set new parameters */
1867 mdp->num_rx_ring = ring->rx_pending;
1868 mdp->num_tx_ring = ring->tx_pending;
1869
1870 ret = sh_eth_ring_init(ndev);
1871 if (ret < 0) {
1872 dev_err(&ndev->dev, "%s: sh_eth_ring_init failed.\n", __func__);
1873 return ret;
1874 }
1875 ret = sh_eth_dev_init(ndev, false);
1876 if (ret < 0) {
1877 dev_err(&ndev->dev, "%s: sh_eth_dev_init failed.\n", __func__);
1878 return ret;
1879 }
1880
1881 if (netif_running(ndev)) {
1882 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1883 /* Setting the Rx mode will start the Rx process. */
1884 sh_eth_write(ndev, EDRRR_R, EDRRR);
1885 netif_wake_queue(ndev);
1886 }
1887
1888 return 0;
1889}
1890
9b07be4b 1891static const struct ethtool_ops sh_eth_ethtool_ops = {
dc19e4e5
NI		 1892 .get_settings = sh_eth_get_settings,
1893 .set_settings = sh_eth_set_settings,
9b07be4b 1894 .nway_reset = sh_eth_nway_reset,
dc19e4e5
NI		 1895 .get_msglevel = sh_eth_get_msglevel,
1896 .set_msglevel = sh_eth_set_msglevel,
9b07be4b 1897 .get_link = ethtool_op_get_link,
dc19e4e5
NI		 1898 .get_strings = sh_eth_get_strings,
1899 .get_ethtool_stats = sh_eth_get_ethtool_stats,
1900 .get_sset_count = sh_eth_get_sset_count,
525b8075
YS		 1901 .get_ringparam = sh_eth_get_ringparam,
1902 .set_ringparam = sh_eth_set_ringparam,
dc19e4e5
NI		 1903};
1904
86a74ff2
NI		 1905/* network device open function */
1906static int sh_eth_open(struct net_device *ndev)
1907{
1908 int ret = 0;
1909 struct sh_eth_private *mdp = netdev_priv(ndev);
1910
bcd5149d
MD		 1911 pm_runtime_get_sync(&mdp->pdev->dev);
1912
d2779e99
SS		 1913 napi_enable(&mdp->napi);
1914
a0607fd3 1915 ret = request_irq(ndev->irq, sh_eth_interrupt,
5b3dfd13 1916 mdp->cd->irq_flags, ndev->name, ndev);
86a74ff2 1917 if (ret) {
380af9e3 1918 dev_err(&ndev->dev, "Can not assign IRQ number\n");
d2779e99 1919 goto out_napi_off;
86a74ff2
NI		 1920 }
1921
1922 /* Descriptor set */
1923 ret = sh_eth_ring_init(ndev);
1924 if (ret)
1925 goto out_free_irq;
1926
1927 /* device init */
525b8075 1928 ret = sh_eth_dev_init(ndev, true);
86a74ff2
NI		 1929 if (ret)
1930 goto out_free_irq;
1931
1932 /* PHY control start*/
1933 ret = sh_eth_phy_start(ndev);
1934 if (ret)
1935 goto out_free_irq;
1936
86a74ff2
NI		 1937 return ret;
1938
1939out_free_irq:
1940 free_irq(ndev->irq, ndev);
d2779e99
SS		 1941out_napi_off:
1942 napi_disable(&mdp->napi);
bcd5149d 1943 pm_runtime_put_sync(&mdp->pdev->dev);
86a74ff2
NI		 1944 return ret;
1945}
1946
1947/* Timeout function */
1948static void sh_eth_tx_timeout(struct net_device *ndev)
1949{
1950 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 1951 struct sh_eth_rxdesc *rxdesc;
1952 int i;
1953
1954 netif_stop_queue(ndev);
1955
dc19e4e5
NI		 1956 if (netif_msg_timer(mdp))
1957 dev_err(&ndev->dev, "%s: transmit timed out, status %8.8x,"
4a55530f 1958 " resetting...\n", ndev->name, (int)sh_eth_read(ndev, EESR));
86a74ff2
NI		 1959
1960 /* tx_errors count up */
bb7d92e3 1961 ndev->stats.tx_errors++;
86a74ff2 1962
86a74ff2 1963 /* Free all the skbuffs in the Rx queue. */
525b8075 1964 for (i = 0; i < mdp->num_rx_ring; i++) {
86a74ff2
NI		 1965 rxdesc = &mdp->rx_ring[i];
1966 rxdesc->status = 0;
1967 rxdesc->addr = 0xBADF00D0;
1968 if (mdp->rx_skbuff[i])
1969 dev_kfree_skb(mdp->rx_skbuff[i]);
1970 mdp->rx_skbuff[i] = NULL;
1971 }
525b8075 1972 for (i = 0; i < mdp->num_tx_ring; i++) {
86a74ff2
NI		 1973 if (mdp->tx_skbuff[i])
1974 dev_kfree_skb(mdp->tx_skbuff[i]);
1975 mdp->tx_skbuff[i] = NULL;
1976 }
1977
1978 /* device init */
525b8075 1979 sh_eth_dev_init(ndev, true);
86a74ff2
NI		 1980}
1981
1982/* Packet transmit function */
1983static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1984{
1985 struct sh_eth_private *mdp = netdev_priv(ndev);
1986 struct sh_eth_txdesc *txdesc;
1987 u32 entry;
fb5e2f9b 1988 unsigned long flags;
86a74ff2
NI		 1989
1990 spin_lock_irqsave(&mdp->lock, flags);
525b8075 1991 if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
86a74ff2 1992 if (!sh_eth_txfree(ndev)) {
dc19e4e5
NI		 1993 if (netif_msg_tx_queued(mdp))
1994 dev_warn(&ndev->dev, "TxFD exhausted.\n");
86a74ff2
NI		 1995 netif_stop_queue(ndev);
1996 spin_unlock_irqrestore(&mdp->lock, flags);
5b548140 1997 return NETDEV_TX_BUSY;
86a74ff2
NI		 1998 }
1999 }
2000 spin_unlock_irqrestore(&mdp->lock, flags);
2001
525b8075 2002 entry = mdp->cur_tx % mdp->num_tx_ring;
86a74ff2
NI		 2003 mdp->tx_skbuff[entry] = skb;
2004 txdesc = &mdp->tx_ring[entry];
86a74ff2 2005 /* soft swap. */
380af9e3
YS		 2006 if (!mdp->cd->hw_swap)
2007 sh_eth_soft_swap(phys_to_virt(ALIGN(txdesc->addr, 4)),
2008 skb->len + 2);
31fcb99d
YS		 2009 txdesc->addr = dma_map_single(&ndev->dev, skb->data, skb->len,
2010 DMA_TO_DEVICE);
86a74ff2
NI		 2011 if (skb->len < ETHERSMALL)
2012 txdesc->buffer_length = ETHERSMALL;
2013 else
2014 txdesc->buffer_length = skb->len;
2015
525b8075 2016 if (entry >= mdp->num_tx_ring - 1)
71557a37 2017 txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE);
86a74ff2 2018 else
71557a37 2019 txdesc->status |= cpu_to_edmac(mdp, TD_TACT);
86a74ff2
NI		 2020
2021 mdp->cur_tx++;
2022
c5ed5368
YS		 2023 if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
2024 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
b0ca2a21 2025
6ed10654 2026 return NETDEV_TX_OK;
86a74ff2
NI		 2027}
2028
2029/* device close function */
2030static int sh_eth_close(struct net_device *ndev)
2031{
2032 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 2033
2034 netif_stop_queue(ndev);
2035
2036 /* Disable interrupts by clearing the interrupt mask. */
4a55530f 2037 sh_eth_write(ndev, 0x0000, EESIPR);
86a74ff2
NI		 2038
2039 /* Stop the chip's Tx and Rx processes. */
4a55530f
YS		 2040 sh_eth_write(ndev, 0, EDTRR);
2041 sh_eth_write(ndev, 0, EDRRR);
86a74ff2
NI		 2042
2043 /* PHY Disconnect */
2044 if (mdp->phydev) {
2045 phy_stop(mdp->phydev);
2046 phy_disconnect(mdp->phydev);
2047 }
2048
2049 free_irq(ndev->irq, ndev);
2050
d2779e99
SS		 2051 napi_disable(&mdp->napi);
2052
86a74ff2
NI		 2053 /* Free all the skbuffs in the Rx queue. */
2054 sh_eth_ring_free(ndev);
2055
2056 /* free DMA buffer */
91c77550 2057 sh_eth_free_dma_buffer(mdp);
86a74ff2 2058
bcd5149d
MD		 2059 pm_runtime_put_sync(&mdp->pdev->dev);
2060
86a74ff2
NI		 2061 return 0;
2062}
2063
2064static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
2065{
2066 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2 2067
bcd5149d
MD		 2068 pm_runtime_get_sync(&mdp->pdev->dev);
2069
bb7d92e3 2070 ndev->stats.tx_dropped += sh_eth_read(ndev, TROCR);
4a55530f 2071 sh_eth_write(ndev, 0, TROCR); /* (write clear) */
bb7d92e3 2072 ndev->stats.collisions += sh_eth_read(ndev, CDCR);
4a55530f 2073 sh_eth_write(ndev, 0, CDCR); /* (write clear) */
bb7d92e3 2074 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, LCCR);
4a55530f 2075 sh_eth_write(ndev, 0, LCCR); /* (write clear) */
c5ed5368 2076 if (sh_eth_is_gether(mdp)) {
bb7d92e3 2077 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CERCR);
c5ed5368 2078 sh_eth_write(ndev, 0, CERCR); /* (write clear) */
bb7d92e3 2079 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CEECR);
c5ed5368
YS		 2080 sh_eth_write(ndev, 0, CEECR); /* (write clear) */
2081 } else {
bb7d92e3 2082 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CNDCR);
c5ed5368
YS		 2083 sh_eth_write(ndev, 0, CNDCR); /* (write clear) */
2084 }
bcd5149d
MD		 2085 pm_runtime_put_sync(&mdp->pdev->dev);
2086
bb7d92e3 2087 return &ndev->stats;
86a74ff2
NI		 2088}
2089
bb7d92e3 2090/* ioctl to device function */
86a74ff2
NI		 2091static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq,
2092 int cmd)
2093{
2094 struct sh_eth_private *mdp = netdev_priv(ndev);
2095 struct phy_device *phydev = mdp->phydev;
2096
2097 if (!netif_running(ndev))
2098 return -EINVAL;
2099
2100 if (!phydev)
2101 return -ENODEV;
2102
28b04113 2103 return phy_mii_ioctl(phydev, rq, cmd);
86a74ff2
NI		 2104}
2105
6743fe6d
YS		 2106/* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
2107static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp,
2108 int entry)
2109{
2110 return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4);
2111}
2112
2113static u32 sh_eth_tsu_get_post_mask(int entry)
2114{
2115 return 0x0f << (28 - ((entry % 8) * 4));
2116}
2117
2118static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
2119{
2120 return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
2121}
2122
2123static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
2124 int entry)
2125{
2126 struct sh_eth_private *mdp = netdev_priv(ndev);
2127 u32 tmp;
2128 void *reg_offset;
2129
2130 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2131 tmp = ioread32(reg_offset);
2132 iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset);
2133}
2134
2135static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
2136 int entry)
2137{
2138 struct sh_eth_private *mdp = netdev_priv(ndev);
2139 u32 post_mask, ref_mask, tmp;
2140 void *reg_offset;
2141
2142 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2143 post_mask = sh_eth_tsu_get_post_mask(entry);
2144 ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
2145
2146 tmp = ioread32(reg_offset);
2147 iowrite32(tmp & ~post_mask, reg_offset);
2148
2149 /* If other port enables, the function returns "true" */
2150 return tmp & ref_mask;
2151}
2152
2153static int sh_eth_tsu_busy(struct net_device *ndev)
2154{
2155 int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
2156 struct sh_eth_private *mdp = netdev_priv(ndev);
2157
2158 while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
2159 udelay(10);
2160 timeout--;
2161 if (timeout <= 0) {
2162 dev_err(&ndev->dev, "%s: timeout\n", __func__);
2163 return -ETIMEDOUT;
2164 }
2165 }
2166
2167 return 0;
2168}
2169
2170static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg,
2171 const u8 *addr)
2172{
2173 u32 val;
2174
2175 val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
2176 iowrite32(val, reg);
2177 if (sh_eth_tsu_busy(ndev) < 0)
2178 return -EBUSY;
2179
2180 val = addr[4] << 8 | addr[5];
2181 iowrite32(val, reg + 4);
2182 if (sh_eth_tsu_busy(ndev) < 0)
2183 return -EBUSY;
2184
2185 return 0;
2186}
2187
2188static void sh_eth_tsu_read_entry(void *reg, u8 *addr)
2189{
2190 u32 val;
2191
2192 val = ioread32(reg);
2193 addr[0] = (val >> 24) & 0xff;
2194 addr[1] = (val >> 16) & 0xff;
2195 addr[2] = (val >> 8) & 0xff;
2196 addr[3] = val & 0xff;
2197 val = ioread32(reg + 4);
2198 addr[4] = (val >> 8) & 0xff;
2199 addr[5] = val & 0xff;
2200}
2201
2202
2203static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
2204{
2205 struct sh_eth_private *mdp = netdev_priv(ndev);
2206 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2207 int i;
2208 u8 c_addr[ETH_ALEN];
2209
2210 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2211 sh_eth_tsu_read_entry(reg_offset, c_addr);
2212 if (memcmp(addr, c_addr, ETH_ALEN) == 0)
2213 return i;
2214 }
2215
2216 return -ENOENT;
2217}
2218
2219static int sh_eth_tsu_find_empty(struct net_device *ndev)
2220{
2221 u8 blank[ETH_ALEN];
2222 int entry;
2223
2224 memset(blank, 0, sizeof(blank));
2225 entry = sh_eth_tsu_find_entry(ndev, blank);
2226 return (entry < 0) ? -ENOMEM : entry;
2227}
2228
2229static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
2230 int entry)
2231{
2232 struct sh_eth_private *mdp = netdev_priv(ndev);
2233 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2234 int ret;
2235 u8 blank[ETH_ALEN];
2236
2237 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
2238 ~(1 << (31 - entry)), TSU_TEN);
2239
2240 memset(blank, 0, sizeof(blank));
2241 ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
2242 if (ret < 0)
2243 return ret;
2244 return 0;
2245}
2246
2247static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
2248{
2249 struct sh_eth_private *mdp = netdev_priv(ndev);
2250 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2251 int i, ret;
2252
2253 if (!mdp->cd->tsu)
2254 return 0;
2255
2256 i = sh_eth_tsu_find_entry(ndev, addr);
2257 if (i < 0) {
2258 /* No entry found, create one */
2259 i = sh_eth_tsu_find_empty(ndev);
2260 if (i < 0)
2261 return -ENOMEM;
2262 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
2263 if (ret < 0)
2264 return ret;
2265
2266 /* Enable the entry */
2267 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
2268 (1 << (31 - i)), TSU_TEN);
2269 }
2270
2271 /* Entry found or created, enable POST */
2272 sh_eth_tsu_enable_cam_entry_post(ndev, i);
2273
2274 return 0;
2275}
2276
2277static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
2278{
2279 struct sh_eth_private *mdp = netdev_priv(ndev);
2280 int i, ret;
2281
2282 if (!mdp->cd->tsu)
2283 return 0;
2284
2285 i = sh_eth_tsu_find_entry(ndev, addr);
2286 if (i) {
2287 /* Entry found */
2288 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2289 goto done;
2290
2291 /* Disable the entry if both ports was disabled */
2292 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2293 if (ret < 0)
2294 return ret;
2295 }
2296done:
2297 return 0;
2298}
2299
2300static int sh_eth_tsu_purge_all(struct net_device *ndev)
2301{
2302 struct sh_eth_private *mdp = netdev_priv(ndev);
2303 int i, ret;
2304
2305 if (unlikely(!mdp->cd->tsu))
2306 return 0;
2307
2308 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
2309 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2310 continue;
2311
2312 /* Disable the entry if both ports was disabled */
2313 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2314 if (ret < 0)
2315 return ret;
2316 }
2317
2318 return 0;
2319}
2320
2321static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
2322{
2323 struct sh_eth_private *mdp = netdev_priv(ndev);
2324 u8 addr[ETH_ALEN];
2325 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2326 int i;
2327
2328 if (unlikely(!mdp->cd->tsu))
2329 return;
2330
2331 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2332 sh_eth_tsu_read_entry(reg_offset, addr);
2333 if (is_multicast_ether_addr(addr))
2334 sh_eth_tsu_del_entry(ndev, addr);
2335 }
2336}
2337
86a74ff2
NI		 2338/* Multicast reception directions set */
2339static void sh_eth_set_multicast_list(struct net_device *ndev)
2340{
6743fe6d
YS		 2341 struct sh_eth_private *mdp = netdev_priv(ndev);
2342 u32 ecmr_bits;
2343 int mcast_all = 0;
2344 unsigned long flags;
2345
2346 spin_lock_irqsave(&mdp->lock, flags);
2347 /*
2348 * Initial condition is MCT = 1, PRM = 0.
2349 * Depending on ndev->flags, set PRM or clear MCT
2350 */
2351 ecmr_bits = (sh_eth_read(ndev, ECMR) & ~ECMR_PRM) | ECMR_MCT;
2352
2353 if (!(ndev->flags & IFF_MULTICAST)) {
2354 sh_eth_tsu_purge_mcast(ndev);
2355 mcast_all = 1;
2356 }
2357 if (ndev->flags & IFF_ALLMULTI) {
2358 sh_eth_tsu_purge_mcast(ndev);
2359 ecmr_bits &= ~ECMR_MCT;
2360 mcast_all = 1;
2361 }
2362
86a74ff2 2363 if (ndev->flags & IFF_PROMISC) {
6743fe6d
YS		 2364 sh_eth_tsu_purge_all(ndev);
2365 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2366 } else if (mdp->cd->tsu) {
2367 struct netdev_hw_addr *ha;
2368 netdev_for_each_mc_addr(ha, ndev) {
2369 if (mcast_all && is_multicast_ether_addr(ha->addr))
2370 continue;
2371
2372 if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2373 if (!mcast_all) {
2374 sh_eth_tsu_purge_mcast(ndev);
2375 ecmr_bits &= ~ECMR_MCT;
2376 mcast_all = 1;
2377 }
2378 }
2379 }
86a74ff2
NI		 2380 } else {
2381 /* Normal, unicast/broadcast-only mode. */
6743fe6d 2382 ecmr_bits = (ecmr_bits & ~ECMR_PRM) | ECMR_MCT;
86a74ff2 2383 }
6743fe6d
YS		 2384
2385 /* update the ethernet mode */
2386 sh_eth_write(ndev, ecmr_bits, ECMR);
2387
2388 spin_unlock_irqrestore(&mdp->lock, flags);
86a74ff2 2389}
71cc7c37
YS		 2390
2391static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2392{
2393 if (!mdp->port)
2394 return TSU_VTAG0;
2395 else
2396 return TSU_VTAG1;
2397}
2398
80d5c368
PM		 2399static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
2400 __be16 proto, u16 vid)
71cc7c37
YS		 2401{
2402 struct sh_eth_private *mdp = netdev_priv(ndev);
2403 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2404
2405 if (unlikely(!mdp->cd->tsu))
2406 return -EPERM;
2407
2408 /* No filtering if vid = 0 */
2409 if (!vid)
2410 return 0;
2411
2412 mdp->vlan_num_ids++;
2413
2414 /*
2415 * The controller has one VLAN tag HW filter. So, if the filter is
2416 * already enabled, the driver disables it and the filte
2417 */
2418 if (mdp->vlan_num_ids > 1) {
2419 /* disable VLAN filter */
2420 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2421 return 0;
2422 }
2423
2424 sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
2425 vtag_reg_index);
2426
2427 return 0;
2428}
2429
80d5c368
PM		 2430static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
2431 __be16 proto, u16 vid)
71cc7c37
YS		 2432{
2433 struct sh_eth_private *mdp = netdev_priv(ndev);
2434 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2435
2436 if (unlikely(!mdp->cd->tsu))
2437 return -EPERM;
2438
2439 /* No filtering if vid = 0 */
2440 if (!vid)
2441 return 0;
2442
2443 mdp->vlan_num_ids--;
2444 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2445
2446 return 0;
2447}
86a74ff2
NI		 2448
2449/* SuperH's TSU register init function */
4a55530f 2450static void sh_eth_tsu_init(struct sh_eth_private *mdp)
86a74ff2 2451{
4a55530f
YS		 2452 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */
2453 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */
2454 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */
2455 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
2456 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
2457 sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
2458 sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
2459 sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
2460 sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
2461 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
c5ed5368
YS		 2462 if (sh_eth_is_gether(mdp)) {
2463 sh_eth_tsu_write(mdp, 0, TSU_QTAG0); /* Disable QTAG(0->1) */
2464 sh_eth_tsu_write(mdp, 0, TSU_QTAG1); /* Disable QTAG(1->0) */
2465 } else {
2466 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */
2467 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */
2468 }
4a55530f
YS		 2469 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */
2470 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */
2471 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2472 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */
2473 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */
2474 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */
2475 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */
86a74ff2
NI		 2476}
2477
2478/* MDIO bus release function */
2479static int sh_mdio_release(struct net_device *ndev)
2480{
2481 struct mii_bus *bus = dev_get_drvdata(&ndev->dev);
2482
2483 /* unregister mdio bus */
2484 mdiobus_unregister(bus);
2485
2486 /* remove mdio bus info from net_device */
2487 dev_set_drvdata(&ndev->dev, NULL);
2488
2489 /* free bitbang info */
2490 free_mdio_bitbang(bus);
2491
2492 return 0;
2493}
2494
2495/* MDIO bus init function */
b3017e6a
YS		 2496static int sh_mdio_init(struct net_device *ndev, int id,
2497 struct sh_eth_plat_data *pd)
86a74ff2
NI		 2498{
2499 int ret, i;
2500 struct bb_info *bitbang;
2501 struct sh_eth_private *mdp = netdev_priv(ndev);
2502
2503 /* create bit control struct for PHY */
d5e07e69
SS		 2504 bitbang = devm_kzalloc(&ndev->dev, sizeof(struct bb_info),
2505 GFP_KERNEL);
86a74ff2
NI		 2506 if (!bitbang) {
2507 ret = -ENOMEM;
2508 goto out;
2509 }
2510
2511 /* bitbang init */
ae70644d 2512 bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
b3017e6a 2513 bitbang->set_gate = pd->set_mdio_gate;
dfed5e7f
SS		 2514 bitbang->mdi_msk = PIR_MDI;
2515 bitbang->mdo_msk = PIR_MDO;
2516 bitbang->mmd_msk = PIR_MMD;
2517 bitbang->mdc_msk = PIR_MDC;
86a74ff2
NI		 2518 bitbang->ctrl.ops = &bb_ops;
2519
c2e07b3a 2520 /* MII controller setting */
86a74ff2
NI		 2521 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
2522 if (!mdp->mii_bus) {
2523 ret = -ENOMEM;
d5e07e69 2524 goto out;
86a74ff2
NI		 2525 }
2526
2527 /* Hook up MII support for ethtool */
2528 mdp->mii_bus->name = "sh_mii";
18ee49dd 2529 mdp->mii_bus->parent = &ndev->dev;
5278fb54 2530 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
34aa6f14 2531 mdp->pdev->name, id);
86a74ff2
NI		 2532
2533 /* PHY IRQ */
d5e07e69
SS		 2534 mdp->mii_bus->irq = devm_kzalloc(&ndev->dev,
2535 sizeof(int) * PHY_MAX_ADDR,
2536 GFP_KERNEL);
86a74ff2
NI		 2537 if (!mdp->mii_bus->irq) {
2538 ret = -ENOMEM;
2539 goto out_free_bus;
2540 }
2541
2542 for (i = 0; i < PHY_MAX_ADDR; i++)
2543 mdp->mii_bus->irq[i] = PHY_POLL;
2544
8f6352f2 2545 /* register mdio bus */
86a74ff2
NI		 2546 ret = mdiobus_register(mdp->mii_bus);
2547 if (ret)
d5e07e69 2548 goto out_free_bus;
86a74ff2
NI		 2549
2550 dev_set_drvdata(&ndev->dev, mdp->mii_bus);
2551
2552 return 0;
2553
86a74ff2 2554out_free_bus:
298cf9be 2555 free_mdio_bitbang(mdp->mii_bus);
86a74ff2 2556
86a74ff2
NI		 2557out:
2558 return ret;
2559}
2560
4a55530f
YS		 2561static const u16 *sh_eth_get_register_offset(int register_type)
2562{
2563 const u16 *reg_offset = NULL;
2564
2565 switch (register_type) {
2566 case SH_ETH_REG_GIGABIT:
2567 reg_offset = sh_eth_offset_gigabit;
2568 break;
a3f109bd
SS		 2569 case SH_ETH_REG_FAST_RCAR:
2570 reg_offset = sh_eth_offset_fast_rcar;
2571 break;
4a55530f
YS		 2572 case SH_ETH_REG_FAST_SH4:
2573 reg_offset = sh_eth_offset_fast_sh4;
2574 break;
2575 case SH_ETH_REG_FAST_SH3_SH2:
2576 reg_offset = sh_eth_offset_fast_sh3_sh2;
2577 break;
2578 default:
14c3326a 2579 pr_err("Unknown register type (%d)\n", register_type);
4a55530f
YS		 2580 break;
2581 }
2582
2583 return reg_offset;
2584}
2585
8f728d79 2586static const struct net_device_ops sh_eth_netdev_ops = {
ebf84eaa
AB		 2587 .ndo_open = sh_eth_open,
2588 .ndo_stop = sh_eth_close,
2589 .ndo_start_xmit = sh_eth_start_xmit,
2590 .ndo_get_stats = sh_eth_get_stats,
ebf84eaa
AB		 2591 .ndo_tx_timeout = sh_eth_tx_timeout,
2592 .ndo_do_ioctl = sh_eth_do_ioctl,
2593 .ndo_validate_addr = eth_validate_addr,
2594 .ndo_set_mac_address = eth_mac_addr,
2595 .ndo_change_mtu = eth_change_mtu,
2596};
2597
8f728d79
SS		 2598static const struct net_device_ops sh_eth_netdev_ops_tsu = {
2599 .ndo_open = sh_eth_open,
2600 .ndo_stop = sh_eth_close,
2601 .ndo_start_xmit = sh_eth_start_xmit,
2602 .ndo_get_stats = sh_eth_get_stats,
2603 .ndo_set_rx_mode = sh_eth_set_multicast_list,
2604 .ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid,
2605 .ndo_vlan_rx_kill_vid = sh_eth_vlan_rx_kill_vid,
2606 .ndo_tx_timeout = sh_eth_tx_timeout,
2607 .ndo_do_ioctl = sh_eth_do_ioctl,
2608 .ndo_validate_addr = eth_validate_addr,
2609 .ndo_set_mac_address = eth_mac_addr,
2610 .ndo_change_mtu = eth_change_mtu,
2611};
2612
86a74ff2
NI		 2613static int sh_eth_drv_probe(struct platform_device *pdev)
2614{
9c38657c 2615 int ret, devno = 0;
86a74ff2
NI		 2616 struct resource *res;
2617 struct net_device *ndev = NULL;
ec0d7551 2618 struct sh_eth_private *mdp = NULL;
0b76b862 2619 struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev);
afe391ad 2620 const struct platform_device_id *id = platform_get_device_id(pdev);
86a74ff2
NI		 2621
2622 /* get base addr */
2623 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2624 if (unlikely(res == NULL)) {
2625 dev_err(&pdev->dev, "invalid resource\n");
2626 ret = -EINVAL;
2627 goto out;
2628 }
2629
2630 ndev = alloc_etherdev(sizeof(struct sh_eth_private));
2631 if (!ndev) {
86a74ff2
NI		 2632 ret = -ENOMEM;
2633 goto out;
2634 }
2635
2636 /* The sh Ether-specific entries in the device structure. */
2637 ndev->base_addr = res->start;
2638 devno = pdev->id;
2639 if (devno < 0)
2640 devno = 0;
2641
2642 ndev->dma = -1;
cc3c080d 2643 ret = platform_get_irq(pdev, 0);
2644 if (ret < 0) {
86a74ff2
NI		 2645 ret = -ENODEV;
2646 goto out_release;
2647 }
cc3c080d 2648 ndev->irq = ret;
86a74ff2
NI		 2649
2650 SET_NETDEV_DEV(ndev, &pdev->dev);
2651
86a74ff2 2652 mdp = netdev_priv(ndev);
525b8075
YS		 2653 mdp->num_tx_ring = TX_RING_SIZE;
2654 mdp->num_rx_ring = RX_RING_SIZE;
d5e07e69
SS		 2655 mdp->addr = devm_ioremap_resource(&pdev->dev, res);
2656 if (IS_ERR(mdp->addr)) {
2657 ret = PTR_ERR(mdp->addr);
ae70644d
YS		 2658 goto out_release;
2659 }
2660
86a74ff2 2661 spin_lock_init(&mdp->lock);
bcd5149d
MD		 2662 mdp->pdev = pdev;
2663 pm_runtime_enable(&pdev->dev);
2664 pm_runtime_resume(&pdev->dev);
86a74ff2
NI		 2665
2666 /* get PHY ID */
71557a37 2667 mdp->phy_id = pd->phy;
e47c9052 2668 mdp->phy_interface = pd->phy_interface;
71557a37
YS		 2669 /* EDMAC endian */
2670 mdp->edmac_endian = pd->edmac_endian;
4923576b
YS		 2671 mdp->no_ether_link = pd->no_ether_link;
2672 mdp->ether_link_active_low = pd->ether_link_active_low;
86a74ff2 2673
380af9e3 2674 /* set cpu data */
589ebdef 2675 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data;
a3153d8c 2676 mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type);
380af9e3
YS		 2677 sh_eth_set_default_cpu_data(mdp->cd);
2678
86a74ff2 2679 /* set function */
8f728d79
SS		 2680 if (mdp->cd->tsu)
2681 ndev->netdev_ops = &sh_eth_netdev_ops_tsu;
2682 else
2683 ndev->netdev_ops = &sh_eth_netdev_ops;
dc19e4e5 2684 SET_ETHTOOL_OPS(ndev, &sh_eth_ethtool_ops);
86a74ff2
NI		 2685 ndev->watchdog_timeo = TX_TIMEOUT;
2686
dc19e4e5
NI		 2687 /* debug message level */
2688 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
86a74ff2
NI		 2689
2690 /* read and set MAC address */
748031f9 2691 read_mac_address(ndev, pd->mac_addr);
ff6e7228
SS		 2692 if (!is_valid_ether_addr(ndev->dev_addr)) {
2693 dev_warn(&pdev->dev,
2694 "no valid MAC address supplied, using a random one.\n");
2695 eth_hw_addr_random(ndev);
2696 }
86a74ff2 2697
6ba88021
YS		 2698 /* ioremap the TSU registers */
2699 if (mdp->cd->tsu) {
2700 struct resource *rtsu;
2701 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
d5e07e69
SS		 2702 mdp->tsu_addr = devm_ioremap_resource(&pdev->dev, rtsu);
2703 if (IS_ERR(mdp->tsu_addr)) {
2704 ret = PTR_ERR(mdp->tsu_addr);
fc0c0900
SS		 2705 goto out_release;
2706 }
6743fe6d 2707 mdp->port = devno % 2;
f646968f 2708 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER;
6ba88021
YS		 2709 }
2710
150647fb
YS		 2711 /* initialize first or needed device */
2712 if (!devno || pd->needs_init) {
380af9e3
YS		 2713 if (mdp->cd->chip_reset)
2714 mdp->cd->chip_reset(ndev);
86a74ff2 2715
4986b996
YS		 2716 if (mdp->cd->tsu) {
2717 /* TSU init (Init only)*/
2718 sh_eth_tsu_init(mdp);
2719 }
86a74ff2
NI		 2720 }
2721
3719109d
SS		 2722 netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64);
2723
86a74ff2
NI		 2724 /* network device register */
2725 ret = register_netdev(ndev);
2726 if (ret)
3719109d 2727 goto out_napi_del;
86a74ff2
NI		 2728
2729 /* mdio bus init */
b3017e6a 2730 ret = sh_mdio_init(ndev, pdev->id, pd);
86a74ff2
NI		 2731 if (ret)
2732 goto out_unregister;
2733
25985edc 2734 /* print device information */
6cd9b49d
HS		 2735 pr_info("Base address at 0x%x, %pM, IRQ %d.\n",
2736 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
86a74ff2
NI		 2737
2738 platform_set_drvdata(pdev, ndev);
2739
2740 return ret;
2741
2742out_unregister:
2743 unregister_netdev(ndev);
2744
3719109d
SS		 2745out_napi_del:
2746 netif_napi_del(&mdp->napi);
2747
86a74ff2
NI		 2748out_release:
2749 /* net_dev free */
2750 if (ndev)
2751 free_netdev(ndev);
2752
2753out:
2754 return ret;
2755}
2756
2757static int sh_eth_drv_remove(struct platform_device *pdev)
2758{
2759 struct net_device *ndev = platform_get_drvdata(pdev);
3719109d 2760 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 2761
2762 sh_mdio_release(ndev);
2763 unregister_netdev(ndev);
3719109d 2764 netif_napi_del(&mdp->napi);
bcd5149d 2765 pm_runtime_disable(&pdev->dev);
86a74ff2 2766 free_netdev(ndev);
86a74ff2
NI		 2767
2768 return 0;
2769}
2770
540ad1b8 2771#ifdef CONFIG_PM
bcd5149d
MD		 2772static int sh_eth_runtime_nop(struct device *dev)
2773{
2774 /*
2775 * Runtime PM callback shared between ->runtime_suspend()
2776 * and ->runtime_resume(). Simply returns success.
2777 *
2778 * This driver re-initializes all registers after
2779 * pm_runtime_get_sync() anyway so there is no need
2780 * to save and restore registers here.
2781 */
2782 return 0;
2783}
2784
540ad1b8 2785static const struct dev_pm_ops sh_eth_dev_pm_ops = {
bcd5149d
MD		 2786 .runtime_suspend = sh_eth_runtime_nop,
2787 .runtime_resume = sh_eth_runtime_nop,
2788};
540ad1b8
NI		 2789#define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
2790#else
2791#define SH_ETH_PM_OPS NULL
2792#endif
bcd5149d 2793
afe391ad 2794static struct platform_device_id sh_eth_id_table[] = {
c18a79ab 2795 { "sh7619-ether", (kernel_ulong_t)&sh7619_data },
7bbe150d 2796 { "sh771x-ether", (kernel_ulong_t)&sh771x_data },
9c3beaab 2797 { "sh7724-ether", (kernel_ulong_t)&sh7724_data },
f5d12767 2798 { "sh7734-gether", (kernel_ulong_t)&sh7734_data },
24549e2a
SS		 2799 { "sh7757-ether", (kernel_ulong_t)&sh7757_data },
2800 { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga },
f5d12767 2801 { "sh7763-gether", (kernel_ulong_t)&sh7763_data },
e5c9b4cd 2802 { "r8a7740-gether", (kernel_ulong_t)&r8a7740_data },
589ebdef 2803 { "r8a777x-ether", (kernel_ulong_t)&r8a777x_data },
e18dbf7e 2804 { "r8a7790-ether", (kernel_ulong_t)&r8a7790_data },
afe391ad
SS		 2805 { }
2806};
2807MODULE_DEVICE_TABLE(platform, sh_eth_id_table);
2808
86a74ff2
NI		 2809static struct platform_driver sh_eth_driver = {
2810 .probe = sh_eth_drv_probe,
2811 .remove = sh_eth_drv_remove,
afe391ad 2812 .id_table = sh_eth_id_table,
86a74ff2
NI		 2813 .driver = {
2814 .name = CARDNAME,
540ad1b8 2815 .pm = SH_ETH_PM_OPS,
86a74ff2
NI		 2816 },
2817};
2818
db62f684 2819module_platform_driver(sh_eth_driver);
86a74ff2
NI		 2820
2821MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
2822MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
2823MODULE_LICENSE("GPL v2");
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