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sh_eth: use TSU register accessors for TSU_POST<n>
[mirror_ubuntu-hirsute-kernel.git] / drivers / net / ethernet / renesas / sh_eth.c
CommitLineData
128296fc 1/* SuperH Ethernet device driver
86a74ff2 2 *
9b39f05c 3 * Copyright (C) 2014 Renesas Electronics Corporation
f0e81fec 4 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu
b356e978 5 * Copyright (C) 2008-2014 Renesas Solutions Corp.
9b39f05c 6 * Copyright (C) 2013-2017 Cogent Embedded, Inc.
702eca02 7 * Copyright (C) 2014 Codethink Limited
86a74ff2
NI		 8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms and conditions of the GNU General Public License,
11 * version 2, as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
86a74ff2
NI		 17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 */
21
0654011d
YS		 22#include <linux/module.h>
23#include <linux/kernel.h>
24#include <linux/spinlock.h>
6a27cded 25#include <linux/interrupt.h>
86a74ff2
NI		 26#include <linux/dma-mapping.h>
27#include <linux/etherdevice.h>
28#include <linux/delay.h>
29#include <linux/platform_device.h>
30#include <linux/mdio-bitbang.h>
31#include <linux/netdevice.h>
b356e978
SS		 32#include <linux/of.h>
33#include <linux/of_device.h>
34#include <linux/of_irq.h>
35#include <linux/of_net.h>
86a74ff2
NI		 36#include <linux/phy.h>
37#include <linux/cache.h>
38#include <linux/io.h>
bcd5149d 39#include <linux/pm_runtime.h>
5a0e3ad6 40#include <linux/slab.h>
dc19e4e5 41#include <linux/ethtool.h>
fdb37a7f 42#include <linux/if_vlan.h>
d4fa0e35 43#include <linux/sh_eth.h>
702eca02 44#include <linux/of_mdio.h>
86a74ff2
NI		 45
46#include "sh_eth.h"
47
dc19e4e5
NI		 48#define SH_ETH_DEF_MSG_ENABLE \
49 (NETIF_MSG_LINK | \
50 NETIF_MSG_TIMER | \
51 NETIF_MSG_RX_ERR| \
52 NETIF_MSG_TX_ERR)
53
2274d375
SS		 54#define SH_ETH_OFFSET_INVALID ((u16)~0)
55
3365711d
BH		 56#define SH_ETH_OFFSET_DEFAULTS \
57 [0 ... SH_ETH_MAX_REGISTER_OFFSET - 1] = SH_ETH_OFFSET_INVALID
58
c0013f6f 59static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
3365711d
BH		 60 SH_ETH_OFFSET_DEFAULTS,
61
c0013f6f
SS		 62 [EDSR] = 0x0000,
63 [EDMR] = 0x0400,
64 [EDTRR] = 0x0408,
65 [EDRRR] = 0x0410,
66 [EESR] = 0x0428,
67 [EESIPR] = 0x0430,
68 [TDLAR] = 0x0010,
69 [TDFAR] = 0x0014,
70 [TDFXR] = 0x0018,
71 [TDFFR] = 0x001c,
72 [RDLAR] = 0x0030,
73 [RDFAR] = 0x0034,
74 [RDFXR] = 0x0038,
75 [RDFFR] = 0x003c,
76 [TRSCER] = 0x0438,
77 [RMFCR] = 0x0440,
78 [TFTR] = 0x0448,
79 [FDR] = 0x0450,
80 [RMCR] = 0x0458,
81 [RPADIR] = 0x0460,
82 [FCFTR] = 0x0468,
83 [CSMR] = 0x04E4,
84
85 [ECMR] = 0x0500,
86 [ECSR] = 0x0510,
87 [ECSIPR] = 0x0518,
88 [PIR] = 0x0520,
89 [PSR] = 0x0528,
90 [PIPR] = 0x052c,
91 [RFLR] = 0x0508,
92 [APR] = 0x0554,
93 [MPR] = 0x0558,
94 [PFTCR] = 0x055c,
95 [PFRCR] = 0x0560,
96 [TPAUSER] = 0x0564,
97 [GECMR] = 0x05b0,
98 [BCULR] = 0x05b4,
99 [MAHR] = 0x05c0,
100 [MALR] = 0x05c8,
101 [TROCR] = 0x0700,
102 [CDCR] = 0x0708,
103 [LCCR] = 0x0710,
104 [CEFCR] = 0x0740,
105 [FRECR] = 0x0748,
106 [TSFRCR] = 0x0750,
107 [TLFRCR] = 0x0758,
108 [RFCR] = 0x0760,
109 [CERCR] = 0x0768,
110 [CEECR] = 0x0770,
111 [MAFCR] = 0x0778,
112 [RMII_MII] = 0x0790,
113
114 [ARSTR] = 0x0000,
115 [TSU_CTRST] = 0x0004,
116 [TSU_FWEN0] = 0x0010,
117 [TSU_FWEN1] = 0x0014,
118 [TSU_FCM] = 0x0018,
119 [TSU_BSYSL0] = 0x0020,
120 [TSU_BSYSL1] = 0x0024,
121 [TSU_PRISL0] = 0x0028,
122 [TSU_PRISL1] = 0x002c,
123 [TSU_FWSL0] = 0x0030,
124 [TSU_FWSL1] = 0x0034,
125 [TSU_FWSLC] = 0x0038,
4869a147
SS		 126 [TSU_QTAGM0] = 0x0040,
127 [TSU_QTAGM1] = 0x0044,
c0013f6f
SS		 128 [TSU_FWSR] = 0x0050,
129 [TSU_FWINMK] = 0x0054,
130 [TSU_ADQT0] = 0x0048,
131 [TSU_ADQT1] = 0x004c,
132 [TSU_VTAG0] = 0x0058,
133 [TSU_VTAG1] = 0x005c,
134 [TSU_ADSBSY] = 0x0060,
135 [TSU_TEN] = 0x0064,
136 [TSU_POST1] = 0x0070,
137 [TSU_POST2] = 0x0074,
138 [TSU_POST3] = 0x0078,
139 [TSU_POST4] = 0x007c,
140 [TSU_ADRH0] = 0x0100,
c0013f6f
SS		 141
142 [TXNLCR0] = 0x0080,
143 [TXALCR0] = 0x0084,
144 [RXNLCR0] = 0x0088,
145 [RXALCR0] = 0x008c,
146 [FWNLCR0] = 0x0090,
147 [FWALCR0] = 0x0094,
148 [TXNLCR1] = 0x00a0,
50f3d740 149 [TXALCR1] = 0x00a4,
c0013f6f
SS		 150 [RXNLCR1] = 0x00a8,
151 [RXALCR1] = 0x00ac,
152 [FWNLCR1] = 0x00b0,
153 [FWALCR1] = 0x00b4,
154};
155
db893473 156static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
3365711d
BH		 157 SH_ETH_OFFSET_DEFAULTS,
158
db893473
SH		 159 [EDSR] = 0x0000,
160 [EDMR] = 0x0400,
161 [EDTRR] = 0x0408,
162 [EDRRR] = 0x0410,
163 [EESR] = 0x0428,
164 [EESIPR] = 0x0430,
165 [TDLAR] = 0x0010,
166 [TDFAR] = 0x0014,
167 [TDFXR] = 0x0018,
168 [TDFFR] = 0x001c,
169 [RDLAR] = 0x0030,
170 [RDFAR] = 0x0034,
171 [RDFXR] = 0x0038,
172 [RDFFR] = 0x003c,
173 [TRSCER] = 0x0438,
174 [RMFCR] = 0x0440,
175 [TFTR] = 0x0448,
176 [FDR] = 0x0450,
177 [RMCR] = 0x0458,
178 [RPADIR] = 0x0460,
179 [FCFTR] = 0x0468,
180 [CSMR] = 0x04E4,
181
182 [ECMR] = 0x0500,
183 [RFLR] = 0x0508,
184 [ECSR] = 0x0510,
185 [ECSIPR] = 0x0518,
186 [PIR] = 0x0520,
187 [APR] = 0x0554,
188 [MPR] = 0x0558,
189 [PFTCR] = 0x055c,
190 [PFRCR] = 0x0560,
191 [TPAUSER] = 0x0564,
192 [MAHR] = 0x05c0,
193 [MALR] = 0x05c8,
194 [CEFCR] = 0x0740,
195 [FRECR] = 0x0748,
196 [TSFRCR] = 0x0750,
197 [TLFRCR] = 0x0758,
198 [RFCR] = 0x0760,
199 [MAFCR] = 0x0778,
200
201 [ARSTR] = 0x0000,
202 [TSU_CTRST] = 0x0004,
e1487888 203 [TSU_FWSLC] = 0x0038,
db893473
SH		 204 [TSU_VTAG0] = 0x0058,
205 [TSU_ADSBSY] = 0x0060,
206 [TSU_TEN] = 0x0064,
e1487888
CB		 207 [TSU_POST1] = 0x0070,
208 [TSU_POST2] = 0x0074,
209 [TSU_POST3] = 0x0078,
210 [TSU_POST4] = 0x007c,
db893473 211 [TSU_ADRH0] = 0x0100,
db893473
SH		 212
213 [TXNLCR0] = 0x0080,
214 [TXALCR0] = 0x0084,
215 [RXNLCR0] = 0x0088,
216 [RXALCR0] = 0x008C,
217};
218
a3f109bd 219static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
3365711d
BH		 220 SH_ETH_OFFSET_DEFAULTS,
221
a3f109bd
SS		 222 [ECMR] = 0x0300,
223 [RFLR] = 0x0308,
224 [ECSR] = 0x0310,
225 [ECSIPR] = 0x0318,
226 [PIR] = 0x0320,
227 [PSR] = 0x0328,
228 [RDMLR] = 0x0340,
229 [IPGR] = 0x0350,
230 [APR] = 0x0354,
231 [MPR] = 0x0358,
232 [RFCF] = 0x0360,
233 [TPAUSER] = 0x0364,
234 [TPAUSECR] = 0x0368,
235 [MAHR] = 0x03c0,
236 [MALR] = 0x03c8,
237 [TROCR] = 0x03d0,
238 [CDCR] = 0x03d4,
239 [LCCR] = 0x03d8,
240 [CNDCR] = 0x03dc,
241 [CEFCR] = 0x03e4,
242 [FRECR] = 0x03e8,
243 [TSFRCR] = 0x03ec,
244 [TLFRCR] = 0x03f0,
245 [RFCR] = 0x03f4,
246 [MAFCR] = 0x03f8,
247
248 [EDMR] = 0x0200,
249 [EDTRR] = 0x0208,
250 [EDRRR] = 0x0210,
251 [TDLAR] = 0x0218,
252 [RDLAR] = 0x0220,
253 [EESR] = 0x0228,
254 [EESIPR] = 0x0230,
255 [TRSCER] = 0x0238,
256 [RMFCR] = 0x0240,
257 [TFTR] = 0x0248,
258 [FDR] = 0x0250,
259 [RMCR] = 0x0258,
260 [TFUCR] = 0x0264,
261 [RFOCR] = 0x0268,
55754f19 262 [RMIIMODE] = 0x026c,
a3f109bd
SS		 263 [FCFTR] = 0x0270,
264 [TRIMD] = 0x027c,
265};
266
c0013f6f 267static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
3365711d
BH		 268 SH_ETH_OFFSET_DEFAULTS,
269
c0013f6f
SS		 270 [ECMR] = 0x0100,
271 [RFLR] = 0x0108,
272 [ECSR] = 0x0110,
273 [ECSIPR] = 0x0118,
274 [PIR] = 0x0120,
275 [PSR] = 0x0128,
276 [RDMLR] = 0x0140,
277 [IPGR] = 0x0150,
278 [APR] = 0x0154,
279 [MPR] = 0x0158,
280 [TPAUSER] = 0x0164,
281 [RFCF] = 0x0160,
282 [TPAUSECR] = 0x0168,
283 [BCFRR] = 0x016c,
284 [MAHR] = 0x01c0,
285 [MALR] = 0x01c8,
286 [TROCR] = 0x01d0,
287 [CDCR] = 0x01d4,
288 [LCCR] = 0x01d8,
289 [CNDCR] = 0x01dc,
290 [CEFCR] = 0x01e4,
291 [FRECR] = 0x01e8,
292 [TSFRCR] = 0x01ec,
293 [TLFRCR] = 0x01f0,
294 [RFCR] = 0x01f4,
295 [MAFCR] = 0x01f8,
296 [RTRATE] = 0x01fc,
297
298 [EDMR] = 0x0000,
299 [EDTRR] = 0x0008,
300 [EDRRR] = 0x0010,
301 [TDLAR] = 0x0018,
302 [RDLAR] = 0x0020,
303 [EESR] = 0x0028,
304 [EESIPR] = 0x0030,
305 [TRSCER] = 0x0038,
306 [RMFCR] = 0x0040,
307 [TFTR] = 0x0048,
308 [FDR] = 0x0050,
309 [RMCR] = 0x0058,
310 [TFUCR] = 0x0064,
311 [RFOCR] = 0x0068,
312 [FCFTR] = 0x0070,
313 [RPADIR] = 0x0078,
314 [TRIMD] = 0x007c,
315 [RBWAR] = 0x00c8,
316 [RDFAR] = 0x00cc,
317 [TBRAR] = 0x00d4,
318 [TDFAR] = 0x00d8,
319};
320
321static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
3365711d
BH		 322 SH_ETH_OFFSET_DEFAULTS,
323
d8b0426a
SS		 324 [EDMR] = 0x0000,
325 [EDTRR] = 0x0004,
326 [EDRRR] = 0x0008,
327 [TDLAR] = 0x000c,
328 [RDLAR] = 0x0010,
329 [EESR] = 0x0014,
330 [EESIPR] = 0x0018,
331 [TRSCER] = 0x001c,
332 [RMFCR] = 0x0020,
333 [TFTR] = 0x0024,
334 [FDR] = 0x0028,
335 [RMCR] = 0x002c,
336 [EDOCR] = 0x0030,
337 [FCFTR] = 0x0034,
338 [RPADIR] = 0x0038,
339 [TRIMD] = 0x003c,
340 [RBWAR] = 0x0040,
341 [RDFAR] = 0x0044,
342 [TBRAR] = 0x004c,
343 [TDFAR] = 0x0050,
344
c0013f6f
SS		 345 [ECMR] = 0x0160,
346 [ECSR] = 0x0164,
347 [ECSIPR] = 0x0168,
348 [PIR] = 0x016c,
349 [MAHR] = 0x0170,
350 [MALR] = 0x0174,
351 [RFLR] = 0x0178,
352 [PSR] = 0x017c,
353 [TROCR] = 0x0180,
354 [CDCR] = 0x0184,
355 [LCCR] = 0x0188,
356 [CNDCR] = 0x018c,
357 [CEFCR] = 0x0194,
358 [FRECR] = 0x0198,
359 [TSFRCR] = 0x019c,
360 [TLFRCR] = 0x01a0,
361 [RFCR] = 0x01a4,
362 [MAFCR] = 0x01a8,
363 [IPGR] = 0x01b4,
364 [APR] = 0x01b8,
365 [MPR] = 0x01bc,
366 [TPAUSER] = 0x01c4,
367 [BCFR] = 0x01cc,
368
369 [ARSTR] = 0x0000,
370 [TSU_CTRST] = 0x0004,
371 [TSU_FWEN0] = 0x0010,
372 [TSU_FWEN1] = 0x0014,
373 [TSU_FCM] = 0x0018,
374 [TSU_BSYSL0] = 0x0020,
375 [TSU_BSYSL1] = 0x0024,
376 [TSU_PRISL0] = 0x0028,
377 [TSU_PRISL1] = 0x002c,
378 [TSU_FWSL0] = 0x0030,
379 [TSU_FWSL1] = 0x0034,
380 [TSU_FWSLC] = 0x0038,
381 [TSU_QTAGM0] = 0x0040,
382 [TSU_QTAGM1] = 0x0044,
383 [TSU_ADQT0] = 0x0048,
384 [TSU_ADQT1] = 0x004c,
385 [TSU_FWSR] = 0x0050,
386 [TSU_FWINMK] = 0x0054,
387 [TSU_ADSBSY] = 0x0060,
388 [TSU_TEN] = 0x0064,
389 [TSU_POST1] = 0x0070,
390 [TSU_POST2] = 0x0074,
391 [TSU_POST3] = 0x0078,
392 [TSU_POST4] = 0x007c,
393
394 [TXNLCR0] = 0x0080,
395 [TXALCR0] = 0x0084,
396 [RXNLCR0] = 0x0088,
397 [RXALCR0] = 0x008c,
398 [FWNLCR0] = 0x0090,
399 [FWALCR0] = 0x0094,
400 [TXNLCR1] = 0x00a0,
50f3d740 401 [TXALCR1] = 0x00a4,
c0013f6f
SS		 402 [RXNLCR1] = 0x00a8,
403 [RXALCR1] = 0x00ac,
404 [FWNLCR1] = 0x00b0,
405 [FWALCR1] = 0x00b4,
406
407 [TSU_ADRH0] = 0x0100,
c0013f6f
SS		 408};
409
740c7f31
BH		 410static void sh_eth_rcv_snd_disable(struct net_device *ndev);
411static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev);
412
2274d375
SS		 413static void sh_eth_write(struct net_device *ndev, u32 data, int enum_index)
414{
415 struct sh_eth_private *mdp = netdev_priv(ndev);
416 u16 offset = mdp->reg_offset[enum_index];
417
418 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
419 return;
420
421 iowrite32(data, mdp->addr + offset);
422}
423
424static u32 sh_eth_read(struct net_device *ndev, int enum_index)
425{
426 struct sh_eth_private *mdp = netdev_priv(ndev);
427 u16 offset = mdp->reg_offset[enum_index];
428
429 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
430 return ~0U;
431
432 return ioread32(mdp->addr + offset);
433}
434
b2b14d2f
SS		 435static void sh_eth_modify(struct net_device *ndev, int enum_index, u32 clear,
436 u32 set)
437{
438 sh_eth_write(ndev, (sh_eth_read(ndev, enum_index) & ~clear) | set,
439 enum_index);
440}
441
55ea8743
SS		 442static void sh_eth_tsu_write(struct sh_eth_private *mdp, u32 data,
443 int enum_index)
444{
445 iowrite32(data, mdp->tsu_addr + mdp->reg_offset[enum_index]);
446}
447
448static u32 sh_eth_tsu_read(struct sh_eth_private *mdp, int enum_index)
449{
450 return ioread32(mdp->tsu_addr + mdp->reg_offset[enum_index]);
451}
452
8e994402 453static void sh_eth_select_mii(struct net_device *ndev)
5e7a76be 454{
5e7a76be 455 struct sh_eth_private *mdp = netdev_priv(ndev);
4fa8c3cc 456 u32 value;
5e7a76be
NI		 457
458 switch (mdp->phy_interface) {
459 case PHY_INTERFACE_MODE_GMII:
460 value = 0x2;
461 break;
462 case PHY_INTERFACE_MODE_MII:
463 value = 0x1;
464 break;
465 case PHY_INTERFACE_MODE_RMII:
466 value = 0x0;
467 break;
468 default:
f75f14ec
SS		 469 netdev_warn(ndev,
470 "PHY interface mode was not setup. Set to MII.\n");
5e7a76be
NI		 471 value = 0x1;
472 break;
473 }
474
475 sh_eth_write(ndev, value, RMII_MII);
476}
5e7a76be 477
8e994402 478static void sh_eth_set_duplex(struct net_device *ndev)
65ac8851
YS		 479{
480 struct sh_eth_private *mdp = netdev_priv(ndev);
65ac8851 481
b2b14d2f 482 sh_eth_modify(ndev, ECMR, ECMR_DM, mdp->duplex ? ECMR_DM : 0);
65ac8851
YS		 483}
484
99f84be6
GU		 485static void sh_eth_chip_reset(struct net_device *ndev)
486{
487 struct sh_eth_private *mdp = netdev_priv(ndev);
488
489 /* reset device */
ec65cfce 490 sh_eth_tsu_write(mdp, ARSTR_ARST, ARSTR);
99f84be6
GU		 491 mdelay(1);
492}
493
4ceedeb1
SS		 494static int sh_eth_soft_reset(struct net_device *ndev)
495{
496 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, EDMR_SRST_ETHER);
497 mdelay(3);
498 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, 0);
499
500 return 0;
501}
502
503static int sh_eth_check_soft_reset(struct net_device *ndev)
504{
505 int cnt;
506
507 for (cnt = 100; cnt > 0; cnt--) {
508 if (!(sh_eth_read(ndev, EDMR) & EDMR_SRST_GETHER))
509 return 0;
510 mdelay(1);
511 }
512
513 netdev_err(ndev, "Device reset failed\n");
514 return -ETIMEDOUT;
515}
516
517static int sh_eth_soft_reset_gether(struct net_device *ndev)
518{
519 struct sh_eth_private *mdp = netdev_priv(ndev);
520 int ret;
521
522 sh_eth_write(ndev, EDSR_ENALL, EDSR);
523 sh_eth_modify(ndev, EDMR, EDMR_SRST_GETHER, EDMR_SRST_GETHER);
524
525 ret = sh_eth_check_soft_reset(ndev);
526 if (ret)
527 return ret;
528
529 /* Table Init */
530 sh_eth_write(ndev, 0, TDLAR);
531 sh_eth_write(ndev, 0, TDFAR);
532 sh_eth_write(ndev, 0, TDFXR);
533 sh_eth_write(ndev, 0, TDFFR);
534 sh_eth_write(ndev, 0, RDLAR);
535 sh_eth_write(ndev, 0, RDFAR);
536 sh_eth_write(ndev, 0, RDFXR);
537 sh_eth_write(ndev, 0, RDFFR);
538
539 /* Reset HW CRC register */
540 if (mdp->cd->hw_checksum)
541 sh_eth_write(ndev, 0, CSMR);
542
543 /* Select MII mode */
544 if (mdp->cd->select_mii)
545 sh_eth_select_mii(ndev);
546
547 return ret;
548}
549
a0f48be3
GU		 550static void sh_eth_set_rate_gether(struct net_device *ndev)
551{
552 struct sh_eth_private *mdp = netdev_priv(ndev);
553
554 switch (mdp->speed) {
555 case 10: /* 10BASE */
556 sh_eth_write(ndev, GECMR_10, GECMR);
557 break;
558 case 100:/* 100BASE */
559 sh_eth_write(ndev, GECMR_100, GECMR);
560 break;
561 case 1000: /* 1000BASE */
562 sh_eth_write(ndev, GECMR_1000, GECMR);
563 break;
a0f48be3
GU		 564 }
565}
566
99f84be6
GU		 567#ifdef CONFIG_OF
568/* R7S72100 */
569static struct sh_eth_cpu_data r7s72100_data = {
4ceedeb1
SS		 570 .soft_reset = sh_eth_soft_reset_gether,
571
99f84be6
GU		 572 .chip_reset = sh_eth_chip_reset,
573 .set_duplex = sh_eth_set_duplex,
574
575 .register_type = SH_ETH_REG_FAST_RZ,
576
3e416992 577 .edtrr_trns = EDTRR_TRNS_GETHER,
99f84be6
GU		 578 .ecsr_value = ECSR_ICD,
579 .ecsipr_value = ECSIPR_ICDIP,
2b2d3eb4
SS		 580 .eesipr_value = EESIPR_TWB1IP | EESIPR_TWBIP | EESIPR_TC1IP |
581 EESIPR_TABTIP | EESIPR_RABTIP | EESIPR_RFCOFIP |
582 EESIPR_ECIIP |
583 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
584 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
585 EESIPR_RMAFIP | EESIPR_RRFIP |
586 EESIPR_RTLFIP | EESIPR_RTSFIP |
587 EESIPR_PREIP | EESIPR_CERFIP,
99f84be6
GU		 588
589 .tx_check = EESR_TC1 | EESR_FTC,
590 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
591 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
9b39f05c 592 EESR_TDE,
99f84be6
GU		 593 .fdr_value = 0x0000070f,
594
595 .no_psr = 1,
596 .apr = 1,
597 .mpr = 1,
598 .tpauser = 1,
599 .hw_swap = 1,
600 .rpadir = 1,
601 .rpadir_value = 2 << 16,
602 .no_trimd = 1,
603 .no_ade = 1,
246e30cc 604 .xdfar_rw = 1,
62e04b7e 605 .hw_checksum = 1,
99f84be6 606 .tsu = 1,
ce9134df 607 .no_tx_cntrs = 1,
99f84be6 608};
a0f48be3
GU		 609
610static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
611{
c66b2581 612 sh_eth_chip_reset(ndev);
a0f48be3
GU		 613
614 sh_eth_select_mii(ndev);
615}
616
617/* R8A7740 */
618static struct sh_eth_cpu_data r8a7740_data = {
4ceedeb1
SS		 619 .soft_reset = sh_eth_soft_reset_gether,
620
a0f48be3
GU		 621 .chip_reset = sh_eth_chip_reset_r8a7740,
622 .set_duplex = sh_eth_set_duplex,
623 .set_rate = sh_eth_set_rate_gether,
624
625 .register_type = SH_ETH_REG_GIGABIT,
626
3e416992 627 .edtrr_trns = EDTRR_TRNS_GETHER,
a0f48be3
GU		 628 .ecsr_value = ECSR_ICD | ECSR_MPD,
629 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
2b2d3eb4
SS		 630 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
631 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
632 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
633 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
634 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
635 EESIPR_CEEFIP | EESIPR_CELFIP |
636 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
637 EESIPR_PREIP | EESIPR_CERFIP,
a0f48be3
GU		 638
639 .tx_check = EESR_TC1 | EESR_FTC,
640 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
641 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
9b39f05c 642 EESR_TDE,
a0f48be3
GU		 643 .fdr_value = 0x0000070f,
644
645 .apr = 1,
646 .mpr = 1,
647 .tpauser = 1,
648 .bculr = 1,
649 .hw_swap = 1,
650 .rpadir = 1,
651 .rpadir_value = 2 << 16,
652 .no_trimd = 1,
653 .no_ade = 1,
246e30cc 654 .xdfar_rw = 1,
62e04b7e 655 .hw_checksum = 1,
a0f48be3
GU		 656 .tsu = 1,
657 .select_mii = 1,
33017e24 658 .magic = 1,
4c1d4585 659 .cexcr = 1,
a0f48be3 660};
99f84be6 661
04b0ed2a 662/* There is CPU dependent code */
6c4b2f7e 663static void sh_eth_set_rate_rcar(struct net_device *ndev)
65ac8851
YS		 664{
665 struct sh_eth_private *mdp = netdev_priv(ndev);
d0418bb7 666
a3f109bd
SS		 667 switch (mdp->speed) {
668 case 10: /* 10BASE */
b2b14d2f 669 sh_eth_modify(ndev, ECMR, ECMR_ELB, 0);
a3f109bd
SS		 670 break;
671 case 100:/* 100BASE */
b2b14d2f 672 sh_eth_modify(ndev, ECMR, ECMR_ELB, ECMR_ELB);
a3f109bd 673 break;
a3f109bd
SS		 674 }
675}
676
6c4b2f7e
SH		 677/* R-Car Gen1 */
678static struct sh_eth_cpu_data rcar_gen1_data = {
4ceedeb1
SS		 679 .soft_reset = sh_eth_soft_reset,
680
a3f109bd 681 .set_duplex = sh_eth_set_duplex,
6c4b2f7e 682 .set_rate = sh_eth_set_rate_rcar,
a3f109bd 683
a3153d8c
SS		 684 .register_type = SH_ETH_REG_FAST_RCAR,
685
3e416992 686 .edtrr_trns = EDTRR_TRNS_ETHER,
a3f109bd
SS		 687 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
688 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
2b2d3eb4
SS		 689 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP |
690 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
691 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
692 EESIPR_RMAFIP | EESIPR_RRFIP |
693 EESIPR_RTLFIP | EESIPR_RTSFIP |
694 EESIPR_PREIP | EESIPR_CERFIP,
a3f109bd
SS		 695
696 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
ca8c3585 697 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
9b39f05c 698 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
d407bc02 699 .fdr_value = 0x00000f0f,
a3f109bd
SS		 700
701 .apr = 1,
702 .mpr = 1,
703 .tpauser = 1,
704 .hw_swap = 1,
6e80e55b 705 .no_xdfar = 1,
a3f109bd 706};
a3f109bd 707
6c4b2f7e
SH		 708/* R-Car Gen2 and RZ/G1 */
709static struct sh_eth_cpu_data rcar_gen2_data = {
4ceedeb1
SS		 710 .soft_reset = sh_eth_soft_reset,
711
e18dbf7e 712 .set_duplex = sh_eth_set_duplex,
6c4b2f7e 713 .set_rate = sh_eth_set_rate_rcar,
e18dbf7e 714
a3153d8c
SS		 715 .register_type = SH_ETH_REG_FAST_RCAR,
716
3e416992 717 .edtrr_trns = EDTRR_TRNS_ETHER,
e410d86d
NS		 718 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD | ECSR_MPD,
719 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP |
720 ECSIPR_MPDIP,
2b2d3eb4
SS		 721 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP |
722 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
723 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
724 EESIPR_RMAFIP | EESIPR_RRFIP |
725 EESIPR_RTLFIP | EESIPR_RTSFIP |
726 EESIPR_PREIP | EESIPR_CERFIP,
e18dbf7e
SH		 727
728 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
ba361cb3 729 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
9b39f05c 730 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
d407bc02 731 .fdr_value = 0x00000f0f,
e18dbf7e 732
01fbd3f5
GU		 733 .trscer_err_mask = DESC_I_RINT8,
734
e18dbf7e
SH		 735 .apr = 1,
736 .mpr = 1,
737 .tpauser = 1,
738 .hw_swap = 1,
6e80e55b 739 .no_xdfar = 1,
e18dbf7e 740 .rmiimode = 1,
e410d86d 741 .magic = 1,
e18dbf7e 742};
c74a2248 743#endif /* CONFIG_OF */
e18dbf7e 744
9c3beaab 745static void sh_eth_set_rate_sh7724(struct net_device *ndev)
a3f109bd
SS		 746{
747 struct sh_eth_private *mdp = netdev_priv(ndev);
65ac8851
YS		 748
749 switch (mdp->speed) {
750 case 10: /* 10BASE */
b2b14d2f 751 sh_eth_modify(ndev, ECMR, ECMR_RTM, 0);
65ac8851
YS		 752 break;
753 case 100:/* 100BASE */
b2b14d2f 754 sh_eth_modify(ndev, ECMR, ECMR_RTM, ECMR_RTM);
65ac8851 755 break;
65ac8851
YS		 756 }
757}
758
759/* SH7724 */
9c3beaab 760static struct sh_eth_cpu_data sh7724_data = {
4ceedeb1
SS		 761 .soft_reset = sh_eth_soft_reset,
762
65ac8851 763 .set_duplex = sh_eth_set_duplex,
9c3beaab 764 .set_rate = sh_eth_set_rate_sh7724,
65ac8851 765
a3153d8c
SS		 766 .register_type = SH_ETH_REG_FAST_SH4,
767
3e416992 768 .edtrr_trns = EDTRR_TRNS_ETHER,
65ac8851
YS		 769 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
770 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
2b2d3eb4
SS		 771 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP |
772 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
773 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
774 EESIPR_RMAFIP | EESIPR_RRFIP |
775 EESIPR_RTLFIP | EESIPR_RTSFIP |
776 EESIPR_PREIP | EESIPR_CERFIP,
65ac8851
YS		 777
778 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
ca8c3585 779 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
9b39f05c 780 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
65ac8851
YS		 781
782 .apr = 1,
783 .mpr = 1,
784 .tpauser = 1,
785 .hw_swap = 1,
503914cf
MD		 786 .rpadir = 1,
787 .rpadir_value = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
65ac8851 788};
5cee1d37 789
24549e2a 790static void sh_eth_set_rate_sh7757(struct net_device *ndev)
f29a3d04
YS		 791{
792 struct sh_eth_private *mdp = netdev_priv(ndev);
f29a3d04
YS		 793
794 switch (mdp->speed) {
795 case 10: /* 10BASE */
4a55530f 796 sh_eth_write(ndev, 0, RTRATE);
f29a3d04
YS		 797 break;
798 case 100:/* 100BASE */
4a55530f 799 sh_eth_write(ndev, 1, RTRATE);
f29a3d04 800 break;
f29a3d04
YS		 801 }
802}
803
804/* SH7757 */
24549e2a 805static struct sh_eth_cpu_data sh7757_data = {
4ceedeb1
SS		 806 .soft_reset = sh_eth_soft_reset,
807
24549e2a
SS		 808 .set_duplex = sh_eth_set_duplex,
809 .set_rate = sh_eth_set_rate_sh7757,
f29a3d04 810
a3153d8c
SS		 811 .register_type = SH_ETH_REG_FAST_SH4,
812
3e416992 813 .edtrr_trns = EDTRR_TRNS_ETHER,
2b2d3eb4
SS		 814 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
815 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
816 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
817 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
818 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
819 EESIPR_CEEFIP | EESIPR_CELFIP |
820 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
821 EESIPR_PREIP | EESIPR_CERFIP,
f29a3d04
YS		 822
823 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
ca8c3585 824 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
9b39f05c 825 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
f29a3d04 826
5b3dfd13 827 .irq_flags = IRQF_SHARED,
f29a3d04
YS		 828 .apr = 1,
829 .mpr = 1,
830 .tpauser = 1,
831 .hw_swap = 1,
832 .no_ade = 1,
2e98e797
YS		 833 .rpadir = 1,
834 .rpadir_value = 2 << 16,
6b4b4fea 835 .rtrate = 1,
a94cf2a6 836 .dual_port = 1,
f29a3d04 837};
65ac8851 838
e403d295 839#define SH_GIGA_ETH_BASE 0xfee00000UL
8fcd4961
YS		 840#define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
841#define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
842static void sh_eth_chip_reset_giga(struct net_device *ndev)
843{
0799c2d6 844 u32 mahr[2], malr[2];
79270922 845 int i;
8fcd4961
YS		 846
847 /* save MAHR and MALR */
848 for (i = 0; i < 2; i++) {
ae70644d
YS		 849 malr[i] = ioread32((void *)GIGA_MALR(i));
850 mahr[i] = ioread32((void *)GIGA_MAHR(i));
8fcd4961
YS		 851 }
852
c66b2581 853 sh_eth_chip_reset(ndev);
8fcd4961
YS		 854
855 /* restore MAHR and MALR */
856 for (i = 0; i < 2; i++) {
ae70644d
YS		 857 iowrite32(malr[i], (void *)GIGA_MALR(i));
858 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
8fcd4961
YS		 859 }
860}
861
8fcd4961
YS		 862static void sh_eth_set_rate_giga(struct net_device *ndev)
863{
864 struct sh_eth_private *mdp = netdev_priv(ndev);
865
866 switch (mdp->speed) {
867 case 10: /* 10BASE */
868 sh_eth_write(ndev, 0x00000000, GECMR);
869 break;
870 case 100:/* 100BASE */
871 sh_eth_write(ndev, 0x00000010, GECMR);
872 break;
873 case 1000: /* 1000BASE */
874 sh_eth_write(ndev, 0x00000020, GECMR);
875 break;
8fcd4961
YS		 876 }
877}
878
879/* SH7757(GETHERC) */
24549e2a 880static struct sh_eth_cpu_data sh7757_data_giga = {
4ceedeb1
SS		 881 .soft_reset = sh_eth_soft_reset_gether,
882
8fcd4961 883 .chip_reset = sh_eth_chip_reset_giga,
04b0ed2a 884 .set_duplex = sh_eth_set_duplex,
8fcd4961
YS		 885 .set_rate = sh_eth_set_rate_giga,
886
a3153d8c
SS		 887 .register_type = SH_ETH_REG_GIGABIT,
888
3e416992 889 .edtrr_trns = EDTRR_TRNS_GETHER,
8fcd4961
YS		 890 .ecsr_value = ECSR_ICD | ECSR_MPD,
891 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
2b2d3eb4
SS		 892 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
893 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
894 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
895 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
896 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
897 EESIPR_CEEFIP | EESIPR_CELFIP |
898 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
899 EESIPR_PREIP | EESIPR_CERFIP,
8fcd4961
YS		 900
901 .tx_check = EESR_TC1 | EESR_FTC,
ca8c3585
SS		 902 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
903 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
9b39f05c 904 EESR_TDE,
8fcd4961 905 .fdr_value = 0x0000072f,
8fcd4961 906
5b3dfd13 907 .irq_flags = IRQF_SHARED,
8fcd4961
YS		 908 .apr = 1,
909 .mpr = 1,
910 .tpauser = 1,
911 .bculr = 1,
912 .hw_swap = 1,
913 .rpadir = 1,
914 .rpadir_value = 2 << 16,
915 .no_trimd = 1,
916 .no_ade = 1,
246e30cc 917 .xdfar_rw = 1,
3acbc971 918 .tsu = 1,
4c1d4585 919 .cexcr = 1,
a94cf2a6 920 .dual_port = 1,
8fcd4961
YS		 921};
922
f5d12767
SS		 923/* SH7734 */
924static struct sh_eth_cpu_data sh7734_data = {
4ceedeb1
SS		 925 .soft_reset = sh_eth_soft_reset_gether,
926
380af9e3
YS		 927 .chip_reset = sh_eth_chip_reset,
928 .set_duplex = sh_eth_set_duplex,
f5d12767
SS		 929 .set_rate = sh_eth_set_rate_gether,
930
a3153d8c
SS		 931 .register_type = SH_ETH_REG_GIGABIT,
932
3e416992 933 .edtrr_trns = EDTRR_TRNS_GETHER,
f5d12767
SS		 934 .ecsr_value = ECSR_ICD | ECSR_MPD,
935 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
2b2d3eb4
SS		 936 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
937 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
938 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
939 EESIPR_DLCIP | EESIPR_CDIP | EESIPR_TROIP |
940 EESIPR_RMAFIP | EESIPR_CEEFIP | EESIPR_CELFIP |
941 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
942 EESIPR_PREIP | EESIPR_CERFIP,
f5d12767
SS		 943
944 .tx_check = EESR_TC1 | EESR_FTC,
ca8c3585
SS		 945 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
946 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
9b39f05c 947 EESR_TDE,
f5d12767
SS		 948
949 .apr = 1,
950 .mpr = 1,
951 .tpauser = 1,
952 .bculr = 1,
953 .hw_swap = 1,
954 .no_trimd = 1,
955 .no_ade = 1,
246e30cc 956 .xdfar_rw = 1,
f5d12767 957 .tsu = 1,
62e04b7e 958 .hw_checksum = 1,
f5d12767 959 .select_mii = 1,
159c2a90 960 .magic = 1,
4c1d4585 961 .cexcr = 1,
f5d12767
SS		 962};
963
964/* SH7763 */
965static struct sh_eth_cpu_data sh7763_data = {
4ceedeb1
SS		 966 .soft_reset = sh_eth_soft_reset_gether,
967
f5d12767
SS		 968 .chip_reset = sh_eth_chip_reset,
969 .set_duplex = sh_eth_set_duplex,
970 .set_rate = sh_eth_set_rate_gether,
380af9e3 971
a3153d8c
SS		 972 .register_type = SH_ETH_REG_GIGABIT,
973
3e416992 974 .edtrr_trns = EDTRR_TRNS_GETHER,
380af9e3
YS		 975 .ecsr_value = ECSR_ICD | ECSR_MPD,
976 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
2b2d3eb4
SS		 977 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
978 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
979 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
980 EESIPR_DLCIP | EESIPR_CDIP | EESIPR_TROIP |
981 EESIPR_RMAFIP | EESIPR_CEEFIP | EESIPR_CELFIP |
982 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
983 EESIPR_PREIP | EESIPR_CERFIP,
380af9e3
YS		 984
985 .tx_check = EESR_TC1 | EESR_FTC,
128296fc 986 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
9b39f05c 987 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
380af9e3
YS		 988
989 .apr = 1,
990 .mpr = 1,
991 .tpauser = 1,
992 .bculr = 1,
993 .hw_swap = 1,
380af9e3
YS		 994 .no_trimd = 1,
995 .no_ade = 1,
246e30cc 996 .xdfar_rw = 1,
4986b996 997 .tsu = 1,
5b3dfd13 998 .irq_flags = IRQF_SHARED,
267e1d5c 999 .magic = 1,
4c1d4585 1000 .cexcr = 1,
a94cf2a6 1001 .dual_port = 1,
380af9e3
YS		 1002};
1003
c18a79ab 1004static struct sh_eth_cpu_data sh7619_data = {
4ceedeb1
SS		 1005 .soft_reset = sh_eth_soft_reset,
1006
a3153d8c
SS		 1007 .register_type = SH_ETH_REG_FAST_SH3_SH2,
1008
3e416992 1009 .edtrr_trns = EDTRR_TRNS_ETHER,
2b2d3eb4
SS		 1010 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
1011 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
1012 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
1013 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
1014 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
1015 EESIPR_CEEFIP | EESIPR_CELFIP |
1016 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
1017 EESIPR_PREIP | EESIPR_CERFIP,
380af9e3
YS		 1018
1019 .apr = 1,
1020 .mpr = 1,
1021 .tpauser = 1,
1022 .hw_swap = 1,
1023};
7bbe150d
SS		 1024
1025static struct sh_eth_cpu_data sh771x_data = {
4ceedeb1
SS		 1026 .soft_reset = sh_eth_soft_reset,
1027
a3153d8c
SS		 1028 .register_type = SH_ETH_REG_FAST_SH3_SH2,
1029
3e416992 1030 .edtrr_trns = EDTRR_TRNS_ETHER,
2b2d3eb4
SS		 1031 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
1032 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
1033 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
1034 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
1035 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
1036 EESIPR_CEEFIP | EESIPR_CELFIP |
1037 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
1038 EESIPR_PREIP | EESIPR_CERFIP,
4986b996 1039 .tsu = 1,
a94cf2a6 1040 .dual_port = 1,
380af9e3 1041};
380af9e3
YS		 1042
1043static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
1044{
1045 if (!cd->ecsr_value)
1046 cd->ecsr_value = DEFAULT_ECSR_INIT;
1047
1048 if (!cd->ecsipr_value)
1049 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
1050
1051 if (!cd->fcftr_value)
128296fc 1052 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF |
380af9e3
YS		 1053 DEFAULT_FIFO_F_D_RFD;
1054
1055 if (!cd->fdr_value)
1056 cd->fdr_value = DEFAULT_FDR_INIT;
1057
380af9e3
YS		 1058 if (!cd->tx_check)
1059 cd->tx_check = DEFAULT_TX_CHECK;
1060
1061 if (!cd->eesr_err_check)
1062 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
b284fbe3
NI		 1063
1064 if (!cd->trscer_err_mask)
1065 cd->trscer_err_mask = DEFAULT_TRSCER_ERR_MASK;
380af9e3
YS		 1066}
1067
380af9e3
YS		 1068static void sh_eth_set_receive_align(struct sk_buff *skb)
1069{
4d6a949c 1070 uintptr_t reserve = (uintptr_t)skb->data & (SH_ETH_RX_ALIGN - 1);
380af9e3 1071
380af9e3 1072 if (reserve)
4d6a949c 1073 skb_reserve(skb, SH_ETH_RX_ALIGN - reserve);
380af9e3 1074}
380af9e3 1075
128296fc 1076/* Program the hardware MAC address from dev->dev_addr. */
86a74ff2
NI		 1077static void update_mac_address(struct net_device *ndev)
1078{
4a55530f 1079 sh_eth_write(ndev,
128296fc
SS		 1080 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
1081 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
4a55530f 1082 sh_eth_write(ndev,
128296fc 1083 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
86a74ff2
NI		 1084}
1085
128296fc 1086/* Get MAC address from SuperH MAC address register
86a74ff2
NI		 1087 *
1088 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
1089 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
1090 * When you want use this device, you must set MAC address in bootloader.
1091 *
1092 */
748031f9 1093static void read_mac_address(struct net_device *ndev, unsigned char *mac)
86a74ff2 1094{
748031f9 1095 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
d458cdf7 1096 memcpy(ndev->dev_addr, mac, ETH_ALEN);
748031f9 1097 } else {
37742f02
SS		 1098 u32 mahr = sh_eth_read(ndev, MAHR);
1099 u32 malr = sh_eth_read(ndev, MALR);
1100
1101 ndev->dev_addr[0] = (mahr >> 24) & 0xFF;
1102 ndev->dev_addr[1] = (mahr >> 16) & 0xFF;
1103 ndev->dev_addr[2] = (mahr >> 8) & 0xFF;
1104 ndev->dev_addr[3] = (mahr >> 0) & 0xFF;
1105 ndev->dev_addr[4] = (malr >> 8) & 0xFF;
1106 ndev->dev_addr[5] = (malr >> 0) & 0xFF;
748031f9 1107 }
86a74ff2
NI		 1108}
1109
1110struct bb_info {
ae70644d 1111 void (*set_gate)(void *addr);
86a74ff2 1112 struct mdiobb_ctrl ctrl;
ae70644d 1113 void *addr;
86a74ff2
NI		 1114};
1115
39b4b06b 1116static void sh_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set)
86a74ff2
NI		 1117{
1118 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
78fa3c5c 1119 u32 pir;
b3017e6a
YS		 1120
1121 if (bitbang->set_gate)
1122 bitbang->set_gate(bitbang->addr);
1123
78fa3c5c 1124 pir = ioread32(bitbang->addr);
39b4b06b 1125 if (set)
78fa3c5c 1126 pir |= mask;
86a74ff2 1127 else
78fa3c5c
SS		 1128 pir &= ~mask;
1129 iowrite32(pir, bitbang->addr);
39b4b06b
SS		 1130}
1131
1132/* Data I/O pin control */
1133static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1134{
1135 sh_mdio_ctrl(ctrl, PIR_MMD, bit);
86a74ff2
NI		 1136}
1137
1138/* Set bit data*/
1139static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
1140{
39b4b06b 1141 sh_mdio_ctrl(ctrl, PIR_MDO, bit);
86a74ff2
NI		 1142}
1143
1144/* Get bit data*/
1145static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
1146{
1147 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
b3017e6a
YS		 1148
1149 if (bitbang->set_gate)
1150 bitbang->set_gate(bitbang->addr);
1151
78fa3c5c 1152 return (ioread32(bitbang->addr) & PIR_MDI) != 0;
86a74ff2
NI		 1153}
1154
1155/* MDC pin control */
1156static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1157{
39b4b06b 1158 sh_mdio_ctrl(ctrl, PIR_MDC, bit);
86a74ff2
NI		 1159}
1160
1161/* mdio bus control struct */
1162static struct mdiobb_ops bb_ops = {
1163 .owner = THIS_MODULE,
1164 .set_mdc = sh_mdc_ctrl,
1165 .set_mdio_dir = sh_mmd_ctrl,
1166 .set_mdio_data = sh_set_mdio,
1167 .get_mdio_data = sh_get_mdio,
1168};
1169
1debdc8f
SS		 1170/* free Tx skb function */
1171static int sh_eth_tx_free(struct net_device *ndev, bool sent_only)
1172{
1173 struct sh_eth_private *mdp = netdev_priv(ndev);
1174 struct sh_eth_txdesc *txdesc;
1175 int free_num = 0;
1176 int entry;
1177 bool sent;
1178
1179 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
1180 entry = mdp->dirty_tx % mdp->num_tx_ring;
1181 txdesc = &mdp->tx_ring[entry];
1182 sent = !(txdesc->status & cpu_to_le32(TD_TACT));
1183 if (sent_only && !sent)
1184 break;
1185 /* TACT bit must be checked before all the following reads */
1186 dma_rmb();
1187 netif_info(mdp, tx_done, ndev,
1188 "tx entry %d status 0x%08x\n",
1189 entry, le32_to_cpu(txdesc->status));
1190 /* Free the original skb. */
1191 if (mdp->tx_skbuff[entry]) {
22c1aed4
TP		 1192 dma_unmap_single(&mdp->pdev->dev,
1193 le32_to_cpu(txdesc->addr),
1debdc8f
SS		 1194 le32_to_cpu(txdesc->len) >> 16,
1195 DMA_TO_DEVICE);
1196 dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1197 mdp->tx_skbuff[entry] = NULL;
1198 free_num++;
1199 }
1200 txdesc->status = cpu_to_le32(TD_TFP);
1201 if (entry >= mdp->num_tx_ring - 1)
1202 txdesc->status |= cpu_to_le32(TD_TDLE);
1203
1204 if (sent) {
1205 ndev->stats.tx_packets++;
1206 ndev->stats.tx_bytes += le32_to_cpu(txdesc->len) >> 16;
1207 }
1208 }
1209 return free_num;
1210}
1211
86a74ff2
NI		 1212/* free skb and descriptor buffer */
1213static void sh_eth_ring_free(struct net_device *ndev)
1214{
1215 struct sh_eth_private *mdp = netdev_priv(ndev);
8e03a5e7 1216 int ringsize, i;
86a74ff2 1217
1debdc8f
SS		 1218 if (mdp->rx_ring) {
1219 for (i = 0; i < mdp->num_rx_ring; i++) {
1220 if (mdp->rx_skbuff[i]) {
1221 struct sh_eth_rxdesc *rxdesc = &mdp->rx_ring[i];
1222
22c1aed4 1223 dma_unmap_single(&mdp->pdev->dev,
1debdc8f
SS		 1224 le32_to_cpu(rxdesc->addr),
1225 ALIGN(mdp->rx_buf_sz, 32),
1226 DMA_FROM_DEVICE);
1227 }
1228 }
1229 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
573500db 1230 dma_free_coherent(&mdp->pdev->dev, ringsize, mdp->rx_ring,
1debdc8f
SS		 1231 mdp->rx_desc_dma);
1232 mdp->rx_ring = NULL;
1233 }
1234
86a74ff2
NI		 1235 /* Free Rx skb ringbuffer */
1236 if (mdp->rx_skbuff) {
179d80af
SS		 1237 for (i = 0; i < mdp->num_rx_ring; i++)
1238 dev_kfree_skb(mdp->rx_skbuff[i]);
86a74ff2
NI		 1239 }
1240 kfree(mdp->rx_skbuff);
91c77550 1241 mdp->rx_skbuff = NULL;
86a74ff2 1242
8e03a5e7 1243 if (mdp->tx_ring) {
1debdc8f
SS		 1244 sh_eth_tx_free(ndev, false);
1245
8e03a5e7 1246 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
573500db 1247 dma_free_coherent(&mdp->pdev->dev, ringsize, mdp->tx_ring,
8e03a5e7
SS		 1248 mdp->tx_desc_dma);
1249 mdp->tx_ring = NULL;
1250 }
1debdc8f
SS		 1251
1252 /* Free Tx skb ringbuffer */
1253 kfree(mdp->tx_skbuff);
1254 mdp->tx_skbuff = NULL;
86a74ff2
NI		 1255}
1256
1257/* format skb and descriptor buffer */
1258static void sh_eth_ring_format(struct net_device *ndev)
1259{
1260 struct sh_eth_private *mdp = netdev_priv(ndev);
1261 int i;
1262 struct sk_buff *skb;
1263 struct sh_eth_rxdesc *rxdesc = NULL;
1264 struct sh_eth_txdesc *txdesc = NULL;
525b8075
YS		 1265 int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
1266 int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
cb368595 1267 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
52b9fa36 1268 dma_addr_t dma_addr;
5cbf20c7 1269 u32 buf_len;
86a74ff2 1270
128296fc
SS		 1271 mdp->cur_rx = 0;
1272 mdp->cur_tx = 0;
1273 mdp->dirty_rx = 0;
1274 mdp->dirty_tx = 0;
86a74ff2
NI		 1275
1276 memset(mdp->rx_ring, 0, rx_ringsize);
1277
1278 /* build Rx ring buffer */
525b8075 1279 for (i = 0; i < mdp->num_rx_ring; i++) {
86a74ff2
NI		 1280 /* skb */
1281 mdp->rx_skbuff[i] = NULL;
4d6a949c 1282 skb = netdev_alloc_skb(ndev, skbuff_size);
86a74ff2
NI		 1283 if (skb == NULL)
1284 break;
380af9e3
YS		 1285 sh_eth_set_receive_align(skb);
1286
ab857916 1287 /* The size of the buffer is a multiple of 32 bytes. */
5cbf20c7 1288 buf_len = ALIGN(mdp->rx_buf_sz, 32);
22c1aed4 1289 dma_addr = dma_map_single(&mdp->pdev->dev, skb->data, buf_len,
52b9fa36 1290 DMA_FROM_DEVICE);
22c1aed4 1291 if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) {
52b9fa36
BH		 1292 kfree_skb(skb);
1293 break;
1294 }
1295 mdp->rx_skbuff[i] = skb;
d0ba9134
SS		 1296
1297 /* RX descriptor */
1298 rxdesc = &mdp->rx_ring[i];
1299 rxdesc->len = cpu_to_le32(buf_len << 16);
7cf72477
SS		 1300 rxdesc->addr = cpu_to_le32(dma_addr);
1301 rxdesc->status = cpu_to_le32(RD_RACT | RD_RFP);
86a74ff2 1302
b0ca2a21
NI		 1303 /* Rx descriptor address set */
1304 if (i == 0) {
4a55530f 1305 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
246e30cc 1306 if (mdp->cd->xdfar_rw)
c5ed5368 1307 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
b0ca2a21 1308 }
86a74ff2
NI		 1309 }
1310
525b8075 1311 mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
86a74ff2
NI		 1312
1313 /* Mark the last entry as wrapping the ring. */
c1b7fca6
SS		 1314 if (rxdesc)
1315 rxdesc->status |= cpu_to_le32(RD_RDLE);
86a74ff2
NI		 1316
1317 memset(mdp->tx_ring, 0, tx_ringsize);
1318
1319 /* build Tx ring buffer */
525b8075 1320 for (i = 0; i < mdp->num_tx_ring; i++) {
86a74ff2
NI		 1321 mdp->tx_skbuff[i] = NULL;
1322 txdesc = &mdp->tx_ring[i];
7cf72477
SS		 1323 txdesc->status = cpu_to_le32(TD_TFP);
1324 txdesc->len = cpu_to_le32(0);
b0ca2a21 1325 if (i == 0) {
71557a37 1326 /* Tx descriptor address set */
4a55530f 1327 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
246e30cc 1328 if (mdp->cd->xdfar_rw)
c5ed5368 1329 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
b0ca2a21 1330 }
86a74ff2
NI		 1331 }
1332
7cf72477 1333 txdesc->status |= cpu_to_le32(TD_TDLE);
86a74ff2
NI		 1334}
1335
1336/* Get skb and descriptor buffer */
1337static int sh_eth_ring_init(struct net_device *ndev)
1338{
1339 struct sh_eth_private *mdp = netdev_priv(ndev);
91d80683 1340 int rx_ringsize, tx_ringsize;
86a74ff2 1341
128296fc 1342 /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
86a74ff2
NI		 1343 * card needs room to do 8 byte alignment, +2 so we can reserve
1344 * the first 2 bytes, and +16 gets room for the status word from the
1345 * card.
1346 */
1347 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
1348 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
503914cf
MD		 1349 if (mdp->cd->rpadir)
1350 mdp->rx_buf_sz += NET_IP_ALIGN;
86a74ff2
NI		 1351
1352 /* Allocate RX and TX skb rings */
2c94e856
SS		 1353 mdp->rx_skbuff = kcalloc(mdp->num_rx_ring, sizeof(*mdp->rx_skbuff),
1354 GFP_KERNEL);
91d80683
SS		 1355 if (!mdp->rx_skbuff)
1356 return -ENOMEM;
86a74ff2 1357
2c94e856
SS		 1358 mdp->tx_skbuff = kcalloc(mdp->num_tx_ring, sizeof(*mdp->tx_skbuff),
1359 GFP_KERNEL);
91d80683 1360 if (!mdp->tx_skbuff)
8e03a5e7 1361 goto ring_free;
86a74ff2
NI		 1362
1363 /* Allocate all Rx descriptors. */
525b8075 1364 rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
573500db
TP		 1365 mdp->rx_ring = dma_alloc_coherent(&mdp->pdev->dev, rx_ringsize,
1366 &mdp->rx_desc_dma, GFP_KERNEL);
91d80683 1367 if (!mdp->rx_ring)
8e03a5e7 1368 goto ring_free;
86a74ff2
NI		 1369
1370 mdp->dirty_rx = 0;
1371
1372 /* Allocate all Tx descriptors. */
525b8075 1373 tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
573500db
TP		 1374 mdp->tx_ring = dma_alloc_coherent(&mdp->pdev->dev, tx_ringsize,
1375 &mdp->tx_desc_dma, GFP_KERNEL);
91d80683 1376 if (!mdp->tx_ring)
8e03a5e7 1377 goto ring_free;
91d80683 1378 return 0;
86a74ff2 1379
8e03a5e7
SS		 1380ring_free:
1381 /* Free Rx and Tx skb ring buffer and DMA buffer */
86a74ff2
NI		 1382 sh_eth_ring_free(ndev);
1383
91d80683 1384 return -ENOMEM;
86a74ff2
NI		 1385}
1386
f7967210 1387static int sh_eth_dev_init(struct net_device *ndev)
86a74ff2 1388{
86a74ff2 1389 struct sh_eth_private *mdp = netdev_priv(ndev);
4fa8c3cc 1390 int ret;
86a74ff2
NI		 1391
1392 /* Soft Reset */
4ceedeb1 1393 ret = mdp->cd->soft_reset(ndev);
5cee1d37 1394 if (ret)
f738a13d 1395 return ret;
86a74ff2 1396
55754f19
SH		 1397 if (mdp->cd->rmiimode)
1398 sh_eth_write(ndev, 0x1, RMIIMODE);
1399
b0ca2a21
NI		 1400 /* Descriptor format */
1401 sh_eth_ring_format(ndev);
380af9e3 1402 if (mdp->cd->rpadir)
4a55530f 1403 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
86a74ff2
NI		 1404
1405 /* all sh_eth int mask */
4a55530f 1406 sh_eth_write(ndev, 0, EESIPR);
86a74ff2 1407
10b9194f 1408#if defined(__LITTLE_ENDIAN)
380af9e3 1409 if (mdp->cd->hw_swap)
4a55530f 1410 sh_eth_write(ndev, EDMR_EL, EDMR);
380af9e3 1411 else
b0ca2a21 1412#endif
4a55530f 1413 sh_eth_write(ndev, 0, EDMR);
86a74ff2 1414
b0ca2a21 1415 /* FIFO size set */
4a55530f
YS		 1416 sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
1417 sh_eth_write(ndev, 0, TFTR);
86a74ff2 1418
530aa2d0
BD		 1419 /* Frame recv control (enable multiple-packets per rx irq) */
1420 sh_eth_write(ndev, RMCR_RNC, RMCR);
86a74ff2 1421
b284fbe3 1422 sh_eth_write(ndev, mdp->cd->trscer_err_mask, TRSCER);
86a74ff2 1423
380af9e3 1424 if (mdp->cd->bculr)
4a55530f 1425 sh_eth_write(ndev, 0x800, BCULR); /* Burst sycle set */
b0ca2a21 1426
4a55530f 1427 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
86a74ff2 1428
380af9e3 1429 if (!mdp->cd->no_trimd)
4a55530f 1430 sh_eth_write(ndev, 0, TRIMD);
86a74ff2 1431
b0ca2a21 1432 /* Recv frame limit set register */
fdb37a7f
YS		 1433 sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1434 RFLR);
86a74ff2 1435
b2b14d2f 1436 sh_eth_modify(ndev, EESR, 0, 0);
f7967210
SS		 1437 mdp->irq_enabled = true;
1438 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
86a74ff2
NI		 1439
1440 /* PAUSE Prohibition */
bffa731f
SS		 1441 sh_eth_write(ndev, ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) |
1442 ECMR_TE | ECMR_RE, ECMR);
b0ca2a21 1443
380af9e3
YS		 1444 if (mdp->cd->set_rate)
1445 mdp->cd->set_rate(ndev);
1446
b0ca2a21 1447 /* E-MAC Status Register clear */
4a55530f 1448 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
b0ca2a21
NI		 1449
1450 /* E-MAC Interrupt Enable register */
f7967210 1451 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
86a74ff2
NI		 1452
1453 /* Set MAC address */
1454 update_mac_address(ndev);
1455
1456 /* mask reset */
380af9e3 1457 if (mdp->cd->apr)
4a55530f 1458 sh_eth_write(ndev, APR_AP, APR);
380af9e3 1459 if (mdp->cd->mpr)
4a55530f 1460 sh_eth_write(ndev, MPR_MP, MPR);
380af9e3 1461 if (mdp->cd->tpauser)
4a55530f 1462 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
b0ca2a21 1463
f7967210
SS		 1464 /* Setting the Rx mode will start the Rx process. */
1465 sh_eth_write(ndev, EDRRR_R, EDRRR);
86a74ff2
NI		 1466
1467 return ret;
1468}
1469
740c7f31
BH		 1470static void sh_eth_dev_exit(struct net_device *ndev)
1471{
1472 struct sh_eth_private *mdp = netdev_priv(ndev);
1473 int i;
1474
1475 /* Deactivate all TX descriptors, so DMA should stop at next
1476 * packet boundary if it's currently running
1477 */
1478 for (i = 0; i < mdp->num_tx_ring; i++)
7cf72477 1479 mdp->tx_ring[i].status &= ~cpu_to_le32(TD_TACT);
740c7f31
BH		 1480
1481 /* Disable TX FIFO egress to MAC */
1482 sh_eth_rcv_snd_disable(ndev);
1483
1484 /* Stop RX DMA at next packet boundary */
1485 sh_eth_write(ndev, 0, EDRRR);
1486
1487 /* Aside from TX DMA, we can't tell when the hardware is
1488 * really stopped, so we need to reset to make sure.
1489 * Before doing that, wait for long enough to *probably*
1490 * finish transmitting the last packet and poll stats.
1491 */
1492 msleep(2); /* max frame time at 10 Mbps < 1250 us */
1493 sh_eth_get_stats(ndev);
4ceedeb1 1494 mdp->cd->soft_reset(ndev);
a14c7d15
GU		 1495
1496 /* Set MAC address again */
1497 update_mac_address(ndev);
740c7f31
BH		 1498}
1499
86a74ff2 1500/* Packet receive function */
3719109d 1501static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
86a74ff2
NI		 1502{
1503 struct sh_eth_private *mdp = netdev_priv(ndev);
1504 struct sh_eth_rxdesc *rxdesc;
1505
525b8075
YS		 1506 int entry = mdp->cur_rx % mdp->num_rx_ring;
1507 int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
319cd520 1508 int limit;
86a74ff2 1509 struct sk_buff *skb;
380af9e3 1510 u32 desc_status;
cb368595 1511 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
52b9fa36 1512 dma_addr_t dma_addr;
4fa8c3cc 1513 u16 pkt_len;
5cbf20c7 1514 u32 buf_len;
86a74ff2 1515
319cd520
MK		 1516 boguscnt = min(boguscnt, *quota);
1517 limit = boguscnt;
86a74ff2 1518 rxdesc = &mdp->rx_ring[entry];
7cf72477 1519 while (!(rxdesc->status & cpu_to_le32(RD_RACT))) {
7d7355f5 1520 /* RACT bit must be checked before all the following reads */
f32bfb9a 1521 dma_rmb();
7cf72477
SS		 1522 desc_status = le32_to_cpu(rxdesc->status);
1523 pkt_len = le32_to_cpu(rxdesc->len) & RD_RFL;
86a74ff2
NI		 1524
1525 if (--boguscnt < 0)
1526 break;
1527
e5fd13f4
BH		 1528 netif_info(mdp, rx_status, ndev,
1529 "rx entry %d status 0x%08x len %d\n",
1530 entry, desc_status, pkt_len);
1531
86a74ff2 1532 if (!(desc_status & RDFEND))
bb7d92e3 1533 ndev->stats.rx_length_errors++;
86a74ff2 1534
128296fc 1535 /* In case of almost all GETHER/ETHERs, the Receive Frame State
dd019897 1536 * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
9b4a6364
BH		 1537 * bit 0. However, in case of the R8A7740 and R7S72100
1538 * the RFS bits are from bit 25 to bit 16. So, the
db893473 1539 * driver needs right shifting by 16.
dd019897 1540 */
62e04b7e 1541 if (mdp->cd->hw_checksum)
ac8025a6 1542 desc_status >>= 16;
dd019897 1543
248be83d 1544 skb = mdp->rx_skbuff[entry];
86a74ff2
NI		 1545 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1546 RD_RFS5 | RD_RFS6 | RD_RFS10)) {
bb7d92e3 1547 ndev->stats.rx_errors++;
86a74ff2 1548 if (desc_status & RD_RFS1)
bb7d92e3 1549 ndev->stats.rx_crc_errors++;
86a74ff2 1550 if (desc_status & RD_RFS2)
bb7d92e3 1551 ndev->stats.rx_frame_errors++;
86a74ff2 1552 if (desc_status & RD_RFS3)
bb7d92e3 1553 ndev->stats.rx_length_errors++;
86a74ff2 1554 if (desc_status & RD_RFS4)
bb7d92e3 1555 ndev->stats.rx_length_errors++;
86a74ff2 1556 if (desc_status & RD_RFS6)
bb7d92e3 1557 ndev->stats.rx_missed_errors++;
86a74ff2 1558 if (desc_status & RD_RFS10)
bb7d92e3 1559 ndev->stats.rx_over_errors++;
248be83d 1560 } else if (skb) {
7cf72477 1561 dma_addr = le32_to_cpu(rxdesc->addr);
380af9e3
YS		 1562 if (!mdp->cd->hw_swap)
1563 sh_eth_soft_swap(
1299653a 1564 phys_to_virt(ALIGN(dma_addr, 4)),
380af9e3 1565 pkt_len + 2);
86a74ff2 1566 mdp->rx_skbuff[entry] = NULL;
503914cf
MD		 1567 if (mdp->cd->rpadir)
1568 skb_reserve(skb, NET_IP_ALIGN);
22c1aed4 1569 dma_unmap_single(&mdp->pdev->dev, dma_addr,
ab857916 1570 ALIGN(mdp->rx_buf_sz, 32),
52b9fa36 1571 DMA_FROM_DEVICE);
86a74ff2
NI		 1572 skb_put(skb, pkt_len);
1573 skb->protocol = eth_type_trans(skb, ndev);
a8e9fd0f 1574 netif_receive_skb(skb);
bb7d92e3
ED		 1575 ndev->stats.rx_packets++;
1576 ndev->stats.rx_bytes += pkt_len;
25b77ad7
BH		 1577 if (desc_status & RD_RFS8)
1578 ndev->stats.multicast++;
86a74ff2 1579 }
525b8075 1580 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
862df497 1581 rxdesc = &mdp->rx_ring[entry];
86a74ff2
NI		 1582 }
1583
1584 /* Refill the Rx ring buffers. */
1585 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
525b8075 1586 entry = mdp->dirty_rx % mdp->num_rx_ring;
86a74ff2 1587 rxdesc = &mdp->rx_ring[entry];
ab857916 1588 /* The size of the buffer is 32 byte boundary. */
5cbf20c7 1589 buf_len = ALIGN(mdp->rx_buf_sz, 32);
7cf72477 1590 rxdesc->len = cpu_to_le32(buf_len << 16);
b0ca2a21 1591
86a74ff2 1592 if (mdp->rx_skbuff[entry] == NULL) {
4d6a949c 1593 skb = netdev_alloc_skb(ndev, skbuff_size);
86a74ff2
NI		 1594 if (skb == NULL)
1595 break; /* Better luck next round. */
380af9e3 1596 sh_eth_set_receive_align(skb);
22c1aed4 1597 dma_addr = dma_map_single(&mdp->pdev->dev, skb->data,
5cbf20c7 1598 buf_len, DMA_FROM_DEVICE);
22c1aed4 1599 if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) {
52b9fa36
BH		 1600 kfree_skb(skb);
1601 break;
1602 }
1603 mdp->rx_skbuff[entry] = skb;
380af9e3 1604
bc8acf2c 1605 skb_checksum_none_assert(skb);
7cf72477 1606 rxdesc->addr = cpu_to_le32(dma_addr);
86a74ff2 1607 }
f32bfb9a 1608 dma_wmb(); /* RACT bit must be set after all the above writes */
525b8075 1609 if (entry >= mdp->num_rx_ring - 1)
86a74ff2 1610 rxdesc->status |=
7cf72477 1611 cpu_to_le32(RD_RACT | RD_RFP | RD_RDLE);
86a74ff2 1612 else
7cf72477 1613 rxdesc->status |= cpu_to_le32(RD_RACT | RD_RFP);
86a74ff2
NI		 1614 }
1615
1616 /* Restart Rx engine if stopped. */
1617 /* If we don't need to check status, don't. -KDU */
79fba9f5 1618 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
a18e08bd 1619 /* fix the values for the next receiving if RDE is set */
6e80e55b 1620 if (intr_status & EESR_RDE && !mdp->cd->no_xdfar) {
128296fc
SS		 1621 u32 count = (sh_eth_read(ndev, RDFAR) -
1622 sh_eth_read(ndev, RDLAR)) >> 4;
1623
1624 mdp->cur_rx = count;
1625 mdp->dirty_rx = count;
1626 }
4a55530f 1627 sh_eth_write(ndev, EDRRR_R, EDRRR);
79fba9f5 1628 }
86a74ff2 1629
319cd520
MK		 1630 *quota -= limit - boguscnt - 1;
1631
4f809cea 1632 return *quota <= 0;
86a74ff2
NI		 1633}
1634
4a55530f 1635static void sh_eth_rcv_snd_disable(struct net_device *ndev)
dc19e4e5
NI		 1636{
1637 /* disable tx and rx */
b2b14d2f 1638 sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0);
dc19e4e5
NI		 1639}
1640
4a55530f 1641static void sh_eth_rcv_snd_enable(struct net_device *ndev)
dc19e4e5
NI		 1642{
1643 /* enable tx and rx */
b2b14d2f 1644 sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE);
dc19e4e5
NI		 1645}
1646
9b39f05c
SS		 1647/* E-MAC interrupt handler */
1648static void sh_eth_emac_interrupt(struct net_device *ndev)
86a74ff2
NI		 1649{
1650 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2 1651 u32 felic_stat;
380af9e3 1652 u32 link_stat;
86a74ff2 1653
9b39f05c
SS		 1654 felic_stat = sh_eth_read(ndev, ECSR) & sh_eth_read(ndev, ECSIPR);
1655 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */
1656 if (felic_stat & ECSR_ICD)
1657 ndev->stats.tx_carrier_errors++;
0cf45a3b
NS		 1658 if (felic_stat & ECSR_MPD)
1659 pm_wakeup_event(&mdp->pdev->dev, 0);
9b39f05c
SS		 1660 if (felic_stat & ECSR_LCHNG) {
1661 /* Link Changed */
1662 if (mdp->cd->no_psr || mdp->no_ether_link)
1663 return;
1664 link_stat = sh_eth_read(ndev, PSR);
1665 if (mdp->ether_link_active_low)
1666 link_stat = ~link_stat;
1667 if (!(link_stat & PHY_ST_LINK)) {
1668 sh_eth_rcv_snd_disable(ndev);
1669 } else {
1670 /* Link Up */
1a0bee6c 1671 sh_eth_modify(ndev, EESIPR, EESIPR_ECIIP, 0);
9b39f05c
SS		 1672 /* clear int */
1673 sh_eth_modify(ndev, ECSR, 0, 0);
1a0bee6c 1674 sh_eth_modify(ndev, EESIPR, EESIPR_ECIIP, EESIPR_ECIIP);
9b39f05c
SS		 1675 /* enable tx and rx */
1676 sh_eth_rcv_snd_enable(ndev);
86a74ff2
NI		 1677 }
1678 }
9b39f05c
SS		 1679}
1680
1681/* error control function */
1682static void sh_eth_error(struct net_device *ndev, u32 intr_status)
1683{
1684 struct sh_eth_private *mdp = netdev_priv(ndev);
1685 u32 mask;
86a74ff2
NI		 1686
1687 if (intr_status & EESR_TWB) {
4eb313a7
SS		 1688 /* Unused write back interrupt */
1689 if (intr_status & EESR_TABT) { /* Transmit Abort int */
bb7d92e3 1690 ndev->stats.tx_aborted_errors++;
8d5009f6 1691 netif_err(mdp, tx_err, ndev, "Transmit Abort\n");
4eb313a7 1692 }
86a74ff2
NI		 1693 }
1694
1695 if (intr_status & EESR_RABT) {
1696 /* Receive Abort int */
1697 if (intr_status & EESR_RFRMER) {
1698 /* Receive Frame Overflow int */
bb7d92e3 1699 ndev->stats.rx_frame_errors++;
86a74ff2
NI		 1700 }
1701 }
380af9e3 1702
dc19e4e5
NI		 1703 if (intr_status & EESR_TDE) {
1704 /* Transmit Descriptor Empty int */
bb7d92e3 1705 ndev->stats.tx_fifo_errors++;
8d5009f6 1706 netif_err(mdp, tx_err, ndev, "Transmit Descriptor Empty\n");
dc19e4e5
NI		 1707 }
1708
1709 if (intr_status & EESR_TFE) {
1710 /* FIFO under flow */
bb7d92e3 1711 ndev->stats.tx_fifo_errors++;
8d5009f6 1712 netif_err(mdp, tx_err, ndev, "Transmit FIFO Under flow\n");
86a74ff2
NI		 1713 }
1714
1715 if (intr_status & EESR_RDE) {
1716 /* Receive Descriptor Empty int */
bb7d92e3 1717 ndev->stats.rx_over_errors++;
86a74ff2 1718 }
dc19e4e5 1719
86a74ff2
NI		 1720 if (intr_status & EESR_RFE) {
1721 /* Receive FIFO Overflow int */
bb7d92e3 1722 ndev->stats.rx_fifo_errors++;
dc19e4e5
NI		 1723 }
1724
1725 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1726 /* Address Error */
bb7d92e3 1727 ndev->stats.tx_fifo_errors++;
8d5009f6 1728 netif_err(mdp, tx_err, ndev, "Address Error\n");
86a74ff2 1729 }
380af9e3
YS		 1730
1731 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1732 if (mdp->cd->no_ade)
1733 mask &= ~EESR_ADE;
1734 if (intr_status & mask) {
86a74ff2 1735 /* Tx error */
4a55530f 1736 u32 edtrr = sh_eth_read(ndev, EDTRR);
090d560f 1737
86a74ff2 1738 /* dmesg */
da246855
SS		 1739 netdev_err(ndev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1740 intr_status, mdp->cur_tx, mdp->dirty_tx,
1741 (u32)ndev->state, edtrr);
86a74ff2 1742 /* dirty buffer free */
1debdc8f 1743 sh_eth_tx_free(ndev, true);
86a74ff2
NI		 1744
1745 /* SH7712 BUG */
3e416992 1746 if (edtrr ^ mdp->cd->edtrr_trns) {
86a74ff2 1747 /* tx dma start */
3e416992 1748 sh_eth_write(ndev, mdp->cd->edtrr_trns, EDTRR);
86a74ff2
NI		 1749 }
1750 /* wakeup */
1751 netif_wake_queue(ndev);
1752 }
1753}
1754
1755static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1756{
1757 struct net_device *ndev = netdev;
1758 struct sh_eth_private *mdp = netdev_priv(ndev);
380af9e3 1759 struct sh_eth_cpu_data *cd = mdp->cd;
0e0fde3c 1760 irqreturn_t ret = IRQ_NONE;
0799c2d6 1761 u32 intr_status, intr_enable;
86a74ff2 1762
86a74ff2
NI		 1763 spin_lock(&mdp->lock);
1764
3893b273 1765 /* Get interrupt status */
4a55530f 1766 intr_status = sh_eth_read(ndev, EESR);
9b39f05c
SS		 1767 /* Mask it with the interrupt mask, forcing ECI interrupt to be always
1768 * enabled since it's the one that comes thru regardless of the mask,
1769 * and we need to fully handle it in sh_eth_emac_interrupt() in order
1770 * to quench it as it doesn't get cleared by just writing 1 to the ECI
1771 * bit...
3893b273 1772 */
3719109d 1773 intr_enable = sh_eth_read(ndev, EESIPR);
1a0bee6c 1774 intr_status &= intr_enable | EESIPR_ECIIP;
9b39f05c
SS		 1775 if (intr_status & (EESR_RX_CHECK | cd->tx_check | EESR_ECI |
1776 cd->eesr_err_check))
0e0fde3c 1777 ret = IRQ_HANDLED;
3719109d 1778 else
283e38db
BH		 1779 goto out;
1780
2344ef3c 1781 if (unlikely(!mdp->irq_enabled)) {
283e38db
BH		 1782 sh_eth_write(ndev, 0, EESIPR);
1783 goto out;
1784 }
86a74ff2 1785
3719109d
SS		 1786 if (intr_status & EESR_RX_CHECK) {
1787 if (napi_schedule_prep(&mdp->napi)) {
1788 /* Mask Rx interrupts */
1789 sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK,
1790 EESIPR);
1791 __napi_schedule(&mdp->napi);
1792 } else {
da246855 1793 netdev_warn(ndev,
0799c2d6 1794 "ignoring interrupt, status 0x%08x, mask 0x%08x.\n",
da246855 1795 intr_status, intr_enable);
3719109d
SS		 1796 }
1797 }
86a74ff2 1798
b0ca2a21 1799 /* Tx Check */
380af9e3 1800 if (intr_status & cd->tx_check) {
3719109d
SS		 1801 /* Clear Tx interrupts */
1802 sh_eth_write(ndev, intr_status & cd->tx_check, EESR);
1803
1debdc8f 1804 sh_eth_tx_free(ndev, true);
86a74ff2
NI		 1805 netif_wake_queue(ndev);
1806 }
1807
9b39f05c
SS		 1808 /* E-MAC interrupt */
1809 if (intr_status & EESR_ECI)
1810 sh_eth_emac_interrupt(ndev);
1811
3719109d
SS		 1812 if (intr_status & cd->eesr_err_check) {
1813 /* Clear error interrupts */
1814 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR);
1815
86a74ff2 1816 sh_eth_error(ndev, intr_status);
3719109d 1817 }
86a74ff2 1818
283e38db 1819out:
86a74ff2
NI		 1820 spin_unlock(&mdp->lock);
1821
0e0fde3c 1822 return ret;
86a74ff2
NI		 1823}
1824
3719109d
SS		 1825static int sh_eth_poll(struct napi_struct *napi, int budget)
1826{
1827 struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private,
1828 napi);
1829 struct net_device *ndev = napi->dev;
1830 int quota = budget;
0799c2d6 1831 u32 intr_status;
3719109d
SS		 1832
1833 for (;;) {
1834 intr_status = sh_eth_read(ndev, EESR);
1835 if (!(intr_status & EESR_RX_CHECK))
1836 break;
1837 /* Clear Rx interrupts */
1838 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR);
1839
1840 if (sh_eth_rx(ndev, intr_status, &quota))
1841 goto out;
1842 }
1843
1844 napi_complete(napi);
1845
1846 /* Reenable Rx interrupts */
283e38db
BH		 1847 if (mdp->irq_enabled)
1848 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
3719109d
SS		 1849out:
1850 return budget - quota;
1851}
1852
86a74ff2
NI		 1853/* PHY state control function */
1854static void sh_eth_adjust_link(struct net_device *ndev)
1855{
1856 struct sh_eth_private *mdp = netdev_priv(ndev);
9fd0375a 1857 struct phy_device *phydev = ndev->phydev;
86a74ff2
NI		 1858 int new_state = 0;
1859
3340d2aa 1860 if (phydev->link) {
86a74ff2
NI		 1861 if (phydev->duplex != mdp->duplex) {
1862 new_state = 1;
1863 mdp->duplex = phydev->duplex;
380af9e3
YS		 1864 if (mdp->cd->set_duplex)
1865 mdp->cd->set_duplex(ndev);
86a74ff2
NI		 1866 }
1867
1868 if (phydev->speed != mdp->speed) {
1869 new_state = 1;
1870 mdp->speed = phydev->speed;
380af9e3
YS		 1871 if (mdp->cd->set_rate)
1872 mdp->cd->set_rate(ndev);
86a74ff2 1873 }
3340d2aa 1874 if (!mdp->link) {
b2b14d2f 1875 sh_eth_modify(ndev, ECMR, ECMR_TXF, 0);
86a74ff2
NI		 1876 new_state = 1;
1877 mdp->link = phydev->link;
1e1b812b
SS		 1878 if (mdp->cd->no_psr || mdp->no_ether_link)
1879 sh_eth_rcv_snd_enable(ndev);
86a74ff2
NI		 1880 }
1881 } else if (mdp->link) {
1882 new_state = 1;
3340d2aa 1883 mdp->link = 0;
86a74ff2
NI		 1884 mdp->speed = 0;
1885 mdp->duplex = -1;
1e1b812b
SS		 1886 if (mdp->cd->no_psr || mdp->no_ether_link)
1887 sh_eth_rcv_snd_disable(ndev);
86a74ff2
NI		 1888 }
1889
dc19e4e5 1890 if (new_state && netif_msg_link(mdp))
86a74ff2
NI		 1891 phy_print_status(phydev);
1892}
1893
1894/* PHY init function */
1895static int sh_eth_phy_init(struct net_device *ndev)
1896{
702eca02 1897 struct device_node *np = ndev->dev.parent->of_node;
86a74ff2 1898 struct sh_eth_private *mdp = netdev_priv(ndev);
4fa8c3cc 1899 struct phy_device *phydev;
86a74ff2 1900
3340d2aa 1901 mdp->link = 0;
86a74ff2
NI		 1902 mdp->speed = 0;
1903 mdp->duplex = -1;
1904
1905 /* Try connect to PHY */
702eca02
BD		 1906 if (np) {
1907 struct device_node *pn;
1908
1909 pn = of_parse_phandle(np, "phy-handle", 0);
1910 phydev = of_phy_connect(ndev, pn,
1911 sh_eth_adjust_link, 0,
1912 mdp->phy_interface);
1913
8da703dc 1914 of_node_put(pn);
702eca02
BD		 1915 if (!phydev)
1916 phydev = ERR_PTR(-ENOENT);
1917 } else {
1918 char phy_id[MII_BUS_ID_SIZE + 3];
1919
1920 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
1921 mdp->mii_bus->id, mdp->phy_id);
1922
1923 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
1924 mdp->phy_interface);
1925 }
1926
86a74ff2 1927 if (IS_ERR(phydev)) {
da246855 1928 netdev_err(ndev, "failed to connect PHY\n");
86a74ff2
NI		 1929 return PTR_ERR(phydev);
1930 }
380af9e3 1931
2aab6b40
TP		 1932 /* mask with MAC supported features */
1933 if (mdp->cd->register_type != SH_ETH_REG_GIGABIT) {
1934 int err = phy_set_max_speed(phydev, SPEED_100);
1935 if (err) {
1936 netdev_err(ndev, "failed to limit PHY to 100 Mbit/s\n");
1937 phy_disconnect(phydev);
1938 return err;
1939 }
1940 }
1941
2220943a 1942 phy_attached_info(phydev);
86a74ff2 1943
86a74ff2
NI		 1944 return 0;
1945}
1946
1947/* PHY control start function */
1948static int sh_eth_phy_start(struct net_device *ndev)
1949{
86a74ff2
NI		 1950 int ret;
1951
1952 ret = sh_eth_phy_init(ndev);
1953 if (ret)
1954 return ret;
1955
9fd0375a 1956 phy_start(ndev->phydev);
86a74ff2
NI		 1957
1958 return 0;
1959}
1960
f08aff44
PR		 1961static int sh_eth_get_link_ksettings(struct net_device *ndev,
1962 struct ethtool_link_ksettings *cmd)
dc19e4e5
NI		 1963{
1964 struct sh_eth_private *mdp = netdev_priv(ndev);
1965 unsigned long flags;
dc19e4e5 1966
9fd0375a 1967 if (!ndev->phydev)
4f9dce23
BH		 1968 return -ENODEV;
1969
dc19e4e5 1970 spin_lock_irqsave(&mdp->lock, flags);
5514174f 1971 phy_ethtool_ksettings_get(ndev->phydev, cmd);
dc19e4e5
NI		 1972 spin_unlock_irqrestore(&mdp->lock, flags);
1973
5514174f 1974 return 0;
dc19e4e5
NI		 1975}
1976
f08aff44
PR		 1977static int sh_eth_set_link_ksettings(struct net_device *ndev,
1978 const struct ethtool_link_ksettings *cmd)
dc19e4e5
NI		 1979{
1980 struct sh_eth_private *mdp = netdev_priv(ndev);
1981 unsigned long flags;
1982 int ret;
dc19e4e5 1983
9fd0375a 1984 if (!ndev->phydev)
4f9dce23
BH		 1985 return -ENODEV;
1986
dc19e4e5
NI		 1987 spin_lock_irqsave(&mdp->lock, flags);
1988
1989 /* disable tx and rx */
4a55530f 1990 sh_eth_rcv_snd_disable(ndev);
dc19e4e5 1991
f08aff44 1992 ret = phy_ethtool_ksettings_set(ndev->phydev, cmd);
dc19e4e5
NI		 1993 if (ret)
1994 goto error_exit;
1995
f08aff44 1996 if (cmd->base.duplex == DUPLEX_FULL)
dc19e4e5
NI		 1997 mdp->duplex = 1;
1998 else
1999 mdp->duplex = 0;
2000
2001 if (mdp->cd->set_duplex)
2002 mdp->cd->set_duplex(ndev);
2003
2004error_exit:
2005 mdelay(1);
2006
2007 /* enable tx and rx */
4a55530f 2008 sh_eth_rcv_snd_enable(ndev);
dc19e4e5
NI		 2009
2010 spin_unlock_irqrestore(&mdp->lock, flags);
2011
2012 return ret;
2013}
2014
6b4b4fea
BH		 2015/* If it is ever necessary to increase SH_ETH_REG_DUMP_MAX_REGS, the
2016 * version must be bumped as well. Just adding registers up to that
2017 * limit is fine, as long as the existing register indices don't
2018 * change.
2019 */
2020#define SH_ETH_REG_DUMP_VERSION 1
2021#define SH_ETH_REG_DUMP_MAX_REGS 256
2022
2023static size_t __sh_eth_get_regs(struct net_device *ndev, u32 *buf)
2024{
2025 struct sh_eth_private *mdp = netdev_priv(ndev);
2026 struct sh_eth_cpu_data *cd = mdp->cd;
2027 u32 *valid_map;
2028 size_t len;
2029
2030 BUILD_BUG_ON(SH_ETH_MAX_REGISTER_OFFSET > SH_ETH_REG_DUMP_MAX_REGS);
2031
2032 /* Dump starts with a bitmap that tells ethtool which
2033 * registers are defined for this chip.
2034 */
2035 len = DIV_ROUND_UP(SH_ETH_REG_DUMP_MAX_REGS, 32);
2036 if (buf) {
2037 valid_map = buf;
2038 buf += len;
2039 } else {
2040 valid_map = NULL;
2041 }
2042
2043 /* Add a register to the dump, if it has a defined offset.
2044 * This automatically skips most undefined registers, but for
2045 * some it is also necessary to check a capability flag in
2046 * struct sh_eth_cpu_data.
2047 */
2048#define mark_reg_valid(reg) valid_map[reg / 32] |= 1U << (reg % 32)
2049#define add_reg_from(reg, read_expr) do { \
2050 if (mdp->reg_offset[reg] != SH_ETH_OFFSET_INVALID) { \
2051 if (buf) { \
2052 mark_reg_valid(reg); \
2053 *buf++ = read_expr; \
2054 } \
2055 ++len; \
2056 } \
2057 } while (0)
2058#define add_reg(reg) add_reg_from(reg, sh_eth_read(ndev, reg))
2059#define add_tsu_reg(reg) add_reg_from(reg, sh_eth_tsu_read(mdp, reg))
2060
2061 add_reg(EDSR);
2062 add_reg(EDMR);
2063 add_reg(EDTRR);
2064 add_reg(EDRRR);
2065 add_reg(EESR);
2066 add_reg(EESIPR);
2067 add_reg(TDLAR);
2068 add_reg(TDFAR);
2069 add_reg(TDFXR);
2070 add_reg(TDFFR);
2071 add_reg(RDLAR);
2072 add_reg(RDFAR);
2073 add_reg(RDFXR);
2074 add_reg(RDFFR);
2075 add_reg(TRSCER);
2076 add_reg(RMFCR);
2077 add_reg(TFTR);
2078 add_reg(FDR);
2079 add_reg(RMCR);
2080 add_reg(TFUCR);
2081 add_reg(RFOCR);
2082 if (cd->rmiimode)
2083 add_reg(RMIIMODE);
2084 add_reg(FCFTR);
2085 if (cd->rpadir)
2086 add_reg(RPADIR);
2087 if (!cd->no_trimd)
2088 add_reg(TRIMD);
2089 add_reg(ECMR);
2090 add_reg(ECSR);
2091 add_reg(ECSIPR);
2092 add_reg(PIR);
2093 if (!cd->no_psr)
2094 add_reg(PSR);
2095 add_reg(RDMLR);
2096 add_reg(RFLR);
2097 add_reg(IPGR);
2098 if (cd->apr)
2099 add_reg(APR);
2100 if (cd->mpr)
2101 add_reg(MPR);
2102 add_reg(RFCR);
2103 add_reg(RFCF);
2104 if (cd->tpauser)
2105 add_reg(TPAUSER);
2106 add_reg(TPAUSECR);
2107 add_reg(GECMR);
2108 if (cd->bculr)
2109 add_reg(BCULR);
2110 add_reg(MAHR);
2111 add_reg(MALR);
2112 add_reg(TROCR);
2113 add_reg(CDCR);
2114 add_reg(LCCR);
2115 add_reg(CNDCR);
2116 add_reg(CEFCR);
2117 add_reg(FRECR);
2118 add_reg(TSFRCR);
2119 add_reg(TLFRCR);
2120 add_reg(CERCR);
2121 add_reg(CEECR);
2122 add_reg(MAFCR);
2123 if (cd->rtrate)
2124 add_reg(RTRATE);
62e04b7e 2125 if (cd->hw_checksum)
6b4b4fea
BH		 2126 add_reg(CSMR);
2127 if (cd->select_mii)
2128 add_reg(RMII_MII);
6b4b4fea 2129 if (cd->tsu) {
17d0fb0c 2130 add_tsu_reg(ARSTR);
6b4b4fea
BH		 2131 add_tsu_reg(TSU_CTRST);
2132 add_tsu_reg(TSU_FWEN0);
2133 add_tsu_reg(TSU_FWEN1);
2134 add_tsu_reg(TSU_FCM);
2135 add_tsu_reg(TSU_BSYSL0);
2136 add_tsu_reg(TSU_BSYSL1);
2137 add_tsu_reg(TSU_PRISL0);
2138 add_tsu_reg(TSU_PRISL1);
2139 add_tsu_reg(TSU_FWSL0);
2140 add_tsu_reg(TSU_FWSL1);
2141 add_tsu_reg(TSU_FWSLC);
6b4b4fea
BH		 2142 add_tsu_reg(TSU_QTAGM0);
2143 add_tsu_reg(TSU_QTAGM1);
2144 add_tsu_reg(TSU_FWSR);
2145 add_tsu_reg(TSU_FWINMK);
2146 add_tsu_reg(TSU_ADQT0);
2147 add_tsu_reg(TSU_ADQT1);
2148 add_tsu_reg(TSU_VTAG0);
2149 add_tsu_reg(TSU_VTAG1);
2150 add_tsu_reg(TSU_ADSBSY);
2151 add_tsu_reg(TSU_TEN);
2152 add_tsu_reg(TSU_POST1);
2153 add_tsu_reg(TSU_POST2);
2154 add_tsu_reg(TSU_POST3);
2155 add_tsu_reg(TSU_POST4);
e14549a5
SS		 2156 /* This is the start of a table, not just a single register. */
2157 if (buf) {
2158 unsigned int i;
2159
2160 mark_reg_valid(TSU_ADRH0);
2161 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES * 2; i++)
2162 *buf++ = ioread32(mdp->tsu_addr +
2163 mdp->reg_offset[TSU_ADRH0] +
2164 i * 4);
6b4b4fea 2165 }
e14549a5 2166 len += SH_ETH_TSU_CAM_ENTRIES * 2;
6b4b4fea
BH		 2167 }
2168
2169#undef mark_reg_valid
2170#undef add_reg_from
2171#undef add_reg
2172#undef add_tsu_reg
2173
2174 return len * 4;
2175}
2176
2177static int sh_eth_get_regs_len(struct net_device *ndev)
2178{
2179 return __sh_eth_get_regs(ndev, NULL);
2180}
2181
2182static void sh_eth_get_regs(struct net_device *ndev, struct ethtool_regs *regs,
2183 void *buf)
2184{
2185 struct sh_eth_private *mdp = netdev_priv(ndev);
2186
2187 regs->version = SH_ETH_REG_DUMP_VERSION;
2188
2189 pm_runtime_get_sync(&mdp->pdev->dev);
2190 __sh_eth_get_regs(ndev, buf);
2191 pm_runtime_put_sync(&mdp->pdev->dev);
2192}
2193
dc19e4e5
NI		 2194static int sh_eth_nway_reset(struct net_device *ndev)
2195{
2196 struct sh_eth_private *mdp = netdev_priv(ndev);
2197 unsigned long flags;
2198 int ret;
2199
9fd0375a 2200 if (!ndev->phydev)
4f9dce23
BH		 2201 return -ENODEV;
2202
dc19e4e5 2203 spin_lock_irqsave(&mdp->lock, flags);
9fd0375a 2204 ret = phy_start_aneg(ndev->phydev);
dc19e4e5
NI		 2205 spin_unlock_irqrestore(&mdp->lock, flags);
2206
2207 return ret;
2208}
2209
2210static u32 sh_eth_get_msglevel(struct net_device *ndev)
2211{
2212 struct sh_eth_private *mdp = netdev_priv(ndev);
2213 return mdp->msg_enable;
2214}
2215
2216static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
2217{
2218 struct sh_eth_private *mdp = netdev_priv(ndev);
2219 mdp->msg_enable = value;
2220}
2221
2222static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
2223 "rx_current", "tx_current",
2224 "rx_dirty", "tx_dirty",
2225};
2226#define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats)
2227
2228static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
2229{
2230 switch (sset) {
2231 case ETH_SS_STATS:
2232 return SH_ETH_STATS_LEN;
2233 default:
2234 return -EOPNOTSUPP;
2235 }
2236}
2237
2238static void sh_eth_get_ethtool_stats(struct net_device *ndev,
128296fc 2239 struct ethtool_stats *stats, u64 *data)
dc19e4e5
NI		 2240{
2241 struct sh_eth_private *mdp = netdev_priv(ndev);
2242 int i = 0;
2243
2244 /* device-specific stats */
2245 data[i++] = mdp->cur_rx;
2246 data[i++] = mdp->cur_tx;
2247 data[i++] = mdp->dirty_rx;
2248 data[i++] = mdp->dirty_tx;
2249}
2250
2251static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
2252{
2253 switch (stringset) {
2254 case ETH_SS_STATS:
2255 memcpy(data, *sh_eth_gstrings_stats,
128296fc 2256 sizeof(sh_eth_gstrings_stats));
dc19e4e5
NI		 2257 break;
2258 }
2259}
2260
525b8075
YS		 2261static void sh_eth_get_ringparam(struct net_device *ndev,
2262 struct ethtool_ringparam *ring)
2263{
2264 struct sh_eth_private *mdp = netdev_priv(ndev);
2265
2266 ring->rx_max_pending = RX_RING_MAX;
2267 ring->tx_max_pending = TX_RING_MAX;
2268 ring->rx_pending = mdp->num_rx_ring;
2269 ring->tx_pending = mdp->num_tx_ring;
2270}
2271
2272static int sh_eth_set_ringparam(struct net_device *ndev,
2273 struct ethtool_ringparam *ring)
2274{
2275 struct sh_eth_private *mdp = netdev_priv(ndev);
2276 int ret;
2277
2278 if (ring->tx_pending > TX_RING_MAX ||
2279 ring->rx_pending > RX_RING_MAX ||
2280 ring->tx_pending < TX_RING_MIN ||
2281 ring->rx_pending < RX_RING_MIN)
2282 return -EINVAL;
2283 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
2284 return -EINVAL;
2285
2286 if (netif_running(ndev)) {
bd888916 2287 netif_device_detach(ndev);
525b8075 2288 netif_tx_disable(ndev);
283e38db
BH		 2289
2290 /* Serialise with the interrupt handler and NAPI, then
2291 * disable interrupts. We have to clear the
2292 * irq_enabled flag first to ensure that interrupts
2293 * won't be re-enabled.
2294 */
2295 mdp->irq_enabled = false;
525b8075 2296 synchronize_irq(ndev->irq);
283e38db 2297 napi_synchronize(&mdp->napi);
525b8075 2298 sh_eth_write(ndev, 0x0000, EESIPR);
525b8075 2299
740c7f31 2300 sh_eth_dev_exit(ndev);
525b8075 2301
8e03a5e7 2302 /* Free all the skbuffs in the Rx queue and the DMA buffers. */
084236d8 2303 sh_eth_ring_free(ndev);
084236d8 2304 }
525b8075
YS		 2305
2306 /* Set new parameters */
2307 mdp->num_rx_ring = ring->rx_pending;
2308 mdp->num_tx_ring = ring->tx_pending;
2309
525b8075 2310 if (netif_running(ndev)) {
084236d8
BH		 2311 ret = sh_eth_ring_init(ndev);
2312 if (ret < 0) {
2313 netdev_err(ndev, "%s: sh_eth_ring_init failed.\n",
2314 __func__);
2315 return ret;
2316 }
f7967210 2317 ret = sh_eth_dev_init(ndev);
084236d8
BH		 2318 if (ret < 0) {
2319 netdev_err(ndev, "%s: sh_eth_dev_init failed.\n",
2320 __func__);
2321 return ret;
2322 }
2323
bd888916 2324 netif_device_attach(ndev);
525b8075
YS		 2325 }
2326
2327 return 0;
2328}
2329
d8981d02
NS		 2330static void sh_eth_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2331{
2332 struct sh_eth_private *mdp = netdev_priv(ndev);
2333
2334 wol->supported = 0;
2335 wol->wolopts = 0;
2336
b4580c95 2337 if (mdp->cd->magic) {
d8981d02
NS		 2338 wol->supported = WAKE_MAGIC;
2339 wol->wolopts = mdp->wol_enabled ? WAKE_MAGIC : 0;
2340 }
2341}
2342
2343static int sh_eth_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2344{
2345 struct sh_eth_private *mdp = netdev_priv(ndev);
2346
b4580c95 2347 if (!mdp->cd->magic || wol->wolopts & ~WAKE_MAGIC)
d8981d02
NS		 2348 return -EOPNOTSUPP;
2349
2350 mdp->wol_enabled = !!(wol->wolopts & WAKE_MAGIC);
2351
2352 device_set_wakeup_enable(&mdp->pdev->dev, mdp->wol_enabled);
2353
2354 return 0;
2355}
2356
9b07be4b 2357static const struct ethtool_ops sh_eth_ethtool_ops = {
6b4b4fea
BH		 2358 .get_regs_len = sh_eth_get_regs_len,
2359 .get_regs = sh_eth_get_regs,
9b07be4b 2360 .nway_reset = sh_eth_nway_reset,
dc19e4e5
NI		 2361 .get_msglevel = sh_eth_get_msglevel,
2362 .set_msglevel = sh_eth_set_msglevel,
9b07be4b 2363 .get_link = ethtool_op_get_link,
dc19e4e5
NI		 2364 .get_strings = sh_eth_get_strings,
2365 .get_ethtool_stats = sh_eth_get_ethtool_stats,
2366 .get_sset_count = sh_eth_get_sset_count,
525b8075
YS		 2367 .get_ringparam = sh_eth_get_ringparam,
2368 .set_ringparam = sh_eth_set_ringparam,
f08aff44
PR		 2369 .get_link_ksettings = sh_eth_get_link_ksettings,
2370 .set_link_ksettings = sh_eth_set_link_ksettings,
d8981d02
NS		 2371 .get_wol = sh_eth_get_wol,
2372 .set_wol = sh_eth_set_wol,
dc19e4e5
NI		 2373};
2374
86a74ff2
NI		 2375/* network device open function */
2376static int sh_eth_open(struct net_device *ndev)
2377{
86a74ff2 2378 struct sh_eth_private *mdp = netdev_priv(ndev);
4fa8c3cc 2379 int ret;
86a74ff2 2380
bcd5149d
MD		 2381 pm_runtime_get_sync(&mdp->pdev->dev);
2382
d2779e99
SS		 2383 napi_enable(&mdp->napi);
2384
a0607fd3 2385 ret = request_irq(ndev->irq, sh_eth_interrupt,
5b3dfd13 2386 mdp->cd->irq_flags, ndev->name, ndev);
86a74ff2 2387 if (ret) {
da246855 2388 netdev_err(ndev, "Can not assign IRQ number\n");
d2779e99 2389 goto out_napi_off;
86a74ff2
NI		 2390 }
2391
2392 /* Descriptor set */
2393 ret = sh_eth_ring_init(ndev);
2394 if (ret)
2395 goto out_free_irq;
2396
2397 /* device init */
f7967210 2398 ret = sh_eth_dev_init(ndev);
86a74ff2
NI		 2399 if (ret)
2400 goto out_free_irq;
2401
2402 /* PHY control start*/
2403 ret = sh_eth_phy_start(ndev);
2404 if (ret)
2405 goto out_free_irq;
2406
ad846aa5
SS		 2407 netif_start_queue(ndev);
2408
7fa2955f
MK		 2409 mdp->is_opened = 1;
2410
86a74ff2
NI		 2411 return ret;
2412
2413out_free_irq:
2414 free_irq(ndev->irq, ndev);
d2779e99
SS		 2415out_napi_off:
2416 napi_disable(&mdp->napi);
bcd5149d 2417 pm_runtime_put_sync(&mdp->pdev->dev);
86a74ff2
NI		 2418 return ret;
2419}
2420
2421/* Timeout function */
2422static void sh_eth_tx_timeout(struct net_device *ndev)
2423{
2424 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 2425 struct sh_eth_rxdesc *rxdesc;
2426 int i;
2427
2428 netif_stop_queue(ndev);
2429
8d5009f6
SS		 2430 netif_err(mdp, timer, ndev,
2431 "transmit timed out, status %8.8x, resetting...\n",
0799c2d6 2432 sh_eth_read(ndev, EESR));
86a74ff2
NI		 2433
2434 /* tx_errors count up */
bb7d92e3 2435 ndev->stats.tx_errors++;
86a74ff2 2436
86a74ff2 2437 /* Free all the skbuffs in the Rx queue. */
525b8075 2438 for (i = 0; i < mdp->num_rx_ring; i++) {
86a74ff2 2439 rxdesc = &mdp->rx_ring[i];
7cf72477
SS		 2440 rxdesc->status = cpu_to_le32(0);
2441 rxdesc->addr = cpu_to_le32(0xBADF00D0);
179d80af 2442 dev_kfree_skb(mdp->rx_skbuff[i]);
86a74ff2
NI		 2443 mdp->rx_skbuff[i] = NULL;
2444 }
525b8075 2445 for (i = 0; i < mdp->num_tx_ring; i++) {
179d80af 2446 dev_kfree_skb(mdp->tx_skbuff[i]);
86a74ff2
NI		 2447 mdp->tx_skbuff[i] = NULL;
2448 }
2449
2450 /* device init */
f7967210 2451 sh_eth_dev_init(ndev);
ad846aa5
SS		 2452
2453 netif_start_queue(ndev);
86a74ff2
NI		 2454}
2455
2456/* Packet transmit function */
2457static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
2458{
2459 struct sh_eth_private *mdp = netdev_priv(ndev);
2460 struct sh_eth_txdesc *txdesc;
1299653a 2461 dma_addr_t dma_addr;
86a74ff2 2462 u32 entry;
fb5e2f9b 2463 unsigned long flags;
86a74ff2
NI		 2464
2465 spin_lock_irqsave(&mdp->lock, flags);
525b8075 2466 if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
1debdc8f 2467 if (!sh_eth_tx_free(ndev, true)) {
8d5009f6 2468 netif_warn(mdp, tx_queued, ndev, "TxFD exhausted.\n");
86a74ff2
NI		 2469 netif_stop_queue(ndev);
2470 spin_unlock_irqrestore(&mdp->lock, flags);
5b548140 2471 return NETDEV_TX_BUSY;
86a74ff2
NI		 2472 }
2473 }
2474 spin_unlock_irqrestore(&mdp->lock, flags);
2475
dacc73e0 2476 if (skb_put_padto(skb, ETH_ZLEN))
eebfb643
BH		 2477 return NETDEV_TX_OK;
2478
525b8075 2479 entry = mdp->cur_tx % mdp->num_tx_ring;
86a74ff2
NI		 2480 mdp->tx_skbuff[entry] = skb;
2481 txdesc = &mdp->tx_ring[entry];
86a74ff2 2482 /* soft swap. */
380af9e3 2483 if (!mdp->cd->hw_swap)
3e230993 2484 sh_eth_soft_swap(PTR_ALIGN(skb->data, 4), skb->len + 2);
22c1aed4 2485 dma_addr = dma_map_single(&mdp->pdev->dev, skb->data, skb->len,
1299653a 2486 DMA_TO_DEVICE);
22c1aed4 2487 if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) {
aa3933b8
BH		 2488 kfree_skb(skb);
2489 return NETDEV_TX_OK;
2490 }
7cf72477
SS		 2491 txdesc->addr = cpu_to_le32(dma_addr);
2492 txdesc->len = cpu_to_le32(skb->len << 16);
86a74ff2 2493
f32bfb9a 2494 dma_wmb(); /* TACT bit must be set after all the above writes */
525b8075 2495 if (entry >= mdp->num_tx_ring - 1)
7cf72477 2496 txdesc->status |= cpu_to_le32(TD_TACT | TD_TDLE);
86a74ff2 2497 else
7cf72477 2498 txdesc->status |= cpu_to_le32(TD_TACT);
86a74ff2
NI		 2499
2500 mdp->cur_tx++;
2501
3e416992
SS		 2502 if (!(sh_eth_read(ndev, EDTRR) & mdp->cd->edtrr_trns))
2503 sh_eth_write(ndev, mdp->cd->edtrr_trns, EDTRR);
b0ca2a21 2504
6ed10654 2505 return NETDEV_TX_OK;
86a74ff2
NI		 2506}
2507
4398f9c8
BH		 2508/* The statistics registers have write-clear behaviour, which means we
2509 * will lose any increment between the read and write. We mitigate
2510 * this by only clearing when we read a non-zero value, so we will
2511 * never falsely report a total of zero.
2512 */
2513static void
2514sh_eth_update_stat(struct net_device *ndev, unsigned long *stat, int reg)
2515{
2516 u32 delta = sh_eth_read(ndev, reg);
2517
2518 if (delta) {
2519 *stat += delta;
2520 sh_eth_write(ndev, 0, reg);
2521 }
2522}
2523
7fa2955f
MK		 2524static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
2525{
2526 struct sh_eth_private *mdp = netdev_priv(ndev);
2527
ce9134df 2528 if (mdp->cd->no_tx_cntrs)
7fa2955f
MK		 2529 return &ndev->stats;
2530
2531 if (!mdp->is_opened)
2532 return &ndev->stats;
2533
4398f9c8
BH		 2534 sh_eth_update_stat(ndev, &ndev->stats.tx_dropped, TROCR);
2535 sh_eth_update_stat(ndev, &ndev->stats.collisions, CDCR);
2536 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, LCCR);
7fa2955f 2537
4c1d4585 2538 if (mdp->cd->cexcr) {
4398f9c8
BH		 2539 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2540 CERCR);
2541 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2542 CEECR);
7fa2955f 2543 } else {
4398f9c8
BH		 2544 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2545 CNDCR);
7fa2955f
MK		 2546 }
2547
2548 return &ndev->stats;
2549}
2550
86a74ff2
NI		 2551/* device close function */
2552static int sh_eth_close(struct net_device *ndev)
2553{
2554 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 2555
2556 netif_stop_queue(ndev);
2557
283e38db
BH		 2558 /* Serialise with the interrupt handler and NAPI, then disable
2559 * interrupts. We have to clear the irq_enabled flag first to
2560 * ensure that interrupts won't be re-enabled.
2561 */
2562 mdp->irq_enabled = false;
2563 synchronize_irq(ndev->irq);
2564 napi_disable(&mdp->napi);
4a55530f 2565 sh_eth_write(ndev, 0x0000, EESIPR);
86a74ff2 2566
740c7f31 2567 sh_eth_dev_exit(ndev);
86a74ff2
NI		 2568
2569 /* PHY Disconnect */
9fd0375a
PR		 2570 if (ndev->phydev) {
2571 phy_stop(ndev->phydev);
2572 phy_disconnect(ndev->phydev);
86a74ff2
NI		 2573 }
2574
2575 free_irq(ndev->irq, ndev);
2576
8e03a5e7 2577 /* Free all the skbuffs in the Rx queue and the DMA buffer. */
86a74ff2
NI		 2578 sh_eth_ring_free(ndev);
2579
bcd5149d
MD		 2580 pm_runtime_put_sync(&mdp->pdev->dev);
2581
7fa2955f 2582 mdp->is_opened = 0;
bcd5149d 2583
7fa2955f 2584 return 0;
86a74ff2
NI		 2585}
2586
bb7d92e3 2587/* ioctl to device function */
128296fc 2588static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
86a74ff2 2589{
9fd0375a 2590 struct phy_device *phydev = ndev->phydev;
86a74ff2
NI		 2591
2592 if (!netif_running(ndev))
2593 return -EINVAL;
2594
2595 if (!phydev)
2596 return -ENODEV;
2597
28b04113 2598 return phy_mii_ioctl(phydev, rq, cmd);
86a74ff2
NI		 2599}
2600
78d61022
NS		 2601static int sh_eth_change_mtu(struct net_device *ndev, int new_mtu)
2602{
2603 if (netif_running(ndev))
2604 return -EBUSY;
2605
2606 ndev->mtu = new_mtu;
2607 netdev_update_features(ndev);
2608
2609 return 0;
2610}
2611
6743fe6d 2612/* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
6743fe6d
YS		 2613static u32 sh_eth_tsu_get_post_mask(int entry)
2614{
2615 return 0x0f << (28 - ((entry % 8) * 4));
2616}
2617
2618static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
2619{
2620 return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
2621}
2622
2623static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
2624 int entry)
2625{
2626 struct sh_eth_private *mdp = netdev_priv(ndev);
77cb065f 2627 int reg = TSU_POST1 + entry / 8;
6743fe6d 2628 u32 tmp;
6743fe6d 2629
77cb065f
SS		 2630 tmp = sh_eth_tsu_read(mdp, reg);
2631 sh_eth_tsu_write(mdp, tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg);
6743fe6d
YS		 2632}
2633
2634static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
2635 int entry)
2636{
2637 struct sh_eth_private *mdp = netdev_priv(ndev);
77cb065f 2638 int reg = TSU_POST1 + entry / 8;
6743fe6d 2639 u32 post_mask, ref_mask, tmp;
6743fe6d 2640
6743fe6d
YS		 2641 post_mask = sh_eth_tsu_get_post_mask(entry);
2642 ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
2643
77cb065f
SS		 2644 tmp = sh_eth_tsu_read(mdp, reg);
2645 sh_eth_tsu_write(mdp, tmp & ~post_mask, reg);
6743fe6d
YS		 2646
2647 /* If other port enables, the function returns "true" */
2648 return tmp & ref_mask;
2649}
2650
2651static int sh_eth_tsu_busy(struct net_device *ndev)
2652{
2653 int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
2654 struct sh_eth_private *mdp = netdev_priv(ndev);
2655
2656 while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
2657 udelay(10);
2658 timeout--;
2659 if (timeout <= 0) {
da246855 2660 netdev_err(ndev, "%s: timeout\n", __func__);
6743fe6d
YS		 2661 return -ETIMEDOUT;
2662 }
2663 }
2664
2665 return 0;
2666}
2667
2668static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg,
2669 const u8 *addr)
2670{
2671 u32 val;
2672
2673 val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
2674 iowrite32(val, reg);
2675 if (sh_eth_tsu_busy(ndev) < 0)
2676 return -EBUSY;
2677
2678 val = addr[4] << 8 | addr[5];
2679 iowrite32(val, reg + 4);
2680 if (sh_eth_tsu_busy(ndev) < 0)
2681 return -EBUSY;
2682
2683 return 0;
2684}
2685
2686static void sh_eth_tsu_read_entry(void *reg, u8 *addr)
2687{
2688 u32 val;
2689
2690 val = ioread32(reg);
2691 addr[0] = (val >> 24) & 0xff;
2692 addr[1] = (val >> 16) & 0xff;
2693 addr[2] = (val >> 8) & 0xff;
2694 addr[3] = val & 0xff;
2695 val = ioread32(reg + 4);
2696 addr[4] = (val >> 8) & 0xff;
2697 addr[5] = val & 0xff;
2698}
2699
2700
2701static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
2702{
2703 struct sh_eth_private *mdp = netdev_priv(ndev);
2704 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2705 int i;
2706 u8 c_addr[ETH_ALEN];
2707
2708 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2709 sh_eth_tsu_read_entry(reg_offset, c_addr);
c4bde29c 2710 if (ether_addr_equal(addr, c_addr))
6743fe6d
YS		 2711 return i;
2712 }
2713
2714 return -ENOENT;
2715}
2716
2717static int sh_eth_tsu_find_empty(struct net_device *ndev)
2718{
2719 u8 blank[ETH_ALEN];
2720 int entry;
2721
2722 memset(blank, 0, sizeof(blank));
2723 entry = sh_eth_tsu_find_entry(ndev, blank);
2724 return (entry < 0) ? -ENOMEM : entry;
2725}
2726
2727static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
2728 int entry)
2729{
2730 struct sh_eth_private *mdp = netdev_priv(ndev);
2731 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2732 int ret;
2733 u8 blank[ETH_ALEN];
2734
2735 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
2736 ~(1 << (31 - entry)), TSU_TEN);
2737
2738 memset(blank, 0, sizeof(blank));
2739 ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
2740 if (ret < 0)
2741 return ret;
2742 return 0;
2743}
2744
2745static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
2746{
2747 struct sh_eth_private *mdp = netdev_priv(ndev);
2748 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2749 int i, ret;
2750
2751 if (!mdp->cd->tsu)
2752 return 0;
2753
2754 i = sh_eth_tsu_find_entry(ndev, addr);
2755 if (i < 0) {
2756 /* No entry found, create one */
2757 i = sh_eth_tsu_find_empty(ndev);
2758 if (i < 0)
2759 return -ENOMEM;
2760 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
2761 if (ret < 0)
2762 return ret;
2763
2764 /* Enable the entry */
2765 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
2766 (1 << (31 - i)), TSU_TEN);
2767 }
2768
2769 /* Entry found or created, enable POST */
2770 sh_eth_tsu_enable_cam_entry_post(ndev, i);
2771
2772 return 0;
2773}
2774
2775static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
2776{
2777 struct sh_eth_private *mdp = netdev_priv(ndev);
2778 int i, ret;
2779
2780 if (!mdp->cd->tsu)
2781 return 0;
2782
2783 i = sh_eth_tsu_find_entry(ndev, addr);
2784 if (i) {
2785 /* Entry found */
2786 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2787 goto done;
2788
2789 /* Disable the entry if both ports was disabled */
2790 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2791 if (ret < 0)
2792 return ret;
2793 }
2794done:
2795 return 0;
2796}
2797
2798static int sh_eth_tsu_purge_all(struct net_device *ndev)
2799{
2800 struct sh_eth_private *mdp = netdev_priv(ndev);
2801 int i, ret;
2802
b37feed7 2803 if (!mdp->cd->tsu)
6743fe6d
YS		 2804 return 0;
2805
2806 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
2807 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2808 continue;
2809
2810 /* Disable the entry if both ports was disabled */
2811 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2812 if (ret < 0)
2813 return ret;
2814 }
2815
2816 return 0;
2817}
2818
2819static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
2820{
2821 struct sh_eth_private *mdp = netdev_priv(ndev);
2822 u8 addr[ETH_ALEN];
2823 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2824 int i;
2825
b37feed7 2826 if (!mdp->cd->tsu)
6743fe6d
YS		 2827 return;
2828
2829 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2830 sh_eth_tsu_read_entry(reg_offset, addr);
2831 if (is_multicast_ether_addr(addr))
2832 sh_eth_tsu_del_entry(ndev, addr);
2833 }
2834}
2835
b37feed7
BH		 2836/* Update promiscuous flag and multicast filter */
2837static void sh_eth_set_rx_mode(struct net_device *ndev)
86a74ff2 2838{
6743fe6d
YS		 2839 struct sh_eth_private *mdp = netdev_priv(ndev);
2840 u32 ecmr_bits;
2841 int mcast_all = 0;
2842 unsigned long flags;
2843
2844 spin_lock_irqsave(&mdp->lock, flags);
128296fc 2845 /* Initial condition is MCT = 1, PRM = 0.
6743fe6d
YS		 2846 * Depending on ndev->flags, set PRM or clear MCT
2847 */
b37feed7
BH		 2848 ecmr_bits = sh_eth_read(ndev, ECMR) & ~ECMR_PRM;
2849 if (mdp->cd->tsu)
2850 ecmr_bits |= ECMR_MCT;
6743fe6d
YS		 2851
2852 if (!(ndev->flags & IFF_MULTICAST)) {
2853 sh_eth_tsu_purge_mcast(ndev);
2854 mcast_all = 1;
2855 }
2856 if (ndev->flags & IFF_ALLMULTI) {
2857 sh_eth_tsu_purge_mcast(ndev);
2858 ecmr_bits &= ~ECMR_MCT;
2859 mcast_all = 1;
2860 }
2861
86a74ff2 2862 if (ndev->flags & IFF_PROMISC) {
6743fe6d
YS		 2863 sh_eth_tsu_purge_all(ndev);
2864 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2865 } else if (mdp->cd->tsu) {
2866 struct netdev_hw_addr *ha;
2867 netdev_for_each_mc_addr(ha, ndev) {
2868 if (mcast_all && is_multicast_ether_addr(ha->addr))
2869 continue;
2870
2871 if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2872 if (!mcast_all) {
2873 sh_eth_tsu_purge_mcast(ndev);
2874 ecmr_bits &= ~ECMR_MCT;
2875 mcast_all = 1;
2876 }
2877 }
2878 }
86a74ff2 2879 }
6743fe6d
YS		 2880
2881 /* update the ethernet mode */
2882 sh_eth_write(ndev, ecmr_bits, ECMR);
2883
2884 spin_unlock_irqrestore(&mdp->lock, flags);
86a74ff2 2885}
71cc7c37
YS		 2886
2887static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2888{
2889 if (!mdp->port)
2890 return TSU_VTAG0;
2891 else
2892 return TSU_VTAG1;
2893}
2894
80d5c368
PM		 2895static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
2896 __be16 proto, u16 vid)
71cc7c37
YS		 2897{
2898 struct sh_eth_private *mdp = netdev_priv(ndev);
2899 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2900
2901 if (unlikely(!mdp->cd->tsu))
2902 return -EPERM;
2903
2904 /* No filtering if vid = 0 */
2905 if (!vid)
2906 return 0;
2907
2908 mdp->vlan_num_ids++;
2909
128296fc 2910 /* The controller has one VLAN tag HW filter. So, if the filter is
71cc7c37
YS		 2911 * already enabled, the driver disables it and the filte
2912 */
2913 if (mdp->vlan_num_ids > 1) {
2914 /* disable VLAN filter */
2915 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2916 return 0;
2917 }
2918
2919 sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
2920 vtag_reg_index);
2921
2922 return 0;
2923}
2924
80d5c368
PM		 2925static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
2926 __be16 proto, u16 vid)
71cc7c37
YS		 2927{
2928 struct sh_eth_private *mdp = netdev_priv(ndev);
2929 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2930
2931 if (unlikely(!mdp->cd->tsu))
2932 return -EPERM;
2933
2934 /* No filtering if vid = 0 */
2935 if (!vid)
2936 return 0;
2937
2938 mdp->vlan_num_ids--;
2939 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2940
2941 return 0;
2942}
86a74ff2
NI		 2943
2944/* SuperH's TSU register init function */
4a55530f 2945static void sh_eth_tsu_init(struct sh_eth_private *mdp)
86a74ff2 2946{
a94cf2a6 2947 if (!mdp->cd->dual_port) {
db893473 2948 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
e1487888
CB		 2949 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL,
2950 TSU_FWSLC); /* Enable POST registers */
db893473
SH		 2951 return;
2952 }
2953
4a55530f
YS		 2954 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */
2955 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */
2956 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */
2957 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
2958 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
2959 sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
2960 sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
2961 sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
2962 sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
2963 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
4869a147
SS		 2964 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */
2965 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */
4a55530f
YS		 2966 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */
2967 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */
2968 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2969 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */
2970 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */
2971 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */
2972 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */
86a74ff2
NI		 2973}
2974
2975/* MDIO bus release function */
bd920ff5 2976static int sh_mdio_release(struct sh_eth_private *mdp)
86a74ff2 2977{
86a74ff2 2978 /* unregister mdio bus */
bd920ff5 2979 mdiobus_unregister(mdp->mii_bus);
86a74ff2
NI		 2980
2981 /* free bitbang info */
bd920ff5 2982 free_mdio_bitbang(mdp->mii_bus);
86a74ff2
NI		 2983
2984 return 0;
2985}
2986
2987/* MDIO bus init function */
bd920ff5 2988static int sh_mdio_init(struct sh_eth_private *mdp,
b3017e6a 2989 struct sh_eth_plat_data *pd)
86a74ff2 2990{
e7f4dc35 2991 int ret;
86a74ff2 2992 struct bb_info *bitbang;
bd920ff5 2993 struct platform_device *pdev = mdp->pdev;
aa8d4225 2994 struct device *dev = &mdp->pdev->dev;
86a74ff2
NI		 2995
2996 /* create bit control struct for PHY */
aa8d4225 2997 bitbang = devm_kzalloc(dev, sizeof(struct bb_info), GFP_KERNEL);
f738a13d
LP		 2998 if (!bitbang)
2999 return -ENOMEM;
86a74ff2
NI		 3000
3001 /* bitbang init */
ae70644d 3002 bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
b3017e6a 3003 bitbang->set_gate = pd->set_mdio_gate;
86a74ff2
NI		 3004 bitbang->ctrl.ops = &bb_ops;
3005
c2e07b3a 3006 /* MII controller setting */
86a74ff2 3007 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
f738a13d
LP		 3008 if (!mdp->mii_bus)
3009 return -ENOMEM;
86a74ff2
NI		 3010
3011 /* Hook up MII support for ethtool */
3012 mdp->mii_bus->name = "sh_mii";
a5bd6060 3013 mdp->mii_bus->parent = dev;
5278fb54 3014 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
bd920ff5 3015 pdev->name, pdev->id);
86a74ff2 3016
bd920ff5
LP		 3017 /* register MDIO bus */
3018 if (dev->of_node) {
3019 ret = of_mdiobus_register(mdp->mii_bus, dev->of_node);
702eca02 3020 } else {
702eca02
BD		 3021 if (pd->phy_irq > 0)
3022 mdp->mii_bus->irq[pd->phy] = pd->phy_irq;
3023
3024 ret = mdiobus_register(mdp->mii_bus);
3025 }
3026
86a74ff2 3027 if (ret)
d5e07e69 3028 goto out_free_bus;
86a74ff2 3029
86a74ff2
NI		 3030 return 0;
3031
86a74ff2 3032out_free_bus:
298cf9be 3033 free_mdio_bitbang(mdp->mii_bus);
86a74ff2
NI		 3034 return ret;
3035}
3036
4a55530f
YS		 3037static const u16 *sh_eth_get_register_offset(int register_type)
3038{
3039 const u16 *reg_offset = NULL;
3040
3041 switch (register_type) {
3042 case SH_ETH_REG_GIGABIT:
3043 reg_offset = sh_eth_offset_gigabit;
3044 break;
db893473
SH		 3045 case SH_ETH_REG_FAST_RZ:
3046 reg_offset = sh_eth_offset_fast_rz;
3047 break;
a3f109bd
SS		 3048 case SH_ETH_REG_FAST_RCAR:
3049 reg_offset = sh_eth_offset_fast_rcar;
3050 break;
4a55530f
YS		 3051 case SH_ETH_REG_FAST_SH4:
3052 reg_offset = sh_eth_offset_fast_sh4;
3053 break;
3054 case SH_ETH_REG_FAST_SH3_SH2:
3055 reg_offset = sh_eth_offset_fast_sh3_sh2;
3056 break;
4a55530f
YS		 3057 }
3058
3059 return reg_offset;
3060}
3061
8f728d79 3062static const struct net_device_ops sh_eth_netdev_ops = {
ebf84eaa
AB		 3063 .ndo_open = sh_eth_open,
3064 .ndo_stop = sh_eth_close,
3065 .ndo_start_xmit = sh_eth_start_xmit,
3066 .ndo_get_stats = sh_eth_get_stats,
b37feed7 3067 .ndo_set_rx_mode = sh_eth_set_rx_mode,
ebf84eaa
AB		 3068 .ndo_tx_timeout = sh_eth_tx_timeout,
3069 .ndo_do_ioctl = sh_eth_do_ioctl,
78d61022 3070 .ndo_change_mtu = sh_eth_change_mtu,
ebf84eaa
AB		 3071 .ndo_validate_addr = eth_validate_addr,
3072 .ndo_set_mac_address = eth_mac_addr,
ebf84eaa
AB		 3073};
3074
8f728d79
SS		 3075static const struct net_device_ops sh_eth_netdev_ops_tsu = {
3076 .ndo_open = sh_eth_open,
3077 .ndo_stop = sh_eth_close,
3078 .ndo_start_xmit = sh_eth_start_xmit,
3079 .ndo_get_stats = sh_eth_get_stats,
b37feed7 3080 .ndo_set_rx_mode = sh_eth_set_rx_mode,
8f728d79
SS		 3081 .ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid,
3082 .ndo_vlan_rx_kill_vid = sh_eth_vlan_rx_kill_vid,
3083 .ndo_tx_timeout = sh_eth_tx_timeout,
3084 .ndo_do_ioctl = sh_eth_do_ioctl,
78d61022 3085 .ndo_change_mtu = sh_eth_change_mtu,
8f728d79
SS		 3086 .ndo_validate_addr = eth_validate_addr,
3087 .ndo_set_mac_address = eth_mac_addr,
8f728d79
SS		 3088};
3089
b356e978
SS		 3090#ifdef CONFIG_OF
3091static struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
3092{
3093 struct device_node *np = dev->of_node;
3094 struct sh_eth_plat_data *pdata;
b356e978
SS		 3095 const char *mac_addr;
3096
3097 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
3098 if (!pdata)
3099 return NULL;
3100
3101 pdata->phy_interface = of_get_phy_mode(np);
3102
b356e978
SS		 3103 mac_addr = of_get_mac_address(np);
3104 if (mac_addr)
3105 memcpy(pdata->mac_addr, mac_addr, ETH_ALEN);
3106
3107 pdata->no_ether_link =
3108 of_property_read_bool(np, "renesas,no-ether-link");
3109 pdata->ether_link_active_low =
3110 of_property_read_bool(np, "renesas,ether-link-active-low");
3111
3112 return pdata;
3113}
3114
3115static const struct of_device_id sh_eth_match_table[] = {
3116 { .compatible = "renesas,gether-r8a7740", .data = &r8a7740_data },
6c4b2f7e
SH		 3117 { .compatible = "renesas,ether-r8a7743", .data = &rcar_gen2_data },
3118 { .compatible = "renesas,ether-r8a7745", .data = &rcar_gen2_data },
3119 { .compatible = "renesas,ether-r8a7778", .data = &rcar_gen1_data },
3120 { .compatible = "renesas,ether-r8a7779", .data = &rcar_gen1_data },
3121 { .compatible = "renesas,ether-r8a7790", .data = &rcar_gen2_data },
3122 { .compatible = "renesas,ether-r8a7791", .data = &rcar_gen2_data },
3123 { .compatible = "renesas,ether-r8a7793", .data = &rcar_gen2_data },
3124 { .compatible = "renesas,ether-r8a7794", .data = &rcar_gen2_data },
b356e978 3125 { .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data },
b4804e0c
SH		 3126 { .compatible = "renesas,rcar-gen1-ether", .data = &rcar_gen1_data },
3127 { .compatible = "renesas,rcar-gen2-ether", .data = &rcar_gen2_data },
b356e978
SS		 3128 { }
3129};
3130MODULE_DEVICE_TABLE(of, sh_eth_match_table);
3131#else
3132static inline struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
3133{
3134 return NULL;
3135}
3136#endif
3137
86a74ff2
NI		 3138static int sh_eth_drv_probe(struct platform_device *pdev)
3139{
86a74ff2 3140 struct resource *res;
0b76b862 3141 struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev);
afe391ad 3142 const struct platform_device_id *id = platform_get_device_id(pdev);
4fa8c3cc
SS		 3143 struct sh_eth_private *mdp;
3144 struct net_device *ndev;
9662ec19 3145 int ret;
86a74ff2
NI		 3146
3147 /* get base addr */
3148 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
86a74ff2
NI		 3149
3150 ndev = alloc_etherdev(sizeof(struct sh_eth_private));
f738a13d
LP		 3151 if (!ndev)
3152 return -ENOMEM;
86a74ff2 3153
b5893a08
BD		 3154 pm_runtime_enable(&pdev->dev);
3155 pm_runtime_get_sync(&pdev->dev);
3156
cc3c080d 3157 ret = platform_get_irq(pdev, 0);
7a468ac6 3158 if (ret < 0)
86a74ff2 3159 goto out_release;
cc3c080d 3160 ndev->irq = ret;
86a74ff2
NI		 3161
3162 SET_NETDEV_DEV(ndev, &pdev->dev);
3163
86a74ff2 3164 mdp = netdev_priv(ndev);
525b8075
YS		 3165 mdp->num_tx_ring = TX_RING_SIZE;
3166 mdp->num_rx_ring = RX_RING_SIZE;
d5e07e69
SS		 3167 mdp->addr = devm_ioremap_resource(&pdev->dev, res);
3168 if (IS_ERR(mdp->addr)) {
3169 ret = PTR_ERR(mdp->addr);
ae70644d
YS		 3170 goto out_release;
3171 }
3172
c960804f
VB		 3173 ndev->base_addr = res->start;
3174
86a74ff2 3175 spin_lock_init(&mdp->lock);
bcd5149d 3176 mdp->pdev = pdev;
86a74ff2 3177
b356e978
SS		 3178 if (pdev->dev.of_node)
3179 pd = sh_eth_parse_dt(&pdev->dev);
3b4c5cbf
SS		 3180 if (!pd) {
3181 dev_err(&pdev->dev, "no platform data\n");
3182 ret = -EINVAL;
3183 goto out_release;
3184 }
3185
86a74ff2 3186 /* get PHY ID */
71557a37 3187 mdp->phy_id = pd->phy;
e47c9052 3188 mdp->phy_interface = pd->phy_interface;
4923576b
YS		 3189 mdp->no_ether_link = pd->no_ether_link;
3190 mdp->ether_link_active_low = pd->ether_link_active_low;
86a74ff2 3191
380af9e3 3192 /* set cpu data */
42a67c9b 3193 if (id)
b356e978 3194 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data;
42a67c9b
WS		 3195 else
3196 mdp->cd = (struct sh_eth_cpu_data *)of_device_get_match_data(&pdev->dev);
b356e978 3197
a3153d8c 3198 mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type);
264be2f5
SS		 3199 if (!mdp->reg_offset) {
3200 dev_err(&pdev->dev, "Unknown register type (%d)\n",
3201 mdp->cd->register_type);
3202 ret = -EINVAL;
3203 goto out_release;
3204 }
380af9e3
YS		 3205 sh_eth_set_default_cpu_data(mdp->cd);
3206
78d61022
NS		 3207 /* User's manual states max MTU should be 2048 but due to the
3208 * alignment calculations in sh_eth_ring_init() the practical
3209 * MTU is a bit less. Maybe this can be optimized some more.
3210 */
3211 ndev->max_mtu = 2000 - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN);
3212 ndev->min_mtu = ETH_MIN_MTU;
3213
86a74ff2 3214 /* set function */
8f728d79
SS		 3215 if (mdp->cd->tsu)
3216 ndev->netdev_ops = &sh_eth_netdev_ops_tsu;
3217 else
3218 ndev->netdev_ops = &sh_eth_netdev_ops;
7ad24ea4 3219 ndev->ethtool_ops = &sh_eth_ethtool_ops;
86a74ff2
NI		 3220 ndev->watchdog_timeo = TX_TIMEOUT;
3221
dc19e4e5
NI		 3222 /* debug message level */
3223 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
86a74ff2
NI		 3224
3225 /* read and set MAC address */
748031f9 3226 read_mac_address(ndev, pd->mac_addr);
ff6e7228
SS		 3227 if (!is_valid_ether_addr(ndev->dev_addr)) {
3228 dev_warn(&pdev->dev,
3229 "no valid MAC address supplied, using a random one.\n");
3230 eth_hw_addr_random(ndev);
3231 }
86a74ff2 3232
6ba88021 3233 if (mdp->cd->tsu) {
9662ec19 3234 int port = pdev->id < 0 ? 0 : pdev->id % 2;
6ba88021 3235 struct resource *rtsu;
dfe8266b 3236
6ba88021 3237 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
dfe8266b
SS		 3238 if (!rtsu) {
3239 dev_err(&pdev->dev, "no TSU resource\n");
3240 ret = -ENODEV;
3241 goto out_release;
3242 }
3243 /* We can only request the TSU region for the first port
3244 * of the two sharing this TSU for the probe to succeed...
3245 */
9662ec19 3246 if (port == 0 &&
dfe8266b
SS		 3247 !devm_request_mem_region(&pdev->dev, rtsu->start,
3248 resource_size(rtsu),
3249 dev_name(&pdev->dev))) {
3250 dev_err(&pdev->dev, "can't request TSU resource.\n");
3251 ret = -EBUSY;
3252 goto out_release;
3253 }
3e14c969 3254 /* ioremap the TSU registers */
dfe8266b
SS		 3255 mdp->tsu_addr = devm_ioremap(&pdev->dev, rtsu->start,
3256 resource_size(rtsu));
3257 if (!mdp->tsu_addr) {
3258 dev_err(&pdev->dev, "TSU region ioremap() failed.\n");
3259 ret = -ENOMEM;
fc0c0900
SS		 3260 goto out_release;
3261 }
9662ec19 3262 mdp->port = port;
f646968f 3263 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER;
6ba88021 3264
3e14c969 3265 /* Need to init only the first port of the two sharing a TSU */
9662ec19 3266 if (port == 0) {
3e14c969
SS		 3267 if (mdp->cd->chip_reset)
3268 mdp->cd->chip_reset(ndev);
86a74ff2 3269
4986b996
YS		 3270 /* TSU init (Init only)*/
3271 sh_eth_tsu_init(mdp);
3272 }
86a74ff2
NI		 3273 }
3274
966d6dbb
HN		 3275 if (mdp->cd->rmiimode)
3276 sh_eth_write(ndev, 0x1, RMIIMODE);
3277
daacf03f
LP		 3278 /* MDIO bus init */
3279 ret = sh_mdio_init(mdp, pd);
3280 if (ret) {
b7ce520e
GU		 3281 if (ret != -EPROBE_DEFER)
3282 dev_err(&pdev->dev, "MDIO init failed: %d\n", ret);
daacf03f
LP		 3283 goto out_release;
3284 }
3285
3719109d
SS		 3286 netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64);
3287
86a74ff2
NI		 3288 /* network device register */
3289 ret = register_netdev(ndev);
3290 if (ret)
3719109d 3291 goto out_napi_del;
86a74ff2 3292
b4580c95 3293 if (mdp->cd->magic)
d8981d02
NS		 3294 device_set_wakeup_capable(&pdev->dev, 1);
3295
25985edc 3296 /* print device information */
f75f14ec
SS		 3297 netdev_info(ndev, "Base address at 0x%x, %pM, IRQ %d.\n",
3298 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
86a74ff2 3299
b5893a08 3300 pm_runtime_put(&pdev->dev);
86a74ff2
NI		 3301 platform_set_drvdata(pdev, ndev);
3302
3303 return ret;
3304
3719109d
SS		 3305out_napi_del:
3306 netif_napi_del(&mdp->napi);
daacf03f 3307 sh_mdio_release(mdp);
3719109d 3308
86a74ff2
NI		 3309out_release:
3310 /* net_dev free */
4282fc47 3311 free_netdev(ndev);
86a74ff2 3312
b5893a08
BD		 3313 pm_runtime_put(&pdev->dev);
3314 pm_runtime_disable(&pdev->dev);
86a74ff2
NI		 3315 return ret;
3316}
3317
3318static int sh_eth_drv_remove(struct platform_device *pdev)
3319{
3320 struct net_device *ndev = platform_get_drvdata(pdev);
3719109d 3321 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2 3322
86a74ff2 3323 unregister_netdev(ndev);
3719109d 3324 netif_napi_del(&mdp->napi);
daacf03f 3325 sh_mdio_release(mdp);
bcd5149d 3326 pm_runtime_disable(&pdev->dev);
86a74ff2 3327 free_netdev(ndev);
86a74ff2
NI		 3328
3329 return 0;
3330}
3331
540ad1b8 3332#ifdef CONFIG_PM
b71af046 3333#ifdef CONFIG_PM_SLEEP
d8981d02
NS		 3334static int sh_eth_wol_setup(struct net_device *ndev)
3335{
3336 struct sh_eth_private *mdp = netdev_priv(ndev);
3337
3338 /* Only allow ECI interrupts */
3339 synchronize_irq(ndev->irq);
3340 napi_disable(&mdp->napi);
1a0bee6c 3341 sh_eth_write(ndev, EESIPR_ECIIP, EESIPR);
d8981d02
NS		 3342
3343 /* Enable MagicPacket */
5e2ed132 3344 sh_eth_modify(ndev, ECMR, ECMR_MPDE, ECMR_MPDE);
d8981d02 3345
d8981d02
NS		 3346 return enable_irq_wake(ndev->irq);
3347}
3348
3349static int sh_eth_wol_restore(struct net_device *ndev)
3350{
3351 struct sh_eth_private *mdp = netdev_priv(ndev);
3352 int ret;
3353
3354 napi_enable(&mdp->napi);
3355
3356 /* Disable MagicPacket */
3357 sh_eth_modify(ndev, ECMR, ECMR_MPDE, 0);
3358
3359 /* The device needs to be reset to restore MagicPacket logic
3360 * for next wakeup. If we close and open the device it will
3361 * both be reset and all registers restored. This is what
3362 * happens during suspend and resume without WoL enabled.
3363 */
3364 ret = sh_eth_close(ndev);
3365 if (ret < 0)
3366 return ret;
3367 ret = sh_eth_open(ndev);
3368 if (ret < 0)
3369 return ret;
3370
d8981d02
NS		 3371 return disable_irq_wake(ndev->irq);
3372}
3373
b71af046
MU		 3374static int sh_eth_suspend(struct device *dev)
3375{
3376 struct net_device *ndev = dev_get_drvdata(dev);
d8981d02 3377 struct sh_eth_private *mdp = netdev_priv(ndev);
b71af046
MU		 3378 int ret = 0;
3379
d8981d02
NS		 3380 if (!netif_running(ndev))
3381 return 0;
3382
3383 netif_device_detach(ndev);
3384
3385 if (mdp->wol_enabled)
3386 ret = sh_eth_wol_setup(ndev);
3387 else
b71af046 3388 ret = sh_eth_close(ndev);
b71af046
MU		 3389
3390 return ret;
3391}
3392
3393static int sh_eth_resume(struct device *dev)
3394{
3395 struct net_device *ndev = dev_get_drvdata(dev);
d8981d02 3396 struct sh_eth_private *mdp = netdev_priv(ndev);
b71af046
MU		 3397 int ret = 0;
3398
d8981d02
NS		 3399 if (!netif_running(ndev))
3400 return 0;
3401
3402 if (mdp->wol_enabled)
3403 ret = sh_eth_wol_restore(ndev);
3404 else
b71af046 3405 ret = sh_eth_open(ndev);
d8981d02
NS		 3406
3407 if (ret < 0)
3408 return ret;
3409
3410 netif_device_attach(ndev);
b71af046
MU		 3411
3412 return ret;
3413}
3414#endif
3415
bcd5149d
MD		 3416static int sh_eth_runtime_nop(struct device *dev)
3417{
128296fc 3418 /* Runtime PM callback shared between ->runtime_suspend()
bcd5149d
MD		 3419 * and ->runtime_resume(). Simply returns success.
3420 *
3421 * This driver re-initializes all registers after
3422 * pm_runtime_get_sync() anyway so there is no need
3423 * to save and restore registers here.
3424 */
3425 return 0;
3426}
3427
540ad1b8 3428static const struct dev_pm_ops sh_eth_dev_pm_ops = {
b71af046 3429 SET_SYSTEM_SLEEP_PM_OPS(sh_eth_suspend, sh_eth_resume)
e7d7e898 3430 SET_RUNTIME_PM_OPS(sh_eth_runtime_nop, sh_eth_runtime_nop, NULL)
bcd5149d 3431};
540ad1b8
NI		 3432#define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
3433#else
3434#define SH_ETH_PM_OPS NULL
3435#endif
bcd5149d 3436
ef00df85 3437static const struct platform_device_id sh_eth_id_table[] = {
c18a79ab 3438 { "sh7619-ether", (kernel_ulong_t)&sh7619_data },
7bbe150d 3439 { "sh771x-ether", (kernel_ulong_t)&sh771x_data },
9c3beaab 3440 { "sh7724-ether", (kernel_ulong_t)&sh7724_data },
f5d12767 3441 { "sh7734-gether", (kernel_ulong_t)&sh7734_data },
24549e2a
SS		 3442 { "sh7757-ether", (kernel_ulong_t)&sh7757_data },
3443 { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga },
f5d12767 3444 { "sh7763-gether", (kernel_ulong_t)&sh7763_data },
afe391ad
SS		 3445 { }
3446};
3447MODULE_DEVICE_TABLE(platform, sh_eth_id_table);
3448
86a74ff2
NI		 3449static struct platform_driver sh_eth_driver = {
3450 .probe = sh_eth_drv_probe,
3451 .remove = sh_eth_drv_remove,
afe391ad 3452 .id_table = sh_eth_id_table,
86a74ff2
NI		 3453 .driver = {
3454 .name = CARDNAME,
540ad1b8 3455 .pm = SH_ETH_PM_OPS,
b356e978 3456 .of_match_table = of_match_ptr(sh_eth_match_table),
86a74ff2
NI		 3457 },
3458};
3459
db62f684 3460module_platform_driver(sh_eth_driver);
86a74ff2
NI		 3461
3462MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
3463MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
3464MODULE_LICENSE("GPL v2");
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