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sh_eth: kill 'ret' variable in sh_eth_ring_init()
[mirror_ubuntu-jammy-kernel.git] / drivers / net / ethernet / renesas / sh_eth.c
CommitLineData
128296fc 1/* SuperH Ethernet device driver
86a74ff2 2 *
966d6dbb 3 * Copyright (C) 2014 Renesas Electronics Corporation
f0e81fec 4 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu
b356e978
SS		 5 * Copyright (C) 2008-2014 Renesas Solutions Corp.
6 * Copyright (C) 2013-2014 Cogent Embedded, Inc.
702eca02 7 * Copyright (C) 2014 Codethink Limited
86a74ff2
NI		 8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms and conditions of the GNU General Public License,
11 * version 2, as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
86a74ff2
NI		 17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 */
21
0654011d
YS		 22#include <linux/module.h>
23#include <linux/kernel.h>
24#include <linux/spinlock.h>
6a27cded 25#include <linux/interrupt.h>
86a74ff2
NI		 26#include <linux/dma-mapping.h>
27#include <linux/etherdevice.h>
28#include <linux/delay.h>
29#include <linux/platform_device.h>
30#include <linux/mdio-bitbang.h>
31#include <linux/netdevice.h>
b356e978
SS		 32#include <linux/of.h>
33#include <linux/of_device.h>
34#include <linux/of_irq.h>
35#include <linux/of_net.h>
86a74ff2
NI		 36#include <linux/phy.h>
37#include <linux/cache.h>
38#include <linux/io.h>
bcd5149d 39#include <linux/pm_runtime.h>
5a0e3ad6 40#include <linux/slab.h>
dc19e4e5 41#include <linux/ethtool.h>
fdb37a7f 42#include <linux/if_vlan.h>
f0e81fec 43#include <linux/clk.h>
d4fa0e35 44#include <linux/sh_eth.h>
702eca02 45#include <linux/of_mdio.h>
86a74ff2
NI		 46
47#include "sh_eth.h"
48
dc19e4e5
NI		 49#define SH_ETH_DEF_MSG_ENABLE \
50 (NETIF_MSG_LINK | \
51 NETIF_MSG_TIMER | \
52 NETIF_MSG_RX_ERR| \
53 NETIF_MSG_TX_ERR)
54
3365711d
BH		 55#define SH_ETH_OFFSET_DEFAULTS \
56 [0 ... SH_ETH_MAX_REGISTER_OFFSET - 1] = SH_ETH_OFFSET_INVALID
57
c0013f6f 58static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
3365711d
BH		 59 SH_ETH_OFFSET_DEFAULTS,
60
c0013f6f
SS		 61 [EDSR] = 0x0000,
62 [EDMR] = 0x0400,
63 [EDTRR] = 0x0408,
64 [EDRRR] = 0x0410,
65 [EESR] = 0x0428,
66 [EESIPR] = 0x0430,
67 [TDLAR] = 0x0010,
68 [TDFAR] = 0x0014,
69 [TDFXR] = 0x0018,
70 [TDFFR] = 0x001c,
71 [RDLAR] = 0x0030,
72 [RDFAR] = 0x0034,
73 [RDFXR] = 0x0038,
74 [RDFFR] = 0x003c,
75 [TRSCER] = 0x0438,
76 [RMFCR] = 0x0440,
77 [TFTR] = 0x0448,
78 [FDR] = 0x0450,
79 [RMCR] = 0x0458,
80 [RPADIR] = 0x0460,
81 [FCFTR] = 0x0468,
82 [CSMR] = 0x04E4,
83
84 [ECMR] = 0x0500,
85 [ECSR] = 0x0510,
86 [ECSIPR] = 0x0518,
87 [PIR] = 0x0520,
88 [PSR] = 0x0528,
89 [PIPR] = 0x052c,
90 [RFLR] = 0x0508,
91 [APR] = 0x0554,
92 [MPR] = 0x0558,
93 [PFTCR] = 0x055c,
94 [PFRCR] = 0x0560,
95 [TPAUSER] = 0x0564,
96 [GECMR] = 0x05b0,
97 [BCULR] = 0x05b4,
98 [MAHR] = 0x05c0,
99 [MALR] = 0x05c8,
100 [TROCR] = 0x0700,
101 [CDCR] = 0x0708,
102 [LCCR] = 0x0710,
103 [CEFCR] = 0x0740,
104 [FRECR] = 0x0748,
105 [TSFRCR] = 0x0750,
106 [TLFRCR] = 0x0758,
107 [RFCR] = 0x0760,
108 [CERCR] = 0x0768,
109 [CEECR] = 0x0770,
110 [MAFCR] = 0x0778,
111 [RMII_MII] = 0x0790,
112
113 [ARSTR] = 0x0000,
114 [TSU_CTRST] = 0x0004,
115 [TSU_FWEN0] = 0x0010,
116 [TSU_FWEN1] = 0x0014,
117 [TSU_FCM] = 0x0018,
118 [TSU_BSYSL0] = 0x0020,
119 [TSU_BSYSL1] = 0x0024,
120 [TSU_PRISL0] = 0x0028,
121 [TSU_PRISL1] = 0x002c,
122 [TSU_FWSL0] = 0x0030,
123 [TSU_FWSL1] = 0x0034,
124 [TSU_FWSLC] = 0x0038,
125 [TSU_QTAG0] = 0x0040,
126 [TSU_QTAG1] = 0x0044,
127 [TSU_FWSR] = 0x0050,
128 [TSU_FWINMK] = 0x0054,
129 [TSU_ADQT0] = 0x0048,
130 [TSU_ADQT1] = 0x004c,
131 [TSU_VTAG0] = 0x0058,
132 [TSU_VTAG1] = 0x005c,
133 [TSU_ADSBSY] = 0x0060,
134 [TSU_TEN] = 0x0064,
135 [TSU_POST1] = 0x0070,
136 [TSU_POST2] = 0x0074,
137 [TSU_POST3] = 0x0078,
138 [TSU_POST4] = 0x007c,
139 [TSU_ADRH0] = 0x0100,
c0013f6f
SS		 140
141 [TXNLCR0] = 0x0080,
142 [TXALCR0] = 0x0084,
143 [RXNLCR0] = 0x0088,
144 [RXALCR0] = 0x008c,
145 [FWNLCR0] = 0x0090,
146 [FWALCR0] = 0x0094,
147 [TXNLCR1] = 0x00a0,
148 [TXALCR1] = 0x00a0,
149 [RXNLCR1] = 0x00a8,
150 [RXALCR1] = 0x00ac,
151 [FWNLCR1] = 0x00b0,
152 [FWALCR1] = 0x00b4,
153};
154
db893473 155static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
3365711d
BH		 156 SH_ETH_OFFSET_DEFAULTS,
157
db893473
SH		 158 [EDSR] = 0x0000,
159 [EDMR] = 0x0400,
160 [EDTRR] = 0x0408,
161 [EDRRR] = 0x0410,
162 [EESR] = 0x0428,
163 [EESIPR] = 0x0430,
164 [TDLAR] = 0x0010,
165 [TDFAR] = 0x0014,
166 [TDFXR] = 0x0018,
167 [TDFFR] = 0x001c,
168 [RDLAR] = 0x0030,
169 [RDFAR] = 0x0034,
170 [RDFXR] = 0x0038,
171 [RDFFR] = 0x003c,
172 [TRSCER] = 0x0438,
173 [RMFCR] = 0x0440,
174 [TFTR] = 0x0448,
175 [FDR] = 0x0450,
176 [RMCR] = 0x0458,
177 [RPADIR] = 0x0460,
178 [FCFTR] = 0x0468,
179 [CSMR] = 0x04E4,
180
181 [ECMR] = 0x0500,
182 [RFLR] = 0x0508,
183 [ECSR] = 0x0510,
184 [ECSIPR] = 0x0518,
185 [PIR] = 0x0520,
186 [APR] = 0x0554,
187 [MPR] = 0x0558,
188 [PFTCR] = 0x055c,
189 [PFRCR] = 0x0560,
190 [TPAUSER] = 0x0564,
191 [MAHR] = 0x05c0,
192 [MALR] = 0x05c8,
193 [CEFCR] = 0x0740,
194 [FRECR] = 0x0748,
195 [TSFRCR] = 0x0750,
196 [TLFRCR] = 0x0758,
197 [RFCR] = 0x0760,
198 [MAFCR] = 0x0778,
199
200 [ARSTR] = 0x0000,
201 [TSU_CTRST] = 0x0004,
202 [TSU_VTAG0] = 0x0058,
203 [TSU_ADSBSY] = 0x0060,
204 [TSU_TEN] = 0x0064,
205 [TSU_ADRH0] = 0x0100,
db893473
SH		 206
207 [TXNLCR0] = 0x0080,
208 [TXALCR0] = 0x0084,
209 [RXNLCR0] = 0x0088,
210 [RXALCR0] = 0x008C,
211};
212
a3f109bd 213static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
3365711d
BH		 214 SH_ETH_OFFSET_DEFAULTS,
215
a3f109bd
SS		 216 [ECMR] = 0x0300,
217 [RFLR] = 0x0308,
218 [ECSR] = 0x0310,
219 [ECSIPR] = 0x0318,
220 [PIR] = 0x0320,
221 [PSR] = 0x0328,
222 [RDMLR] = 0x0340,
223 [IPGR] = 0x0350,
224 [APR] = 0x0354,
225 [MPR] = 0x0358,
226 [RFCF] = 0x0360,
227 [TPAUSER] = 0x0364,
228 [TPAUSECR] = 0x0368,
229 [MAHR] = 0x03c0,
230 [MALR] = 0x03c8,
231 [TROCR] = 0x03d0,
232 [CDCR] = 0x03d4,
233 [LCCR] = 0x03d8,
234 [CNDCR] = 0x03dc,
235 [CEFCR] = 0x03e4,
236 [FRECR] = 0x03e8,
237 [TSFRCR] = 0x03ec,
238 [TLFRCR] = 0x03f0,
239 [RFCR] = 0x03f4,
240 [MAFCR] = 0x03f8,
241
242 [EDMR] = 0x0200,
243 [EDTRR] = 0x0208,
244 [EDRRR] = 0x0210,
245 [TDLAR] = 0x0218,
246 [RDLAR] = 0x0220,
247 [EESR] = 0x0228,
248 [EESIPR] = 0x0230,
249 [TRSCER] = 0x0238,
250 [RMFCR] = 0x0240,
251 [TFTR] = 0x0248,
252 [FDR] = 0x0250,
253 [RMCR] = 0x0258,
254 [TFUCR] = 0x0264,
255 [RFOCR] = 0x0268,
55754f19 256 [RMIIMODE] = 0x026c,
a3f109bd
SS		 257 [FCFTR] = 0x0270,
258 [TRIMD] = 0x027c,
259};
260
c0013f6f 261static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
3365711d
BH		 262 SH_ETH_OFFSET_DEFAULTS,
263
c0013f6f
SS		 264 [ECMR] = 0x0100,
265 [RFLR] = 0x0108,
266 [ECSR] = 0x0110,
267 [ECSIPR] = 0x0118,
268 [PIR] = 0x0120,
269 [PSR] = 0x0128,
270 [RDMLR] = 0x0140,
271 [IPGR] = 0x0150,
272 [APR] = 0x0154,
273 [MPR] = 0x0158,
274 [TPAUSER] = 0x0164,
275 [RFCF] = 0x0160,
276 [TPAUSECR] = 0x0168,
277 [BCFRR] = 0x016c,
278 [MAHR] = 0x01c0,
279 [MALR] = 0x01c8,
280 [TROCR] = 0x01d0,
281 [CDCR] = 0x01d4,
282 [LCCR] = 0x01d8,
283 [CNDCR] = 0x01dc,
284 [CEFCR] = 0x01e4,
285 [FRECR] = 0x01e8,
286 [TSFRCR] = 0x01ec,
287 [TLFRCR] = 0x01f0,
288 [RFCR] = 0x01f4,
289 [MAFCR] = 0x01f8,
290 [RTRATE] = 0x01fc,
291
292 [EDMR] = 0x0000,
293 [EDTRR] = 0x0008,
294 [EDRRR] = 0x0010,
295 [TDLAR] = 0x0018,
296 [RDLAR] = 0x0020,
297 [EESR] = 0x0028,
298 [EESIPR] = 0x0030,
299 [TRSCER] = 0x0038,
300 [RMFCR] = 0x0040,
301 [TFTR] = 0x0048,
302 [FDR] = 0x0050,
303 [RMCR] = 0x0058,
304 [TFUCR] = 0x0064,
305 [RFOCR] = 0x0068,
306 [FCFTR] = 0x0070,
307 [RPADIR] = 0x0078,
308 [TRIMD] = 0x007c,
309 [RBWAR] = 0x00c8,
310 [RDFAR] = 0x00cc,
311 [TBRAR] = 0x00d4,
312 [TDFAR] = 0x00d8,
313};
314
315static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
3365711d
BH		 316 SH_ETH_OFFSET_DEFAULTS,
317
d8b0426a
SS		 318 [EDMR] = 0x0000,
319 [EDTRR] = 0x0004,
320 [EDRRR] = 0x0008,
321 [TDLAR] = 0x000c,
322 [RDLAR] = 0x0010,
323 [EESR] = 0x0014,
324 [EESIPR] = 0x0018,
325 [TRSCER] = 0x001c,
326 [RMFCR] = 0x0020,
327 [TFTR] = 0x0024,
328 [FDR] = 0x0028,
329 [RMCR] = 0x002c,
330 [EDOCR] = 0x0030,
331 [FCFTR] = 0x0034,
332 [RPADIR] = 0x0038,
333 [TRIMD] = 0x003c,
334 [RBWAR] = 0x0040,
335 [RDFAR] = 0x0044,
336 [TBRAR] = 0x004c,
337 [TDFAR] = 0x0050,
338
c0013f6f
SS		 339 [ECMR] = 0x0160,
340 [ECSR] = 0x0164,
341 [ECSIPR] = 0x0168,
342 [PIR] = 0x016c,
343 [MAHR] = 0x0170,
344 [MALR] = 0x0174,
345 [RFLR] = 0x0178,
346 [PSR] = 0x017c,
347 [TROCR] = 0x0180,
348 [CDCR] = 0x0184,
349 [LCCR] = 0x0188,
350 [CNDCR] = 0x018c,
351 [CEFCR] = 0x0194,
352 [FRECR] = 0x0198,
353 [TSFRCR] = 0x019c,
354 [TLFRCR] = 0x01a0,
355 [RFCR] = 0x01a4,
356 [MAFCR] = 0x01a8,
357 [IPGR] = 0x01b4,
358 [APR] = 0x01b8,
359 [MPR] = 0x01bc,
360 [TPAUSER] = 0x01c4,
361 [BCFR] = 0x01cc,
362
363 [ARSTR] = 0x0000,
364 [TSU_CTRST] = 0x0004,
365 [TSU_FWEN0] = 0x0010,
366 [TSU_FWEN1] = 0x0014,
367 [TSU_FCM] = 0x0018,
368 [TSU_BSYSL0] = 0x0020,
369 [TSU_BSYSL1] = 0x0024,
370 [TSU_PRISL0] = 0x0028,
371 [TSU_PRISL1] = 0x002c,
372 [TSU_FWSL0] = 0x0030,
373 [TSU_FWSL1] = 0x0034,
374 [TSU_FWSLC] = 0x0038,
375 [TSU_QTAGM0] = 0x0040,
376 [TSU_QTAGM1] = 0x0044,
377 [TSU_ADQT0] = 0x0048,
378 [TSU_ADQT1] = 0x004c,
379 [TSU_FWSR] = 0x0050,
380 [TSU_FWINMK] = 0x0054,
381 [TSU_ADSBSY] = 0x0060,
382 [TSU_TEN] = 0x0064,
383 [TSU_POST1] = 0x0070,
384 [TSU_POST2] = 0x0074,
385 [TSU_POST3] = 0x0078,
386 [TSU_POST4] = 0x007c,
387
388 [TXNLCR0] = 0x0080,
389 [TXALCR0] = 0x0084,
390 [RXNLCR0] = 0x0088,
391 [RXALCR0] = 0x008c,
392 [FWNLCR0] = 0x0090,
393 [FWALCR0] = 0x0094,
394 [TXNLCR1] = 0x00a0,
395 [TXALCR1] = 0x00a0,
396 [RXNLCR1] = 0x00a8,
397 [RXALCR1] = 0x00ac,
398 [FWNLCR1] = 0x00b0,
399 [FWALCR1] = 0x00b4,
400
401 [TSU_ADRH0] = 0x0100,
c0013f6f
SS		 402};
403
740c7f31
BH		 404static void sh_eth_rcv_snd_disable(struct net_device *ndev);
405static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev);
406
504c8ca5 407static bool sh_eth_is_gether(struct sh_eth_private *mdp)
dabdde9e 408{
504c8ca5 409 return mdp->reg_offset == sh_eth_offset_gigabit;
dabdde9e
NI		 410}
411
db893473
SH		 412static bool sh_eth_is_rz_fast_ether(struct sh_eth_private *mdp)
413{
414 return mdp->reg_offset == sh_eth_offset_fast_rz;
415}
416
8e994402 417static void sh_eth_select_mii(struct net_device *ndev)
5e7a76be
NI		 418{
419 u32 value = 0x0;
420 struct sh_eth_private *mdp = netdev_priv(ndev);
421
422 switch (mdp->phy_interface) {
423 case PHY_INTERFACE_MODE_GMII:
424 value = 0x2;
425 break;
426 case PHY_INTERFACE_MODE_MII:
427 value = 0x1;
428 break;
429 case PHY_INTERFACE_MODE_RMII:
430 value = 0x0;
431 break;
432 default:
f75f14ec
SS		 433 netdev_warn(ndev,
434 "PHY interface mode was not setup. Set to MII.\n");
5e7a76be
NI		 435 value = 0x1;
436 break;
437 }
438
439 sh_eth_write(ndev, value, RMII_MII);
440}
5e7a76be 441
8e994402 442static void sh_eth_set_duplex(struct net_device *ndev)
65ac8851
YS		 443{
444 struct sh_eth_private *mdp = netdev_priv(ndev);
65ac8851
YS		 445
446 if (mdp->duplex) /* Full */
4a55530f 447 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
65ac8851 448 else /* Half */
4a55530f 449 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
65ac8851
YS		 450}
451
04b0ed2a 452/* There is CPU dependent code */
589ebdef 453static void sh_eth_set_rate_r8a777x(struct net_device *ndev)
65ac8851
YS		 454{
455 struct sh_eth_private *mdp = netdev_priv(ndev);
d0418bb7 456
a3f109bd
SS		 457 switch (mdp->speed) {
458 case 10: /* 10BASE */
459 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_ELB, ECMR);
460 break;
461 case 100:/* 100BASE */
462 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_ELB, ECMR);
463 break;
464 default:
465 break;
466 }
467}
468
674853b2 469/* R8A7778/9 */
589ebdef 470static struct sh_eth_cpu_data r8a777x_data = {
a3f109bd 471 .set_duplex = sh_eth_set_duplex,
589ebdef 472 .set_rate = sh_eth_set_rate_r8a777x,
a3f109bd 473
a3153d8c
SS		 474 .register_type = SH_ETH_REG_FAST_RCAR,
475
a3f109bd
SS		 476 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
477 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
478 .eesipr_value = 0x01ff009f,
479
480 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
ca8c3585
SS		 481 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
482 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
483 EESR_ECI,
d407bc02 484 .fdr_value = 0x00000f0f,
a3f109bd
SS		 485
486 .apr = 1,
487 .mpr = 1,
488 .tpauser = 1,
489 .hw_swap = 1,
490};
a3f109bd 491
94a12b15
SS		 492/* R8A7790/1 */
493static struct sh_eth_cpu_data r8a779x_data = {
e18dbf7e
SH		 494 .set_duplex = sh_eth_set_duplex,
495 .set_rate = sh_eth_set_rate_r8a777x,
496
a3153d8c
SS		 497 .register_type = SH_ETH_REG_FAST_RCAR,
498
e18dbf7e
SH		 499 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
500 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
501 .eesipr_value = 0x01ff009f,
502
503 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
ba361cb3
LP		 504 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
505 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
506 EESR_ECI,
d407bc02 507 .fdr_value = 0x00000f0f,
e18dbf7e 508
01fbd3f5
GU		 509 .trscer_err_mask = DESC_I_RINT8,
510
e18dbf7e
SH		 511 .apr = 1,
512 .mpr = 1,
513 .tpauser = 1,
514 .hw_swap = 1,
515 .rmiimode = 1,
516};
517
9c3beaab 518static void sh_eth_set_rate_sh7724(struct net_device *ndev)
a3f109bd
SS		 519{
520 struct sh_eth_private *mdp = netdev_priv(ndev);
65ac8851
YS		 521
522 switch (mdp->speed) {
523 case 10: /* 10BASE */
a3f109bd 524 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_RTM, ECMR);
65ac8851
YS		 525 break;
526 case 100:/* 100BASE */
a3f109bd 527 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_RTM, ECMR);
65ac8851
YS		 528 break;
529 default:
530 break;
531 }
532}
533
534/* SH7724 */
9c3beaab 535static struct sh_eth_cpu_data sh7724_data = {
65ac8851 536 .set_duplex = sh_eth_set_duplex,
9c3beaab 537 .set_rate = sh_eth_set_rate_sh7724,
65ac8851 538
a3153d8c
SS		 539 .register_type = SH_ETH_REG_FAST_SH4,
540
65ac8851
YS		 541 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
542 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
a80c3de7 543 .eesipr_value = 0x01ff009f,
65ac8851
YS		 544
545 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
ca8c3585
SS		 546 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
547 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
548 EESR_ECI,
65ac8851
YS		 549
550 .apr = 1,
551 .mpr = 1,
552 .tpauser = 1,
553 .hw_swap = 1,
503914cf
MD		 554 .rpadir = 1,
555 .rpadir_value = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
65ac8851 556};
5cee1d37 557
24549e2a 558static void sh_eth_set_rate_sh7757(struct net_device *ndev)
f29a3d04
YS		 559{
560 struct sh_eth_private *mdp = netdev_priv(ndev);
f29a3d04
YS		 561
562 switch (mdp->speed) {
563 case 10: /* 10BASE */
4a55530f 564 sh_eth_write(ndev, 0, RTRATE);
f29a3d04
YS		 565 break;
566 case 100:/* 100BASE */
4a55530f 567 sh_eth_write(ndev, 1, RTRATE);
f29a3d04
YS		 568 break;
569 default:
570 break;
571 }
572}
573
574/* SH7757 */
24549e2a
SS		 575static struct sh_eth_cpu_data sh7757_data = {
576 .set_duplex = sh_eth_set_duplex,
577 .set_rate = sh_eth_set_rate_sh7757,
f29a3d04 578
a3153d8c
SS		 579 .register_type = SH_ETH_REG_FAST_SH4,
580
f29a3d04 581 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
f29a3d04
YS		 582
583 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
ca8c3585
SS		 584 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
585 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
586 EESR_ECI,
f29a3d04 587
5b3dfd13 588 .irq_flags = IRQF_SHARED,
f29a3d04
YS		 589 .apr = 1,
590 .mpr = 1,
591 .tpauser = 1,
592 .hw_swap = 1,
593 .no_ade = 1,
2e98e797
YS		 594 .rpadir = 1,
595 .rpadir_value = 2 << 16,
6b4b4fea 596 .rtrate = 1,
f29a3d04 597};
65ac8851 598
e403d295 599#define SH_GIGA_ETH_BASE 0xfee00000UL
8fcd4961
YS		 600#define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
601#define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
602static void sh_eth_chip_reset_giga(struct net_device *ndev)
603{
604 int i;
0799c2d6 605 u32 mahr[2], malr[2];
8fcd4961
YS		 606
607 /* save MAHR and MALR */
608 for (i = 0; i < 2; i++) {
ae70644d
YS		 609 malr[i] = ioread32((void *)GIGA_MALR(i));
610 mahr[i] = ioread32((void *)GIGA_MAHR(i));
8fcd4961
YS		 611 }
612
613 /* reset device */
ae70644d 614 iowrite32(ARSTR_ARSTR, (void *)(SH_GIGA_ETH_BASE + 0x1800));
8fcd4961
YS		 615 mdelay(1);
616
617 /* restore MAHR and MALR */
618 for (i = 0; i < 2; i++) {
ae70644d
YS		 619 iowrite32(malr[i], (void *)GIGA_MALR(i));
620 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
8fcd4961
YS		 621 }
622}
623
8fcd4961
YS		 624static void sh_eth_set_rate_giga(struct net_device *ndev)
625{
626 struct sh_eth_private *mdp = netdev_priv(ndev);
627
628 switch (mdp->speed) {
629 case 10: /* 10BASE */
630 sh_eth_write(ndev, 0x00000000, GECMR);
631 break;
632 case 100:/* 100BASE */
633 sh_eth_write(ndev, 0x00000010, GECMR);
634 break;
635 case 1000: /* 1000BASE */
636 sh_eth_write(ndev, 0x00000020, GECMR);
637 break;
638 default:
639 break;
640 }
641}
642
643/* SH7757(GETHERC) */
24549e2a 644static struct sh_eth_cpu_data sh7757_data_giga = {
8fcd4961 645 .chip_reset = sh_eth_chip_reset_giga,
04b0ed2a 646 .set_duplex = sh_eth_set_duplex,
8fcd4961
YS		 647 .set_rate = sh_eth_set_rate_giga,
648
a3153d8c
SS		 649 .register_type = SH_ETH_REG_GIGABIT,
650
8fcd4961
YS		 651 .ecsr_value = ECSR_ICD | ECSR_MPD,
652 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
653 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
654
655 .tx_check = EESR_TC1 | EESR_FTC,
ca8c3585
SS		 656 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
657 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
658 EESR_TDE | EESR_ECI,
8fcd4961 659 .fdr_value = 0x0000072f,
8fcd4961 660
5b3dfd13 661 .irq_flags = IRQF_SHARED,
8fcd4961
YS		 662 .apr = 1,
663 .mpr = 1,
664 .tpauser = 1,
665 .bculr = 1,
666 .hw_swap = 1,
667 .rpadir = 1,
668 .rpadir_value = 2 << 16,
669 .no_trimd = 1,
670 .no_ade = 1,
3acbc971 671 .tsu = 1,
8fcd4961
YS		 672};
673
380af9e3
YS		 674static void sh_eth_chip_reset(struct net_device *ndev)
675{
4986b996
YS		 676 struct sh_eth_private *mdp = netdev_priv(ndev);
677
380af9e3 678 /* reset device */
4986b996 679 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
380af9e3
YS		 680 mdelay(1);
681}
682
f5d12767 683static void sh_eth_set_rate_gether(struct net_device *ndev)
380af9e3
YS		 684{
685 struct sh_eth_private *mdp = netdev_priv(ndev);
380af9e3
YS		 686
687 switch (mdp->speed) {
688 case 10: /* 10BASE */
4a55530f 689 sh_eth_write(ndev, GECMR_10, GECMR);
380af9e3
YS		 690 break;
691 case 100:/* 100BASE */
4a55530f 692 sh_eth_write(ndev, GECMR_100, GECMR);
380af9e3
YS		 693 break;
694 case 1000: /* 1000BASE */
4a55530f 695 sh_eth_write(ndev, GECMR_1000, GECMR);
380af9e3
YS		 696 break;
697 default:
698 break;
699 }
700}
701
f5d12767
SS		 702/* SH7734 */
703static struct sh_eth_cpu_data sh7734_data = {
380af9e3
YS		 704 .chip_reset = sh_eth_chip_reset,
705 .set_duplex = sh_eth_set_duplex,
f5d12767
SS		 706 .set_rate = sh_eth_set_rate_gether,
707
a3153d8c
SS		 708 .register_type = SH_ETH_REG_GIGABIT,
709
f5d12767
SS		 710 .ecsr_value = ECSR_ICD | ECSR_MPD,
711 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
712 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
713
714 .tx_check = EESR_TC1 | EESR_FTC,
ca8c3585
SS		 715 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
716 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
717 EESR_TDE | EESR_ECI,
f5d12767
SS		 718
719 .apr = 1,
720 .mpr = 1,
721 .tpauser = 1,
722 .bculr = 1,
723 .hw_swap = 1,
724 .no_trimd = 1,
725 .no_ade = 1,
726 .tsu = 1,
727 .hw_crc = 1,
728 .select_mii = 1,
729};
730
731/* SH7763 */
732static struct sh_eth_cpu_data sh7763_data = {
733 .chip_reset = sh_eth_chip_reset,
734 .set_duplex = sh_eth_set_duplex,
735 .set_rate = sh_eth_set_rate_gether,
380af9e3 736
a3153d8c
SS		 737 .register_type = SH_ETH_REG_GIGABIT,
738
380af9e3
YS		 739 .ecsr_value = ECSR_ICD | ECSR_MPD,
740 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
741 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
742
743 .tx_check = EESR_TC1 | EESR_FTC,
128296fc
SS		 744 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
745 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
380af9e3 746 EESR_ECI,
380af9e3
YS		 747
748 .apr = 1,
749 .mpr = 1,
750 .tpauser = 1,
751 .bculr = 1,
752 .hw_swap = 1,
380af9e3
YS		 753 .no_trimd = 1,
754 .no_ade = 1,
4986b996 755 .tsu = 1,
5b3dfd13 756 .irq_flags = IRQF_SHARED,
380af9e3
YS		 757};
758
e5c9b4cd 759static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
73a0d907
YS		 760{
761 struct sh_eth_private *mdp = netdev_priv(ndev);
73a0d907
YS		 762
763 /* reset device */
764 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
765 mdelay(1);
766
5e7a76be 767 sh_eth_select_mii(ndev);
73a0d907
YS		 768}
769
73a0d907 770/* R8A7740 */
e5c9b4cd
SS		 771static struct sh_eth_cpu_data r8a7740_data = {
772 .chip_reset = sh_eth_chip_reset_r8a7740,
73a0d907 773 .set_duplex = sh_eth_set_duplex,
e5c9b4cd 774 .set_rate = sh_eth_set_rate_gether,
73a0d907 775
a3153d8c
SS		 776 .register_type = SH_ETH_REG_GIGABIT,
777
73a0d907
YS		 778 .ecsr_value = ECSR_ICD | ECSR_MPD,
779 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
780 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
781
782 .tx_check = EESR_TC1 | EESR_FTC,
ca8c3585
SS		 783 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
784 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
785 EESR_TDE | EESR_ECI,
cc23528d 786 .fdr_value = 0x0000070f,
73a0d907
YS		 787
788 .apr = 1,
789 .mpr = 1,
790 .tpauser = 1,
791 .bculr = 1,
792 .hw_swap = 1,
cc23528d
SH		 793 .rpadir = 1,
794 .rpadir_value = 2 << 16,
73a0d907
YS		 795 .no_trimd = 1,
796 .no_ade = 1,
797 .tsu = 1,
5e7a76be 798 .select_mii = 1,
ac8025a6 799 .shift_rd0 = 1,
73a0d907
YS		 800};
801
db893473
SH		 802/* R7S72100 */
803static struct sh_eth_cpu_data r7s72100_data = {
804 .chip_reset = sh_eth_chip_reset,
805 .set_duplex = sh_eth_set_duplex,
806
807 .register_type = SH_ETH_REG_FAST_RZ,
808
809 .ecsr_value = ECSR_ICD,
810 .ecsipr_value = ECSIPR_ICDIP,
811 .eesipr_value = 0xff7f009f,
812
813 .tx_check = EESR_TC1 | EESR_FTC,
814 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
815 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
816 EESR_TDE | EESR_ECI,
817 .fdr_value = 0x0000070f,
db893473
SH		 818
819 .no_psr = 1,
820 .apr = 1,
821 .mpr = 1,
822 .tpauser = 1,
823 .hw_swap = 1,
824 .rpadir = 1,
825 .rpadir_value = 2 << 16,
826 .no_trimd = 1,
827 .no_ade = 1,
828 .hw_crc = 1,
829 .tsu = 1,
830 .shift_rd0 = 1,
831};
832
c18a79ab 833static struct sh_eth_cpu_data sh7619_data = {
a3153d8c
SS		 834 .register_type = SH_ETH_REG_FAST_SH3_SH2,
835
380af9e3
YS		 836 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
837
838 .apr = 1,
839 .mpr = 1,
840 .tpauser = 1,
841 .hw_swap = 1,
842};
7bbe150d
SS		 843
844static struct sh_eth_cpu_data sh771x_data = {
a3153d8c
SS		 845 .register_type = SH_ETH_REG_FAST_SH3_SH2,
846
380af9e3 847 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
4986b996 848 .tsu = 1,
380af9e3 849};
380af9e3
YS		 850
851static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
852{
853 if (!cd->ecsr_value)
854 cd->ecsr_value = DEFAULT_ECSR_INIT;
855
856 if (!cd->ecsipr_value)
857 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
858
859 if (!cd->fcftr_value)
128296fc 860 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF |
380af9e3
YS		 861 DEFAULT_FIFO_F_D_RFD;
862
863 if (!cd->fdr_value)
864 cd->fdr_value = DEFAULT_FDR_INIT;
865
380af9e3
YS		 866 if (!cd->tx_check)
867 cd->tx_check = DEFAULT_TX_CHECK;
868
869 if (!cd->eesr_err_check)
870 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
b284fbe3
NI		 871
872 if (!cd->trscer_err_mask)
873 cd->trscer_err_mask = DEFAULT_TRSCER_ERR_MASK;
380af9e3
YS		 874}
875
5cee1d37
NI		 876static int sh_eth_check_reset(struct net_device *ndev)
877{
878 int ret = 0;
879 int cnt = 100;
880
881 while (cnt > 0) {
882 if (!(sh_eth_read(ndev, EDMR) & 0x3))
883 break;
884 mdelay(1);
885 cnt--;
886 }
9f8c4265 887 if (cnt <= 0) {
f75f14ec 888 netdev_err(ndev, "Device reset failed\n");
5cee1d37
NI		 889 ret = -ETIMEDOUT;
890 }
891 return ret;
380af9e3 892}
dabdde9e
NI		 893
894static int sh_eth_reset(struct net_device *ndev)
895{
896 struct sh_eth_private *mdp = netdev_priv(ndev);
897 int ret = 0;
898
db893473 899 if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp)) {
dabdde9e
NI		 900 sh_eth_write(ndev, EDSR_ENALL, EDSR);
901 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER,
902 EDMR);
903
904 ret = sh_eth_check_reset(ndev);
905 if (ret)
f738a13d 906 return ret;
dabdde9e
NI		 907
908 /* Table Init */
909 sh_eth_write(ndev, 0x0, TDLAR);
910 sh_eth_write(ndev, 0x0, TDFAR);
911 sh_eth_write(ndev, 0x0, TDFXR);
912 sh_eth_write(ndev, 0x0, TDFFR);
913 sh_eth_write(ndev, 0x0, RDLAR);
914 sh_eth_write(ndev, 0x0, RDFAR);
915 sh_eth_write(ndev, 0x0, RDFXR);
916 sh_eth_write(ndev, 0x0, RDFFR);
917
918 /* Reset HW CRC register */
919 if (mdp->cd->hw_crc)
920 sh_eth_write(ndev, 0x0, CSMR);
921
922 /* Select MII mode */
923 if (mdp->cd->select_mii)
924 sh_eth_select_mii(ndev);
925 } else {
926 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER,
927 EDMR);
928 mdelay(3);
929 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER,
930 EDMR);
931 }
932
dabdde9e
NI		 933 return ret;
934}
380af9e3 935
380af9e3
YS		 936static void sh_eth_set_receive_align(struct sk_buff *skb)
937{
4d6a949c 938 uintptr_t reserve = (uintptr_t)skb->data & (SH_ETH_RX_ALIGN - 1);
380af9e3 939
380af9e3 940 if (reserve)
4d6a949c 941 skb_reserve(skb, SH_ETH_RX_ALIGN - reserve);
380af9e3 942}
380af9e3
YS		 943
944
71557a37
YS		 945/* CPU <-> EDMAC endian convert */
946static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x)
947{
948 switch (mdp->edmac_endian) {
949 case EDMAC_LITTLE_ENDIAN:
950 return cpu_to_le32(x);
951 case EDMAC_BIG_ENDIAN:
952 return cpu_to_be32(x);
953 }
954 return x;
955}
956
957static inline __u32 edmac_to_cpu(struct sh_eth_private *mdp, u32 x)
958{
959 switch (mdp->edmac_endian) {
960 case EDMAC_LITTLE_ENDIAN:
961 return le32_to_cpu(x);
962 case EDMAC_BIG_ENDIAN:
963 return be32_to_cpu(x);
964 }
965 return x;
966}
967
128296fc 968/* Program the hardware MAC address from dev->dev_addr. */
86a74ff2
NI		 969static void update_mac_address(struct net_device *ndev)
970{
4a55530f 971 sh_eth_write(ndev,
128296fc
SS		 972 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
973 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
4a55530f 974 sh_eth_write(ndev,
128296fc 975 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
86a74ff2
NI		 976}
977
128296fc 978/* Get MAC address from SuperH MAC address register
86a74ff2
NI		 979 *
980 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
981 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
982 * When you want use this device, you must set MAC address in bootloader.
983 *
984 */
748031f9 985static void read_mac_address(struct net_device *ndev, unsigned char *mac)
86a74ff2 986{
748031f9 987 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
d458cdf7 988 memcpy(ndev->dev_addr, mac, ETH_ALEN);
748031f9 989 } else {
4a55530f
YS		 990 ndev->dev_addr[0] = (sh_eth_read(ndev, MAHR) >> 24);
991 ndev->dev_addr[1] = (sh_eth_read(ndev, MAHR) >> 16) & 0xFF;
992 ndev->dev_addr[2] = (sh_eth_read(ndev, MAHR) >> 8) & 0xFF;
993 ndev->dev_addr[3] = (sh_eth_read(ndev, MAHR) & 0xFF);
994 ndev->dev_addr[4] = (sh_eth_read(ndev, MALR) >> 8) & 0xFF;
995 ndev->dev_addr[5] = (sh_eth_read(ndev, MALR) & 0xFF);
748031f9 996 }
86a74ff2
NI		 997}
998
0799c2d6 999static u32 sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
c5ed5368 1000{
db893473 1001 if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp))
c5ed5368
YS		 1002 return EDTRR_TRNS_GETHER;
1003 else
1004 return EDTRR_TRNS_ETHER;
1005}
1006
86a74ff2 1007struct bb_info {
ae70644d 1008 void (*set_gate)(void *addr);
86a74ff2 1009 struct mdiobb_ctrl ctrl;
ae70644d 1010 void *addr;
86a74ff2
NI		 1011 u32 mmd_msk;/* MMD */
1012 u32 mdo_msk;
1013 u32 mdi_msk;
1014 u32 mdc_msk;
1015};
1016
1017/* PHY bit set */
ae70644d 1018static void bb_set(void *addr, u32 msk)
86a74ff2 1019{
ae70644d 1020 iowrite32(ioread32(addr) | msk, addr);
86a74ff2
NI		 1021}
1022
1023/* PHY bit clear */
ae70644d 1024static void bb_clr(void *addr, u32 msk)
86a74ff2 1025{
ae70644d 1026 iowrite32((ioread32(addr) & ~msk), addr);
86a74ff2
NI		 1027}
1028
1029/* PHY bit read */
ae70644d 1030static int bb_read(void *addr, u32 msk)
86a74ff2 1031{
ae70644d 1032 return (ioread32(addr) & msk) != 0;
86a74ff2
NI		 1033}
1034
1035/* Data I/O pin control */
1036static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1037{
1038 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
b3017e6a
YS		 1039
1040 if (bitbang->set_gate)
1041 bitbang->set_gate(bitbang->addr);
1042
86a74ff2
NI		 1043 if (bit)
1044 bb_set(bitbang->addr, bitbang->mmd_msk);
1045 else
1046 bb_clr(bitbang->addr, bitbang->mmd_msk);
1047}
1048
1049/* Set bit data*/
1050static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
1051{
1052 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1053
b3017e6a
YS		 1054 if (bitbang->set_gate)
1055 bitbang->set_gate(bitbang->addr);
1056
86a74ff2
NI		 1057 if (bit)
1058 bb_set(bitbang->addr, bitbang->mdo_msk);
1059 else
1060 bb_clr(bitbang->addr, bitbang->mdo_msk);
1061}
1062
1063/* Get bit data*/
1064static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
1065{
1066 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
b3017e6a
YS		 1067
1068 if (bitbang->set_gate)
1069 bitbang->set_gate(bitbang->addr);
1070
86a74ff2
NI		 1071 return bb_read(bitbang->addr, bitbang->mdi_msk);
1072}
1073
1074/* MDC pin control */
1075static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1076{
1077 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1078
b3017e6a
YS		 1079 if (bitbang->set_gate)
1080 bitbang->set_gate(bitbang->addr);
1081
86a74ff2
NI		 1082 if (bit)
1083 bb_set(bitbang->addr, bitbang->mdc_msk);
1084 else
1085 bb_clr(bitbang->addr, bitbang->mdc_msk);
1086}
1087
1088/* mdio bus control struct */
1089static struct mdiobb_ops bb_ops = {
1090 .owner = THIS_MODULE,
1091 .set_mdc = sh_mdc_ctrl,
1092 .set_mdio_dir = sh_mmd_ctrl,
1093 .set_mdio_data = sh_set_mdio,
1094 .get_mdio_data = sh_get_mdio,
1095};
1096
86a74ff2
NI		 1097/* free skb and descriptor buffer */
1098static void sh_eth_ring_free(struct net_device *ndev)
1099{
1100 struct sh_eth_private *mdp = netdev_priv(ndev);
1101 int i;
1102
1103 /* Free Rx skb ringbuffer */
1104 if (mdp->rx_skbuff) {
179d80af
SS		 1105 for (i = 0; i < mdp->num_rx_ring; i++)
1106 dev_kfree_skb(mdp->rx_skbuff[i]);
86a74ff2
NI		 1107 }
1108 kfree(mdp->rx_skbuff);
91c77550 1109 mdp->rx_skbuff = NULL;
86a74ff2
NI		 1110
1111 /* Free Tx skb ringbuffer */
1112 if (mdp->tx_skbuff) {
179d80af
SS		 1113 for (i = 0; i < mdp->num_tx_ring; i++)
1114 dev_kfree_skb(mdp->tx_skbuff[i]);
86a74ff2
NI		 1115 }
1116 kfree(mdp->tx_skbuff);
91c77550 1117 mdp->tx_skbuff = NULL;
86a74ff2
NI		 1118}
1119
1120/* format skb and descriptor buffer */
1121static void sh_eth_ring_format(struct net_device *ndev)
1122{
1123 struct sh_eth_private *mdp = netdev_priv(ndev);
1124 int i;
1125 struct sk_buff *skb;
1126 struct sh_eth_rxdesc *rxdesc = NULL;
1127 struct sh_eth_txdesc *txdesc = NULL;
525b8075
YS		 1128 int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
1129 int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
cb368595 1130 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
52b9fa36 1131 dma_addr_t dma_addr;
86a74ff2 1132
128296fc
SS		 1133 mdp->cur_rx = 0;
1134 mdp->cur_tx = 0;
1135 mdp->dirty_rx = 0;
1136 mdp->dirty_tx = 0;
86a74ff2
NI		 1137
1138 memset(mdp->rx_ring, 0, rx_ringsize);
1139
1140 /* build Rx ring buffer */
525b8075 1141 for (i = 0; i < mdp->num_rx_ring; i++) {
86a74ff2
NI		 1142 /* skb */
1143 mdp->rx_skbuff[i] = NULL;
4d6a949c 1144 skb = netdev_alloc_skb(ndev, skbuff_size);
86a74ff2
NI		 1145 if (skb == NULL)
1146 break;
380af9e3
YS		 1147 sh_eth_set_receive_align(skb);
1148
86a74ff2
NI		 1149 /* RX descriptor */
1150 rxdesc = &mdp->rx_ring[i];
ab857916
SS		 1151 /* The size of the buffer is a multiple of 32 bytes. */
1152 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 32);
52b9fa36
BH		 1153 dma_addr = dma_map_single(&ndev->dev, skb->data,
1154 rxdesc->buffer_length,
1155 DMA_FROM_DEVICE);
1156 if (dma_mapping_error(&ndev->dev, dma_addr)) {
1157 kfree_skb(skb);
1158 break;
1159 }
1160 mdp->rx_skbuff[i] = skb;
1161 rxdesc->addr = dma_addr;
71557a37 1162 rxdesc->status = cpu_to_edmac(mdp, RD_RACT | RD_RFP);
86a74ff2 1163
b0ca2a21
NI		 1164 /* Rx descriptor address set */
1165 if (i == 0) {
4a55530f 1166 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
db893473
SH		 1167 if (sh_eth_is_gether(mdp) ||
1168 sh_eth_is_rz_fast_ether(mdp))
c5ed5368 1169 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
b0ca2a21 1170 }
86a74ff2
NI		 1171 }
1172
525b8075 1173 mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
86a74ff2
NI		 1174
1175 /* Mark the last entry as wrapping the ring. */
c238041f 1176 rxdesc->status |= cpu_to_edmac(mdp, RD_RDLE);
86a74ff2
NI		 1177
1178 memset(mdp->tx_ring, 0, tx_ringsize);
1179
1180 /* build Tx ring buffer */
525b8075 1181 for (i = 0; i < mdp->num_tx_ring; i++) {
86a74ff2
NI		 1182 mdp->tx_skbuff[i] = NULL;
1183 txdesc = &mdp->tx_ring[i];
71557a37 1184 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
86a74ff2 1185 txdesc->buffer_length = 0;
b0ca2a21 1186 if (i == 0) {
71557a37 1187 /* Tx descriptor address set */
4a55530f 1188 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
db893473
SH		 1189 if (sh_eth_is_gether(mdp) ||
1190 sh_eth_is_rz_fast_ether(mdp))
c5ed5368 1191 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
b0ca2a21 1192 }
86a74ff2
NI		 1193 }
1194
71557a37 1195 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
86a74ff2
NI		 1196}
1197
1198/* Get skb and descriptor buffer */
1199static int sh_eth_ring_init(struct net_device *ndev)
1200{
1201 struct sh_eth_private *mdp = netdev_priv(ndev);
91d80683 1202 int rx_ringsize, tx_ringsize;
86a74ff2 1203
128296fc 1204 /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
86a74ff2
NI		 1205 * card needs room to do 8 byte alignment, +2 so we can reserve
1206 * the first 2 bytes, and +16 gets room for the status word from the
1207 * card.
1208 */
1209 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
1210 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
503914cf
MD		 1211 if (mdp->cd->rpadir)
1212 mdp->rx_buf_sz += NET_IP_ALIGN;
86a74ff2
NI		 1213
1214 /* Allocate RX and TX skb rings */
2c94e856
SS		 1215 mdp->rx_skbuff = kcalloc(mdp->num_rx_ring, sizeof(*mdp->rx_skbuff),
1216 GFP_KERNEL);
91d80683
SS		 1217 if (!mdp->rx_skbuff)
1218 return -ENOMEM;
86a74ff2 1219
2c94e856
SS		 1220 mdp->tx_skbuff = kcalloc(mdp->num_tx_ring, sizeof(*mdp->tx_skbuff),
1221 GFP_KERNEL);
91d80683 1222 if (!mdp->tx_skbuff)
86a74ff2 1223 goto skb_ring_free;
86a74ff2
NI		 1224
1225 /* Allocate all Rx descriptors. */
525b8075 1226 rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
86a74ff2 1227 mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
d0320f75 1228 GFP_KERNEL);
91d80683 1229 if (!mdp->rx_ring)
b61ed8fd 1230 goto skb_ring_free;
86a74ff2
NI		 1231
1232 mdp->dirty_rx = 0;
1233
1234 /* Allocate all Tx descriptors. */
525b8075 1235 tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
86a74ff2 1236 mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
d0320f75 1237 GFP_KERNEL);
91d80683 1238 if (!mdp->tx_ring)
86a74ff2 1239 goto desc_ring_free;
91d80683 1240 return 0;
86a74ff2
NI		 1241
1242desc_ring_free:
1243 /* free DMA buffer */
1244 dma_free_coherent(NULL, rx_ringsize, mdp->rx_ring, mdp->rx_desc_dma);
1245
1246skb_ring_free:
1247 /* Free Rx and Tx skb ring buffer */
1248 sh_eth_ring_free(ndev);
91c77550
YS		 1249 mdp->tx_ring = NULL;
1250 mdp->rx_ring = NULL;
86a74ff2 1251
91d80683 1252 return -ENOMEM;
86a74ff2
NI		 1253}
1254
91c77550
YS		 1255static void sh_eth_free_dma_buffer(struct sh_eth_private *mdp)
1256{
1257 int ringsize;
1258
1259 if (mdp->rx_ring) {
525b8075 1260 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
91c77550
YS		 1261 dma_free_coherent(NULL, ringsize, mdp->rx_ring,
1262 mdp->rx_desc_dma);
1263 mdp->rx_ring = NULL;
1264 }
1265
1266 if (mdp->tx_ring) {
525b8075 1267 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
91c77550
YS		 1268 dma_free_coherent(NULL, ringsize, mdp->tx_ring,
1269 mdp->tx_desc_dma);
1270 mdp->tx_ring = NULL;
1271 }
1272}
1273
525b8075 1274static int sh_eth_dev_init(struct net_device *ndev, bool start)
86a74ff2
NI		 1275{
1276 int ret = 0;
1277 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 1278 u32 val;
1279
1280 /* Soft Reset */
5cee1d37
NI		 1281 ret = sh_eth_reset(ndev);
1282 if (ret)
f738a13d 1283 return ret;
86a74ff2 1284
55754f19
SH		 1285 if (mdp->cd->rmiimode)
1286 sh_eth_write(ndev, 0x1, RMIIMODE);
1287
b0ca2a21
NI		 1288 /* Descriptor format */
1289 sh_eth_ring_format(ndev);
380af9e3 1290 if (mdp->cd->rpadir)
4a55530f 1291 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
86a74ff2
NI		 1292
1293 /* all sh_eth int mask */
4a55530f 1294 sh_eth_write(ndev, 0, EESIPR);
86a74ff2 1295
10b9194f 1296#if defined(__LITTLE_ENDIAN)
380af9e3 1297 if (mdp->cd->hw_swap)
4a55530f 1298 sh_eth_write(ndev, EDMR_EL, EDMR);
380af9e3 1299 else
b0ca2a21 1300#endif
4a55530f 1301 sh_eth_write(ndev, 0, EDMR);
86a74ff2 1302
b0ca2a21 1303 /* FIFO size set */
4a55530f
YS		 1304 sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
1305 sh_eth_write(ndev, 0, TFTR);
86a74ff2 1306
530aa2d0
BD		 1307 /* Frame recv control (enable multiple-packets per rx irq) */
1308 sh_eth_write(ndev, RMCR_RNC, RMCR);
86a74ff2 1309
b284fbe3 1310 sh_eth_write(ndev, mdp->cd->trscer_err_mask, TRSCER);
86a74ff2 1311
380af9e3 1312 if (mdp->cd->bculr)
4a55530f 1313 sh_eth_write(ndev, 0x800, BCULR); /* Burst sycle set */
b0ca2a21 1314
4a55530f 1315 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
86a74ff2 1316
380af9e3 1317 if (!mdp->cd->no_trimd)
4a55530f 1318 sh_eth_write(ndev, 0, TRIMD);
86a74ff2 1319
b0ca2a21 1320 /* Recv frame limit set register */
fdb37a7f
YS		 1321 sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1322 RFLR);
86a74ff2 1323
4a55530f 1324 sh_eth_write(ndev, sh_eth_read(ndev, EESR), EESR);
283e38db
BH		 1325 if (start) {
1326 mdp->irq_enabled = true;
525b8075 1327 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
283e38db 1328 }
86a74ff2
NI		 1329
1330 /* PAUSE Prohibition */
4a55530f 1331 val = (sh_eth_read(ndev, ECMR) & ECMR_DM) |
86a74ff2
NI		 1332 ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE;
1333
4a55530f 1334 sh_eth_write(ndev, val, ECMR);
b0ca2a21 1335
380af9e3
YS		 1336 if (mdp->cd->set_rate)
1337 mdp->cd->set_rate(ndev);
1338
b0ca2a21 1339 /* E-MAC Status Register clear */
4a55530f 1340 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
b0ca2a21
NI		 1341
1342 /* E-MAC Interrupt Enable register */
525b8075
YS		 1343 if (start)
1344 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
86a74ff2
NI		 1345
1346 /* Set MAC address */
1347 update_mac_address(ndev);
1348
1349 /* mask reset */
380af9e3 1350 if (mdp->cd->apr)
4a55530f 1351 sh_eth_write(ndev, APR_AP, APR);
380af9e3 1352 if (mdp->cd->mpr)
4a55530f 1353 sh_eth_write(ndev, MPR_MP, MPR);
380af9e3 1354 if (mdp->cd->tpauser)
4a55530f 1355 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
b0ca2a21 1356
525b8075
YS		 1357 if (start) {
1358 /* Setting the Rx mode will start the Rx process. */
1359 sh_eth_write(ndev, EDRRR_R, EDRRR);
86a74ff2 1360
525b8075
YS		 1361 netif_start_queue(ndev);
1362 }
86a74ff2
NI		 1363
1364 return ret;
1365}
1366
740c7f31
BH		 1367static void sh_eth_dev_exit(struct net_device *ndev)
1368{
1369 struct sh_eth_private *mdp = netdev_priv(ndev);
1370 int i;
1371
1372 /* Deactivate all TX descriptors, so DMA should stop at next
1373 * packet boundary if it's currently running
1374 */
1375 for (i = 0; i < mdp->num_tx_ring; i++)
1376 mdp->tx_ring[i].status &= ~cpu_to_edmac(mdp, TD_TACT);
1377
1378 /* Disable TX FIFO egress to MAC */
1379 sh_eth_rcv_snd_disable(ndev);
1380
1381 /* Stop RX DMA at next packet boundary */
1382 sh_eth_write(ndev, 0, EDRRR);
1383
1384 /* Aside from TX DMA, we can't tell when the hardware is
1385 * really stopped, so we need to reset to make sure.
1386 * Before doing that, wait for long enough to *probably*
1387 * finish transmitting the last packet and poll stats.
1388 */
1389 msleep(2); /* max frame time at 10 Mbps < 1250 us */
1390 sh_eth_get_stats(ndev);
1391 sh_eth_reset(ndev);
a14c7d15
GU		 1392
1393 /* Set MAC address again */
1394 update_mac_address(ndev);
740c7f31
BH		 1395}
1396
86a74ff2
NI		 1397/* free Tx skb function */
1398static int sh_eth_txfree(struct net_device *ndev)
1399{
1400 struct sh_eth_private *mdp = netdev_priv(ndev);
1401 struct sh_eth_txdesc *txdesc;
128296fc 1402 int free_num = 0;
86a74ff2
NI		 1403 int entry = 0;
1404
1405 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
525b8075 1406 entry = mdp->dirty_tx % mdp->num_tx_ring;
86a74ff2 1407 txdesc = &mdp->tx_ring[entry];
71557a37 1408 if (txdesc->status & cpu_to_edmac(mdp, TD_TACT))
86a74ff2 1409 break;
7d7355f5 1410 /* TACT bit must be checked before all the following reads */
f32bfb9a 1411 dma_rmb();
e5fd13f4
BH		 1412 netif_info(mdp, tx_done, ndev,
1413 "tx entry %d status 0x%08x\n",
1414 entry, edmac_to_cpu(mdp, txdesc->status));
86a74ff2
NI		 1415 /* Free the original skb. */
1416 if (mdp->tx_skbuff[entry]) {
31fcb99d
YS		 1417 dma_unmap_single(&ndev->dev, txdesc->addr,
1418 txdesc->buffer_length, DMA_TO_DEVICE);
86a74ff2
NI		 1419 dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1420 mdp->tx_skbuff[entry] = NULL;
128296fc 1421 free_num++;
86a74ff2 1422 }
71557a37 1423 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
525b8075 1424 if (entry >= mdp->num_tx_ring - 1)
71557a37 1425 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
86a74ff2 1426
bb7d92e3
ED		 1427 ndev->stats.tx_packets++;
1428 ndev->stats.tx_bytes += txdesc->buffer_length;
86a74ff2 1429 }
128296fc 1430 return free_num;
86a74ff2
NI		 1431}
1432
1433/* Packet receive function */
3719109d 1434static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
86a74ff2
NI		 1435{
1436 struct sh_eth_private *mdp = netdev_priv(ndev);
1437 struct sh_eth_rxdesc *rxdesc;
1438
525b8075
YS		 1439 int entry = mdp->cur_rx % mdp->num_rx_ring;
1440 int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
319cd520 1441 int limit;
86a74ff2
NI		 1442 struct sk_buff *skb;
1443 u16 pkt_len = 0;
380af9e3 1444 u32 desc_status;
cb368595 1445 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
52b9fa36 1446 dma_addr_t dma_addr;
86a74ff2 1447
319cd520
MK		 1448 boguscnt = min(boguscnt, *quota);
1449 limit = boguscnt;
86a74ff2 1450 rxdesc = &mdp->rx_ring[entry];
71557a37 1451 while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) {
7d7355f5 1452 /* RACT bit must be checked before all the following reads */
f32bfb9a 1453 dma_rmb();
71557a37 1454 desc_status = edmac_to_cpu(mdp, rxdesc->status);
86a74ff2
NI		 1455 pkt_len = rxdesc->frame_length;
1456
1457 if (--boguscnt < 0)
1458 break;
1459
e5fd13f4
BH		 1460 netif_info(mdp, rx_status, ndev,
1461 "rx entry %d status 0x%08x len %d\n",
1462 entry, desc_status, pkt_len);
1463
86a74ff2 1464 if (!(desc_status & RDFEND))
bb7d92e3 1465 ndev->stats.rx_length_errors++;
86a74ff2 1466
128296fc 1467 /* In case of almost all GETHER/ETHERs, the Receive Frame State
dd019897 1468 * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
9b4a6364
BH		 1469 * bit 0. However, in case of the R8A7740 and R7S72100
1470 * the RFS bits are from bit 25 to bit 16. So, the
db893473 1471 * driver needs right shifting by 16.
dd019897 1472 */
ac8025a6
SS		 1473 if (mdp->cd->shift_rd0)
1474 desc_status >>= 16;
dd019897 1475
86a74ff2
NI		 1476 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1477 RD_RFS5 | RD_RFS6 | RD_RFS10)) {
bb7d92e3 1478 ndev->stats.rx_errors++;
86a74ff2 1479 if (desc_status & RD_RFS1)
bb7d92e3 1480 ndev->stats.rx_crc_errors++;
86a74ff2 1481 if (desc_status & RD_RFS2)
bb7d92e3 1482 ndev->stats.rx_frame_errors++;
86a74ff2 1483 if (desc_status & RD_RFS3)
bb7d92e3 1484 ndev->stats.rx_length_errors++;
86a74ff2 1485 if (desc_status & RD_RFS4)
bb7d92e3 1486 ndev->stats.rx_length_errors++;
86a74ff2 1487 if (desc_status & RD_RFS6)
bb7d92e3 1488 ndev->stats.rx_missed_errors++;
86a74ff2 1489 if (desc_status & RD_RFS10)
bb7d92e3 1490 ndev->stats.rx_over_errors++;
86a74ff2 1491 } else {
380af9e3
YS		 1492 if (!mdp->cd->hw_swap)
1493 sh_eth_soft_swap(
1494 phys_to_virt(ALIGN(rxdesc->addr, 4)),
1495 pkt_len + 2);
86a74ff2
NI		 1496 skb = mdp->rx_skbuff[entry];
1497 mdp->rx_skbuff[entry] = NULL;
503914cf
MD		 1498 if (mdp->cd->rpadir)
1499 skb_reserve(skb, NET_IP_ALIGN);
52b9fa36 1500 dma_unmap_single(&ndev->dev, rxdesc->addr,
ab857916 1501 ALIGN(mdp->rx_buf_sz, 32),
52b9fa36 1502 DMA_FROM_DEVICE);
86a74ff2
NI		 1503 skb_put(skb, pkt_len);
1504 skb->protocol = eth_type_trans(skb, ndev);
a8e9fd0f 1505 netif_receive_skb(skb);
bb7d92e3
ED		 1506 ndev->stats.rx_packets++;
1507 ndev->stats.rx_bytes += pkt_len;
25b77ad7
BH		 1508 if (desc_status & RD_RFS8)
1509 ndev->stats.multicast++;
86a74ff2 1510 }
525b8075 1511 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
862df497 1512 rxdesc = &mdp->rx_ring[entry];
86a74ff2
NI		 1513 }
1514
1515 /* Refill the Rx ring buffers. */
1516 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
525b8075 1517 entry = mdp->dirty_rx % mdp->num_rx_ring;
86a74ff2 1518 rxdesc = &mdp->rx_ring[entry];
ab857916
SS		 1519 /* The size of the buffer is 32 byte boundary. */
1520 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 32);
b0ca2a21 1521
86a74ff2 1522 if (mdp->rx_skbuff[entry] == NULL) {
4d6a949c 1523 skb = netdev_alloc_skb(ndev, skbuff_size);
86a74ff2
NI		 1524 if (skb == NULL)
1525 break; /* Better luck next round. */
380af9e3 1526 sh_eth_set_receive_align(skb);
52b9fa36
BH		 1527 dma_addr = dma_map_single(&ndev->dev, skb->data,
1528 rxdesc->buffer_length,
1529 DMA_FROM_DEVICE);
1530 if (dma_mapping_error(&ndev->dev, dma_addr)) {
1531 kfree_skb(skb);
1532 break;
1533 }
1534 mdp->rx_skbuff[entry] = skb;
380af9e3 1535
bc8acf2c 1536 skb_checksum_none_assert(skb);
52b9fa36 1537 rxdesc->addr = dma_addr;
86a74ff2 1538 }
f32bfb9a 1539 dma_wmb(); /* RACT bit must be set after all the above writes */
525b8075 1540 if (entry >= mdp->num_rx_ring - 1)
86a74ff2 1541 rxdesc->status |=
c238041f 1542 cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDLE);
86a74ff2
NI		 1543 else
1544 rxdesc->status |=
71557a37 1545 cpu_to_edmac(mdp, RD_RACT | RD_RFP);
86a74ff2
NI		 1546 }
1547
1548 /* Restart Rx engine if stopped. */
1549 /* If we don't need to check status, don't. -KDU */
79fba9f5 1550 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
a18e08bd 1551 /* fix the values for the next receiving if RDE is set */
3365711d
BH		 1552 if (intr_status & EESR_RDE &&
1553 mdp->reg_offset[RDFAR] != SH_ETH_OFFSET_INVALID) {
128296fc
SS		 1554 u32 count = (sh_eth_read(ndev, RDFAR) -
1555 sh_eth_read(ndev, RDLAR)) >> 4;
1556
1557 mdp->cur_rx = count;
1558 mdp->dirty_rx = count;
1559 }
4a55530f 1560 sh_eth_write(ndev, EDRRR_R, EDRRR);
79fba9f5 1561 }
86a74ff2 1562
319cd520
MK		 1563 *quota -= limit - boguscnt - 1;
1564
4f809cea 1565 return *quota <= 0;
86a74ff2
NI		 1566}
1567
4a55530f 1568static void sh_eth_rcv_snd_disable(struct net_device *ndev)
dc19e4e5
NI		 1569{
1570 /* disable tx and rx */
4a55530f
YS		 1571 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) &
1572 ~(ECMR_RE | ECMR_TE), ECMR);
dc19e4e5
NI		 1573}
1574
4a55530f 1575static void sh_eth_rcv_snd_enable(struct net_device *ndev)
dc19e4e5
NI		 1576{
1577 /* enable tx and rx */
4a55530f
YS		 1578 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) |
1579 (ECMR_RE | ECMR_TE), ECMR);
dc19e4e5
NI		 1580}
1581
86a74ff2 1582/* error control function */
0799c2d6 1583static void sh_eth_error(struct net_device *ndev, u32 intr_status)
86a74ff2
NI		 1584{
1585 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2 1586 u32 felic_stat;
380af9e3
YS		 1587 u32 link_stat;
1588 u32 mask;
86a74ff2
NI		 1589
1590 if (intr_status & EESR_ECI) {
4a55530f
YS		 1591 felic_stat = sh_eth_read(ndev, ECSR);
1592 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */
86a74ff2 1593 if (felic_stat & ECSR_ICD)
bb7d92e3 1594 ndev->stats.tx_carrier_errors++;
86a74ff2
NI		 1595 if (felic_stat & ECSR_LCHNG) {
1596 /* Link Changed */
4923576b 1597 if (mdp->cd->no_psr || mdp->no_ether_link) {
1e1b812b 1598 goto ignore_link;
380af9e3 1599 } else {
4a55530f 1600 link_stat = (sh_eth_read(ndev, PSR));
4923576b
YS		 1601 if (mdp->ether_link_active_low)
1602 link_stat = ~link_stat;
380af9e3 1603 }
128296fc 1604 if (!(link_stat & PHY_ST_LINK)) {
4a55530f 1605 sh_eth_rcv_snd_disable(ndev);
128296fc 1606 } else {
86a74ff2 1607 /* Link Up */
4a55530f 1608 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) &
128296fc
SS		 1609 ~DMAC_M_ECI, EESIPR);
1610 /* clear int */
4a55530f 1611 sh_eth_write(ndev, sh_eth_read(ndev, ECSR),
128296fc 1612 ECSR);
4a55530f 1613 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) |
128296fc 1614 DMAC_M_ECI, EESIPR);
86a74ff2 1615 /* enable tx and rx */
4a55530f 1616 sh_eth_rcv_snd_enable(ndev);
86a74ff2
NI		 1617 }
1618 }
1619 }
1620
1e1b812b 1621ignore_link:
86a74ff2 1622 if (intr_status & EESR_TWB) {
4eb313a7
SS		 1623 /* Unused write back interrupt */
1624 if (intr_status & EESR_TABT) { /* Transmit Abort int */
bb7d92e3 1625 ndev->stats.tx_aborted_errors++;
8d5009f6 1626 netif_err(mdp, tx_err, ndev, "Transmit Abort\n");
4eb313a7 1627 }
86a74ff2
NI		 1628 }
1629
1630 if (intr_status & EESR_RABT) {
1631 /* Receive Abort int */
1632 if (intr_status & EESR_RFRMER) {
1633 /* Receive Frame Overflow int */
bb7d92e3 1634 ndev->stats.rx_frame_errors++;
86a74ff2
NI		 1635 }
1636 }
380af9e3 1637
dc19e4e5
NI		 1638 if (intr_status & EESR_TDE) {
1639 /* Transmit Descriptor Empty int */
bb7d92e3 1640 ndev->stats.tx_fifo_errors++;
8d5009f6 1641 netif_err(mdp, tx_err, ndev, "Transmit Descriptor Empty\n");
dc19e4e5
NI		 1642 }
1643
1644 if (intr_status & EESR_TFE) {
1645 /* FIFO under flow */
bb7d92e3 1646 ndev->stats.tx_fifo_errors++;
8d5009f6 1647 netif_err(mdp, tx_err, ndev, "Transmit FIFO Under flow\n");
86a74ff2
NI		 1648 }
1649
1650 if (intr_status & EESR_RDE) {
1651 /* Receive Descriptor Empty int */
bb7d92e3 1652 ndev->stats.rx_over_errors++;
86a74ff2 1653 }
dc19e4e5 1654
86a74ff2
NI		 1655 if (intr_status & EESR_RFE) {
1656 /* Receive FIFO Overflow int */
bb7d92e3 1657 ndev->stats.rx_fifo_errors++;
dc19e4e5
NI		 1658 }
1659
1660 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1661 /* Address Error */
bb7d92e3 1662 ndev->stats.tx_fifo_errors++;
8d5009f6 1663 netif_err(mdp, tx_err, ndev, "Address Error\n");
86a74ff2 1664 }
380af9e3
YS		 1665
1666 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1667 if (mdp->cd->no_ade)
1668 mask &= ~EESR_ADE;
1669 if (intr_status & mask) {
86a74ff2 1670 /* Tx error */
4a55530f 1671 u32 edtrr = sh_eth_read(ndev, EDTRR);
090d560f 1672
86a74ff2 1673 /* dmesg */
da246855
SS		 1674 netdev_err(ndev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1675 intr_status, mdp->cur_tx, mdp->dirty_tx,
1676 (u32)ndev->state, edtrr);
86a74ff2
NI		 1677 /* dirty buffer free */
1678 sh_eth_txfree(ndev);
1679
1680 /* SH7712 BUG */
c5ed5368 1681 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
86a74ff2 1682 /* tx dma start */
c5ed5368 1683 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
86a74ff2
NI		 1684 }
1685 /* wakeup */
1686 netif_wake_queue(ndev);
1687 }
1688}
1689
1690static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1691{
1692 struct net_device *ndev = netdev;
1693 struct sh_eth_private *mdp = netdev_priv(ndev);
380af9e3 1694 struct sh_eth_cpu_data *cd = mdp->cd;
0e0fde3c 1695 irqreturn_t ret = IRQ_NONE;
0799c2d6 1696 u32 intr_status, intr_enable;
86a74ff2 1697
86a74ff2
NI		 1698 spin_lock(&mdp->lock);
1699
3893b273 1700 /* Get interrupt status */
4a55530f 1701 intr_status = sh_eth_read(ndev, EESR);
3893b273
SS		 1702 /* Mask it with the interrupt mask, forcing ECI interrupt to be always
1703 * enabled since it's the one that comes thru regardless of the mask,
1704 * and we need to fully handle it in sh_eth_error() in order to quench
1705 * it as it doesn't get cleared by just writing 1 to the ECI bit...
1706 */
3719109d
SS		 1707 intr_enable = sh_eth_read(ndev, EESIPR);
1708 intr_status &= intr_enable | DMAC_M_ECI;
1709 if (intr_status & (EESR_RX_CHECK | cd->tx_check | cd->eesr_err_check))
0e0fde3c 1710 ret = IRQ_HANDLED;
3719109d 1711 else
283e38db
BH		 1712 goto out;
1713
1714 if (!likely(mdp->irq_enabled)) {
1715 sh_eth_write(ndev, 0, EESIPR);
1716 goto out;
1717 }
86a74ff2 1718
3719109d
SS		 1719 if (intr_status & EESR_RX_CHECK) {
1720 if (napi_schedule_prep(&mdp->napi)) {
1721 /* Mask Rx interrupts */
1722 sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK,
1723 EESIPR);
1724 __napi_schedule(&mdp->napi);
1725 } else {
da246855 1726 netdev_warn(ndev,
0799c2d6 1727 "ignoring interrupt, status 0x%08x, mask 0x%08x.\n",
da246855 1728 intr_status, intr_enable);
3719109d
SS		 1729 }
1730 }
86a74ff2 1731
b0ca2a21 1732 /* Tx Check */
380af9e3 1733 if (intr_status & cd->tx_check) {
3719109d
SS		 1734 /* Clear Tx interrupts */
1735 sh_eth_write(ndev, intr_status & cd->tx_check, EESR);
1736
86a74ff2
NI		 1737 sh_eth_txfree(ndev);
1738 netif_wake_queue(ndev);
1739 }
1740
3719109d
SS		 1741 if (intr_status & cd->eesr_err_check) {
1742 /* Clear error interrupts */
1743 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR);
1744
86a74ff2 1745 sh_eth_error(ndev, intr_status);
3719109d 1746 }
86a74ff2 1747
283e38db 1748out:
86a74ff2
NI		 1749 spin_unlock(&mdp->lock);
1750
0e0fde3c 1751 return ret;
86a74ff2
NI		 1752}
1753
3719109d
SS		 1754static int sh_eth_poll(struct napi_struct *napi, int budget)
1755{
1756 struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private,
1757 napi);
1758 struct net_device *ndev = napi->dev;
1759 int quota = budget;
0799c2d6 1760 u32 intr_status;
3719109d
SS		 1761
1762 for (;;) {
1763 intr_status = sh_eth_read(ndev, EESR);
1764 if (!(intr_status & EESR_RX_CHECK))
1765 break;
1766 /* Clear Rx interrupts */
1767 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR);
1768
1769 if (sh_eth_rx(ndev, intr_status, &quota))
1770 goto out;
1771 }
1772
1773 napi_complete(napi);
1774
1775 /* Reenable Rx interrupts */
283e38db
BH		 1776 if (mdp->irq_enabled)
1777 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
3719109d
SS		 1778out:
1779 return budget - quota;
1780}
1781
86a74ff2
NI		 1782/* PHY state control function */
1783static void sh_eth_adjust_link(struct net_device *ndev)
1784{
1785 struct sh_eth_private *mdp = netdev_priv(ndev);
1786 struct phy_device *phydev = mdp->phydev;
86a74ff2
NI		 1787 int new_state = 0;
1788
3340d2aa 1789 if (phydev->link) {
86a74ff2
NI		 1790 if (phydev->duplex != mdp->duplex) {
1791 new_state = 1;
1792 mdp->duplex = phydev->duplex;
380af9e3
YS		 1793 if (mdp->cd->set_duplex)
1794 mdp->cd->set_duplex(ndev);
86a74ff2
NI		 1795 }
1796
1797 if (phydev->speed != mdp->speed) {
1798 new_state = 1;
1799 mdp->speed = phydev->speed;
380af9e3
YS		 1800 if (mdp->cd->set_rate)
1801 mdp->cd->set_rate(ndev);
86a74ff2 1802 }
3340d2aa 1803 if (!mdp->link) {
91a56152 1804 sh_eth_write(ndev,
128296fc
SS		 1805 sh_eth_read(ndev, ECMR) & ~ECMR_TXF,
1806 ECMR);
86a74ff2
NI		 1807 new_state = 1;
1808 mdp->link = phydev->link;
1e1b812b
SS		 1809 if (mdp->cd->no_psr || mdp->no_ether_link)
1810 sh_eth_rcv_snd_enable(ndev);
86a74ff2
NI		 1811 }
1812 } else if (mdp->link) {
1813 new_state = 1;
3340d2aa 1814 mdp->link = 0;
86a74ff2
NI		 1815 mdp->speed = 0;
1816 mdp->duplex = -1;
1e1b812b
SS		 1817 if (mdp->cd->no_psr || mdp->no_ether_link)
1818 sh_eth_rcv_snd_disable(ndev);
86a74ff2
NI		 1819 }
1820
dc19e4e5 1821 if (new_state && netif_msg_link(mdp))
86a74ff2
NI		 1822 phy_print_status(phydev);
1823}
1824
1825/* PHY init function */
1826static int sh_eth_phy_init(struct net_device *ndev)
1827{
702eca02 1828 struct device_node *np = ndev->dev.parent->of_node;
86a74ff2 1829 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 1830 struct phy_device *phydev = NULL;
1831
3340d2aa 1832 mdp->link = 0;
86a74ff2
NI		 1833 mdp->speed = 0;
1834 mdp->duplex = -1;
1835
1836 /* Try connect to PHY */
702eca02
BD		 1837 if (np) {
1838 struct device_node *pn;
1839
1840 pn = of_parse_phandle(np, "phy-handle", 0);
1841 phydev = of_phy_connect(ndev, pn,
1842 sh_eth_adjust_link, 0,
1843 mdp->phy_interface);
1844
1845 if (!phydev)
1846 phydev = ERR_PTR(-ENOENT);
1847 } else {
1848 char phy_id[MII_BUS_ID_SIZE + 3];
1849
1850 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
1851 mdp->mii_bus->id, mdp->phy_id);
1852
1853 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
1854 mdp->phy_interface);
1855 }
1856
86a74ff2 1857 if (IS_ERR(phydev)) {
da246855 1858 netdev_err(ndev, "failed to connect PHY\n");
86a74ff2
NI		 1859 return PTR_ERR(phydev);
1860 }
380af9e3 1861
da246855
SS		 1862 netdev_info(ndev, "attached PHY %d (IRQ %d) to driver %s\n",
1863 phydev->addr, phydev->irq, phydev->drv->name);
86a74ff2
NI		 1864
1865 mdp->phydev = phydev;
1866
1867 return 0;
1868}
1869
1870/* PHY control start function */
1871static int sh_eth_phy_start(struct net_device *ndev)
1872{
1873 struct sh_eth_private *mdp = netdev_priv(ndev);
1874 int ret;
1875
1876 ret = sh_eth_phy_init(ndev);
1877 if (ret)
1878 return ret;
1879
86a74ff2
NI		 1880 phy_start(mdp->phydev);
1881
1882 return 0;
1883}
1884
dc19e4e5 1885static int sh_eth_get_settings(struct net_device *ndev,
128296fc 1886 struct ethtool_cmd *ecmd)
dc19e4e5
NI		 1887{
1888 struct sh_eth_private *mdp = netdev_priv(ndev);
1889 unsigned long flags;
1890 int ret;
1891
4f9dce23
BH		 1892 if (!mdp->phydev)
1893 return -ENODEV;
1894
dc19e4e5
NI		 1895 spin_lock_irqsave(&mdp->lock, flags);
1896 ret = phy_ethtool_gset(mdp->phydev, ecmd);
1897 spin_unlock_irqrestore(&mdp->lock, flags);
1898
1899 return ret;
1900}
1901
1902static int sh_eth_set_settings(struct net_device *ndev,
128296fc 1903 struct ethtool_cmd *ecmd)
dc19e4e5
NI		 1904{
1905 struct sh_eth_private *mdp = netdev_priv(ndev);
1906 unsigned long flags;
1907 int ret;
dc19e4e5 1908
4f9dce23
BH		 1909 if (!mdp->phydev)
1910 return -ENODEV;
1911
dc19e4e5
NI		 1912 spin_lock_irqsave(&mdp->lock, flags);
1913
1914 /* disable tx and rx */
4a55530f 1915 sh_eth_rcv_snd_disable(ndev);
dc19e4e5
NI		 1916
1917 ret = phy_ethtool_sset(mdp->phydev, ecmd);
1918 if (ret)
1919 goto error_exit;
1920
1921 if (ecmd->duplex == DUPLEX_FULL)
1922 mdp->duplex = 1;
1923 else
1924 mdp->duplex = 0;
1925
1926 if (mdp->cd->set_duplex)
1927 mdp->cd->set_duplex(ndev);
1928
1929error_exit:
1930 mdelay(1);
1931
1932 /* enable tx and rx */
4a55530f 1933 sh_eth_rcv_snd_enable(ndev);
dc19e4e5
NI		 1934
1935 spin_unlock_irqrestore(&mdp->lock, flags);
1936
1937 return ret;
1938}
1939
6b4b4fea
BH		 1940/* If it is ever necessary to increase SH_ETH_REG_DUMP_MAX_REGS, the
1941 * version must be bumped as well. Just adding registers up to that
1942 * limit is fine, as long as the existing register indices don't
1943 * change.
1944 */
1945#define SH_ETH_REG_DUMP_VERSION 1
1946#define SH_ETH_REG_DUMP_MAX_REGS 256
1947
1948static size_t __sh_eth_get_regs(struct net_device *ndev, u32 *buf)
1949{
1950 struct sh_eth_private *mdp = netdev_priv(ndev);
1951 struct sh_eth_cpu_data *cd = mdp->cd;
1952 u32 *valid_map;
1953 size_t len;
1954
1955 BUILD_BUG_ON(SH_ETH_MAX_REGISTER_OFFSET > SH_ETH_REG_DUMP_MAX_REGS);
1956
1957 /* Dump starts with a bitmap that tells ethtool which
1958 * registers are defined for this chip.
1959 */
1960 len = DIV_ROUND_UP(SH_ETH_REG_DUMP_MAX_REGS, 32);
1961 if (buf) {
1962 valid_map = buf;
1963 buf += len;
1964 } else {
1965 valid_map = NULL;
1966 }
1967
1968 /* Add a register to the dump, if it has a defined offset.
1969 * This automatically skips most undefined registers, but for
1970 * some it is also necessary to check a capability flag in
1971 * struct sh_eth_cpu_data.
1972 */
1973#define mark_reg_valid(reg) valid_map[reg / 32] |= 1U << (reg % 32)
1974#define add_reg_from(reg, read_expr) do { \
1975 if (mdp->reg_offset[reg] != SH_ETH_OFFSET_INVALID) { \
1976 if (buf) { \
1977 mark_reg_valid(reg); \
1978 *buf++ = read_expr; \
1979 } \
1980 ++len; \
1981 } \
1982 } while (0)
1983#define add_reg(reg) add_reg_from(reg, sh_eth_read(ndev, reg))
1984#define add_tsu_reg(reg) add_reg_from(reg, sh_eth_tsu_read(mdp, reg))
1985
1986 add_reg(EDSR);
1987 add_reg(EDMR);
1988 add_reg(EDTRR);
1989 add_reg(EDRRR);
1990 add_reg(EESR);
1991 add_reg(EESIPR);
1992 add_reg(TDLAR);
1993 add_reg(TDFAR);
1994 add_reg(TDFXR);
1995 add_reg(TDFFR);
1996 add_reg(RDLAR);
1997 add_reg(RDFAR);
1998 add_reg(RDFXR);
1999 add_reg(RDFFR);
2000 add_reg(TRSCER);
2001 add_reg(RMFCR);
2002 add_reg(TFTR);
2003 add_reg(FDR);
2004 add_reg(RMCR);
2005 add_reg(TFUCR);
2006 add_reg(RFOCR);
2007 if (cd->rmiimode)
2008 add_reg(RMIIMODE);
2009 add_reg(FCFTR);
2010 if (cd->rpadir)
2011 add_reg(RPADIR);
2012 if (!cd->no_trimd)
2013 add_reg(TRIMD);
2014 add_reg(ECMR);
2015 add_reg(ECSR);
2016 add_reg(ECSIPR);
2017 add_reg(PIR);
2018 if (!cd->no_psr)
2019 add_reg(PSR);
2020 add_reg(RDMLR);
2021 add_reg(RFLR);
2022 add_reg(IPGR);
2023 if (cd->apr)
2024 add_reg(APR);
2025 if (cd->mpr)
2026 add_reg(MPR);
2027 add_reg(RFCR);
2028 add_reg(RFCF);
2029 if (cd->tpauser)
2030 add_reg(TPAUSER);
2031 add_reg(TPAUSECR);
2032 add_reg(GECMR);
2033 if (cd->bculr)
2034 add_reg(BCULR);
2035 add_reg(MAHR);
2036 add_reg(MALR);
2037 add_reg(TROCR);
2038 add_reg(CDCR);
2039 add_reg(LCCR);
2040 add_reg(CNDCR);
2041 add_reg(CEFCR);
2042 add_reg(FRECR);
2043 add_reg(TSFRCR);
2044 add_reg(TLFRCR);
2045 add_reg(CERCR);
2046 add_reg(CEECR);
2047 add_reg(MAFCR);
2048 if (cd->rtrate)
2049 add_reg(RTRATE);
2050 if (cd->hw_crc)
2051 add_reg(CSMR);
2052 if (cd->select_mii)
2053 add_reg(RMII_MII);
2054 add_reg(ARSTR);
2055 if (cd->tsu) {
2056 add_tsu_reg(TSU_CTRST);
2057 add_tsu_reg(TSU_FWEN0);
2058 add_tsu_reg(TSU_FWEN1);
2059 add_tsu_reg(TSU_FCM);
2060 add_tsu_reg(TSU_BSYSL0);
2061 add_tsu_reg(TSU_BSYSL1);
2062 add_tsu_reg(TSU_PRISL0);
2063 add_tsu_reg(TSU_PRISL1);
2064 add_tsu_reg(TSU_FWSL0);
2065 add_tsu_reg(TSU_FWSL1);
2066 add_tsu_reg(TSU_FWSLC);
2067 add_tsu_reg(TSU_QTAG0);
2068 add_tsu_reg(TSU_QTAG1);
2069 add_tsu_reg(TSU_QTAGM0);
2070 add_tsu_reg(TSU_QTAGM1);
2071 add_tsu_reg(TSU_FWSR);
2072 add_tsu_reg(TSU_FWINMK);
2073 add_tsu_reg(TSU_ADQT0);
2074 add_tsu_reg(TSU_ADQT1);
2075 add_tsu_reg(TSU_VTAG0);
2076 add_tsu_reg(TSU_VTAG1);
2077 add_tsu_reg(TSU_ADSBSY);
2078 add_tsu_reg(TSU_TEN);
2079 add_tsu_reg(TSU_POST1);
2080 add_tsu_reg(TSU_POST2);
2081 add_tsu_reg(TSU_POST3);
2082 add_tsu_reg(TSU_POST4);
2083 if (mdp->reg_offset[TSU_ADRH0] != SH_ETH_OFFSET_INVALID) {
2084 /* This is the start of a table, not just a single
2085 * register.
2086 */
2087 if (buf) {
2088 unsigned int i;
2089
2090 mark_reg_valid(TSU_ADRH0);
2091 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES * 2; i++)
2092 *buf++ = ioread32(
2093 mdp->tsu_addr +
2094 mdp->reg_offset[TSU_ADRH0] +
2095 i * 4);
2096 }
2097 len += SH_ETH_TSU_CAM_ENTRIES * 2;
2098 }
2099 }
2100
2101#undef mark_reg_valid
2102#undef add_reg_from
2103#undef add_reg
2104#undef add_tsu_reg
2105
2106 return len * 4;
2107}
2108
2109static int sh_eth_get_regs_len(struct net_device *ndev)
2110{
2111 return __sh_eth_get_regs(ndev, NULL);
2112}
2113
2114static void sh_eth_get_regs(struct net_device *ndev, struct ethtool_regs *regs,
2115 void *buf)
2116{
2117 struct sh_eth_private *mdp = netdev_priv(ndev);
2118
2119 regs->version = SH_ETH_REG_DUMP_VERSION;
2120
2121 pm_runtime_get_sync(&mdp->pdev->dev);
2122 __sh_eth_get_regs(ndev, buf);
2123 pm_runtime_put_sync(&mdp->pdev->dev);
2124}
2125
dc19e4e5
NI		 2126static int sh_eth_nway_reset(struct net_device *ndev)
2127{
2128 struct sh_eth_private *mdp = netdev_priv(ndev);
2129 unsigned long flags;
2130 int ret;
2131
4f9dce23
BH		 2132 if (!mdp->phydev)
2133 return -ENODEV;
2134
dc19e4e5
NI		 2135 spin_lock_irqsave(&mdp->lock, flags);
2136 ret = phy_start_aneg(mdp->phydev);
2137 spin_unlock_irqrestore(&mdp->lock, flags);
2138
2139 return ret;
2140}
2141
2142static u32 sh_eth_get_msglevel(struct net_device *ndev)
2143{
2144 struct sh_eth_private *mdp = netdev_priv(ndev);
2145 return mdp->msg_enable;
2146}
2147
2148static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
2149{
2150 struct sh_eth_private *mdp = netdev_priv(ndev);
2151 mdp->msg_enable = value;
2152}
2153
2154static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
2155 "rx_current", "tx_current",
2156 "rx_dirty", "tx_dirty",
2157};
2158#define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats)
2159
2160static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
2161{
2162 switch (sset) {
2163 case ETH_SS_STATS:
2164 return SH_ETH_STATS_LEN;
2165 default:
2166 return -EOPNOTSUPP;
2167 }
2168}
2169
2170static void sh_eth_get_ethtool_stats(struct net_device *ndev,
128296fc 2171 struct ethtool_stats *stats, u64 *data)
dc19e4e5
NI		 2172{
2173 struct sh_eth_private *mdp = netdev_priv(ndev);
2174 int i = 0;
2175
2176 /* device-specific stats */
2177 data[i++] = mdp->cur_rx;
2178 data[i++] = mdp->cur_tx;
2179 data[i++] = mdp->dirty_rx;
2180 data[i++] = mdp->dirty_tx;
2181}
2182
2183static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
2184{
2185 switch (stringset) {
2186 case ETH_SS_STATS:
2187 memcpy(data, *sh_eth_gstrings_stats,
128296fc 2188 sizeof(sh_eth_gstrings_stats));
dc19e4e5
NI		 2189 break;
2190 }
2191}
2192
525b8075
YS		 2193static void sh_eth_get_ringparam(struct net_device *ndev,
2194 struct ethtool_ringparam *ring)
2195{
2196 struct sh_eth_private *mdp = netdev_priv(ndev);
2197
2198 ring->rx_max_pending = RX_RING_MAX;
2199 ring->tx_max_pending = TX_RING_MAX;
2200 ring->rx_pending = mdp->num_rx_ring;
2201 ring->tx_pending = mdp->num_tx_ring;
2202}
2203
2204static int sh_eth_set_ringparam(struct net_device *ndev,
2205 struct ethtool_ringparam *ring)
2206{
2207 struct sh_eth_private *mdp = netdev_priv(ndev);
2208 int ret;
2209
2210 if (ring->tx_pending > TX_RING_MAX ||
2211 ring->rx_pending > RX_RING_MAX ||
2212 ring->tx_pending < TX_RING_MIN ||
2213 ring->rx_pending < RX_RING_MIN)
2214 return -EINVAL;
2215 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
2216 return -EINVAL;
2217
2218 if (netif_running(ndev)) {
bd888916 2219 netif_device_detach(ndev);
525b8075 2220 netif_tx_disable(ndev);
283e38db
BH		 2221
2222 /* Serialise with the interrupt handler and NAPI, then
2223 * disable interrupts. We have to clear the
2224 * irq_enabled flag first to ensure that interrupts
2225 * won't be re-enabled.
2226 */
2227 mdp->irq_enabled = false;
525b8075 2228 synchronize_irq(ndev->irq);
283e38db 2229 napi_synchronize(&mdp->napi);
525b8075 2230 sh_eth_write(ndev, 0x0000, EESIPR);
525b8075 2231
740c7f31 2232 sh_eth_dev_exit(ndev);
525b8075 2233
084236d8
BH		 2234 /* Free all the skbuffs in the Rx queue. */
2235 sh_eth_ring_free(ndev);
2236 /* Free DMA buffer */
2237 sh_eth_free_dma_buffer(mdp);
2238 }
525b8075
YS		 2239
2240 /* Set new parameters */
2241 mdp->num_rx_ring = ring->rx_pending;
2242 mdp->num_tx_ring = ring->tx_pending;
2243
525b8075 2244 if (netif_running(ndev)) {
084236d8
BH		 2245 ret = sh_eth_ring_init(ndev);
2246 if (ret < 0) {
2247 netdev_err(ndev, "%s: sh_eth_ring_init failed.\n",
2248 __func__);
2249 return ret;
2250 }
2251 ret = sh_eth_dev_init(ndev, false);
2252 if (ret < 0) {
2253 netdev_err(ndev, "%s: sh_eth_dev_init failed.\n",
2254 __func__);
2255 return ret;
2256 }
2257
283e38db 2258 mdp->irq_enabled = true;
525b8075
YS		 2259 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
2260 /* Setting the Rx mode will start the Rx process. */
2261 sh_eth_write(ndev, EDRRR_R, EDRRR);
bd888916 2262 netif_device_attach(ndev);
525b8075
YS		 2263 }
2264
2265 return 0;
2266}
2267
9b07be4b 2268static const struct ethtool_ops sh_eth_ethtool_ops = {
dc19e4e5
NI		 2269 .get_settings = sh_eth_get_settings,
2270 .set_settings = sh_eth_set_settings,
6b4b4fea
BH		 2271 .get_regs_len = sh_eth_get_regs_len,
2272 .get_regs = sh_eth_get_regs,
9b07be4b 2273 .nway_reset = sh_eth_nway_reset,
dc19e4e5
NI		 2274 .get_msglevel = sh_eth_get_msglevel,
2275 .set_msglevel = sh_eth_set_msglevel,
9b07be4b 2276 .get_link = ethtool_op_get_link,
dc19e4e5
NI		 2277 .get_strings = sh_eth_get_strings,
2278 .get_ethtool_stats = sh_eth_get_ethtool_stats,
2279 .get_sset_count = sh_eth_get_sset_count,
525b8075
YS		 2280 .get_ringparam = sh_eth_get_ringparam,
2281 .set_ringparam = sh_eth_set_ringparam,
dc19e4e5
NI		 2282};
2283
86a74ff2
NI		 2284/* network device open function */
2285static int sh_eth_open(struct net_device *ndev)
2286{
2287 int ret = 0;
2288 struct sh_eth_private *mdp = netdev_priv(ndev);
2289
bcd5149d
MD		 2290 pm_runtime_get_sync(&mdp->pdev->dev);
2291
d2779e99
SS		 2292 napi_enable(&mdp->napi);
2293
a0607fd3 2294 ret = request_irq(ndev->irq, sh_eth_interrupt,
5b3dfd13 2295 mdp->cd->irq_flags, ndev->name, ndev);
86a74ff2 2296 if (ret) {
da246855 2297 netdev_err(ndev, "Can not assign IRQ number\n");
d2779e99 2298 goto out_napi_off;
86a74ff2
NI		 2299 }
2300
2301 /* Descriptor set */
2302 ret = sh_eth_ring_init(ndev);
2303 if (ret)
2304 goto out_free_irq;
2305
2306 /* device init */
525b8075 2307 ret = sh_eth_dev_init(ndev, true);
86a74ff2
NI		 2308 if (ret)
2309 goto out_free_irq;
2310
2311 /* PHY control start*/
2312 ret = sh_eth_phy_start(ndev);
2313 if (ret)
2314 goto out_free_irq;
2315
7fa2955f
MK		 2316 mdp->is_opened = 1;
2317
86a74ff2
NI		 2318 return ret;
2319
2320out_free_irq:
2321 free_irq(ndev->irq, ndev);
d2779e99
SS		 2322out_napi_off:
2323 napi_disable(&mdp->napi);
bcd5149d 2324 pm_runtime_put_sync(&mdp->pdev->dev);
86a74ff2
NI		 2325 return ret;
2326}
2327
2328/* Timeout function */
2329static void sh_eth_tx_timeout(struct net_device *ndev)
2330{
2331 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 2332 struct sh_eth_rxdesc *rxdesc;
2333 int i;
2334
2335 netif_stop_queue(ndev);
2336
8d5009f6
SS		 2337 netif_err(mdp, timer, ndev,
2338 "transmit timed out, status %8.8x, resetting...\n",
0799c2d6 2339 sh_eth_read(ndev, EESR));
86a74ff2
NI		 2340
2341 /* tx_errors count up */
bb7d92e3 2342 ndev->stats.tx_errors++;
86a74ff2 2343
86a74ff2 2344 /* Free all the skbuffs in the Rx queue. */
525b8075 2345 for (i = 0; i < mdp->num_rx_ring; i++) {
86a74ff2
NI		 2346 rxdesc = &mdp->rx_ring[i];
2347 rxdesc->status = 0;
2348 rxdesc->addr = 0xBADF00D0;
179d80af 2349 dev_kfree_skb(mdp->rx_skbuff[i]);
86a74ff2
NI		 2350 mdp->rx_skbuff[i] = NULL;
2351 }
525b8075 2352 for (i = 0; i < mdp->num_tx_ring; i++) {
179d80af 2353 dev_kfree_skb(mdp->tx_skbuff[i]);
86a74ff2
NI		 2354 mdp->tx_skbuff[i] = NULL;
2355 }
2356
2357 /* device init */
525b8075 2358 sh_eth_dev_init(ndev, true);
86a74ff2
NI		 2359}
2360
2361/* Packet transmit function */
2362static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
2363{
2364 struct sh_eth_private *mdp = netdev_priv(ndev);
2365 struct sh_eth_txdesc *txdesc;
2366 u32 entry;
fb5e2f9b 2367 unsigned long flags;
86a74ff2
NI		 2368
2369 spin_lock_irqsave(&mdp->lock, flags);
525b8075 2370 if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
86a74ff2 2371 if (!sh_eth_txfree(ndev)) {
8d5009f6 2372 netif_warn(mdp, tx_queued, ndev, "TxFD exhausted.\n");
86a74ff2
NI		 2373 netif_stop_queue(ndev);
2374 spin_unlock_irqrestore(&mdp->lock, flags);
5b548140 2375 return NETDEV_TX_BUSY;
86a74ff2
NI		 2376 }
2377 }
2378 spin_unlock_irqrestore(&mdp->lock, flags);
2379
dacc73e0 2380 if (skb_put_padto(skb, ETH_ZLEN))
eebfb643
BH		 2381 return NETDEV_TX_OK;
2382
525b8075 2383 entry = mdp->cur_tx % mdp->num_tx_ring;
86a74ff2
NI		 2384 mdp->tx_skbuff[entry] = skb;
2385 txdesc = &mdp->tx_ring[entry];
86a74ff2 2386 /* soft swap. */
380af9e3
YS		 2387 if (!mdp->cd->hw_swap)
2388 sh_eth_soft_swap(phys_to_virt(ALIGN(txdesc->addr, 4)),
2389 skb->len + 2);
31fcb99d
YS		 2390 txdesc->addr = dma_map_single(&ndev->dev, skb->data, skb->len,
2391 DMA_TO_DEVICE);
aa3933b8
BH		 2392 if (dma_mapping_error(&ndev->dev, txdesc->addr)) {
2393 kfree_skb(skb);
2394 return NETDEV_TX_OK;
2395 }
eebfb643 2396 txdesc->buffer_length = skb->len;
86a74ff2 2397
f32bfb9a 2398 dma_wmb(); /* TACT bit must be set after all the above writes */
525b8075 2399 if (entry >= mdp->num_tx_ring - 1)
71557a37 2400 txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE);
86a74ff2 2401 else
71557a37 2402 txdesc->status |= cpu_to_edmac(mdp, TD_TACT);
86a74ff2
NI		 2403
2404 mdp->cur_tx++;
2405
c5ed5368
YS		 2406 if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
2407 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
b0ca2a21 2408
6ed10654 2409 return NETDEV_TX_OK;
86a74ff2
NI		 2410}
2411
4398f9c8
BH		 2412/* The statistics registers have write-clear behaviour, which means we
2413 * will lose any increment between the read and write. We mitigate
2414 * this by only clearing when we read a non-zero value, so we will
2415 * never falsely report a total of zero.
2416 */
2417static void
2418sh_eth_update_stat(struct net_device *ndev, unsigned long *stat, int reg)
2419{
2420 u32 delta = sh_eth_read(ndev, reg);
2421
2422 if (delta) {
2423 *stat += delta;
2424 sh_eth_write(ndev, 0, reg);
2425 }
2426}
2427
7fa2955f
MK		 2428static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
2429{
2430 struct sh_eth_private *mdp = netdev_priv(ndev);
2431
2432 if (sh_eth_is_rz_fast_ether(mdp))
2433 return &ndev->stats;
2434
2435 if (!mdp->is_opened)
2436 return &ndev->stats;
2437
4398f9c8
BH		 2438 sh_eth_update_stat(ndev, &ndev->stats.tx_dropped, TROCR);
2439 sh_eth_update_stat(ndev, &ndev->stats.collisions, CDCR);
2440 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, LCCR);
7fa2955f
MK		 2441
2442 if (sh_eth_is_gether(mdp)) {
4398f9c8
BH		 2443 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2444 CERCR);
2445 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2446 CEECR);
7fa2955f 2447 } else {
4398f9c8
BH		 2448 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2449 CNDCR);
7fa2955f
MK		 2450 }
2451
2452 return &ndev->stats;
2453}
2454
86a74ff2
NI		 2455/* device close function */
2456static int sh_eth_close(struct net_device *ndev)
2457{
2458 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 2459
2460 netif_stop_queue(ndev);
2461
283e38db
BH		 2462 /* Serialise with the interrupt handler and NAPI, then disable
2463 * interrupts. We have to clear the irq_enabled flag first to
2464 * ensure that interrupts won't be re-enabled.
2465 */
2466 mdp->irq_enabled = false;
2467 synchronize_irq(ndev->irq);
2468 napi_disable(&mdp->napi);
4a55530f 2469 sh_eth_write(ndev, 0x0000, EESIPR);
86a74ff2 2470
740c7f31 2471 sh_eth_dev_exit(ndev);
86a74ff2
NI		 2472
2473 /* PHY Disconnect */
2474 if (mdp->phydev) {
2475 phy_stop(mdp->phydev);
2476 phy_disconnect(mdp->phydev);
4f9dce23 2477 mdp->phydev = NULL;
86a74ff2
NI		 2478 }
2479
2480 free_irq(ndev->irq, ndev);
2481
86a74ff2
NI		 2482 /* Free all the skbuffs in the Rx queue. */
2483 sh_eth_ring_free(ndev);
2484
2485 /* free DMA buffer */
91c77550 2486 sh_eth_free_dma_buffer(mdp);
86a74ff2 2487
bcd5149d
MD		 2488 pm_runtime_put_sync(&mdp->pdev->dev);
2489
7fa2955f 2490 mdp->is_opened = 0;
bcd5149d 2491
7fa2955f 2492 return 0;
86a74ff2
NI		 2493}
2494
bb7d92e3 2495/* ioctl to device function */
128296fc 2496static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
86a74ff2
NI		 2497{
2498 struct sh_eth_private *mdp = netdev_priv(ndev);
2499 struct phy_device *phydev = mdp->phydev;
2500
2501 if (!netif_running(ndev))
2502 return -EINVAL;
2503
2504 if (!phydev)
2505 return -ENODEV;
2506
28b04113 2507 return phy_mii_ioctl(phydev, rq, cmd);
86a74ff2
NI		 2508}
2509
6743fe6d
YS		 2510/* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
2511static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp,
2512 int entry)
2513{
2514 return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4);
2515}
2516
2517static u32 sh_eth_tsu_get_post_mask(int entry)
2518{
2519 return 0x0f << (28 - ((entry % 8) * 4));
2520}
2521
2522static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
2523{
2524 return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
2525}
2526
2527static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
2528 int entry)
2529{
2530 struct sh_eth_private *mdp = netdev_priv(ndev);
2531 u32 tmp;
2532 void *reg_offset;
2533
2534 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2535 tmp = ioread32(reg_offset);
2536 iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset);
2537}
2538
2539static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
2540 int entry)
2541{
2542 struct sh_eth_private *mdp = netdev_priv(ndev);
2543 u32 post_mask, ref_mask, tmp;
2544 void *reg_offset;
2545
2546 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2547 post_mask = sh_eth_tsu_get_post_mask(entry);
2548 ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
2549
2550 tmp = ioread32(reg_offset);
2551 iowrite32(tmp & ~post_mask, reg_offset);
2552
2553 /* If other port enables, the function returns "true" */
2554 return tmp & ref_mask;
2555}
2556
2557static int sh_eth_tsu_busy(struct net_device *ndev)
2558{
2559 int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
2560 struct sh_eth_private *mdp = netdev_priv(ndev);
2561
2562 while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
2563 udelay(10);
2564 timeout--;
2565 if (timeout <= 0) {
da246855 2566 netdev_err(ndev, "%s: timeout\n", __func__);
6743fe6d
YS		 2567 return -ETIMEDOUT;
2568 }
2569 }
2570
2571 return 0;
2572}
2573
2574static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg,
2575 const u8 *addr)
2576{
2577 u32 val;
2578
2579 val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
2580 iowrite32(val, reg);
2581 if (sh_eth_tsu_busy(ndev) < 0)
2582 return -EBUSY;
2583
2584 val = addr[4] << 8 | addr[5];
2585 iowrite32(val, reg + 4);
2586 if (sh_eth_tsu_busy(ndev) < 0)
2587 return -EBUSY;
2588
2589 return 0;
2590}
2591
2592static void sh_eth_tsu_read_entry(void *reg, u8 *addr)
2593{
2594 u32 val;
2595
2596 val = ioread32(reg);
2597 addr[0] = (val >> 24) & 0xff;
2598 addr[1] = (val >> 16) & 0xff;
2599 addr[2] = (val >> 8) & 0xff;
2600 addr[3] = val & 0xff;
2601 val = ioread32(reg + 4);
2602 addr[4] = (val >> 8) & 0xff;
2603 addr[5] = val & 0xff;
2604}
2605
2606
2607static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
2608{
2609 struct sh_eth_private *mdp = netdev_priv(ndev);
2610 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2611 int i;
2612 u8 c_addr[ETH_ALEN];
2613
2614 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2615 sh_eth_tsu_read_entry(reg_offset, c_addr);
c4bde29c 2616 if (ether_addr_equal(addr, c_addr))
6743fe6d
YS		 2617 return i;
2618 }
2619
2620 return -ENOENT;
2621}
2622
2623static int sh_eth_tsu_find_empty(struct net_device *ndev)
2624{
2625 u8 blank[ETH_ALEN];
2626 int entry;
2627
2628 memset(blank, 0, sizeof(blank));
2629 entry = sh_eth_tsu_find_entry(ndev, blank);
2630 return (entry < 0) ? -ENOMEM : entry;
2631}
2632
2633static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
2634 int entry)
2635{
2636 struct sh_eth_private *mdp = netdev_priv(ndev);
2637 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2638 int ret;
2639 u8 blank[ETH_ALEN];
2640
2641 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
2642 ~(1 << (31 - entry)), TSU_TEN);
2643
2644 memset(blank, 0, sizeof(blank));
2645 ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
2646 if (ret < 0)
2647 return ret;
2648 return 0;
2649}
2650
2651static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
2652{
2653 struct sh_eth_private *mdp = netdev_priv(ndev);
2654 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2655 int i, ret;
2656
2657 if (!mdp->cd->tsu)
2658 return 0;
2659
2660 i = sh_eth_tsu_find_entry(ndev, addr);
2661 if (i < 0) {
2662 /* No entry found, create one */
2663 i = sh_eth_tsu_find_empty(ndev);
2664 if (i < 0)
2665 return -ENOMEM;
2666 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
2667 if (ret < 0)
2668 return ret;
2669
2670 /* Enable the entry */
2671 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
2672 (1 << (31 - i)), TSU_TEN);
2673 }
2674
2675 /* Entry found or created, enable POST */
2676 sh_eth_tsu_enable_cam_entry_post(ndev, i);
2677
2678 return 0;
2679}
2680
2681static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
2682{
2683 struct sh_eth_private *mdp = netdev_priv(ndev);
2684 int i, ret;
2685
2686 if (!mdp->cd->tsu)
2687 return 0;
2688
2689 i = sh_eth_tsu_find_entry(ndev, addr);
2690 if (i) {
2691 /* Entry found */
2692 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2693 goto done;
2694
2695 /* Disable the entry if both ports was disabled */
2696 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2697 if (ret < 0)
2698 return ret;
2699 }
2700done:
2701 return 0;
2702}
2703
2704static int sh_eth_tsu_purge_all(struct net_device *ndev)
2705{
2706 struct sh_eth_private *mdp = netdev_priv(ndev);
2707 int i, ret;
2708
b37feed7 2709 if (!mdp->cd->tsu)
6743fe6d
YS		 2710 return 0;
2711
2712 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
2713 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2714 continue;
2715
2716 /* Disable the entry if both ports was disabled */
2717 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2718 if (ret < 0)
2719 return ret;
2720 }
2721
2722 return 0;
2723}
2724
2725static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
2726{
2727 struct sh_eth_private *mdp = netdev_priv(ndev);
2728 u8 addr[ETH_ALEN];
2729 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2730 int i;
2731
b37feed7 2732 if (!mdp->cd->tsu)
6743fe6d
YS		 2733 return;
2734
2735 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2736 sh_eth_tsu_read_entry(reg_offset, addr);
2737 if (is_multicast_ether_addr(addr))
2738 sh_eth_tsu_del_entry(ndev, addr);
2739 }
2740}
2741
b37feed7
BH		 2742/* Update promiscuous flag and multicast filter */
2743static void sh_eth_set_rx_mode(struct net_device *ndev)
86a74ff2 2744{
6743fe6d
YS		 2745 struct sh_eth_private *mdp = netdev_priv(ndev);
2746 u32 ecmr_bits;
2747 int mcast_all = 0;
2748 unsigned long flags;
2749
2750 spin_lock_irqsave(&mdp->lock, flags);
128296fc 2751 /* Initial condition is MCT = 1, PRM = 0.
6743fe6d
YS		 2752 * Depending on ndev->flags, set PRM or clear MCT
2753 */
b37feed7
BH		 2754 ecmr_bits = sh_eth_read(ndev, ECMR) & ~ECMR_PRM;
2755 if (mdp->cd->tsu)
2756 ecmr_bits |= ECMR_MCT;
6743fe6d
YS		 2757
2758 if (!(ndev->flags & IFF_MULTICAST)) {
2759 sh_eth_tsu_purge_mcast(ndev);
2760 mcast_all = 1;
2761 }
2762 if (ndev->flags & IFF_ALLMULTI) {
2763 sh_eth_tsu_purge_mcast(ndev);
2764 ecmr_bits &= ~ECMR_MCT;
2765 mcast_all = 1;
2766 }
2767
86a74ff2 2768 if (ndev->flags & IFF_PROMISC) {
6743fe6d
YS		 2769 sh_eth_tsu_purge_all(ndev);
2770 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2771 } else if (mdp->cd->tsu) {
2772 struct netdev_hw_addr *ha;
2773 netdev_for_each_mc_addr(ha, ndev) {
2774 if (mcast_all && is_multicast_ether_addr(ha->addr))
2775 continue;
2776
2777 if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2778 if (!mcast_all) {
2779 sh_eth_tsu_purge_mcast(ndev);
2780 ecmr_bits &= ~ECMR_MCT;
2781 mcast_all = 1;
2782 }
2783 }
2784 }
86a74ff2 2785 }
6743fe6d
YS		 2786
2787 /* update the ethernet mode */
2788 sh_eth_write(ndev, ecmr_bits, ECMR);
2789
2790 spin_unlock_irqrestore(&mdp->lock, flags);
86a74ff2 2791}
71cc7c37
YS		 2792
2793static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2794{
2795 if (!mdp->port)
2796 return TSU_VTAG0;
2797 else
2798 return TSU_VTAG1;
2799}
2800
80d5c368
PM		 2801static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
2802 __be16 proto, u16 vid)
71cc7c37
YS		 2803{
2804 struct sh_eth_private *mdp = netdev_priv(ndev);
2805 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2806
2807 if (unlikely(!mdp->cd->tsu))
2808 return -EPERM;
2809
2810 /* No filtering if vid = 0 */
2811 if (!vid)
2812 return 0;
2813
2814 mdp->vlan_num_ids++;
2815
128296fc 2816 /* The controller has one VLAN tag HW filter. So, if the filter is
71cc7c37
YS		 2817 * already enabled, the driver disables it and the filte
2818 */
2819 if (mdp->vlan_num_ids > 1) {
2820 /* disable VLAN filter */
2821 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2822 return 0;
2823 }
2824
2825 sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
2826 vtag_reg_index);
2827
2828 return 0;
2829}
2830
80d5c368
PM		 2831static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
2832 __be16 proto, u16 vid)
71cc7c37
YS		 2833{
2834 struct sh_eth_private *mdp = netdev_priv(ndev);
2835 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2836
2837 if (unlikely(!mdp->cd->tsu))
2838 return -EPERM;
2839
2840 /* No filtering if vid = 0 */
2841 if (!vid)
2842 return 0;
2843
2844 mdp->vlan_num_ids--;
2845 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2846
2847 return 0;
2848}
86a74ff2
NI		 2849
2850/* SuperH's TSU register init function */
4a55530f 2851static void sh_eth_tsu_init(struct sh_eth_private *mdp)
86a74ff2 2852{
db893473
SH		 2853 if (sh_eth_is_rz_fast_ether(mdp)) {
2854 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2855 return;
2856 }
2857
4a55530f
YS		 2858 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */
2859 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */
2860 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */
2861 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
2862 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
2863 sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
2864 sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
2865 sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
2866 sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
2867 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
c5ed5368
YS		 2868 if (sh_eth_is_gether(mdp)) {
2869 sh_eth_tsu_write(mdp, 0, TSU_QTAG0); /* Disable QTAG(0->1) */
2870 sh_eth_tsu_write(mdp, 0, TSU_QTAG1); /* Disable QTAG(1->0) */
2871 } else {
2872 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */
2873 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */
2874 }
4a55530f
YS		 2875 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */
2876 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */
2877 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2878 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */
2879 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */
2880 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */
2881 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */
86a74ff2
NI		 2882}
2883
2884/* MDIO bus release function */
bd920ff5 2885static int sh_mdio_release(struct sh_eth_private *mdp)
86a74ff2 2886{
86a74ff2 2887 /* unregister mdio bus */
bd920ff5 2888 mdiobus_unregister(mdp->mii_bus);
86a74ff2
NI		 2889
2890 /* free bitbang info */
bd920ff5 2891 free_mdio_bitbang(mdp->mii_bus);
86a74ff2
NI		 2892
2893 return 0;
2894}
2895
2896/* MDIO bus init function */
bd920ff5 2897static int sh_mdio_init(struct sh_eth_private *mdp,
b3017e6a 2898 struct sh_eth_plat_data *pd)
86a74ff2
NI		 2899{
2900 int ret, i;
2901 struct bb_info *bitbang;
bd920ff5 2902 struct platform_device *pdev = mdp->pdev;
aa8d4225 2903 struct device *dev = &mdp->pdev->dev;
86a74ff2
NI		 2904
2905 /* create bit control struct for PHY */
aa8d4225 2906 bitbang = devm_kzalloc(dev, sizeof(struct bb_info), GFP_KERNEL);
f738a13d
LP		 2907 if (!bitbang)
2908 return -ENOMEM;
86a74ff2
NI		 2909
2910 /* bitbang init */
ae70644d 2911 bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
b3017e6a 2912 bitbang->set_gate = pd->set_mdio_gate;
dfed5e7f
SS		 2913 bitbang->mdi_msk = PIR_MDI;
2914 bitbang->mdo_msk = PIR_MDO;
2915 bitbang->mmd_msk = PIR_MMD;
2916 bitbang->mdc_msk = PIR_MDC;
86a74ff2
NI		 2917 bitbang->ctrl.ops = &bb_ops;
2918
c2e07b3a 2919 /* MII controller setting */
86a74ff2 2920 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
f738a13d
LP		 2921 if (!mdp->mii_bus)
2922 return -ENOMEM;
86a74ff2
NI		 2923
2924 /* Hook up MII support for ethtool */
2925 mdp->mii_bus->name = "sh_mii";
a5bd6060 2926 mdp->mii_bus->parent = dev;
5278fb54 2927 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
bd920ff5 2928 pdev->name, pdev->id);
86a74ff2
NI		 2929
2930 /* PHY IRQ */
86b5d251
SS		 2931 mdp->mii_bus->irq = devm_kmalloc_array(dev, PHY_MAX_ADDR, sizeof(int),
2932 GFP_KERNEL);
86a74ff2
NI		 2933 if (!mdp->mii_bus->irq) {
2934 ret = -ENOMEM;
2935 goto out_free_bus;
2936 }
2937
bd920ff5
LP		 2938 /* register MDIO bus */
2939 if (dev->of_node) {
2940 ret = of_mdiobus_register(mdp->mii_bus, dev->of_node);
702eca02
BD		 2941 } else {
2942 for (i = 0; i < PHY_MAX_ADDR; i++)
2943 mdp->mii_bus->irq[i] = PHY_POLL;
2944 if (pd->phy_irq > 0)
2945 mdp->mii_bus->irq[pd->phy] = pd->phy_irq;
2946
2947 ret = mdiobus_register(mdp->mii_bus);
2948 }
2949
86a74ff2 2950 if (ret)
d5e07e69 2951 goto out_free_bus;
86a74ff2 2952
86a74ff2
NI		 2953 return 0;
2954
86a74ff2 2955out_free_bus:
298cf9be 2956 free_mdio_bitbang(mdp->mii_bus);
86a74ff2
NI		 2957 return ret;
2958}
2959
4a55530f
YS		 2960static const u16 *sh_eth_get_register_offset(int register_type)
2961{
2962 const u16 *reg_offset = NULL;
2963
2964 switch (register_type) {
2965 case SH_ETH_REG_GIGABIT:
2966 reg_offset = sh_eth_offset_gigabit;
2967 break;
db893473
SH		 2968 case SH_ETH_REG_FAST_RZ:
2969 reg_offset = sh_eth_offset_fast_rz;
2970 break;
a3f109bd
SS		 2971 case SH_ETH_REG_FAST_RCAR:
2972 reg_offset = sh_eth_offset_fast_rcar;
2973 break;
4a55530f
YS		 2974 case SH_ETH_REG_FAST_SH4:
2975 reg_offset = sh_eth_offset_fast_sh4;
2976 break;
2977 case SH_ETH_REG_FAST_SH3_SH2:
2978 reg_offset = sh_eth_offset_fast_sh3_sh2;
2979 break;
2980 default:
4a55530f
YS		 2981 break;
2982 }
2983
2984 return reg_offset;
2985}
2986
8f728d79 2987static const struct net_device_ops sh_eth_netdev_ops = {
ebf84eaa
AB		 2988 .ndo_open = sh_eth_open,
2989 .ndo_stop = sh_eth_close,
2990 .ndo_start_xmit = sh_eth_start_xmit,
2991 .ndo_get_stats = sh_eth_get_stats,
b37feed7 2992 .ndo_set_rx_mode = sh_eth_set_rx_mode,
ebf84eaa
AB		 2993 .ndo_tx_timeout = sh_eth_tx_timeout,
2994 .ndo_do_ioctl = sh_eth_do_ioctl,
2995 .ndo_validate_addr = eth_validate_addr,
2996 .ndo_set_mac_address = eth_mac_addr,
2997 .ndo_change_mtu = eth_change_mtu,
2998};
2999
8f728d79
SS		 3000static const struct net_device_ops sh_eth_netdev_ops_tsu = {
3001 .ndo_open = sh_eth_open,
3002 .ndo_stop = sh_eth_close,
3003 .ndo_start_xmit = sh_eth_start_xmit,
3004 .ndo_get_stats = sh_eth_get_stats,
b37feed7 3005 .ndo_set_rx_mode = sh_eth_set_rx_mode,
8f728d79
SS		 3006 .ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid,
3007 .ndo_vlan_rx_kill_vid = sh_eth_vlan_rx_kill_vid,
3008 .ndo_tx_timeout = sh_eth_tx_timeout,
3009 .ndo_do_ioctl = sh_eth_do_ioctl,
3010 .ndo_validate_addr = eth_validate_addr,
3011 .ndo_set_mac_address = eth_mac_addr,
3012 .ndo_change_mtu = eth_change_mtu,
3013};
3014
b356e978
SS		 3015#ifdef CONFIG_OF
3016static struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
3017{
3018 struct device_node *np = dev->of_node;
3019 struct sh_eth_plat_data *pdata;
b356e978
SS		 3020 const char *mac_addr;
3021
3022 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
3023 if (!pdata)
3024 return NULL;
3025
3026 pdata->phy_interface = of_get_phy_mode(np);
3027
b356e978
SS		 3028 mac_addr = of_get_mac_address(np);
3029 if (mac_addr)
3030 memcpy(pdata->mac_addr, mac_addr, ETH_ALEN);
3031
3032 pdata->no_ether_link =
3033 of_property_read_bool(np, "renesas,no-ether-link");
3034 pdata->ether_link_active_low =
3035 of_property_read_bool(np, "renesas,ether-link-active-low");
3036
3037 return pdata;
3038}
3039
3040static const struct of_device_id sh_eth_match_table[] = {
3041 { .compatible = "renesas,gether-r8a7740", .data = &r8a7740_data },
3042 { .compatible = "renesas,ether-r8a7778", .data = &r8a777x_data },
3043 { .compatible = "renesas,ether-r8a7779", .data = &r8a777x_data },
3044 { .compatible = "renesas,ether-r8a7790", .data = &r8a779x_data },
3045 { .compatible = "renesas,ether-r8a7791", .data = &r8a779x_data },
9488e1e5 3046 { .compatible = "renesas,ether-r8a7793", .data = &r8a779x_data },
0f76b9d8 3047 { .compatible = "renesas,ether-r8a7794", .data = &r8a779x_data },
b356e978
SS		 3048 { .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data },
3049 { }
3050};
3051MODULE_DEVICE_TABLE(of, sh_eth_match_table);
3052#else
3053static inline struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
3054{
3055 return NULL;
3056}
3057#endif
3058
86a74ff2
NI		 3059static int sh_eth_drv_probe(struct platform_device *pdev)
3060{
9c38657c 3061 int ret, devno = 0;
86a74ff2
NI		 3062 struct resource *res;
3063 struct net_device *ndev = NULL;
ec0d7551 3064 struct sh_eth_private *mdp = NULL;
0b76b862 3065 struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev);
afe391ad 3066 const struct platform_device_id *id = platform_get_device_id(pdev);
86a74ff2
NI		 3067
3068 /* get base addr */
3069 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
86a74ff2
NI		 3070
3071 ndev = alloc_etherdev(sizeof(struct sh_eth_private));
f738a13d
LP		 3072 if (!ndev)
3073 return -ENOMEM;
86a74ff2 3074
b5893a08
BD		 3075 pm_runtime_enable(&pdev->dev);
3076 pm_runtime_get_sync(&pdev->dev);
3077
86a74ff2
NI		 3078 devno = pdev->id;
3079 if (devno < 0)
3080 devno = 0;
3081
3082 ndev->dma = -1;
cc3c080d 3083 ret = platform_get_irq(pdev, 0);
7a468ac6 3084 if (ret < 0)
86a74ff2 3085 goto out_release;
cc3c080d 3086 ndev->irq = ret;
86a74ff2
NI		 3087
3088 SET_NETDEV_DEV(ndev, &pdev->dev);
3089
86a74ff2 3090 mdp = netdev_priv(ndev);
525b8075
YS		 3091 mdp->num_tx_ring = TX_RING_SIZE;
3092 mdp->num_rx_ring = RX_RING_SIZE;
d5e07e69
SS		 3093 mdp->addr = devm_ioremap_resource(&pdev->dev, res);
3094 if (IS_ERR(mdp->addr)) {
3095 ret = PTR_ERR(mdp->addr);
ae70644d
YS		 3096 goto out_release;
3097 }
3098
c960804f
VB		 3099 ndev->base_addr = res->start;
3100
86a74ff2 3101 spin_lock_init(&mdp->lock);
bcd5149d 3102 mdp->pdev = pdev;
86a74ff2 3103
b356e978
SS		 3104 if (pdev->dev.of_node)
3105 pd = sh_eth_parse_dt(&pdev->dev);
3b4c5cbf
SS		 3106 if (!pd) {
3107 dev_err(&pdev->dev, "no platform data\n");
3108 ret = -EINVAL;
3109 goto out_release;
3110 }
3111
86a74ff2 3112 /* get PHY ID */
71557a37 3113 mdp->phy_id = pd->phy;
e47c9052 3114 mdp->phy_interface = pd->phy_interface;
71557a37
YS		 3115 /* EDMAC endian */
3116 mdp->edmac_endian = pd->edmac_endian;
4923576b
YS		 3117 mdp->no_ether_link = pd->no_ether_link;
3118 mdp->ether_link_active_low = pd->ether_link_active_low;
86a74ff2 3119
380af9e3 3120 /* set cpu data */
b356e978
SS		 3121 if (id) {
3122 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data;
3123 } else {
3124 const struct of_device_id *match;
3125
3126 match = of_match_device(of_match_ptr(sh_eth_match_table),
3127 &pdev->dev);
3128 mdp->cd = (struct sh_eth_cpu_data *)match->data;
3129 }
a3153d8c 3130 mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type);
264be2f5
SS		 3131 if (!mdp->reg_offset) {
3132 dev_err(&pdev->dev, "Unknown register type (%d)\n",
3133 mdp->cd->register_type);
3134 ret = -EINVAL;
3135 goto out_release;
3136 }
380af9e3
YS		 3137 sh_eth_set_default_cpu_data(mdp->cd);
3138
86a74ff2 3139 /* set function */
8f728d79
SS		 3140 if (mdp->cd->tsu)
3141 ndev->netdev_ops = &sh_eth_netdev_ops_tsu;
3142 else
3143 ndev->netdev_ops = &sh_eth_netdev_ops;
7ad24ea4 3144 ndev->ethtool_ops = &sh_eth_ethtool_ops;
86a74ff2
NI		 3145 ndev->watchdog_timeo = TX_TIMEOUT;
3146
dc19e4e5
NI		 3147 /* debug message level */
3148 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
86a74ff2
NI		 3149
3150 /* read and set MAC address */
748031f9 3151 read_mac_address(ndev, pd->mac_addr);
ff6e7228
SS		 3152 if (!is_valid_ether_addr(ndev->dev_addr)) {
3153 dev_warn(&pdev->dev,
3154 "no valid MAC address supplied, using a random one.\n");
3155 eth_hw_addr_random(ndev);
3156 }
86a74ff2 3157
6ba88021
YS		 3158 /* ioremap the TSU registers */
3159 if (mdp->cd->tsu) {
3160 struct resource *rtsu;
3161 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
d5e07e69
SS		 3162 mdp->tsu_addr = devm_ioremap_resource(&pdev->dev, rtsu);
3163 if (IS_ERR(mdp->tsu_addr)) {
3164 ret = PTR_ERR(mdp->tsu_addr);
fc0c0900
SS		 3165 goto out_release;
3166 }
6743fe6d 3167 mdp->port = devno % 2;
f646968f 3168 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER;
6ba88021
YS		 3169 }
3170
150647fb
YS		 3171 /* initialize first or needed device */
3172 if (!devno || pd->needs_init) {
380af9e3
YS		 3173 if (mdp->cd->chip_reset)
3174 mdp->cd->chip_reset(ndev);
86a74ff2 3175
4986b996
YS		 3176 if (mdp->cd->tsu) {
3177 /* TSU init (Init only)*/
3178 sh_eth_tsu_init(mdp);
3179 }
86a74ff2
NI		 3180 }
3181
966d6dbb
HN		 3182 if (mdp->cd->rmiimode)
3183 sh_eth_write(ndev, 0x1, RMIIMODE);
3184
daacf03f
LP		 3185 /* MDIO bus init */
3186 ret = sh_mdio_init(mdp, pd);
3187 if (ret) {
3188 dev_err(&ndev->dev, "failed to initialise MDIO\n");
3189 goto out_release;
3190 }
3191
3719109d
SS		 3192 netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64);
3193
86a74ff2
NI		 3194 /* network device register */
3195 ret = register_netdev(ndev);
3196 if (ret)
3719109d 3197 goto out_napi_del;
86a74ff2 3198
25985edc 3199 /* print device information */
f75f14ec
SS		 3200 netdev_info(ndev, "Base address at 0x%x, %pM, IRQ %d.\n",
3201 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
86a74ff2 3202
b5893a08 3203 pm_runtime_put(&pdev->dev);
86a74ff2
NI		 3204 platform_set_drvdata(pdev, ndev);
3205
3206 return ret;
3207
3719109d
SS		 3208out_napi_del:
3209 netif_napi_del(&mdp->napi);
daacf03f 3210 sh_mdio_release(mdp);
3719109d 3211
86a74ff2
NI		 3212out_release:
3213 /* net_dev free */
3214 if (ndev)
3215 free_netdev(ndev);
3216
b5893a08
BD		 3217 pm_runtime_put(&pdev->dev);
3218 pm_runtime_disable(&pdev->dev);
86a74ff2
NI		 3219 return ret;
3220}
3221
3222static int sh_eth_drv_remove(struct platform_device *pdev)
3223{
3224 struct net_device *ndev = platform_get_drvdata(pdev);
3719109d 3225 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2 3226
86a74ff2 3227 unregister_netdev(ndev);
3719109d 3228 netif_napi_del(&mdp->napi);
daacf03f 3229 sh_mdio_release(mdp);
bcd5149d 3230 pm_runtime_disable(&pdev->dev);
86a74ff2 3231 free_netdev(ndev);
86a74ff2
NI		 3232
3233 return 0;
3234}
3235
540ad1b8 3236#ifdef CONFIG_PM
b71af046
MU		 3237#ifdef CONFIG_PM_SLEEP
3238static int sh_eth_suspend(struct device *dev)
3239{
3240 struct net_device *ndev = dev_get_drvdata(dev);
3241 int ret = 0;
3242
3243 if (netif_running(ndev)) {
3244 netif_device_detach(ndev);
3245 ret = sh_eth_close(ndev);
3246 }
3247
3248 return ret;
3249}
3250
3251static int sh_eth_resume(struct device *dev)
3252{
3253 struct net_device *ndev = dev_get_drvdata(dev);
3254 int ret = 0;
3255
3256 if (netif_running(ndev)) {
3257 ret = sh_eth_open(ndev);
3258 if (ret < 0)
3259 return ret;
3260 netif_device_attach(ndev);
3261 }
3262
3263 return ret;
3264}
3265#endif
3266
bcd5149d
MD		 3267static int sh_eth_runtime_nop(struct device *dev)
3268{
128296fc 3269 /* Runtime PM callback shared between ->runtime_suspend()
bcd5149d
MD		 3270 * and ->runtime_resume(). Simply returns success.
3271 *
3272 * This driver re-initializes all registers after
3273 * pm_runtime_get_sync() anyway so there is no need
3274 * to save and restore registers here.
3275 */
3276 return 0;
3277}
3278
540ad1b8 3279static const struct dev_pm_ops sh_eth_dev_pm_ops = {
b71af046 3280 SET_SYSTEM_SLEEP_PM_OPS(sh_eth_suspend, sh_eth_resume)
e7d7e898 3281 SET_RUNTIME_PM_OPS(sh_eth_runtime_nop, sh_eth_runtime_nop, NULL)
bcd5149d 3282};
540ad1b8
NI		 3283#define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
3284#else
3285#define SH_ETH_PM_OPS NULL
3286#endif
bcd5149d 3287
afe391ad 3288static struct platform_device_id sh_eth_id_table[] = {
c18a79ab 3289 { "sh7619-ether", (kernel_ulong_t)&sh7619_data },
7bbe150d 3290 { "sh771x-ether", (kernel_ulong_t)&sh771x_data },
9c3beaab 3291 { "sh7724-ether", (kernel_ulong_t)&sh7724_data },
f5d12767 3292 { "sh7734-gether", (kernel_ulong_t)&sh7734_data },
24549e2a
SS		 3293 { "sh7757-ether", (kernel_ulong_t)&sh7757_data },
3294 { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga },
f5d12767 3295 { "sh7763-gether", (kernel_ulong_t)&sh7763_data },
db893473 3296 { "r7s72100-ether", (kernel_ulong_t)&r7s72100_data },
e5c9b4cd 3297 { "r8a7740-gether", (kernel_ulong_t)&r8a7740_data },
589ebdef 3298 { "r8a777x-ether", (kernel_ulong_t)&r8a777x_data },
94a12b15
SS		 3299 { "r8a7790-ether", (kernel_ulong_t)&r8a779x_data },
3300 { "r8a7791-ether", (kernel_ulong_t)&r8a779x_data },
9488e1e5 3301 { "r8a7793-ether", (kernel_ulong_t)&r8a779x_data },
0f76b9d8 3302 { "r8a7794-ether", (kernel_ulong_t)&r8a779x_data },
afe391ad
SS		 3303 { }
3304};
3305MODULE_DEVICE_TABLE(platform, sh_eth_id_table);
3306
86a74ff2
NI		 3307static struct platform_driver sh_eth_driver = {
3308 .probe = sh_eth_drv_probe,
3309 .remove = sh_eth_drv_remove,
afe391ad 3310 .id_table = sh_eth_id_table,
86a74ff2
NI		 3311 .driver = {
3312 .name = CARDNAME,
540ad1b8 3313 .pm = SH_ETH_PM_OPS,
b356e978 3314 .of_match_table = of_match_ptr(sh_eth_match_table),
86a74ff2
NI		 3315 },
3316};
3317
db62f684 3318module_platform_driver(sh_eth_driver);
86a74ff2
NI		 3319
3320MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
3321MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
3322MODULE_LICENSE("GPL v2");
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