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sh_eth: remove SH_ETH_HAS_TSU
[mirror_ubuntu-zesty-kernel.git] / drivers / net / ethernet / renesas / sh_eth.c
CommitLineData
86a74ff2
NI		 1/*
2 * SuperH Ethernet device driver
3 *
f0e81fec 4 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu
a3f109bd
SS		 5 * Copyright (C) 2008-2013 Renesas Solutions Corp.
6 * Copyright (C) 2013 Cogent Embedded, Inc.
86a74ff2
NI		 7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 * You should have received a copy of the GNU General Public License along with
17 * this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * The full GNU General Public License is included in this distribution in
21 * the file called "COPYING".
22 */
23
86a74ff2 24#include <linux/init.h>
0654011d
YS		 25#include <linux/module.h>
26#include <linux/kernel.h>
27#include <linux/spinlock.h>
6a27cded 28#include <linux/interrupt.h>
86a74ff2
NI		 29#include <linux/dma-mapping.h>
30#include <linux/etherdevice.h>
31#include <linux/delay.h>
32#include <linux/platform_device.h>
33#include <linux/mdio-bitbang.h>
34#include <linux/netdevice.h>
35#include <linux/phy.h>
36#include <linux/cache.h>
37#include <linux/io.h>
bcd5149d 38#include <linux/pm_runtime.h>
5a0e3ad6 39#include <linux/slab.h>
dc19e4e5 40#include <linux/ethtool.h>
fdb37a7f 41#include <linux/if_vlan.h>
f0e81fec 42#include <linux/clk.h>
d4fa0e35 43#include <linux/sh_eth.h>
86a74ff2
NI		 44
45#include "sh_eth.h"
46
dc19e4e5
NI		 47#define SH_ETH_DEF_MSG_ENABLE \
48 (NETIF_MSG_LINK | \
49 NETIF_MSG_TIMER | \
50 NETIF_MSG_RX_ERR| \
51 NETIF_MSG_TX_ERR)
52
c0013f6f
SS		 53static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
54 [EDSR] = 0x0000,
55 [EDMR] = 0x0400,
56 [EDTRR] = 0x0408,
57 [EDRRR] = 0x0410,
58 [EESR] = 0x0428,
59 [EESIPR] = 0x0430,
60 [TDLAR] = 0x0010,
61 [TDFAR] = 0x0014,
62 [TDFXR] = 0x0018,
63 [TDFFR] = 0x001c,
64 [RDLAR] = 0x0030,
65 [RDFAR] = 0x0034,
66 [RDFXR] = 0x0038,
67 [RDFFR] = 0x003c,
68 [TRSCER] = 0x0438,
69 [RMFCR] = 0x0440,
70 [TFTR] = 0x0448,
71 [FDR] = 0x0450,
72 [RMCR] = 0x0458,
73 [RPADIR] = 0x0460,
74 [FCFTR] = 0x0468,
75 [CSMR] = 0x04E4,
76
77 [ECMR] = 0x0500,
78 [ECSR] = 0x0510,
79 [ECSIPR] = 0x0518,
80 [PIR] = 0x0520,
81 [PSR] = 0x0528,
82 [PIPR] = 0x052c,
83 [RFLR] = 0x0508,
84 [APR] = 0x0554,
85 [MPR] = 0x0558,
86 [PFTCR] = 0x055c,
87 [PFRCR] = 0x0560,
88 [TPAUSER] = 0x0564,
89 [GECMR] = 0x05b0,
90 [BCULR] = 0x05b4,
91 [MAHR] = 0x05c0,
92 [MALR] = 0x05c8,
93 [TROCR] = 0x0700,
94 [CDCR] = 0x0708,
95 [LCCR] = 0x0710,
96 [CEFCR] = 0x0740,
97 [FRECR] = 0x0748,
98 [TSFRCR] = 0x0750,
99 [TLFRCR] = 0x0758,
100 [RFCR] = 0x0760,
101 [CERCR] = 0x0768,
102 [CEECR] = 0x0770,
103 [MAFCR] = 0x0778,
104 [RMII_MII] = 0x0790,
105
106 [ARSTR] = 0x0000,
107 [TSU_CTRST] = 0x0004,
108 [TSU_FWEN0] = 0x0010,
109 [TSU_FWEN1] = 0x0014,
110 [TSU_FCM] = 0x0018,
111 [TSU_BSYSL0] = 0x0020,
112 [TSU_BSYSL1] = 0x0024,
113 [TSU_PRISL0] = 0x0028,
114 [TSU_PRISL1] = 0x002c,
115 [TSU_FWSL0] = 0x0030,
116 [TSU_FWSL1] = 0x0034,
117 [TSU_FWSLC] = 0x0038,
118 [TSU_QTAG0] = 0x0040,
119 [TSU_QTAG1] = 0x0044,
120 [TSU_FWSR] = 0x0050,
121 [TSU_FWINMK] = 0x0054,
122 [TSU_ADQT0] = 0x0048,
123 [TSU_ADQT1] = 0x004c,
124 [TSU_VTAG0] = 0x0058,
125 [TSU_VTAG1] = 0x005c,
126 [TSU_ADSBSY] = 0x0060,
127 [TSU_TEN] = 0x0064,
128 [TSU_POST1] = 0x0070,
129 [TSU_POST2] = 0x0074,
130 [TSU_POST3] = 0x0078,
131 [TSU_POST4] = 0x007c,
132 [TSU_ADRH0] = 0x0100,
133 [TSU_ADRL0] = 0x0104,
134 [TSU_ADRH31] = 0x01f8,
135 [TSU_ADRL31] = 0x01fc,
136
137 [TXNLCR0] = 0x0080,
138 [TXALCR0] = 0x0084,
139 [RXNLCR0] = 0x0088,
140 [RXALCR0] = 0x008c,
141 [FWNLCR0] = 0x0090,
142 [FWALCR0] = 0x0094,
143 [TXNLCR1] = 0x00a0,
144 [TXALCR1] = 0x00a0,
145 [RXNLCR1] = 0x00a8,
146 [RXALCR1] = 0x00ac,
147 [FWNLCR1] = 0x00b0,
148 [FWALCR1] = 0x00b4,
149};
150
a3f109bd
SS		 151static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
152 [ECMR] = 0x0300,
153 [RFLR] = 0x0308,
154 [ECSR] = 0x0310,
155 [ECSIPR] = 0x0318,
156 [PIR] = 0x0320,
157 [PSR] = 0x0328,
158 [RDMLR] = 0x0340,
159 [IPGR] = 0x0350,
160 [APR] = 0x0354,
161 [MPR] = 0x0358,
162 [RFCF] = 0x0360,
163 [TPAUSER] = 0x0364,
164 [TPAUSECR] = 0x0368,
165 [MAHR] = 0x03c0,
166 [MALR] = 0x03c8,
167 [TROCR] = 0x03d0,
168 [CDCR] = 0x03d4,
169 [LCCR] = 0x03d8,
170 [CNDCR] = 0x03dc,
171 [CEFCR] = 0x03e4,
172 [FRECR] = 0x03e8,
173 [TSFRCR] = 0x03ec,
174 [TLFRCR] = 0x03f0,
175 [RFCR] = 0x03f4,
176 [MAFCR] = 0x03f8,
177
178 [EDMR] = 0x0200,
179 [EDTRR] = 0x0208,
180 [EDRRR] = 0x0210,
181 [TDLAR] = 0x0218,
182 [RDLAR] = 0x0220,
183 [EESR] = 0x0228,
184 [EESIPR] = 0x0230,
185 [TRSCER] = 0x0238,
186 [RMFCR] = 0x0240,
187 [TFTR] = 0x0248,
188 [FDR] = 0x0250,
189 [RMCR] = 0x0258,
190 [TFUCR] = 0x0264,
191 [RFOCR] = 0x0268,
192 [FCFTR] = 0x0270,
193 [TRIMD] = 0x027c,
194};
195
c0013f6f
SS		 196static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
197 [ECMR] = 0x0100,
198 [RFLR] = 0x0108,
199 [ECSR] = 0x0110,
200 [ECSIPR] = 0x0118,
201 [PIR] = 0x0120,
202 [PSR] = 0x0128,
203 [RDMLR] = 0x0140,
204 [IPGR] = 0x0150,
205 [APR] = 0x0154,
206 [MPR] = 0x0158,
207 [TPAUSER] = 0x0164,
208 [RFCF] = 0x0160,
209 [TPAUSECR] = 0x0168,
210 [BCFRR] = 0x016c,
211 [MAHR] = 0x01c0,
212 [MALR] = 0x01c8,
213 [TROCR] = 0x01d0,
214 [CDCR] = 0x01d4,
215 [LCCR] = 0x01d8,
216 [CNDCR] = 0x01dc,
217 [CEFCR] = 0x01e4,
218 [FRECR] = 0x01e8,
219 [TSFRCR] = 0x01ec,
220 [TLFRCR] = 0x01f0,
221 [RFCR] = 0x01f4,
222 [MAFCR] = 0x01f8,
223 [RTRATE] = 0x01fc,
224
225 [EDMR] = 0x0000,
226 [EDTRR] = 0x0008,
227 [EDRRR] = 0x0010,
228 [TDLAR] = 0x0018,
229 [RDLAR] = 0x0020,
230 [EESR] = 0x0028,
231 [EESIPR] = 0x0030,
232 [TRSCER] = 0x0038,
233 [RMFCR] = 0x0040,
234 [TFTR] = 0x0048,
235 [FDR] = 0x0050,
236 [RMCR] = 0x0058,
237 [TFUCR] = 0x0064,
238 [RFOCR] = 0x0068,
239 [FCFTR] = 0x0070,
240 [RPADIR] = 0x0078,
241 [TRIMD] = 0x007c,
242 [RBWAR] = 0x00c8,
243 [RDFAR] = 0x00cc,
244 [TBRAR] = 0x00d4,
245 [TDFAR] = 0x00d8,
246};
247
248static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
249 [ECMR] = 0x0160,
250 [ECSR] = 0x0164,
251 [ECSIPR] = 0x0168,
252 [PIR] = 0x016c,
253 [MAHR] = 0x0170,
254 [MALR] = 0x0174,
255 [RFLR] = 0x0178,
256 [PSR] = 0x017c,
257 [TROCR] = 0x0180,
258 [CDCR] = 0x0184,
259 [LCCR] = 0x0188,
260 [CNDCR] = 0x018c,
261 [CEFCR] = 0x0194,
262 [FRECR] = 0x0198,
263 [TSFRCR] = 0x019c,
264 [TLFRCR] = 0x01a0,
265 [RFCR] = 0x01a4,
266 [MAFCR] = 0x01a8,
267 [IPGR] = 0x01b4,
268 [APR] = 0x01b8,
269 [MPR] = 0x01bc,
270 [TPAUSER] = 0x01c4,
271 [BCFR] = 0x01cc,
272
273 [ARSTR] = 0x0000,
274 [TSU_CTRST] = 0x0004,
275 [TSU_FWEN0] = 0x0010,
276 [TSU_FWEN1] = 0x0014,
277 [TSU_FCM] = 0x0018,
278 [TSU_BSYSL0] = 0x0020,
279 [TSU_BSYSL1] = 0x0024,
280 [TSU_PRISL0] = 0x0028,
281 [TSU_PRISL1] = 0x002c,
282 [TSU_FWSL0] = 0x0030,
283 [TSU_FWSL1] = 0x0034,
284 [TSU_FWSLC] = 0x0038,
285 [TSU_QTAGM0] = 0x0040,
286 [TSU_QTAGM1] = 0x0044,
287 [TSU_ADQT0] = 0x0048,
288 [TSU_ADQT1] = 0x004c,
289 [TSU_FWSR] = 0x0050,
290 [TSU_FWINMK] = 0x0054,
291 [TSU_ADSBSY] = 0x0060,
292 [TSU_TEN] = 0x0064,
293 [TSU_POST1] = 0x0070,
294 [TSU_POST2] = 0x0074,
295 [TSU_POST3] = 0x0078,
296 [TSU_POST4] = 0x007c,
297
298 [TXNLCR0] = 0x0080,
299 [TXALCR0] = 0x0084,
300 [RXNLCR0] = 0x0088,
301 [RXALCR0] = 0x008c,
302 [FWNLCR0] = 0x0090,
303 [FWALCR0] = 0x0094,
304 [TXNLCR1] = 0x00a0,
305 [TXALCR1] = 0x00a0,
306 [RXNLCR1] = 0x00a8,
307 [RXALCR1] = 0x00ac,
308 [FWNLCR1] = 0x00b0,
309 [FWALCR1] = 0x00b4,
310
311 [TSU_ADRH0] = 0x0100,
312 [TSU_ADRL0] = 0x0104,
313 [TSU_ADRL31] = 0x01fc,
314};
315
5e7a76be
NI		 316#if defined(CONFIG_CPU_SUBTYPE_SH7734) || \
317 defined(CONFIG_CPU_SUBTYPE_SH7763) || \
318 defined(CONFIG_ARCH_R8A7740)
319static void sh_eth_select_mii(struct net_device *ndev)
320{
321 u32 value = 0x0;
322 struct sh_eth_private *mdp = netdev_priv(ndev);
323
324 switch (mdp->phy_interface) {
325 case PHY_INTERFACE_MODE_GMII:
326 value = 0x2;
327 break;
328 case PHY_INTERFACE_MODE_MII:
329 value = 0x1;
330 break;
331 case PHY_INTERFACE_MODE_RMII:
332 value = 0x0;
333 break;
334 default:
335 pr_warn("PHY interface mode was not setup. Set to MII.\n");
336 value = 0x1;
337 break;
338 }
339
340 sh_eth_write(ndev, value, RMII_MII);
341}
342#endif
343
04b0ed2a 344static void __maybe_unused sh_eth_set_duplex(struct net_device *ndev)
65ac8851
YS		 345{
346 struct sh_eth_private *mdp = netdev_priv(ndev);
65ac8851
YS		 347
348 if (mdp->duplex) /* Full */
4a55530f 349 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
65ac8851 350 else /* Half */
4a55530f 351 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
65ac8851
YS		 352}
353
04b0ed2a
NI		 354/* There is CPU dependent code */
355#if defined(CONFIG_ARCH_R8A7778) || defined(CONFIG_ARCH_R8A7779)
356#define SH_ETH_RESET_DEFAULT 1
65ac8851
YS		 357static void sh_eth_set_rate(struct net_device *ndev)
358{
359 struct sh_eth_private *mdp = netdev_priv(ndev);
d0418bb7 360
a3f109bd
SS		 361 switch (mdp->speed) {
362 case 10: /* 10BASE */
363 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_ELB, ECMR);
364 break;
365 case 100:/* 100BASE */
366 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_ELB, ECMR);
367 break;
368 default:
369 break;
370 }
371}
372
674853b2 373/* R8A7778/9 */
a3f109bd
SS		 374static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
375 .set_duplex = sh_eth_set_duplex,
376 .set_rate = sh_eth_set_rate,
377
378 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
379 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
380 .eesipr_value = 0x01ff009f,
381
382 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
383 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE |
384 EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI,
385 .tx_error_check = EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE,
386
387 .apr = 1,
388 .mpr = 1,
389 .tpauser = 1,
390 .hw_swap = 1,
391};
392#elif defined(CONFIG_CPU_SUBTYPE_SH7724)
393#define SH_ETH_RESET_DEFAULT 1
a3f109bd
SS		 394
395static void sh_eth_set_rate(struct net_device *ndev)
396{
397 struct sh_eth_private *mdp = netdev_priv(ndev);
65ac8851
YS		 398
399 switch (mdp->speed) {
400 case 10: /* 10BASE */
a3f109bd 401 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_RTM, ECMR);
65ac8851
YS		 402 break;
403 case 100:/* 100BASE */
a3f109bd 404 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_RTM, ECMR);
65ac8851
YS		 405 break;
406 default:
407 break;
408 }
409}
410
411/* SH7724 */
412static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
413 .set_duplex = sh_eth_set_duplex,
414 .set_rate = sh_eth_set_rate,
415
416 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
417 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
418 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x01ff009f,
419
420 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
421 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE |
422 EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI,
423 .tx_error_check = EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE,
424
425 .apr = 1,
426 .mpr = 1,
427 .tpauser = 1,
428 .hw_swap = 1,
503914cf
MD		 429 .rpadir = 1,
430 .rpadir_value = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
65ac8851 431};
f29a3d04 432#elif defined(CONFIG_CPU_SUBTYPE_SH7757)
8fcd4961 433#define SH_ETH_HAS_BOTH_MODULES 1
5cee1d37
NI		 434static int sh_eth_check_reset(struct net_device *ndev);
435
f29a3d04
YS		 436static void sh_eth_set_rate(struct net_device *ndev)
437{
438 struct sh_eth_private *mdp = netdev_priv(ndev);
f29a3d04
YS		 439
440 switch (mdp->speed) {
441 case 10: /* 10BASE */
4a55530f 442 sh_eth_write(ndev, 0, RTRATE);
f29a3d04
YS		 443 break;
444 case 100:/* 100BASE */
4a55530f 445 sh_eth_write(ndev, 1, RTRATE);
f29a3d04
YS		 446 break;
447 default:
448 break;
449 }
450}
451
452/* SH7757 */
453static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
454 .set_duplex = sh_eth_set_duplex,
455 .set_rate = sh_eth_set_rate,
456
457 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
458 .rmcr_value = 0x00000001,
459
460 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
461 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE |
462 EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI,
463 .tx_error_check = EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE,
464
465 .apr = 1,
466 .mpr = 1,
467 .tpauser = 1,
468 .hw_swap = 1,
469 .no_ade = 1,
2e98e797
YS		 470 .rpadir = 1,
471 .rpadir_value = 2 << 16,
f29a3d04 472};
65ac8851 473
8fcd4961
YS		 474#define SH_GIGA_ETH_BASE 0xfee00000
475#define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
476#define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
477static void sh_eth_chip_reset_giga(struct net_device *ndev)
478{
479 int i;
480 unsigned long mahr[2], malr[2];
481
482 /* save MAHR and MALR */
483 for (i = 0; i < 2; i++) {
ae70644d
YS		 484 malr[i] = ioread32((void *)GIGA_MALR(i));
485 mahr[i] = ioread32((void *)GIGA_MAHR(i));
8fcd4961
YS		 486 }
487
488 /* reset device */
ae70644d 489 iowrite32(ARSTR_ARSTR, (void *)(SH_GIGA_ETH_BASE + 0x1800));
8fcd4961
YS		 490 mdelay(1);
491
492 /* restore MAHR and MALR */
493 for (i = 0; i < 2; i++) {
ae70644d
YS		 494 iowrite32(malr[i], (void *)GIGA_MALR(i));
495 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
8fcd4961
YS		 496 }
497}
498
499static int sh_eth_is_gether(struct sh_eth_private *mdp);
5cee1d37 500static int sh_eth_reset(struct net_device *ndev)
8fcd4961
YS		 501{
502 struct sh_eth_private *mdp = netdev_priv(ndev);
5cee1d37 503 int ret = 0;
8fcd4961
YS		 504
505 if (sh_eth_is_gether(mdp)) {
ddcd91c6 506 sh_eth_write(ndev, EDSR_ENALL, EDSR);
8fcd4961
YS		 507 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER,
508 EDMR);
5cee1d37
NI		 509
510 ret = sh_eth_check_reset(ndev);
511 if (ret)
512 goto out;
8fcd4961
YS		 513
514 /* Table Init */
515 sh_eth_write(ndev, 0x0, TDLAR);
516 sh_eth_write(ndev, 0x0, TDFAR);
517 sh_eth_write(ndev, 0x0, TDFXR);
518 sh_eth_write(ndev, 0x0, TDFFR);
519 sh_eth_write(ndev, 0x0, RDLAR);
520 sh_eth_write(ndev, 0x0, RDFAR);
521 sh_eth_write(ndev, 0x0, RDFXR);
522 sh_eth_write(ndev, 0x0, RDFFR);
523 } else {
524 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER,
525 EDMR);
526 mdelay(3);
527 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER,
528 EDMR);
529 }
5cee1d37
NI		 530
531out:
532 return ret;
8fcd4961
YS		 533}
534
8fcd4961
YS		 535static void sh_eth_set_rate_giga(struct net_device *ndev)
536{
537 struct sh_eth_private *mdp = netdev_priv(ndev);
538
539 switch (mdp->speed) {
540 case 10: /* 10BASE */
541 sh_eth_write(ndev, 0x00000000, GECMR);
542 break;
543 case 100:/* 100BASE */
544 sh_eth_write(ndev, 0x00000010, GECMR);
545 break;
546 case 1000: /* 1000BASE */
547 sh_eth_write(ndev, 0x00000020, GECMR);
548 break;
549 default:
550 break;
551 }
552}
553
554/* SH7757(GETHERC) */
555static struct sh_eth_cpu_data sh_eth_my_cpu_data_giga = {
556 .chip_reset = sh_eth_chip_reset_giga,
04b0ed2a 557 .set_duplex = sh_eth_set_duplex,
8fcd4961
YS		 558 .set_rate = sh_eth_set_rate_giga,
559
560 .ecsr_value = ECSR_ICD | ECSR_MPD,
561 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
562 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
563
564 .tx_check = EESR_TC1 | EESR_FTC,
565 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \
566 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \
567 EESR_ECI,
568 .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \
569 EESR_TFE,
570 .fdr_value = 0x0000072f,
571 .rmcr_value = 0x00000001,
572
573 .apr = 1,
574 .mpr = 1,
575 .tpauser = 1,
576 .bculr = 1,
577 .hw_swap = 1,
578 .rpadir = 1,
579 .rpadir_value = 2 << 16,
580 .no_trimd = 1,
581 .no_ade = 1,
3acbc971 582 .tsu = 1,
8fcd4961
YS		 583};
584
585static struct sh_eth_cpu_data *sh_eth_get_cpu_data(struct sh_eth_private *mdp)
586{
587 if (sh_eth_is_gether(mdp))
588 return &sh_eth_my_cpu_data_giga;
589 else
590 return &sh_eth_my_cpu_data;
591}
592
f0e81fec 593#elif defined(CONFIG_CPU_SUBTYPE_SH7734) || defined(CONFIG_CPU_SUBTYPE_SH7763)
5cee1d37 594static int sh_eth_check_reset(struct net_device *ndev);
f0e81fec 595static void sh_eth_reset_hw_crc(struct net_device *ndev);
5e7a76be 596
380af9e3
YS		 597static void sh_eth_chip_reset(struct net_device *ndev)
598{
4986b996
YS		 599 struct sh_eth_private *mdp = netdev_priv(ndev);
600
380af9e3 601 /* reset device */
4986b996 602 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
380af9e3
YS		 603 mdelay(1);
604}
605
380af9e3
YS		 606static void sh_eth_set_rate(struct net_device *ndev)
607{
608 struct sh_eth_private *mdp = netdev_priv(ndev);
380af9e3
YS		 609
610 switch (mdp->speed) {
611 case 10: /* 10BASE */
4a55530f 612 sh_eth_write(ndev, GECMR_10, GECMR);
380af9e3
YS		 613 break;
614 case 100:/* 100BASE */
4a55530f 615 sh_eth_write(ndev, GECMR_100, GECMR);
380af9e3
YS		 616 break;
617 case 1000: /* 1000BASE */
4a55530f 618 sh_eth_write(ndev, GECMR_1000, GECMR);
380af9e3
YS		 619 break;
620 default:
621 break;
622 }
623}
624
625/* sh7763 */
626static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
627 .chip_reset = sh_eth_chip_reset,
628 .set_duplex = sh_eth_set_duplex,
629 .set_rate = sh_eth_set_rate,
630
631 .ecsr_value = ECSR_ICD | ECSR_MPD,
632 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
633 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
634
635 .tx_check = EESR_TC1 | EESR_FTC,
636 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \
637 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \
638 EESR_ECI,
639 .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \
640 EESR_TFE,
641
642 .apr = 1,
643 .mpr = 1,
644 .tpauser = 1,
645 .bculr = 1,
646 .hw_swap = 1,
380af9e3
YS		 647 .no_trimd = 1,
648 .no_ade = 1,
4986b996 649 .tsu = 1,
f0e81fec
NI		 650#if defined(CONFIG_CPU_SUBTYPE_SH7734)
651 .hw_crc = 1,
5e7a76be 652 .select_mii = 1,
f0e81fec 653#endif
380af9e3
YS		 654};
655
5cee1d37 656static int sh_eth_reset(struct net_device *ndev)
5e7a76be 657{
5cee1d37 658 int ret = 0;
5e7a76be
NI		 659
660 sh_eth_write(ndev, EDSR_ENALL, EDSR);
661 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER, EDMR);
5cee1d37
NI		 662
663 ret = sh_eth_check_reset(ndev);
664 if (ret)
665 goto out;
5e7a76be
NI		 666
667 /* Table Init */
668 sh_eth_write(ndev, 0x0, TDLAR);
669 sh_eth_write(ndev, 0x0, TDFAR);
670 sh_eth_write(ndev, 0x0, TDFXR);
671 sh_eth_write(ndev, 0x0, TDFFR);
672 sh_eth_write(ndev, 0x0, RDLAR);
673 sh_eth_write(ndev, 0x0, RDFAR);
674 sh_eth_write(ndev, 0x0, RDFXR);
675 sh_eth_write(ndev, 0x0, RDFFR);
676
677 /* Reset HW CRC register */
678 sh_eth_reset_hw_crc(ndev);
679
680 /* Select MII mode */
681 if (sh_eth_my_cpu_data.select_mii)
682 sh_eth_select_mii(ndev);
5cee1d37
NI		 683out:
684 return ret;
5e7a76be
NI		 685}
686
f0e81fec
NI		 687static void sh_eth_reset_hw_crc(struct net_device *ndev)
688{
689 if (sh_eth_my_cpu_data.hw_crc)
690 sh_eth_write(ndev, 0x0, CSMR);
691}
692
73a0d907 693#elif defined(CONFIG_ARCH_R8A7740)
5cee1d37
NI		 694static int sh_eth_check_reset(struct net_device *ndev);
695
73a0d907
YS		 696static void sh_eth_chip_reset(struct net_device *ndev)
697{
698 struct sh_eth_private *mdp = netdev_priv(ndev);
73a0d907
YS		 699
700 /* reset device */
701 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
702 mdelay(1);
703
5e7a76be 704 sh_eth_select_mii(ndev);
73a0d907
YS		 705}
706
5cee1d37 707static int sh_eth_reset(struct net_device *ndev)
73a0d907 708{
5cee1d37 709 int ret = 0;
73a0d907
YS		 710
711 sh_eth_write(ndev, EDSR_ENALL, EDSR);
712 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER, EDMR);
5cee1d37
NI		 713
714 ret = sh_eth_check_reset(ndev);
715 if (ret)
716 goto out;
73a0d907
YS		 717
718 /* Table Init */
719 sh_eth_write(ndev, 0x0, TDLAR);
720 sh_eth_write(ndev, 0x0, TDFAR);
721 sh_eth_write(ndev, 0x0, TDFXR);
722 sh_eth_write(ndev, 0x0, TDFFR);
723 sh_eth_write(ndev, 0x0, RDLAR);
724 sh_eth_write(ndev, 0x0, RDFAR);
725 sh_eth_write(ndev, 0x0, RDFXR);
726 sh_eth_write(ndev, 0x0, RDFFR);
5cee1d37
NI		 727
728out:
729 return ret;
73a0d907
YS		 730}
731
73a0d907
YS		 732static void sh_eth_set_rate(struct net_device *ndev)
733{
734 struct sh_eth_private *mdp = netdev_priv(ndev);
735
736 switch (mdp->speed) {
737 case 10: /* 10BASE */
738 sh_eth_write(ndev, GECMR_10, GECMR);
739 break;
740 case 100:/* 100BASE */
741 sh_eth_write(ndev, GECMR_100, GECMR);
742 break;
743 case 1000: /* 1000BASE */
744 sh_eth_write(ndev, GECMR_1000, GECMR);
745 break;
746 default:
747 break;
748 }
749}
750
751/* R8A7740 */
752static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
753 .chip_reset = sh_eth_chip_reset,
754 .set_duplex = sh_eth_set_duplex,
755 .set_rate = sh_eth_set_rate,
756
757 .ecsr_value = ECSR_ICD | ECSR_MPD,
758 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
759 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
760
761 .tx_check = EESR_TC1 | EESR_FTC,
762 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \
763 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \
764 EESR_ECI,
765 .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \
766 EESR_TFE,
767
768 .apr = 1,
769 .mpr = 1,
770 .tpauser = 1,
771 .bculr = 1,
772 .hw_swap = 1,
773 .no_trimd = 1,
774 .no_ade = 1,
775 .tsu = 1,
5e7a76be 776 .select_mii = 1,
73a0d907
YS		 777};
778
380af9e3
YS		 779#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
780#define SH_ETH_RESET_DEFAULT 1
781static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
782 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
783
784 .apr = 1,
785 .mpr = 1,
786 .tpauser = 1,
787 .hw_swap = 1,
788};
789#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
790#define SH_ETH_RESET_DEFAULT 1
380af9e3
YS		 791static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
792 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
4986b996 793 .tsu = 1,
380af9e3
YS		 794};
795#endif
796
797static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
798{
799 if (!cd->ecsr_value)
800 cd->ecsr_value = DEFAULT_ECSR_INIT;
801
802 if (!cd->ecsipr_value)
803 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
804
805 if (!cd->fcftr_value)
806 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF | \
807 DEFAULT_FIFO_F_D_RFD;
808
809 if (!cd->fdr_value)
810 cd->fdr_value = DEFAULT_FDR_INIT;
811
812 if (!cd->rmcr_value)
813 cd->rmcr_value = DEFAULT_RMCR_VALUE;
814
815 if (!cd->tx_check)
816 cd->tx_check = DEFAULT_TX_CHECK;
817
818 if (!cd->eesr_err_check)
819 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
820
821 if (!cd->tx_error_check)
822 cd->tx_error_check = DEFAULT_TX_ERROR_CHECK;
823}
824
825#if defined(SH_ETH_RESET_DEFAULT)
826/* Chip Reset */
5cee1d37 827static int sh_eth_reset(struct net_device *ndev)
380af9e3 828{
c5ed5368 829 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER, EDMR);
380af9e3 830 mdelay(3);
c5ed5368 831 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER, EDMR);
5cee1d37
NI		 832
833 return 0;
834}
835#else
836static int sh_eth_check_reset(struct net_device *ndev)
837{
838 int ret = 0;
839 int cnt = 100;
840
841 while (cnt > 0) {
842 if (!(sh_eth_read(ndev, EDMR) & 0x3))
843 break;
844 mdelay(1);
845 cnt--;
846 }
847 if (cnt < 0) {
14c3326a 848 pr_err("Device reset fail\n");
5cee1d37
NI		 849 ret = -ETIMEDOUT;
850 }
851 return ret;
380af9e3
YS		 852}
853#endif
854
73a0d907 855#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
380af9e3
YS		 856static void sh_eth_set_receive_align(struct sk_buff *skb)
857{
858 int reserve;
859
860 reserve = SH4_SKB_RX_ALIGN - ((u32)skb->data & (SH4_SKB_RX_ALIGN - 1));
861 if (reserve)
862 skb_reserve(skb, reserve);
863}
864#else
865static void sh_eth_set_receive_align(struct sk_buff *skb)
866{
867 skb_reserve(skb, SH2_SH3_SKB_RX_ALIGN);
868}
869#endif
870
871
71557a37
YS		 872/* CPU <-> EDMAC endian convert */
873static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x)
874{
875 switch (mdp->edmac_endian) {
876 case EDMAC_LITTLE_ENDIAN:
877 return cpu_to_le32(x);
878 case EDMAC_BIG_ENDIAN:
879 return cpu_to_be32(x);
880 }
881 return x;
882}
883
884static inline __u32 edmac_to_cpu(struct sh_eth_private *mdp, u32 x)
885{
886 switch (mdp->edmac_endian) {
887 case EDMAC_LITTLE_ENDIAN:
888 return le32_to_cpu(x);
889 case EDMAC_BIG_ENDIAN:
890 return be32_to_cpu(x);
891 }
892 return x;
893}
894
86a74ff2
NI		 895/*
896 * Program the hardware MAC address from dev->dev_addr.
897 */
898static void update_mac_address(struct net_device *ndev)
899{
4a55530f
YS		 900 sh_eth_write(ndev,
901 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
902 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
903 sh_eth_write(ndev,
904 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
86a74ff2
NI		 905}
906
907/*
908 * Get MAC address from SuperH MAC address register
909 *
910 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
911 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
912 * When you want use this device, you must set MAC address in bootloader.
913 *
914 */
748031f9 915static void read_mac_address(struct net_device *ndev, unsigned char *mac)
86a74ff2 916{
748031f9
MD		 917 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
918 memcpy(ndev->dev_addr, mac, 6);
919 } else {
4a55530f
YS		 920 ndev->dev_addr[0] = (sh_eth_read(ndev, MAHR) >> 24);
921 ndev->dev_addr[1] = (sh_eth_read(ndev, MAHR) >> 16) & 0xFF;
922 ndev->dev_addr[2] = (sh_eth_read(ndev, MAHR) >> 8) & 0xFF;
923 ndev->dev_addr[3] = (sh_eth_read(ndev, MAHR) & 0xFF);
924 ndev->dev_addr[4] = (sh_eth_read(ndev, MALR) >> 8) & 0xFF;
925 ndev->dev_addr[5] = (sh_eth_read(ndev, MALR) & 0xFF);
748031f9 926 }
86a74ff2
NI		 927}
928
c5ed5368
YS		 929static int sh_eth_is_gether(struct sh_eth_private *mdp)
930{
931 if (mdp->reg_offset == sh_eth_offset_gigabit)
932 return 1;
933 else
934 return 0;
935}
936
937static unsigned long sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
938{
939 if (sh_eth_is_gether(mdp))
940 return EDTRR_TRNS_GETHER;
941 else
942 return EDTRR_TRNS_ETHER;
943}
944
86a74ff2 945struct bb_info {
ae70644d 946 void (*set_gate)(void *addr);
86a74ff2 947 struct mdiobb_ctrl ctrl;
ae70644d 948 void *addr;
86a74ff2
NI		 949 u32 mmd_msk;/* MMD */
950 u32 mdo_msk;
951 u32 mdi_msk;
952 u32 mdc_msk;
953};
954
955/* PHY bit set */
ae70644d 956static void bb_set(void *addr, u32 msk)
86a74ff2 957{
ae70644d 958 iowrite32(ioread32(addr) | msk, addr);
86a74ff2
NI		 959}
960
961/* PHY bit clear */
ae70644d 962static void bb_clr(void *addr, u32 msk)
86a74ff2 963{
ae70644d 964 iowrite32((ioread32(addr) & ~msk), addr);
86a74ff2
NI		 965}
966
967/* PHY bit read */
ae70644d 968static int bb_read(void *addr, u32 msk)
86a74ff2 969{
ae70644d 970 return (ioread32(addr) & msk) != 0;
86a74ff2
NI		 971}
972
973/* Data I/O pin control */
974static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
975{
976 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
b3017e6a
YS		 977
978 if (bitbang->set_gate)
979 bitbang->set_gate(bitbang->addr);
980
86a74ff2
NI		 981 if (bit)
982 bb_set(bitbang->addr, bitbang->mmd_msk);
983 else
984 bb_clr(bitbang->addr, bitbang->mmd_msk);
985}
986
987/* Set bit data*/
988static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
989{
990 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
991
b3017e6a
YS		 992 if (bitbang->set_gate)
993 bitbang->set_gate(bitbang->addr);
994
86a74ff2
NI		 995 if (bit)
996 bb_set(bitbang->addr, bitbang->mdo_msk);
997 else
998 bb_clr(bitbang->addr, bitbang->mdo_msk);
999}
1000
1001/* Get bit data*/
1002static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
1003{
1004 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
b3017e6a
YS		 1005
1006 if (bitbang->set_gate)
1007 bitbang->set_gate(bitbang->addr);
1008
86a74ff2
NI		 1009 return bb_read(bitbang->addr, bitbang->mdi_msk);
1010}
1011
1012/* MDC pin control */
1013static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1014{
1015 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1016
b3017e6a
YS		 1017 if (bitbang->set_gate)
1018 bitbang->set_gate(bitbang->addr);
1019
86a74ff2
NI		 1020 if (bit)
1021 bb_set(bitbang->addr, bitbang->mdc_msk);
1022 else
1023 bb_clr(bitbang->addr, bitbang->mdc_msk);
1024}
1025
1026/* mdio bus control struct */
1027static struct mdiobb_ops bb_ops = {
1028 .owner = THIS_MODULE,
1029 .set_mdc = sh_mdc_ctrl,
1030 .set_mdio_dir = sh_mmd_ctrl,
1031 .set_mdio_data = sh_set_mdio,
1032 .get_mdio_data = sh_get_mdio,
1033};
1034
86a74ff2
NI		 1035/* free skb and descriptor buffer */
1036static void sh_eth_ring_free(struct net_device *ndev)
1037{
1038 struct sh_eth_private *mdp = netdev_priv(ndev);
1039 int i;
1040
1041 /* Free Rx skb ringbuffer */
1042 if (mdp->rx_skbuff) {
525b8075 1043 for (i = 0; i < mdp->num_rx_ring; i++) {
86a74ff2
NI		 1044 if (mdp->rx_skbuff[i])
1045 dev_kfree_skb(mdp->rx_skbuff[i]);
1046 }
1047 }
1048 kfree(mdp->rx_skbuff);
91c77550 1049 mdp->rx_skbuff = NULL;
86a74ff2
NI		 1050
1051 /* Free Tx skb ringbuffer */
1052 if (mdp->tx_skbuff) {
525b8075 1053 for (i = 0; i < mdp->num_tx_ring; i++) {
86a74ff2
NI		 1054 if (mdp->tx_skbuff[i])
1055 dev_kfree_skb(mdp->tx_skbuff[i]);
1056 }
1057 }
1058 kfree(mdp->tx_skbuff);
91c77550 1059 mdp->tx_skbuff = NULL;
86a74ff2
NI		 1060}
1061
1062/* format skb and descriptor buffer */
1063static void sh_eth_ring_format(struct net_device *ndev)
1064{
1065 struct sh_eth_private *mdp = netdev_priv(ndev);
1066 int i;
1067 struct sk_buff *skb;
1068 struct sh_eth_rxdesc *rxdesc = NULL;
1069 struct sh_eth_txdesc *txdesc = NULL;
525b8075
YS		 1070 int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
1071 int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
86a74ff2
NI		 1072
1073 mdp->cur_rx = mdp->cur_tx = 0;
1074 mdp->dirty_rx = mdp->dirty_tx = 0;
1075
1076 memset(mdp->rx_ring, 0, rx_ringsize);
1077
1078 /* build Rx ring buffer */
525b8075 1079 for (i = 0; i < mdp->num_rx_ring; i++) {
86a74ff2
NI		 1080 /* skb */
1081 mdp->rx_skbuff[i] = NULL;
dae2e9f4 1082 skb = netdev_alloc_skb(ndev, mdp->rx_buf_sz);
86a74ff2
NI		 1083 mdp->rx_skbuff[i] = skb;
1084 if (skb == NULL)
1085 break;
bb7d92e3 1086 dma_map_single(&ndev->dev, skb->data, mdp->rx_buf_sz,
e88aae7b 1087 DMA_FROM_DEVICE);
380af9e3
YS		 1088 sh_eth_set_receive_align(skb);
1089
86a74ff2
NI		 1090 /* RX descriptor */
1091 rxdesc = &mdp->rx_ring[i];
0029d64a 1092 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
71557a37 1093 rxdesc->status = cpu_to_edmac(mdp, RD_RACT | RD_RFP);
86a74ff2
NI		 1094
1095 /* The size of the buffer is 16 byte boundary. */
0029d64a 1096 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
b0ca2a21
NI		 1097 /* Rx descriptor address set */
1098 if (i == 0) {
4a55530f 1099 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
c5ed5368
YS		 1100 if (sh_eth_is_gether(mdp))
1101 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
b0ca2a21 1102 }
86a74ff2
NI		 1103 }
1104
525b8075 1105 mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
86a74ff2
NI		 1106
1107 /* Mark the last entry as wrapping the ring. */
71557a37 1108 rxdesc->status |= cpu_to_edmac(mdp, RD_RDEL);
86a74ff2
NI		 1109
1110 memset(mdp->tx_ring, 0, tx_ringsize);
1111
1112 /* build Tx ring buffer */
525b8075 1113 for (i = 0; i < mdp->num_tx_ring; i++) {
86a74ff2
NI		 1114 mdp->tx_skbuff[i] = NULL;
1115 txdesc = &mdp->tx_ring[i];
71557a37 1116 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
86a74ff2 1117 txdesc->buffer_length = 0;
b0ca2a21 1118 if (i == 0) {
71557a37 1119 /* Tx descriptor address set */
4a55530f 1120 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
c5ed5368
YS		 1121 if (sh_eth_is_gether(mdp))
1122 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
b0ca2a21 1123 }
86a74ff2
NI		 1124 }
1125
71557a37 1126 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
86a74ff2
NI		 1127}
1128
1129/* Get skb and descriptor buffer */
1130static int sh_eth_ring_init(struct net_device *ndev)
1131{
1132 struct sh_eth_private *mdp = netdev_priv(ndev);
1133 int rx_ringsize, tx_ringsize, ret = 0;
1134
1135 /*
1136 * +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
1137 * card needs room to do 8 byte alignment, +2 so we can reserve
1138 * the first 2 bytes, and +16 gets room for the status word from the
1139 * card.
1140 */
1141 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
1142 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
503914cf
MD		 1143 if (mdp->cd->rpadir)
1144 mdp->rx_buf_sz += NET_IP_ALIGN;
86a74ff2
NI		 1145
1146 /* Allocate RX and TX skb rings */
b2adaca9
JP		 1147 mdp->rx_skbuff = kmalloc_array(mdp->num_rx_ring,
1148 sizeof(*mdp->rx_skbuff), GFP_KERNEL);
86a74ff2 1149 if (!mdp->rx_skbuff) {
86a74ff2
NI		 1150 ret = -ENOMEM;
1151 return ret;
1152 }
1153
b2adaca9
JP		 1154 mdp->tx_skbuff = kmalloc_array(mdp->num_tx_ring,
1155 sizeof(*mdp->tx_skbuff), GFP_KERNEL);
86a74ff2 1156 if (!mdp->tx_skbuff) {
86a74ff2
NI		 1157 ret = -ENOMEM;
1158 goto skb_ring_free;
1159 }
1160
1161 /* Allocate all Rx descriptors. */
525b8075 1162 rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
86a74ff2 1163 mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
d0320f75 1164 GFP_KERNEL);
86a74ff2 1165 if (!mdp->rx_ring) {
86a74ff2
NI		 1166 ret = -ENOMEM;
1167 goto desc_ring_free;
1168 }
1169
1170 mdp->dirty_rx = 0;
1171
1172 /* Allocate all Tx descriptors. */
525b8075 1173 tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
86a74ff2 1174 mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
d0320f75 1175 GFP_KERNEL);
86a74ff2 1176 if (!mdp->tx_ring) {
86a74ff2
NI		 1177 ret = -ENOMEM;
1178 goto desc_ring_free;
1179 }
1180 return ret;
1181
1182desc_ring_free:
1183 /* free DMA buffer */
1184 dma_free_coherent(NULL, rx_ringsize, mdp->rx_ring, mdp->rx_desc_dma);
1185
1186skb_ring_free:
1187 /* Free Rx and Tx skb ring buffer */
1188 sh_eth_ring_free(ndev);
91c77550
YS		 1189 mdp->tx_ring = NULL;
1190 mdp->rx_ring = NULL;
86a74ff2
NI		 1191
1192 return ret;
1193}
1194
91c77550
YS		 1195static void sh_eth_free_dma_buffer(struct sh_eth_private *mdp)
1196{
1197 int ringsize;
1198
1199 if (mdp->rx_ring) {
525b8075 1200 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
91c77550
YS		 1201 dma_free_coherent(NULL, ringsize, mdp->rx_ring,
1202 mdp->rx_desc_dma);
1203 mdp->rx_ring = NULL;
1204 }
1205
1206 if (mdp->tx_ring) {
525b8075 1207 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
91c77550
YS		 1208 dma_free_coherent(NULL, ringsize, mdp->tx_ring,
1209 mdp->tx_desc_dma);
1210 mdp->tx_ring = NULL;
1211 }
1212}
1213
525b8075 1214static int sh_eth_dev_init(struct net_device *ndev, bool start)
86a74ff2
NI		 1215{
1216 int ret = 0;
1217 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 1218 u32 val;
1219
1220 /* Soft Reset */
5cee1d37
NI		 1221 ret = sh_eth_reset(ndev);
1222 if (ret)
1223 goto out;
86a74ff2 1224
b0ca2a21
NI		 1225 /* Descriptor format */
1226 sh_eth_ring_format(ndev);
380af9e3 1227 if (mdp->cd->rpadir)
4a55530f 1228 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
86a74ff2
NI		 1229
1230 /* all sh_eth int mask */
4a55530f 1231 sh_eth_write(ndev, 0, EESIPR);
86a74ff2 1232
10b9194f 1233#if defined(__LITTLE_ENDIAN)
380af9e3 1234 if (mdp->cd->hw_swap)
4a55530f 1235 sh_eth_write(ndev, EDMR_EL, EDMR);
380af9e3 1236 else
b0ca2a21 1237#endif
4a55530f 1238 sh_eth_write(ndev, 0, EDMR);
86a74ff2 1239
b0ca2a21 1240 /* FIFO size set */
4a55530f
YS		 1241 sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
1242 sh_eth_write(ndev, 0, TFTR);
86a74ff2 1243
b0ca2a21 1244 /* Frame recv control */
4a55530f 1245 sh_eth_write(ndev, mdp->cd->rmcr_value, RMCR);
86a74ff2 1246
2ecbb783 1247 sh_eth_write(ndev, DESC_I_RINT8 | DESC_I_RINT5 | DESC_I_TINT2, TRSCER);
86a74ff2 1248
380af9e3 1249 if (mdp->cd->bculr)
4a55530f 1250 sh_eth_write(ndev, 0x800, BCULR); /* Burst sycle set */
b0ca2a21 1251
4a55530f 1252 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
86a74ff2 1253
380af9e3 1254 if (!mdp->cd->no_trimd)
4a55530f 1255 sh_eth_write(ndev, 0, TRIMD);
86a74ff2 1256
b0ca2a21 1257 /* Recv frame limit set register */
fdb37a7f
YS		 1258 sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1259 RFLR);
86a74ff2 1260
4a55530f 1261 sh_eth_write(ndev, sh_eth_read(ndev, EESR), EESR);
525b8075
YS		 1262 if (start)
1263 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
86a74ff2
NI		 1264
1265 /* PAUSE Prohibition */
4a55530f 1266 val = (sh_eth_read(ndev, ECMR) & ECMR_DM) |
86a74ff2
NI		 1267 ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE;
1268
4a55530f 1269 sh_eth_write(ndev, val, ECMR);
b0ca2a21 1270
380af9e3
YS		 1271 if (mdp->cd->set_rate)
1272 mdp->cd->set_rate(ndev);
1273
b0ca2a21 1274 /* E-MAC Status Register clear */
4a55530f 1275 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
b0ca2a21
NI		 1276
1277 /* E-MAC Interrupt Enable register */
525b8075
YS		 1278 if (start)
1279 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
86a74ff2
NI		 1280
1281 /* Set MAC address */
1282 update_mac_address(ndev);
1283
1284 /* mask reset */
380af9e3 1285 if (mdp->cd->apr)
4a55530f 1286 sh_eth_write(ndev, APR_AP, APR);
380af9e3 1287 if (mdp->cd->mpr)
4a55530f 1288 sh_eth_write(ndev, MPR_MP, MPR);
380af9e3 1289 if (mdp->cd->tpauser)
4a55530f 1290 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
b0ca2a21 1291
525b8075
YS		 1292 if (start) {
1293 /* Setting the Rx mode will start the Rx process. */
1294 sh_eth_write(ndev, EDRRR_R, EDRRR);
86a74ff2 1295
525b8075
YS		 1296 netif_start_queue(ndev);
1297 }
86a74ff2 1298
5cee1d37 1299out:
86a74ff2
NI		 1300 return ret;
1301}
1302
1303/* free Tx skb function */
1304static int sh_eth_txfree(struct net_device *ndev)
1305{
1306 struct sh_eth_private *mdp = netdev_priv(ndev);
1307 struct sh_eth_txdesc *txdesc;
1308 int freeNum = 0;
1309 int entry = 0;
1310
1311 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
525b8075 1312 entry = mdp->dirty_tx % mdp->num_tx_ring;
86a74ff2 1313 txdesc = &mdp->tx_ring[entry];
71557a37 1314 if (txdesc->status & cpu_to_edmac(mdp, TD_TACT))
86a74ff2
NI		 1315 break;
1316 /* Free the original skb. */
1317 if (mdp->tx_skbuff[entry]) {
31fcb99d
YS		 1318 dma_unmap_single(&ndev->dev, txdesc->addr,
1319 txdesc->buffer_length, DMA_TO_DEVICE);
86a74ff2
NI		 1320 dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1321 mdp->tx_skbuff[entry] = NULL;
1322 freeNum++;
1323 }
71557a37 1324 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
525b8075 1325 if (entry >= mdp->num_tx_ring - 1)
71557a37 1326 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
86a74ff2 1327
bb7d92e3
ED		 1328 ndev->stats.tx_packets++;
1329 ndev->stats.tx_bytes += txdesc->buffer_length;
86a74ff2
NI		 1330 }
1331 return freeNum;
1332}
1333
1334/* Packet receive function */
a18e08bd 1335static int sh_eth_rx(struct net_device *ndev, u32 intr_status)
86a74ff2
NI		 1336{
1337 struct sh_eth_private *mdp = netdev_priv(ndev);
1338 struct sh_eth_rxdesc *rxdesc;
1339
525b8075
YS		 1340 int entry = mdp->cur_rx % mdp->num_rx_ring;
1341 int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
86a74ff2
NI		 1342 struct sk_buff *skb;
1343 u16 pkt_len = 0;
380af9e3 1344 u32 desc_status;
86a74ff2
NI		 1345
1346 rxdesc = &mdp->rx_ring[entry];
71557a37
YS		 1347 while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) {
1348 desc_status = edmac_to_cpu(mdp, rxdesc->status);
86a74ff2
NI		 1349 pkt_len = rxdesc->frame_length;
1350
73a0d907
YS		 1351#if defined(CONFIG_ARCH_R8A7740)
1352 desc_status >>= 16;
1353#endif
1354
86a74ff2
NI		 1355 if (--boguscnt < 0)
1356 break;
1357
1358 if (!(desc_status & RDFEND))
bb7d92e3 1359 ndev->stats.rx_length_errors++;
86a74ff2
NI		 1360
1361 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1362 RD_RFS5 | RD_RFS6 | RD_RFS10)) {
bb7d92e3 1363 ndev->stats.rx_errors++;
86a74ff2 1364 if (desc_status & RD_RFS1)
bb7d92e3 1365 ndev->stats.rx_crc_errors++;
86a74ff2 1366 if (desc_status & RD_RFS2)
bb7d92e3 1367 ndev->stats.rx_frame_errors++;
86a74ff2 1368 if (desc_status & RD_RFS3)
bb7d92e3 1369 ndev->stats.rx_length_errors++;
86a74ff2 1370 if (desc_status & RD_RFS4)
bb7d92e3 1371 ndev->stats.rx_length_errors++;
86a74ff2 1372 if (desc_status & RD_RFS6)
bb7d92e3 1373 ndev->stats.rx_missed_errors++;
86a74ff2 1374 if (desc_status & RD_RFS10)
bb7d92e3 1375 ndev->stats.rx_over_errors++;
86a74ff2 1376 } else {
380af9e3
YS		 1377 if (!mdp->cd->hw_swap)
1378 sh_eth_soft_swap(
1379 phys_to_virt(ALIGN(rxdesc->addr, 4)),
1380 pkt_len + 2);
86a74ff2
NI		 1381 skb = mdp->rx_skbuff[entry];
1382 mdp->rx_skbuff[entry] = NULL;
503914cf
MD		 1383 if (mdp->cd->rpadir)
1384 skb_reserve(skb, NET_IP_ALIGN);
86a74ff2
NI		 1385 skb_put(skb, pkt_len);
1386 skb->protocol = eth_type_trans(skb, ndev);
1387 netif_rx(skb);
bb7d92e3
ED		 1388 ndev->stats.rx_packets++;
1389 ndev->stats.rx_bytes += pkt_len;
86a74ff2 1390 }
71557a37 1391 rxdesc->status |= cpu_to_edmac(mdp, RD_RACT);
525b8075 1392 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
862df497 1393 rxdesc = &mdp->rx_ring[entry];
86a74ff2
NI		 1394 }
1395
1396 /* Refill the Rx ring buffers. */
1397 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
525b8075 1398 entry = mdp->dirty_rx % mdp->num_rx_ring;
86a74ff2 1399 rxdesc = &mdp->rx_ring[entry];
b0ca2a21 1400 /* The size of the buffer is 16 byte boundary. */
0029d64a 1401 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
b0ca2a21 1402
86a74ff2 1403 if (mdp->rx_skbuff[entry] == NULL) {
dae2e9f4 1404 skb = netdev_alloc_skb(ndev, mdp->rx_buf_sz);
86a74ff2
NI		 1405 mdp->rx_skbuff[entry] = skb;
1406 if (skb == NULL)
1407 break; /* Better luck next round. */
bb7d92e3 1408 dma_map_single(&ndev->dev, skb->data, mdp->rx_buf_sz,
e88aae7b 1409 DMA_FROM_DEVICE);
380af9e3
YS		 1410 sh_eth_set_receive_align(skb);
1411
bc8acf2c 1412 skb_checksum_none_assert(skb);
0029d64a 1413 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
86a74ff2 1414 }
525b8075 1415 if (entry >= mdp->num_rx_ring - 1)
86a74ff2 1416 rxdesc->status |=
71557a37 1417 cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDEL);
86a74ff2
NI		 1418 else
1419 rxdesc->status |=
71557a37 1420 cpu_to_edmac(mdp, RD_RACT | RD_RFP);
86a74ff2
NI		 1421 }
1422
1423 /* Restart Rx engine if stopped. */
1424 /* If we don't need to check status, don't. -KDU */
79fba9f5 1425 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
a18e08bd
YS		 1426 /* fix the values for the next receiving if RDE is set */
1427 if (intr_status & EESR_RDE)
1428 mdp->cur_rx = mdp->dirty_rx =
1429 (sh_eth_read(ndev, RDFAR) -
1430 sh_eth_read(ndev, RDLAR)) >> 4;
4a55530f 1431 sh_eth_write(ndev, EDRRR_R, EDRRR);
79fba9f5 1432 }
86a74ff2
NI		 1433
1434 return 0;
1435}
1436
4a55530f 1437static void sh_eth_rcv_snd_disable(struct net_device *ndev)
dc19e4e5
NI		 1438{
1439 /* disable tx and rx */
4a55530f
YS		 1440 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) &
1441 ~(ECMR_RE | ECMR_TE), ECMR);
dc19e4e5
NI		 1442}
1443
4a55530f 1444static void sh_eth_rcv_snd_enable(struct net_device *ndev)
dc19e4e5
NI		 1445{
1446 /* enable tx and rx */
4a55530f
YS		 1447 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) |
1448 (ECMR_RE | ECMR_TE), ECMR);
dc19e4e5
NI		 1449}
1450
86a74ff2
NI		 1451/* error control function */
1452static void sh_eth_error(struct net_device *ndev, int intr_status)
1453{
1454 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2 1455 u32 felic_stat;
380af9e3
YS		 1456 u32 link_stat;
1457 u32 mask;
86a74ff2
NI		 1458
1459 if (intr_status & EESR_ECI) {
4a55530f
YS		 1460 felic_stat = sh_eth_read(ndev, ECSR);
1461 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */
86a74ff2 1462 if (felic_stat & ECSR_ICD)
bb7d92e3 1463 ndev->stats.tx_carrier_errors++;
86a74ff2
NI		 1464 if (felic_stat & ECSR_LCHNG) {
1465 /* Link Changed */
4923576b 1466 if (mdp->cd->no_psr || mdp->no_ether_link) {
1e1b812b 1467 goto ignore_link;
380af9e3 1468 } else {
4a55530f 1469 link_stat = (sh_eth_read(ndev, PSR));
4923576b
YS		 1470 if (mdp->ether_link_active_low)
1471 link_stat = ~link_stat;
380af9e3 1472 }
dc19e4e5 1473 if (!(link_stat & PHY_ST_LINK))
4a55530f 1474 sh_eth_rcv_snd_disable(ndev);
dc19e4e5 1475 else {
86a74ff2 1476 /* Link Up */
4a55530f
YS		 1477 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) &
1478 ~DMAC_M_ECI, EESIPR);
86a74ff2 1479 /*clear int */
4a55530f
YS		 1480 sh_eth_write(ndev, sh_eth_read(ndev, ECSR),
1481 ECSR);
1482 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) |
1483 DMAC_M_ECI, EESIPR);
86a74ff2 1484 /* enable tx and rx */
4a55530f 1485 sh_eth_rcv_snd_enable(ndev);
86a74ff2
NI		 1486 }
1487 }
1488 }
1489
1e1b812b 1490ignore_link:
86a74ff2
NI		 1491 if (intr_status & EESR_TWB) {
1492 /* Write buck end. unused write back interrupt */
1493 if (intr_status & EESR_TABT) /* Transmit Abort int */
bb7d92e3 1494 ndev->stats.tx_aborted_errors++;
dc19e4e5
NI		 1495 if (netif_msg_tx_err(mdp))
1496 dev_err(&ndev->dev, "Transmit Abort\n");
86a74ff2
NI		 1497 }
1498
1499 if (intr_status & EESR_RABT) {
1500 /* Receive Abort int */
1501 if (intr_status & EESR_RFRMER) {
1502 /* Receive Frame Overflow int */
bb7d92e3 1503 ndev->stats.rx_frame_errors++;
dc19e4e5
NI		 1504 if (netif_msg_rx_err(mdp))
1505 dev_err(&ndev->dev, "Receive Abort\n");
86a74ff2
NI		 1506 }
1507 }
380af9e3 1508
dc19e4e5
NI		 1509 if (intr_status & EESR_TDE) {
1510 /* Transmit Descriptor Empty int */
bb7d92e3 1511 ndev->stats.tx_fifo_errors++;
dc19e4e5
NI		 1512 if (netif_msg_tx_err(mdp))
1513 dev_err(&ndev->dev, "Transmit Descriptor Empty\n");
1514 }
1515
1516 if (intr_status & EESR_TFE) {
1517 /* FIFO under flow */
bb7d92e3 1518 ndev->stats.tx_fifo_errors++;
dc19e4e5
NI		 1519 if (netif_msg_tx_err(mdp))
1520 dev_err(&ndev->dev, "Transmit FIFO Under flow\n");
86a74ff2
NI		 1521 }
1522
1523 if (intr_status & EESR_RDE) {
1524 /* Receive Descriptor Empty int */
bb7d92e3 1525 ndev->stats.rx_over_errors++;
86a74ff2 1526
dc19e4e5
NI		 1527 if (netif_msg_rx_err(mdp))
1528 dev_err(&ndev->dev, "Receive Descriptor Empty\n");
86a74ff2 1529 }
dc19e4e5 1530
86a74ff2
NI		 1531 if (intr_status & EESR_RFE) {
1532 /* Receive FIFO Overflow int */
bb7d92e3 1533 ndev->stats.rx_fifo_errors++;
dc19e4e5
NI		 1534 if (netif_msg_rx_err(mdp))
1535 dev_err(&ndev->dev, "Receive FIFO Overflow\n");
1536 }
1537
1538 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1539 /* Address Error */
bb7d92e3 1540 ndev->stats.tx_fifo_errors++;
dc19e4e5
NI		 1541 if (netif_msg_tx_err(mdp))
1542 dev_err(&ndev->dev, "Address Error\n");
86a74ff2 1543 }
380af9e3
YS		 1544
1545 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1546 if (mdp->cd->no_ade)
1547 mask &= ~EESR_ADE;
1548 if (intr_status & mask) {
86a74ff2 1549 /* Tx error */
4a55530f 1550 u32 edtrr = sh_eth_read(ndev, EDTRR);
86a74ff2 1551 /* dmesg */
380af9e3
YS		 1552 dev_err(&ndev->dev, "TX error. status=%8.8x cur_tx=%8.8x ",
1553 intr_status, mdp->cur_tx);
1554 dev_err(&ndev->dev, "dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
86a74ff2
NI		 1555 mdp->dirty_tx, (u32) ndev->state, edtrr);
1556 /* dirty buffer free */
1557 sh_eth_txfree(ndev);
1558
1559 /* SH7712 BUG */
c5ed5368 1560 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
86a74ff2 1561 /* tx dma start */
c5ed5368 1562 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
86a74ff2
NI		 1563 }
1564 /* wakeup */
1565 netif_wake_queue(ndev);
1566 }
1567}
1568
1569static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1570{
1571 struct net_device *ndev = netdev;
1572 struct sh_eth_private *mdp = netdev_priv(ndev);
380af9e3 1573 struct sh_eth_cpu_data *cd = mdp->cd;
0e0fde3c 1574 irqreturn_t ret = IRQ_NONE;
3893b273 1575 unsigned long intr_status;
86a74ff2 1576
86a74ff2
NI		 1577 spin_lock(&mdp->lock);
1578
3893b273 1579 /* Get interrupt status */
4a55530f 1580 intr_status = sh_eth_read(ndev, EESR);
3893b273
SS		 1581 /* Mask it with the interrupt mask, forcing ECI interrupt to be always
1582 * enabled since it's the one that comes thru regardless of the mask,
1583 * and we need to fully handle it in sh_eth_error() in order to quench
1584 * it as it doesn't get cleared by just writing 1 to the ECI bit...
1585 */
1586 intr_status &= sh_eth_read(ndev, EESIPR) | DMAC_M_ECI;
86a74ff2 1587 /* Clear interrupt */
0e0fde3c
NI		 1588 if (intr_status & (EESR_FRC | EESR_RMAF | EESR_RRF |
1589 EESR_RTLF | EESR_RTSF | EESR_PRE | EESR_CERF |
380af9e3 1590 cd->tx_check | cd->eesr_err_check)) {
4a55530f 1591 sh_eth_write(ndev, intr_status, EESR);
0e0fde3c
NI		 1592 ret = IRQ_HANDLED;
1593 } else
1594 goto other_irq;
86a74ff2 1595
b0ca2a21
NI		 1596 if (intr_status & (EESR_FRC | /* Frame recv*/
1597 EESR_RMAF | /* Multi cast address recv*/
1598 EESR_RRF | /* Bit frame recv */
1599 EESR_RTLF | /* Long frame recv*/
1600 EESR_RTSF | /* short frame recv */
1601 EESR_PRE | /* PHY-LSI recv error */
1602 EESR_CERF)){ /* recv frame CRC error */
a18e08bd 1603 sh_eth_rx(ndev, intr_status);
b0ca2a21 1604 }
86a74ff2 1605
b0ca2a21 1606 /* Tx Check */
380af9e3 1607 if (intr_status & cd->tx_check) {
86a74ff2
NI		 1608 sh_eth_txfree(ndev);
1609 netif_wake_queue(ndev);
1610 }
1611
380af9e3 1612 if (intr_status & cd->eesr_err_check)
86a74ff2
NI		 1613 sh_eth_error(ndev, intr_status);
1614
0e0fde3c 1615other_irq:
86a74ff2
NI		 1616 spin_unlock(&mdp->lock);
1617
0e0fde3c 1618 return ret;
86a74ff2
NI		 1619}
1620
86a74ff2
NI		 1621/* PHY state control function */
1622static void sh_eth_adjust_link(struct net_device *ndev)
1623{
1624 struct sh_eth_private *mdp = netdev_priv(ndev);
1625 struct phy_device *phydev = mdp->phydev;
86a74ff2
NI		 1626 int new_state = 0;
1627
3340d2aa 1628 if (phydev->link) {
86a74ff2
NI		 1629 if (phydev->duplex != mdp->duplex) {
1630 new_state = 1;
1631 mdp->duplex = phydev->duplex;
380af9e3
YS		 1632 if (mdp->cd->set_duplex)
1633 mdp->cd->set_duplex(ndev);
86a74ff2
NI		 1634 }
1635
1636 if (phydev->speed != mdp->speed) {
1637 new_state = 1;
1638 mdp->speed = phydev->speed;
380af9e3
YS		 1639 if (mdp->cd->set_rate)
1640 mdp->cd->set_rate(ndev);
86a74ff2 1641 }
3340d2aa 1642 if (!mdp->link) {
91a56152
YS		 1643 sh_eth_write(ndev,
1644 (sh_eth_read(ndev, ECMR) & ~ECMR_TXF), ECMR);
86a74ff2
NI		 1645 new_state = 1;
1646 mdp->link = phydev->link;
1e1b812b
SS		 1647 if (mdp->cd->no_psr || mdp->no_ether_link)
1648 sh_eth_rcv_snd_enable(ndev);
86a74ff2
NI		 1649 }
1650 } else if (mdp->link) {
1651 new_state = 1;
3340d2aa 1652 mdp->link = 0;
86a74ff2
NI		 1653 mdp->speed = 0;
1654 mdp->duplex = -1;
1e1b812b
SS		 1655 if (mdp->cd->no_psr || mdp->no_ether_link)
1656 sh_eth_rcv_snd_disable(ndev);
86a74ff2
NI		 1657 }
1658
dc19e4e5 1659 if (new_state && netif_msg_link(mdp))
86a74ff2
NI		 1660 phy_print_status(phydev);
1661}
1662
1663/* PHY init function */
1664static int sh_eth_phy_init(struct net_device *ndev)
1665{
1666 struct sh_eth_private *mdp = netdev_priv(ndev);
0a372eb9 1667 char phy_id[MII_BUS_ID_SIZE + 3];
86a74ff2
NI		 1668 struct phy_device *phydev = NULL;
1669
fb28ad35 1670 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
86a74ff2
NI		 1671 mdp->mii_bus->id , mdp->phy_id);
1672
3340d2aa 1673 mdp->link = 0;
86a74ff2
NI		 1674 mdp->speed = 0;
1675 mdp->duplex = -1;
1676
1677 /* Try connect to PHY */
c061b18d 1678 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
f9a8f83b 1679 mdp->phy_interface);
86a74ff2
NI		 1680 if (IS_ERR(phydev)) {
1681 dev_err(&ndev->dev, "phy_connect failed\n");
1682 return PTR_ERR(phydev);
1683 }
380af9e3 1684
86a74ff2 1685 dev_info(&ndev->dev, "attached phy %i to driver %s\n",
380af9e3 1686 phydev->addr, phydev->drv->name);
86a74ff2
NI		 1687
1688 mdp->phydev = phydev;
1689
1690 return 0;
1691}
1692
1693/* PHY control start function */
1694static int sh_eth_phy_start(struct net_device *ndev)
1695{
1696 struct sh_eth_private *mdp = netdev_priv(ndev);
1697 int ret;
1698
1699 ret = sh_eth_phy_init(ndev);
1700 if (ret)
1701 return ret;
1702
1703 /* reset phy - this also wakes it from PDOWN */
1704 phy_write(mdp->phydev, MII_BMCR, BMCR_RESET);
1705 phy_start(mdp->phydev);
1706
1707 return 0;
1708}
1709
dc19e4e5
NI		 1710static int sh_eth_get_settings(struct net_device *ndev,
1711 struct ethtool_cmd *ecmd)
1712{
1713 struct sh_eth_private *mdp = netdev_priv(ndev);
1714 unsigned long flags;
1715 int ret;
1716
1717 spin_lock_irqsave(&mdp->lock, flags);
1718 ret = phy_ethtool_gset(mdp->phydev, ecmd);
1719 spin_unlock_irqrestore(&mdp->lock, flags);
1720
1721 return ret;
1722}
1723
1724static int sh_eth_set_settings(struct net_device *ndev,
1725 struct ethtool_cmd *ecmd)
1726{
1727 struct sh_eth_private *mdp = netdev_priv(ndev);
1728 unsigned long flags;
1729 int ret;
dc19e4e5
NI		 1730
1731 spin_lock_irqsave(&mdp->lock, flags);
1732
1733 /* disable tx and rx */
4a55530f 1734 sh_eth_rcv_snd_disable(ndev);
dc19e4e5
NI		 1735
1736 ret = phy_ethtool_sset(mdp->phydev, ecmd);
1737 if (ret)
1738 goto error_exit;
1739
1740 if (ecmd->duplex == DUPLEX_FULL)
1741 mdp->duplex = 1;
1742 else
1743 mdp->duplex = 0;
1744
1745 if (mdp->cd->set_duplex)
1746 mdp->cd->set_duplex(ndev);
1747
1748error_exit:
1749 mdelay(1);
1750
1751 /* enable tx and rx */
4a55530f 1752 sh_eth_rcv_snd_enable(ndev);
dc19e4e5
NI		 1753
1754 spin_unlock_irqrestore(&mdp->lock, flags);
1755
1756 return ret;
1757}
1758
1759static int sh_eth_nway_reset(struct net_device *ndev)
1760{
1761 struct sh_eth_private *mdp = netdev_priv(ndev);
1762 unsigned long flags;
1763 int ret;
1764
1765 spin_lock_irqsave(&mdp->lock, flags);
1766 ret = phy_start_aneg(mdp->phydev);
1767 spin_unlock_irqrestore(&mdp->lock, flags);
1768
1769 return ret;
1770}
1771
1772static u32 sh_eth_get_msglevel(struct net_device *ndev)
1773{
1774 struct sh_eth_private *mdp = netdev_priv(ndev);
1775 return mdp->msg_enable;
1776}
1777
1778static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
1779{
1780 struct sh_eth_private *mdp = netdev_priv(ndev);
1781 mdp->msg_enable = value;
1782}
1783
1784static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
1785 "rx_current", "tx_current",
1786 "rx_dirty", "tx_dirty",
1787};
1788#define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats)
1789
1790static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
1791{
1792 switch (sset) {
1793 case ETH_SS_STATS:
1794 return SH_ETH_STATS_LEN;
1795 default:
1796 return -EOPNOTSUPP;
1797 }
1798}
1799
1800static void sh_eth_get_ethtool_stats(struct net_device *ndev,
1801 struct ethtool_stats *stats, u64 *data)
1802{
1803 struct sh_eth_private *mdp = netdev_priv(ndev);
1804 int i = 0;
1805
1806 /* device-specific stats */
1807 data[i++] = mdp->cur_rx;
1808 data[i++] = mdp->cur_tx;
1809 data[i++] = mdp->dirty_rx;
1810 data[i++] = mdp->dirty_tx;
1811}
1812
1813static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1814{
1815 switch (stringset) {
1816 case ETH_SS_STATS:
1817 memcpy(data, *sh_eth_gstrings_stats,
1818 sizeof(sh_eth_gstrings_stats));
1819 break;
1820 }
1821}
1822
525b8075
YS		 1823static void sh_eth_get_ringparam(struct net_device *ndev,
1824 struct ethtool_ringparam *ring)
1825{
1826 struct sh_eth_private *mdp = netdev_priv(ndev);
1827
1828 ring->rx_max_pending = RX_RING_MAX;
1829 ring->tx_max_pending = TX_RING_MAX;
1830 ring->rx_pending = mdp->num_rx_ring;
1831 ring->tx_pending = mdp->num_tx_ring;
1832}
1833
1834static int sh_eth_set_ringparam(struct net_device *ndev,
1835 struct ethtool_ringparam *ring)
1836{
1837 struct sh_eth_private *mdp = netdev_priv(ndev);
1838 int ret;
1839
1840 if (ring->tx_pending > TX_RING_MAX ||
1841 ring->rx_pending > RX_RING_MAX ||
1842 ring->tx_pending < TX_RING_MIN ||
1843 ring->rx_pending < RX_RING_MIN)
1844 return -EINVAL;
1845 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
1846 return -EINVAL;
1847
1848 if (netif_running(ndev)) {
1849 netif_tx_disable(ndev);
1850 /* Disable interrupts by clearing the interrupt mask. */
1851 sh_eth_write(ndev, 0x0000, EESIPR);
1852 /* Stop the chip's Tx and Rx processes. */
1853 sh_eth_write(ndev, 0, EDTRR);
1854 sh_eth_write(ndev, 0, EDRRR);
1855 synchronize_irq(ndev->irq);
1856 }
1857
1858 /* Free all the skbuffs in the Rx queue. */
1859 sh_eth_ring_free(ndev);
1860 /* Free DMA buffer */
1861 sh_eth_free_dma_buffer(mdp);
1862
1863 /* Set new parameters */
1864 mdp->num_rx_ring = ring->rx_pending;
1865 mdp->num_tx_ring = ring->tx_pending;
1866
1867 ret = sh_eth_ring_init(ndev);
1868 if (ret < 0) {
1869 dev_err(&ndev->dev, "%s: sh_eth_ring_init failed.\n", __func__);
1870 return ret;
1871 }
1872 ret = sh_eth_dev_init(ndev, false);
1873 if (ret < 0) {
1874 dev_err(&ndev->dev, "%s: sh_eth_dev_init failed.\n", __func__);
1875 return ret;
1876 }
1877
1878 if (netif_running(ndev)) {
1879 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1880 /* Setting the Rx mode will start the Rx process. */
1881 sh_eth_write(ndev, EDRRR_R, EDRRR);
1882 netif_wake_queue(ndev);
1883 }
1884
1885 return 0;
1886}
1887
9b07be4b 1888static const struct ethtool_ops sh_eth_ethtool_ops = {
dc19e4e5
NI		 1889 .get_settings = sh_eth_get_settings,
1890 .set_settings = sh_eth_set_settings,
9b07be4b 1891 .nway_reset = sh_eth_nway_reset,
dc19e4e5
NI		 1892 .get_msglevel = sh_eth_get_msglevel,
1893 .set_msglevel = sh_eth_set_msglevel,
9b07be4b 1894 .get_link = ethtool_op_get_link,
dc19e4e5
NI		 1895 .get_strings = sh_eth_get_strings,
1896 .get_ethtool_stats = sh_eth_get_ethtool_stats,
1897 .get_sset_count = sh_eth_get_sset_count,
525b8075
YS		 1898 .get_ringparam = sh_eth_get_ringparam,
1899 .set_ringparam = sh_eth_set_ringparam,
dc19e4e5
NI		 1900};
1901
86a74ff2
NI		 1902/* network device open function */
1903static int sh_eth_open(struct net_device *ndev)
1904{
1905 int ret = 0;
1906 struct sh_eth_private *mdp = netdev_priv(ndev);
1907
bcd5149d
MD		 1908 pm_runtime_get_sync(&mdp->pdev->dev);
1909
a0607fd3 1910 ret = request_irq(ndev->irq, sh_eth_interrupt,
f29a3d04 1911#if defined(CONFIG_CPU_SUBTYPE_SH7763) || \
dc19e4e5
NI		 1912 defined(CONFIG_CPU_SUBTYPE_SH7764) || \
1913 defined(CONFIG_CPU_SUBTYPE_SH7757)
0e0fde3c
NI		 1914 IRQF_SHARED,
1915#else
1916 0,
1917#endif
1918 ndev->name, ndev);
86a74ff2 1919 if (ret) {
380af9e3 1920 dev_err(&ndev->dev, "Can not assign IRQ number\n");
86a74ff2
NI		 1921 return ret;
1922 }
1923
1924 /* Descriptor set */
1925 ret = sh_eth_ring_init(ndev);
1926 if (ret)
1927 goto out_free_irq;
1928
1929 /* device init */
525b8075 1930 ret = sh_eth_dev_init(ndev, true);
86a74ff2
NI		 1931 if (ret)
1932 goto out_free_irq;
1933
1934 /* PHY control start*/
1935 ret = sh_eth_phy_start(ndev);
1936 if (ret)
1937 goto out_free_irq;
1938
86a74ff2
NI		 1939 return ret;
1940
1941out_free_irq:
1942 free_irq(ndev->irq, ndev);
bcd5149d 1943 pm_runtime_put_sync(&mdp->pdev->dev);
86a74ff2
NI		 1944 return ret;
1945}
1946
1947/* Timeout function */
1948static void sh_eth_tx_timeout(struct net_device *ndev)
1949{
1950 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 1951 struct sh_eth_rxdesc *rxdesc;
1952 int i;
1953
1954 netif_stop_queue(ndev);
1955
dc19e4e5
NI		 1956 if (netif_msg_timer(mdp))
1957 dev_err(&ndev->dev, "%s: transmit timed out, status %8.8x,"
4a55530f 1958 " resetting...\n", ndev->name, (int)sh_eth_read(ndev, EESR));
86a74ff2
NI		 1959
1960 /* tx_errors count up */
bb7d92e3 1961 ndev->stats.tx_errors++;
86a74ff2 1962
86a74ff2 1963 /* Free all the skbuffs in the Rx queue. */
525b8075 1964 for (i = 0; i < mdp->num_rx_ring; i++) {
86a74ff2
NI		 1965 rxdesc = &mdp->rx_ring[i];
1966 rxdesc->status = 0;
1967 rxdesc->addr = 0xBADF00D0;
1968 if (mdp->rx_skbuff[i])
1969 dev_kfree_skb(mdp->rx_skbuff[i]);
1970 mdp->rx_skbuff[i] = NULL;
1971 }
525b8075 1972 for (i = 0; i < mdp->num_tx_ring; i++) {
86a74ff2
NI		 1973 if (mdp->tx_skbuff[i])
1974 dev_kfree_skb(mdp->tx_skbuff[i]);
1975 mdp->tx_skbuff[i] = NULL;
1976 }
1977
1978 /* device init */
525b8075 1979 sh_eth_dev_init(ndev, true);
86a74ff2
NI		 1980}
1981
1982/* Packet transmit function */
1983static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1984{
1985 struct sh_eth_private *mdp = netdev_priv(ndev);
1986 struct sh_eth_txdesc *txdesc;
1987 u32 entry;
fb5e2f9b 1988 unsigned long flags;
86a74ff2
NI		 1989
1990 spin_lock_irqsave(&mdp->lock, flags);
525b8075 1991 if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
86a74ff2 1992 if (!sh_eth_txfree(ndev)) {
dc19e4e5
NI		 1993 if (netif_msg_tx_queued(mdp))
1994 dev_warn(&ndev->dev, "TxFD exhausted.\n");
86a74ff2
NI		 1995 netif_stop_queue(ndev);
1996 spin_unlock_irqrestore(&mdp->lock, flags);
5b548140 1997 return NETDEV_TX_BUSY;
86a74ff2
NI		 1998 }
1999 }
2000 spin_unlock_irqrestore(&mdp->lock, flags);
2001
525b8075 2002 entry = mdp->cur_tx % mdp->num_tx_ring;
86a74ff2
NI		 2003 mdp->tx_skbuff[entry] = skb;
2004 txdesc = &mdp->tx_ring[entry];
86a74ff2 2005 /* soft swap. */
380af9e3
YS		 2006 if (!mdp->cd->hw_swap)
2007 sh_eth_soft_swap(phys_to_virt(ALIGN(txdesc->addr, 4)),
2008 skb->len + 2);
31fcb99d
YS		 2009 txdesc->addr = dma_map_single(&ndev->dev, skb->data, skb->len,
2010 DMA_TO_DEVICE);
86a74ff2
NI		 2011 if (skb->len < ETHERSMALL)
2012 txdesc->buffer_length = ETHERSMALL;
2013 else
2014 txdesc->buffer_length = skb->len;
2015
525b8075 2016 if (entry >= mdp->num_tx_ring - 1)
71557a37 2017 txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE);
86a74ff2 2018 else
71557a37 2019 txdesc->status |= cpu_to_edmac(mdp, TD_TACT);
86a74ff2
NI		 2020
2021 mdp->cur_tx++;
2022
c5ed5368
YS		 2023 if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
2024 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
b0ca2a21 2025
6ed10654 2026 return NETDEV_TX_OK;
86a74ff2
NI		 2027}
2028
2029/* device close function */
2030static int sh_eth_close(struct net_device *ndev)
2031{
2032 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 2033
2034 netif_stop_queue(ndev);
2035
2036 /* Disable interrupts by clearing the interrupt mask. */
4a55530f 2037 sh_eth_write(ndev, 0x0000, EESIPR);
86a74ff2
NI		 2038
2039 /* Stop the chip's Tx and Rx processes. */
4a55530f
YS		 2040 sh_eth_write(ndev, 0, EDTRR);
2041 sh_eth_write(ndev, 0, EDRRR);
86a74ff2
NI		 2042
2043 /* PHY Disconnect */
2044 if (mdp->phydev) {
2045 phy_stop(mdp->phydev);
2046 phy_disconnect(mdp->phydev);
2047 }
2048
2049 free_irq(ndev->irq, ndev);
2050
86a74ff2
NI		 2051 /* Free all the skbuffs in the Rx queue. */
2052 sh_eth_ring_free(ndev);
2053
2054 /* free DMA buffer */
91c77550 2055 sh_eth_free_dma_buffer(mdp);
86a74ff2 2056
bcd5149d
MD		 2057 pm_runtime_put_sync(&mdp->pdev->dev);
2058
86a74ff2
NI		 2059 return 0;
2060}
2061
2062static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
2063{
2064 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2 2065
bcd5149d
MD		 2066 pm_runtime_get_sync(&mdp->pdev->dev);
2067
bb7d92e3 2068 ndev->stats.tx_dropped += sh_eth_read(ndev, TROCR);
4a55530f 2069 sh_eth_write(ndev, 0, TROCR); /* (write clear) */
bb7d92e3 2070 ndev->stats.collisions += sh_eth_read(ndev, CDCR);
4a55530f 2071 sh_eth_write(ndev, 0, CDCR); /* (write clear) */
bb7d92e3 2072 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, LCCR);
4a55530f 2073 sh_eth_write(ndev, 0, LCCR); /* (write clear) */
c5ed5368 2074 if (sh_eth_is_gether(mdp)) {
bb7d92e3 2075 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CERCR);
c5ed5368 2076 sh_eth_write(ndev, 0, CERCR); /* (write clear) */
bb7d92e3 2077 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CEECR);
c5ed5368
YS		 2078 sh_eth_write(ndev, 0, CEECR); /* (write clear) */
2079 } else {
bb7d92e3 2080 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CNDCR);
c5ed5368
YS		 2081 sh_eth_write(ndev, 0, CNDCR); /* (write clear) */
2082 }
bcd5149d
MD		 2083 pm_runtime_put_sync(&mdp->pdev->dev);
2084
bb7d92e3 2085 return &ndev->stats;
86a74ff2
NI		 2086}
2087
bb7d92e3 2088/* ioctl to device function */
86a74ff2
NI		 2089static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq,
2090 int cmd)
2091{
2092 struct sh_eth_private *mdp = netdev_priv(ndev);
2093 struct phy_device *phydev = mdp->phydev;
2094
2095 if (!netif_running(ndev))
2096 return -EINVAL;
2097
2098 if (!phydev)
2099 return -ENODEV;
2100
28b04113 2101 return phy_mii_ioctl(phydev, rq, cmd);
86a74ff2
NI		 2102}
2103
6743fe6d
YS		 2104/* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
2105static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp,
2106 int entry)
2107{
2108 return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4);
2109}
2110
2111static u32 sh_eth_tsu_get_post_mask(int entry)
2112{
2113 return 0x0f << (28 - ((entry % 8) * 4));
2114}
2115
2116static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
2117{
2118 return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
2119}
2120
2121static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
2122 int entry)
2123{
2124 struct sh_eth_private *mdp = netdev_priv(ndev);
2125 u32 tmp;
2126 void *reg_offset;
2127
2128 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2129 tmp = ioread32(reg_offset);
2130 iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset);
2131}
2132
2133static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
2134 int entry)
2135{
2136 struct sh_eth_private *mdp = netdev_priv(ndev);
2137 u32 post_mask, ref_mask, tmp;
2138 void *reg_offset;
2139
2140 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2141 post_mask = sh_eth_tsu_get_post_mask(entry);
2142 ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
2143
2144 tmp = ioread32(reg_offset);
2145 iowrite32(tmp & ~post_mask, reg_offset);
2146
2147 /* If other port enables, the function returns "true" */
2148 return tmp & ref_mask;
2149}
2150
2151static int sh_eth_tsu_busy(struct net_device *ndev)
2152{
2153 int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
2154 struct sh_eth_private *mdp = netdev_priv(ndev);
2155
2156 while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
2157 udelay(10);
2158 timeout--;
2159 if (timeout <= 0) {
2160 dev_err(&ndev->dev, "%s: timeout\n", __func__);
2161 return -ETIMEDOUT;
2162 }
2163 }
2164
2165 return 0;
2166}
2167
2168static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg,
2169 const u8 *addr)
2170{
2171 u32 val;
2172
2173 val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
2174 iowrite32(val, reg);
2175 if (sh_eth_tsu_busy(ndev) < 0)
2176 return -EBUSY;
2177
2178 val = addr[4] << 8 | addr[5];
2179 iowrite32(val, reg + 4);
2180 if (sh_eth_tsu_busy(ndev) < 0)
2181 return -EBUSY;
2182
2183 return 0;
2184}
2185
2186static void sh_eth_tsu_read_entry(void *reg, u8 *addr)
2187{
2188 u32 val;
2189
2190 val = ioread32(reg);
2191 addr[0] = (val >> 24) & 0xff;
2192 addr[1] = (val >> 16) & 0xff;
2193 addr[2] = (val >> 8) & 0xff;
2194 addr[3] = val & 0xff;
2195 val = ioread32(reg + 4);
2196 addr[4] = (val >> 8) & 0xff;
2197 addr[5] = val & 0xff;
2198}
2199
2200
2201static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
2202{
2203 struct sh_eth_private *mdp = netdev_priv(ndev);
2204 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2205 int i;
2206 u8 c_addr[ETH_ALEN];
2207
2208 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2209 sh_eth_tsu_read_entry(reg_offset, c_addr);
2210 if (memcmp(addr, c_addr, ETH_ALEN) == 0)
2211 return i;
2212 }
2213
2214 return -ENOENT;
2215}
2216
2217static int sh_eth_tsu_find_empty(struct net_device *ndev)
2218{
2219 u8 blank[ETH_ALEN];
2220 int entry;
2221
2222 memset(blank, 0, sizeof(blank));
2223 entry = sh_eth_tsu_find_entry(ndev, blank);
2224 return (entry < 0) ? -ENOMEM : entry;
2225}
2226
2227static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
2228 int entry)
2229{
2230 struct sh_eth_private *mdp = netdev_priv(ndev);
2231 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2232 int ret;
2233 u8 blank[ETH_ALEN];
2234
2235 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
2236 ~(1 << (31 - entry)), TSU_TEN);
2237
2238 memset(blank, 0, sizeof(blank));
2239 ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
2240 if (ret < 0)
2241 return ret;
2242 return 0;
2243}
2244
2245static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
2246{
2247 struct sh_eth_private *mdp = netdev_priv(ndev);
2248 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2249 int i, ret;
2250
2251 if (!mdp->cd->tsu)
2252 return 0;
2253
2254 i = sh_eth_tsu_find_entry(ndev, addr);
2255 if (i < 0) {
2256 /* No entry found, create one */
2257 i = sh_eth_tsu_find_empty(ndev);
2258 if (i < 0)
2259 return -ENOMEM;
2260 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
2261 if (ret < 0)
2262 return ret;
2263
2264 /* Enable the entry */
2265 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
2266 (1 << (31 - i)), TSU_TEN);
2267 }
2268
2269 /* Entry found or created, enable POST */
2270 sh_eth_tsu_enable_cam_entry_post(ndev, i);
2271
2272 return 0;
2273}
2274
2275static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
2276{
2277 struct sh_eth_private *mdp = netdev_priv(ndev);
2278 int i, ret;
2279
2280 if (!mdp->cd->tsu)
2281 return 0;
2282
2283 i = sh_eth_tsu_find_entry(ndev, addr);
2284 if (i) {
2285 /* Entry found */
2286 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2287 goto done;
2288
2289 /* Disable the entry if both ports was disabled */
2290 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2291 if (ret < 0)
2292 return ret;
2293 }
2294done:
2295 return 0;
2296}
2297
2298static int sh_eth_tsu_purge_all(struct net_device *ndev)
2299{
2300 struct sh_eth_private *mdp = netdev_priv(ndev);
2301 int i, ret;
2302
2303 if (unlikely(!mdp->cd->tsu))
2304 return 0;
2305
2306 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
2307 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2308 continue;
2309
2310 /* Disable the entry if both ports was disabled */
2311 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2312 if (ret < 0)
2313 return ret;
2314 }
2315
2316 return 0;
2317}
2318
2319static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
2320{
2321 struct sh_eth_private *mdp = netdev_priv(ndev);
2322 u8 addr[ETH_ALEN];
2323 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2324 int i;
2325
2326 if (unlikely(!mdp->cd->tsu))
2327 return;
2328
2329 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2330 sh_eth_tsu_read_entry(reg_offset, addr);
2331 if (is_multicast_ether_addr(addr))
2332 sh_eth_tsu_del_entry(ndev, addr);
2333 }
2334}
2335
86a74ff2
NI		 2336/* Multicast reception directions set */
2337static void sh_eth_set_multicast_list(struct net_device *ndev)
2338{
6743fe6d
YS		 2339 struct sh_eth_private *mdp = netdev_priv(ndev);
2340 u32 ecmr_bits;
2341 int mcast_all = 0;
2342 unsigned long flags;
2343
2344 spin_lock_irqsave(&mdp->lock, flags);
2345 /*
2346 * Initial condition is MCT = 1, PRM = 0.
2347 * Depending on ndev->flags, set PRM or clear MCT
2348 */
2349 ecmr_bits = (sh_eth_read(ndev, ECMR) & ~ECMR_PRM) | ECMR_MCT;
2350
2351 if (!(ndev->flags & IFF_MULTICAST)) {
2352 sh_eth_tsu_purge_mcast(ndev);
2353 mcast_all = 1;
2354 }
2355 if (ndev->flags & IFF_ALLMULTI) {
2356 sh_eth_tsu_purge_mcast(ndev);
2357 ecmr_bits &= ~ECMR_MCT;
2358 mcast_all = 1;
2359 }
2360
86a74ff2 2361 if (ndev->flags & IFF_PROMISC) {
6743fe6d
YS		 2362 sh_eth_tsu_purge_all(ndev);
2363 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2364 } else if (mdp->cd->tsu) {
2365 struct netdev_hw_addr *ha;
2366 netdev_for_each_mc_addr(ha, ndev) {
2367 if (mcast_all && is_multicast_ether_addr(ha->addr))
2368 continue;
2369
2370 if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2371 if (!mcast_all) {
2372 sh_eth_tsu_purge_mcast(ndev);
2373 ecmr_bits &= ~ECMR_MCT;
2374 mcast_all = 1;
2375 }
2376 }
2377 }
86a74ff2
NI		 2378 } else {
2379 /* Normal, unicast/broadcast-only mode. */
6743fe6d 2380 ecmr_bits = (ecmr_bits & ~ECMR_PRM) | ECMR_MCT;
86a74ff2 2381 }
6743fe6d
YS		 2382
2383 /* update the ethernet mode */
2384 sh_eth_write(ndev, ecmr_bits, ECMR);
2385
2386 spin_unlock_irqrestore(&mdp->lock, flags);
86a74ff2 2387}
71cc7c37
YS		 2388
2389static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2390{
2391 if (!mdp->port)
2392 return TSU_VTAG0;
2393 else
2394 return TSU_VTAG1;
2395}
2396
80d5c368
PM		 2397static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
2398 __be16 proto, u16 vid)
71cc7c37
YS		 2399{
2400 struct sh_eth_private *mdp = netdev_priv(ndev);
2401 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2402
2403 if (unlikely(!mdp->cd->tsu))
2404 return -EPERM;
2405
2406 /* No filtering if vid = 0 */
2407 if (!vid)
2408 return 0;
2409
2410 mdp->vlan_num_ids++;
2411
2412 /*
2413 * The controller has one VLAN tag HW filter. So, if the filter is
2414 * already enabled, the driver disables it and the filte
2415 */
2416 if (mdp->vlan_num_ids > 1) {
2417 /* disable VLAN filter */
2418 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2419 return 0;
2420 }
2421
2422 sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
2423 vtag_reg_index);
2424
2425 return 0;
2426}
2427
80d5c368
PM		 2428static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
2429 __be16 proto, u16 vid)
71cc7c37
YS		 2430{
2431 struct sh_eth_private *mdp = netdev_priv(ndev);
2432 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2433
2434 if (unlikely(!mdp->cd->tsu))
2435 return -EPERM;
2436
2437 /* No filtering if vid = 0 */
2438 if (!vid)
2439 return 0;
2440
2441 mdp->vlan_num_ids--;
2442 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2443
2444 return 0;
2445}
86a74ff2
NI		 2446
2447/* SuperH's TSU register init function */
4a55530f 2448static void sh_eth_tsu_init(struct sh_eth_private *mdp)
86a74ff2 2449{
4a55530f
YS		 2450 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */
2451 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */
2452 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */
2453 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
2454 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
2455 sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
2456 sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
2457 sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
2458 sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
2459 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
c5ed5368
YS		 2460 if (sh_eth_is_gether(mdp)) {
2461 sh_eth_tsu_write(mdp, 0, TSU_QTAG0); /* Disable QTAG(0->1) */
2462 sh_eth_tsu_write(mdp, 0, TSU_QTAG1); /* Disable QTAG(1->0) */
2463 } else {
2464 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */
2465 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */
2466 }
4a55530f
YS		 2467 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */
2468 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */
2469 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2470 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */
2471 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */
2472 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */
2473 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */
86a74ff2
NI		 2474}
2475
2476/* MDIO bus release function */
2477static int sh_mdio_release(struct net_device *ndev)
2478{
2479 struct mii_bus *bus = dev_get_drvdata(&ndev->dev);
2480
2481 /* unregister mdio bus */
2482 mdiobus_unregister(bus);
2483
2484 /* remove mdio bus info from net_device */
2485 dev_set_drvdata(&ndev->dev, NULL);
2486
2487 /* free bitbang info */
2488 free_mdio_bitbang(bus);
2489
2490 return 0;
2491}
2492
2493/* MDIO bus init function */
b3017e6a
YS		 2494static int sh_mdio_init(struct net_device *ndev, int id,
2495 struct sh_eth_plat_data *pd)
86a74ff2
NI		 2496{
2497 int ret, i;
2498 struct bb_info *bitbang;
2499 struct sh_eth_private *mdp = netdev_priv(ndev);
2500
2501 /* create bit control struct for PHY */
d5e07e69
SS		 2502 bitbang = devm_kzalloc(&ndev->dev, sizeof(struct bb_info),
2503 GFP_KERNEL);
86a74ff2
NI		 2504 if (!bitbang) {
2505 ret = -ENOMEM;
2506 goto out;
2507 }
2508
2509 /* bitbang init */
ae70644d 2510 bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
b3017e6a 2511 bitbang->set_gate = pd->set_mdio_gate;
dfed5e7f
SS		 2512 bitbang->mdi_msk = PIR_MDI;
2513 bitbang->mdo_msk = PIR_MDO;
2514 bitbang->mmd_msk = PIR_MMD;
2515 bitbang->mdc_msk = PIR_MDC;
86a74ff2
NI		 2516 bitbang->ctrl.ops = &bb_ops;
2517
c2e07b3a 2518 /* MII controller setting */
86a74ff2
NI		 2519 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
2520 if (!mdp->mii_bus) {
2521 ret = -ENOMEM;
d5e07e69 2522 goto out;
86a74ff2
NI		 2523 }
2524
2525 /* Hook up MII support for ethtool */
2526 mdp->mii_bus->name = "sh_mii";
18ee49dd 2527 mdp->mii_bus->parent = &ndev->dev;
5278fb54 2528 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
34aa6f14 2529 mdp->pdev->name, id);
86a74ff2
NI		 2530
2531 /* PHY IRQ */
d5e07e69
SS		 2532 mdp->mii_bus->irq = devm_kzalloc(&ndev->dev,
2533 sizeof(int) * PHY_MAX_ADDR,
2534 GFP_KERNEL);
86a74ff2
NI		 2535 if (!mdp->mii_bus->irq) {
2536 ret = -ENOMEM;
2537 goto out_free_bus;
2538 }
2539
2540 for (i = 0; i < PHY_MAX_ADDR; i++)
2541 mdp->mii_bus->irq[i] = PHY_POLL;
2542
8f6352f2 2543 /* register mdio bus */
86a74ff2
NI		 2544 ret = mdiobus_register(mdp->mii_bus);
2545 if (ret)
d5e07e69 2546 goto out_free_bus;
86a74ff2
NI		 2547
2548 dev_set_drvdata(&ndev->dev, mdp->mii_bus);
2549
2550 return 0;
2551
86a74ff2 2552out_free_bus:
298cf9be 2553 free_mdio_bitbang(mdp->mii_bus);
86a74ff2 2554
86a74ff2
NI		 2555out:
2556 return ret;
2557}
2558
4a55530f
YS		 2559static const u16 *sh_eth_get_register_offset(int register_type)
2560{
2561 const u16 *reg_offset = NULL;
2562
2563 switch (register_type) {
2564 case SH_ETH_REG_GIGABIT:
2565 reg_offset = sh_eth_offset_gigabit;
2566 break;
a3f109bd
SS		 2567 case SH_ETH_REG_FAST_RCAR:
2568 reg_offset = sh_eth_offset_fast_rcar;
2569 break;
4a55530f
YS		 2570 case SH_ETH_REG_FAST_SH4:
2571 reg_offset = sh_eth_offset_fast_sh4;
2572 break;
2573 case SH_ETH_REG_FAST_SH3_SH2:
2574 reg_offset = sh_eth_offset_fast_sh3_sh2;
2575 break;
2576 default:
14c3326a 2577 pr_err("Unknown register type (%d)\n", register_type);
4a55530f
YS		 2578 break;
2579 }
2580
2581 return reg_offset;
2582}
2583
9f861341 2584static struct net_device_ops sh_eth_netdev_ops = {
ebf84eaa
AB		 2585 .ndo_open = sh_eth_open,
2586 .ndo_stop = sh_eth_close,
2587 .ndo_start_xmit = sh_eth_start_xmit,
2588 .ndo_get_stats = sh_eth_get_stats,
ebf84eaa
AB		 2589 .ndo_tx_timeout = sh_eth_tx_timeout,
2590 .ndo_do_ioctl = sh_eth_do_ioctl,
2591 .ndo_validate_addr = eth_validate_addr,
2592 .ndo_set_mac_address = eth_mac_addr,
2593 .ndo_change_mtu = eth_change_mtu,
2594};
2595
86a74ff2
NI		 2596static int sh_eth_drv_probe(struct platform_device *pdev)
2597{
9c38657c 2598 int ret, devno = 0;
86a74ff2
NI		 2599 struct resource *res;
2600 struct net_device *ndev = NULL;
ec0d7551 2601 struct sh_eth_private *mdp = NULL;
564044b0 2602 struct sh_eth_plat_data *pd = pdev->dev.platform_data;
86a74ff2
NI		 2603
2604 /* get base addr */
2605 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2606 if (unlikely(res == NULL)) {
2607 dev_err(&pdev->dev, "invalid resource\n");
2608 ret = -EINVAL;
2609 goto out;
2610 }
2611
2612 ndev = alloc_etherdev(sizeof(struct sh_eth_private));
2613 if (!ndev) {
86a74ff2
NI		 2614 ret = -ENOMEM;
2615 goto out;
2616 }
2617
2618 /* The sh Ether-specific entries in the device structure. */
2619 ndev->base_addr = res->start;
2620 devno = pdev->id;
2621 if (devno < 0)
2622 devno = 0;
2623
2624 ndev->dma = -1;
cc3c080d 2625 ret = platform_get_irq(pdev, 0);
2626 if (ret < 0) {
86a74ff2
NI		 2627 ret = -ENODEV;
2628 goto out_release;
2629 }
cc3c080d 2630 ndev->irq = ret;
86a74ff2
NI		 2631
2632 SET_NETDEV_DEV(ndev, &pdev->dev);
2633
2634 /* Fill in the fields of the device structure with ethernet values. */
2635 ether_setup(ndev);
2636
2637 mdp = netdev_priv(ndev);
525b8075
YS		 2638 mdp->num_tx_ring = TX_RING_SIZE;
2639 mdp->num_rx_ring = RX_RING_SIZE;
d5e07e69
SS		 2640 mdp->addr = devm_ioremap_resource(&pdev->dev, res);
2641 if (IS_ERR(mdp->addr)) {
2642 ret = PTR_ERR(mdp->addr);
ae70644d
YS		 2643 goto out_release;
2644 }
2645
86a74ff2 2646 spin_lock_init(&mdp->lock);
bcd5149d
MD		 2647 mdp->pdev = pdev;
2648 pm_runtime_enable(&pdev->dev);
2649 pm_runtime_resume(&pdev->dev);
86a74ff2
NI		 2650
2651 /* get PHY ID */
71557a37 2652 mdp->phy_id = pd->phy;
e47c9052 2653 mdp->phy_interface = pd->phy_interface;
71557a37
YS		 2654 /* EDMAC endian */
2655 mdp->edmac_endian = pd->edmac_endian;
4923576b
YS		 2656 mdp->no_ether_link = pd->no_ether_link;
2657 mdp->ether_link_active_low = pd->ether_link_active_low;
4a55530f 2658 mdp->reg_offset = sh_eth_get_register_offset(pd->register_type);
86a74ff2 2659
380af9e3 2660 /* set cpu data */
8fcd4961
YS		 2661#if defined(SH_ETH_HAS_BOTH_MODULES)
2662 mdp->cd = sh_eth_get_cpu_data(mdp);
2663#else
380af9e3 2664 mdp->cd = &sh_eth_my_cpu_data;
8fcd4961 2665#endif
380af9e3
YS		 2666 sh_eth_set_default_cpu_data(mdp->cd);
2667
86a74ff2 2668 /* set function */
9f861341
NI		 2669 if (mdp->cd->tsu) {
2670 sh_eth_netdev_ops.ndo_set_rx_mode = sh_eth_set_multicast_list;
2671 sh_eth_netdev_ops.ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid;
2672 sh_eth_netdev_ops.ndo_vlan_rx_kill_vid =
2673 sh_eth_vlan_rx_kill_vid;
2674 }
2675
ebf84eaa 2676 ndev->netdev_ops = &sh_eth_netdev_ops;
dc19e4e5 2677 SET_ETHTOOL_OPS(ndev, &sh_eth_ethtool_ops);
86a74ff2
NI		 2678 ndev->watchdog_timeo = TX_TIMEOUT;
2679
dc19e4e5
NI		 2680 /* debug message level */
2681 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
86a74ff2
NI		 2682
2683 /* read and set MAC address */
748031f9 2684 read_mac_address(ndev, pd->mac_addr);
ff6e7228
SS		 2685 if (!is_valid_ether_addr(ndev->dev_addr)) {
2686 dev_warn(&pdev->dev,
2687 "no valid MAC address supplied, using a random one.\n");
2688 eth_hw_addr_random(ndev);
2689 }
86a74ff2 2690
6ba88021
YS		 2691 /* ioremap the TSU registers */
2692 if (mdp->cd->tsu) {
2693 struct resource *rtsu;
2694 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
d5e07e69
SS		 2695 mdp->tsu_addr = devm_ioremap_resource(&pdev->dev, rtsu);
2696 if (IS_ERR(mdp->tsu_addr)) {
2697 ret = PTR_ERR(mdp->tsu_addr);
fc0c0900
SS		 2698 goto out_release;
2699 }
6743fe6d 2700 mdp->port = devno % 2;
f646968f 2701 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER;
6ba88021
YS		 2702 }
2703
150647fb
YS		 2704 /* initialize first or needed device */
2705 if (!devno || pd->needs_init) {
380af9e3
YS		 2706 if (mdp->cd->chip_reset)
2707 mdp->cd->chip_reset(ndev);
86a74ff2 2708
4986b996
YS		 2709 if (mdp->cd->tsu) {
2710 /* TSU init (Init only)*/
2711 sh_eth_tsu_init(mdp);
2712 }
86a74ff2
NI		 2713 }
2714
2715 /* network device register */
2716 ret = register_netdev(ndev);
2717 if (ret)
2718 goto out_release;
2719
2720 /* mdio bus init */
b3017e6a 2721 ret = sh_mdio_init(ndev, pdev->id, pd);
86a74ff2
NI		 2722 if (ret)
2723 goto out_unregister;
2724
25985edc 2725 /* print device information */
6cd9b49d
HS		 2726 pr_info("Base address at 0x%x, %pM, IRQ %d.\n",
2727 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
86a74ff2
NI		 2728
2729 platform_set_drvdata(pdev, ndev);
2730
2731 return ret;
2732
2733out_unregister:
2734 unregister_netdev(ndev);
2735
2736out_release:
2737 /* net_dev free */
2738 if (ndev)
2739 free_netdev(ndev);
2740
2741out:
2742 return ret;
2743}
2744
2745static int sh_eth_drv_remove(struct platform_device *pdev)
2746{
2747 struct net_device *ndev = platform_get_drvdata(pdev);
2748
2749 sh_mdio_release(ndev);
2750 unregister_netdev(ndev);
bcd5149d 2751 pm_runtime_disable(&pdev->dev);
86a74ff2 2752 free_netdev(ndev);
86a74ff2
NI		 2753
2754 return 0;
2755}
2756
bcd5149d
MD		 2757static int sh_eth_runtime_nop(struct device *dev)
2758{
2759 /*
2760 * Runtime PM callback shared between ->runtime_suspend()
2761 * and ->runtime_resume(). Simply returns success.
2762 *
2763 * This driver re-initializes all registers after
2764 * pm_runtime_get_sync() anyway so there is no need
2765 * to save and restore registers here.
2766 */
2767 return 0;
2768}
2769
2770static struct dev_pm_ops sh_eth_dev_pm_ops = {
2771 .runtime_suspend = sh_eth_runtime_nop,
2772 .runtime_resume = sh_eth_runtime_nop,
2773};
2774
86a74ff2
NI		 2775static struct platform_driver sh_eth_driver = {
2776 .probe = sh_eth_drv_probe,
2777 .remove = sh_eth_drv_remove,
2778 .driver = {
2779 .name = CARDNAME,
bcd5149d 2780 .pm = &sh_eth_dev_pm_ops,
86a74ff2
NI		 2781 },
2782};
2783
db62f684 2784module_platform_driver(sh_eth_driver);
86a74ff2
NI		 2785
2786MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
2787MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
2788MODULE_LICENSE("GPL v2");
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