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sh_eth: uninline sh_eth_soft_swap()
[mirror_ubuntu-hirsute-kernel.git] / drivers / net / ethernet / renesas / sh_eth.c
CommitLineData
128296fc 1/* SuperH Ethernet device driver
86a74ff2 2 *
9b39f05c 3 * Copyright (C) 2014 Renesas Electronics Corporation
f0e81fec 4 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu
b356e978 5 * Copyright (C) 2008-2014 Renesas Solutions Corp.
9b39f05c 6 * Copyright (C) 2013-2017 Cogent Embedded, Inc.
702eca02 7 * Copyright (C) 2014 Codethink Limited
86a74ff2
NI		 8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms and conditions of the GNU General Public License,
11 * version 2, as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
86a74ff2
NI		 17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 */
21
0654011d
YS		 22#include <linux/module.h>
23#include <linux/kernel.h>
24#include <linux/spinlock.h>
6a27cded 25#include <linux/interrupt.h>
86a74ff2
NI		 26#include <linux/dma-mapping.h>
27#include <linux/etherdevice.h>
28#include <linux/delay.h>
29#include <linux/platform_device.h>
30#include <linux/mdio-bitbang.h>
31#include <linux/netdevice.h>
b356e978
SS		 32#include <linux/of.h>
33#include <linux/of_device.h>
34#include <linux/of_irq.h>
35#include <linux/of_net.h>
86a74ff2
NI		 36#include <linux/phy.h>
37#include <linux/cache.h>
38#include <linux/io.h>
bcd5149d 39#include <linux/pm_runtime.h>
5a0e3ad6 40#include <linux/slab.h>
dc19e4e5 41#include <linux/ethtool.h>
fdb37a7f 42#include <linux/if_vlan.h>
d4fa0e35 43#include <linux/sh_eth.h>
702eca02 44#include <linux/of_mdio.h>
86a74ff2
NI		 45
46#include "sh_eth.h"
47
dc19e4e5
NI		 48#define SH_ETH_DEF_MSG_ENABLE \
49 (NETIF_MSG_LINK | \
50 NETIF_MSG_TIMER | \
51 NETIF_MSG_RX_ERR| \
52 NETIF_MSG_TX_ERR)
53
2274d375
SS		 54#define SH_ETH_OFFSET_INVALID ((u16)~0)
55
3365711d
BH		 56#define SH_ETH_OFFSET_DEFAULTS \
57 [0 ... SH_ETH_MAX_REGISTER_OFFSET - 1] = SH_ETH_OFFSET_INVALID
58
c0013f6f 59static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
3365711d
BH		 60 SH_ETH_OFFSET_DEFAULTS,
61
c0013f6f
SS		 62 [EDSR] = 0x0000,
63 [EDMR] = 0x0400,
64 [EDTRR] = 0x0408,
65 [EDRRR] = 0x0410,
66 [EESR] = 0x0428,
67 [EESIPR] = 0x0430,
68 [TDLAR] = 0x0010,
69 [TDFAR] = 0x0014,
70 [TDFXR] = 0x0018,
71 [TDFFR] = 0x001c,
72 [RDLAR] = 0x0030,
73 [RDFAR] = 0x0034,
74 [RDFXR] = 0x0038,
75 [RDFFR] = 0x003c,
76 [TRSCER] = 0x0438,
77 [RMFCR] = 0x0440,
78 [TFTR] = 0x0448,
79 [FDR] = 0x0450,
80 [RMCR] = 0x0458,
81 [RPADIR] = 0x0460,
82 [FCFTR] = 0x0468,
83 [CSMR] = 0x04E4,
84
85 [ECMR] = 0x0500,
86 [ECSR] = 0x0510,
87 [ECSIPR] = 0x0518,
88 [PIR] = 0x0520,
89 [PSR] = 0x0528,
90 [PIPR] = 0x052c,
91 [RFLR] = 0x0508,
92 [APR] = 0x0554,
93 [MPR] = 0x0558,
94 [PFTCR] = 0x055c,
95 [PFRCR] = 0x0560,
96 [TPAUSER] = 0x0564,
97 [GECMR] = 0x05b0,
98 [BCULR] = 0x05b4,
99 [MAHR] = 0x05c0,
100 [MALR] = 0x05c8,
101 [TROCR] = 0x0700,
102 [CDCR] = 0x0708,
103 [LCCR] = 0x0710,
104 [CEFCR] = 0x0740,
105 [FRECR] = 0x0748,
106 [TSFRCR] = 0x0750,
107 [TLFRCR] = 0x0758,
108 [RFCR] = 0x0760,
109 [CERCR] = 0x0768,
110 [CEECR] = 0x0770,
111 [MAFCR] = 0x0778,
112 [RMII_MII] = 0x0790,
113
114 [ARSTR] = 0x0000,
115 [TSU_CTRST] = 0x0004,
116 [TSU_FWEN0] = 0x0010,
117 [TSU_FWEN1] = 0x0014,
118 [TSU_FCM] = 0x0018,
119 [TSU_BSYSL0] = 0x0020,
120 [TSU_BSYSL1] = 0x0024,
121 [TSU_PRISL0] = 0x0028,
122 [TSU_PRISL1] = 0x002c,
123 [TSU_FWSL0] = 0x0030,
124 [TSU_FWSL1] = 0x0034,
125 [TSU_FWSLC] = 0x0038,
4869a147
SS		 126 [TSU_QTAGM0] = 0x0040,
127 [TSU_QTAGM1] = 0x0044,
c0013f6f
SS		 128 [TSU_FWSR] = 0x0050,
129 [TSU_FWINMK] = 0x0054,
130 [TSU_ADQT0] = 0x0048,
131 [TSU_ADQT1] = 0x004c,
132 [TSU_VTAG0] = 0x0058,
133 [TSU_VTAG1] = 0x005c,
134 [TSU_ADSBSY] = 0x0060,
135 [TSU_TEN] = 0x0064,
136 [TSU_POST1] = 0x0070,
137 [TSU_POST2] = 0x0074,
138 [TSU_POST3] = 0x0078,
139 [TSU_POST4] = 0x007c,
140 [TSU_ADRH0] = 0x0100,
c0013f6f
SS		 141
142 [TXNLCR0] = 0x0080,
143 [TXALCR0] = 0x0084,
144 [RXNLCR0] = 0x0088,
145 [RXALCR0] = 0x008c,
146 [FWNLCR0] = 0x0090,
147 [FWALCR0] = 0x0094,
148 [TXNLCR1] = 0x00a0,
50f3d740 149 [TXALCR1] = 0x00a4,
c0013f6f
SS		 150 [RXNLCR1] = 0x00a8,
151 [RXALCR1] = 0x00ac,
152 [FWNLCR1] = 0x00b0,
153 [FWALCR1] = 0x00b4,
154};
155
db893473 156static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
3365711d
BH		 157 SH_ETH_OFFSET_DEFAULTS,
158
db893473
SH		 159 [EDSR] = 0x0000,
160 [EDMR] = 0x0400,
161 [EDTRR] = 0x0408,
162 [EDRRR] = 0x0410,
163 [EESR] = 0x0428,
164 [EESIPR] = 0x0430,
165 [TDLAR] = 0x0010,
166 [TDFAR] = 0x0014,
167 [TDFXR] = 0x0018,
168 [TDFFR] = 0x001c,
169 [RDLAR] = 0x0030,
170 [RDFAR] = 0x0034,
171 [RDFXR] = 0x0038,
172 [RDFFR] = 0x003c,
173 [TRSCER] = 0x0438,
174 [RMFCR] = 0x0440,
175 [TFTR] = 0x0448,
176 [FDR] = 0x0450,
177 [RMCR] = 0x0458,
178 [RPADIR] = 0x0460,
179 [FCFTR] = 0x0468,
180 [CSMR] = 0x04E4,
181
182 [ECMR] = 0x0500,
183 [RFLR] = 0x0508,
184 [ECSR] = 0x0510,
185 [ECSIPR] = 0x0518,
186 [PIR] = 0x0520,
187 [APR] = 0x0554,
188 [MPR] = 0x0558,
189 [PFTCR] = 0x055c,
190 [PFRCR] = 0x0560,
191 [TPAUSER] = 0x0564,
192 [MAHR] = 0x05c0,
193 [MALR] = 0x05c8,
194 [CEFCR] = 0x0740,
195 [FRECR] = 0x0748,
196 [TSFRCR] = 0x0750,
197 [TLFRCR] = 0x0758,
198 [RFCR] = 0x0760,
199 [MAFCR] = 0x0778,
200
201 [ARSTR] = 0x0000,
202 [TSU_CTRST] = 0x0004,
e1487888 203 [TSU_FWSLC] = 0x0038,
db893473
SH		 204 [TSU_VTAG0] = 0x0058,
205 [TSU_ADSBSY] = 0x0060,
206 [TSU_TEN] = 0x0064,
e1487888
CB		 207 [TSU_POST1] = 0x0070,
208 [TSU_POST2] = 0x0074,
209 [TSU_POST3] = 0x0078,
210 [TSU_POST4] = 0x007c,
db893473 211 [TSU_ADRH0] = 0x0100,
db893473
SH		 212
213 [TXNLCR0] = 0x0080,
214 [TXALCR0] = 0x0084,
215 [RXNLCR0] = 0x0088,
216 [RXALCR0] = 0x008C,
217};
218
a3f109bd 219static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
3365711d
BH		 220 SH_ETH_OFFSET_DEFAULTS,
221
a3f109bd
SS		 222 [ECMR] = 0x0300,
223 [RFLR] = 0x0308,
224 [ECSR] = 0x0310,
225 [ECSIPR] = 0x0318,
226 [PIR] = 0x0320,
227 [PSR] = 0x0328,
228 [RDMLR] = 0x0340,
229 [IPGR] = 0x0350,
230 [APR] = 0x0354,
231 [MPR] = 0x0358,
232 [RFCF] = 0x0360,
233 [TPAUSER] = 0x0364,
234 [TPAUSECR] = 0x0368,
235 [MAHR] = 0x03c0,
236 [MALR] = 0x03c8,
237 [TROCR] = 0x03d0,
238 [CDCR] = 0x03d4,
239 [LCCR] = 0x03d8,
240 [CNDCR] = 0x03dc,
241 [CEFCR] = 0x03e4,
242 [FRECR] = 0x03e8,
243 [TSFRCR] = 0x03ec,
244 [TLFRCR] = 0x03f0,
245 [RFCR] = 0x03f4,
246 [MAFCR] = 0x03f8,
247
248 [EDMR] = 0x0200,
249 [EDTRR] = 0x0208,
250 [EDRRR] = 0x0210,
251 [TDLAR] = 0x0218,
252 [RDLAR] = 0x0220,
253 [EESR] = 0x0228,
254 [EESIPR] = 0x0230,
255 [TRSCER] = 0x0238,
256 [RMFCR] = 0x0240,
257 [TFTR] = 0x0248,
258 [FDR] = 0x0250,
259 [RMCR] = 0x0258,
260 [TFUCR] = 0x0264,
261 [RFOCR] = 0x0268,
55754f19 262 [RMIIMODE] = 0x026c,
a3f109bd
SS		 263 [FCFTR] = 0x0270,
264 [TRIMD] = 0x027c,
265};
266
c0013f6f 267static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
3365711d
BH		 268 SH_ETH_OFFSET_DEFAULTS,
269
c0013f6f
SS		 270 [ECMR] = 0x0100,
271 [RFLR] = 0x0108,
272 [ECSR] = 0x0110,
273 [ECSIPR] = 0x0118,
274 [PIR] = 0x0120,
275 [PSR] = 0x0128,
276 [RDMLR] = 0x0140,
277 [IPGR] = 0x0150,
278 [APR] = 0x0154,
279 [MPR] = 0x0158,
280 [TPAUSER] = 0x0164,
281 [RFCF] = 0x0160,
282 [TPAUSECR] = 0x0168,
283 [BCFRR] = 0x016c,
284 [MAHR] = 0x01c0,
285 [MALR] = 0x01c8,
286 [TROCR] = 0x01d0,
287 [CDCR] = 0x01d4,
288 [LCCR] = 0x01d8,
289 [CNDCR] = 0x01dc,
290 [CEFCR] = 0x01e4,
291 [FRECR] = 0x01e8,
292 [TSFRCR] = 0x01ec,
293 [TLFRCR] = 0x01f0,
294 [RFCR] = 0x01f4,
295 [MAFCR] = 0x01f8,
296 [RTRATE] = 0x01fc,
297
298 [EDMR] = 0x0000,
299 [EDTRR] = 0x0008,
300 [EDRRR] = 0x0010,
301 [TDLAR] = 0x0018,
302 [RDLAR] = 0x0020,
303 [EESR] = 0x0028,
304 [EESIPR] = 0x0030,
305 [TRSCER] = 0x0038,
306 [RMFCR] = 0x0040,
307 [TFTR] = 0x0048,
308 [FDR] = 0x0050,
309 [RMCR] = 0x0058,
310 [TFUCR] = 0x0064,
311 [RFOCR] = 0x0068,
312 [FCFTR] = 0x0070,
313 [RPADIR] = 0x0078,
314 [TRIMD] = 0x007c,
315 [RBWAR] = 0x00c8,
316 [RDFAR] = 0x00cc,
317 [TBRAR] = 0x00d4,
318 [TDFAR] = 0x00d8,
319};
320
321static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
3365711d
BH		 322 SH_ETH_OFFSET_DEFAULTS,
323
d8b0426a
SS		 324 [EDMR] = 0x0000,
325 [EDTRR] = 0x0004,
326 [EDRRR] = 0x0008,
327 [TDLAR] = 0x000c,
328 [RDLAR] = 0x0010,
329 [EESR] = 0x0014,
330 [EESIPR] = 0x0018,
331 [TRSCER] = 0x001c,
332 [RMFCR] = 0x0020,
333 [TFTR] = 0x0024,
334 [FDR] = 0x0028,
335 [RMCR] = 0x002c,
336 [EDOCR] = 0x0030,
337 [FCFTR] = 0x0034,
338 [RPADIR] = 0x0038,
339 [TRIMD] = 0x003c,
340 [RBWAR] = 0x0040,
341 [RDFAR] = 0x0044,
342 [TBRAR] = 0x004c,
343 [TDFAR] = 0x0050,
344
c0013f6f
SS		 345 [ECMR] = 0x0160,
346 [ECSR] = 0x0164,
347 [ECSIPR] = 0x0168,
348 [PIR] = 0x016c,
349 [MAHR] = 0x0170,
350 [MALR] = 0x0174,
351 [RFLR] = 0x0178,
352 [PSR] = 0x017c,
353 [TROCR] = 0x0180,
354 [CDCR] = 0x0184,
355 [LCCR] = 0x0188,
356 [CNDCR] = 0x018c,
357 [CEFCR] = 0x0194,
358 [FRECR] = 0x0198,
359 [TSFRCR] = 0x019c,
360 [TLFRCR] = 0x01a0,
361 [RFCR] = 0x01a4,
362 [MAFCR] = 0x01a8,
363 [IPGR] = 0x01b4,
364 [APR] = 0x01b8,
365 [MPR] = 0x01bc,
366 [TPAUSER] = 0x01c4,
367 [BCFR] = 0x01cc,
368
369 [ARSTR] = 0x0000,
370 [TSU_CTRST] = 0x0004,
371 [TSU_FWEN0] = 0x0010,
372 [TSU_FWEN1] = 0x0014,
373 [TSU_FCM] = 0x0018,
374 [TSU_BSYSL0] = 0x0020,
375 [TSU_BSYSL1] = 0x0024,
376 [TSU_PRISL0] = 0x0028,
377 [TSU_PRISL1] = 0x002c,
378 [TSU_FWSL0] = 0x0030,
379 [TSU_FWSL1] = 0x0034,
380 [TSU_FWSLC] = 0x0038,
381 [TSU_QTAGM0] = 0x0040,
382 [TSU_QTAGM1] = 0x0044,
383 [TSU_ADQT0] = 0x0048,
384 [TSU_ADQT1] = 0x004c,
385 [TSU_FWSR] = 0x0050,
386 [TSU_FWINMK] = 0x0054,
387 [TSU_ADSBSY] = 0x0060,
388 [TSU_TEN] = 0x0064,
389 [TSU_POST1] = 0x0070,
390 [TSU_POST2] = 0x0074,
391 [TSU_POST3] = 0x0078,
392 [TSU_POST4] = 0x007c,
393
394 [TXNLCR0] = 0x0080,
395 [TXALCR0] = 0x0084,
396 [RXNLCR0] = 0x0088,
397 [RXALCR0] = 0x008c,
398 [FWNLCR0] = 0x0090,
399 [FWALCR0] = 0x0094,
400 [TXNLCR1] = 0x00a0,
50f3d740 401 [TXALCR1] = 0x00a4,
c0013f6f
SS		 402 [RXNLCR1] = 0x00a8,
403 [RXALCR1] = 0x00ac,
404 [FWNLCR1] = 0x00b0,
405 [FWALCR1] = 0x00b4,
406
407 [TSU_ADRH0] = 0x0100,
c0013f6f
SS		 408};
409
740c7f31
BH		 410static void sh_eth_rcv_snd_disable(struct net_device *ndev);
411static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev);
412
2274d375
SS		 413static void sh_eth_write(struct net_device *ndev, u32 data, int enum_index)
414{
415 struct sh_eth_private *mdp = netdev_priv(ndev);
416 u16 offset = mdp->reg_offset[enum_index];
417
418 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
419 return;
420
421 iowrite32(data, mdp->addr + offset);
422}
423
424static u32 sh_eth_read(struct net_device *ndev, int enum_index)
425{
426 struct sh_eth_private *mdp = netdev_priv(ndev);
427 u16 offset = mdp->reg_offset[enum_index];
428
429 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
430 return ~0U;
431
432 return ioread32(mdp->addr + offset);
433}
434
b2b14d2f
SS		 435static void sh_eth_modify(struct net_device *ndev, int enum_index, u32 clear,
436 u32 set)
437{
438 sh_eth_write(ndev, (sh_eth_read(ndev, enum_index) & ~clear) | set,
439 enum_index);
440}
441
55ea8743
SS		 442static void sh_eth_tsu_write(struct sh_eth_private *mdp, u32 data,
443 int enum_index)
444{
627a0d20
SS		 445 u16 offset = mdp->reg_offset[enum_index];
446
447 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
448 return;
449
450 iowrite32(data, mdp->tsu_addr + offset);
55ea8743
SS		 451}
452
453static u32 sh_eth_tsu_read(struct sh_eth_private *mdp, int enum_index)
454{
627a0d20
SS		 455 u16 offset = mdp->reg_offset[enum_index];
456
457 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
458 return ~0U;
459
460 return ioread32(mdp->tsu_addr + offset);
55ea8743
SS		 461}
462
bb2fa4e8
SS		 463static void sh_eth_soft_swap(char *src, int len)
464{
465#ifdef __LITTLE_ENDIAN
466 u32 *p = (u32 *)src;
467 u32 *maxp = p + ((len + sizeof(u32) - 1) / sizeof(u32));
468
469 for (; p < maxp; p++)
470 *p = swab32(*p);
471#endif
472}
473
8e994402 474static void sh_eth_select_mii(struct net_device *ndev)
5e7a76be 475{
5e7a76be 476 struct sh_eth_private *mdp = netdev_priv(ndev);
4fa8c3cc 477 u32 value;
5e7a76be
NI		 478
479 switch (mdp->phy_interface) {
230c1846
SS		 480 case PHY_INTERFACE_MODE_RGMII ... PHY_INTERFACE_MODE_RGMII_TXID:
481 value = 0x3;
482 break;
5e7a76be
NI		 483 case PHY_INTERFACE_MODE_GMII:
484 value = 0x2;
485 break;
486 case PHY_INTERFACE_MODE_MII:
487 value = 0x1;
488 break;
489 case PHY_INTERFACE_MODE_RMII:
490 value = 0x0;
491 break;
492 default:
f75f14ec
SS		 493 netdev_warn(ndev,
494 "PHY interface mode was not setup. Set to MII.\n");
5e7a76be
NI		 495 value = 0x1;
496 break;
497 }
498
499 sh_eth_write(ndev, value, RMII_MII);
500}
5e7a76be 501
8e994402 502static void sh_eth_set_duplex(struct net_device *ndev)
65ac8851
YS		 503{
504 struct sh_eth_private *mdp = netdev_priv(ndev);
65ac8851 505
b2b14d2f 506 sh_eth_modify(ndev, ECMR, ECMR_DM, mdp->duplex ? ECMR_DM : 0);
65ac8851
YS		 507}
508
99f84be6
GU		 509static void sh_eth_chip_reset(struct net_device *ndev)
510{
511 struct sh_eth_private *mdp = netdev_priv(ndev);
512
513 /* reset device */
ec65cfce 514 sh_eth_tsu_write(mdp, ARSTR_ARST, ARSTR);
99f84be6
GU		 515 mdelay(1);
516}
517
4ceedeb1
SS		 518static int sh_eth_soft_reset(struct net_device *ndev)
519{
520 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, EDMR_SRST_ETHER);
521 mdelay(3);
522 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, 0);
523
524 return 0;
525}
526
527static int sh_eth_check_soft_reset(struct net_device *ndev)
528{
529 int cnt;
530
531 for (cnt = 100; cnt > 0; cnt--) {
532 if (!(sh_eth_read(ndev, EDMR) & EDMR_SRST_GETHER))
533 return 0;
534 mdelay(1);
535 }
536
537 netdev_err(ndev, "Device reset failed\n");
538 return -ETIMEDOUT;
539}
540
541static int sh_eth_soft_reset_gether(struct net_device *ndev)
542{
543 struct sh_eth_private *mdp = netdev_priv(ndev);
544 int ret;
545
546 sh_eth_write(ndev, EDSR_ENALL, EDSR);
547 sh_eth_modify(ndev, EDMR, EDMR_SRST_GETHER, EDMR_SRST_GETHER);
548
549 ret = sh_eth_check_soft_reset(ndev);
550 if (ret)
551 return ret;
552
553 /* Table Init */
554 sh_eth_write(ndev, 0, TDLAR);
555 sh_eth_write(ndev, 0, TDFAR);
556 sh_eth_write(ndev, 0, TDFXR);
557 sh_eth_write(ndev, 0, TDFFR);
558 sh_eth_write(ndev, 0, RDLAR);
559 sh_eth_write(ndev, 0, RDFAR);
560 sh_eth_write(ndev, 0, RDFXR);
561 sh_eth_write(ndev, 0, RDFFR);
562
563 /* Reset HW CRC register */
564 if (mdp->cd->hw_checksum)
565 sh_eth_write(ndev, 0, CSMR);
566
567 /* Select MII mode */
568 if (mdp->cd->select_mii)
569 sh_eth_select_mii(ndev);
570
571 return ret;
572}
573
a0f48be3
GU		 574static void sh_eth_set_rate_gether(struct net_device *ndev)
575{
576 struct sh_eth_private *mdp = netdev_priv(ndev);
577
578 switch (mdp->speed) {
579 case 10: /* 10BASE */
580 sh_eth_write(ndev, GECMR_10, GECMR);
581 break;
582 case 100:/* 100BASE */
583 sh_eth_write(ndev, GECMR_100, GECMR);
584 break;
585 case 1000: /* 1000BASE */
586 sh_eth_write(ndev, GECMR_1000, GECMR);
587 break;
a0f48be3
GU		 588 }
589}
590
99f84be6
GU		 591#ifdef CONFIG_OF
592/* R7S72100 */
593static struct sh_eth_cpu_data r7s72100_data = {
4ceedeb1
SS		 594 .soft_reset = sh_eth_soft_reset_gether,
595
99f84be6
GU		 596 .chip_reset = sh_eth_chip_reset,
597 .set_duplex = sh_eth_set_duplex,
598
599 .register_type = SH_ETH_REG_FAST_RZ,
600
3e416992 601 .edtrr_trns = EDTRR_TRNS_GETHER,
99f84be6
GU		 602 .ecsr_value = ECSR_ICD,
603 .ecsipr_value = ECSIPR_ICDIP,
2b2d3eb4
SS		 604 .eesipr_value = EESIPR_TWB1IP | EESIPR_TWBIP | EESIPR_TC1IP |
605 EESIPR_TABTIP | EESIPR_RABTIP | EESIPR_RFCOFIP |
606 EESIPR_ECIIP |
607 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
608 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
609 EESIPR_RMAFIP | EESIPR_RRFIP |
610 EESIPR_RTLFIP | EESIPR_RTSFIP |
611 EESIPR_PREIP | EESIPR_CERFIP,
99f84be6
GU		 612
613 .tx_check = EESR_TC1 | EESR_FTC,
614 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
615 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
9b39f05c 616 EESR_TDE,
99f84be6
GU		 617 .fdr_value = 0x0000070f,
618
619 .no_psr = 1,
620 .apr = 1,
621 .mpr = 1,
622 .tpauser = 1,
623 .hw_swap = 1,
624 .rpadir = 1,
625 .rpadir_value = 2 << 16,
626 .no_trimd = 1,
627 .no_ade = 1,
246e30cc 628 .xdfar_rw = 1,
62e04b7e 629 .hw_checksum = 1,
99f84be6 630 .tsu = 1,
ce9134df 631 .no_tx_cntrs = 1,
99f84be6 632};
a0f48be3
GU		 633
634static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
635{
c66b2581 636 sh_eth_chip_reset(ndev);
a0f48be3
GU		 637
638 sh_eth_select_mii(ndev);
639}
640
641/* R8A7740 */
642static struct sh_eth_cpu_data r8a7740_data = {
4ceedeb1
SS		 643 .soft_reset = sh_eth_soft_reset_gether,
644
a0f48be3
GU		 645 .chip_reset = sh_eth_chip_reset_r8a7740,
646 .set_duplex = sh_eth_set_duplex,
647 .set_rate = sh_eth_set_rate_gether,
648
649 .register_type = SH_ETH_REG_GIGABIT,
650
3e416992 651 .edtrr_trns = EDTRR_TRNS_GETHER,
a0f48be3
GU		 652 .ecsr_value = ECSR_ICD | ECSR_MPD,
653 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
2b2d3eb4
SS		 654 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
655 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
656 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
657 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
658 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
659 EESIPR_CEEFIP | EESIPR_CELFIP |
660 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
661 EESIPR_PREIP | EESIPR_CERFIP,
a0f48be3
GU		 662
663 .tx_check = EESR_TC1 | EESR_FTC,
664 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
665 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
9b39f05c 666 EESR_TDE,
a0f48be3
GU		 667 .fdr_value = 0x0000070f,
668
669 .apr = 1,
670 .mpr = 1,
671 .tpauser = 1,
672 .bculr = 1,
673 .hw_swap = 1,
674 .rpadir = 1,
675 .rpadir_value = 2 << 16,
676 .no_trimd = 1,
677 .no_ade = 1,
246e30cc 678 .xdfar_rw = 1,
62e04b7e 679 .hw_checksum = 1,
a0f48be3
GU		 680 .tsu = 1,
681 .select_mii = 1,
33017e24 682 .magic = 1,
4c1d4585 683 .cexcr = 1,
a0f48be3 684};
99f84be6 685
04b0ed2a 686/* There is CPU dependent code */
6c4b2f7e 687static void sh_eth_set_rate_rcar(struct net_device *ndev)
65ac8851
YS		 688{
689 struct sh_eth_private *mdp = netdev_priv(ndev);
d0418bb7 690
a3f109bd
SS		 691 switch (mdp->speed) {
692 case 10: /* 10BASE */
b2b14d2f 693 sh_eth_modify(ndev, ECMR, ECMR_ELB, 0);
a3f109bd
SS		 694 break;
695 case 100:/* 100BASE */
b2b14d2f 696 sh_eth_modify(ndev, ECMR, ECMR_ELB, ECMR_ELB);
a3f109bd 697 break;
a3f109bd
SS		 698 }
699}
700
6c4b2f7e
SH		 701/* R-Car Gen1 */
702static struct sh_eth_cpu_data rcar_gen1_data = {
4ceedeb1
SS		 703 .soft_reset = sh_eth_soft_reset,
704
a3f109bd 705 .set_duplex = sh_eth_set_duplex,
6c4b2f7e 706 .set_rate = sh_eth_set_rate_rcar,
a3f109bd 707
a3153d8c
SS		 708 .register_type = SH_ETH_REG_FAST_RCAR,
709
3e416992 710 .edtrr_trns = EDTRR_TRNS_ETHER,
a3f109bd
SS		 711 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
712 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
2b2d3eb4
SS		 713 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP |
714 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
715 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
716 EESIPR_RMAFIP | EESIPR_RRFIP |
717 EESIPR_RTLFIP | EESIPR_RTSFIP |
718 EESIPR_PREIP | EESIPR_CERFIP,
a3f109bd 719
27164491 720 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO,
ca8c3585 721 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
9b39f05c 722 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
d407bc02 723 .fdr_value = 0x00000f0f,
a3f109bd
SS		 724
725 .apr = 1,
726 .mpr = 1,
727 .tpauser = 1,
728 .hw_swap = 1,
6e80e55b 729 .no_xdfar = 1,
a3f109bd 730};
a3f109bd 731
6c4b2f7e
SH		 732/* R-Car Gen2 and RZ/G1 */
733static struct sh_eth_cpu_data rcar_gen2_data = {
4ceedeb1
SS		 734 .soft_reset = sh_eth_soft_reset,
735
e18dbf7e 736 .set_duplex = sh_eth_set_duplex,
6c4b2f7e 737 .set_rate = sh_eth_set_rate_rcar,
e18dbf7e 738
a3153d8c
SS		 739 .register_type = SH_ETH_REG_FAST_RCAR,
740
3e416992 741 .edtrr_trns = EDTRR_TRNS_ETHER,
e410d86d
NS		 742 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD | ECSR_MPD,
743 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP |
744 ECSIPR_MPDIP,
2b2d3eb4
SS		 745 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP |
746 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
747 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
748 EESIPR_RMAFIP | EESIPR_RRFIP |
749 EESIPR_RTLFIP | EESIPR_RTSFIP |
750 EESIPR_PREIP | EESIPR_CERFIP,
e18dbf7e 751
27164491 752 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO,
ba361cb3 753 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
9b39f05c 754 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
d407bc02 755 .fdr_value = 0x00000f0f,
e18dbf7e 756
01fbd3f5
GU		 757 .trscer_err_mask = DESC_I_RINT8,
758
e18dbf7e
SH		 759 .apr = 1,
760 .mpr = 1,
761 .tpauser = 1,
762 .hw_swap = 1,
6e80e55b 763 .no_xdfar = 1,
e18dbf7e 764 .rmiimode = 1,
e410d86d 765 .magic = 1,
e18dbf7e 766};
3eb9c2ad
SS		 767
768/* R8A77980 */
769static struct sh_eth_cpu_data r8a77980_data = {
770 .soft_reset = sh_eth_soft_reset_gether,
771
772 .set_duplex = sh_eth_set_duplex,
773 .set_rate = sh_eth_set_rate_gether,
774
775 .register_type = SH_ETH_REG_GIGABIT,
776
777 .edtrr_trns = EDTRR_TRNS_GETHER,
778 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD | ECSR_MPD,
779 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP |
780 ECSIPR_MPDIP,
781 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
782 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
783 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
784 EESIPR_RMAFIP | EESIPR_RRFIP |
785 EESIPR_RTLFIP | EESIPR_RTSFIP |
786 EESIPR_PREIP | EESIPR_CERFIP,
787
27164491 788 .tx_check = EESR_FTC | EESR_CD | EESR_TRO,
3eb9c2ad
SS		 789 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
790 EESR_RFE | EESR_RDE | EESR_RFRMER |
791 EESR_TFE | EESR_TDE | EESR_ECI,
792 .fdr_value = 0x0000070f,
793
794 .apr = 1,
795 .mpr = 1,
796 .tpauser = 1,
797 .bculr = 1,
798 .hw_swap = 1,
799 .nbst = 1,
800 .rpadir = 1,
801 .rpadir_value = 2 << 16,
802 .no_trimd = 1,
803 .no_ade = 1,
804 .xdfar_rw = 1,
805 .hw_checksum = 1,
806 .select_mii = 1,
807 .magic = 1,
808 .cexcr = 1,
809};
c74a2248 810#endif /* CONFIG_OF */
e18dbf7e 811
9c3beaab 812static void sh_eth_set_rate_sh7724(struct net_device *ndev)
a3f109bd
SS		 813{
814 struct sh_eth_private *mdp = netdev_priv(ndev);
65ac8851
YS		 815
816 switch (mdp->speed) {
817 case 10: /* 10BASE */
b2b14d2f 818 sh_eth_modify(ndev, ECMR, ECMR_RTM, 0);
65ac8851
YS		 819 break;
820 case 100:/* 100BASE */
b2b14d2f 821 sh_eth_modify(ndev, ECMR, ECMR_RTM, ECMR_RTM);
65ac8851 822 break;
65ac8851
YS		 823 }
824}
825
826/* SH7724 */
9c3beaab 827static struct sh_eth_cpu_data sh7724_data = {
4ceedeb1
SS		 828 .soft_reset = sh_eth_soft_reset,
829
65ac8851 830 .set_duplex = sh_eth_set_duplex,
9c3beaab 831 .set_rate = sh_eth_set_rate_sh7724,
65ac8851 832
a3153d8c
SS		 833 .register_type = SH_ETH_REG_FAST_SH4,
834
3e416992 835 .edtrr_trns = EDTRR_TRNS_ETHER,
65ac8851
YS		 836 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
837 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
2b2d3eb4
SS		 838 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP |
839 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
840 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
841 EESIPR_RMAFIP | EESIPR_RRFIP |
842 EESIPR_RTLFIP | EESIPR_RTSFIP |
843 EESIPR_PREIP | EESIPR_CERFIP,
65ac8851 844
27164491 845 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO,
ca8c3585 846 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
9b39f05c 847 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
65ac8851
YS		 848
849 .apr = 1,
850 .mpr = 1,
851 .tpauser = 1,
852 .hw_swap = 1,
503914cf
MD		 853 .rpadir = 1,
854 .rpadir_value = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
65ac8851 855};
5cee1d37 856
24549e2a 857static void sh_eth_set_rate_sh7757(struct net_device *ndev)
f29a3d04
YS		 858{
859 struct sh_eth_private *mdp = netdev_priv(ndev);
f29a3d04
YS		 860
861 switch (mdp->speed) {
862 case 10: /* 10BASE */
4a55530f 863 sh_eth_write(ndev, 0, RTRATE);
f29a3d04
YS		 864 break;
865 case 100:/* 100BASE */
4a55530f 866 sh_eth_write(ndev, 1, RTRATE);
f29a3d04 867 break;
f29a3d04
YS		 868 }
869}
870
871/* SH7757 */
24549e2a 872static struct sh_eth_cpu_data sh7757_data = {
4ceedeb1
SS		 873 .soft_reset = sh_eth_soft_reset,
874
24549e2a
SS		 875 .set_duplex = sh_eth_set_duplex,
876 .set_rate = sh_eth_set_rate_sh7757,
f29a3d04 877
a3153d8c
SS		 878 .register_type = SH_ETH_REG_FAST_SH4,
879
3e416992 880 .edtrr_trns = EDTRR_TRNS_ETHER,
2b2d3eb4
SS		 881 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
882 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
883 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
884 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
885 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
886 EESIPR_CEEFIP | EESIPR_CELFIP |
887 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
888 EESIPR_PREIP | EESIPR_CERFIP,
f29a3d04 889
27164491 890 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO,
ca8c3585 891 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
9b39f05c 892 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
f29a3d04 893
5b3dfd13 894 .irq_flags = IRQF_SHARED,
f29a3d04
YS		 895 .apr = 1,
896 .mpr = 1,
897 .tpauser = 1,
898 .hw_swap = 1,
899 .no_ade = 1,
2e98e797
YS		 900 .rpadir = 1,
901 .rpadir_value = 2 << 16,
6b4b4fea 902 .rtrate = 1,
a94cf2a6 903 .dual_port = 1,
f29a3d04 904};
65ac8851 905
e403d295 906#define SH_GIGA_ETH_BASE 0xfee00000UL
8fcd4961
YS		 907#define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
908#define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
909static void sh_eth_chip_reset_giga(struct net_device *ndev)
910{
0799c2d6 911 u32 mahr[2], malr[2];
79270922 912 int i;
8fcd4961
YS		 913
914 /* save MAHR and MALR */
915 for (i = 0; i < 2; i++) {
ae70644d
YS		 916 malr[i] = ioread32((void *)GIGA_MALR(i));
917 mahr[i] = ioread32((void *)GIGA_MAHR(i));
8fcd4961
YS		 918 }
919
c66b2581 920 sh_eth_chip_reset(ndev);
8fcd4961
YS		 921
922 /* restore MAHR and MALR */
923 for (i = 0; i < 2; i++) {
ae70644d
YS		 924 iowrite32(malr[i], (void *)GIGA_MALR(i));
925 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
8fcd4961
YS		 926 }
927}
928
8fcd4961
YS		 929static void sh_eth_set_rate_giga(struct net_device *ndev)
930{
931 struct sh_eth_private *mdp = netdev_priv(ndev);
932
933 switch (mdp->speed) {
934 case 10: /* 10BASE */
935 sh_eth_write(ndev, 0x00000000, GECMR);
936 break;
937 case 100:/* 100BASE */
938 sh_eth_write(ndev, 0x00000010, GECMR);
939 break;
940 case 1000: /* 1000BASE */
941 sh_eth_write(ndev, 0x00000020, GECMR);
942 break;
8fcd4961
YS		 943 }
944}
945
946/* SH7757(GETHERC) */
24549e2a 947static struct sh_eth_cpu_data sh7757_data_giga = {
4ceedeb1
SS		 948 .soft_reset = sh_eth_soft_reset_gether,
949
8fcd4961 950 .chip_reset = sh_eth_chip_reset_giga,
04b0ed2a 951 .set_duplex = sh_eth_set_duplex,
8fcd4961
YS		 952 .set_rate = sh_eth_set_rate_giga,
953
a3153d8c
SS		 954 .register_type = SH_ETH_REG_GIGABIT,
955
3e416992 956 .edtrr_trns = EDTRR_TRNS_GETHER,
8fcd4961
YS		 957 .ecsr_value = ECSR_ICD | ECSR_MPD,
958 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
2b2d3eb4
SS		 959 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
960 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
961 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
962 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
963 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
964 EESIPR_CEEFIP | EESIPR_CELFIP |
965 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
966 EESIPR_PREIP | EESIPR_CERFIP,
8fcd4961
YS		 967
968 .tx_check = EESR_TC1 | EESR_FTC,
ca8c3585
SS		 969 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
970 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
9b39f05c 971 EESR_TDE,
8fcd4961 972 .fdr_value = 0x0000072f,
8fcd4961 973
5b3dfd13 974 .irq_flags = IRQF_SHARED,
8fcd4961
YS		 975 .apr = 1,
976 .mpr = 1,
977 .tpauser = 1,
978 .bculr = 1,
979 .hw_swap = 1,
980 .rpadir = 1,
981 .rpadir_value = 2 << 16,
982 .no_trimd = 1,
983 .no_ade = 1,
246e30cc 984 .xdfar_rw = 1,
3acbc971 985 .tsu = 1,
4c1d4585 986 .cexcr = 1,
a94cf2a6 987 .dual_port = 1,
8fcd4961
YS		 988};
989
f5d12767
SS		 990/* SH7734 */
991static struct sh_eth_cpu_data sh7734_data = {
4ceedeb1
SS		 992 .soft_reset = sh_eth_soft_reset_gether,
993
380af9e3
YS		 994 .chip_reset = sh_eth_chip_reset,
995 .set_duplex = sh_eth_set_duplex,
f5d12767
SS		 996 .set_rate = sh_eth_set_rate_gether,
997
a3153d8c
SS		 998 .register_type = SH_ETH_REG_GIGABIT,
999
3e416992 1000 .edtrr_trns = EDTRR_TRNS_GETHER,
f5d12767
SS		 1001 .ecsr_value = ECSR_ICD | ECSR_MPD,
1002 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
2b2d3eb4
SS		 1003 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
1004 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
1005 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
1006 EESIPR_DLCIP | EESIPR_CDIP | EESIPR_TROIP |
1007 EESIPR_RMAFIP | EESIPR_CEEFIP | EESIPR_CELFIP |
1008 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
1009 EESIPR_PREIP | EESIPR_CERFIP,
f5d12767
SS		 1010
1011 .tx_check = EESR_TC1 | EESR_FTC,
ca8c3585
SS		 1012 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
1013 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
9b39f05c 1014 EESR_TDE,
f5d12767
SS		 1015
1016 .apr = 1,
1017 .mpr = 1,
1018 .tpauser = 1,
1019 .bculr = 1,
1020 .hw_swap = 1,
1021 .no_trimd = 1,
1022 .no_ade = 1,
246e30cc 1023 .xdfar_rw = 1,
f5d12767 1024 .tsu = 1,
62e04b7e 1025 .hw_checksum = 1,
f5d12767 1026 .select_mii = 1,
159c2a90 1027 .magic = 1,
4c1d4585 1028 .cexcr = 1,
f5d12767
SS		 1029};
1030
1031/* SH7763 */
1032static struct sh_eth_cpu_data sh7763_data = {
4ceedeb1
SS		 1033 .soft_reset = sh_eth_soft_reset_gether,
1034
f5d12767
SS		 1035 .chip_reset = sh_eth_chip_reset,
1036 .set_duplex = sh_eth_set_duplex,
1037 .set_rate = sh_eth_set_rate_gether,
380af9e3 1038
a3153d8c
SS		 1039 .register_type = SH_ETH_REG_GIGABIT,
1040
3e416992 1041 .edtrr_trns = EDTRR_TRNS_GETHER,
380af9e3
YS		 1042 .ecsr_value = ECSR_ICD | ECSR_MPD,
1043 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
2b2d3eb4
SS		 1044 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
1045 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
1046 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
1047 EESIPR_DLCIP | EESIPR_CDIP | EESIPR_TROIP |
1048 EESIPR_RMAFIP | EESIPR_CEEFIP | EESIPR_CELFIP |
1049 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
1050 EESIPR_PREIP | EESIPR_CERFIP,
380af9e3
YS		 1051
1052 .tx_check = EESR_TC1 | EESR_FTC,
128296fc 1053 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
9b39f05c 1054 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
380af9e3
YS		 1055
1056 .apr = 1,
1057 .mpr = 1,
1058 .tpauser = 1,
1059 .bculr = 1,
1060 .hw_swap = 1,
380af9e3
YS		 1061 .no_trimd = 1,
1062 .no_ade = 1,
246e30cc 1063 .xdfar_rw = 1,
4986b996 1064 .tsu = 1,
5b3dfd13 1065 .irq_flags = IRQF_SHARED,
267e1d5c 1066 .magic = 1,
4c1d4585 1067 .cexcr = 1,
a94cf2a6 1068 .dual_port = 1,
380af9e3
YS		 1069};
1070
c18a79ab 1071static struct sh_eth_cpu_data sh7619_data = {
4ceedeb1
SS		 1072 .soft_reset = sh_eth_soft_reset,
1073
a3153d8c
SS		 1074 .register_type = SH_ETH_REG_FAST_SH3_SH2,
1075
3e416992 1076 .edtrr_trns = EDTRR_TRNS_ETHER,
2b2d3eb4
SS		 1077 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
1078 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
1079 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
1080 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
1081 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
1082 EESIPR_CEEFIP | EESIPR_CELFIP |
1083 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
1084 EESIPR_PREIP | EESIPR_CERFIP,
380af9e3
YS		 1085
1086 .apr = 1,
1087 .mpr = 1,
1088 .tpauser = 1,
1089 .hw_swap = 1,
1090};
7bbe150d
SS		 1091
1092static struct sh_eth_cpu_data sh771x_data = {
4ceedeb1
SS		 1093 .soft_reset = sh_eth_soft_reset,
1094
a3153d8c
SS		 1095 .register_type = SH_ETH_REG_FAST_SH3_SH2,
1096
3e416992 1097 .edtrr_trns = EDTRR_TRNS_ETHER,
2b2d3eb4
SS		 1098 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
1099 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
1100 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
1101 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
1102 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
1103 EESIPR_CEEFIP | EESIPR_CELFIP |
1104 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
1105 EESIPR_PREIP | EESIPR_CERFIP,
4986b996 1106 .tsu = 1,
a94cf2a6 1107 .dual_port = 1,
380af9e3 1108};
380af9e3
YS		 1109
1110static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
1111{
1112 if (!cd->ecsr_value)
1113 cd->ecsr_value = DEFAULT_ECSR_INIT;
1114
1115 if (!cd->ecsipr_value)
1116 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
1117
1118 if (!cd->fcftr_value)
128296fc 1119 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF |
380af9e3
YS		 1120 DEFAULT_FIFO_F_D_RFD;
1121
1122 if (!cd->fdr_value)
1123 cd->fdr_value = DEFAULT_FDR_INIT;
1124
380af9e3
YS		 1125 if (!cd->tx_check)
1126 cd->tx_check = DEFAULT_TX_CHECK;
1127
1128 if (!cd->eesr_err_check)
1129 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
b284fbe3
NI		 1130
1131 if (!cd->trscer_err_mask)
1132 cd->trscer_err_mask = DEFAULT_TRSCER_ERR_MASK;
380af9e3
YS		 1133}
1134
380af9e3
YS		 1135static void sh_eth_set_receive_align(struct sk_buff *skb)
1136{
4d6a949c 1137 uintptr_t reserve = (uintptr_t)skb->data & (SH_ETH_RX_ALIGN - 1);
380af9e3 1138
380af9e3 1139 if (reserve)
4d6a949c 1140 skb_reserve(skb, SH_ETH_RX_ALIGN - reserve);
380af9e3 1141}
380af9e3 1142
128296fc 1143/* Program the hardware MAC address from dev->dev_addr. */
86a74ff2
NI		 1144static void update_mac_address(struct net_device *ndev)
1145{
4a55530f 1146 sh_eth_write(ndev,
128296fc
SS		 1147 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
1148 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
4a55530f 1149 sh_eth_write(ndev,
128296fc 1150 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
86a74ff2
NI		 1151}
1152
128296fc 1153/* Get MAC address from SuperH MAC address register
86a74ff2
NI		 1154 *
1155 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
1156 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
1157 * When you want use this device, you must set MAC address in bootloader.
1158 *
1159 */
748031f9 1160static void read_mac_address(struct net_device *ndev, unsigned char *mac)
86a74ff2 1161{
748031f9 1162 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
d458cdf7 1163 memcpy(ndev->dev_addr, mac, ETH_ALEN);
748031f9 1164 } else {
37742f02
SS		 1165 u32 mahr = sh_eth_read(ndev, MAHR);
1166 u32 malr = sh_eth_read(ndev, MALR);
1167
1168 ndev->dev_addr[0] = (mahr >> 24) & 0xFF;
1169 ndev->dev_addr[1] = (mahr >> 16) & 0xFF;
1170 ndev->dev_addr[2] = (mahr >> 8) & 0xFF;
1171 ndev->dev_addr[3] = (mahr >> 0) & 0xFF;
1172 ndev->dev_addr[4] = (malr >> 8) & 0xFF;
1173 ndev->dev_addr[5] = (malr >> 0) & 0xFF;
748031f9 1174 }
86a74ff2
NI		 1175}
1176
1177struct bb_info {
ae70644d 1178 void (*set_gate)(void *addr);
86a74ff2 1179 struct mdiobb_ctrl ctrl;
ae70644d 1180 void *addr;
86a74ff2
NI		 1181};
1182
39b4b06b 1183static void sh_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set)
86a74ff2
NI		 1184{
1185 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
78fa3c5c 1186 u32 pir;
b3017e6a
YS		 1187
1188 if (bitbang->set_gate)
1189 bitbang->set_gate(bitbang->addr);
1190
78fa3c5c 1191 pir = ioread32(bitbang->addr);
39b4b06b 1192 if (set)
78fa3c5c 1193 pir |= mask;
86a74ff2 1194 else
78fa3c5c
SS		 1195 pir &= ~mask;
1196 iowrite32(pir, bitbang->addr);
39b4b06b
SS		 1197}
1198
1199/* Data I/O pin control */
1200static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1201{
1202 sh_mdio_ctrl(ctrl, PIR_MMD, bit);
86a74ff2
NI		 1203}
1204
1205/* Set bit data*/
1206static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
1207{
39b4b06b 1208 sh_mdio_ctrl(ctrl, PIR_MDO, bit);
86a74ff2
NI		 1209}
1210
1211/* Get bit data*/
1212static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
1213{
1214 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
b3017e6a
YS		 1215
1216 if (bitbang->set_gate)
1217 bitbang->set_gate(bitbang->addr);
1218
78fa3c5c 1219 return (ioread32(bitbang->addr) & PIR_MDI) != 0;
86a74ff2
NI		 1220}
1221
1222/* MDC pin control */
1223static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1224{
39b4b06b 1225 sh_mdio_ctrl(ctrl, PIR_MDC, bit);
86a74ff2
NI		 1226}
1227
1228/* mdio bus control struct */
1229static struct mdiobb_ops bb_ops = {
1230 .owner = THIS_MODULE,
1231 .set_mdc = sh_mdc_ctrl,
1232 .set_mdio_dir = sh_mmd_ctrl,
1233 .set_mdio_data = sh_set_mdio,
1234 .get_mdio_data = sh_get_mdio,
1235};
1236
1debdc8f
SS		 1237/* free Tx skb function */
1238static int sh_eth_tx_free(struct net_device *ndev, bool sent_only)
1239{
1240 struct sh_eth_private *mdp = netdev_priv(ndev);
1241 struct sh_eth_txdesc *txdesc;
1242 int free_num = 0;
1243 int entry;
1244 bool sent;
1245
1246 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
1247 entry = mdp->dirty_tx % mdp->num_tx_ring;
1248 txdesc = &mdp->tx_ring[entry];
1249 sent = !(txdesc->status & cpu_to_le32(TD_TACT));
1250 if (sent_only && !sent)
1251 break;
1252 /* TACT bit must be checked before all the following reads */
1253 dma_rmb();
1254 netif_info(mdp, tx_done, ndev,
1255 "tx entry %d status 0x%08x\n",
1256 entry, le32_to_cpu(txdesc->status));
1257 /* Free the original skb. */
1258 if (mdp->tx_skbuff[entry]) {
22c1aed4
TP		 1259 dma_unmap_single(&mdp->pdev->dev,
1260 le32_to_cpu(txdesc->addr),
1debdc8f
SS		 1261 le32_to_cpu(txdesc->len) >> 16,
1262 DMA_TO_DEVICE);
1263 dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1264 mdp->tx_skbuff[entry] = NULL;
1265 free_num++;
1266 }
1267 txdesc->status = cpu_to_le32(TD_TFP);
1268 if (entry >= mdp->num_tx_ring - 1)
1269 txdesc->status |= cpu_to_le32(TD_TDLE);
1270
1271 if (sent) {
1272 ndev->stats.tx_packets++;
1273 ndev->stats.tx_bytes += le32_to_cpu(txdesc->len) >> 16;
1274 }
1275 }
1276 return free_num;
1277}
1278
86a74ff2
NI		 1279/* free skb and descriptor buffer */
1280static void sh_eth_ring_free(struct net_device *ndev)
1281{
1282 struct sh_eth_private *mdp = netdev_priv(ndev);
8e03a5e7 1283 int ringsize, i;
86a74ff2 1284
1debdc8f
SS		 1285 if (mdp->rx_ring) {
1286 for (i = 0; i < mdp->num_rx_ring; i++) {
1287 if (mdp->rx_skbuff[i]) {
1288 struct sh_eth_rxdesc *rxdesc = &mdp->rx_ring[i];
1289
22c1aed4 1290 dma_unmap_single(&mdp->pdev->dev,
1debdc8f
SS		 1291 le32_to_cpu(rxdesc->addr),
1292 ALIGN(mdp->rx_buf_sz, 32),
1293 DMA_FROM_DEVICE);
1294 }
1295 }
1296 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
573500db 1297 dma_free_coherent(&mdp->pdev->dev, ringsize, mdp->rx_ring,
1debdc8f
SS		 1298 mdp->rx_desc_dma);
1299 mdp->rx_ring = NULL;
1300 }
1301
86a74ff2
NI		 1302 /* Free Rx skb ringbuffer */
1303 if (mdp->rx_skbuff) {
179d80af
SS		 1304 for (i = 0; i < mdp->num_rx_ring; i++)
1305 dev_kfree_skb(mdp->rx_skbuff[i]);
86a74ff2
NI		 1306 }
1307 kfree(mdp->rx_skbuff);
91c77550 1308 mdp->rx_skbuff = NULL;
86a74ff2 1309
8e03a5e7 1310 if (mdp->tx_ring) {
1debdc8f
SS		 1311 sh_eth_tx_free(ndev, false);
1312
8e03a5e7 1313 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
573500db 1314 dma_free_coherent(&mdp->pdev->dev, ringsize, mdp->tx_ring,
8e03a5e7
SS		 1315 mdp->tx_desc_dma);
1316 mdp->tx_ring = NULL;
1317 }
1debdc8f
SS		 1318
1319 /* Free Tx skb ringbuffer */
1320 kfree(mdp->tx_skbuff);
1321 mdp->tx_skbuff = NULL;
86a74ff2
NI		 1322}
1323
1324/* format skb and descriptor buffer */
1325static void sh_eth_ring_format(struct net_device *ndev)
1326{
1327 struct sh_eth_private *mdp = netdev_priv(ndev);
1328 int i;
1329 struct sk_buff *skb;
1330 struct sh_eth_rxdesc *rxdesc = NULL;
1331 struct sh_eth_txdesc *txdesc = NULL;
525b8075
YS		 1332 int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
1333 int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
cb368595 1334 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
52b9fa36 1335 dma_addr_t dma_addr;
5cbf20c7 1336 u32 buf_len;
86a74ff2 1337
128296fc
SS		 1338 mdp->cur_rx = 0;
1339 mdp->cur_tx = 0;
1340 mdp->dirty_rx = 0;
1341 mdp->dirty_tx = 0;
86a74ff2
NI		 1342
1343 memset(mdp->rx_ring, 0, rx_ringsize);
1344
1345 /* build Rx ring buffer */
525b8075 1346 for (i = 0; i < mdp->num_rx_ring; i++) {
86a74ff2
NI		 1347 /* skb */
1348 mdp->rx_skbuff[i] = NULL;
4d6a949c 1349 skb = netdev_alloc_skb(ndev, skbuff_size);
86a74ff2
NI		 1350 if (skb == NULL)
1351 break;
380af9e3
YS		 1352 sh_eth_set_receive_align(skb);
1353
ab857916 1354 /* The size of the buffer is a multiple of 32 bytes. */
5cbf20c7 1355 buf_len = ALIGN(mdp->rx_buf_sz, 32);
22c1aed4 1356 dma_addr = dma_map_single(&mdp->pdev->dev, skb->data, buf_len,
52b9fa36 1357 DMA_FROM_DEVICE);
22c1aed4 1358 if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) {
52b9fa36
BH		 1359 kfree_skb(skb);
1360 break;
1361 }
1362 mdp->rx_skbuff[i] = skb;
d0ba9134
SS		 1363
1364 /* RX descriptor */
1365 rxdesc = &mdp->rx_ring[i];
1366 rxdesc->len = cpu_to_le32(buf_len << 16);
7cf72477
SS		 1367 rxdesc->addr = cpu_to_le32(dma_addr);
1368 rxdesc->status = cpu_to_le32(RD_RACT | RD_RFP);
86a74ff2 1369
b0ca2a21
NI		 1370 /* Rx descriptor address set */
1371 if (i == 0) {
4a55530f 1372 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
246e30cc 1373 if (mdp->cd->xdfar_rw)
c5ed5368 1374 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
b0ca2a21 1375 }
86a74ff2
NI		 1376 }
1377
525b8075 1378 mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
86a74ff2
NI		 1379
1380 /* Mark the last entry as wrapping the ring. */
c1b7fca6
SS		 1381 if (rxdesc)
1382 rxdesc->status |= cpu_to_le32(RD_RDLE);
86a74ff2
NI		 1383
1384 memset(mdp->tx_ring, 0, tx_ringsize);
1385
1386 /* build Tx ring buffer */
525b8075 1387 for (i = 0; i < mdp->num_tx_ring; i++) {
86a74ff2
NI		 1388 mdp->tx_skbuff[i] = NULL;
1389 txdesc = &mdp->tx_ring[i];
7cf72477
SS		 1390 txdesc->status = cpu_to_le32(TD_TFP);
1391 txdesc->len = cpu_to_le32(0);
b0ca2a21 1392 if (i == 0) {
71557a37 1393 /* Tx descriptor address set */
4a55530f 1394 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
246e30cc 1395 if (mdp->cd->xdfar_rw)
c5ed5368 1396 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
b0ca2a21 1397 }
86a74ff2
NI		 1398 }
1399
7cf72477 1400 txdesc->status |= cpu_to_le32(TD_TDLE);
86a74ff2
NI		 1401}
1402
1403/* Get skb and descriptor buffer */
1404static int sh_eth_ring_init(struct net_device *ndev)
1405{
1406 struct sh_eth_private *mdp = netdev_priv(ndev);
91d80683 1407 int rx_ringsize, tx_ringsize;
86a74ff2 1408
128296fc 1409 /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
86a74ff2
NI		 1410 * card needs room to do 8 byte alignment, +2 so we can reserve
1411 * the first 2 bytes, and +16 gets room for the status word from the
1412 * card.
1413 */
1414 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
1415 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
503914cf
MD		 1416 if (mdp->cd->rpadir)
1417 mdp->rx_buf_sz += NET_IP_ALIGN;
86a74ff2
NI		 1418
1419 /* Allocate RX and TX skb rings */
2c94e856
SS		 1420 mdp->rx_skbuff = kcalloc(mdp->num_rx_ring, sizeof(*mdp->rx_skbuff),
1421 GFP_KERNEL);
91d80683
SS		 1422 if (!mdp->rx_skbuff)
1423 return -ENOMEM;
86a74ff2 1424
2c94e856
SS		 1425 mdp->tx_skbuff = kcalloc(mdp->num_tx_ring, sizeof(*mdp->tx_skbuff),
1426 GFP_KERNEL);
91d80683 1427 if (!mdp->tx_skbuff)
8e03a5e7 1428 goto ring_free;
86a74ff2
NI		 1429
1430 /* Allocate all Rx descriptors. */
525b8075 1431 rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
573500db
TP		 1432 mdp->rx_ring = dma_alloc_coherent(&mdp->pdev->dev, rx_ringsize,
1433 &mdp->rx_desc_dma, GFP_KERNEL);
91d80683 1434 if (!mdp->rx_ring)
8e03a5e7 1435 goto ring_free;
86a74ff2
NI		 1436
1437 mdp->dirty_rx = 0;
1438
1439 /* Allocate all Tx descriptors. */
525b8075 1440 tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
573500db
TP		 1441 mdp->tx_ring = dma_alloc_coherent(&mdp->pdev->dev, tx_ringsize,
1442 &mdp->tx_desc_dma, GFP_KERNEL);
91d80683 1443 if (!mdp->tx_ring)
8e03a5e7 1444 goto ring_free;
91d80683 1445 return 0;
86a74ff2 1446
8e03a5e7
SS		 1447ring_free:
1448 /* Free Rx and Tx skb ring buffer and DMA buffer */
86a74ff2
NI		 1449 sh_eth_ring_free(ndev);
1450
91d80683 1451 return -ENOMEM;
86a74ff2
NI		 1452}
1453
f7967210 1454static int sh_eth_dev_init(struct net_device *ndev)
86a74ff2 1455{
86a74ff2 1456 struct sh_eth_private *mdp = netdev_priv(ndev);
4fa8c3cc 1457 int ret;
86a74ff2
NI		 1458
1459 /* Soft Reset */
4ceedeb1 1460 ret = mdp->cd->soft_reset(ndev);
5cee1d37 1461 if (ret)
f738a13d 1462 return ret;
86a74ff2 1463
55754f19
SH		 1464 if (mdp->cd->rmiimode)
1465 sh_eth_write(ndev, 0x1, RMIIMODE);
1466
b0ca2a21
NI		 1467 /* Descriptor format */
1468 sh_eth_ring_format(ndev);
380af9e3 1469 if (mdp->cd->rpadir)
4a55530f 1470 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
86a74ff2
NI		 1471
1472 /* all sh_eth int mask */
4a55530f 1473 sh_eth_write(ndev, 0, EESIPR);
86a74ff2 1474
10b9194f 1475#if defined(__LITTLE_ENDIAN)
380af9e3 1476 if (mdp->cd->hw_swap)
4a55530f 1477 sh_eth_write(ndev, EDMR_EL, EDMR);
380af9e3 1478 else
b0ca2a21 1479#endif
4a55530f 1480 sh_eth_write(ndev, 0, EDMR);
86a74ff2 1481
b0ca2a21 1482 /* FIFO size set */
4a55530f
YS		 1483 sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
1484 sh_eth_write(ndev, 0, TFTR);
86a74ff2 1485
530aa2d0
BD		 1486 /* Frame recv control (enable multiple-packets per rx irq) */
1487 sh_eth_write(ndev, RMCR_RNC, RMCR);
86a74ff2 1488
b284fbe3 1489 sh_eth_write(ndev, mdp->cd->trscer_err_mask, TRSCER);
86a74ff2 1490
93f0fa75
SS		 1491 /* DMA transfer burst mode */
1492 if (mdp->cd->nbst)
1493 sh_eth_modify(ndev, EDMR, EDMR_NBST, EDMR_NBST);
1494
6b14787a 1495 /* Burst cycle count upper-limit */
380af9e3 1496 if (mdp->cd->bculr)
6b14787a 1497 sh_eth_write(ndev, 0x800, BCULR);
b0ca2a21 1498
4a55530f 1499 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
86a74ff2 1500
380af9e3 1501 if (!mdp->cd->no_trimd)
4a55530f 1502 sh_eth_write(ndev, 0, TRIMD);
86a74ff2 1503
b0ca2a21 1504 /* Recv frame limit set register */
fdb37a7f
YS		 1505 sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1506 RFLR);
86a74ff2 1507
b2b14d2f 1508 sh_eth_modify(ndev, EESR, 0, 0);
f7967210
SS		 1509 mdp->irq_enabled = true;
1510 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
86a74ff2
NI		 1511
1512 /* PAUSE Prohibition */
bffa731f
SS		 1513 sh_eth_write(ndev, ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) |
1514 ECMR_TE | ECMR_RE, ECMR);
b0ca2a21 1515
380af9e3
YS		 1516 if (mdp->cd->set_rate)
1517 mdp->cd->set_rate(ndev);
1518
b0ca2a21 1519 /* E-MAC Status Register clear */
4a55530f 1520 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
b0ca2a21
NI		 1521
1522 /* E-MAC Interrupt Enable register */
f7967210 1523 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
86a74ff2
NI		 1524
1525 /* Set MAC address */
1526 update_mac_address(ndev);
1527
1528 /* mask reset */
380af9e3 1529 if (mdp->cd->apr)
4a55530f 1530 sh_eth_write(ndev, APR_AP, APR);
380af9e3 1531 if (mdp->cd->mpr)
4a55530f 1532 sh_eth_write(ndev, MPR_MP, MPR);
380af9e3 1533 if (mdp->cd->tpauser)
4a55530f 1534 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
b0ca2a21 1535
f7967210
SS		 1536 /* Setting the Rx mode will start the Rx process. */
1537 sh_eth_write(ndev, EDRRR_R, EDRRR);
86a74ff2
NI		 1538
1539 return ret;
1540}
1541
740c7f31
BH		 1542static void sh_eth_dev_exit(struct net_device *ndev)
1543{
1544 struct sh_eth_private *mdp = netdev_priv(ndev);
1545 int i;
1546
1547 /* Deactivate all TX descriptors, so DMA should stop at next
1548 * packet boundary if it's currently running
1549 */
1550 for (i = 0; i < mdp->num_tx_ring; i++)
7cf72477 1551 mdp->tx_ring[i].status &= ~cpu_to_le32(TD_TACT);
740c7f31
BH		 1552
1553 /* Disable TX FIFO egress to MAC */
1554 sh_eth_rcv_snd_disable(ndev);
1555
1556 /* Stop RX DMA at next packet boundary */
1557 sh_eth_write(ndev, 0, EDRRR);
1558
1559 /* Aside from TX DMA, we can't tell when the hardware is
1560 * really stopped, so we need to reset to make sure.
1561 * Before doing that, wait for long enough to *probably*
1562 * finish transmitting the last packet and poll stats.
1563 */
1564 msleep(2); /* max frame time at 10 Mbps < 1250 us */
1565 sh_eth_get_stats(ndev);
4ceedeb1 1566 mdp->cd->soft_reset(ndev);
a14c7d15
GU		 1567
1568 /* Set MAC address again */
1569 update_mac_address(ndev);
740c7f31
BH		 1570}
1571
86a74ff2 1572/* Packet receive function */
3719109d 1573static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
86a74ff2
NI		 1574{
1575 struct sh_eth_private *mdp = netdev_priv(ndev);
1576 struct sh_eth_rxdesc *rxdesc;
1577
525b8075
YS		 1578 int entry = mdp->cur_rx % mdp->num_rx_ring;
1579 int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
319cd520 1580 int limit;
86a74ff2 1581 struct sk_buff *skb;
380af9e3 1582 u32 desc_status;
cb368595 1583 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
52b9fa36 1584 dma_addr_t dma_addr;
4fa8c3cc 1585 u16 pkt_len;
5cbf20c7 1586 u32 buf_len;
86a74ff2 1587
319cd520
MK		 1588 boguscnt = min(boguscnt, *quota);
1589 limit = boguscnt;
86a74ff2 1590 rxdesc = &mdp->rx_ring[entry];
7cf72477 1591 while (!(rxdesc->status & cpu_to_le32(RD_RACT))) {
7d7355f5 1592 /* RACT bit must be checked before all the following reads */
f32bfb9a 1593 dma_rmb();
7cf72477
SS		 1594 desc_status = le32_to_cpu(rxdesc->status);
1595 pkt_len = le32_to_cpu(rxdesc->len) & RD_RFL;
86a74ff2
NI		 1596
1597 if (--boguscnt < 0)
1598 break;
1599
e5fd13f4
BH		 1600 netif_info(mdp, rx_status, ndev,
1601 "rx entry %d status 0x%08x len %d\n",
1602 entry, desc_status, pkt_len);
1603
86a74ff2 1604 if (!(desc_status & RDFEND))
bb7d92e3 1605 ndev->stats.rx_length_errors++;
86a74ff2 1606
128296fc 1607 /* In case of almost all GETHER/ETHERs, the Receive Frame State
dd019897 1608 * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
9b4a6364
BH		 1609 * bit 0. However, in case of the R8A7740 and R7S72100
1610 * the RFS bits are from bit 25 to bit 16. So, the
db893473 1611 * driver needs right shifting by 16.
dd019897 1612 */
62e04b7e 1613 if (mdp->cd->hw_checksum)
ac8025a6 1614 desc_status >>= 16;
dd019897 1615
248be83d 1616 skb = mdp->rx_skbuff[entry];
86a74ff2
NI		 1617 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1618 RD_RFS5 | RD_RFS6 | RD_RFS10)) {
bb7d92e3 1619 ndev->stats.rx_errors++;
86a74ff2 1620 if (desc_status & RD_RFS1)
bb7d92e3 1621 ndev->stats.rx_crc_errors++;
86a74ff2 1622 if (desc_status & RD_RFS2)
bb7d92e3 1623 ndev->stats.rx_frame_errors++;
86a74ff2 1624 if (desc_status & RD_RFS3)
bb7d92e3 1625 ndev->stats.rx_length_errors++;
86a74ff2 1626 if (desc_status & RD_RFS4)
bb7d92e3 1627 ndev->stats.rx_length_errors++;
86a74ff2 1628 if (desc_status & RD_RFS6)
bb7d92e3 1629 ndev->stats.rx_missed_errors++;
86a74ff2 1630 if (desc_status & RD_RFS10)
bb7d92e3 1631 ndev->stats.rx_over_errors++;
248be83d 1632 } else if (skb) {
7cf72477 1633 dma_addr = le32_to_cpu(rxdesc->addr);
380af9e3
YS		 1634 if (!mdp->cd->hw_swap)
1635 sh_eth_soft_swap(
1299653a 1636 phys_to_virt(ALIGN(dma_addr, 4)),
380af9e3 1637 pkt_len + 2);
86a74ff2 1638 mdp->rx_skbuff[entry] = NULL;
503914cf
MD		 1639 if (mdp->cd->rpadir)
1640 skb_reserve(skb, NET_IP_ALIGN);
22c1aed4 1641 dma_unmap_single(&mdp->pdev->dev, dma_addr,
ab857916 1642 ALIGN(mdp->rx_buf_sz, 32),
52b9fa36 1643 DMA_FROM_DEVICE);
86a74ff2
NI		 1644 skb_put(skb, pkt_len);
1645 skb->protocol = eth_type_trans(skb, ndev);
a8e9fd0f 1646 netif_receive_skb(skb);
bb7d92e3
ED		 1647 ndev->stats.rx_packets++;
1648 ndev->stats.rx_bytes += pkt_len;
25b77ad7
BH		 1649 if (desc_status & RD_RFS8)
1650 ndev->stats.multicast++;
86a74ff2 1651 }
525b8075 1652 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
862df497 1653 rxdesc = &mdp->rx_ring[entry];
86a74ff2
NI		 1654 }
1655
1656 /* Refill the Rx ring buffers. */
1657 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
525b8075 1658 entry = mdp->dirty_rx % mdp->num_rx_ring;
86a74ff2 1659 rxdesc = &mdp->rx_ring[entry];
ab857916 1660 /* The size of the buffer is 32 byte boundary. */
5cbf20c7 1661 buf_len = ALIGN(mdp->rx_buf_sz, 32);
7cf72477 1662 rxdesc->len = cpu_to_le32(buf_len << 16);
b0ca2a21 1663
86a74ff2 1664 if (mdp->rx_skbuff[entry] == NULL) {
4d6a949c 1665 skb = netdev_alloc_skb(ndev, skbuff_size);
86a74ff2
NI		 1666 if (skb == NULL)
1667 break; /* Better luck next round. */
380af9e3 1668 sh_eth_set_receive_align(skb);
22c1aed4 1669 dma_addr = dma_map_single(&mdp->pdev->dev, skb->data,
5cbf20c7 1670 buf_len, DMA_FROM_DEVICE);
22c1aed4 1671 if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) {
52b9fa36
BH		 1672 kfree_skb(skb);
1673 break;
1674 }
1675 mdp->rx_skbuff[entry] = skb;
380af9e3 1676
bc8acf2c 1677 skb_checksum_none_assert(skb);
7cf72477 1678 rxdesc->addr = cpu_to_le32(dma_addr);
86a74ff2 1679 }
f32bfb9a 1680 dma_wmb(); /* RACT bit must be set after all the above writes */
525b8075 1681 if (entry >= mdp->num_rx_ring - 1)
86a74ff2 1682 rxdesc->status |=
7cf72477 1683 cpu_to_le32(RD_RACT | RD_RFP | RD_RDLE);
86a74ff2 1684 else
7cf72477 1685 rxdesc->status |= cpu_to_le32(RD_RACT | RD_RFP);
86a74ff2
NI		 1686 }
1687
1688 /* Restart Rx engine if stopped. */
1689 /* If we don't need to check status, don't. -KDU */
79fba9f5 1690 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
a18e08bd 1691 /* fix the values for the next receiving if RDE is set */
6e80e55b 1692 if (intr_status & EESR_RDE && !mdp->cd->no_xdfar) {
128296fc
SS		 1693 u32 count = (sh_eth_read(ndev, RDFAR) -
1694 sh_eth_read(ndev, RDLAR)) >> 4;
1695
1696 mdp->cur_rx = count;
1697 mdp->dirty_rx = count;
1698 }
4a55530f 1699 sh_eth_write(ndev, EDRRR_R, EDRRR);
79fba9f5 1700 }
86a74ff2 1701
319cd520
MK		 1702 *quota -= limit - boguscnt - 1;
1703
4f809cea 1704 return *quota <= 0;
86a74ff2
NI		 1705}
1706
4a55530f 1707static void sh_eth_rcv_snd_disable(struct net_device *ndev)
dc19e4e5
NI		 1708{
1709 /* disable tx and rx */
b2b14d2f 1710 sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0);
dc19e4e5
NI		 1711}
1712
4a55530f 1713static void sh_eth_rcv_snd_enable(struct net_device *ndev)
dc19e4e5
NI		 1714{
1715 /* enable tx and rx */
b2b14d2f 1716 sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE);
dc19e4e5
NI		 1717}
1718
9b39f05c
SS		 1719/* E-MAC interrupt handler */
1720static void sh_eth_emac_interrupt(struct net_device *ndev)
86a74ff2
NI		 1721{
1722 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2 1723 u32 felic_stat;
380af9e3 1724 u32 link_stat;
86a74ff2 1725
9b39f05c
SS		 1726 felic_stat = sh_eth_read(ndev, ECSR) & sh_eth_read(ndev, ECSIPR);
1727 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */
1728 if (felic_stat & ECSR_ICD)
1729 ndev->stats.tx_carrier_errors++;
0cf45a3b
NS		 1730 if (felic_stat & ECSR_MPD)
1731 pm_wakeup_event(&mdp->pdev->dev, 0);
9b39f05c
SS		 1732 if (felic_stat & ECSR_LCHNG) {
1733 /* Link Changed */
1734 if (mdp->cd->no_psr || mdp->no_ether_link)
1735 return;
1736 link_stat = sh_eth_read(ndev, PSR);
1737 if (mdp->ether_link_active_low)
1738 link_stat = ~link_stat;
1739 if (!(link_stat & PHY_ST_LINK)) {
1740 sh_eth_rcv_snd_disable(ndev);
1741 } else {
1742 /* Link Up */
1a0bee6c 1743 sh_eth_modify(ndev, EESIPR, EESIPR_ECIIP, 0);
9b39f05c
SS		 1744 /* clear int */
1745 sh_eth_modify(ndev, ECSR, 0, 0);
1a0bee6c 1746 sh_eth_modify(ndev, EESIPR, EESIPR_ECIIP, EESIPR_ECIIP);
9b39f05c
SS		 1747 /* enable tx and rx */
1748 sh_eth_rcv_snd_enable(ndev);
86a74ff2
NI		 1749 }
1750 }
9b39f05c
SS		 1751}
1752
1753/* error control function */
1754static void sh_eth_error(struct net_device *ndev, u32 intr_status)
1755{
1756 struct sh_eth_private *mdp = netdev_priv(ndev);
1757 u32 mask;
86a74ff2
NI		 1758
1759 if (intr_status & EESR_TWB) {
4eb313a7
SS		 1760 /* Unused write back interrupt */
1761 if (intr_status & EESR_TABT) { /* Transmit Abort int */
bb7d92e3 1762 ndev->stats.tx_aborted_errors++;
8d5009f6 1763 netif_err(mdp, tx_err, ndev, "Transmit Abort\n");
4eb313a7 1764 }
86a74ff2
NI		 1765 }
1766
1767 if (intr_status & EESR_RABT) {
1768 /* Receive Abort int */
1769 if (intr_status & EESR_RFRMER) {
1770 /* Receive Frame Overflow int */
bb7d92e3 1771 ndev->stats.rx_frame_errors++;
86a74ff2
NI		 1772 }
1773 }
380af9e3 1774
dc19e4e5
NI		 1775 if (intr_status & EESR_TDE) {
1776 /* Transmit Descriptor Empty int */
bb7d92e3 1777 ndev->stats.tx_fifo_errors++;
8d5009f6 1778 netif_err(mdp, tx_err, ndev, "Transmit Descriptor Empty\n");
dc19e4e5
NI		 1779 }
1780
1781 if (intr_status & EESR_TFE) {
1782 /* FIFO under flow */
bb7d92e3 1783 ndev->stats.tx_fifo_errors++;
8d5009f6 1784 netif_err(mdp, tx_err, ndev, "Transmit FIFO Under flow\n");
86a74ff2
NI		 1785 }
1786
1787 if (intr_status & EESR_RDE) {
1788 /* Receive Descriptor Empty int */
bb7d92e3 1789 ndev->stats.rx_over_errors++;
86a74ff2 1790 }
dc19e4e5 1791
86a74ff2
NI		 1792 if (intr_status & EESR_RFE) {
1793 /* Receive FIFO Overflow int */
bb7d92e3 1794 ndev->stats.rx_fifo_errors++;
dc19e4e5
NI		 1795 }
1796
1797 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1798 /* Address Error */
bb7d92e3 1799 ndev->stats.tx_fifo_errors++;
8d5009f6 1800 netif_err(mdp, tx_err, ndev, "Address Error\n");
86a74ff2 1801 }
380af9e3
YS		 1802
1803 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1804 if (mdp->cd->no_ade)
1805 mask &= ~EESR_ADE;
1806 if (intr_status & mask) {
86a74ff2 1807 /* Tx error */
4a55530f 1808 u32 edtrr = sh_eth_read(ndev, EDTRR);
090d560f 1809
86a74ff2 1810 /* dmesg */
da246855
SS		 1811 netdev_err(ndev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1812 intr_status, mdp->cur_tx, mdp->dirty_tx,
1813 (u32)ndev->state, edtrr);
86a74ff2 1814 /* dirty buffer free */
1debdc8f 1815 sh_eth_tx_free(ndev, true);
86a74ff2
NI		 1816
1817 /* SH7712 BUG */
3e416992 1818 if (edtrr ^ mdp->cd->edtrr_trns) {
86a74ff2 1819 /* tx dma start */
3e416992 1820 sh_eth_write(ndev, mdp->cd->edtrr_trns, EDTRR);
86a74ff2
NI		 1821 }
1822 /* wakeup */
1823 netif_wake_queue(ndev);
1824 }
1825}
1826
1827static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1828{
1829 struct net_device *ndev = netdev;
1830 struct sh_eth_private *mdp = netdev_priv(ndev);
380af9e3 1831 struct sh_eth_cpu_data *cd = mdp->cd;
0e0fde3c 1832 irqreturn_t ret = IRQ_NONE;
0799c2d6 1833 u32 intr_status, intr_enable;
86a74ff2 1834
86a74ff2
NI		 1835 spin_lock(&mdp->lock);
1836
3893b273 1837 /* Get interrupt status */
4a55530f 1838 intr_status = sh_eth_read(ndev, EESR);
9b39f05c
SS		 1839 /* Mask it with the interrupt mask, forcing ECI interrupt to be always
1840 * enabled since it's the one that comes thru regardless of the mask,
1841 * and we need to fully handle it in sh_eth_emac_interrupt() in order
1842 * to quench it as it doesn't get cleared by just writing 1 to the ECI
1843 * bit...
3893b273 1844 */
3719109d 1845 intr_enable = sh_eth_read(ndev, EESIPR);
1a0bee6c 1846 intr_status &= intr_enable | EESIPR_ECIIP;
9b39f05c
SS		 1847 if (intr_status & (EESR_RX_CHECK | cd->tx_check | EESR_ECI |
1848 cd->eesr_err_check))
0e0fde3c 1849 ret = IRQ_HANDLED;
3719109d 1850 else
283e38db
BH		 1851 goto out;
1852
2344ef3c 1853 if (unlikely(!mdp->irq_enabled)) {
283e38db
BH		 1854 sh_eth_write(ndev, 0, EESIPR);
1855 goto out;
1856 }
86a74ff2 1857
3719109d
SS		 1858 if (intr_status & EESR_RX_CHECK) {
1859 if (napi_schedule_prep(&mdp->napi)) {
1860 /* Mask Rx interrupts */
1861 sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK,
1862 EESIPR);
1863 __napi_schedule(&mdp->napi);
1864 } else {
da246855 1865 netdev_warn(ndev,
0799c2d6 1866 "ignoring interrupt, status 0x%08x, mask 0x%08x.\n",
da246855 1867 intr_status, intr_enable);
3719109d
SS		 1868 }
1869 }
86a74ff2 1870
b0ca2a21 1871 /* Tx Check */
380af9e3 1872 if (intr_status & cd->tx_check) {
3719109d
SS		 1873 /* Clear Tx interrupts */
1874 sh_eth_write(ndev, intr_status & cd->tx_check, EESR);
1875
1debdc8f 1876 sh_eth_tx_free(ndev, true);
86a74ff2
NI		 1877 netif_wake_queue(ndev);
1878 }
1879
9b39f05c
SS		 1880 /* E-MAC interrupt */
1881 if (intr_status & EESR_ECI)
1882 sh_eth_emac_interrupt(ndev);
1883
3719109d
SS		 1884 if (intr_status & cd->eesr_err_check) {
1885 /* Clear error interrupts */
1886 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR);
1887
86a74ff2 1888 sh_eth_error(ndev, intr_status);
3719109d 1889 }
86a74ff2 1890
283e38db 1891out:
86a74ff2
NI		 1892 spin_unlock(&mdp->lock);
1893
0e0fde3c 1894 return ret;
86a74ff2
NI		 1895}
1896
3719109d
SS		 1897static int sh_eth_poll(struct napi_struct *napi, int budget)
1898{
1899 struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private,
1900 napi);
1901 struct net_device *ndev = napi->dev;
1902 int quota = budget;
0799c2d6 1903 u32 intr_status;
3719109d
SS		 1904
1905 for (;;) {
1906 intr_status = sh_eth_read(ndev, EESR);
1907 if (!(intr_status & EESR_RX_CHECK))
1908 break;
1909 /* Clear Rx interrupts */
1910 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR);
1911
1912 if (sh_eth_rx(ndev, intr_status, &quota))
1913 goto out;
1914 }
1915
1916 napi_complete(napi);
1917
1918 /* Reenable Rx interrupts */
283e38db
BH		 1919 if (mdp->irq_enabled)
1920 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
3719109d
SS		 1921out:
1922 return budget - quota;
1923}
1924
86a74ff2
NI		 1925/* PHY state control function */
1926static void sh_eth_adjust_link(struct net_device *ndev)
1927{
1928 struct sh_eth_private *mdp = netdev_priv(ndev);
9fd0375a 1929 struct phy_device *phydev = ndev->phydev;
86a74ff2
NI		 1930 int new_state = 0;
1931
3340d2aa 1932 if (phydev->link) {
86a74ff2
NI		 1933 if (phydev->duplex != mdp->duplex) {
1934 new_state = 1;
1935 mdp->duplex = phydev->duplex;
380af9e3
YS		 1936 if (mdp->cd->set_duplex)
1937 mdp->cd->set_duplex(ndev);
86a74ff2
NI		 1938 }
1939
1940 if (phydev->speed != mdp->speed) {
1941 new_state = 1;
1942 mdp->speed = phydev->speed;
380af9e3
YS		 1943 if (mdp->cd->set_rate)
1944 mdp->cd->set_rate(ndev);
86a74ff2 1945 }
3340d2aa 1946 if (!mdp->link) {
b2b14d2f 1947 sh_eth_modify(ndev, ECMR, ECMR_TXF, 0);
86a74ff2
NI		 1948 new_state = 1;
1949 mdp->link = phydev->link;
1e1b812b
SS		 1950 if (mdp->cd->no_psr || mdp->no_ether_link)
1951 sh_eth_rcv_snd_enable(ndev);
86a74ff2
NI		 1952 }
1953 } else if (mdp->link) {
1954 new_state = 1;
3340d2aa 1955 mdp->link = 0;
86a74ff2
NI		 1956 mdp->speed = 0;
1957 mdp->duplex = -1;
1e1b812b
SS		 1958 if (mdp->cd->no_psr || mdp->no_ether_link)
1959 sh_eth_rcv_snd_disable(ndev);
86a74ff2
NI		 1960 }
1961
dc19e4e5 1962 if (new_state && netif_msg_link(mdp))
86a74ff2
NI		 1963 phy_print_status(phydev);
1964}
1965
1966/* PHY init function */
1967static int sh_eth_phy_init(struct net_device *ndev)
1968{
702eca02 1969 struct device_node *np = ndev->dev.parent->of_node;
86a74ff2 1970 struct sh_eth_private *mdp = netdev_priv(ndev);
4fa8c3cc 1971 struct phy_device *phydev;
86a74ff2 1972
3340d2aa 1973 mdp->link = 0;
86a74ff2
NI		 1974 mdp->speed = 0;
1975 mdp->duplex = -1;
1976
1977 /* Try connect to PHY */
702eca02
BD		 1978 if (np) {
1979 struct device_node *pn;
1980
1981 pn = of_parse_phandle(np, "phy-handle", 0);
1982 phydev = of_phy_connect(ndev, pn,
1983 sh_eth_adjust_link, 0,
1984 mdp->phy_interface);
1985
8da703dc 1986 of_node_put(pn);
702eca02
BD		 1987 if (!phydev)
1988 phydev = ERR_PTR(-ENOENT);
1989 } else {
1990 char phy_id[MII_BUS_ID_SIZE + 3];
1991
1992 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
1993 mdp->mii_bus->id, mdp->phy_id);
1994
1995 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
1996 mdp->phy_interface);
1997 }
1998
86a74ff2 1999 if (IS_ERR(phydev)) {
da246855 2000 netdev_err(ndev, "failed to connect PHY\n");
86a74ff2
NI		 2001 return PTR_ERR(phydev);
2002 }
380af9e3 2003
2aab6b40
TP		 2004 /* mask with MAC supported features */
2005 if (mdp->cd->register_type != SH_ETH_REG_GIGABIT) {
2006 int err = phy_set_max_speed(phydev, SPEED_100);
2007 if (err) {
2008 netdev_err(ndev, "failed to limit PHY to 100 Mbit/s\n");
2009 phy_disconnect(phydev);
2010 return err;
2011 }
2012 }
2013
2220943a 2014 phy_attached_info(phydev);
86a74ff2 2015
86a74ff2
NI		 2016 return 0;
2017}
2018
2019/* PHY control start function */
2020static int sh_eth_phy_start(struct net_device *ndev)
2021{
86a74ff2
NI		 2022 int ret;
2023
2024 ret = sh_eth_phy_init(ndev);
2025 if (ret)
2026 return ret;
2027
9fd0375a 2028 phy_start(ndev->phydev);
86a74ff2
NI		 2029
2030 return 0;
2031}
2032
f08aff44
PR		 2033static int sh_eth_get_link_ksettings(struct net_device *ndev,
2034 struct ethtool_link_ksettings *cmd)
dc19e4e5
NI		 2035{
2036 struct sh_eth_private *mdp = netdev_priv(ndev);
2037 unsigned long flags;
dc19e4e5 2038
9fd0375a 2039 if (!ndev->phydev)
4f9dce23
BH		 2040 return -ENODEV;
2041
dc19e4e5 2042 spin_lock_irqsave(&mdp->lock, flags);
5514174f 2043 phy_ethtool_ksettings_get(ndev->phydev, cmd);
dc19e4e5
NI		 2044 spin_unlock_irqrestore(&mdp->lock, flags);
2045
5514174f 2046 return 0;
dc19e4e5
NI		 2047}
2048
f08aff44
PR		 2049static int sh_eth_set_link_ksettings(struct net_device *ndev,
2050 const struct ethtool_link_ksettings *cmd)
dc19e4e5
NI		 2051{
2052 struct sh_eth_private *mdp = netdev_priv(ndev);
2053 unsigned long flags;
2054 int ret;
dc19e4e5 2055
9fd0375a 2056 if (!ndev->phydev)
4f9dce23
BH		 2057 return -ENODEV;
2058
dc19e4e5
NI		 2059 spin_lock_irqsave(&mdp->lock, flags);
2060
2061 /* disable tx and rx */
4a55530f 2062 sh_eth_rcv_snd_disable(ndev);
dc19e4e5 2063
f08aff44 2064 ret = phy_ethtool_ksettings_set(ndev->phydev, cmd);
dc19e4e5
NI		 2065 if (ret)
2066 goto error_exit;
2067
f08aff44 2068 if (cmd->base.duplex == DUPLEX_FULL)
dc19e4e5
NI		 2069 mdp->duplex = 1;
2070 else
2071 mdp->duplex = 0;
2072
2073 if (mdp->cd->set_duplex)
2074 mdp->cd->set_duplex(ndev);
2075
2076error_exit:
2077 mdelay(1);
2078
2079 /* enable tx and rx */
4a55530f 2080 sh_eth_rcv_snd_enable(ndev);
dc19e4e5
NI		 2081
2082 spin_unlock_irqrestore(&mdp->lock, flags);
2083
2084 return ret;
2085}
2086
6b4b4fea
BH		 2087/* If it is ever necessary to increase SH_ETH_REG_DUMP_MAX_REGS, the
2088 * version must be bumped as well. Just adding registers up to that
2089 * limit is fine, as long as the existing register indices don't
2090 * change.
2091 */
2092#define SH_ETH_REG_DUMP_VERSION 1
2093#define SH_ETH_REG_DUMP_MAX_REGS 256
2094
2095static size_t __sh_eth_get_regs(struct net_device *ndev, u32 *buf)
2096{
2097 struct sh_eth_private *mdp = netdev_priv(ndev);
2098 struct sh_eth_cpu_data *cd = mdp->cd;
2099 u32 *valid_map;
2100 size_t len;
2101
2102 BUILD_BUG_ON(SH_ETH_MAX_REGISTER_OFFSET > SH_ETH_REG_DUMP_MAX_REGS);
2103
2104 /* Dump starts with a bitmap that tells ethtool which
2105 * registers are defined for this chip.
2106 */
2107 len = DIV_ROUND_UP(SH_ETH_REG_DUMP_MAX_REGS, 32);
2108 if (buf) {
2109 valid_map = buf;
2110 buf += len;
2111 } else {
2112 valid_map = NULL;
2113 }
2114
2115 /* Add a register to the dump, if it has a defined offset.
2116 * This automatically skips most undefined registers, but for
2117 * some it is also necessary to check a capability flag in
2118 * struct sh_eth_cpu_data.
2119 */
2120#define mark_reg_valid(reg) valid_map[reg / 32] |= 1U << (reg % 32)
2121#define add_reg_from(reg, read_expr) do { \
2122 if (mdp->reg_offset[reg] != SH_ETH_OFFSET_INVALID) { \
2123 if (buf) { \
2124 mark_reg_valid(reg); \
2125 *buf++ = read_expr; \
2126 } \
2127 ++len; \
2128 } \
2129 } while (0)
2130#define add_reg(reg) add_reg_from(reg, sh_eth_read(ndev, reg))
2131#define add_tsu_reg(reg) add_reg_from(reg, sh_eth_tsu_read(mdp, reg))
2132
2133 add_reg(EDSR);
2134 add_reg(EDMR);
2135 add_reg(EDTRR);
2136 add_reg(EDRRR);
2137 add_reg(EESR);
2138 add_reg(EESIPR);
2139 add_reg(TDLAR);
2140 add_reg(TDFAR);
2141 add_reg(TDFXR);
2142 add_reg(TDFFR);
2143 add_reg(RDLAR);
2144 add_reg(RDFAR);
2145 add_reg(RDFXR);
2146 add_reg(RDFFR);
2147 add_reg(TRSCER);
2148 add_reg(RMFCR);
2149 add_reg(TFTR);
2150 add_reg(FDR);
2151 add_reg(RMCR);
2152 add_reg(TFUCR);
2153 add_reg(RFOCR);
2154 if (cd->rmiimode)
2155 add_reg(RMIIMODE);
2156 add_reg(FCFTR);
2157 if (cd->rpadir)
2158 add_reg(RPADIR);
2159 if (!cd->no_trimd)
2160 add_reg(TRIMD);
2161 add_reg(ECMR);
2162 add_reg(ECSR);
2163 add_reg(ECSIPR);
2164 add_reg(PIR);
2165 if (!cd->no_psr)
2166 add_reg(PSR);
2167 add_reg(RDMLR);
2168 add_reg(RFLR);
2169 add_reg(IPGR);
2170 if (cd->apr)
2171 add_reg(APR);
2172 if (cd->mpr)
2173 add_reg(MPR);
2174 add_reg(RFCR);
2175 add_reg(RFCF);
2176 if (cd->tpauser)
2177 add_reg(TPAUSER);
2178 add_reg(TPAUSECR);
2179 add_reg(GECMR);
2180 if (cd->bculr)
2181 add_reg(BCULR);
2182 add_reg(MAHR);
2183 add_reg(MALR);
2184 add_reg(TROCR);
2185 add_reg(CDCR);
2186 add_reg(LCCR);
2187 add_reg(CNDCR);
2188 add_reg(CEFCR);
2189 add_reg(FRECR);
2190 add_reg(TSFRCR);
2191 add_reg(TLFRCR);
2192 add_reg(CERCR);
2193 add_reg(CEECR);
2194 add_reg(MAFCR);
2195 if (cd->rtrate)
2196 add_reg(RTRATE);
62e04b7e 2197 if (cd->hw_checksum)
6b4b4fea
BH		 2198 add_reg(CSMR);
2199 if (cd->select_mii)
2200 add_reg(RMII_MII);
6b4b4fea 2201 if (cd->tsu) {
17d0fb0c 2202 add_tsu_reg(ARSTR);
6b4b4fea
BH		 2203 add_tsu_reg(TSU_CTRST);
2204 add_tsu_reg(TSU_FWEN0);
2205 add_tsu_reg(TSU_FWEN1);
2206 add_tsu_reg(TSU_FCM);
2207 add_tsu_reg(TSU_BSYSL0);
2208 add_tsu_reg(TSU_BSYSL1);
2209 add_tsu_reg(TSU_PRISL0);
2210 add_tsu_reg(TSU_PRISL1);
2211 add_tsu_reg(TSU_FWSL0);
2212 add_tsu_reg(TSU_FWSL1);
2213 add_tsu_reg(TSU_FWSLC);
6b4b4fea
BH		 2214 add_tsu_reg(TSU_QTAGM0);
2215 add_tsu_reg(TSU_QTAGM1);
2216 add_tsu_reg(TSU_FWSR);
2217 add_tsu_reg(TSU_FWINMK);
2218 add_tsu_reg(TSU_ADQT0);
2219 add_tsu_reg(TSU_ADQT1);
2220 add_tsu_reg(TSU_VTAG0);
2221 add_tsu_reg(TSU_VTAG1);
2222 add_tsu_reg(TSU_ADSBSY);
2223 add_tsu_reg(TSU_TEN);
2224 add_tsu_reg(TSU_POST1);
2225 add_tsu_reg(TSU_POST2);
2226 add_tsu_reg(TSU_POST3);
2227 add_tsu_reg(TSU_POST4);
e14549a5
SS		 2228 /* This is the start of a table, not just a single register. */
2229 if (buf) {
2230 unsigned int i;
2231
2232 mark_reg_valid(TSU_ADRH0);
2233 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES * 2; i++)
2234 *buf++ = ioread32(mdp->tsu_addr +
2235 mdp->reg_offset[TSU_ADRH0] +
2236 i * 4);
6b4b4fea 2237 }
e14549a5 2238 len += SH_ETH_TSU_CAM_ENTRIES * 2;
6b4b4fea
BH		 2239 }
2240
2241#undef mark_reg_valid
2242#undef add_reg_from
2243#undef add_reg
2244#undef add_tsu_reg
2245
2246 return len * 4;
2247}
2248
2249static int sh_eth_get_regs_len(struct net_device *ndev)
2250{
2251 return __sh_eth_get_regs(ndev, NULL);
2252}
2253
2254static void sh_eth_get_regs(struct net_device *ndev, struct ethtool_regs *regs,
2255 void *buf)
2256{
2257 struct sh_eth_private *mdp = netdev_priv(ndev);
2258
2259 regs->version = SH_ETH_REG_DUMP_VERSION;
2260
2261 pm_runtime_get_sync(&mdp->pdev->dev);
2262 __sh_eth_get_regs(ndev, buf);
2263 pm_runtime_put_sync(&mdp->pdev->dev);
2264}
2265
dc19e4e5
NI		 2266static int sh_eth_nway_reset(struct net_device *ndev)
2267{
2268 struct sh_eth_private *mdp = netdev_priv(ndev);
2269 unsigned long flags;
2270 int ret;
2271
9fd0375a 2272 if (!ndev->phydev)
4f9dce23
BH		 2273 return -ENODEV;
2274
dc19e4e5 2275 spin_lock_irqsave(&mdp->lock, flags);
9fd0375a 2276 ret = phy_start_aneg(ndev->phydev);
dc19e4e5
NI		 2277 spin_unlock_irqrestore(&mdp->lock, flags);
2278
2279 return ret;
2280}
2281
2282static u32 sh_eth_get_msglevel(struct net_device *ndev)
2283{
2284 struct sh_eth_private *mdp = netdev_priv(ndev);
2285 return mdp->msg_enable;
2286}
2287
2288static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
2289{
2290 struct sh_eth_private *mdp = netdev_priv(ndev);
2291 mdp->msg_enable = value;
2292}
2293
2294static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
2295 "rx_current", "tx_current",
2296 "rx_dirty", "tx_dirty",
2297};
2298#define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats)
2299
2300static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
2301{
2302 switch (sset) {
2303 case ETH_SS_STATS:
2304 return SH_ETH_STATS_LEN;
2305 default:
2306 return -EOPNOTSUPP;
2307 }
2308}
2309
2310static void sh_eth_get_ethtool_stats(struct net_device *ndev,
128296fc 2311 struct ethtool_stats *stats, u64 *data)
dc19e4e5
NI		 2312{
2313 struct sh_eth_private *mdp = netdev_priv(ndev);
2314 int i = 0;
2315
2316 /* device-specific stats */
2317 data[i++] = mdp->cur_rx;
2318 data[i++] = mdp->cur_tx;
2319 data[i++] = mdp->dirty_rx;
2320 data[i++] = mdp->dirty_tx;
2321}
2322
2323static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
2324{
2325 switch (stringset) {
2326 case ETH_SS_STATS:
2327 memcpy(data, *sh_eth_gstrings_stats,
128296fc 2328 sizeof(sh_eth_gstrings_stats));
dc19e4e5
NI		 2329 break;
2330 }
2331}
2332
525b8075
YS		 2333static void sh_eth_get_ringparam(struct net_device *ndev,
2334 struct ethtool_ringparam *ring)
2335{
2336 struct sh_eth_private *mdp = netdev_priv(ndev);
2337
2338 ring->rx_max_pending = RX_RING_MAX;
2339 ring->tx_max_pending = TX_RING_MAX;
2340 ring->rx_pending = mdp->num_rx_ring;
2341 ring->tx_pending = mdp->num_tx_ring;
2342}
2343
2344static int sh_eth_set_ringparam(struct net_device *ndev,
2345 struct ethtool_ringparam *ring)
2346{
2347 struct sh_eth_private *mdp = netdev_priv(ndev);
2348 int ret;
2349
2350 if (ring->tx_pending > TX_RING_MAX ||
2351 ring->rx_pending > RX_RING_MAX ||
2352 ring->tx_pending < TX_RING_MIN ||
2353 ring->rx_pending < RX_RING_MIN)
2354 return -EINVAL;
2355 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
2356 return -EINVAL;
2357
2358 if (netif_running(ndev)) {
bd888916 2359 netif_device_detach(ndev);
525b8075 2360 netif_tx_disable(ndev);
283e38db
BH		 2361
2362 /* Serialise with the interrupt handler and NAPI, then
2363 * disable interrupts. We have to clear the
2364 * irq_enabled flag first to ensure that interrupts
2365 * won't be re-enabled.
2366 */
2367 mdp->irq_enabled = false;
525b8075 2368 synchronize_irq(ndev->irq);
283e38db 2369 napi_synchronize(&mdp->napi);
525b8075 2370 sh_eth_write(ndev, 0x0000, EESIPR);
525b8075 2371
740c7f31 2372 sh_eth_dev_exit(ndev);
525b8075 2373
8e03a5e7 2374 /* Free all the skbuffs in the Rx queue and the DMA buffers. */
084236d8 2375 sh_eth_ring_free(ndev);
084236d8 2376 }
525b8075
YS		 2377
2378 /* Set new parameters */
2379 mdp->num_rx_ring = ring->rx_pending;
2380 mdp->num_tx_ring = ring->tx_pending;
2381
525b8075 2382 if (netif_running(ndev)) {
084236d8
BH		 2383 ret = sh_eth_ring_init(ndev);
2384 if (ret < 0) {
2385 netdev_err(ndev, "%s: sh_eth_ring_init failed.\n",
2386 __func__);
2387 return ret;
2388 }
f7967210 2389 ret = sh_eth_dev_init(ndev);
084236d8
BH		 2390 if (ret < 0) {
2391 netdev_err(ndev, "%s: sh_eth_dev_init failed.\n",
2392 __func__);
2393 return ret;
2394 }
2395
bd888916 2396 netif_device_attach(ndev);
525b8075
YS		 2397 }
2398
2399 return 0;
2400}
2401
d8981d02
NS		 2402static void sh_eth_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2403{
2404 struct sh_eth_private *mdp = netdev_priv(ndev);
2405
2406 wol->supported = 0;
2407 wol->wolopts = 0;
2408
b4580c95 2409 if (mdp->cd->magic) {
d8981d02
NS		 2410 wol->supported = WAKE_MAGIC;
2411 wol->wolopts = mdp->wol_enabled ? WAKE_MAGIC : 0;
2412 }
2413}
2414
2415static int sh_eth_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2416{
2417 struct sh_eth_private *mdp = netdev_priv(ndev);
2418
b4580c95 2419 if (!mdp->cd->magic || wol->wolopts & ~WAKE_MAGIC)
d8981d02
NS		 2420 return -EOPNOTSUPP;
2421
2422 mdp->wol_enabled = !!(wol->wolopts & WAKE_MAGIC);
2423
2424 device_set_wakeup_enable(&mdp->pdev->dev, mdp->wol_enabled);
2425
2426 return 0;
2427}
2428
9b07be4b 2429static const struct ethtool_ops sh_eth_ethtool_ops = {
6b4b4fea
BH		 2430 .get_regs_len = sh_eth_get_regs_len,
2431 .get_regs = sh_eth_get_regs,
9b07be4b 2432 .nway_reset = sh_eth_nway_reset,
dc19e4e5
NI		 2433 .get_msglevel = sh_eth_get_msglevel,
2434 .set_msglevel = sh_eth_set_msglevel,
9b07be4b 2435 .get_link = ethtool_op_get_link,
dc19e4e5
NI		 2436 .get_strings = sh_eth_get_strings,
2437 .get_ethtool_stats = sh_eth_get_ethtool_stats,
2438 .get_sset_count = sh_eth_get_sset_count,
525b8075
YS		 2439 .get_ringparam = sh_eth_get_ringparam,
2440 .set_ringparam = sh_eth_set_ringparam,
f08aff44
PR		 2441 .get_link_ksettings = sh_eth_get_link_ksettings,
2442 .set_link_ksettings = sh_eth_set_link_ksettings,
d8981d02
NS		 2443 .get_wol = sh_eth_get_wol,
2444 .set_wol = sh_eth_set_wol,
dc19e4e5
NI		 2445};
2446
86a74ff2
NI		 2447/* network device open function */
2448static int sh_eth_open(struct net_device *ndev)
2449{
86a74ff2 2450 struct sh_eth_private *mdp = netdev_priv(ndev);
4fa8c3cc 2451 int ret;
86a74ff2 2452
bcd5149d
MD		 2453 pm_runtime_get_sync(&mdp->pdev->dev);
2454
d2779e99
SS		 2455 napi_enable(&mdp->napi);
2456
a0607fd3 2457 ret = request_irq(ndev->irq, sh_eth_interrupt,
5b3dfd13 2458 mdp->cd->irq_flags, ndev->name, ndev);
86a74ff2 2459 if (ret) {
da246855 2460 netdev_err(ndev, "Can not assign IRQ number\n");
d2779e99 2461 goto out_napi_off;
86a74ff2
NI		 2462 }
2463
2464 /* Descriptor set */
2465 ret = sh_eth_ring_init(ndev);
2466 if (ret)
2467 goto out_free_irq;
2468
2469 /* device init */
f7967210 2470 ret = sh_eth_dev_init(ndev);
86a74ff2
NI		 2471 if (ret)
2472 goto out_free_irq;
2473
2474 /* PHY control start*/
2475 ret = sh_eth_phy_start(ndev);
2476 if (ret)
2477 goto out_free_irq;
2478
ad846aa5
SS		 2479 netif_start_queue(ndev);
2480
7fa2955f
MK		 2481 mdp->is_opened = 1;
2482
86a74ff2
NI		 2483 return ret;
2484
2485out_free_irq:
2486 free_irq(ndev->irq, ndev);
d2779e99
SS		 2487out_napi_off:
2488 napi_disable(&mdp->napi);
bcd5149d 2489 pm_runtime_put_sync(&mdp->pdev->dev);
86a74ff2
NI		 2490 return ret;
2491}
2492
2493/* Timeout function */
2494static void sh_eth_tx_timeout(struct net_device *ndev)
2495{
2496 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 2497 struct sh_eth_rxdesc *rxdesc;
2498 int i;
2499
2500 netif_stop_queue(ndev);
2501
8d5009f6
SS		 2502 netif_err(mdp, timer, ndev,
2503 "transmit timed out, status %8.8x, resetting...\n",
0799c2d6 2504 sh_eth_read(ndev, EESR));
86a74ff2
NI		 2505
2506 /* tx_errors count up */
bb7d92e3 2507 ndev->stats.tx_errors++;
86a74ff2 2508
86a74ff2 2509 /* Free all the skbuffs in the Rx queue. */
525b8075 2510 for (i = 0; i < mdp->num_rx_ring; i++) {
86a74ff2 2511 rxdesc = &mdp->rx_ring[i];
7cf72477
SS		 2512 rxdesc->status = cpu_to_le32(0);
2513 rxdesc->addr = cpu_to_le32(0xBADF00D0);
179d80af 2514 dev_kfree_skb(mdp->rx_skbuff[i]);
86a74ff2
NI		 2515 mdp->rx_skbuff[i] = NULL;
2516 }
525b8075 2517 for (i = 0; i < mdp->num_tx_ring; i++) {
179d80af 2518 dev_kfree_skb(mdp->tx_skbuff[i]);
86a74ff2
NI		 2519 mdp->tx_skbuff[i] = NULL;
2520 }
2521
2522 /* device init */
f7967210 2523 sh_eth_dev_init(ndev);
ad846aa5
SS		 2524
2525 netif_start_queue(ndev);
86a74ff2
NI		 2526}
2527
2528/* Packet transmit function */
2529static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
2530{
2531 struct sh_eth_private *mdp = netdev_priv(ndev);
2532 struct sh_eth_txdesc *txdesc;
1299653a 2533 dma_addr_t dma_addr;
86a74ff2 2534 u32 entry;
fb5e2f9b 2535 unsigned long flags;
86a74ff2
NI		 2536
2537 spin_lock_irqsave(&mdp->lock, flags);
525b8075 2538 if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
1debdc8f 2539 if (!sh_eth_tx_free(ndev, true)) {
8d5009f6 2540 netif_warn(mdp, tx_queued, ndev, "TxFD exhausted.\n");
86a74ff2
NI		 2541 netif_stop_queue(ndev);
2542 spin_unlock_irqrestore(&mdp->lock, flags);
5b548140 2543 return NETDEV_TX_BUSY;
86a74ff2
NI		 2544 }
2545 }
2546 spin_unlock_irqrestore(&mdp->lock, flags);
2547
dacc73e0 2548 if (skb_put_padto(skb, ETH_ZLEN))
eebfb643
BH		 2549 return NETDEV_TX_OK;
2550
525b8075 2551 entry = mdp->cur_tx % mdp->num_tx_ring;
86a74ff2
NI		 2552 mdp->tx_skbuff[entry] = skb;
2553 txdesc = &mdp->tx_ring[entry];
86a74ff2 2554 /* soft swap. */
380af9e3 2555 if (!mdp->cd->hw_swap)
3e230993 2556 sh_eth_soft_swap(PTR_ALIGN(skb->data, 4), skb->len + 2);
22c1aed4 2557 dma_addr = dma_map_single(&mdp->pdev->dev, skb->data, skb->len,
1299653a 2558 DMA_TO_DEVICE);
22c1aed4 2559 if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) {
aa3933b8
BH		 2560 kfree_skb(skb);
2561 return NETDEV_TX_OK;
2562 }
7cf72477
SS		 2563 txdesc->addr = cpu_to_le32(dma_addr);
2564 txdesc->len = cpu_to_le32(skb->len << 16);
86a74ff2 2565
f32bfb9a 2566 dma_wmb(); /* TACT bit must be set after all the above writes */
525b8075 2567 if (entry >= mdp->num_tx_ring - 1)
7cf72477 2568 txdesc->status |= cpu_to_le32(TD_TACT | TD_TDLE);
86a74ff2 2569 else
7cf72477 2570 txdesc->status |= cpu_to_le32(TD_TACT);
86a74ff2
NI		 2571
2572 mdp->cur_tx++;
2573
3e416992
SS		 2574 if (!(sh_eth_read(ndev, EDTRR) & mdp->cd->edtrr_trns))
2575 sh_eth_write(ndev, mdp->cd->edtrr_trns, EDTRR);
b0ca2a21 2576
6ed10654 2577 return NETDEV_TX_OK;
86a74ff2
NI		 2578}
2579
4398f9c8
BH		 2580/* The statistics registers have write-clear behaviour, which means we
2581 * will lose any increment between the read and write. We mitigate
2582 * this by only clearing when we read a non-zero value, so we will
2583 * never falsely report a total of zero.
2584 */
2585static void
2586sh_eth_update_stat(struct net_device *ndev, unsigned long *stat, int reg)
2587{
2588 u32 delta = sh_eth_read(ndev, reg);
2589
2590 if (delta) {
2591 *stat += delta;
2592 sh_eth_write(ndev, 0, reg);
2593 }
2594}
2595
7fa2955f
MK		 2596static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
2597{
2598 struct sh_eth_private *mdp = netdev_priv(ndev);
2599
ce9134df 2600 if (mdp->cd->no_tx_cntrs)
7fa2955f
MK		 2601 return &ndev->stats;
2602
2603 if (!mdp->is_opened)
2604 return &ndev->stats;
2605
4398f9c8
BH		 2606 sh_eth_update_stat(ndev, &ndev->stats.tx_dropped, TROCR);
2607 sh_eth_update_stat(ndev, &ndev->stats.collisions, CDCR);
2608 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, LCCR);
7fa2955f 2609
4c1d4585 2610 if (mdp->cd->cexcr) {
4398f9c8
BH		 2611 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2612 CERCR);
2613 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2614 CEECR);
7fa2955f 2615 } else {
4398f9c8
BH		 2616 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2617 CNDCR);
7fa2955f
MK		 2618 }
2619
2620 return &ndev->stats;
2621}
2622
86a74ff2
NI		 2623/* device close function */
2624static int sh_eth_close(struct net_device *ndev)
2625{
2626 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 2627
2628 netif_stop_queue(ndev);
2629
283e38db
BH		 2630 /* Serialise with the interrupt handler and NAPI, then disable
2631 * interrupts. We have to clear the irq_enabled flag first to
2632 * ensure that interrupts won't be re-enabled.
2633 */
2634 mdp->irq_enabled = false;
2635 synchronize_irq(ndev->irq);
2636 napi_disable(&mdp->napi);
4a55530f 2637 sh_eth_write(ndev, 0x0000, EESIPR);
86a74ff2 2638
740c7f31 2639 sh_eth_dev_exit(ndev);
86a74ff2
NI		 2640
2641 /* PHY Disconnect */
9fd0375a
PR		 2642 if (ndev->phydev) {
2643 phy_stop(ndev->phydev);
2644 phy_disconnect(ndev->phydev);
86a74ff2
NI		 2645 }
2646
2647 free_irq(ndev->irq, ndev);
2648
8e03a5e7 2649 /* Free all the skbuffs in the Rx queue and the DMA buffer. */
86a74ff2
NI		 2650 sh_eth_ring_free(ndev);
2651
bcd5149d
MD		 2652 pm_runtime_put_sync(&mdp->pdev->dev);
2653
7fa2955f 2654 mdp->is_opened = 0;
bcd5149d 2655
7fa2955f 2656 return 0;
86a74ff2
NI		 2657}
2658
bb7d92e3 2659/* ioctl to device function */
128296fc 2660static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
86a74ff2 2661{
9fd0375a 2662 struct phy_device *phydev = ndev->phydev;
86a74ff2
NI		 2663
2664 if (!netif_running(ndev))
2665 return -EINVAL;
2666
2667 if (!phydev)
2668 return -ENODEV;
2669
28b04113 2670 return phy_mii_ioctl(phydev, rq, cmd);
86a74ff2
NI		 2671}
2672
78d61022
NS		 2673static int sh_eth_change_mtu(struct net_device *ndev, int new_mtu)
2674{
2675 if (netif_running(ndev))
2676 return -EBUSY;
2677
2678 ndev->mtu = new_mtu;
2679 netdev_update_features(ndev);
2680
2681 return 0;
2682}
2683
6743fe6d 2684/* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
6743fe6d
YS		 2685static u32 sh_eth_tsu_get_post_mask(int entry)
2686{
2687 return 0x0f << (28 - ((entry % 8) * 4));
2688}
2689
2690static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
2691{
2692 return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
2693}
2694
2695static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
2696 int entry)
2697{
2698 struct sh_eth_private *mdp = netdev_priv(ndev);
77cb065f 2699 int reg = TSU_POST1 + entry / 8;
6743fe6d 2700 u32 tmp;
6743fe6d 2701
77cb065f
SS		 2702 tmp = sh_eth_tsu_read(mdp, reg);
2703 sh_eth_tsu_write(mdp, tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg);
6743fe6d
YS		 2704}
2705
2706static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
2707 int entry)
2708{
2709 struct sh_eth_private *mdp = netdev_priv(ndev);
77cb065f 2710 int reg = TSU_POST1 + entry / 8;
6743fe6d 2711 u32 post_mask, ref_mask, tmp;
6743fe6d 2712
6743fe6d
YS		 2713 post_mask = sh_eth_tsu_get_post_mask(entry);
2714 ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
2715
77cb065f
SS		 2716 tmp = sh_eth_tsu_read(mdp, reg);
2717 sh_eth_tsu_write(mdp, tmp & ~post_mask, reg);
6743fe6d
YS		 2718
2719 /* If other port enables, the function returns "true" */
2720 return tmp & ref_mask;
2721}
2722
2723static int sh_eth_tsu_busy(struct net_device *ndev)
2724{
2725 int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
2726 struct sh_eth_private *mdp = netdev_priv(ndev);
2727
2728 while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
2729 udelay(10);
2730 timeout--;
2731 if (timeout <= 0) {
da246855 2732 netdev_err(ndev, "%s: timeout\n", __func__);
6743fe6d
YS		 2733 return -ETIMEDOUT;
2734 }
2735 }
2736
2737 return 0;
2738}
2739
2740static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg,
2741 const u8 *addr)
2742{
2743 u32 val;
2744
2745 val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
2746 iowrite32(val, reg);
2747 if (sh_eth_tsu_busy(ndev) < 0)
2748 return -EBUSY;
2749
2750 val = addr[4] << 8 | addr[5];
2751 iowrite32(val, reg + 4);
2752 if (sh_eth_tsu_busy(ndev) < 0)
2753 return -EBUSY;
2754
2755 return 0;
2756}
2757
2758static void sh_eth_tsu_read_entry(void *reg, u8 *addr)
2759{
2760 u32 val;
2761
2762 val = ioread32(reg);
2763 addr[0] = (val >> 24) & 0xff;
2764 addr[1] = (val >> 16) & 0xff;
2765 addr[2] = (val >> 8) & 0xff;
2766 addr[3] = val & 0xff;
2767 val = ioread32(reg + 4);
2768 addr[4] = (val >> 8) & 0xff;
2769 addr[5] = val & 0xff;
2770}
2771
2772
2773static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
2774{
2775 struct sh_eth_private *mdp = netdev_priv(ndev);
2776 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2777 int i;
2778 u8 c_addr[ETH_ALEN];
2779
2780 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2781 sh_eth_tsu_read_entry(reg_offset, c_addr);
c4bde29c 2782 if (ether_addr_equal(addr, c_addr))
6743fe6d
YS		 2783 return i;
2784 }
2785
2786 return -ENOENT;
2787}
2788
2789static int sh_eth_tsu_find_empty(struct net_device *ndev)
2790{
2791 u8 blank[ETH_ALEN];
2792 int entry;
2793
2794 memset(blank, 0, sizeof(blank));
2795 entry = sh_eth_tsu_find_entry(ndev, blank);
2796 return (entry < 0) ? -ENOMEM : entry;
2797}
2798
2799static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
2800 int entry)
2801{
2802 struct sh_eth_private *mdp = netdev_priv(ndev);
2803 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2804 int ret;
2805 u8 blank[ETH_ALEN];
2806
2807 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
2808 ~(1 << (31 - entry)), TSU_TEN);
2809
2810 memset(blank, 0, sizeof(blank));
2811 ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
2812 if (ret < 0)
2813 return ret;
2814 return 0;
2815}
2816
2817static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
2818{
2819 struct sh_eth_private *mdp = netdev_priv(ndev);
2820 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2821 int i, ret;
2822
2823 if (!mdp->cd->tsu)
2824 return 0;
2825
2826 i = sh_eth_tsu_find_entry(ndev, addr);
2827 if (i < 0) {
2828 /* No entry found, create one */
2829 i = sh_eth_tsu_find_empty(ndev);
2830 if (i < 0)
2831 return -ENOMEM;
2832 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
2833 if (ret < 0)
2834 return ret;
2835
2836 /* Enable the entry */
2837 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
2838 (1 << (31 - i)), TSU_TEN);
2839 }
2840
2841 /* Entry found or created, enable POST */
2842 sh_eth_tsu_enable_cam_entry_post(ndev, i);
2843
2844 return 0;
2845}
2846
2847static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
2848{
2849 struct sh_eth_private *mdp = netdev_priv(ndev);
2850 int i, ret;
2851
2852 if (!mdp->cd->tsu)
2853 return 0;
2854
2855 i = sh_eth_tsu_find_entry(ndev, addr);
2856 if (i) {
2857 /* Entry found */
2858 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2859 goto done;
2860
2861 /* Disable the entry if both ports was disabled */
2862 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2863 if (ret < 0)
2864 return ret;
2865 }
2866done:
2867 return 0;
2868}
2869
2870static int sh_eth_tsu_purge_all(struct net_device *ndev)
2871{
2872 struct sh_eth_private *mdp = netdev_priv(ndev);
2873 int i, ret;
2874
b37feed7 2875 if (!mdp->cd->tsu)
6743fe6d
YS		 2876 return 0;
2877
2878 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
2879 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2880 continue;
2881
2882 /* Disable the entry if both ports was disabled */
2883 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2884 if (ret < 0)
2885 return ret;
2886 }
2887
2888 return 0;
2889}
2890
2891static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
2892{
2893 struct sh_eth_private *mdp = netdev_priv(ndev);
2894 u8 addr[ETH_ALEN];
2895 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2896 int i;
2897
b37feed7 2898 if (!mdp->cd->tsu)
6743fe6d
YS		 2899 return;
2900
2901 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2902 sh_eth_tsu_read_entry(reg_offset, addr);
2903 if (is_multicast_ether_addr(addr))
2904 sh_eth_tsu_del_entry(ndev, addr);
2905 }
2906}
2907
b37feed7
BH		 2908/* Update promiscuous flag and multicast filter */
2909static void sh_eth_set_rx_mode(struct net_device *ndev)
86a74ff2 2910{
6743fe6d
YS		 2911 struct sh_eth_private *mdp = netdev_priv(ndev);
2912 u32 ecmr_bits;
2913 int mcast_all = 0;
2914 unsigned long flags;
2915
2916 spin_lock_irqsave(&mdp->lock, flags);
128296fc 2917 /* Initial condition is MCT = 1, PRM = 0.
6743fe6d
YS		 2918 * Depending on ndev->flags, set PRM or clear MCT
2919 */
b37feed7
BH		 2920 ecmr_bits = sh_eth_read(ndev, ECMR) & ~ECMR_PRM;
2921 if (mdp->cd->tsu)
2922 ecmr_bits |= ECMR_MCT;
6743fe6d
YS		 2923
2924 if (!(ndev->flags & IFF_MULTICAST)) {
2925 sh_eth_tsu_purge_mcast(ndev);
2926 mcast_all = 1;
2927 }
2928 if (ndev->flags & IFF_ALLMULTI) {
2929 sh_eth_tsu_purge_mcast(ndev);
2930 ecmr_bits &= ~ECMR_MCT;
2931 mcast_all = 1;
2932 }
2933
86a74ff2 2934 if (ndev->flags & IFF_PROMISC) {
6743fe6d
YS		 2935 sh_eth_tsu_purge_all(ndev);
2936 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2937 } else if (mdp->cd->tsu) {
2938 struct netdev_hw_addr *ha;
2939 netdev_for_each_mc_addr(ha, ndev) {
2940 if (mcast_all && is_multicast_ether_addr(ha->addr))
2941 continue;
2942
2943 if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2944 if (!mcast_all) {
2945 sh_eth_tsu_purge_mcast(ndev);
2946 ecmr_bits &= ~ECMR_MCT;
2947 mcast_all = 1;
2948 }
2949 }
2950 }
86a74ff2 2951 }
6743fe6d
YS		 2952
2953 /* update the ethernet mode */
2954 sh_eth_write(ndev, ecmr_bits, ECMR);
2955
2956 spin_unlock_irqrestore(&mdp->lock, flags);
86a74ff2 2957}
71cc7c37
YS		 2958
2959static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2960{
2961 if (!mdp->port)
2962 return TSU_VTAG0;
2963 else
2964 return TSU_VTAG1;
2965}
2966
80d5c368
PM		 2967static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
2968 __be16 proto, u16 vid)
71cc7c37
YS		 2969{
2970 struct sh_eth_private *mdp = netdev_priv(ndev);
2971 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2972
2973 if (unlikely(!mdp->cd->tsu))
2974 return -EPERM;
2975
2976 /* No filtering if vid = 0 */
2977 if (!vid)
2978 return 0;
2979
2980 mdp->vlan_num_ids++;
2981
128296fc 2982 /* The controller has one VLAN tag HW filter. So, if the filter is
71cc7c37
YS		 2983 * already enabled, the driver disables it and the filte
2984 */
2985 if (mdp->vlan_num_ids > 1) {
2986 /* disable VLAN filter */
2987 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2988 return 0;
2989 }
2990
2991 sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
2992 vtag_reg_index);
2993
2994 return 0;
2995}
2996
80d5c368
PM		 2997static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
2998 __be16 proto, u16 vid)
71cc7c37
YS		 2999{
3000 struct sh_eth_private *mdp = netdev_priv(ndev);
3001 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
3002
3003 if (unlikely(!mdp->cd->tsu))
3004 return -EPERM;
3005
3006 /* No filtering if vid = 0 */
3007 if (!vid)
3008 return 0;
3009
3010 mdp->vlan_num_ids--;
3011 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
3012
3013 return 0;
3014}
86a74ff2
NI		 3015
3016/* SuperH's TSU register init function */
4a55530f 3017static void sh_eth_tsu_init(struct sh_eth_private *mdp)
86a74ff2 3018{
a94cf2a6 3019 if (!mdp->cd->dual_port) {
db893473 3020 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
e1487888
CB		 3021 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL,
3022 TSU_FWSLC); /* Enable POST registers */
db893473
SH		 3023 return;
3024 }
3025
4a55530f
YS		 3026 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */
3027 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */
3028 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */
3029 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
3030 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
3031 sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
3032 sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
3033 sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
3034 sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
3035 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
4869a147
SS		 3036 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */
3037 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */
4a55530f
YS		 3038 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */
3039 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */
3040 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
3041 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */
3042 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */
3043 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */
3044 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */
86a74ff2
NI		 3045}
3046
3047/* MDIO bus release function */
bd920ff5 3048static int sh_mdio_release(struct sh_eth_private *mdp)
86a74ff2 3049{
86a74ff2 3050 /* unregister mdio bus */
bd920ff5 3051 mdiobus_unregister(mdp->mii_bus);
86a74ff2
NI		 3052
3053 /* free bitbang info */
bd920ff5 3054 free_mdio_bitbang(mdp->mii_bus);
86a74ff2
NI		 3055
3056 return 0;
3057}
3058
3059/* MDIO bus init function */
bd920ff5 3060static int sh_mdio_init(struct sh_eth_private *mdp,
b3017e6a 3061 struct sh_eth_plat_data *pd)
86a74ff2 3062{
e7f4dc35 3063 int ret;
86a74ff2 3064 struct bb_info *bitbang;
bd920ff5 3065 struct platform_device *pdev = mdp->pdev;
aa8d4225 3066 struct device *dev = &mdp->pdev->dev;
86a74ff2
NI		 3067
3068 /* create bit control struct for PHY */
aa8d4225 3069 bitbang = devm_kzalloc(dev, sizeof(struct bb_info), GFP_KERNEL);
f738a13d
LP		 3070 if (!bitbang)
3071 return -ENOMEM;
86a74ff2
NI		 3072
3073 /* bitbang init */
ae70644d 3074 bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
b3017e6a 3075 bitbang->set_gate = pd->set_mdio_gate;
86a74ff2
NI		 3076 bitbang->ctrl.ops = &bb_ops;
3077
c2e07b3a 3078 /* MII controller setting */
86a74ff2 3079 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
f738a13d
LP		 3080 if (!mdp->mii_bus)
3081 return -ENOMEM;
86a74ff2
NI		 3082
3083 /* Hook up MII support for ethtool */
3084 mdp->mii_bus->name = "sh_mii";
a5bd6060 3085 mdp->mii_bus->parent = dev;
5278fb54 3086 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
bd920ff5 3087 pdev->name, pdev->id);
86a74ff2 3088
bd920ff5 3089 /* register MDIO bus */
00e798c7
FF		 3090 if (pd->phy_irq > 0)
3091 mdp->mii_bus->irq[pd->phy] = pd->phy_irq;
702eca02 3092
00e798c7 3093 ret = of_mdiobus_register(mdp->mii_bus, dev->of_node);
86a74ff2 3094 if (ret)
d5e07e69 3095 goto out_free_bus;
86a74ff2 3096
86a74ff2
NI		 3097 return 0;
3098
86a74ff2 3099out_free_bus:
298cf9be 3100 free_mdio_bitbang(mdp->mii_bus);
86a74ff2
NI		 3101 return ret;
3102}
3103
4a55530f
YS		 3104static const u16 *sh_eth_get_register_offset(int register_type)
3105{
3106 const u16 *reg_offset = NULL;
3107
3108 switch (register_type) {
3109 case SH_ETH_REG_GIGABIT:
3110 reg_offset = sh_eth_offset_gigabit;
3111 break;
db893473
SH		 3112 case SH_ETH_REG_FAST_RZ:
3113 reg_offset = sh_eth_offset_fast_rz;
3114 break;
a3f109bd
SS		 3115 case SH_ETH_REG_FAST_RCAR:
3116 reg_offset = sh_eth_offset_fast_rcar;
3117 break;
4a55530f
YS		 3118 case SH_ETH_REG_FAST_SH4:
3119 reg_offset = sh_eth_offset_fast_sh4;
3120 break;
3121 case SH_ETH_REG_FAST_SH3_SH2:
3122 reg_offset = sh_eth_offset_fast_sh3_sh2;
3123 break;
4a55530f
YS		 3124 }
3125
3126 return reg_offset;
3127}
3128
8f728d79 3129static const struct net_device_ops sh_eth_netdev_ops = {
ebf84eaa
AB		 3130 .ndo_open = sh_eth_open,
3131 .ndo_stop = sh_eth_close,
3132 .ndo_start_xmit = sh_eth_start_xmit,
3133 .ndo_get_stats = sh_eth_get_stats,
b37feed7 3134 .ndo_set_rx_mode = sh_eth_set_rx_mode,
ebf84eaa
AB		 3135 .ndo_tx_timeout = sh_eth_tx_timeout,
3136 .ndo_do_ioctl = sh_eth_do_ioctl,
78d61022 3137 .ndo_change_mtu = sh_eth_change_mtu,
ebf84eaa
AB		 3138 .ndo_validate_addr = eth_validate_addr,
3139 .ndo_set_mac_address = eth_mac_addr,
ebf84eaa
AB		 3140};
3141
8f728d79
SS		 3142static const struct net_device_ops sh_eth_netdev_ops_tsu = {
3143 .ndo_open = sh_eth_open,
3144 .ndo_stop = sh_eth_close,
3145 .ndo_start_xmit = sh_eth_start_xmit,
3146 .ndo_get_stats = sh_eth_get_stats,
b37feed7 3147 .ndo_set_rx_mode = sh_eth_set_rx_mode,
8f728d79
SS		 3148 .ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid,
3149 .ndo_vlan_rx_kill_vid = sh_eth_vlan_rx_kill_vid,
3150 .ndo_tx_timeout = sh_eth_tx_timeout,
3151 .ndo_do_ioctl = sh_eth_do_ioctl,
78d61022 3152 .ndo_change_mtu = sh_eth_change_mtu,
8f728d79
SS		 3153 .ndo_validate_addr = eth_validate_addr,
3154 .ndo_set_mac_address = eth_mac_addr,
8f728d79
SS		 3155};
3156
b356e978
SS		 3157#ifdef CONFIG_OF
3158static struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
3159{
3160 struct device_node *np = dev->of_node;
3161 struct sh_eth_plat_data *pdata;
b356e978
SS		 3162 const char *mac_addr;
3163
3164 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
3165 if (!pdata)
3166 return NULL;
3167
3168 pdata->phy_interface = of_get_phy_mode(np);
3169
b356e978
SS		 3170 mac_addr = of_get_mac_address(np);
3171 if (mac_addr)
3172 memcpy(pdata->mac_addr, mac_addr, ETH_ALEN);
3173
3174 pdata->no_ether_link =
3175 of_property_read_bool(np, "renesas,no-ether-link");
3176 pdata->ether_link_active_low =
3177 of_property_read_bool(np, "renesas,ether-link-active-low");
3178
3179 return pdata;
3180}
3181
3182static const struct of_device_id sh_eth_match_table[] = {
3183 { .compatible = "renesas,gether-r8a7740", .data = &r8a7740_data },
6c4b2f7e
SH		 3184 { .compatible = "renesas,ether-r8a7743", .data = &rcar_gen2_data },
3185 { .compatible = "renesas,ether-r8a7745", .data = &rcar_gen2_data },
3186 { .compatible = "renesas,ether-r8a7778", .data = &rcar_gen1_data },
3187 { .compatible = "renesas,ether-r8a7779", .data = &rcar_gen1_data },
3188 { .compatible = "renesas,ether-r8a7790", .data = &rcar_gen2_data },
3189 { .compatible = "renesas,ether-r8a7791", .data = &rcar_gen2_data },
3190 { .compatible = "renesas,ether-r8a7793", .data = &rcar_gen2_data },
3191 { .compatible = "renesas,ether-r8a7794", .data = &rcar_gen2_data },
3eb9c2ad 3192 { .compatible = "renesas,gether-r8a77980", .data = &r8a77980_data },
b356e978 3193 { .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data },
b4804e0c
SH		 3194 { .compatible = "renesas,rcar-gen1-ether", .data = &rcar_gen1_data },
3195 { .compatible = "renesas,rcar-gen2-ether", .data = &rcar_gen2_data },
b356e978
SS		 3196 { }
3197};
3198MODULE_DEVICE_TABLE(of, sh_eth_match_table);
3199#else
3200static inline struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
3201{
3202 return NULL;
3203}
3204#endif
3205
86a74ff2
NI		 3206static int sh_eth_drv_probe(struct platform_device *pdev)
3207{
86a74ff2 3208 struct resource *res;
0b76b862 3209 struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev);
afe391ad 3210 const struct platform_device_id *id = platform_get_device_id(pdev);
4fa8c3cc
SS		 3211 struct sh_eth_private *mdp;
3212 struct net_device *ndev;
9662ec19 3213 int ret;
86a74ff2
NI		 3214
3215 /* get base addr */
3216 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
86a74ff2
NI		 3217
3218 ndev = alloc_etherdev(sizeof(struct sh_eth_private));
f738a13d
LP		 3219 if (!ndev)
3220 return -ENOMEM;
86a74ff2 3221
b5893a08
BD		 3222 pm_runtime_enable(&pdev->dev);
3223 pm_runtime_get_sync(&pdev->dev);
3224
cc3c080d 3225 ret = platform_get_irq(pdev, 0);
7a468ac6 3226 if (ret < 0)
86a74ff2 3227 goto out_release;
cc3c080d 3228 ndev->irq = ret;
86a74ff2
NI		 3229
3230 SET_NETDEV_DEV(ndev, &pdev->dev);
3231
86a74ff2 3232 mdp = netdev_priv(ndev);
525b8075
YS		 3233 mdp->num_tx_ring = TX_RING_SIZE;
3234 mdp->num_rx_ring = RX_RING_SIZE;
d5e07e69
SS		 3235 mdp->addr = devm_ioremap_resource(&pdev->dev, res);
3236 if (IS_ERR(mdp->addr)) {
3237 ret = PTR_ERR(mdp->addr);
ae70644d
YS		 3238 goto out_release;
3239 }
3240
c960804f
VB		 3241 ndev->base_addr = res->start;
3242
86a74ff2 3243 spin_lock_init(&mdp->lock);
bcd5149d 3244 mdp->pdev = pdev;
86a74ff2 3245
b356e978
SS		 3246 if (pdev->dev.of_node)
3247 pd = sh_eth_parse_dt(&pdev->dev);
3b4c5cbf
SS		 3248 if (!pd) {
3249 dev_err(&pdev->dev, "no platform data\n");
3250 ret = -EINVAL;
3251 goto out_release;
3252 }
3253
86a74ff2 3254 /* get PHY ID */
71557a37 3255 mdp->phy_id = pd->phy;
e47c9052 3256 mdp->phy_interface = pd->phy_interface;
4923576b
YS		 3257 mdp->no_ether_link = pd->no_ether_link;
3258 mdp->ether_link_active_low = pd->ether_link_active_low;
86a74ff2 3259
380af9e3 3260 /* set cpu data */
42a67c9b 3261 if (id)
b356e978 3262 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data;
42a67c9b
WS		 3263 else
3264 mdp->cd = (struct sh_eth_cpu_data *)of_device_get_match_data(&pdev->dev);
b356e978 3265
a3153d8c 3266 mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type);
264be2f5
SS		 3267 if (!mdp->reg_offset) {
3268 dev_err(&pdev->dev, "Unknown register type (%d)\n",
3269 mdp->cd->register_type);
3270 ret = -EINVAL;
3271 goto out_release;
3272 }
380af9e3
YS		 3273 sh_eth_set_default_cpu_data(mdp->cd);
3274
78d61022
NS		 3275 /* User's manual states max MTU should be 2048 but due to the
3276 * alignment calculations in sh_eth_ring_init() the practical
3277 * MTU is a bit less. Maybe this can be optimized some more.
3278 */
3279 ndev->max_mtu = 2000 - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN);
3280 ndev->min_mtu = ETH_MIN_MTU;
3281
86a74ff2 3282 /* set function */
8f728d79
SS		 3283 if (mdp->cd->tsu)
3284 ndev->netdev_ops = &sh_eth_netdev_ops_tsu;
3285 else
3286 ndev->netdev_ops = &sh_eth_netdev_ops;
7ad24ea4 3287 ndev->ethtool_ops = &sh_eth_ethtool_ops;
86a74ff2
NI		 3288 ndev->watchdog_timeo = TX_TIMEOUT;
3289
dc19e4e5
NI		 3290 /* debug message level */
3291 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
86a74ff2
NI		 3292
3293 /* read and set MAC address */
748031f9 3294 read_mac_address(ndev, pd->mac_addr);
ff6e7228
SS		 3295 if (!is_valid_ether_addr(ndev->dev_addr)) {
3296 dev_warn(&pdev->dev,
3297 "no valid MAC address supplied, using a random one.\n");
3298 eth_hw_addr_random(ndev);
3299 }
86a74ff2 3300
6ba88021 3301 if (mdp->cd->tsu) {
9662ec19 3302 int port = pdev->id < 0 ? 0 : pdev->id % 2;
6ba88021 3303 struct resource *rtsu;
dfe8266b 3304
6ba88021 3305 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
dfe8266b
SS		 3306 if (!rtsu) {
3307 dev_err(&pdev->dev, "no TSU resource\n");
3308 ret = -ENODEV;
3309 goto out_release;
3310 }
3311 /* We can only request the TSU region for the first port
3312 * of the two sharing this TSU for the probe to succeed...
3313 */
9662ec19 3314 if (port == 0 &&
dfe8266b
SS		 3315 !devm_request_mem_region(&pdev->dev, rtsu->start,
3316 resource_size(rtsu),
3317 dev_name(&pdev->dev))) {
3318 dev_err(&pdev->dev, "can't request TSU resource.\n");
3319 ret = -EBUSY;
3320 goto out_release;
3321 }
3e14c969 3322 /* ioremap the TSU registers */
dfe8266b
SS		 3323 mdp->tsu_addr = devm_ioremap(&pdev->dev, rtsu->start,
3324 resource_size(rtsu));
3325 if (!mdp->tsu_addr) {
3326 dev_err(&pdev->dev, "TSU region ioremap() failed.\n");
3327 ret = -ENOMEM;
fc0c0900
SS		 3328 goto out_release;
3329 }
9662ec19 3330 mdp->port = port;
f646968f 3331 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER;
6ba88021 3332
3e14c969 3333 /* Need to init only the first port of the two sharing a TSU */
9662ec19 3334 if (port == 0) {
3e14c969
SS		 3335 if (mdp->cd->chip_reset)
3336 mdp->cd->chip_reset(ndev);
86a74ff2 3337
4986b996
YS		 3338 /* TSU init (Init only)*/
3339 sh_eth_tsu_init(mdp);
3340 }
86a74ff2
NI		 3341 }
3342
966d6dbb
HN		 3343 if (mdp->cd->rmiimode)
3344 sh_eth_write(ndev, 0x1, RMIIMODE);
3345
daacf03f
LP		 3346 /* MDIO bus init */
3347 ret = sh_mdio_init(mdp, pd);
3348 if (ret) {
b7ce520e
GU		 3349 if (ret != -EPROBE_DEFER)
3350 dev_err(&pdev->dev, "MDIO init failed: %d\n", ret);
daacf03f
LP		 3351 goto out_release;
3352 }
3353
3719109d
SS		 3354 netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64);
3355
86a74ff2
NI		 3356 /* network device register */
3357 ret = register_netdev(ndev);
3358 if (ret)
3719109d 3359 goto out_napi_del;
86a74ff2 3360
b4580c95 3361 if (mdp->cd->magic)
d8981d02
NS		 3362 device_set_wakeup_capable(&pdev->dev, 1);
3363
25985edc 3364 /* print device information */
f75f14ec
SS		 3365 netdev_info(ndev, "Base address at 0x%x, %pM, IRQ %d.\n",
3366 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
86a74ff2 3367
b5893a08 3368 pm_runtime_put(&pdev->dev);
86a74ff2
NI		 3369 platform_set_drvdata(pdev, ndev);
3370
3371 return ret;
3372
3719109d
SS		 3373out_napi_del:
3374 netif_napi_del(&mdp->napi);
daacf03f 3375 sh_mdio_release(mdp);
3719109d 3376
86a74ff2
NI		 3377out_release:
3378 /* net_dev free */
4282fc47 3379 free_netdev(ndev);
86a74ff2 3380
b5893a08
BD		 3381 pm_runtime_put(&pdev->dev);
3382 pm_runtime_disable(&pdev->dev);
86a74ff2
NI		 3383 return ret;
3384}
3385
3386static int sh_eth_drv_remove(struct platform_device *pdev)
3387{
3388 struct net_device *ndev = platform_get_drvdata(pdev);
3719109d 3389 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2 3390
86a74ff2 3391 unregister_netdev(ndev);
3719109d 3392 netif_napi_del(&mdp->napi);
daacf03f 3393 sh_mdio_release(mdp);
bcd5149d 3394 pm_runtime_disable(&pdev->dev);
86a74ff2 3395 free_netdev(ndev);
86a74ff2
NI		 3396
3397 return 0;
3398}
3399
540ad1b8 3400#ifdef CONFIG_PM
b71af046 3401#ifdef CONFIG_PM_SLEEP
d8981d02
NS		 3402static int sh_eth_wol_setup(struct net_device *ndev)
3403{
3404 struct sh_eth_private *mdp = netdev_priv(ndev);
3405
3406 /* Only allow ECI interrupts */
3407 synchronize_irq(ndev->irq);
3408 napi_disable(&mdp->napi);
1a0bee6c 3409 sh_eth_write(ndev, EESIPR_ECIIP, EESIPR);
d8981d02
NS		 3410
3411 /* Enable MagicPacket */
5e2ed132 3412 sh_eth_modify(ndev, ECMR, ECMR_MPDE, ECMR_MPDE);
d8981d02 3413
d8981d02
NS		 3414 return enable_irq_wake(ndev->irq);
3415}
3416
3417static int sh_eth_wol_restore(struct net_device *ndev)
3418{
3419 struct sh_eth_private *mdp = netdev_priv(ndev);
3420 int ret;
3421
3422 napi_enable(&mdp->napi);
3423
3424 /* Disable MagicPacket */
3425 sh_eth_modify(ndev, ECMR, ECMR_MPDE, 0);
3426
3427 /* The device needs to be reset to restore MagicPacket logic
3428 * for next wakeup. If we close and open the device it will
3429 * both be reset and all registers restored. This is what
3430 * happens during suspend and resume without WoL enabled.
3431 */
3432 ret = sh_eth_close(ndev);
3433 if (ret < 0)
3434 return ret;
3435 ret = sh_eth_open(ndev);
3436 if (ret < 0)
3437 return ret;
3438
d8981d02
NS		 3439 return disable_irq_wake(ndev->irq);
3440}
3441
b71af046
MU		 3442static int sh_eth_suspend(struct device *dev)
3443{
3444 struct net_device *ndev = dev_get_drvdata(dev);
d8981d02 3445 struct sh_eth_private *mdp = netdev_priv(ndev);
b71af046
MU		 3446 int ret = 0;
3447
d8981d02
NS		 3448 if (!netif_running(ndev))
3449 return 0;
3450
3451 netif_device_detach(ndev);
3452
3453 if (mdp->wol_enabled)
3454 ret = sh_eth_wol_setup(ndev);
3455 else
b71af046 3456 ret = sh_eth_close(ndev);
b71af046
MU		 3457
3458 return ret;
3459}
3460
3461static int sh_eth_resume(struct device *dev)
3462{
3463 struct net_device *ndev = dev_get_drvdata(dev);
d8981d02 3464 struct sh_eth_private *mdp = netdev_priv(ndev);
b71af046
MU		 3465 int ret = 0;
3466
d8981d02
NS		 3467 if (!netif_running(ndev))
3468 return 0;
3469
3470 if (mdp->wol_enabled)
3471 ret = sh_eth_wol_restore(ndev);
3472 else
b71af046 3473 ret = sh_eth_open(ndev);
d8981d02
NS		 3474
3475 if (ret < 0)
3476 return ret;
3477
3478 netif_device_attach(ndev);
b71af046
MU		 3479
3480 return ret;
3481}
3482#endif
3483
bcd5149d
MD		 3484static int sh_eth_runtime_nop(struct device *dev)
3485{
128296fc 3486 /* Runtime PM callback shared between ->runtime_suspend()
bcd5149d
MD		 3487 * and ->runtime_resume(). Simply returns success.
3488 *
3489 * This driver re-initializes all registers after
3490 * pm_runtime_get_sync() anyway so there is no need
3491 * to save and restore registers here.
3492 */
3493 return 0;
3494}
3495
540ad1b8 3496static const struct dev_pm_ops sh_eth_dev_pm_ops = {
b71af046 3497 SET_SYSTEM_SLEEP_PM_OPS(sh_eth_suspend, sh_eth_resume)
e7d7e898 3498 SET_RUNTIME_PM_OPS(sh_eth_runtime_nop, sh_eth_runtime_nop, NULL)
bcd5149d 3499};
540ad1b8
NI		 3500#define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
3501#else
3502#define SH_ETH_PM_OPS NULL
3503#endif
bcd5149d 3504
ef00df85 3505static const struct platform_device_id sh_eth_id_table[] = {
c18a79ab 3506 { "sh7619-ether", (kernel_ulong_t)&sh7619_data },
7bbe150d 3507 { "sh771x-ether", (kernel_ulong_t)&sh771x_data },
9c3beaab 3508 { "sh7724-ether", (kernel_ulong_t)&sh7724_data },
f5d12767 3509 { "sh7734-gether", (kernel_ulong_t)&sh7734_data },
24549e2a
SS		 3510 { "sh7757-ether", (kernel_ulong_t)&sh7757_data },
3511 { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga },
f5d12767 3512 { "sh7763-gether", (kernel_ulong_t)&sh7763_data },
afe391ad
SS		 3513 { }
3514};
3515MODULE_DEVICE_TABLE(platform, sh_eth_id_table);
3516
86a74ff2
NI		 3517static struct platform_driver sh_eth_driver = {
3518 .probe = sh_eth_drv_probe,
3519 .remove = sh_eth_drv_remove,
afe391ad 3520 .id_table = sh_eth_id_table,
86a74ff2
NI		 3521 .driver = {
3522 .name = CARDNAME,
540ad1b8 3523 .pm = SH_ETH_PM_OPS,
b356e978 3524 .of_match_table = of_match_ptr(sh_eth_match_table),
86a74ff2
NI		 3525 },
3526};
3527
db62f684 3528module_platform_driver(sh_eth_driver);
86a74ff2
NI		 3529
3530MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
3531MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
3532MODULE_LICENSE("GPL v2");
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