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Merge branch 'for-rc' of git://git.kernel.org/pub/scm/linux/kernel/git/rzhang/linux
[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / renesas / sh_eth.c
CommitLineData
128296fc 1/* SuperH Ethernet device driver
86a74ff2 2 *
966d6dbb 3 * Copyright (C) 2014 Renesas Electronics Corporation
f0e81fec 4 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu
b356e978 5 * Copyright (C) 2008-2014 Renesas Solutions Corp.
b2b14d2f 6 * Copyright (C) 2013-2016 Cogent Embedded, Inc.
702eca02 7 * Copyright (C) 2014 Codethink Limited
86a74ff2
NI		 8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms and conditions of the GNU General Public License,
11 * version 2, as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
86a74ff2
NI		 17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 */
21
0654011d
YS		 22#include <linux/module.h>
23#include <linux/kernel.h>
24#include <linux/spinlock.h>
6a27cded 25#include <linux/interrupt.h>
86a74ff2
NI		 26#include <linux/dma-mapping.h>
27#include <linux/etherdevice.h>
28#include <linux/delay.h>
29#include <linux/platform_device.h>
30#include <linux/mdio-bitbang.h>
31#include <linux/netdevice.h>
b356e978
SS		 32#include <linux/of.h>
33#include <linux/of_device.h>
34#include <linux/of_irq.h>
35#include <linux/of_net.h>
86a74ff2
NI		 36#include <linux/phy.h>
37#include <linux/cache.h>
38#include <linux/io.h>
bcd5149d 39#include <linux/pm_runtime.h>
5a0e3ad6 40#include <linux/slab.h>
dc19e4e5 41#include <linux/ethtool.h>
fdb37a7f 42#include <linux/if_vlan.h>
f0e81fec 43#include <linux/clk.h>
d4fa0e35 44#include <linux/sh_eth.h>
702eca02 45#include <linux/of_mdio.h>
86a74ff2
NI		 46
47#include "sh_eth.h"
48
dc19e4e5
NI		 49#define SH_ETH_DEF_MSG_ENABLE \
50 (NETIF_MSG_LINK | \
51 NETIF_MSG_TIMER | \
52 NETIF_MSG_RX_ERR| \
53 NETIF_MSG_TX_ERR)
54
2274d375
SS		 55#define SH_ETH_OFFSET_INVALID ((u16)~0)
56
3365711d
BH		 57#define SH_ETH_OFFSET_DEFAULTS \
58 [0 ... SH_ETH_MAX_REGISTER_OFFSET - 1] = SH_ETH_OFFSET_INVALID
59
c0013f6f 60static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
3365711d
BH		 61 SH_ETH_OFFSET_DEFAULTS,
62
c0013f6f
SS		 63 [EDSR] = 0x0000,
64 [EDMR] = 0x0400,
65 [EDTRR] = 0x0408,
66 [EDRRR] = 0x0410,
67 [EESR] = 0x0428,
68 [EESIPR] = 0x0430,
69 [TDLAR] = 0x0010,
70 [TDFAR] = 0x0014,
71 [TDFXR] = 0x0018,
72 [TDFFR] = 0x001c,
73 [RDLAR] = 0x0030,
74 [RDFAR] = 0x0034,
75 [RDFXR] = 0x0038,
76 [RDFFR] = 0x003c,
77 [TRSCER] = 0x0438,
78 [RMFCR] = 0x0440,
79 [TFTR] = 0x0448,
80 [FDR] = 0x0450,
81 [RMCR] = 0x0458,
82 [RPADIR] = 0x0460,
83 [FCFTR] = 0x0468,
84 [CSMR] = 0x04E4,
85
86 [ECMR] = 0x0500,
87 [ECSR] = 0x0510,
88 [ECSIPR] = 0x0518,
89 [PIR] = 0x0520,
90 [PSR] = 0x0528,
91 [PIPR] = 0x052c,
92 [RFLR] = 0x0508,
93 [APR] = 0x0554,
94 [MPR] = 0x0558,
95 [PFTCR] = 0x055c,
96 [PFRCR] = 0x0560,
97 [TPAUSER] = 0x0564,
98 [GECMR] = 0x05b0,
99 [BCULR] = 0x05b4,
100 [MAHR] = 0x05c0,
101 [MALR] = 0x05c8,
102 [TROCR] = 0x0700,
103 [CDCR] = 0x0708,
104 [LCCR] = 0x0710,
105 [CEFCR] = 0x0740,
106 [FRECR] = 0x0748,
107 [TSFRCR] = 0x0750,
108 [TLFRCR] = 0x0758,
109 [RFCR] = 0x0760,
110 [CERCR] = 0x0768,
111 [CEECR] = 0x0770,
112 [MAFCR] = 0x0778,
113 [RMII_MII] = 0x0790,
114
115 [ARSTR] = 0x0000,
116 [TSU_CTRST] = 0x0004,
117 [TSU_FWEN0] = 0x0010,
118 [TSU_FWEN1] = 0x0014,
119 [TSU_FCM] = 0x0018,
120 [TSU_BSYSL0] = 0x0020,
121 [TSU_BSYSL1] = 0x0024,
122 [TSU_PRISL0] = 0x0028,
123 [TSU_PRISL1] = 0x002c,
124 [TSU_FWSL0] = 0x0030,
125 [TSU_FWSL1] = 0x0034,
126 [TSU_FWSLC] = 0x0038,
127 [TSU_QTAG0] = 0x0040,
128 [TSU_QTAG1] = 0x0044,
129 [TSU_FWSR] = 0x0050,
130 [TSU_FWINMK] = 0x0054,
131 [TSU_ADQT0] = 0x0048,
132 [TSU_ADQT1] = 0x004c,
133 [TSU_VTAG0] = 0x0058,
134 [TSU_VTAG1] = 0x005c,
135 [TSU_ADSBSY] = 0x0060,
136 [TSU_TEN] = 0x0064,
137 [TSU_POST1] = 0x0070,
138 [TSU_POST2] = 0x0074,
139 [TSU_POST3] = 0x0078,
140 [TSU_POST4] = 0x007c,
141 [TSU_ADRH0] = 0x0100,
c0013f6f
SS		 142
143 [TXNLCR0] = 0x0080,
144 [TXALCR0] = 0x0084,
145 [RXNLCR0] = 0x0088,
146 [RXALCR0] = 0x008c,
147 [FWNLCR0] = 0x0090,
148 [FWALCR0] = 0x0094,
149 [TXNLCR1] = 0x00a0,
150 [TXALCR1] = 0x00a0,
151 [RXNLCR1] = 0x00a8,
152 [RXALCR1] = 0x00ac,
153 [FWNLCR1] = 0x00b0,
154 [FWALCR1] = 0x00b4,
155};
156
db893473 157static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
3365711d
BH		 158 SH_ETH_OFFSET_DEFAULTS,
159
db893473
SH		 160 [EDSR] = 0x0000,
161 [EDMR] = 0x0400,
162 [EDTRR] = 0x0408,
163 [EDRRR] = 0x0410,
164 [EESR] = 0x0428,
165 [EESIPR] = 0x0430,
166 [TDLAR] = 0x0010,
167 [TDFAR] = 0x0014,
168 [TDFXR] = 0x0018,
169 [TDFFR] = 0x001c,
170 [RDLAR] = 0x0030,
171 [RDFAR] = 0x0034,
172 [RDFXR] = 0x0038,
173 [RDFFR] = 0x003c,
174 [TRSCER] = 0x0438,
175 [RMFCR] = 0x0440,
176 [TFTR] = 0x0448,
177 [FDR] = 0x0450,
178 [RMCR] = 0x0458,
179 [RPADIR] = 0x0460,
180 [FCFTR] = 0x0468,
181 [CSMR] = 0x04E4,
182
183 [ECMR] = 0x0500,
184 [RFLR] = 0x0508,
185 [ECSR] = 0x0510,
186 [ECSIPR] = 0x0518,
187 [PIR] = 0x0520,
188 [APR] = 0x0554,
189 [MPR] = 0x0558,
190 [PFTCR] = 0x055c,
191 [PFRCR] = 0x0560,
192 [TPAUSER] = 0x0564,
193 [MAHR] = 0x05c0,
194 [MALR] = 0x05c8,
195 [CEFCR] = 0x0740,
196 [FRECR] = 0x0748,
197 [TSFRCR] = 0x0750,
198 [TLFRCR] = 0x0758,
199 [RFCR] = 0x0760,
200 [MAFCR] = 0x0778,
201
202 [ARSTR] = 0x0000,
203 [TSU_CTRST] = 0x0004,
e1487888 204 [TSU_FWSLC] = 0x0038,
db893473
SH		 205 [TSU_VTAG0] = 0x0058,
206 [TSU_ADSBSY] = 0x0060,
207 [TSU_TEN] = 0x0064,
e1487888
CB		 208 [TSU_POST1] = 0x0070,
209 [TSU_POST2] = 0x0074,
210 [TSU_POST3] = 0x0078,
211 [TSU_POST4] = 0x007c,
db893473 212 [TSU_ADRH0] = 0x0100,
db893473
SH		 213
214 [TXNLCR0] = 0x0080,
215 [TXALCR0] = 0x0084,
216 [RXNLCR0] = 0x0088,
217 [RXALCR0] = 0x008C,
218};
219
a3f109bd 220static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
3365711d
BH		 221 SH_ETH_OFFSET_DEFAULTS,
222
a3f109bd
SS		 223 [ECMR] = 0x0300,
224 [RFLR] = 0x0308,
225 [ECSR] = 0x0310,
226 [ECSIPR] = 0x0318,
227 [PIR] = 0x0320,
228 [PSR] = 0x0328,
229 [RDMLR] = 0x0340,
230 [IPGR] = 0x0350,
231 [APR] = 0x0354,
232 [MPR] = 0x0358,
233 [RFCF] = 0x0360,
234 [TPAUSER] = 0x0364,
235 [TPAUSECR] = 0x0368,
236 [MAHR] = 0x03c0,
237 [MALR] = 0x03c8,
238 [TROCR] = 0x03d0,
239 [CDCR] = 0x03d4,
240 [LCCR] = 0x03d8,
241 [CNDCR] = 0x03dc,
242 [CEFCR] = 0x03e4,
243 [FRECR] = 0x03e8,
244 [TSFRCR] = 0x03ec,
245 [TLFRCR] = 0x03f0,
246 [RFCR] = 0x03f4,
247 [MAFCR] = 0x03f8,
248
249 [EDMR] = 0x0200,
250 [EDTRR] = 0x0208,
251 [EDRRR] = 0x0210,
252 [TDLAR] = 0x0218,
253 [RDLAR] = 0x0220,
254 [EESR] = 0x0228,
255 [EESIPR] = 0x0230,
256 [TRSCER] = 0x0238,
257 [RMFCR] = 0x0240,
258 [TFTR] = 0x0248,
259 [FDR] = 0x0250,
260 [RMCR] = 0x0258,
261 [TFUCR] = 0x0264,
262 [RFOCR] = 0x0268,
55754f19 263 [RMIIMODE] = 0x026c,
a3f109bd
SS		 264 [FCFTR] = 0x0270,
265 [TRIMD] = 0x027c,
266};
267
c0013f6f 268static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
3365711d
BH		 269 SH_ETH_OFFSET_DEFAULTS,
270
c0013f6f
SS		 271 [ECMR] = 0x0100,
272 [RFLR] = 0x0108,
273 [ECSR] = 0x0110,
274 [ECSIPR] = 0x0118,
275 [PIR] = 0x0120,
276 [PSR] = 0x0128,
277 [RDMLR] = 0x0140,
278 [IPGR] = 0x0150,
279 [APR] = 0x0154,
280 [MPR] = 0x0158,
281 [TPAUSER] = 0x0164,
282 [RFCF] = 0x0160,
283 [TPAUSECR] = 0x0168,
284 [BCFRR] = 0x016c,
285 [MAHR] = 0x01c0,
286 [MALR] = 0x01c8,
287 [TROCR] = 0x01d0,
288 [CDCR] = 0x01d4,
289 [LCCR] = 0x01d8,
290 [CNDCR] = 0x01dc,
291 [CEFCR] = 0x01e4,
292 [FRECR] = 0x01e8,
293 [TSFRCR] = 0x01ec,
294 [TLFRCR] = 0x01f0,
295 [RFCR] = 0x01f4,
296 [MAFCR] = 0x01f8,
297 [RTRATE] = 0x01fc,
298
299 [EDMR] = 0x0000,
300 [EDTRR] = 0x0008,
301 [EDRRR] = 0x0010,
302 [TDLAR] = 0x0018,
303 [RDLAR] = 0x0020,
304 [EESR] = 0x0028,
305 [EESIPR] = 0x0030,
306 [TRSCER] = 0x0038,
307 [RMFCR] = 0x0040,
308 [TFTR] = 0x0048,
309 [FDR] = 0x0050,
310 [RMCR] = 0x0058,
311 [TFUCR] = 0x0064,
312 [RFOCR] = 0x0068,
313 [FCFTR] = 0x0070,
314 [RPADIR] = 0x0078,
315 [TRIMD] = 0x007c,
316 [RBWAR] = 0x00c8,
317 [RDFAR] = 0x00cc,
318 [TBRAR] = 0x00d4,
319 [TDFAR] = 0x00d8,
320};
321
322static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
3365711d
BH		 323 SH_ETH_OFFSET_DEFAULTS,
324
d8b0426a
SS		 325 [EDMR] = 0x0000,
326 [EDTRR] = 0x0004,
327 [EDRRR] = 0x0008,
328 [TDLAR] = 0x000c,
329 [RDLAR] = 0x0010,
330 [EESR] = 0x0014,
331 [EESIPR] = 0x0018,
332 [TRSCER] = 0x001c,
333 [RMFCR] = 0x0020,
334 [TFTR] = 0x0024,
335 [FDR] = 0x0028,
336 [RMCR] = 0x002c,
337 [EDOCR] = 0x0030,
338 [FCFTR] = 0x0034,
339 [RPADIR] = 0x0038,
340 [TRIMD] = 0x003c,
341 [RBWAR] = 0x0040,
342 [RDFAR] = 0x0044,
343 [TBRAR] = 0x004c,
344 [TDFAR] = 0x0050,
345
c0013f6f
SS		 346 [ECMR] = 0x0160,
347 [ECSR] = 0x0164,
348 [ECSIPR] = 0x0168,
349 [PIR] = 0x016c,
350 [MAHR] = 0x0170,
351 [MALR] = 0x0174,
352 [RFLR] = 0x0178,
353 [PSR] = 0x017c,
354 [TROCR] = 0x0180,
355 [CDCR] = 0x0184,
356 [LCCR] = 0x0188,
357 [CNDCR] = 0x018c,
358 [CEFCR] = 0x0194,
359 [FRECR] = 0x0198,
360 [TSFRCR] = 0x019c,
361 [TLFRCR] = 0x01a0,
362 [RFCR] = 0x01a4,
363 [MAFCR] = 0x01a8,
364 [IPGR] = 0x01b4,
365 [APR] = 0x01b8,
366 [MPR] = 0x01bc,
367 [TPAUSER] = 0x01c4,
368 [BCFR] = 0x01cc,
369
370 [ARSTR] = 0x0000,
371 [TSU_CTRST] = 0x0004,
372 [TSU_FWEN0] = 0x0010,
373 [TSU_FWEN1] = 0x0014,
374 [TSU_FCM] = 0x0018,
375 [TSU_BSYSL0] = 0x0020,
376 [TSU_BSYSL1] = 0x0024,
377 [TSU_PRISL0] = 0x0028,
378 [TSU_PRISL1] = 0x002c,
379 [TSU_FWSL0] = 0x0030,
380 [TSU_FWSL1] = 0x0034,
381 [TSU_FWSLC] = 0x0038,
382 [TSU_QTAGM0] = 0x0040,
383 [TSU_QTAGM1] = 0x0044,
384 [TSU_ADQT0] = 0x0048,
385 [TSU_ADQT1] = 0x004c,
386 [TSU_FWSR] = 0x0050,
387 [TSU_FWINMK] = 0x0054,
388 [TSU_ADSBSY] = 0x0060,
389 [TSU_TEN] = 0x0064,
390 [TSU_POST1] = 0x0070,
391 [TSU_POST2] = 0x0074,
392 [TSU_POST3] = 0x0078,
393 [TSU_POST4] = 0x007c,
394
395 [TXNLCR0] = 0x0080,
396 [TXALCR0] = 0x0084,
397 [RXNLCR0] = 0x0088,
398 [RXALCR0] = 0x008c,
399 [FWNLCR0] = 0x0090,
400 [FWALCR0] = 0x0094,
401 [TXNLCR1] = 0x00a0,
402 [TXALCR1] = 0x00a0,
403 [RXNLCR1] = 0x00a8,
404 [RXALCR1] = 0x00ac,
405 [FWNLCR1] = 0x00b0,
406 [FWALCR1] = 0x00b4,
407
408 [TSU_ADRH0] = 0x0100,
c0013f6f
SS		 409};
410
740c7f31
BH		 411static void sh_eth_rcv_snd_disable(struct net_device *ndev);
412static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev);
413
2274d375
SS		 414static void sh_eth_write(struct net_device *ndev, u32 data, int enum_index)
415{
416 struct sh_eth_private *mdp = netdev_priv(ndev);
417 u16 offset = mdp->reg_offset[enum_index];
418
419 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
420 return;
421
422 iowrite32(data, mdp->addr + offset);
423}
424
425static u32 sh_eth_read(struct net_device *ndev, int enum_index)
426{
427 struct sh_eth_private *mdp = netdev_priv(ndev);
428 u16 offset = mdp->reg_offset[enum_index];
429
430 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
431 return ~0U;
432
433 return ioread32(mdp->addr + offset);
434}
435
b2b14d2f
SS		 436static void sh_eth_modify(struct net_device *ndev, int enum_index, u32 clear,
437 u32 set)
438{
439 sh_eth_write(ndev, (sh_eth_read(ndev, enum_index) & ~clear) | set,
440 enum_index);
441}
442
504c8ca5 443static bool sh_eth_is_gether(struct sh_eth_private *mdp)
dabdde9e 444{
504c8ca5 445 return mdp->reg_offset == sh_eth_offset_gigabit;
dabdde9e
NI		 446}
447
db893473
SH		 448static bool sh_eth_is_rz_fast_ether(struct sh_eth_private *mdp)
449{
450 return mdp->reg_offset == sh_eth_offset_fast_rz;
451}
452
8e994402 453static void sh_eth_select_mii(struct net_device *ndev)
5e7a76be 454{
5e7a76be 455 struct sh_eth_private *mdp = netdev_priv(ndev);
4fa8c3cc 456 u32 value;
5e7a76be
NI		 457
458 switch (mdp->phy_interface) {
459 case PHY_INTERFACE_MODE_GMII:
460 value = 0x2;
461 break;
462 case PHY_INTERFACE_MODE_MII:
463 value = 0x1;
464 break;
465 case PHY_INTERFACE_MODE_RMII:
466 value = 0x0;
467 break;
468 default:
f75f14ec
SS		 469 netdev_warn(ndev,
470 "PHY interface mode was not setup. Set to MII.\n");
5e7a76be
NI		 471 value = 0x1;
472 break;
473 }
474
475 sh_eth_write(ndev, value, RMII_MII);
476}
5e7a76be 477
8e994402 478static void sh_eth_set_duplex(struct net_device *ndev)
65ac8851
YS		 479{
480 struct sh_eth_private *mdp = netdev_priv(ndev);
65ac8851 481
b2b14d2f 482 sh_eth_modify(ndev, ECMR, ECMR_DM, mdp->duplex ? ECMR_DM : 0);
65ac8851
YS		 483}
484
99f84be6
GU		 485static void sh_eth_chip_reset(struct net_device *ndev)
486{
487 struct sh_eth_private *mdp = netdev_priv(ndev);
488
489 /* reset device */
ec65cfce 490 sh_eth_tsu_write(mdp, ARSTR_ARST, ARSTR);
99f84be6
GU		 491 mdelay(1);
492}
493
a0f48be3
GU		 494static void sh_eth_set_rate_gether(struct net_device *ndev)
495{
496 struct sh_eth_private *mdp = netdev_priv(ndev);
497
498 switch (mdp->speed) {
499 case 10: /* 10BASE */
500 sh_eth_write(ndev, GECMR_10, GECMR);
501 break;
502 case 100:/* 100BASE */
503 sh_eth_write(ndev, GECMR_100, GECMR);
504 break;
505 case 1000: /* 1000BASE */
506 sh_eth_write(ndev, GECMR_1000, GECMR);
507 break;
a0f48be3
GU		 508 }
509}
510
99f84be6
GU		 511#ifdef CONFIG_OF
512/* R7S72100 */
513static struct sh_eth_cpu_data r7s72100_data = {
514 .chip_reset = sh_eth_chip_reset,
515 .set_duplex = sh_eth_set_duplex,
516
517 .register_type = SH_ETH_REG_FAST_RZ,
518
519 .ecsr_value = ECSR_ICD,
520 .ecsipr_value = ECSIPR_ICDIP,
33d446db 521 .eesipr_value = 0xe77f009f,
99f84be6
GU		 522
523 .tx_check = EESR_TC1 | EESR_FTC,
524 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
525 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
526 EESR_TDE | EESR_ECI,
527 .fdr_value = 0x0000070f,
528
529 .no_psr = 1,
530 .apr = 1,
531 .mpr = 1,
532 .tpauser = 1,
533 .hw_swap = 1,
534 .rpadir = 1,
535 .rpadir_value = 2 << 16,
536 .no_trimd = 1,
537 .no_ade = 1,
538 .hw_crc = 1,
539 .tsu = 1,
540 .shift_rd0 = 1,
541};
a0f48be3
GU		 542
543static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
544{
c66b2581 545 sh_eth_chip_reset(ndev);
a0f48be3
GU		 546
547 sh_eth_select_mii(ndev);
548}
549
550/* R8A7740 */
551static struct sh_eth_cpu_data r8a7740_data = {
552 .chip_reset = sh_eth_chip_reset_r8a7740,
553 .set_duplex = sh_eth_set_duplex,
554 .set_rate = sh_eth_set_rate_gether,
555
556 .register_type = SH_ETH_REG_GIGABIT,
557
558 .ecsr_value = ECSR_ICD | ECSR_MPD,
559 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
560 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
561
562 .tx_check = EESR_TC1 | EESR_FTC,
563 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
564 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
565 EESR_TDE | EESR_ECI,
566 .fdr_value = 0x0000070f,
567
568 .apr = 1,
569 .mpr = 1,
570 .tpauser = 1,
571 .bculr = 1,
572 .hw_swap = 1,
573 .rpadir = 1,
574 .rpadir_value = 2 << 16,
575 .no_trimd = 1,
576 .no_ade = 1,
0f1f9cbc 577 .hw_crc = 1,
a0f48be3
GU		 578 .tsu = 1,
579 .select_mii = 1,
580 .shift_rd0 = 1,
581};
99f84be6 582
04b0ed2a 583/* There is CPU dependent code */
589ebdef 584static void sh_eth_set_rate_r8a777x(struct net_device *ndev)
65ac8851
YS		 585{
586 struct sh_eth_private *mdp = netdev_priv(ndev);
d0418bb7 587
a3f109bd
SS		 588 switch (mdp->speed) {
589 case 10: /* 10BASE */
b2b14d2f 590 sh_eth_modify(ndev, ECMR, ECMR_ELB, 0);
a3f109bd
SS		 591 break;
592 case 100:/* 100BASE */
b2b14d2f 593 sh_eth_modify(ndev, ECMR, ECMR_ELB, ECMR_ELB);
a3f109bd 594 break;
a3f109bd
SS		 595 }
596}
597
674853b2 598/* R8A7778/9 */
589ebdef 599static struct sh_eth_cpu_data r8a777x_data = {
a3f109bd 600 .set_duplex = sh_eth_set_duplex,
589ebdef 601 .set_rate = sh_eth_set_rate_r8a777x,
a3f109bd 602
a3153d8c
SS		 603 .register_type = SH_ETH_REG_FAST_RCAR,
604
a3f109bd
SS		 605 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
606 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
607 .eesipr_value = 0x01ff009f,
608
609 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
ca8c3585
SS		 610 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
611 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
612 EESR_ECI,
d407bc02 613 .fdr_value = 0x00000f0f,
a3f109bd
SS		 614
615 .apr = 1,
616 .mpr = 1,
617 .tpauser = 1,
618 .hw_swap = 1,
619};
a3f109bd 620
94a12b15
SS		 621/* R8A7790/1 */
622static struct sh_eth_cpu_data r8a779x_data = {
e18dbf7e
SH		 623 .set_duplex = sh_eth_set_duplex,
624 .set_rate = sh_eth_set_rate_r8a777x,
625
a3153d8c
SS		 626 .register_type = SH_ETH_REG_FAST_RCAR,
627
e18dbf7e
SH		 628 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
629 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
630 .eesipr_value = 0x01ff009f,
631
632 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
ba361cb3
LP		 633 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
634 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
635 EESR_ECI,
d407bc02 636 .fdr_value = 0x00000f0f,
e18dbf7e 637
01fbd3f5
GU		 638 .trscer_err_mask = DESC_I_RINT8,
639
e18dbf7e
SH		 640 .apr = 1,
641 .mpr = 1,
642 .tpauser = 1,
643 .hw_swap = 1,
644 .rmiimode = 1,
645};
c74a2248 646#endif /* CONFIG_OF */
e18dbf7e 647
9c3beaab 648static void sh_eth_set_rate_sh7724(struct net_device *ndev)
a3f109bd
SS		 649{
650 struct sh_eth_private *mdp = netdev_priv(ndev);
65ac8851
YS		 651
652 switch (mdp->speed) {
653 case 10: /* 10BASE */
b2b14d2f 654 sh_eth_modify(ndev, ECMR, ECMR_RTM, 0);
65ac8851
YS		 655 break;
656 case 100:/* 100BASE */
b2b14d2f 657 sh_eth_modify(ndev, ECMR, ECMR_RTM, ECMR_RTM);
65ac8851 658 break;
65ac8851
YS		 659 }
660}
661
662/* SH7724 */
9c3beaab 663static struct sh_eth_cpu_data sh7724_data = {
65ac8851 664 .set_duplex = sh_eth_set_duplex,
9c3beaab 665 .set_rate = sh_eth_set_rate_sh7724,
65ac8851 666
a3153d8c
SS		 667 .register_type = SH_ETH_REG_FAST_SH4,
668
65ac8851
YS		 669 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
670 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
a80c3de7 671 .eesipr_value = 0x01ff009f,
65ac8851
YS		 672
673 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
ca8c3585
SS		 674 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
675 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
676 EESR_ECI,
65ac8851
YS		 677
678 .apr = 1,
679 .mpr = 1,
680 .tpauser = 1,
681 .hw_swap = 1,
503914cf
MD		 682 .rpadir = 1,
683 .rpadir_value = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
65ac8851 684};
5cee1d37 685
24549e2a 686static void sh_eth_set_rate_sh7757(struct net_device *ndev)
f29a3d04
YS		 687{
688 struct sh_eth_private *mdp = netdev_priv(ndev);
f29a3d04
YS		 689
690 switch (mdp->speed) {
691 case 10: /* 10BASE */
4a55530f 692 sh_eth_write(ndev, 0, RTRATE);
f29a3d04
YS		 693 break;
694 case 100:/* 100BASE */
4a55530f 695 sh_eth_write(ndev, 1, RTRATE);
f29a3d04 696 break;
f29a3d04
YS		 697 }
698}
699
700/* SH7757 */
24549e2a
SS		 701static struct sh_eth_cpu_data sh7757_data = {
702 .set_duplex = sh_eth_set_duplex,
703 .set_rate = sh_eth_set_rate_sh7757,
f29a3d04 704
a3153d8c
SS		 705 .register_type = SH_ETH_REG_FAST_SH4,
706
f29a3d04 707 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
f29a3d04
YS		 708
709 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
ca8c3585
SS		 710 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
711 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
712 EESR_ECI,
f29a3d04 713
5b3dfd13 714 .irq_flags = IRQF_SHARED,
f29a3d04
YS		 715 .apr = 1,
716 .mpr = 1,
717 .tpauser = 1,
718 .hw_swap = 1,
719 .no_ade = 1,
2e98e797
YS		 720 .rpadir = 1,
721 .rpadir_value = 2 << 16,
6b4b4fea 722 .rtrate = 1,
f29a3d04 723};
65ac8851 724
e403d295 725#define SH_GIGA_ETH_BASE 0xfee00000UL
8fcd4961
YS		 726#define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
727#define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
728static void sh_eth_chip_reset_giga(struct net_device *ndev)
729{
0799c2d6 730 u32 mahr[2], malr[2];
79270922 731 int i;
8fcd4961
YS		 732
733 /* save MAHR and MALR */
734 for (i = 0; i < 2; i++) {
ae70644d
YS		 735 malr[i] = ioread32((void *)GIGA_MALR(i));
736 mahr[i] = ioread32((void *)GIGA_MAHR(i));
8fcd4961
YS		 737 }
738
c66b2581 739 sh_eth_chip_reset(ndev);
8fcd4961
YS		 740
741 /* restore MAHR and MALR */
742 for (i = 0; i < 2; i++) {
ae70644d
YS		 743 iowrite32(malr[i], (void *)GIGA_MALR(i));
744 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
8fcd4961
YS		 745 }
746}
747
8fcd4961
YS		 748static void sh_eth_set_rate_giga(struct net_device *ndev)
749{
750 struct sh_eth_private *mdp = netdev_priv(ndev);
751
752 switch (mdp->speed) {
753 case 10: /* 10BASE */
754 sh_eth_write(ndev, 0x00000000, GECMR);
755 break;
756 case 100:/* 100BASE */
757 sh_eth_write(ndev, 0x00000010, GECMR);
758 break;
759 case 1000: /* 1000BASE */
760 sh_eth_write(ndev, 0x00000020, GECMR);
761 break;
8fcd4961
YS		 762 }
763}
764
765/* SH7757(GETHERC) */
24549e2a 766static struct sh_eth_cpu_data sh7757_data_giga = {
8fcd4961 767 .chip_reset = sh_eth_chip_reset_giga,
04b0ed2a 768 .set_duplex = sh_eth_set_duplex,
8fcd4961
YS		 769 .set_rate = sh_eth_set_rate_giga,
770
a3153d8c
SS		 771 .register_type = SH_ETH_REG_GIGABIT,
772
8fcd4961
YS		 773 .ecsr_value = ECSR_ICD | ECSR_MPD,
774 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
775 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
776
777 .tx_check = EESR_TC1 | EESR_FTC,
ca8c3585
SS		 778 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
779 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
780 EESR_TDE | EESR_ECI,
8fcd4961 781 .fdr_value = 0x0000072f,
8fcd4961 782
5b3dfd13 783 .irq_flags = IRQF_SHARED,
8fcd4961
YS		 784 .apr = 1,
785 .mpr = 1,
786 .tpauser = 1,
787 .bculr = 1,
788 .hw_swap = 1,
789 .rpadir = 1,
790 .rpadir_value = 2 << 16,
791 .no_trimd = 1,
792 .no_ade = 1,
3acbc971 793 .tsu = 1,
8fcd4961
YS		 794};
795
f5d12767
SS		 796/* SH7734 */
797static struct sh_eth_cpu_data sh7734_data = {
380af9e3
YS		 798 .chip_reset = sh_eth_chip_reset,
799 .set_duplex = sh_eth_set_duplex,
f5d12767
SS		 800 .set_rate = sh_eth_set_rate_gether,
801
a3153d8c
SS		 802 .register_type = SH_ETH_REG_GIGABIT,
803
f5d12767
SS		 804 .ecsr_value = ECSR_ICD | ECSR_MPD,
805 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
978d3639 806 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003f07ff,
f5d12767
SS		 807
808 .tx_check = EESR_TC1 | EESR_FTC,
ca8c3585
SS		 809 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
810 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
811 EESR_TDE | EESR_ECI,
f5d12767
SS		 812
813 .apr = 1,
814 .mpr = 1,
815 .tpauser = 1,
816 .bculr = 1,
817 .hw_swap = 1,
818 .no_trimd = 1,
819 .no_ade = 1,
820 .tsu = 1,
821 .hw_crc = 1,
822 .select_mii = 1,
71eae1ca 823 .shift_rd0 = 1,
f5d12767
SS		 824};
825
826/* SH7763 */
827static struct sh_eth_cpu_data sh7763_data = {
828 .chip_reset = sh_eth_chip_reset,
829 .set_duplex = sh_eth_set_duplex,
830 .set_rate = sh_eth_set_rate_gether,
380af9e3 831
a3153d8c
SS		 832 .register_type = SH_ETH_REG_GIGABIT,
833
380af9e3
YS		 834 .ecsr_value = ECSR_ICD | ECSR_MPD,
835 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
978d3639 836 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003f07ff,
380af9e3
YS		 837
838 .tx_check = EESR_TC1 | EESR_FTC,
128296fc
SS		 839 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
840 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
380af9e3 841 EESR_ECI,
380af9e3
YS		 842
843 .apr = 1,
844 .mpr = 1,
845 .tpauser = 1,
846 .bculr = 1,
847 .hw_swap = 1,
380af9e3
YS		 848 .no_trimd = 1,
849 .no_ade = 1,
4986b996 850 .tsu = 1,
5b3dfd13 851 .irq_flags = IRQF_SHARED,
380af9e3
YS		 852};
853
c18a79ab 854static struct sh_eth_cpu_data sh7619_data = {
a3153d8c
SS		 855 .register_type = SH_ETH_REG_FAST_SH3_SH2,
856
380af9e3
YS		 857 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
858
859 .apr = 1,
860 .mpr = 1,
861 .tpauser = 1,
862 .hw_swap = 1,
863};
7bbe150d
SS		 864
865static struct sh_eth_cpu_data sh771x_data = {
a3153d8c
SS		 866 .register_type = SH_ETH_REG_FAST_SH3_SH2,
867
380af9e3 868 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
4986b996 869 .tsu = 1,
380af9e3 870};
380af9e3
YS		 871
872static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
873{
874 if (!cd->ecsr_value)
875 cd->ecsr_value = DEFAULT_ECSR_INIT;
876
877 if (!cd->ecsipr_value)
878 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
879
880 if (!cd->fcftr_value)
128296fc 881 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF |
380af9e3
YS		 882 DEFAULT_FIFO_F_D_RFD;
883
884 if (!cd->fdr_value)
885 cd->fdr_value = DEFAULT_FDR_INIT;
886
380af9e3
YS		 887 if (!cd->tx_check)
888 cd->tx_check = DEFAULT_TX_CHECK;
889
890 if (!cd->eesr_err_check)
891 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
b284fbe3
NI		 892
893 if (!cd->trscer_err_mask)
894 cd->trscer_err_mask = DEFAULT_TRSCER_ERR_MASK;
380af9e3
YS		 895}
896
5cee1d37
NI		 897static int sh_eth_check_reset(struct net_device *ndev)
898{
899 int ret = 0;
900 int cnt = 100;
901
902 while (cnt > 0) {
97717edc 903 if (!(sh_eth_read(ndev, EDMR) & EDMR_SRST_GETHER))
5cee1d37
NI		 904 break;
905 mdelay(1);
906 cnt--;
907 }
9f8c4265 908 if (cnt <= 0) {
f75f14ec 909 netdev_err(ndev, "Device reset failed\n");
5cee1d37
NI		 910 ret = -ETIMEDOUT;
911 }
912 return ret;
380af9e3 913}
dabdde9e
NI		 914
915static int sh_eth_reset(struct net_device *ndev)
916{
917 struct sh_eth_private *mdp = netdev_priv(ndev);
918 int ret = 0;
919
db893473 920 if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp)) {
dabdde9e 921 sh_eth_write(ndev, EDSR_ENALL, EDSR);
b2b14d2f 922 sh_eth_modify(ndev, EDMR, EDMR_SRST_GETHER, EDMR_SRST_GETHER);
dabdde9e
NI		 923
924 ret = sh_eth_check_reset(ndev);
925 if (ret)
f738a13d 926 return ret;
dabdde9e
NI		 927
928 /* Table Init */
929 sh_eth_write(ndev, 0x0, TDLAR);
930 sh_eth_write(ndev, 0x0, TDFAR);
931 sh_eth_write(ndev, 0x0, TDFXR);
932 sh_eth_write(ndev, 0x0, TDFFR);
933 sh_eth_write(ndev, 0x0, RDLAR);
934 sh_eth_write(ndev, 0x0, RDFAR);
935 sh_eth_write(ndev, 0x0, RDFXR);
936 sh_eth_write(ndev, 0x0, RDFFR);
937
938 /* Reset HW CRC register */
939 if (mdp->cd->hw_crc)
940 sh_eth_write(ndev, 0x0, CSMR);
941
942 /* Select MII mode */
943 if (mdp->cd->select_mii)
944 sh_eth_select_mii(ndev);
945 } else {
b2b14d2f 946 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, EDMR_SRST_ETHER);
dabdde9e 947 mdelay(3);
b2b14d2f 948 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, 0);
dabdde9e
NI		 949 }
950
dabdde9e
NI		 951 return ret;
952}
380af9e3 953
380af9e3
YS		 954static void sh_eth_set_receive_align(struct sk_buff *skb)
955{
4d6a949c 956 uintptr_t reserve = (uintptr_t)skb->data & (SH_ETH_RX_ALIGN - 1);
380af9e3 957
380af9e3 958 if (reserve)
4d6a949c 959 skb_reserve(skb, SH_ETH_RX_ALIGN - reserve);
380af9e3 960}
380af9e3 961
128296fc 962/* Program the hardware MAC address from dev->dev_addr. */
86a74ff2
NI		 963static void update_mac_address(struct net_device *ndev)
964{
4a55530f 965 sh_eth_write(ndev,
128296fc
SS		 966 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
967 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
4a55530f 968 sh_eth_write(ndev,
128296fc 969 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
86a74ff2
NI		 970}
971
128296fc 972/* Get MAC address from SuperH MAC address register
86a74ff2
NI		 973 *
974 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
975 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
976 * When you want use this device, you must set MAC address in bootloader.
977 *
978 */
748031f9 979static void read_mac_address(struct net_device *ndev, unsigned char *mac)
86a74ff2 980{
748031f9 981 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
d458cdf7 982 memcpy(ndev->dev_addr, mac, ETH_ALEN);
748031f9 983 } else {
37742f02
SS		 984 u32 mahr = sh_eth_read(ndev, MAHR);
985 u32 malr = sh_eth_read(ndev, MALR);
986
987 ndev->dev_addr[0] = (mahr >> 24) & 0xFF;
988 ndev->dev_addr[1] = (mahr >> 16) & 0xFF;
989 ndev->dev_addr[2] = (mahr >> 8) & 0xFF;
990 ndev->dev_addr[3] = (mahr >> 0) & 0xFF;
991 ndev->dev_addr[4] = (malr >> 8) & 0xFF;
992 ndev->dev_addr[5] = (malr >> 0) & 0xFF;
748031f9 993 }
86a74ff2
NI		 994}
995
0799c2d6 996static u32 sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
c5ed5368 997{
db893473 998 if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp))
c5ed5368
YS		 999 return EDTRR_TRNS_GETHER;
1000 else
1001 return EDTRR_TRNS_ETHER;
1002}
1003
86a74ff2 1004struct bb_info {
ae70644d 1005 void (*set_gate)(void *addr);
86a74ff2 1006 struct mdiobb_ctrl ctrl;
ae70644d 1007 void *addr;
86a74ff2
NI		 1008};
1009
39b4b06b 1010static void sh_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set)
86a74ff2
NI		 1011{
1012 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
78fa3c5c 1013 u32 pir;
b3017e6a
YS		 1014
1015 if (bitbang->set_gate)
1016 bitbang->set_gate(bitbang->addr);
1017
78fa3c5c 1018 pir = ioread32(bitbang->addr);
39b4b06b 1019 if (set)
78fa3c5c 1020 pir |= mask;
86a74ff2 1021 else
78fa3c5c
SS		 1022 pir &= ~mask;
1023 iowrite32(pir, bitbang->addr);
39b4b06b
SS		 1024}
1025
1026/* Data I/O pin control */
1027static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1028{
1029 sh_mdio_ctrl(ctrl, PIR_MMD, bit);
86a74ff2
NI		 1030}
1031
1032/* Set bit data*/
1033static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
1034{
39b4b06b 1035 sh_mdio_ctrl(ctrl, PIR_MDO, bit);
86a74ff2
NI		 1036}
1037
1038/* Get bit data*/
1039static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
1040{
1041 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
b3017e6a
YS		 1042
1043 if (bitbang->set_gate)
1044 bitbang->set_gate(bitbang->addr);
1045
78fa3c5c 1046 return (ioread32(bitbang->addr) & PIR_MDI) != 0;
86a74ff2
NI		 1047}
1048
1049/* MDC pin control */
1050static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1051{
39b4b06b 1052 sh_mdio_ctrl(ctrl, PIR_MDC, bit);
86a74ff2
NI		 1053}
1054
1055/* mdio bus control struct */
1056static struct mdiobb_ops bb_ops = {
1057 .owner = THIS_MODULE,
1058 .set_mdc = sh_mdc_ctrl,
1059 .set_mdio_dir = sh_mmd_ctrl,
1060 .set_mdio_data = sh_set_mdio,
1061 .get_mdio_data = sh_get_mdio,
1062};
1063
86a74ff2
NI		 1064/* free skb and descriptor buffer */
1065static void sh_eth_ring_free(struct net_device *ndev)
1066{
1067 struct sh_eth_private *mdp = netdev_priv(ndev);
8e03a5e7 1068 int ringsize, i;
86a74ff2
NI		 1069
1070 /* Free Rx skb ringbuffer */
1071 if (mdp->rx_skbuff) {
179d80af
SS		 1072 for (i = 0; i < mdp->num_rx_ring; i++)
1073 dev_kfree_skb(mdp->rx_skbuff[i]);
86a74ff2
NI		 1074 }
1075 kfree(mdp->rx_skbuff);
91c77550 1076 mdp->rx_skbuff = NULL;
86a74ff2
NI		 1077
1078 /* Free Tx skb ringbuffer */
1079 if (mdp->tx_skbuff) {
179d80af
SS		 1080 for (i = 0; i < mdp->num_tx_ring; i++)
1081 dev_kfree_skb(mdp->tx_skbuff[i]);
86a74ff2
NI		 1082 }
1083 kfree(mdp->tx_skbuff);
91c77550 1084 mdp->tx_skbuff = NULL;
8e03a5e7
SS		 1085
1086 if (mdp->rx_ring) {
1087 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1088 dma_free_coherent(NULL, ringsize, mdp->rx_ring,
1089 mdp->rx_desc_dma);
1090 mdp->rx_ring = NULL;
1091 }
1092
1093 if (mdp->tx_ring) {
1094 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1095 dma_free_coherent(NULL, ringsize, mdp->tx_ring,
1096 mdp->tx_desc_dma);
1097 mdp->tx_ring = NULL;
1098 }
86a74ff2
NI		 1099}
1100
1101/* format skb and descriptor buffer */
1102static void sh_eth_ring_format(struct net_device *ndev)
1103{
1104 struct sh_eth_private *mdp = netdev_priv(ndev);
1105 int i;
1106 struct sk_buff *skb;
1107 struct sh_eth_rxdesc *rxdesc = NULL;
1108 struct sh_eth_txdesc *txdesc = NULL;
525b8075
YS		 1109 int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
1110 int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
cb368595 1111 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
52b9fa36 1112 dma_addr_t dma_addr;
5cbf20c7 1113 u32 buf_len;
86a74ff2 1114
128296fc
SS		 1115 mdp->cur_rx = 0;
1116 mdp->cur_tx = 0;
1117 mdp->dirty_rx = 0;
1118 mdp->dirty_tx = 0;
86a74ff2
NI		 1119
1120 memset(mdp->rx_ring, 0, rx_ringsize);
1121
1122 /* build Rx ring buffer */
525b8075 1123 for (i = 0; i < mdp->num_rx_ring; i++) {
86a74ff2
NI		 1124 /* skb */
1125 mdp->rx_skbuff[i] = NULL;
4d6a949c 1126 skb = netdev_alloc_skb(ndev, skbuff_size);
86a74ff2
NI		 1127 if (skb == NULL)
1128 break;
380af9e3
YS		 1129 sh_eth_set_receive_align(skb);
1130
ab857916 1131 /* The size of the buffer is a multiple of 32 bytes. */
5cbf20c7 1132 buf_len = ALIGN(mdp->rx_buf_sz, 32);
5cbf20c7 1133 dma_addr = dma_map_single(&ndev->dev, skb->data, buf_len,
52b9fa36
BH		 1134 DMA_FROM_DEVICE);
1135 if (dma_mapping_error(&ndev->dev, dma_addr)) {
1136 kfree_skb(skb);
1137 break;
1138 }
1139 mdp->rx_skbuff[i] = skb;
d0ba9134
SS		 1140
1141 /* RX descriptor */
1142 rxdesc = &mdp->rx_ring[i];
1143 rxdesc->len = cpu_to_le32(buf_len << 16);
7cf72477
SS		 1144 rxdesc->addr = cpu_to_le32(dma_addr);
1145 rxdesc->status = cpu_to_le32(RD_RACT | RD_RFP);
86a74ff2 1146
b0ca2a21
NI		 1147 /* Rx descriptor address set */
1148 if (i == 0) {
4a55530f 1149 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
db893473
SH		 1150 if (sh_eth_is_gether(mdp) ||
1151 sh_eth_is_rz_fast_ether(mdp))
c5ed5368 1152 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
b0ca2a21 1153 }
86a74ff2
NI		 1154 }
1155
525b8075 1156 mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
86a74ff2
NI		 1157
1158 /* Mark the last entry as wrapping the ring. */
c1b7fca6
SS		 1159 if (rxdesc)
1160 rxdesc->status |= cpu_to_le32(RD_RDLE);
86a74ff2
NI		 1161
1162 memset(mdp->tx_ring, 0, tx_ringsize);
1163
1164 /* build Tx ring buffer */
525b8075 1165 for (i = 0; i < mdp->num_tx_ring; i++) {
86a74ff2
NI		 1166 mdp->tx_skbuff[i] = NULL;
1167 txdesc = &mdp->tx_ring[i];
7cf72477
SS		 1168 txdesc->status = cpu_to_le32(TD_TFP);
1169 txdesc->len = cpu_to_le32(0);
b0ca2a21 1170 if (i == 0) {
71557a37 1171 /* Tx descriptor address set */
4a55530f 1172 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
db893473
SH		 1173 if (sh_eth_is_gether(mdp) ||
1174 sh_eth_is_rz_fast_ether(mdp))
c5ed5368 1175 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
b0ca2a21 1176 }
86a74ff2
NI		 1177 }
1178
7cf72477 1179 txdesc->status |= cpu_to_le32(TD_TDLE);
86a74ff2
NI		 1180}
1181
1182/* Get skb and descriptor buffer */
1183static int sh_eth_ring_init(struct net_device *ndev)
1184{
1185 struct sh_eth_private *mdp = netdev_priv(ndev);
91d80683 1186 int rx_ringsize, tx_ringsize;
86a74ff2 1187
128296fc 1188 /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
86a74ff2
NI		 1189 * card needs room to do 8 byte alignment, +2 so we can reserve
1190 * the first 2 bytes, and +16 gets room for the status word from the
1191 * card.
1192 */
1193 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
1194 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
503914cf
MD		 1195 if (mdp->cd->rpadir)
1196 mdp->rx_buf_sz += NET_IP_ALIGN;
86a74ff2
NI		 1197
1198 /* Allocate RX and TX skb rings */
2c94e856
SS		 1199 mdp->rx_skbuff = kcalloc(mdp->num_rx_ring, sizeof(*mdp->rx_skbuff),
1200 GFP_KERNEL);
91d80683
SS		 1201 if (!mdp->rx_skbuff)
1202 return -ENOMEM;
86a74ff2 1203
2c94e856
SS		 1204 mdp->tx_skbuff = kcalloc(mdp->num_tx_ring, sizeof(*mdp->tx_skbuff),
1205 GFP_KERNEL);
91d80683 1206 if (!mdp->tx_skbuff)
8e03a5e7 1207 goto ring_free;
86a74ff2
NI		 1208
1209 /* Allocate all Rx descriptors. */
525b8075 1210 rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
86a74ff2 1211 mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
d0320f75 1212 GFP_KERNEL);
91d80683 1213 if (!mdp->rx_ring)
8e03a5e7 1214 goto ring_free;
86a74ff2
NI		 1215
1216 mdp->dirty_rx = 0;
1217
1218 /* Allocate all Tx descriptors. */
525b8075 1219 tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
86a74ff2 1220 mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
d0320f75 1221 GFP_KERNEL);
91d80683 1222 if (!mdp->tx_ring)
8e03a5e7 1223 goto ring_free;
91d80683 1224 return 0;
86a74ff2 1225
8e03a5e7
SS		 1226ring_free:
1227 /* Free Rx and Tx skb ring buffer and DMA buffer */
86a74ff2
NI		 1228 sh_eth_ring_free(ndev);
1229
91d80683 1230 return -ENOMEM;
86a74ff2
NI		 1231}
1232
f7967210 1233static int sh_eth_dev_init(struct net_device *ndev)
86a74ff2 1234{
86a74ff2 1235 struct sh_eth_private *mdp = netdev_priv(ndev);
4fa8c3cc 1236 int ret;
86a74ff2
NI		 1237
1238 /* Soft Reset */
5cee1d37
NI		 1239 ret = sh_eth_reset(ndev);
1240 if (ret)
f738a13d 1241 return ret;
86a74ff2 1242
55754f19
SH		 1243 if (mdp->cd->rmiimode)
1244 sh_eth_write(ndev, 0x1, RMIIMODE);
1245
b0ca2a21
NI		 1246 /* Descriptor format */
1247 sh_eth_ring_format(ndev);
380af9e3 1248 if (mdp->cd->rpadir)
4a55530f 1249 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
86a74ff2
NI		 1250
1251 /* all sh_eth int mask */
4a55530f 1252 sh_eth_write(ndev, 0, EESIPR);
86a74ff2 1253
10b9194f 1254#if defined(__LITTLE_ENDIAN)
380af9e3 1255 if (mdp->cd->hw_swap)
4a55530f 1256 sh_eth_write(ndev, EDMR_EL, EDMR);
380af9e3 1257 else
b0ca2a21 1258#endif
4a55530f 1259 sh_eth_write(ndev, 0, EDMR);
86a74ff2 1260
b0ca2a21 1261 /* FIFO size set */
4a55530f
YS		 1262 sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
1263 sh_eth_write(ndev, 0, TFTR);
86a74ff2 1264
530aa2d0
BD		 1265 /* Frame recv control (enable multiple-packets per rx irq) */
1266 sh_eth_write(ndev, RMCR_RNC, RMCR);
86a74ff2 1267
b284fbe3 1268 sh_eth_write(ndev, mdp->cd->trscer_err_mask, TRSCER);
86a74ff2 1269
380af9e3 1270 if (mdp->cd->bculr)
4a55530f 1271 sh_eth_write(ndev, 0x800, BCULR); /* Burst sycle set */
b0ca2a21 1272
4a55530f 1273 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
86a74ff2 1274
380af9e3 1275 if (!mdp->cd->no_trimd)
4a55530f 1276 sh_eth_write(ndev, 0, TRIMD);
86a74ff2 1277
b0ca2a21 1278 /* Recv frame limit set register */
fdb37a7f
YS		 1279 sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1280 RFLR);
86a74ff2 1281
b2b14d2f 1282 sh_eth_modify(ndev, EESR, 0, 0);
f7967210
SS		 1283 mdp->irq_enabled = true;
1284 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
86a74ff2
NI		 1285
1286 /* PAUSE Prohibition */
bffa731f
SS		 1287 sh_eth_write(ndev, ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) |
1288 ECMR_TE | ECMR_RE, ECMR);
b0ca2a21 1289
380af9e3
YS		 1290 if (mdp->cd->set_rate)
1291 mdp->cd->set_rate(ndev);
1292
b0ca2a21 1293 /* E-MAC Status Register clear */
4a55530f 1294 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
b0ca2a21
NI		 1295
1296 /* E-MAC Interrupt Enable register */
f7967210 1297 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
86a74ff2
NI		 1298
1299 /* Set MAC address */
1300 update_mac_address(ndev);
1301
1302 /* mask reset */
380af9e3 1303 if (mdp->cd->apr)
4a55530f 1304 sh_eth_write(ndev, APR_AP, APR);
380af9e3 1305 if (mdp->cd->mpr)
4a55530f 1306 sh_eth_write(ndev, MPR_MP, MPR);
380af9e3 1307 if (mdp->cd->tpauser)
4a55530f 1308 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
b0ca2a21 1309
f7967210
SS		 1310 /* Setting the Rx mode will start the Rx process. */
1311 sh_eth_write(ndev, EDRRR_R, EDRRR);
86a74ff2
NI		 1312
1313 return ret;
1314}
1315
740c7f31
BH		 1316static void sh_eth_dev_exit(struct net_device *ndev)
1317{
1318 struct sh_eth_private *mdp = netdev_priv(ndev);
1319 int i;
1320
1321 /* Deactivate all TX descriptors, so DMA should stop at next
1322 * packet boundary if it's currently running
1323 */
1324 for (i = 0; i < mdp->num_tx_ring; i++)
7cf72477 1325 mdp->tx_ring[i].status &= ~cpu_to_le32(TD_TACT);
740c7f31
BH		 1326
1327 /* Disable TX FIFO egress to MAC */
1328 sh_eth_rcv_snd_disable(ndev);
1329
1330 /* Stop RX DMA at next packet boundary */
1331 sh_eth_write(ndev, 0, EDRRR);
1332
1333 /* Aside from TX DMA, we can't tell when the hardware is
1334 * really stopped, so we need to reset to make sure.
1335 * Before doing that, wait for long enough to *probably*
1336 * finish transmitting the last packet and poll stats.
1337 */
1338 msleep(2); /* max frame time at 10 Mbps < 1250 us */
1339 sh_eth_get_stats(ndev);
1340 sh_eth_reset(ndev);
a14c7d15
GU		 1341
1342 /* Set MAC address again */
1343 update_mac_address(ndev);
740c7f31
BH		 1344}
1345
86a74ff2
NI		 1346/* free Tx skb function */
1347static int sh_eth_txfree(struct net_device *ndev)
1348{
1349 struct sh_eth_private *mdp = netdev_priv(ndev);
1350 struct sh_eth_txdesc *txdesc;
128296fc 1351 int free_num = 0;
4fa8c3cc 1352 int entry;
86a74ff2
NI		 1353
1354 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
525b8075 1355 entry = mdp->dirty_tx % mdp->num_tx_ring;
86a74ff2 1356 txdesc = &mdp->tx_ring[entry];
7cf72477 1357 if (txdesc->status & cpu_to_le32(TD_TACT))
86a74ff2 1358 break;
7d7355f5 1359 /* TACT bit must be checked before all the following reads */
f32bfb9a 1360 dma_rmb();
e5fd13f4
BH		 1361 netif_info(mdp, tx_done, ndev,
1362 "tx entry %d status 0x%08x\n",
7cf72477 1363 entry, le32_to_cpu(txdesc->status));
86a74ff2
NI		 1364 /* Free the original skb. */
1365 if (mdp->tx_skbuff[entry]) {
7cf72477
SS		 1366 dma_unmap_single(&ndev->dev, le32_to_cpu(txdesc->addr),
1367 le32_to_cpu(txdesc->len) >> 16,
5cbf20c7 1368 DMA_TO_DEVICE);
86a74ff2
NI		 1369 dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1370 mdp->tx_skbuff[entry] = NULL;
128296fc 1371 free_num++;
86a74ff2 1372 }
7cf72477 1373 txdesc->status = cpu_to_le32(TD_TFP);
525b8075 1374 if (entry >= mdp->num_tx_ring - 1)
7cf72477 1375 txdesc->status |= cpu_to_le32(TD_TDLE);
86a74ff2 1376
bb7d92e3 1377 ndev->stats.tx_packets++;
7cf72477 1378 ndev->stats.tx_bytes += le32_to_cpu(txdesc->len) >> 16;
86a74ff2 1379 }
128296fc 1380 return free_num;
86a74ff2
NI		 1381}
1382
1383/* Packet receive function */
3719109d 1384static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
86a74ff2
NI		 1385{
1386 struct sh_eth_private *mdp = netdev_priv(ndev);
1387 struct sh_eth_rxdesc *rxdesc;
1388
525b8075
YS		 1389 int entry = mdp->cur_rx % mdp->num_rx_ring;
1390 int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
319cd520 1391 int limit;
86a74ff2 1392 struct sk_buff *skb;
380af9e3 1393 u32 desc_status;
cb368595 1394 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
52b9fa36 1395 dma_addr_t dma_addr;
4fa8c3cc 1396 u16 pkt_len;
5cbf20c7 1397 u32 buf_len;
86a74ff2 1398
319cd520
MK		 1399 boguscnt = min(boguscnt, *quota);
1400 limit = boguscnt;
86a74ff2 1401 rxdesc = &mdp->rx_ring[entry];
7cf72477 1402 while (!(rxdesc->status & cpu_to_le32(RD_RACT))) {
7d7355f5 1403 /* RACT bit must be checked before all the following reads */
f32bfb9a 1404 dma_rmb();
7cf72477
SS		 1405 desc_status = le32_to_cpu(rxdesc->status);
1406 pkt_len = le32_to_cpu(rxdesc->len) & RD_RFL;
86a74ff2
NI		 1407
1408 if (--boguscnt < 0)
1409 break;
1410
e5fd13f4
BH		 1411 netif_info(mdp, rx_status, ndev,
1412 "rx entry %d status 0x%08x len %d\n",
1413 entry, desc_status, pkt_len);
1414
86a74ff2 1415 if (!(desc_status & RDFEND))
bb7d92e3 1416 ndev->stats.rx_length_errors++;
86a74ff2 1417
128296fc 1418 /* In case of almost all GETHER/ETHERs, the Receive Frame State
dd019897 1419 * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
9b4a6364
BH		 1420 * bit 0. However, in case of the R8A7740 and R7S72100
1421 * the RFS bits are from bit 25 to bit 16. So, the
db893473 1422 * driver needs right shifting by 16.
dd019897 1423 */
ac8025a6
SS		 1424 if (mdp->cd->shift_rd0)
1425 desc_status >>= 16;
dd019897 1426
248be83d 1427 skb = mdp->rx_skbuff[entry];
86a74ff2
NI		 1428 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1429 RD_RFS5 | RD_RFS6 | RD_RFS10)) {
bb7d92e3 1430 ndev->stats.rx_errors++;
86a74ff2 1431 if (desc_status & RD_RFS1)
bb7d92e3 1432 ndev->stats.rx_crc_errors++;
86a74ff2 1433 if (desc_status & RD_RFS2)
bb7d92e3 1434 ndev->stats.rx_frame_errors++;
86a74ff2 1435 if (desc_status & RD_RFS3)
bb7d92e3 1436 ndev->stats.rx_length_errors++;
86a74ff2 1437 if (desc_status & RD_RFS4)
bb7d92e3 1438 ndev->stats.rx_length_errors++;
86a74ff2 1439 if (desc_status & RD_RFS6)
bb7d92e3 1440 ndev->stats.rx_missed_errors++;
86a74ff2 1441 if (desc_status & RD_RFS10)
bb7d92e3 1442 ndev->stats.rx_over_errors++;
248be83d 1443 } else if (skb) {
7cf72477 1444 dma_addr = le32_to_cpu(rxdesc->addr);
380af9e3
YS		 1445 if (!mdp->cd->hw_swap)
1446 sh_eth_soft_swap(
1299653a 1447 phys_to_virt(ALIGN(dma_addr, 4)),
380af9e3 1448 pkt_len + 2);
86a74ff2 1449 mdp->rx_skbuff[entry] = NULL;
503914cf
MD		 1450 if (mdp->cd->rpadir)
1451 skb_reserve(skb, NET_IP_ALIGN);
1299653a 1452 dma_unmap_single(&ndev->dev, dma_addr,
ab857916 1453 ALIGN(mdp->rx_buf_sz, 32),
52b9fa36 1454 DMA_FROM_DEVICE);
86a74ff2
NI		 1455 skb_put(skb, pkt_len);
1456 skb->protocol = eth_type_trans(skb, ndev);
a8e9fd0f 1457 netif_receive_skb(skb);
bb7d92e3
ED		 1458 ndev->stats.rx_packets++;
1459 ndev->stats.rx_bytes += pkt_len;
25b77ad7
BH		 1460 if (desc_status & RD_RFS8)
1461 ndev->stats.multicast++;
86a74ff2 1462 }
525b8075 1463 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
862df497 1464 rxdesc = &mdp->rx_ring[entry];
86a74ff2
NI		 1465 }
1466
1467 /* Refill the Rx ring buffers. */
1468 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
525b8075 1469 entry = mdp->dirty_rx % mdp->num_rx_ring;
86a74ff2 1470 rxdesc = &mdp->rx_ring[entry];
ab857916 1471 /* The size of the buffer is 32 byte boundary. */
5cbf20c7 1472 buf_len = ALIGN(mdp->rx_buf_sz, 32);
7cf72477 1473 rxdesc->len = cpu_to_le32(buf_len << 16);
b0ca2a21 1474
86a74ff2 1475 if (mdp->rx_skbuff[entry] == NULL) {
4d6a949c 1476 skb = netdev_alloc_skb(ndev, skbuff_size);
86a74ff2
NI		 1477 if (skb == NULL)
1478 break; /* Better luck next round. */
380af9e3 1479 sh_eth_set_receive_align(skb);
52b9fa36 1480 dma_addr = dma_map_single(&ndev->dev, skb->data,
5cbf20c7 1481 buf_len, DMA_FROM_DEVICE);
52b9fa36
BH		 1482 if (dma_mapping_error(&ndev->dev, dma_addr)) {
1483 kfree_skb(skb);
1484 break;
1485 }
1486 mdp->rx_skbuff[entry] = skb;
380af9e3 1487
bc8acf2c 1488 skb_checksum_none_assert(skb);
7cf72477 1489 rxdesc->addr = cpu_to_le32(dma_addr);
86a74ff2 1490 }
f32bfb9a 1491 dma_wmb(); /* RACT bit must be set after all the above writes */
525b8075 1492 if (entry >= mdp->num_rx_ring - 1)
86a74ff2 1493 rxdesc->status |=
7cf72477 1494 cpu_to_le32(RD_RACT | RD_RFP | RD_RDLE);
86a74ff2 1495 else
7cf72477 1496 rxdesc->status |= cpu_to_le32(RD_RACT | RD_RFP);
86a74ff2
NI		 1497 }
1498
1499 /* Restart Rx engine if stopped. */
1500 /* If we don't need to check status, don't. -KDU */
79fba9f5 1501 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
a18e08bd 1502 /* fix the values for the next receiving if RDE is set */
3365711d
BH		 1503 if (intr_status & EESR_RDE &&
1504 mdp->reg_offset[RDFAR] != SH_ETH_OFFSET_INVALID) {
128296fc
SS		 1505 u32 count = (sh_eth_read(ndev, RDFAR) -
1506 sh_eth_read(ndev, RDLAR)) >> 4;
1507
1508 mdp->cur_rx = count;
1509 mdp->dirty_rx = count;
1510 }
4a55530f 1511 sh_eth_write(ndev, EDRRR_R, EDRRR);
79fba9f5 1512 }
86a74ff2 1513
319cd520
MK		 1514 *quota -= limit - boguscnt - 1;
1515
4f809cea 1516 return *quota <= 0;
86a74ff2
NI		 1517}
1518
4a55530f 1519static void sh_eth_rcv_snd_disable(struct net_device *ndev)
dc19e4e5
NI		 1520{
1521 /* disable tx and rx */
b2b14d2f 1522 sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0);
dc19e4e5
NI		 1523}
1524
4a55530f 1525static void sh_eth_rcv_snd_enable(struct net_device *ndev)
dc19e4e5
NI		 1526{
1527 /* enable tx and rx */
b2b14d2f 1528 sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE);
dc19e4e5
NI		 1529}
1530
86a74ff2 1531/* error control function */
0799c2d6 1532static void sh_eth_error(struct net_device *ndev, u32 intr_status)
86a74ff2
NI		 1533{
1534 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2 1535 u32 felic_stat;
380af9e3
YS		 1536 u32 link_stat;
1537 u32 mask;
86a74ff2
NI		 1538
1539 if (intr_status & EESR_ECI) {
4a55530f
YS		 1540 felic_stat = sh_eth_read(ndev, ECSR);
1541 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */
86a74ff2 1542 if (felic_stat & ECSR_ICD)
bb7d92e3 1543 ndev->stats.tx_carrier_errors++;
86a74ff2
NI		 1544 if (felic_stat & ECSR_LCHNG) {
1545 /* Link Changed */
4923576b 1546 if (mdp->cd->no_psr || mdp->no_ether_link) {
1e1b812b 1547 goto ignore_link;
380af9e3 1548 } else {
4a55530f 1549 link_stat = (sh_eth_read(ndev, PSR));
4923576b
YS		 1550 if (mdp->ether_link_active_low)
1551 link_stat = ~link_stat;
380af9e3 1552 }
128296fc 1553 if (!(link_stat & PHY_ST_LINK)) {
4a55530f 1554 sh_eth_rcv_snd_disable(ndev);
128296fc 1555 } else {
86a74ff2 1556 /* Link Up */
b2b14d2f 1557 sh_eth_modify(ndev, EESIPR, DMAC_M_ECI, 0);
128296fc 1558 /* clear int */
b2b14d2f
SS		 1559 sh_eth_modify(ndev, ECSR, 0, 0);
1560 sh_eth_modify(ndev, EESIPR, DMAC_M_ECI,
1561 DMAC_M_ECI);
86a74ff2 1562 /* enable tx and rx */
4a55530f 1563 sh_eth_rcv_snd_enable(ndev);
86a74ff2
NI		 1564 }
1565 }
1566 }
1567
1e1b812b 1568ignore_link:
86a74ff2 1569 if (intr_status & EESR_TWB) {
4eb313a7
SS		 1570 /* Unused write back interrupt */
1571 if (intr_status & EESR_TABT) { /* Transmit Abort int */
bb7d92e3 1572 ndev->stats.tx_aborted_errors++;
8d5009f6 1573 netif_err(mdp, tx_err, ndev, "Transmit Abort\n");
4eb313a7 1574 }
86a74ff2
NI		 1575 }
1576
1577 if (intr_status & EESR_RABT) {
1578 /* Receive Abort int */
1579 if (intr_status & EESR_RFRMER) {
1580 /* Receive Frame Overflow int */
bb7d92e3 1581 ndev->stats.rx_frame_errors++;
86a74ff2
NI		 1582 }
1583 }
380af9e3 1584
dc19e4e5
NI		 1585 if (intr_status & EESR_TDE) {
1586 /* Transmit Descriptor Empty int */
bb7d92e3 1587 ndev->stats.tx_fifo_errors++;
8d5009f6 1588 netif_err(mdp, tx_err, ndev, "Transmit Descriptor Empty\n");
dc19e4e5
NI		 1589 }
1590
1591 if (intr_status & EESR_TFE) {
1592 /* FIFO under flow */
bb7d92e3 1593 ndev->stats.tx_fifo_errors++;
8d5009f6 1594 netif_err(mdp, tx_err, ndev, "Transmit FIFO Under flow\n");
86a74ff2
NI		 1595 }
1596
1597 if (intr_status & EESR_RDE) {
1598 /* Receive Descriptor Empty int */
bb7d92e3 1599 ndev->stats.rx_over_errors++;
86a74ff2 1600 }
dc19e4e5 1601
86a74ff2
NI		 1602 if (intr_status & EESR_RFE) {
1603 /* Receive FIFO Overflow int */
bb7d92e3 1604 ndev->stats.rx_fifo_errors++;
dc19e4e5
NI		 1605 }
1606
1607 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1608 /* Address Error */
bb7d92e3 1609 ndev->stats.tx_fifo_errors++;
8d5009f6 1610 netif_err(mdp, tx_err, ndev, "Address Error\n");
86a74ff2 1611 }
380af9e3
YS		 1612
1613 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1614 if (mdp->cd->no_ade)
1615 mask &= ~EESR_ADE;
1616 if (intr_status & mask) {
86a74ff2 1617 /* Tx error */
4a55530f 1618 u32 edtrr = sh_eth_read(ndev, EDTRR);
090d560f 1619
86a74ff2 1620 /* dmesg */
da246855
SS		 1621 netdev_err(ndev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1622 intr_status, mdp->cur_tx, mdp->dirty_tx,
1623 (u32)ndev->state, edtrr);
86a74ff2
NI		 1624 /* dirty buffer free */
1625 sh_eth_txfree(ndev);
1626
1627 /* SH7712 BUG */
c5ed5368 1628 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
86a74ff2 1629 /* tx dma start */
c5ed5368 1630 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
86a74ff2
NI		 1631 }
1632 /* wakeup */
1633 netif_wake_queue(ndev);
1634 }
1635}
1636
1637static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1638{
1639 struct net_device *ndev = netdev;
1640 struct sh_eth_private *mdp = netdev_priv(ndev);
380af9e3 1641 struct sh_eth_cpu_data *cd = mdp->cd;
0e0fde3c 1642 irqreturn_t ret = IRQ_NONE;
0799c2d6 1643 u32 intr_status, intr_enable;
86a74ff2 1644
86a74ff2
NI		 1645 spin_lock(&mdp->lock);
1646
3893b273 1647 /* Get interrupt status */
4a55530f 1648 intr_status = sh_eth_read(ndev, EESR);
3893b273
SS		 1649 /* Mask it with the interrupt mask, forcing ECI interrupt to be always
1650 * enabled since it's the one that comes thru regardless of the mask,
1651 * and we need to fully handle it in sh_eth_error() in order to quench
1652 * it as it doesn't get cleared by just writing 1 to the ECI bit...
1653 */
3719109d
SS		 1654 intr_enable = sh_eth_read(ndev, EESIPR);
1655 intr_status &= intr_enable | DMAC_M_ECI;
1656 if (intr_status & (EESR_RX_CHECK | cd->tx_check | cd->eesr_err_check))
0e0fde3c 1657 ret = IRQ_HANDLED;
3719109d 1658 else
283e38db
BH		 1659 goto out;
1660
2344ef3c 1661 if (unlikely(!mdp->irq_enabled)) {
283e38db
BH		 1662 sh_eth_write(ndev, 0, EESIPR);
1663 goto out;
1664 }
86a74ff2 1665
3719109d
SS		 1666 if (intr_status & EESR_RX_CHECK) {
1667 if (napi_schedule_prep(&mdp->napi)) {
1668 /* Mask Rx interrupts */
1669 sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK,
1670 EESIPR);
1671 __napi_schedule(&mdp->napi);
1672 } else {
da246855 1673 netdev_warn(ndev,
0799c2d6 1674 "ignoring interrupt, status 0x%08x, mask 0x%08x.\n",
da246855 1675 intr_status, intr_enable);
3719109d
SS		 1676 }
1677 }
86a74ff2 1678
b0ca2a21 1679 /* Tx Check */
380af9e3 1680 if (intr_status & cd->tx_check) {
3719109d
SS		 1681 /* Clear Tx interrupts */
1682 sh_eth_write(ndev, intr_status & cd->tx_check, EESR);
1683
86a74ff2
NI		 1684 sh_eth_txfree(ndev);
1685 netif_wake_queue(ndev);
1686 }
1687
3719109d
SS		 1688 if (intr_status & cd->eesr_err_check) {
1689 /* Clear error interrupts */
1690 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR);
1691
86a74ff2 1692 sh_eth_error(ndev, intr_status);
3719109d 1693 }
86a74ff2 1694
283e38db 1695out:
86a74ff2
NI		 1696 spin_unlock(&mdp->lock);
1697
0e0fde3c 1698 return ret;
86a74ff2
NI		 1699}
1700
3719109d
SS		 1701static int sh_eth_poll(struct napi_struct *napi, int budget)
1702{
1703 struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private,
1704 napi);
1705 struct net_device *ndev = napi->dev;
1706 int quota = budget;
0799c2d6 1707 u32 intr_status;
3719109d
SS		 1708
1709 for (;;) {
1710 intr_status = sh_eth_read(ndev, EESR);
1711 if (!(intr_status & EESR_RX_CHECK))
1712 break;
1713 /* Clear Rx interrupts */
1714 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR);
1715
1716 if (sh_eth_rx(ndev, intr_status, &quota))
1717 goto out;
1718 }
1719
1720 napi_complete(napi);
1721
1722 /* Reenable Rx interrupts */
283e38db
BH		 1723 if (mdp->irq_enabled)
1724 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
3719109d
SS		 1725out:
1726 return budget - quota;
1727}
1728
86a74ff2
NI		 1729/* PHY state control function */
1730static void sh_eth_adjust_link(struct net_device *ndev)
1731{
1732 struct sh_eth_private *mdp = netdev_priv(ndev);
9fd0375a 1733 struct phy_device *phydev = ndev->phydev;
86a74ff2
NI		 1734 int new_state = 0;
1735
3340d2aa 1736 if (phydev->link) {
86a74ff2
NI		 1737 if (phydev->duplex != mdp->duplex) {
1738 new_state = 1;
1739 mdp->duplex = phydev->duplex;
380af9e3
YS		 1740 if (mdp->cd->set_duplex)
1741 mdp->cd->set_duplex(ndev);
86a74ff2
NI		 1742 }
1743
1744 if (phydev->speed != mdp->speed) {
1745 new_state = 1;
1746 mdp->speed = phydev->speed;
380af9e3
YS		 1747 if (mdp->cd->set_rate)
1748 mdp->cd->set_rate(ndev);
86a74ff2 1749 }
3340d2aa 1750 if (!mdp->link) {
b2b14d2f 1751 sh_eth_modify(ndev, ECMR, ECMR_TXF, 0);
86a74ff2
NI		 1752 new_state = 1;
1753 mdp->link = phydev->link;
1e1b812b
SS		 1754 if (mdp->cd->no_psr || mdp->no_ether_link)
1755 sh_eth_rcv_snd_enable(ndev);
86a74ff2
NI		 1756 }
1757 } else if (mdp->link) {
1758 new_state = 1;
3340d2aa 1759 mdp->link = 0;
86a74ff2
NI		 1760 mdp->speed = 0;
1761 mdp->duplex = -1;
1e1b812b
SS		 1762 if (mdp->cd->no_psr || mdp->no_ether_link)
1763 sh_eth_rcv_snd_disable(ndev);
86a74ff2
NI		 1764 }
1765
dc19e4e5 1766 if (new_state && netif_msg_link(mdp))
86a74ff2
NI		 1767 phy_print_status(phydev);
1768}
1769
1770/* PHY init function */
1771static int sh_eth_phy_init(struct net_device *ndev)
1772{
702eca02 1773 struct device_node *np = ndev->dev.parent->of_node;
86a74ff2 1774 struct sh_eth_private *mdp = netdev_priv(ndev);
4fa8c3cc 1775 struct phy_device *phydev;
86a74ff2 1776
3340d2aa 1777 mdp->link = 0;
86a74ff2
NI		 1778 mdp->speed = 0;
1779 mdp->duplex = -1;
1780
1781 /* Try connect to PHY */
702eca02
BD		 1782 if (np) {
1783 struct device_node *pn;
1784
1785 pn = of_parse_phandle(np, "phy-handle", 0);
1786 phydev = of_phy_connect(ndev, pn,
1787 sh_eth_adjust_link, 0,
1788 mdp->phy_interface);
1789
8da703dc 1790 of_node_put(pn);
702eca02
BD		 1791 if (!phydev)
1792 phydev = ERR_PTR(-ENOENT);
1793 } else {
1794 char phy_id[MII_BUS_ID_SIZE + 3];
1795
1796 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
1797 mdp->mii_bus->id, mdp->phy_id);
1798
1799 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
1800 mdp->phy_interface);
1801 }
1802
86a74ff2 1803 if (IS_ERR(phydev)) {
da246855 1804 netdev_err(ndev, "failed to connect PHY\n");
86a74ff2
NI		 1805 return PTR_ERR(phydev);
1806 }
380af9e3 1807
2220943a 1808 phy_attached_info(phydev);
86a74ff2 1809
86a74ff2
NI		 1810 return 0;
1811}
1812
1813/* PHY control start function */
1814static int sh_eth_phy_start(struct net_device *ndev)
1815{
86a74ff2
NI		 1816 int ret;
1817
1818 ret = sh_eth_phy_init(ndev);
1819 if (ret)
1820 return ret;
1821
9fd0375a 1822 phy_start(ndev->phydev);
86a74ff2
NI		 1823
1824 return 0;
1825}
1826
f08aff44
PR		 1827static int sh_eth_get_link_ksettings(struct net_device *ndev,
1828 struct ethtool_link_ksettings *cmd)
dc19e4e5
NI		 1829{
1830 struct sh_eth_private *mdp = netdev_priv(ndev);
1831 unsigned long flags;
1832 int ret;
1833
9fd0375a 1834 if (!ndev->phydev)
4f9dce23
BH		 1835 return -ENODEV;
1836
dc19e4e5 1837 spin_lock_irqsave(&mdp->lock, flags);
f08aff44 1838 ret = phy_ethtool_ksettings_get(ndev->phydev, cmd);
dc19e4e5
NI		 1839 spin_unlock_irqrestore(&mdp->lock, flags);
1840
1841 return ret;
1842}
1843
f08aff44
PR		 1844static int sh_eth_set_link_ksettings(struct net_device *ndev,
1845 const struct ethtool_link_ksettings *cmd)
dc19e4e5
NI		 1846{
1847 struct sh_eth_private *mdp = netdev_priv(ndev);
1848 unsigned long flags;
1849 int ret;
dc19e4e5 1850
9fd0375a 1851 if (!ndev->phydev)
4f9dce23
BH		 1852 return -ENODEV;
1853
dc19e4e5
NI		 1854 spin_lock_irqsave(&mdp->lock, flags);
1855
1856 /* disable tx and rx */
4a55530f 1857 sh_eth_rcv_snd_disable(ndev);
dc19e4e5 1858
f08aff44 1859 ret = phy_ethtool_ksettings_set(ndev->phydev, cmd);
dc19e4e5
NI		 1860 if (ret)
1861 goto error_exit;
1862
f08aff44 1863 if (cmd->base.duplex == DUPLEX_FULL)
dc19e4e5
NI		 1864 mdp->duplex = 1;
1865 else
1866 mdp->duplex = 0;
1867
1868 if (mdp->cd->set_duplex)
1869 mdp->cd->set_duplex(ndev);
1870
1871error_exit:
1872 mdelay(1);
1873
1874 /* enable tx and rx */
4a55530f 1875 sh_eth_rcv_snd_enable(ndev);
dc19e4e5
NI		 1876
1877 spin_unlock_irqrestore(&mdp->lock, flags);
1878
1879 return ret;
1880}
1881
6b4b4fea
BH		 1882/* If it is ever necessary to increase SH_ETH_REG_DUMP_MAX_REGS, the
1883 * version must be bumped as well. Just adding registers up to that
1884 * limit is fine, as long as the existing register indices don't
1885 * change.
1886 */
1887#define SH_ETH_REG_DUMP_VERSION 1
1888#define SH_ETH_REG_DUMP_MAX_REGS 256
1889
1890static size_t __sh_eth_get_regs(struct net_device *ndev, u32 *buf)
1891{
1892 struct sh_eth_private *mdp = netdev_priv(ndev);
1893 struct sh_eth_cpu_data *cd = mdp->cd;
1894 u32 *valid_map;
1895 size_t len;
1896
1897 BUILD_BUG_ON(SH_ETH_MAX_REGISTER_OFFSET > SH_ETH_REG_DUMP_MAX_REGS);
1898
1899 /* Dump starts with a bitmap that tells ethtool which
1900 * registers are defined for this chip.
1901 */
1902 len = DIV_ROUND_UP(SH_ETH_REG_DUMP_MAX_REGS, 32);
1903 if (buf) {
1904 valid_map = buf;
1905 buf += len;
1906 } else {
1907 valid_map = NULL;
1908 }
1909
1910 /* Add a register to the dump, if it has a defined offset.
1911 * This automatically skips most undefined registers, but for
1912 * some it is also necessary to check a capability flag in
1913 * struct sh_eth_cpu_data.
1914 */
1915#define mark_reg_valid(reg) valid_map[reg / 32] |= 1U << (reg % 32)
1916#define add_reg_from(reg, read_expr) do { \
1917 if (mdp->reg_offset[reg] != SH_ETH_OFFSET_INVALID) { \
1918 if (buf) { \
1919 mark_reg_valid(reg); \
1920 *buf++ = read_expr; \
1921 } \
1922 ++len; \
1923 } \
1924 } while (0)
1925#define add_reg(reg) add_reg_from(reg, sh_eth_read(ndev, reg))
1926#define add_tsu_reg(reg) add_reg_from(reg, sh_eth_tsu_read(mdp, reg))
1927
1928 add_reg(EDSR);
1929 add_reg(EDMR);
1930 add_reg(EDTRR);
1931 add_reg(EDRRR);
1932 add_reg(EESR);
1933 add_reg(EESIPR);
1934 add_reg(TDLAR);
1935 add_reg(TDFAR);
1936 add_reg(TDFXR);
1937 add_reg(TDFFR);
1938 add_reg(RDLAR);
1939 add_reg(RDFAR);
1940 add_reg(RDFXR);
1941 add_reg(RDFFR);
1942 add_reg(TRSCER);
1943 add_reg(RMFCR);
1944 add_reg(TFTR);
1945 add_reg(FDR);
1946 add_reg(RMCR);
1947 add_reg(TFUCR);
1948 add_reg(RFOCR);
1949 if (cd->rmiimode)
1950 add_reg(RMIIMODE);
1951 add_reg(FCFTR);
1952 if (cd->rpadir)
1953 add_reg(RPADIR);
1954 if (!cd->no_trimd)
1955 add_reg(TRIMD);
1956 add_reg(ECMR);
1957 add_reg(ECSR);
1958 add_reg(ECSIPR);
1959 add_reg(PIR);
1960 if (!cd->no_psr)
1961 add_reg(PSR);
1962 add_reg(RDMLR);
1963 add_reg(RFLR);
1964 add_reg(IPGR);
1965 if (cd->apr)
1966 add_reg(APR);
1967 if (cd->mpr)
1968 add_reg(MPR);
1969 add_reg(RFCR);
1970 add_reg(RFCF);
1971 if (cd->tpauser)
1972 add_reg(TPAUSER);
1973 add_reg(TPAUSECR);
1974 add_reg(GECMR);
1975 if (cd->bculr)
1976 add_reg(BCULR);
1977 add_reg(MAHR);
1978 add_reg(MALR);
1979 add_reg(TROCR);
1980 add_reg(CDCR);
1981 add_reg(LCCR);
1982 add_reg(CNDCR);
1983 add_reg(CEFCR);
1984 add_reg(FRECR);
1985 add_reg(TSFRCR);
1986 add_reg(TLFRCR);
1987 add_reg(CERCR);
1988 add_reg(CEECR);
1989 add_reg(MAFCR);
1990 if (cd->rtrate)
1991 add_reg(RTRATE);
1992 if (cd->hw_crc)
1993 add_reg(CSMR);
1994 if (cd->select_mii)
1995 add_reg(RMII_MII);
1996 add_reg(ARSTR);
1997 if (cd->tsu) {
1998 add_tsu_reg(TSU_CTRST);
1999 add_tsu_reg(TSU_FWEN0);
2000 add_tsu_reg(TSU_FWEN1);
2001 add_tsu_reg(TSU_FCM);
2002 add_tsu_reg(TSU_BSYSL0);
2003 add_tsu_reg(TSU_BSYSL1);
2004 add_tsu_reg(TSU_PRISL0);
2005 add_tsu_reg(TSU_PRISL1);
2006 add_tsu_reg(TSU_FWSL0);
2007 add_tsu_reg(TSU_FWSL1);
2008 add_tsu_reg(TSU_FWSLC);
2009 add_tsu_reg(TSU_QTAG0);
2010 add_tsu_reg(TSU_QTAG1);
2011 add_tsu_reg(TSU_QTAGM0);
2012 add_tsu_reg(TSU_QTAGM1);
2013 add_tsu_reg(TSU_FWSR);
2014 add_tsu_reg(TSU_FWINMK);
2015 add_tsu_reg(TSU_ADQT0);
2016 add_tsu_reg(TSU_ADQT1);
2017 add_tsu_reg(TSU_VTAG0);
2018 add_tsu_reg(TSU_VTAG1);
2019 add_tsu_reg(TSU_ADSBSY);
2020 add_tsu_reg(TSU_TEN);
2021 add_tsu_reg(TSU_POST1);
2022 add_tsu_reg(TSU_POST2);
2023 add_tsu_reg(TSU_POST3);
2024 add_tsu_reg(TSU_POST4);
2025 if (mdp->reg_offset[TSU_ADRH0] != SH_ETH_OFFSET_INVALID) {
2026 /* This is the start of a table, not just a single
2027 * register.
2028 */
2029 if (buf) {
2030 unsigned int i;
2031
2032 mark_reg_valid(TSU_ADRH0);
2033 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES * 2; i++)
2034 *buf++ = ioread32(
2035 mdp->tsu_addr +
2036 mdp->reg_offset[TSU_ADRH0] +
2037 i * 4);
2038 }
2039 len += SH_ETH_TSU_CAM_ENTRIES * 2;
2040 }
2041 }
2042
2043#undef mark_reg_valid
2044#undef add_reg_from
2045#undef add_reg
2046#undef add_tsu_reg
2047
2048 return len * 4;
2049}
2050
2051static int sh_eth_get_regs_len(struct net_device *ndev)
2052{
2053 return __sh_eth_get_regs(ndev, NULL);
2054}
2055
2056static void sh_eth_get_regs(struct net_device *ndev, struct ethtool_regs *regs,
2057 void *buf)
2058{
2059 struct sh_eth_private *mdp = netdev_priv(ndev);
2060
2061 regs->version = SH_ETH_REG_DUMP_VERSION;
2062
2063 pm_runtime_get_sync(&mdp->pdev->dev);
2064 __sh_eth_get_regs(ndev, buf);
2065 pm_runtime_put_sync(&mdp->pdev->dev);
2066}
2067
dc19e4e5
NI		 2068static int sh_eth_nway_reset(struct net_device *ndev)
2069{
2070 struct sh_eth_private *mdp = netdev_priv(ndev);
2071 unsigned long flags;
2072 int ret;
2073
9fd0375a 2074 if (!ndev->phydev)
4f9dce23
BH		 2075 return -ENODEV;
2076
dc19e4e5 2077 spin_lock_irqsave(&mdp->lock, flags);
9fd0375a 2078 ret = phy_start_aneg(ndev->phydev);
dc19e4e5
NI		 2079 spin_unlock_irqrestore(&mdp->lock, flags);
2080
2081 return ret;
2082}
2083
2084static u32 sh_eth_get_msglevel(struct net_device *ndev)
2085{
2086 struct sh_eth_private *mdp = netdev_priv(ndev);
2087 return mdp->msg_enable;
2088}
2089
2090static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
2091{
2092 struct sh_eth_private *mdp = netdev_priv(ndev);
2093 mdp->msg_enable = value;
2094}
2095
2096static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
2097 "rx_current", "tx_current",
2098 "rx_dirty", "tx_dirty",
2099};
2100#define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats)
2101
2102static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
2103{
2104 switch (sset) {
2105 case ETH_SS_STATS:
2106 return SH_ETH_STATS_LEN;
2107 default:
2108 return -EOPNOTSUPP;
2109 }
2110}
2111
2112static void sh_eth_get_ethtool_stats(struct net_device *ndev,
128296fc 2113 struct ethtool_stats *stats, u64 *data)
dc19e4e5
NI		 2114{
2115 struct sh_eth_private *mdp = netdev_priv(ndev);
2116 int i = 0;
2117
2118 /* device-specific stats */
2119 data[i++] = mdp->cur_rx;
2120 data[i++] = mdp->cur_tx;
2121 data[i++] = mdp->dirty_rx;
2122 data[i++] = mdp->dirty_tx;
2123}
2124
2125static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
2126{
2127 switch (stringset) {
2128 case ETH_SS_STATS:
2129 memcpy(data, *sh_eth_gstrings_stats,
128296fc 2130 sizeof(sh_eth_gstrings_stats));
dc19e4e5
NI		 2131 break;
2132 }
2133}
2134
525b8075
YS		 2135static void sh_eth_get_ringparam(struct net_device *ndev,
2136 struct ethtool_ringparam *ring)
2137{
2138 struct sh_eth_private *mdp = netdev_priv(ndev);
2139
2140 ring->rx_max_pending = RX_RING_MAX;
2141 ring->tx_max_pending = TX_RING_MAX;
2142 ring->rx_pending = mdp->num_rx_ring;
2143 ring->tx_pending = mdp->num_tx_ring;
2144}
2145
2146static int sh_eth_set_ringparam(struct net_device *ndev,
2147 struct ethtool_ringparam *ring)
2148{
2149 struct sh_eth_private *mdp = netdev_priv(ndev);
2150 int ret;
2151
2152 if (ring->tx_pending > TX_RING_MAX ||
2153 ring->rx_pending > RX_RING_MAX ||
2154 ring->tx_pending < TX_RING_MIN ||
2155 ring->rx_pending < RX_RING_MIN)
2156 return -EINVAL;
2157 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
2158 return -EINVAL;
2159
2160 if (netif_running(ndev)) {
bd888916 2161 netif_device_detach(ndev);
525b8075 2162 netif_tx_disable(ndev);
283e38db
BH		 2163
2164 /* Serialise with the interrupt handler and NAPI, then
2165 * disable interrupts. We have to clear the
2166 * irq_enabled flag first to ensure that interrupts
2167 * won't be re-enabled.
2168 */
2169 mdp->irq_enabled = false;
525b8075 2170 synchronize_irq(ndev->irq);
283e38db 2171 napi_synchronize(&mdp->napi);
525b8075 2172 sh_eth_write(ndev, 0x0000, EESIPR);
525b8075 2173
740c7f31 2174 sh_eth_dev_exit(ndev);
525b8075 2175
8e03a5e7 2176 /* Free all the skbuffs in the Rx queue and the DMA buffers. */
084236d8 2177 sh_eth_ring_free(ndev);
084236d8 2178 }
525b8075
YS		 2179
2180 /* Set new parameters */
2181 mdp->num_rx_ring = ring->rx_pending;
2182 mdp->num_tx_ring = ring->tx_pending;
2183
525b8075 2184 if (netif_running(ndev)) {
084236d8
BH		 2185 ret = sh_eth_ring_init(ndev);
2186 if (ret < 0) {
2187 netdev_err(ndev, "%s: sh_eth_ring_init failed.\n",
2188 __func__);
2189 return ret;
2190 }
f7967210 2191 ret = sh_eth_dev_init(ndev);
084236d8
BH		 2192 if (ret < 0) {
2193 netdev_err(ndev, "%s: sh_eth_dev_init failed.\n",
2194 __func__);
2195 return ret;
2196 }
2197
bd888916 2198 netif_device_attach(ndev);
525b8075
YS		 2199 }
2200
2201 return 0;
2202}
2203
9b07be4b 2204static const struct ethtool_ops sh_eth_ethtool_ops = {
6b4b4fea
BH		 2205 .get_regs_len = sh_eth_get_regs_len,
2206 .get_regs = sh_eth_get_regs,
9b07be4b 2207 .nway_reset = sh_eth_nway_reset,
dc19e4e5
NI		 2208 .get_msglevel = sh_eth_get_msglevel,
2209 .set_msglevel = sh_eth_set_msglevel,
9b07be4b 2210 .get_link = ethtool_op_get_link,
dc19e4e5
NI		 2211 .get_strings = sh_eth_get_strings,
2212 .get_ethtool_stats = sh_eth_get_ethtool_stats,
2213 .get_sset_count = sh_eth_get_sset_count,
525b8075
YS		 2214 .get_ringparam = sh_eth_get_ringparam,
2215 .set_ringparam = sh_eth_set_ringparam,
f08aff44
PR		 2216 .get_link_ksettings = sh_eth_get_link_ksettings,
2217 .set_link_ksettings = sh_eth_set_link_ksettings,
dc19e4e5
NI		 2218};
2219
86a74ff2
NI		 2220/* network device open function */
2221static int sh_eth_open(struct net_device *ndev)
2222{
86a74ff2 2223 struct sh_eth_private *mdp = netdev_priv(ndev);
4fa8c3cc 2224 int ret;
86a74ff2 2225
bcd5149d
MD		 2226 pm_runtime_get_sync(&mdp->pdev->dev);
2227
d2779e99
SS		 2228 napi_enable(&mdp->napi);
2229
a0607fd3 2230 ret = request_irq(ndev->irq, sh_eth_interrupt,
5b3dfd13 2231 mdp->cd->irq_flags, ndev->name, ndev);
86a74ff2 2232 if (ret) {
da246855 2233 netdev_err(ndev, "Can not assign IRQ number\n");
d2779e99 2234 goto out_napi_off;
86a74ff2
NI		 2235 }
2236
2237 /* Descriptor set */
2238 ret = sh_eth_ring_init(ndev);
2239 if (ret)
2240 goto out_free_irq;
2241
2242 /* device init */
f7967210 2243 ret = sh_eth_dev_init(ndev);
86a74ff2
NI		 2244 if (ret)
2245 goto out_free_irq;
2246
2247 /* PHY control start*/
2248 ret = sh_eth_phy_start(ndev);
2249 if (ret)
2250 goto out_free_irq;
2251
ad846aa5
SS		 2252 netif_start_queue(ndev);
2253
7fa2955f
MK		 2254 mdp->is_opened = 1;
2255
86a74ff2
NI		 2256 return ret;
2257
2258out_free_irq:
2259 free_irq(ndev->irq, ndev);
d2779e99
SS		 2260out_napi_off:
2261 napi_disable(&mdp->napi);
bcd5149d 2262 pm_runtime_put_sync(&mdp->pdev->dev);
86a74ff2
NI		 2263 return ret;
2264}
2265
2266/* Timeout function */
2267static void sh_eth_tx_timeout(struct net_device *ndev)
2268{
2269 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 2270 struct sh_eth_rxdesc *rxdesc;
2271 int i;
2272
2273 netif_stop_queue(ndev);
2274
8d5009f6
SS		 2275 netif_err(mdp, timer, ndev,
2276 "transmit timed out, status %8.8x, resetting...\n",
0799c2d6 2277 sh_eth_read(ndev, EESR));
86a74ff2
NI		 2278
2279 /* tx_errors count up */
bb7d92e3 2280 ndev->stats.tx_errors++;
86a74ff2 2281
86a74ff2 2282 /* Free all the skbuffs in the Rx queue. */
525b8075 2283 for (i = 0; i < mdp->num_rx_ring; i++) {
86a74ff2 2284 rxdesc = &mdp->rx_ring[i];
7cf72477
SS		 2285 rxdesc->status = cpu_to_le32(0);
2286 rxdesc->addr = cpu_to_le32(0xBADF00D0);
179d80af 2287 dev_kfree_skb(mdp->rx_skbuff[i]);
86a74ff2
NI		 2288 mdp->rx_skbuff[i] = NULL;
2289 }
525b8075 2290 for (i = 0; i < mdp->num_tx_ring; i++) {
179d80af 2291 dev_kfree_skb(mdp->tx_skbuff[i]);
86a74ff2
NI		 2292 mdp->tx_skbuff[i] = NULL;
2293 }
2294
2295 /* device init */
f7967210 2296 sh_eth_dev_init(ndev);
ad846aa5
SS		 2297
2298 netif_start_queue(ndev);
86a74ff2
NI		 2299}
2300
2301/* Packet transmit function */
2302static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
2303{
2304 struct sh_eth_private *mdp = netdev_priv(ndev);
2305 struct sh_eth_txdesc *txdesc;
1299653a 2306 dma_addr_t dma_addr;
86a74ff2 2307 u32 entry;
fb5e2f9b 2308 unsigned long flags;
86a74ff2
NI		 2309
2310 spin_lock_irqsave(&mdp->lock, flags);
525b8075 2311 if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
86a74ff2 2312 if (!sh_eth_txfree(ndev)) {
8d5009f6 2313 netif_warn(mdp, tx_queued, ndev, "TxFD exhausted.\n");
86a74ff2
NI		 2314 netif_stop_queue(ndev);
2315 spin_unlock_irqrestore(&mdp->lock, flags);
5b548140 2316 return NETDEV_TX_BUSY;
86a74ff2
NI		 2317 }
2318 }
2319 spin_unlock_irqrestore(&mdp->lock, flags);
2320
dacc73e0 2321 if (skb_put_padto(skb, ETH_ZLEN))
eebfb643
BH		 2322 return NETDEV_TX_OK;
2323
525b8075 2324 entry = mdp->cur_tx % mdp->num_tx_ring;
86a74ff2
NI		 2325 mdp->tx_skbuff[entry] = skb;
2326 txdesc = &mdp->tx_ring[entry];
86a74ff2 2327 /* soft swap. */
380af9e3 2328 if (!mdp->cd->hw_swap)
3e230993 2329 sh_eth_soft_swap(PTR_ALIGN(skb->data, 4), skb->len + 2);
1299653a
SS		 2330 dma_addr = dma_map_single(&ndev->dev, skb->data, skb->len,
2331 DMA_TO_DEVICE);
2332 if (dma_mapping_error(&ndev->dev, dma_addr)) {
aa3933b8
BH		 2333 kfree_skb(skb);
2334 return NETDEV_TX_OK;
2335 }
7cf72477
SS		 2336 txdesc->addr = cpu_to_le32(dma_addr);
2337 txdesc->len = cpu_to_le32(skb->len << 16);
86a74ff2 2338
f32bfb9a 2339 dma_wmb(); /* TACT bit must be set after all the above writes */
525b8075 2340 if (entry >= mdp->num_tx_ring - 1)
7cf72477 2341 txdesc->status |= cpu_to_le32(TD_TACT | TD_TDLE);
86a74ff2 2342 else
7cf72477 2343 txdesc->status |= cpu_to_le32(TD_TACT);
86a74ff2
NI		 2344
2345 mdp->cur_tx++;
2346
c5ed5368
YS		 2347 if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
2348 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
b0ca2a21 2349
6ed10654 2350 return NETDEV_TX_OK;
86a74ff2
NI		 2351}
2352
4398f9c8
BH		 2353/* The statistics registers have write-clear behaviour, which means we
2354 * will lose any increment between the read and write. We mitigate
2355 * this by only clearing when we read a non-zero value, so we will
2356 * never falsely report a total of zero.
2357 */
2358static void
2359sh_eth_update_stat(struct net_device *ndev, unsigned long *stat, int reg)
2360{
2361 u32 delta = sh_eth_read(ndev, reg);
2362
2363 if (delta) {
2364 *stat += delta;
2365 sh_eth_write(ndev, 0, reg);
2366 }
2367}
2368
7fa2955f
MK		 2369static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
2370{
2371 struct sh_eth_private *mdp = netdev_priv(ndev);
2372
2373 if (sh_eth_is_rz_fast_ether(mdp))
2374 return &ndev->stats;
2375
2376 if (!mdp->is_opened)
2377 return &ndev->stats;
2378
4398f9c8
BH		 2379 sh_eth_update_stat(ndev, &ndev->stats.tx_dropped, TROCR);
2380 sh_eth_update_stat(ndev, &ndev->stats.collisions, CDCR);
2381 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, LCCR);
7fa2955f
MK		 2382
2383 if (sh_eth_is_gether(mdp)) {
4398f9c8
BH		 2384 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2385 CERCR);
2386 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2387 CEECR);
7fa2955f 2388 } else {
4398f9c8
BH		 2389 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2390 CNDCR);
7fa2955f
MK		 2391 }
2392
2393 return &ndev->stats;
2394}
2395
86a74ff2
NI		 2396/* device close function */
2397static int sh_eth_close(struct net_device *ndev)
2398{
2399 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 2400
2401 netif_stop_queue(ndev);
2402
283e38db
BH		 2403 /* Serialise with the interrupt handler and NAPI, then disable
2404 * interrupts. We have to clear the irq_enabled flag first to
2405 * ensure that interrupts won't be re-enabled.
2406 */
2407 mdp->irq_enabled = false;
2408 synchronize_irq(ndev->irq);
2409 napi_disable(&mdp->napi);
4a55530f 2410 sh_eth_write(ndev, 0x0000, EESIPR);
86a74ff2 2411
740c7f31 2412 sh_eth_dev_exit(ndev);
86a74ff2
NI		 2413
2414 /* PHY Disconnect */
9fd0375a
PR		 2415 if (ndev->phydev) {
2416 phy_stop(ndev->phydev);
2417 phy_disconnect(ndev->phydev);
86a74ff2
NI		 2418 }
2419
2420 free_irq(ndev->irq, ndev);
2421
8e03a5e7 2422 /* Free all the skbuffs in the Rx queue and the DMA buffer. */
86a74ff2
NI		 2423 sh_eth_ring_free(ndev);
2424
bcd5149d
MD		 2425 pm_runtime_put_sync(&mdp->pdev->dev);
2426
7fa2955f 2427 mdp->is_opened = 0;
bcd5149d 2428
7fa2955f 2429 return 0;
86a74ff2
NI		 2430}
2431
bb7d92e3 2432/* ioctl to device function */
128296fc 2433static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
86a74ff2 2434{
9fd0375a 2435 struct phy_device *phydev = ndev->phydev;
86a74ff2
NI		 2436
2437 if (!netif_running(ndev))
2438 return -EINVAL;
2439
2440 if (!phydev)
2441 return -ENODEV;
2442
28b04113 2443 return phy_mii_ioctl(phydev, rq, cmd);
86a74ff2
NI		 2444}
2445
6743fe6d
YS		 2446/* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
2447static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp,
2448 int entry)
2449{
2450 return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4);
2451}
2452
2453static u32 sh_eth_tsu_get_post_mask(int entry)
2454{
2455 return 0x0f << (28 - ((entry % 8) * 4));
2456}
2457
2458static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
2459{
2460 return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
2461}
2462
2463static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
2464 int entry)
2465{
2466 struct sh_eth_private *mdp = netdev_priv(ndev);
2467 u32 tmp;
2468 void *reg_offset;
2469
2470 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2471 tmp = ioread32(reg_offset);
2472 iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset);
2473}
2474
2475static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
2476 int entry)
2477{
2478 struct sh_eth_private *mdp = netdev_priv(ndev);
2479 u32 post_mask, ref_mask, tmp;
2480 void *reg_offset;
2481
2482 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2483 post_mask = sh_eth_tsu_get_post_mask(entry);
2484 ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
2485
2486 tmp = ioread32(reg_offset);
2487 iowrite32(tmp & ~post_mask, reg_offset);
2488
2489 /* If other port enables, the function returns "true" */
2490 return tmp & ref_mask;
2491}
2492
2493static int sh_eth_tsu_busy(struct net_device *ndev)
2494{
2495 int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
2496 struct sh_eth_private *mdp = netdev_priv(ndev);
2497
2498 while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
2499 udelay(10);
2500 timeout--;
2501 if (timeout <= 0) {
da246855 2502 netdev_err(ndev, "%s: timeout\n", __func__);
6743fe6d
YS		 2503 return -ETIMEDOUT;
2504 }
2505 }
2506
2507 return 0;
2508}
2509
2510static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg,
2511 const u8 *addr)
2512{
2513 u32 val;
2514
2515 val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
2516 iowrite32(val, reg);
2517 if (sh_eth_tsu_busy(ndev) < 0)
2518 return -EBUSY;
2519
2520 val = addr[4] << 8 | addr[5];
2521 iowrite32(val, reg + 4);
2522 if (sh_eth_tsu_busy(ndev) < 0)
2523 return -EBUSY;
2524
2525 return 0;
2526}
2527
2528static void sh_eth_tsu_read_entry(void *reg, u8 *addr)
2529{
2530 u32 val;
2531
2532 val = ioread32(reg);
2533 addr[0] = (val >> 24) & 0xff;
2534 addr[1] = (val >> 16) & 0xff;
2535 addr[2] = (val >> 8) & 0xff;
2536 addr[3] = val & 0xff;
2537 val = ioread32(reg + 4);
2538 addr[4] = (val >> 8) & 0xff;
2539 addr[5] = val & 0xff;
2540}
2541
2542
2543static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
2544{
2545 struct sh_eth_private *mdp = netdev_priv(ndev);
2546 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2547 int i;
2548 u8 c_addr[ETH_ALEN];
2549
2550 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2551 sh_eth_tsu_read_entry(reg_offset, c_addr);
c4bde29c 2552 if (ether_addr_equal(addr, c_addr))
6743fe6d
YS		 2553 return i;
2554 }
2555
2556 return -ENOENT;
2557}
2558
2559static int sh_eth_tsu_find_empty(struct net_device *ndev)
2560{
2561 u8 blank[ETH_ALEN];
2562 int entry;
2563
2564 memset(blank, 0, sizeof(blank));
2565 entry = sh_eth_tsu_find_entry(ndev, blank);
2566 return (entry < 0) ? -ENOMEM : entry;
2567}
2568
2569static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
2570 int entry)
2571{
2572 struct sh_eth_private *mdp = netdev_priv(ndev);
2573 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2574 int ret;
2575 u8 blank[ETH_ALEN];
2576
2577 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
2578 ~(1 << (31 - entry)), TSU_TEN);
2579
2580 memset(blank, 0, sizeof(blank));
2581 ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
2582 if (ret < 0)
2583 return ret;
2584 return 0;
2585}
2586
2587static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
2588{
2589 struct sh_eth_private *mdp = netdev_priv(ndev);
2590 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2591 int i, ret;
2592
2593 if (!mdp->cd->tsu)
2594 return 0;
2595
2596 i = sh_eth_tsu_find_entry(ndev, addr);
2597 if (i < 0) {
2598 /* No entry found, create one */
2599 i = sh_eth_tsu_find_empty(ndev);
2600 if (i < 0)
2601 return -ENOMEM;
2602 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
2603 if (ret < 0)
2604 return ret;
2605
2606 /* Enable the entry */
2607 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
2608 (1 << (31 - i)), TSU_TEN);
2609 }
2610
2611 /* Entry found or created, enable POST */
2612 sh_eth_tsu_enable_cam_entry_post(ndev, i);
2613
2614 return 0;
2615}
2616
2617static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
2618{
2619 struct sh_eth_private *mdp = netdev_priv(ndev);
2620 int i, ret;
2621
2622 if (!mdp->cd->tsu)
2623 return 0;
2624
2625 i = sh_eth_tsu_find_entry(ndev, addr);
2626 if (i) {
2627 /* Entry found */
2628 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2629 goto done;
2630
2631 /* Disable the entry if both ports was disabled */
2632 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2633 if (ret < 0)
2634 return ret;
2635 }
2636done:
2637 return 0;
2638}
2639
2640static int sh_eth_tsu_purge_all(struct net_device *ndev)
2641{
2642 struct sh_eth_private *mdp = netdev_priv(ndev);
2643 int i, ret;
2644
b37feed7 2645 if (!mdp->cd->tsu)
6743fe6d
YS		 2646 return 0;
2647
2648 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
2649 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2650 continue;
2651
2652 /* Disable the entry if both ports was disabled */
2653 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2654 if (ret < 0)
2655 return ret;
2656 }
2657
2658 return 0;
2659}
2660
2661static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
2662{
2663 struct sh_eth_private *mdp = netdev_priv(ndev);
2664 u8 addr[ETH_ALEN];
2665 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2666 int i;
2667
b37feed7 2668 if (!mdp->cd->tsu)
6743fe6d
YS		 2669 return;
2670
2671 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2672 sh_eth_tsu_read_entry(reg_offset, addr);
2673 if (is_multicast_ether_addr(addr))
2674 sh_eth_tsu_del_entry(ndev, addr);
2675 }
2676}
2677
b37feed7
BH		 2678/* Update promiscuous flag and multicast filter */
2679static void sh_eth_set_rx_mode(struct net_device *ndev)
86a74ff2 2680{
6743fe6d
YS		 2681 struct sh_eth_private *mdp = netdev_priv(ndev);
2682 u32 ecmr_bits;
2683 int mcast_all = 0;
2684 unsigned long flags;
2685
2686 spin_lock_irqsave(&mdp->lock, flags);
128296fc 2687 /* Initial condition is MCT = 1, PRM = 0.
6743fe6d
YS		 2688 * Depending on ndev->flags, set PRM or clear MCT
2689 */
b37feed7
BH		 2690 ecmr_bits = sh_eth_read(ndev, ECMR) & ~ECMR_PRM;
2691 if (mdp->cd->tsu)
2692 ecmr_bits |= ECMR_MCT;
6743fe6d
YS		 2693
2694 if (!(ndev->flags & IFF_MULTICAST)) {
2695 sh_eth_tsu_purge_mcast(ndev);
2696 mcast_all = 1;
2697 }
2698 if (ndev->flags & IFF_ALLMULTI) {
2699 sh_eth_tsu_purge_mcast(ndev);
2700 ecmr_bits &= ~ECMR_MCT;
2701 mcast_all = 1;
2702 }
2703
86a74ff2 2704 if (ndev->flags & IFF_PROMISC) {
6743fe6d
YS		 2705 sh_eth_tsu_purge_all(ndev);
2706 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2707 } else if (mdp->cd->tsu) {
2708 struct netdev_hw_addr *ha;
2709 netdev_for_each_mc_addr(ha, ndev) {
2710 if (mcast_all && is_multicast_ether_addr(ha->addr))
2711 continue;
2712
2713 if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2714 if (!mcast_all) {
2715 sh_eth_tsu_purge_mcast(ndev);
2716 ecmr_bits &= ~ECMR_MCT;
2717 mcast_all = 1;
2718 }
2719 }
2720 }
86a74ff2 2721 }
6743fe6d
YS		 2722
2723 /* update the ethernet mode */
2724 sh_eth_write(ndev, ecmr_bits, ECMR);
2725
2726 spin_unlock_irqrestore(&mdp->lock, flags);
86a74ff2 2727}
71cc7c37
YS		 2728
2729static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2730{
2731 if (!mdp->port)
2732 return TSU_VTAG0;
2733 else
2734 return TSU_VTAG1;
2735}
2736
80d5c368
PM		 2737static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
2738 __be16 proto, u16 vid)
71cc7c37
YS		 2739{
2740 struct sh_eth_private *mdp = netdev_priv(ndev);
2741 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2742
2743 if (unlikely(!mdp->cd->tsu))
2744 return -EPERM;
2745
2746 /* No filtering if vid = 0 */
2747 if (!vid)
2748 return 0;
2749
2750 mdp->vlan_num_ids++;
2751
128296fc 2752 /* The controller has one VLAN tag HW filter. So, if the filter is
71cc7c37
YS		 2753 * already enabled, the driver disables it and the filte
2754 */
2755 if (mdp->vlan_num_ids > 1) {
2756 /* disable VLAN filter */
2757 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2758 return 0;
2759 }
2760
2761 sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
2762 vtag_reg_index);
2763
2764 return 0;
2765}
2766
80d5c368
PM		 2767static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
2768 __be16 proto, u16 vid)
71cc7c37
YS		 2769{
2770 struct sh_eth_private *mdp = netdev_priv(ndev);
2771 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2772
2773 if (unlikely(!mdp->cd->tsu))
2774 return -EPERM;
2775
2776 /* No filtering if vid = 0 */
2777 if (!vid)
2778 return 0;
2779
2780 mdp->vlan_num_ids--;
2781 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2782
2783 return 0;
2784}
86a74ff2
NI		 2785
2786/* SuperH's TSU register init function */
4a55530f 2787static void sh_eth_tsu_init(struct sh_eth_private *mdp)
86a74ff2 2788{
db893473
SH		 2789 if (sh_eth_is_rz_fast_ether(mdp)) {
2790 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
e1487888
CB		 2791 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL,
2792 TSU_FWSLC); /* Enable POST registers */
db893473
SH		 2793 return;
2794 }
2795
4a55530f
YS		 2796 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */
2797 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */
2798 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */
2799 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
2800 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
2801 sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
2802 sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
2803 sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
2804 sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
2805 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
c5ed5368
YS		 2806 if (sh_eth_is_gether(mdp)) {
2807 sh_eth_tsu_write(mdp, 0, TSU_QTAG0); /* Disable QTAG(0->1) */
2808 sh_eth_tsu_write(mdp, 0, TSU_QTAG1); /* Disable QTAG(1->0) */
2809 } else {
2810 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */
2811 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */
2812 }
4a55530f
YS		 2813 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */
2814 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */
2815 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2816 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */
2817 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */
2818 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */
2819 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */
86a74ff2
NI		 2820}
2821
2822/* MDIO bus release function */
bd920ff5 2823static int sh_mdio_release(struct sh_eth_private *mdp)
86a74ff2 2824{
86a74ff2 2825 /* unregister mdio bus */
bd920ff5 2826 mdiobus_unregister(mdp->mii_bus);
86a74ff2
NI		 2827
2828 /* free bitbang info */
bd920ff5 2829 free_mdio_bitbang(mdp->mii_bus);
86a74ff2
NI		 2830
2831 return 0;
2832}
2833
2834/* MDIO bus init function */
bd920ff5 2835static int sh_mdio_init(struct sh_eth_private *mdp,
b3017e6a 2836 struct sh_eth_plat_data *pd)
86a74ff2 2837{
e7f4dc35 2838 int ret;
86a74ff2 2839 struct bb_info *bitbang;
bd920ff5 2840 struct platform_device *pdev = mdp->pdev;
aa8d4225 2841 struct device *dev = &mdp->pdev->dev;
86a74ff2
NI		 2842
2843 /* create bit control struct for PHY */
aa8d4225 2844 bitbang = devm_kzalloc(dev, sizeof(struct bb_info), GFP_KERNEL);
f738a13d
LP		 2845 if (!bitbang)
2846 return -ENOMEM;
86a74ff2
NI		 2847
2848 /* bitbang init */
ae70644d 2849 bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
b3017e6a 2850 bitbang->set_gate = pd->set_mdio_gate;
86a74ff2
NI		 2851 bitbang->ctrl.ops = &bb_ops;
2852
c2e07b3a 2853 /* MII controller setting */
86a74ff2 2854 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
f738a13d
LP		 2855 if (!mdp->mii_bus)
2856 return -ENOMEM;
86a74ff2
NI		 2857
2858 /* Hook up MII support for ethtool */
2859 mdp->mii_bus->name = "sh_mii";
a5bd6060 2860 mdp->mii_bus->parent = dev;
5278fb54 2861 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
bd920ff5 2862 pdev->name, pdev->id);
86a74ff2 2863
bd920ff5
LP		 2864 /* register MDIO bus */
2865 if (dev->of_node) {
2866 ret = of_mdiobus_register(mdp->mii_bus, dev->of_node);
702eca02 2867 } else {
702eca02
BD		 2868 if (pd->phy_irq > 0)
2869 mdp->mii_bus->irq[pd->phy] = pd->phy_irq;
2870
2871 ret = mdiobus_register(mdp->mii_bus);
2872 }
2873
86a74ff2 2874 if (ret)
d5e07e69 2875 goto out_free_bus;
86a74ff2 2876
86a74ff2
NI		 2877 return 0;
2878
86a74ff2 2879out_free_bus:
298cf9be 2880 free_mdio_bitbang(mdp->mii_bus);
86a74ff2
NI		 2881 return ret;
2882}
2883
4a55530f
YS		 2884static const u16 *sh_eth_get_register_offset(int register_type)
2885{
2886 const u16 *reg_offset = NULL;
2887
2888 switch (register_type) {
2889 case SH_ETH_REG_GIGABIT:
2890 reg_offset = sh_eth_offset_gigabit;
2891 break;
db893473
SH		 2892 case SH_ETH_REG_FAST_RZ:
2893 reg_offset = sh_eth_offset_fast_rz;
2894 break;
a3f109bd
SS		 2895 case SH_ETH_REG_FAST_RCAR:
2896 reg_offset = sh_eth_offset_fast_rcar;
2897 break;
4a55530f
YS		 2898 case SH_ETH_REG_FAST_SH4:
2899 reg_offset = sh_eth_offset_fast_sh4;
2900 break;
2901 case SH_ETH_REG_FAST_SH3_SH2:
2902 reg_offset = sh_eth_offset_fast_sh3_sh2;
2903 break;
4a55530f
YS		 2904 }
2905
2906 return reg_offset;
2907}
2908
8f728d79 2909static const struct net_device_ops sh_eth_netdev_ops = {
ebf84eaa
AB		 2910 .ndo_open = sh_eth_open,
2911 .ndo_stop = sh_eth_close,
2912 .ndo_start_xmit = sh_eth_start_xmit,
2913 .ndo_get_stats = sh_eth_get_stats,
b37feed7 2914 .ndo_set_rx_mode = sh_eth_set_rx_mode,
ebf84eaa
AB		 2915 .ndo_tx_timeout = sh_eth_tx_timeout,
2916 .ndo_do_ioctl = sh_eth_do_ioctl,
2917 .ndo_validate_addr = eth_validate_addr,
2918 .ndo_set_mac_address = eth_mac_addr,
ebf84eaa
AB		 2919};
2920
8f728d79
SS		 2921static const struct net_device_ops sh_eth_netdev_ops_tsu = {
2922 .ndo_open = sh_eth_open,
2923 .ndo_stop = sh_eth_close,
2924 .ndo_start_xmit = sh_eth_start_xmit,
2925 .ndo_get_stats = sh_eth_get_stats,
b37feed7 2926 .ndo_set_rx_mode = sh_eth_set_rx_mode,
8f728d79
SS		 2927 .ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid,
2928 .ndo_vlan_rx_kill_vid = sh_eth_vlan_rx_kill_vid,
2929 .ndo_tx_timeout = sh_eth_tx_timeout,
2930 .ndo_do_ioctl = sh_eth_do_ioctl,
2931 .ndo_validate_addr = eth_validate_addr,
2932 .ndo_set_mac_address = eth_mac_addr,
8f728d79
SS		 2933};
2934
b356e978
SS		 2935#ifdef CONFIG_OF
2936static struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
2937{
2938 struct device_node *np = dev->of_node;
2939 struct sh_eth_plat_data *pdata;
b356e978
SS		 2940 const char *mac_addr;
2941
2942 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
2943 if (!pdata)
2944 return NULL;
2945
2946 pdata->phy_interface = of_get_phy_mode(np);
2947
b356e978
SS		 2948 mac_addr = of_get_mac_address(np);
2949 if (mac_addr)
2950 memcpy(pdata->mac_addr, mac_addr, ETH_ALEN);
2951
2952 pdata->no_ether_link =
2953 of_property_read_bool(np, "renesas,no-ether-link");
2954 pdata->ether_link_active_low =
2955 of_property_read_bool(np, "renesas,ether-link-active-low");
2956
2957 return pdata;
2958}
2959
2960static const struct of_device_id sh_eth_match_table[] = {
2961 { .compatible = "renesas,gether-r8a7740", .data = &r8a7740_data },
c099ff3c
SS		 2962 { .compatible = "renesas,ether-r8a7743", .data = &r8a779x_data },
2963 { .compatible = "renesas,ether-r8a7745", .data = &r8a779x_data },
b356e978
SS		 2964 { .compatible = "renesas,ether-r8a7778", .data = &r8a777x_data },
2965 { .compatible = "renesas,ether-r8a7779", .data = &r8a777x_data },
2966 { .compatible = "renesas,ether-r8a7790", .data = &r8a779x_data },
2967 { .compatible = "renesas,ether-r8a7791", .data = &r8a779x_data },
9488e1e5 2968 { .compatible = "renesas,ether-r8a7793", .data = &r8a779x_data },
0f76b9d8 2969 { .compatible = "renesas,ether-r8a7794", .data = &r8a779x_data },
b356e978
SS		 2970 { .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data },
2971 { }
2972};
2973MODULE_DEVICE_TABLE(of, sh_eth_match_table);
2974#else
2975static inline struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
2976{
2977 return NULL;
2978}
2979#endif
2980
86a74ff2
NI		 2981static int sh_eth_drv_probe(struct platform_device *pdev)
2982{
86a74ff2 2983 struct resource *res;
0b76b862 2984 struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev);
afe391ad 2985 const struct platform_device_id *id = platform_get_device_id(pdev);
4fa8c3cc
SS		 2986 struct sh_eth_private *mdp;
2987 struct net_device *ndev;
2988 int ret, devno;
86a74ff2
NI		 2989
2990 /* get base addr */
2991 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
86a74ff2
NI		 2992
2993 ndev = alloc_etherdev(sizeof(struct sh_eth_private));
f738a13d
LP		 2994 if (!ndev)
2995 return -ENOMEM;
86a74ff2 2996
b5893a08
BD		 2997 pm_runtime_enable(&pdev->dev);
2998 pm_runtime_get_sync(&pdev->dev);
2999
86a74ff2
NI		 3000 devno = pdev->id;
3001 if (devno < 0)
3002 devno = 0;
3003
cc3c080d 3004 ret = platform_get_irq(pdev, 0);
7a468ac6 3005 if (ret < 0)
86a74ff2 3006 goto out_release;
cc3c080d 3007 ndev->irq = ret;
86a74ff2
NI		 3008
3009 SET_NETDEV_DEV(ndev, &pdev->dev);
3010
86a74ff2 3011 mdp = netdev_priv(ndev);
525b8075
YS		 3012 mdp->num_tx_ring = TX_RING_SIZE;
3013 mdp->num_rx_ring = RX_RING_SIZE;
d5e07e69
SS		 3014 mdp->addr = devm_ioremap_resource(&pdev->dev, res);
3015 if (IS_ERR(mdp->addr)) {
3016 ret = PTR_ERR(mdp->addr);
ae70644d
YS		 3017 goto out_release;
3018 }
3019
c960804f
VB		 3020 ndev->base_addr = res->start;
3021
86a74ff2 3022 spin_lock_init(&mdp->lock);
bcd5149d 3023 mdp->pdev = pdev;
86a74ff2 3024
b356e978
SS		 3025 if (pdev->dev.of_node)
3026 pd = sh_eth_parse_dt(&pdev->dev);
3b4c5cbf
SS		 3027 if (!pd) {
3028 dev_err(&pdev->dev, "no platform data\n");
3029 ret = -EINVAL;
3030 goto out_release;
3031 }
3032
86a74ff2 3033 /* get PHY ID */
71557a37 3034 mdp->phy_id = pd->phy;
e47c9052 3035 mdp->phy_interface = pd->phy_interface;
4923576b
YS		 3036 mdp->no_ether_link = pd->no_ether_link;
3037 mdp->ether_link_active_low = pd->ether_link_active_low;
86a74ff2 3038
380af9e3 3039 /* set cpu data */
42a67c9b 3040 if (id)
b356e978 3041 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data;
42a67c9b
WS		 3042 else
3043 mdp->cd = (struct sh_eth_cpu_data *)of_device_get_match_data(&pdev->dev);
b356e978 3044
a3153d8c 3045 mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type);
264be2f5
SS		 3046 if (!mdp->reg_offset) {
3047 dev_err(&pdev->dev, "Unknown register type (%d)\n",
3048 mdp->cd->register_type);
3049 ret = -EINVAL;
3050 goto out_release;
3051 }
380af9e3
YS		 3052 sh_eth_set_default_cpu_data(mdp->cd);
3053
86a74ff2 3054 /* set function */
8f728d79
SS		 3055 if (mdp->cd->tsu)
3056 ndev->netdev_ops = &sh_eth_netdev_ops_tsu;
3057 else
3058 ndev->netdev_ops = &sh_eth_netdev_ops;
7ad24ea4 3059 ndev->ethtool_ops = &sh_eth_ethtool_ops;
86a74ff2
NI		 3060 ndev->watchdog_timeo = TX_TIMEOUT;
3061
dc19e4e5
NI		 3062 /* debug message level */
3063 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
86a74ff2
NI		 3064
3065 /* read and set MAC address */
748031f9 3066 read_mac_address(ndev, pd->mac_addr);
ff6e7228
SS		 3067 if (!is_valid_ether_addr(ndev->dev_addr)) {
3068 dev_warn(&pdev->dev,
3069 "no valid MAC address supplied, using a random one.\n");
3070 eth_hw_addr_random(ndev);
3071 }
86a74ff2 3072
6ba88021
YS		 3073 /* ioremap the TSU registers */
3074 if (mdp->cd->tsu) {
3075 struct resource *rtsu;
3076 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
d5e07e69
SS		 3077 mdp->tsu_addr = devm_ioremap_resource(&pdev->dev, rtsu);
3078 if (IS_ERR(mdp->tsu_addr)) {
3079 ret = PTR_ERR(mdp->tsu_addr);
fc0c0900
SS		 3080 goto out_release;
3081 }
6743fe6d 3082 mdp->port = devno % 2;
f646968f 3083 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER;
6ba88021
YS		 3084 }
3085
150647fb
YS		 3086 /* initialize first or needed device */
3087 if (!devno || pd->needs_init) {
380af9e3
YS		 3088 if (mdp->cd->chip_reset)
3089 mdp->cd->chip_reset(ndev);
86a74ff2 3090
4986b996
YS		 3091 if (mdp->cd->tsu) {
3092 /* TSU init (Init only)*/
3093 sh_eth_tsu_init(mdp);
3094 }
86a74ff2
NI		 3095 }
3096
966d6dbb
HN		 3097 if (mdp->cd->rmiimode)
3098 sh_eth_write(ndev, 0x1, RMIIMODE);
3099
daacf03f
LP		 3100 /* MDIO bus init */
3101 ret = sh_mdio_init(mdp, pd);
3102 if (ret) {
3103 dev_err(&ndev->dev, "failed to initialise MDIO\n");
3104 goto out_release;
3105 }
3106
3719109d
SS		 3107 netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64);
3108
86a74ff2
NI		 3109 /* network device register */
3110 ret = register_netdev(ndev);
3111 if (ret)
3719109d 3112 goto out_napi_del;
86a74ff2 3113
25985edc 3114 /* print device information */
f75f14ec
SS		 3115 netdev_info(ndev, "Base address at 0x%x, %pM, IRQ %d.\n",
3116 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
86a74ff2 3117
b5893a08 3118 pm_runtime_put(&pdev->dev);
86a74ff2
NI		 3119 platform_set_drvdata(pdev, ndev);
3120
3121 return ret;
3122
3719109d
SS		 3123out_napi_del:
3124 netif_napi_del(&mdp->napi);
daacf03f 3125 sh_mdio_release(mdp);
3719109d 3126
86a74ff2
NI		 3127out_release:
3128 /* net_dev free */
3129 if (ndev)
3130 free_netdev(ndev);
3131
b5893a08
BD		 3132 pm_runtime_put(&pdev->dev);
3133 pm_runtime_disable(&pdev->dev);
86a74ff2
NI		 3134 return ret;
3135}
3136
3137static int sh_eth_drv_remove(struct platform_device *pdev)
3138{
3139 struct net_device *ndev = platform_get_drvdata(pdev);
3719109d 3140 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2 3141
86a74ff2 3142 unregister_netdev(ndev);
3719109d 3143 netif_napi_del(&mdp->napi);
daacf03f 3144 sh_mdio_release(mdp);
bcd5149d 3145 pm_runtime_disable(&pdev->dev);
86a74ff2 3146 free_netdev(ndev);
86a74ff2
NI		 3147
3148 return 0;
3149}
3150
540ad1b8 3151#ifdef CONFIG_PM
b71af046
MU		 3152#ifdef CONFIG_PM_SLEEP
3153static int sh_eth_suspend(struct device *dev)
3154{
3155 struct net_device *ndev = dev_get_drvdata(dev);
3156 int ret = 0;
3157
3158 if (netif_running(ndev)) {
3159 netif_device_detach(ndev);
3160 ret = sh_eth_close(ndev);
3161 }
3162
3163 return ret;
3164}
3165
3166static int sh_eth_resume(struct device *dev)
3167{
3168 struct net_device *ndev = dev_get_drvdata(dev);
3169 int ret = 0;
3170
3171 if (netif_running(ndev)) {
3172 ret = sh_eth_open(ndev);
3173 if (ret < 0)
3174 return ret;
3175 netif_device_attach(ndev);
3176 }
3177
3178 return ret;
3179}
3180#endif
3181
bcd5149d
MD		 3182static int sh_eth_runtime_nop(struct device *dev)
3183{
128296fc 3184 /* Runtime PM callback shared between ->runtime_suspend()
bcd5149d
MD		 3185 * and ->runtime_resume(). Simply returns success.
3186 *
3187 * This driver re-initializes all registers after
3188 * pm_runtime_get_sync() anyway so there is no need
3189 * to save and restore registers here.
3190 */
3191 return 0;
3192}
3193
540ad1b8 3194static const struct dev_pm_ops sh_eth_dev_pm_ops = {
b71af046 3195 SET_SYSTEM_SLEEP_PM_OPS(sh_eth_suspend, sh_eth_resume)
e7d7e898 3196 SET_RUNTIME_PM_OPS(sh_eth_runtime_nop, sh_eth_runtime_nop, NULL)
bcd5149d 3197};
540ad1b8
NI		 3198#define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
3199#else
3200#define SH_ETH_PM_OPS NULL
3201#endif
bcd5149d 3202
afe391ad 3203static struct platform_device_id sh_eth_id_table[] = {
c18a79ab 3204 { "sh7619-ether", (kernel_ulong_t)&sh7619_data },
7bbe150d 3205 { "sh771x-ether", (kernel_ulong_t)&sh771x_data },
9c3beaab 3206 { "sh7724-ether", (kernel_ulong_t)&sh7724_data },
f5d12767 3207 { "sh7734-gether", (kernel_ulong_t)&sh7734_data },
24549e2a
SS		 3208 { "sh7757-ether", (kernel_ulong_t)&sh7757_data },
3209 { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga },
f5d12767 3210 { "sh7763-gether", (kernel_ulong_t)&sh7763_data },
afe391ad
SS		 3211 { }
3212};
3213MODULE_DEVICE_TABLE(platform, sh_eth_id_table);
3214
86a74ff2
NI		 3215static struct platform_driver sh_eth_driver = {
3216 .probe = sh_eth_drv_probe,
3217 .remove = sh_eth_drv_remove,
afe391ad 3218 .id_table = sh_eth_id_table,
86a74ff2
NI		 3219 .driver = {
3220 .name = CARDNAME,
540ad1b8 3221 .pm = SH_ETH_PM_OPS,
b356e978 3222 .of_match_table = of_match_ptr(sh_eth_match_table),
86a74ff2
NI		 3223 },
3224};
3225
db62f684 3226module_platform_driver(sh_eth_driver);
86a74ff2
NI		 3227
3228MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
3229MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
3230MODULE_LICENSE("GPL v2");
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