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SolutionEngine7724: fix Ether support
[mirror_ubuntu-jammy-kernel.git] / drivers / net / ethernet / renesas / sh_eth.c
CommitLineData
86a74ff2
NI		 1/*
2 * SuperH Ethernet device driver
3 *
f0e81fec 4 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu
a3f109bd
SS		 5 * Copyright (C) 2008-2013 Renesas Solutions Corp.
6 * Copyright (C) 2013 Cogent Embedded, Inc.
86a74ff2
NI		 7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 * You should have received a copy of the GNU General Public License along with
17 * this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * The full GNU General Public License is included in this distribution in
21 * the file called "COPYING".
22 */
23
86a74ff2 24#include <linux/init.h>
0654011d
YS		 25#include <linux/module.h>
26#include <linux/kernel.h>
27#include <linux/spinlock.h>
6a27cded 28#include <linux/interrupt.h>
86a74ff2
NI		 29#include <linux/dma-mapping.h>
30#include <linux/etherdevice.h>
31#include <linux/delay.h>
32#include <linux/platform_device.h>
33#include <linux/mdio-bitbang.h>
34#include <linux/netdevice.h>
35#include <linux/phy.h>
36#include <linux/cache.h>
37#include <linux/io.h>
bcd5149d 38#include <linux/pm_runtime.h>
5a0e3ad6 39#include <linux/slab.h>
dc19e4e5 40#include <linux/ethtool.h>
fdb37a7f 41#include <linux/if_vlan.h>
f0e81fec 42#include <linux/clk.h>
d4fa0e35 43#include <linux/sh_eth.h>
86a74ff2
NI		 44
45#include "sh_eth.h"
46
dc19e4e5
NI		 47#define SH_ETH_DEF_MSG_ENABLE \
48 (NETIF_MSG_LINK | \
49 NETIF_MSG_TIMER | \
50 NETIF_MSG_RX_ERR| \
51 NETIF_MSG_TX_ERR)
52
c0013f6f
SS		 53static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
54 [EDSR] = 0x0000,
55 [EDMR] = 0x0400,
56 [EDTRR] = 0x0408,
57 [EDRRR] = 0x0410,
58 [EESR] = 0x0428,
59 [EESIPR] = 0x0430,
60 [TDLAR] = 0x0010,
61 [TDFAR] = 0x0014,
62 [TDFXR] = 0x0018,
63 [TDFFR] = 0x001c,
64 [RDLAR] = 0x0030,
65 [RDFAR] = 0x0034,
66 [RDFXR] = 0x0038,
67 [RDFFR] = 0x003c,
68 [TRSCER] = 0x0438,
69 [RMFCR] = 0x0440,
70 [TFTR] = 0x0448,
71 [FDR] = 0x0450,
72 [RMCR] = 0x0458,
73 [RPADIR] = 0x0460,
74 [FCFTR] = 0x0468,
75 [CSMR] = 0x04E4,
76
77 [ECMR] = 0x0500,
78 [ECSR] = 0x0510,
79 [ECSIPR] = 0x0518,
80 [PIR] = 0x0520,
81 [PSR] = 0x0528,
82 [PIPR] = 0x052c,
83 [RFLR] = 0x0508,
84 [APR] = 0x0554,
85 [MPR] = 0x0558,
86 [PFTCR] = 0x055c,
87 [PFRCR] = 0x0560,
88 [TPAUSER] = 0x0564,
89 [GECMR] = 0x05b0,
90 [BCULR] = 0x05b4,
91 [MAHR] = 0x05c0,
92 [MALR] = 0x05c8,
93 [TROCR] = 0x0700,
94 [CDCR] = 0x0708,
95 [LCCR] = 0x0710,
96 [CEFCR] = 0x0740,
97 [FRECR] = 0x0748,
98 [TSFRCR] = 0x0750,
99 [TLFRCR] = 0x0758,
100 [RFCR] = 0x0760,
101 [CERCR] = 0x0768,
102 [CEECR] = 0x0770,
103 [MAFCR] = 0x0778,
104 [RMII_MII] = 0x0790,
105
106 [ARSTR] = 0x0000,
107 [TSU_CTRST] = 0x0004,
108 [TSU_FWEN0] = 0x0010,
109 [TSU_FWEN1] = 0x0014,
110 [TSU_FCM] = 0x0018,
111 [TSU_BSYSL0] = 0x0020,
112 [TSU_BSYSL1] = 0x0024,
113 [TSU_PRISL0] = 0x0028,
114 [TSU_PRISL1] = 0x002c,
115 [TSU_FWSL0] = 0x0030,
116 [TSU_FWSL1] = 0x0034,
117 [TSU_FWSLC] = 0x0038,
118 [TSU_QTAG0] = 0x0040,
119 [TSU_QTAG1] = 0x0044,
120 [TSU_FWSR] = 0x0050,
121 [TSU_FWINMK] = 0x0054,
122 [TSU_ADQT0] = 0x0048,
123 [TSU_ADQT1] = 0x004c,
124 [TSU_VTAG0] = 0x0058,
125 [TSU_VTAG1] = 0x005c,
126 [TSU_ADSBSY] = 0x0060,
127 [TSU_TEN] = 0x0064,
128 [TSU_POST1] = 0x0070,
129 [TSU_POST2] = 0x0074,
130 [TSU_POST3] = 0x0078,
131 [TSU_POST4] = 0x007c,
132 [TSU_ADRH0] = 0x0100,
133 [TSU_ADRL0] = 0x0104,
134 [TSU_ADRH31] = 0x01f8,
135 [TSU_ADRL31] = 0x01fc,
136
137 [TXNLCR0] = 0x0080,
138 [TXALCR0] = 0x0084,
139 [RXNLCR0] = 0x0088,
140 [RXALCR0] = 0x008c,
141 [FWNLCR0] = 0x0090,
142 [FWALCR0] = 0x0094,
143 [TXNLCR1] = 0x00a0,
144 [TXALCR1] = 0x00a0,
145 [RXNLCR1] = 0x00a8,
146 [RXALCR1] = 0x00ac,
147 [FWNLCR1] = 0x00b0,
148 [FWALCR1] = 0x00b4,
149};
150
a3f109bd
SS		 151static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
152 [ECMR] = 0x0300,
153 [RFLR] = 0x0308,
154 [ECSR] = 0x0310,
155 [ECSIPR] = 0x0318,
156 [PIR] = 0x0320,
157 [PSR] = 0x0328,
158 [RDMLR] = 0x0340,
159 [IPGR] = 0x0350,
160 [APR] = 0x0354,
161 [MPR] = 0x0358,
162 [RFCF] = 0x0360,
163 [TPAUSER] = 0x0364,
164 [TPAUSECR] = 0x0368,
165 [MAHR] = 0x03c0,
166 [MALR] = 0x03c8,
167 [TROCR] = 0x03d0,
168 [CDCR] = 0x03d4,
169 [LCCR] = 0x03d8,
170 [CNDCR] = 0x03dc,
171 [CEFCR] = 0x03e4,
172 [FRECR] = 0x03e8,
173 [TSFRCR] = 0x03ec,
174 [TLFRCR] = 0x03f0,
175 [RFCR] = 0x03f4,
176 [MAFCR] = 0x03f8,
177
178 [EDMR] = 0x0200,
179 [EDTRR] = 0x0208,
180 [EDRRR] = 0x0210,
181 [TDLAR] = 0x0218,
182 [RDLAR] = 0x0220,
183 [EESR] = 0x0228,
184 [EESIPR] = 0x0230,
185 [TRSCER] = 0x0238,
186 [RMFCR] = 0x0240,
187 [TFTR] = 0x0248,
188 [FDR] = 0x0250,
189 [RMCR] = 0x0258,
190 [TFUCR] = 0x0264,
191 [RFOCR] = 0x0268,
55754f19 192 [RMIIMODE] = 0x026c,
a3f109bd
SS		 193 [FCFTR] = 0x0270,
194 [TRIMD] = 0x027c,
195};
196
c0013f6f
SS		 197static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
198 [ECMR] = 0x0100,
199 [RFLR] = 0x0108,
200 [ECSR] = 0x0110,
201 [ECSIPR] = 0x0118,
202 [PIR] = 0x0120,
203 [PSR] = 0x0128,
204 [RDMLR] = 0x0140,
205 [IPGR] = 0x0150,
206 [APR] = 0x0154,
207 [MPR] = 0x0158,
208 [TPAUSER] = 0x0164,
209 [RFCF] = 0x0160,
210 [TPAUSECR] = 0x0168,
211 [BCFRR] = 0x016c,
212 [MAHR] = 0x01c0,
213 [MALR] = 0x01c8,
214 [TROCR] = 0x01d0,
215 [CDCR] = 0x01d4,
216 [LCCR] = 0x01d8,
217 [CNDCR] = 0x01dc,
218 [CEFCR] = 0x01e4,
219 [FRECR] = 0x01e8,
220 [TSFRCR] = 0x01ec,
221 [TLFRCR] = 0x01f0,
222 [RFCR] = 0x01f4,
223 [MAFCR] = 0x01f8,
224 [RTRATE] = 0x01fc,
225
226 [EDMR] = 0x0000,
227 [EDTRR] = 0x0008,
228 [EDRRR] = 0x0010,
229 [TDLAR] = 0x0018,
230 [RDLAR] = 0x0020,
231 [EESR] = 0x0028,
232 [EESIPR] = 0x0030,
233 [TRSCER] = 0x0038,
234 [RMFCR] = 0x0040,
235 [TFTR] = 0x0048,
236 [FDR] = 0x0050,
237 [RMCR] = 0x0058,
238 [TFUCR] = 0x0064,
239 [RFOCR] = 0x0068,
240 [FCFTR] = 0x0070,
241 [RPADIR] = 0x0078,
242 [TRIMD] = 0x007c,
243 [RBWAR] = 0x00c8,
244 [RDFAR] = 0x00cc,
245 [TBRAR] = 0x00d4,
246 [TDFAR] = 0x00d8,
247};
248
249static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
250 [ECMR] = 0x0160,
251 [ECSR] = 0x0164,
252 [ECSIPR] = 0x0168,
253 [PIR] = 0x016c,
254 [MAHR] = 0x0170,
255 [MALR] = 0x0174,
256 [RFLR] = 0x0178,
257 [PSR] = 0x017c,
258 [TROCR] = 0x0180,
259 [CDCR] = 0x0184,
260 [LCCR] = 0x0188,
261 [CNDCR] = 0x018c,
262 [CEFCR] = 0x0194,
263 [FRECR] = 0x0198,
264 [TSFRCR] = 0x019c,
265 [TLFRCR] = 0x01a0,
266 [RFCR] = 0x01a4,
267 [MAFCR] = 0x01a8,
268 [IPGR] = 0x01b4,
269 [APR] = 0x01b8,
270 [MPR] = 0x01bc,
271 [TPAUSER] = 0x01c4,
272 [BCFR] = 0x01cc,
273
274 [ARSTR] = 0x0000,
275 [TSU_CTRST] = 0x0004,
276 [TSU_FWEN0] = 0x0010,
277 [TSU_FWEN1] = 0x0014,
278 [TSU_FCM] = 0x0018,
279 [TSU_BSYSL0] = 0x0020,
280 [TSU_BSYSL1] = 0x0024,
281 [TSU_PRISL0] = 0x0028,
282 [TSU_PRISL1] = 0x002c,
283 [TSU_FWSL0] = 0x0030,
284 [TSU_FWSL1] = 0x0034,
285 [TSU_FWSLC] = 0x0038,
286 [TSU_QTAGM0] = 0x0040,
287 [TSU_QTAGM1] = 0x0044,
288 [TSU_ADQT0] = 0x0048,
289 [TSU_ADQT1] = 0x004c,
290 [TSU_FWSR] = 0x0050,
291 [TSU_FWINMK] = 0x0054,
292 [TSU_ADSBSY] = 0x0060,
293 [TSU_TEN] = 0x0064,
294 [TSU_POST1] = 0x0070,
295 [TSU_POST2] = 0x0074,
296 [TSU_POST3] = 0x0078,
297 [TSU_POST4] = 0x007c,
298
299 [TXNLCR0] = 0x0080,
300 [TXALCR0] = 0x0084,
301 [RXNLCR0] = 0x0088,
302 [RXALCR0] = 0x008c,
303 [FWNLCR0] = 0x0090,
304 [FWALCR0] = 0x0094,
305 [TXNLCR1] = 0x00a0,
306 [TXALCR1] = 0x00a0,
307 [RXNLCR1] = 0x00a8,
308 [RXALCR1] = 0x00ac,
309 [FWNLCR1] = 0x00b0,
310 [FWALCR1] = 0x00b4,
311
312 [TSU_ADRH0] = 0x0100,
313 [TSU_ADRL0] = 0x0104,
314 [TSU_ADRL31] = 0x01fc,
315};
316
dabdde9e
NI		 317static int sh_eth_is_gether(struct sh_eth_private *mdp)
318{
319 if (mdp->reg_offset == sh_eth_offset_gigabit)
320 return 1;
321 else
322 return 0;
323}
324
8e994402 325static void sh_eth_select_mii(struct net_device *ndev)
5e7a76be
NI		 326{
327 u32 value = 0x0;
328 struct sh_eth_private *mdp = netdev_priv(ndev);
329
330 switch (mdp->phy_interface) {
331 case PHY_INTERFACE_MODE_GMII:
332 value = 0x2;
333 break;
334 case PHY_INTERFACE_MODE_MII:
335 value = 0x1;
336 break;
337 case PHY_INTERFACE_MODE_RMII:
338 value = 0x0;
339 break;
340 default:
341 pr_warn("PHY interface mode was not setup. Set to MII.\n");
342 value = 0x1;
343 break;
344 }
345
346 sh_eth_write(ndev, value, RMII_MII);
347}
5e7a76be 348
8e994402 349static void sh_eth_set_duplex(struct net_device *ndev)
65ac8851
YS		 350{
351 struct sh_eth_private *mdp = netdev_priv(ndev);
65ac8851
YS		 352
353 if (mdp->duplex) /* Full */
4a55530f 354 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
65ac8851 355 else /* Half */
4a55530f 356 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
65ac8851
YS		 357}
358
04b0ed2a 359/* There is CPU dependent code */
589ebdef 360static void sh_eth_set_rate_r8a777x(struct net_device *ndev)
65ac8851
YS		 361{
362 struct sh_eth_private *mdp = netdev_priv(ndev);
d0418bb7 363
a3f109bd
SS		 364 switch (mdp->speed) {
365 case 10: /* 10BASE */
366 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_ELB, ECMR);
367 break;
368 case 100:/* 100BASE */
369 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_ELB, ECMR);
370 break;
371 default:
372 break;
373 }
374}
375
674853b2 376/* R8A7778/9 */
589ebdef 377static struct sh_eth_cpu_data r8a777x_data = {
a3f109bd 378 .set_duplex = sh_eth_set_duplex,
589ebdef 379 .set_rate = sh_eth_set_rate_r8a777x,
a3f109bd
SS		 380
381 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
382 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
383 .eesipr_value = 0x01ff009f,
384
385 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
ca8c3585
SS		 386 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
387 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
388 EESR_ECI,
a3f109bd
SS		 389
390 .apr = 1,
391 .mpr = 1,
392 .tpauser = 1,
393 .hw_swap = 1,
394};
a3f109bd 395
e18dbf7e
SH		 396/* R8A7790 */
397static struct sh_eth_cpu_data r8a7790_data = {
398 .set_duplex = sh_eth_set_duplex,
399 .set_rate = sh_eth_set_rate_r8a777x,
400
401 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
402 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
403 .eesipr_value = 0x01ff009f,
404
405 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
ba361cb3
LP		 406 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
407 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
408 EESR_ECI,
e18dbf7e
SH		 409
410 .apr = 1,
411 .mpr = 1,
412 .tpauser = 1,
413 .hw_swap = 1,
414 .rmiimode = 1,
415};
416
9c3beaab 417static void sh_eth_set_rate_sh7724(struct net_device *ndev)
a3f109bd
SS		 418{
419 struct sh_eth_private *mdp = netdev_priv(ndev);
65ac8851
YS		 420
421 switch (mdp->speed) {
422 case 10: /* 10BASE */
a3f109bd 423 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_RTM, ECMR);
65ac8851
YS		 424 break;
425 case 100:/* 100BASE */
a3f109bd 426 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_RTM, ECMR);
65ac8851
YS		 427 break;
428 default:
429 break;
430 }
431}
432
433/* SH7724 */
9c3beaab 434static struct sh_eth_cpu_data sh7724_data = {
65ac8851 435 .set_duplex = sh_eth_set_duplex,
9c3beaab 436 .set_rate = sh_eth_set_rate_sh7724,
65ac8851
YS		 437
438 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
439 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
a80c3de7 440 .eesipr_value = 0x01ff009f,
65ac8851
YS		 441
442 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
ca8c3585
SS		 443 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
444 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
445 EESR_ECI,
65ac8851
YS		 446
447 .apr = 1,
448 .mpr = 1,
449 .tpauser = 1,
450 .hw_swap = 1,
503914cf
MD		 451 .rpadir = 1,
452 .rpadir_value = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
65ac8851 453};
5cee1d37 454
24549e2a 455static void sh_eth_set_rate_sh7757(struct net_device *ndev)
f29a3d04
YS		 456{
457 struct sh_eth_private *mdp = netdev_priv(ndev);
f29a3d04
YS		 458
459 switch (mdp->speed) {
460 case 10: /* 10BASE */
4a55530f 461 sh_eth_write(ndev, 0, RTRATE);
f29a3d04
YS		 462 break;
463 case 100:/* 100BASE */
4a55530f 464 sh_eth_write(ndev, 1, RTRATE);
f29a3d04
YS		 465 break;
466 default:
467 break;
468 }
469}
470
471/* SH7757 */
24549e2a
SS		 472static struct sh_eth_cpu_data sh7757_data = {
473 .set_duplex = sh_eth_set_duplex,
474 .set_rate = sh_eth_set_rate_sh7757,
f29a3d04
YS		 475
476 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
477 .rmcr_value = 0x00000001,
478
479 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
ca8c3585
SS		 480 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
481 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
482 EESR_ECI,
f29a3d04 483
5b3dfd13 484 .irq_flags = IRQF_SHARED,
f29a3d04
YS		 485 .apr = 1,
486 .mpr = 1,
487 .tpauser = 1,
488 .hw_swap = 1,
489 .no_ade = 1,
2e98e797
YS		 490 .rpadir = 1,
491 .rpadir_value = 2 << 16,
f29a3d04 492};
65ac8851 493
e403d295 494#define SH_GIGA_ETH_BASE 0xfee00000UL
8fcd4961
YS		 495#define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
496#define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
497static void sh_eth_chip_reset_giga(struct net_device *ndev)
498{
499 int i;
500 unsigned long mahr[2], malr[2];
501
502 /* save MAHR and MALR */
503 for (i = 0; i < 2; i++) {
ae70644d
YS		 504 malr[i] = ioread32((void *)GIGA_MALR(i));
505 mahr[i] = ioread32((void *)GIGA_MAHR(i));
8fcd4961
YS		 506 }
507
508 /* reset device */
ae70644d 509 iowrite32(ARSTR_ARSTR, (void *)(SH_GIGA_ETH_BASE + 0x1800));
8fcd4961
YS		 510 mdelay(1);
511
512 /* restore MAHR and MALR */
513 for (i = 0; i < 2; i++) {
ae70644d
YS		 514 iowrite32(malr[i], (void *)GIGA_MALR(i));
515 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
8fcd4961
YS		 516 }
517}
518
8fcd4961
YS		 519static void sh_eth_set_rate_giga(struct net_device *ndev)
520{
521 struct sh_eth_private *mdp = netdev_priv(ndev);
522
523 switch (mdp->speed) {
524 case 10: /* 10BASE */
525 sh_eth_write(ndev, 0x00000000, GECMR);
526 break;
527 case 100:/* 100BASE */
528 sh_eth_write(ndev, 0x00000010, GECMR);
529 break;
530 case 1000: /* 1000BASE */
531 sh_eth_write(ndev, 0x00000020, GECMR);
532 break;
533 default:
534 break;
535 }
536}
537
538/* SH7757(GETHERC) */
24549e2a 539static struct sh_eth_cpu_data sh7757_data_giga = {
8fcd4961 540 .chip_reset = sh_eth_chip_reset_giga,
04b0ed2a 541 .set_duplex = sh_eth_set_duplex,
8fcd4961
YS		 542 .set_rate = sh_eth_set_rate_giga,
543
544 .ecsr_value = ECSR_ICD | ECSR_MPD,
545 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
546 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
547
548 .tx_check = EESR_TC1 | EESR_FTC,
ca8c3585
SS		 549 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
550 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
551 EESR_TDE | EESR_ECI,
8fcd4961
YS		 552 .fdr_value = 0x0000072f,
553 .rmcr_value = 0x00000001,
554
5b3dfd13 555 .irq_flags = IRQF_SHARED,
8fcd4961
YS		 556 .apr = 1,
557 .mpr = 1,
558 .tpauser = 1,
559 .bculr = 1,
560 .hw_swap = 1,
561 .rpadir = 1,
562 .rpadir_value = 2 << 16,
563 .no_trimd = 1,
564 .no_ade = 1,
3acbc971 565 .tsu = 1,
8fcd4961
YS		 566};
567
380af9e3
YS		 568static void sh_eth_chip_reset(struct net_device *ndev)
569{
4986b996
YS		 570 struct sh_eth_private *mdp = netdev_priv(ndev);
571
380af9e3 572 /* reset device */
4986b996 573 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
380af9e3
YS		 574 mdelay(1);
575}
576
f5d12767 577static void sh_eth_set_rate_gether(struct net_device *ndev)
380af9e3
YS		 578{
579 struct sh_eth_private *mdp = netdev_priv(ndev);
380af9e3
YS		 580
581 switch (mdp->speed) {
582 case 10: /* 10BASE */
4a55530f 583 sh_eth_write(ndev, GECMR_10, GECMR);
380af9e3
YS		 584 break;
585 case 100:/* 100BASE */
4a55530f 586 sh_eth_write(ndev, GECMR_100, GECMR);
380af9e3
YS		 587 break;
588 case 1000: /* 1000BASE */
4a55530f 589 sh_eth_write(ndev, GECMR_1000, GECMR);
380af9e3
YS		 590 break;
591 default:
592 break;
593 }
594}
595
f5d12767
SS		 596/* SH7734 */
597static struct sh_eth_cpu_data sh7734_data = {
380af9e3
YS		 598 .chip_reset = sh_eth_chip_reset,
599 .set_duplex = sh_eth_set_duplex,
f5d12767
SS		 600 .set_rate = sh_eth_set_rate_gether,
601
602 .ecsr_value = ECSR_ICD | ECSR_MPD,
603 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
604 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
605
606 .tx_check = EESR_TC1 | EESR_FTC,
ca8c3585
SS		 607 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
608 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
609 EESR_TDE | EESR_ECI,
f5d12767
SS		 610
611 .apr = 1,
612 .mpr = 1,
613 .tpauser = 1,
614 .bculr = 1,
615 .hw_swap = 1,
616 .no_trimd = 1,
617 .no_ade = 1,
618 .tsu = 1,
619 .hw_crc = 1,
620 .select_mii = 1,
621};
622
623/* SH7763 */
624static struct sh_eth_cpu_data sh7763_data = {
625 .chip_reset = sh_eth_chip_reset,
626 .set_duplex = sh_eth_set_duplex,
627 .set_rate = sh_eth_set_rate_gether,
380af9e3
YS		 628
629 .ecsr_value = ECSR_ICD | ECSR_MPD,
630 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
631 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
632
633 .tx_check = EESR_TC1 | EESR_FTC,
634 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \
635 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \
636 EESR_ECI,
380af9e3
YS		 637
638 .apr = 1,
639 .mpr = 1,
640 .tpauser = 1,
641 .bculr = 1,
642 .hw_swap = 1,
380af9e3
YS		 643 .no_trimd = 1,
644 .no_ade = 1,
4986b996 645 .tsu = 1,
5b3dfd13 646 .irq_flags = IRQF_SHARED,
380af9e3
YS		 647};
648
e5c9b4cd 649static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
73a0d907
YS		 650{
651 struct sh_eth_private *mdp = netdev_priv(ndev);
73a0d907
YS		 652
653 /* reset device */
654 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
655 mdelay(1);
656
5e7a76be 657 sh_eth_select_mii(ndev);
73a0d907
YS		 658}
659
73a0d907 660/* R8A7740 */
e5c9b4cd
SS		 661static struct sh_eth_cpu_data r8a7740_data = {
662 .chip_reset = sh_eth_chip_reset_r8a7740,
73a0d907 663 .set_duplex = sh_eth_set_duplex,
e5c9b4cd 664 .set_rate = sh_eth_set_rate_gether,
73a0d907
YS		 665
666 .ecsr_value = ECSR_ICD | ECSR_MPD,
667 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
668 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
669
670 .tx_check = EESR_TC1 | EESR_FTC,
ca8c3585
SS		 671 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
672 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
673 EESR_TDE | EESR_ECI,
73a0d907
YS		 674
675 .apr = 1,
676 .mpr = 1,
677 .tpauser = 1,
678 .bculr = 1,
679 .hw_swap = 1,
680 .no_trimd = 1,
681 .no_ade = 1,
682 .tsu = 1,
5e7a76be 683 .select_mii = 1,
ac8025a6 684 .shift_rd0 = 1,
73a0d907
YS		 685};
686
c18a79ab 687static struct sh_eth_cpu_data sh7619_data = {
380af9e3
YS		 688 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
689
690 .apr = 1,
691 .mpr = 1,
692 .tpauser = 1,
693 .hw_swap = 1,
694};
7bbe150d
SS		 695
696static struct sh_eth_cpu_data sh771x_data = {
380af9e3 697 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
4986b996 698 .tsu = 1,
380af9e3 699};
380af9e3
YS		 700
701static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
702{
703 if (!cd->ecsr_value)
704 cd->ecsr_value = DEFAULT_ECSR_INIT;
705
706 if (!cd->ecsipr_value)
707 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
708
709 if (!cd->fcftr_value)
710 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF | \
711 DEFAULT_FIFO_F_D_RFD;
712
713 if (!cd->fdr_value)
714 cd->fdr_value = DEFAULT_FDR_INIT;
715
716 if (!cd->rmcr_value)
717 cd->rmcr_value = DEFAULT_RMCR_VALUE;
718
719 if (!cd->tx_check)
720 cd->tx_check = DEFAULT_TX_CHECK;
721
722 if (!cd->eesr_err_check)
723 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
380af9e3
YS		 724}
725
5cee1d37
NI		 726static int sh_eth_check_reset(struct net_device *ndev)
727{
728 int ret = 0;
729 int cnt = 100;
730
731 while (cnt > 0) {
732 if (!(sh_eth_read(ndev, EDMR) & 0x3))
733 break;
734 mdelay(1);
735 cnt--;
736 }
9f8c4265
SS		 737 if (cnt <= 0) {
738 pr_err("Device reset failed\n");
5cee1d37
NI		 739 ret = -ETIMEDOUT;
740 }
741 return ret;
380af9e3 742}
dabdde9e
NI		 743
744static int sh_eth_reset(struct net_device *ndev)
745{
746 struct sh_eth_private *mdp = netdev_priv(ndev);
747 int ret = 0;
748
749 if (sh_eth_is_gether(mdp)) {
750 sh_eth_write(ndev, EDSR_ENALL, EDSR);
751 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER,
752 EDMR);
753
754 ret = sh_eth_check_reset(ndev);
755 if (ret)
756 goto out;
757
758 /* Table Init */
759 sh_eth_write(ndev, 0x0, TDLAR);
760 sh_eth_write(ndev, 0x0, TDFAR);
761 sh_eth_write(ndev, 0x0, TDFXR);
762 sh_eth_write(ndev, 0x0, TDFFR);
763 sh_eth_write(ndev, 0x0, RDLAR);
764 sh_eth_write(ndev, 0x0, RDFAR);
765 sh_eth_write(ndev, 0x0, RDFXR);
766 sh_eth_write(ndev, 0x0, RDFFR);
767
768 /* Reset HW CRC register */
769 if (mdp->cd->hw_crc)
770 sh_eth_write(ndev, 0x0, CSMR);
771
772 /* Select MII mode */
773 if (mdp->cd->select_mii)
774 sh_eth_select_mii(ndev);
775 } else {
776 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER,
777 EDMR);
778 mdelay(3);
779 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER,
780 EDMR);
781 }
782
783out:
784 return ret;
785}
380af9e3 786
73a0d907 787#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
380af9e3
YS		 788static void sh_eth_set_receive_align(struct sk_buff *skb)
789{
790 int reserve;
791
792 reserve = SH4_SKB_RX_ALIGN - ((u32)skb->data & (SH4_SKB_RX_ALIGN - 1));
793 if (reserve)
794 skb_reserve(skb, reserve);
795}
796#else
797static void sh_eth_set_receive_align(struct sk_buff *skb)
798{
799 skb_reserve(skb, SH2_SH3_SKB_RX_ALIGN);
800}
801#endif
802
803
71557a37
YS		 804/* CPU <-> EDMAC endian convert */
805static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x)
806{
807 switch (mdp->edmac_endian) {
808 case EDMAC_LITTLE_ENDIAN:
809 return cpu_to_le32(x);
810 case EDMAC_BIG_ENDIAN:
811 return cpu_to_be32(x);
812 }
813 return x;
814}
815
816static inline __u32 edmac_to_cpu(struct sh_eth_private *mdp, u32 x)
817{
818 switch (mdp->edmac_endian) {
819 case EDMAC_LITTLE_ENDIAN:
820 return le32_to_cpu(x);
821 case EDMAC_BIG_ENDIAN:
822 return be32_to_cpu(x);
823 }
824 return x;
825}
826
86a74ff2
NI		 827/*
828 * Program the hardware MAC address from dev->dev_addr.
829 */
830static void update_mac_address(struct net_device *ndev)
831{
4a55530f
YS		 832 sh_eth_write(ndev,
833 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
834 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
835 sh_eth_write(ndev,
836 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
86a74ff2
NI		 837}
838
839/*
840 * Get MAC address from SuperH MAC address register
841 *
842 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
843 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
844 * When you want use this device, you must set MAC address in bootloader.
845 *
846 */
748031f9 847static void read_mac_address(struct net_device *ndev, unsigned char *mac)
86a74ff2 848{
748031f9
MD		 849 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
850 memcpy(ndev->dev_addr, mac, 6);
851 } else {
4a55530f
YS		 852 ndev->dev_addr[0] = (sh_eth_read(ndev, MAHR) >> 24);
853 ndev->dev_addr[1] = (sh_eth_read(ndev, MAHR) >> 16) & 0xFF;
854 ndev->dev_addr[2] = (sh_eth_read(ndev, MAHR) >> 8) & 0xFF;
855 ndev->dev_addr[3] = (sh_eth_read(ndev, MAHR) & 0xFF);
856 ndev->dev_addr[4] = (sh_eth_read(ndev, MALR) >> 8) & 0xFF;
857 ndev->dev_addr[5] = (sh_eth_read(ndev, MALR) & 0xFF);
748031f9 858 }
86a74ff2
NI		 859}
860
c5ed5368
YS		 861static unsigned long sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
862{
863 if (sh_eth_is_gether(mdp))
864 return EDTRR_TRNS_GETHER;
865 else
866 return EDTRR_TRNS_ETHER;
867}
868
86a74ff2 869struct bb_info {
ae70644d 870 void (*set_gate)(void *addr);
86a74ff2 871 struct mdiobb_ctrl ctrl;
ae70644d 872 void *addr;
86a74ff2
NI		 873 u32 mmd_msk;/* MMD */
874 u32 mdo_msk;
875 u32 mdi_msk;
876 u32 mdc_msk;
877};
878
879/* PHY bit set */
ae70644d 880static void bb_set(void *addr, u32 msk)
86a74ff2 881{
ae70644d 882 iowrite32(ioread32(addr) | msk, addr);
86a74ff2
NI		 883}
884
885/* PHY bit clear */
ae70644d 886static void bb_clr(void *addr, u32 msk)
86a74ff2 887{
ae70644d 888 iowrite32((ioread32(addr) & ~msk), addr);
86a74ff2
NI		 889}
890
891/* PHY bit read */
ae70644d 892static int bb_read(void *addr, u32 msk)
86a74ff2 893{
ae70644d 894 return (ioread32(addr) & msk) != 0;
86a74ff2
NI		 895}
896
897/* Data I/O pin control */
898static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
899{
900 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
b3017e6a
YS		 901
902 if (bitbang->set_gate)
903 bitbang->set_gate(bitbang->addr);
904
86a74ff2
NI		 905 if (bit)
906 bb_set(bitbang->addr, bitbang->mmd_msk);
907 else
908 bb_clr(bitbang->addr, bitbang->mmd_msk);
909}
910
911/* Set bit data*/
912static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
913{
914 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
915
b3017e6a
YS		 916 if (bitbang->set_gate)
917 bitbang->set_gate(bitbang->addr);
918
86a74ff2
NI		 919 if (bit)
920 bb_set(bitbang->addr, bitbang->mdo_msk);
921 else
922 bb_clr(bitbang->addr, bitbang->mdo_msk);
923}
924
925/* Get bit data*/
926static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
927{
928 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
b3017e6a
YS		 929
930 if (bitbang->set_gate)
931 bitbang->set_gate(bitbang->addr);
932
86a74ff2
NI		 933 return bb_read(bitbang->addr, bitbang->mdi_msk);
934}
935
936/* MDC pin control */
937static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
938{
939 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
940
b3017e6a
YS		 941 if (bitbang->set_gate)
942 bitbang->set_gate(bitbang->addr);
943
86a74ff2
NI		 944 if (bit)
945 bb_set(bitbang->addr, bitbang->mdc_msk);
946 else
947 bb_clr(bitbang->addr, bitbang->mdc_msk);
948}
949
950/* mdio bus control struct */
951static struct mdiobb_ops bb_ops = {
952 .owner = THIS_MODULE,
953 .set_mdc = sh_mdc_ctrl,
954 .set_mdio_dir = sh_mmd_ctrl,
955 .set_mdio_data = sh_set_mdio,
956 .get_mdio_data = sh_get_mdio,
957};
958
86a74ff2
NI		 959/* free skb and descriptor buffer */
960static void sh_eth_ring_free(struct net_device *ndev)
961{
962 struct sh_eth_private *mdp = netdev_priv(ndev);
963 int i;
964
965 /* Free Rx skb ringbuffer */
966 if (mdp->rx_skbuff) {
525b8075 967 for (i = 0; i < mdp->num_rx_ring; i++) {
86a74ff2
NI		 968 if (mdp->rx_skbuff[i])
969 dev_kfree_skb(mdp->rx_skbuff[i]);
970 }
971 }
972 kfree(mdp->rx_skbuff);
91c77550 973 mdp->rx_skbuff = NULL;
86a74ff2
NI		 974
975 /* Free Tx skb ringbuffer */
976 if (mdp->tx_skbuff) {
525b8075 977 for (i = 0; i < mdp->num_tx_ring; i++) {
86a74ff2
NI		 978 if (mdp->tx_skbuff[i])
979 dev_kfree_skb(mdp->tx_skbuff[i]);
980 }
981 }
982 kfree(mdp->tx_skbuff);
91c77550 983 mdp->tx_skbuff = NULL;
86a74ff2
NI		 984}
985
986/* format skb and descriptor buffer */
987static void sh_eth_ring_format(struct net_device *ndev)
988{
989 struct sh_eth_private *mdp = netdev_priv(ndev);
990 int i;
991 struct sk_buff *skb;
992 struct sh_eth_rxdesc *rxdesc = NULL;
993 struct sh_eth_txdesc *txdesc = NULL;
525b8075
YS		 994 int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
995 int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
86a74ff2
NI		 996
997 mdp->cur_rx = mdp->cur_tx = 0;
998 mdp->dirty_rx = mdp->dirty_tx = 0;
999
1000 memset(mdp->rx_ring, 0, rx_ringsize);
1001
1002 /* build Rx ring buffer */
525b8075 1003 for (i = 0; i < mdp->num_rx_ring; i++) {
86a74ff2
NI		 1004 /* skb */
1005 mdp->rx_skbuff[i] = NULL;
dae2e9f4 1006 skb = netdev_alloc_skb(ndev, mdp->rx_buf_sz);
86a74ff2
NI		 1007 mdp->rx_skbuff[i] = skb;
1008 if (skb == NULL)
1009 break;
bb7d92e3 1010 dma_map_single(&ndev->dev, skb->data, mdp->rx_buf_sz,
e88aae7b 1011 DMA_FROM_DEVICE);
380af9e3
YS		 1012 sh_eth_set_receive_align(skb);
1013
86a74ff2
NI		 1014 /* RX descriptor */
1015 rxdesc = &mdp->rx_ring[i];
0029d64a 1016 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
71557a37 1017 rxdesc->status = cpu_to_edmac(mdp, RD_RACT | RD_RFP);
86a74ff2
NI		 1018
1019 /* The size of the buffer is 16 byte boundary. */
0029d64a 1020 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
b0ca2a21
NI		 1021 /* Rx descriptor address set */
1022 if (i == 0) {
4a55530f 1023 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
c5ed5368
YS		 1024 if (sh_eth_is_gether(mdp))
1025 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
b0ca2a21 1026 }
86a74ff2
NI		 1027 }
1028
525b8075 1029 mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
86a74ff2
NI		 1030
1031 /* Mark the last entry as wrapping the ring. */
71557a37 1032 rxdesc->status |= cpu_to_edmac(mdp, RD_RDEL);
86a74ff2
NI		 1033
1034 memset(mdp->tx_ring, 0, tx_ringsize);
1035
1036 /* build Tx ring buffer */
525b8075 1037 for (i = 0; i < mdp->num_tx_ring; i++) {
86a74ff2
NI		 1038 mdp->tx_skbuff[i] = NULL;
1039 txdesc = &mdp->tx_ring[i];
71557a37 1040 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
86a74ff2 1041 txdesc->buffer_length = 0;
b0ca2a21 1042 if (i == 0) {
71557a37 1043 /* Tx descriptor address set */
4a55530f 1044 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
c5ed5368
YS		 1045 if (sh_eth_is_gether(mdp))
1046 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
b0ca2a21 1047 }
86a74ff2
NI		 1048 }
1049
71557a37 1050 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
86a74ff2
NI		 1051}
1052
1053/* Get skb and descriptor buffer */
1054static int sh_eth_ring_init(struct net_device *ndev)
1055{
1056 struct sh_eth_private *mdp = netdev_priv(ndev);
1057 int rx_ringsize, tx_ringsize, ret = 0;
1058
1059 /*
1060 * +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
1061 * card needs room to do 8 byte alignment, +2 so we can reserve
1062 * the first 2 bytes, and +16 gets room for the status word from the
1063 * card.
1064 */
1065 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
1066 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
503914cf
MD		 1067 if (mdp->cd->rpadir)
1068 mdp->rx_buf_sz += NET_IP_ALIGN;
86a74ff2
NI		 1069
1070 /* Allocate RX and TX skb rings */
b2adaca9
JP		 1071 mdp->rx_skbuff = kmalloc_array(mdp->num_rx_ring,
1072 sizeof(*mdp->rx_skbuff), GFP_KERNEL);
86a74ff2 1073 if (!mdp->rx_skbuff) {
86a74ff2
NI		 1074 ret = -ENOMEM;
1075 return ret;
1076 }
1077
b2adaca9
JP		 1078 mdp->tx_skbuff = kmalloc_array(mdp->num_tx_ring,
1079 sizeof(*mdp->tx_skbuff), GFP_KERNEL);
86a74ff2 1080 if (!mdp->tx_skbuff) {
86a74ff2
NI		 1081 ret = -ENOMEM;
1082 goto skb_ring_free;
1083 }
1084
1085 /* Allocate all Rx descriptors. */
525b8075 1086 rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
86a74ff2 1087 mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
d0320f75 1088 GFP_KERNEL);
86a74ff2 1089 if (!mdp->rx_ring) {
86a74ff2
NI		 1090 ret = -ENOMEM;
1091 goto desc_ring_free;
1092 }
1093
1094 mdp->dirty_rx = 0;
1095
1096 /* Allocate all Tx descriptors. */
525b8075 1097 tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
86a74ff2 1098 mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
d0320f75 1099 GFP_KERNEL);
86a74ff2 1100 if (!mdp->tx_ring) {
86a74ff2
NI		 1101 ret = -ENOMEM;
1102 goto desc_ring_free;
1103 }
1104 return ret;
1105
1106desc_ring_free:
1107 /* free DMA buffer */
1108 dma_free_coherent(NULL, rx_ringsize, mdp->rx_ring, mdp->rx_desc_dma);
1109
1110skb_ring_free:
1111 /* Free Rx and Tx skb ring buffer */
1112 sh_eth_ring_free(ndev);
91c77550
YS		 1113 mdp->tx_ring = NULL;
1114 mdp->rx_ring = NULL;
86a74ff2
NI		 1115
1116 return ret;
1117}
1118
91c77550
YS		 1119static void sh_eth_free_dma_buffer(struct sh_eth_private *mdp)
1120{
1121 int ringsize;
1122
1123 if (mdp->rx_ring) {
525b8075 1124 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
91c77550
YS		 1125 dma_free_coherent(NULL, ringsize, mdp->rx_ring,
1126 mdp->rx_desc_dma);
1127 mdp->rx_ring = NULL;
1128 }
1129
1130 if (mdp->tx_ring) {
525b8075 1131 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
91c77550
YS		 1132 dma_free_coherent(NULL, ringsize, mdp->tx_ring,
1133 mdp->tx_desc_dma);
1134 mdp->tx_ring = NULL;
1135 }
1136}
1137
525b8075 1138static int sh_eth_dev_init(struct net_device *ndev, bool start)
86a74ff2
NI		 1139{
1140 int ret = 0;
1141 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 1142 u32 val;
1143
1144 /* Soft Reset */
5cee1d37
NI		 1145 ret = sh_eth_reset(ndev);
1146 if (ret)
1147 goto out;
86a74ff2 1148
55754f19
SH		 1149 if (mdp->cd->rmiimode)
1150 sh_eth_write(ndev, 0x1, RMIIMODE);
1151
b0ca2a21
NI		 1152 /* Descriptor format */
1153 sh_eth_ring_format(ndev);
380af9e3 1154 if (mdp->cd->rpadir)
4a55530f 1155 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
86a74ff2
NI		 1156
1157 /* all sh_eth int mask */
4a55530f 1158 sh_eth_write(ndev, 0, EESIPR);
86a74ff2 1159
10b9194f 1160#if defined(__LITTLE_ENDIAN)
380af9e3 1161 if (mdp->cd->hw_swap)
4a55530f 1162 sh_eth_write(ndev, EDMR_EL, EDMR);
380af9e3 1163 else
b0ca2a21 1164#endif
4a55530f 1165 sh_eth_write(ndev, 0, EDMR);
86a74ff2 1166
b0ca2a21 1167 /* FIFO size set */
4a55530f
YS		 1168 sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
1169 sh_eth_write(ndev, 0, TFTR);
86a74ff2 1170
b0ca2a21 1171 /* Frame recv control */
4a55530f 1172 sh_eth_write(ndev, mdp->cd->rmcr_value, RMCR);
86a74ff2 1173
2ecbb783 1174 sh_eth_write(ndev, DESC_I_RINT8 | DESC_I_RINT5 | DESC_I_TINT2, TRSCER);
86a74ff2 1175
380af9e3 1176 if (mdp->cd->bculr)
4a55530f 1177 sh_eth_write(ndev, 0x800, BCULR); /* Burst sycle set */
b0ca2a21 1178
4a55530f 1179 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
86a74ff2 1180
380af9e3 1181 if (!mdp->cd->no_trimd)
4a55530f 1182 sh_eth_write(ndev, 0, TRIMD);
86a74ff2 1183
b0ca2a21 1184 /* Recv frame limit set register */
fdb37a7f
YS		 1185 sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1186 RFLR);
86a74ff2 1187
4a55530f 1188 sh_eth_write(ndev, sh_eth_read(ndev, EESR), EESR);
525b8075
YS		 1189 if (start)
1190 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
86a74ff2
NI		 1191
1192 /* PAUSE Prohibition */
4a55530f 1193 val = (sh_eth_read(ndev, ECMR) & ECMR_DM) |
86a74ff2
NI		 1194 ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE;
1195
4a55530f 1196 sh_eth_write(ndev, val, ECMR);
b0ca2a21 1197
380af9e3
YS		 1198 if (mdp->cd->set_rate)
1199 mdp->cd->set_rate(ndev);
1200
b0ca2a21 1201 /* E-MAC Status Register clear */
4a55530f 1202 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
b0ca2a21
NI		 1203
1204 /* E-MAC Interrupt Enable register */
525b8075
YS		 1205 if (start)
1206 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
86a74ff2
NI		 1207
1208 /* Set MAC address */
1209 update_mac_address(ndev);
1210
1211 /* mask reset */
380af9e3 1212 if (mdp->cd->apr)
4a55530f 1213 sh_eth_write(ndev, APR_AP, APR);
380af9e3 1214 if (mdp->cd->mpr)
4a55530f 1215 sh_eth_write(ndev, MPR_MP, MPR);
380af9e3 1216 if (mdp->cd->tpauser)
4a55530f 1217 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
b0ca2a21 1218
525b8075
YS		 1219 if (start) {
1220 /* Setting the Rx mode will start the Rx process. */
1221 sh_eth_write(ndev, EDRRR_R, EDRRR);
86a74ff2 1222
525b8075
YS		 1223 netif_start_queue(ndev);
1224 }
86a74ff2 1225
5cee1d37 1226out:
86a74ff2
NI		 1227 return ret;
1228}
1229
1230/* free Tx skb function */
1231static int sh_eth_txfree(struct net_device *ndev)
1232{
1233 struct sh_eth_private *mdp = netdev_priv(ndev);
1234 struct sh_eth_txdesc *txdesc;
1235 int freeNum = 0;
1236 int entry = 0;
1237
1238 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
525b8075 1239 entry = mdp->dirty_tx % mdp->num_tx_ring;
86a74ff2 1240 txdesc = &mdp->tx_ring[entry];
71557a37 1241 if (txdesc->status & cpu_to_edmac(mdp, TD_TACT))
86a74ff2
NI		 1242 break;
1243 /* Free the original skb. */
1244 if (mdp->tx_skbuff[entry]) {
31fcb99d
YS		 1245 dma_unmap_single(&ndev->dev, txdesc->addr,
1246 txdesc->buffer_length, DMA_TO_DEVICE);
86a74ff2
NI		 1247 dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1248 mdp->tx_skbuff[entry] = NULL;
1249 freeNum++;
1250 }
71557a37 1251 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
525b8075 1252 if (entry >= mdp->num_tx_ring - 1)
71557a37 1253 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
86a74ff2 1254
bb7d92e3
ED		 1255 ndev->stats.tx_packets++;
1256 ndev->stats.tx_bytes += txdesc->buffer_length;
86a74ff2
NI		 1257 }
1258 return freeNum;
1259}
1260
1261/* Packet receive function */
3719109d 1262static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
86a74ff2
NI		 1263{
1264 struct sh_eth_private *mdp = netdev_priv(ndev);
1265 struct sh_eth_rxdesc *rxdesc;
1266
525b8075
YS		 1267 int entry = mdp->cur_rx % mdp->num_rx_ring;
1268 int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
86a74ff2 1269 struct sk_buff *skb;
3719109d 1270 int exceeded = 0;
86a74ff2 1271 u16 pkt_len = 0;
380af9e3 1272 u32 desc_status;
86a74ff2
NI		 1273
1274 rxdesc = &mdp->rx_ring[entry];
71557a37
YS		 1275 while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) {
1276 desc_status = edmac_to_cpu(mdp, rxdesc->status);
86a74ff2
NI		 1277 pkt_len = rxdesc->frame_length;
1278
1279 if (--boguscnt < 0)
1280 break;
1281
3719109d
SS		 1282 if (*quota <= 0) {
1283 exceeded = 1;
1284 break;
1285 }
1286 (*quota)--;
1287
86a74ff2 1288 if (!(desc_status & RDFEND))
bb7d92e3 1289 ndev->stats.rx_length_errors++;
86a74ff2 1290
dd019897
YS		 1291 /*
1292 * In case of almost all GETHER/ETHERs, the Receive Frame State
1293 * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
1294 * bit 0. However, in case of the R8A7740's GETHER, the RFS
1295 * bits are from bit 25 to bit 16. So, the driver needs right
1296 * shifting by 16.
1297 */
ac8025a6
SS		 1298 if (mdp->cd->shift_rd0)
1299 desc_status >>= 16;
dd019897 1300
86a74ff2
NI		 1301 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1302 RD_RFS5 | RD_RFS6 | RD_RFS10)) {
bb7d92e3 1303 ndev->stats.rx_errors++;
86a74ff2 1304 if (desc_status & RD_RFS1)
bb7d92e3 1305 ndev->stats.rx_crc_errors++;
86a74ff2 1306 if (desc_status & RD_RFS2)
bb7d92e3 1307 ndev->stats.rx_frame_errors++;
86a74ff2 1308 if (desc_status & RD_RFS3)
bb7d92e3 1309 ndev->stats.rx_length_errors++;
86a74ff2 1310 if (desc_status & RD_RFS4)
bb7d92e3 1311 ndev->stats.rx_length_errors++;
86a74ff2 1312 if (desc_status & RD_RFS6)
bb7d92e3 1313 ndev->stats.rx_missed_errors++;
86a74ff2 1314 if (desc_status & RD_RFS10)
bb7d92e3 1315 ndev->stats.rx_over_errors++;
86a74ff2 1316 } else {
380af9e3
YS		 1317 if (!mdp->cd->hw_swap)
1318 sh_eth_soft_swap(
1319 phys_to_virt(ALIGN(rxdesc->addr, 4)),
1320 pkt_len + 2);
86a74ff2
NI		 1321 skb = mdp->rx_skbuff[entry];
1322 mdp->rx_skbuff[entry] = NULL;
503914cf
MD		 1323 if (mdp->cd->rpadir)
1324 skb_reserve(skb, NET_IP_ALIGN);
86a74ff2
NI		 1325 skb_put(skb, pkt_len);
1326 skb->protocol = eth_type_trans(skb, ndev);
1327 netif_rx(skb);
bb7d92e3
ED		 1328 ndev->stats.rx_packets++;
1329 ndev->stats.rx_bytes += pkt_len;
86a74ff2 1330 }
71557a37 1331 rxdesc->status |= cpu_to_edmac(mdp, RD_RACT);
525b8075 1332 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
862df497 1333 rxdesc = &mdp->rx_ring[entry];
86a74ff2
NI		 1334 }
1335
1336 /* Refill the Rx ring buffers. */
1337 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
525b8075 1338 entry = mdp->dirty_rx % mdp->num_rx_ring;
86a74ff2 1339 rxdesc = &mdp->rx_ring[entry];
b0ca2a21 1340 /* The size of the buffer is 16 byte boundary. */
0029d64a 1341 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
b0ca2a21 1342
86a74ff2 1343 if (mdp->rx_skbuff[entry] == NULL) {
dae2e9f4 1344 skb = netdev_alloc_skb(ndev, mdp->rx_buf_sz);
86a74ff2
NI		 1345 mdp->rx_skbuff[entry] = skb;
1346 if (skb == NULL)
1347 break; /* Better luck next round. */
bb7d92e3 1348 dma_map_single(&ndev->dev, skb->data, mdp->rx_buf_sz,
e88aae7b 1349 DMA_FROM_DEVICE);
380af9e3
YS		 1350 sh_eth_set_receive_align(skb);
1351
bc8acf2c 1352 skb_checksum_none_assert(skb);
0029d64a 1353 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
86a74ff2 1354 }
525b8075 1355 if (entry >= mdp->num_rx_ring - 1)
86a74ff2 1356 rxdesc->status |=
71557a37 1357 cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDEL);
86a74ff2
NI		 1358 else
1359 rxdesc->status |=
71557a37 1360 cpu_to_edmac(mdp, RD_RACT | RD_RFP);
86a74ff2
NI		 1361 }
1362
1363 /* Restart Rx engine if stopped. */
1364 /* If we don't need to check status, don't. -KDU */
79fba9f5 1365 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
a18e08bd
YS		 1366 /* fix the values for the next receiving if RDE is set */
1367 if (intr_status & EESR_RDE)
1368 mdp->cur_rx = mdp->dirty_rx =
1369 (sh_eth_read(ndev, RDFAR) -
1370 sh_eth_read(ndev, RDLAR)) >> 4;
4a55530f 1371 sh_eth_write(ndev, EDRRR_R, EDRRR);
79fba9f5 1372 }
86a74ff2 1373
3719109d 1374 return exceeded;
86a74ff2
NI		 1375}
1376
4a55530f 1377static void sh_eth_rcv_snd_disable(struct net_device *ndev)
dc19e4e5
NI		 1378{
1379 /* disable tx and rx */
4a55530f
YS		 1380 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) &
1381 ~(ECMR_RE | ECMR_TE), ECMR);
dc19e4e5
NI		 1382}
1383
4a55530f 1384static void sh_eth_rcv_snd_enable(struct net_device *ndev)
dc19e4e5
NI		 1385{
1386 /* enable tx and rx */
4a55530f
YS		 1387 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) |
1388 (ECMR_RE | ECMR_TE), ECMR);
dc19e4e5
NI		 1389}
1390
86a74ff2
NI		 1391/* error control function */
1392static void sh_eth_error(struct net_device *ndev, int intr_status)
1393{
1394 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2 1395 u32 felic_stat;
380af9e3
YS		 1396 u32 link_stat;
1397 u32 mask;
86a74ff2
NI		 1398
1399 if (intr_status & EESR_ECI) {
4a55530f
YS		 1400 felic_stat = sh_eth_read(ndev, ECSR);
1401 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */
86a74ff2 1402 if (felic_stat & ECSR_ICD)
bb7d92e3 1403 ndev->stats.tx_carrier_errors++;
86a74ff2
NI		 1404 if (felic_stat & ECSR_LCHNG) {
1405 /* Link Changed */
4923576b 1406 if (mdp->cd->no_psr || mdp->no_ether_link) {
1e1b812b 1407 goto ignore_link;
380af9e3 1408 } else {
4a55530f 1409 link_stat = (sh_eth_read(ndev, PSR));
4923576b
YS		 1410 if (mdp->ether_link_active_low)
1411 link_stat = ~link_stat;
380af9e3 1412 }
dc19e4e5 1413 if (!(link_stat & PHY_ST_LINK))
4a55530f 1414 sh_eth_rcv_snd_disable(ndev);
dc19e4e5 1415 else {
86a74ff2 1416 /* Link Up */
4a55530f
YS		 1417 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) &
1418 ~DMAC_M_ECI, EESIPR);
86a74ff2 1419 /*clear int */
4a55530f
YS		 1420 sh_eth_write(ndev, sh_eth_read(ndev, ECSR),
1421 ECSR);
1422 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) |
1423 DMAC_M_ECI, EESIPR);
86a74ff2 1424 /* enable tx and rx */
4a55530f 1425 sh_eth_rcv_snd_enable(ndev);
86a74ff2
NI		 1426 }
1427 }
1428 }
1429
1e1b812b 1430ignore_link:
86a74ff2 1431 if (intr_status & EESR_TWB) {
4eb313a7
SS		 1432 /* Unused write back interrupt */
1433 if (intr_status & EESR_TABT) { /* Transmit Abort int */
bb7d92e3 1434 ndev->stats.tx_aborted_errors++;
dc19e4e5
NI		 1435 if (netif_msg_tx_err(mdp))
1436 dev_err(&ndev->dev, "Transmit Abort\n");
4eb313a7 1437 }
86a74ff2
NI		 1438 }
1439
1440 if (intr_status & EESR_RABT) {
1441 /* Receive Abort int */
1442 if (intr_status & EESR_RFRMER) {
1443 /* Receive Frame Overflow int */
bb7d92e3 1444 ndev->stats.rx_frame_errors++;
dc19e4e5
NI		 1445 if (netif_msg_rx_err(mdp))
1446 dev_err(&ndev->dev, "Receive Abort\n");
86a74ff2
NI		 1447 }
1448 }
380af9e3 1449
dc19e4e5
NI		 1450 if (intr_status & EESR_TDE) {
1451 /* Transmit Descriptor Empty int */
bb7d92e3 1452 ndev->stats.tx_fifo_errors++;
dc19e4e5
NI		 1453 if (netif_msg_tx_err(mdp))
1454 dev_err(&ndev->dev, "Transmit Descriptor Empty\n");
1455 }
1456
1457 if (intr_status & EESR_TFE) {
1458 /* FIFO under flow */
bb7d92e3 1459 ndev->stats.tx_fifo_errors++;
dc19e4e5
NI		 1460 if (netif_msg_tx_err(mdp))
1461 dev_err(&ndev->dev, "Transmit FIFO Under flow\n");
86a74ff2
NI		 1462 }
1463
1464 if (intr_status & EESR_RDE) {
1465 /* Receive Descriptor Empty int */
bb7d92e3 1466 ndev->stats.rx_over_errors++;
86a74ff2 1467
dc19e4e5
NI		 1468 if (netif_msg_rx_err(mdp))
1469 dev_err(&ndev->dev, "Receive Descriptor Empty\n");
86a74ff2 1470 }
dc19e4e5 1471
86a74ff2
NI		 1472 if (intr_status & EESR_RFE) {
1473 /* Receive FIFO Overflow int */
bb7d92e3 1474 ndev->stats.rx_fifo_errors++;
dc19e4e5
NI		 1475 if (netif_msg_rx_err(mdp))
1476 dev_err(&ndev->dev, "Receive FIFO Overflow\n");
1477 }
1478
1479 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1480 /* Address Error */
bb7d92e3 1481 ndev->stats.tx_fifo_errors++;
dc19e4e5
NI		 1482 if (netif_msg_tx_err(mdp))
1483 dev_err(&ndev->dev, "Address Error\n");
86a74ff2 1484 }
380af9e3
YS		 1485
1486 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1487 if (mdp->cd->no_ade)
1488 mask &= ~EESR_ADE;
1489 if (intr_status & mask) {
86a74ff2 1490 /* Tx error */
4a55530f 1491 u32 edtrr = sh_eth_read(ndev, EDTRR);
86a74ff2 1492 /* dmesg */
380af9e3
YS		 1493 dev_err(&ndev->dev, "TX error. status=%8.8x cur_tx=%8.8x ",
1494 intr_status, mdp->cur_tx);
1495 dev_err(&ndev->dev, "dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
86a74ff2
NI		 1496 mdp->dirty_tx, (u32) ndev->state, edtrr);
1497 /* dirty buffer free */
1498 sh_eth_txfree(ndev);
1499
1500 /* SH7712 BUG */
c5ed5368 1501 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
86a74ff2 1502 /* tx dma start */
c5ed5368 1503 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
86a74ff2
NI		 1504 }
1505 /* wakeup */
1506 netif_wake_queue(ndev);
1507 }
1508}
1509
1510static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1511{
1512 struct net_device *ndev = netdev;
1513 struct sh_eth_private *mdp = netdev_priv(ndev);
380af9e3 1514 struct sh_eth_cpu_data *cd = mdp->cd;
0e0fde3c 1515 irqreturn_t ret = IRQ_NONE;
3719109d 1516 unsigned long intr_status, intr_enable;
86a74ff2 1517
86a74ff2
NI		 1518 spin_lock(&mdp->lock);
1519
3893b273 1520 /* Get interrupt status */
4a55530f 1521 intr_status = sh_eth_read(ndev, EESR);
3893b273
SS		 1522 /* Mask it with the interrupt mask, forcing ECI interrupt to be always
1523 * enabled since it's the one that comes thru regardless of the mask,
1524 * and we need to fully handle it in sh_eth_error() in order to quench
1525 * it as it doesn't get cleared by just writing 1 to the ECI bit...
1526 */
3719109d
SS		 1527 intr_enable = sh_eth_read(ndev, EESIPR);
1528 intr_status &= intr_enable | DMAC_M_ECI;
1529 if (intr_status & (EESR_RX_CHECK | cd->tx_check | cd->eesr_err_check))
0e0fde3c 1530 ret = IRQ_HANDLED;
3719109d 1531 else
0e0fde3c 1532 goto other_irq;
86a74ff2 1533
3719109d
SS		 1534 if (intr_status & EESR_RX_CHECK) {
1535 if (napi_schedule_prep(&mdp->napi)) {
1536 /* Mask Rx interrupts */
1537 sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK,
1538 EESIPR);
1539 __napi_schedule(&mdp->napi);
1540 } else {
1541 dev_warn(&ndev->dev,
1542 "ignoring interrupt, status 0x%08lx, mask 0x%08lx.\n",
1543 intr_status, intr_enable);
1544 }
1545 }
86a74ff2 1546
b0ca2a21 1547 /* Tx Check */
380af9e3 1548 if (intr_status & cd->tx_check) {
3719109d
SS		 1549 /* Clear Tx interrupts */
1550 sh_eth_write(ndev, intr_status & cd->tx_check, EESR);
1551
86a74ff2
NI		 1552 sh_eth_txfree(ndev);
1553 netif_wake_queue(ndev);
1554 }
1555
3719109d
SS		 1556 if (intr_status & cd->eesr_err_check) {
1557 /* Clear error interrupts */
1558 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR);
1559
86a74ff2 1560 sh_eth_error(ndev, intr_status);
3719109d 1561 }
86a74ff2 1562
0e0fde3c 1563other_irq:
86a74ff2
NI		 1564 spin_unlock(&mdp->lock);
1565
0e0fde3c 1566 return ret;
86a74ff2
NI		 1567}
1568
3719109d
SS		 1569static int sh_eth_poll(struct napi_struct *napi, int budget)
1570{
1571 struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private,
1572 napi);
1573 struct net_device *ndev = napi->dev;
1574 int quota = budget;
1575 unsigned long intr_status;
1576
1577 for (;;) {
1578 intr_status = sh_eth_read(ndev, EESR);
1579 if (!(intr_status & EESR_RX_CHECK))
1580 break;
1581 /* Clear Rx interrupts */
1582 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR);
1583
1584 if (sh_eth_rx(ndev, intr_status, &quota))
1585 goto out;
1586 }
1587
1588 napi_complete(napi);
1589
1590 /* Reenable Rx interrupts */
1591 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1592out:
1593 return budget - quota;
1594}
1595
86a74ff2
NI		 1596/* PHY state control function */
1597static void sh_eth_adjust_link(struct net_device *ndev)
1598{
1599 struct sh_eth_private *mdp = netdev_priv(ndev);
1600 struct phy_device *phydev = mdp->phydev;
86a74ff2
NI		 1601 int new_state = 0;
1602
3340d2aa 1603 if (phydev->link) {
86a74ff2
NI		 1604 if (phydev->duplex != mdp->duplex) {
1605 new_state = 1;
1606 mdp->duplex = phydev->duplex;
380af9e3
YS		 1607 if (mdp->cd->set_duplex)
1608 mdp->cd->set_duplex(ndev);
86a74ff2
NI		 1609 }
1610
1611 if (phydev->speed != mdp->speed) {
1612 new_state = 1;
1613 mdp->speed = phydev->speed;
380af9e3
YS		 1614 if (mdp->cd->set_rate)
1615 mdp->cd->set_rate(ndev);
86a74ff2 1616 }
3340d2aa 1617 if (!mdp->link) {
91a56152
YS		 1618 sh_eth_write(ndev,
1619 (sh_eth_read(ndev, ECMR) & ~ECMR_TXF), ECMR);
86a74ff2
NI		 1620 new_state = 1;
1621 mdp->link = phydev->link;
1e1b812b
SS		 1622 if (mdp->cd->no_psr || mdp->no_ether_link)
1623 sh_eth_rcv_snd_enable(ndev);
86a74ff2
NI		 1624 }
1625 } else if (mdp->link) {
1626 new_state = 1;
3340d2aa 1627 mdp->link = 0;
86a74ff2
NI		 1628 mdp->speed = 0;
1629 mdp->duplex = -1;
1e1b812b
SS		 1630 if (mdp->cd->no_psr || mdp->no_ether_link)
1631 sh_eth_rcv_snd_disable(ndev);
86a74ff2
NI		 1632 }
1633
dc19e4e5 1634 if (new_state && netif_msg_link(mdp))
86a74ff2
NI		 1635 phy_print_status(phydev);
1636}
1637
1638/* PHY init function */
1639static int sh_eth_phy_init(struct net_device *ndev)
1640{
1641 struct sh_eth_private *mdp = netdev_priv(ndev);
0a372eb9 1642 char phy_id[MII_BUS_ID_SIZE + 3];
86a74ff2
NI		 1643 struct phy_device *phydev = NULL;
1644
fb28ad35 1645 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
86a74ff2
NI		 1646 mdp->mii_bus->id , mdp->phy_id);
1647
3340d2aa 1648 mdp->link = 0;
86a74ff2
NI		 1649 mdp->speed = 0;
1650 mdp->duplex = -1;
1651
1652 /* Try connect to PHY */
c061b18d 1653 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
f9a8f83b 1654 mdp->phy_interface);
86a74ff2
NI		 1655 if (IS_ERR(phydev)) {
1656 dev_err(&ndev->dev, "phy_connect failed\n");
1657 return PTR_ERR(phydev);
1658 }
380af9e3 1659
86a74ff2 1660 dev_info(&ndev->dev, "attached phy %i to driver %s\n",
380af9e3 1661 phydev->addr, phydev->drv->name);
86a74ff2
NI		 1662
1663 mdp->phydev = phydev;
1664
1665 return 0;
1666}
1667
1668/* PHY control start function */
1669static int sh_eth_phy_start(struct net_device *ndev)
1670{
1671 struct sh_eth_private *mdp = netdev_priv(ndev);
1672 int ret;
1673
1674 ret = sh_eth_phy_init(ndev);
1675 if (ret)
1676 return ret;
1677
1678 /* reset phy - this also wakes it from PDOWN */
1679 phy_write(mdp->phydev, MII_BMCR, BMCR_RESET);
1680 phy_start(mdp->phydev);
1681
1682 return 0;
1683}
1684
dc19e4e5
NI		 1685static int sh_eth_get_settings(struct net_device *ndev,
1686 struct ethtool_cmd *ecmd)
1687{
1688 struct sh_eth_private *mdp = netdev_priv(ndev);
1689 unsigned long flags;
1690 int ret;
1691
1692 spin_lock_irqsave(&mdp->lock, flags);
1693 ret = phy_ethtool_gset(mdp->phydev, ecmd);
1694 spin_unlock_irqrestore(&mdp->lock, flags);
1695
1696 return ret;
1697}
1698
1699static int sh_eth_set_settings(struct net_device *ndev,
1700 struct ethtool_cmd *ecmd)
1701{
1702 struct sh_eth_private *mdp = netdev_priv(ndev);
1703 unsigned long flags;
1704 int ret;
dc19e4e5
NI		 1705
1706 spin_lock_irqsave(&mdp->lock, flags);
1707
1708 /* disable tx and rx */
4a55530f 1709 sh_eth_rcv_snd_disable(ndev);
dc19e4e5
NI		 1710
1711 ret = phy_ethtool_sset(mdp->phydev, ecmd);
1712 if (ret)
1713 goto error_exit;
1714
1715 if (ecmd->duplex == DUPLEX_FULL)
1716 mdp->duplex = 1;
1717 else
1718 mdp->duplex = 0;
1719
1720 if (mdp->cd->set_duplex)
1721 mdp->cd->set_duplex(ndev);
1722
1723error_exit:
1724 mdelay(1);
1725
1726 /* enable tx and rx */
4a55530f 1727 sh_eth_rcv_snd_enable(ndev);
dc19e4e5
NI		 1728
1729 spin_unlock_irqrestore(&mdp->lock, flags);
1730
1731 return ret;
1732}
1733
1734static int sh_eth_nway_reset(struct net_device *ndev)
1735{
1736 struct sh_eth_private *mdp = netdev_priv(ndev);
1737 unsigned long flags;
1738 int ret;
1739
1740 spin_lock_irqsave(&mdp->lock, flags);
1741 ret = phy_start_aneg(mdp->phydev);
1742 spin_unlock_irqrestore(&mdp->lock, flags);
1743
1744 return ret;
1745}
1746
1747static u32 sh_eth_get_msglevel(struct net_device *ndev)
1748{
1749 struct sh_eth_private *mdp = netdev_priv(ndev);
1750 return mdp->msg_enable;
1751}
1752
1753static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
1754{
1755 struct sh_eth_private *mdp = netdev_priv(ndev);
1756 mdp->msg_enable = value;
1757}
1758
1759static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
1760 "rx_current", "tx_current",
1761 "rx_dirty", "tx_dirty",
1762};
1763#define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats)
1764
1765static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
1766{
1767 switch (sset) {
1768 case ETH_SS_STATS:
1769 return SH_ETH_STATS_LEN;
1770 default:
1771 return -EOPNOTSUPP;
1772 }
1773}
1774
1775static void sh_eth_get_ethtool_stats(struct net_device *ndev,
1776 struct ethtool_stats *stats, u64 *data)
1777{
1778 struct sh_eth_private *mdp = netdev_priv(ndev);
1779 int i = 0;
1780
1781 /* device-specific stats */
1782 data[i++] = mdp->cur_rx;
1783 data[i++] = mdp->cur_tx;
1784 data[i++] = mdp->dirty_rx;
1785 data[i++] = mdp->dirty_tx;
1786}
1787
1788static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1789{
1790 switch (stringset) {
1791 case ETH_SS_STATS:
1792 memcpy(data, *sh_eth_gstrings_stats,
1793 sizeof(sh_eth_gstrings_stats));
1794 break;
1795 }
1796}
1797
525b8075
YS		 1798static void sh_eth_get_ringparam(struct net_device *ndev,
1799 struct ethtool_ringparam *ring)
1800{
1801 struct sh_eth_private *mdp = netdev_priv(ndev);
1802
1803 ring->rx_max_pending = RX_RING_MAX;
1804 ring->tx_max_pending = TX_RING_MAX;
1805 ring->rx_pending = mdp->num_rx_ring;
1806 ring->tx_pending = mdp->num_tx_ring;
1807}
1808
1809static int sh_eth_set_ringparam(struct net_device *ndev,
1810 struct ethtool_ringparam *ring)
1811{
1812 struct sh_eth_private *mdp = netdev_priv(ndev);
1813 int ret;
1814
1815 if (ring->tx_pending > TX_RING_MAX ||
1816 ring->rx_pending > RX_RING_MAX ||
1817 ring->tx_pending < TX_RING_MIN ||
1818 ring->rx_pending < RX_RING_MIN)
1819 return -EINVAL;
1820 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
1821 return -EINVAL;
1822
1823 if (netif_running(ndev)) {
1824 netif_tx_disable(ndev);
1825 /* Disable interrupts by clearing the interrupt mask. */
1826 sh_eth_write(ndev, 0x0000, EESIPR);
1827 /* Stop the chip's Tx and Rx processes. */
1828 sh_eth_write(ndev, 0, EDTRR);
1829 sh_eth_write(ndev, 0, EDRRR);
1830 synchronize_irq(ndev->irq);
1831 }
1832
1833 /* Free all the skbuffs in the Rx queue. */
1834 sh_eth_ring_free(ndev);
1835 /* Free DMA buffer */
1836 sh_eth_free_dma_buffer(mdp);
1837
1838 /* Set new parameters */
1839 mdp->num_rx_ring = ring->rx_pending;
1840 mdp->num_tx_ring = ring->tx_pending;
1841
1842 ret = sh_eth_ring_init(ndev);
1843 if (ret < 0) {
1844 dev_err(&ndev->dev, "%s: sh_eth_ring_init failed.\n", __func__);
1845 return ret;
1846 }
1847 ret = sh_eth_dev_init(ndev, false);
1848 if (ret < 0) {
1849 dev_err(&ndev->dev, "%s: sh_eth_dev_init failed.\n", __func__);
1850 return ret;
1851 }
1852
1853 if (netif_running(ndev)) {
1854 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1855 /* Setting the Rx mode will start the Rx process. */
1856 sh_eth_write(ndev, EDRRR_R, EDRRR);
1857 netif_wake_queue(ndev);
1858 }
1859
1860 return 0;
1861}
1862
9b07be4b 1863static const struct ethtool_ops sh_eth_ethtool_ops = {
dc19e4e5
NI		 1864 .get_settings = sh_eth_get_settings,
1865 .set_settings = sh_eth_set_settings,
9b07be4b 1866 .nway_reset = sh_eth_nway_reset,
dc19e4e5
NI		 1867 .get_msglevel = sh_eth_get_msglevel,
1868 .set_msglevel = sh_eth_set_msglevel,
9b07be4b 1869 .get_link = ethtool_op_get_link,
dc19e4e5
NI		 1870 .get_strings = sh_eth_get_strings,
1871 .get_ethtool_stats = sh_eth_get_ethtool_stats,
1872 .get_sset_count = sh_eth_get_sset_count,
525b8075
YS		 1873 .get_ringparam = sh_eth_get_ringparam,
1874 .set_ringparam = sh_eth_set_ringparam,
dc19e4e5
NI		 1875};
1876
86a74ff2
NI		 1877/* network device open function */
1878static int sh_eth_open(struct net_device *ndev)
1879{
1880 int ret = 0;
1881 struct sh_eth_private *mdp = netdev_priv(ndev);
1882
bcd5149d
MD		 1883 pm_runtime_get_sync(&mdp->pdev->dev);
1884
a0607fd3 1885 ret = request_irq(ndev->irq, sh_eth_interrupt,
5b3dfd13 1886 mdp->cd->irq_flags, ndev->name, ndev);
86a74ff2 1887 if (ret) {
380af9e3 1888 dev_err(&ndev->dev, "Can not assign IRQ number\n");
86a74ff2
NI		 1889 return ret;
1890 }
1891
1892 /* Descriptor set */
1893 ret = sh_eth_ring_init(ndev);
1894 if (ret)
1895 goto out_free_irq;
1896
1897 /* device init */
525b8075 1898 ret = sh_eth_dev_init(ndev, true);
86a74ff2
NI		 1899 if (ret)
1900 goto out_free_irq;
1901
1902 /* PHY control start*/
1903 ret = sh_eth_phy_start(ndev);
1904 if (ret)
1905 goto out_free_irq;
1906
3719109d
SS		 1907 napi_enable(&mdp->napi);
1908
86a74ff2
NI		 1909 return ret;
1910
1911out_free_irq:
1912 free_irq(ndev->irq, ndev);
bcd5149d 1913 pm_runtime_put_sync(&mdp->pdev->dev);
86a74ff2
NI		 1914 return ret;
1915}
1916
1917/* Timeout function */
1918static void sh_eth_tx_timeout(struct net_device *ndev)
1919{
1920 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 1921 struct sh_eth_rxdesc *rxdesc;
1922 int i;
1923
1924 netif_stop_queue(ndev);
1925
dc19e4e5
NI		 1926 if (netif_msg_timer(mdp))
1927 dev_err(&ndev->dev, "%s: transmit timed out, status %8.8x,"
4a55530f 1928 " resetting...\n", ndev->name, (int)sh_eth_read(ndev, EESR));
86a74ff2
NI		 1929
1930 /* tx_errors count up */
bb7d92e3 1931 ndev->stats.tx_errors++;
86a74ff2 1932
86a74ff2 1933 /* Free all the skbuffs in the Rx queue. */
525b8075 1934 for (i = 0; i < mdp->num_rx_ring; i++) {
86a74ff2
NI		 1935 rxdesc = &mdp->rx_ring[i];
1936 rxdesc->status = 0;
1937 rxdesc->addr = 0xBADF00D0;
1938 if (mdp->rx_skbuff[i])
1939 dev_kfree_skb(mdp->rx_skbuff[i]);
1940 mdp->rx_skbuff[i] = NULL;
1941 }
525b8075 1942 for (i = 0; i < mdp->num_tx_ring; i++) {
86a74ff2
NI		 1943 if (mdp->tx_skbuff[i])
1944 dev_kfree_skb(mdp->tx_skbuff[i]);
1945 mdp->tx_skbuff[i] = NULL;
1946 }
1947
1948 /* device init */
525b8075 1949 sh_eth_dev_init(ndev, true);
86a74ff2
NI		 1950}
1951
1952/* Packet transmit function */
1953static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1954{
1955 struct sh_eth_private *mdp = netdev_priv(ndev);
1956 struct sh_eth_txdesc *txdesc;
1957 u32 entry;
fb5e2f9b 1958 unsigned long flags;
86a74ff2
NI		 1959
1960 spin_lock_irqsave(&mdp->lock, flags);
525b8075 1961 if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
86a74ff2 1962 if (!sh_eth_txfree(ndev)) {
dc19e4e5
NI		 1963 if (netif_msg_tx_queued(mdp))
1964 dev_warn(&ndev->dev, "TxFD exhausted.\n");
86a74ff2
NI		 1965 netif_stop_queue(ndev);
1966 spin_unlock_irqrestore(&mdp->lock, flags);
5b548140 1967 return NETDEV_TX_BUSY;
86a74ff2
NI		 1968 }
1969 }
1970 spin_unlock_irqrestore(&mdp->lock, flags);
1971
525b8075 1972 entry = mdp->cur_tx % mdp->num_tx_ring;
86a74ff2
NI		 1973 mdp->tx_skbuff[entry] = skb;
1974 txdesc = &mdp->tx_ring[entry];
86a74ff2 1975 /* soft swap. */
380af9e3
YS		 1976 if (!mdp->cd->hw_swap)
1977 sh_eth_soft_swap(phys_to_virt(ALIGN(txdesc->addr, 4)),
1978 skb->len + 2);
31fcb99d
YS		 1979 txdesc->addr = dma_map_single(&ndev->dev, skb->data, skb->len,
1980 DMA_TO_DEVICE);
86a74ff2
NI		 1981 if (skb->len < ETHERSMALL)
1982 txdesc->buffer_length = ETHERSMALL;
1983 else
1984 txdesc->buffer_length = skb->len;
1985
525b8075 1986 if (entry >= mdp->num_tx_ring - 1)
71557a37 1987 txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE);
86a74ff2 1988 else
71557a37 1989 txdesc->status |= cpu_to_edmac(mdp, TD_TACT);
86a74ff2
NI		 1990
1991 mdp->cur_tx++;
1992
c5ed5368
YS		 1993 if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
1994 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
b0ca2a21 1995
6ed10654 1996 return NETDEV_TX_OK;
86a74ff2
NI		 1997}
1998
1999/* device close function */
2000static int sh_eth_close(struct net_device *ndev)
2001{
2002 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2 2003
3719109d
SS		 2004 napi_disable(&mdp->napi);
2005
86a74ff2
NI		 2006 netif_stop_queue(ndev);
2007
2008 /* Disable interrupts by clearing the interrupt mask. */
4a55530f 2009 sh_eth_write(ndev, 0x0000, EESIPR);
86a74ff2
NI		 2010
2011 /* Stop the chip's Tx and Rx processes. */
4a55530f
YS		 2012 sh_eth_write(ndev, 0, EDTRR);
2013 sh_eth_write(ndev, 0, EDRRR);
86a74ff2
NI		 2014
2015 /* PHY Disconnect */
2016 if (mdp->phydev) {
2017 phy_stop(mdp->phydev);
2018 phy_disconnect(mdp->phydev);
2019 }
2020
2021 free_irq(ndev->irq, ndev);
2022
86a74ff2
NI		 2023 /* Free all the skbuffs in the Rx queue. */
2024 sh_eth_ring_free(ndev);
2025
2026 /* free DMA buffer */
91c77550 2027 sh_eth_free_dma_buffer(mdp);
86a74ff2 2028
bcd5149d
MD		 2029 pm_runtime_put_sync(&mdp->pdev->dev);
2030
86a74ff2
NI		 2031 return 0;
2032}
2033
2034static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
2035{
2036 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2 2037
bcd5149d
MD		 2038 pm_runtime_get_sync(&mdp->pdev->dev);
2039
bb7d92e3 2040 ndev->stats.tx_dropped += sh_eth_read(ndev, TROCR);
4a55530f 2041 sh_eth_write(ndev, 0, TROCR); /* (write clear) */
bb7d92e3 2042 ndev->stats.collisions += sh_eth_read(ndev, CDCR);
4a55530f 2043 sh_eth_write(ndev, 0, CDCR); /* (write clear) */
bb7d92e3 2044 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, LCCR);
4a55530f 2045 sh_eth_write(ndev, 0, LCCR); /* (write clear) */
c5ed5368 2046 if (sh_eth_is_gether(mdp)) {
bb7d92e3 2047 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CERCR);
c5ed5368 2048 sh_eth_write(ndev, 0, CERCR); /* (write clear) */
bb7d92e3 2049 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CEECR);
c5ed5368
YS		 2050 sh_eth_write(ndev, 0, CEECR); /* (write clear) */
2051 } else {
bb7d92e3 2052 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CNDCR);
c5ed5368
YS		 2053 sh_eth_write(ndev, 0, CNDCR); /* (write clear) */
2054 }
bcd5149d
MD		 2055 pm_runtime_put_sync(&mdp->pdev->dev);
2056
bb7d92e3 2057 return &ndev->stats;
86a74ff2
NI		 2058}
2059
bb7d92e3 2060/* ioctl to device function */
86a74ff2
NI		 2061static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq,
2062 int cmd)
2063{
2064 struct sh_eth_private *mdp = netdev_priv(ndev);
2065 struct phy_device *phydev = mdp->phydev;
2066
2067 if (!netif_running(ndev))
2068 return -EINVAL;
2069
2070 if (!phydev)
2071 return -ENODEV;
2072
28b04113 2073 return phy_mii_ioctl(phydev, rq, cmd);
86a74ff2
NI		 2074}
2075
6743fe6d
YS		 2076/* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
2077static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp,
2078 int entry)
2079{
2080 return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4);
2081}
2082
2083static u32 sh_eth_tsu_get_post_mask(int entry)
2084{
2085 return 0x0f << (28 - ((entry % 8) * 4));
2086}
2087
2088static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
2089{
2090 return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
2091}
2092
2093static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
2094 int entry)
2095{
2096 struct sh_eth_private *mdp = netdev_priv(ndev);
2097 u32 tmp;
2098 void *reg_offset;
2099
2100 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2101 tmp = ioread32(reg_offset);
2102 iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset);
2103}
2104
2105static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
2106 int entry)
2107{
2108 struct sh_eth_private *mdp = netdev_priv(ndev);
2109 u32 post_mask, ref_mask, tmp;
2110 void *reg_offset;
2111
2112 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2113 post_mask = sh_eth_tsu_get_post_mask(entry);
2114 ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
2115
2116 tmp = ioread32(reg_offset);
2117 iowrite32(tmp & ~post_mask, reg_offset);
2118
2119 /* If other port enables, the function returns "true" */
2120 return tmp & ref_mask;
2121}
2122
2123static int sh_eth_tsu_busy(struct net_device *ndev)
2124{
2125 int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
2126 struct sh_eth_private *mdp = netdev_priv(ndev);
2127
2128 while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
2129 udelay(10);
2130 timeout--;
2131 if (timeout <= 0) {
2132 dev_err(&ndev->dev, "%s: timeout\n", __func__);
2133 return -ETIMEDOUT;
2134 }
2135 }
2136
2137 return 0;
2138}
2139
2140static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg,
2141 const u8 *addr)
2142{
2143 u32 val;
2144
2145 val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
2146 iowrite32(val, reg);
2147 if (sh_eth_tsu_busy(ndev) < 0)
2148 return -EBUSY;
2149
2150 val = addr[4] << 8 | addr[5];
2151 iowrite32(val, reg + 4);
2152 if (sh_eth_tsu_busy(ndev) < 0)
2153 return -EBUSY;
2154
2155 return 0;
2156}
2157
2158static void sh_eth_tsu_read_entry(void *reg, u8 *addr)
2159{
2160 u32 val;
2161
2162 val = ioread32(reg);
2163 addr[0] = (val >> 24) & 0xff;
2164 addr[1] = (val >> 16) & 0xff;
2165 addr[2] = (val >> 8) & 0xff;
2166 addr[3] = val & 0xff;
2167 val = ioread32(reg + 4);
2168 addr[4] = (val >> 8) & 0xff;
2169 addr[5] = val & 0xff;
2170}
2171
2172
2173static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
2174{
2175 struct sh_eth_private *mdp = netdev_priv(ndev);
2176 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2177 int i;
2178 u8 c_addr[ETH_ALEN];
2179
2180 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2181 sh_eth_tsu_read_entry(reg_offset, c_addr);
2182 if (memcmp(addr, c_addr, ETH_ALEN) == 0)
2183 return i;
2184 }
2185
2186 return -ENOENT;
2187}
2188
2189static int sh_eth_tsu_find_empty(struct net_device *ndev)
2190{
2191 u8 blank[ETH_ALEN];
2192 int entry;
2193
2194 memset(blank, 0, sizeof(blank));
2195 entry = sh_eth_tsu_find_entry(ndev, blank);
2196 return (entry < 0) ? -ENOMEM : entry;
2197}
2198
2199static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
2200 int entry)
2201{
2202 struct sh_eth_private *mdp = netdev_priv(ndev);
2203 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2204 int ret;
2205 u8 blank[ETH_ALEN];
2206
2207 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
2208 ~(1 << (31 - entry)), TSU_TEN);
2209
2210 memset(blank, 0, sizeof(blank));
2211 ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
2212 if (ret < 0)
2213 return ret;
2214 return 0;
2215}
2216
2217static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
2218{
2219 struct sh_eth_private *mdp = netdev_priv(ndev);
2220 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2221 int i, ret;
2222
2223 if (!mdp->cd->tsu)
2224 return 0;
2225
2226 i = sh_eth_tsu_find_entry(ndev, addr);
2227 if (i < 0) {
2228 /* No entry found, create one */
2229 i = sh_eth_tsu_find_empty(ndev);
2230 if (i < 0)
2231 return -ENOMEM;
2232 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
2233 if (ret < 0)
2234 return ret;
2235
2236 /* Enable the entry */
2237 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
2238 (1 << (31 - i)), TSU_TEN);
2239 }
2240
2241 /* Entry found or created, enable POST */
2242 sh_eth_tsu_enable_cam_entry_post(ndev, i);
2243
2244 return 0;
2245}
2246
2247static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
2248{
2249 struct sh_eth_private *mdp = netdev_priv(ndev);
2250 int i, ret;
2251
2252 if (!mdp->cd->tsu)
2253 return 0;
2254
2255 i = sh_eth_tsu_find_entry(ndev, addr);
2256 if (i) {
2257 /* Entry found */
2258 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2259 goto done;
2260
2261 /* Disable the entry if both ports was disabled */
2262 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2263 if (ret < 0)
2264 return ret;
2265 }
2266done:
2267 return 0;
2268}
2269
2270static int sh_eth_tsu_purge_all(struct net_device *ndev)
2271{
2272 struct sh_eth_private *mdp = netdev_priv(ndev);
2273 int i, ret;
2274
2275 if (unlikely(!mdp->cd->tsu))
2276 return 0;
2277
2278 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
2279 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2280 continue;
2281
2282 /* Disable the entry if both ports was disabled */
2283 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2284 if (ret < 0)
2285 return ret;
2286 }
2287
2288 return 0;
2289}
2290
2291static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
2292{
2293 struct sh_eth_private *mdp = netdev_priv(ndev);
2294 u8 addr[ETH_ALEN];
2295 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2296 int i;
2297
2298 if (unlikely(!mdp->cd->tsu))
2299 return;
2300
2301 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2302 sh_eth_tsu_read_entry(reg_offset, addr);
2303 if (is_multicast_ether_addr(addr))
2304 sh_eth_tsu_del_entry(ndev, addr);
2305 }
2306}
2307
86a74ff2
NI		 2308/* Multicast reception directions set */
2309static void sh_eth_set_multicast_list(struct net_device *ndev)
2310{
6743fe6d
YS		 2311 struct sh_eth_private *mdp = netdev_priv(ndev);
2312 u32 ecmr_bits;
2313 int mcast_all = 0;
2314 unsigned long flags;
2315
2316 spin_lock_irqsave(&mdp->lock, flags);
2317 /*
2318 * Initial condition is MCT = 1, PRM = 0.
2319 * Depending on ndev->flags, set PRM or clear MCT
2320 */
2321 ecmr_bits = (sh_eth_read(ndev, ECMR) & ~ECMR_PRM) | ECMR_MCT;
2322
2323 if (!(ndev->flags & IFF_MULTICAST)) {
2324 sh_eth_tsu_purge_mcast(ndev);
2325 mcast_all = 1;
2326 }
2327 if (ndev->flags & IFF_ALLMULTI) {
2328 sh_eth_tsu_purge_mcast(ndev);
2329 ecmr_bits &= ~ECMR_MCT;
2330 mcast_all = 1;
2331 }
2332
86a74ff2 2333 if (ndev->flags & IFF_PROMISC) {
6743fe6d
YS		 2334 sh_eth_tsu_purge_all(ndev);
2335 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2336 } else if (mdp->cd->tsu) {
2337 struct netdev_hw_addr *ha;
2338 netdev_for_each_mc_addr(ha, ndev) {
2339 if (mcast_all && is_multicast_ether_addr(ha->addr))
2340 continue;
2341
2342 if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2343 if (!mcast_all) {
2344 sh_eth_tsu_purge_mcast(ndev);
2345 ecmr_bits &= ~ECMR_MCT;
2346 mcast_all = 1;
2347 }
2348 }
2349 }
86a74ff2
NI		 2350 } else {
2351 /* Normal, unicast/broadcast-only mode. */
6743fe6d 2352 ecmr_bits = (ecmr_bits & ~ECMR_PRM) | ECMR_MCT;
86a74ff2 2353 }
6743fe6d
YS		 2354
2355 /* update the ethernet mode */
2356 sh_eth_write(ndev, ecmr_bits, ECMR);
2357
2358 spin_unlock_irqrestore(&mdp->lock, flags);
86a74ff2 2359}
71cc7c37
YS		 2360
2361static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2362{
2363 if (!mdp->port)
2364 return TSU_VTAG0;
2365 else
2366 return TSU_VTAG1;
2367}
2368
80d5c368
PM		 2369static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
2370 __be16 proto, u16 vid)
71cc7c37
YS		 2371{
2372 struct sh_eth_private *mdp = netdev_priv(ndev);
2373 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2374
2375 if (unlikely(!mdp->cd->tsu))
2376 return -EPERM;
2377
2378 /* No filtering if vid = 0 */
2379 if (!vid)
2380 return 0;
2381
2382 mdp->vlan_num_ids++;
2383
2384 /*
2385 * The controller has one VLAN tag HW filter. So, if the filter is
2386 * already enabled, the driver disables it and the filte
2387 */
2388 if (mdp->vlan_num_ids > 1) {
2389 /* disable VLAN filter */
2390 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2391 return 0;
2392 }
2393
2394 sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
2395 vtag_reg_index);
2396
2397 return 0;
2398}
2399
80d5c368
PM		 2400static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
2401 __be16 proto, u16 vid)
71cc7c37
YS		 2402{
2403 struct sh_eth_private *mdp = netdev_priv(ndev);
2404 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2405
2406 if (unlikely(!mdp->cd->tsu))
2407 return -EPERM;
2408
2409 /* No filtering if vid = 0 */
2410 if (!vid)
2411 return 0;
2412
2413 mdp->vlan_num_ids--;
2414 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2415
2416 return 0;
2417}
86a74ff2
NI		 2418
2419/* SuperH's TSU register init function */
4a55530f 2420static void sh_eth_tsu_init(struct sh_eth_private *mdp)
86a74ff2 2421{
4a55530f
YS		 2422 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */
2423 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */
2424 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */
2425 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
2426 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
2427 sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
2428 sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
2429 sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
2430 sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
2431 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
c5ed5368
YS		 2432 if (sh_eth_is_gether(mdp)) {
2433 sh_eth_tsu_write(mdp, 0, TSU_QTAG0); /* Disable QTAG(0->1) */
2434 sh_eth_tsu_write(mdp, 0, TSU_QTAG1); /* Disable QTAG(1->0) */
2435 } else {
2436 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */
2437 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */
2438 }
4a55530f
YS		 2439 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */
2440 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */
2441 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2442 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */
2443 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */
2444 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */
2445 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */
86a74ff2
NI		 2446}
2447
2448/* MDIO bus release function */
2449static int sh_mdio_release(struct net_device *ndev)
2450{
2451 struct mii_bus *bus = dev_get_drvdata(&ndev->dev);
2452
2453 /* unregister mdio bus */
2454 mdiobus_unregister(bus);
2455
2456 /* remove mdio bus info from net_device */
2457 dev_set_drvdata(&ndev->dev, NULL);
2458
2459 /* free bitbang info */
2460 free_mdio_bitbang(bus);
2461
2462 return 0;
2463}
2464
2465/* MDIO bus init function */
b3017e6a
YS		 2466static int sh_mdio_init(struct net_device *ndev, int id,
2467 struct sh_eth_plat_data *pd)
86a74ff2
NI		 2468{
2469 int ret, i;
2470 struct bb_info *bitbang;
2471 struct sh_eth_private *mdp = netdev_priv(ndev);
2472
2473 /* create bit control struct for PHY */
d5e07e69
SS		 2474 bitbang = devm_kzalloc(&ndev->dev, sizeof(struct bb_info),
2475 GFP_KERNEL);
86a74ff2
NI		 2476 if (!bitbang) {
2477 ret = -ENOMEM;
2478 goto out;
2479 }
2480
2481 /* bitbang init */
ae70644d 2482 bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
b3017e6a 2483 bitbang->set_gate = pd->set_mdio_gate;
dfed5e7f
SS		 2484 bitbang->mdi_msk = PIR_MDI;
2485 bitbang->mdo_msk = PIR_MDO;
2486 bitbang->mmd_msk = PIR_MMD;
2487 bitbang->mdc_msk = PIR_MDC;
86a74ff2
NI		 2488 bitbang->ctrl.ops = &bb_ops;
2489
c2e07b3a 2490 /* MII controller setting */
86a74ff2
NI		 2491 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
2492 if (!mdp->mii_bus) {
2493 ret = -ENOMEM;
d5e07e69 2494 goto out;
86a74ff2
NI		 2495 }
2496
2497 /* Hook up MII support for ethtool */
2498 mdp->mii_bus->name = "sh_mii";
18ee49dd 2499 mdp->mii_bus->parent = &ndev->dev;
5278fb54 2500 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
34aa6f14 2501 mdp->pdev->name, id);
86a74ff2
NI		 2502
2503 /* PHY IRQ */
d5e07e69
SS		 2504 mdp->mii_bus->irq = devm_kzalloc(&ndev->dev,
2505 sizeof(int) * PHY_MAX_ADDR,
2506 GFP_KERNEL);
86a74ff2
NI		 2507 if (!mdp->mii_bus->irq) {
2508 ret = -ENOMEM;
2509 goto out_free_bus;
2510 }
2511
2512 for (i = 0; i < PHY_MAX_ADDR; i++)
2513 mdp->mii_bus->irq[i] = PHY_POLL;
2514
8f6352f2 2515 /* register mdio bus */
86a74ff2
NI		 2516 ret = mdiobus_register(mdp->mii_bus);
2517 if (ret)
d5e07e69 2518 goto out_free_bus;
86a74ff2
NI		 2519
2520 dev_set_drvdata(&ndev->dev, mdp->mii_bus);
2521
2522 return 0;
2523
86a74ff2 2524out_free_bus:
298cf9be 2525 free_mdio_bitbang(mdp->mii_bus);
86a74ff2 2526
86a74ff2
NI		 2527out:
2528 return ret;
2529}
2530
4a55530f
YS		 2531static const u16 *sh_eth_get_register_offset(int register_type)
2532{
2533 const u16 *reg_offset = NULL;
2534
2535 switch (register_type) {
2536 case SH_ETH_REG_GIGABIT:
2537 reg_offset = sh_eth_offset_gigabit;
2538 break;
a3f109bd
SS		 2539 case SH_ETH_REG_FAST_RCAR:
2540 reg_offset = sh_eth_offset_fast_rcar;
2541 break;
4a55530f
YS		 2542 case SH_ETH_REG_FAST_SH4:
2543 reg_offset = sh_eth_offset_fast_sh4;
2544 break;
2545 case SH_ETH_REG_FAST_SH3_SH2:
2546 reg_offset = sh_eth_offset_fast_sh3_sh2;
2547 break;
2548 default:
14c3326a 2549 pr_err("Unknown register type (%d)\n", register_type);
4a55530f
YS		 2550 break;
2551 }
2552
2553 return reg_offset;
2554}
2555
8f728d79 2556static const struct net_device_ops sh_eth_netdev_ops = {
ebf84eaa
AB		 2557 .ndo_open = sh_eth_open,
2558 .ndo_stop = sh_eth_close,
2559 .ndo_start_xmit = sh_eth_start_xmit,
2560 .ndo_get_stats = sh_eth_get_stats,
ebf84eaa
AB		 2561 .ndo_tx_timeout = sh_eth_tx_timeout,
2562 .ndo_do_ioctl = sh_eth_do_ioctl,
2563 .ndo_validate_addr = eth_validate_addr,
2564 .ndo_set_mac_address = eth_mac_addr,
2565 .ndo_change_mtu = eth_change_mtu,
2566};
2567
8f728d79
SS		 2568static const struct net_device_ops sh_eth_netdev_ops_tsu = {
2569 .ndo_open = sh_eth_open,
2570 .ndo_stop = sh_eth_close,
2571 .ndo_start_xmit = sh_eth_start_xmit,
2572 .ndo_get_stats = sh_eth_get_stats,
2573 .ndo_set_rx_mode = sh_eth_set_multicast_list,
2574 .ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid,
2575 .ndo_vlan_rx_kill_vid = sh_eth_vlan_rx_kill_vid,
2576 .ndo_tx_timeout = sh_eth_tx_timeout,
2577 .ndo_do_ioctl = sh_eth_do_ioctl,
2578 .ndo_validate_addr = eth_validate_addr,
2579 .ndo_set_mac_address = eth_mac_addr,
2580 .ndo_change_mtu = eth_change_mtu,
2581};
2582
86a74ff2
NI		 2583static int sh_eth_drv_probe(struct platform_device *pdev)
2584{
9c38657c 2585 int ret, devno = 0;
86a74ff2
NI		 2586 struct resource *res;
2587 struct net_device *ndev = NULL;
ec0d7551 2588 struct sh_eth_private *mdp = NULL;
564044b0 2589 struct sh_eth_plat_data *pd = pdev->dev.platform_data;
afe391ad 2590 const struct platform_device_id *id = platform_get_device_id(pdev);
86a74ff2
NI		 2591
2592 /* get base addr */
2593 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2594 if (unlikely(res == NULL)) {
2595 dev_err(&pdev->dev, "invalid resource\n");
2596 ret = -EINVAL;
2597 goto out;
2598 }
2599
2600 ndev = alloc_etherdev(sizeof(struct sh_eth_private));
2601 if (!ndev) {
86a74ff2
NI		 2602 ret = -ENOMEM;
2603 goto out;
2604 }
2605
2606 /* The sh Ether-specific entries in the device structure. */
2607 ndev->base_addr = res->start;
2608 devno = pdev->id;
2609 if (devno < 0)
2610 devno = 0;
2611
2612 ndev->dma = -1;
cc3c080d 2613 ret = platform_get_irq(pdev, 0);
2614 if (ret < 0) {
86a74ff2
NI		 2615 ret = -ENODEV;
2616 goto out_release;
2617 }
cc3c080d 2618 ndev->irq = ret;
86a74ff2
NI		 2619
2620 SET_NETDEV_DEV(ndev, &pdev->dev);
2621
2622 /* Fill in the fields of the device structure with ethernet values. */
2623 ether_setup(ndev);
2624
2625 mdp = netdev_priv(ndev);
525b8075
YS		 2626 mdp->num_tx_ring = TX_RING_SIZE;
2627 mdp->num_rx_ring = RX_RING_SIZE;
d5e07e69
SS		 2628 mdp->addr = devm_ioremap_resource(&pdev->dev, res);
2629 if (IS_ERR(mdp->addr)) {
2630 ret = PTR_ERR(mdp->addr);
ae70644d
YS		 2631 goto out_release;
2632 }
2633
86a74ff2 2634 spin_lock_init(&mdp->lock);
bcd5149d
MD		 2635 mdp->pdev = pdev;
2636 pm_runtime_enable(&pdev->dev);
2637 pm_runtime_resume(&pdev->dev);
86a74ff2
NI		 2638
2639 /* get PHY ID */
71557a37 2640 mdp->phy_id = pd->phy;
e47c9052 2641 mdp->phy_interface = pd->phy_interface;
71557a37
YS		 2642 /* EDMAC endian */
2643 mdp->edmac_endian = pd->edmac_endian;
4923576b
YS		 2644 mdp->no_ether_link = pd->no_ether_link;
2645 mdp->ether_link_active_low = pd->ether_link_active_low;
4a55530f 2646 mdp->reg_offset = sh_eth_get_register_offset(pd->register_type);
86a74ff2 2647
380af9e3 2648 /* set cpu data */
589ebdef 2649 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data;
380af9e3
YS		 2650 sh_eth_set_default_cpu_data(mdp->cd);
2651
86a74ff2 2652 /* set function */
8f728d79
SS		 2653 if (mdp->cd->tsu)
2654 ndev->netdev_ops = &sh_eth_netdev_ops_tsu;
2655 else
2656 ndev->netdev_ops = &sh_eth_netdev_ops;
dc19e4e5 2657 SET_ETHTOOL_OPS(ndev, &sh_eth_ethtool_ops);
86a74ff2
NI		 2658 ndev->watchdog_timeo = TX_TIMEOUT;
2659
dc19e4e5
NI		 2660 /* debug message level */
2661 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
86a74ff2
NI		 2662
2663 /* read and set MAC address */
748031f9 2664 read_mac_address(ndev, pd->mac_addr);
ff6e7228
SS		 2665 if (!is_valid_ether_addr(ndev->dev_addr)) {
2666 dev_warn(&pdev->dev,
2667 "no valid MAC address supplied, using a random one.\n");
2668 eth_hw_addr_random(ndev);
2669 }
86a74ff2 2670
6ba88021
YS		 2671 /* ioremap the TSU registers */
2672 if (mdp->cd->tsu) {
2673 struct resource *rtsu;
2674 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
d5e07e69
SS		 2675 mdp->tsu_addr = devm_ioremap_resource(&pdev->dev, rtsu);
2676 if (IS_ERR(mdp->tsu_addr)) {
2677 ret = PTR_ERR(mdp->tsu_addr);
fc0c0900
SS		 2678 goto out_release;
2679 }
6743fe6d 2680 mdp->port = devno % 2;
f646968f 2681 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER;
6ba88021
YS		 2682 }
2683
150647fb
YS		 2684 /* initialize first or needed device */
2685 if (!devno || pd->needs_init) {
380af9e3
YS		 2686 if (mdp->cd->chip_reset)
2687 mdp->cd->chip_reset(ndev);
86a74ff2 2688
4986b996
YS		 2689 if (mdp->cd->tsu) {
2690 /* TSU init (Init only)*/
2691 sh_eth_tsu_init(mdp);
2692 }
86a74ff2
NI		 2693 }
2694
3719109d
SS		 2695 netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64);
2696
86a74ff2
NI		 2697 /* network device register */
2698 ret = register_netdev(ndev);
2699 if (ret)
3719109d 2700 goto out_napi_del;
86a74ff2
NI		 2701
2702 /* mdio bus init */
b3017e6a 2703 ret = sh_mdio_init(ndev, pdev->id, pd);
86a74ff2
NI		 2704 if (ret)
2705 goto out_unregister;
2706
25985edc 2707 /* print device information */
6cd9b49d
HS		 2708 pr_info("Base address at 0x%x, %pM, IRQ %d.\n",
2709 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
86a74ff2
NI		 2710
2711 platform_set_drvdata(pdev, ndev);
2712
2713 return ret;
2714
2715out_unregister:
2716 unregister_netdev(ndev);
2717
3719109d
SS		 2718out_napi_del:
2719 netif_napi_del(&mdp->napi);
2720
86a74ff2
NI		 2721out_release:
2722 /* net_dev free */
2723 if (ndev)
2724 free_netdev(ndev);
2725
2726out:
2727 return ret;
2728}
2729
2730static int sh_eth_drv_remove(struct platform_device *pdev)
2731{
2732 struct net_device *ndev = platform_get_drvdata(pdev);
3719109d 2733 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 2734
2735 sh_mdio_release(ndev);
2736 unregister_netdev(ndev);
3719109d 2737 netif_napi_del(&mdp->napi);
bcd5149d 2738 pm_runtime_disable(&pdev->dev);
86a74ff2 2739 free_netdev(ndev);
86a74ff2
NI		 2740
2741 return 0;
2742}
2743
540ad1b8 2744#ifdef CONFIG_PM
bcd5149d
MD		 2745static int sh_eth_runtime_nop(struct device *dev)
2746{
2747 /*
2748 * Runtime PM callback shared between ->runtime_suspend()
2749 * and ->runtime_resume(). Simply returns success.
2750 *
2751 * This driver re-initializes all registers after
2752 * pm_runtime_get_sync() anyway so there is no need
2753 * to save and restore registers here.
2754 */
2755 return 0;
2756}
2757
540ad1b8 2758static const struct dev_pm_ops sh_eth_dev_pm_ops = {
bcd5149d
MD		 2759 .runtime_suspend = sh_eth_runtime_nop,
2760 .runtime_resume = sh_eth_runtime_nop,
2761};
540ad1b8
NI		 2762#define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
2763#else
2764#define SH_ETH_PM_OPS NULL
2765#endif
bcd5149d 2766
afe391ad 2767static struct platform_device_id sh_eth_id_table[] = {
c18a79ab 2768 { "sh7619-ether", (kernel_ulong_t)&sh7619_data },
7bbe150d 2769 { "sh771x-ether", (kernel_ulong_t)&sh771x_data },
9c3beaab 2770 { "sh7724-ether", (kernel_ulong_t)&sh7724_data },
f5d12767 2771 { "sh7734-gether", (kernel_ulong_t)&sh7734_data },
24549e2a
SS		 2772 { "sh7757-ether", (kernel_ulong_t)&sh7757_data },
2773 { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga },
f5d12767 2774 { "sh7763-gether", (kernel_ulong_t)&sh7763_data },
e5c9b4cd 2775 { "r8a7740-gether", (kernel_ulong_t)&r8a7740_data },
589ebdef 2776 { "r8a777x-ether", (kernel_ulong_t)&r8a777x_data },
e18dbf7e 2777 { "r8a7790-ether", (kernel_ulong_t)&r8a7790_data },
afe391ad
SS		 2778 { }
2779};
2780MODULE_DEVICE_TABLE(platform, sh_eth_id_table);
2781
86a74ff2
NI		 2782static struct platform_driver sh_eth_driver = {
2783 .probe = sh_eth_drv_probe,
2784 .remove = sh_eth_drv_remove,
afe391ad 2785 .id_table = sh_eth_id_table,
86a74ff2
NI		 2786 .driver = {
2787 .name = CARDNAME,
540ad1b8 2788 .pm = SH_ETH_PM_OPS,
86a74ff2
NI		 2789 },
2790};
2791
db62f684 2792module_platform_driver(sh_eth_driver);
86a74ff2
NI		 2793
2794MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
2795MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
2796MODULE_LICENSE("GPL v2");
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