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128296fc | 1 | /* SuperH Ethernet device driver |
86a74ff2 | 2 | * |
9b39f05c | 3 | * Copyright (C) 2014 Renesas Electronics Corporation |
f0e81fec | 4 | * Copyright (C) 2006-2012 Nobuhiro Iwamatsu |
b356e978 | 5 | * Copyright (C) 2008-2014 Renesas Solutions Corp. |
9b39f05c | 6 | * Copyright (C) 2013-2017 Cogent Embedded, Inc. |
702eca02 | 7 | * Copyright (C) 2014 Codethink Limited |
86a74ff2 NI |
8 | * |
9 | * This program is free software; you can redistribute it and/or modify it | |
10 | * under the terms and conditions of the GNU General Public License, | |
11 | * version 2, as published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope it will be useful, but WITHOUT | |
14 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
15 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
16 | * more details. | |
86a74ff2 NI |
17 | * |
18 | * The full GNU General Public License is included in this distribution in | |
19 | * the file called "COPYING". | |
20 | */ | |
21 | ||
0654011d YS |
22 | #include <linux/module.h> |
23 | #include <linux/kernel.h> | |
24 | #include <linux/spinlock.h> | |
6a27cded | 25 | #include <linux/interrupt.h> |
86a74ff2 NI |
26 | #include <linux/dma-mapping.h> |
27 | #include <linux/etherdevice.h> | |
28 | #include <linux/delay.h> | |
29 | #include <linux/platform_device.h> | |
30 | #include <linux/mdio-bitbang.h> | |
31 | #include <linux/netdevice.h> | |
b356e978 SS |
32 | #include <linux/of.h> |
33 | #include <linux/of_device.h> | |
34 | #include <linux/of_irq.h> | |
35 | #include <linux/of_net.h> | |
86a74ff2 NI |
36 | #include <linux/phy.h> |
37 | #include <linux/cache.h> | |
38 | #include <linux/io.h> | |
bcd5149d | 39 | #include <linux/pm_runtime.h> |
5a0e3ad6 | 40 | #include <linux/slab.h> |
dc19e4e5 | 41 | #include <linux/ethtool.h> |
fdb37a7f | 42 | #include <linux/if_vlan.h> |
f0e81fec | 43 | #include <linux/clk.h> |
d4fa0e35 | 44 | #include <linux/sh_eth.h> |
702eca02 | 45 | #include <linux/of_mdio.h> |
86a74ff2 NI |
46 | |
47 | #include "sh_eth.h" | |
48 | ||
dc19e4e5 NI |
49 | #define SH_ETH_DEF_MSG_ENABLE \ |
50 | (NETIF_MSG_LINK | \ | |
51 | NETIF_MSG_TIMER | \ | |
52 | NETIF_MSG_RX_ERR| \ | |
53 | NETIF_MSG_TX_ERR) | |
54 | ||
2274d375 SS |
55 | #define SH_ETH_OFFSET_INVALID ((u16)~0) |
56 | ||
3365711d BH |
57 | #define SH_ETH_OFFSET_DEFAULTS \ |
58 | [0 ... SH_ETH_MAX_REGISTER_OFFSET - 1] = SH_ETH_OFFSET_INVALID | |
59 | ||
c0013f6f | 60 | static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = { |
3365711d BH |
61 | SH_ETH_OFFSET_DEFAULTS, |
62 | ||
c0013f6f SS |
63 | [EDSR] = 0x0000, |
64 | [EDMR] = 0x0400, | |
65 | [EDTRR] = 0x0408, | |
66 | [EDRRR] = 0x0410, | |
67 | [EESR] = 0x0428, | |
68 | [EESIPR] = 0x0430, | |
69 | [TDLAR] = 0x0010, | |
70 | [TDFAR] = 0x0014, | |
71 | [TDFXR] = 0x0018, | |
72 | [TDFFR] = 0x001c, | |
73 | [RDLAR] = 0x0030, | |
74 | [RDFAR] = 0x0034, | |
75 | [RDFXR] = 0x0038, | |
76 | [RDFFR] = 0x003c, | |
77 | [TRSCER] = 0x0438, | |
78 | [RMFCR] = 0x0440, | |
79 | [TFTR] = 0x0448, | |
80 | [FDR] = 0x0450, | |
81 | [RMCR] = 0x0458, | |
82 | [RPADIR] = 0x0460, | |
83 | [FCFTR] = 0x0468, | |
84 | [CSMR] = 0x04E4, | |
85 | ||
86 | [ECMR] = 0x0500, | |
87 | [ECSR] = 0x0510, | |
88 | [ECSIPR] = 0x0518, | |
89 | [PIR] = 0x0520, | |
90 | [PSR] = 0x0528, | |
91 | [PIPR] = 0x052c, | |
92 | [RFLR] = 0x0508, | |
93 | [APR] = 0x0554, | |
94 | [MPR] = 0x0558, | |
95 | [PFTCR] = 0x055c, | |
96 | [PFRCR] = 0x0560, | |
97 | [TPAUSER] = 0x0564, | |
98 | [GECMR] = 0x05b0, | |
99 | [BCULR] = 0x05b4, | |
100 | [MAHR] = 0x05c0, | |
101 | [MALR] = 0x05c8, | |
102 | [TROCR] = 0x0700, | |
103 | [CDCR] = 0x0708, | |
104 | [LCCR] = 0x0710, | |
105 | [CEFCR] = 0x0740, | |
106 | [FRECR] = 0x0748, | |
107 | [TSFRCR] = 0x0750, | |
108 | [TLFRCR] = 0x0758, | |
109 | [RFCR] = 0x0760, | |
110 | [CERCR] = 0x0768, | |
111 | [CEECR] = 0x0770, | |
112 | [MAFCR] = 0x0778, | |
113 | [RMII_MII] = 0x0790, | |
114 | ||
115 | [ARSTR] = 0x0000, | |
116 | [TSU_CTRST] = 0x0004, | |
117 | [TSU_FWEN0] = 0x0010, | |
118 | [TSU_FWEN1] = 0x0014, | |
119 | [TSU_FCM] = 0x0018, | |
120 | [TSU_BSYSL0] = 0x0020, | |
121 | [TSU_BSYSL1] = 0x0024, | |
122 | [TSU_PRISL0] = 0x0028, | |
123 | [TSU_PRISL1] = 0x002c, | |
124 | [TSU_FWSL0] = 0x0030, | |
125 | [TSU_FWSL1] = 0x0034, | |
126 | [TSU_FWSLC] = 0x0038, | |
127 | [TSU_QTAG0] = 0x0040, | |
128 | [TSU_QTAG1] = 0x0044, | |
129 | [TSU_FWSR] = 0x0050, | |
130 | [TSU_FWINMK] = 0x0054, | |
131 | [TSU_ADQT0] = 0x0048, | |
132 | [TSU_ADQT1] = 0x004c, | |
133 | [TSU_VTAG0] = 0x0058, | |
134 | [TSU_VTAG1] = 0x005c, | |
135 | [TSU_ADSBSY] = 0x0060, | |
136 | [TSU_TEN] = 0x0064, | |
137 | [TSU_POST1] = 0x0070, | |
138 | [TSU_POST2] = 0x0074, | |
139 | [TSU_POST3] = 0x0078, | |
140 | [TSU_POST4] = 0x007c, | |
141 | [TSU_ADRH0] = 0x0100, | |
c0013f6f SS |
142 | |
143 | [TXNLCR0] = 0x0080, | |
144 | [TXALCR0] = 0x0084, | |
145 | [RXNLCR0] = 0x0088, | |
146 | [RXALCR0] = 0x008c, | |
147 | [FWNLCR0] = 0x0090, | |
148 | [FWALCR0] = 0x0094, | |
149 | [TXNLCR1] = 0x00a0, | |
150 | [TXALCR1] = 0x00a0, | |
151 | [RXNLCR1] = 0x00a8, | |
152 | [RXALCR1] = 0x00ac, | |
153 | [FWNLCR1] = 0x00b0, | |
154 | [FWALCR1] = 0x00b4, | |
155 | }; | |
156 | ||
db893473 | 157 | static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = { |
3365711d BH |
158 | SH_ETH_OFFSET_DEFAULTS, |
159 | ||
db893473 SH |
160 | [EDSR] = 0x0000, |
161 | [EDMR] = 0x0400, | |
162 | [EDTRR] = 0x0408, | |
163 | [EDRRR] = 0x0410, | |
164 | [EESR] = 0x0428, | |
165 | [EESIPR] = 0x0430, | |
166 | [TDLAR] = 0x0010, | |
167 | [TDFAR] = 0x0014, | |
168 | [TDFXR] = 0x0018, | |
169 | [TDFFR] = 0x001c, | |
170 | [RDLAR] = 0x0030, | |
171 | [RDFAR] = 0x0034, | |
172 | [RDFXR] = 0x0038, | |
173 | [RDFFR] = 0x003c, | |
174 | [TRSCER] = 0x0438, | |
175 | [RMFCR] = 0x0440, | |
176 | [TFTR] = 0x0448, | |
177 | [FDR] = 0x0450, | |
178 | [RMCR] = 0x0458, | |
179 | [RPADIR] = 0x0460, | |
180 | [FCFTR] = 0x0468, | |
181 | [CSMR] = 0x04E4, | |
182 | ||
183 | [ECMR] = 0x0500, | |
184 | [RFLR] = 0x0508, | |
185 | [ECSR] = 0x0510, | |
186 | [ECSIPR] = 0x0518, | |
187 | [PIR] = 0x0520, | |
188 | [APR] = 0x0554, | |
189 | [MPR] = 0x0558, | |
190 | [PFTCR] = 0x055c, | |
191 | [PFRCR] = 0x0560, | |
192 | [TPAUSER] = 0x0564, | |
193 | [MAHR] = 0x05c0, | |
194 | [MALR] = 0x05c8, | |
195 | [CEFCR] = 0x0740, | |
196 | [FRECR] = 0x0748, | |
197 | [TSFRCR] = 0x0750, | |
198 | [TLFRCR] = 0x0758, | |
199 | [RFCR] = 0x0760, | |
200 | [MAFCR] = 0x0778, | |
201 | ||
202 | [ARSTR] = 0x0000, | |
203 | [TSU_CTRST] = 0x0004, | |
e1487888 | 204 | [TSU_FWSLC] = 0x0038, |
db893473 SH |
205 | [TSU_VTAG0] = 0x0058, |
206 | [TSU_ADSBSY] = 0x0060, | |
207 | [TSU_TEN] = 0x0064, | |
e1487888 CB |
208 | [TSU_POST1] = 0x0070, |
209 | [TSU_POST2] = 0x0074, | |
210 | [TSU_POST3] = 0x0078, | |
211 | [TSU_POST4] = 0x007c, | |
db893473 | 212 | [TSU_ADRH0] = 0x0100, |
db893473 SH |
213 | |
214 | [TXNLCR0] = 0x0080, | |
215 | [TXALCR0] = 0x0084, | |
216 | [RXNLCR0] = 0x0088, | |
217 | [RXALCR0] = 0x008C, | |
218 | }; | |
219 | ||
a3f109bd | 220 | static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = { |
3365711d BH |
221 | SH_ETH_OFFSET_DEFAULTS, |
222 | ||
a3f109bd SS |
223 | [ECMR] = 0x0300, |
224 | [RFLR] = 0x0308, | |
225 | [ECSR] = 0x0310, | |
226 | [ECSIPR] = 0x0318, | |
227 | [PIR] = 0x0320, | |
228 | [PSR] = 0x0328, | |
229 | [RDMLR] = 0x0340, | |
230 | [IPGR] = 0x0350, | |
231 | [APR] = 0x0354, | |
232 | [MPR] = 0x0358, | |
233 | [RFCF] = 0x0360, | |
234 | [TPAUSER] = 0x0364, | |
235 | [TPAUSECR] = 0x0368, | |
236 | [MAHR] = 0x03c0, | |
237 | [MALR] = 0x03c8, | |
238 | [TROCR] = 0x03d0, | |
239 | [CDCR] = 0x03d4, | |
240 | [LCCR] = 0x03d8, | |
241 | [CNDCR] = 0x03dc, | |
242 | [CEFCR] = 0x03e4, | |
243 | [FRECR] = 0x03e8, | |
244 | [TSFRCR] = 0x03ec, | |
245 | [TLFRCR] = 0x03f0, | |
246 | [RFCR] = 0x03f4, | |
247 | [MAFCR] = 0x03f8, | |
248 | ||
249 | [EDMR] = 0x0200, | |
250 | [EDTRR] = 0x0208, | |
251 | [EDRRR] = 0x0210, | |
252 | [TDLAR] = 0x0218, | |
253 | [RDLAR] = 0x0220, | |
254 | [EESR] = 0x0228, | |
255 | [EESIPR] = 0x0230, | |
256 | [TRSCER] = 0x0238, | |
257 | [RMFCR] = 0x0240, | |
258 | [TFTR] = 0x0248, | |
259 | [FDR] = 0x0250, | |
260 | [RMCR] = 0x0258, | |
261 | [TFUCR] = 0x0264, | |
262 | [RFOCR] = 0x0268, | |
55754f19 | 263 | [RMIIMODE] = 0x026c, |
a3f109bd SS |
264 | [FCFTR] = 0x0270, |
265 | [TRIMD] = 0x027c, | |
266 | }; | |
267 | ||
c0013f6f | 268 | static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = { |
3365711d BH |
269 | SH_ETH_OFFSET_DEFAULTS, |
270 | ||
c0013f6f SS |
271 | [ECMR] = 0x0100, |
272 | [RFLR] = 0x0108, | |
273 | [ECSR] = 0x0110, | |
274 | [ECSIPR] = 0x0118, | |
275 | [PIR] = 0x0120, | |
276 | [PSR] = 0x0128, | |
277 | [RDMLR] = 0x0140, | |
278 | [IPGR] = 0x0150, | |
279 | [APR] = 0x0154, | |
280 | [MPR] = 0x0158, | |
281 | [TPAUSER] = 0x0164, | |
282 | [RFCF] = 0x0160, | |
283 | [TPAUSECR] = 0x0168, | |
284 | [BCFRR] = 0x016c, | |
285 | [MAHR] = 0x01c0, | |
286 | [MALR] = 0x01c8, | |
287 | [TROCR] = 0x01d0, | |
288 | [CDCR] = 0x01d4, | |
289 | [LCCR] = 0x01d8, | |
290 | [CNDCR] = 0x01dc, | |
291 | [CEFCR] = 0x01e4, | |
292 | [FRECR] = 0x01e8, | |
293 | [TSFRCR] = 0x01ec, | |
294 | [TLFRCR] = 0x01f0, | |
295 | [RFCR] = 0x01f4, | |
296 | [MAFCR] = 0x01f8, | |
297 | [RTRATE] = 0x01fc, | |
298 | ||
299 | [EDMR] = 0x0000, | |
300 | [EDTRR] = 0x0008, | |
301 | [EDRRR] = 0x0010, | |
302 | [TDLAR] = 0x0018, | |
303 | [RDLAR] = 0x0020, | |
304 | [EESR] = 0x0028, | |
305 | [EESIPR] = 0x0030, | |
306 | [TRSCER] = 0x0038, | |
307 | [RMFCR] = 0x0040, | |
308 | [TFTR] = 0x0048, | |
309 | [FDR] = 0x0050, | |
310 | [RMCR] = 0x0058, | |
311 | [TFUCR] = 0x0064, | |
312 | [RFOCR] = 0x0068, | |
313 | [FCFTR] = 0x0070, | |
314 | [RPADIR] = 0x0078, | |
315 | [TRIMD] = 0x007c, | |
316 | [RBWAR] = 0x00c8, | |
317 | [RDFAR] = 0x00cc, | |
318 | [TBRAR] = 0x00d4, | |
319 | [TDFAR] = 0x00d8, | |
320 | }; | |
321 | ||
322 | static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = { | |
3365711d BH |
323 | SH_ETH_OFFSET_DEFAULTS, |
324 | ||
d8b0426a SS |
325 | [EDMR] = 0x0000, |
326 | [EDTRR] = 0x0004, | |
327 | [EDRRR] = 0x0008, | |
328 | [TDLAR] = 0x000c, | |
329 | [RDLAR] = 0x0010, | |
330 | [EESR] = 0x0014, | |
331 | [EESIPR] = 0x0018, | |
332 | [TRSCER] = 0x001c, | |
333 | [RMFCR] = 0x0020, | |
334 | [TFTR] = 0x0024, | |
335 | [FDR] = 0x0028, | |
336 | [RMCR] = 0x002c, | |
337 | [EDOCR] = 0x0030, | |
338 | [FCFTR] = 0x0034, | |
339 | [RPADIR] = 0x0038, | |
340 | [TRIMD] = 0x003c, | |
341 | [RBWAR] = 0x0040, | |
342 | [RDFAR] = 0x0044, | |
343 | [TBRAR] = 0x004c, | |
344 | [TDFAR] = 0x0050, | |
345 | ||
c0013f6f SS |
346 | [ECMR] = 0x0160, |
347 | [ECSR] = 0x0164, | |
348 | [ECSIPR] = 0x0168, | |
349 | [PIR] = 0x016c, | |
350 | [MAHR] = 0x0170, | |
351 | [MALR] = 0x0174, | |
352 | [RFLR] = 0x0178, | |
353 | [PSR] = 0x017c, | |
354 | [TROCR] = 0x0180, | |
355 | [CDCR] = 0x0184, | |
356 | [LCCR] = 0x0188, | |
357 | [CNDCR] = 0x018c, | |
358 | [CEFCR] = 0x0194, | |
359 | [FRECR] = 0x0198, | |
360 | [TSFRCR] = 0x019c, | |
361 | [TLFRCR] = 0x01a0, | |
362 | [RFCR] = 0x01a4, | |
363 | [MAFCR] = 0x01a8, | |
364 | [IPGR] = 0x01b4, | |
365 | [APR] = 0x01b8, | |
366 | [MPR] = 0x01bc, | |
367 | [TPAUSER] = 0x01c4, | |
368 | [BCFR] = 0x01cc, | |
369 | ||
370 | [ARSTR] = 0x0000, | |
371 | [TSU_CTRST] = 0x0004, | |
372 | [TSU_FWEN0] = 0x0010, | |
373 | [TSU_FWEN1] = 0x0014, | |
374 | [TSU_FCM] = 0x0018, | |
375 | [TSU_BSYSL0] = 0x0020, | |
376 | [TSU_BSYSL1] = 0x0024, | |
377 | [TSU_PRISL0] = 0x0028, | |
378 | [TSU_PRISL1] = 0x002c, | |
379 | [TSU_FWSL0] = 0x0030, | |
380 | [TSU_FWSL1] = 0x0034, | |
381 | [TSU_FWSLC] = 0x0038, | |
382 | [TSU_QTAGM0] = 0x0040, | |
383 | [TSU_QTAGM1] = 0x0044, | |
384 | [TSU_ADQT0] = 0x0048, | |
385 | [TSU_ADQT1] = 0x004c, | |
386 | [TSU_FWSR] = 0x0050, | |
387 | [TSU_FWINMK] = 0x0054, | |
388 | [TSU_ADSBSY] = 0x0060, | |
389 | [TSU_TEN] = 0x0064, | |
390 | [TSU_POST1] = 0x0070, | |
391 | [TSU_POST2] = 0x0074, | |
392 | [TSU_POST3] = 0x0078, | |
393 | [TSU_POST4] = 0x007c, | |
394 | ||
395 | [TXNLCR0] = 0x0080, | |
396 | [TXALCR0] = 0x0084, | |
397 | [RXNLCR0] = 0x0088, | |
398 | [RXALCR0] = 0x008c, | |
399 | [FWNLCR0] = 0x0090, | |
400 | [FWALCR0] = 0x0094, | |
401 | [TXNLCR1] = 0x00a0, | |
402 | [TXALCR1] = 0x00a0, | |
403 | [RXNLCR1] = 0x00a8, | |
404 | [RXALCR1] = 0x00ac, | |
405 | [FWNLCR1] = 0x00b0, | |
406 | [FWALCR1] = 0x00b4, | |
407 | ||
408 | [TSU_ADRH0] = 0x0100, | |
c0013f6f SS |
409 | }; |
410 | ||
740c7f31 BH |
411 | static void sh_eth_rcv_snd_disable(struct net_device *ndev); |
412 | static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev); | |
413 | ||
2274d375 SS |
414 | static void sh_eth_write(struct net_device *ndev, u32 data, int enum_index) |
415 | { | |
416 | struct sh_eth_private *mdp = netdev_priv(ndev); | |
417 | u16 offset = mdp->reg_offset[enum_index]; | |
418 | ||
419 | if (WARN_ON(offset == SH_ETH_OFFSET_INVALID)) | |
420 | return; | |
421 | ||
422 | iowrite32(data, mdp->addr + offset); | |
423 | } | |
424 | ||
425 | static u32 sh_eth_read(struct net_device *ndev, int enum_index) | |
426 | { | |
427 | struct sh_eth_private *mdp = netdev_priv(ndev); | |
428 | u16 offset = mdp->reg_offset[enum_index]; | |
429 | ||
430 | if (WARN_ON(offset == SH_ETH_OFFSET_INVALID)) | |
431 | return ~0U; | |
432 | ||
433 | return ioread32(mdp->addr + offset); | |
434 | } | |
435 | ||
b2b14d2f SS |
436 | static void sh_eth_modify(struct net_device *ndev, int enum_index, u32 clear, |
437 | u32 set) | |
438 | { | |
439 | sh_eth_write(ndev, (sh_eth_read(ndev, enum_index) & ~clear) | set, | |
440 | enum_index); | |
441 | } | |
442 | ||
504c8ca5 | 443 | static bool sh_eth_is_gether(struct sh_eth_private *mdp) |
dabdde9e | 444 | { |
504c8ca5 | 445 | return mdp->reg_offset == sh_eth_offset_gigabit; |
dabdde9e NI |
446 | } |
447 | ||
db893473 SH |
448 | static bool sh_eth_is_rz_fast_ether(struct sh_eth_private *mdp) |
449 | { | |
450 | return mdp->reg_offset == sh_eth_offset_fast_rz; | |
451 | } | |
452 | ||
8e994402 | 453 | static void sh_eth_select_mii(struct net_device *ndev) |
5e7a76be | 454 | { |
5e7a76be | 455 | struct sh_eth_private *mdp = netdev_priv(ndev); |
4fa8c3cc | 456 | u32 value; |
5e7a76be NI |
457 | |
458 | switch (mdp->phy_interface) { | |
459 | case PHY_INTERFACE_MODE_GMII: | |
460 | value = 0x2; | |
461 | break; | |
462 | case PHY_INTERFACE_MODE_MII: | |
463 | value = 0x1; | |
464 | break; | |
465 | case PHY_INTERFACE_MODE_RMII: | |
466 | value = 0x0; | |
467 | break; | |
468 | default: | |
f75f14ec SS |
469 | netdev_warn(ndev, |
470 | "PHY interface mode was not setup. Set to MII.\n"); | |
5e7a76be NI |
471 | value = 0x1; |
472 | break; | |
473 | } | |
474 | ||
475 | sh_eth_write(ndev, value, RMII_MII); | |
476 | } | |
5e7a76be | 477 | |
8e994402 | 478 | static void sh_eth_set_duplex(struct net_device *ndev) |
65ac8851 YS |
479 | { |
480 | struct sh_eth_private *mdp = netdev_priv(ndev); | |
65ac8851 | 481 | |
b2b14d2f | 482 | sh_eth_modify(ndev, ECMR, ECMR_DM, mdp->duplex ? ECMR_DM : 0); |
65ac8851 YS |
483 | } |
484 | ||
99f84be6 GU |
485 | static void sh_eth_chip_reset(struct net_device *ndev) |
486 | { | |
487 | struct sh_eth_private *mdp = netdev_priv(ndev); | |
488 | ||
489 | /* reset device */ | |
ec65cfce | 490 | sh_eth_tsu_write(mdp, ARSTR_ARST, ARSTR); |
99f84be6 GU |
491 | mdelay(1); |
492 | } | |
493 | ||
a0f48be3 GU |
494 | static void sh_eth_set_rate_gether(struct net_device *ndev) |
495 | { | |
496 | struct sh_eth_private *mdp = netdev_priv(ndev); | |
497 | ||
498 | switch (mdp->speed) { | |
499 | case 10: /* 10BASE */ | |
500 | sh_eth_write(ndev, GECMR_10, GECMR); | |
501 | break; | |
502 | case 100:/* 100BASE */ | |
503 | sh_eth_write(ndev, GECMR_100, GECMR); | |
504 | break; | |
505 | case 1000: /* 1000BASE */ | |
506 | sh_eth_write(ndev, GECMR_1000, GECMR); | |
507 | break; | |
a0f48be3 GU |
508 | } |
509 | } | |
510 | ||
99f84be6 GU |
511 | #ifdef CONFIG_OF |
512 | /* R7S72100 */ | |
513 | static struct sh_eth_cpu_data r7s72100_data = { | |
514 | .chip_reset = sh_eth_chip_reset, | |
515 | .set_duplex = sh_eth_set_duplex, | |
516 | ||
517 | .register_type = SH_ETH_REG_FAST_RZ, | |
518 | ||
519 | .ecsr_value = ECSR_ICD, | |
520 | .ecsipr_value = ECSIPR_ICDIP, | |
2b2d3eb4 SS |
521 | .eesipr_value = EESIPR_TWB1IP | EESIPR_TWBIP | EESIPR_TC1IP | |
522 | EESIPR_TABTIP | EESIPR_RABTIP | EESIPR_RFCOFIP | | |
523 | EESIPR_ECIIP | | |
524 | EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | | |
525 | EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | | |
526 | EESIPR_RMAFIP | EESIPR_RRFIP | | |
527 | EESIPR_RTLFIP | EESIPR_RTSFIP | | |
528 | EESIPR_PREIP | EESIPR_CERFIP, | |
99f84be6 GU |
529 | |
530 | .tx_check = EESR_TC1 | EESR_FTC, | |
531 | .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | | |
532 | EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE | | |
9b39f05c | 533 | EESR_TDE, |
99f84be6 GU |
534 | .fdr_value = 0x0000070f, |
535 | ||
536 | .no_psr = 1, | |
537 | .apr = 1, | |
538 | .mpr = 1, | |
539 | .tpauser = 1, | |
540 | .hw_swap = 1, | |
541 | .rpadir = 1, | |
542 | .rpadir_value = 2 << 16, | |
543 | .no_trimd = 1, | |
544 | .no_ade = 1, | |
62e04b7e | 545 | .hw_checksum = 1, |
99f84be6 | 546 | .tsu = 1, |
99f84be6 | 547 | }; |
a0f48be3 GU |
548 | |
549 | static void sh_eth_chip_reset_r8a7740(struct net_device *ndev) | |
550 | { | |
c66b2581 | 551 | sh_eth_chip_reset(ndev); |
a0f48be3 GU |
552 | |
553 | sh_eth_select_mii(ndev); | |
554 | } | |
555 | ||
556 | /* R8A7740 */ | |
557 | static struct sh_eth_cpu_data r8a7740_data = { | |
558 | .chip_reset = sh_eth_chip_reset_r8a7740, | |
559 | .set_duplex = sh_eth_set_duplex, | |
560 | .set_rate = sh_eth_set_rate_gether, | |
561 | ||
562 | .register_type = SH_ETH_REG_GIGABIT, | |
563 | ||
564 | .ecsr_value = ECSR_ICD | ECSR_MPD, | |
565 | .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, | |
2b2d3eb4 SS |
566 | .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | |
567 | EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | | |
568 | EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | | |
569 | 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP | | |
570 | EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP | | |
571 | EESIPR_CEEFIP | EESIPR_CELFIP | | |
572 | EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | | |
573 | EESIPR_PREIP | EESIPR_CERFIP, | |
a0f48be3 GU |
574 | |
575 | .tx_check = EESR_TC1 | EESR_FTC, | |
576 | .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | | |
577 | EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE | | |
9b39f05c | 578 | EESR_TDE, |
a0f48be3 GU |
579 | .fdr_value = 0x0000070f, |
580 | ||
581 | .apr = 1, | |
582 | .mpr = 1, | |
583 | .tpauser = 1, | |
584 | .bculr = 1, | |
585 | .hw_swap = 1, | |
586 | .rpadir = 1, | |
587 | .rpadir_value = 2 << 16, | |
588 | .no_trimd = 1, | |
589 | .no_ade = 1, | |
62e04b7e | 590 | .hw_checksum = 1, |
a0f48be3 GU |
591 | .tsu = 1, |
592 | .select_mii = 1, | |
33017e24 | 593 | .magic = 1, |
a0f48be3 | 594 | }; |
99f84be6 | 595 | |
04b0ed2a | 596 | /* There is CPU dependent code */ |
589ebdef | 597 | static void sh_eth_set_rate_r8a777x(struct net_device *ndev) |
65ac8851 YS |
598 | { |
599 | struct sh_eth_private *mdp = netdev_priv(ndev); | |
d0418bb7 | 600 | |
a3f109bd SS |
601 | switch (mdp->speed) { |
602 | case 10: /* 10BASE */ | |
b2b14d2f | 603 | sh_eth_modify(ndev, ECMR, ECMR_ELB, 0); |
a3f109bd SS |
604 | break; |
605 | case 100:/* 100BASE */ | |
b2b14d2f | 606 | sh_eth_modify(ndev, ECMR, ECMR_ELB, ECMR_ELB); |
a3f109bd | 607 | break; |
a3f109bd SS |
608 | } |
609 | } | |
610 | ||
674853b2 | 611 | /* R8A7778/9 */ |
589ebdef | 612 | static struct sh_eth_cpu_data r8a777x_data = { |
a3f109bd | 613 | .set_duplex = sh_eth_set_duplex, |
589ebdef | 614 | .set_rate = sh_eth_set_rate_r8a777x, |
a3f109bd | 615 | |
a3153d8c SS |
616 | .register_type = SH_ETH_REG_FAST_RCAR, |
617 | ||
a3f109bd SS |
618 | .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD, |
619 | .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP, | |
2b2d3eb4 SS |
620 | .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP | |
621 | EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | | |
622 | EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | | |
623 | EESIPR_RMAFIP | EESIPR_RRFIP | | |
624 | EESIPR_RTLFIP | EESIPR_RTSFIP | | |
625 | EESIPR_PREIP | EESIPR_CERFIP, | |
a3f109bd SS |
626 | |
627 | .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO, | |
ca8c3585 | 628 | .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | |
9b39f05c | 629 | EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE, |
d407bc02 | 630 | .fdr_value = 0x00000f0f, |
a3f109bd SS |
631 | |
632 | .apr = 1, | |
633 | .mpr = 1, | |
634 | .tpauser = 1, | |
635 | .hw_swap = 1, | |
636 | }; | |
a3f109bd | 637 | |
94a12b15 SS |
638 | /* R8A7790/1 */ |
639 | static struct sh_eth_cpu_data r8a779x_data = { | |
e18dbf7e SH |
640 | .set_duplex = sh_eth_set_duplex, |
641 | .set_rate = sh_eth_set_rate_r8a777x, | |
642 | ||
a3153d8c SS |
643 | .register_type = SH_ETH_REG_FAST_RCAR, |
644 | ||
e410d86d NS |
645 | .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD | ECSR_MPD, |
646 | .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP | | |
647 | ECSIPR_MPDIP, | |
2b2d3eb4 SS |
648 | .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP | |
649 | EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | | |
650 | EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | | |
651 | EESIPR_RMAFIP | EESIPR_RRFIP | | |
652 | EESIPR_RTLFIP | EESIPR_RTSFIP | | |
653 | EESIPR_PREIP | EESIPR_CERFIP, | |
e18dbf7e SH |
654 | |
655 | .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO, | |
ba361cb3 | 656 | .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | |
9b39f05c | 657 | EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE, |
d407bc02 | 658 | .fdr_value = 0x00000f0f, |
e18dbf7e | 659 | |
01fbd3f5 GU |
660 | .trscer_err_mask = DESC_I_RINT8, |
661 | ||
e18dbf7e SH |
662 | .apr = 1, |
663 | .mpr = 1, | |
664 | .tpauser = 1, | |
665 | .hw_swap = 1, | |
666 | .rmiimode = 1, | |
e410d86d | 667 | .magic = 1, |
e18dbf7e | 668 | }; |
c74a2248 | 669 | #endif /* CONFIG_OF */ |
e18dbf7e | 670 | |
9c3beaab | 671 | static void sh_eth_set_rate_sh7724(struct net_device *ndev) |
a3f109bd SS |
672 | { |
673 | struct sh_eth_private *mdp = netdev_priv(ndev); | |
65ac8851 YS |
674 | |
675 | switch (mdp->speed) { | |
676 | case 10: /* 10BASE */ | |
b2b14d2f | 677 | sh_eth_modify(ndev, ECMR, ECMR_RTM, 0); |
65ac8851 YS |
678 | break; |
679 | case 100:/* 100BASE */ | |
b2b14d2f | 680 | sh_eth_modify(ndev, ECMR, ECMR_RTM, ECMR_RTM); |
65ac8851 | 681 | break; |
65ac8851 YS |
682 | } |
683 | } | |
684 | ||
685 | /* SH7724 */ | |
9c3beaab | 686 | static struct sh_eth_cpu_data sh7724_data = { |
65ac8851 | 687 | .set_duplex = sh_eth_set_duplex, |
9c3beaab | 688 | .set_rate = sh_eth_set_rate_sh7724, |
65ac8851 | 689 | |
a3153d8c SS |
690 | .register_type = SH_ETH_REG_FAST_SH4, |
691 | ||
65ac8851 YS |
692 | .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD, |
693 | .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP, | |
2b2d3eb4 SS |
694 | .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP | |
695 | EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | | |
696 | EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | | |
697 | EESIPR_RMAFIP | EESIPR_RRFIP | | |
698 | EESIPR_RTLFIP | EESIPR_RTSFIP | | |
699 | EESIPR_PREIP | EESIPR_CERFIP, | |
65ac8851 YS |
700 | |
701 | .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO, | |
ca8c3585 | 702 | .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | |
9b39f05c | 703 | EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE, |
65ac8851 YS |
704 | |
705 | .apr = 1, | |
706 | .mpr = 1, | |
707 | .tpauser = 1, | |
708 | .hw_swap = 1, | |
503914cf MD |
709 | .rpadir = 1, |
710 | .rpadir_value = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */ | |
65ac8851 | 711 | }; |
5cee1d37 | 712 | |
24549e2a | 713 | static void sh_eth_set_rate_sh7757(struct net_device *ndev) |
f29a3d04 YS |
714 | { |
715 | struct sh_eth_private *mdp = netdev_priv(ndev); | |
f29a3d04 YS |
716 | |
717 | switch (mdp->speed) { | |
718 | case 10: /* 10BASE */ | |
4a55530f | 719 | sh_eth_write(ndev, 0, RTRATE); |
f29a3d04 YS |
720 | break; |
721 | case 100:/* 100BASE */ | |
4a55530f | 722 | sh_eth_write(ndev, 1, RTRATE); |
f29a3d04 | 723 | break; |
f29a3d04 YS |
724 | } |
725 | } | |
726 | ||
727 | /* SH7757 */ | |
24549e2a SS |
728 | static struct sh_eth_cpu_data sh7757_data = { |
729 | .set_duplex = sh_eth_set_duplex, | |
730 | .set_rate = sh_eth_set_rate_sh7757, | |
f29a3d04 | 731 | |
a3153d8c SS |
732 | .register_type = SH_ETH_REG_FAST_SH4, |
733 | ||
2b2d3eb4 SS |
734 | .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | |
735 | EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | | |
736 | EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | | |
737 | 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP | | |
738 | EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP | | |
739 | EESIPR_CEEFIP | EESIPR_CELFIP | | |
740 | EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | | |
741 | EESIPR_PREIP | EESIPR_CERFIP, | |
f29a3d04 YS |
742 | |
743 | .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO, | |
ca8c3585 | 744 | .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | |
9b39f05c | 745 | EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE, |
f29a3d04 | 746 | |
5b3dfd13 | 747 | .irq_flags = IRQF_SHARED, |
f29a3d04 YS |
748 | .apr = 1, |
749 | .mpr = 1, | |
750 | .tpauser = 1, | |
751 | .hw_swap = 1, | |
752 | .no_ade = 1, | |
2e98e797 YS |
753 | .rpadir = 1, |
754 | .rpadir_value = 2 << 16, | |
6b4b4fea | 755 | .rtrate = 1, |
f29a3d04 | 756 | }; |
65ac8851 | 757 | |
e403d295 | 758 | #define SH_GIGA_ETH_BASE 0xfee00000UL |
8fcd4961 YS |
759 | #define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8) |
760 | #define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0) | |
761 | static void sh_eth_chip_reset_giga(struct net_device *ndev) | |
762 | { | |
0799c2d6 | 763 | u32 mahr[2], malr[2]; |
79270922 | 764 | int i; |
8fcd4961 YS |
765 | |
766 | /* save MAHR and MALR */ | |
767 | for (i = 0; i < 2; i++) { | |
ae70644d YS |
768 | malr[i] = ioread32((void *)GIGA_MALR(i)); |
769 | mahr[i] = ioread32((void *)GIGA_MAHR(i)); | |
8fcd4961 YS |
770 | } |
771 | ||
c66b2581 | 772 | sh_eth_chip_reset(ndev); |
8fcd4961 YS |
773 | |
774 | /* restore MAHR and MALR */ | |
775 | for (i = 0; i < 2; i++) { | |
ae70644d YS |
776 | iowrite32(malr[i], (void *)GIGA_MALR(i)); |
777 | iowrite32(mahr[i], (void *)GIGA_MAHR(i)); | |
8fcd4961 YS |
778 | } |
779 | } | |
780 | ||
8fcd4961 YS |
781 | static void sh_eth_set_rate_giga(struct net_device *ndev) |
782 | { | |
783 | struct sh_eth_private *mdp = netdev_priv(ndev); | |
784 | ||
785 | switch (mdp->speed) { | |
786 | case 10: /* 10BASE */ | |
787 | sh_eth_write(ndev, 0x00000000, GECMR); | |
788 | break; | |
789 | case 100:/* 100BASE */ | |
790 | sh_eth_write(ndev, 0x00000010, GECMR); | |
791 | break; | |
792 | case 1000: /* 1000BASE */ | |
793 | sh_eth_write(ndev, 0x00000020, GECMR); | |
794 | break; | |
8fcd4961 YS |
795 | } |
796 | } | |
797 | ||
798 | /* SH7757(GETHERC) */ | |
24549e2a | 799 | static struct sh_eth_cpu_data sh7757_data_giga = { |
8fcd4961 | 800 | .chip_reset = sh_eth_chip_reset_giga, |
04b0ed2a | 801 | .set_duplex = sh_eth_set_duplex, |
8fcd4961 YS |
802 | .set_rate = sh_eth_set_rate_giga, |
803 | ||
a3153d8c SS |
804 | .register_type = SH_ETH_REG_GIGABIT, |
805 | ||
8fcd4961 YS |
806 | .ecsr_value = ECSR_ICD | ECSR_MPD, |
807 | .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, | |
2b2d3eb4 SS |
808 | .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | |
809 | EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | | |
810 | EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | | |
811 | 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP | | |
812 | EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP | | |
813 | EESIPR_CEEFIP | EESIPR_CELFIP | | |
814 | EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | | |
815 | EESIPR_PREIP | EESIPR_CERFIP, | |
8fcd4961 YS |
816 | |
817 | .tx_check = EESR_TC1 | EESR_FTC, | |
ca8c3585 SS |
818 | .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | |
819 | EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE | | |
9b39f05c | 820 | EESR_TDE, |
8fcd4961 | 821 | .fdr_value = 0x0000072f, |
8fcd4961 | 822 | |
5b3dfd13 | 823 | .irq_flags = IRQF_SHARED, |
8fcd4961 YS |
824 | .apr = 1, |
825 | .mpr = 1, | |
826 | .tpauser = 1, | |
827 | .bculr = 1, | |
828 | .hw_swap = 1, | |
829 | .rpadir = 1, | |
830 | .rpadir_value = 2 << 16, | |
831 | .no_trimd = 1, | |
832 | .no_ade = 1, | |
3acbc971 | 833 | .tsu = 1, |
8fcd4961 YS |
834 | }; |
835 | ||
f5d12767 SS |
836 | /* SH7734 */ |
837 | static struct sh_eth_cpu_data sh7734_data = { | |
380af9e3 YS |
838 | .chip_reset = sh_eth_chip_reset, |
839 | .set_duplex = sh_eth_set_duplex, | |
f5d12767 SS |
840 | .set_rate = sh_eth_set_rate_gether, |
841 | ||
a3153d8c SS |
842 | .register_type = SH_ETH_REG_GIGABIT, |
843 | ||
f5d12767 SS |
844 | .ecsr_value = ECSR_ICD | ECSR_MPD, |
845 | .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, | |
2b2d3eb4 SS |
846 | .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | |
847 | EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | | |
848 | EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | | |
849 | EESIPR_DLCIP | EESIPR_CDIP | EESIPR_TROIP | | |
850 | EESIPR_RMAFIP | EESIPR_CEEFIP | EESIPR_CELFIP | | |
851 | EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | | |
852 | EESIPR_PREIP | EESIPR_CERFIP, | |
f5d12767 SS |
853 | |
854 | .tx_check = EESR_TC1 | EESR_FTC, | |
ca8c3585 SS |
855 | .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | |
856 | EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE | | |
9b39f05c | 857 | EESR_TDE, |
f5d12767 SS |
858 | |
859 | .apr = 1, | |
860 | .mpr = 1, | |
861 | .tpauser = 1, | |
862 | .bculr = 1, | |
863 | .hw_swap = 1, | |
864 | .no_trimd = 1, | |
865 | .no_ade = 1, | |
866 | .tsu = 1, | |
62e04b7e | 867 | .hw_checksum = 1, |
f5d12767 | 868 | .select_mii = 1, |
159c2a90 | 869 | .magic = 1, |
f5d12767 SS |
870 | }; |
871 | ||
872 | /* SH7763 */ | |
873 | static struct sh_eth_cpu_data sh7763_data = { | |
874 | .chip_reset = sh_eth_chip_reset, | |
875 | .set_duplex = sh_eth_set_duplex, | |
876 | .set_rate = sh_eth_set_rate_gether, | |
380af9e3 | 877 | |
a3153d8c SS |
878 | .register_type = SH_ETH_REG_GIGABIT, |
879 | ||
380af9e3 YS |
880 | .ecsr_value = ECSR_ICD | ECSR_MPD, |
881 | .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, | |
2b2d3eb4 SS |
882 | .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | |
883 | EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | | |
884 | EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | | |
885 | EESIPR_DLCIP | EESIPR_CDIP | EESIPR_TROIP | | |
886 | EESIPR_RMAFIP | EESIPR_CEEFIP | EESIPR_CELFIP | | |
887 | EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | | |
888 | EESIPR_PREIP | EESIPR_CERFIP, | |
380af9e3 YS |
889 | |
890 | .tx_check = EESR_TC1 | EESR_FTC, | |
128296fc | 891 | .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | |
9b39f05c | 892 | EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE, |
380af9e3 YS |
893 | |
894 | .apr = 1, | |
895 | .mpr = 1, | |
896 | .tpauser = 1, | |
897 | .bculr = 1, | |
898 | .hw_swap = 1, | |
380af9e3 YS |
899 | .no_trimd = 1, |
900 | .no_ade = 1, | |
4986b996 | 901 | .tsu = 1, |
5b3dfd13 | 902 | .irq_flags = IRQF_SHARED, |
267e1d5c | 903 | .magic = 1, |
380af9e3 YS |
904 | }; |
905 | ||
c18a79ab | 906 | static struct sh_eth_cpu_data sh7619_data = { |
a3153d8c SS |
907 | .register_type = SH_ETH_REG_FAST_SH3_SH2, |
908 | ||
2b2d3eb4 SS |
909 | .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | |
910 | EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | | |
911 | EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | | |
912 | 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP | | |
913 | EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP | | |
914 | EESIPR_CEEFIP | EESIPR_CELFIP | | |
915 | EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | | |
916 | EESIPR_PREIP | EESIPR_CERFIP, | |
380af9e3 YS |
917 | |
918 | .apr = 1, | |
919 | .mpr = 1, | |
920 | .tpauser = 1, | |
921 | .hw_swap = 1, | |
922 | }; | |
7bbe150d SS |
923 | |
924 | static struct sh_eth_cpu_data sh771x_data = { | |
a3153d8c SS |
925 | .register_type = SH_ETH_REG_FAST_SH3_SH2, |
926 | ||
2b2d3eb4 SS |
927 | .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | |
928 | EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | | |
929 | EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | | |
930 | 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP | | |
931 | EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP | | |
932 | EESIPR_CEEFIP | EESIPR_CELFIP | | |
933 | EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | | |
934 | EESIPR_PREIP | EESIPR_CERFIP, | |
4986b996 | 935 | .tsu = 1, |
380af9e3 | 936 | }; |
380af9e3 YS |
937 | |
938 | static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd) | |
939 | { | |
940 | if (!cd->ecsr_value) | |
941 | cd->ecsr_value = DEFAULT_ECSR_INIT; | |
942 | ||
943 | if (!cd->ecsipr_value) | |
944 | cd->ecsipr_value = DEFAULT_ECSIPR_INIT; | |
945 | ||
946 | if (!cd->fcftr_value) | |
128296fc | 947 | cd->fcftr_value = DEFAULT_FIFO_F_D_RFF | |
380af9e3 YS |
948 | DEFAULT_FIFO_F_D_RFD; |
949 | ||
950 | if (!cd->fdr_value) | |
951 | cd->fdr_value = DEFAULT_FDR_INIT; | |
952 | ||
380af9e3 YS |
953 | if (!cd->tx_check) |
954 | cd->tx_check = DEFAULT_TX_CHECK; | |
955 | ||
956 | if (!cd->eesr_err_check) | |
957 | cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK; | |
b284fbe3 NI |
958 | |
959 | if (!cd->trscer_err_mask) | |
960 | cd->trscer_err_mask = DEFAULT_TRSCER_ERR_MASK; | |
380af9e3 YS |
961 | } |
962 | ||
5cee1d37 NI |
963 | static int sh_eth_check_reset(struct net_device *ndev) |
964 | { | |
965 | int ret = 0; | |
966 | int cnt = 100; | |
967 | ||
968 | while (cnt > 0) { | |
97717edc | 969 | if (!(sh_eth_read(ndev, EDMR) & EDMR_SRST_GETHER)) |
5cee1d37 NI |
970 | break; |
971 | mdelay(1); | |
972 | cnt--; | |
973 | } | |
9f8c4265 | 974 | if (cnt <= 0) { |
f75f14ec | 975 | netdev_err(ndev, "Device reset failed\n"); |
5cee1d37 NI |
976 | ret = -ETIMEDOUT; |
977 | } | |
978 | return ret; | |
380af9e3 | 979 | } |
dabdde9e NI |
980 | |
981 | static int sh_eth_reset(struct net_device *ndev) | |
982 | { | |
983 | struct sh_eth_private *mdp = netdev_priv(ndev); | |
984 | int ret = 0; | |
985 | ||
db893473 | 986 | if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp)) { |
dabdde9e | 987 | sh_eth_write(ndev, EDSR_ENALL, EDSR); |
b2b14d2f | 988 | sh_eth_modify(ndev, EDMR, EDMR_SRST_GETHER, EDMR_SRST_GETHER); |
dabdde9e NI |
989 | |
990 | ret = sh_eth_check_reset(ndev); | |
991 | if (ret) | |
f738a13d | 992 | return ret; |
dabdde9e NI |
993 | |
994 | /* Table Init */ | |
995 | sh_eth_write(ndev, 0x0, TDLAR); | |
996 | sh_eth_write(ndev, 0x0, TDFAR); | |
997 | sh_eth_write(ndev, 0x0, TDFXR); | |
998 | sh_eth_write(ndev, 0x0, TDFFR); | |
999 | sh_eth_write(ndev, 0x0, RDLAR); | |
1000 | sh_eth_write(ndev, 0x0, RDFAR); | |
1001 | sh_eth_write(ndev, 0x0, RDFXR); | |
1002 | sh_eth_write(ndev, 0x0, RDFFR); | |
1003 | ||
1004 | /* Reset HW CRC register */ | |
62e04b7e | 1005 | if (mdp->cd->hw_checksum) |
dabdde9e NI |
1006 | sh_eth_write(ndev, 0x0, CSMR); |
1007 | ||
1008 | /* Select MII mode */ | |
1009 | if (mdp->cd->select_mii) | |
1010 | sh_eth_select_mii(ndev); | |
1011 | } else { | |
b2b14d2f | 1012 | sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, EDMR_SRST_ETHER); |
dabdde9e | 1013 | mdelay(3); |
b2b14d2f | 1014 | sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, 0); |
dabdde9e NI |
1015 | } |
1016 | ||
dabdde9e NI |
1017 | return ret; |
1018 | } | |
380af9e3 | 1019 | |
380af9e3 YS |
1020 | static void sh_eth_set_receive_align(struct sk_buff *skb) |
1021 | { | |
4d6a949c | 1022 | uintptr_t reserve = (uintptr_t)skb->data & (SH_ETH_RX_ALIGN - 1); |
380af9e3 | 1023 | |
380af9e3 | 1024 | if (reserve) |
4d6a949c | 1025 | skb_reserve(skb, SH_ETH_RX_ALIGN - reserve); |
380af9e3 | 1026 | } |
380af9e3 | 1027 | |
128296fc | 1028 | /* Program the hardware MAC address from dev->dev_addr. */ |
86a74ff2 NI |
1029 | static void update_mac_address(struct net_device *ndev) |
1030 | { | |
4a55530f | 1031 | sh_eth_write(ndev, |
128296fc SS |
1032 | (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) | |
1033 | (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR); | |
4a55530f | 1034 | sh_eth_write(ndev, |
128296fc | 1035 | (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR); |
86a74ff2 NI |
1036 | } |
1037 | ||
128296fc | 1038 | /* Get MAC address from SuperH MAC address register |
86a74ff2 NI |
1039 | * |
1040 | * SuperH's Ethernet device doesn't have 'ROM' to MAC address. | |
1041 | * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g). | |
1042 | * When you want use this device, you must set MAC address in bootloader. | |
1043 | * | |
1044 | */ | |
748031f9 | 1045 | static void read_mac_address(struct net_device *ndev, unsigned char *mac) |
86a74ff2 | 1046 | { |
748031f9 | 1047 | if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) { |
d458cdf7 | 1048 | memcpy(ndev->dev_addr, mac, ETH_ALEN); |
748031f9 | 1049 | } else { |
37742f02 SS |
1050 | u32 mahr = sh_eth_read(ndev, MAHR); |
1051 | u32 malr = sh_eth_read(ndev, MALR); | |
1052 | ||
1053 | ndev->dev_addr[0] = (mahr >> 24) & 0xFF; | |
1054 | ndev->dev_addr[1] = (mahr >> 16) & 0xFF; | |
1055 | ndev->dev_addr[2] = (mahr >> 8) & 0xFF; | |
1056 | ndev->dev_addr[3] = (mahr >> 0) & 0xFF; | |
1057 | ndev->dev_addr[4] = (malr >> 8) & 0xFF; | |
1058 | ndev->dev_addr[5] = (malr >> 0) & 0xFF; | |
748031f9 | 1059 | } |
86a74ff2 NI |
1060 | } |
1061 | ||
0799c2d6 | 1062 | static u32 sh_eth_get_edtrr_trns(struct sh_eth_private *mdp) |
c5ed5368 | 1063 | { |
db893473 | 1064 | if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp)) |
c5ed5368 YS |
1065 | return EDTRR_TRNS_GETHER; |
1066 | else | |
1067 | return EDTRR_TRNS_ETHER; | |
1068 | } | |
1069 | ||
86a74ff2 | 1070 | struct bb_info { |
ae70644d | 1071 | void (*set_gate)(void *addr); |
86a74ff2 | 1072 | struct mdiobb_ctrl ctrl; |
ae70644d | 1073 | void *addr; |
86a74ff2 NI |
1074 | }; |
1075 | ||
39b4b06b | 1076 | static void sh_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set) |
86a74ff2 NI |
1077 | { |
1078 | struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl); | |
78fa3c5c | 1079 | u32 pir; |
b3017e6a YS |
1080 | |
1081 | if (bitbang->set_gate) | |
1082 | bitbang->set_gate(bitbang->addr); | |
1083 | ||
78fa3c5c | 1084 | pir = ioread32(bitbang->addr); |
39b4b06b | 1085 | if (set) |
78fa3c5c | 1086 | pir |= mask; |
86a74ff2 | 1087 | else |
78fa3c5c SS |
1088 | pir &= ~mask; |
1089 | iowrite32(pir, bitbang->addr); | |
39b4b06b SS |
1090 | } |
1091 | ||
1092 | /* Data I/O pin control */ | |
1093 | static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit) | |
1094 | { | |
1095 | sh_mdio_ctrl(ctrl, PIR_MMD, bit); | |
86a74ff2 NI |
1096 | } |
1097 | ||
1098 | /* Set bit data*/ | |
1099 | static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit) | |
1100 | { | |
39b4b06b | 1101 | sh_mdio_ctrl(ctrl, PIR_MDO, bit); |
86a74ff2 NI |
1102 | } |
1103 | ||
1104 | /* Get bit data*/ | |
1105 | static int sh_get_mdio(struct mdiobb_ctrl *ctrl) | |
1106 | { | |
1107 | struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl); | |
b3017e6a YS |
1108 | |
1109 | if (bitbang->set_gate) | |
1110 | bitbang->set_gate(bitbang->addr); | |
1111 | ||
78fa3c5c | 1112 | return (ioread32(bitbang->addr) & PIR_MDI) != 0; |
86a74ff2 NI |
1113 | } |
1114 | ||
1115 | /* MDC pin control */ | |
1116 | static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit) | |
1117 | { | |
39b4b06b | 1118 | sh_mdio_ctrl(ctrl, PIR_MDC, bit); |
86a74ff2 NI |
1119 | } |
1120 | ||
1121 | /* mdio bus control struct */ | |
1122 | static struct mdiobb_ops bb_ops = { | |
1123 | .owner = THIS_MODULE, | |
1124 | .set_mdc = sh_mdc_ctrl, | |
1125 | .set_mdio_dir = sh_mmd_ctrl, | |
1126 | .set_mdio_data = sh_set_mdio, | |
1127 | .get_mdio_data = sh_get_mdio, | |
1128 | }; | |
1129 | ||
1debdc8f SS |
1130 | /* free Tx skb function */ |
1131 | static int sh_eth_tx_free(struct net_device *ndev, bool sent_only) | |
1132 | { | |
1133 | struct sh_eth_private *mdp = netdev_priv(ndev); | |
1134 | struct sh_eth_txdesc *txdesc; | |
1135 | int free_num = 0; | |
1136 | int entry; | |
1137 | bool sent; | |
1138 | ||
1139 | for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) { | |
1140 | entry = mdp->dirty_tx % mdp->num_tx_ring; | |
1141 | txdesc = &mdp->tx_ring[entry]; | |
1142 | sent = !(txdesc->status & cpu_to_le32(TD_TACT)); | |
1143 | if (sent_only && !sent) | |
1144 | break; | |
1145 | /* TACT bit must be checked before all the following reads */ | |
1146 | dma_rmb(); | |
1147 | netif_info(mdp, tx_done, ndev, | |
1148 | "tx entry %d status 0x%08x\n", | |
1149 | entry, le32_to_cpu(txdesc->status)); | |
1150 | /* Free the original skb. */ | |
1151 | if (mdp->tx_skbuff[entry]) { | |
1152 | dma_unmap_single(&ndev->dev, le32_to_cpu(txdesc->addr), | |
1153 | le32_to_cpu(txdesc->len) >> 16, | |
1154 | DMA_TO_DEVICE); | |
1155 | dev_kfree_skb_irq(mdp->tx_skbuff[entry]); | |
1156 | mdp->tx_skbuff[entry] = NULL; | |
1157 | free_num++; | |
1158 | } | |
1159 | txdesc->status = cpu_to_le32(TD_TFP); | |
1160 | if (entry >= mdp->num_tx_ring - 1) | |
1161 | txdesc->status |= cpu_to_le32(TD_TDLE); | |
1162 | ||
1163 | if (sent) { | |
1164 | ndev->stats.tx_packets++; | |
1165 | ndev->stats.tx_bytes += le32_to_cpu(txdesc->len) >> 16; | |
1166 | } | |
1167 | } | |
1168 | return free_num; | |
1169 | } | |
1170 | ||
86a74ff2 NI |
1171 | /* free skb and descriptor buffer */ |
1172 | static void sh_eth_ring_free(struct net_device *ndev) | |
1173 | { | |
1174 | struct sh_eth_private *mdp = netdev_priv(ndev); | |
8e03a5e7 | 1175 | int ringsize, i; |
86a74ff2 | 1176 | |
1debdc8f SS |
1177 | if (mdp->rx_ring) { |
1178 | for (i = 0; i < mdp->num_rx_ring; i++) { | |
1179 | if (mdp->rx_skbuff[i]) { | |
1180 | struct sh_eth_rxdesc *rxdesc = &mdp->rx_ring[i]; | |
1181 | ||
1182 | dma_unmap_single(&ndev->dev, | |
1183 | le32_to_cpu(rxdesc->addr), | |
1184 | ALIGN(mdp->rx_buf_sz, 32), | |
1185 | DMA_FROM_DEVICE); | |
1186 | } | |
1187 | } | |
1188 | ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring; | |
1189 | dma_free_coherent(NULL, ringsize, mdp->rx_ring, | |
1190 | mdp->rx_desc_dma); | |
1191 | mdp->rx_ring = NULL; | |
1192 | } | |
1193 | ||
86a74ff2 NI |
1194 | /* Free Rx skb ringbuffer */ |
1195 | if (mdp->rx_skbuff) { | |
179d80af SS |
1196 | for (i = 0; i < mdp->num_rx_ring; i++) |
1197 | dev_kfree_skb(mdp->rx_skbuff[i]); | |
86a74ff2 NI |
1198 | } |
1199 | kfree(mdp->rx_skbuff); | |
91c77550 | 1200 | mdp->rx_skbuff = NULL; |
86a74ff2 | 1201 | |
8e03a5e7 | 1202 | if (mdp->tx_ring) { |
1debdc8f SS |
1203 | sh_eth_tx_free(ndev, false); |
1204 | ||
8e03a5e7 SS |
1205 | ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring; |
1206 | dma_free_coherent(NULL, ringsize, mdp->tx_ring, | |
1207 | mdp->tx_desc_dma); | |
1208 | mdp->tx_ring = NULL; | |
1209 | } | |
1debdc8f SS |
1210 | |
1211 | /* Free Tx skb ringbuffer */ | |
1212 | kfree(mdp->tx_skbuff); | |
1213 | mdp->tx_skbuff = NULL; | |
86a74ff2 NI |
1214 | } |
1215 | ||
1216 | /* format skb and descriptor buffer */ | |
1217 | static void sh_eth_ring_format(struct net_device *ndev) | |
1218 | { | |
1219 | struct sh_eth_private *mdp = netdev_priv(ndev); | |
1220 | int i; | |
1221 | struct sk_buff *skb; | |
1222 | struct sh_eth_rxdesc *rxdesc = NULL; | |
1223 | struct sh_eth_txdesc *txdesc = NULL; | |
525b8075 YS |
1224 | int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring; |
1225 | int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring; | |
cb368595 | 1226 | int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1; |
52b9fa36 | 1227 | dma_addr_t dma_addr; |
5cbf20c7 | 1228 | u32 buf_len; |
86a74ff2 | 1229 | |
128296fc SS |
1230 | mdp->cur_rx = 0; |
1231 | mdp->cur_tx = 0; | |
1232 | mdp->dirty_rx = 0; | |
1233 | mdp->dirty_tx = 0; | |
86a74ff2 NI |
1234 | |
1235 | memset(mdp->rx_ring, 0, rx_ringsize); | |
1236 | ||
1237 | /* build Rx ring buffer */ | |
525b8075 | 1238 | for (i = 0; i < mdp->num_rx_ring; i++) { |
86a74ff2 NI |
1239 | /* skb */ |
1240 | mdp->rx_skbuff[i] = NULL; | |
4d6a949c | 1241 | skb = netdev_alloc_skb(ndev, skbuff_size); |
86a74ff2 NI |
1242 | if (skb == NULL) |
1243 | break; | |
380af9e3 YS |
1244 | sh_eth_set_receive_align(skb); |
1245 | ||
ab857916 | 1246 | /* The size of the buffer is a multiple of 32 bytes. */ |
5cbf20c7 | 1247 | buf_len = ALIGN(mdp->rx_buf_sz, 32); |
5cbf20c7 | 1248 | dma_addr = dma_map_single(&ndev->dev, skb->data, buf_len, |
52b9fa36 BH |
1249 | DMA_FROM_DEVICE); |
1250 | if (dma_mapping_error(&ndev->dev, dma_addr)) { | |
1251 | kfree_skb(skb); | |
1252 | break; | |
1253 | } | |
1254 | mdp->rx_skbuff[i] = skb; | |
d0ba9134 SS |
1255 | |
1256 | /* RX descriptor */ | |
1257 | rxdesc = &mdp->rx_ring[i]; | |
1258 | rxdesc->len = cpu_to_le32(buf_len << 16); | |
7cf72477 SS |
1259 | rxdesc->addr = cpu_to_le32(dma_addr); |
1260 | rxdesc->status = cpu_to_le32(RD_RACT | RD_RFP); | |
86a74ff2 | 1261 | |
b0ca2a21 NI |
1262 | /* Rx descriptor address set */ |
1263 | if (i == 0) { | |
4a55530f | 1264 | sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR); |
db893473 SH |
1265 | if (sh_eth_is_gether(mdp) || |
1266 | sh_eth_is_rz_fast_ether(mdp)) | |
c5ed5368 | 1267 | sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR); |
b0ca2a21 | 1268 | } |
86a74ff2 NI |
1269 | } |
1270 | ||
525b8075 | 1271 | mdp->dirty_rx = (u32) (i - mdp->num_rx_ring); |
86a74ff2 NI |
1272 | |
1273 | /* Mark the last entry as wrapping the ring. */ | |
c1b7fca6 SS |
1274 | if (rxdesc) |
1275 | rxdesc->status |= cpu_to_le32(RD_RDLE); | |
86a74ff2 NI |
1276 | |
1277 | memset(mdp->tx_ring, 0, tx_ringsize); | |
1278 | ||
1279 | /* build Tx ring buffer */ | |
525b8075 | 1280 | for (i = 0; i < mdp->num_tx_ring; i++) { |
86a74ff2 NI |
1281 | mdp->tx_skbuff[i] = NULL; |
1282 | txdesc = &mdp->tx_ring[i]; | |
7cf72477 SS |
1283 | txdesc->status = cpu_to_le32(TD_TFP); |
1284 | txdesc->len = cpu_to_le32(0); | |
b0ca2a21 | 1285 | if (i == 0) { |
71557a37 | 1286 | /* Tx descriptor address set */ |
4a55530f | 1287 | sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR); |
db893473 SH |
1288 | if (sh_eth_is_gether(mdp) || |
1289 | sh_eth_is_rz_fast_ether(mdp)) | |
c5ed5368 | 1290 | sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR); |
b0ca2a21 | 1291 | } |
86a74ff2 NI |
1292 | } |
1293 | ||
7cf72477 | 1294 | txdesc->status |= cpu_to_le32(TD_TDLE); |
86a74ff2 NI |
1295 | } |
1296 | ||
1297 | /* Get skb and descriptor buffer */ | |
1298 | static int sh_eth_ring_init(struct net_device *ndev) | |
1299 | { | |
1300 | struct sh_eth_private *mdp = netdev_priv(ndev); | |
91d80683 | 1301 | int rx_ringsize, tx_ringsize; |
86a74ff2 | 1302 | |
128296fc | 1303 | /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the |
86a74ff2 NI |
1304 | * card needs room to do 8 byte alignment, +2 so we can reserve |
1305 | * the first 2 bytes, and +16 gets room for the status word from the | |
1306 | * card. | |
1307 | */ | |
1308 | mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ : | |
1309 | (((ndev->mtu + 26 + 7) & ~7) + 2 + 16)); | |
503914cf MD |
1310 | if (mdp->cd->rpadir) |
1311 | mdp->rx_buf_sz += NET_IP_ALIGN; | |
86a74ff2 NI |
1312 | |
1313 | /* Allocate RX and TX skb rings */ | |
2c94e856 SS |
1314 | mdp->rx_skbuff = kcalloc(mdp->num_rx_ring, sizeof(*mdp->rx_skbuff), |
1315 | GFP_KERNEL); | |
91d80683 SS |
1316 | if (!mdp->rx_skbuff) |
1317 | return -ENOMEM; | |
86a74ff2 | 1318 | |
2c94e856 SS |
1319 | mdp->tx_skbuff = kcalloc(mdp->num_tx_ring, sizeof(*mdp->tx_skbuff), |
1320 | GFP_KERNEL); | |
91d80683 | 1321 | if (!mdp->tx_skbuff) |
8e03a5e7 | 1322 | goto ring_free; |
86a74ff2 NI |
1323 | |
1324 | /* Allocate all Rx descriptors. */ | |
525b8075 | 1325 | rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring; |
86a74ff2 | 1326 | mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma, |
d0320f75 | 1327 | GFP_KERNEL); |
91d80683 | 1328 | if (!mdp->rx_ring) |
8e03a5e7 | 1329 | goto ring_free; |
86a74ff2 NI |
1330 | |
1331 | mdp->dirty_rx = 0; | |
1332 | ||
1333 | /* Allocate all Tx descriptors. */ | |
525b8075 | 1334 | tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring; |
86a74ff2 | 1335 | mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma, |
d0320f75 | 1336 | GFP_KERNEL); |
91d80683 | 1337 | if (!mdp->tx_ring) |
8e03a5e7 | 1338 | goto ring_free; |
91d80683 | 1339 | return 0; |
86a74ff2 | 1340 | |
8e03a5e7 SS |
1341 | ring_free: |
1342 | /* Free Rx and Tx skb ring buffer and DMA buffer */ | |
86a74ff2 NI |
1343 | sh_eth_ring_free(ndev); |
1344 | ||
91d80683 | 1345 | return -ENOMEM; |
86a74ff2 NI |
1346 | } |
1347 | ||
f7967210 | 1348 | static int sh_eth_dev_init(struct net_device *ndev) |
86a74ff2 | 1349 | { |
86a74ff2 | 1350 | struct sh_eth_private *mdp = netdev_priv(ndev); |
4fa8c3cc | 1351 | int ret; |
86a74ff2 NI |
1352 | |
1353 | /* Soft Reset */ | |
5cee1d37 NI |
1354 | ret = sh_eth_reset(ndev); |
1355 | if (ret) | |
f738a13d | 1356 | return ret; |
86a74ff2 | 1357 | |
55754f19 SH |
1358 | if (mdp->cd->rmiimode) |
1359 | sh_eth_write(ndev, 0x1, RMIIMODE); | |
1360 | ||
b0ca2a21 NI |
1361 | /* Descriptor format */ |
1362 | sh_eth_ring_format(ndev); | |
380af9e3 | 1363 | if (mdp->cd->rpadir) |
4a55530f | 1364 | sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR); |
86a74ff2 NI |
1365 | |
1366 | /* all sh_eth int mask */ | |
4a55530f | 1367 | sh_eth_write(ndev, 0, EESIPR); |
86a74ff2 | 1368 | |
10b9194f | 1369 | #if defined(__LITTLE_ENDIAN) |
380af9e3 | 1370 | if (mdp->cd->hw_swap) |
4a55530f | 1371 | sh_eth_write(ndev, EDMR_EL, EDMR); |
380af9e3 | 1372 | else |
b0ca2a21 | 1373 | #endif |
4a55530f | 1374 | sh_eth_write(ndev, 0, EDMR); |
86a74ff2 | 1375 | |
b0ca2a21 | 1376 | /* FIFO size set */ |
4a55530f YS |
1377 | sh_eth_write(ndev, mdp->cd->fdr_value, FDR); |
1378 | sh_eth_write(ndev, 0, TFTR); | |
86a74ff2 | 1379 | |
530aa2d0 BD |
1380 | /* Frame recv control (enable multiple-packets per rx irq) */ |
1381 | sh_eth_write(ndev, RMCR_RNC, RMCR); | |
86a74ff2 | 1382 | |
b284fbe3 | 1383 | sh_eth_write(ndev, mdp->cd->trscer_err_mask, TRSCER); |
86a74ff2 | 1384 | |
380af9e3 | 1385 | if (mdp->cd->bculr) |
4a55530f | 1386 | sh_eth_write(ndev, 0x800, BCULR); /* Burst sycle set */ |
b0ca2a21 | 1387 | |
4a55530f | 1388 | sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR); |
86a74ff2 | 1389 | |
380af9e3 | 1390 | if (!mdp->cd->no_trimd) |
4a55530f | 1391 | sh_eth_write(ndev, 0, TRIMD); |
86a74ff2 | 1392 | |
b0ca2a21 | 1393 | /* Recv frame limit set register */ |
fdb37a7f YS |
1394 | sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, |
1395 | RFLR); | |
86a74ff2 | 1396 | |
b2b14d2f | 1397 | sh_eth_modify(ndev, EESR, 0, 0); |
f7967210 SS |
1398 | mdp->irq_enabled = true; |
1399 | sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR); | |
86a74ff2 NI |
1400 | |
1401 | /* PAUSE Prohibition */ | |
bffa731f SS |
1402 | sh_eth_write(ndev, ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | |
1403 | ECMR_TE | ECMR_RE, ECMR); | |
b0ca2a21 | 1404 | |
380af9e3 YS |
1405 | if (mdp->cd->set_rate) |
1406 | mdp->cd->set_rate(ndev); | |
1407 | ||
b0ca2a21 | 1408 | /* E-MAC Status Register clear */ |
4a55530f | 1409 | sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR); |
b0ca2a21 NI |
1410 | |
1411 | /* E-MAC Interrupt Enable register */ | |
f7967210 | 1412 | sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR); |
86a74ff2 NI |
1413 | |
1414 | /* Set MAC address */ | |
1415 | update_mac_address(ndev); | |
1416 | ||
1417 | /* mask reset */ | |
380af9e3 | 1418 | if (mdp->cd->apr) |
4a55530f | 1419 | sh_eth_write(ndev, APR_AP, APR); |
380af9e3 | 1420 | if (mdp->cd->mpr) |
4a55530f | 1421 | sh_eth_write(ndev, MPR_MP, MPR); |
380af9e3 | 1422 | if (mdp->cd->tpauser) |
4a55530f | 1423 | sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER); |
b0ca2a21 | 1424 | |
f7967210 SS |
1425 | /* Setting the Rx mode will start the Rx process. */ |
1426 | sh_eth_write(ndev, EDRRR_R, EDRRR); | |
86a74ff2 NI |
1427 | |
1428 | return ret; | |
1429 | } | |
1430 | ||
740c7f31 BH |
1431 | static void sh_eth_dev_exit(struct net_device *ndev) |
1432 | { | |
1433 | struct sh_eth_private *mdp = netdev_priv(ndev); | |
1434 | int i; | |
1435 | ||
1436 | /* Deactivate all TX descriptors, so DMA should stop at next | |
1437 | * packet boundary if it's currently running | |
1438 | */ | |
1439 | for (i = 0; i < mdp->num_tx_ring; i++) | |
7cf72477 | 1440 | mdp->tx_ring[i].status &= ~cpu_to_le32(TD_TACT); |
740c7f31 BH |
1441 | |
1442 | /* Disable TX FIFO egress to MAC */ | |
1443 | sh_eth_rcv_snd_disable(ndev); | |
1444 | ||
1445 | /* Stop RX DMA at next packet boundary */ | |
1446 | sh_eth_write(ndev, 0, EDRRR); | |
1447 | ||
1448 | /* Aside from TX DMA, we can't tell when the hardware is | |
1449 | * really stopped, so we need to reset to make sure. | |
1450 | * Before doing that, wait for long enough to *probably* | |
1451 | * finish transmitting the last packet and poll stats. | |
1452 | */ | |
1453 | msleep(2); /* max frame time at 10 Mbps < 1250 us */ | |
1454 | sh_eth_get_stats(ndev); | |
1455 | sh_eth_reset(ndev); | |
a14c7d15 GU |
1456 | |
1457 | /* Set MAC address again */ | |
1458 | update_mac_address(ndev); | |
740c7f31 BH |
1459 | } |
1460 | ||
86a74ff2 | 1461 | /* Packet receive function */ |
3719109d | 1462 | static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota) |
86a74ff2 NI |
1463 | { |
1464 | struct sh_eth_private *mdp = netdev_priv(ndev); | |
1465 | struct sh_eth_rxdesc *rxdesc; | |
1466 | ||
525b8075 YS |
1467 | int entry = mdp->cur_rx % mdp->num_rx_ring; |
1468 | int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx; | |
319cd520 | 1469 | int limit; |
86a74ff2 | 1470 | struct sk_buff *skb; |
380af9e3 | 1471 | u32 desc_status; |
cb368595 | 1472 | int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1; |
52b9fa36 | 1473 | dma_addr_t dma_addr; |
4fa8c3cc | 1474 | u16 pkt_len; |
5cbf20c7 | 1475 | u32 buf_len; |
86a74ff2 | 1476 | |
319cd520 MK |
1477 | boguscnt = min(boguscnt, *quota); |
1478 | limit = boguscnt; | |
86a74ff2 | 1479 | rxdesc = &mdp->rx_ring[entry]; |
7cf72477 | 1480 | while (!(rxdesc->status & cpu_to_le32(RD_RACT))) { |
7d7355f5 | 1481 | /* RACT bit must be checked before all the following reads */ |
f32bfb9a | 1482 | dma_rmb(); |
7cf72477 SS |
1483 | desc_status = le32_to_cpu(rxdesc->status); |
1484 | pkt_len = le32_to_cpu(rxdesc->len) & RD_RFL; | |
86a74ff2 NI |
1485 | |
1486 | if (--boguscnt < 0) | |
1487 | break; | |
1488 | ||
e5fd13f4 BH |
1489 | netif_info(mdp, rx_status, ndev, |
1490 | "rx entry %d status 0x%08x len %d\n", | |
1491 | entry, desc_status, pkt_len); | |
1492 | ||
86a74ff2 | 1493 | if (!(desc_status & RDFEND)) |
bb7d92e3 | 1494 | ndev->stats.rx_length_errors++; |
86a74ff2 | 1495 | |
128296fc | 1496 | /* In case of almost all GETHER/ETHERs, the Receive Frame State |
dd019897 | 1497 | * (RFS) bits in the Receive Descriptor 0 are from bit 9 to |
9b4a6364 BH |
1498 | * bit 0. However, in case of the R8A7740 and R7S72100 |
1499 | * the RFS bits are from bit 25 to bit 16. So, the | |
db893473 | 1500 | * driver needs right shifting by 16. |
dd019897 | 1501 | */ |
62e04b7e | 1502 | if (mdp->cd->hw_checksum) |
ac8025a6 | 1503 | desc_status >>= 16; |
dd019897 | 1504 | |
248be83d | 1505 | skb = mdp->rx_skbuff[entry]; |
86a74ff2 NI |
1506 | if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 | |
1507 | RD_RFS5 | RD_RFS6 | RD_RFS10)) { | |
bb7d92e3 | 1508 | ndev->stats.rx_errors++; |
86a74ff2 | 1509 | if (desc_status & RD_RFS1) |
bb7d92e3 | 1510 | ndev->stats.rx_crc_errors++; |
86a74ff2 | 1511 | if (desc_status & RD_RFS2) |
bb7d92e3 | 1512 | ndev->stats.rx_frame_errors++; |
86a74ff2 | 1513 | if (desc_status & RD_RFS3) |
bb7d92e3 | 1514 | ndev->stats.rx_length_errors++; |
86a74ff2 | 1515 | if (desc_status & RD_RFS4) |
bb7d92e3 | 1516 | ndev->stats.rx_length_errors++; |
86a74ff2 | 1517 | if (desc_status & RD_RFS6) |
bb7d92e3 | 1518 | ndev->stats.rx_missed_errors++; |
86a74ff2 | 1519 | if (desc_status & RD_RFS10) |
bb7d92e3 | 1520 | ndev->stats.rx_over_errors++; |
248be83d | 1521 | } else if (skb) { |
7cf72477 | 1522 | dma_addr = le32_to_cpu(rxdesc->addr); |
380af9e3 YS |
1523 | if (!mdp->cd->hw_swap) |
1524 | sh_eth_soft_swap( | |
1299653a | 1525 | phys_to_virt(ALIGN(dma_addr, 4)), |
380af9e3 | 1526 | pkt_len + 2); |
86a74ff2 | 1527 | mdp->rx_skbuff[entry] = NULL; |
503914cf MD |
1528 | if (mdp->cd->rpadir) |
1529 | skb_reserve(skb, NET_IP_ALIGN); | |
1299653a | 1530 | dma_unmap_single(&ndev->dev, dma_addr, |
ab857916 | 1531 | ALIGN(mdp->rx_buf_sz, 32), |
52b9fa36 | 1532 | DMA_FROM_DEVICE); |
86a74ff2 NI |
1533 | skb_put(skb, pkt_len); |
1534 | skb->protocol = eth_type_trans(skb, ndev); | |
a8e9fd0f | 1535 | netif_receive_skb(skb); |
bb7d92e3 ED |
1536 | ndev->stats.rx_packets++; |
1537 | ndev->stats.rx_bytes += pkt_len; | |
25b77ad7 BH |
1538 | if (desc_status & RD_RFS8) |
1539 | ndev->stats.multicast++; | |
86a74ff2 | 1540 | } |
525b8075 | 1541 | entry = (++mdp->cur_rx) % mdp->num_rx_ring; |
862df497 | 1542 | rxdesc = &mdp->rx_ring[entry]; |
86a74ff2 NI |
1543 | } |
1544 | ||
1545 | /* Refill the Rx ring buffers. */ | |
1546 | for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) { | |
525b8075 | 1547 | entry = mdp->dirty_rx % mdp->num_rx_ring; |
86a74ff2 | 1548 | rxdesc = &mdp->rx_ring[entry]; |
ab857916 | 1549 | /* The size of the buffer is 32 byte boundary. */ |
5cbf20c7 | 1550 | buf_len = ALIGN(mdp->rx_buf_sz, 32); |
7cf72477 | 1551 | rxdesc->len = cpu_to_le32(buf_len << 16); |
b0ca2a21 | 1552 | |
86a74ff2 | 1553 | if (mdp->rx_skbuff[entry] == NULL) { |
4d6a949c | 1554 | skb = netdev_alloc_skb(ndev, skbuff_size); |
86a74ff2 NI |
1555 | if (skb == NULL) |
1556 | break; /* Better luck next round. */ | |
380af9e3 | 1557 | sh_eth_set_receive_align(skb); |
52b9fa36 | 1558 | dma_addr = dma_map_single(&ndev->dev, skb->data, |
5cbf20c7 | 1559 | buf_len, DMA_FROM_DEVICE); |
52b9fa36 BH |
1560 | if (dma_mapping_error(&ndev->dev, dma_addr)) { |
1561 | kfree_skb(skb); | |
1562 | break; | |
1563 | } | |
1564 | mdp->rx_skbuff[entry] = skb; | |
380af9e3 | 1565 | |
bc8acf2c | 1566 | skb_checksum_none_assert(skb); |
7cf72477 | 1567 | rxdesc->addr = cpu_to_le32(dma_addr); |
86a74ff2 | 1568 | } |
f32bfb9a | 1569 | dma_wmb(); /* RACT bit must be set after all the above writes */ |
525b8075 | 1570 | if (entry >= mdp->num_rx_ring - 1) |
86a74ff2 | 1571 | rxdesc->status |= |
7cf72477 | 1572 | cpu_to_le32(RD_RACT | RD_RFP | RD_RDLE); |
86a74ff2 | 1573 | else |
7cf72477 | 1574 | rxdesc->status |= cpu_to_le32(RD_RACT | RD_RFP); |
86a74ff2 NI |
1575 | } |
1576 | ||
1577 | /* Restart Rx engine if stopped. */ | |
1578 | /* If we don't need to check status, don't. -KDU */ | |
79fba9f5 | 1579 | if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) { |
a18e08bd | 1580 | /* fix the values for the next receiving if RDE is set */ |
3365711d BH |
1581 | if (intr_status & EESR_RDE && |
1582 | mdp->reg_offset[RDFAR] != SH_ETH_OFFSET_INVALID) { | |
128296fc SS |
1583 | u32 count = (sh_eth_read(ndev, RDFAR) - |
1584 | sh_eth_read(ndev, RDLAR)) >> 4; | |
1585 | ||
1586 | mdp->cur_rx = count; | |
1587 | mdp->dirty_rx = count; | |
1588 | } | |
4a55530f | 1589 | sh_eth_write(ndev, EDRRR_R, EDRRR); |
79fba9f5 | 1590 | } |
86a74ff2 | 1591 | |
319cd520 MK |
1592 | *quota -= limit - boguscnt - 1; |
1593 | ||
4f809cea | 1594 | return *quota <= 0; |
86a74ff2 NI |
1595 | } |
1596 | ||
4a55530f | 1597 | static void sh_eth_rcv_snd_disable(struct net_device *ndev) |
dc19e4e5 NI |
1598 | { |
1599 | /* disable tx and rx */ | |
b2b14d2f | 1600 | sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0); |
dc19e4e5 NI |
1601 | } |
1602 | ||
4a55530f | 1603 | static void sh_eth_rcv_snd_enable(struct net_device *ndev) |
dc19e4e5 NI |
1604 | { |
1605 | /* enable tx and rx */ | |
b2b14d2f | 1606 | sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE); |
dc19e4e5 NI |
1607 | } |
1608 | ||
9b39f05c SS |
1609 | /* E-MAC interrupt handler */ |
1610 | static void sh_eth_emac_interrupt(struct net_device *ndev) | |
86a74ff2 NI |
1611 | { |
1612 | struct sh_eth_private *mdp = netdev_priv(ndev); | |
86a74ff2 | 1613 | u32 felic_stat; |
380af9e3 | 1614 | u32 link_stat; |
86a74ff2 | 1615 | |
9b39f05c SS |
1616 | felic_stat = sh_eth_read(ndev, ECSR) & sh_eth_read(ndev, ECSIPR); |
1617 | sh_eth_write(ndev, felic_stat, ECSR); /* clear int */ | |
1618 | if (felic_stat & ECSR_ICD) | |
1619 | ndev->stats.tx_carrier_errors++; | |
0cf45a3b NS |
1620 | if (felic_stat & ECSR_MPD) |
1621 | pm_wakeup_event(&mdp->pdev->dev, 0); | |
9b39f05c SS |
1622 | if (felic_stat & ECSR_LCHNG) { |
1623 | /* Link Changed */ | |
1624 | if (mdp->cd->no_psr || mdp->no_ether_link) | |
1625 | return; | |
1626 | link_stat = sh_eth_read(ndev, PSR); | |
1627 | if (mdp->ether_link_active_low) | |
1628 | link_stat = ~link_stat; | |
1629 | if (!(link_stat & PHY_ST_LINK)) { | |
1630 | sh_eth_rcv_snd_disable(ndev); | |
1631 | } else { | |
1632 | /* Link Up */ | |
1a0bee6c | 1633 | sh_eth_modify(ndev, EESIPR, EESIPR_ECIIP, 0); |
9b39f05c SS |
1634 | /* clear int */ |
1635 | sh_eth_modify(ndev, ECSR, 0, 0); | |
1a0bee6c | 1636 | sh_eth_modify(ndev, EESIPR, EESIPR_ECIIP, EESIPR_ECIIP); |
9b39f05c SS |
1637 | /* enable tx and rx */ |
1638 | sh_eth_rcv_snd_enable(ndev); | |
86a74ff2 NI |
1639 | } |
1640 | } | |
9b39f05c SS |
1641 | } |
1642 | ||
1643 | /* error control function */ | |
1644 | static void sh_eth_error(struct net_device *ndev, u32 intr_status) | |
1645 | { | |
1646 | struct sh_eth_private *mdp = netdev_priv(ndev); | |
1647 | u32 mask; | |
86a74ff2 NI |
1648 | |
1649 | if (intr_status & EESR_TWB) { | |
4eb313a7 SS |
1650 | /* Unused write back interrupt */ |
1651 | if (intr_status & EESR_TABT) { /* Transmit Abort int */ | |
bb7d92e3 | 1652 | ndev->stats.tx_aborted_errors++; |
8d5009f6 | 1653 | netif_err(mdp, tx_err, ndev, "Transmit Abort\n"); |
4eb313a7 | 1654 | } |
86a74ff2 NI |
1655 | } |
1656 | ||
1657 | if (intr_status & EESR_RABT) { | |
1658 | /* Receive Abort int */ | |
1659 | if (intr_status & EESR_RFRMER) { | |
1660 | /* Receive Frame Overflow int */ | |
bb7d92e3 | 1661 | ndev->stats.rx_frame_errors++; |
86a74ff2 NI |
1662 | } |
1663 | } | |
380af9e3 | 1664 | |
dc19e4e5 NI |
1665 | if (intr_status & EESR_TDE) { |
1666 | /* Transmit Descriptor Empty int */ | |
bb7d92e3 | 1667 | ndev->stats.tx_fifo_errors++; |
8d5009f6 | 1668 | netif_err(mdp, tx_err, ndev, "Transmit Descriptor Empty\n"); |
dc19e4e5 NI |
1669 | } |
1670 | ||
1671 | if (intr_status & EESR_TFE) { | |
1672 | /* FIFO under flow */ | |
bb7d92e3 | 1673 | ndev->stats.tx_fifo_errors++; |
8d5009f6 | 1674 | netif_err(mdp, tx_err, ndev, "Transmit FIFO Under flow\n"); |
86a74ff2 NI |
1675 | } |
1676 | ||
1677 | if (intr_status & EESR_RDE) { | |
1678 | /* Receive Descriptor Empty int */ | |
bb7d92e3 | 1679 | ndev->stats.rx_over_errors++; |
86a74ff2 | 1680 | } |
dc19e4e5 | 1681 | |
86a74ff2 NI |
1682 | if (intr_status & EESR_RFE) { |
1683 | /* Receive FIFO Overflow int */ | |
bb7d92e3 | 1684 | ndev->stats.rx_fifo_errors++; |
dc19e4e5 NI |
1685 | } |
1686 | ||
1687 | if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) { | |
1688 | /* Address Error */ | |
bb7d92e3 | 1689 | ndev->stats.tx_fifo_errors++; |
8d5009f6 | 1690 | netif_err(mdp, tx_err, ndev, "Address Error\n"); |
86a74ff2 | 1691 | } |
380af9e3 YS |
1692 | |
1693 | mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE; | |
1694 | if (mdp->cd->no_ade) | |
1695 | mask &= ~EESR_ADE; | |
1696 | if (intr_status & mask) { | |
86a74ff2 | 1697 | /* Tx error */ |
4a55530f | 1698 | u32 edtrr = sh_eth_read(ndev, EDTRR); |
090d560f | 1699 | |
86a74ff2 | 1700 | /* dmesg */ |
da246855 SS |
1701 | netdev_err(ndev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n", |
1702 | intr_status, mdp->cur_tx, mdp->dirty_tx, | |
1703 | (u32)ndev->state, edtrr); | |
86a74ff2 | 1704 | /* dirty buffer free */ |
1debdc8f | 1705 | sh_eth_tx_free(ndev, true); |
86a74ff2 NI |
1706 | |
1707 | /* SH7712 BUG */ | |
c5ed5368 | 1708 | if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) { |
86a74ff2 | 1709 | /* tx dma start */ |
c5ed5368 | 1710 | sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR); |
86a74ff2 NI |
1711 | } |
1712 | /* wakeup */ | |
1713 | netif_wake_queue(ndev); | |
1714 | } | |
1715 | } | |
1716 | ||
1717 | static irqreturn_t sh_eth_interrupt(int irq, void *netdev) | |
1718 | { | |
1719 | struct net_device *ndev = netdev; | |
1720 | struct sh_eth_private *mdp = netdev_priv(ndev); | |
380af9e3 | 1721 | struct sh_eth_cpu_data *cd = mdp->cd; |
0e0fde3c | 1722 | irqreturn_t ret = IRQ_NONE; |
0799c2d6 | 1723 | u32 intr_status, intr_enable; |
86a74ff2 | 1724 | |
86a74ff2 NI |
1725 | spin_lock(&mdp->lock); |
1726 | ||
3893b273 | 1727 | /* Get interrupt status */ |
4a55530f | 1728 | intr_status = sh_eth_read(ndev, EESR); |
9b39f05c SS |
1729 | /* Mask it with the interrupt mask, forcing ECI interrupt to be always |
1730 | * enabled since it's the one that comes thru regardless of the mask, | |
1731 | * and we need to fully handle it in sh_eth_emac_interrupt() in order | |
1732 | * to quench it as it doesn't get cleared by just writing 1 to the ECI | |
1733 | * bit... | |
3893b273 | 1734 | */ |
3719109d | 1735 | intr_enable = sh_eth_read(ndev, EESIPR); |
1a0bee6c | 1736 | intr_status &= intr_enable | EESIPR_ECIIP; |
9b39f05c SS |
1737 | if (intr_status & (EESR_RX_CHECK | cd->tx_check | EESR_ECI | |
1738 | cd->eesr_err_check)) | |
0e0fde3c | 1739 | ret = IRQ_HANDLED; |
3719109d | 1740 | else |
283e38db BH |
1741 | goto out; |
1742 | ||
2344ef3c | 1743 | if (unlikely(!mdp->irq_enabled)) { |
283e38db BH |
1744 | sh_eth_write(ndev, 0, EESIPR); |
1745 | goto out; | |
1746 | } | |
86a74ff2 | 1747 | |
3719109d SS |
1748 | if (intr_status & EESR_RX_CHECK) { |
1749 | if (napi_schedule_prep(&mdp->napi)) { | |
1750 | /* Mask Rx interrupts */ | |
1751 | sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK, | |
1752 | EESIPR); | |
1753 | __napi_schedule(&mdp->napi); | |
1754 | } else { | |
da246855 | 1755 | netdev_warn(ndev, |
0799c2d6 | 1756 | "ignoring interrupt, status 0x%08x, mask 0x%08x.\n", |
da246855 | 1757 | intr_status, intr_enable); |
3719109d SS |
1758 | } |
1759 | } | |
86a74ff2 | 1760 | |
b0ca2a21 | 1761 | /* Tx Check */ |
380af9e3 | 1762 | if (intr_status & cd->tx_check) { |
3719109d SS |
1763 | /* Clear Tx interrupts */ |
1764 | sh_eth_write(ndev, intr_status & cd->tx_check, EESR); | |
1765 | ||
1debdc8f | 1766 | sh_eth_tx_free(ndev, true); |
86a74ff2 NI |
1767 | netif_wake_queue(ndev); |
1768 | } | |
1769 | ||
9b39f05c SS |
1770 | /* E-MAC interrupt */ |
1771 | if (intr_status & EESR_ECI) | |
1772 | sh_eth_emac_interrupt(ndev); | |
1773 | ||
3719109d SS |
1774 | if (intr_status & cd->eesr_err_check) { |
1775 | /* Clear error interrupts */ | |
1776 | sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR); | |
1777 | ||
86a74ff2 | 1778 | sh_eth_error(ndev, intr_status); |
3719109d | 1779 | } |
86a74ff2 | 1780 | |
283e38db | 1781 | out: |
86a74ff2 NI |
1782 | spin_unlock(&mdp->lock); |
1783 | ||
0e0fde3c | 1784 | return ret; |
86a74ff2 NI |
1785 | } |
1786 | ||
3719109d SS |
1787 | static int sh_eth_poll(struct napi_struct *napi, int budget) |
1788 | { | |
1789 | struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private, | |
1790 | napi); | |
1791 | struct net_device *ndev = napi->dev; | |
1792 | int quota = budget; | |
0799c2d6 | 1793 | u32 intr_status; |
3719109d SS |
1794 | |
1795 | for (;;) { | |
1796 | intr_status = sh_eth_read(ndev, EESR); | |
1797 | if (!(intr_status & EESR_RX_CHECK)) | |
1798 | break; | |
1799 | /* Clear Rx interrupts */ | |
1800 | sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR); | |
1801 | ||
1802 | if (sh_eth_rx(ndev, intr_status, "a)) | |
1803 | goto out; | |
1804 | } | |
1805 | ||
1806 | napi_complete(napi); | |
1807 | ||
1808 | /* Reenable Rx interrupts */ | |
283e38db BH |
1809 | if (mdp->irq_enabled) |
1810 | sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR); | |
3719109d SS |
1811 | out: |
1812 | return budget - quota; | |
1813 | } | |
1814 | ||
86a74ff2 NI |
1815 | /* PHY state control function */ |
1816 | static void sh_eth_adjust_link(struct net_device *ndev) | |
1817 | { | |
1818 | struct sh_eth_private *mdp = netdev_priv(ndev); | |
9fd0375a | 1819 | struct phy_device *phydev = ndev->phydev; |
86a74ff2 NI |
1820 | int new_state = 0; |
1821 | ||
3340d2aa | 1822 | if (phydev->link) { |
86a74ff2 NI |
1823 | if (phydev->duplex != mdp->duplex) { |
1824 | new_state = 1; | |
1825 | mdp->duplex = phydev->duplex; | |
380af9e3 YS |
1826 | if (mdp->cd->set_duplex) |
1827 | mdp->cd->set_duplex(ndev); | |
86a74ff2 NI |
1828 | } |
1829 | ||
1830 | if (phydev->speed != mdp->speed) { | |
1831 | new_state = 1; | |
1832 | mdp->speed = phydev->speed; | |
380af9e3 YS |
1833 | if (mdp->cd->set_rate) |
1834 | mdp->cd->set_rate(ndev); | |
86a74ff2 | 1835 | } |
3340d2aa | 1836 | if (!mdp->link) { |
b2b14d2f | 1837 | sh_eth_modify(ndev, ECMR, ECMR_TXF, 0); |
86a74ff2 NI |
1838 | new_state = 1; |
1839 | mdp->link = phydev->link; | |
1e1b812b SS |
1840 | if (mdp->cd->no_psr || mdp->no_ether_link) |
1841 | sh_eth_rcv_snd_enable(ndev); | |
86a74ff2 NI |
1842 | } |
1843 | } else if (mdp->link) { | |
1844 | new_state = 1; | |
3340d2aa | 1845 | mdp->link = 0; |
86a74ff2 NI |
1846 | mdp->speed = 0; |
1847 | mdp->duplex = -1; | |
1e1b812b SS |
1848 | if (mdp->cd->no_psr || mdp->no_ether_link) |
1849 | sh_eth_rcv_snd_disable(ndev); | |
86a74ff2 NI |
1850 | } |
1851 | ||
dc19e4e5 | 1852 | if (new_state && netif_msg_link(mdp)) |
86a74ff2 NI |
1853 | phy_print_status(phydev); |
1854 | } | |
1855 | ||
1856 | /* PHY init function */ | |
1857 | static int sh_eth_phy_init(struct net_device *ndev) | |
1858 | { | |
702eca02 | 1859 | struct device_node *np = ndev->dev.parent->of_node; |
86a74ff2 | 1860 | struct sh_eth_private *mdp = netdev_priv(ndev); |
4fa8c3cc | 1861 | struct phy_device *phydev; |
86a74ff2 | 1862 | |
3340d2aa | 1863 | mdp->link = 0; |
86a74ff2 NI |
1864 | mdp->speed = 0; |
1865 | mdp->duplex = -1; | |
1866 | ||
1867 | /* Try connect to PHY */ | |
702eca02 BD |
1868 | if (np) { |
1869 | struct device_node *pn; | |
1870 | ||
1871 | pn = of_parse_phandle(np, "phy-handle", 0); | |
1872 | phydev = of_phy_connect(ndev, pn, | |
1873 | sh_eth_adjust_link, 0, | |
1874 | mdp->phy_interface); | |
1875 | ||
8da703dc | 1876 | of_node_put(pn); |
702eca02 BD |
1877 | if (!phydev) |
1878 | phydev = ERR_PTR(-ENOENT); | |
1879 | } else { | |
1880 | char phy_id[MII_BUS_ID_SIZE + 3]; | |
1881 | ||
1882 | snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT, | |
1883 | mdp->mii_bus->id, mdp->phy_id); | |
1884 | ||
1885 | phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link, | |
1886 | mdp->phy_interface); | |
1887 | } | |
1888 | ||
86a74ff2 | 1889 | if (IS_ERR(phydev)) { |
da246855 | 1890 | netdev_err(ndev, "failed to connect PHY\n"); |
86a74ff2 NI |
1891 | return PTR_ERR(phydev); |
1892 | } | |
380af9e3 | 1893 | |
2220943a | 1894 | phy_attached_info(phydev); |
86a74ff2 | 1895 | |
86a74ff2 NI |
1896 | return 0; |
1897 | } | |
1898 | ||
1899 | /* PHY control start function */ | |
1900 | static int sh_eth_phy_start(struct net_device *ndev) | |
1901 | { | |
86a74ff2 NI |
1902 | int ret; |
1903 | ||
1904 | ret = sh_eth_phy_init(ndev); | |
1905 | if (ret) | |
1906 | return ret; | |
1907 | ||
9fd0375a | 1908 | phy_start(ndev->phydev); |
86a74ff2 NI |
1909 | |
1910 | return 0; | |
1911 | } | |
1912 | ||
f08aff44 PR |
1913 | static int sh_eth_get_link_ksettings(struct net_device *ndev, |
1914 | struct ethtool_link_ksettings *cmd) | |
dc19e4e5 NI |
1915 | { |
1916 | struct sh_eth_private *mdp = netdev_priv(ndev); | |
1917 | unsigned long flags; | |
dc19e4e5 | 1918 | |
9fd0375a | 1919 | if (!ndev->phydev) |
4f9dce23 BH |
1920 | return -ENODEV; |
1921 | ||
dc19e4e5 | 1922 | spin_lock_irqsave(&mdp->lock, flags); |
5514174f | 1923 | phy_ethtool_ksettings_get(ndev->phydev, cmd); |
dc19e4e5 NI |
1924 | spin_unlock_irqrestore(&mdp->lock, flags); |
1925 | ||
5514174f | 1926 | return 0; |
dc19e4e5 NI |
1927 | } |
1928 | ||
f08aff44 PR |
1929 | static int sh_eth_set_link_ksettings(struct net_device *ndev, |
1930 | const struct ethtool_link_ksettings *cmd) | |
dc19e4e5 NI |
1931 | { |
1932 | struct sh_eth_private *mdp = netdev_priv(ndev); | |
1933 | unsigned long flags; | |
1934 | int ret; | |
dc19e4e5 | 1935 | |
9fd0375a | 1936 | if (!ndev->phydev) |
4f9dce23 BH |
1937 | return -ENODEV; |
1938 | ||
dc19e4e5 NI |
1939 | spin_lock_irqsave(&mdp->lock, flags); |
1940 | ||
1941 | /* disable tx and rx */ | |
4a55530f | 1942 | sh_eth_rcv_snd_disable(ndev); |
dc19e4e5 | 1943 | |
f08aff44 | 1944 | ret = phy_ethtool_ksettings_set(ndev->phydev, cmd); |
dc19e4e5 NI |
1945 | if (ret) |
1946 | goto error_exit; | |
1947 | ||
f08aff44 | 1948 | if (cmd->base.duplex == DUPLEX_FULL) |
dc19e4e5 NI |
1949 | mdp->duplex = 1; |
1950 | else | |
1951 | mdp->duplex = 0; | |
1952 | ||
1953 | if (mdp->cd->set_duplex) | |
1954 | mdp->cd->set_duplex(ndev); | |
1955 | ||
1956 | error_exit: | |
1957 | mdelay(1); | |
1958 | ||
1959 | /* enable tx and rx */ | |
4a55530f | 1960 | sh_eth_rcv_snd_enable(ndev); |
dc19e4e5 NI |
1961 | |
1962 | spin_unlock_irqrestore(&mdp->lock, flags); | |
1963 | ||
1964 | return ret; | |
1965 | } | |
1966 | ||
6b4b4fea BH |
1967 | /* If it is ever necessary to increase SH_ETH_REG_DUMP_MAX_REGS, the |
1968 | * version must be bumped as well. Just adding registers up to that | |
1969 | * limit is fine, as long as the existing register indices don't | |
1970 | * change. | |
1971 | */ | |
1972 | #define SH_ETH_REG_DUMP_VERSION 1 | |
1973 | #define SH_ETH_REG_DUMP_MAX_REGS 256 | |
1974 | ||
1975 | static size_t __sh_eth_get_regs(struct net_device *ndev, u32 *buf) | |
1976 | { | |
1977 | struct sh_eth_private *mdp = netdev_priv(ndev); | |
1978 | struct sh_eth_cpu_data *cd = mdp->cd; | |
1979 | u32 *valid_map; | |
1980 | size_t len; | |
1981 | ||
1982 | BUILD_BUG_ON(SH_ETH_MAX_REGISTER_OFFSET > SH_ETH_REG_DUMP_MAX_REGS); | |
1983 | ||
1984 | /* Dump starts with a bitmap that tells ethtool which | |
1985 | * registers are defined for this chip. | |
1986 | */ | |
1987 | len = DIV_ROUND_UP(SH_ETH_REG_DUMP_MAX_REGS, 32); | |
1988 | if (buf) { | |
1989 | valid_map = buf; | |
1990 | buf += len; | |
1991 | } else { | |
1992 | valid_map = NULL; | |
1993 | } | |
1994 | ||
1995 | /* Add a register to the dump, if it has a defined offset. | |
1996 | * This automatically skips most undefined registers, but for | |
1997 | * some it is also necessary to check a capability flag in | |
1998 | * struct sh_eth_cpu_data. | |
1999 | */ | |
2000 | #define mark_reg_valid(reg) valid_map[reg / 32] |= 1U << (reg % 32) | |
2001 | #define add_reg_from(reg, read_expr) do { \ | |
2002 | if (mdp->reg_offset[reg] != SH_ETH_OFFSET_INVALID) { \ | |
2003 | if (buf) { \ | |
2004 | mark_reg_valid(reg); \ | |
2005 | *buf++ = read_expr; \ | |
2006 | } \ | |
2007 | ++len; \ | |
2008 | } \ | |
2009 | } while (0) | |
2010 | #define add_reg(reg) add_reg_from(reg, sh_eth_read(ndev, reg)) | |
2011 | #define add_tsu_reg(reg) add_reg_from(reg, sh_eth_tsu_read(mdp, reg)) | |
2012 | ||
2013 | add_reg(EDSR); | |
2014 | add_reg(EDMR); | |
2015 | add_reg(EDTRR); | |
2016 | add_reg(EDRRR); | |
2017 | add_reg(EESR); | |
2018 | add_reg(EESIPR); | |
2019 | add_reg(TDLAR); | |
2020 | add_reg(TDFAR); | |
2021 | add_reg(TDFXR); | |
2022 | add_reg(TDFFR); | |
2023 | add_reg(RDLAR); | |
2024 | add_reg(RDFAR); | |
2025 | add_reg(RDFXR); | |
2026 | add_reg(RDFFR); | |
2027 | add_reg(TRSCER); | |
2028 | add_reg(RMFCR); | |
2029 | add_reg(TFTR); | |
2030 | add_reg(FDR); | |
2031 | add_reg(RMCR); | |
2032 | add_reg(TFUCR); | |
2033 | add_reg(RFOCR); | |
2034 | if (cd->rmiimode) | |
2035 | add_reg(RMIIMODE); | |
2036 | add_reg(FCFTR); | |
2037 | if (cd->rpadir) | |
2038 | add_reg(RPADIR); | |
2039 | if (!cd->no_trimd) | |
2040 | add_reg(TRIMD); | |
2041 | add_reg(ECMR); | |
2042 | add_reg(ECSR); | |
2043 | add_reg(ECSIPR); | |
2044 | add_reg(PIR); | |
2045 | if (!cd->no_psr) | |
2046 | add_reg(PSR); | |
2047 | add_reg(RDMLR); | |
2048 | add_reg(RFLR); | |
2049 | add_reg(IPGR); | |
2050 | if (cd->apr) | |
2051 | add_reg(APR); | |
2052 | if (cd->mpr) | |
2053 | add_reg(MPR); | |
2054 | add_reg(RFCR); | |
2055 | add_reg(RFCF); | |
2056 | if (cd->tpauser) | |
2057 | add_reg(TPAUSER); | |
2058 | add_reg(TPAUSECR); | |
2059 | add_reg(GECMR); | |
2060 | if (cd->bculr) | |
2061 | add_reg(BCULR); | |
2062 | add_reg(MAHR); | |
2063 | add_reg(MALR); | |
2064 | add_reg(TROCR); | |
2065 | add_reg(CDCR); | |
2066 | add_reg(LCCR); | |
2067 | add_reg(CNDCR); | |
2068 | add_reg(CEFCR); | |
2069 | add_reg(FRECR); | |
2070 | add_reg(TSFRCR); | |
2071 | add_reg(TLFRCR); | |
2072 | add_reg(CERCR); | |
2073 | add_reg(CEECR); | |
2074 | add_reg(MAFCR); | |
2075 | if (cd->rtrate) | |
2076 | add_reg(RTRATE); | |
62e04b7e | 2077 | if (cd->hw_checksum) |
6b4b4fea BH |
2078 | add_reg(CSMR); |
2079 | if (cd->select_mii) | |
2080 | add_reg(RMII_MII); | |
2081 | add_reg(ARSTR); | |
2082 | if (cd->tsu) { | |
2083 | add_tsu_reg(TSU_CTRST); | |
2084 | add_tsu_reg(TSU_FWEN0); | |
2085 | add_tsu_reg(TSU_FWEN1); | |
2086 | add_tsu_reg(TSU_FCM); | |
2087 | add_tsu_reg(TSU_BSYSL0); | |
2088 | add_tsu_reg(TSU_BSYSL1); | |
2089 | add_tsu_reg(TSU_PRISL0); | |
2090 | add_tsu_reg(TSU_PRISL1); | |
2091 | add_tsu_reg(TSU_FWSL0); | |
2092 | add_tsu_reg(TSU_FWSL1); | |
2093 | add_tsu_reg(TSU_FWSLC); | |
2094 | add_tsu_reg(TSU_QTAG0); | |
2095 | add_tsu_reg(TSU_QTAG1); | |
2096 | add_tsu_reg(TSU_QTAGM0); | |
2097 | add_tsu_reg(TSU_QTAGM1); | |
2098 | add_tsu_reg(TSU_FWSR); | |
2099 | add_tsu_reg(TSU_FWINMK); | |
2100 | add_tsu_reg(TSU_ADQT0); | |
2101 | add_tsu_reg(TSU_ADQT1); | |
2102 | add_tsu_reg(TSU_VTAG0); | |
2103 | add_tsu_reg(TSU_VTAG1); | |
2104 | add_tsu_reg(TSU_ADSBSY); | |
2105 | add_tsu_reg(TSU_TEN); | |
2106 | add_tsu_reg(TSU_POST1); | |
2107 | add_tsu_reg(TSU_POST2); | |
2108 | add_tsu_reg(TSU_POST3); | |
2109 | add_tsu_reg(TSU_POST4); | |
2110 | if (mdp->reg_offset[TSU_ADRH0] != SH_ETH_OFFSET_INVALID) { | |
2111 | /* This is the start of a table, not just a single | |
2112 | * register. | |
2113 | */ | |
2114 | if (buf) { | |
2115 | unsigned int i; | |
2116 | ||
2117 | mark_reg_valid(TSU_ADRH0); | |
2118 | for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES * 2; i++) | |
2119 | *buf++ = ioread32( | |
2120 | mdp->tsu_addr + | |
2121 | mdp->reg_offset[TSU_ADRH0] + | |
2122 | i * 4); | |
2123 | } | |
2124 | len += SH_ETH_TSU_CAM_ENTRIES * 2; | |
2125 | } | |
2126 | } | |
2127 | ||
2128 | #undef mark_reg_valid | |
2129 | #undef add_reg_from | |
2130 | #undef add_reg | |
2131 | #undef add_tsu_reg | |
2132 | ||
2133 | return len * 4; | |
2134 | } | |
2135 | ||
2136 | static int sh_eth_get_regs_len(struct net_device *ndev) | |
2137 | { | |
2138 | return __sh_eth_get_regs(ndev, NULL); | |
2139 | } | |
2140 | ||
2141 | static void sh_eth_get_regs(struct net_device *ndev, struct ethtool_regs *regs, | |
2142 | void *buf) | |
2143 | { | |
2144 | struct sh_eth_private *mdp = netdev_priv(ndev); | |
2145 | ||
2146 | regs->version = SH_ETH_REG_DUMP_VERSION; | |
2147 | ||
2148 | pm_runtime_get_sync(&mdp->pdev->dev); | |
2149 | __sh_eth_get_regs(ndev, buf); | |
2150 | pm_runtime_put_sync(&mdp->pdev->dev); | |
2151 | } | |
2152 | ||
dc19e4e5 NI |
2153 | static int sh_eth_nway_reset(struct net_device *ndev) |
2154 | { | |
2155 | struct sh_eth_private *mdp = netdev_priv(ndev); | |
2156 | unsigned long flags; | |
2157 | int ret; | |
2158 | ||
9fd0375a | 2159 | if (!ndev->phydev) |
4f9dce23 BH |
2160 | return -ENODEV; |
2161 | ||
dc19e4e5 | 2162 | spin_lock_irqsave(&mdp->lock, flags); |
9fd0375a | 2163 | ret = phy_start_aneg(ndev->phydev); |
dc19e4e5 NI |
2164 | spin_unlock_irqrestore(&mdp->lock, flags); |
2165 | ||
2166 | return ret; | |
2167 | } | |
2168 | ||
2169 | static u32 sh_eth_get_msglevel(struct net_device *ndev) | |
2170 | { | |
2171 | struct sh_eth_private *mdp = netdev_priv(ndev); | |
2172 | return mdp->msg_enable; | |
2173 | } | |
2174 | ||
2175 | static void sh_eth_set_msglevel(struct net_device *ndev, u32 value) | |
2176 | { | |
2177 | struct sh_eth_private *mdp = netdev_priv(ndev); | |
2178 | mdp->msg_enable = value; | |
2179 | } | |
2180 | ||
2181 | static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = { | |
2182 | "rx_current", "tx_current", | |
2183 | "rx_dirty", "tx_dirty", | |
2184 | }; | |
2185 | #define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats) | |
2186 | ||
2187 | static int sh_eth_get_sset_count(struct net_device *netdev, int sset) | |
2188 | { | |
2189 | switch (sset) { | |
2190 | case ETH_SS_STATS: | |
2191 | return SH_ETH_STATS_LEN; | |
2192 | default: | |
2193 | return -EOPNOTSUPP; | |
2194 | } | |
2195 | } | |
2196 | ||
2197 | static void sh_eth_get_ethtool_stats(struct net_device *ndev, | |
128296fc | 2198 | struct ethtool_stats *stats, u64 *data) |
dc19e4e5 NI |
2199 | { |
2200 | struct sh_eth_private *mdp = netdev_priv(ndev); | |
2201 | int i = 0; | |
2202 | ||
2203 | /* device-specific stats */ | |
2204 | data[i++] = mdp->cur_rx; | |
2205 | data[i++] = mdp->cur_tx; | |
2206 | data[i++] = mdp->dirty_rx; | |
2207 | data[i++] = mdp->dirty_tx; | |
2208 | } | |
2209 | ||
2210 | static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data) | |
2211 | { | |
2212 | switch (stringset) { | |
2213 | case ETH_SS_STATS: | |
2214 | memcpy(data, *sh_eth_gstrings_stats, | |
128296fc | 2215 | sizeof(sh_eth_gstrings_stats)); |
dc19e4e5 NI |
2216 | break; |
2217 | } | |
2218 | } | |
2219 | ||
525b8075 YS |
2220 | static void sh_eth_get_ringparam(struct net_device *ndev, |
2221 | struct ethtool_ringparam *ring) | |
2222 | { | |
2223 | struct sh_eth_private *mdp = netdev_priv(ndev); | |
2224 | ||
2225 | ring->rx_max_pending = RX_RING_MAX; | |
2226 | ring->tx_max_pending = TX_RING_MAX; | |
2227 | ring->rx_pending = mdp->num_rx_ring; | |
2228 | ring->tx_pending = mdp->num_tx_ring; | |
2229 | } | |
2230 | ||
2231 | static int sh_eth_set_ringparam(struct net_device *ndev, | |
2232 | struct ethtool_ringparam *ring) | |
2233 | { | |
2234 | struct sh_eth_private *mdp = netdev_priv(ndev); | |
2235 | int ret; | |
2236 | ||
2237 | if (ring->tx_pending > TX_RING_MAX || | |
2238 | ring->rx_pending > RX_RING_MAX || | |
2239 | ring->tx_pending < TX_RING_MIN || | |
2240 | ring->rx_pending < RX_RING_MIN) | |
2241 | return -EINVAL; | |
2242 | if (ring->rx_mini_pending || ring->rx_jumbo_pending) | |
2243 | return -EINVAL; | |
2244 | ||
2245 | if (netif_running(ndev)) { | |
bd888916 | 2246 | netif_device_detach(ndev); |
525b8075 | 2247 | netif_tx_disable(ndev); |
283e38db BH |
2248 | |
2249 | /* Serialise with the interrupt handler and NAPI, then | |
2250 | * disable interrupts. We have to clear the | |
2251 | * irq_enabled flag first to ensure that interrupts | |
2252 | * won't be re-enabled. | |
2253 | */ | |
2254 | mdp->irq_enabled = false; | |
525b8075 | 2255 | synchronize_irq(ndev->irq); |
283e38db | 2256 | napi_synchronize(&mdp->napi); |
525b8075 | 2257 | sh_eth_write(ndev, 0x0000, EESIPR); |
525b8075 | 2258 | |
740c7f31 | 2259 | sh_eth_dev_exit(ndev); |
525b8075 | 2260 | |
8e03a5e7 | 2261 | /* Free all the skbuffs in the Rx queue and the DMA buffers. */ |
084236d8 | 2262 | sh_eth_ring_free(ndev); |
084236d8 | 2263 | } |
525b8075 YS |
2264 | |
2265 | /* Set new parameters */ | |
2266 | mdp->num_rx_ring = ring->rx_pending; | |
2267 | mdp->num_tx_ring = ring->tx_pending; | |
2268 | ||
525b8075 | 2269 | if (netif_running(ndev)) { |
084236d8 BH |
2270 | ret = sh_eth_ring_init(ndev); |
2271 | if (ret < 0) { | |
2272 | netdev_err(ndev, "%s: sh_eth_ring_init failed.\n", | |
2273 | __func__); | |
2274 | return ret; | |
2275 | } | |
f7967210 | 2276 | ret = sh_eth_dev_init(ndev); |
084236d8 BH |
2277 | if (ret < 0) { |
2278 | netdev_err(ndev, "%s: sh_eth_dev_init failed.\n", | |
2279 | __func__); | |
2280 | return ret; | |
2281 | } | |
2282 | ||
bd888916 | 2283 | netif_device_attach(ndev); |
525b8075 YS |
2284 | } |
2285 | ||
2286 | return 0; | |
2287 | } | |
2288 | ||
d8981d02 NS |
2289 | static void sh_eth_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) |
2290 | { | |
2291 | struct sh_eth_private *mdp = netdev_priv(ndev); | |
2292 | ||
2293 | wol->supported = 0; | |
2294 | wol->wolopts = 0; | |
2295 | ||
2296 | if (mdp->cd->magic && mdp->clk) { | |
2297 | wol->supported = WAKE_MAGIC; | |
2298 | wol->wolopts = mdp->wol_enabled ? WAKE_MAGIC : 0; | |
2299 | } | |
2300 | } | |
2301 | ||
2302 | static int sh_eth_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) | |
2303 | { | |
2304 | struct sh_eth_private *mdp = netdev_priv(ndev); | |
2305 | ||
2306 | if (!mdp->cd->magic || !mdp->clk || wol->wolopts & ~WAKE_MAGIC) | |
2307 | return -EOPNOTSUPP; | |
2308 | ||
2309 | mdp->wol_enabled = !!(wol->wolopts & WAKE_MAGIC); | |
2310 | ||
2311 | device_set_wakeup_enable(&mdp->pdev->dev, mdp->wol_enabled); | |
2312 | ||
2313 | return 0; | |
2314 | } | |
2315 | ||
9b07be4b | 2316 | static const struct ethtool_ops sh_eth_ethtool_ops = { |
6b4b4fea BH |
2317 | .get_regs_len = sh_eth_get_regs_len, |
2318 | .get_regs = sh_eth_get_regs, | |
9b07be4b | 2319 | .nway_reset = sh_eth_nway_reset, |
dc19e4e5 NI |
2320 | .get_msglevel = sh_eth_get_msglevel, |
2321 | .set_msglevel = sh_eth_set_msglevel, | |
9b07be4b | 2322 | .get_link = ethtool_op_get_link, |
dc19e4e5 NI |
2323 | .get_strings = sh_eth_get_strings, |
2324 | .get_ethtool_stats = sh_eth_get_ethtool_stats, | |
2325 | .get_sset_count = sh_eth_get_sset_count, | |
525b8075 YS |
2326 | .get_ringparam = sh_eth_get_ringparam, |
2327 | .set_ringparam = sh_eth_set_ringparam, | |
f08aff44 PR |
2328 | .get_link_ksettings = sh_eth_get_link_ksettings, |
2329 | .set_link_ksettings = sh_eth_set_link_ksettings, | |
d8981d02 NS |
2330 | .get_wol = sh_eth_get_wol, |
2331 | .set_wol = sh_eth_set_wol, | |
dc19e4e5 NI |
2332 | }; |
2333 | ||
86a74ff2 NI |
2334 | /* network device open function */ |
2335 | static int sh_eth_open(struct net_device *ndev) | |
2336 | { | |
86a74ff2 | 2337 | struct sh_eth_private *mdp = netdev_priv(ndev); |
4fa8c3cc | 2338 | int ret; |
86a74ff2 | 2339 | |
bcd5149d MD |
2340 | pm_runtime_get_sync(&mdp->pdev->dev); |
2341 | ||
d2779e99 SS |
2342 | napi_enable(&mdp->napi); |
2343 | ||
a0607fd3 | 2344 | ret = request_irq(ndev->irq, sh_eth_interrupt, |
5b3dfd13 | 2345 | mdp->cd->irq_flags, ndev->name, ndev); |
86a74ff2 | 2346 | if (ret) { |
da246855 | 2347 | netdev_err(ndev, "Can not assign IRQ number\n"); |
d2779e99 | 2348 | goto out_napi_off; |
86a74ff2 NI |
2349 | } |
2350 | ||
2351 | /* Descriptor set */ | |
2352 | ret = sh_eth_ring_init(ndev); | |
2353 | if (ret) | |
2354 | goto out_free_irq; | |
2355 | ||
2356 | /* device init */ | |
f7967210 | 2357 | ret = sh_eth_dev_init(ndev); |
86a74ff2 NI |
2358 | if (ret) |
2359 | goto out_free_irq; | |
2360 | ||
2361 | /* PHY control start*/ | |
2362 | ret = sh_eth_phy_start(ndev); | |
2363 | if (ret) | |
2364 | goto out_free_irq; | |
2365 | ||
ad846aa5 SS |
2366 | netif_start_queue(ndev); |
2367 | ||
7fa2955f MK |
2368 | mdp->is_opened = 1; |
2369 | ||
86a74ff2 NI |
2370 | return ret; |
2371 | ||
2372 | out_free_irq: | |
2373 | free_irq(ndev->irq, ndev); | |
d2779e99 SS |
2374 | out_napi_off: |
2375 | napi_disable(&mdp->napi); | |
bcd5149d | 2376 | pm_runtime_put_sync(&mdp->pdev->dev); |
86a74ff2 NI |
2377 | return ret; |
2378 | } | |
2379 | ||
2380 | /* Timeout function */ | |
2381 | static void sh_eth_tx_timeout(struct net_device *ndev) | |
2382 | { | |
2383 | struct sh_eth_private *mdp = netdev_priv(ndev); | |
86a74ff2 NI |
2384 | struct sh_eth_rxdesc *rxdesc; |
2385 | int i; | |
2386 | ||
2387 | netif_stop_queue(ndev); | |
2388 | ||
8d5009f6 SS |
2389 | netif_err(mdp, timer, ndev, |
2390 | "transmit timed out, status %8.8x, resetting...\n", | |
0799c2d6 | 2391 | sh_eth_read(ndev, EESR)); |
86a74ff2 NI |
2392 | |
2393 | /* tx_errors count up */ | |
bb7d92e3 | 2394 | ndev->stats.tx_errors++; |
86a74ff2 | 2395 | |
86a74ff2 | 2396 | /* Free all the skbuffs in the Rx queue. */ |
525b8075 | 2397 | for (i = 0; i < mdp->num_rx_ring; i++) { |
86a74ff2 | 2398 | rxdesc = &mdp->rx_ring[i]; |
7cf72477 SS |
2399 | rxdesc->status = cpu_to_le32(0); |
2400 | rxdesc->addr = cpu_to_le32(0xBADF00D0); | |
179d80af | 2401 | dev_kfree_skb(mdp->rx_skbuff[i]); |
86a74ff2 NI |
2402 | mdp->rx_skbuff[i] = NULL; |
2403 | } | |
525b8075 | 2404 | for (i = 0; i < mdp->num_tx_ring; i++) { |
179d80af | 2405 | dev_kfree_skb(mdp->tx_skbuff[i]); |
86a74ff2 NI |
2406 | mdp->tx_skbuff[i] = NULL; |
2407 | } | |
2408 | ||
2409 | /* device init */ | |
f7967210 | 2410 | sh_eth_dev_init(ndev); |
ad846aa5 SS |
2411 | |
2412 | netif_start_queue(ndev); | |
86a74ff2 NI |
2413 | } |
2414 | ||
2415 | /* Packet transmit function */ | |
2416 | static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev) | |
2417 | { | |
2418 | struct sh_eth_private *mdp = netdev_priv(ndev); | |
2419 | struct sh_eth_txdesc *txdesc; | |
1299653a | 2420 | dma_addr_t dma_addr; |
86a74ff2 | 2421 | u32 entry; |
fb5e2f9b | 2422 | unsigned long flags; |
86a74ff2 NI |
2423 | |
2424 | spin_lock_irqsave(&mdp->lock, flags); | |
525b8075 | 2425 | if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) { |
1debdc8f | 2426 | if (!sh_eth_tx_free(ndev, true)) { |
8d5009f6 | 2427 | netif_warn(mdp, tx_queued, ndev, "TxFD exhausted.\n"); |
86a74ff2 NI |
2428 | netif_stop_queue(ndev); |
2429 | spin_unlock_irqrestore(&mdp->lock, flags); | |
5b548140 | 2430 | return NETDEV_TX_BUSY; |
86a74ff2 NI |
2431 | } |
2432 | } | |
2433 | spin_unlock_irqrestore(&mdp->lock, flags); | |
2434 | ||
dacc73e0 | 2435 | if (skb_put_padto(skb, ETH_ZLEN)) |
eebfb643 BH |
2436 | return NETDEV_TX_OK; |
2437 | ||
525b8075 | 2438 | entry = mdp->cur_tx % mdp->num_tx_ring; |
86a74ff2 NI |
2439 | mdp->tx_skbuff[entry] = skb; |
2440 | txdesc = &mdp->tx_ring[entry]; | |
86a74ff2 | 2441 | /* soft swap. */ |
380af9e3 | 2442 | if (!mdp->cd->hw_swap) |
3e230993 | 2443 | sh_eth_soft_swap(PTR_ALIGN(skb->data, 4), skb->len + 2); |
1299653a SS |
2444 | dma_addr = dma_map_single(&ndev->dev, skb->data, skb->len, |
2445 | DMA_TO_DEVICE); | |
2446 | if (dma_mapping_error(&ndev->dev, dma_addr)) { | |
aa3933b8 BH |
2447 | kfree_skb(skb); |
2448 | return NETDEV_TX_OK; | |
2449 | } | |
7cf72477 SS |
2450 | txdesc->addr = cpu_to_le32(dma_addr); |
2451 | txdesc->len = cpu_to_le32(skb->len << 16); | |
86a74ff2 | 2452 | |
f32bfb9a | 2453 | dma_wmb(); /* TACT bit must be set after all the above writes */ |
525b8075 | 2454 | if (entry >= mdp->num_tx_ring - 1) |
7cf72477 | 2455 | txdesc->status |= cpu_to_le32(TD_TACT | TD_TDLE); |
86a74ff2 | 2456 | else |
7cf72477 | 2457 | txdesc->status |= cpu_to_le32(TD_TACT); |
86a74ff2 NI |
2458 | |
2459 | mdp->cur_tx++; | |
2460 | ||
c5ed5368 YS |
2461 | if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp))) |
2462 | sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR); | |
b0ca2a21 | 2463 | |
6ed10654 | 2464 | return NETDEV_TX_OK; |
86a74ff2 NI |
2465 | } |
2466 | ||
4398f9c8 BH |
2467 | /* The statistics registers have write-clear behaviour, which means we |
2468 | * will lose any increment between the read and write. We mitigate | |
2469 | * this by only clearing when we read a non-zero value, so we will | |
2470 | * never falsely report a total of zero. | |
2471 | */ | |
2472 | static void | |
2473 | sh_eth_update_stat(struct net_device *ndev, unsigned long *stat, int reg) | |
2474 | { | |
2475 | u32 delta = sh_eth_read(ndev, reg); | |
2476 | ||
2477 | if (delta) { | |
2478 | *stat += delta; | |
2479 | sh_eth_write(ndev, 0, reg); | |
2480 | } | |
2481 | } | |
2482 | ||
7fa2955f MK |
2483 | static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev) |
2484 | { | |
2485 | struct sh_eth_private *mdp = netdev_priv(ndev); | |
2486 | ||
2487 | if (sh_eth_is_rz_fast_ether(mdp)) | |
2488 | return &ndev->stats; | |
2489 | ||
2490 | if (!mdp->is_opened) | |
2491 | return &ndev->stats; | |
2492 | ||
4398f9c8 BH |
2493 | sh_eth_update_stat(ndev, &ndev->stats.tx_dropped, TROCR); |
2494 | sh_eth_update_stat(ndev, &ndev->stats.collisions, CDCR); | |
2495 | sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, LCCR); | |
7fa2955f MK |
2496 | |
2497 | if (sh_eth_is_gether(mdp)) { | |
4398f9c8 BH |
2498 | sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, |
2499 | CERCR); | |
2500 | sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, | |
2501 | CEECR); | |
7fa2955f | 2502 | } else { |
4398f9c8 BH |
2503 | sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, |
2504 | CNDCR); | |
7fa2955f MK |
2505 | } |
2506 | ||
2507 | return &ndev->stats; | |
2508 | } | |
2509 | ||
86a74ff2 NI |
2510 | /* device close function */ |
2511 | static int sh_eth_close(struct net_device *ndev) | |
2512 | { | |
2513 | struct sh_eth_private *mdp = netdev_priv(ndev); | |
86a74ff2 NI |
2514 | |
2515 | netif_stop_queue(ndev); | |
2516 | ||
283e38db BH |
2517 | /* Serialise with the interrupt handler and NAPI, then disable |
2518 | * interrupts. We have to clear the irq_enabled flag first to | |
2519 | * ensure that interrupts won't be re-enabled. | |
2520 | */ | |
2521 | mdp->irq_enabled = false; | |
2522 | synchronize_irq(ndev->irq); | |
2523 | napi_disable(&mdp->napi); | |
4a55530f | 2524 | sh_eth_write(ndev, 0x0000, EESIPR); |
86a74ff2 | 2525 | |
740c7f31 | 2526 | sh_eth_dev_exit(ndev); |
86a74ff2 NI |
2527 | |
2528 | /* PHY Disconnect */ | |
9fd0375a PR |
2529 | if (ndev->phydev) { |
2530 | phy_stop(ndev->phydev); | |
2531 | phy_disconnect(ndev->phydev); | |
86a74ff2 NI |
2532 | } |
2533 | ||
2534 | free_irq(ndev->irq, ndev); | |
2535 | ||
8e03a5e7 | 2536 | /* Free all the skbuffs in the Rx queue and the DMA buffer. */ |
86a74ff2 NI |
2537 | sh_eth_ring_free(ndev); |
2538 | ||
bcd5149d MD |
2539 | pm_runtime_put_sync(&mdp->pdev->dev); |
2540 | ||
7fa2955f | 2541 | mdp->is_opened = 0; |
bcd5149d | 2542 | |
7fa2955f | 2543 | return 0; |
86a74ff2 NI |
2544 | } |
2545 | ||
bb7d92e3 | 2546 | /* ioctl to device function */ |
128296fc | 2547 | static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd) |
86a74ff2 | 2548 | { |
9fd0375a | 2549 | struct phy_device *phydev = ndev->phydev; |
86a74ff2 NI |
2550 | |
2551 | if (!netif_running(ndev)) | |
2552 | return -EINVAL; | |
2553 | ||
2554 | if (!phydev) | |
2555 | return -ENODEV; | |
2556 | ||
28b04113 | 2557 | return phy_mii_ioctl(phydev, rq, cmd); |
86a74ff2 NI |
2558 | } |
2559 | ||
78d61022 NS |
2560 | static int sh_eth_change_mtu(struct net_device *ndev, int new_mtu) |
2561 | { | |
2562 | if (netif_running(ndev)) | |
2563 | return -EBUSY; | |
2564 | ||
2565 | ndev->mtu = new_mtu; | |
2566 | netdev_update_features(ndev); | |
2567 | ||
2568 | return 0; | |
2569 | } | |
2570 | ||
6743fe6d YS |
2571 | /* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */ |
2572 | static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp, | |
2573 | int entry) | |
2574 | { | |
2575 | return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4); | |
2576 | } | |
2577 | ||
2578 | static u32 sh_eth_tsu_get_post_mask(int entry) | |
2579 | { | |
2580 | return 0x0f << (28 - ((entry % 8) * 4)); | |
2581 | } | |
2582 | ||
2583 | static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry) | |
2584 | { | |
2585 | return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4)); | |
2586 | } | |
2587 | ||
2588 | static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev, | |
2589 | int entry) | |
2590 | { | |
2591 | struct sh_eth_private *mdp = netdev_priv(ndev); | |
2592 | u32 tmp; | |
2593 | void *reg_offset; | |
2594 | ||
2595 | reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry); | |
2596 | tmp = ioread32(reg_offset); | |
2597 | iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset); | |
2598 | } | |
2599 | ||
2600 | static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev, | |
2601 | int entry) | |
2602 | { | |
2603 | struct sh_eth_private *mdp = netdev_priv(ndev); | |
2604 | u32 post_mask, ref_mask, tmp; | |
2605 | void *reg_offset; | |
2606 | ||
2607 | reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry); | |
2608 | post_mask = sh_eth_tsu_get_post_mask(entry); | |
2609 | ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask; | |
2610 | ||
2611 | tmp = ioread32(reg_offset); | |
2612 | iowrite32(tmp & ~post_mask, reg_offset); | |
2613 | ||
2614 | /* If other port enables, the function returns "true" */ | |
2615 | return tmp & ref_mask; | |
2616 | } | |
2617 | ||
2618 | static int sh_eth_tsu_busy(struct net_device *ndev) | |
2619 | { | |
2620 | int timeout = SH_ETH_TSU_TIMEOUT_MS * 100; | |
2621 | struct sh_eth_private *mdp = netdev_priv(ndev); | |
2622 | ||
2623 | while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) { | |
2624 | udelay(10); | |
2625 | timeout--; | |
2626 | if (timeout <= 0) { | |
da246855 | 2627 | netdev_err(ndev, "%s: timeout\n", __func__); |
6743fe6d YS |
2628 | return -ETIMEDOUT; |
2629 | } | |
2630 | } | |
2631 | ||
2632 | return 0; | |
2633 | } | |
2634 | ||
2635 | static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg, | |
2636 | const u8 *addr) | |
2637 | { | |
2638 | u32 val; | |
2639 | ||
2640 | val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3]; | |
2641 | iowrite32(val, reg); | |
2642 | if (sh_eth_tsu_busy(ndev) < 0) | |
2643 | return -EBUSY; | |
2644 | ||
2645 | val = addr[4] << 8 | addr[5]; | |
2646 | iowrite32(val, reg + 4); | |
2647 | if (sh_eth_tsu_busy(ndev) < 0) | |
2648 | return -EBUSY; | |
2649 | ||
2650 | return 0; | |
2651 | } | |
2652 | ||
2653 | static void sh_eth_tsu_read_entry(void *reg, u8 *addr) | |
2654 | { | |
2655 | u32 val; | |
2656 | ||
2657 | val = ioread32(reg); | |
2658 | addr[0] = (val >> 24) & 0xff; | |
2659 | addr[1] = (val >> 16) & 0xff; | |
2660 | addr[2] = (val >> 8) & 0xff; | |
2661 | addr[3] = val & 0xff; | |
2662 | val = ioread32(reg + 4); | |
2663 | addr[4] = (val >> 8) & 0xff; | |
2664 | addr[5] = val & 0xff; | |
2665 | } | |
2666 | ||
2667 | ||
2668 | static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr) | |
2669 | { | |
2670 | struct sh_eth_private *mdp = netdev_priv(ndev); | |
2671 | void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); | |
2672 | int i; | |
2673 | u8 c_addr[ETH_ALEN]; | |
2674 | ||
2675 | for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) { | |
2676 | sh_eth_tsu_read_entry(reg_offset, c_addr); | |
c4bde29c | 2677 | if (ether_addr_equal(addr, c_addr)) |
6743fe6d YS |
2678 | return i; |
2679 | } | |
2680 | ||
2681 | return -ENOENT; | |
2682 | } | |
2683 | ||
2684 | static int sh_eth_tsu_find_empty(struct net_device *ndev) | |
2685 | { | |
2686 | u8 blank[ETH_ALEN]; | |
2687 | int entry; | |
2688 | ||
2689 | memset(blank, 0, sizeof(blank)); | |
2690 | entry = sh_eth_tsu_find_entry(ndev, blank); | |
2691 | return (entry < 0) ? -ENOMEM : entry; | |
2692 | } | |
2693 | ||
2694 | static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev, | |
2695 | int entry) | |
2696 | { | |
2697 | struct sh_eth_private *mdp = netdev_priv(ndev); | |
2698 | void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); | |
2699 | int ret; | |
2700 | u8 blank[ETH_ALEN]; | |
2701 | ||
2702 | sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) & | |
2703 | ~(1 << (31 - entry)), TSU_TEN); | |
2704 | ||
2705 | memset(blank, 0, sizeof(blank)); | |
2706 | ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank); | |
2707 | if (ret < 0) | |
2708 | return ret; | |
2709 | return 0; | |
2710 | } | |
2711 | ||
2712 | static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr) | |
2713 | { | |
2714 | struct sh_eth_private *mdp = netdev_priv(ndev); | |
2715 | void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); | |
2716 | int i, ret; | |
2717 | ||
2718 | if (!mdp->cd->tsu) | |
2719 | return 0; | |
2720 | ||
2721 | i = sh_eth_tsu_find_entry(ndev, addr); | |
2722 | if (i < 0) { | |
2723 | /* No entry found, create one */ | |
2724 | i = sh_eth_tsu_find_empty(ndev); | |
2725 | if (i < 0) | |
2726 | return -ENOMEM; | |
2727 | ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr); | |
2728 | if (ret < 0) | |
2729 | return ret; | |
2730 | ||
2731 | /* Enable the entry */ | |
2732 | sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) | | |
2733 | (1 << (31 - i)), TSU_TEN); | |
2734 | } | |
2735 | ||
2736 | /* Entry found or created, enable POST */ | |
2737 | sh_eth_tsu_enable_cam_entry_post(ndev, i); | |
2738 | ||
2739 | return 0; | |
2740 | } | |
2741 | ||
2742 | static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr) | |
2743 | { | |
2744 | struct sh_eth_private *mdp = netdev_priv(ndev); | |
2745 | int i, ret; | |
2746 | ||
2747 | if (!mdp->cd->tsu) | |
2748 | return 0; | |
2749 | ||
2750 | i = sh_eth_tsu_find_entry(ndev, addr); | |
2751 | if (i) { | |
2752 | /* Entry found */ | |
2753 | if (sh_eth_tsu_disable_cam_entry_post(ndev, i)) | |
2754 | goto done; | |
2755 | ||
2756 | /* Disable the entry if both ports was disabled */ | |
2757 | ret = sh_eth_tsu_disable_cam_entry_table(ndev, i); | |
2758 | if (ret < 0) | |
2759 | return ret; | |
2760 | } | |
2761 | done: | |
2762 | return 0; | |
2763 | } | |
2764 | ||
2765 | static int sh_eth_tsu_purge_all(struct net_device *ndev) | |
2766 | { | |
2767 | struct sh_eth_private *mdp = netdev_priv(ndev); | |
2768 | int i, ret; | |
2769 | ||
b37feed7 | 2770 | if (!mdp->cd->tsu) |
6743fe6d YS |
2771 | return 0; |
2772 | ||
2773 | for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) { | |
2774 | if (sh_eth_tsu_disable_cam_entry_post(ndev, i)) | |
2775 | continue; | |
2776 | ||
2777 | /* Disable the entry if both ports was disabled */ | |
2778 | ret = sh_eth_tsu_disable_cam_entry_table(ndev, i); | |
2779 | if (ret < 0) | |
2780 | return ret; | |
2781 | } | |
2782 | ||
2783 | return 0; | |
2784 | } | |
2785 | ||
2786 | static void sh_eth_tsu_purge_mcast(struct net_device *ndev) | |
2787 | { | |
2788 | struct sh_eth_private *mdp = netdev_priv(ndev); | |
2789 | u8 addr[ETH_ALEN]; | |
2790 | void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); | |
2791 | int i; | |
2792 | ||
b37feed7 | 2793 | if (!mdp->cd->tsu) |
6743fe6d YS |
2794 | return; |
2795 | ||
2796 | for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) { | |
2797 | sh_eth_tsu_read_entry(reg_offset, addr); | |
2798 | if (is_multicast_ether_addr(addr)) | |
2799 | sh_eth_tsu_del_entry(ndev, addr); | |
2800 | } | |
2801 | } | |
2802 | ||
b37feed7 BH |
2803 | /* Update promiscuous flag and multicast filter */ |
2804 | static void sh_eth_set_rx_mode(struct net_device *ndev) | |
86a74ff2 | 2805 | { |
6743fe6d YS |
2806 | struct sh_eth_private *mdp = netdev_priv(ndev); |
2807 | u32 ecmr_bits; | |
2808 | int mcast_all = 0; | |
2809 | unsigned long flags; | |
2810 | ||
2811 | spin_lock_irqsave(&mdp->lock, flags); | |
128296fc | 2812 | /* Initial condition is MCT = 1, PRM = 0. |
6743fe6d YS |
2813 | * Depending on ndev->flags, set PRM or clear MCT |
2814 | */ | |
b37feed7 BH |
2815 | ecmr_bits = sh_eth_read(ndev, ECMR) & ~ECMR_PRM; |
2816 | if (mdp->cd->tsu) | |
2817 | ecmr_bits |= ECMR_MCT; | |
6743fe6d YS |
2818 | |
2819 | if (!(ndev->flags & IFF_MULTICAST)) { | |
2820 | sh_eth_tsu_purge_mcast(ndev); | |
2821 | mcast_all = 1; | |
2822 | } | |
2823 | if (ndev->flags & IFF_ALLMULTI) { | |
2824 | sh_eth_tsu_purge_mcast(ndev); | |
2825 | ecmr_bits &= ~ECMR_MCT; | |
2826 | mcast_all = 1; | |
2827 | } | |
2828 | ||
86a74ff2 | 2829 | if (ndev->flags & IFF_PROMISC) { |
6743fe6d YS |
2830 | sh_eth_tsu_purge_all(ndev); |
2831 | ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM; | |
2832 | } else if (mdp->cd->tsu) { | |
2833 | struct netdev_hw_addr *ha; | |
2834 | netdev_for_each_mc_addr(ha, ndev) { | |
2835 | if (mcast_all && is_multicast_ether_addr(ha->addr)) | |
2836 | continue; | |
2837 | ||
2838 | if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) { | |
2839 | if (!mcast_all) { | |
2840 | sh_eth_tsu_purge_mcast(ndev); | |
2841 | ecmr_bits &= ~ECMR_MCT; | |
2842 | mcast_all = 1; | |
2843 | } | |
2844 | } | |
2845 | } | |
86a74ff2 | 2846 | } |
6743fe6d YS |
2847 | |
2848 | /* update the ethernet mode */ | |
2849 | sh_eth_write(ndev, ecmr_bits, ECMR); | |
2850 | ||
2851 | spin_unlock_irqrestore(&mdp->lock, flags); | |
86a74ff2 | 2852 | } |
71cc7c37 YS |
2853 | |
2854 | static int sh_eth_get_vtag_index(struct sh_eth_private *mdp) | |
2855 | { | |
2856 | if (!mdp->port) | |
2857 | return TSU_VTAG0; | |
2858 | else | |
2859 | return TSU_VTAG1; | |
2860 | } | |
2861 | ||
80d5c368 PM |
2862 | static int sh_eth_vlan_rx_add_vid(struct net_device *ndev, |
2863 | __be16 proto, u16 vid) | |
71cc7c37 YS |
2864 | { |
2865 | struct sh_eth_private *mdp = netdev_priv(ndev); | |
2866 | int vtag_reg_index = sh_eth_get_vtag_index(mdp); | |
2867 | ||
2868 | if (unlikely(!mdp->cd->tsu)) | |
2869 | return -EPERM; | |
2870 | ||
2871 | /* No filtering if vid = 0 */ | |
2872 | if (!vid) | |
2873 | return 0; | |
2874 | ||
2875 | mdp->vlan_num_ids++; | |
2876 | ||
128296fc | 2877 | /* The controller has one VLAN tag HW filter. So, if the filter is |
71cc7c37 YS |
2878 | * already enabled, the driver disables it and the filte |
2879 | */ | |
2880 | if (mdp->vlan_num_ids > 1) { | |
2881 | /* disable VLAN filter */ | |
2882 | sh_eth_tsu_write(mdp, 0, vtag_reg_index); | |
2883 | return 0; | |
2884 | } | |
2885 | ||
2886 | sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK), | |
2887 | vtag_reg_index); | |
2888 | ||
2889 | return 0; | |
2890 | } | |
2891 | ||
80d5c368 PM |
2892 | static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev, |
2893 | __be16 proto, u16 vid) | |
71cc7c37 YS |
2894 | { |
2895 | struct sh_eth_private *mdp = netdev_priv(ndev); | |
2896 | int vtag_reg_index = sh_eth_get_vtag_index(mdp); | |
2897 | ||
2898 | if (unlikely(!mdp->cd->tsu)) | |
2899 | return -EPERM; | |
2900 | ||
2901 | /* No filtering if vid = 0 */ | |
2902 | if (!vid) | |
2903 | return 0; | |
2904 | ||
2905 | mdp->vlan_num_ids--; | |
2906 | sh_eth_tsu_write(mdp, 0, vtag_reg_index); | |
2907 | ||
2908 | return 0; | |
2909 | } | |
86a74ff2 NI |
2910 | |
2911 | /* SuperH's TSU register init function */ | |
4a55530f | 2912 | static void sh_eth_tsu_init(struct sh_eth_private *mdp) |
86a74ff2 | 2913 | { |
db893473 SH |
2914 | if (sh_eth_is_rz_fast_ether(mdp)) { |
2915 | sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */ | |
e1487888 CB |
2916 | sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, |
2917 | TSU_FWSLC); /* Enable POST registers */ | |
db893473 SH |
2918 | return; |
2919 | } | |
2920 | ||
4a55530f YS |
2921 | sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */ |
2922 | sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */ | |
2923 | sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */ | |
2924 | sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0); | |
2925 | sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1); | |
2926 | sh_eth_tsu_write(mdp, 0, TSU_PRISL0); | |
2927 | sh_eth_tsu_write(mdp, 0, TSU_PRISL1); | |
2928 | sh_eth_tsu_write(mdp, 0, TSU_FWSL0); | |
2929 | sh_eth_tsu_write(mdp, 0, TSU_FWSL1); | |
2930 | sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC); | |
c5ed5368 YS |
2931 | if (sh_eth_is_gether(mdp)) { |
2932 | sh_eth_tsu_write(mdp, 0, TSU_QTAG0); /* Disable QTAG(0->1) */ | |
2933 | sh_eth_tsu_write(mdp, 0, TSU_QTAG1); /* Disable QTAG(1->0) */ | |
2934 | } else { | |
2935 | sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */ | |
2936 | sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */ | |
2937 | } | |
4a55530f YS |
2938 | sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */ |
2939 | sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */ | |
2940 | sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */ | |
2941 | sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */ | |
2942 | sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */ | |
2943 | sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */ | |
2944 | sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */ | |
86a74ff2 NI |
2945 | } |
2946 | ||
2947 | /* MDIO bus release function */ | |
bd920ff5 | 2948 | static int sh_mdio_release(struct sh_eth_private *mdp) |
86a74ff2 | 2949 | { |
86a74ff2 | 2950 | /* unregister mdio bus */ |
bd920ff5 | 2951 | mdiobus_unregister(mdp->mii_bus); |
86a74ff2 NI |
2952 | |
2953 | /* free bitbang info */ | |
bd920ff5 | 2954 | free_mdio_bitbang(mdp->mii_bus); |
86a74ff2 NI |
2955 | |
2956 | return 0; | |
2957 | } | |
2958 | ||
2959 | /* MDIO bus init function */ | |
bd920ff5 | 2960 | static int sh_mdio_init(struct sh_eth_private *mdp, |
b3017e6a | 2961 | struct sh_eth_plat_data *pd) |
86a74ff2 | 2962 | { |
e7f4dc35 | 2963 | int ret; |
86a74ff2 | 2964 | struct bb_info *bitbang; |
bd920ff5 | 2965 | struct platform_device *pdev = mdp->pdev; |
aa8d4225 | 2966 | struct device *dev = &mdp->pdev->dev; |
86a74ff2 NI |
2967 | |
2968 | /* create bit control struct for PHY */ | |
aa8d4225 | 2969 | bitbang = devm_kzalloc(dev, sizeof(struct bb_info), GFP_KERNEL); |
f738a13d LP |
2970 | if (!bitbang) |
2971 | return -ENOMEM; | |
86a74ff2 NI |
2972 | |
2973 | /* bitbang init */ | |
ae70644d | 2974 | bitbang->addr = mdp->addr + mdp->reg_offset[PIR]; |
b3017e6a | 2975 | bitbang->set_gate = pd->set_mdio_gate; |
86a74ff2 NI |
2976 | bitbang->ctrl.ops = &bb_ops; |
2977 | ||
c2e07b3a | 2978 | /* MII controller setting */ |
86a74ff2 | 2979 | mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl); |
f738a13d LP |
2980 | if (!mdp->mii_bus) |
2981 | return -ENOMEM; | |
86a74ff2 NI |
2982 | |
2983 | /* Hook up MII support for ethtool */ | |
2984 | mdp->mii_bus->name = "sh_mii"; | |
a5bd6060 | 2985 | mdp->mii_bus->parent = dev; |
5278fb54 | 2986 | snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", |
bd920ff5 | 2987 | pdev->name, pdev->id); |
86a74ff2 | 2988 | |
bd920ff5 LP |
2989 | /* register MDIO bus */ |
2990 | if (dev->of_node) { | |
2991 | ret = of_mdiobus_register(mdp->mii_bus, dev->of_node); | |
702eca02 | 2992 | } else { |
702eca02 BD |
2993 | if (pd->phy_irq > 0) |
2994 | mdp->mii_bus->irq[pd->phy] = pd->phy_irq; | |
2995 | ||
2996 | ret = mdiobus_register(mdp->mii_bus); | |
2997 | } | |
2998 | ||
86a74ff2 | 2999 | if (ret) |
d5e07e69 | 3000 | goto out_free_bus; |
86a74ff2 | 3001 | |
86a74ff2 NI |
3002 | return 0; |
3003 | ||
86a74ff2 | 3004 | out_free_bus: |
298cf9be | 3005 | free_mdio_bitbang(mdp->mii_bus); |
86a74ff2 NI |
3006 | return ret; |
3007 | } | |
3008 | ||
4a55530f YS |
3009 | static const u16 *sh_eth_get_register_offset(int register_type) |
3010 | { | |
3011 | const u16 *reg_offset = NULL; | |
3012 | ||
3013 | switch (register_type) { | |
3014 | case SH_ETH_REG_GIGABIT: | |
3015 | reg_offset = sh_eth_offset_gigabit; | |
3016 | break; | |
db893473 SH |
3017 | case SH_ETH_REG_FAST_RZ: |
3018 | reg_offset = sh_eth_offset_fast_rz; | |
3019 | break; | |
a3f109bd SS |
3020 | case SH_ETH_REG_FAST_RCAR: |
3021 | reg_offset = sh_eth_offset_fast_rcar; | |
3022 | break; | |
4a55530f YS |
3023 | case SH_ETH_REG_FAST_SH4: |
3024 | reg_offset = sh_eth_offset_fast_sh4; | |
3025 | break; | |
3026 | case SH_ETH_REG_FAST_SH3_SH2: | |
3027 | reg_offset = sh_eth_offset_fast_sh3_sh2; | |
3028 | break; | |
4a55530f YS |
3029 | } |
3030 | ||
3031 | return reg_offset; | |
3032 | } | |
3033 | ||
8f728d79 | 3034 | static const struct net_device_ops sh_eth_netdev_ops = { |
ebf84eaa AB |
3035 | .ndo_open = sh_eth_open, |
3036 | .ndo_stop = sh_eth_close, | |
3037 | .ndo_start_xmit = sh_eth_start_xmit, | |
3038 | .ndo_get_stats = sh_eth_get_stats, | |
b37feed7 | 3039 | .ndo_set_rx_mode = sh_eth_set_rx_mode, |
ebf84eaa AB |
3040 | .ndo_tx_timeout = sh_eth_tx_timeout, |
3041 | .ndo_do_ioctl = sh_eth_do_ioctl, | |
78d61022 | 3042 | .ndo_change_mtu = sh_eth_change_mtu, |
ebf84eaa AB |
3043 | .ndo_validate_addr = eth_validate_addr, |
3044 | .ndo_set_mac_address = eth_mac_addr, | |
ebf84eaa AB |
3045 | }; |
3046 | ||
8f728d79 SS |
3047 | static const struct net_device_ops sh_eth_netdev_ops_tsu = { |
3048 | .ndo_open = sh_eth_open, | |
3049 | .ndo_stop = sh_eth_close, | |
3050 | .ndo_start_xmit = sh_eth_start_xmit, | |
3051 | .ndo_get_stats = sh_eth_get_stats, | |
b37feed7 | 3052 | .ndo_set_rx_mode = sh_eth_set_rx_mode, |
8f728d79 SS |
3053 | .ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid, |
3054 | .ndo_vlan_rx_kill_vid = sh_eth_vlan_rx_kill_vid, | |
3055 | .ndo_tx_timeout = sh_eth_tx_timeout, | |
3056 | .ndo_do_ioctl = sh_eth_do_ioctl, | |
78d61022 | 3057 | .ndo_change_mtu = sh_eth_change_mtu, |
8f728d79 SS |
3058 | .ndo_validate_addr = eth_validate_addr, |
3059 | .ndo_set_mac_address = eth_mac_addr, | |
8f728d79 SS |
3060 | }; |
3061 | ||
b356e978 SS |
3062 | #ifdef CONFIG_OF |
3063 | static struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev) | |
3064 | { | |
3065 | struct device_node *np = dev->of_node; | |
3066 | struct sh_eth_plat_data *pdata; | |
b356e978 SS |
3067 | const char *mac_addr; |
3068 | ||
3069 | pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); | |
3070 | if (!pdata) | |
3071 | return NULL; | |
3072 | ||
3073 | pdata->phy_interface = of_get_phy_mode(np); | |
3074 | ||
b356e978 SS |
3075 | mac_addr = of_get_mac_address(np); |
3076 | if (mac_addr) | |
3077 | memcpy(pdata->mac_addr, mac_addr, ETH_ALEN); | |
3078 | ||
3079 | pdata->no_ether_link = | |
3080 | of_property_read_bool(np, "renesas,no-ether-link"); | |
3081 | pdata->ether_link_active_low = | |
3082 | of_property_read_bool(np, "renesas,ether-link-active-low"); | |
3083 | ||
3084 | return pdata; | |
3085 | } | |
3086 | ||
3087 | static const struct of_device_id sh_eth_match_table[] = { | |
3088 | { .compatible = "renesas,gether-r8a7740", .data = &r8a7740_data }, | |
c099ff3c SS |
3089 | { .compatible = "renesas,ether-r8a7743", .data = &r8a779x_data }, |
3090 | { .compatible = "renesas,ether-r8a7745", .data = &r8a779x_data }, | |
b356e978 SS |
3091 | { .compatible = "renesas,ether-r8a7778", .data = &r8a777x_data }, |
3092 | { .compatible = "renesas,ether-r8a7779", .data = &r8a777x_data }, | |
3093 | { .compatible = "renesas,ether-r8a7790", .data = &r8a779x_data }, | |
3094 | { .compatible = "renesas,ether-r8a7791", .data = &r8a779x_data }, | |
9488e1e5 | 3095 | { .compatible = "renesas,ether-r8a7793", .data = &r8a779x_data }, |
0f76b9d8 | 3096 | { .compatible = "renesas,ether-r8a7794", .data = &r8a779x_data }, |
b356e978 SS |
3097 | { .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data }, |
3098 | { } | |
3099 | }; | |
3100 | MODULE_DEVICE_TABLE(of, sh_eth_match_table); | |
3101 | #else | |
3102 | static inline struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev) | |
3103 | { | |
3104 | return NULL; | |
3105 | } | |
3106 | #endif | |
3107 | ||
86a74ff2 NI |
3108 | static int sh_eth_drv_probe(struct platform_device *pdev) |
3109 | { | |
86a74ff2 | 3110 | struct resource *res; |
0b76b862 | 3111 | struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev); |
afe391ad | 3112 | const struct platform_device_id *id = platform_get_device_id(pdev); |
4fa8c3cc SS |
3113 | struct sh_eth_private *mdp; |
3114 | struct net_device *ndev; | |
3115 | int ret, devno; | |
86a74ff2 NI |
3116 | |
3117 | /* get base addr */ | |
3118 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
86a74ff2 NI |
3119 | |
3120 | ndev = alloc_etherdev(sizeof(struct sh_eth_private)); | |
f738a13d LP |
3121 | if (!ndev) |
3122 | return -ENOMEM; | |
86a74ff2 | 3123 | |
b5893a08 BD |
3124 | pm_runtime_enable(&pdev->dev); |
3125 | pm_runtime_get_sync(&pdev->dev); | |
3126 | ||
86a74ff2 NI |
3127 | devno = pdev->id; |
3128 | if (devno < 0) | |
3129 | devno = 0; | |
3130 | ||
cc3c080d | 3131 | ret = platform_get_irq(pdev, 0); |
7a468ac6 | 3132 | if (ret < 0) |
86a74ff2 | 3133 | goto out_release; |
cc3c080d | 3134 | ndev->irq = ret; |
86a74ff2 NI |
3135 | |
3136 | SET_NETDEV_DEV(ndev, &pdev->dev); | |
3137 | ||
86a74ff2 | 3138 | mdp = netdev_priv(ndev); |
525b8075 YS |
3139 | mdp->num_tx_ring = TX_RING_SIZE; |
3140 | mdp->num_rx_ring = RX_RING_SIZE; | |
d5e07e69 SS |
3141 | mdp->addr = devm_ioremap_resource(&pdev->dev, res); |
3142 | if (IS_ERR(mdp->addr)) { | |
3143 | ret = PTR_ERR(mdp->addr); | |
ae70644d YS |
3144 | goto out_release; |
3145 | } | |
3146 | ||
d8981d02 NS |
3147 | /* Get clock, if not found that's OK but Wake-On-Lan is unavailable */ |
3148 | mdp->clk = devm_clk_get(&pdev->dev, NULL); | |
3149 | if (IS_ERR(mdp->clk)) | |
3150 | mdp->clk = NULL; | |
3151 | ||
c960804f VB |
3152 | ndev->base_addr = res->start; |
3153 | ||
86a74ff2 | 3154 | spin_lock_init(&mdp->lock); |
bcd5149d | 3155 | mdp->pdev = pdev; |
86a74ff2 | 3156 | |
b356e978 SS |
3157 | if (pdev->dev.of_node) |
3158 | pd = sh_eth_parse_dt(&pdev->dev); | |
3b4c5cbf SS |
3159 | if (!pd) { |
3160 | dev_err(&pdev->dev, "no platform data\n"); | |
3161 | ret = -EINVAL; | |
3162 | goto out_release; | |
3163 | } | |
3164 | ||
86a74ff2 | 3165 | /* get PHY ID */ |
71557a37 | 3166 | mdp->phy_id = pd->phy; |
e47c9052 | 3167 | mdp->phy_interface = pd->phy_interface; |
4923576b YS |
3168 | mdp->no_ether_link = pd->no_ether_link; |
3169 | mdp->ether_link_active_low = pd->ether_link_active_low; | |
86a74ff2 | 3170 | |
380af9e3 | 3171 | /* set cpu data */ |
42a67c9b | 3172 | if (id) |
b356e978 | 3173 | mdp->cd = (struct sh_eth_cpu_data *)id->driver_data; |
42a67c9b WS |
3174 | else |
3175 | mdp->cd = (struct sh_eth_cpu_data *)of_device_get_match_data(&pdev->dev); | |
b356e978 | 3176 | |
a3153d8c | 3177 | mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type); |
264be2f5 SS |
3178 | if (!mdp->reg_offset) { |
3179 | dev_err(&pdev->dev, "Unknown register type (%d)\n", | |
3180 | mdp->cd->register_type); | |
3181 | ret = -EINVAL; | |
3182 | goto out_release; | |
3183 | } | |
380af9e3 YS |
3184 | sh_eth_set_default_cpu_data(mdp->cd); |
3185 | ||
78d61022 NS |
3186 | /* User's manual states max MTU should be 2048 but due to the |
3187 | * alignment calculations in sh_eth_ring_init() the practical | |
3188 | * MTU is a bit less. Maybe this can be optimized some more. | |
3189 | */ | |
3190 | ndev->max_mtu = 2000 - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN); | |
3191 | ndev->min_mtu = ETH_MIN_MTU; | |
3192 | ||
86a74ff2 | 3193 | /* set function */ |
8f728d79 SS |
3194 | if (mdp->cd->tsu) |
3195 | ndev->netdev_ops = &sh_eth_netdev_ops_tsu; | |
3196 | else | |
3197 | ndev->netdev_ops = &sh_eth_netdev_ops; | |
7ad24ea4 | 3198 | ndev->ethtool_ops = &sh_eth_ethtool_ops; |
86a74ff2 NI |
3199 | ndev->watchdog_timeo = TX_TIMEOUT; |
3200 | ||
dc19e4e5 NI |
3201 | /* debug message level */ |
3202 | mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE; | |
86a74ff2 NI |
3203 | |
3204 | /* read and set MAC address */ | |
748031f9 | 3205 | read_mac_address(ndev, pd->mac_addr); |
ff6e7228 SS |
3206 | if (!is_valid_ether_addr(ndev->dev_addr)) { |
3207 | dev_warn(&pdev->dev, | |
3208 | "no valid MAC address supplied, using a random one.\n"); | |
3209 | eth_hw_addr_random(ndev); | |
3210 | } | |
86a74ff2 | 3211 | |
6ba88021 YS |
3212 | /* ioremap the TSU registers */ |
3213 | if (mdp->cd->tsu) { | |
3214 | struct resource *rtsu; | |
3215 | rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
d5e07e69 SS |
3216 | mdp->tsu_addr = devm_ioremap_resource(&pdev->dev, rtsu); |
3217 | if (IS_ERR(mdp->tsu_addr)) { | |
3218 | ret = PTR_ERR(mdp->tsu_addr); | |
fc0c0900 SS |
3219 | goto out_release; |
3220 | } | |
6743fe6d | 3221 | mdp->port = devno % 2; |
f646968f | 3222 | ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER; |
6ba88021 YS |
3223 | } |
3224 | ||
150647fb YS |
3225 | /* initialize first or needed device */ |
3226 | if (!devno || pd->needs_init) { | |
380af9e3 YS |
3227 | if (mdp->cd->chip_reset) |
3228 | mdp->cd->chip_reset(ndev); | |
86a74ff2 | 3229 | |
4986b996 YS |
3230 | if (mdp->cd->tsu) { |
3231 | /* TSU init (Init only)*/ | |
3232 | sh_eth_tsu_init(mdp); | |
3233 | } | |
86a74ff2 NI |
3234 | } |
3235 | ||
966d6dbb HN |
3236 | if (mdp->cd->rmiimode) |
3237 | sh_eth_write(ndev, 0x1, RMIIMODE); | |
3238 | ||
daacf03f LP |
3239 | /* MDIO bus init */ |
3240 | ret = sh_mdio_init(mdp, pd); | |
3241 | if (ret) { | |
b7ce520e GU |
3242 | if (ret != -EPROBE_DEFER) |
3243 | dev_err(&pdev->dev, "MDIO init failed: %d\n", ret); | |
daacf03f LP |
3244 | goto out_release; |
3245 | } | |
3246 | ||
3719109d SS |
3247 | netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64); |
3248 | ||
86a74ff2 NI |
3249 | /* network device register */ |
3250 | ret = register_netdev(ndev); | |
3251 | if (ret) | |
3719109d | 3252 | goto out_napi_del; |
86a74ff2 | 3253 | |
d8981d02 NS |
3254 | if (mdp->cd->magic && mdp->clk) |
3255 | device_set_wakeup_capable(&pdev->dev, 1); | |
3256 | ||
25985edc | 3257 | /* print device information */ |
f75f14ec SS |
3258 | netdev_info(ndev, "Base address at 0x%x, %pM, IRQ %d.\n", |
3259 | (u32)ndev->base_addr, ndev->dev_addr, ndev->irq); | |
86a74ff2 | 3260 | |
b5893a08 | 3261 | pm_runtime_put(&pdev->dev); |
86a74ff2 NI |
3262 | platform_set_drvdata(pdev, ndev); |
3263 | ||
3264 | return ret; | |
3265 | ||
3719109d SS |
3266 | out_napi_del: |
3267 | netif_napi_del(&mdp->napi); | |
daacf03f | 3268 | sh_mdio_release(mdp); |
3719109d | 3269 | |
86a74ff2 NI |
3270 | out_release: |
3271 | /* net_dev free */ | |
3272 | if (ndev) | |
3273 | free_netdev(ndev); | |
3274 | ||
b5893a08 BD |
3275 | pm_runtime_put(&pdev->dev); |
3276 | pm_runtime_disable(&pdev->dev); | |
86a74ff2 NI |
3277 | return ret; |
3278 | } | |
3279 | ||
3280 | static int sh_eth_drv_remove(struct platform_device *pdev) | |
3281 | { | |
3282 | struct net_device *ndev = platform_get_drvdata(pdev); | |
3719109d | 3283 | struct sh_eth_private *mdp = netdev_priv(ndev); |
86a74ff2 | 3284 | |
86a74ff2 | 3285 | unregister_netdev(ndev); |
3719109d | 3286 | netif_napi_del(&mdp->napi); |
daacf03f | 3287 | sh_mdio_release(mdp); |
bcd5149d | 3288 | pm_runtime_disable(&pdev->dev); |
86a74ff2 | 3289 | free_netdev(ndev); |
86a74ff2 NI |
3290 | |
3291 | return 0; | |
3292 | } | |
3293 | ||
540ad1b8 | 3294 | #ifdef CONFIG_PM |
b71af046 | 3295 | #ifdef CONFIG_PM_SLEEP |
d8981d02 NS |
3296 | static int sh_eth_wol_setup(struct net_device *ndev) |
3297 | { | |
3298 | struct sh_eth_private *mdp = netdev_priv(ndev); | |
3299 | ||
3300 | /* Only allow ECI interrupts */ | |
3301 | synchronize_irq(ndev->irq); | |
3302 | napi_disable(&mdp->napi); | |
1a0bee6c | 3303 | sh_eth_write(ndev, EESIPR_ECIIP, EESIPR); |
d8981d02 NS |
3304 | |
3305 | /* Enable MagicPacket */ | |
5e2ed132 | 3306 | sh_eth_modify(ndev, ECMR, ECMR_MPDE, ECMR_MPDE); |
d8981d02 NS |
3307 | |
3308 | /* Increased clock usage so device won't be suspended */ | |
3309 | clk_enable(mdp->clk); | |
3310 | ||
3311 | return enable_irq_wake(ndev->irq); | |
3312 | } | |
3313 | ||
3314 | static int sh_eth_wol_restore(struct net_device *ndev) | |
3315 | { | |
3316 | struct sh_eth_private *mdp = netdev_priv(ndev); | |
3317 | int ret; | |
3318 | ||
3319 | napi_enable(&mdp->napi); | |
3320 | ||
3321 | /* Disable MagicPacket */ | |
3322 | sh_eth_modify(ndev, ECMR, ECMR_MPDE, 0); | |
3323 | ||
3324 | /* The device needs to be reset to restore MagicPacket logic | |
3325 | * for next wakeup. If we close and open the device it will | |
3326 | * both be reset and all registers restored. This is what | |
3327 | * happens during suspend and resume without WoL enabled. | |
3328 | */ | |
3329 | ret = sh_eth_close(ndev); | |
3330 | if (ret < 0) | |
3331 | return ret; | |
3332 | ret = sh_eth_open(ndev); | |
3333 | if (ret < 0) | |
3334 | return ret; | |
3335 | ||
3336 | /* Restore clock usage count */ | |
3337 | clk_disable(mdp->clk); | |
3338 | ||
3339 | return disable_irq_wake(ndev->irq); | |
3340 | } | |
3341 | ||
b71af046 MU |
3342 | static int sh_eth_suspend(struct device *dev) |
3343 | { | |
3344 | struct net_device *ndev = dev_get_drvdata(dev); | |
d8981d02 | 3345 | struct sh_eth_private *mdp = netdev_priv(ndev); |
b71af046 MU |
3346 | int ret = 0; |
3347 | ||
d8981d02 NS |
3348 | if (!netif_running(ndev)) |
3349 | return 0; | |
3350 | ||
3351 | netif_device_detach(ndev); | |
3352 | ||
3353 | if (mdp->wol_enabled) | |
3354 | ret = sh_eth_wol_setup(ndev); | |
3355 | else | |
b71af046 | 3356 | ret = sh_eth_close(ndev); |
b71af046 MU |
3357 | |
3358 | return ret; | |
3359 | } | |
3360 | ||
3361 | static int sh_eth_resume(struct device *dev) | |
3362 | { | |
3363 | struct net_device *ndev = dev_get_drvdata(dev); | |
d8981d02 | 3364 | struct sh_eth_private *mdp = netdev_priv(ndev); |
b71af046 MU |
3365 | int ret = 0; |
3366 | ||
d8981d02 NS |
3367 | if (!netif_running(ndev)) |
3368 | return 0; | |
3369 | ||
3370 | if (mdp->wol_enabled) | |
3371 | ret = sh_eth_wol_restore(ndev); | |
3372 | else | |
b71af046 | 3373 | ret = sh_eth_open(ndev); |
d8981d02 NS |
3374 | |
3375 | if (ret < 0) | |
3376 | return ret; | |
3377 | ||
3378 | netif_device_attach(ndev); | |
b71af046 MU |
3379 | |
3380 | return ret; | |
3381 | } | |
3382 | #endif | |
3383 | ||
bcd5149d MD |
3384 | static int sh_eth_runtime_nop(struct device *dev) |
3385 | { | |
128296fc | 3386 | /* Runtime PM callback shared between ->runtime_suspend() |
bcd5149d MD |
3387 | * and ->runtime_resume(). Simply returns success. |
3388 | * | |
3389 | * This driver re-initializes all registers after | |
3390 | * pm_runtime_get_sync() anyway so there is no need | |
3391 | * to save and restore registers here. | |
3392 | */ | |
3393 | return 0; | |
3394 | } | |
3395 | ||
540ad1b8 | 3396 | static const struct dev_pm_ops sh_eth_dev_pm_ops = { |
b71af046 | 3397 | SET_SYSTEM_SLEEP_PM_OPS(sh_eth_suspend, sh_eth_resume) |
e7d7e898 | 3398 | SET_RUNTIME_PM_OPS(sh_eth_runtime_nop, sh_eth_runtime_nop, NULL) |
bcd5149d | 3399 | }; |
540ad1b8 NI |
3400 | #define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops) |
3401 | #else | |
3402 | #define SH_ETH_PM_OPS NULL | |
3403 | #endif | |
bcd5149d | 3404 | |
afe391ad | 3405 | static struct platform_device_id sh_eth_id_table[] = { |
c18a79ab | 3406 | { "sh7619-ether", (kernel_ulong_t)&sh7619_data }, |
7bbe150d | 3407 | { "sh771x-ether", (kernel_ulong_t)&sh771x_data }, |
9c3beaab | 3408 | { "sh7724-ether", (kernel_ulong_t)&sh7724_data }, |
f5d12767 | 3409 | { "sh7734-gether", (kernel_ulong_t)&sh7734_data }, |
24549e2a SS |
3410 | { "sh7757-ether", (kernel_ulong_t)&sh7757_data }, |
3411 | { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga }, | |
f5d12767 | 3412 | { "sh7763-gether", (kernel_ulong_t)&sh7763_data }, |
afe391ad SS |
3413 | { } |
3414 | }; | |
3415 | MODULE_DEVICE_TABLE(platform, sh_eth_id_table); | |
3416 | ||
86a74ff2 NI |
3417 | static struct platform_driver sh_eth_driver = { |
3418 | .probe = sh_eth_drv_probe, | |
3419 | .remove = sh_eth_drv_remove, | |
afe391ad | 3420 | .id_table = sh_eth_id_table, |
86a74ff2 NI |
3421 | .driver = { |
3422 | .name = CARDNAME, | |
540ad1b8 | 3423 | .pm = SH_ETH_PM_OPS, |
b356e978 | 3424 | .of_match_table = of_match_ptr(sh_eth_match_table), |
86a74ff2 NI |
3425 | }, |
3426 | }; | |
3427 | ||
db62f684 | 3428 | module_platform_driver(sh_eth_driver); |
86a74ff2 NI |
3429 | |
3430 | MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda"); | |
3431 | MODULE_DESCRIPTION("Renesas SuperH Ethernet driver"); | |
3432 | MODULE_LICENSE("GPL v2"); |