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Merge branch 'MDIO-bus-reset-GPIO-cleanups'
[mirror_ubuntu-jammy-kernel.git] / drivers / net / ethernet / renesas / sh_eth.c
CommitLineData
128296fc 1/* SuperH Ethernet device driver
86a74ff2 2 *
9b39f05c 3 * Copyright (C) 2014 Renesas Electronics Corporation
f0e81fec 4 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu
b356e978 5 * Copyright (C) 2008-2014 Renesas Solutions Corp.
9b39f05c 6 * Copyright (C) 2013-2017 Cogent Embedded, Inc.
702eca02 7 * Copyright (C) 2014 Codethink Limited
86a74ff2
NI		 8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms and conditions of the GNU General Public License,
11 * version 2, as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
86a74ff2
NI		 17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 */
21
0654011d
YS		 22#include <linux/module.h>
23#include <linux/kernel.h>
24#include <linux/spinlock.h>
6a27cded 25#include <linux/interrupt.h>
86a74ff2
NI		 26#include <linux/dma-mapping.h>
27#include <linux/etherdevice.h>
28#include <linux/delay.h>
29#include <linux/platform_device.h>
30#include <linux/mdio-bitbang.h>
31#include <linux/netdevice.h>
b356e978
SS		 32#include <linux/of.h>
33#include <linux/of_device.h>
34#include <linux/of_irq.h>
35#include <linux/of_net.h>
86a74ff2
NI		 36#include <linux/phy.h>
37#include <linux/cache.h>
38#include <linux/io.h>
bcd5149d 39#include <linux/pm_runtime.h>
5a0e3ad6 40#include <linux/slab.h>
dc19e4e5 41#include <linux/ethtool.h>
fdb37a7f 42#include <linux/if_vlan.h>
f0e81fec 43#include <linux/clk.h>
d4fa0e35 44#include <linux/sh_eth.h>
702eca02 45#include <linux/of_mdio.h>
86a74ff2
NI		 46
47#include "sh_eth.h"
48
dc19e4e5
NI		 49#define SH_ETH_DEF_MSG_ENABLE \
50 (NETIF_MSG_LINK | \
51 NETIF_MSG_TIMER | \
52 NETIF_MSG_RX_ERR| \
53 NETIF_MSG_TX_ERR)
54
2274d375
SS		 55#define SH_ETH_OFFSET_INVALID ((u16)~0)
56
3365711d
BH		 57#define SH_ETH_OFFSET_DEFAULTS \
58 [0 ... SH_ETH_MAX_REGISTER_OFFSET - 1] = SH_ETH_OFFSET_INVALID
59
c0013f6f 60static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
3365711d
BH		 61 SH_ETH_OFFSET_DEFAULTS,
62
c0013f6f
SS		 63 [EDSR] = 0x0000,
64 [EDMR] = 0x0400,
65 [EDTRR] = 0x0408,
66 [EDRRR] = 0x0410,
67 [EESR] = 0x0428,
68 [EESIPR] = 0x0430,
69 [TDLAR] = 0x0010,
70 [TDFAR] = 0x0014,
71 [TDFXR] = 0x0018,
72 [TDFFR] = 0x001c,
73 [RDLAR] = 0x0030,
74 [RDFAR] = 0x0034,
75 [RDFXR] = 0x0038,
76 [RDFFR] = 0x003c,
77 [TRSCER] = 0x0438,
78 [RMFCR] = 0x0440,
79 [TFTR] = 0x0448,
80 [FDR] = 0x0450,
81 [RMCR] = 0x0458,
82 [RPADIR] = 0x0460,
83 [FCFTR] = 0x0468,
84 [CSMR] = 0x04E4,
85
86 [ECMR] = 0x0500,
87 [ECSR] = 0x0510,
88 [ECSIPR] = 0x0518,
89 [PIR] = 0x0520,
90 [PSR] = 0x0528,
91 [PIPR] = 0x052c,
92 [RFLR] = 0x0508,
93 [APR] = 0x0554,
94 [MPR] = 0x0558,
95 [PFTCR] = 0x055c,
96 [PFRCR] = 0x0560,
97 [TPAUSER] = 0x0564,
98 [GECMR] = 0x05b0,
99 [BCULR] = 0x05b4,
100 [MAHR] = 0x05c0,
101 [MALR] = 0x05c8,
102 [TROCR] = 0x0700,
103 [CDCR] = 0x0708,
104 [LCCR] = 0x0710,
105 [CEFCR] = 0x0740,
106 [FRECR] = 0x0748,
107 [TSFRCR] = 0x0750,
108 [TLFRCR] = 0x0758,
109 [RFCR] = 0x0760,
110 [CERCR] = 0x0768,
111 [CEECR] = 0x0770,
112 [MAFCR] = 0x0778,
113 [RMII_MII] = 0x0790,
114
115 [ARSTR] = 0x0000,
116 [TSU_CTRST] = 0x0004,
117 [TSU_FWEN0] = 0x0010,
118 [TSU_FWEN1] = 0x0014,
119 [TSU_FCM] = 0x0018,
120 [TSU_BSYSL0] = 0x0020,
121 [TSU_BSYSL1] = 0x0024,
122 [TSU_PRISL0] = 0x0028,
123 [TSU_PRISL1] = 0x002c,
124 [TSU_FWSL0] = 0x0030,
125 [TSU_FWSL1] = 0x0034,
126 [TSU_FWSLC] = 0x0038,
127 [TSU_QTAG0] = 0x0040,
128 [TSU_QTAG1] = 0x0044,
129 [TSU_FWSR] = 0x0050,
130 [TSU_FWINMK] = 0x0054,
131 [TSU_ADQT0] = 0x0048,
132 [TSU_ADQT1] = 0x004c,
133 [TSU_VTAG0] = 0x0058,
134 [TSU_VTAG1] = 0x005c,
135 [TSU_ADSBSY] = 0x0060,
136 [TSU_TEN] = 0x0064,
137 [TSU_POST1] = 0x0070,
138 [TSU_POST2] = 0x0074,
139 [TSU_POST3] = 0x0078,
140 [TSU_POST4] = 0x007c,
141 [TSU_ADRH0] = 0x0100,
c0013f6f
SS		 142
143 [TXNLCR0] = 0x0080,
144 [TXALCR0] = 0x0084,
145 [RXNLCR0] = 0x0088,
146 [RXALCR0] = 0x008c,
147 [FWNLCR0] = 0x0090,
148 [FWALCR0] = 0x0094,
149 [TXNLCR1] = 0x00a0,
150 [TXALCR1] = 0x00a0,
151 [RXNLCR1] = 0x00a8,
152 [RXALCR1] = 0x00ac,
153 [FWNLCR1] = 0x00b0,
154 [FWALCR1] = 0x00b4,
155};
156
db893473 157static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
3365711d
BH		 158 SH_ETH_OFFSET_DEFAULTS,
159
db893473
SH		 160 [EDSR] = 0x0000,
161 [EDMR] = 0x0400,
162 [EDTRR] = 0x0408,
163 [EDRRR] = 0x0410,
164 [EESR] = 0x0428,
165 [EESIPR] = 0x0430,
166 [TDLAR] = 0x0010,
167 [TDFAR] = 0x0014,
168 [TDFXR] = 0x0018,
169 [TDFFR] = 0x001c,
170 [RDLAR] = 0x0030,
171 [RDFAR] = 0x0034,
172 [RDFXR] = 0x0038,
173 [RDFFR] = 0x003c,
174 [TRSCER] = 0x0438,
175 [RMFCR] = 0x0440,
176 [TFTR] = 0x0448,
177 [FDR] = 0x0450,
178 [RMCR] = 0x0458,
179 [RPADIR] = 0x0460,
180 [FCFTR] = 0x0468,
181 [CSMR] = 0x04E4,
182
183 [ECMR] = 0x0500,
184 [RFLR] = 0x0508,
185 [ECSR] = 0x0510,
186 [ECSIPR] = 0x0518,
187 [PIR] = 0x0520,
188 [APR] = 0x0554,
189 [MPR] = 0x0558,
190 [PFTCR] = 0x055c,
191 [PFRCR] = 0x0560,
192 [TPAUSER] = 0x0564,
193 [MAHR] = 0x05c0,
194 [MALR] = 0x05c8,
195 [CEFCR] = 0x0740,
196 [FRECR] = 0x0748,
197 [TSFRCR] = 0x0750,
198 [TLFRCR] = 0x0758,
199 [RFCR] = 0x0760,
200 [MAFCR] = 0x0778,
201
202 [ARSTR] = 0x0000,
203 [TSU_CTRST] = 0x0004,
e1487888 204 [TSU_FWSLC] = 0x0038,
db893473
SH		 205 [TSU_VTAG0] = 0x0058,
206 [TSU_ADSBSY] = 0x0060,
207 [TSU_TEN] = 0x0064,
e1487888
CB		 208 [TSU_POST1] = 0x0070,
209 [TSU_POST2] = 0x0074,
210 [TSU_POST3] = 0x0078,
211 [TSU_POST4] = 0x007c,
db893473 212 [TSU_ADRH0] = 0x0100,
db893473
SH		 213
214 [TXNLCR0] = 0x0080,
215 [TXALCR0] = 0x0084,
216 [RXNLCR0] = 0x0088,
217 [RXALCR0] = 0x008C,
218};
219
a3f109bd 220static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
3365711d
BH		 221 SH_ETH_OFFSET_DEFAULTS,
222
a3f109bd
SS		 223 [ECMR] = 0x0300,
224 [RFLR] = 0x0308,
225 [ECSR] = 0x0310,
226 [ECSIPR] = 0x0318,
227 [PIR] = 0x0320,
228 [PSR] = 0x0328,
229 [RDMLR] = 0x0340,
230 [IPGR] = 0x0350,
231 [APR] = 0x0354,
232 [MPR] = 0x0358,
233 [RFCF] = 0x0360,
234 [TPAUSER] = 0x0364,
235 [TPAUSECR] = 0x0368,
236 [MAHR] = 0x03c0,
237 [MALR] = 0x03c8,
238 [TROCR] = 0x03d0,
239 [CDCR] = 0x03d4,
240 [LCCR] = 0x03d8,
241 [CNDCR] = 0x03dc,
242 [CEFCR] = 0x03e4,
243 [FRECR] = 0x03e8,
244 [TSFRCR] = 0x03ec,
245 [TLFRCR] = 0x03f0,
246 [RFCR] = 0x03f4,
247 [MAFCR] = 0x03f8,
248
249 [EDMR] = 0x0200,
250 [EDTRR] = 0x0208,
251 [EDRRR] = 0x0210,
252 [TDLAR] = 0x0218,
253 [RDLAR] = 0x0220,
254 [EESR] = 0x0228,
255 [EESIPR] = 0x0230,
256 [TRSCER] = 0x0238,
257 [RMFCR] = 0x0240,
258 [TFTR] = 0x0248,
259 [FDR] = 0x0250,
260 [RMCR] = 0x0258,
261 [TFUCR] = 0x0264,
262 [RFOCR] = 0x0268,
55754f19 263 [RMIIMODE] = 0x026c,
a3f109bd
SS		 264 [FCFTR] = 0x0270,
265 [TRIMD] = 0x027c,
266};
267
c0013f6f 268static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
3365711d
BH		 269 SH_ETH_OFFSET_DEFAULTS,
270
c0013f6f
SS		 271 [ECMR] = 0x0100,
272 [RFLR] = 0x0108,
273 [ECSR] = 0x0110,
274 [ECSIPR] = 0x0118,
275 [PIR] = 0x0120,
276 [PSR] = 0x0128,
277 [RDMLR] = 0x0140,
278 [IPGR] = 0x0150,
279 [APR] = 0x0154,
280 [MPR] = 0x0158,
281 [TPAUSER] = 0x0164,
282 [RFCF] = 0x0160,
283 [TPAUSECR] = 0x0168,
284 [BCFRR] = 0x016c,
285 [MAHR] = 0x01c0,
286 [MALR] = 0x01c8,
287 [TROCR] = 0x01d0,
288 [CDCR] = 0x01d4,
289 [LCCR] = 0x01d8,
290 [CNDCR] = 0x01dc,
291 [CEFCR] = 0x01e4,
292 [FRECR] = 0x01e8,
293 [TSFRCR] = 0x01ec,
294 [TLFRCR] = 0x01f0,
295 [RFCR] = 0x01f4,
296 [MAFCR] = 0x01f8,
297 [RTRATE] = 0x01fc,
298
299 [EDMR] = 0x0000,
300 [EDTRR] = 0x0008,
301 [EDRRR] = 0x0010,
302 [TDLAR] = 0x0018,
303 [RDLAR] = 0x0020,
304 [EESR] = 0x0028,
305 [EESIPR] = 0x0030,
306 [TRSCER] = 0x0038,
307 [RMFCR] = 0x0040,
308 [TFTR] = 0x0048,
309 [FDR] = 0x0050,
310 [RMCR] = 0x0058,
311 [TFUCR] = 0x0064,
312 [RFOCR] = 0x0068,
313 [FCFTR] = 0x0070,
314 [RPADIR] = 0x0078,
315 [TRIMD] = 0x007c,
316 [RBWAR] = 0x00c8,
317 [RDFAR] = 0x00cc,
318 [TBRAR] = 0x00d4,
319 [TDFAR] = 0x00d8,
320};
321
322static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
3365711d
BH		 323 SH_ETH_OFFSET_DEFAULTS,
324
d8b0426a
SS		 325 [EDMR] = 0x0000,
326 [EDTRR] = 0x0004,
327 [EDRRR] = 0x0008,
328 [TDLAR] = 0x000c,
329 [RDLAR] = 0x0010,
330 [EESR] = 0x0014,
331 [EESIPR] = 0x0018,
332 [TRSCER] = 0x001c,
333 [RMFCR] = 0x0020,
334 [TFTR] = 0x0024,
335 [FDR] = 0x0028,
336 [RMCR] = 0x002c,
337 [EDOCR] = 0x0030,
338 [FCFTR] = 0x0034,
339 [RPADIR] = 0x0038,
340 [TRIMD] = 0x003c,
341 [RBWAR] = 0x0040,
342 [RDFAR] = 0x0044,
343 [TBRAR] = 0x004c,
344 [TDFAR] = 0x0050,
345
c0013f6f
SS		 346 [ECMR] = 0x0160,
347 [ECSR] = 0x0164,
348 [ECSIPR] = 0x0168,
349 [PIR] = 0x016c,
350 [MAHR] = 0x0170,
351 [MALR] = 0x0174,
352 [RFLR] = 0x0178,
353 [PSR] = 0x017c,
354 [TROCR] = 0x0180,
355 [CDCR] = 0x0184,
356 [LCCR] = 0x0188,
357 [CNDCR] = 0x018c,
358 [CEFCR] = 0x0194,
359 [FRECR] = 0x0198,
360 [TSFRCR] = 0x019c,
361 [TLFRCR] = 0x01a0,
362 [RFCR] = 0x01a4,
363 [MAFCR] = 0x01a8,
364 [IPGR] = 0x01b4,
365 [APR] = 0x01b8,
366 [MPR] = 0x01bc,
367 [TPAUSER] = 0x01c4,
368 [BCFR] = 0x01cc,
369
370 [ARSTR] = 0x0000,
371 [TSU_CTRST] = 0x0004,
372 [TSU_FWEN0] = 0x0010,
373 [TSU_FWEN1] = 0x0014,
374 [TSU_FCM] = 0x0018,
375 [TSU_BSYSL0] = 0x0020,
376 [TSU_BSYSL1] = 0x0024,
377 [TSU_PRISL0] = 0x0028,
378 [TSU_PRISL1] = 0x002c,
379 [TSU_FWSL0] = 0x0030,
380 [TSU_FWSL1] = 0x0034,
381 [TSU_FWSLC] = 0x0038,
382 [TSU_QTAGM0] = 0x0040,
383 [TSU_QTAGM1] = 0x0044,
384 [TSU_ADQT0] = 0x0048,
385 [TSU_ADQT1] = 0x004c,
386 [TSU_FWSR] = 0x0050,
387 [TSU_FWINMK] = 0x0054,
388 [TSU_ADSBSY] = 0x0060,
389 [TSU_TEN] = 0x0064,
390 [TSU_POST1] = 0x0070,
391 [TSU_POST2] = 0x0074,
392 [TSU_POST3] = 0x0078,
393 [TSU_POST4] = 0x007c,
394
395 [TXNLCR0] = 0x0080,
396 [TXALCR0] = 0x0084,
397 [RXNLCR0] = 0x0088,
398 [RXALCR0] = 0x008c,
399 [FWNLCR0] = 0x0090,
400 [FWALCR0] = 0x0094,
401 [TXNLCR1] = 0x00a0,
402 [TXALCR1] = 0x00a0,
403 [RXNLCR1] = 0x00a8,
404 [RXALCR1] = 0x00ac,
405 [FWNLCR1] = 0x00b0,
406 [FWALCR1] = 0x00b4,
407
408 [TSU_ADRH0] = 0x0100,
c0013f6f
SS		 409};
410
740c7f31
BH		 411static void sh_eth_rcv_snd_disable(struct net_device *ndev);
412static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev);
413
2274d375
SS		 414static void sh_eth_write(struct net_device *ndev, u32 data, int enum_index)
415{
416 struct sh_eth_private *mdp = netdev_priv(ndev);
417 u16 offset = mdp->reg_offset[enum_index];
418
419 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
420 return;
421
422 iowrite32(data, mdp->addr + offset);
423}
424
425static u32 sh_eth_read(struct net_device *ndev, int enum_index)
426{
427 struct sh_eth_private *mdp = netdev_priv(ndev);
428 u16 offset = mdp->reg_offset[enum_index];
429
430 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
431 return ~0U;
432
433 return ioread32(mdp->addr + offset);
434}
435
b2b14d2f
SS		 436static void sh_eth_modify(struct net_device *ndev, int enum_index, u32 clear,
437 u32 set)
438{
439 sh_eth_write(ndev, (sh_eth_read(ndev, enum_index) & ~clear) | set,
440 enum_index);
441}
442
504c8ca5 443static bool sh_eth_is_gether(struct sh_eth_private *mdp)
dabdde9e 444{
504c8ca5 445 return mdp->reg_offset == sh_eth_offset_gigabit;
dabdde9e
NI		 446}
447
db893473
SH		 448static bool sh_eth_is_rz_fast_ether(struct sh_eth_private *mdp)
449{
450 return mdp->reg_offset == sh_eth_offset_fast_rz;
451}
452
8e994402 453static void sh_eth_select_mii(struct net_device *ndev)
5e7a76be 454{
5e7a76be 455 struct sh_eth_private *mdp = netdev_priv(ndev);
4fa8c3cc 456 u32 value;
5e7a76be
NI		 457
458 switch (mdp->phy_interface) {
459 case PHY_INTERFACE_MODE_GMII:
460 value = 0x2;
461 break;
462 case PHY_INTERFACE_MODE_MII:
463 value = 0x1;
464 break;
465 case PHY_INTERFACE_MODE_RMII:
466 value = 0x0;
467 break;
468 default:
f75f14ec
SS		 469 netdev_warn(ndev,
470 "PHY interface mode was not setup. Set to MII.\n");
5e7a76be
NI		 471 value = 0x1;
472 break;
473 }
474
475 sh_eth_write(ndev, value, RMII_MII);
476}
5e7a76be 477
8e994402 478static void sh_eth_set_duplex(struct net_device *ndev)
65ac8851
YS		 479{
480 struct sh_eth_private *mdp = netdev_priv(ndev);
65ac8851 481
b2b14d2f 482 sh_eth_modify(ndev, ECMR, ECMR_DM, mdp->duplex ? ECMR_DM : 0);
65ac8851
YS		 483}
484
99f84be6
GU		 485static void sh_eth_chip_reset(struct net_device *ndev)
486{
487 struct sh_eth_private *mdp = netdev_priv(ndev);
488
489 /* reset device */
ec65cfce 490 sh_eth_tsu_write(mdp, ARSTR_ARST, ARSTR);
99f84be6
GU		 491 mdelay(1);
492}
493
a0f48be3
GU		 494static void sh_eth_set_rate_gether(struct net_device *ndev)
495{
496 struct sh_eth_private *mdp = netdev_priv(ndev);
497
498 switch (mdp->speed) {
499 case 10: /* 10BASE */
500 sh_eth_write(ndev, GECMR_10, GECMR);
501 break;
502 case 100:/* 100BASE */
503 sh_eth_write(ndev, GECMR_100, GECMR);
504 break;
505 case 1000: /* 1000BASE */
506 sh_eth_write(ndev, GECMR_1000, GECMR);
507 break;
a0f48be3
GU		 508 }
509}
510
99f84be6
GU		 511#ifdef CONFIG_OF
512/* R7S72100 */
513static struct sh_eth_cpu_data r7s72100_data = {
514 .chip_reset = sh_eth_chip_reset,
515 .set_duplex = sh_eth_set_duplex,
516
517 .register_type = SH_ETH_REG_FAST_RZ,
518
519 .ecsr_value = ECSR_ICD,
520 .ecsipr_value = ECSIPR_ICDIP,
2b2d3eb4
SS		 521 .eesipr_value = EESIPR_TWB1IP | EESIPR_TWBIP | EESIPR_TC1IP |
522 EESIPR_TABTIP | EESIPR_RABTIP | EESIPR_RFCOFIP |
523 EESIPR_ECIIP |
524 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
525 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
526 EESIPR_RMAFIP | EESIPR_RRFIP |
527 EESIPR_RTLFIP | EESIPR_RTSFIP |
528 EESIPR_PREIP | EESIPR_CERFIP,
99f84be6
GU		 529
530 .tx_check = EESR_TC1 | EESR_FTC,
531 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
532 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
9b39f05c 533 EESR_TDE,
99f84be6
GU		 534 .fdr_value = 0x0000070f,
535
536 .no_psr = 1,
537 .apr = 1,
538 .mpr = 1,
539 .tpauser = 1,
540 .hw_swap = 1,
541 .rpadir = 1,
542 .rpadir_value = 2 << 16,
543 .no_trimd = 1,
544 .no_ade = 1,
62e04b7e 545 .hw_checksum = 1,
99f84be6 546 .tsu = 1,
99f84be6 547};
a0f48be3
GU		 548
549static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
550{
c66b2581 551 sh_eth_chip_reset(ndev);
a0f48be3
GU		 552
553 sh_eth_select_mii(ndev);
554}
555
556/* R8A7740 */
557static struct sh_eth_cpu_data r8a7740_data = {
558 .chip_reset = sh_eth_chip_reset_r8a7740,
559 .set_duplex = sh_eth_set_duplex,
560 .set_rate = sh_eth_set_rate_gether,
561
562 .register_type = SH_ETH_REG_GIGABIT,
563
564 .ecsr_value = ECSR_ICD | ECSR_MPD,
565 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
2b2d3eb4
SS		 566 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
567 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
568 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
569 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
570 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
571 EESIPR_CEEFIP | EESIPR_CELFIP |
572 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
573 EESIPR_PREIP | EESIPR_CERFIP,
a0f48be3
GU		 574
575 .tx_check = EESR_TC1 | EESR_FTC,
576 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
577 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
9b39f05c 578 EESR_TDE,
a0f48be3
GU		 579 .fdr_value = 0x0000070f,
580
581 .apr = 1,
582 .mpr = 1,
583 .tpauser = 1,
584 .bculr = 1,
585 .hw_swap = 1,
586 .rpadir = 1,
587 .rpadir_value = 2 << 16,
588 .no_trimd = 1,
589 .no_ade = 1,
62e04b7e 590 .hw_checksum = 1,
a0f48be3
GU		 591 .tsu = 1,
592 .select_mii = 1,
33017e24 593 .magic = 1,
a0f48be3 594};
99f84be6 595
04b0ed2a 596/* There is CPU dependent code */
589ebdef 597static void sh_eth_set_rate_r8a777x(struct net_device *ndev)
65ac8851
YS		 598{
599 struct sh_eth_private *mdp = netdev_priv(ndev);
d0418bb7 600
a3f109bd
SS		 601 switch (mdp->speed) {
602 case 10: /* 10BASE */
b2b14d2f 603 sh_eth_modify(ndev, ECMR, ECMR_ELB, 0);
a3f109bd
SS		 604 break;
605 case 100:/* 100BASE */
b2b14d2f 606 sh_eth_modify(ndev, ECMR, ECMR_ELB, ECMR_ELB);
a3f109bd 607 break;
a3f109bd
SS		 608 }
609}
610
674853b2 611/* R8A7778/9 */
589ebdef 612static struct sh_eth_cpu_data r8a777x_data = {
a3f109bd 613 .set_duplex = sh_eth_set_duplex,
589ebdef 614 .set_rate = sh_eth_set_rate_r8a777x,
a3f109bd 615
a3153d8c
SS		 616 .register_type = SH_ETH_REG_FAST_RCAR,
617
a3f109bd
SS		 618 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
619 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
2b2d3eb4
SS		 620 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP |
621 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
622 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
623 EESIPR_RMAFIP | EESIPR_RRFIP |
624 EESIPR_RTLFIP | EESIPR_RTSFIP |
625 EESIPR_PREIP | EESIPR_CERFIP,
a3f109bd
SS		 626
627 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
ca8c3585 628 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
9b39f05c 629 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
d407bc02 630 .fdr_value = 0x00000f0f,
a3f109bd
SS		 631
632 .apr = 1,
633 .mpr = 1,
634 .tpauser = 1,
635 .hw_swap = 1,
636};
a3f109bd 637
94a12b15
SS		 638/* R8A7790/1 */
639static struct sh_eth_cpu_data r8a779x_data = {
e18dbf7e
SH		 640 .set_duplex = sh_eth_set_duplex,
641 .set_rate = sh_eth_set_rate_r8a777x,
642
a3153d8c
SS		 643 .register_type = SH_ETH_REG_FAST_RCAR,
644
e410d86d
NS		 645 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD | ECSR_MPD,
646 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP |
647 ECSIPR_MPDIP,
2b2d3eb4
SS		 648 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP |
649 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
650 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
651 EESIPR_RMAFIP | EESIPR_RRFIP |
652 EESIPR_RTLFIP | EESIPR_RTSFIP |
653 EESIPR_PREIP | EESIPR_CERFIP,
e18dbf7e
SH		 654
655 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
ba361cb3 656 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
9b39f05c 657 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
d407bc02 658 .fdr_value = 0x00000f0f,
e18dbf7e 659
01fbd3f5
GU		 660 .trscer_err_mask = DESC_I_RINT8,
661
e18dbf7e
SH		 662 .apr = 1,
663 .mpr = 1,
664 .tpauser = 1,
665 .hw_swap = 1,
666 .rmiimode = 1,
e410d86d 667 .magic = 1,
e18dbf7e 668};
c74a2248 669#endif /* CONFIG_OF */
e18dbf7e 670
9c3beaab 671static void sh_eth_set_rate_sh7724(struct net_device *ndev)
a3f109bd
SS		 672{
673 struct sh_eth_private *mdp = netdev_priv(ndev);
65ac8851
YS		 674
675 switch (mdp->speed) {
676 case 10: /* 10BASE */
b2b14d2f 677 sh_eth_modify(ndev, ECMR, ECMR_RTM, 0);
65ac8851
YS		 678 break;
679 case 100:/* 100BASE */
b2b14d2f 680 sh_eth_modify(ndev, ECMR, ECMR_RTM, ECMR_RTM);
65ac8851 681 break;
65ac8851
YS		 682 }
683}
684
685/* SH7724 */
9c3beaab 686static struct sh_eth_cpu_data sh7724_data = {
65ac8851 687 .set_duplex = sh_eth_set_duplex,
9c3beaab 688 .set_rate = sh_eth_set_rate_sh7724,
65ac8851 689
a3153d8c
SS		 690 .register_type = SH_ETH_REG_FAST_SH4,
691
65ac8851
YS		 692 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
693 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
2b2d3eb4
SS		 694 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP |
695 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
696 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
697 EESIPR_RMAFIP | EESIPR_RRFIP |
698 EESIPR_RTLFIP | EESIPR_RTSFIP |
699 EESIPR_PREIP | EESIPR_CERFIP,
65ac8851
YS		 700
701 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
ca8c3585 702 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
9b39f05c 703 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
65ac8851
YS		 704
705 .apr = 1,
706 .mpr = 1,
707 .tpauser = 1,
708 .hw_swap = 1,
503914cf
MD		 709 .rpadir = 1,
710 .rpadir_value = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
65ac8851 711};
5cee1d37 712
24549e2a 713static void sh_eth_set_rate_sh7757(struct net_device *ndev)
f29a3d04
YS		 714{
715 struct sh_eth_private *mdp = netdev_priv(ndev);
f29a3d04
YS		 716
717 switch (mdp->speed) {
718 case 10: /* 10BASE */
4a55530f 719 sh_eth_write(ndev, 0, RTRATE);
f29a3d04
YS		 720 break;
721 case 100:/* 100BASE */
4a55530f 722 sh_eth_write(ndev, 1, RTRATE);
f29a3d04 723 break;
f29a3d04
YS		 724 }
725}
726
727/* SH7757 */
24549e2a
SS		 728static struct sh_eth_cpu_data sh7757_data = {
729 .set_duplex = sh_eth_set_duplex,
730 .set_rate = sh_eth_set_rate_sh7757,
f29a3d04 731
a3153d8c
SS		 732 .register_type = SH_ETH_REG_FAST_SH4,
733
2b2d3eb4
SS		 734 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
735 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
736 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
737 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
738 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
739 EESIPR_CEEFIP | EESIPR_CELFIP |
740 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
741 EESIPR_PREIP | EESIPR_CERFIP,
f29a3d04
YS		 742
743 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
ca8c3585 744 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
9b39f05c 745 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
f29a3d04 746
5b3dfd13 747 .irq_flags = IRQF_SHARED,
f29a3d04
YS		 748 .apr = 1,
749 .mpr = 1,
750 .tpauser = 1,
751 .hw_swap = 1,
752 .no_ade = 1,
2e98e797
YS		 753 .rpadir = 1,
754 .rpadir_value = 2 << 16,
6b4b4fea 755 .rtrate = 1,
f29a3d04 756};
65ac8851 757
e403d295 758#define SH_GIGA_ETH_BASE 0xfee00000UL
8fcd4961
YS		 759#define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
760#define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
761static void sh_eth_chip_reset_giga(struct net_device *ndev)
762{
0799c2d6 763 u32 mahr[2], malr[2];
79270922 764 int i;
8fcd4961
YS		 765
766 /* save MAHR and MALR */
767 for (i = 0; i < 2; i++) {
ae70644d
YS		 768 malr[i] = ioread32((void *)GIGA_MALR(i));
769 mahr[i] = ioread32((void *)GIGA_MAHR(i));
8fcd4961
YS		 770 }
771
c66b2581 772 sh_eth_chip_reset(ndev);
8fcd4961
YS		 773
774 /* restore MAHR and MALR */
775 for (i = 0; i < 2; i++) {
ae70644d
YS		 776 iowrite32(malr[i], (void *)GIGA_MALR(i));
777 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
8fcd4961
YS		 778 }
779}
780
8fcd4961
YS		 781static void sh_eth_set_rate_giga(struct net_device *ndev)
782{
783 struct sh_eth_private *mdp = netdev_priv(ndev);
784
785 switch (mdp->speed) {
786 case 10: /* 10BASE */
787 sh_eth_write(ndev, 0x00000000, GECMR);
788 break;
789 case 100:/* 100BASE */
790 sh_eth_write(ndev, 0x00000010, GECMR);
791 break;
792 case 1000: /* 1000BASE */
793 sh_eth_write(ndev, 0x00000020, GECMR);
794 break;
8fcd4961
YS		 795 }
796}
797
798/* SH7757(GETHERC) */
24549e2a 799static struct sh_eth_cpu_data sh7757_data_giga = {
8fcd4961 800 .chip_reset = sh_eth_chip_reset_giga,
04b0ed2a 801 .set_duplex = sh_eth_set_duplex,
8fcd4961
YS		 802 .set_rate = sh_eth_set_rate_giga,
803
a3153d8c
SS		 804 .register_type = SH_ETH_REG_GIGABIT,
805
8fcd4961
YS		 806 .ecsr_value = ECSR_ICD | ECSR_MPD,
807 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
2b2d3eb4
SS		 808 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
809 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
810 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
811 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
812 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
813 EESIPR_CEEFIP | EESIPR_CELFIP |
814 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
815 EESIPR_PREIP | EESIPR_CERFIP,
8fcd4961
YS		 816
817 .tx_check = EESR_TC1 | EESR_FTC,
ca8c3585
SS		 818 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
819 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
9b39f05c 820 EESR_TDE,
8fcd4961 821 .fdr_value = 0x0000072f,
8fcd4961 822
5b3dfd13 823 .irq_flags = IRQF_SHARED,
8fcd4961
YS		 824 .apr = 1,
825 .mpr = 1,
826 .tpauser = 1,
827 .bculr = 1,
828 .hw_swap = 1,
829 .rpadir = 1,
830 .rpadir_value = 2 << 16,
831 .no_trimd = 1,
832 .no_ade = 1,
3acbc971 833 .tsu = 1,
8fcd4961
YS		 834};
835
f5d12767
SS		 836/* SH7734 */
837static struct sh_eth_cpu_data sh7734_data = {
380af9e3
YS		 838 .chip_reset = sh_eth_chip_reset,
839 .set_duplex = sh_eth_set_duplex,
f5d12767
SS		 840 .set_rate = sh_eth_set_rate_gether,
841
a3153d8c
SS		 842 .register_type = SH_ETH_REG_GIGABIT,
843
f5d12767
SS		 844 .ecsr_value = ECSR_ICD | ECSR_MPD,
845 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
2b2d3eb4
SS		 846 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
847 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
848 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
849 EESIPR_DLCIP | EESIPR_CDIP | EESIPR_TROIP |
850 EESIPR_RMAFIP | EESIPR_CEEFIP | EESIPR_CELFIP |
851 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
852 EESIPR_PREIP | EESIPR_CERFIP,
f5d12767
SS		 853
854 .tx_check = EESR_TC1 | EESR_FTC,
ca8c3585
SS		 855 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
856 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
9b39f05c 857 EESR_TDE,
f5d12767
SS		 858
859 .apr = 1,
860 .mpr = 1,
861 .tpauser = 1,
862 .bculr = 1,
863 .hw_swap = 1,
864 .no_trimd = 1,
865 .no_ade = 1,
866 .tsu = 1,
62e04b7e 867 .hw_checksum = 1,
f5d12767 868 .select_mii = 1,
159c2a90 869 .magic = 1,
f5d12767
SS		 870};
871
872/* SH7763 */
873static struct sh_eth_cpu_data sh7763_data = {
874 .chip_reset = sh_eth_chip_reset,
875 .set_duplex = sh_eth_set_duplex,
876 .set_rate = sh_eth_set_rate_gether,
380af9e3 877
a3153d8c
SS		 878 .register_type = SH_ETH_REG_GIGABIT,
879
380af9e3
YS		 880 .ecsr_value = ECSR_ICD | ECSR_MPD,
881 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
2b2d3eb4
SS		 882 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
883 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
884 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
885 EESIPR_DLCIP | EESIPR_CDIP | EESIPR_TROIP |
886 EESIPR_RMAFIP | EESIPR_CEEFIP | EESIPR_CELFIP |
887 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
888 EESIPR_PREIP | EESIPR_CERFIP,
380af9e3
YS		 889
890 .tx_check = EESR_TC1 | EESR_FTC,
128296fc 891 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
9b39f05c 892 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
380af9e3
YS		 893
894 .apr = 1,
895 .mpr = 1,
896 .tpauser = 1,
897 .bculr = 1,
898 .hw_swap = 1,
380af9e3
YS		 899 .no_trimd = 1,
900 .no_ade = 1,
4986b996 901 .tsu = 1,
5b3dfd13 902 .irq_flags = IRQF_SHARED,
267e1d5c 903 .magic = 1,
380af9e3
YS		 904};
905
c18a79ab 906static struct sh_eth_cpu_data sh7619_data = {
a3153d8c
SS		 907 .register_type = SH_ETH_REG_FAST_SH3_SH2,
908
2b2d3eb4
SS		 909 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
910 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
911 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
912 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
913 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
914 EESIPR_CEEFIP | EESIPR_CELFIP |
915 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
916 EESIPR_PREIP | EESIPR_CERFIP,
380af9e3
YS		 917
918 .apr = 1,
919 .mpr = 1,
920 .tpauser = 1,
921 .hw_swap = 1,
922};
7bbe150d
SS		 923
924static struct sh_eth_cpu_data sh771x_data = {
a3153d8c
SS		 925 .register_type = SH_ETH_REG_FAST_SH3_SH2,
926
2b2d3eb4
SS		 927 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
928 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
929 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
930 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
931 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
932 EESIPR_CEEFIP | EESIPR_CELFIP |
933 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
934 EESIPR_PREIP | EESIPR_CERFIP,
4986b996 935 .tsu = 1,
380af9e3 936};
380af9e3
YS		 937
938static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
939{
940 if (!cd->ecsr_value)
941 cd->ecsr_value = DEFAULT_ECSR_INIT;
942
943 if (!cd->ecsipr_value)
944 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
945
946 if (!cd->fcftr_value)
128296fc 947 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF |
380af9e3
YS		 948 DEFAULT_FIFO_F_D_RFD;
949
950 if (!cd->fdr_value)
951 cd->fdr_value = DEFAULT_FDR_INIT;
952
380af9e3
YS		 953 if (!cd->tx_check)
954 cd->tx_check = DEFAULT_TX_CHECK;
955
956 if (!cd->eesr_err_check)
957 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
b284fbe3
NI		 958
959 if (!cd->trscer_err_mask)
960 cd->trscer_err_mask = DEFAULT_TRSCER_ERR_MASK;
380af9e3
YS		 961}
962
5cee1d37
NI		 963static int sh_eth_check_reset(struct net_device *ndev)
964{
965 int ret = 0;
966 int cnt = 100;
967
968 while (cnt > 0) {
97717edc 969 if (!(sh_eth_read(ndev, EDMR) & EDMR_SRST_GETHER))
5cee1d37
NI		 970 break;
971 mdelay(1);
972 cnt--;
973 }
9f8c4265 974 if (cnt <= 0) {
f75f14ec 975 netdev_err(ndev, "Device reset failed\n");
5cee1d37
NI		 976 ret = -ETIMEDOUT;
977 }
978 return ret;
380af9e3 979}
dabdde9e
NI		 980
981static int sh_eth_reset(struct net_device *ndev)
982{
983 struct sh_eth_private *mdp = netdev_priv(ndev);
984 int ret = 0;
985
db893473 986 if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp)) {
dabdde9e 987 sh_eth_write(ndev, EDSR_ENALL, EDSR);
b2b14d2f 988 sh_eth_modify(ndev, EDMR, EDMR_SRST_GETHER, EDMR_SRST_GETHER);
dabdde9e
NI		 989
990 ret = sh_eth_check_reset(ndev);
991 if (ret)
f738a13d 992 return ret;
dabdde9e
NI		 993
994 /* Table Init */
995 sh_eth_write(ndev, 0x0, TDLAR);
996 sh_eth_write(ndev, 0x0, TDFAR);
997 sh_eth_write(ndev, 0x0, TDFXR);
998 sh_eth_write(ndev, 0x0, TDFFR);
999 sh_eth_write(ndev, 0x0, RDLAR);
1000 sh_eth_write(ndev, 0x0, RDFAR);
1001 sh_eth_write(ndev, 0x0, RDFXR);
1002 sh_eth_write(ndev, 0x0, RDFFR);
1003
1004 /* Reset HW CRC register */
62e04b7e 1005 if (mdp->cd->hw_checksum)
dabdde9e
NI		 1006 sh_eth_write(ndev, 0x0, CSMR);
1007
1008 /* Select MII mode */
1009 if (mdp->cd->select_mii)
1010 sh_eth_select_mii(ndev);
1011 } else {
b2b14d2f 1012 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, EDMR_SRST_ETHER);
dabdde9e 1013 mdelay(3);
b2b14d2f 1014 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, 0);
dabdde9e
NI		 1015 }
1016
dabdde9e
NI		 1017 return ret;
1018}
380af9e3 1019
380af9e3
YS		 1020static void sh_eth_set_receive_align(struct sk_buff *skb)
1021{
4d6a949c 1022 uintptr_t reserve = (uintptr_t)skb->data & (SH_ETH_RX_ALIGN - 1);
380af9e3 1023
380af9e3 1024 if (reserve)
4d6a949c 1025 skb_reserve(skb, SH_ETH_RX_ALIGN - reserve);
380af9e3 1026}
380af9e3 1027
128296fc 1028/* Program the hardware MAC address from dev->dev_addr. */
86a74ff2
NI		 1029static void update_mac_address(struct net_device *ndev)
1030{
4a55530f 1031 sh_eth_write(ndev,
128296fc
SS		 1032 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
1033 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
4a55530f 1034 sh_eth_write(ndev,
128296fc 1035 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
86a74ff2
NI		 1036}
1037
128296fc 1038/* Get MAC address from SuperH MAC address register
86a74ff2
NI		 1039 *
1040 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
1041 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
1042 * When you want use this device, you must set MAC address in bootloader.
1043 *
1044 */
748031f9 1045static void read_mac_address(struct net_device *ndev, unsigned char *mac)
86a74ff2 1046{
748031f9 1047 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
d458cdf7 1048 memcpy(ndev->dev_addr, mac, ETH_ALEN);
748031f9 1049 } else {
37742f02
SS		 1050 u32 mahr = sh_eth_read(ndev, MAHR);
1051 u32 malr = sh_eth_read(ndev, MALR);
1052
1053 ndev->dev_addr[0] = (mahr >> 24) & 0xFF;
1054 ndev->dev_addr[1] = (mahr >> 16) & 0xFF;
1055 ndev->dev_addr[2] = (mahr >> 8) & 0xFF;
1056 ndev->dev_addr[3] = (mahr >> 0) & 0xFF;
1057 ndev->dev_addr[4] = (malr >> 8) & 0xFF;
1058 ndev->dev_addr[5] = (malr >> 0) & 0xFF;
748031f9 1059 }
86a74ff2
NI		 1060}
1061
0799c2d6 1062static u32 sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
c5ed5368 1063{
db893473 1064 if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp))
c5ed5368
YS		 1065 return EDTRR_TRNS_GETHER;
1066 else
1067 return EDTRR_TRNS_ETHER;
1068}
1069
86a74ff2 1070struct bb_info {
ae70644d 1071 void (*set_gate)(void *addr);
86a74ff2 1072 struct mdiobb_ctrl ctrl;
ae70644d 1073 void *addr;
86a74ff2
NI		 1074};
1075
39b4b06b 1076static void sh_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set)
86a74ff2
NI		 1077{
1078 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
78fa3c5c 1079 u32 pir;
b3017e6a
YS		 1080
1081 if (bitbang->set_gate)
1082 bitbang->set_gate(bitbang->addr);
1083
78fa3c5c 1084 pir = ioread32(bitbang->addr);
39b4b06b 1085 if (set)
78fa3c5c 1086 pir |= mask;
86a74ff2 1087 else
78fa3c5c
SS		 1088 pir &= ~mask;
1089 iowrite32(pir, bitbang->addr);
39b4b06b
SS		 1090}
1091
1092/* Data I/O pin control */
1093static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1094{
1095 sh_mdio_ctrl(ctrl, PIR_MMD, bit);
86a74ff2
NI		 1096}
1097
1098/* Set bit data*/
1099static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
1100{
39b4b06b 1101 sh_mdio_ctrl(ctrl, PIR_MDO, bit);
86a74ff2
NI		 1102}
1103
1104/* Get bit data*/
1105static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
1106{
1107 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
b3017e6a
YS		 1108
1109 if (bitbang->set_gate)
1110 bitbang->set_gate(bitbang->addr);
1111
78fa3c5c 1112 return (ioread32(bitbang->addr) & PIR_MDI) != 0;
86a74ff2
NI		 1113}
1114
1115/* MDC pin control */
1116static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1117{
39b4b06b 1118 sh_mdio_ctrl(ctrl, PIR_MDC, bit);
86a74ff2
NI		 1119}
1120
1121/* mdio bus control struct */
1122static struct mdiobb_ops bb_ops = {
1123 .owner = THIS_MODULE,
1124 .set_mdc = sh_mdc_ctrl,
1125 .set_mdio_dir = sh_mmd_ctrl,
1126 .set_mdio_data = sh_set_mdio,
1127 .get_mdio_data = sh_get_mdio,
1128};
1129
1debdc8f
SS		 1130/* free Tx skb function */
1131static int sh_eth_tx_free(struct net_device *ndev, bool sent_only)
1132{
1133 struct sh_eth_private *mdp = netdev_priv(ndev);
1134 struct sh_eth_txdesc *txdesc;
1135 int free_num = 0;
1136 int entry;
1137 bool sent;
1138
1139 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
1140 entry = mdp->dirty_tx % mdp->num_tx_ring;
1141 txdesc = &mdp->tx_ring[entry];
1142 sent = !(txdesc->status & cpu_to_le32(TD_TACT));
1143 if (sent_only && !sent)
1144 break;
1145 /* TACT bit must be checked before all the following reads */
1146 dma_rmb();
1147 netif_info(mdp, tx_done, ndev,
1148 "tx entry %d status 0x%08x\n",
1149 entry, le32_to_cpu(txdesc->status));
1150 /* Free the original skb. */
1151 if (mdp->tx_skbuff[entry]) {
1152 dma_unmap_single(&ndev->dev, le32_to_cpu(txdesc->addr),
1153 le32_to_cpu(txdesc->len) >> 16,
1154 DMA_TO_DEVICE);
1155 dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1156 mdp->tx_skbuff[entry] = NULL;
1157 free_num++;
1158 }
1159 txdesc->status = cpu_to_le32(TD_TFP);
1160 if (entry >= mdp->num_tx_ring - 1)
1161 txdesc->status |= cpu_to_le32(TD_TDLE);
1162
1163 if (sent) {
1164 ndev->stats.tx_packets++;
1165 ndev->stats.tx_bytes += le32_to_cpu(txdesc->len) >> 16;
1166 }
1167 }
1168 return free_num;
1169}
1170
86a74ff2
NI		 1171/* free skb and descriptor buffer */
1172static void sh_eth_ring_free(struct net_device *ndev)
1173{
1174 struct sh_eth_private *mdp = netdev_priv(ndev);
8e03a5e7 1175 int ringsize, i;
86a74ff2 1176
1debdc8f
SS		 1177 if (mdp->rx_ring) {
1178 for (i = 0; i < mdp->num_rx_ring; i++) {
1179 if (mdp->rx_skbuff[i]) {
1180 struct sh_eth_rxdesc *rxdesc = &mdp->rx_ring[i];
1181
1182 dma_unmap_single(&ndev->dev,
1183 le32_to_cpu(rxdesc->addr),
1184 ALIGN(mdp->rx_buf_sz, 32),
1185 DMA_FROM_DEVICE);
1186 }
1187 }
1188 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1189 dma_free_coherent(NULL, ringsize, mdp->rx_ring,
1190 mdp->rx_desc_dma);
1191 mdp->rx_ring = NULL;
1192 }
1193
86a74ff2
NI		 1194 /* Free Rx skb ringbuffer */
1195 if (mdp->rx_skbuff) {
179d80af
SS		 1196 for (i = 0; i < mdp->num_rx_ring; i++)
1197 dev_kfree_skb(mdp->rx_skbuff[i]);
86a74ff2
NI		 1198 }
1199 kfree(mdp->rx_skbuff);
91c77550 1200 mdp->rx_skbuff = NULL;
86a74ff2 1201
8e03a5e7 1202 if (mdp->tx_ring) {
1debdc8f
SS		 1203 sh_eth_tx_free(ndev, false);
1204
8e03a5e7
SS		 1205 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1206 dma_free_coherent(NULL, ringsize, mdp->tx_ring,
1207 mdp->tx_desc_dma);
1208 mdp->tx_ring = NULL;
1209 }
1debdc8f
SS		 1210
1211 /* Free Tx skb ringbuffer */
1212 kfree(mdp->tx_skbuff);
1213 mdp->tx_skbuff = NULL;
86a74ff2
NI		 1214}
1215
1216/* format skb and descriptor buffer */
1217static void sh_eth_ring_format(struct net_device *ndev)
1218{
1219 struct sh_eth_private *mdp = netdev_priv(ndev);
1220 int i;
1221 struct sk_buff *skb;
1222 struct sh_eth_rxdesc *rxdesc = NULL;
1223 struct sh_eth_txdesc *txdesc = NULL;
525b8075
YS		 1224 int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
1225 int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
cb368595 1226 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
52b9fa36 1227 dma_addr_t dma_addr;
5cbf20c7 1228 u32 buf_len;
86a74ff2 1229
128296fc
SS		 1230 mdp->cur_rx = 0;
1231 mdp->cur_tx = 0;
1232 mdp->dirty_rx = 0;
1233 mdp->dirty_tx = 0;
86a74ff2
NI		 1234
1235 memset(mdp->rx_ring, 0, rx_ringsize);
1236
1237 /* build Rx ring buffer */
525b8075 1238 for (i = 0; i < mdp->num_rx_ring; i++) {
86a74ff2
NI		 1239 /* skb */
1240 mdp->rx_skbuff[i] = NULL;
4d6a949c 1241 skb = netdev_alloc_skb(ndev, skbuff_size);
86a74ff2
NI		 1242 if (skb == NULL)
1243 break;
380af9e3
YS		 1244 sh_eth_set_receive_align(skb);
1245
ab857916 1246 /* The size of the buffer is a multiple of 32 bytes. */
5cbf20c7 1247 buf_len = ALIGN(mdp->rx_buf_sz, 32);
5cbf20c7 1248 dma_addr = dma_map_single(&ndev->dev, skb->data, buf_len,
52b9fa36
BH		 1249 DMA_FROM_DEVICE);
1250 if (dma_mapping_error(&ndev->dev, dma_addr)) {
1251 kfree_skb(skb);
1252 break;
1253 }
1254 mdp->rx_skbuff[i] = skb;
d0ba9134
SS		 1255
1256 /* RX descriptor */
1257 rxdesc = &mdp->rx_ring[i];
1258 rxdesc->len = cpu_to_le32(buf_len << 16);
7cf72477
SS		 1259 rxdesc->addr = cpu_to_le32(dma_addr);
1260 rxdesc->status = cpu_to_le32(RD_RACT | RD_RFP);
86a74ff2 1261
b0ca2a21
NI		 1262 /* Rx descriptor address set */
1263 if (i == 0) {
4a55530f 1264 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
db893473
SH		 1265 if (sh_eth_is_gether(mdp) ||
1266 sh_eth_is_rz_fast_ether(mdp))
c5ed5368 1267 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
b0ca2a21 1268 }
86a74ff2
NI		 1269 }
1270
525b8075 1271 mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
86a74ff2
NI		 1272
1273 /* Mark the last entry as wrapping the ring. */
c1b7fca6
SS		 1274 if (rxdesc)
1275 rxdesc->status |= cpu_to_le32(RD_RDLE);
86a74ff2
NI		 1276
1277 memset(mdp->tx_ring, 0, tx_ringsize);
1278
1279 /* build Tx ring buffer */
525b8075 1280 for (i = 0; i < mdp->num_tx_ring; i++) {
86a74ff2
NI		 1281 mdp->tx_skbuff[i] = NULL;
1282 txdesc = &mdp->tx_ring[i];
7cf72477
SS		 1283 txdesc->status = cpu_to_le32(TD_TFP);
1284 txdesc->len = cpu_to_le32(0);
b0ca2a21 1285 if (i == 0) {
71557a37 1286 /* Tx descriptor address set */
4a55530f 1287 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
db893473
SH		 1288 if (sh_eth_is_gether(mdp) ||
1289 sh_eth_is_rz_fast_ether(mdp))
c5ed5368 1290 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
b0ca2a21 1291 }
86a74ff2
NI		 1292 }
1293
7cf72477 1294 txdesc->status |= cpu_to_le32(TD_TDLE);
86a74ff2
NI		 1295}
1296
1297/* Get skb and descriptor buffer */
1298static int sh_eth_ring_init(struct net_device *ndev)
1299{
1300 struct sh_eth_private *mdp = netdev_priv(ndev);
91d80683 1301 int rx_ringsize, tx_ringsize;
86a74ff2 1302
128296fc 1303 /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
86a74ff2
NI		 1304 * card needs room to do 8 byte alignment, +2 so we can reserve
1305 * the first 2 bytes, and +16 gets room for the status word from the
1306 * card.
1307 */
1308 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
1309 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
503914cf
MD		 1310 if (mdp->cd->rpadir)
1311 mdp->rx_buf_sz += NET_IP_ALIGN;
86a74ff2
NI		 1312
1313 /* Allocate RX and TX skb rings */
2c94e856
SS		 1314 mdp->rx_skbuff = kcalloc(mdp->num_rx_ring, sizeof(*mdp->rx_skbuff),
1315 GFP_KERNEL);
91d80683
SS		 1316 if (!mdp->rx_skbuff)
1317 return -ENOMEM;
86a74ff2 1318
2c94e856
SS		 1319 mdp->tx_skbuff = kcalloc(mdp->num_tx_ring, sizeof(*mdp->tx_skbuff),
1320 GFP_KERNEL);
91d80683 1321 if (!mdp->tx_skbuff)
8e03a5e7 1322 goto ring_free;
86a74ff2
NI		 1323
1324 /* Allocate all Rx descriptors. */
525b8075 1325 rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
86a74ff2 1326 mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
d0320f75 1327 GFP_KERNEL);
91d80683 1328 if (!mdp->rx_ring)
8e03a5e7 1329 goto ring_free;
86a74ff2
NI		 1330
1331 mdp->dirty_rx = 0;
1332
1333 /* Allocate all Tx descriptors. */
525b8075 1334 tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
86a74ff2 1335 mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
d0320f75 1336 GFP_KERNEL);
91d80683 1337 if (!mdp->tx_ring)
8e03a5e7 1338 goto ring_free;
91d80683 1339 return 0;
86a74ff2 1340
8e03a5e7
SS		 1341ring_free:
1342 /* Free Rx and Tx skb ring buffer and DMA buffer */
86a74ff2
NI		 1343 sh_eth_ring_free(ndev);
1344
91d80683 1345 return -ENOMEM;
86a74ff2
NI		 1346}
1347
f7967210 1348static int sh_eth_dev_init(struct net_device *ndev)
86a74ff2 1349{
86a74ff2 1350 struct sh_eth_private *mdp = netdev_priv(ndev);
4fa8c3cc 1351 int ret;
86a74ff2
NI		 1352
1353 /* Soft Reset */
5cee1d37
NI		 1354 ret = sh_eth_reset(ndev);
1355 if (ret)
f738a13d 1356 return ret;
86a74ff2 1357
55754f19
SH		 1358 if (mdp->cd->rmiimode)
1359 sh_eth_write(ndev, 0x1, RMIIMODE);
1360
b0ca2a21
NI		 1361 /* Descriptor format */
1362 sh_eth_ring_format(ndev);
380af9e3 1363 if (mdp->cd->rpadir)
4a55530f 1364 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
86a74ff2
NI		 1365
1366 /* all sh_eth int mask */
4a55530f 1367 sh_eth_write(ndev, 0, EESIPR);
86a74ff2 1368
10b9194f 1369#if defined(__LITTLE_ENDIAN)
380af9e3 1370 if (mdp->cd->hw_swap)
4a55530f 1371 sh_eth_write(ndev, EDMR_EL, EDMR);
380af9e3 1372 else
b0ca2a21 1373#endif
4a55530f 1374 sh_eth_write(ndev, 0, EDMR);
86a74ff2 1375
b0ca2a21 1376 /* FIFO size set */
4a55530f
YS		 1377 sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
1378 sh_eth_write(ndev, 0, TFTR);
86a74ff2 1379
530aa2d0
BD		 1380 /* Frame recv control (enable multiple-packets per rx irq) */
1381 sh_eth_write(ndev, RMCR_RNC, RMCR);
86a74ff2 1382
b284fbe3 1383 sh_eth_write(ndev, mdp->cd->trscer_err_mask, TRSCER);
86a74ff2 1384
380af9e3 1385 if (mdp->cd->bculr)
4a55530f 1386 sh_eth_write(ndev, 0x800, BCULR); /* Burst sycle set */
b0ca2a21 1387
4a55530f 1388 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
86a74ff2 1389
380af9e3 1390 if (!mdp->cd->no_trimd)
4a55530f 1391 sh_eth_write(ndev, 0, TRIMD);
86a74ff2 1392
b0ca2a21 1393 /* Recv frame limit set register */
fdb37a7f
YS		 1394 sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1395 RFLR);
86a74ff2 1396
b2b14d2f 1397 sh_eth_modify(ndev, EESR, 0, 0);
f7967210
SS		 1398 mdp->irq_enabled = true;
1399 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
86a74ff2
NI		 1400
1401 /* PAUSE Prohibition */
bffa731f
SS		 1402 sh_eth_write(ndev, ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) |
1403 ECMR_TE | ECMR_RE, ECMR);
b0ca2a21 1404
380af9e3
YS		 1405 if (mdp->cd->set_rate)
1406 mdp->cd->set_rate(ndev);
1407
b0ca2a21 1408 /* E-MAC Status Register clear */
4a55530f 1409 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
b0ca2a21
NI		 1410
1411 /* E-MAC Interrupt Enable register */
f7967210 1412 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
86a74ff2
NI		 1413
1414 /* Set MAC address */
1415 update_mac_address(ndev);
1416
1417 /* mask reset */
380af9e3 1418 if (mdp->cd->apr)
4a55530f 1419 sh_eth_write(ndev, APR_AP, APR);
380af9e3 1420 if (mdp->cd->mpr)
4a55530f 1421 sh_eth_write(ndev, MPR_MP, MPR);
380af9e3 1422 if (mdp->cd->tpauser)
4a55530f 1423 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
b0ca2a21 1424
f7967210
SS		 1425 /* Setting the Rx mode will start the Rx process. */
1426 sh_eth_write(ndev, EDRRR_R, EDRRR);
86a74ff2
NI		 1427
1428 return ret;
1429}
1430
740c7f31
BH		 1431static void sh_eth_dev_exit(struct net_device *ndev)
1432{
1433 struct sh_eth_private *mdp = netdev_priv(ndev);
1434 int i;
1435
1436 /* Deactivate all TX descriptors, so DMA should stop at next
1437 * packet boundary if it's currently running
1438 */
1439 for (i = 0; i < mdp->num_tx_ring; i++)
7cf72477 1440 mdp->tx_ring[i].status &= ~cpu_to_le32(TD_TACT);
740c7f31
BH		 1441
1442 /* Disable TX FIFO egress to MAC */
1443 sh_eth_rcv_snd_disable(ndev);
1444
1445 /* Stop RX DMA at next packet boundary */
1446 sh_eth_write(ndev, 0, EDRRR);
1447
1448 /* Aside from TX DMA, we can't tell when the hardware is
1449 * really stopped, so we need to reset to make sure.
1450 * Before doing that, wait for long enough to *probably*
1451 * finish transmitting the last packet and poll stats.
1452 */
1453 msleep(2); /* max frame time at 10 Mbps < 1250 us */
1454 sh_eth_get_stats(ndev);
1455 sh_eth_reset(ndev);
a14c7d15
GU		 1456
1457 /* Set MAC address again */
1458 update_mac_address(ndev);
740c7f31
BH		 1459}
1460
86a74ff2 1461/* Packet receive function */
3719109d 1462static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
86a74ff2
NI		 1463{
1464 struct sh_eth_private *mdp = netdev_priv(ndev);
1465 struct sh_eth_rxdesc *rxdesc;
1466
525b8075
YS		 1467 int entry = mdp->cur_rx % mdp->num_rx_ring;
1468 int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
319cd520 1469 int limit;
86a74ff2 1470 struct sk_buff *skb;
380af9e3 1471 u32 desc_status;
cb368595 1472 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
52b9fa36 1473 dma_addr_t dma_addr;
4fa8c3cc 1474 u16 pkt_len;
5cbf20c7 1475 u32 buf_len;
86a74ff2 1476
319cd520
MK		 1477 boguscnt = min(boguscnt, *quota);
1478 limit = boguscnt;
86a74ff2 1479 rxdesc = &mdp->rx_ring[entry];
7cf72477 1480 while (!(rxdesc->status & cpu_to_le32(RD_RACT))) {
7d7355f5 1481 /* RACT bit must be checked before all the following reads */
f32bfb9a 1482 dma_rmb();
7cf72477
SS		 1483 desc_status = le32_to_cpu(rxdesc->status);
1484 pkt_len = le32_to_cpu(rxdesc->len) & RD_RFL;
86a74ff2
NI		 1485
1486 if (--boguscnt < 0)
1487 break;
1488
e5fd13f4
BH		 1489 netif_info(mdp, rx_status, ndev,
1490 "rx entry %d status 0x%08x len %d\n",
1491 entry, desc_status, pkt_len);
1492
86a74ff2 1493 if (!(desc_status & RDFEND))
bb7d92e3 1494 ndev->stats.rx_length_errors++;
86a74ff2 1495
128296fc 1496 /* In case of almost all GETHER/ETHERs, the Receive Frame State
dd019897 1497 * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
9b4a6364
BH		 1498 * bit 0. However, in case of the R8A7740 and R7S72100
1499 * the RFS bits are from bit 25 to bit 16. So, the
db893473 1500 * driver needs right shifting by 16.
dd019897 1501 */
62e04b7e 1502 if (mdp->cd->hw_checksum)
ac8025a6 1503 desc_status >>= 16;
dd019897 1504
248be83d 1505 skb = mdp->rx_skbuff[entry];
86a74ff2
NI		 1506 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1507 RD_RFS5 | RD_RFS6 | RD_RFS10)) {
bb7d92e3 1508 ndev->stats.rx_errors++;
86a74ff2 1509 if (desc_status & RD_RFS1)
bb7d92e3 1510 ndev->stats.rx_crc_errors++;
86a74ff2 1511 if (desc_status & RD_RFS2)
bb7d92e3 1512 ndev->stats.rx_frame_errors++;
86a74ff2 1513 if (desc_status & RD_RFS3)
bb7d92e3 1514 ndev->stats.rx_length_errors++;
86a74ff2 1515 if (desc_status & RD_RFS4)
bb7d92e3 1516 ndev->stats.rx_length_errors++;
86a74ff2 1517 if (desc_status & RD_RFS6)
bb7d92e3 1518 ndev->stats.rx_missed_errors++;
86a74ff2 1519 if (desc_status & RD_RFS10)
bb7d92e3 1520 ndev->stats.rx_over_errors++;
248be83d 1521 } else if (skb) {
7cf72477 1522 dma_addr = le32_to_cpu(rxdesc->addr);
380af9e3
YS		 1523 if (!mdp->cd->hw_swap)
1524 sh_eth_soft_swap(
1299653a 1525 phys_to_virt(ALIGN(dma_addr, 4)),
380af9e3 1526 pkt_len + 2);
86a74ff2 1527 mdp->rx_skbuff[entry] = NULL;
503914cf
MD		 1528 if (mdp->cd->rpadir)
1529 skb_reserve(skb, NET_IP_ALIGN);
1299653a 1530 dma_unmap_single(&ndev->dev, dma_addr,
ab857916 1531 ALIGN(mdp->rx_buf_sz, 32),
52b9fa36 1532 DMA_FROM_DEVICE);
86a74ff2
NI		 1533 skb_put(skb, pkt_len);
1534 skb->protocol = eth_type_trans(skb, ndev);
a8e9fd0f 1535 netif_receive_skb(skb);
bb7d92e3
ED		 1536 ndev->stats.rx_packets++;
1537 ndev->stats.rx_bytes += pkt_len;
25b77ad7
BH		 1538 if (desc_status & RD_RFS8)
1539 ndev->stats.multicast++;
86a74ff2 1540 }
525b8075 1541 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
862df497 1542 rxdesc = &mdp->rx_ring[entry];
86a74ff2
NI		 1543 }
1544
1545 /* Refill the Rx ring buffers. */
1546 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
525b8075 1547 entry = mdp->dirty_rx % mdp->num_rx_ring;
86a74ff2 1548 rxdesc = &mdp->rx_ring[entry];
ab857916 1549 /* The size of the buffer is 32 byte boundary. */
5cbf20c7 1550 buf_len = ALIGN(mdp->rx_buf_sz, 32);
7cf72477 1551 rxdesc->len = cpu_to_le32(buf_len << 16);
b0ca2a21 1552
86a74ff2 1553 if (mdp->rx_skbuff[entry] == NULL) {
4d6a949c 1554 skb = netdev_alloc_skb(ndev, skbuff_size);
86a74ff2
NI		 1555 if (skb == NULL)
1556 break; /* Better luck next round. */
380af9e3 1557 sh_eth_set_receive_align(skb);
52b9fa36 1558 dma_addr = dma_map_single(&ndev->dev, skb->data,
5cbf20c7 1559 buf_len, DMA_FROM_DEVICE);
52b9fa36
BH		 1560 if (dma_mapping_error(&ndev->dev, dma_addr)) {
1561 kfree_skb(skb);
1562 break;
1563 }
1564 mdp->rx_skbuff[entry] = skb;
380af9e3 1565
bc8acf2c 1566 skb_checksum_none_assert(skb);
7cf72477 1567 rxdesc->addr = cpu_to_le32(dma_addr);
86a74ff2 1568 }
f32bfb9a 1569 dma_wmb(); /* RACT bit must be set after all the above writes */
525b8075 1570 if (entry >= mdp->num_rx_ring - 1)
86a74ff2 1571 rxdesc->status |=
7cf72477 1572 cpu_to_le32(RD_RACT | RD_RFP | RD_RDLE);
86a74ff2 1573 else
7cf72477 1574 rxdesc->status |= cpu_to_le32(RD_RACT | RD_RFP);
86a74ff2
NI		 1575 }
1576
1577 /* Restart Rx engine if stopped. */
1578 /* If we don't need to check status, don't. -KDU */
79fba9f5 1579 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
a18e08bd 1580 /* fix the values for the next receiving if RDE is set */
3365711d
BH		 1581 if (intr_status & EESR_RDE &&
1582 mdp->reg_offset[RDFAR] != SH_ETH_OFFSET_INVALID) {
128296fc
SS		 1583 u32 count = (sh_eth_read(ndev, RDFAR) -
1584 sh_eth_read(ndev, RDLAR)) >> 4;
1585
1586 mdp->cur_rx = count;
1587 mdp->dirty_rx = count;
1588 }
4a55530f 1589 sh_eth_write(ndev, EDRRR_R, EDRRR);
79fba9f5 1590 }
86a74ff2 1591
319cd520
MK		 1592 *quota -= limit - boguscnt - 1;
1593
4f809cea 1594 return *quota <= 0;
86a74ff2
NI		 1595}
1596
4a55530f 1597static void sh_eth_rcv_snd_disable(struct net_device *ndev)
dc19e4e5
NI		 1598{
1599 /* disable tx and rx */
b2b14d2f 1600 sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0);
dc19e4e5
NI		 1601}
1602
4a55530f 1603static void sh_eth_rcv_snd_enable(struct net_device *ndev)
dc19e4e5
NI		 1604{
1605 /* enable tx and rx */
b2b14d2f 1606 sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE);
dc19e4e5
NI		 1607}
1608
9b39f05c
SS		 1609/* E-MAC interrupt handler */
1610static void sh_eth_emac_interrupt(struct net_device *ndev)
86a74ff2
NI		 1611{
1612 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2 1613 u32 felic_stat;
380af9e3 1614 u32 link_stat;
86a74ff2 1615
9b39f05c
SS		 1616 felic_stat = sh_eth_read(ndev, ECSR) & sh_eth_read(ndev, ECSIPR);
1617 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */
1618 if (felic_stat & ECSR_ICD)
1619 ndev->stats.tx_carrier_errors++;
0cf45a3b
NS		 1620 if (felic_stat & ECSR_MPD)
1621 pm_wakeup_event(&mdp->pdev->dev, 0);
9b39f05c
SS		 1622 if (felic_stat & ECSR_LCHNG) {
1623 /* Link Changed */
1624 if (mdp->cd->no_psr || mdp->no_ether_link)
1625 return;
1626 link_stat = sh_eth_read(ndev, PSR);
1627 if (mdp->ether_link_active_low)
1628 link_stat = ~link_stat;
1629 if (!(link_stat & PHY_ST_LINK)) {
1630 sh_eth_rcv_snd_disable(ndev);
1631 } else {
1632 /* Link Up */
1a0bee6c 1633 sh_eth_modify(ndev, EESIPR, EESIPR_ECIIP, 0);
9b39f05c
SS		 1634 /* clear int */
1635 sh_eth_modify(ndev, ECSR, 0, 0);
1a0bee6c 1636 sh_eth_modify(ndev, EESIPR, EESIPR_ECIIP, EESIPR_ECIIP);
9b39f05c
SS		 1637 /* enable tx and rx */
1638 sh_eth_rcv_snd_enable(ndev);
86a74ff2
NI		 1639 }
1640 }
9b39f05c
SS		 1641}
1642
1643/* error control function */
1644static void sh_eth_error(struct net_device *ndev, u32 intr_status)
1645{
1646 struct sh_eth_private *mdp = netdev_priv(ndev);
1647 u32 mask;
86a74ff2
NI		 1648
1649 if (intr_status & EESR_TWB) {
4eb313a7
SS		 1650 /* Unused write back interrupt */
1651 if (intr_status & EESR_TABT) { /* Transmit Abort int */
bb7d92e3 1652 ndev->stats.tx_aborted_errors++;
8d5009f6 1653 netif_err(mdp, tx_err, ndev, "Transmit Abort\n");
4eb313a7 1654 }
86a74ff2
NI		 1655 }
1656
1657 if (intr_status & EESR_RABT) {
1658 /* Receive Abort int */
1659 if (intr_status & EESR_RFRMER) {
1660 /* Receive Frame Overflow int */
bb7d92e3 1661 ndev->stats.rx_frame_errors++;
86a74ff2
NI		 1662 }
1663 }
380af9e3 1664
dc19e4e5
NI		 1665 if (intr_status & EESR_TDE) {
1666 /* Transmit Descriptor Empty int */
bb7d92e3 1667 ndev->stats.tx_fifo_errors++;
8d5009f6 1668 netif_err(mdp, tx_err, ndev, "Transmit Descriptor Empty\n");
dc19e4e5
NI		 1669 }
1670
1671 if (intr_status & EESR_TFE) {
1672 /* FIFO under flow */
bb7d92e3 1673 ndev->stats.tx_fifo_errors++;
8d5009f6 1674 netif_err(mdp, tx_err, ndev, "Transmit FIFO Under flow\n");
86a74ff2
NI		 1675 }
1676
1677 if (intr_status & EESR_RDE) {
1678 /* Receive Descriptor Empty int */
bb7d92e3 1679 ndev->stats.rx_over_errors++;
86a74ff2 1680 }
dc19e4e5 1681
86a74ff2
NI		 1682 if (intr_status & EESR_RFE) {
1683 /* Receive FIFO Overflow int */
bb7d92e3 1684 ndev->stats.rx_fifo_errors++;
dc19e4e5
NI		 1685 }
1686
1687 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1688 /* Address Error */
bb7d92e3 1689 ndev->stats.tx_fifo_errors++;
8d5009f6 1690 netif_err(mdp, tx_err, ndev, "Address Error\n");
86a74ff2 1691 }
380af9e3
YS		 1692
1693 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1694 if (mdp->cd->no_ade)
1695 mask &= ~EESR_ADE;
1696 if (intr_status & mask) {
86a74ff2 1697 /* Tx error */
4a55530f 1698 u32 edtrr = sh_eth_read(ndev, EDTRR);
090d560f 1699
86a74ff2 1700 /* dmesg */
da246855
SS		 1701 netdev_err(ndev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1702 intr_status, mdp->cur_tx, mdp->dirty_tx,
1703 (u32)ndev->state, edtrr);
86a74ff2 1704 /* dirty buffer free */
1debdc8f 1705 sh_eth_tx_free(ndev, true);
86a74ff2
NI		 1706
1707 /* SH7712 BUG */
c5ed5368 1708 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
86a74ff2 1709 /* tx dma start */
c5ed5368 1710 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
86a74ff2
NI		 1711 }
1712 /* wakeup */
1713 netif_wake_queue(ndev);
1714 }
1715}
1716
1717static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1718{
1719 struct net_device *ndev = netdev;
1720 struct sh_eth_private *mdp = netdev_priv(ndev);
380af9e3 1721 struct sh_eth_cpu_data *cd = mdp->cd;
0e0fde3c 1722 irqreturn_t ret = IRQ_NONE;
0799c2d6 1723 u32 intr_status, intr_enable;
86a74ff2 1724
86a74ff2
NI		 1725 spin_lock(&mdp->lock);
1726
3893b273 1727 /* Get interrupt status */
4a55530f 1728 intr_status = sh_eth_read(ndev, EESR);
9b39f05c
SS		 1729 /* Mask it with the interrupt mask, forcing ECI interrupt to be always
1730 * enabled since it's the one that comes thru regardless of the mask,
1731 * and we need to fully handle it in sh_eth_emac_interrupt() in order
1732 * to quench it as it doesn't get cleared by just writing 1 to the ECI
1733 * bit...
3893b273 1734 */
3719109d 1735 intr_enable = sh_eth_read(ndev, EESIPR);
1a0bee6c 1736 intr_status &= intr_enable | EESIPR_ECIIP;
9b39f05c
SS		 1737 if (intr_status & (EESR_RX_CHECK | cd->tx_check | EESR_ECI |
1738 cd->eesr_err_check))
0e0fde3c 1739 ret = IRQ_HANDLED;
3719109d 1740 else
283e38db
BH		 1741 goto out;
1742
2344ef3c 1743 if (unlikely(!mdp->irq_enabled)) {
283e38db
BH		 1744 sh_eth_write(ndev, 0, EESIPR);
1745 goto out;
1746 }
86a74ff2 1747
3719109d
SS		 1748 if (intr_status & EESR_RX_CHECK) {
1749 if (napi_schedule_prep(&mdp->napi)) {
1750 /* Mask Rx interrupts */
1751 sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK,
1752 EESIPR);
1753 __napi_schedule(&mdp->napi);
1754 } else {
da246855 1755 netdev_warn(ndev,
0799c2d6 1756 "ignoring interrupt, status 0x%08x, mask 0x%08x.\n",
da246855 1757 intr_status, intr_enable);
3719109d
SS		 1758 }
1759 }
86a74ff2 1760
b0ca2a21 1761 /* Tx Check */
380af9e3 1762 if (intr_status & cd->tx_check) {
3719109d
SS		 1763 /* Clear Tx interrupts */
1764 sh_eth_write(ndev, intr_status & cd->tx_check, EESR);
1765
1debdc8f 1766 sh_eth_tx_free(ndev, true);
86a74ff2
NI		 1767 netif_wake_queue(ndev);
1768 }
1769
9b39f05c
SS		 1770 /* E-MAC interrupt */
1771 if (intr_status & EESR_ECI)
1772 sh_eth_emac_interrupt(ndev);
1773
3719109d
SS		 1774 if (intr_status & cd->eesr_err_check) {
1775 /* Clear error interrupts */
1776 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR);
1777
86a74ff2 1778 sh_eth_error(ndev, intr_status);
3719109d 1779 }
86a74ff2 1780
283e38db 1781out:
86a74ff2
NI		 1782 spin_unlock(&mdp->lock);
1783
0e0fde3c 1784 return ret;
86a74ff2
NI		 1785}
1786
3719109d
SS		 1787static int sh_eth_poll(struct napi_struct *napi, int budget)
1788{
1789 struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private,
1790 napi);
1791 struct net_device *ndev = napi->dev;
1792 int quota = budget;
0799c2d6 1793 u32 intr_status;
3719109d
SS		 1794
1795 for (;;) {
1796 intr_status = sh_eth_read(ndev, EESR);
1797 if (!(intr_status & EESR_RX_CHECK))
1798 break;
1799 /* Clear Rx interrupts */
1800 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR);
1801
1802 if (sh_eth_rx(ndev, intr_status, &quota))
1803 goto out;
1804 }
1805
1806 napi_complete(napi);
1807
1808 /* Reenable Rx interrupts */
283e38db
BH		 1809 if (mdp->irq_enabled)
1810 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
3719109d
SS		 1811out:
1812 return budget - quota;
1813}
1814
86a74ff2
NI		 1815/* PHY state control function */
1816static void sh_eth_adjust_link(struct net_device *ndev)
1817{
1818 struct sh_eth_private *mdp = netdev_priv(ndev);
9fd0375a 1819 struct phy_device *phydev = ndev->phydev;
86a74ff2
NI		 1820 int new_state = 0;
1821
3340d2aa 1822 if (phydev->link) {
86a74ff2
NI		 1823 if (phydev->duplex != mdp->duplex) {
1824 new_state = 1;
1825 mdp->duplex = phydev->duplex;
380af9e3
YS		 1826 if (mdp->cd->set_duplex)
1827 mdp->cd->set_duplex(ndev);
86a74ff2
NI		 1828 }
1829
1830 if (phydev->speed != mdp->speed) {
1831 new_state = 1;
1832 mdp->speed = phydev->speed;
380af9e3
YS		 1833 if (mdp->cd->set_rate)
1834 mdp->cd->set_rate(ndev);
86a74ff2 1835 }
3340d2aa 1836 if (!mdp->link) {
b2b14d2f 1837 sh_eth_modify(ndev, ECMR, ECMR_TXF, 0);
86a74ff2
NI		 1838 new_state = 1;
1839 mdp->link = phydev->link;
1e1b812b
SS		 1840 if (mdp->cd->no_psr || mdp->no_ether_link)
1841 sh_eth_rcv_snd_enable(ndev);
86a74ff2
NI		 1842 }
1843 } else if (mdp->link) {
1844 new_state = 1;
3340d2aa 1845 mdp->link = 0;
86a74ff2
NI		 1846 mdp->speed = 0;
1847 mdp->duplex = -1;
1e1b812b
SS		 1848 if (mdp->cd->no_psr || mdp->no_ether_link)
1849 sh_eth_rcv_snd_disable(ndev);
86a74ff2
NI		 1850 }
1851
dc19e4e5 1852 if (new_state && netif_msg_link(mdp))
86a74ff2
NI		 1853 phy_print_status(phydev);
1854}
1855
1856/* PHY init function */
1857static int sh_eth_phy_init(struct net_device *ndev)
1858{
702eca02 1859 struct device_node *np = ndev->dev.parent->of_node;
86a74ff2 1860 struct sh_eth_private *mdp = netdev_priv(ndev);
4fa8c3cc 1861 struct phy_device *phydev;
86a74ff2 1862
3340d2aa 1863 mdp->link = 0;
86a74ff2
NI		 1864 mdp->speed = 0;
1865 mdp->duplex = -1;
1866
1867 /* Try connect to PHY */
702eca02
BD		 1868 if (np) {
1869 struct device_node *pn;
1870
1871 pn = of_parse_phandle(np, "phy-handle", 0);
1872 phydev = of_phy_connect(ndev, pn,
1873 sh_eth_adjust_link, 0,
1874 mdp->phy_interface);
1875
8da703dc 1876 of_node_put(pn);
702eca02
BD		 1877 if (!phydev)
1878 phydev = ERR_PTR(-ENOENT);
1879 } else {
1880 char phy_id[MII_BUS_ID_SIZE + 3];
1881
1882 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
1883 mdp->mii_bus->id, mdp->phy_id);
1884
1885 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
1886 mdp->phy_interface);
1887 }
1888
86a74ff2 1889 if (IS_ERR(phydev)) {
da246855 1890 netdev_err(ndev, "failed to connect PHY\n");
86a74ff2
NI		 1891 return PTR_ERR(phydev);
1892 }
380af9e3 1893
2220943a 1894 phy_attached_info(phydev);
86a74ff2 1895
86a74ff2
NI		 1896 return 0;
1897}
1898
1899/* PHY control start function */
1900static int sh_eth_phy_start(struct net_device *ndev)
1901{
86a74ff2
NI		 1902 int ret;
1903
1904 ret = sh_eth_phy_init(ndev);
1905 if (ret)
1906 return ret;
1907
9fd0375a 1908 phy_start(ndev->phydev);
86a74ff2
NI		 1909
1910 return 0;
1911}
1912
f08aff44
PR		 1913static int sh_eth_get_link_ksettings(struct net_device *ndev,
1914 struct ethtool_link_ksettings *cmd)
dc19e4e5
NI		 1915{
1916 struct sh_eth_private *mdp = netdev_priv(ndev);
1917 unsigned long flags;
1918 int ret;
1919
9fd0375a 1920 if (!ndev->phydev)
4f9dce23
BH		 1921 return -ENODEV;
1922
dc19e4e5 1923 spin_lock_irqsave(&mdp->lock, flags);
f08aff44 1924 ret = phy_ethtool_ksettings_get(ndev->phydev, cmd);
dc19e4e5
NI		 1925 spin_unlock_irqrestore(&mdp->lock, flags);
1926
1927 return ret;
1928}
1929
f08aff44
PR		 1930static int sh_eth_set_link_ksettings(struct net_device *ndev,
1931 const struct ethtool_link_ksettings *cmd)
dc19e4e5
NI		 1932{
1933 struct sh_eth_private *mdp = netdev_priv(ndev);
1934 unsigned long flags;
1935 int ret;
dc19e4e5 1936
9fd0375a 1937 if (!ndev->phydev)
4f9dce23
BH		 1938 return -ENODEV;
1939
dc19e4e5
NI		 1940 spin_lock_irqsave(&mdp->lock, flags);
1941
1942 /* disable tx and rx */
4a55530f 1943 sh_eth_rcv_snd_disable(ndev);
dc19e4e5 1944
f08aff44 1945 ret = phy_ethtool_ksettings_set(ndev->phydev, cmd);
dc19e4e5
NI		 1946 if (ret)
1947 goto error_exit;
1948
f08aff44 1949 if (cmd->base.duplex == DUPLEX_FULL)
dc19e4e5
NI		 1950 mdp->duplex = 1;
1951 else
1952 mdp->duplex = 0;
1953
1954 if (mdp->cd->set_duplex)
1955 mdp->cd->set_duplex(ndev);
1956
1957error_exit:
1958 mdelay(1);
1959
1960 /* enable tx and rx */
4a55530f 1961 sh_eth_rcv_snd_enable(ndev);
dc19e4e5
NI		 1962
1963 spin_unlock_irqrestore(&mdp->lock, flags);
1964
1965 return ret;
1966}
1967
6b4b4fea
BH		 1968/* If it is ever necessary to increase SH_ETH_REG_DUMP_MAX_REGS, the
1969 * version must be bumped as well. Just adding registers up to that
1970 * limit is fine, as long as the existing register indices don't
1971 * change.
1972 */
1973#define SH_ETH_REG_DUMP_VERSION 1
1974#define SH_ETH_REG_DUMP_MAX_REGS 256
1975
1976static size_t __sh_eth_get_regs(struct net_device *ndev, u32 *buf)
1977{
1978 struct sh_eth_private *mdp = netdev_priv(ndev);
1979 struct sh_eth_cpu_data *cd = mdp->cd;
1980 u32 *valid_map;
1981 size_t len;
1982
1983 BUILD_BUG_ON(SH_ETH_MAX_REGISTER_OFFSET > SH_ETH_REG_DUMP_MAX_REGS);
1984
1985 /* Dump starts with a bitmap that tells ethtool which
1986 * registers are defined for this chip.
1987 */
1988 len = DIV_ROUND_UP(SH_ETH_REG_DUMP_MAX_REGS, 32);
1989 if (buf) {
1990 valid_map = buf;
1991 buf += len;
1992 } else {
1993 valid_map = NULL;
1994 }
1995
1996 /* Add a register to the dump, if it has a defined offset.
1997 * This automatically skips most undefined registers, but for
1998 * some it is also necessary to check a capability flag in
1999 * struct sh_eth_cpu_data.
2000 */
2001#define mark_reg_valid(reg) valid_map[reg / 32] |= 1U << (reg % 32)
2002#define add_reg_from(reg, read_expr) do { \
2003 if (mdp->reg_offset[reg] != SH_ETH_OFFSET_INVALID) { \
2004 if (buf) { \
2005 mark_reg_valid(reg); \
2006 *buf++ = read_expr; \
2007 } \
2008 ++len; \
2009 } \
2010 } while (0)
2011#define add_reg(reg) add_reg_from(reg, sh_eth_read(ndev, reg))
2012#define add_tsu_reg(reg) add_reg_from(reg, sh_eth_tsu_read(mdp, reg))
2013
2014 add_reg(EDSR);
2015 add_reg(EDMR);
2016 add_reg(EDTRR);
2017 add_reg(EDRRR);
2018 add_reg(EESR);
2019 add_reg(EESIPR);
2020 add_reg(TDLAR);
2021 add_reg(TDFAR);
2022 add_reg(TDFXR);
2023 add_reg(TDFFR);
2024 add_reg(RDLAR);
2025 add_reg(RDFAR);
2026 add_reg(RDFXR);
2027 add_reg(RDFFR);
2028 add_reg(TRSCER);
2029 add_reg(RMFCR);
2030 add_reg(TFTR);
2031 add_reg(FDR);
2032 add_reg(RMCR);
2033 add_reg(TFUCR);
2034 add_reg(RFOCR);
2035 if (cd->rmiimode)
2036 add_reg(RMIIMODE);
2037 add_reg(FCFTR);
2038 if (cd->rpadir)
2039 add_reg(RPADIR);
2040 if (!cd->no_trimd)
2041 add_reg(TRIMD);
2042 add_reg(ECMR);
2043 add_reg(ECSR);
2044 add_reg(ECSIPR);
2045 add_reg(PIR);
2046 if (!cd->no_psr)
2047 add_reg(PSR);
2048 add_reg(RDMLR);
2049 add_reg(RFLR);
2050 add_reg(IPGR);
2051 if (cd->apr)
2052 add_reg(APR);
2053 if (cd->mpr)
2054 add_reg(MPR);
2055 add_reg(RFCR);
2056 add_reg(RFCF);
2057 if (cd->tpauser)
2058 add_reg(TPAUSER);
2059 add_reg(TPAUSECR);
2060 add_reg(GECMR);
2061 if (cd->bculr)
2062 add_reg(BCULR);
2063 add_reg(MAHR);
2064 add_reg(MALR);
2065 add_reg(TROCR);
2066 add_reg(CDCR);
2067 add_reg(LCCR);
2068 add_reg(CNDCR);
2069 add_reg(CEFCR);
2070 add_reg(FRECR);
2071 add_reg(TSFRCR);
2072 add_reg(TLFRCR);
2073 add_reg(CERCR);
2074 add_reg(CEECR);
2075 add_reg(MAFCR);
2076 if (cd->rtrate)
2077 add_reg(RTRATE);
62e04b7e 2078 if (cd->hw_checksum)
6b4b4fea
BH		 2079 add_reg(CSMR);
2080 if (cd->select_mii)
2081 add_reg(RMII_MII);
2082 add_reg(ARSTR);
2083 if (cd->tsu) {
2084 add_tsu_reg(TSU_CTRST);
2085 add_tsu_reg(TSU_FWEN0);
2086 add_tsu_reg(TSU_FWEN1);
2087 add_tsu_reg(TSU_FCM);
2088 add_tsu_reg(TSU_BSYSL0);
2089 add_tsu_reg(TSU_BSYSL1);
2090 add_tsu_reg(TSU_PRISL0);
2091 add_tsu_reg(TSU_PRISL1);
2092 add_tsu_reg(TSU_FWSL0);
2093 add_tsu_reg(TSU_FWSL1);
2094 add_tsu_reg(TSU_FWSLC);
2095 add_tsu_reg(TSU_QTAG0);
2096 add_tsu_reg(TSU_QTAG1);
2097 add_tsu_reg(TSU_QTAGM0);
2098 add_tsu_reg(TSU_QTAGM1);
2099 add_tsu_reg(TSU_FWSR);
2100 add_tsu_reg(TSU_FWINMK);
2101 add_tsu_reg(TSU_ADQT0);
2102 add_tsu_reg(TSU_ADQT1);
2103 add_tsu_reg(TSU_VTAG0);
2104 add_tsu_reg(TSU_VTAG1);
2105 add_tsu_reg(TSU_ADSBSY);
2106 add_tsu_reg(TSU_TEN);
2107 add_tsu_reg(TSU_POST1);
2108 add_tsu_reg(TSU_POST2);
2109 add_tsu_reg(TSU_POST3);
2110 add_tsu_reg(TSU_POST4);
2111 if (mdp->reg_offset[TSU_ADRH0] != SH_ETH_OFFSET_INVALID) {
2112 /* This is the start of a table, not just a single
2113 * register.
2114 */
2115 if (buf) {
2116 unsigned int i;
2117
2118 mark_reg_valid(TSU_ADRH0);
2119 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES * 2; i++)
2120 *buf++ = ioread32(
2121 mdp->tsu_addr +
2122 mdp->reg_offset[TSU_ADRH0] +
2123 i * 4);
2124 }
2125 len += SH_ETH_TSU_CAM_ENTRIES * 2;
2126 }
2127 }
2128
2129#undef mark_reg_valid
2130#undef add_reg_from
2131#undef add_reg
2132#undef add_tsu_reg
2133
2134 return len * 4;
2135}
2136
2137static int sh_eth_get_regs_len(struct net_device *ndev)
2138{
2139 return __sh_eth_get_regs(ndev, NULL);
2140}
2141
2142static void sh_eth_get_regs(struct net_device *ndev, struct ethtool_regs *regs,
2143 void *buf)
2144{
2145 struct sh_eth_private *mdp = netdev_priv(ndev);
2146
2147 regs->version = SH_ETH_REG_DUMP_VERSION;
2148
2149 pm_runtime_get_sync(&mdp->pdev->dev);
2150 __sh_eth_get_regs(ndev, buf);
2151 pm_runtime_put_sync(&mdp->pdev->dev);
2152}
2153
dc19e4e5
NI		 2154static int sh_eth_nway_reset(struct net_device *ndev)
2155{
2156 struct sh_eth_private *mdp = netdev_priv(ndev);
2157 unsigned long flags;
2158 int ret;
2159
9fd0375a 2160 if (!ndev->phydev)
4f9dce23
BH		 2161 return -ENODEV;
2162
dc19e4e5 2163 spin_lock_irqsave(&mdp->lock, flags);
9fd0375a 2164 ret = phy_start_aneg(ndev->phydev);
dc19e4e5
NI		 2165 spin_unlock_irqrestore(&mdp->lock, flags);
2166
2167 return ret;
2168}
2169
2170static u32 sh_eth_get_msglevel(struct net_device *ndev)
2171{
2172 struct sh_eth_private *mdp = netdev_priv(ndev);
2173 return mdp->msg_enable;
2174}
2175
2176static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
2177{
2178 struct sh_eth_private *mdp = netdev_priv(ndev);
2179 mdp->msg_enable = value;
2180}
2181
2182static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
2183 "rx_current", "tx_current",
2184 "rx_dirty", "tx_dirty",
2185};
2186#define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats)
2187
2188static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
2189{
2190 switch (sset) {
2191 case ETH_SS_STATS:
2192 return SH_ETH_STATS_LEN;
2193 default:
2194 return -EOPNOTSUPP;
2195 }
2196}
2197
2198static void sh_eth_get_ethtool_stats(struct net_device *ndev,
128296fc 2199 struct ethtool_stats *stats, u64 *data)
dc19e4e5
NI		 2200{
2201 struct sh_eth_private *mdp = netdev_priv(ndev);
2202 int i = 0;
2203
2204 /* device-specific stats */
2205 data[i++] = mdp->cur_rx;
2206 data[i++] = mdp->cur_tx;
2207 data[i++] = mdp->dirty_rx;
2208 data[i++] = mdp->dirty_tx;
2209}
2210
2211static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
2212{
2213 switch (stringset) {
2214 case ETH_SS_STATS:
2215 memcpy(data, *sh_eth_gstrings_stats,
128296fc 2216 sizeof(sh_eth_gstrings_stats));
dc19e4e5
NI		 2217 break;
2218 }
2219}
2220
525b8075
YS		 2221static void sh_eth_get_ringparam(struct net_device *ndev,
2222 struct ethtool_ringparam *ring)
2223{
2224 struct sh_eth_private *mdp = netdev_priv(ndev);
2225
2226 ring->rx_max_pending = RX_RING_MAX;
2227 ring->tx_max_pending = TX_RING_MAX;
2228 ring->rx_pending = mdp->num_rx_ring;
2229 ring->tx_pending = mdp->num_tx_ring;
2230}
2231
2232static int sh_eth_set_ringparam(struct net_device *ndev,
2233 struct ethtool_ringparam *ring)
2234{
2235 struct sh_eth_private *mdp = netdev_priv(ndev);
2236 int ret;
2237
2238 if (ring->tx_pending > TX_RING_MAX ||
2239 ring->rx_pending > RX_RING_MAX ||
2240 ring->tx_pending < TX_RING_MIN ||
2241 ring->rx_pending < RX_RING_MIN)
2242 return -EINVAL;
2243 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
2244 return -EINVAL;
2245
2246 if (netif_running(ndev)) {
bd888916 2247 netif_device_detach(ndev);
525b8075 2248 netif_tx_disable(ndev);
283e38db
BH		 2249
2250 /* Serialise with the interrupt handler and NAPI, then
2251 * disable interrupts. We have to clear the
2252 * irq_enabled flag first to ensure that interrupts
2253 * won't be re-enabled.
2254 */
2255 mdp->irq_enabled = false;
525b8075 2256 synchronize_irq(ndev->irq);
283e38db 2257 napi_synchronize(&mdp->napi);
525b8075 2258 sh_eth_write(ndev, 0x0000, EESIPR);
525b8075 2259
740c7f31 2260 sh_eth_dev_exit(ndev);
525b8075 2261
8e03a5e7 2262 /* Free all the skbuffs in the Rx queue and the DMA buffers. */
084236d8 2263 sh_eth_ring_free(ndev);
084236d8 2264 }
525b8075
YS		 2265
2266 /* Set new parameters */
2267 mdp->num_rx_ring = ring->rx_pending;
2268 mdp->num_tx_ring = ring->tx_pending;
2269
525b8075 2270 if (netif_running(ndev)) {
084236d8
BH		 2271 ret = sh_eth_ring_init(ndev);
2272 if (ret < 0) {
2273 netdev_err(ndev, "%s: sh_eth_ring_init failed.\n",
2274 __func__);
2275 return ret;
2276 }
f7967210 2277 ret = sh_eth_dev_init(ndev);
084236d8
BH		 2278 if (ret < 0) {
2279 netdev_err(ndev, "%s: sh_eth_dev_init failed.\n",
2280 __func__);
2281 return ret;
2282 }
2283
bd888916 2284 netif_device_attach(ndev);
525b8075
YS		 2285 }
2286
2287 return 0;
2288}
2289
d8981d02
NS		 2290static void sh_eth_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2291{
2292 struct sh_eth_private *mdp = netdev_priv(ndev);
2293
2294 wol->supported = 0;
2295 wol->wolopts = 0;
2296
2297 if (mdp->cd->magic && mdp->clk) {
2298 wol->supported = WAKE_MAGIC;
2299 wol->wolopts = mdp->wol_enabled ? WAKE_MAGIC : 0;
2300 }
2301}
2302
2303static int sh_eth_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2304{
2305 struct sh_eth_private *mdp = netdev_priv(ndev);
2306
2307 if (!mdp->cd->magic || !mdp->clk || wol->wolopts & ~WAKE_MAGIC)
2308 return -EOPNOTSUPP;
2309
2310 mdp->wol_enabled = !!(wol->wolopts & WAKE_MAGIC);
2311
2312 device_set_wakeup_enable(&mdp->pdev->dev, mdp->wol_enabled);
2313
2314 return 0;
2315}
2316
9b07be4b 2317static const struct ethtool_ops sh_eth_ethtool_ops = {
6b4b4fea
BH		 2318 .get_regs_len = sh_eth_get_regs_len,
2319 .get_regs = sh_eth_get_regs,
9b07be4b 2320 .nway_reset = sh_eth_nway_reset,
dc19e4e5
NI		 2321 .get_msglevel = sh_eth_get_msglevel,
2322 .set_msglevel = sh_eth_set_msglevel,
9b07be4b 2323 .get_link = ethtool_op_get_link,
dc19e4e5
NI		 2324 .get_strings = sh_eth_get_strings,
2325 .get_ethtool_stats = sh_eth_get_ethtool_stats,
2326 .get_sset_count = sh_eth_get_sset_count,
525b8075
YS		 2327 .get_ringparam = sh_eth_get_ringparam,
2328 .set_ringparam = sh_eth_set_ringparam,
f08aff44
PR		 2329 .get_link_ksettings = sh_eth_get_link_ksettings,
2330 .set_link_ksettings = sh_eth_set_link_ksettings,
d8981d02
NS		 2331 .get_wol = sh_eth_get_wol,
2332 .set_wol = sh_eth_set_wol,
dc19e4e5
NI		 2333};
2334
86a74ff2
NI		 2335/* network device open function */
2336static int sh_eth_open(struct net_device *ndev)
2337{
86a74ff2 2338 struct sh_eth_private *mdp = netdev_priv(ndev);
4fa8c3cc 2339 int ret;
86a74ff2 2340
bcd5149d
MD		 2341 pm_runtime_get_sync(&mdp->pdev->dev);
2342
d2779e99
SS		 2343 napi_enable(&mdp->napi);
2344
a0607fd3 2345 ret = request_irq(ndev->irq, sh_eth_interrupt,
5b3dfd13 2346 mdp->cd->irq_flags, ndev->name, ndev);
86a74ff2 2347 if (ret) {
da246855 2348 netdev_err(ndev, "Can not assign IRQ number\n");
d2779e99 2349 goto out_napi_off;
86a74ff2
NI		 2350 }
2351
2352 /* Descriptor set */
2353 ret = sh_eth_ring_init(ndev);
2354 if (ret)
2355 goto out_free_irq;
2356
2357 /* device init */
f7967210 2358 ret = sh_eth_dev_init(ndev);
86a74ff2
NI		 2359 if (ret)
2360 goto out_free_irq;
2361
2362 /* PHY control start*/
2363 ret = sh_eth_phy_start(ndev);
2364 if (ret)
2365 goto out_free_irq;
2366
ad846aa5
SS		 2367 netif_start_queue(ndev);
2368
7fa2955f
MK		 2369 mdp->is_opened = 1;
2370
86a74ff2
NI		 2371 return ret;
2372
2373out_free_irq:
2374 free_irq(ndev->irq, ndev);
d2779e99
SS		 2375out_napi_off:
2376 napi_disable(&mdp->napi);
bcd5149d 2377 pm_runtime_put_sync(&mdp->pdev->dev);
86a74ff2
NI		 2378 return ret;
2379}
2380
2381/* Timeout function */
2382static void sh_eth_tx_timeout(struct net_device *ndev)
2383{
2384 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 2385 struct sh_eth_rxdesc *rxdesc;
2386 int i;
2387
2388 netif_stop_queue(ndev);
2389
8d5009f6
SS		 2390 netif_err(mdp, timer, ndev,
2391 "transmit timed out, status %8.8x, resetting...\n",
0799c2d6 2392 sh_eth_read(ndev, EESR));
86a74ff2
NI		 2393
2394 /* tx_errors count up */
bb7d92e3 2395 ndev->stats.tx_errors++;
86a74ff2 2396
86a74ff2 2397 /* Free all the skbuffs in the Rx queue. */
525b8075 2398 for (i = 0; i < mdp->num_rx_ring; i++) {
86a74ff2 2399 rxdesc = &mdp->rx_ring[i];
7cf72477
SS		 2400 rxdesc->status = cpu_to_le32(0);
2401 rxdesc->addr = cpu_to_le32(0xBADF00D0);
179d80af 2402 dev_kfree_skb(mdp->rx_skbuff[i]);
86a74ff2
NI		 2403 mdp->rx_skbuff[i] = NULL;
2404 }
525b8075 2405 for (i = 0; i < mdp->num_tx_ring; i++) {
179d80af 2406 dev_kfree_skb(mdp->tx_skbuff[i]);
86a74ff2
NI		 2407 mdp->tx_skbuff[i] = NULL;
2408 }
2409
2410 /* device init */
f7967210 2411 sh_eth_dev_init(ndev);
ad846aa5
SS		 2412
2413 netif_start_queue(ndev);
86a74ff2
NI		 2414}
2415
2416/* Packet transmit function */
2417static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
2418{
2419 struct sh_eth_private *mdp = netdev_priv(ndev);
2420 struct sh_eth_txdesc *txdesc;
1299653a 2421 dma_addr_t dma_addr;
86a74ff2 2422 u32 entry;
fb5e2f9b 2423 unsigned long flags;
86a74ff2
NI		 2424
2425 spin_lock_irqsave(&mdp->lock, flags);
525b8075 2426 if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
1debdc8f 2427 if (!sh_eth_tx_free(ndev, true)) {
8d5009f6 2428 netif_warn(mdp, tx_queued, ndev, "TxFD exhausted.\n");
86a74ff2
NI		 2429 netif_stop_queue(ndev);
2430 spin_unlock_irqrestore(&mdp->lock, flags);
5b548140 2431 return NETDEV_TX_BUSY;
86a74ff2
NI		 2432 }
2433 }
2434 spin_unlock_irqrestore(&mdp->lock, flags);
2435
dacc73e0 2436 if (skb_put_padto(skb, ETH_ZLEN))
eebfb643
BH		 2437 return NETDEV_TX_OK;
2438
525b8075 2439 entry = mdp->cur_tx % mdp->num_tx_ring;
86a74ff2
NI		 2440 mdp->tx_skbuff[entry] = skb;
2441 txdesc = &mdp->tx_ring[entry];
86a74ff2 2442 /* soft swap. */
380af9e3 2443 if (!mdp->cd->hw_swap)
3e230993 2444 sh_eth_soft_swap(PTR_ALIGN(skb->data, 4), skb->len + 2);
1299653a
SS		 2445 dma_addr = dma_map_single(&ndev->dev, skb->data, skb->len,
2446 DMA_TO_DEVICE);
2447 if (dma_mapping_error(&ndev->dev, dma_addr)) {
aa3933b8
BH		 2448 kfree_skb(skb);
2449 return NETDEV_TX_OK;
2450 }
7cf72477
SS		 2451 txdesc->addr = cpu_to_le32(dma_addr);
2452 txdesc->len = cpu_to_le32(skb->len << 16);
86a74ff2 2453
f32bfb9a 2454 dma_wmb(); /* TACT bit must be set after all the above writes */
525b8075 2455 if (entry >= mdp->num_tx_ring - 1)
7cf72477 2456 txdesc->status |= cpu_to_le32(TD_TACT | TD_TDLE);
86a74ff2 2457 else
7cf72477 2458 txdesc->status |= cpu_to_le32(TD_TACT);
86a74ff2
NI		 2459
2460 mdp->cur_tx++;
2461
c5ed5368
YS		 2462 if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
2463 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
b0ca2a21 2464
6ed10654 2465 return NETDEV_TX_OK;
86a74ff2
NI		 2466}
2467
4398f9c8
BH		 2468/* The statistics registers have write-clear behaviour, which means we
2469 * will lose any increment between the read and write. We mitigate
2470 * this by only clearing when we read a non-zero value, so we will
2471 * never falsely report a total of zero.
2472 */
2473static void
2474sh_eth_update_stat(struct net_device *ndev, unsigned long *stat, int reg)
2475{
2476 u32 delta = sh_eth_read(ndev, reg);
2477
2478 if (delta) {
2479 *stat += delta;
2480 sh_eth_write(ndev, 0, reg);
2481 }
2482}
2483
7fa2955f
MK		 2484static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
2485{
2486 struct sh_eth_private *mdp = netdev_priv(ndev);
2487
2488 if (sh_eth_is_rz_fast_ether(mdp))
2489 return &ndev->stats;
2490
2491 if (!mdp->is_opened)
2492 return &ndev->stats;
2493
4398f9c8
BH		 2494 sh_eth_update_stat(ndev, &ndev->stats.tx_dropped, TROCR);
2495 sh_eth_update_stat(ndev, &ndev->stats.collisions, CDCR);
2496 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, LCCR);
7fa2955f
MK		 2497
2498 if (sh_eth_is_gether(mdp)) {
4398f9c8
BH		 2499 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2500 CERCR);
2501 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2502 CEECR);
7fa2955f 2503 } else {
4398f9c8
BH		 2504 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2505 CNDCR);
7fa2955f
MK		 2506 }
2507
2508 return &ndev->stats;
2509}
2510
86a74ff2
NI		 2511/* device close function */
2512static int sh_eth_close(struct net_device *ndev)
2513{
2514 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 2515
2516 netif_stop_queue(ndev);
2517
283e38db
BH		 2518 /* Serialise with the interrupt handler and NAPI, then disable
2519 * interrupts. We have to clear the irq_enabled flag first to
2520 * ensure that interrupts won't be re-enabled.
2521 */
2522 mdp->irq_enabled = false;
2523 synchronize_irq(ndev->irq);
2524 napi_disable(&mdp->napi);
4a55530f 2525 sh_eth_write(ndev, 0x0000, EESIPR);
86a74ff2 2526
740c7f31 2527 sh_eth_dev_exit(ndev);
86a74ff2
NI		 2528
2529 /* PHY Disconnect */
9fd0375a
PR		 2530 if (ndev->phydev) {
2531 phy_stop(ndev->phydev);
2532 phy_disconnect(ndev->phydev);
86a74ff2
NI		 2533 }
2534
2535 free_irq(ndev->irq, ndev);
2536
8e03a5e7 2537 /* Free all the skbuffs in the Rx queue and the DMA buffer. */
86a74ff2
NI		 2538 sh_eth_ring_free(ndev);
2539
bcd5149d
MD		 2540 pm_runtime_put_sync(&mdp->pdev->dev);
2541
7fa2955f 2542 mdp->is_opened = 0;
bcd5149d 2543
7fa2955f 2544 return 0;
86a74ff2
NI		 2545}
2546
bb7d92e3 2547/* ioctl to device function */
128296fc 2548static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
86a74ff2 2549{
9fd0375a 2550 struct phy_device *phydev = ndev->phydev;
86a74ff2
NI		 2551
2552 if (!netif_running(ndev))
2553 return -EINVAL;
2554
2555 if (!phydev)
2556 return -ENODEV;
2557
28b04113 2558 return phy_mii_ioctl(phydev, rq, cmd);
86a74ff2
NI		 2559}
2560
78d61022
NS		 2561static int sh_eth_change_mtu(struct net_device *ndev, int new_mtu)
2562{
2563 if (netif_running(ndev))
2564 return -EBUSY;
2565
2566 ndev->mtu = new_mtu;
2567 netdev_update_features(ndev);
2568
2569 return 0;
2570}
2571
6743fe6d
YS		 2572/* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
2573static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp,
2574 int entry)
2575{
2576 return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4);
2577}
2578
2579static u32 sh_eth_tsu_get_post_mask(int entry)
2580{
2581 return 0x0f << (28 - ((entry % 8) * 4));
2582}
2583
2584static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
2585{
2586 return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
2587}
2588
2589static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
2590 int entry)
2591{
2592 struct sh_eth_private *mdp = netdev_priv(ndev);
2593 u32 tmp;
2594 void *reg_offset;
2595
2596 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2597 tmp = ioread32(reg_offset);
2598 iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset);
2599}
2600
2601static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
2602 int entry)
2603{
2604 struct sh_eth_private *mdp = netdev_priv(ndev);
2605 u32 post_mask, ref_mask, tmp;
2606 void *reg_offset;
2607
2608 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2609 post_mask = sh_eth_tsu_get_post_mask(entry);
2610 ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
2611
2612 tmp = ioread32(reg_offset);
2613 iowrite32(tmp & ~post_mask, reg_offset);
2614
2615 /* If other port enables, the function returns "true" */
2616 return tmp & ref_mask;
2617}
2618
2619static int sh_eth_tsu_busy(struct net_device *ndev)
2620{
2621 int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
2622 struct sh_eth_private *mdp = netdev_priv(ndev);
2623
2624 while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
2625 udelay(10);
2626 timeout--;
2627 if (timeout <= 0) {
da246855 2628 netdev_err(ndev, "%s: timeout\n", __func__);
6743fe6d
YS		 2629 return -ETIMEDOUT;
2630 }
2631 }
2632
2633 return 0;
2634}
2635
2636static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg,
2637 const u8 *addr)
2638{
2639 u32 val;
2640
2641 val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
2642 iowrite32(val, reg);
2643 if (sh_eth_tsu_busy(ndev) < 0)
2644 return -EBUSY;
2645
2646 val = addr[4] << 8 | addr[5];
2647 iowrite32(val, reg + 4);
2648 if (sh_eth_tsu_busy(ndev) < 0)
2649 return -EBUSY;
2650
2651 return 0;
2652}
2653
2654static void sh_eth_tsu_read_entry(void *reg, u8 *addr)
2655{
2656 u32 val;
2657
2658 val = ioread32(reg);
2659 addr[0] = (val >> 24) & 0xff;
2660 addr[1] = (val >> 16) & 0xff;
2661 addr[2] = (val >> 8) & 0xff;
2662 addr[3] = val & 0xff;
2663 val = ioread32(reg + 4);
2664 addr[4] = (val >> 8) & 0xff;
2665 addr[5] = val & 0xff;
2666}
2667
2668
2669static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
2670{
2671 struct sh_eth_private *mdp = netdev_priv(ndev);
2672 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2673 int i;
2674 u8 c_addr[ETH_ALEN];
2675
2676 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2677 sh_eth_tsu_read_entry(reg_offset, c_addr);
c4bde29c 2678 if (ether_addr_equal(addr, c_addr))
6743fe6d
YS		 2679 return i;
2680 }
2681
2682 return -ENOENT;
2683}
2684
2685static int sh_eth_tsu_find_empty(struct net_device *ndev)
2686{
2687 u8 blank[ETH_ALEN];
2688 int entry;
2689
2690 memset(blank, 0, sizeof(blank));
2691 entry = sh_eth_tsu_find_entry(ndev, blank);
2692 return (entry < 0) ? -ENOMEM : entry;
2693}
2694
2695static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
2696 int entry)
2697{
2698 struct sh_eth_private *mdp = netdev_priv(ndev);
2699 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2700 int ret;
2701 u8 blank[ETH_ALEN];
2702
2703 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
2704 ~(1 << (31 - entry)), TSU_TEN);
2705
2706 memset(blank, 0, sizeof(blank));
2707 ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
2708 if (ret < 0)
2709 return ret;
2710 return 0;
2711}
2712
2713static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
2714{
2715 struct sh_eth_private *mdp = netdev_priv(ndev);
2716 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2717 int i, ret;
2718
2719 if (!mdp->cd->tsu)
2720 return 0;
2721
2722 i = sh_eth_tsu_find_entry(ndev, addr);
2723 if (i < 0) {
2724 /* No entry found, create one */
2725 i = sh_eth_tsu_find_empty(ndev);
2726 if (i < 0)
2727 return -ENOMEM;
2728 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
2729 if (ret < 0)
2730 return ret;
2731
2732 /* Enable the entry */
2733 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
2734 (1 << (31 - i)), TSU_TEN);
2735 }
2736
2737 /* Entry found or created, enable POST */
2738 sh_eth_tsu_enable_cam_entry_post(ndev, i);
2739
2740 return 0;
2741}
2742
2743static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
2744{
2745 struct sh_eth_private *mdp = netdev_priv(ndev);
2746 int i, ret;
2747
2748 if (!mdp->cd->tsu)
2749 return 0;
2750
2751 i = sh_eth_tsu_find_entry(ndev, addr);
2752 if (i) {
2753 /* Entry found */
2754 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2755 goto done;
2756
2757 /* Disable the entry if both ports was disabled */
2758 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2759 if (ret < 0)
2760 return ret;
2761 }
2762done:
2763 return 0;
2764}
2765
2766static int sh_eth_tsu_purge_all(struct net_device *ndev)
2767{
2768 struct sh_eth_private *mdp = netdev_priv(ndev);
2769 int i, ret;
2770
b37feed7 2771 if (!mdp->cd->tsu)
6743fe6d
YS		 2772 return 0;
2773
2774 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
2775 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2776 continue;
2777
2778 /* Disable the entry if both ports was disabled */
2779 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2780 if (ret < 0)
2781 return ret;
2782 }
2783
2784 return 0;
2785}
2786
2787static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
2788{
2789 struct sh_eth_private *mdp = netdev_priv(ndev);
2790 u8 addr[ETH_ALEN];
2791 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2792 int i;
2793
b37feed7 2794 if (!mdp->cd->tsu)
6743fe6d
YS		 2795 return;
2796
2797 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2798 sh_eth_tsu_read_entry(reg_offset, addr);
2799 if (is_multicast_ether_addr(addr))
2800 sh_eth_tsu_del_entry(ndev, addr);
2801 }
2802}
2803
b37feed7
BH		 2804/* Update promiscuous flag and multicast filter */
2805static void sh_eth_set_rx_mode(struct net_device *ndev)
86a74ff2 2806{
6743fe6d
YS		 2807 struct sh_eth_private *mdp = netdev_priv(ndev);
2808 u32 ecmr_bits;
2809 int mcast_all = 0;
2810 unsigned long flags;
2811
2812 spin_lock_irqsave(&mdp->lock, flags);
128296fc 2813 /* Initial condition is MCT = 1, PRM = 0.
6743fe6d
YS		 2814 * Depending on ndev->flags, set PRM or clear MCT
2815 */
b37feed7
BH		 2816 ecmr_bits = sh_eth_read(ndev, ECMR) & ~ECMR_PRM;
2817 if (mdp->cd->tsu)
2818 ecmr_bits |= ECMR_MCT;
6743fe6d
YS		 2819
2820 if (!(ndev->flags & IFF_MULTICAST)) {
2821 sh_eth_tsu_purge_mcast(ndev);
2822 mcast_all = 1;
2823 }
2824 if (ndev->flags & IFF_ALLMULTI) {
2825 sh_eth_tsu_purge_mcast(ndev);
2826 ecmr_bits &= ~ECMR_MCT;
2827 mcast_all = 1;
2828 }
2829
86a74ff2 2830 if (ndev->flags & IFF_PROMISC) {
6743fe6d
YS		 2831 sh_eth_tsu_purge_all(ndev);
2832 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2833 } else if (mdp->cd->tsu) {
2834 struct netdev_hw_addr *ha;
2835 netdev_for_each_mc_addr(ha, ndev) {
2836 if (mcast_all && is_multicast_ether_addr(ha->addr))
2837 continue;
2838
2839 if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2840 if (!mcast_all) {
2841 sh_eth_tsu_purge_mcast(ndev);
2842 ecmr_bits &= ~ECMR_MCT;
2843 mcast_all = 1;
2844 }
2845 }
2846 }
86a74ff2 2847 }
6743fe6d
YS		 2848
2849 /* update the ethernet mode */
2850 sh_eth_write(ndev, ecmr_bits, ECMR);
2851
2852 spin_unlock_irqrestore(&mdp->lock, flags);
86a74ff2 2853}
71cc7c37
YS		 2854
2855static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2856{
2857 if (!mdp->port)
2858 return TSU_VTAG0;
2859 else
2860 return TSU_VTAG1;
2861}
2862
80d5c368
PM		 2863static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
2864 __be16 proto, u16 vid)
71cc7c37
YS		 2865{
2866 struct sh_eth_private *mdp = netdev_priv(ndev);
2867 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2868
2869 if (unlikely(!mdp->cd->tsu))
2870 return -EPERM;
2871
2872 /* No filtering if vid = 0 */
2873 if (!vid)
2874 return 0;
2875
2876 mdp->vlan_num_ids++;
2877
128296fc 2878 /* The controller has one VLAN tag HW filter. So, if the filter is
71cc7c37
YS		 2879 * already enabled, the driver disables it and the filte
2880 */
2881 if (mdp->vlan_num_ids > 1) {
2882 /* disable VLAN filter */
2883 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2884 return 0;
2885 }
2886
2887 sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
2888 vtag_reg_index);
2889
2890 return 0;
2891}
2892
80d5c368
PM		 2893static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
2894 __be16 proto, u16 vid)
71cc7c37
YS		 2895{
2896 struct sh_eth_private *mdp = netdev_priv(ndev);
2897 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2898
2899 if (unlikely(!mdp->cd->tsu))
2900 return -EPERM;
2901
2902 /* No filtering if vid = 0 */
2903 if (!vid)
2904 return 0;
2905
2906 mdp->vlan_num_ids--;
2907 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2908
2909 return 0;
2910}
86a74ff2
NI		 2911
2912/* SuperH's TSU register init function */
4a55530f 2913static void sh_eth_tsu_init(struct sh_eth_private *mdp)
86a74ff2 2914{
db893473
SH		 2915 if (sh_eth_is_rz_fast_ether(mdp)) {
2916 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
e1487888
CB		 2917 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL,
2918 TSU_FWSLC); /* Enable POST registers */
db893473
SH		 2919 return;
2920 }
2921
4a55530f
YS		 2922 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */
2923 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */
2924 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */
2925 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
2926 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
2927 sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
2928 sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
2929 sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
2930 sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
2931 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
c5ed5368
YS		 2932 if (sh_eth_is_gether(mdp)) {
2933 sh_eth_tsu_write(mdp, 0, TSU_QTAG0); /* Disable QTAG(0->1) */
2934 sh_eth_tsu_write(mdp, 0, TSU_QTAG1); /* Disable QTAG(1->0) */
2935 } else {
2936 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */
2937 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */
2938 }
4a55530f
YS		 2939 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */
2940 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */
2941 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2942 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */
2943 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */
2944 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */
2945 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */
86a74ff2
NI		 2946}
2947
2948/* MDIO bus release function */
bd920ff5 2949static int sh_mdio_release(struct sh_eth_private *mdp)
86a74ff2 2950{
86a74ff2 2951 /* unregister mdio bus */
bd920ff5 2952 mdiobus_unregister(mdp->mii_bus);
86a74ff2
NI		 2953
2954 /* free bitbang info */
bd920ff5 2955 free_mdio_bitbang(mdp->mii_bus);
86a74ff2
NI		 2956
2957 return 0;
2958}
2959
2960/* MDIO bus init function */
bd920ff5 2961static int sh_mdio_init(struct sh_eth_private *mdp,
b3017e6a 2962 struct sh_eth_plat_data *pd)
86a74ff2 2963{
e7f4dc35 2964 int ret;
86a74ff2 2965 struct bb_info *bitbang;
bd920ff5 2966 struct platform_device *pdev = mdp->pdev;
aa8d4225 2967 struct device *dev = &mdp->pdev->dev;
86a74ff2
NI		 2968
2969 /* create bit control struct for PHY */
aa8d4225 2970 bitbang = devm_kzalloc(dev, sizeof(struct bb_info), GFP_KERNEL);
f738a13d
LP		 2971 if (!bitbang)
2972 return -ENOMEM;
86a74ff2
NI		 2973
2974 /* bitbang init */
ae70644d 2975 bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
b3017e6a 2976 bitbang->set_gate = pd->set_mdio_gate;
86a74ff2
NI		 2977 bitbang->ctrl.ops = &bb_ops;
2978
c2e07b3a 2979 /* MII controller setting */
86a74ff2 2980 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
f738a13d
LP		 2981 if (!mdp->mii_bus)
2982 return -ENOMEM;
86a74ff2
NI		 2983
2984 /* Hook up MII support for ethtool */
2985 mdp->mii_bus->name = "sh_mii";
a5bd6060 2986 mdp->mii_bus->parent = dev;
5278fb54 2987 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
bd920ff5 2988 pdev->name, pdev->id);
86a74ff2 2989
bd920ff5
LP		 2990 /* register MDIO bus */
2991 if (dev->of_node) {
2992 ret = of_mdiobus_register(mdp->mii_bus, dev->of_node);
702eca02 2993 } else {
702eca02
BD		 2994 if (pd->phy_irq > 0)
2995 mdp->mii_bus->irq[pd->phy] = pd->phy_irq;
2996
2997 ret = mdiobus_register(mdp->mii_bus);
2998 }
2999
86a74ff2 3000 if (ret)
d5e07e69 3001 goto out_free_bus;
86a74ff2 3002
86a74ff2
NI		 3003 return 0;
3004
86a74ff2 3005out_free_bus:
298cf9be 3006 free_mdio_bitbang(mdp->mii_bus);
86a74ff2
NI		 3007 return ret;
3008}
3009
4a55530f
YS		 3010static const u16 *sh_eth_get_register_offset(int register_type)
3011{
3012 const u16 *reg_offset = NULL;
3013
3014 switch (register_type) {
3015 case SH_ETH_REG_GIGABIT:
3016 reg_offset = sh_eth_offset_gigabit;
3017 break;
db893473
SH		 3018 case SH_ETH_REG_FAST_RZ:
3019 reg_offset = sh_eth_offset_fast_rz;
3020 break;
a3f109bd
SS		 3021 case SH_ETH_REG_FAST_RCAR:
3022 reg_offset = sh_eth_offset_fast_rcar;
3023 break;
4a55530f
YS		 3024 case SH_ETH_REG_FAST_SH4:
3025 reg_offset = sh_eth_offset_fast_sh4;
3026 break;
3027 case SH_ETH_REG_FAST_SH3_SH2:
3028 reg_offset = sh_eth_offset_fast_sh3_sh2;
3029 break;
4a55530f
YS		 3030 }
3031
3032 return reg_offset;
3033}
3034
8f728d79 3035static const struct net_device_ops sh_eth_netdev_ops = {
ebf84eaa
AB		 3036 .ndo_open = sh_eth_open,
3037 .ndo_stop = sh_eth_close,
3038 .ndo_start_xmit = sh_eth_start_xmit,
3039 .ndo_get_stats = sh_eth_get_stats,
b37feed7 3040 .ndo_set_rx_mode = sh_eth_set_rx_mode,
ebf84eaa
AB		 3041 .ndo_tx_timeout = sh_eth_tx_timeout,
3042 .ndo_do_ioctl = sh_eth_do_ioctl,
78d61022 3043 .ndo_change_mtu = sh_eth_change_mtu,
ebf84eaa
AB		 3044 .ndo_validate_addr = eth_validate_addr,
3045 .ndo_set_mac_address = eth_mac_addr,
ebf84eaa
AB		 3046};
3047
8f728d79
SS		 3048static const struct net_device_ops sh_eth_netdev_ops_tsu = {
3049 .ndo_open = sh_eth_open,
3050 .ndo_stop = sh_eth_close,
3051 .ndo_start_xmit = sh_eth_start_xmit,
3052 .ndo_get_stats = sh_eth_get_stats,
b37feed7 3053 .ndo_set_rx_mode = sh_eth_set_rx_mode,
8f728d79
SS		 3054 .ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid,
3055 .ndo_vlan_rx_kill_vid = sh_eth_vlan_rx_kill_vid,
3056 .ndo_tx_timeout = sh_eth_tx_timeout,
3057 .ndo_do_ioctl = sh_eth_do_ioctl,
78d61022 3058 .ndo_change_mtu = sh_eth_change_mtu,
8f728d79
SS		 3059 .ndo_validate_addr = eth_validate_addr,
3060 .ndo_set_mac_address = eth_mac_addr,
8f728d79
SS		 3061};
3062
b356e978
SS		 3063#ifdef CONFIG_OF
3064static struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
3065{
3066 struct device_node *np = dev->of_node;
3067 struct sh_eth_plat_data *pdata;
b356e978
SS		 3068 const char *mac_addr;
3069
3070 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
3071 if (!pdata)
3072 return NULL;
3073
3074 pdata->phy_interface = of_get_phy_mode(np);
3075
b356e978
SS		 3076 mac_addr = of_get_mac_address(np);
3077 if (mac_addr)
3078 memcpy(pdata->mac_addr, mac_addr, ETH_ALEN);
3079
3080 pdata->no_ether_link =
3081 of_property_read_bool(np, "renesas,no-ether-link");
3082 pdata->ether_link_active_low =
3083 of_property_read_bool(np, "renesas,ether-link-active-low");
3084
3085 return pdata;
3086}
3087
3088static const struct of_device_id sh_eth_match_table[] = {
3089 { .compatible = "renesas,gether-r8a7740", .data = &r8a7740_data },
c099ff3c
SS		 3090 { .compatible = "renesas,ether-r8a7743", .data = &r8a779x_data },
3091 { .compatible = "renesas,ether-r8a7745", .data = &r8a779x_data },
b356e978
SS		 3092 { .compatible = "renesas,ether-r8a7778", .data = &r8a777x_data },
3093 { .compatible = "renesas,ether-r8a7779", .data = &r8a777x_data },
3094 { .compatible = "renesas,ether-r8a7790", .data = &r8a779x_data },
3095 { .compatible = "renesas,ether-r8a7791", .data = &r8a779x_data },
9488e1e5 3096 { .compatible = "renesas,ether-r8a7793", .data = &r8a779x_data },
0f76b9d8 3097 { .compatible = "renesas,ether-r8a7794", .data = &r8a779x_data },
b356e978
SS		 3098 { .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data },
3099 { }
3100};
3101MODULE_DEVICE_TABLE(of, sh_eth_match_table);
3102#else
3103static inline struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
3104{
3105 return NULL;
3106}
3107#endif
3108
86a74ff2
NI		 3109static int sh_eth_drv_probe(struct platform_device *pdev)
3110{
86a74ff2 3111 struct resource *res;
0b76b862 3112 struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev);
afe391ad 3113 const struct platform_device_id *id = platform_get_device_id(pdev);
4fa8c3cc
SS		 3114 struct sh_eth_private *mdp;
3115 struct net_device *ndev;
3116 int ret, devno;
86a74ff2
NI		 3117
3118 /* get base addr */
3119 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
86a74ff2
NI		 3120
3121 ndev = alloc_etherdev(sizeof(struct sh_eth_private));
f738a13d
LP		 3122 if (!ndev)
3123 return -ENOMEM;
86a74ff2 3124
b5893a08
BD		 3125 pm_runtime_enable(&pdev->dev);
3126 pm_runtime_get_sync(&pdev->dev);
3127
86a74ff2
NI		 3128 devno = pdev->id;
3129 if (devno < 0)
3130 devno = 0;
3131
cc3c080d 3132 ret = platform_get_irq(pdev, 0);
7a468ac6 3133 if (ret < 0)
86a74ff2 3134 goto out_release;
cc3c080d 3135 ndev->irq = ret;
86a74ff2
NI		 3136
3137 SET_NETDEV_DEV(ndev, &pdev->dev);
3138
86a74ff2 3139 mdp = netdev_priv(ndev);
525b8075
YS		 3140 mdp->num_tx_ring = TX_RING_SIZE;
3141 mdp->num_rx_ring = RX_RING_SIZE;
d5e07e69
SS		 3142 mdp->addr = devm_ioremap_resource(&pdev->dev, res);
3143 if (IS_ERR(mdp->addr)) {
3144 ret = PTR_ERR(mdp->addr);
ae70644d
YS		 3145 goto out_release;
3146 }
3147
d8981d02
NS		 3148 /* Get clock, if not found that's OK but Wake-On-Lan is unavailable */
3149 mdp->clk = devm_clk_get(&pdev->dev, NULL);
3150 if (IS_ERR(mdp->clk))
3151 mdp->clk = NULL;
3152
c960804f
VB		 3153 ndev->base_addr = res->start;
3154
86a74ff2 3155 spin_lock_init(&mdp->lock);
bcd5149d 3156 mdp->pdev = pdev;
86a74ff2 3157
b356e978
SS		 3158 if (pdev->dev.of_node)
3159 pd = sh_eth_parse_dt(&pdev->dev);
3b4c5cbf
SS		 3160 if (!pd) {
3161 dev_err(&pdev->dev, "no platform data\n");
3162 ret = -EINVAL;
3163 goto out_release;
3164 }
3165
86a74ff2 3166 /* get PHY ID */
71557a37 3167 mdp->phy_id = pd->phy;
e47c9052 3168 mdp->phy_interface = pd->phy_interface;
4923576b
YS		 3169 mdp->no_ether_link = pd->no_ether_link;
3170 mdp->ether_link_active_low = pd->ether_link_active_low;
86a74ff2 3171
380af9e3 3172 /* set cpu data */
42a67c9b 3173 if (id)
b356e978 3174 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data;
42a67c9b
WS		 3175 else
3176 mdp->cd = (struct sh_eth_cpu_data *)of_device_get_match_data(&pdev->dev);
b356e978 3177
a3153d8c 3178 mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type);
264be2f5
SS		 3179 if (!mdp->reg_offset) {
3180 dev_err(&pdev->dev, "Unknown register type (%d)\n",
3181 mdp->cd->register_type);
3182 ret = -EINVAL;
3183 goto out_release;
3184 }
380af9e3
YS		 3185 sh_eth_set_default_cpu_data(mdp->cd);
3186
78d61022
NS		 3187 /* User's manual states max MTU should be 2048 but due to the
3188 * alignment calculations in sh_eth_ring_init() the practical
3189 * MTU is a bit less. Maybe this can be optimized some more.
3190 */
3191 ndev->max_mtu = 2000 - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN);
3192 ndev->min_mtu = ETH_MIN_MTU;
3193
86a74ff2 3194 /* set function */
8f728d79
SS		 3195 if (mdp->cd->tsu)
3196 ndev->netdev_ops = &sh_eth_netdev_ops_tsu;
3197 else
3198 ndev->netdev_ops = &sh_eth_netdev_ops;
7ad24ea4 3199 ndev->ethtool_ops = &sh_eth_ethtool_ops;
86a74ff2
NI		 3200 ndev->watchdog_timeo = TX_TIMEOUT;
3201
dc19e4e5
NI		 3202 /* debug message level */
3203 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
86a74ff2
NI		 3204
3205 /* read and set MAC address */
748031f9 3206 read_mac_address(ndev, pd->mac_addr);
ff6e7228
SS		 3207 if (!is_valid_ether_addr(ndev->dev_addr)) {
3208 dev_warn(&pdev->dev,
3209 "no valid MAC address supplied, using a random one.\n");
3210 eth_hw_addr_random(ndev);
3211 }
86a74ff2 3212
6ba88021
YS		 3213 /* ioremap the TSU registers */
3214 if (mdp->cd->tsu) {
3215 struct resource *rtsu;
3216 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
d5e07e69
SS		 3217 mdp->tsu_addr = devm_ioremap_resource(&pdev->dev, rtsu);
3218 if (IS_ERR(mdp->tsu_addr)) {
3219 ret = PTR_ERR(mdp->tsu_addr);
fc0c0900
SS		 3220 goto out_release;
3221 }
6743fe6d 3222 mdp->port = devno % 2;
f646968f 3223 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER;
6ba88021
YS		 3224 }
3225
150647fb
YS		 3226 /* initialize first or needed device */
3227 if (!devno || pd->needs_init) {
380af9e3
YS		 3228 if (mdp->cd->chip_reset)
3229 mdp->cd->chip_reset(ndev);
86a74ff2 3230
4986b996
YS		 3231 if (mdp->cd->tsu) {
3232 /* TSU init (Init only)*/
3233 sh_eth_tsu_init(mdp);
3234 }
86a74ff2
NI		 3235 }
3236
966d6dbb
HN		 3237 if (mdp->cd->rmiimode)
3238 sh_eth_write(ndev, 0x1, RMIIMODE);
3239
daacf03f
LP		 3240 /* MDIO bus init */
3241 ret = sh_mdio_init(mdp, pd);
3242 if (ret) {
b7ce520e
GU		 3243 if (ret != -EPROBE_DEFER)
3244 dev_err(&pdev->dev, "MDIO init failed: %d\n", ret);
daacf03f
LP		 3245 goto out_release;
3246 }
3247
3719109d
SS		 3248 netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64);
3249
86a74ff2
NI		 3250 /* network device register */
3251 ret = register_netdev(ndev);
3252 if (ret)
3719109d 3253 goto out_napi_del;
86a74ff2 3254
d8981d02
NS		 3255 if (mdp->cd->magic && mdp->clk)
3256 device_set_wakeup_capable(&pdev->dev, 1);
3257
25985edc 3258 /* print device information */
f75f14ec
SS		 3259 netdev_info(ndev, "Base address at 0x%x, %pM, IRQ %d.\n",
3260 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
86a74ff2 3261
b5893a08 3262 pm_runtime_put(&pdev->dev);
86a74ff2
NI		 3263 platform_set_drvdata(pdev, ndev);
3264
3265 return ret;
3266
3719109d
SS		 3267out_napi_del:
3268 netif_napi_del(&mdp->napi);
daacf03f 3269 sh_mdio_release(mdp);
3719109d 3270
86a74ff2
NI		 3271out_release:
3272 /* net_dev free */
3273 if (ndev)
3274 free_netdev(ndev);
3275
b5893a08
BD		 3276 pm_runtime_put(&pdev->dev);
3277 pm_runtime_disable(&pdev->dev);
86a74ff2
NI		 3278 return ret;
3279}
3280
3281static int sh_eth_drv_remove(struct platform_device *pdev)
3282{
3283 struct net_device *ndev = platform_get_drvdata(pdev);
3719109d 3284 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2 3285
86a74ff2 3286 unregister_netdev(ndev);
3719109d 3287 netif_napi_del(&mdp->napi);
daacf03f 3288 sh_mdio_release(mdp);
bcd5149d 3289 pm_runtime_disable(&pdev->dev);
86a74ff2 3290 free_netdev(ndev);
86a74ff2
NI		 3291
3292 return 0;
3293}
3294
540ad1b8 3295#ifdef CONFIG_PM
b71af046 3296#ifdef CONFIG_PM_SLEEP
d8981d02
NS		 3297static int sh_eth_wol_setup(struct net_device *ndev)
3298{
3299 struct sh_eth_private *mdp = netdev_priv(ndev);
3300
3301 /* Only allow ECI interrupts */
3302 synchronize_irq(ndev->irq);
3303 napi_disable(&mdp->napi);
1a0bee6c 3304 sh_eth_write(ndev, EESIPR_ECIIP, EESIPR);
d8981d02
NS		 3305
3306 /* Enable MagicPacket */
5e2ed132 3307 sh_eth_modify(ndev, ECMR, ECMR_MPDE, ECMR_MPDE);
d8981d02
NS		 3308
3309 /* Increased clock usage so device won't be suspended */
3310 clk_enable(mdp->clk);
3311
3312 return enable_irq_wake(ndev->irq);
3313}
3314
3315static int sh_eth_wol_restore(struct net_device *ndev)
3316{
3317 struct sh_eth_private *mdp = netdev_priv(ndev);
3318 int ret;
3319
3320 napi_enable(&mdp->napi);
3321
3322 /* Disable MagicPacket */
3323 sh_eth_modify(ndev, ECMR, ECMR_MPDE, 0);
3324
3325 /* The device needs to be reset to restore MagicPacket logic
3326 * for next wakeup. If we close and open the device it will
3327 * both be reset and all registers restored. This is what
3328 * happens during suspend and resume without WoL enabled.
3329 */
3330 ret = sh_eth_close(ndev);
3331 if (ret < 0)
3332 return ret;
3333 ret = sh_eth_open(ndev);
3334 if (ret < 0)
3335 return ret;
3336
3337 /* Restore clock usage count */
3338 clk_disable(mdp->clk);
3339
3340 return disable_irq_wake(ndev->irq);
3341}
3342
b71af046
MU		 3343static int sh_eth_suspend(struct device *dev)
3344{
3345 struct net_device *ndev = dev_get_drvdata(dev);
d8981d02 3346 struct sh_eth_private *mdp = netdev_priv(ndev);
b71af046
MU		 3347 int ret = 0;
3348
d8981d02
NS		 3349 if (!netif_running(ndev))
3350 return 0;
3351
3352 netif_device_detach(ndev);
3353
3354 if (mdp->wol_enabled)
3355 ret = sh_eth_wol_setup(ndev);
3356 else
b71af046 3357 ret = sh_eth_close(ndev);
b71af046
MU		 3358
3359 return ret;
3360}
3361
3362static int sh_eth_resume(struct device *dev)
3363{
3364 struct net_device *ndev = dev_get_drvdata(dev);
d8981d02 3365 struct sh_eth_private *mdp = netdev_priv(ndev);
b71af046
MU		 3366 int ret = 0;
3367
d8981d02
NS		 3368 if (!netif_running(ndev))
3369 return 0;
3370
3371 if (mdp->wol_enabled)
3372 ret = sh_eth_wol_restore(ndev);
3373 else
b71af046 3374 ret = sh_eth_open(ndev);
d8981d02
NS		 3375
3376 if (ret < 0)
3377 return ret;
3378
3379 netif_device_attach(ndev);
b71af046
MU		 3380
3381 return ret;
3382}
3383#endif
3384
bcd5149d
MD		 3385static int sh_eth_runtime_nop(struct device *dev)
3386{
128296fc 3387 /* Runtime PM callback shared between ->runtime_suspend()
bcd5149d
MD		 3388 * and ->runtime_resume(). Simply returns success.
3389 *
3390 * This driver re-initializes all registers after
3391 * pm_runtime_get_sync() anyway so there is no need
3392 * to save and restore registers here.
3393 */
3394 return 0;
3395}
3396
540ad1b8 3397static const struct dev_pm_ops sh_eth_dev_pm_ops = {
b71af046 3398 SET_SYSTEM_SLEEP_PM_OPS(sh_eth_suspend, sh_eth_resume)
e7d7e898 3399 SET_RUNTIME_PM_OPS(sh_eth_runtime_nop, sh_eth_runtime_nop, NULL)
bcd5149d 3400};
540ad1b8
NI		 3401#define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
3402#else
3403#define SH_ETH_PM_OPS NULL
3404#endif
bcd5149d 3405
afe391ad 3406static struct platform_device_id sh_eth_id_table[] = {
c18a79ab 3407 { "sh7619-ether", (kernel_ulong_t)&sh7619_data },
7bbe150d 3408 { "sh771x-ether", (kernel_ulong_t)&sh771x_data },
9c3beaab 3409 { "sh7724-ether", (kernel_ulong_t)&sh7724_data },
f5d12767 3410 { "sh7734-gether", (kernel_ulong_t)&sh7734_data },
24549e2a
SS		 3411 { "sh7757-ether", (kernel_ulong_t)&sh7757_data },
3412 { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga },
f5d12767 3413 { "sh7763-gether", (kernel_ulong_t)&sh7763_data },
afe391ad
SS		 3414 { }
3415};
3416MODULE_DEVICE_TABLE(platform, sh_eth_id_table);
3417
86a74ff2
NI		 3418static struct platform_driver sh_eth_driver = {
3419 .probe = sh_eth_drv_probe,
3420 .remove = sh_eth_drv_remove,
afe391ad 3421 .id_table = sh_eth_id_table,
86a74ff2
NI		 3422 .driver = {
3423 .name = CARDNAME,
540ad1b8 3424 .pm = SH_ETH_PM_OPS,
b356e978 3425 .of_match_table = of_match_ptr(sh_eth_match_table),
86a74ff2
NI		 3426 },
3427};
3428
db62f684 3429module_platform_driver(sh_eth_driver);
86a74ff2
NI		 3430
3431MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
3432MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
3433MODULE_LICENSE("GPL v2");
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