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sh_eth: define/use EESR_RX_CHECK macro
[mirror_ubuntu-jammy-kernel.git] / drivers / net / ethernet / renesas / sh_eth.c
CommitLineData
86a74ff2
NI		 1/*
2 * SuperH Ethernet device driver
3 *
f0e81fec 4 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu
a3f109bd
SS		 5 * Copyright (C) 2008-2013 Renesas Solutions Corp.
6 * Copyright (C) 2013 Cogent Embedded, Inc.
86a74ff2
NI		 7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 * You should have received a copy of the GNU General Public License along with
17 * this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * The full GNU General Public License is included in this distribution in
21 * the file called "COPYING".
22 */
23
86a74ff2 24#include <linux/init.h>
0654011d
YS		 25#include <linux/module.h>
26#include <linux/kernel.h>
27#include <linux/spinlock.h>
6a27cded 28#include <linux/interrupt.h>
86a74ff2
NI		 29#include <linux/dma-mapping.h>
30#include <linux/etherdevice.h>
31#include <linux/delay.h>
32#include <linux/platform_device.h>
33#include <linux/mdio-bitbang.h>
34#include <linux/netdevice.h>
35#include <linux/phy.h>
36#include <linux/cache.h>
37#include <linux/io.h>
bcd5149d 38#include <linux/pm_runtime.h>
5a0e3ad6 39#include <linux/slab.h>
dc19e4e5 40#include <linux/ethtool.h>
fdb37a7f 41#include <linux/if_vlan.h>
f0e81fec 42#include <linux/clk.h>
d4fa0e35 43#include <linux/sh_eth.h>
86a74ff2
NI		 44
45#include "sh_eth.h"
46
dc19e4e5
NI		 47#define SH_ETH_DEF_MSG_ENABLE \
48 (NETIF_MSG_LINK | \
49 NETIF_MSG_TIMER | \
50 NETIF_MSG_RX_ERR| \
51 NETIF_MSG_TX_ERR)
52
c0013f6f
SS		 53static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
54 [EDSR] = 0x0000,
55 [EDMR] = 0x0400,
56 [EDTRR] = 0x0408,
57 [EDRRR] = 0x0410,
58 [EESR] = 0x0428,
59 [EESIPR] = 0x0430,
60 [TDLAR] = 0x0010,
61 [TDFAR] = 0x0014,
62 [TDFXR] = 0x0018,
63 [TDFFR] = 0x001c,
64 [RDLAR] = 0x0030,
65 [RDFAR] = 0x0034,
66 [RDFXR] = 0x0038,
67 [RDFFR] = 0x003c,
68 [TRSCER] = 0x0438,
69 [RMFCR] = 0x0440,
70 [TFTR] = 0x0448,
71 [FDR] = 0x0450,
72 [RMCR] = 0x0458,
73 [RPADIR] = 0x0460,
74 [FCFTR] = 0x0468,
75 [CSMR] = 0x04E4,
76
77 [ECMR] = 0x0500,
78 [ECSR] = 0x0510,
79 [ECSIPR] = 0x0518,
80 [PIR] = 0x0520,
81 [PSR] = 0x0528,
82 [PIPR] = 0x052c,
83 [RFLR] = 0x0508,
84 [APR] = 0x0554,
85 [MPR] = 0x0558,
86 [PFTCR] = 0x055c,
87 [PFRCR] = 0x0560,
88 [TPAUSER] = 0x0564,
89 [GECMR] = 0x05b0,
90 [BCULR] = 0x05b4,
91 [MAHR] = 0x05c0,
92 [MALR] = 0x05c8,
93 [TROCR] = 0x0700,
94 [CDCR] = 0x0708,
95 [LCCR] = 0x0710,
96 [CEFCR] = 0x0740,
97 [FRECR] = 0x0748,
98 [TSFRCR] = 0x0750,
99 [TLFRCR] = 0x0758,
100 [RFCR] = 0x0760,
101 [CERCR] = 0x0768,
102 [CEECR] = 0x0770,
103 [MAFCR] = 0x0778,
104 [RMII_MII] = 0x0790,
105
106 [ARSTR] = 0x0000,
107 [TSU_CTRST] = 0x0004,
108 [TSU_FWEN0] = 0x0010,
109 [TSU_FWEN1] = 0x0014,
110 [TSU_FCM] = 0x0018,
111 [TSU_BSYSL0] = 0x0020,
112 [TSU_BSYSL1] = 0x0024,
113 [TSU_PRISL0] = 0x0028,
114 [TSU_PRISL1] = 0x002c,
115 [TSU_FWSL0] = 0x0030,
116 [TSU_FWSL1] = 0x0034,
117 [TSU_FWSLC] = 0x0038,
118 [TSU_QTAG0] = 0x0040,
119 [TSU_QTAG1] = 0x0044,
120 [TSU_FWSR] = 0x0050,
121 [TSU_FWINMK] = 0x0054,
122 [TSU_ADQT0] = 0x0048,
123 [TSU_ADQT1] = 0x004c,
124 [TSU_VTAG0] = 0x0058,
125 [TSU_VTAG1] = 0x005c,
126 [TSU_ADSBSY] = 0x0060,
127 [TSU_TEN] = 0x0064,
128 [TSU_POST1] = 0x0070,
129 [TSU_POST2] = 0x0074,
130 [TSU_POST3] = 0x0078,
131 [TSU_POST4] = 0x007c,
132 [TSU_ADRH0] = 0x0100,
133 [TSU_ADRL0] = 0x0104,
134 [TSU_ADRH31] = 0x01f8,
135 [TSU_ADRL31] = 0x01fc,
136
137 [TXNLCR0] = 0x0080,
138 [TXALCR0] = 0x0084,
139 [RXNLCR0] = 0x0088,
140 [RXALCR0] = 0x008c,
141 [FWNLCR0] = 0x0090,
142 [FWALCR0] = 0x0094,
143 [TXNLCR1] = 0x00a0,
144 [TXALCR1] = 0x00a0,
145 [RXNLCR1] = 0x00a8,
146 [RXALCR1] = 0x00ac,
147 [FWNLCR1] = 0x00b0,
148 [FWALCR1] = 0x00b4,
149};
150
a3f109bd
SS		 151static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
152 [ECMR] = 0x0300,
153 [RFLR] = 0x0308,
154 [ECSR] = 0x0310,
155 [ECSIPR] = 0x0318,
156 [PIR] = 0x0320,
157 [PSR] = 0x0328,
158 [RDMLR] = 0x0340,
159 [IPGR] = 0x0350,
160 [APR] = 0x0354,
161 [MPR] = 0x0358,
162 [RFCF] = 0x0360,
163 [TPAUSER] = 0x0364,
164 [TPAUSECR] = 0x0368,
165 [MAHR] = 0x03c0,
166 [MALR] = 0x03c8,
167 [TROCR] = 0x03d0,
168 [CDCR] = 0x03d4,
169 [LCCR] = 0x03d8,
170 [CNDCR] = 0x03dc,
171 [CEFCR] = 0x03e4,
172 [FRECR] = 0x03e8,
173 [TSFRCR] = 0x03ec,
174 [TLFRCR] = 0x03f0,
175 [RFCR] = 0x03f4,
176 [MAFCR] = 0x03f8,
177
178 [EDMR] = 0x0200,
179 [EDTRR] = 0x0208,
180 [EDRRR] = 0x0210,
181 [TDLAR] = 0x0218,
182 [RDLAR] = 0x0220,
183 [EESR] = 0x0228,
184 [EESIPR] = 0x0230,
185 [TRSCER] = 0x0238,
186 [RMFCR] = 0x0240,
187 [TFTR] = 0x0248,
188 [FDR] = 0x0250,
189 [RMCR] = 0x0258,
190 [TFUCR] = 0x0264,
191 [RFOCR] = 0x0268,
192 [FCFTR] = 0x0270,
193 [TRIMD] = 0x027c,
194};
195
c0013f6f
SS		 196static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
197 [ECMR] = 0x0100,
198 [RFLR] = 0x0108,
199 [ECSR] = 0x0110,
200 [ECSIPR] = 0x0118,
201 [PIR] = 0x0120,
202 [PSR] = 0x0128,
203 [RDMLR] = 0x0140,
204 [IPGR] = 0x0150,
205 [APR] = 0x0154,
206 [MPR] = 0x0158,
207 [TPAUSER] = 0x0164,
208 [RFCF] = 0x0160,
209 [TPAUSECR] = 0x0168,
210 [BCFRR] = 0x016c,
211 [MAHR] = 0x01c0,
212 [MALR] = 0x01c8,
213 [TROCR] = 0x01d0,
214 [CDCR] = 0x01d4,
215 [LCCR] = 0x01d8,
216 [CNDCR] = 0x01dc,
217 [CEFCR] = 0x01e4,
218 [FRECR] = 0x01e8,
219 [TSFRCR] = 0x01ec,
220 [TLFRCR] = 0x01f0,
221 [RFCR] = 0x01f4,
222 [MAFCR] = 0x01f8,
223 [RTRATE] = 0x01fc,
224
225 [EDMR] = 0x0000,
226 [EDTRR] = 0x0008,
227 [EDRRR] = 0x0010,
228 [TDLAR] = 0x0018,
229 [RDLAR] = 0x0020,
230 [EESR] = 0x0028,
231 [EESIPR] = 0x0030,
232 [TRSCER] = 0x0038,
233 [RMFCR] = 0x0040,
234 [TFTR] = 0x0048,
235 [FDR] = 0x0050,
236 [RMCR] = 0x0058,
237 [TFUCR] = 0x0064,
238 [RFOCR] = 0x0068,
239 [FCFTR] = 0x0070,
240 [RPADIR] = 0x0078,
241 [TRIMD] = 0x007c,
242 [RBWAR] = 0x00c8,
243 [RDFAR] = 0x00cc,
244 [TBRAR] = 0x00d4,
245 [TDFAR] = 0x00d8,
246};
247
248static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
249 [ECMR] = 0x0160,
250 [ECSR] = 0x0164,
251 [ECSIPR] = 0x0168,
252 [PIR] = 0x016c,
253 [MAHR] = 0x0170,
254 [MALR] = 0x0174,
255 [RFLR] = 0x0178,
256 [PSR] = 0x017c,
257 [TROCR] = 0x0180,
258 [CDCR] = 0x0184,
259 [LCCR] = 0x0188,
260 [CNDCR] = 0x018c,
261 [CEFCR] = 0x0194,
262 [FRECR] = 0x0198,
263 [TSFRCR] = 0x019c,
264 [TLFRCR] = 0x01a0,
265 [RFCR] = 0x01a4,
266 [MAFCR] = 0x01a8,
267 [IPGR] = 0x01b4,
268 [APR] = 0x01b8,
269 [MPR] = 0x01bc,
270 [TPAUSER] = 0x01c4,
271 [BCFR] = 0x01cc,
272
273 [ARSTR] = 0x0000,
274 [TSU_CTRST] = 0x0004,
275 [TSU_FWEN0] = 0x0010,
276 [TSU_FWEN1] = 0x0014,
277 [TSU_FCM] = 0x0018,
278 [TSU_BSYSL0] = 0x0020,
279 [TSU_BSYSL1] = 0x0024,
280 [TSU_PRISL0] = 0x0028,
281 [TSU_PRISL1] = 0x002c,
282 [TSU_FWSL0] = 0x0030,
283 [TSU_FWSL1] = 0x0034,
284 [TSU_FWSLC] = 0x0038,
285 [TSU_QTAGM0] = 0x0040,
286 [TSU_QTAGM1] = 0x0044,
287 [TSU_ADQT0] = 0x0048,
288 [TSU_ADQT1] = 0x004c,
289 [TSU_FWSR] = 0x0050,
290 [TSU_FWINMK] = 0x0054,
291 [TSU_ADSBSY] = 0x0060,
292 [TSU_TEN] = 0x0064,
293 [TSU_POST1] = 0x0070,
294 [TSU_POST2] = 0x0074,
295 [TSU_POST3] = 0x0078,
296 [TSU_POST4] = 0x007c,
297
298 [TXNLCR0] = 0x0080,
299 [TXALCR0] = 0x0084,
300 [RXNLCR0] = 0x0088,
301 [RXALCR0] = 0x008c,
302 [FWNLCR0] = 0x0090,
303 [FWALCR0] = 0x0094,
304 [TXNLCR1] = 0x00a0,
305 [TXALCR1] = 0x00a0,
306 [RXNLCR1] = 0x00a8,
307 [RXALCR1] = 0x00ac,
308 [FWNLCR1] = 0x00b0,
309 [FWALCR1] = 0x00b4,
310
311 [TSU_ADRH0] = 0x0100,
312 [TSU_ADRL0] = 0x0104,
313 [TSU_ADRL31] = 0x01fc,
314};
315
dabdde9e
NI		 316static int sh_eth_is_gether(struct sh_eth_private *mdp)
317{
318 if (mdp->reg_offset == sh_eth_offset_gigabit)
319 return 1;
320 else
321 return 0;
322}
323
8e994402 324static void sh_eth_select_mii(struct net_device *ndev)
5e7a76be
NI		 325{
326 u32 value = 0x0;
327 struct sh_eth_private *mdp = netdev_priv(ndev);
328
329 switch (mdp->phy_interface) {
330 case PHY_INTERFACE_MODE_GMII:
331 value = 0x2;
332 break;
333 case PHY_INTERFACE_MODE_MII:
334 value = 0x1;
335 break;
336 case PHY_INTERFACE_MODE_RMII:
337 value = 0x0;
338 break;
339 default:
340 pr_warn("PHY interface mode was not setup. Set to MII.\n");
341 value = 0x1;
342 break;
343 }
344
345 sh_eth_write(ndev, value, RMII_MII);
346}
5e7a76be 347
8e994402 348static void sh_eth_set_duplex(struct net_device *ndev)
65ac8851
YS		 349{
350 struct sh_eth_private *mdp = netdev_priv(ndev);
65ac8851
YS		 351
352 if (mdp->duplex) /* Full */
4a55530f 353 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
65ac8851 354 else /* Half */
4a55530f 355 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
65ac8851
YS		 356}
357
04b0ed2a 358/* There is CPU dependent code */
589ebdef 359static void sh_eth_set_rate_r8a777x(struct net_device *ndev)
65ac8851
YS		 360{
361 struct sh_eth_private *mdp = netdev_priv(ndev);
d0418bb7 362
a3f109bd
SS		 363 switch (mdp->speed) {
364 case 10: /* 10BASE */
365 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_ELB, ECMR);
366 break;
367 case 100:/* 100BASE */
368 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_ELB, ECMR);
369 break;
370 default:
371 break;
372 }
373}
374
674853b2 375/* R8A7778/9 */
589ebdef 376static struct sh_eth_cpu_data r8a777x_data = {
a3f109bd 377 .set_duplex = sh_eth_set_duplex,
589ebdef 378 .set_rate = sh_eth_set_rate_r8a777x,
a3f109bd
SS		 379
380 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
381 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
382 .eesipr_value = 0x01ff009f,
383
384 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
385 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE |
386 EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI,
387 .tx_error_check = EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE,
388
389 .apr = 1,
390 .mpr = 1,
391 .tpauser = 1,
392 .hw_swap = 1,
393};
a3f109bd 394
9c3beaab 395static void sh_eth_set_rate_sh7724(struct net_device *ndev)
a3f109bd
SS		 396{
397 struct sh_eth_private *mdp = netdev_priv(ndev);
65ac8851
YS		 398
399 switch (mdp->speed) {
400 case 10: /* 10BASE */
a3f109bd 401 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_RTM, ECMR);
65ac8851
YS		 402 break;
403 case 100:/* 100BASE */
a3f109bd 404 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_RTM, ECMR);
65ac8851
YS		 405 break;
406 default:
407 break;
408 }
409}
410
411/* SH7724 */
9c3beaab 412static struct sh_eth_cpu_data sh7724_data = {
65ac8851 413 .set_duplex = sh_eth_set_duplex,
9c3beaab 414 .set_rate = sh_eth_set_rate_sh7724,
65ac8851
YS		 415
416 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
417 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
418 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x01ff009f,
419
420 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
421 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE |
422 EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI,
423 .tx_error_check = EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE,
424
425 .apr = 1,
426 .mpr = 1,
427 .tpauser = 1,
428 .hw_swap = 1,
503914cf
MD		 429 .rpadir = 1,
430 .rpadir_value = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
65ac8851 431};
5cee1d37 432
24549e2a 433static void sh_eth_set_rate_sh7757(struct net_device *ndev)
f29a3d04
YS		 434{
435 struct sh_eth_private *mdp = netdev_priv(ndev);
f29a3d04
YS		 436
437 switch (mdp->speed) {
438 case 10: /* 10BASE */
4a55530f 439 sh_eth_write(ndev, 0, RTRATE);
f29a3d04
YS		 440 break;
441 case 100:/* 100BASE */
4a55530f 442 sh_eth_write(ndev, 1, RTRATE);
f29a3d04
YS		 443 break;
444 default:
445 break;
446 }
447}
448
449/* SH7757 */
24549e2a
SS		 450static struct sh_eth_cpu_data sh7757_data = {
451 .set_duplex = sh_eth_set_duplex,
452 .set_rate = sh_eth_set_rate_sh7757,
f29a3d04
YS		 453
454 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
455 .rmcr_value = 0x00000001,
456
457 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
458 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE |
459 EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI,
460 .tx_error_check = EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE,
461
5b3dfd13 462 .irq_flags = IRQF_SHARED,
f29a3d04
YS		 463 .apr = 1,
464 .mpr = 1,
465 .tpauser = 1,
466 .hw_swap = 1,
467 .no_ade = 1,
2e98e797
YS		 468 .rpadir = 1,
469 .rpadir_value = 2 << 16,
f29a3d04 470};
65ac8851 471
e403d295 472#define SH_GIGA_ETH_BASE 0xfee00000UL
8fcd4961
YS		 473#define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
474#define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
475static void sh_eth_chip_reset_giga(struct net_device *ndev)
476{
477 int i;
478 unsigned long mahr[2], malr[2];
479
480 /* save MAHR and MALR */
481 for (i = 0; i < 2; i++) {
ae70644d
YS		 482 malr[i] = ioread32((void *)GIGA_MALR(i));
483 mahr[i] = ioread32((void *)GIGA_MAHR(i));
8fcd4961
YS		 484 }
485
486 /* reset device */
ae70644d 487 iowrite32(ARSTR_ARSTR, (void *)(SH_GIGA_ETH_BASE + 0x1800));
8fcd4961
YS		 488 mdelay(1);
489
490 /* restore MAHR and MALR */
491 for (i = 0; i < 2; i++) {
ae70644d
YS		 492 iowrite32(malr[i], (void *)GIGA_MALR(i));
493 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
8fcd4961
YS		 494 }
495}
496
8fcd4961
YS		 497static void sh_eth_set_rate_giga(struct net_device *ndev)
498{
499 struct sh_eth_private *mdp = netdev_priv(ndev);
500
501 switch (mdp->speed) {
502 case 10: /* 10BASE */
503 sh_eth_write(ndev, 0x00000000, GECMR);
504 break;
505 case 100:/* 100BASE */
506 sh_eth_write(ndev, 0x00000010, GECMR);
507 break;
508 case 1000: /* 1000BASE */
509 sh_eth_write(ndev, 0x00000020, GECMR);
510 break;
511 default:
512 break;
513 }
514}
515
516/* SH7757(GETHERC) */
24549e2a 517static struct sh_eth_cpu_data sh7757_data_giga = {
8fcd4961 518 .chip_reset = sh_eth_chip_reset_giga,
04b0ed2a 519 .set_duplex = sh_eth_set_duplex,
8fcd4961
YS		 520 .set_rate = sh_eth_set_rate_giga,
521
522 .ecsr_value = ECSR_ICD | ECSR_MPD,
523 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
524 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
525
526 .tx_check = EESR_TC1 | EESR_FTC,
527 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \
528 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \
529 EESR_ECI,
530 .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \
531 EESR_TFE,
532 .fdr_value = 0x0000072f,
533 .rmcr_value = 0x00000001,
534
5b3dfd13 535 .irq_flags = IRQF_SHARED,
8fcd4961
YS		 536 .apr = 1,
537 .mpr = 1,
538 .tpauser = 1,
539 .bculr = 1,
540 .hw_swap = 1,
541 .rpadir = 1,
542 .rpadir_value = 2 << 16,
543 .no_trimd = 1,
544 .no_ade = 1,
3acbc971 545 .tsu = 1,
8fcd4961
YS		 546};
547
380af9e3
YS		 548static void sh_eth_chip_reset(struct net_device *ndev)
549{
4986b996
YS		 550 struct sh_eth_private *mdp = netdev_priv(ndev);
551
380af9e3 552 /* reset device */
4986b996 553 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
380af9e3
YS		 554 mdelay(1);
555}
556
f5d12767 557static void sh_eth_set_rate_gether(struct net_device *ndev)
380af9e3
YS		 558{
559 struct sh_eth_private *mdp = netdev_priv(ndev);
380af9e3
YS		 560
561 switch (mdp->speed) {
562 case 10: /* 10BASE */
4a55530f 563 sh_eth_write(ndev, GECMR_10, GECMR);
380af9e3
YS		 564 break;
565 case 100:/* 100BASE */
4a55530f 566 sh_eth_write(ndev, GECMR_100, GECMR);
380af9e3
YS		 567 break;
568 case 1000: /* 1000BASE */
4a55530f 569 sh_eth_write(ndev, GECMR_1000, GECMR);
380af9e3
YS		 570 break;
571 default:
572 break;
573 }
574}
575
f5d12767
SS		 576/* SH7734 */
577static struct sh_eth_cpu_data sh7734_data = {
380af9e3
YS		 578 .chip_reset = sh_eth_chip_reset,
579 .set_duplex = sh_eth_set_duplex,
f5d12767
SS		 580 .set_rate = sh_eth_set_rate_gether,
581
582 .ecsr_value = ECSR_ICD | ECSR_MPD,
583 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
584 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
585
586 .tx_check = EESR_TC1 | EESR_FTC,
587 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \
588 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \
589 EESR_ECI,
590 .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \
591 EESR_TFE,
592
593 .apr = 1,
594 .mpr = 1,
595 .tpauser = 1,
596 .bculr = 1,
597 .hw_swap = 1,
598 .no_trimd = 1,
599 .no_ade = 1,
600 .tsu = 1,
601 .hw_crc = 1,
602 .select_mii = 1,
603};
604
605/* SH7763 */
606static struct sh_eth_cpu_data sh7763_data = {
607 .chip_reset = sh_eth_chip_reset,
608 .set_duplex = sh_eth_set_duplex,
609 .set_rate = sh_eth_set_rate_gether,
380af9e3
YS		 610
611 .ecsr_value = ECSR_ICD | ECSR_MPD,
612 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
613 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
614
615 .tx_check = EESR_TC1 | EESR_FTC,
616 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \
617 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \
618 EESR_ECI,
619 .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \
620 EESR_TFE,
621
622 .apr = 1,
623 .mpr = 1,
624 .tpauser = 1,
625 .bculr = 1,
626 .hw_swap = 1,
380af9e3
YS		 627 .no_trimd = 1,
628 .no_ade = 1,
4986b996 629 .tsu = 1,
5b3dfd13 630 .irq_flags = IRQF_SHARED,
380af9e3
YS		 631};
632
e5c9b4cd 633static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
73a0d907
YS		 634{
635 struct sh_eth_private *mdp = netdev_priv(ndev);
73a0d907
YS		 636
637 /* reset device */
638 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
639 mdelay(1);
640
5e7a76be 641 sh_eth_select_mii(ndev);
73a0d907
YS		 642}
643
73a0d907 644/* R8A7740 */
e5c9b4cd
SS		 645static struct sh_eth_cpu_data r8a7740_data = {
646 .chip_reset = sh_eth_chip_reset_r8a7740,
73a0d907 647 .set_duplex = sh_eth_set_duplex,
e5c9b4cd 648 .set_rate = sh_eth_set_rate_gether,
73a0d907
YS		 649
650 .ecsr_value = ECSR_ICD | ECSR_MPD,
651 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
652 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
653
654 .tx_check = EESR_TC1 | EESR_FTC,
655 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \
656 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \
657 EESR_ECI,
658 .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \
659 EESR_TFE,
660
661 .apr = 1,
662 .mpr = 1,
663 .tpauser = 1,
664 .bculr = 1,
665 .hw_swap = 1,
666 .no_trimd = 1,
667 .no_ade = 1,
668 .tsu = 1,
5e7a76be 669 .select_mii = 1,
73a0d907
YS		 670};
671
c18a79ab 672static struct sh_eth_cpu_data sh7619_data = {
380af9e3
YS		 673 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
674
675 .apr = 1,
676 .mpr = 1,
677 .tpauser = 1,
678 .hw_swap = 1,
679};
7bbe150d
SS		 680
681static struct sh_eth_cpu_data sh771x_data = {
380af9e3 682 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
4986b996 683 .tsu = 1,
380af9e3 684};
380af9e3
YS		 685
686static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
687{
688 if (!cd->ecsr_value)
689 cd->ecsr_value = DEFAULT_ECSR_INIT;
690
691 if (!cd->ecsipr_value)
692 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
693
694 if (!cd->fcftr_value)
695 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF | \
696 DEFAULT_FIFO_F_D_RFD;
697
698 if (!cd->fdr_value)
699 cd->fdr_value = DEFAULT_FDR_INIT;
700
701 if (!cd->rmcr_value)
702 cd->rmcr_value = DEFAULT_RMCR_VALUE;
703
704 if (!cd->tx_check)
705 cd->tx_check = DEFAULT_TX_CHECK;
706
707 if (!cd->eesr_err_check)
708 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
709
710 if (!cd->tx_error_check)
711 cd->tx_error_check = DEFAULT_TX_ERROR_CHECK;
712}
713
5cee1d37
NI		 714static int sh_eth_check_reset(struct net_device *ndev)
715{
716 int ret = 0;
717 int cnt = 100;
718
719 while (cnt > 0) {
720 if (!(sh_eth_read(ndev, EDMR) & 0x3))
721 break;
722 mdelay(1);
723 cnt--;
724 }
9f8c4265
SS		 725 if (cnt <= 0) {
726 pr_err("Device reset failed\n");
5cee1d37
NI		 727 ret = -ETIMEDOUT;
728 }
729 return ret;
380af9e3 730}
dabdde9e
NI		 731
732static int sh_eth_reset(struct net_device *ndev)
733{
734 struct sh_eth_private *mdp = netdev_priv(ndev);
735 int ret = 0;
736
737 if (sh_eth_is_gether(mdp)) {
738 sh_eth_write(ndev, EDSR_ENALL, EDSR);
739 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER,
740 EDMR);
741
742 ret = sh_eth_check_reset(ndev);
743 if (ret)
744 goto out;
745
746 /* Table Init */
747 sh_eth_write(ndev, 0x0, TDLAR);
748 sh_eth_write(ndev, 0x0, TDFAR);
749 sh_eth_write(ndev, 0x0, TDFXR);
750 sh_eth_write(ndev, 0x0, TDFFR);
751 sh_eth_write(ndev, 0x0, RDLAR);
752 sh_eth_write(ndev, 0x0, RDFAR);
753 sh_eth_write(ndev, 0x0, RDFXR);
754 sh_eth_write(ndev, 0x0, RDFFR);
755
756 /* Reset HW CRC register */
757 if (mdp->cd->hw_crc)
758 sh_eth_write(ndev, 0x0, CSMR);
759
760 /* Select MII mode */
761 if (mdp->cd->select_mii)
762 sh_eth_select_mii(ndev);
763 } else {
764 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER,
765 EDMR);
766 mdelay(3);
767 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER,
768 EDMR);
769 }
770
771out:
772 return ret;
773}
380af9e3 774
73a0d907 775#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
380af9e3
YS		 776static void sh_eth_set_receive_align(struct sk_buff *skb)
777{
778 int reserve;
779
780 reserve = SH4_SKB_RX_ALIGN - ((u32)skb->data & (SH4_SKB_RX_ALIGN - 1));
781 if (reserve)
782 skb_reserve(skb, reserve);
783}
784#else
785static void sh_eth_set_receive_align(struct sk_buff *skb)
786{
787 skb_reserve(skb, SH2_SH3_SKB_RX_ALIGN);
788}
789#endif
790
791
71557a37
YS		 792/* CPU <-> EDMAC endian convert */
793static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x)
794{
795 switch (mdp->edmac_endian) {
796 case EDMAC_LITTLE_ENDIAN:
797 return cpu_to_le32(x);
798 case EDMAC_BIG_ENDIAN:
799 return cpu_to_be32(x);
800 }
801 return x;
802}
803
804static inline __u32 edmac_to_cpu(struct sh_eth_private *mdp, u32 x)
805{
806 switch (mdp->edmac_endian) {
807 case EDMAC_LITTLE_ENDIAN:
808 return le32_to_cpu(x);
809 case EDMAC_BIG_ENDIAN:
810 return be32_to_cpu(x);
811 }
812 return x;
813}
814
86a74ff2
NI		 815/*
816 * Program the hardware MAC address from dev->dev_addr.
817 */
818static void update_mac_address(struct net_device *ndev)
819{
4a55530f
YS		 820 sh_eth_write(ndev,
821 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
822 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
823 sh_eth_write(ndev,
824 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
86a74ff2
NI		 825}
826
827/*
828 * Get MAC address from SuperH MAC address register
829 *
830 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
831 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
832 * When you want use this device, you must set MAC address in bootloader.
833 *
834 */
748031f9 835static void read_mac_address(struct net_device *ndev, unsigned char *mac)
86a74ff2 836{
748031f9
MD		 837 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
838 memcpy(ndev->dev_addr, mac, 6);
839 } else {
4a55530f
YS		 840 ndev->dev_addr[0] = (sh_eth_read(ndev, MAHR) >> 24);
841 ndev->dev_addr[1] = (sh_eth_read(ndev, MAHR) >> 16) & 0xFF;
842 ndev->dev_addr[2] = (sh_eth_read(ndev, MAHR) >> 8) & 0xFF;
843 ndev->dev_addr[3] = (sh_eth_read(ndev, MAHR) & 0xFF);
844 ndev->dev_addr[4] = (sh_eth_read(ndev, MALR) >> 8) & 0xFF;
845 ndev->dev_addr[5] = (sh_eth_read(ndev, MALR) & 0xFF);
748031f9 846 }
86a74ff2
NI		 847}
848
c5ed5368
YS		 849static unsigned long sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
850{
851 if (sh_eth_is_gether(mdp))
852 return EDTRR_TRNS_GETHER;
853 else
854 return EDTRR_TRNS_ETHER;
855}
856
86a74ff2 857struct bb_info {
ae70644d 858 void (*set_gate)(void *addr);
86a74ff2 859 struct mdiobb_ctrl ctrl;
ae70644d 860 void *addr;
86a74ff2
NI		 861 u32 mmd_msk;/* MMD */
862 u32 mdo_msk;
863 u32 mdi_msk;
864 u32 mdc_msk;
865};
866
867/* PHY bit set */
ae70644d 868static void bb_set(void *addr, u32 msk)
86a74ff2 869{
ae70644d 870 iowrite32(ioread32(addr) | msk, addr);
86a74ff2
NI		 871}
872
873/* PHY bit clear */
ae70644d 874static void bb_clr(void *addr, u32 msk)
86a74ff2 875{
ae70644d 876 iowrite32((ioread32(addr) & ~msk), addr);
86a74ff2
NI		 877}
878
879/* PHY bit read */
ae70644d 880static int bb_read(void *addr, u32 msk)
86a74ff2 881{
ae70644d 882 return (ioread32(addr) & msk) != 0;
86a74ff2
NI		 883}
884
885/* Data I/O pin control */
886static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
887{
888 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
b3017e6a
YS		 889
890 if (bitbang->set_gate)
891 bitbang->set_gate(bitbang->addr);
892
86a74ff2
NI		 893 if (bit)
894 bb_set(bitbang->addr, bitbang->mmd_msk);
895 else
896 bb_clr(bitbang->addr, bitbang->mmd_msk);
897}
898
899/* Set bit data*/
900static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
901{
902 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
903
b3017e6a
YS		 904 if (bitbang->set_gate)
905 bitbang->set_gate(bitbang->addr);
906
86a74ff2
NI		 907 if (bit)
908 bb_set(bitbang->addr, bitbang->mdo_msk);
909 else
910 bb_clr(bitbang->addr, bitbang->mdo_msk);
911}
912
913/* Get bit data*/
914static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
915{
916 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
b3017e6a
YS		 917
918 if (bitbang->set_gate)
919 bitbang->set_gate(bitbang->addr);
920
86a74ff2
NI		 921 return bb_read(bitbang->addr, bitbang->mdi_msk);
922}
923
924/* MDC pin control */
925static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
926{
927 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
928
b3017e6a
YS		 929 if (bitbang->set_gate)
930 bitbang->set_gate(bitbang->addr);
931
86a74ff2
NI		 932 if (bit)
933 bb_set(bitbang->addr, bitbang->mdc_msk);
934 else
935 bb_clr(bitbang->addr, bitbang->mdc_msk);
936}
937
938/* mdio bus control struct */
939static struct mdiobb_ops bb_ops = {
940 .owner = THIS_MODULE,
941 .set_mdc = sh_mdc_ctrl,
942 .set_mdio_dir = sh_mmd_ctrl,
943 .set_mdio_data = sh_set_mdio,
944 .get_mdio_data = sh_get_mdio,
945};
946
86a74ff2
NI		 947/* free skb and descriptor buffer */
948static void sh_eth_ring_free(struct net_device *ndev)
949{
950 struct sh_eth_private *mdp = netdev_priv(ndev);
951 int i;
952
953 /* Free Rx skb ringbuffer */
954 if (mdp->rx_skbuff) {
525b8075 955 for (i = 0; i < mdp->num_rx_ring; i++) {
86a74ff2
NI		 956 if (mdp->rx_skbuff[i])
957 dev_kfree_skb(mdp->rx_skbuff[i]);
958 }
959 }
960 kfree(mdp->rx_skbuff);
91c77550 961 mdp->rx_skbuff = NULL;
86a74ff2
NI		 962
963 /* Free Tx skb ringbuffer */
964 if (mdp->tx_skbuff) {
525b8075 965 for (i = 0; i < mdp->num_tx_ring; i++) {
86a74ff2
NI		 966 if (mdp->tx_skbuff[i])
967 dev_kfree_skb(mdp->tx_skbuff[i]);
968 }
969 }
970 kfree(mdp->tx_skbuff);
91c77550 971 mdp->tx_skbuff = NULL;
86a74ff2
NI		 972}
973
974/* format skb and descriptor buffer */
975static void sh_eth_ring_format(struct net_device *ndev)
976{
977 struct sh_eth_private *mdp = netdev_priv(ndev);
978 int i;
979 struct sk_buff *skb;
980 struct sh_eth_rxdesc *rxdesc = NULL;
981 struct sh_eth_txdesc *txdesc = NULL;
525b8075
YS		 982 int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
983 int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
86a74ff2
NI		 984
985 mdp->cur_rx = mdp->cur_tx = 0;
986 mdp->dirty_rx = mdp->dirty_tx = 0;
987
988 memset(mdp->rx_ring, 0, rx_ringsize);
989
990 /* build Rx ring buffer */
525b8075 991 for (i = 0; i < mdp->num_rx_ring; i++) {
86a74ff2
NI		 992 /* skb */
993 mdp->rx_skbuff[i] = NULL;
dae2e9f4 994 skb = netdev_alloc_skb(ndev, mdp->rx_buf_sz);
86a74ff2
NI		 995 mdp->rx_skbuff[i] = skb;
996 if (skb == NULL)
997 break;
bb7d92e3 998 dma_map_single(&ndev->dev, skb->data, mdp->rx_buf_sz,
e88aae7b 999 DMA_FROM_DEVICE);
380af9e3
YS		 1000 sh_eth_set_receive_align(skb);
1001
86a74ff2
NI		 1002 /* RX descriptor */
1003 rxdesc = &mdp->rx_ring[i];
0029d64a 1004 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
71557a37 1005 rxdesc->status = cpu_to_edmac(mdp, RD_RACT | RD_RFP);
86a74ff2
NI		 1006
1007 /* The size of the buffer is 16 byte boundary. */
0029d64a 1008 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
b0ca2a21
NI		 1009 /* Rx descriptor address set */
1010 if (i == 0) {
4a55530f 1011 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
c5ed5368
YS		 1012 if (sh_eth_is_gether(mdp))
1013 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
b0ca2a21 1014 }
86a74ff2
NI		 1015 }
1016
525b8075 1017 mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
86a74ff2
NI		 1018
1019 /* Mark the last entry as wrapping the ring. */
71557a37 1020 rxdesc->status |= cpu_to_edmac(mdp, RD_RDEL);
86a74ff2
NI		 1021
1022 memset(mdp->tx_ring, 0, tx_ringsize);
1023
1024 /* build Tx ring buffer */
525b8075 1025 for (i = 0; i < mdp->num_tx_ring; i++) {
86a74ff2
NI		 1026 mdp->tx_skbuff[i] = NULL;
1027 txdesc = &mdp->tx_ring[i];
71557a37 1028 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
86a74ff2 1029 txdesc->buffer_length = 0;
b0ca2a21 1030 if (i == 0) {
71557a37 1031 /* Tx descriptor address set */
4a55530f 1032 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
c5ed5368
YS		 1033 if (sh_eth_is_gether(mdp))
1034 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
b0ca2a21 1035 }
86a74ff2
NI		 1036 }
1037
71557a37 1038 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
86a74ff2
NI		 1039}
1040
1041/* Get skb and descriptor buffer */
1042static int sh_eth_ring_init(struct net_device *ndev)
1043{
1044 struct sh_eth_private *mdp = netdev_priv(ndev);
1045 int rx_ringsize, tx_ringsize, ret = 0;
1046
1047 /*
1048 * +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
1049 * card needs room to do 8 byte alignment, +2 so we can reserve
1050 * the first 2 bytes, and +16 gets room for the status word from the
1051 * card.
1052 */
1053 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
1054 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
503914cf
MD		 1055 if (mdp->cd->rpadir)
1056 mdp->rx_buf_sz += NET_IP_ALIGN;
86a74ff2
NI		 1057
1058 /* Allocate RX and TX skb rings */
b2adaca9
JP		 1059 mdp->rx_skbuff = kmalloc_array(mdp->num_rx_ring,
1060 sizeof(*mdp->rx_skbuff), GFP_KERNEL);
86a74ff2 1061 if (!mdp->rx_skbuff) {
86a74ff2
NI		 1062 ret = -ENOMEM;
1063 return ret;
1064 }
1065
b2adaca9
JP		 1066 mdp->tx_skbuff = kmalloc_array(mdp->num_tx_ring,
1067 sizeof(*mdp->tx_skbuff), GFP_KERNEL);
86a74ff2 1068 if (!mdp->tx_skbuff) {
86a74ff2
NI		 1069 ret = -ENOMEM;
1070 goto skb_ring_free;
1071 }
1072
1073 /* Allocate all Rx descriptors. */
525b8075 1074 rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
86a74ff2 1075 mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
d0320f75 1076 GFP_KERNEL);
86a74ff2 1077 if (!mdp->rx_ring) {
86a74ff2
NI		 1078 ret = -ENOMEM;
1079 goto desc_ring_free;
1080 }
1081
1082 mdp->dirty_rx = 0;
1083
1084 /* Allocate all Tx descriptors. */
525b8075 1085 tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
86a74ff2 1086 mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
d0320f75 1087 GFP_KERNEL);
86a74ff2 1088 if (!mdp->tx_ring) {
86a74ff2
NI		 1089 ret = -ENOMEM;
1090 goto desc_ring_free;
1091 }
1092 return ret;
1093
1094desc_ring_free:
1095 /* free DMA buffer */
1096 dma_free_coherent(NULL, rx_ringsize, mdp->rx_ring, mdp->rx_desc_dma);
1097
1098skb_ring_free:
1099 /* Free Rx and Tx skb ring buffer */
1100 sh_eth_ring_free(ndev);
91c77550
YS		 1101 mdp->tx_ring = NULL;
1102 mdp->rx_ring = NULL;
86a74ff2
NI		 1103
1104 return ret;
1105}
1106
91c77550
YS		 1107static void sh_eth_free_dma_buffer(struct sh_eth_private *mdp)
1108{
1109 int ringsize;
1110
1111 if (mdp->rx_ring) {
525b8075 1112 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
91c77550
YS		 1113 dma_free_coherent(NULL, ringsize, mdp->rx_ring,
1114 mdp->rx_desc_dma);
1115 mdp->rx_ring = NULL;
1116 }
1117
1118 if (mdp->tx_ring) {
525b8075 1119 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
91c77550
YS		 1120 dma_free_coherent(NULL, ringsize, mdp->tx_ring,
1121 mdp->tx_desc_dma);
1122 mdp->tx_ring = NULL;
1123 }
1124}
1125
525b8075 1126static int sh_eth_dev_init(struct net_device *ndev, bool start)
86a74ff2
NI		 1127{
1128 int ret = 0;
1129 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 1130 u32 val;
1131
1132 /* Soft Reset */
5cee1d37
NI		 1133 ret = sh_eth_reset(ndev);
1134 if (ret)
1135 goto out;
86a74ff2 1136
b0ca2a21
NI		 1137 /* Descriptor format */
1138 sh_eth_ring_format(ndev);
380af9e3 1139 if (mdp->cd->rpadir)
4a55530f 1140 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
86a74ff2
NI		 1141
1142 /* all sh_eth int mask */
4a55530f 1143 sh_eth_write(ndev, 0, EESIPR);
86a74ff2 1144
10b9194f 1145#if defined(__LITTLE_ENDIAN)
380af9e3 1146 if (mdp->cd->hw_swap)
4a55530f 1147 sh_eth_write(ndev, EDMR_EL, EDMR);
380af9e3 1148 else
b0ca2a21 1149#endif
4a55530f 1150 sh_eth_write(ndev, 0, EDMR);
86a74ff2 1151
b0ca2a21 1152 /* FIFO size set */
4a55530f
YS		 1153 sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
1154 sh_eth_write(ndev, 0, TFTR);
86a74ff2 1155
b0ca2a21 1156 /* Frame recv control */
4a55530f 1157 sh_eth_write(ndev, mdp->cd->rmcr_value, RMCR);
86a74ff2 1158
2ecbb783 1159 sh_eth_write(ndev, DESC_I_RINT8 | DESC_I_RINT5 | DESC_I_TINT2, TRSCER);
86a74ff2 1160
380af9e3 1161 if (mdp->cd->bculr)
4a55530f 1162 sh_eth_write(ndev, 0x800, BCULR); /* Burst sycle set */
b0ca2a21 1163
4a55530f 1164 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
86a74ff2 1165
380af9e3 1166 if (!mdp->cd->no_trimd)
4a55530f 1167 sh_eth_write(ndev, 0, TRIMD);
86a74ff2 1168
b0ca2a21 1169 /* Recv frame limit set register */
fdb37a7f
YS		 1170 sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1171 RFLR);
86a74ff2 1172
4a55530f 1173 sh_eth_write(ndev, sh_eth_read(ndev, EESR), EESR);
525b8075
YS		 1174 if (start)
1175 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
86a74ff2
NI		 1176
1177 /* PAUSE Prohibition */
4a55530f 1178 val = (sh_eth_read(ndev, ECMR) & ECMR_DM) |
86a74ff2
NI		 1179 ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE;
1180
4a55530f 1181 sh_eth_write(ndev, val, ECMR);
b0ca2a21 1182
380af9e3
YS		 1183 if (mdp->cd->set_rate)
1184 mdp->cd->set_rate(ndev);
1185
b0ca2a21 1186 /* E-MAC Status Register clear */
4a55530f 1187 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
b0ca2a21
NI		 1188
1189 /* E-MAC Interrupt Enable register */
525b8075
YS		 1190 if (start)
1191 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
86a74ff2
NI		 1192
1193 /* Set MAC address */
1194 update_mac_address(ndev);
1195
1196 /* mask reset */
380af9e3 1197 if (mdp->cd->apr)
4a55530f 1198 sh_eth_write(ndev, APR_AP, APR);
380af9e3 1199 if (mdp->cd->mpr)
4a55530f 1200 sh_eth_write(ndev, MPR_MP, MPR);
380af9e3 1201 if (mdp->cd->tpauser)
4a55530f 1202 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
b0ca2a21 1203
525b8075
YS		 1204 if (start) {
1205 /* Setting the Rx mode will start the Rx process. */
1206 sh_eth_write(ndev, EDRRR_R, EDRRR);
86a74ff2 1207
525b8075
YS		 1208 netif_start_queue(ndev);
1209 }
86a74ff2 1210
5cee1d37 1211out:
86a74ff2
NI		 1212 return ret;
1213}
1214
1215/* free Tx skb function */
1216static int sh_eth_txfree(struct net_device *ndev)
1217{
1218 struct sh_eth_private *mdp = netdev_priv(ndev);
1219 struct sh_eth_txdesc *txdesc;
1220 int freeNum = 0;
1221 int entry = 0;
1222
1223 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
525b8075 1224 entry = mdp->dirty_tx % mdp->num_tx_ring;
86a74ff2 1225 txdesc = &mdp->tx_ring[entry];
71557a37 1226 if (txdesc->status & cpu_to_edmac(mdp, TD_TACT))
86a74ff2
NI		 1227 break;
1228 /* Free the original skb. */
1229 if (mdp->tx_skbuff[entry]) {
31fcb99d
YS		 1230 dma_unmap_single(&ndev->dev, txdesc->addr,
1231 txdesc->buffer_length, DMA_TO_DEVICE);
86a74ff2
NI		 1232 dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1233 mdp->tx_skbuff[entry] = NULL;
1234 freeNum++;
1235 }
71557a37 1236 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
525b8075 1237 if (entry >= mdp->num_tx_ring - 1)
71557a37 1238 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
86a74ff2 1239
bb7d92e3
ED		 1240 ndev->stats.tx_packets++;
1241 ndev->stats.tx_bytes += txdesc->buffer_length;
86a74ff2
NI		 1242 }
1243 return freeNum;
1244}
1245
1246/* Packet receive function */
a18e08bd 1247static int sh_eth_rx(struct net_device *ndev, u32 intr_status)
86a74ff2
NI		 1248{
1249 struct sh_eth_private *mdp = netdev_priv(ndev);
1250 struct sh_eth_rxdesc *rxdesc;
1251
525b8075
YS		 1252 int entry = mdp->cur_rx % mdp->num_rx_ring;
1253 int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
86a74ff2
NI		 1254 struct sk_buff *skb;
1255 u16 pkt_len = 0;
380af9e3 1256 u32 desc_status;
86a74ff2
NI		 1257
1258 rxdesc = &mdp->rx_ring[entry];
71557a37
YS		 1259 while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) {
1260 desc_status = edmac_to_cpu(mdp, rxdesc->status);
86a74ff2
NI		 1261 pkt_len = rxdesc->frame_length;
1262
1263 if (--boguscnt < 0)
1264 break;
1265
1266 if (!(desc_status & RDFEND))
bb7d92e3 1267 ndev->stats.rx_length_errors++;
86a74ff2 1268
dd019897
YS		 1269#if defined(CONFIG_ARCH_R8A7740)
1270 /*
1271 * In case of almost all GETHER/ETHERs, the Receive Frame State
1272 * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
1273 * bit 0. However, in case of the R8A7740's GETHER, the RFS
1274 * bits are from bit 25 to bit 16. So, the driver needs right
1275 * shifting by 16.
1276 */
1277 desc_status >>= 16;
1278#endif
1279
86a74ff2
NI		 1280 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1281 RD_RFS5 | RD_RFS6 | RD_RFS10)) {
bb7d92e3 1282 ndev->stats.rx_errors++;
86a74ff2 1283 if (desc_status & RD_RFS1)
bb7d92e3 1284 ndev->stats.rx_crc_errors++;
86a74ff2 1285 if (desc_status & RD_RFS2)
bb7d92e3 1286 ndev->stats.rx_frame_errors++;
86a74ff2 1287 if (desc_status & RD_RFS3)
bb7d92e3 1288 ndev->stats.rx_length_errors++;
86a74ff2 1289 if (desc_status & RD_RFS4)
bb7d92e3 1290 ndev->stats.rx_length_errors++;
86a74ff2 1291 if (desc_status & RD_RFS6)
bb7d92e3 1292 ndev->stats.rx_missed_errors++;
86a74ff2 1293 if (desc_status & RD_RFS10)
bb7d92e3 1294 ndev->stats.rx_over_errors++;
86a74ff2 1295 } else {
380af9e3
YS		 1296 if (!mdp->cd->hw_swap)
1297 sh_eth_soft_swap(
1298 phys_to_virt(ALIGN(rxdesc->addr, 4)),
1299 pkt_len + 2);
86a74ff2
NI		 1300 skb = mdp->rx_skbuff[entry];
1301 mdp->rx_skbuff[entry] = NULL;
503914cf
MD		 1302 if (mdp->cd->rpadir)
1303 skb_reserve(skb, NET_IP_ALIGN);
86a74ff2
NI		 1304 skb_put(skb, pkt_len);
1305 skb->protocol = eth_type_trans(skb, ndev);
1306 netif_rx(skb);
bb7d92e3
ED		 1307 ndev->stats.rx_packets++;
1308 ndev->stats.rx_bytes += pkt_len;
86a74ff2 1309 }
71557a37 1310 rxdesc->status |= cpu_to_edmac(mdp, RD_RACT);
525b8075 1311 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
862df497 1312 rxdesc = &mdp->rx_ring[entry];
86a74ff2
NI		 1313 }
1314
1315 /* Refill the Rx ring buffers. */
1316 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
525b8075 1317 entry = mdp->dirty_rx % mdp->num_rx_ring;
86a74ff2 1318 rxdesc = &mdp->rx_ring[entry];
b0ca2a21 1319 /* The size of the buffer is 16 byte boundary. */
0029d64a 1320 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
b0ca2a21 1321
86a74ff2 1322 if (mdp->rx_skbuff[entry] == NULL) {
dae2e9f4 1323 skb = netdev_alloc_skb(ndev, mdp->rx_buf_sz);
86a74ff2
NI		 1324 mdp->rx_skbuff[entry] = skb;
1325 if (skb == NULL)
1326 break; /* Better luck next round. */
bb7d92e3 1327 dma_map_single(&ndev->dev, skb->data, mdp->rx_buf_sz,
e88aae7b 1328 DMA_FROM_DEVICE);
380af9e3
YS		 1329 sh_eth_set_receive_align(skb);
1330
bc8acf2c 1331 skb_checksum_none_assert(skb);
0029d64a 1332 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
86a74ff2 1333 }
525b8075 1334 if (entry >= mdp->num_rx_ring - 1)
86a74ff2 1335 rxdesc->status |=
71557a37 1336 cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDEL);
86a74ff2
NI		 1337 else
1338 rxdesc->status |=
71557a37 1339 cpu_to_edmac(mdp, RD_RACT | RD_RFP);
86a74ff2
NI		 1340 }
1341
1342 /* Restart Rx engine if stopped. */
1343 /* If we don't need to check status, don't. -KDU */
79fba9f5 1344 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
a18e08bd
YS		 1345 /* fix the values for the next receiving if RDE is set */
1346 if (intr_status & EESR_RDE)
1347 mdp->cur_rx = mdp->dirty_rx =
1348 (sh_eth_read(ndev, RDFAR) -
1349 sh_eth_read(ndev, RDLAR)) >> 4;
4a55530f 1350 sh_eth_write(ndev, EDRRR_R, EDRRR);
79fba9f5 1351 }
86a74ff2
NI		 1352
1353 return 0;
1354}
1355
4a55530f 1356static void sh_eth_rcv_snd_disable(struct net_device *ndev)
dc19e4e5
NI		 1357{
1358 /* disable tx and rx */
4a55530f
YS		 1359 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) &
1360 ~(ECMR_RE | ECMR_TE), ECMR);
dc19e4e5
NI		 1361}
1362
4a55530f 1363static void sh_eth_rcv_snd_enable(struct net_device *ndev)
dc19e4e5
NI		 1364{
1365 /* enable tx and rx */
4a55530f
YS		 1366 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) |
1367 (ECMR_RE | ECMR_TE), ECMR);
dc19e4e5
NI		 1368}
1369
86a74ff2
NI		 1370/* error control function */
1371static void sh_eth_error(struct net_device *ndev, int intr_status)
1372{
1373 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2 1374 u32 felic_stat;
380af9e3
YS		 1375 u32 link_stat;
1376 u32 mask;
86a74ff2
NI		 1377
1378 if (intr_status & EESR_ECI) {
4a55530f
YS		 1379 felic_stat = sh_eth_read(ndev, ECSR);
1380 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */
86a74ff2 1381 if (felic_stat & ECSR_ICD)
bb7d92e3 1382 ndev->stats.tx_carrier_errors++;
86a74ff2
NI		 1383 if (felic_stat & ECSR_LCHNG) {
1384 /* Link Changed */
4923576b 1385 if (mdp->cd->no_psr || mdp->no_ether_link) {
1e1b812b 1386 goto ignore_link;
380af9e3 1387 } else {
4a55530f 1388 link_stat = (sh_eth_read(ndev, PSR));
4923576b
YS		 1389 if (mdp->ether_link_active_low)
1390 link_stat = ~link_stat;
380af9e3 1391 }
dc19e4e5 1392 if (!(link_stat & PHY_ST_LINK))
4a55530f 1393 sh_eth_rcv_snd_disable(ndev);
dc19e4e5 1394 else {
86a74ff2 1395 /* Link Up */
4a55530f
YS		 1396 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) &
1397 ~DMAC_M_ECI, EESIPR);
86a74ff2 1398 /*clear int */
4a55530f
YS		 1399 sh_eth_write(ndev, sh_eth_read(ndev, ECSR),
1400 ECSR);
1401 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) |
1402 DMAC_M_ECI, EESIPR);
86a74ff2 1403 /* enable tx and rx */
4a55530f 1404 sh_eth_rcv_snd_enable(ndev);
86a74ff2
NI		 1405 }
1406 }
1407 }
1408
1e1b812b 1409ignore_link:
86a74ff2
NI		 1410 if (intr_status & EESR_TWB) {
1411 /* Write buck end. unused write back interrupt */
1412 if (intr_status & EESR_TABT) /* Transmit Abort int */
bb7d92e3 1413 ndev->stats.tx_aborted_errors++;
dc19e4e5
NI		 1414 if (netif_msg_tx_err(mdp))
1415 dev_err(&ndev->dev, "Transmit Abort\n");
86a74ff2
NI		 1416 }
1417
1418 if (intr_status & EESR_RABT) {
1419 /* Receive Abort int */
1420 if (intr_status & EESR_RFRMER) {
1421 /* Receive Frame Overflow int */
bb7d92e3 1422 ndev->stats.rx_frame_errors++;
dc19e4e5
NI		 1423 if (netif_msg_rx_err(mdp))
1424 dev_err(&ndev->dev, "Receive Abort\n");
86a74ff2
NI		 1425 }
1426 }
380af9e3 1427
dc19e4e5
NI		 1428 if (intr_status & EESR_TDE) {
1429 /* Transmit Descriptor Empty int */
bb7d92e3 1430 ndev->stats.tx_fifo_errors++;
dc19e4e5
NI		 1431 if (netif_msg_tx_err(mdp))
1432 dev_err(&ndev->dev, "Transmit Descriptor Empty\n");
1433 }
1434
1435 if (intr_status & EESR_TFE) {
1436 /* FIFO under flow */
bb7d92e3 1437 ndev->stats.tx_fifo_errors++;
dc19e4e5
NI		 1438 if (netif_msg_tx_err(mdp))
1439 dev_err(&ndev->dev, "Transmit FIFO Under flow\n");
86a74ff2
NI		 1440 }
1441
1442 if (intr_status & EESR_RDE) {
1443 /* Receive Descriptor Empty int */
bb7d92e3 1444 ndev->stats.rx_over_errors++;
86a74ff2 1445
dc19e4e5
NI		 1446 if (netif_msg_rx_err(mdp))
1447 dev_err(&ndev->dev, "Receive Descriptor Empty\n");
86a74ff2 1448 }
dc19e4e5 1449
86a74ff2
NI		 1450 if (intr_status & EESR_RFE) {
1451 /* Receive FIFO Overflow int */
bb7d92e3 1452 ndev->stats.rx_fifo_errors++;
dc19e4e5
NI		 1453 if (netif_msg_rx_err(mdp))
1454 dev_err(&ndev->dev, "Receive FIFO Overflow\n");
1455 }
1456
1457 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1458 /* Address Error */
bb7d92e3 1459 ndev->stats.tx_fifo_errors++;
dc19e4e5
NI		 1460 if (netif_msg_tx_err(mdp))
1461 dev_err(&ndev->dev, "Address Error\n");
86a74ff2 1462 }
380af9e3
YS		 1463
1464 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1465 if (mdp->cd->no_ade)
1466 mask &= ~EESR_ADE;
1467 if (intr_status & mask) {
86a74ff2 1468 /* Tx error */
4a55530f 1469 u32 edtrr = sh_eth_read(ndev, EDTRR);
86a74ff2 1470 /* dmesg */
380af9e3
YS		 1471 dev_err(&ndev->dev, "TX error. status=%8.8x cur_tx=%8.8x ",
1472 intr_status, mdp->cur_tx);
1473 dev_err(&ndev->dev, "dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
86a74ff2
NI		 1474 mdp->dirty_tx, (u32) ndev->state, edtrr);
1475 /* dirty buffer free */
1476 sh_eth_txfree(ndev);
1477
1478 /* SH7712 BUG */
c5ed5368 1479 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
86a74ff2 1480 /* tx dma start */
c5ed5368 1481 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
86a74ff2
NI		 1482 }
1483 /* wakeup */
1484 netif_wake_queue(ndev);
1485 }
1486}
1487
1488static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1489{
1490 struct net_device *ndev = netdev;
1491 struct sh_eth_private *mdp = netdev_priv(ndev);
380af9e3 1492 struct sh_eth_cpu_data *cd = mdp->cd;
0e0fde3c 1493 irqreturn_t ret = IRQ_NONE;
3893b273 1494 unsigned long intr_status;
86a74ff2 1495
86a74ff2
NI		 1496 spin_lock(&mdp->lock);
1497
3893b273 1498 /* Get interrupt status */
4a55530f 1499 intr_status = sh_eth_read(ndev, EESR);
3893b273
SS		 1500 /* Mask it with the interrupt mask, forcing ECI interrupt to be always
1501 * enabled since it's the one that comes thru regardless of the mask,
1502 * and we need to fully handle it in sh_eth_error() in order to quench
1503 * it as it doesn't get cleared by just writing 1 to the ECI bit...
1504 */
1505 intr_status &= sh_eth_read(ndev, EESIPR) | DMAC_M_ECI;
86a74ff2 1506 /* Clear interrupt */
ea7d69e7 1507 if (intr_status & (EESR_RX_CHECK | cd->tx_check | cd->eesr_err_check)) {
4a55530f 1508 sh_eth_write(ndev, intr_status, EESR);
0e0fde3c
NI		 1509 ret = IRQ_HANDLED;
1510 } else
1511 goto other_irq;
86a74ff2 1512
ea7d69e7 1513 if (intr_status & EESR_RX_CHECK)
a18e08bd 1514 sh_eth_rx(ndev, intr_status);
86a74ff2 1515
b0ca2a21 1516 /* Tx Check */
380af9e3 1517 if (intr_status & cd->tx_check) {
86a74ff2
NI		 1518 sh_eth_txfree(ndev);
1519 netif_wake_queue(ndev);
1520 }
1521
380af9e3 1522 if (intr_status & cd->eesr_err_check)
86a74ff2
NI		 1523 sh_eth_error(ndev, intr_status);
1524
0e0fde3c 1525other_irq:
86a74ff2
NI		 1526 spin_unlock(&mdp->lock);
1527
0e0fde3c 1528 return ret;
86a74ff2
NI		 1529}
1530
86a74ff2
NI		 1531/* PHY state control function */
1532static void sh_eth_adjust_link(struct net_device *ndev)
1533{
1534 struct sh_eth_private *mdp = netdev_priv(ndev);
1535 struct phy_device *phydev = mdp->phydev;
86a74ff2
NI		 1536 int new_state = 0;
1537
3340d2aa 1538 if (phydev->link) {
86a74ff2
NI		 1539 if (phydev->duplex != mdp->duplex) {
1540 new_state = 1;
1541 mdp->duplex = phydev->duplex;
380af9e3
YS		 1542 if (mdp->cd->set_duplex)
1543 mdp->cd->set_duplex(ndev);
86a74ff2
NI		 1544 }
1545
1546 if (phydev->speed != mdp->speed) {
1547 new_state = 1;
1548 mdp->speed = phydev->speed;
380af9e3
YS		 1549 if (mdp->cd->set_rate)
1550 mdp->cd->set_rate(ndev);
86a74ff2 1551 }
3340d2aa 1552 if (!mdp->link) {
91a56152
YS		 1553 sh_eth_write(ndev,
1554 (sh_eth_read(ndev, ECMR) & ~ECMR_TXF), ECMR);
86a74ff2
NI		 1555 new_state = 1;
1556 mdp->link = phydev->link;
1e1b812b
SS		 1557 if (mdp->cd->no_psr || mdp->no_ether_link)
1558 sh_eth_rcv_snd_enable(ndev);
86a74ff2
NI		 1559 }
1560 } else if (mdp->link) {
1561 new_state = 1;
3340d2aa 1562 mdp->link = 0;
86a74ff2
NI		 1563 mdp->speed = 0;
1564 mdp->duplex = -1;
1e1b812b
SS		 1565 if (mdp->cd->no_psr || mdp->no_ether_link)
1566 sh_eth_rcv_snd_disable(ndev);
86a74ff2
NI		 1567 }
1568
dc19e4e5 1569 if (new_state && netif_msg_link(mdp))
86a74ff2
NI		 1570 phy_print_status(phydev);
1571}
1572
1573/* PHY init function */
1574static int sh_eth_phy_init(struct net_device *ndev)
1575{
1576 struct sh_eth_private *mdp = netdev_priv(ndev);
0a372eb9 1577 char phy_id[MII_BUS_ID_SIZE + 3];
86a74ff2
NI		 1578 struct phy_device *phydev = NULL;
1579
fb28ad35 1580 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
86a74ff2
NI		 1581 mdp->mii_bus->id , mdp->phy_id);
1582
3340d2aa 1583 mdp->link = 0;
86a74ff2
NI		 1584 mdp->speed = 0;
1585 mdp->duplex = -1;
1586
1587 /* Try connect to PHY */
c061b18d 1588 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
f9a8f83b 1589 mdp->phy_interface);
86a74ff2
NI		 1590 if (IS_ERR(phydev)) {
1591 dev_err(&ndev->dev, "phy_connect failed\n");
1592 return PTR_ERR(phydev);
1593 }
380af9e3 1594
86a74ff2 1595 dev_info(&ndev->dev, "attached phy %i to driver %s\n",
380af9e3 1596 phydev->addr, phydev->drv->name);
86a74ff2
NI		 1597
1598 mdp->phydev = phydev;
1599
1600 return 0;
1601}
1602
1603/* PHY control start function */
1604static int sh_eth_phy_start(struct net_device *ndev)
1605{
1606 struct sh_eth_private *mdp = netdev_priv(ndev);
1607 int ret;
1608
1609 ret = sh_eth_phy_init(ndev);
1610 if (ret)
1611 return ret;
1612
1613 /* reset phy - this also wakes it from PDOWN */
1614 phy_write(mdp->phydev, MII_BMCR, BMCR_RESET);
1615 phy_start(mdp->phydev);
1616
1617 return 0;
1618}
1619
dc19e4e5
NI		 1620static int sh_eth_get_settings(struct net_device *ndev,
1621 struct ethtool_cmd *ecmd)
1622{
1623 struct sh_eth_private *mdp = netdev_priv(ndev);
1624 unsigned long flags;
1625 int ret;
1626
1627 spin_lock_irqsave(&mdp->lock, flags);
1628 ret = phy_ethtool_gset(mdp->phydev, ecmd);
1629 spin_unlock_irqrestore(&mdp->lock, flags);
1630
1631 return ret;
1632}
1633
1634static int sh_eth_set_settings(struct net_device *ndev,
1635 struct ethtool_cmd *ecmd)
1636{
1637 struct sh_eth_private *mdp = netdev_priv(ndev);
1638 unsigned long flags;
1639 int ret;
dc19e4e5
NI		 1640
1641 spin_lock_irqsave(&mdp->lock, flags);
1642
1643 /* disable tx and rx */
4a55530f 1644 sh_eth_rcv_snd_disable(ndev);
dc19e4e5
NI		 1645
1646 ret = phy_ethtool_sset(mdp->phydev, ecmd);
1647 if (ret)
1648 goto error_exit;
1649
1650 if (ecmd->duplex == DUPLEX_FULL)
1651 mdp->duplex = 1;
1652 else
1653 mdp->duplex = 0;
1654
1655 if (mdp->cd->set_duplex)
1656 mdp->cd->set_duplex(ndev);
1657
1658error_exit:
1659 mdelay(1);
1660
1661 /* enable tx and rx */
4a55530f 1662 sh_eth_rcv_snd_enable(ndev);
dc19e4e5
NI		 1663
1664 spin_unlock_irqrestore(&mdp->lock, flags);
1665
1666 return ret;
1667}
1668
1669static int sh_eth_nway_reset(struct net_device *ndev)
1670{
1671 struct sh_eth_private *mdp = netdev_priv(ndev);
1672 unsigned long flags;
1673 int ret;
1674
1675 spin_lock_irqsave(&mdp->lock, flags);
1676 ret = phy_start_aneg(mdp->phydev);
1677 spin_unlock_irqrestore(&mdp->lock, flags);
1678
1679 return ret;
1680}
1681
1682static u32 sh_eth_get_msglevel(struct net_device *ndev)
1683{
1684 struct sh_eth_private *mdp = netdev_priv(ndev);
1685 return mdp->msg_enable;
1686}
1687
1688static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
1689{
1690 struct sh_eth_private *mdp = netdev_priv(ndev);
1691 mdp->msg_enable = value;
1692}
1693
1694static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
1695 "rx_current", "tx_current",
1696 "rx_dirty", "tx_dirty",
1697};
1698#define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats)
1699
1700static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
1701{
1702 switch (sset) {
1703 case ETH_SS_STATS:
1704 return SH_ETH_STATS_LEN;
1705 default:
1706 return -EOPNOTSUPP;
1707 }
1708}
1709
1710static void sh_eth_get_ethtool_stats(struct net_device *ndev,
1711 struct ethtool_stats *stats, u64 *data)
1712{
1713 struct sh_eth_private *mdp = netdev_priv(ndev);
1714 int i = 0;
1715
1716 /* device-specific stats */
1717 data[i++] = mdp->cur_rx;
1718 data[i++] = mdp->cur_tx;
1719 data[i++] = mdp->dirty_rx;
1720 data[i++] = mdp->dirty_tx;
1721}
1722
1723static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1724{
1725 switch (stringset) {
1726 case ETH_SS_STATS:
1727 memcpy(data, *sh_eth_gstrings_stats,
1728 sizeof(sh_eth_gstrings_stats));
1729 break;
1730 }
1731}
1732
525b8075
YS		 1733static void sh_eth_get_ringparam(struct net_device *ndev,
1734 struct ethtool_ringparam *ring)
1735{
1736 struct sh_eth_private *mdp = netdev_priv(ndev);
1737
1738 ring->rx_max_pending = RX_RING_MAX;
1739 ring->tx_max_pending = TX_RING_MAX;
1740 ring->rx_pending = mdp->num_rx_ring;
1741 ring->tx_pending = mdp->num_tx_ring;
1742}
1743
1744static int sh_eth_set_ringparam(struct net_device *ndev,
1745 struct ethtool_ringparam *ring)
1746{
1747 struct sh_eth_private *mdp = netdev_priv(ndev);
1748 int ret;
1749
1750 if (ring->tx_pending > TX_RING_MAX ||
1751 ring->rx_pending > RX_RING_MAX ||
1752 ring->tx_pending < TX_RING_MIN ||
1753 ring->rx_pending < RX_RING_MIN)
1754 return -EINVAL;
1755 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
1756 return -EINVAL;
1757
1758 if (netif_running(ndev)) {
1759 netif_tx_disable(ndev);
1760 /* Disable interrupts by clearing the interrupt mask. */
1761 sh_eth_write(ndev, 0x0000, EESIPR);
1762 /* Stop the chip's Tx and Rx processes. */
1763 sh_eth_write(ndev, 0, EDTRR);
1764 sh_eth_write(ndev, 0, EDRRR);
1765 synchronize_irq(ndev->irq);
1766 }
1767
1768 /* Free all the skbuffs in the Rx queue. */
1769 sh_eth_ring_free(ndev);
1770 /* Free DMA buffer */
1771 sh_eth_free_dma_buffer(mdp);
1772
1773 /* Set new parameters */
1774 mdp->num_rx_ring = ring->rx_pending;
1775 mdp->num_tx_ring = ring->tx_pending;
1776
1777 ret = sh_eth_ring_init(ndev);
1778 if (ret < 0) {
1779 dev_err(&ndev->dev, "%s: sh_eth_ring_init failed.\n", __func__);
1780 return ret;
1781 }
1782 ret = sh_eth_dev_init(ndev, false);
1783 if (ret < 0) {
1784 dev_err(&ndev->dev, "%s: sh_eth_dev_init failed.\n", __func__);
1785 return ret;
1786 }
1787
1788 if (netif_running(ndev)) {
1789 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1790 /* Setting the Rx mode will start the Rx process. */
1791 sh_eth_write(ndev, EDRRR_R, EDRRR);
1792 netif_wake_queue(ndev);
1793 }
1794
1795 return 0;
1796}
1797
9b07be4b 1798static const struct ethtool_ops sh_eth_ethtool_ops = {
dc19e4e5
NI		 1799 .get_settings = sh_eth_get_settings,
1800 .set_settings = sh_eth_set_settings,
9b07be4b 1801 .nway_reset = sh_eth_nway_reset,
dc19e4e5
NI		 1802 .get_msglevel = sh_eth_get_msglevel,
1803 .set_msglevel = sh_eth_set_msglevel,
9b07be4b 1804 .get_link = ethtool_op_get_link,
dc19e4e5
NI		 1805 .get_strings = sh_eth_get_strings,
1806 .get_ethtool_stats = sh_eth_get_ethtool_stats,
1807 .get_sset_count = sh_eth_get_sset_count,
525b8075
YS		 1808 .get_ringparam = sh_eth_get_ringparam,
1809 .set_ringparam = sh_eth_set_ringparam,
dc19e4e5
NI		 1810};
1811
86a74ff2
NI		 1812/* network device open function */
1813static int sh_eth_open(struct net_device *ndev)
1814{
1815 int ret = 0;
1816 struct sh_eth_private *mdp = netdev_priv(ndev);
1817
bcd5149d
MD		 1818 pm_runtime_get_sync(&mdp->pdev->dev);
1819
a0607fd3 1820 ret = request_irq(ndev->irq, sh_eth_interrupt,
5b3dfd13 1821 mdp->cd->irq_flags, ndev->name, ndev);
86a74ff2 1822 if (ret) {
380af9e3 1823 dev_err(&ndev->dev, "Can not assign IRQ number\n");
86a74ff2
NI		 1824 return ret;
1825 }
1826
1827 /* Descriptor set */
1828 ret = sh_eth_ring_init(ndev);
1829 if (ret)
1830 goto out_free_irq;
1831
1832 /* device init */
525b8075 1833 ret = sh_eth_dev_init(ndev, true);
86a74ff2
NI		 1834 if (ret)
1835 goto out_free_irq;
1836
1837 /* PHY control start*/
1838 ret = sh_eth_phy_start(ndev);
1839 if (ret)
1840 goto out_free_irq;
1841
86a74ff2
NI		 1842 return ret;
1843
1844out_free_irq:
1845 free_irq(ndev->irq, ndev);
bcd5149d 1846 pm_runtime_put_sync(&mdp->pdev->dev);
86a74ff2
NI		 1847 return ret;
1848}
1849
1850/* Timeout function */
1851static void sh_eth_tx_timeout(struct net_device *ndev)
1852{
1853 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 1854 struct sh_eth_rxdesc *rxdesc;
1855 int i;
1856
1857 netif_stop_queue(ndev);
1858
dc19e4e5
NI		 1859 if (netif_msg_timer(mdp))
1860 dev_err(&ndev->dev, "%s: transmit timed out, status %8.8x,"
4a55530f 1861 " resetting...\n", ndev->name, (int)sh_eth_read(ndev, EESR));
86a74ff2
NI		 1862
1863 /* tx_errors count up */
bb7d92e3 1864 ndev->stats.tx_errors++;
86a74ff2 1865
86a74ff2 1866 /* Free all the skbuffs in the Rx queue. */
525b8075 1867 for (i = 0; i < mdp->num_rx_ring; i++) {
86a74ff2
NI		 1868 rxdesc = &mdp->rx_ring[i];
1869 rxdesc->status = 0;
1870 rxdesc->addr = 0xBADF00D0;
1871 if (mdp->rx_skbuff[i])
1872 dev_kfree_skb(mdp->rx_skbuff[i]);
1873 mdp->rx_skbuff[i] = NULL;
1874 }
525b8075 1875 for (i = 0; i < mdp->num_tx_ring; i++) {
86a74ff2
NI		 1876 if (mdp->tx_skbuff[i])
1877 dev_kfree_skb(mdp->tx_skbuff[i]);
1878 mdp->tx_skbuff[i] = NULL;
1879 }
1880
1881 /* device init */
525b8075 1882 sh_eth_dev_init(ndev, true);
86a74ff2
NI		 1883}
1884
1885/* Packet transmit function */
1886static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1887{
1888 struct sh_eth_private *mdp = netdev_priv(ndev);
1889 struct sh_eth_txdesc *txdesc;
1890 u32 entry;
fb5e2f9b 1891 unsigned long flags;
86a74ff2
NI		 1892
1893 spin_lock_irqsave(&mdp->lock, flags);
525b8075 1894 if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
86a74ff2 1895 if (!sh_eth_txfree(ndev)) {
dc19e4e5
NI		 1896 if (netif_msg_tx_queued(mdp))
1897 dev_warn(&ndev->dev, "TxFD exhausted.\n");
86a74ff2
NI		 1898 netif_stop_queue(ndev);
1899 spin_unlock_irqrestore(&mdp->lock, flags);
5b548140 1900 return NETDEV_TX_BUSY;
86a74ff2
NI		 1901 }
1902 }
1903 spin_unlock_irqrestore(&mdp->lock, flags);
1904
525b8075 1905 entry = mdp->cur_tx % mdp->num_tx_ring;
86a74ff2
NI		 1906 mdp->tx_skbuff[entry] = skb;
1907 txdesc = &mdp->tx_ring[entry];
86a74ff2 1908 /* soft swap. */
380af9e3
YS		 1909 if (!mdp->cd->hw_swap)
1910 sh_eth_soft_swap(phys_to_virt(ALIGN(txdesc->addr, 4)),
1911 skb->len + 2);
31fcb99d
YS		 1912 txdesc->addr = dma_map_single(&ndev->dev, skb->data, skb->len,
1913 DMA_TO_DEVICE);
86a74ff2
NI		 1914 if (skb->len < ETHERSMALL)
1915 txdesc->buffer_length = ETHERSMALL;
1916 else
1917 txdesc->buffer_length = skb->len;
1918
525b8075 1919 if (entry >= mdp->num_tx_ring - 1)
71557a37 1920 txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE);
86a74ff2 1921 else
71557a37 1922 txdesc->status |= cpu_to_edmac(mdp, TD_TACT);
86a74ff2
NI		 1923
1924 mdp->cur_tx++;
1925
c5ed5368
YS		 1926 if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
1927 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
b0ca2a21 1928
6ed10654 1929 return NETDEV_TX_OK;
86a74ff2
NI		 1930}
1931
1932/* device close function */
1933static int sh_eth_close(struct net_device *ndev)
1934{
1935 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 1936
1937 netif_stop_queue(ndev);
1938
1939 /* Disable interrupts by clearing the interrupt mask. */
4a55530f 1940 sh_eth_write(ndev, 0x0000, EESIPR);
86a74ff2
NI		 1941
1942 /* Stop the chip's Tx and Rx processes. */
4a55530f
YS		 1943 sh_eth_write(ndev, 0, EDTRR);
1944 sh_eth_write(ndev, 0, EDRRR);
86a74ff2
NI		 1945
1946 /* PHY Disconnect */
1947 if (mdp->phydev) {
1948 phy_stop(mdp->phydev);
1949 phy_disconnect(mdp->phydev);
1950 }
1951
1952 free_irq(ndev->irq, ndev);
1953
86a74ff2
NI		 1954 /* Free all the skbuffs in the Rx queue. */
1955 sh_eth_ring_free(ndev);
1956
1957 /* free DMA buffer */
91c77550 1958 sh_eth_free_dma_buffer(mdp);
86a74ff2 1959
bcd5149d
MD		 1960 pm_runtime_put_sync(&mdp->pdev->dev);
1961
86a74ff2
NI		 1962 return 0;
1963}
1964
1965static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
1966{
1967 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2 1968
bcd5149d
MD		 1969 pm_runtime_get_sync(&mdp->pdev->dev);
1970
bb7d92e3 1971 ndev->stats.tx_dropped += sh_eth_read(ndev, TROCR);
4a55530f 1972 sh_eth_write(ndev, 0, TROCR); /* (write clear) */
bb7d92e3 1973 ndev->stats.collisions += sh_eth_read(ndev, CDCR);
4a55530f 1974 sh_eth_write(ndev, 0, CDCR); /* (write clear) */
bb7d92e3 1975 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, LCCR);
4a55530f 1976 sh_eth_write(ndev, 0, LCCR); /* (write clear) */
c5ed5368 1977 if (sh_eth_is_gether(mdp)) {
bb7d92e3 1978 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CERCR);
c5ed5368 1979 sh_eth_write(ndev, 0, CERCR); /* (write clear) */
bb7d92e3 1980 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CEECR);
c5ed5368
YS		 1981 sh_eth_write(ndev, 0, CEECR); /* (write clear) */
1982 } else {
bb7d92e3 1983 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CNDCR);
c5ed5368
YS		 1984 sh_eth_write(ndev, 0, CNDCR); /* (write clear) */
1985 }
bcd5149d
MD		 1986 pm_runtime_put_sync(&mdp->pdev->dev);
1987
bb7d92e3 1988 return &ndev->stats;
86a74ff2
NI		 1989}
1990
bb7d92e3 1991/* ioctl to device function */
86a74ff2
NI		 1992static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq,
1993 int cmd)
1994{
1995 struct sh_eth_private *mdp = netdev_priv(ndev);
1996 struct phy_device *phydev = mdp->phydev;
1997
1998 if (!netif_running(ndev))
1999 return -EINVAL;
2000
2001 if (!phydev)
2002 return -ENODEV;
2003
28b04113 2004 return phy_mii_ioctl(phydev, rq, cmd);
86a74ff2
NI		 2005}
2006
6743fe6d
YS		 2007/* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
2008static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp,
2009 int entry)
2010{
2011 return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4);
2012}
2013
2014static u32 sh_eth_tsu_get_post_mask(int entry)
2015{
2016 return 0x0f << (28 - ((entry % 8) * 4));
2017}
2018
2019static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
2020{
2021 return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
2022}
2023
2024static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
2025 int entry)
2026{
2027 struct sh_eth_private *mdp = netdev_priv(ndev);
2028 u32 tmp;
2029 void *reg_offset;
2030
2031 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2032 tmp = ioread32(reg_offset);
2033 iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset);
2034}
2035
2036static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
2037 int entry)
2038{
2039 struct sh_eth_private *mdp = netdev_priv(ndev);
2040 u32 post_mask, ref_mask, tmp;
2041 void *reg_offset;
2042
2043 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2044 post_mask = sh_eth_tsu_get_post_mask(entry);
2045 ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
2046
2047 tmp = ioread32(reg_offset);
2048 iowrite32(tmp & ~post_mask, reg_offset);
2049
2050 /* If other port enables, the function returns "true" */
2051 return tmp & ref_mask;
2052}
2053
2054static int sh_eth_tsu_busy(struct net_device *ndev)
2055{
2056 int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
2057 struct sh_eth_private *mdp = netdev_priv(ndev);
2058
2059 while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
2060 udelay(10);
2061 timeout--;
2062 if (timeout <= 0) {
2063 dev_err(&ndev->dev, "%s: timeout\n", __func__);
2064 return -ETIMEDOUT;
2065 }
2066 }
2067
2068 return 0;
2069}
2070
2071static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg,
2072 const u8 *addr)
2073{
2074 u32 val;
2075
2076 val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
2077 iowrite32(val, reg);
2078 if (sh_eth_tsu_busy(ndev) < 0)
2079 return -EBUSY;
2080
2081 val = addr[4] << 8 | addr[5];
2082 iowrite32(val, reg + 4);
2083 if (sh_eth_tsu_busy(ndev) < 0)
2084 return -EBUSY;
2085
2086 return 0;
2087}
2088
2089static void sh_eth_tsu_read_entry(void *reg, u8 *addr)
2090{
2091 u32 val;
2092
2093 val = ioread32(reg);
2094 addr[0] = (val >> 24) & 0xff;
2095 addr[1] = (val >> 16) & 0xff;
2096 addr[2] = (val >> 8) & 0xff;
2097 addr[3] = val & 0xff;
2098 val = ioread32(reg + 4);
2099 addr[4] = (val >> 8) & 0xff;
2100 addr[5] = val & 0xff;
2101}
2102
2103
2104static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
2105{
2106 struct sh_eth_private *mdp = netdev_priv(ndev);
2107 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2108 int i;
2109 u8 c_addr[ETH_ALEN];
2110
2111 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2112 sh_eth_tsu_read_entry(reg_offset, c_addr);
2113 if (memcmp(addr, c_addr, ETH_ALEN) == 0)
2114 return i;
2115 }
2116
2117 return -ENOENT;
2118}
2119
2120static int sh_eth_tsu_find_empty(struct net_device *ndev)
2121{
2122 u8 blank[ETH_ALEN];
2123 int entry;
2124
2125 memset(blank, 0, sizeof(blank));
2126 entry = sh_eth_tsu_find_entry(ndev, blank);
2127 return (entry < 0) ? -ENOMEM : entry;
2128}
2129
2130static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
2131 int entry)
2132{
2133 struct sh_eth_private *mdp = netdev_priv(ndev);
2134 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2135 int ret;
2136 u8 blank[ETH_ALEN];
2137
2138 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
2139 ~(1 << (31 - entry)), TSU_TEN);
2140
2141 memset(blank, 0, sizeof(blank));
2142 ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
2143 if (ret < 0)
2144 return ret;
2145 return 0;
2146}
2147
2148static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
2149{
2150 struct sh_eth_private *mdp = netdev_priv(ndev);
2151 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2152 int i, ret;
2153
2154 if (!mdp->cd->tsu)
2155 return 0;
2156
2157 i = sh_eth_tsu_find_entry(ndev, addr);
2158 if (i < 0) {
2159 /* No entry found, create one */
2160 i = sh_eth_tsu_find_empty(ndev);
2161 if (i < 0)
2162 return -ENOMEM;
2163 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
2164 if (ret < 0)
2165 return ret;
2166
2167 /* Enable the entry */
2168 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
2169 (1 << (31 - i)), TSU_TEN);
2170 }
2171
2172 /* Entry found or created, enable POST */
2173 sh_eth_tsu_enable_cam_entry_post(ndev, i);
2174
2175 return 0;
2176}
2177
2178static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
2179{
2180 struct sh_eth_private *mdp = netdev_priv(ndev);
2181 int i, ret;
2182
2183 if (!mdp->cd->tsu)
2184 return 0;
2185
2186 i = sh_eth_tsu_find_entry(ndev, addr);
2187 if (i) {
2188 /* Entry found */
2189 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2190 goto done;
2191
2192 /* Disable the entry if both ports was disabled */
2193 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2194 if (ret < 0)
2195 return ret;
2196 }
2197done:
2198 return 0;
2199}
2200
2201static int sh_eth_tsu_purge_all(struct net_device *ndev)
2202{
2203 struct sh_eth_private *mdp = netdev_priv(ndev);
2204 int i, ret;
2205
2206 if (unlikely(!mdp->cd->tsu))
2207 return 0;
2208
2209 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
2210 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2211 continue;
2212
2213 /* Disable the entry if both ports was disabled */
2214 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2215 if (ret < 0)
2216 return ret;
2217 }
2218
2219 return 0;
2220}
2221
2222static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
2223{
2224 struct sh_eth_private *mdp = netdev_priv(ndev);
2225 u8 addr[ETH_ALEN];
2226 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2227 int i;
2228
2229 if (unlikely(!mdp->cd->tsu))
2230 return;
2231
2232 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2233 sh_eth_tsu_read_entry(reg_offset, addr);
2234 if (is_multicast_ether_addr(addr))
2235 sh_eth_tsu_del_entry(ndev, addr);
2236 }
2237}
2238
86a74ff2
NI		 2239/* Multicast reception directions set */
2240static void sh_eth_set_multicast_list(struct net_device *ndev)
2241{
6743fe6d
YS		 2242 struct sh_eth_private *mdp = netdev_priv(ndev);
2243 u32 ecmr_bits;
2244 int mcast_all = 0;
2245 unsigned long flags;
2246
2247 spin_lock_irqsave(&mdp->lock, flags);
2248 /*
2249 * Initial condition is MCT = 1, PRM = 0.
2250 * Depending on ndev->flags, set PRM or clear MCT
2251 */
2252 ecmr_bits = (sh_eth_read(ndev, ECMR) & ~ECMR_PRM) | ECMR_MCT;
2253
2254 if (!(ndev->flags & IFF_MULTICAST)) {
2255 sh_eth_tsu_purge_mcast(ndev);
2256 mcast_all = 1;
2257 }
2258 if (ndev->flags & IFF_ALLMULTI) {
2259 sh_eth_tsu_purge_mcast(ndev);
2260 ecmr_bits &= ~ECMR_MCT;
2261 mcast_all = 1;
2262 }
2263
86a74ff2 2264 if (ndev->flags & IFF_PROMISC) {
6743fe6d
YS		 2265 sh_eth_tsu_purge_all(ndev);
2266 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2267 } else if (mdp->cd->tsu) {
2268 struct netdev_hw_addr *ha;
2269 netdev_for_each_mc_addr(ha, ndev) {
2270 if (mcast_all && is_multicast_ether_addr(ha->addr))
2271 continue;
2272
2273 if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2274 if (!mcast_all) {
2275 sh_eth_tsu_purge_mcast(ndev);
2276 ecmr_bits &= ~ECMR_MCT;
2277 mcast_all = 1;
2278 }
2279 }
2280 }
86a74ff2
NI		 2281 } else {
2282 /* Normal, unicast/broadcast-only mode. */
6743fe6d 2283 ecmr_bits = (ecmr_bits & ~ECMR_PRM) | ECMR_MCT;
86a74ff2 2284 }
6743fe6d
YS		 2285
2286 /* update the ethernet mode */
2287 sh_eth_write(ndev, ecmr_bits, ECMR);
2288
2289 spin_unlock_irqrestore(&mdp->lock, flags);
86a74ff2 2290}
71cc7c37
YS		 2291
2292static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2293{
2294 if (!mdp->port)
2295 return TSU_VTAG0;
2296 else
2297 return TSU_VTAG1;
2298}
2299
80d5c368
PM		 2300static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
2301 __be16 proto, u16 vid)
71cc7c37
YS		 2302{
2303 struct sh_eth_private *mdp = netdev_priv(ndev);
2304 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2305
2306 if (unlikely(!mdp->cd->tsu))
2307 return -EPERM;
2308
2309 /* No filtering if vid = 0 */
2310 if (!vid)
2311 return 0;
2312
2313 mdp->vlan_num_ids++;
2314
2315 /*
2316 * The controller has one VLAN tag HW filter. So, if the filter is
2317 * already enabled, the driver disables it and the filte
2318 */
2319 if (mdp->vlan_num_ids > 1) {
2320 /* disable VLAN filter */
2321 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2322 return 0;
2323 }
2324
2325 sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
2326 vtag_reg_index);
2327
2328 return 0;
2329}
2330
80d5c368
PM		 2331static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
2332 __be16 proto, u16 vid)
71cc7c37
YS		 2333{
2334 struct sh_eth_private *mdp = netdev_priv(ndev);
2335 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2336
2337 if (unlikely(!mdp->cd->tsu))
2338 return -EPERM;
2339
2340 /* No filtering if vid = 0 */
2341 if (!vid)
2342 return 0;
2343
2344 mdp->vlan_num_ids--;
2345 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2346
2347 return 0;
2348}
86a74ff2
NI		 2349
2350/* SuperH's TSU register init function */
4a55530f 2351static void sh_eth_tsu_init(struct sh_eth_private *mdp)
86a74ff2 2352{
4a55530f
YS		 2353 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */
2354 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */
2355 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */
2356 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
2357 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
2358 sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
2359 sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
2360 sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
2361 sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
2362 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
c5ed5368
YS		 2363 if (sh_eth_is_gether(mdp)) {
2364 sh_eth_tsu_write(mdp, 0, TSU_QTAG0); /* Disable QTAG(0->1) */
2365 sh_eth_tsu_write(mdp, 0, TSU_QTAG1); /* Disable QTAG(1->0) */
2366 } else {
2367 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */
2368 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */
2369 }
4a55530f
YS		 2370 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */
2371 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */
2372 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2373 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */
2374 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */
2375 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */
2376 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */
86a74ff2
NI		 2377}
2378
2379/* MDIO bus release function */
2380static int sh_mdio_release(struct net_device *ndev)
2381{
2382 struct mii_bus *bus = dev_get_drvdata(&ndev->dev);
2383
2384 /* unregister mdio bus */
2385 mdiobus_unregister(bus);
2386
2387 /* remove mdio bus info from net_device */
2388 dev_set_drvdata(&ndev->dev, NULL);
2389
2390 /* free bitbang info */
2391 free_mdio_bitbang(bus);
2392
2393 return 0;
2394}
2395
2396/* MDIO bus init function */
b3017e6a
YS		 2397static int sh_mdio_init(struct net_device *ndev, int id,
2398 struct sh_eth_plat_data *pd)
86a74ff2
NI		 2399{
2400 int ret, i;
2401 struct bb_info *bitbang;
2402 struct sh_eth_private *mdp = netdev_priv(ndev);
2403
2404 /* create bit control struct for PHY */
d5e07e69
SS		 2405 bitbang = devm_kzalloc(&ndev->dev, sizeof(struct bb_info),
2406 GFP_KERNEL);
86a74ff2
NI		 2407 if (!bitbang) {
2408 ret = -ENOMEM;
2409 goto out;
2410 }
2411
2412 /* bitbang init */
ae70644d 2413 bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
b3017e6a 2414 bitbang->set_gate = pd->set_mdio_gate;
dfed5e7f
SS		 2415 bitbang->mdi_msk = PIR_MDI;
2416 bitbang->mdo_msk = PIR_MDO;
2417 bitbang->mmd_msk = PIR_MMD;
2418 bitbang->mdc_msk = PIR_MDC;
86a74ff2
NI		 2419 bitbang->ctrl.ops = &bb_ops;
2420
c2e07b3a 2421 /* MII controller setting */
86a74ff2
NI		 2422 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
2423 if (!mdp->mii_bus) {
2424 ret = -ENOMEM;
d5e07e69 2425 goto out;
86a74ff2
NI		 2426 }
2427
2428 /* Hook up MII support for ethtool */
2429 mdp->mii_bus->name = "sh_mii";
18ee49dd 2430 mdp->mii_bus->parent = &ndev->dev;
5278fb54 2431 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
34aa6f14 2432 mdp->pdev->name, id);
86a74ff2
NI		 2433
2434 /* PHY IRQ */
d5e07e69
SS		 2435 mdp->mii_bus->irq = devm_kzalloc(&ndev->dev,
2436 sizeof(int) * PHY_MAX_ADDR,
2437 GFP_KERNEL);
86a74ff2
NI		 2438 if (!mdp->mii_bus->irq) {
2439 ret = -ENOMEM;
2440 goto out_free_bus;
2441 }
2442
2443 for (i = 0; i < PHY_MAX_ADDR; i++)
2444 mdp->mii_bus->irq[i] = PHY_POLL;
2445
8f6352f2 2446 /* register mdio bus */
86a74ff2
NI		 2447 ret = mdiobus_register(mdp->mii_bus);
2448 if (ret)
d5e07e69 2449 goto out_free_bus;
86a74ff2
NI		 2450
2451 dev_set_drvdata(&ndev->dev, mdp->mii_bus);
2452
2453 return 0;
2454
86a74ff2 2455out_free_bus:
298cf9be 2456 free_mdio_bitbang(mdp->mii_bus);
86a74ff2 2457
86a74ff2
NI		 2458out:
2459 return ret;
2460}
2461
4a55530f
YS		 2462static const u16 *sh_eth_get_register_offset(int register_type)
2463{
2464 const u16 *reg_offset = NULL;
2465
2466 switch (register_type) {
2467 case SH_ETH_REG_GIGABIT:
2468 reg_offset = sh_eth_offset_gigabit;
2469 break;
a3f109bd
SS		 2470 case SH_ETH_REG_FAST_RCAR:
2471 reg_offset = sh_eth_offset_fast_rcar;
2472 break;
4a55530f
YS		 2473 case SH_ETH_REG_FAST_SH4:
2474 reg_offset = sh_eth_offset_fast_sh4;
2475 break;
2476 case SH_ETH_REG_FAST_SH3_SH2:
2477 reg_offset = sh_eth_offset_fast_sh3_sh2;
2478 break;
2479 default:
14c3326a 2480 pr_err("Unknown register type (%d)\n", register_type);
4a55530f
YS		 2481 break;
2482 }
2483
2484 return reg_offset;
2485}
2486
8f728d79 2487static const struct net_device_ops sh_eth_netdev_ops = {
ebf84eaa
AB		 2488 .ndo_open = sh_eth_open,
2489 .ndo_stop = sh_eth_close,
2490 .ndo_start_xmit = sh_eth_start_xmit,
2491 .ndo_get_stats = sh_eth_get_stats,
ebf84eaa
AB		 2492 .ndo_tx_timeout = sh_eth_tx_timeout,
2493 .ndo_do_ioctl = sh_eth_do_ioctl,
2494 .ndo_validate_addr = eth_validate_addr,
2495 .ndo_set_mac_address = eth_mac_addr,
2496 .ndo_change_mtu = eth_change_mtu,
2497};
2498
8f728d79
SS		 2499static const struct net_device_ops sh_eth_netdev_ops_tsu = {
2500 .ndo_open = sh_eth_open,
2501 .ndo_stop = sh_eth_close,
2502 .ndo_start_xmit = sh_eth_start_xmit,
2503 .ndo_get_stats = sh_eth_get_stats,
2504 .ndo_set_rx_mode = sh_eth_set_multicast_list,
2505 .ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid,
2506 .ndo_vlan_rx_kill_vid = sh_eth_vlan_rx_kill_vid,
2507 .ndo_tx_timeout = sh_eth_tx_timeout,
2508 .ndo_do_ioctl = sh_eth_do_ioctl,
2509 .ndo_validate_addr = eth_validate_addr,
2510 .ndo_set_mac_address = eth_mac_addr,
2511 .ndo_change_mtu = eth_change_mtu,
2512};
2513
86a74ff2
NI		 2514static int sh_eth_drv_probe(struct platform_device *pdev)
2515{
9c38657c 2516 int ret, devno = 0;
86a74ff2
NI		 2517 struct resource *res;
2518 struct net_device *ndev = NULL;
ec0d7551 2519 struct sh_eth_private *mdp = NULL;
564044b0 2520 struct sh_eth_plat_data *pd = pdev->dev.platform_data;
afe391ad 2521 const struct platform_device_id *id = platform_get_device_id(pdev);
86a74ff2
NI		 2522
2523 /* get base addr */
2524 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2525 if (unlikely(res == NULL)) {
2526 dev_err(&pdev->dev, "invalid resource\n");
2527 ret = -EINVAL;
2528 goto out;
2529 }
2530
2531 ndev = alloc_etherdev(sizeof(struct sh_eth_private));
2532 if (!ndev) {
86a74ff2
NI		 2533 ret = -ENOMEM;
2534 goto out;
2535 }
2536
2537 /* The sh Ether-specific entries in the device structure. */
2538 ndev->base_addr = res->start;
2539 devno = pdev->id;
2540 if (devno < 0)
2541 devno = 0;
2542
2543 ndev->dma = -1;
cc3c080d 2544 ret = platform_get_irq(pdev, 0);
2545 if (ret < 0) {
86a74ff2
NI		 2546 ret = -ENODEV;
2547 goto out_release;
2548 }
cc3c080d 2549 ndev->irq = ret;
86a74ff2
NI		 2550
2551 SET_NETDEV_DEV(ndev, &pdev->dev);
2552
2553 /* Fill in the fields of the device structure with ethernet values. */
2554 ether_setup(ndev);
2555
2556 mdp = netdev_priv(ndev);
525b8075
YS		 2557 mdp->num_tx_ring = TX_RING_SIZE;
2558 mdp->num_rx_ring = RX_RING_SIZE;
d5e07e69
SS		 2559 mdp->addr = devm_ioremap_resource(&pdev->dev, res);
2560 if (IS_ERR(mdp->addr)) {
2561 ret = PTR_ERR(mdp->addr);
ae70644d
YS		 2562 goto out_release;
2563 }
2564
86a74ff2 2565 spin_lock_init(&mdp->lock);
bcd5149d
MD		 2566 mdp->pdev = pdev;
2567 pm_runtime_enable(&pdev->dev);
2568 pm_runtime_resume(&pdev->dev);
86a74ff2
NI		 2569
2570 /* get PHY ID */
71557a37 2571 mdp->phy_id = pd->phy;
e47c9052 2572 mdp->phy_interface = pd->phy_interface;
71557a37
YS		 2573 /* EDMAC endian */
2574 mdp->edmac_endian = pd->edmac_endian;
4923576b
YS		 2575 mdp->no_ether_link = pd->no_ether_link;
2576 mdp->ether_link_active_low = pd->ether_link_active_low;
4a55530f 2577 mdp->reg_offset = sh_eth_get_register_offset(pd->register_type);
86a74ff2 2578
380af9e3 2579 /* set cpu data */
589ebdef 2580 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data;
380af9e3
YS		 2581 sh_eth_set_default_cpu_data(mdp->cd);
2582
86a74ff2 2583 /* set function */
8f728d79
SS		 2584 if (mdp->cd->tsu)
2585 ndev->netdev_ops = &sh_eth_netdev_ops_tsu;
2586 else
2587 ndev->netdev_ops = &sh_eth_netdev_ops;
dc19e4e5 2588 SET_ETHTOOL_OPS(ndev, &sh_eth_ethtool_ops);
86a74ff2
NI		 2589 ndev->watchdog_timeo = TX_TIMEOUT;
2590
dc19e4e5
NI		 2591 /* debug message level */
2592 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
86a74ff2
NI		 2593
2594 /* read and set MAC address */
748031f9 2595 read_mac_address(ndev, pd->mac_addr);
ff6e7228
SS		 2596 if (!is_valid_ether_addr(ndev->dev_addr)) {
2597 dev_warn(&pdev->dev,
2598 "no valid MAC address supplied, using a random one.\n");
2599 eth_hw_addr_random(ndev);
2600 }
86a74ff2 2601
6ba88021
YS		 2602 /* ioremap the TSU registers */
2603 if (mdp->cd->tsu) {
2604 struct resource *rtsu;
2605 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
d5e07e69
SS		 2606 mdp->tsu_addr = devm_ioremap_resource(&pdev->dev, rtsu);
2607 if (IS_ERR(mdp->tsu_addr)) {
2608 ret = PTR_ERR(mdp->tsu_addr);
fc0c0900
SS		 2609 goto out_release;
2610 }
6743fe6d 2611 mdp->port = devno % 2;
f646968f 2612 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER;
6ba88021
YS		 2613 }
2614
150647fb
YS		 2615 /* initialize first or needed device */
2616 if (!devno || pd->needs_init) {
380af9e3
YS		 2617 if (mdp->cd->chip_reset)
2618 mdp->cd->chip_reset(ndev);
86a74ff2 2619
4986b996
YS		 2620 if (mdp->cd->tsu) {
2621 /* TSU init (Init only)*/
2622 sh_eth_tsu_init(mdp);
2623 }
86a74ff2
NI		 2624 }
2625
2626 /* network device register */
2627 ret = register_netdev(ndev);
2628 if (ret)
2629 goto out_release;
2630
2631 /* mdio bus init */
b3017e6a 2632 ret = sh_mdio_init(ndev, pdev->id, pd);
86a74ff2
NI		 2633 if (ret)
2634 goto out_unregister;
2635
25985edc 2636 /* print device information */
6cd9b49d
HS		 2637 pr_info("Base address at 0x%x, %pM, IRQ %d.\n",
2638 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
86a74ff2
NI		 2639
2640 platform_set_drvdata(pdev, ndev);
2641
2642 return ret;
2643
2644out_unregister:
2645 unregister_netdev(ndev);
2646
2647out_release:
2648 /* net_dev free */
2649 if (ndev)
2650 free_netdev(ndev);
2651
2652out:
2653 return ret;
2654}
2655
2656static int sh_eth_drv_remove(struct platform_device *pdev)
2657{
2658 struct net_device *ndev = platform_get_drvdata(pdev);
2659
2660 sh_mdio_release(ndev);
2661 unregister_netdev(ndev);
bcd5149d 2662 pm_runtime_disable(&pdev->dev);
86a74ff2 2663 free_netdev(ndev);
86a74ff2
NI		 2664
2665 return 0;
2666}
2667
540ad1b8 2668#ifdef CONFIG_PM
bcd5149d
MD		 2669static int sh_eth_runtime_nop(struct device *dev)
2670{
2671 /*
2672 * Runtime PM callback shared between ->runtime_suspend()
2673 * and ->runtime_resume(). Simply returns success.
2674 *
2675 * This driver re-initializes all registers after
2676 * pm_runtime_get_sync() anyway so there is no need
2677 * to save and restore registers here.
2678 */
2679 return 0;
2680}
2681
540ad1b8 2682static const struct dev_pm_ops sh_eth_dev_pm_ops = {
bcd5149d
MD		 2683 .runtime_suspend = sh_eth_runtime_nop,
2684 .runtime_resume = sh_eth_runtime_nop,
2685};
540ad1b8
NI		 2686#define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
2687#else
2688#define SH_ETH_PM_OPS NULL
2689#endif
bcd5149d 2690
afe391ad 2691static struct platform_device_id sh_eth_id_table[] = {
c18a79ab 2692 { "sh7619-ether", (kernel_ulong_t)&sh7619_data },
7bbe150d 2693 { "sh771x-ether", (kernel_ulong_t)&sh771x_data },
9c3beaab 2694 { "sh7724-ether", (kernel_ulong_t)&sh7724_data },
f5d12767 2695 { "sh7734-gether", (kernel_ulong_t)&sh7734_data },
24549e2a
SS		 2696 { "sh7757-ether", (kernel_ulong_t)&sh7757_data },
2697 { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga },
f5d12767 2698 { "sh7763-gether", (kernel_ulong_t)&sh7763_data },
e5c9b4cd 2699 { "r8a7740-gether", (kernel_ulong_t)&r8a7740_data },
589ebdef 2700 { "r8a777x-ether", (kernel_ulong_t)&r8a777x_data },
afe391ad
SS		 2701 { }
2702};
2703MODULE_DEVICE_TABLE(platform, sh_eth_id_table);
2704
86a74ff2
NI		 2705static struct platform_driver sh_eth_driver = {
2706 .probe = sh_eth_drv_probe,
2707 .remove = sh_eth_drv_remove,
afe391ad 2708 .id_table = sh_eth_id_table,
86a74ff2
NI		 2709 .driver = {
2710 .name = CARDNAME,
540ad1b8 2711 .pm = SH_ETH_PM_OPS,
86a74ff2
NI		 2712 },
2713};
2714
db62f684 2715module_platform_driver(sh_eth_driver);
86a74ff2
NI		 2716
2717MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
2718MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
2719MODULE_LICENSE("GPL v2");
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