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CommitLineData
128296fc 1/* SuperH Ethernet device driver
86a74ff2 2 *
966d6dbb 3 * Copyright (C) 2014 Renesas Electronics Corporation
f0e81fec 4 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu
b356e978
SS		 5 * Copyright (C) 2008-2014 Renesas Solutions Corp.
6 * Copyright (C) 2013-2014 Cogent Embedded, Inc.
702eca02 7 * Copyright (C) 2014 Codethink Limited
86a74ff2
NI		 8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms and conditions of the GNU General Public License,
11 * version 2, as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
86a74ff2
NI		 17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 */
21
0654011d
YS		 22#include <linux/module.h>
23#include <linux/kernel.h>
24#include <linux/spinlock.h>
6a27cded 25#include <linux/interrupt.h>
86a74ff2
NI		 26#include <linux/dma-mapping.h>
27#include <linux/etherdevice.h>
28#include <linux/delay.h>
29#include <linux/platform_device.h>
30#include <linux/mdio-bitbang.h>
31#include <linux/netdevice.h>
b356e978
SS		 32#include <linux/of.h>
33#include <linux/of_device.h>
34#include <linux/of_irq.h>
35#include <linux/of_net.h>
86a74ff2
NI		 36#include <linux/phy.h>
37#include <linux/cache.h>
38#include <linux/io.h>
bcd5149d 39#include <linux/pm_runtime.h>
5a0e3ad6 40#include <linux/slab.h>
dc19e4e5 41#include <linux/ethtool.h>
fdb37a7f 42#include <linux/if_vlan.h>
f0e81fec 43#include <linux/clk.h>
d4fa0e35 44#include <linux/sh_eth.h>
702eca02 45#include <linux/of_mdio.h>
86a74ff2
NI		 46
47#include "sh_eth.h"
48
dc19e4e5
NI		 49#define SH_ETH_DEF_MSG_ENABLE \
50 (NETIF_MSG_LINK | \
51 NETIF_MSG_TIMER | \
52 NETIF_MSG_RX_ERR| \
53 NETIF_MSG_TX_ERR)
54
c0013f6f
SS		 55static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
56 [EDSR] = 0x0000,
57 [EDMR] = 0x0400,
58 [EDTRR] = 0x0408,
59 [EDRRR] = 0x0410,
60 [EESR] = 0x0428,
61 [EESIPR] = 0x0430,
62 [TDLAR] = 0x0010,
63 [TDFAR] = 0x0014,
64 [TDFXR] = 0x0018,
65 [TDFFR] = 0x001c,
66 [RDLAR] = 0x0030,
67 [RDFAR] = 0x0034,
68 [RDFXR] = 0x0038,
69 [RDFFR] = 0x003c,
70 [TRSCER] = 0x0438,
71 [RMFCR] = 0x0440,
72 [TFTR] = 0x0448,
73 [FDR] = 0x0450,
74 [RMCR] = 0x0458,
75 [RPADIR] = 0x0460,
76 [FCFTR] = 0x0468,
77 [CSMR] = 0x04E4,
78
79 [ECMR] = 0x0500,
80 [ECSR] = 0x0510,
81 [ECSIPR] = 0x0518,
82 [PIR] = 0x0520,
83 [PSR] = 0x0528,
84 [PIPR] = 0x052c,
85 [RFLR] = 0x0508,
86 [APR] = 0x0554,
87 [MPR] = 0x0558,
88 [PFTCR] = 0x055c,
89 [PFRCR] = 0x0560,
90 [TPAUSER] = 0x0564,
91 [GECMR] = 0x05b0,
92 [BCULR] = 0x05b4,
93 [MAHR] = 0x05c0,
94 [MALR] = 0x05c8,
95 [TROCR] = 0x0700,
96 [CDCR] = 0x0708,
97 [LCCR] = 0x0710,
98 [CEFCR] = 0x0740,
99 [FRECR] = 0x0748,
100 [TSFRCR] = 0x0750,
101 [TLFRCR] = 0x0758,
102 [RFCR] = 0x0760,
103 [CERCR] = 0x0768,
104 [CEECR] = 0x0770,
105 [MAFCR] = 0x0778,
106 [RMII_MII] = 0x0790,
107
108 [ARSTR] = 0x0000,
109 [TSU_CTRST] = 0x0004,
110 [TSU_FWEN0] = 0x0010,
111 [TSU_FWEN1] = 0x0014,
112 [TSU_FCM] = 0x0018,
113 [TSU_BSYSL0] = 0x0020,
114 [TSU_BSYSL1] = 0x0024,
115 [TSU_PRISL0] = 0x0028,
116 [TSU_PRISL1] = 0x002c,
117 [TSU_FWSL0] = 0x0030,
118 [TSU_FWSL1] = 0x0034,
119 [TSU_FWSLC] = 0x0038,
120 [TSU_QTAG0] = 0x0040,
121 [TSU_QTAG1] = 0x0044,
122 [TSU_FWSR] = 0x0050,
123 [TSU_FWINMK] = 0x0054,
124 [TSU_ADQT0] = 0x0048,
125 [TSU_ADQT1] = 0x004c,
126 [TSU_VTAG0] = 0x0058,
127 [TSU_VTAG1] = 0x005c,
128 [TSU_ADSBSY] = 0x0060,
129 [TSU_TEN] = 0x0064,
130 [TSU_POST1] = 0x0070,
131 [TSU_POST2] = 0x0074,
132 [TSU_POST3] = 0x0078,
133 [TSU_POST4] = 0x007c,
134 [TSU_ADRH0] = 0x0100,
135 [TSU_ADRL0] = 0x0104,
136 [TSU_ADRH31] = 0x01f8,
137 [TSU_ADRL31] = 0x01fc,
138
139 [TXNLCR0] = 0x0080,
140 [TXALCR0] = 0x0084,
141 [RXNLCR0] = 0x0088,
142 [RXALCR0] = 0x008c,
143 [FWNLCR0] = 0x0090,
144 [FWALCR0] = 0x0094,
145 [TXNLCR1] = 0x00a0,
146 [TXALCR1] = 0x00a0,
147 [RXNLCR1] = 0x00a8,
148 [RXALCR1] = 0x00ac,
149 [FWNLCR1] = 0x00b0,
150 [FWALCR1] = 0x00b4,
151};
152
db893473
SH		 153static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
154 [EDSR] = 0x0000,
155 [EDMR] = 0x0400,
156 [EDTRR] = 0x0408,
157 [EDRRR] = 0x0410,
158 [EESR] = 0x0428,
159 [EESIPR] = 0x0430,
160 [TDLAR] = 0x0010,
161 [TDFAR] = 0x0014,
162 [TDFXR] = 0x0018,
163 [TDFFR] = 0x001c,
164 [RDLAR] = 0x0030,
165 [RDFAR] = 0x0034,
166 [RDFXR] = 0x0038,
167 [RDFFR] = 0x003c,
168 [TRSCER] = 0x0438,
169 [RMFCR] = 0x0440,
170 [TFTR] = 0x0448,
171 [FDR] = 0x0450,
172 [RMCR] = 0x0458,
173 [RPADIR] = 0x0460,
174 [FCFTR] = 0x0468,
175 [CSMR] = 0x04E4,
176
177 [ECMR] = 0x0500,
178 [RFLR] = 0x0508,
179 [ECSR] = 0x0510,
180 [ECSIPR] = 0x0518,
181 [PIR] = 0x0520,
182 [APR] = 0x0554,
183 [MPR] = 0x0558,
184 [PFTCR] = 0x055c,
185 [PFRCR] = 0x0560,
186 [TPAUSER] = 0x0564,
187 [MAHR] = 0x05c0,
188 [MALR] = 0x05c8,
189 [CEFCR] = 0x0740,
190 [FRECR] = 0x0748,
191 [TSFRCR] = 0x0750,
192 [TLFRCR] = 0x0758,
193 [RFCR] = 0x0760,
194 [MAFCR] = 0x0778,
195
196 [ARSTR] = 0x0000,
197 [TSU_CTRST] = 0x0004,
198 [TSU_VTAG0] = 0x0058,
199 [TSU_ADSBSY] = 0x0060,
200 [TSU_TEN] = 0x0064,
201 [TSU_ADRH0] = 0x0100,
202 [TSU_ADRL0] = 0x0104,
203 [TSU_ADRH31] = 0x01f8,
204 [TSU_ADRL31] = 0x01fc,
205
206 [TXNLCR0] = 0x0080,
207 [TXALCR0] = 0x0084,
208 [RXNLCR0] = 0x0088,
209 [RXALCR0] = 0x008C,
210};
211
a3f109bd
SS		 212static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
213 [ECMR] = 0x0300,
214 [RFLR] = 0x0308,
215 [ECSR] = 0x0310,
216 [ECSIPR] = 0x0318,
217 [PIR] = 0x0320,
218 [PSR] = 0x0328,
219 [RDMLR] = 0x0340,
220 [IPGR] = 0x0350,
221 [APR] = 0x0354,
222 [MPR] = 0x0358,
223 [RFCF] = 0x0360,
224 [TPAUSER] = 0x0364,
225 [TPAUSECR] = 0x0368,
226 [MAHR] = 0x03c0,
227 [MALR] = 0x03c8,
228 [TROCR] = 0x03d0,
229 [CDCR] = 0x03d4,
230 [LCCR] = 0x03d8,
231 [CNDCR] = 0x03dc,
232 [CEFCR] = 0x03e4,
233 [FRECR] = 0x03e8,
234 [TSFRCR] = 0x03ec,
235 [TLFRCR] = 0x03f0,
236 [RFCR] = 0x03f4,
237 [MAFCR] = 0x03f8,
238
239 [EDMR] = 0x0200,
240 [EDTRR] = 0x0208,
241 [EDRRR] = 0x0210,
242 [TDLAR] = 0x0218,
243 [RDLAR] = 0x0220,
244 [EESR] = 0x0228,
245 [EESIPR] = 0x0230,
246 [TRSCER] = 0x0238,
247 [RMFCR] = 0x0240,
248 [TFTR] = 0x0248,
249 [FDR] = 0x0250,
250 [RMCR] = 0x0258,
251 [TFUCR] = 0x0264,
252 [RFOCR] = 0x0268,
55754f19 253 [RMIIMODE] = 0x026c,
a3f109bd
SS		 254 [FCFTR] = 0x0270,
255 [TRIMD] = 0x027c,
256};
257
c0013f6f
SS		 258static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
259 [ECMR] = 0x0100,
260 [RFLR] = 0x0108,
261 [ECSR] = 0x0110,
262 [ECSIPR] = 0x0118,
263 [PIR] = 0x0120,
264 [PSR] = 0x0128,
265 [RDMLR] = 0x0140,
266 [IPGR] = 0x0150,
267 [APR] = 0x0154,
268 [MPR] = 0x0158,
269 [TPAUSER] = 0x0164,
270 [RFCF] = 0x0160,
271 [TPAUSECR] = 0x0168,
272 [BCFRR] = 0x016c,
273 [MAHR] = 0x01c0,
274 [MALR] = 0x01c8,
275 [TROCR] = 0x01d0,
276 [CDCR] = 0x01d4,
277 [LCCR] = 0x01d8,
278 [CNDCR] = 0x01dc,
279 [CEFCR] = 0x01e4,
280 [FRECR] = 0x01e8,
281 [TSFRCR] = 0x01ec,
282 [TLFRCR] = 0x01f0,
283 [RFCR] = 0x01f4,
284 [MAFCR] = 0x01f8,
285 [RTRATE] = 0x01fc,
286
287 [EDMR] = 0x0000,
288 [EDTRR] = 0x0008,
289 [EDRRR] = 0x0010,
290 [TDLAR] = 0x0018,
291 [RDLAR] = 0x0020,
292 [EESR] = 0x0028,
293 [EESIPR] = 0x0030,
294 [TRSCER] = 0x0038,
295 [RMFCR] = 0x0040,
296 [TFTR] = 0x0048,
297 [FDR] = 0x0050,
298 [RMCR] = 0x0058,
299 [TFUCR] = 0x0064,
300 [RFOCR] = 0x0068,
301 [FCFTR] = 0x0070,
302 [RPADIR] = 0x0078,
303 [TRIMD] = 0x007c,
304 [RBWAR] = 0x00c8,
305 [RDFAR] = 0x00cc,
306 [TBRAR] = 0x00d4,
307 [TDFAR] = 0x00d8,
308};
309
310static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
d8b0426a
SS		 311 [EDMR] = 0x0000,
312 [EDTRR] = 0x0004,
313 [EDRRR] = 0x0008,
314 [TDLAR] = 0x000c,
315 [RDLAR] = 0x0010,
316 [EESR] = 0x0014,
317 [EESIPR] = 0x0018,
318 [TRSCER] = 0x001c,
319 [RMFCR] = 0x0020,
320 [TFTR] = 0x0024,
321 [FDR] = 0x0028,
322 [RMCR] = 0x002c,
323 [EDOCR] = 0x0030,
324 [FCFTR] = 0x0034,
325 [RPADIR] = 0x0038,
326 [TRIMD] = 0x003c,
327 [RBWAR] = 0x0040,
328 [RDFAR] = 0x0044,
329 [TBRAR] = 0x004c,
330 [TDFAR] = 0x0050,
331
c0013f6f
SS		 332 [ECMR] = 0x0160,
333 [ECSR] = 0x0164,
334 [ECSIPR] = 0x0168,
335 [PIR] = 0x016c,
336 [MAHR] = 0x0170,
337 [MALR] = 0x0174,
338 [RFLR] = 0x0178,
339 [PSR] = 0x017c,
340 [TROCR] = 0x0180,
341 [CDCR] = 0x0184,
342 [LCCR] = 0x0188,
343 [CNDCR] = 0x018c,
344 [CEFCR] = 0x0194,
345 [FRECR] = 0x0198,
346 [TSFRCR] = 0x019c,
347 [TLFRCR] = 0x01a0,
348 [RFCR] = 0x01a4,
349 [MAFCR] = 0x01a8,
350 [IPGR] = 0x01b4,
351 [APR] = 0x01b8,
352 [MPR] = 0x01bc,
353 [TPAUSER] = 0x01c4,
354 [BCFR] = 0x01cc,
355
356 [ARSTR] = 0x0000,
357 [TSU_CTRST] = 0x0004,
358 [TSU_FWEN0] = 0x0010,
359 [TSU_FWEN1] = 0x0014,
360 [TSU_FCM] = 0x0018,
361 [TSU_BSYSL0] = 0x0020,
362 [TSU_BSYSL1] = 0x0024,
363 [TSU_PRISL0] = 0x0028,
364 [TSU_PRISL1] = 0x002c,
365 [TSU_FWSL0] = 0x0030,
366 [TSU_FWSL1] = 0x0034,
367 [TSU_FWSLC] = 0x0038,
368 [TSU_QTAGM0] = 0x0040,
369 [TSU_QTAGM1] = 0x0044,
370 [TSU_ADQT0] = 0x0048,
371 [TSU_ADQT1] = 0x004c,
372 [TSU_FWSR] = 0x0050,
373 [TSU_FWINMK] = 0x0054,
374 [TSU_ADSBSY] = 0x0060,
375 [TSU_TEN] = 0x0064,
376 [TSU_POST1] = 0x0070,
377 [TSU_POST2] = 0x0074,
378 [TSU_POST3] = 0x0078,
379 [TSU_POST4] = 0x007c,
380
381 [TXNLCR0] = 0x0080,
382 [TXALCR0] = 0x0084,
383 [RXNLCR0] = 0x0088,
384 [RXALCR0] = 0x008c,
385 [FWNLCR0] = 0x0090,
386 [FWALCR0] = 0x0094,
387 [TXNLCR1] = 0x00a0,
388 [TXALCR1] = 0x00a0,
389 [RXNLCR1] = 0x00a8,
390 [RXALCR1] = 0x00ac,
391 [FWNLCR1] = 0x00b0,
392 [FWALCR1] = 0x00b4,
393
394 [TSU_ADRH0] = 0x0100,
395 [TSU_ADRL0] = 0x0104,
396 [TSU_ADRL31] = 0x01fc,
397};
398
740c7f31
BH		 399static void sh_eth_rcv_snd_disable(struct net_device *ndev);
400static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev);
401
504c8ca5 402static bool sh_eth_is_gether(struct sh_eth_private *mdp)
dabdde9e 403{
504c8ca5 404 return mdp->reg_offset == sh_eth_offset_gigabit;
dabdde9e
NI		 405}
406
db893473
SH		 407static bool sh_eth_is_rz_fast_ether(struct sh_eth_private *mdp)
408{
409 return mdp->reg_offset == sh_eth_offset_fast_rz;
410}
411
8e994402 412static void sh_eth_select_mii(struct net_device *ndev)
5e7a76be
NI		 413{
414 u32 value = 0x0;
415 struct sh_eth_private *mdp = netdev_priv(ndev);
416
417 switch (mdp->phy_interface) {
418 case PHY_INTERFACE_MODE_GMII:
419 value = 0x2;
420 break;
421 case PHY_INTERFACE_MODE_MII:
422 value = 0x1;
423 break;
424 case PHY_INTERFACE_MODE_RMII:
425 value = 0x0;
426 break;
427 default:
f75f14ec
SS		 428 netdev_warn(ndev,
429 "PHY interface mode was not setup. Set to MII.\n");
5e7a76be
NI		 430 value = 0x1;
431 break;
432 }
433
434 sh_eth_write(ndev, value, RMII_MII);
435}
5e7a76be 436
8e994402 437static void sh_eth_set_duplex(struct net_device *ndev)
65ac8851
YS		 438{
439 struct sh_eth_private *mdp = netdev_priv(ndev);
65ac8851
YS		 440
441 if (mdp->duplex) /* Full */
4a55530f 442 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
65ac8851 443 else /* Half */
4a55530f 444 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
65ac8851
YS		 445}
446
04b0ed2a 447/* There is CPU dependent code */
589ebdef 448static void sh_eth_set_rate_r8a777x(struct net_device *ndev)
65ac8851
YS		 449{
450 struct sh_eth_private *mdp = netdev_priv(ndev);
d0418bb7 451
a3f109bd
SS		 452 switch (mdp->speed) {
453 case 10: /* 10BASE */
454 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_ELB, ECMR);
455 break;
456 case 100:/* 100BASE */
457 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_ELB, ECMR);
458 break;
459 default:
460 break;
461 }
462}
463
674853b2 464/* R8A7778/9 */
589ebdef 465static struct sh_eth_cpu_data r8a777x_data = {
a3f109bd 466 .set_duplex = sh_eth_set_duplex,
589ebdef 467 .set_rate = sh_eth_set_rate_r8a777x,
a3f109bd 468
a3153d8c
SS		 469 .register_type = SH_ETH_REG_FAST_RCAR,
470
a3f109bd
SS		 471 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
472 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
473 .eesipr_value = 0x01ff009f,
474
475 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
ca8c3585
SS		 476 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
477 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
478 EESR_ECI,
d407bc02 479 .fdr_value = 0x00000f0f,
a3f109bd
SS		 480
481 .apr = 1,
482 .mpr = 1,
483 .tpauser = 1,
484 .hw_swap = 1,
485};
a3f109bd 486
94a12b15
SS		 487/* R8A7790/1 */
488static struct sh_eth_cpu_data r8a779x_data = {
e18dbf7e
SH		 489 .set_duplex = sh_eth_set_duplex,
490 .set_rate = sh_eth_set_rate_r8a777x,
491
a3153d8c
SS		 492 .register_type = SH_ETH_REG_FAST_RCAR,
493
e18dbf7e
SH		 494 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
495 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
496 .eesipr_value = 0x01ff009f,
497
498 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
ba361cb3
LP		 499 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
500 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
501 EESR_ECI,
d407bc02 502 .fdr_value = 0x00000f0f,
e18dbf7e 503
01fbd3f5
GU		 504 .trscer_err_mask = DESC_I_RINT8,
505
e18dbf7e
SH		 506 .apr = 1,
507 .mpr = 1,
508 .tpauser = 1,
509 .hw_swap = 1,
510 .rmiimode = 1,
fd9af07c 511 .shift_rd0 = 1,
e18dbf7e
SH		 512};
513
9c3beaab 514static void sh_eth_set_rate_sh7724(struct net_device *ndev)
a3f109bd
SS		 515{
516 struct sh_eth_private *mdp = netdev_priv(ndev);
65ac8851
YS		 517
518 switch (mdp->speed) {
519 case 10: /* 10BASE */
a3f109bd 520 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_RTM, ECMR);
65ac8851
YS		 521 break;
522 case 100:/* 100BASE */
a3f109bd 523 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_RTM, ECMR);
65ac8851
YS		 524 break;
525 default:
526 break;
527 }
528}
529
530/* SH7724 */
9c3beaab 531static struct sh_eth_cpu_data sh7724_data = {
65ac8851 532 .set_duplex = sh_eth_set_duplex,
9c3beaab 533 .set_rate = sh_eth_set_rate_sh7724,
65ac8851 534
a3153d8c
SS		 535 .register_type = SH_ETH_REG_FAST_SH4,
536
65ac8851
YS		 537 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
538 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
a80c3de7 539 .eesipr_value = 0x01ff009f,
65ac8851
YS		 540
541 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
ca8c3585
SS		 542 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
543 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
544 EESR_ECI,
65ac8851
YS		 545
546 .apr = 1,
547 .mpr = 1,
548 .tpauser = 1,
549 .hw_swap = 1,
503914cf
MD		 550 .rpadir = 1,
551 .rpadir_value = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
65ac8851 552};
5cee1d37 553
24549e2a 554static void sh_eth_set_rate_sh7757(struct net_device *ndev)
f29a3d04
YS		 555{
556 struct sh_eth_private *mdp = netdev_priv(ndev);
f29a3d04
YS		 557
558 switch (mdp->speed) {
559 case 10: /* 10BASE */
4a55530f 560 sh_eth_write(ndev, 0, RTRATE);
f29a3d04
YS		 561 break;
562 case 100:/* 100BASE */
4a55530f 563 sh_eth_write(ndev, 1, RTRATE);
f29a3d04
YS		 564 break;
565 default:
566 break;
567 }
568}
569
570/* SH7757 */
24549e2a
SS		 571static struct sh_eth_cpu_data sh7757_data = {
572 .set_duplex = sh_eth_set_duplex,
573 .set_rate = sh_eth_set_rate_sh7757,
f29a3d04 574
a3153d8c
SS		 575 .register_type = SH_ETH_REG_FAST_SH4,
576
f29a3d04 577 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
f29a3d04
YS		 578
579 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
ca8c3585
SS		 580 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
581 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
582 EESR_ECI,
f29a3d04 583
5b3dfd13 584 .irq_flags = IRQF_SHARED,
f29a3d04
YS		 585 .apr = 1,
586 .mpr = 1,
587 .tpauser = 1,
588 .hw_swap = 1,
589 .no_ade = 1,
2e98e797
YS		 590 .rpadir = 1,
591 .rpadir_value = 2 << 16,
f29a3d04 592};
65ac8851 593
e403d295 594#define SH_GIGA_ETH_BASE 0xfee00000UL
8fcd4961
YS		 595#define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
596#define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
597static void sh_eth_chip_reset_giga(struct net_device *ndev)
598{
599 int i;
0799c2d6 600 u32 mahr[2], malr[2];
8fcd4961
YS		 601
602 /* save MAHR and MALR */
603 for (i = 0; i < 2; i++) {
ae70644d
YS		 604 malr[i] = ioread32((void *)GIGA_MALR(i));
605 mahr[i] = ioread32((void *)GIGA_MAHR(i));
8fcd4961
YS		 606 }
607
608 /* reset device */
ae70644d 609 iowrite32(ARSTR_ARSTR, (void *)(SH_GIGA_ETH_BASE + 0x1800));
8fcd4961
YS		 610 mdelay(1);
611
612 /* restore MAHR and MALR */
613 for (i = 0; i < 2; i++) {
ae70644d
YS		 614 iowrite32(malr[i], (void *)GIGA_MALR(i));
615 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
8fcd4961
YS		 616 }
617}
618
8fcd4961
YS		 619static void sh_eth_set_rate_giga(struct net_device *ndev)
620{
621 struct sh_eth_private *mdp = netdev_priv(ndev);
622
623 switch (mdp->speed) {
624 case 10: /* 10BASE */
625 sh_eth_write(ndev, 0x00000000, GECMR);
626 break;
627 case 100:/* 100BASE */
628 sh_eth_write(ndev, 0x00000010, GECMR);
629 break;
630 case 1000: /* 1000BASE */
631 sh_eth_write(ndev, 0x00000020, GECMR);
632 break;
633 default:
634 break;
635 }
636}
637
638/* SH7757(GETHERC) */
24549e2a 639static struct sh_eth_cpu_data sh7757_data_giga = {
8fcd4961 640 .chip_reset = sh_eth_chip_reset_giga,
04b0ed2a 641 .set_duplex = sh_eth_set_duplex,
8fcd4961
YS		 642 .set_rate = sh_eth_set_rate_giga,
643
a3153d8c
SS		 644 .register_type = SH_ETH_REG_GIGABIT,
645
8fcd4961
YS		 646 .ecsr_value = ECSR_ICD | ECSR_MPD,
647 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
648 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
649
650 .tx_check = EESR_TC1 | EESR_FTC,
ca8c3585
SS		 651 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
652 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
653 EESR_TDE | EESR_ECI,
8fcd4961 654 .fdr_value = 0x0000072f,
8fcd4961 655
5b3dfd13 656 .irq_flags = IRQF_SHARED,
8fcd4961
YS		 657 .apr = 1,
658 .mpr = 1,
659 .tpauser = 1,
660 .bculr = 1,
661 .hw_swap = 1,
662 .rpadir = 1,
663 .rpadir_value = 2 << 16,
664 .no_trimd = 1,
665 .no_ade = 1,
3acbc971 666 .tsu = 1,
8fcd4961
YS		 667};
668
380af9e3
YS		 669static void sh_eth_chip_reset(struct net_device *ndev)
670{
4986b996
YS		 671 struct sh_eth_private *mdp = netdev_priv(ndev);
672
380af9e3 673 /* reset device */
4986b996 674 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
380af9e3
YS		 675 mdelay(1);
676}
677
f5d12767 678static void sh_eth_set_rate_gether(struct net_device *ndev)
380af9e3
YS		 679{
680 struct sh_eth_private *mdp = netdev_priv(ndev);
380af9e3
YS		 681
682 switch (mdp->speed) {
683 case 10: /* 10BASE */
4a55530f 684 sh_eth_write(ndev, GECMR_10, GECMR);
380af9e3
YS		 685 break;
686 case 100:/* 100BASE */
4a55530f 687 sh_eth_write(ndev, GECMR_100, GECMR);
380af9e3
YS		 688 break;
689 case 1000: /* 1000BASE */
4a55530f 690 sh_eth_write(ndev, GECMR_1000, GECMR);
380af9e3
YS		 691 break;
692 default:
693 break;
694 }
695}
696
f5d12767
SS		 697/* SH7734 */
698static struct sh_eth_cpu_data sh7734_data = {
380af9e3
YS		 699 .chip_reset = sh_eth_chip_reset,
700 .set_duplex = sh_eth_set_duplex,
f5d12767
SS		 701 .set_rate = sh_eth_set_rate_gether,
702
a3153d8c
SS		 703 .register_type = SH_ETH_REG_GIGABIT,
704
f5d12767
SS		 705 .ecsr_value = ECSR_ICD | ECSR_MPD,
706 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
707 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
708
709 .tx_check = EESR_TC1 | EESR_FTC,
ca8c3585
SS		 710 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
711 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
712 EESR_TDE | EESR_ECI,
f5d12767
SS		 713
714 .apr = 1,
715 .mpr = 1,
716 .tpauser = 1,
717 .bculr = 1,
718 .hw_swap = 1,
719 .no_trimd = 1,
720 .no_ade = 1,
721 .tsu = 1,
722 .hw_crc = 1,
723 .select_mii = 1,
724};
725
726/* SH7763 */
727static struct sh_eth_cpu_data sh7763_data = {
728 .chip_reset = sh_eth_chip_reset,
729 .set_duplex = sh_eth_set_duplex,
730 .set_rate = sh_eth_set_rate_gether,
380af9e3 731
a3153d8c
SS		 732 .register_type = SH_ETH_REG_GIGABIT,
733
380af9e3
YS		 734 .ecsr_value = ECSR_ICD | ECSR_MPD,
735 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
736 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
737
738 .tx_check = EESR_TC1 | EESR_FTC,
128296fc
SS		 739 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
740 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
380af9e3 741 EESR_ECI,
380af9e3
YS		 742
743 .apr = 1,
744 .mpr = 1,
745 .tpauser = 1,
746 .bculr = 1,
747 .hw_swap = 1,
380af9e3
YS		 748 .no_trimd = 1,
749 .no_ade = 1,
4986b996 750 .tsu = 1,
5b3dfd13 751 .irq_flags = IRQF_SHARED,
380af9e3
YS		 752};
753
e5c9b4cd 754static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
73a0d907
YS		 755{
756 struct sh_eth_private *mdp = netdev_priv(ndev);
73a0d907
YS		 757
758 /* reset device */
759 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
760 mdelay(1);
761
5e7a76be 762 sh_eth_select_mii(ndev);
73a0d907
YS		 763}
764
73a0d907 765/* R8A7740 */
e5c9b4cd
SS		 766static struct sh_eth_cpu_data r8a7740_data = {
767 .chip_reset = sh_eth_chip_reset_r8a7740,
73a0d907 768 .set_duplex = sh_eth_set_duplex,
e5c9b4cd 769 .set_rate = sh_eth_set_rate_gether,
73a0d907 770
a3153d8c
SS		 771 .register_type = SH_ETH_REG_GIGABIT,
772
73a0d907
YS		 773 .ecsr_value = ECSR_ICD | ECSR_MPD,
774 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
775 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
776
777 .tx_check = EESR_TC1 | EESR_FTC,
ca8c3585
SS		 778 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
779 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
780 EESR_TDE | EESR_ECI,
cc23528d 781 .fdr_value = 0x0000070f,
73a0d907
YS		 782
783 .apr = 1,
784 .mpr = 1,
785 .tpauser = 1,
786 .bculr = 1,
787 .hw_swap = 1,
cc23528d
SH		 788 .rpadir = 1,
789 .rpadir_value = 2 << 16,
73a0d907
YS		 790 .no_trimd = 1,
791 .no_ade = 1,
792 .tsu = 1,
5e7a76be 793 .select_mii = 1,
ac8025a6 794 .shift_rd0 = 1,
73a0d907
YS		 795};
796
db893473
SH		 797/* R7S72100 */
798static struct sh_eth_cpu_data r7s72100_data = {
799 .chip_reset = sh_eth_chip_reset,
800 .set_duplex = sh_eth_set_duplex,
801
802 .register_type = SH_ETH_REG_FAST_RZ,
803
804 .ecsr_value = ECSR_ICD,
805 .ecsipr_value = ECSIPR_ICDIP,
806 .eesipr_value = 0xff7f009f,
807
808 .tx_check = EESR_TC1 | EESR_FTC,
809 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
810 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
811 EESR_TDE | EESR_ECI,
812 .fdr_value = 0x0000070f,
db893473
SH		 813
814 .no_psr = 1,
815 .apr = 1,
816 .mpr = 1,
817 .tpauser = 1,
818 .hw_swap = 1,
819 .rpadir = 1,
820 .rpadir_value = 2 << 16,
821 .no_trimd = 1,
822 .no_ade = 1,
823 .hw_crc = 1,
824 .tsu = 1,
825 .shift_rd0 = 1,
826};
827
c18a79ab 828static struct sh_eth_cpu_data sh7619_data = {
a3153d8c
SS		 829 .register_type = SH_ETH_REG_FAST_SH3_SH2,
830
380af9e3
YS		 831 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
832
833 .apr = 1,
834 .mpr = 1,
835 .tpauser = 1,
836 .hw_swap = 1,
837};
7bbe150d
SS		 838
839static struct sh_eth_cpu_data sh771x_data = {
a3153d8c
SS		 840 .register_type = SH_ETH_REG_FAST_SH3_SH2,
841
380af9e3 842 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
4986b996 843 .tsu = 1,
380af9e3 844};
380af9e3
YS		 845
846static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
847{
848 if (!cd->ecsr_value)
849 cd->ecsr_value = DEFAULT_ECSR_INIT;
850
851 if (!cd->ecsipr_value)
852 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
853
854 if (!cd->fcftr_value)
128296fc 855 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF |
380af9e3
YS		 856 DEFAULT_FIFO_F_D_RFD;
857
858 if (!cd->fdr_value)
859 cd->fdr_value = DEFAULT_FDR_INIT;
860
380af9e3
YS		 861 if (!cd->tx_check)
862 cd->tx_check = DEFAULT_TX_CHECK;
863
864 if (!cd->eesr_err_check)
865 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
b284fbe3
NI		 866
867 if (!cd->trscer_err_mask)
868 cd->trscer_err_mask = DEFAULT_TRSCER_ERR_MASK;
380af9e3
YS		 869}
870
5cee1d37
NI		 871static int sh_eth_check_reset(struct net_device *ndev)
872{
873 int ret = 0;
874 int cnt = 100;
875
876 while (cnt > 0) {
877 if (!(sh_eth_read(ndev, EDMR) & 0x3))
878 break;
879 mdelay(1);
880 cnt--;
881 }
9f8c4265 882 if (cnt <= 0) {
f75f14ec 883 netdev_err(ndev, "Device reset failed\n");
5cee1d37
NI		 884 ret = -ETIMEDOUT;
885 }
886 return ret;
380af9e3 887}
dabdde9e
NI		 888
889static int sh_eth_reset(struct net_device *ndev)
890{
891 struct sh_eth_private *mdp = netdev_priv(ndev);
892 int ret = 0;
893
db893473 894 if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp)) {
dabdde9e
NI		 895 sh_eth_write(ndev, EDSR_ENALL, EDSR);
896 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER,
897 EDMR);
898
899 ret = sh_eth_check_reset(ndev);
900 if (ret)
f738a13d 901 return ret;
dabdde9e
NI		 902
903 /* Table Init */
904 sh_eth_write(ndev, 0x0, TDLAR);
905 sh_eth_write(ndev, 0x0, TDFAR);
906 sh_eth_write(ndev, 0x0, TDFXR);
907 sh_eth_write(ndev, 0x0, TDFFR);
908 sh_eth_write(ndev, 0x0, RDLAR);
909 sh_eth_write(ndev, 0x0, RDFAR);
910 sh_eth_write(ndev, 0x0, RDFXR);
911 sh_eth_write(ndev, 0x0, RDFFR);
912
913 /* Reset HW CRC register */
914 if (mdp->cd->hw_crc)
915 sh_eth_write(ndev, 0x0, CSMR);
916
917 /* Select MII mode */
918 if (mdp->cd->select_mii)
919 sh_eth_select_mii(ndev);
920 } else {
921 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER,
922 EDMR);
923 mdelay(3);
924 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER,
925 EDMR);
926 }
927
dabdde9e
NI		 928 return ret;
929}
380af9e3 930
380af9e3
YS		 931static void sh_eth_set_receive_align(struct sk_buff *skb)
932{
4d6a949c 933 uintptr_t reserve = (uintptr_t)skb->data & (SH_ETH_RX_ALIGN - 1);
380af9e3 934
380af9e3 935 if (reserve)
4d6a949c 936 skb_reserve(skb, SH_ETH_RX_ALIGN - reserve);
380af9e3 937}
380af9e3
YS		 938
939
71557a37
YS		 940/* CPU <-> EDMAC endian convert */
941static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x)
942{
943 switch (mdp->edmac_endian) {
944 case EDMAC_LITTLE_ENDIAN:
945 return cpu_to_le32(x);
946 case EDMAC_BIG_ENDIAN:
947 return cpu_to_be32(x);
948 }
949 return x;
950}
951
952static inline __u32 edmac_to_cpu(struct sh_eth_private *mdp, u32 x)
953{
954 switch (mdp->edmac_endian) {
955 case EDMAC_LITTLE_ENDIAN:
956 return le32_to_cpu(x);
957 case EDMAC_BIG_ENDIAN:
958 return be32_to_cpu(x);
959 }
960 return x;
961}
962
128296fc 963/* Program the hardware MAC address from dev->dev_addr. */
86a74ff2
NI		 964static void update_mac_address(struct net_device *ndev)
965{
4a55530f 966 sh_eth_write(ndev,
128296fc
SS		 967 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
968 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
4a55530f 969 sh_eth_write(ndev,
128296fc 970 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
86a74ff2
NI		 971}
972
128296fc 973/* Get MAC address from SuperH MAC address register
86a74ff2
NI		 974 *
975 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
976 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
977 * When you want use this device, you must set MAC address in bootloader.
978 *
979 */
748031f9 980static void read_mac_address(struct net_device *ndev, unsigned char *mac)
86a74ff2 981{
748031f9 982 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
d458cdf7 983 memcpy(ndev->dev_addr, mac, ETH_ALEN);
748031f9 984 } else {
4a55530f
YS		 985 ndev->dev_addr[0] = (sh_eth_read(ndev, MAHR) >> 24);
986 ndev->dev_addr[1] = (sh_eth_read(ndev, MAHR) >> 16) & 0xFF;
987 ndev->dev_addr[2] = (sh_eth_read(ndev, MAHR) >> 8) & 0xFF;
988 ndev->dev_addr[3] = (sh_eth_read(ndev, MAHR) & 0xFF);
989 ndev->dev_addr[4] = (sh_eth_read(ndev, MALR) >> 8) & 0xFF;
990 ndev->dev_addr[5] = (sh_eth_read(ndev, MALR) & 0xFF);
748031f9 991 }
86a74ff2
NI		 992}
993
0799c2d6 994static u32 sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
c5ed5368 995{
db893473 996 if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp))
c5ed5368
YS		 997 return EDTRR_TRNS_GETHER;
998 else
999 return EDTRR_TRNS_ETHER;
1000}
1001
86a74ff2 1002struct bb_info {
ae70644d 1003 void (*set_gate)(void *addr);
86a74ff2 1004 struct mdiobb_ctrl ctrl;
ae70644d 1005 void *addr;
86a74ff2
NI		 1006 u32 mmd_msk;/* MMD */
1007 u32 mdo_msk;
1008 u32 mdi_msk;
1009 u32 mdc_msk;
1010};
1011
1012/* PHY bit set */
ae70644d 1013static void bb_set(void *addr, u32 msk)
86a74ff2 1014{
ae70644d 1015 iowrite32(ioread32(addr) | msk, addr);
86a74ff2
NI		 1016}
1017
1018/* PHY bit clear */
ae70644d 1019static void bb_clr(void *addr, u32 msk)
86a74ff2 1020{
ae70644d 1021 iowrite32((ioread32(addr) & ~msk), addr);
86a74ff2
NI		 1022}
1023
1024/* PHY bit read */
ae70644d 1025static int bb_read(void *addr, u32 msk)
86a74ff2 1026{
ae70644d 1027 return (ioread32(addr) & msk) != 0;
86a74ff2
NI		 1028}
1029
1030/* Data I/O pin control */
1031static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1032{
1033 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
b3017e6a
YS		 1034
1035 if (bitbang->set_gate)
1036 bitbang->set_gate(bitbang->addr);
1037
86a74ff2
NI		 1038 if (bit)
1039 bb_set(bitbang->addr, bitbang->mmd_msk);
1040 else
1041 bb_clr(bitbang->addr, bitbang->mmd_msk);
1042}
1043
1044/* Set bit data*/
1045static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
1046{
1047 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1048
b3017e6a
YS		 1049 if (bitbang->set_gate)
1050 bitbang->set_gate(bitbang->addr);
1051
86a74ff2
NI		 1052 if (bit)
1053 bb_set(bitbang->addr, bitbang->mdo_msk);
1054 else
1055 bb_clr(bitbang->addr, bitbang->mdo_msk);
1056}
1057
1058/* Get bit data*/
1059static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
1060{
1061 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
b3017e6a
YS		 1062
1063 if (bitbang->set_gate)
1064 bitbang->set_gate(bitbang->addr);
1065
86a74ff2
NI		 1066 return bb_read(bitbang->addr, bitbang->mdi_msk);
1067}
1068
1069/* MDC pin control */
1070static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1071{
1072 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1073
b3017e6a
YS		 1074 if (bitbang->set_gate)
1075 bitbang->set_gate(bitbang->addr);
1076
86a74ff2
NI		 1077 if (bit)
1078 bb_set(bitbang->addr, bitbang->mdc_msk);
1079 else
1080 bb_clr(bitbang->addr, bitbang->mdc_msk);
1081}
1082
1083/* mdio bus control struct */
1084static struct mdiobb_ops bb_ops = {
1085 .owner = THIS_MODULE,
1086 .set_mdc = sh_mdc_ctrl,
1087 .set_mdio_dir = sh_mmd_ctrl,
1088 .set_mdio_data = sh_set_mdio,
1089 .get_mdio_data = sh_get_mdio,
1090};
1091
86a74ff2
NI		 1092/* free skb and descriptor buffer */
1093static void sh_eth_ring_free(struct net_device *ndev)
1094{
1095 struct sh_eth_private *mdp = netdev_priv(ndev);
1096 int i;
1097
1098 /* Free Rx skb ringbuffer */
1099 if (mdp->rx_skbuff) {
179d80af
SS		 1100 for (i = 0; i < mdp->num_rx_ring; i++)
1101 dev_kfree_skb(mdp->rx_skbuff[i]);
86a74ff2
NI		 1102 }
1103 kfree(mdp->rx_skbuff);
91c77550 1104 mdp->rx_skbuff = NULL;
86a74ff2
NI		 1105
1106 /* Free Tx skb ringbuffer */
1107 if (mdp->tx_skbuff) {
179d80af
SS		 1108 for (i = 0; i < mdp->num_tx_ring; i++)
1109 dev_kfree_skb(mdp->tx_skbuff[i]);
86a74ff2
NI		 1110 }
1111 kfree(mdp->tx_skbuff);
91c77550 1112 mdp->tx_skbuff = NULL;
86a74ff2
NI		 1113}
1114
1115/* format skb and descriptor buffer */
1116static void sh_eth_ring_format(struct net_device *ndev)
1117{
1118 struct sh_eth_private *mdp = netdev_priv(ndev);
1119 int i;
1120 struct sk_buff *skb;
1121 struct sh_eth_rxdesc *rxdesc = NULL;
1122 struct sh_eth_txdesc *txdesc = NULL;
525b8075
YS		 1123 int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
1124 int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
4d6a949c 1125 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN - 1;
52b9fa36 1126 dma_addr_t dma_addr;
86a74ff2 1127
128296fc
SS		 1128 mdp->cur_rx = 0;
1129 mdp->cur_tx = 0;
1130 mdp->dirty_rx = 0;
1131 mdp->dirty_tx = 0;
86a74ff2
NI		 1132
1133 memset(mdp->rx_ring, 0, rx_ringsize);
1134
1135 /* build Rx ring buffer */
525b8075 1136 for (i = 0; i < mdp->num_rx_ring; i++) {
86a74ff2
NI		 1137 /* skb */
1138 mdp->rx_skbuff[i] = NULL;
4d6a949c 1139 skb = netdev_alloc_skb(ndev, skbuff_size);
86a74ff2
NI		 1140 if (skb == NULL)
1141 break;
380af9e3
YS		 1142 sh_eth_set_receive_align(skb);
1143
86a74ff2
NI		 1144 /* RX descriptor */
1145 rxdesc = &mdp->rx_ring[i];
4d6a949c
MK		 1146 /* The size of the buffer is a multiple of 16 bytes. */
1147 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
52b9fa36
BH		 1148 dma_addr = dma_map_single(&ndev->dev, skb->data,
1149 rxdesc->buffer_length,
1150 DMA_FROM_DEVICE);
1151 if (dma_mapping_error(&ndev->dev, dma_addr)) {
1152 kfree_skb(skb);
1153 break;
1154 }
1155 mdp->rx_skbuff[i] = skb;
1156 rxdesc->addr = dma_addr;
71557a37 1157 rxdesc->status = cpu_to_edmac(mdp, RD_RACT | RD_RFP);
86a74ff2 1158
b0ca2a21
NI		 1159 /* Rx descriptor address set */
1160 if (i == 0) {
4a55530f 1161 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
db893473
SH		 1162 if (sh_eth_is_gether(mdp) ||
1163 sh_eth_is_rz_fast_ether(mdp))
c5ed5368 1164 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
b0ca2a21 1165 }
86a74ff2
NI		 1166 }
1167
525b8075 1168 mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
86a74ff2
NI		 1169
1170 /* Mark the last entry as wrapping the ring. */
71557a37 1171 rxdesc->status |= cpu_to_edmac(mdp, RD_RDEL);
86a74ff2
NI		 1172
1173 memset(mdp->tx_ring, 0, tx_ringsize);
1174
1175 /* build Tx ring buffer */
525b8075 1176 for (i = 0; i < mdp->num_tx_ring; i++) {
86a74ff2
NI		 1177 mdp->tx_skbuff[i] = NULL;
1178 txdesc = &mdp->tx_ring[i];
71557a37 1179 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
86a74ff2 1180 txdesc->buffer_length = 0;
b0ca2a21 1181 if (i == 0) {
71557a37 1182 /* Tx descriptor address set */
4a55530f 1183 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
db893473
SH		 1184 if (sh_eth_is_gether(mdp) ||
1185 sh_eth_is_rz_fast_ether(mdp))
c5ed5368 1186 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
b0ca2a21 1187 }
86a74ff2
NI		 1188 }
1189
71557a37 1190 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
86a74ff2
NI		 1191}
1192
1193/* Get skb and descriptor buffer */
1194static int sh_eth_ring_init(struct net_device *ndev)
1195{
1196 struct sh_eth_private *mdp = netdev_priv(ndev);
1197 int rx_ringsize, tx_ringsize, ret = 0;
1198
128296fc 1199 /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
86a74ff2
NI		 1200 * card needs room to do 8 byte alignment, +2 so we can reserve
1201 * the first 2 bytes, and +16 gets room for the status word from the
1202 * card.
1203 */
1204 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
1205 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
503914cf
MD		 1206 if (mdp->cd->rpadir)
1207 mdp->rx_buf_sz += NET_IP_ALIGN;
86a74ff2
NI		 1208
1209 /* Allocate RX and TX skb rings */
b2adaca9
JP		 1210 mdp->rx_skbuff = kmalloc_array(mdp->num_rx_ring,
1211 sizeof(*mdp->rx_skbuff), GFP_KERNEL);
86a74ff2 1212 if (!mdp->rx_skbuff) {
86a74ff2
NI		 1213 ret = -ENOMEM;
1214 return ret;
1215 }
1216
b2adaca9
JP		 1217 mdp->tx_skbuff = kmalloc_array(mdp->num_tx_ring,
1218 sizeof(*mdp->tx_skbuff), GFP_KERNEL);
86a74ff2 1219 if (!mdp->tx_skbuff) {
86a74ff2
NI		 1220 ret = -ENOMEM;
1221 goto skb_ring_free;
1222 }
1223
1224 /* Allocate all Rx descriptors. */
525b8075 1225 rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
86a74ff2 1226 mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
d0320f75 1227 GFP_KERNEL);
86a74ff2 1228 if (!mdp->rx_ring) {
86a74ff2
NI		 1229 ret = -ENOMEM;
1230 goto desc_ring_free;
1231 }
1232
1233 mdp->dirty_rx = 0;
1234
1235 /* Allocate all Tx descriptors. */
525b8075 1236 tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
86a74ff2 1237 mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
d0320f75 1238 GFP_KERNEL);
86a74ff2 1239 if (!mdp->tx_ring) {
86a74ff2
NI		 1240 ret = -ENOMEM;
1241 goto desc_ring_free;
1242 }
1243 return ret;
1244
1245desc_ring_free:
1246 /* free DMA buffer */
1247 dma_free_coherent(NULL, rx_ringsize, mdp->rx_ring, mdp->rx_desc_dma);
1248
1249skb_ring_free:
1250 /* Free Rx and Tx skb ring buffer */
1251 sh_eth_ring_free(ndev);
91c77550
YS		 1252 mdp->tx_ring = NULL;
1253 mdp->rx_ring = NULL;
86a74ff2
NI		 1254
1255 return ret;
1256}
1257
91c77550
YS		 1258static void sh_eth_free_dma_buffer(struct sh_eth_private *mdp)
1259{
1260 int ringsize;
1261
1262 if (mdp->rx_ring) {
525b8075 1263 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
91c77550
YS		 1264 dma_free_coherent(NULL, ringsize, mdp->rx_ring,
1265 mdp->rx_desc_dma);
1266 mdp->rx_ring = NULL;
1267 }
1268
1269 if (mdp->tx_ring) {
525b8075 1270 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
91c77550
YS		 1271 dma_free_coherent(NULL, ringsize, mdp->tx_ring,
1272 mdp->tx_desc_dma);
1273 mdp->tx_ring = NULL;
1274 }
1275}
1276
525b8075 1277static int sh_eth_dev_init(struct net_device *ndev, bool start)
86a74ff2
NI		 1278{
1279 int ret = 0;
1280 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 1281 u32 val;
1282
1283 /* Soft Reset */
5cee1d37
NI		 1284 ret = sh_eth_reset(ndev);
1285 if (ret)
f738a13d 1286 return ret;
86a74ff2 1287
55754f19
SH		 1288 if (mdp->cd->rmiimode)
1289 sh_eth_write(ndev, 0x1, RMIIMODE);
1290
b0ca2a21
NI		 1291 /* Descriptor format */
1292 sh_eth_ring_format(ndev);
380af9e3 1293 if (mdp->cd->rpadir)
4a55530f 1294 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
86a74ff2
NI		 1295
1296 /* all sh_eth int mask */
4a55530f 1297 sh_eth_write(ndev, 0, EESIPR);
86a74ff2 1298
10b9194f 1299#if defined(__LITTLE_ENDIAN)
380af9e3 1300 if (mdp->cd->hw_swap)
4a55530f 1301 sh_eth_write(ndev, EDMR_EL, EDMR);
380af9e3 1302 else
b0ca2a21 1303#endif
4a55530f 1304 sh_eth_write(ndev, 0, EDMR);
86a74ff2 1305
b0ca2a21 1306 /* FIFO size set */
4a55530f
YS		 1307 sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
1308 sh_eth_write(ndev, 0, TFTR);
86a74ff2 1309
530aa2d0
BD		 1310 /* Frame recv control (enable multiple-packets per rx irq) */
1311 sh_eth_write(ndev, RMCR_RNC, RMCR);
86a74ff2 1312
b284fbe3 1313 sh_eth_write(ndev, mdp->cd->trscer_err_mask, TRSCER);
86a74ff2 1314
380af9e3 1315 if (mdp->cd->bculr)
4a55530f 1316 sh_eth_write(ndev, 0x800, BCULR); /* Burst sycle set */
b0ca2a21 1317
4a55530f 1318 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
86a74ff2 1319
380af9e3 1320 if (!mdp->cd->no_trimd)
4a55530f 1321 sh_eth_write(ndev, 0, TRIMD);
86a74ff2 1322
b0ca2a21 1323 /* Recv frame limit set register */
fdb37a7f
YS		 1324 sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1325 RFLR);
86a74ff2 1326
4a55530f 1327 sh_eth_write(ndev, sh_eth_read(ndev, EESR), EESR);
283e38db
BH		 1328 if (start) {
1329 mdp->irq_enabled = true;
525b8075 1330 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
283e38db 1331 }
86a74ff2
NI		 1332
1333 /* PAUSE Prohibition */
4a55530f 1334 val = (sh_eth_read(ndev, ECMR) & ECMR_DM) |
86a74ff2
NI		 1335 ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE;
1336
4a55530f 1337 sh_eth_write(ndev, val, ECMR);
b0ca2a21 1338
380af9e3
YS		 1339 if (mdp->cd->set_rate)
1340 mdp->cd->set_rate(ndev);
1341
b0ca2a21 1342 /* E-MAC Status Register clear */
4a55530f 1343 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
b0ca2a21
NI		 1344
1345 /* E-MAC Interrupt Enable register */
525b8075
YS		 1346 if (start)
1347 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
86a74ff2
NI		 1348
1349 /* Set MAC address */
1350 update_mac_address(ndev);
1351
1352 /* mask reset */
380af9e3 1353 if (mdp->cd->apr)
4a55530f 1354 sh_eth_write(ndev, APR_AP, APR);
380af9e3 1355 if (mdp->cd->mpr)
4a55530f 1356 sh_eth_write(ndev, MPR_MP, MPR);
380af9e3 1357 if (mdp->cd->tpauser)
4a55530f 1358 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
b0ca2a21 1359
525b8075
YS		 1360 if (start) {
1361 /* Setting the Rx mode will start the Rx process. */
1362 sh_eth_write(ndev, EDRRR_R, EDRRR);
86a74ff2 1363
525b8075
YS		 1364 netif_start_queue(ndev);
1365 }
86a74ff2
NI		 1366
1367 return ret;
1368}
1369
740c7f31
BH		 1370static void sh_eth_dev_exit(struct net_device *ndev)
1371{
1372 struct sh_eth_private *mdp = netdev_priv(ndev);
1373 int i;
1374
1375 /* Deactivate all TX descriptors, so DMA should stop at next
1376 * packet boundary if it's currently running
1377 */
1378 for (i = 0; i < mdp->num_tx_ring; i++)
1379 mdp->tx_ring[i].status &= ~cpu_to_edmac(mdp, TD_TACT);
1380
1381 /* Disable TX FIFO egress to MAC */
1382 sh_eth_rcv_snd_disable(ndev);
1383
1384 /* Stop RX DMA at next packet boundary */
1385 sh_eth_write(ndev, 0, EDRRR);
1386
1387 /* Aside from TX DMA, we can't tell when the hardware is
1388 * really stopped, so we need to reset to make sure.
1389 * Before doing that, wait for long enough to *probably*
1390 * finish transmitting the last packet and poll stats.
1391 */
1392 msleep(2); /* max frame time at 10 Mbps < 1250 us */
1393 sh_eth_get_stats(ndev);
1394 sh_eth_reset(ndev);
a14c7d15
GU		 1395
1396 /* Set MAC address again */
1397 update_mac_address(ndev);
740c7f31
BH		 1398}
1399
86a74ff2
NI		 1400/* free Tx skb function */
1401static int sh_eth_txfree(struct net_device *ndev)
1402{
1403 struct sh_eth_private *mdp = netdev_priv(ndev);
1404 struct sh_eth_txdesc *txdesc;
128296fc 1405 int free_num = 0;
86a74ff2
NI		 1406 int entry = 0;
1407
1408 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
525b8075 1409 entry = mdp->dirty_tx % mdp->num_tx_ring;
86a74ff2 1410 txdesc = &mdp->tx_ring[entry];
71557a37 1411 if (txdesc->status & cpu_to_edmac(mdp, TD_TACT))
86a74ff2
NI		 1412 break;
1413 /* Free the original skb. */
1414 if (mdp->tx_skbuff[entry]) {
31fcb99d
YS		 1415 dma_unmap_single(&ndev->dev, txdesc->addr,
1416 txdesc->buffer_length, DMA_TO_DEVICE);
86a74ff2
NI		 1417 dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1418 mdp->tx_skbuff[entry] = NULL;
128296fc 1419 free_num++;
86a74ff2 1420 }
71557a37 1421 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
525b8075 1422 if (entry >= mdp->num_tx_ring - 1)
71557a37 1423 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
86a74ff2 1424
bb7d92e3
ED		 1425 ndev->stats.tx_packets++;
1426 ndev->stats.tx_bytes += txdesc->buffer_length;
86a74ff2 1427 }
128296fc 1428 return free_num;
86a74ff2
NI		 1429}
1430
1431/* Packet receive function */
3719109d 1432static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
86a74ff2
NI		 1433{
1434 struct sh_eth_private *mdp = netdev_priv(ndev);
1435 struct sh_eth_rxdesc *rxdesc;
1436
525b8075
YS		 1437 int entry = mdp->cur_rx % mdp->num_rx_ring;
1438 int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
319cd520 1439 int limit;
86a74ff2
NI		 1440 struct sk_buff *skb;
1441 u16 pkt_len = 0;
380af9e3 1442 u32 desc_status;
4d6a949c 1443 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN - 1;
52b9fa36 1444 dma_addr_t dma_addr;
86a74ff2 1445
319cd520
MK		 1446 boguscnt = min(boguscnt, *quota);
1447 limit = boguscnt;
86a74ff2 1448 rxdesc = &mdp->rx_ring[entry];
71557a37
YS		 1449 while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) {
1450 desc_status = edmac_to_cpu(mdp, rxdesc->status);
86a74ff2
NI		 1451 pkt_len = rxdesc->frame_length;
1452
1453 if (--boguscnt < 0)
1454 break;
1455
1456 if (!(desc_status & RDFEND))
bb7d92e3 1457 ndev->stats.rx_length_errors++;
86a74ff2 1458
128296fc 1459 /* In case of almost all GETHER/ETHERs, the Receive Frame State
dd019897 1460 * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
db893473
SH		 1461 * bit 0. However, in case of the R8A7740, R8A779x, and
1462 * R7S72100 the RFS bits are from bit 25 to bit 16. So, the
1463 * driver needs right shifting by 16.
dd019897 1464 */
ac8025a6
SS		 1465 if (mdp->cd->shift_rd0)
1466 desc_status >>= 16;
dd019897 1467
86a74ff2
NI		 1468 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1469 RD_RFS5 | RD_RFS6 | RD_RFS10)) {
bb7d92e3 1470 ndev->stats.rx_errors++;
86a74ff2 1471 if (desc_status & RD_RFS1)
bb7d92e3 1472 ndev->stats.rx_crc_errors++;
86a74ff2 1473 if (desc_status & RD_RFS2)
bb7d92e3 1474 ndev->stats.rx_frame_errors++;
86a74ff2 1475 if (desc_status & RD_RFS3)
bb7d92e3 1476 ndev->stats.rx_length_errors++;
86a74ff2 1477 if (desc_status & RD_RFS4)
bb7d92e3 1478 ndev->stats.rx_length_errors++;
86a74ff2 1479 if (desc_status & RD_RFS6)
bb7d92e3 1480 ndev->stats.rx_missed_errors++;
86a74ff2 1481 if (desc_status & RD_RFS10)
bb7d92e3 1482 ndev->stats.rx_over_errors++;
86a74ff2 1483 } else {
380af9e3
YS		 1484 if (!mdp->cd->hw_swap)
1485 sh_eth_soft_swap(
1486 phys_to_virt(ALIGN(rxdesc->addr, 4)),
1487 pkt_len + 2);
86a74ff2
NI		 1488 skb = mdp->rx_skbuff[entry];
1489 mdp->rx_skbuff[entry] = NULL;
503914cf
MD		 1490 if (mdp->cd->rpadir)
1491 skb_reserve(skb, NET_IP_ALIGN);
52b9fa36
BH		 1492 dma_unmap_single(&ndev->dev, rxdesc->addr,
1493 ALIGN(mdp->rx_buf_sz, 16),
1494 DMA_FROM_DEVICE);
86a74ff2
NI		 1495 skb_put(skb, pkt_len);
1496 skb->protocol = eth_type_trans(skb, ndev);
a8e9fd0f 1497 netif_receive_skb(skb);
bb7d92e3
ED		 1498 ndev->stats.rx_packets++;
1499 ndev->stats.rx_bytes += pkt_len;
86a74ff2 1500 }
525b8075 1501 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
862df497 1502 rxdesc = &mdp->rx_ring[entry];
86a74ff2
NI		 1503 }
1504
1505 /* Refill the Rx ring buffers. */
1506 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
525b8075 1507 entry = mdp->dirty_rx % mdp->num_rx_ring;
86a74ff2 1508 rxdesc = &mdp->rx_ring[entry];
b0ca2a21 1509 /* The size of the buffer is 16 byte boundary. */
0029d64a 1510 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
b0ca2a21 1511
86a74ff2 1512 if (mdp->rx_skbuff[entry] == NULL) {
4d6a949c 1513 skb = netdev_alloc_skb(ndev, skbuff_size);
86a74ff2
NI		 1514 if (skb == NULL)
1515 break; /* Better luck next round. */
380af9e3 1516 sh_eth_set_receive_align(skb);
52b9fa36
BH		 1517 dma_addr = dma_map_single(&ndev->dev, skb->data,
1518 rxdesc->buffer_length,
1519 DMA_FROM_DEVICE);
1520 if (dma_mapping_error(&ndev->dev, dma_addr)) {
1521 kfree_skb(skb);
1522 break;
1523 }
1524 mdp->rx_skbuff[entry] = skb;
380af9e3 1525
bc8acf2c 1526 skb_checksum_none_assert(skb);
52b9fa36 1527 rxdesc->addr = dma_addr;
86a74ff2 1528 }
525b8075 1529 if (entry >= mdp->num_rx_ring - 1)
86a74ff2 1530 rxdesc->status |=
71557a37 1531 cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDEL);
86a74ff2
NI		 1532 else
1533 rxdesc->status |=
71557a37 1534 cpu_to_edmac(mdp, RD_RACT | RD_RFP);
86a74ff2
NI		 1535 }
1536
1537 /* Restart Rx engine if stopped. */
1538 /* If we don't need to check status, don't. -KDU */
79fba9f5 1539 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
a18e08bd 1540 /* fix the values for the next receiving if RDE is set */
128296fc
SS		 1541 if (intr_status & EESR_RDE) {
1542 u32 count = (sh_eth_read(ndev, RDFAR) -
1543 sh_eth_read(ndev, RDLAR)) >> 4;
1544
1545 mdp->cur_rx = count;
1546 mdp->dirty_rx = count;
1547 }
4a55530f 1548 sh_eth_write(ndev, EDRRR_R, EDRRR);
79fba9f5 1549 }
86a74ff2 1550
319cd520
MK		 1551 *quota -= limit - boguscnt - 1;
1552
4f809cea 1553 return *quota <= 0;
86a74ff2
NI		 1554}
1555
4a55530f 1556static void sh_eth_rcv_snd_disable(struct net_device *ndev)
dc19e4e5
NI		 1557{
1558 /* disable tx and rx */
4a55530f
YS		 1559 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) &
1560 ~(ECMR_RE | ECMR_TE), ECMR);
dc19e4e5
NI		 1561}
1562
4a55530f 1563static void sh_eth_rcv_snd_enable(struct net_device *ndev)
dc19e4e5
NI		 1564{
1565 /* enable tx and rx */
4a55530f
YS		 1566 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) |
1567 (ECMR_RE | ECMR_TE), ECMR);
dc19e4e5
NI		 1568}
1569
86a74ff2 1570/* error control function */
0799c2d6 1571static void sh_eth_error(struct net_device *ndev, u32 intr_status)
86a74ff2
NI		 1572{
1573 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2 1574 u32 felic_stat;
380af9e3
YS		 1575 u32 link_stat;
1576 u32 mask;
86a74ff2
NI		 1577
1578 if (intr_status & EESR_ECI) {
4a55530f
YS		 1579 felic_stat = sh_eth_read(ndev, ECSR);
1580 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */
86a74ff2 1581 if (felic_stat & ECSR_ICD)
bb7d92e3 1582 ndev->stats.tx_carrier_errors++;
86a74ff2
NI		 1583 if (felic_stat & ECSR_LCHNG) {
1584 /* Link Changed */
4923576b 1585 if (mdp->cd->no_psr || mdp->no_ether_link) {
1e1b812b 1586 goto ignore_link;
380af9e3 1587 } else {
4a55530f 1588 link_stat = (sh_eth_read(ndev, PSR));
4923576b
YS		 1589 if (mdp->ether_link_active_low)
1590 link_stat = ~link_stat;
380af9e3 1591 }
128296fc 1592 if (!(link_stat & PHY_ST_LINK)) {
4a55530f 1593 sh_eth_rcv_snd_disable(ndev);
128296fc 1594 } else {
86a74ff2 1595 /* Link Up */
4a55530f 1596 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) &
128296fc
SS		 1597 ~DMAC_M_ECI, EESIPR);
1598 /* clear int */
4a55530f 1599 sh_eth_write(ndev, sh_eth_read(ndev, ECSR),
128296fc 1600 ECSR);
4a55530f 1601 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) |
128296fc 1602 DMAC_M_ECI, EESIPR);
86a74ff2 1603 /* enable tx and rx */
4a55530f 1604 sh_eth_rcv_snd_enable(ndev);
86a74ff2
NI		 1605 }
1606 }
1607 }
1608
1e1b812b 1609ignore_link:
86a74ff2 1610 if (intr_status & EESR_TWB) {
4eb313a7
SS		 1611 /* Unused write back interrupt */
1612 if (intr_status & EESR_TABT) { /* Transmit Abort int */
bb7d92e3 1613 ndev->stats.tx_aborted_errors++;
8d5009f6 1614 netif_err(mdp, tx_err, ndev, "Transmit Abort\n");
4eb313a7 1615 }
86a74ff2
NI		 1616 }
1617
1618 if (intr_status & EESR_RABT) {
1619 /* Receive Abort int */
1620 if (intr_status & EESR_RFRMER) {
1621 /* Receive Frame Overflow int */
bb7d92e3 1622 ndev->stats.rx_frame_errors++;
86a74ff2
NI		 1623 }
1624 }
380af9e3 1625
dc19e4e5
NI		 1626 if (intr_status & EESR_TDE) {
1627 /* Transmit Descriptor Empty int */
bb7d92e3 1628 ndev->stats.tx_fifo_errors++;
8d5009f6 1629 netif_err(mdp, tx_err, ndev, "Transmit Descriptor Empty\n");
dc19e4e5
NI		 1630 }
1631
1632 if (intr_status & EESR_TFE) {
1633 /* FIFO under flow */
bb7d92e3 1634 ndev->stats.tx_fifo_errors++;
8d5009f6 1635 netif_err(mdp, tx_err, ndev, "Transmit FIFO Under flow\n");
86a74ff2
NI		 1636 }
1637
1638 if (intr_status & EESR_RDE) {
1639 /* Receive Descriptor Empty int */
bb7d92e3 1640 ndev->stats.rx_over_errors++;
86a74ff2 1641 }
dc19e4e5 1642
86a74ff2
NI		 1643 if (intr_status & EESR_RFE) {
1644 /* Receive FIFO Overflow int */
bb7d92e3 1645 ndev->stats.rx_fifo_errors++;
dc19e4e5
NI		 1646 }
1647
1648 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1649 /* Address Error */
bb7d92e3 1650 ndev->stats.tx_fifo_errors++;
8d5009f6 1651 netif_err(mdp, tx_err, ndev, "Address Error\n");
86a74ff2 1652 }
380af9e3
YS		 1653
1654 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1655 if (mdp->cd->no_ade)
1656 mask &= ~EESR_ADE;
1657 if (intr_status & mask) {
86a74ff2 1658 /* Tx error */
4a55530f 1659 u32 edtrr = sh_eth_read(ndev, EDTRR);
090d560f 1660
86a74ff2 1661 /* dmesg */
da246855
SS		 1662 netdev_err(ndev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1663 intr_status, mdp->cur_tx, mdp->dirty_tx,
1664 (u32)ndev->state, edtrr);
86a74ff2
NI		 1665 /* dirty buffer free */
1666 sh_eth_txfree(ndev);
1667
1668 /* SH7712 BUG */
c5ed5368 1669 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
86a74ff2 1670 /* tx dma start */
c5ed5368 1671 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
86a74ff2
NI		 1672 }
1673 /* wakeup */
1674 netif_wake_queue(ndev);
1675 }
1676}
1677
1678static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1679{
1680 struct net_device *ndev = netdev;
1681 struct sh_eth_private *mdp = netdev_priv(ndev);
380af9e3 1682 struct sh_eth_cpu_data *cd = mdp->cd;
0e0fde3c 1683 irqreturn_t ret = IRQ_NONE;
0799c2d6 1684 u32 intr_status, intr_enable;
86a74ff2 1685
86a74ff2
NI		 1686 spin_lock(&mdp->lock);
1687
3893b273 1688 /* Get interrupt status */
4a55530f 1689 intr_status = sh_eth_read(ndev, EESR);
3893b273
SS		 1690 /* Mask it with the interrupt mask, forcing ECI interrupt to be always
1691 * enabled since it's the one that comes thru regardless of the mask,
1692 * and we need to fully handle it in sh_eth_error() in order to quench
1693 * it as it doesn't get cleared by just writing 1 to the ECI bit...
1694 */
3719109d
SS		 1695 intr_enable = sh_eth_read(ndev, EESIPR);
1696 intr_status &= intr_enable | DMAC_M_ECI;
1697 if (intr_status & (EESR_RX_CHECK | cd->tx_check | cd->eesr_err_check))
0e0fde3c 1698 ret = IRQ_HANDLED;
3719109d 1699 else
283e38db
BH		 1700 goto out;
1701
1702 if (!likely(mdp->irq_enabled)) {
1703 sh_eth_write(ndev, 0, EESIPR);
1704 goto out;
1705 }
86a74ff2 1706
3719109d
SS		 1707 if (intr_status & EESR_RX_CHECK) {
1708 if (napi_schedule_prep(&mdp->napi)) {
1709 /* Mask Rx interrupts */
1710 sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK,
1711 EESIPR);
1712 __napi_schedule(&mdp->napi);
1713 } else {
da246855 1714 netdev_warn(ndev,
0799c2d6 1715 "ignoring interrupt, status 0x%08x, mask 0x%08x.\n",
da246855 1716 intr_status, intr_enable);
3719109d
SS		 1717 }
1718 }
86a74ff2 1719
b0ca2a21 1720 /* Tx Check */
380af9e3 1721 if (intr_status & cd->tx_check) {
3719109d
SS		 1722 /* Clear Tx interrupts */
1723 sh_eth_write(ndev, intr_status & cd->tx_check, EESR);
1724
86a74ff2
NI		 1725 sh_eth_txfree(ndev);
1726 netif_wake_queue(ndev);
1727 }
1728
3719109d
SS		 1729 if (intr_status & cd->eesr_err_check) {
1730 /* Clear error interrupts */
1731 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR);
1732
86a74ff2 1733 sh_eth_error(ndev, intr_status);
3719109d 1734 }
86a74ff2 1735
283e38db 1736out:
86a74ff2
NI		 1737 spin_unlock(&mdp->lock);
1738
0e0fde3c 1739 return ret;
86a74ff2
NI		 1740}
1741
3719109d
SS		 1742static int sh_eth_poll(struct napi_struct *napi, int budget)
1743{
1744 struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private,
1745 napi);
1746 struct net_device *ndev = napi->dev;
1747 int quota = budget;
0799c2d6 1748 u32 intr_status;
3719109d
SS		 1749
1750 for (;;) {
1751 intr_status = sh_eth_read(ndev, EESR);
1752 if (!(intr_status & EESR_RX_CHECK))
1753 break;
1754 /* Clear Rx interrupts */
1755 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR);
1756
1757 if (sh_eth_rx(ndev, intr_status, &quota))
1758 goto out;
1759 }
1760
1761 napi_complete(napi);
1762
1763 /* Reenable Rx interrupts */
283e38db
BH		 1764 if (mdp->irq_enabled)
1765 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
3719109d
SS		 1766out:
1767 return budget - quota;
1768}
1769
86a74ff2
NI		 1770/* PHY state control function */
1771static void sh_eth_adjust_link(struct net_device *ndev)
1772{
1773 struct sh_eth_private *mdp = netdev_priv(ndev);
1774 struct phy_device *phydev = mdp->phydev;
86a74ff2
NI		 1775 int new_state = 0;
1776
3340d2aa 1777 if (phydev->link) {
86a74ff2
NI		 1778 if (phydev->duplex != mdp->duplex) {
1779 new_state = 1;
1780 mdp->duplex = phydev->duplex;
380af9e3
YS		 1781 if (mdp->cd->set_duplex)
1782 mdp->cd->set_duplex(ndev);
86a74ff2
NI		 1783 }
1784
1785 if (phydev->speed != mdp->speed) {
1786 new_state = 1;
1787 mdp->speed = phydev->speed;
380af9e3
YS		 1788 if (mdp->cd->set_rate)
1789 mdp->cd->set_rate(ndev);
86a74ff2 1790 }
3340d2aa 1791 if (!mdp->link) {
91a56152 1792 sh_eth_write(ndev,
128296fc
SS		 1793 sh_eth_read(ndev, ECMR) & ~ECMR_TXF,
1794 ECMR);
86a74ff2
NI		 1795 new_state = 1;
1796 mdp->link = phydev->link;
1e1b812b
SS		 1797 if (mdp->cd->no_psr || mdp->no_ether_link)
1798 sh_eth_rcv_snd_enable(ndev);
86a74ff2
NI		 1799 }
1800 } else if (mdp->link) {
1801 new_state = 1;
3340d2aa 1802 mdp->link = 0;
86a74ff2
NI		 1803 mdp->speed = 0;
1804 mdp->duplex = -1;
1e1b812b
SS		 1805 if (mdp->cd->no_psr || mdp->no_ether_link)
1806 sh_eth_rcv_snd_disable(ndev);
86a74ff2
NI		 1807 }
1808
dc19e4e5 1809 if (new_state && netif_msg_link(mdp))
86a74ff2
NI		 1810 phy_print_status(phydev);
1811}
1812
1813/* PHY init function */
1814static int sh_eth_phy_init(struct net_device *ndev)
1815{
702eca02 1816 struct device_node *np = ndev->dev.parent->of_node;
86a74ff2 1817 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 1818 struct phy_device *phydev = NULL;
1819
3340d2aa 1820 mdp->link = 0;
86a74ff2
NI		 1821 mdp->speed = 0;
1822 mdp->duplex = -1;
1823
1824 /* Try connect to PHY */
702eca02
BD		 1825 if (np) {
1826 struct device_node *pn;
1827
1828 pn = of_parse_phandle(np, "phy-handle", 0);
1829 phydev = of_phy_connect(ndev, pn,
1830 sh_eth_adjust_link, 0,
1831 mdp->phy_interface);
1832
1833 if (!phydev)
1834 phydev = ERR_PTR(-ENOENT);
1835 } else {
1836 char phy_id[MII_BUS_ID_SIZE + 3];
1837
1838 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
1839 mdp->mii_bus->id, mdp->phy_id);
1840
1841 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
1842 mdp->phy_interface);
1843 }
1844
86a74ff2 1845 if (IS_ERR(phydev)) {
da246855 1846 netdev_err(ndev, "failed to connect PHY\n");
86a74ff2
NI		 1847 return PTR_ERR(phydev);
1848 }
380af9e3 1849
da246855
SS		 1850 netdev_info(ndev, "attached PHY %d (IRQ %d) to driver %s\n",
1851 phydev->addr, phydev->irq, phydev->drv->name);
86a74ff2
NI		 1852
1853 mdp->phydev = phydev;
1854
1855 return 0;
1856}
1857
1858/* PHY control start function */
1859static int sh_eth_phy_start(struct net_device *ndev)
1860{
1861 struct sh_eth_private *mdp = netdev_priv(ndev);
1862 int ret;
1863
1864 ret = sh_eth_phy_init(ndev);
1865 if (ret)
1866 return ret;
1867
86a74ff2
NI		 1868 phy_start(mdp->phydev);
1869
1870 return 0;
1871}
1872
dc19e4e5 1873static int sh_eth_get_settings(struct net_device *ndev,
128296fc 1874 struct ethtool_cmd *ecmd)
dc19e4e5
NI		 1875{
1876 struct sh_eth_private *mdp = netdev_priv(ndev);
1877 unsigned long flags;
1878 int ret;
1879
4f9dce23
BH		 1880 if (!mdp->phydev)
1881 return -ENODEV;
1882
dc19e4e5
NI		 1883 spin_lock_irqsave(&mdp->lock, flags);
1884 ret = phy_ethtool_gset(mdp->phydev, ecmd);
1885 spin_unlock_irqrestore(&mdp->lock, flags);
1886
1887 return ret;
1888}
1889
1890static int sh_eth_set_settings(struct net_device *ndev,
128296fc 1891 struct ethtool_cmd *ecmd)
dc19e4e5
NI		 1892{
1893 struct sh_eth_private *mdp = netdev_priv(ndev);
1894 unsigned long flags;
1895 int ret;
dc19e4e5 1896
4f9dce23
BH		 1897 if (!mdp->phydev)
1898 return -ENODEV;
1899
dc19e4e5
NI		 1900 spin_lock_irqsave(&mdp->lock, flags);
1901
1902 /* disable tx and rx */
4a55530f 1903 sh_eth_rcv_snd_disable(ndev);
dc19e4e5
NI		 1904
1905 ret = phy_ethtool_sset(mdp->phydev, ecmd);
1906 if (ret)
1907 goto error_exit;
1908
1909 if (ecmd->duplex == DUPLEX_FULL)
1910 mdp->duplex = 1;
1911 else
1912 mdp->duplex = 0;
1913
1914 if (mdp->cd->set_duplex)
1915 mdp->cd->set_duplex(ndev);
1916
1917error_exit:
1918 mdelay(1);
1919
1920 /* enable tx and rx */
4a55530f 1921 sh_eth_rcv_snd_enable(ndev);
dc19e4e5
NI		 1922
1923 spin_unlock_irqrestore(&mdp->lock, flags);
1924
1925 return ret;
1926}
1927
1928static int sh_eth_nway_reset(struct net_device *ndev)
1929{
1930 struct sh_eth_private *mdp = netdev_priv(ndev);
1931 unsigned long flags;
1932 int ret;
1933
4f9dce23
BH		 1934 if (!mdp->phydev)
1935 return -ENODEV;
1936
dc19e4e5
NI		 1937 spin_lock_irqsave(&mdp->lock, flags);
1938 ret = phy_start_aneg(mdp->phydev);
1939 spin_unlock_irqrestore(&mdp->lock, flags);
1940
1941 return ret;
1942}
1943
1944static u32 sh_eth_get_msglevel(struct net_device *ndev)
1945{
1946 struct sh_eth_private *mdp = netdev_priv(ndev);
1947 return mdp->msg_enable;
1948}
1949
1950static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
1951{
1952 struct sh_eth_private *mdp = netdev_priv(ndev);
1953 mdp->msg_enable = value;
1954}
1955
1956static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
1957 "rx_current", "tx_current",
1958 "rx_dirty", "tx_dirty",
1959};
1960#define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats)
1961
1962static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
1963{
1964 switch (sset) {
1965 case ETH_SS_STATS:
1966 return SH_ETH_STATS_LEN;
1967 default:
1968 return -EOPNOTSUPP;
1969 }
1970}
1971
1972static void sh_eth_get_ethtool_stats(struct net_device *ndev,
128296fc 1973 struct ethtool_stats *stats, u64 *data)
dc19e4e5
NI		 1974{
1975 struct sh_eth_private *mdp = netdev_priv(ndev);
1976 int i = 0;
1977
1978 /* device-specific stats */
1979 data[i++] = mdp->cur_rx;
1980 data[i++] = mdp->cur_tx;
1981 data[i++] = mdp->dirty_rx;
1982 data[i++] = mdp->dirty_tx;
1983}
1984
1985static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1986{
1987 switch (stringset) {
1988 case ETH_SS_STATS:
1989 memcpy(data, *sh_eth_gstrings_stats,
128296fc 1990 sizeof(sh_eth_gstrings_stats));
dc19e4e5
NI		 1991 break;
1992 }
1993}
1994
525b8075
YS		 1995static void sh_eth_get_ringparam(struct net_device *ndev,
1996 struct ethtool_ringparam *ring)
1997{
1998 struct sh_eth_private *mdp = netdev_priv(ndev);
1999
2000 ring->rx_max_pending = RX_RING_MAX;
2001 ring->tx_max_pending = TX_RING_MAX;
2002 ring->rx_pending = mdp->num_rx_ring;
2003 ring->tx_pending = mdp->num_tx_ring;
2004}
2005
2006static int sh_eth_set_ringparam(struct net_device *ndev,
2007 struct ethtool_ringparam *ring)
2008{
2009 struct sh_eth_private *mdp = netdev_priv(ndev);
2010 int ret;
2011
2012 if (ring->tx_pending > TX_RING_MAX ||
2013 ring->rx_pending > RX_RING_MAX ||
2014 ring->tx_pending < TX_RING_MIN ||
2015 ring->rx_pending < RX_RING_MIN)
2016 return -EINVAL;
2017 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
2018 return -EINVAL;
2019
2020 if (netif_running(ndev)) {
bd888916 2021 netif_device_detach(ndev);
525b8075 2022 netif_tx_disable(ndev);
283e38db
BH		 2023
2024 /* Serialise with the interrupt handler and NAPI, then
2025 * disable interrupts. We have to clear the
2026 * irq_enabled flag first to ensure that interrupts
2027 * won't be re-enabled.
2028 */
2029 mdp->irq_enabled = false;
525b8075 2030 synchronize_irq(ndev->irq);
283e38db 2031 napi_synchronize(&mdp->napi);
525b8075 2032 sh_eth_write(ndev, 0x0000, EESIPR);
525b8075 2033
740c7f31 2034 sh_eth_dev_exit(ndev);
525b8075 2035
084236d8
BH		 2036 /* Free all the skbuffs in the Rx queue. */
2037 sh_eth_ring_free(ndev);
2038 /* Free DMA buffer */
2039 sh_eth_free_dma_buffer(mdp);
2040 }
525b8075
YS		 2041
2042 /* Set new parameters */
2043 mdp->num_rx_ring = ring->rx_pending;
2044 mdp->num_tx_ring = ring->tx_pending;
2045
525b8075 2046 if (netif_running(ndev)) {
084236d8
BH		 2047 ret = sh_eth_ring_init(ndev);
2048 if (ret < 0) {
2049 netdev_err(ndev, "%s: sh_eth_ring_init failed.\n",
2050 __func__);
2051 return ret;
2052 }
2053 ret = sh_eth_dev_init(ndev, false);
2054 if (ret < 0) {
2055 netdev_err(ndev, "%s: sh_eth_dev_init failed.\n",
2056 __func__);
2057 return ret;
2058 }
2059
283e38db 2060 mdp->irq_enabled = true;
525b8075
YS		 2061 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
2062 /* Setting the Rx mode will start the Rx process. */
2063 sh_eth_write(ndev, EDRRR_R, EDRRR);
bd888916 2064 netif_device_attach(ndev);
525b8075
YS		 2065 }
2066
2067 return 0;
2068}
2069
9b07be4b 2070static const struct ethtool_ops sh_eth_ethtool_ops = {
dc19e4e5
NI		 2071 .get_settings = sh_eth_get_settings,
2072 .set_settings = sh_eth_set_settings,
9b07be4b 2073 .nway_reset = sh_eth_nway_reset,
dc19e4e5
NI		 2074 .get_msglevel = sh_eth_get_msglevel,
2075 .set_msglevel = sh_eth_set_msglevel,
9b07be4b 2076 .get_link = ethtool_op_get_link,
dc19e4e5
NI		 2077 .get_strings = sh_eth_get_strings,
2078 .get_ethtool_stats = sh_eth_get_ethtool_stats,
2079 .get_sset_count = sh_eth_get_sset_count,
525b8075
YS		 2080 .get_ringparam = sh_eth_get_ringparam,
2081 .set_ringparam = sh_eth_set_ringparam,
dc19e4e5
NI		 2082};
2083
86a74ff2
NI		 2084/* network device open function */
2085static int sh_eth_open(struct net_device *ndev)
2086{
2087 int ret = 0;
2088 struct sh_eth_private *mdp = netdev_priv(ndev);
2089
bcd5149d
MD		 2090 pm_runtime_get_sync(&mdp->pdev->dev);
2091
d2779e99
SS		 2092 napi_enable(&mdp->napi);
2093
a0607fd3 2094 ret = request_irq(ndev->irq, sh_eth_interrupt,
5b3dfd13 2095 mdp->cd->irq_flags, ndev->name, ndev);
86a74ff2 2096 if (ret) {
da246855 2097 netdev_err(ndev, "Can not assign IRQ number\n");
d2779e99 2098 goto out_napi_off;
86a74ff2
NI		 2099 }
2100
2101 /* Descriptor set */
2102 ret = sh_eth_ring_init(ndev);
2103 if (ret)
2104 goto out_free_irq;
2105
2106 /* device init */
525b8075 2107 ret = sh_eth_dev_init(ndev, true);
86a74ff2
NI		 2108 if (ret)
2109 goto out_free_irq;
2110
2111 /* PHY control start*/
2112 ret = sh_eth_phy_start(ndev);
2113 if (ret)
2114 goto out_free_irq;
2115
7fa2955f
MK		 2116 mdp->is_opened = 1;
2117
86a74ff2
NI		 2118 return ret;
2119
2120out_free_irq:
2121 free_irq(ndev->irq, ndev);
d2779e99
SS		 2122out_napi_off:
2123 napi_disable(&mdp->napi);
bcd5149d 2124 pm_runtime_put_sync(&mdp->pdev->dev);
86a74ff2
NI		 2125 return ret;
2126}
2127
2128/* Timeout function */
2129static void sh_eth_tx_timeout(struct net_device *ndev)
2130{
2131 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 2132 struct sh_eth_rxdesc *rxdesc;
2133 int i;
2134
2135 netif_stop_queue(ndev);
2136
8d5009f6
SS		 2137 netif_err(mdp, timer, ndev,
2138 "transmit timed out, status %8.8x, resetting...\n",
0799c2d6 2139 sh_eth_read(ndev, EESR));
86a74ff2
NI		 2140
2141 /* tx_errors count up */
bb7d92e3 2142 ndev->stats.tx_errors++;
86a74ff2 2143
86a74ff2 2144 /* Free all the skbuffs in the Rx queue. */
525b8075 2145 for (i = 0; i < mdp->num_rx_ring; i++) {
86a74ff2
NI		 2146 rxdesc = &mdp->rx_ring[i];
2147 rxdesc->status = 0;
2148 rxdesc->addr = 0xBADF00D0;
179d80af 2149 dev_kfree_skb(mdp->rx_skbuff[i]);
86a74ff2
NI		 2150 mdp->rx_skbuff[i] = NULL;
2151 }
525b8075 2152 for (i = 0; i < mdp->num_tx_ring; i++) {
179d80af 2153 dev_kfree_skb(mdp->tx_skbuff[i]);
86a74ff2
NI		 2154 mdp->tx_skbuff[i] = NULL;
2155 }
2156
2157 /* device init */
525b8075 2158 sh_eth_dev_init(ndev, true);
86a74ff2
NI		 2159}
2160
2161/* Packet transmit function */
2162static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
2163{
2164 struct sh_eth_private *mdp = netdev_priv(ndev);
2165 struct sh_eth_txdesc *txdesc;
2166 u32 entry;
fb5e2f9b 2167 unsigned long flags;
86a74ff2
NI		 2168
2169 spin_lock_irqsave(&mdp->lock, flags);
525b8075 2170 if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
86a74ff2 2171 if (!sh_eth_txfree(ndev)) {
8d5009f6 2172 netif_warn(mdp, tx_queued, ndev, "TxFD exhausted.\n");
86a74ff2
NI		 2173 netif_stop_queue(ndev);
2174 spin_unlock_irqrestore(&mdp->lock, flags);
5b548140 2175 return NETDEV_TX_BUSY;
86a74ff2
NI		 2176 }
2177 }
2178 spin_unlock_irqrestore(&mdp->lock, flags);
2179
eebfb643
BH		 2180 if (skb_padto(skb, ETH_ZLEN))
2181 return NETDEV_TX_OK;
2182
525b8075 2183 entry = mdp->cur_tx % mdp->num_tx_ring;
86a74ff2
NI		 2184 mdp->tx_skbuff[entry] = skb;
2185 txdesc = &mdp->tx_ring[entry];
86a74ff2 2186 /* soft swap. */
380af9e3
YS		 2187 if (!mdp->cd->hw_swap)
2188 sh_eth_soft_swap(phys_to_virt(ALIGN(txdesc->addr, 4)),
2189 skb->len + 2);
31fcb99d
YS		 2190 txdesc->addr = dma_map_single(&ndev->dev, skb->data, skb->len,
2191 DMA_TO_DEVICE);
aa3933b8
BH		 2192 if (dma_mapping_error(&ndev->dev, txdesc->addr)) {
2193 kfree_skb(skb);
2194 return NETDEV_TX_OK;
2195 }
eebfb643 2196 txdesc->buffer_length = skb->len;
86a74ff2 2197
525b8075 2198 if (entry >= mdp->num_tx_ring - 1)
71557a37 2199 txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE);
86a74ff2 2200 else
71557a37 2201 txdesc->status |= cpu_to_edmac(mdp, TD_TACT);
86a74ff2
NI		 2202
2203 mdp->cur_tx++;
2204
c5ed5368
YS		 2205 if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
2206 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
b0ca2a21 2207
6ed10654 2208 return NETDEV_TX_OK;
86a74ff2
NI		 2209}
2210
7fa2955f
MK		 2211static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
2212{
2213 struct sh_eth_private *mdp = netdev_priv(ndev);
2214
2215 if (sh_eth_is_rz_fast_ether(mdp))
2216 return &ndev->stats;
2217
2218 if (!mdp->is_opened)
2219 return &ndev->stats;
2220
2221 ndev->stats.tx_dropped += sh_eth_read(ndev, TROCR);
2222 sh_eth_write(ndev, 0, TROCR); /* (write clear) */
2223 ndev->stats.collisions += sh_eth_read(ndev, CDCR);
2224 sh_eth_write(ndev, 0, CDCR); /* (write clear) */
2225 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, LCCR);
2226 sh_eth_write(ndev, 0, LCCR); /* (write clear) */
2227
2228 if (sh_eth_is_gether(mdp)) {
2229 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CERCR);
2230 sh_eth_write(ndev, 0, CERCR); /* (write clear) */
2231 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CEECR);
2232 sh_eth_write(ndev, 0, CEECR); /* (write clear) */
2233 } else {
2234 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CNDCR);
2235 sh_eth_write(ndev, 0, CNDCR); /* (write clear) */
2236 }
2237
2238 return &ndev->stats;
2239}
2240
86a74ff2
NI		 2241/* device close function */
2242static int sh_eth_close(struct net_device *ndev)
2243{
2244 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 2245
2246 netif_stop_queue(ndev);
2247
283e38db
BH		 2248 /* Serialise with the interrupt handler and NAPI, then disable
2249 * interrupts. We have to clear the irq_enabled flag first to
2250 * ensure that interrupts won't be re-enabled.
2251 */
2252 mdp->irq_enabled = false;
2253 synchronize_irq(ndev->irq);
2254 napi_disable(&mdp->napi);
4a55530f 2255 sh_eth_write(ndev, 0x0000, EESIPR);
86a74ff2 2256
740c7f31 2257 sh_eth_dev_exit(ndev);
86a74ff2
NI		 2258
2259 /* PHY Disconnect */
2260 if (mdp->phydev) {
2261 phy_stop(mdp->phydev);
2262 phy_disconnect(mdp->phydev);
4f9dce23 2263 mdp->phydev = NULL;
86a74ff2
NI		 2264 }
2265
2266 free_irq(ndev->irq, ndev);
2267
86a74ff2
NI		 2268 /* Free all the skbuffs in the Rx queue. */
2269 sh_eth_ring_free(ndev);
2270
2271 /* free DMA buffer */
91c77550 2272 sh_eth_free_dma_buffer(mdp);
86a74ff2 2273
bcd5149d
MD		 2274 pm_runtime_put_sync(&mdp->pdev->dev);
2275
7fa2955f 2276 mdp->is_opened = 0;
bcd5149d 2277
7fa2955f 2278 return 0;
86a74ff2
NI		 2279}
2280
bb7d92e3 2281/* ioctl to device function */
128296fc 2282static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
86a74ff2
NI		 2283{
2284 struct sh_eth_private *mdp = netdev_priv(ndev);
2285 struct phy_device *phydev = mdp->phydev;
2286
2287 if (!netif_running(ndev))
2288 return -EINVAL;
2289
2290 if (!phydev)
2291 return -ENODEV;
2292
28b04113 2293 return phy_mii_ioctl(phydev, rq, cmd);
86a74ff2
NI		 2294}
2295
6743fe6d
YS		 2296/* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
2297static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp,
2298 int entry)
2299{
2300 return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4);
2301}
2302
2303static u32 sh_eth_tsu_get_post_mask(int entry)
2304{
2305 return 0x0f << (28 - ((entry % 8) * 4));
2306}
2307
2308static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
2309{
2310 return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
2311}
2312
2313static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
2314 int entry)
2315{
2316 struct sh_eth_private *mdp = netdev_priv(ndev);
2317 u32 tmp;
2318 void *reg_offset;
2319
2320 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2321 tmp = ioread32(reg_offset);
2322 iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset);
2323}
2324
2325static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
2326 int entry)
2327{
2328 struct sh_eth_private *mdp = netdev_priv(ndev);
2329 u32 post_mask, ref_mask, tmp;
2330 void *reg_offset;
2331
2332 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2333 post_mask = sh_eth_tsu_get_post_mask(entry);
2334 ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
2335
2336 tmp = ioread32(reg_offset);
2337 iowrite32(tmp & ~post_mask, reg_offset);
2338
2339 /* If other port enables, the function returns "true" */
2340 return tmp & ref_mask;
2341}
2342
2343static int sh_eth_tsu_busy(struct net_device *ndev)
2344{
2345 int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
2346 struct sh_eth_private *mdp = netdev_priv(ndev);
2347
2348 while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
2349 udelay(10);
2350 timeout--;
2351 if (timeout <= 0) {
da246855 2352 netdev_err(ndev, "%s: timeout\n", __func__);
6743fe6d
YS		 2353 return -ETIMEDOUT;
2354 }
2355 }
2356
2357 return 0;
2358}
2359
2360static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg,
2361 const u8 *addr)
2362{
2363 u32 val;
2364
2365 val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
2366 iowrite32(val, reg);
2367 if (sh_eth_tsu_busy(ndev) < 0)
2368 return -EBUSY;
2369
2370 val = addr[4] << 8 | addr[5];
2371 iowrite32(val, reg + 4);
2372 if (sh_eth_tsu_busy(ndev) < 0)
2373 return -EBUSY;
2374
2375 return 0;
2376}
2377
2378static void sh_eth_tsu_read_entry(void *reg, u8 *addr)
2379{
2380 u32 val;
2381
2382 val = ioread32(reg);
2383 addr[0] = (val >> 24) & 0xff;
2384 addr[1] = (val >> 16) & 0xff;
2385 addr[2] = (val >> 8) & 0xff;
2386 addr[3] = val & 0xff;
2387 val = ioread32(reg + 4);
2388 addr[4] = (val >> 8) & 0xff;
2389 addr[5] = val & 0xff;
2390}
2391
2392
2393static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
2394{
2395 struct sh_eth_private *mdp = netdev_priv(ndev);
2396 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2397 int i;
2398 u8 c_addr[ETH_ALEN];
2399
2400 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2401 sh_eth_tsu_read_entry(reg_offset, c_addr);
c4bde29c 2402 if (ether_addr_equal(addr, c_addr))
6743fe6d
YS		 2403 return i;
2404 }
2405
2406 return -ENOENT;
2407}
2408
2409static int sh_eth_tsu_find_empty(struct net_device *ndev)
2410{
2411 u8 blank[ETH_ALEN];
2412 int entry;
2413
2414 memset(blank, 0, sizeof(blank));
2415 entry = sh_eth_tsu_find_entry(ndev, blank);
2416 return (entry < 0) ? -ENOMEM : entry;
2417}
2418
2419static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
2420 int entry)
2421{
2422 struct sh_eth_private *mdp = netdev_priv(ndev);
2423 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2424 int ret;
2425 u8 blank[ETH_ALEN];
2426
2427 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
2428 ~(1 << (31 - entry)), TSU_TEN);
2429
2430 memset(blank, 0, sizeof(blank));
2431 ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
2432 if (ret < 0)
2433 return ret;
2434 return 0;
2435}
2436
2437static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
2438{
2439 struct sh_eth_private *mdp = netdev_priv(ndev);
2440 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2441 int i, ret;
2442
2443 if (!mdp->cd->tsu)
2444 return 0;
2445
2446 i = sh_eth_tsu_find_entry(ndev, addr);
2447 if (i < 0) {
2448 /* No entry found, create one */
2449 i = sh_eth_tsu_find_empty(ndev);
2450 if (i < 0)
2451 return -ENOMEM;
2452 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
2453 if (ret < 0)
2454 return ret;
2455
2456 /* Enable the entry */
2457 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
2458 (1 << (31 - i)), TSU_TEN);
2459 }
2460
2461 /* Entry found or created, enable POST */
2462 sh_eth_tsu_enable_cam_entry_post(ndev, i);
2463
2464 return 0;
2465}
2466
2467static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
2468{
2469 struct sh_eth_private *mdp = netdev_priv(ndev);
2470 int i, ret;
2471
2472 if (!mdp->cd->tsu)
2473 return 0;
2474
2475 i = sh_eth_tsu_find_entry(ndev, addr);
2476 if (i) {
2477 /* Entry found */
2478 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2479 goto done;
2480
2481 /* Disable the entry if both ports was disabled */
2482 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2483 if (ret < 0)
2484 return ret;
2485 }
2486done:
2487 return 0;
2488}
2489
2490static int sh_eth_tsu_purge_all(struct net_device *ndev)
2491{
2492 struct sh_eth_private *mdp = netdev_priv(ndev);
2493 int i, ret;
2494
b37feed7 2495 if (!mdp->cd->tsu)
6743fe6d
YS		 2496 return 0;
2497
2498 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
2499 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2500 continue;
2501
2502 /* Disable the entry if both ports was disabled */
2503 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2504 if (ret < 0)
2505 return ret;
2506 }
2507
2508 return 0;
2509}
2510
2511static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
2512{
2513 struct sh_eth_private *mdp = netdev_priv(ndev);
2514 u8 addr[ETH_ALEN];
2515 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2516 int i;
2517
b37feed7 2518 if (!mdp->cd->tsu)
6743fe6d
YS		 2519 return;
2520
2521 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2522 sh_eth_tsu_read_entry(reg_offset, addr);
2523 if (is_multicast_ether_addr(addr))
2524 sh_eth_tsu_del_entry(ndev, addr);
2525 }
2526}
2527
b37feed7
BH		 2528/* Update promiscuous flag and multicast filter */
2529static void sh_eth_set_rx_mode(struct net_device *ndev)
86a74ff2 2530{
6743fe6d
YS		 2531 struct sh_eth_private *mdp = netdev_priv(ndev);
2532 u32 ecmr_bits;
2533 int mcast_all = 0;
2534 unsigned long flags;
2535
2536 spin_lock_irqsave(&mdp->lock, flags);
128296fc 2537 /* Initial condition is MCT = 1, PRM = 0.
6743fe6d
YS		 2538 * Depending on ndev->flags, set PRM or clear MCT
2539 */
b37feed7
BH		 2540 ecmr_bits = sh_eth_read(ndev, ECMR) & ~ECMR_PRM;
2541 if (mdp->cd->tsu)
2542 ecmr_bits |= ECMR_MCT;
6743fe6d
YS		 2543
2544 if (!(ndev->flags & IFF_MULTICAST)) {
2545 sh_eth_tsu_purge_mcast(ndev);
2546 mcast_all = 1;
2547 }
2548 if (ndev->flags & IFF_ALLMULTI) {
2549 sh_eth_tsu_purge_mcast(ndev);
2550 ecmr_bits &= ~ECMR_MCT;
2551 mcast_all = 1;
2552 }
2553
86a74ff2 2554 if (ndev->flags & IFF_PROMISC) {
6743fe6d
YS		 2555 sh_eth_tsu_purge_all(ndev);
2556 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2557 } else if (mdp->cd->tsu) {
2558 struct netdev_hw_addr *ha;
2559 netdev_for_each_mc_addr(ha, ndev) {
2560 if (mcast_all && is_multicast_ether_addr(ha->addr))
2561 continue;
2562
2563 if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2564 if (!mcast_all) {
2565 sh_eth_tsu_purge_mcast(ndev);
2566 ecmr_bits &= ~ECMR_MCT;
2567 mcast_all = 1;
2568 }
2569 }
2570 }
86a74ff2 2571 }
6743fe6d
YS		 2572
2573 /* update the ethernet mode */
2574 sh_eth_write(ndev, ecmr_bits, ECMR);
2575
2576 spin_unlock_irqrestore(&mdp->lock, flags);
86a74ff2 2577}
71cc7c37
YS		 2578
2579static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2580{
2581 if (!mdp->port)
2582 return TSU_VTAG0;
2583 else
2584 return TSU_VTAG1;
2585}
2586
80d5c368
PM		 2587static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
2588 __be16 proto, u16 vid)
71cc7c37
YS		 2589{
2590 struct sh_eth_private *mdp = netdev_priv(ndev);
2591 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2592
2593 if (unlikely(!mdp->cd->tsu))
2594 return -EPERM;
2595
2596 /* No filtering if vid = 0 */
2597 if (!vid)
2598 return 0;
2599
2600 mdp->vlan_num_ids++;
2601
128296fc 2602 /* The controller has one VLAN tag HW filter. So, if the filter is
71cc7c37
YS		 2603 * already enabled, the driver disables it and the filte
2604 */
2605 if (mdp->vlan_num_ids > 1) {
2606 /* disable VLAN filter */
2607 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2608 return 0;
2609 }
2610
2611 sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
2612 vtag_reg_index);
2613
2614 return 0;
2615}
2616
80d5c368
PM		 2617static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
2618 __be16 proto, u16 vid)
71cc7c37
YS		 2619{
2620 struct sh_eth_private *mdp = netdev_priv(ndev);
2621 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2622
2623 if (unlikely(!mdp->cd->tsu))
2624 return -EPERM;
2625
2626 /* No filtering if vid = 0 */
2627 if (!vid)
2628 return 0;
2629
2630 mdp->vlan_num_ids--;
2631 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2632
2633 return 0;
2634}
86a74ff2
NI		 2635
2636/* SuperH's TSU register init function */
4a55530f 2637static void sh_eth_tsu_init(struct sh_eth_private *mdp)
86a74ff2 2638{
db893473
SH		 2639 if (sh_eth_is_rz_fast_ether(mdp)) {
2640 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2641 return;
2642 }
2643
4a55530f
YS		 2644 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */
2645 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */
2646 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */
2647 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
2648 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
2649 sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
2650 sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
2651 sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
2652 sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
2653 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
c5ed5368
YS		 2654 if (sh_eth_is_gether(mdp)) {
2655 sh_eth_tsu_write(mdp, 0, TSU_QTAG0); /* Disable QTAG(0->1) */
2656 sh_eth_tsu_write(mdp, 0, TSU_QTAG1); /* Disable QTAG(1->0) */
2657 } else {
2658 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */
2659 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */
2660 }
4a55530f
YS		 2661 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */
2662 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */
2663 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2664 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */
2665 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */
2666 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */
2667 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */
86a74ff2
NI		 2668}
2669
2670/* MDIO bus release function */
bd920ff5 2671static int sh_mdio_release(struct sh_eth_private *mdp)
86a74ff2 2672{
86a74ff2 2673 /* unregister mdio bus */
bd920ff5 2674 mdiobus_unregister(mdp->mii_bus);
86a74ff2
NI		 2675
2676 /* free bitbang info */
bd920ff5 2677 free_mdio_bitbang(mdp->mii_bus);
86a74ff2
NI		 2678
2679 return 0;
2680}
2681
2682/* MDIO bus init function */
bd920ff5 2683static int sh_mdio_init(struct sh_eth_private *mdp,
b3017e6a 2684 struct sh_eth_plat_data *pd)
86a74ff2
NI		 2685{
2686 int ret, i;
2687 struct bb_info *bitbang;
bd920ff5 2688 struct platform_device *pdev = mdp->pdev;
aa8d4225 2689 struct device *dev = &mdp->pdev->dev;
86a74ff2
NI		 2690
2691 /* create bit control struct for PHY */
aa8d4225 2692 bitbang = devm_kzalloc(dev, sizeof(struct bb_info), GFP_KERNEL);
f738a13d
LP		 2693 if (!bitbang)
2694 return -ENOMEM;
86a74ff2
NI		 2695
2696 /* bitbang init */
ae70644d 2697 bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
b3017e6a 2698 bitbang->set_gate = pd->set_mdio_gate;
dfed5e7f
SS		 2699 bitbang->mdi_msk = PIR_MDI;
2700 bitbang->mdo_msk = PIR_MDO;
2701 bitbang->mmd_msk = PIR_MMD;
2702 bitbang->mdc_msk = PIR_MDC;
86a74ff2
NI		 2703 bitbang->ctrl.ops = &bb_ops;
2704
c2e07b3a 2705 /* MII controller setting */
86a74ff2 2706 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
f738a13d
LP		 2707 if (!mdp->mii_bus)
2708 return -ENOMEM;
86a74ff2
NI		 2709
2710 /* Hook up MII support for ethtool */
2711 mdp->mii_bus->name = "sh_mii";
a5bd6060 2712 mdp->mii_bus->parent = dev;
5278fb54 2713 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
bd920ff5 2714 pdev->name, pdev->id);
86a74ff2
NI		 2715
2716 /* PHY IRQ */
86b5d251
SS		 2717 mdp->mii_bus->irq = devm_kmalloc_array(dev, PHY_MAX_ADDR, sizeof(int),
2718 GFP_KERNEL);
86a74ff2
NI		 2719 if (!mdp->mii_bus->irq) {
2720 ret = -ENOMEM;
2721 goto out_free_bus;
2722 }
2723
bd920ff5
LP		 2724 /* register MDIO bus */
2725 if (dev->of_node) {
2726 ret = of_mdiobus_register(mdp->mii_bus, dev->of_node);
702eca02
BD		 2727 } else {
2728 for (i = 0; i < PHY_MAX_ADDR; i++)
2729 mdp->mii_bus->irq[i] = PHY_POLL;
2730 if (pd->phy_irq > 0)
2731 mdp->mii_bus->irq[pd->phy] = pd->phy_irq;
2732
2733 ret = mdiobus_register(mdp->mii_bus);
2734 }
2735
86a74ff2 2736 if (ret)
d5e07e69 2737 goto out_free_bus;
86a74ff2 2738
86a74ff2
NI		 2739 return 0;
2740
86a74ff2 2741out_free_bus:
298cf9be 2742 free_mdio_bitbang(mdp->mii_bus);
86a74ff2
NI		 2743 return ret;
2744}
2745
4a55530f
YS		 2746static const u16 *sh_eth_get_register_offset(int register_type)
2747{
2748 const u16 *reg_offset = NULL;
2749
2750 switch (register_type) {
2751 case SH_ETH_REG_GIGABIT:
2752 reg_offset = sh_eth_offset_gigabit;
2753 break;
db893473
SH		 2754 case SH_ETH_REG_FAST_RZ:
2755 reg_offset = sh_eth_offset_fast_rz;
2756 break;
a3f109bd
SS		 2757 case SH_ETH_REG_FAST_RCAR:
2758 reg_offset = sh_eth_offset_fast_rcar;
2759 break;
4a55530f
YS		 2760 case SH_ETH_REG_FAST_SH4:
2761 reg_offset = sh_eth_offset_fast_sh4;
2762 break;
2763 case SH_ETH_REG_FAST_SH3_SH2:
2764 reg_offset = sh_eth_offset_fast_sh3_sh2;
2765 break;
2766 default:
4a55530f
YS		 2767 break;
2768 }
2769
2770 return reg_offset;
2771}
2772
8f728d79 2773static const struct net_device_ops sh_eth_netdev_ops = {
ebf84eaa
AB		 2774 .ndo_open = sh_eth_open,
2775 .ndo_stop = sh_eth_close,
2776 .ndo_start_xmit = sh_eth_start_xmit,
2777 .ndo_get_stats = sh_eth_get_stats,
b37feed7 2778 .ndo_set_rx_mode = sh_eth_set_rx_mode,
ebf84eaa
AB		 2779 .ndo_tx_timeout = sh_eth_tx_timeout,
2780 .ndo_do_ioctl = sh_eth_do_ioctl,
2781 .ndo_validate_addr = eth_validate_addr,
2782 .ndo_set_mac_address = eth_mac_addr,
2783 .ndo_change_mtu = eth_change_mtu,
2784};
2785
8f728d79
SS		 2786static const struct net_device_ops sh_eth_netdev_ops_tsu = {
2787 .ndo_open = sh_eth_open,
2788 .ndo_stop = sh_eth_close,
2789 .ndo_start_xmit = sh_eth_start_xmit,
2790 .ndo_get_stats = sh_eth_get_stats,
b37feed7 2791 .ndo_set_rx_mode = sh_eth_set_rx_mode,
8f728d79
SS		 2792 .ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid,
2793 .ndo_vlan_rx_kill_vid = sh_eth_vlan_rx_kill_vid,
2794 .ndo_tx_timeout = sh_eth_tx_timeout,
2795 .ndo_do_ioctl = sh_eth_do_ioctl,
2796 .ndo_validate_addr = eth_validate_addr,
2797 .ndo_set_mac_address = eth_mac_addr,
2798 .ndo_change_mtu = eth_change_mtu,
2799};
2800
b356e978
SS		 2801#ifdef CONFIG_OF
2802static struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
2803{
2804 struct device_node *np = dev->of_node;
2805 struct sh_eth_plat_data *pdata;
b356e978
SS		 2806 const char *mac_addr;
2807
2808 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
2809 if (!pdata)
2810 return NULL;
2811
2812 pdata->phy_interface = of_get_phy_mode(np);
2813
b356e978
SS		 2814 mac_addr = of_get_mac_address(np);
2815 if (mac_addr)
2816 memcpy(pdata->mac_addr, mac_addr, ETH_ALEN);
2817
2818 pdata->no_ether_link =
2819 of_property_read_bool(np, "renesas,no-ether-link");
2820 pdata->ether_link_active_low =
2821 of_property_read_bool(np, "renesas,ether-link-active-low");
2822
2823 return pdata;
2824}
2825
2826static const struct of_device_id sh_eth_match_table[] = {
2827 { .compatible = "renesas,gether-r8a7740", .data = &r8a7740_data },
2828 { .compatible = "renesas,ether-r8a7778", .data = &r8a777x_data },
2829 { .compatible = "renesas,ether-r8a7779", .data = &r8a777x_data },
2830 { .compatible = "renesas,ether-r8a7790", .data = &r8a779x_data },
2831 { .compatible = "renesas,ether-r8a7791", .data = &r8a779x_data },
9488e1e5 2832 { .compatible = "renesas,ether-r8a7793", .data = &r8a779x_data },
0f76b9d8 2833 { .compatible = "renesas,ether-r8a7794", .data = &r8a779x_data },
b356e978
SS		 2834 { .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data },
2835 { }
2836};
2837MODULE_DEVICE_TABLE(of, sh_eth_match_table);
2838#else
2839static inline struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
2840{
2841 return NULL;
2842}
2843#endif
2844
86a74ff2
NI		 2845static int sh_eth_drv_probe(struct platform_device *pdev)
2846{
9c38657c 2847 int ret, devno = 0;
86a74ff2
NI		 2848 struct resource *res;
2849 struct net_device *ndev = NULL;
ec0d7551 2850 struct sh_eth_private *mdp = NULL;
0b76b862 2851 struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev);
afe391ad 2852 const struct platform_device_id *id = platform_get_device_id(pdev);
86a74ff2
NI		 2853
2854 /* get base addr */
2855 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
86a74ff2
NI		 2856
2857 ndev = alloc_etherdev(sizeof(struct sh_eth_private));
f738a13d
LP		 2858 if (!ndev)
2859 return -ENOMEM;
86a74ff2 2860
b5893a08
BD		 2861 pm_runtime_enable(&pdev->dev);
2862 pm_runtime_get_sync(&pdev->dev);
2863
86a74ff2
NI		 2864 devno = pdev->id;
2865 if (devno < 0)
2866 devno = 0;
2867
2868 ndev->dma = -1;
cc3c080d 2869 ret = platform_get_irq(pdev, 0);
2870 if (ret < 0) {
86a74ff2
NI		 2871 ret = -ENODEV;
2872 goto out_release;
2873 }
cc3c080d 2874 ndev->irq = ret;
86a74ff2
NI		 2875
2876 SET_NETDEV_DEV(ndev, &pdev->dev);
2877
86a74ff2 2878 mdp = netdev_priv(ndev);
525b8075
YS		 2879 mdp->num_tx_ring = TX_RING_SIZE;
2880 mdp->num_rx_ring = RX_RING_SIZE;
d5e07e69
SS		 2881 mdp->addr = devm_ioremap_resource(&pdev->dev, res);
2882 if (IS_ERR(mdp->addr)) {
2883 ret = PTR_ERR(mdp->addr);
ae70644d
YS		 2884 goto out_release;
2885 }
2886
c960804f
VB		 2887 ndev->base_addr = res->start;
2888
86a74ff2 2889 spin_lock_init(&mdp->lock);
bcd5149d 2890 mdp->pdev = pdev;
86a74ff2 2891
b356e978
SS		 2892 if (pdev->dev.of_node)
2893 pd = sh_eth_parse_dt(&pdev->dev);
3b4c5cbf
SS		 2894 if (!pd) {
2895 dev_err(&pdev->dev, "no platform data\n");
2896 ret = -EINVAL;
2897 goto out_release;
2898 }
2899
86a74ff2 2900 /* get PHY ID */
71557a37 2901 mdp->phy_id = pd->phy;
e47c9052 2902 mdp->phy_interface = pd->phy_interface;
71557a37
YS		 2903 /* EDMAC endian */
2904 mdp->edmac_endian = pd->edmac_endian;
4923576b
YS		 2905 mdp->no_ether_link = pd->no_ether_link;
2906 mdp->ether_link_active_low = pd->ether_link_active_low;
86a74ff2 2907
380af9e3 2908 /* set cpu data */
b356e978
SS		 2909 if (id) {
2910 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data;
2911 } else {
2912 const struct of_device_id *match;
2913
2914 match = of_match_device(of_match_ptr(sh_eth_match_table),
2915 &pdev->dev);
2916 mdp->cd = (struct sh_eth_cpu_data *)match->data;
2917 }
a3153d8c 2918 mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type);
264be2f5
SS		 2919 if (!mdp->reg_offset) {
2920 dev_err(&pdev->dev, "Unknown register type (%d)\n",
2921 mdp->cd->register_type);
2922 ret = -EINVAL;
2923 goto out_release;
2924 }
380af9e3
YS		 2925 sh_eth_set_default_cpu_data(mdp->cd);
2926
86a74ff2 2927 /* set function */
8f728d79
SS		 2928 if (mdp->cd->tsu)
2929 ndev->netdev_ops = &sh_eth_netdev_ops_tsu;
2930 else
2931 ndev->netdev_ops = &sh_eth_netdev_ops;
7ad24ea4 2932 ndev->ethtool_ops = &sh_eth_ethtool_ops;
86a74ff2
NI		 2933 ndev->watchdog_timeo = TX_TIMEOUT;
2934
dc19e4e5
NI		 2935 /* debug message level */
2936 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
86a74ff2
NI		 2937
2938 /* read and set MAC address */
748031f9 2939 read_mac_address(ndev, pd->mac_addr);
ff6e7228
SS		 2940 if (!is_valid_ether_addr(ndev->dev_addr)) {
2941 dev_warn(&pdev->dev,
2942 "no valid MAC address supplied, using a random one.\n");
2943 eth_hw_addr_random(ndev);
2944 }
86a74ff2 2945
6ba88021
YS		 2946 /* ioremap the TSU registers */
2947 if (mdp->cd->tsu) {
2948 struct resource *rtsu;
2949 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
d5e07e69
SS		 2950 mdp->tsu_addr = devm_ioremap_resource(&pdev->dev, rtsu);
2951 if (IS_ERR(mdp->tsu_addr)) {
2952 ret = PTR_ERR(mdp->tsu_addr);
fc0c0900
SS		 2953 goto out_release;
2954 }
6743fe6d 2955 mdp->port = devno % 2;
f646968f 2956 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER;
6ba88021
YS		 2957 }
2958
150647fb
YS		 2959 /* initialize first or needed device */
2960 if (!devno || pd->needs_init) {
380af9e3
YS		 2961 if (mdp->cd->chip_reset)
2962 mdp->cd->chip_reset(ndev);
86a74ff2 2963
4986b996
YS		 2964 if (mdp->cd->tsu) {
2965 /* TSU init (Init only)*/
2966 sh_eth_tsu_init(mdp);
2967 }
86a74ff2
NI		 2968 }
2969
966d6dbb
HN		 2970 if (mdp->cd->rmiimode)
2971 sh_eth_write(ndev, 0x1, RMIIMODE);
2972
daacf03f
LP		 2973 /* MDIO bus init */
2974 ret = sh_mdio_init(mdp, pd);
2975 if (ret) {
2976 dev_err(&ndev->dev, "failed to initialise MDIO\n");
2977 goto out_release;
2978 }
2979
3719109d
SS		 2980 netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64);
2981
86a74ff2
NI		 2982 /* network device register */
2983 ret = register_netdev(ndev);
2984 if (ret)
3719109d 2985 goto out_napi_del;
86a74ff2 2986
25985edc 2987 /* print device information */
f75f14ec
SS		 2988 netdev_info(ndev, "Base address at 0x%x, %pM, IRQ %d.\n",
2989 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
86a74ff2 2990
b5893a08 2991 pm_runtime_put(&pdev->dev);
86a74ff2
NI		 2992 platform_set_drvdata(pdev, ndev);
2993
2994 return ret;
2995
3719109d
SS		 2996out_napi_del:
2997 netif_napi_del(&mdp->napi);
daacf03f 2998 sh_mdio_release(mdp);
3719109d 2999
86a74ff2
NI		 3000out_release:
3001 /* net_dev free */
3002 if (ndev)
3003 free_netdev(ndev);
3004
b5893a08
BD		 3005 pm_runtime_put(&pdev->dev);
3006 pm_runtime_disable(&pdev->dev);
86a74ff2
NI		 3007 return ret;
3008}
3009
3010static int sh_eth_drv_remove(struct platform_device *pdev)
3011{
3012 struct net_device *ndev = platform_get_drvdata(pdev);
3719109d 3013 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2 3014
86a74ff2 3015 unregister_netdev(ndev);
3719109d 3016 netif_napi_del(&mdp->napi);
daacf03f 3017 sh_mdio_release(mdp);
bcd5149d 3018 pm_runtime_disable(&pdev->dev);
86a74ff2 3019 free_netdev(ndev);
86a74ff2
NI		 3020
3021 return 0;
3022}
3023
540ad1b8 3024#ifdef CONFIG_PM
b71af046
MU		 3025#ifdef CONFIG_PM_SLEEP
3026static int sh_eth_suspend(struct device *dev)
3027{
3028 struct net_device *ndev = dev_get_drvdata(dev);
3029 int ret = 0;
3030
3031 if (netif_running(ndev)) {
3032 netif_device_detach(ndev);
3033 ret = sh_eth_close(ndev);
3034 }
3035
3036 return ret;
3037}
3038
3039static int sh_eth_resume(struct device *dev)
3040{
3041 struct net_device *ndev = dev_get_drvdata(dev);
3042 int ret = 0;
3043
3044 if (netif_running(ndev)) {
3045 ret = sh_eth_open(ndev);
3046 if (ret < 0)
3047 return ret;
3048 netif_device_attach(ndev);
3049 }
3050
3051 return ret;
3052}
3053#endif
3054
bcd5149d
MD		 3055static int sh_eth_runtime_nop(struct device *dev)
3056{
128296fc 3057 /* Runtime PM callback shared between ->runtime_suspend()
bcd5149d
MD		 3058 * and ->runtime_resume(). Simply returns success.
3059 *
3060 * This driver re-initializes all registers after
3061 * pm_runtime_get_sync() anyway so there is no need
3062 * to save and restore registers here.
3063 */
3064 return 0;
3065}
3066
540ad1b8 3067static const struct dev_pm_ops sh_eth_dev_pm_ops = {
b71af046 3068 SET_SYSTEM_SLEEP_PM_OPS(sh_eth_suspend, sh_eth_resume)
e7d7e898 3069 SET_RUNTIME_PM_OPS(sh_eth_runtime_nop, sh_eth_runtime_nop, NULL)
bcd5149d 3070};
540ad1b8
NI		 3071#define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
3072#else
3073#define SH_ETH_PM_OPS NULL
3074#endif
bcd5149d 3075
afe391ad 3076static struct platform_device_id sh_eth_id_table[] = {
c18a79ab 3077 { "sh7619-ether", (kernel_ulong_t)&sh7619_data },
7bbe150d 3078 { "sh771x-ether", (kernel_ulong_t)&sh771x_data },
9c3beaab 3079 { "sh7724-ether", (kernel_ulong_t)&sh7724_data },
f5d12767 3080 { "sh7734-gether", (kernel_ulong_t)&sh7734_data },
24549e2a
SS		 3081 { "sh7757-ether", (kernel_ulong_t)&sh7757_data },
3082 { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga },
f5d12767 3083 { "sh7763-gether", (kernel_ulong_t)&sh7763_data },
db893473 3084 { "r7s72100-ether", (kernel_ulong_t)&r7s72100_data },
e5c9b4cd 3085 { "r8a7740-gether", (kernel_ulong_t)&r8a7740_data },
589ebdef 3086 { "r8a777x-ether", (kernel_ulong_t)&r8a777x_data },
94a12b15
SS		 3087 { "r8a7790-ether", (kernel_ulong_t)&r8a779x_data },
3088 { "r8a7791-ether", (kernel_ulong_t)&r8a779x_data },
9488e1e5 3089 { "r8a7793-ether", (kernel_ulong_t)&r8a779x_data },
0f76b9d8 3090 { "r8a7794-ether", (kernel_ulong_t)&r8a779x_data },
afe391ad
SS		 3091 { }
3092};
3093MODULE_DEVICE_TABLE(platform, sh_eth_id_table);
3094
86a74ff2
NI		 3095static struct platform_driver sh_eth_driver = {
3096 .probe = sh_eth_drv_probe,
3097 .remove = sh_eth_drv_remove,
afe391ad 3098 .id_table = sh_eth_id_table,
86a74ff2
NI		 3099 .driver = {
3100 .name = CARDNAME,
540ad1b8 3101 .pm = SH_ETH_PM_OPS,
b356e978 3102 .of_match_table = of_match_ptr(sh_eth_match_table),
86a74ff2
NI		 3103 },
3104};
3105
db62f684 3106module_platform_driver(sh_eth_driver);
86a74ff2
NI		 3107
3108MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
3109MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
3110MODULE_LICENSE("GPL v2");
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