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sh_eth: get SH77{34|63} support out of #ifdef
[mirror_ubuntu-hirsute-kernel.git] / drivers / net / ethernet / renesas / sh_eth.c
CommitLineData
86a74ff2
NI		 1/*
2 * SuperH Ethernet device driver
3 *
f0e81fec 4 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu
a3f109bd
SS		 5 * Copyright (C) 2008-2013 Renesas Solutions Corp.
6 * Copyright (C) 2013 Cogent Embedded, Inc.
86a74ff2
NI		 7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 * You should have received a copy of the GNU General Public License along with
17 * this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * The full GNU General Public License is included in this distribution in
21 * the file called "COPYING".
22 */
23
86a74ff2 24#include <linux/init.h>
0654011d
YS		 25#include <linux/module.h>
26#include <linux/kernel.h>
27#include <linux/spinlock.h>
6a27cded 28#include <linux/interrupt.h>
86a74ff2
NI		 29#include <linux/dma-mapping.h>
30#include <linux/etherdevice.h>
31#include <linux/delay.h>
32#include <linux/platform_device.h>
33#include <linux/mdio-bitbang.h>
34#include <linux/netdevice.h>
35#include <linux/phy.h>
36#include <linux/cache.h>
37#include <linux/io.h>
bcd5149d 38#include <linux/pm_runtime.h>
5a0e3ad6 39#include <linux/slab.h>
dc19e4e5 40#include <linux/ethtool.h>
fdb37a7f 41#include <linux/if_vlan.h>
f0e81fec 42#include <linux/clk.h>
d4fa0e35 43#include <linux/sh_eth.h>
86a74ff2
NI		 44
45#include "sh_eth.h"
46
dc19e4e5
NI		 47#define SH_ETH_DEF_MSG_ENABLE \
48 (NETIF_MSG_LINK | \
49 NETIF_MSG_TIMER | \
50 NETIF_MSG_RX_ERR| \
51 NETIF_MSG_TX_ERR)
52
c0013f6f
SS		 53static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
54 [EDSR] = 0x0000,
55 [EDMR] = 0x0400,
56 [EDTRR] = 0x0408,
57 [EDRRR] = 0x0410,
58 [EESR] = 0x0428,
59 [EESIPR] = 0x0430,
60 [TDLAR] = 0x0010,
61 [TDFAR] = 0x0014,
62 [TDFXR] = 0x0018,
63 [TDFFR] = 0x001c,
64 [RDLAR] = 0x0030,
65 [RDFAR] = 0x0034,
66 [RDFXR] = 0x0038,
67 [RDFFR] = 0x003c,
68 [TRSCER] = 0x0438,
69 [RMFCR] = 0x0440,
70 [TFTR] = 0x0448,
71 [FDR] = 0x0450,
72 [RMCR] = 0x0458,
73 [RPADIR] = 0x0460,
74 [FCFTR] = 0x0468,
75 [CSMR] = 0x04E4,
76
77 [ECMR] = 0x0500,
78 [ECSR] = 0x0510,
79 [ECSIPR] = 0x0518,
80 [PIR] = 0x0520,
81 [PSR] = 0x0528,
82 [PIPR] = 0x052c,
83 [RFLR] = 0x0508,
84 [APR] = 0x0554,
85 [MPR] = 0x0558,
86 [PFTCR] = 0x055c,
87 [PFRCR] = 0x0560,
88 [TPAUSER] = 0x0564,
89 [GECMR] = 0x05b0,
90 [BCULR] = 0x05b4,
91 [MAHR] = 0x05c0,
92 [MALR] = 0x05c8,
93 [TROCR] = 0x0700,
94 [CDCR] = 0x0708,
95 [LCCR] = 0x0710,
96 [CEFCR] = 0x0740,
97 [FRECR] = 0x0748,
98 [TSFRCR] = 0x0750,
99 [TLFRCR] = 0x0758,
100 [RFCR] = 0x0760,
101 [CERCR] = 0x0768,
102 [CEECR] = 0x0770,
103 [MAFCR] = 0x0778,
104 [RMII_MII] = 0x0790,
105
106 [ARSTR] = 0x0000,
107 [TSU_CTRST] = 0x0004,
108 [TSU_FWEN0] = 0x0010,
109 [TSU_FWEN1] = 0x0014,
110 [TSU_FCM] = 0x0018,
111 [TSU_BSYSL0] = 0x0020,
112 [TSU_BSYSL1] = 0x0024,
113 [TSU_PRISL0] = 0x0028,
114 [TSU_PRISL1] = 0x002c,
115 [TSU_FWSL0] = 0x0030,
116 [TSU_FWSL1] = 0x0034,
117 [TSU_FWSLC] = 0x0038,
118 [TSU_QTAG0] = 0x0040,
119 [TSU_QTAG1] = 0x0044,
120 [TSU_FWSR] = 0x0050,
121 [TSU_FWINMK] = 0x0054,
122 [TSU_ADQT0] = 0x0048,
123 [TSU_ADQT1] = 0x004c,
124 [TSU_VTAG0] = 0x0058,
125 [TSU_VTAG1] = 0x005c,
126 [TSU_ADSBSY] = 0x0060,
127 [TSU_TEN] = 0x0064,
128 [TSU_POST1] = 0x0070,
129 [TSU_POST2] = 0x0074,
130 [TSU_POST3] = 0x0078,
131 [TSU_POST4] = 0x007c,
132 [TSU_ADRH0] = 0x0100,
133 [TSU_ADRL0] = 0x0104,
134 [TSU_ADRH31] = 0x01f8,
135 [TSU_ADRL31] = 0x01fc,
136
137 [TXNLCR0] = 0x0080,
138 [TXALCR0] = 0x0084,
139 [RXNLCR0] = 0x0088,
140 [RXALCR0] = 0x008c,
141 [FWNLCR0] = 0x0090,
142 [FWALCR0] = 0x0094,
143 [TXNLCR1] = 0x00a0,
144 [TXALCR1] = 0x00a0,
145 [RXNLCR1] = 0x00a8,
146 [RXALCR1] = 0x00ac,
147 [FWNLCR1] = 0x00b0,
148 [FWALCR1] = 0x00b4,
149};
150
a3f109bd
SS		 151static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
152 [ECMR] = 0x0300,
153 [RFLR] = 0x0308,
154 [ECSR] = 0x0310,
155 [ECSIPR] = 0x0318,
156 [PIR] = 0x0320,
157 [PSR] = 0x0328,
158 [RDMLR] = 0x0340,
159 [IPGR] = 0x0350,
160 [APR] = 0x0354,
161 [MPR] = 0x0358,
162 [RFCF] = 0x0360,
163 [TPAUSER] = 0x0364,
164 [TPAUSECR] = 0x0368,
165 [MAHR] = 0x03c0,
166 [MALR] = 0x03c8,
167 [TROCR] = 0x03d0,
168 [CDCR] = 0x03d4,
169 [LCCR] = 0x03d8,
170 [CNDCR] = 0x03dc,
171 [CEFCR] = 0x03e4,
172 [FRECR] = 0x03e8,
173 [TSFRCR] = 0x03ec,
174 [TLFRCR] = 0x03f0,
175 [RFCR] = 0x03f4,
176 [MAFCR] = 0x03f8,
177
178 [EDMR] = 0x0200,
179 [EDTRR] = 0x0208,
180 [EDRRR] = 0x0210,
181 [TDLAR] = 0x0218,
182 [RDLAR] = 0x0220,
183 [EESR] = 0x0228,
184 [EESIPR] = 0x0230,
185 [TRSCER] = 0x0238,
186 [RMFCR] = 0x0240,
187 [TFTR] = 0x0248,
188 [FDR] = 0x0250,
189 [RMCR] = 0x0258,
190 [TFUCR] = 0x0264,
191 [RFOCR] = 0x0268,
192 [FCFTR] = 0x0270,
193 [TRIMD] = 0x027c,
194};
195
c0013f6f
SS		 196static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
197 [ECMR] = 0x0100,
198 [RFLR] = 0x0108,
199 [ECSR] = 0x0110,
200 [ECSIPR] = 0x0118,
201 [PIR] = 0x0120,
202 [PSR] = 0x0128,
203 [RDMLR] = 0x0140,
204 [IPGR] = 0x0150,
205 [APR] = 0x0154,
206 [MPR] = 0x0158,
207 [TPAUSER] = 0x0164,
208 [RFCF] = 0x0160,
209 [TPAUSECR] = 0x0168,
210 [BCFRR] = 0x016c,
211 [MAHR] = 0x01c0,
212 [MALR] = 0x01c8,
213 [TROCR] = 0x01d0,
214 [CDCR] = 0x01d4,
215 [LCCR] = 0x01d8,
216 [CNDCR] = 0x01dc,
217 [CEFCR] = 0x01e4,
218 [FRECR] = 0x01e8,
219 [TSFRCR] = 0x01ec,
220 [TLFRCR] = 0x01f0,
221 [RFCR] = 0x01f4,
222 [MAFCR] = 0x01f8,
223 [RTRATE] = 0x01fc,
224
225 [EDMR] = 0x0000,
226 [EDTRR] = 0x0008,
227 [EDRRR] = 0x0010,
228 [TDLAR] = 0x0018,
229 [RDLAR] = 0x0020,
230 [EESR] = 0x0028,
231 [EESIPR] = 0x0030,
232 [TRSCER] = 0x0038,
233 [RMFCR] = 0x0040,
234 [TFTR] = 0x0048,
235 [FDR] = 0x0050,
236 [RMCR] = 0x0058,
237 [TFUCR] = 0x0064,
238 [RFOCR] = 0x0068,
239 [FCFTR] = 0x0070,
240 [RPADIR] = 0x0078,
241 [TRIMD] = 0x007c,
242 [RBWAR] = 0x00c8,
243 [RDFAR] = 0x00cc,
244 [TBRAR] = 0x00d4,
245 [TDFAR] = 0x00d8,
246};
247
248static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
249 [ECMR] = 0x0160,
250 [ECSR] = 0x0164,
251 [ECSIPR] = 0x0168,
252 [PIR] = 0x016c,
253 [MAHR] = 0x0170,
254 [MALR] = 0x0174,
255 [RFLR] = 0x0178,
256 [PSR] = 0x017c,
257 [TROCR] = 0x0180,
258 [CDCR] = 0x0184,
259 [LCCR] = 0x0188,
260 [CNDCR] = 0x018c,
261 [CEFCR] = 0x0194,
262 [FRECR] = 0x0198,
263 [TSFRCR] = 0x019c,
264 [TLFRCR] = 0x01a0,
265 [RFCR] = 0x01a4,
266 [MAFCR] = 0x01a8,
267 [IPGR] = 0x01b4,
268 [APR] = 0x01b8,
269 [MPR] = 0x01bc,
270 [TPAUSER] = 0x01c4,
271 [BCFR] = 0x01cc,
272
273 [ARSTR] = 0x0000,
274 [TSU_CTRST] = 0x0004,
275 [TSU_FWEN0] = 0x0010,
276 [TSU_FWEN1] = 0x0014,
277 [TSU_FCM] = 0x0018,
278 [TSU_BSYSL0] = 0x0020,
279 [TSU_BSYSL1] = 0x0024,
280 [TSU_PRISL0] = 0x0028,
281 [TSU_PRISL1] = 0x002c,
282 [TSU_FWSL0] = 0x0030,
283 [TSU_FWSL1] = 0x0034,
284 [TSU_FWSLC] = 0x0038,
285 [TSU_QTAGM0] = 0x0040,
286 [TSU_QTAGM1] = 0x0044,
287 [TSU_ADQT0] = 0x0048,
288 [TSU_ADQT1] = 0x004c,
289 [TSU_FWSR] = 0x0050,
290 [TSU_FWINMK] = 0x0054,
291 [TSU_ADSBSY] = 0x0060,
292 [TSU_TEN] = 0x0064,
293 [TSU_POST1] = 0x0070,
294 [TSU_POST2] = 0x0074,
295 [TSU_POST3] = 0x0078,
296 [TSU_POST4] = 0x007c,
297
298 [TXNLCR0] = 0x0080,
299 [TXALCR0] = 0x0084,
300 [RXNLCR0] = 0x0088,
301 [RXALCR0] = 0x008c,
302 [FWNLCR0] = 0x0090,
303 [FWALCR0] = 0x0094,
304 [TXNLCR1] = 0x00a0,
305 [TXALCR1] = 0x00a0,
306 [RXNLCR1] = 0x00a8,
307 [RXALCR1] = 0x00ac,
308 [FWNLCR1] = 0x00b0,
309 [FWALCR1] = 0x00b4,
310
311 [TSU_ADRH0] = 0x0100,
312 [TSU_ADRL0] = 0x0104,
313 [TSU_ADRL31] = 0x01fc,
314};
315
dabdde9e
NI		 316static int sh_eth_is_gether(struct sh_eth_private *mdp)
317{
318 if (mdp->reg_offset == sh_eth_offset_gigabit)
319 return 1;
320 else
321 return 0;
322}
323
b7feacf1 324static void __maybe_unused sh_eth_select_mii(struct net_device *ndev)
5e7a76be
NI		 325{
326 u32 value = 0x0;
327 struct sh_eth_private *mdp = netdev_priv(ndev);
328
329 switch (mdp->phy_interface) {
330 case PHY_INTERFACE_MODE_GMII:
331 value = 0x2;
332 break;
333 case PHY_INTERFACE_MODE_MII:
334 value = 0x1;
335 break;
336 case PHY_INTERFACE_MODE_RMII:
337 value = 0x0;
338 break;
339 default:
340 pr_warn("PHY interface mode was not setup. Set to MII.\n");
341 value = 0x1;
342 break;
343 }
344
345 sh_eth_write(ndev, value, RMII_MII);
346}
5e7a76be 347
04b0ed2a 348static void __maybe_unused sh_eth_set_duplex(struct net_device *ndev)
65ac8851
YS		 349{
350 struct sh_eth_private *mdp = netdev_priv(ndev);
65ac8851
YS		 351
352 if (mdp->duplex) /* Full */
4a55530f 353 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
65ac8851 354 else /* Half */
4a55530f 355 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
65ac8851
YS		 356}
357
04b0ed2a
NI		 358/* There is CPU dependent code */
359#if defined(CONFIG_ARCH_R8A7778) || defined(CONFIG_ARCH_R8A7779)
65ac8851
YS		 360static void sh_eth_set_rate(struct net_device *ndev)
361{
362 struct sh_eth_private *mdp = netdev_priv(ndev);
d0418bb7 363
a3f109bd
SS		 364 switch (mdp->speed) {
365 case 10: /* 10BASE */
366 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_ELB, ECMR);
367 break;
368 case 100:/* 100BASE */
369 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_ELB, ECMR);
370 break;
371 default:
372 break;
373 }
374}
375
674853b2 376/* R8A7778/9 */
a3f109bd
SS		 377static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
378 .set_duplex = sh_eth_set_duplex,
379 .set_rate = sh_eth_set_rate,
380
381 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
382 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
383 .eesipr_value = 0x01ff009f,
384
385 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
386 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE |
387 EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI,
388 .tx_error_check = EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE,
389
390 .apr = 1,
391 .mpr = 1,
392 .tpauser = 1,
393 .hw_swap = 1,
394};
395#elif defined(CONFIG_CPU_SUBTYPE_SH7724)
a3f109bd
SS		 396
397static void sh_eth_set_rate(struct net_device *ndev)
398{
399 struct sh_eth_private *mdp = netdev_priv(ndev);
65ac8851
YS		 400
401 switch (mdp->speed) {
402 case 10: /* 10BASE */
a3f109bd 403 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_RTM, ECMR);
65ac8851
YS		 404 break;
405 case 100:/* 100BASE */
a3f109bd 406 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_RTM, ECMR);
65ac8851
YS		 407 break;
408 default:
409 break;
410 }
411}
412
413/* SH7724 */
414static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
415 .set_duplex = sh_eth_set_duplex,
416 .set_rate = sh_eth_set_rate,
417
418 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
419 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
420 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x01ff009f,
421
422 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
423 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE |
424 EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI,
425 .tx_error_check = EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE,
426
427 .apr = 1,
428 .mpr = 1,
429 .tpauser = 1,
430 .hw_swap = 1,
503914cf
MD		 431 .rpadir = 1,
432 .rpadir_value = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
65ac8851 433};
f29a3d04 434#elif defined(CONFIG_CPU_SUBTYPE_SH7757)
8fcd4961 435#define SH_ETH_HAS_BOTH_MODULES 1
5cee1d37 436
f29a3d04
YS		 437static void sh_eth_set_rate(struct net_device *ndev)
438{
439 struct sh_eth_private *mdp = netdev_priv(ndev);
f29a3d04
YS		 440
441 switch (mdp->speed) {
442 case 10: /* 10BASE */
4a55530f 443 sh_eth_write(ndev, 0, RTRATE);
f29a3d04
YS		 444 break;
445 case 100:/* 100BASE */
4a55530f 446 sh_eth_write(ndev, 1, RTRATE);
f29a3d04
YS		 447 break;
448 default:
449 break;
450 }
451}
452
453/* SH7757 */
454static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
455 .set_duplex = sh_eth_set_duplex,
456 .set_rate = sh_eth_set_rate,
457
458 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
459 .rmcr_value = 0x00000001,
460
461 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
462 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE |
463 EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI,
464 .tx_error_check = EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE,
465
5b3dfd13 466 .irq_flags = IRQF_SHARED,
f29a3d04
YS		 467 .apr = 1,
468 .mpr = 1,
469 .tpauser = 1,
470 .hw_swap = 1,
471 .no_ade = 1,
2e98e797
YS		 472 .rpadir = 1,
473 .rpadir_value = 2 << 16,
f29a3d04 474};
65ac8851 475
8fcd4961
YS		 476#define SH_GIGA_ETH_BASE 0xfee00000
477#define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
478#define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
479static void sh_eth_chip_reset_giga(struct net_device *ndev)
480{
481 int i;
482 unsigned long mahr[2], malr[2];
483
484 /* save MAHR and MALR */
485 for (i = 0; i < 2; i++) {
ae70644d
YS		 486 malr[i] = ioread32((void *)GIGA_MALR(i));
487 mahr[i] = ioread32((void *)GIGA_MAHR(i));
8fcd4961
YS		 488 }
489
490 /* reset device */
ae70644d 491 iowrite32(ARSTR_ARSTR, (void *)(SH_GIGA_ETH_BASE + 0x1800));
8fcd4961
YS		 492 mdelay(1);
493
494 /* restore MAHR and MALR */
495 for (i = 0; i < 2; i++) {
ae70644d
YS		 496 iowrite32(malr[i], (void *)GIGA_MALR(i));
497 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
8fcd4961
YS		 498 }
499}
500
8fcd4961
YS		 501static void sh_eth_set_rate_giga(struct net_device *ndev)
502{
503 struct sh_eth_private *mdp = netdev_priv(ndev);
504
505 switch (mdp->speed) {
506 case 10: /* 10BASE */
507 sh_eth_write(ndev, 0x00000000, GECMR);
508 break;
509 case 100:/* 100BASE */
510 sh_eth_write(ndev, 0x00000010, GECMR);
511 break;
512 case 1000: /* 1000BASE */
513 sh_eth_write(ndev, 0x00000020, GECMR);
514 break;
515 default:
516 break;
517 }
518}
519
520/* SH7757(GETHERC) */
521static struct sh_eth_cpu_data sh_eth_my_cpu_data_giga = {
522 .chip_reset = sh_eth_chip_reset_giga,
04b0ed2a 523 .set_duplex = sh_eth_set_duplex,
8fcd4961
YS		 524 .set_rate = sh_eth_set_rate_giga,
525
526 .ecsr_value = ECSR_ICD | ECSR_MPD,
527 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
528 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
529
530 .tx_check = EESR_TC1 | EESR_FTC,
531 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \
532 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \
533 EESR_ECI,
534 .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \
535 EESR_TFE,
536 .fdr_value = 0x0000072f,
537 .rmcr_value = 0x00000001,
538
5b3dfd13 539 .irq_flags = IRQF_SHARED,
8fcd4961
YS		 540 .apr = 1,
541 .mpr = 1,
542 .tpauser = 1,
543 .bculr = 1,
544 .hw_swap = 1,
545 .rpadir = 1,
546 .rpadir_value = 2 << 16,
547 .no_trimd = 1,
548 .no_ade = 1,
3acbc971 549 .tsu = 1,
8fcd4961
YS		 550};
551
552static struct sh_eth_cpu_data *sh_eth_get_cpu_data(struct sh_eth_private *mdp)
553{
554 if (sh_eth_is_gether(mdp))
555 return &sh_eth_my_cpu_data_giga;
556 else
557 return &sh_eth_my_cpu_data;
558}
f5d12767 559#endif
5e7a76be 560
380af9e3
YS		 561static void sh_eth_chip_reset(struct net_device *ndev)
562{
4986b996
YS		 563 struct sh_eth_private *mdp = netdev_priv(ndev);
564
380af9e3 565 /* reset device */
4986b996 566 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
380af9e3
YS		 567 mdelay(1);
568}
569
f5d12767 570static void sh_eth_set_rate_gether(struct net_device *ndev)
380af9e3
YS		 571{
572 struct sh_eth_private *mdp = netdev_priv(ndev);
380af9e3
YS		 573
574 switch (mdp->speed) {
575 case 10: /* 10BASE */
4a55530f 576 sh_eth_write(ndev, GECMR_10, GECMR);
380af9e3
YS		 577 break;
578 case 100:/* 100BASE */
4a55530f 579 sh_eth_write(ndev, GECMR_100, GECMR);
380af9e3
YS		 580 break;
581 case 1000: /* 1000BASE */
4a55530f 582 sh_eth_write(ndev, GECMR_1000, GECMR);
380af9e3
YS		 583 break;
584 default:
585 break;
586 }
587}
588
f5d12767
SS		 589/* SH7734 */
590static struct sh_eth_cpu_data sh7734_data = {
380af9e3
YS		 591 .chip_reset = sh_eth_chip_reset,
592 .set_duplex = sh_eth_set_duplex,
f5d12767
SS		 593 .set_rate = sh_eth_set_rate_gether,
594
595 .ecsr_value = ECSR_ICD | ECSR_MPD,
596 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
597 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
598
599 .tx_check = EESR_TC1 | EESR_FTC,
600 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \
601 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \
602 EESR_ECI,
603 .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \
604 EESR_TFE,
605
606 .apr = 1,
607 .mpr = 1,
608 .tpauser = 1,
609 .bculr = 1,
610 .hw_swap = 1,
611 .no_trimd = 1,
612 .no_ade = 1,
613 .tsu = 1,
614 .hw_crc = 1,
615 .select_mii = 1,
616};
617
618/* SH7763 */
619static struct sh_eth_cpu_data sh7763_data = {
620 .chip_reset = sh_eth_chip_reset,
621 .set_duplex = sh_eth_set_duplex,
622 .set_rate = sh_eth_set_rate_gether,
380af9e3
YS		 623
624 .ecsr_value = ECSR_ICD | ECSR_MPD,
625 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
626 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
627
628 .tx_check = EESR_TC1 | EESR_FTC,
629 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \
630 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \
631 EESR_ECI,
632 .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \
633 EESR_TFE,
634
635 .apr = 1,
636 .mpr = 1,
637 .tpauser = 1,
638 .bculr = 1,
639 .hw_swap = 1,
380af9e3
YS		 640 .no_trimd = 1,
641 .no_ade = 1,
4986b996 642 .tsu = 1,
5b3dfd13 643 .irq_flags = IRQF_SHARED,
380af9e3
YS		 644};
645
e5c9b4cd 646static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
73a0d907
YS		 647{
648 struct sh_eth_private *mdp = netdev_priv(ndev);
73a0d907
YS		 649
650 /* reset device */
651 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
652 mdelay(1);
653
5e7a76be 654 sh_eth_select_mii(ndev);
73a0d907
YS		 655}
656
73a0d907 657/* R8A7740 */
e5c9b4cd
SS		 658static struct sh_eth_cpu_data r8a7740_data = {
659 .chip_reset = sh_eth_chip_reset_r8a7740,
73a0d907 660 .set_duplex = sh_eth_set_duplex,
e5c9b4cd 661 .set_rate = sh_eth_set_rate_gether,
73a0d907
YS		 662
663 .ecsr_value = ECSR_ICD | ECSR_MPD,
664 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
665 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
666
667 .tx_check = EESR_TC1 | EESR_FTC,
668 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \
669 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \
670 EESR_ECI,
671 .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \
672 EESR_TFE,
673
674 .apr = 1,
675 .mpr = 1,
676 .tpauser = 1,
677 .bculr = 1,
678 .hw_swap = 1,
679 .no_trimd = 1,
680 .no_ade = 1,
681 .tsu = 1,
5e7a76be 682 .select_mii = 1,
73a0d907
YS		 683};
684
c18a79ab 685static struct sh_eth_cpu_data sh7619_data = {
380af9e3
YS		 686 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
687
688 .apr = 1,
689 .mpr = 1,
690 .tpauser = 1,
691 .hw_swap = 1,
692};
7bbe150d
SS		 693
694static struct sh_eth_cpu_data sh771x_data = {
380af9e3 695 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
4986b996 696 .tsu = 1,
380af9e3 697};
380af9e3
YS		 698
699static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
700{
701 if (!cd->ecsr_value)
702 cd->ecsr_value = DEFAULT_ECSR_INIT;
703
704 if (!cd->ecsipr_value)
705 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
706
707 if (!cd->fcftr_value)
708 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF | \
709 DEFAULT_FIFO_F_D_RFD;
710
711 if (!cd->fdr_value)
712 cd->fdr_value = DEFAULT_FDR_INIT;
713
714 if (!cd->rmcr_value)
715 cd->rmcr_value = DEFAULT_RMCR_VALUE;
716
717 if (!cd->tx_check)
718 cd->tx_check = DEFAULT_TX_CHECK;
719
720 if (!cd->eesr_err_check)
721 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
722
723 if (!cd->tx_error_check)
724 cd->tx_error_check = DEFAULT_TX_ERROR_CHECK;
725}
726
5cee1d37
NI		 727static int sh_eth_check_reset(struct net_device *ndev)
728{
729 int ret = 0;
730 int cnt = 100;
731
732 while (cnt > 0) {
733 if (!(sh_eth_read(ndev, EDMR) & 0x3))
734 break;
735 mdelay(1);
736 cnt--;
737 }
738 if (cnt < 0) {
14c3326a 739 pr_err("Device reset fail\n");
5cee1d37
NI		 740 ret = -ETIMEDOUT;
741 }
742 return ret;
380af9e3 743}
dabdde9e
NI		 744
745static int sh_eth_reset(struct net_device *ndev)
746{
747 struct sh_eth_private *mdp = netdev_priv(ndev);
748 int ret = 0;
749
750 if (sh_eth_is_gether(mdp)) {
751 sh_eth_write(ndev, EDSR_ENALL, EDSR);
752 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER,
753 EDMR);
754
755 ret = sh_eth_check_reset(ndev);
756 if (ret)
757 goto out;
758
759 /* Table Init */
760 sh_eth_write(ndev, 0x0, TDLAR);
761 sh_eth_write(ndev, 0x0, TDFAR);
762 sh_eth_write(ndev, 0x0, TDFXR);
763 sh_eth_write(ndev, 0x0, TDFFR);
764 sh_eth_write(ndev, 0x0, RDLAR);
765 sh_eth_write(ndev, 0x0, RDFAR);
766 sh_eth_write(ndev, 0x0, RDFXR);
767 sh_eth_write(ndev, 0x0, RDFFR);
768
769 /* Reset HW CRC register */
770 if (mdp->cd->hw_crc)
771 sh_eth_write(ndev, 0x0, CSMR);
772
773 /* Select MII mode */
774 if (mdp->cd->select_mii)
775 sh_eth_select_mii(ndev);
776 } else {
777 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER,
778 EDMR);
779 mdelay(3);
780 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER,
781 EDMR);
782 }
783
784out:
785 return ret;
786}
380af9e3 787
73a0d907 788#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
380af9e3
YS		 789static void sh_eth_set_receive_align(struct sk_buff *skb)
790{
791 int reserve;
792
793 reserve = SH4_SKB_RX_ALIGN - ((u32)skb->data & (SH4_SKB_RX_ALIGN - 1));
794 if (reserve)
795 skb_reserve(skb, reserve);
796}
797#else
798static void sh_eth_set_receive_align(struct sk_buff *skb)
799{
800 skb_reserve(skb, SH2_SH3_SKB_RX_ALIGN);
801}
802#endif
803
804
71557a37
YS		 805/* CPU <-> EDMAC endian convert */
806static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x)
807{
808 switch (mdp->edmac_endian) {
809 case EDMAC_LITTLE_ENDIAN:
810 return cpu_to_le32(x);
811 case EDMAC_BIG_ENDIAN:
812 return cpu_to_be32(x);
813 }
814 return x;
815}
816
817static inline __u32 edmac_to_cpu(struct sh_eth_private *mdp, u32 x)
818{
819 switch (mdp->edmac_endian) {
820 case EDMAC_LITTLE_ENDIAN:
821 return le32_to_cpu(x);
822 case EDMAC_BIG_ENDIAN:
823 return be32_to_cpu(x);
824 }
825 return x;
826}
827
86a74ff2
NI		 828/*
829 * Program the hardware MAC address from dev->dev_addr.
830 */
831static void update_mac_address(struct net_device *ndev)
832{
4a55530f
YS		 833 sh_eth_write(ndev,
834 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
835 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
836 sh_eth_write(ndev,
837 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
86a74ff2
NI		 838}
839
840/*
841 * Get MAC address from SuperH MAC address register
842 *
843 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
844 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
845 * When you want use this device, you must set MAC address in bootloader.
846 *
847 */
748031f9 848static void read_mac_address(struct net_device *ndev, unsigned char *mac)
86a74ff2 849{
748031f9
MD		 850 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
851 memcpy(ndev->dev_addr, mac, 6);
852 } else {
4a55530f
YS		 853 ndev->dev_addr[0] = (sh_eth_read(ndev, MAHR) >> 24);
854 ndev->dev_addr[1] = (sh_eth_read(ndev, MAHR) >> 16) & 0xFF;
855 ndev->dev_addr[2] = (sh_eth_read(ndev, MAHR) >> 8) & 0xFF;
856 ndev->dev_addr[3] = (sh_eth_read(ndev, MAHR) & 0xFF);
857 ndev->dev_addr[4] = (sh_eth_read(ndev, MALR) >> 8) & 0xFF;
858 ndev->dev_addr[5] = (sh_eth_read(ndev, MALR) & 0xFF);
748031f9 859 }
86a74ff2
NI		 860}
861
c5ed5368
YS		 862static unsigned long sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
863{
864 if (sh_eth_is_gether(mdp))
865 return EDTRR_TRNS_GETHER;
866 else
867 return EDTRR_TRNS_ETHER;
868}
869
86a74ff2 870struct bb_info {
ae70644d 871 void (*set_gate)(void *addr);
86a74ff2 872 struct mdiobb_ctrl ctrl;
ae70644d 873 void *addr;
86a74ff2
NI		 874 u32 mmd_msk;/* MMD */
875 u32 mdo_msk;
876 u32 mdi_msk;
877 u32 mdc_msk;
878};
879
880/* PHY bit set */
ae70644d 881static void bb_set(void *addr, u32 msk)
86a74ff2 882{
ae70644d 883 iowrite32(ioread32(addr) | msk, addr);
86a74ff2
NI		 884}
885
886/* PHY bit clear */
ae70644d 887static void bb_clr(void *addr, u32 msk)
86a74ff2 888{
ae70644d 889 iowrite32((ioread32(addr) & ~msk), addr);
86a74ff2
NI		 890}
891
892/* PHY bit read */
ae70644d 893static int bb_read(void *addr, u32 msk)
86a74ff2 894{
ae70644d 895 return (ioread32(addr) & msk) != 0;
86a74ff2
NI		 896}
897
898/* Data I/O pin control */
899static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
900{
901 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
b3017e6a
YS		 902
903 if (bitbang->set_gate)
904 bitbang->set_gate(bitbang->addr);
905
86a74ff2
NI		 906 if (bit)
907 bb_set(bitbang->addr, bitbang->mmd_msk);
908 else
909 bb_clr(bitbang->addr, bitbang->mmd_msk);
910}
911
912/* Set bit data*/
913static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
914{
915 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
916
b3017e6a
YS		 917 if (bitbang->set_gate)
918 bitbang->set_gate(bitbang->addr);
919
86a74ff2
NI		 920 if (bit)
921 bb_set(bitbang->addr, bitbang->mdo_msk);
922 else
923 bb_clr(bitbang->addr, bitbang->mdo_msk);
924}
925
926/* Get bit data*/
927static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
928{
929 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
b3017e6a
YS		 930
931 if (bitbang->set_gate)
932 bitbang->set_gate(bitbang->addr);
933
86a74ff2
NI		 934 return bb_read(bitbang->addr, bitbang->mdi_msk);
935}
936
937/* MDC pin control */
938static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
939{
940 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
941
b3017e6a
YS		 942 if (bitbang->set_gate)
943 bitbang->set_gate(bitbang->addr);
944
86a74ff2
NI		 945 if (bit)
946 bb_set(bitbang->addr, bitbang->mdc_msk);
947 else
948 bb_clr(bitbang->addr, bitbang->mdc_msk);
949}
950
951/* mdio bus control struct */
952static struct mdiobb_ops bb_ops = {
953 .owner = THIS_MODULE,
954 .set_mdc = sh_mdc_ctrl,
955 .set_mdio_dir = sh_mmd_ctrl,
956 .set_mdio_data = sh_set_mdio,
957 .get_mdio_data = sh_get_mdio,
958};
959
86a74ff2
NI		 960/* free skb and descriptor buffer */
961static void sh_eth_ring_free(struct net_device *ndev)
962{
963 struct sh_eth_private *mdp = netdev_priv(ndev);
964 int i;
965
966 /* Free Rx skb ringbuffer */
967 if (mdp->rx_skbuff) {
525b8075 968 for (i = 0; i < mdp->num_rx_ring; i++) {
86a74ff2
NI		 969 if (mdp->rx_skbuff[i])
970 dev_kfree_skb(mdp->rx_skbuff[i]);
971 }
972 }
973 kfree(mdp->rx_skbuff);
91c77550 974 mdp->rx_skbuff = NULL;
86a74ff2
NI		 975
976 /* Free Tx skb ringbuffer */
977 if (mdp->tx_skbuff) {
525b8075 978 for (i = 0; i < mdp->num_tx_ring; i++) {
86a74ff2
NI		 979 if (mdp->tx_skbuff[i])
980 dev_kfree_skb(mdp->tx_skbuff[i]);
981 }
982 }
983 kfree(mdp->tx_skbuff);
91c77550 984 mdp->tx_skbuff = NULL;
86a74ff2
NI		 985}
986
987/* format skb and descriptor buffer */
988static void sh_eth_ring_format(struct net_device *ndev)
989{
990 struct sh_eth_private *mdp = netdev_priv(ndev);
991 int i;
992 struct sk_buff *skb;
993 struct sh_eth_rxdesc *rxdesc = NULL;
994 struct sh_eth_txdesc *txdesc = NULL;
525b8075
YS		 995 int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
996 int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
86a74ff2
NI		 997
998 mdp->cur_rx = mdp->cur_tx = 0;
999 mdp->dirty_rx = mdp->dirty_tx = 0;
1000
1001 memset(mdp->rx_ring, 0, rx_ringsize);
1002
1003 /* build Rx ring buffer */
525b8075 1004 for (i = 0; i < mdp->num_rx_ring; i++) {
86a74ff2
NI		 1005 /* skb */
1006 mdp->rx_skbuff[i] = NULL;
dae2e9f4 1007 skb = netdev_alloc_skb(ndev, mdp->rx_buf_sz);
86a74ff2
NI		 1008 mdp->rx_skbuff[i] = skb;
1009 if (skb == NULL)
1010 break;
bb7d92e3 1011 dma_map_single(&ndev->dev, skb->data, mdp->rx_buf_sz,
e88aae7b 1012 DMA_FROM_DEVICE);
380af9e3
YS		 1013 sh_eth_set_receive_align(skb);
1014
86a74ff2
NI		 1015 /* RX descriptor */
1016 rxdesc = &mdp->rx_ring[i];
0029d64a 1017 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
71557a37 1018 rxdesc->status = cpu_to_edmac(mdp, RD_RACT | RD_RFP);
86a74ff2
NI		 1019
1020 /* The size of the buffer is 16 byte boundary. */
0029d64a 1021 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
b0ca2a21
NI		 1022 /* Rx descriptor address set */
1023 if (i == 0) {
4a55530f 1024 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
c5ed5368
YS		 1025 if (sh_eth_is_gether(mdp))
1026 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
b0ca2a21 1027 }
86a74ff2
NI		 1028 }
1029
525b8075 1030 mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
86a74ff2
NI		 1031
1032 /* Mark the last entry as wrapping the ring. */
71557a37 1033 rxdesc->status |= cpu_to_edmac(mdp, RD_RDEL);
86a74ff2
NI		 1034
1035 memset(mdp->tx_ring, 0, tx_ringsize);
1036
1037 /* build Tx ring buffer */
525b8075 1038 for (i = 0; i < mdp->num_tx_ring; i++) {
86a74ff2
NI		 1039 mdp->tx_skbuff[i] = NULL;
1040 txdesc = &mdp->tx_ring[i];
71557a37 1041 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
86a74ff2 1042 txdesc->buffer_length = 0;
b0ca2a21 1043 if (i == 0) {
71557a37 1044 /* Tx descriptor address set */
4a55530f 1045 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
c5ed5368
YS		 1046 if (sh_eth_is_gether(mdp))
1047 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
b0ca2a21 1048 }
86a74ff2
NI		 1049 }
1050
71557a37 1051 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
86a74ff2
NI		 1052}
1053
1054/* Get skb and descriptor buffer */
1055static int sh_eth_ring_init(struct net_device *ndev)
1056{
1057 struct sh_eth_private *mdp = netdev_priv(ndev);
1058 int rx_ringsize, tx_ringsize, ret = 0;
1059
1060 /*
1061 * +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
1062 * card needs room to do 8 byte alignment, +2 so we can reserve
1063 * the first 2 bytes, and +16 gets room for the status word from the
1064 * card.
1065 */
1066 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
1067 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
503914cf
MD		 1068 if (mdp->cd->rpadir)
1069 mdp->rx_buf_sz += NET_IP_ALIGN;
86a74ff2
NI		 1070
1071 /* Allocate RX and TX skb rings */
b2adaca9
JP		 1072 mdp->rx_skbuff = kmalloc_array(mdp->num_rx_ring,
1073 sizeof(*mdp->rx_skbuff), GFP_KERNEL);
86a74ff2 1074 if (!mdp->rx_skbuff) {
86a74ff2
NI		 1075 ret = -ENOMEM;
1076 return ret;
1077 }
1078
b2adaca9
JP		 1079 mdp->tx_skbuff = kmalloc_array(mdp->num_tx_ring,
1080 sizeof(*mdp->tx_skbuff), GFP_KERNEL);
86a74ff2 1081 if (!mdp->tx_skbuff) {
86a74ff2
NI		 1082 ret = -ENOMEM;
1083 goto skb_ring_free;
1084 }
1085
1086 /* Allocate all Rx descriptors. */
525b8075 1087 rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
86a74ff2 1088 mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
d0320f75 1089 GFP_KERNEL);
86a74ff2 1090 if (!mdp->rx_ring) {
86a74ff2
NI		 1091 ret = -ENOMEM;
1092 goto desc_ring_free;
1093 }
1094
1095 mdp->dirty_rx = 0;
1096
1097 /* Allocate all Tx descriptors. */
525b8075 1098 tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
86a74ff2 1099 mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
d0320f75 1100 GFP_KERNEL);
86a74ff2 1101 if (!mdp->tx_ring) {
86a74ff2
NI		 1102 ret = -ENOMEM;
1103 goto desc_ring_free;
1104 }
1105 return ret;
1106
1107desc_ring_free:
1108 /* free DMA buffer */
1109 dma_free_coherent(NULL, rx_ringsize, mdp->rx_ring, mdp->rx_desc_dma);
1110
1111skb_ring_free:
1112 /* Free Rx and Tx skb ring buffer */
1113 sh_eth_ring_free(ndev);
91c77550
YS		 1114 mdp->tx_ring = NULL;
1115 mdp->rx_ring = NULL;
86a74ff2
NI		 1116
1117 return ret;
1118}
1119
91c77550
YS		 1120static void sh_eth_free_dma_buffer(struct sh_eth_private *mdp)
1121{
1122 int ringsize;
1123
1124 if (mdp->rx_ring) {
525b8075 1125 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
91c77550
YS		 1126 dma_free_coherent(NULL, ringsize, mdp->rx_ring,
1127 mdp->rx_desc_dma);
1128 mdp->rx_ring = NULL;
1129 }
1130
1131 if (mdp->tx_ring) {
525b8075 1132 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
91c77550
YS		 1133 dma_free_coherent(NULL, ringsize, mdp->tx_ring,
1134 mdp->tx_desc_dma);
1135 mdp->tx_ring = NULL;
1136 }
1137}
1138
525b8075 1139static int sh_eth_dev_init(struct net_device *ndev, bool start)
86a74ff2
NI		 1140{
1141 int ret = 0;
1142 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 1143 u32 val;
1144
1145 /* Soft Reset */
5cee1d37
NI		 1146 ret = sh_eth_reset(ndev);
1147 if (ret)
1148 goto out;
86a74ff2 1149
b0ca2a21
NI		 1150 /* Descriptor format */
1151 sh_eth_ring_format(ndev);
380af9e3 1152 if (mdp->cd->rpadir)
4a55530f 1153 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
86a74ff2
NI		 1154
1155 /* all sh_eth int mask */
4a55530f 1156 sh_eth_write(ndev, 0, EESIPR);
86a74ff2 1157
10b9194f 1158#if defined(__LITTLE_ENDIAN)
380af9e3 1159 if (mdp->cd->hw_swap)
4a55530f 1160 sh_eth_write(ndev, EDMR_EL, EDMR);
380af9e3 1161 else
b0ca2a21 1162#endif
4a55530f 1163 sh_eth_write(ndev, 0, EDMR);
86a74ff2 1164
b0ca2a21 1165 /* FIFO size set */
4a55530f
YS		 1166 sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
1167 sh_eth_write(ndev, 0, TFTR);
86a74ff2 1168
b0ca2a21 1169 /* Frame recv control */
4a55530f 1170 sh_eth_write(ndev, mdp->cd->rmcr_value, RMCR);
86a74ff2 1171
2ecbb783 1172 sh_eth_write(ndev, DESC_I_RINT8 | DESC_I_RINT5 | DESC_I_TINT2, TRSCER);
86a74ff2 1173
380af9e3 1174 if (mdp->cd->bculr)
4a55530f 1175 sh_eth_write(ndev, 0x800, BCULR); /* Burst sycle set */
b0ca2a21 1176
4a55530f 1177 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
86a74ff2 1178
380af9e3 1179 if (!mdp->cd->no_trimd)
4a55530f 1180 sh_eth_write(ndev, 0, TRIMD);
86a74ff2 1181
b0ca2a21 1182 /* Recv frame limit set register */
fdb37a7f
YS		 1183 sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1184 RFLR);
86a74ff2 1185
4a55530f 1186 sh_eth_write(ndev, sh_eth_read(ndev, EESR), EESR);
525b8075
YS		 1187 if (start)
1188 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
86a74ff2
NI		 1189
1190 /* PAUSE Prohibition */
4a55530f 1191 val = (sh_eth_read(ndev, ECMR) & ECMR_DM) |
86a74ff2
NI		 1192 ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE;
1193
4a55530f 1194 sh_eth_write(ndev, val, ECMR);
b0ca2a21 1195
380af9e3
YS		 1196 if (mdp->cd->set_rate)
1197 mdp->cd->set_rate(ndev);
1198
b0ca2a21 1199 /* E-MAC Status Register clear */
4a55530f 1200 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
b0ca2a21
NI		 1201
1202 /* E-MAC Interrupt Enable register */
525b8075
YS		 1203 if (start)
1204 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
86a74ff2
NI		 1205
1206 /* Set MAC address */
1207 update_mac_address(ndev);
1208
1209 /* mask reset */
380af9e3 1210 if (mdp->cd->apr)
4a55530f 1211 sh_eth_write(ndev, APR_AP, APR);
380af9e3 1212 if (mdp->cd->mpr)
4a55530f 1213 sh_eth_write(ndev, MPR_MP, MPR);
380af9e3 1214 if (mdp->cd->tpauser)
4a55530f 1215 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
b0ca2a21 1216
525b8075
YS		 1217 if (start) {
1218 /* Setting the Rx mode will start the Rx process. */
1219 sh_eth_write(ndev, EDRRR_R, EDRRR);
86a74ff2 1220
525b8075
YS		 1221 netif_start_queue(ndev);
1222 }
86a74ff2 1223
5cee1d37 1224out:
86a74ff2
NI		 1225 return ret;
1226}
1227
1228/* free Tx skb function */
1229static int sh_eth_txfree(struct net_device *ndev)
1230{
1231 struct sh_eth_private *mdp = netdev_priv(ndev);
1232 struct sh_eth_txdesc *txdesc;
1233 int freeNum = 0;
1234 int entry = 0;
1235
1236 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
525b8075 1237 entry = mdp->dirty_tx % mdp->num_tx_ring;
86a74ff2 1238 txdesc = &mdp->tx_ring[entry];
71557a37 1239 if (txdesc->status & cpu_to_edmac(mdp, TD_TACT))
86a74ff2
NI		 1240 break;
1241 /* Free the original skb. */
1242 if (mdp->tx_skbuff[entry]) {
31fcb99d
YS		 1243 dma_unmap_single(&ndev->dev, txdesc->addr,
1244 txdesc->buffer_length, DMA_TO_DEVICE);
86a74ff2
NI		 1245 dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1246 mdp->tx_skbuff[entry] = NULL;
1247 freeNum++;
1248 }
71557a37 1249 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
525b8075 1250 if (entry >= mdp->num_tx_ring - 1)
71557a37 1251 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
86a74ff2 1252
bb7d92e3
ED		 1253 ndev->stats.tx_packets++;
1254 ndev->stats.tx_bytes += txdesc->buffer_length;
86a74ff2
NI		 1255 }
1256 return freeNum;
1257}
1258
1259/* Packet receive function */
a18e08bd 1260static int sh_eth_rx(struct net_device *ndev, u32 intr_status)
86a74ff2
NI		 1261{
1262 struct sh_eth_private *mdp = netdev_priv(ndev);
1263 struct sh_eth_rxdesc *rxdesc;
1264
525b8075
YS		 1265 int entry = mdp->cur_rx % mdp->num_rx_ring;
1266 int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
86a74ff2
NI		 1267 struct sk_buff *skb;
1268 u16 pkt_len = 0;
380af9e3 1269 u32 desc_status;
86a74ff2
NI		 1270
1271 rxdesc = &mdp->rx_ring[entry];
71557a37
YS		 1272 while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) {
1273 desc_status = edmac_to_cpu(mdp, rxdesc->status);
86a74ff2
NI		 1274 pkt_len = rxdesc->frame_length;
1275
73a0d907
YS		 1276#if defined(CONFIG_ARCH_R8A7740)
1277 desc_status >>= 16;
1278#endif
1279
86a74ff2
NI		 1280 if (--boguscnt < 0)
1281 break;
1282
1283 if (!(desc_status & RDFEND))
bb7d92e3 1284 ndev->stats.rx_length_errors++;
86a74ff2
NI		 1285
1286 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1287 RD_RFS5 | RD_RFS6 | RD_RFS10)) {
bb7d92e3 1288 ndev->stats.rx_errors++;
86a74ff2 1289 if (desc_status & RD_RFS1)
bb7d92e3 1290 ndev->stats.rx_crc_errors++;
86a74ff2 1291 if (desc_status & RD_RFS2)
bb7d92e3 1292 ndev->stats.rx_frame_errors++;
86a74ff2 1293 if (desc_status & RD_RFS3)
bb7d92e3 1294 ndev->stats.rx_length_errors++;
86a74ff2 1295 if (desc_status & RD_RFS4)
bb7d92e3 1296 ndev->stats.rx_length_errors++;
86a74ff2 1297 if (desc_status & RD_RFS6)
bb7d92e3 1298 ndev->stats.rx_missed_errors++;
86a74ff2 1299 if (desc_status & RD_RFS10)
bb7d92e3 1300 ndev->stats.rx_over_errors++;
86a74ff2 1301 } else {
380af9e3
YS		 1302 if (!mdp->cd->hw_swap)
1303 sh_eth_soft_swap(
1304 phys_to_virt(ALIGN(rxdesc->addr, 4)),
1305 pkt_len + 2);
86a74ff2
NI		 1306 skb = mdp->rx_skbuff[entry];
1307 mdp->rx_skbuff[entry] = NULL;
503914cf
MD		 1308 if (mdp->cd->rpadir)
1309 skb_reserve(skb, NET_IP_ALIGN);
86a74ff2
NI		 1310 skb_put(skb, pkt_len);
1311 skb->protocol = eth_type_trans(skb, ndev);
1312 netif_rx(skb);
bb7d92e3
ED		 1313 ndev->stats.rx_packets++;
1314 ndev->stats.rx_bytes += pkt_len;
86a74ff2 1315 }
71557a37 1316 rxdesc->status |= cpu_to_edmac(mdp, RD_RACT);
525b8075 1317 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
862df497 1318 rxdesc = &mdp->rx_ring[entry];
86a74ff2
NI		 1319 }
1320
1321 /* Refill the Rx ring buffers. */
1322 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
525b8075 1323 entry = mdp->dirty_rx % mdp->num_rx_ring;
86a74ff2 1324 rxdesc = &mdp->rx_ring[entry];
b0ca2a21 1325 /* The size of the buffer is 16 byte boundary. */
0029d64a 1326 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
b0ca2a21 1327
86a74ff2 1328 if (mdp->rx_skbuff[entry] == NULL) {
dae2e9f4 1329 skb = netdev_alloc_skb(ndev, mdp->rx_buf_sz);
86a74ff2
NI		 1330 mdp->rx_skbuff[entry] = skb;
1331 if (skb == NULL)
1332 break; /* Better luck next round. */
bb7d92e3 1333 dma_map_single(&ndev->dev, skb->data, mdp->rx_buf_sz,
e88aae7b 1334 DMA_FROM_DEVICE);
380af9e3
YS		 1335 sh_eth_set_receive_align(skb);
1336
bc8acf2c 1337 skb_checksum_none_assert(skb);
0029d64a 1338 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
86a74ff2 1339 }
525b8075 1340 if (entry >= mdp->num_rx_ring - 1)
86a74ff2 1341 rxdesc->status |=
71557a37 1342 cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDEL);
86a74ff2
NI		 1343 else
1344 rxdesc->status |=
71557a37 1345 cpu_to_edmac(mdp, RD_RACT | RD_RFP);
86a74ff2
NI		 1346 }
1347
1348 /* Restart Rx engine if stopped. */
1349 /* If we don't need to check status, don't. -KDU */
79fba9f5 1350 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
a18e08bd
YS		 1351 /* fix the values for the next receiving if RDE is set */
1352 if (intr_status & EESR_RDE)
1353 mdp->cur_rx = mdp->dirty_rx =
1354 (sh_eth_read(ndev, RDFAR) -
1355 sh_eth_read(ndev, RDLAR)) >> 4;
4a55530f 1356 sh_eth_write(ndev, EDRRR_R, EDRRR);
79fba9f5 1357 }
86a74ff2
NI		 1358
1359 return 0;
1360}
1361
4a55530f 1362static void sh_eth_rcv_snd_disable(struct net_device *ndev)
dc19e4e5
NI		 1363{
1364 /* disable tx and rx */
4a55530f
YS		 1365 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) &
1366 ~(ECMR_RE | ECMR_TE), ECMR);
dc19e4e5
NI		 1367}
1368
4a55530f 1369static void sh_eth_rcv_snd_enable(struct net_device *ndev)
dc19e4e5
NI		 1370{
1371 /* enable tx and rx */
4a55530f
YS		 1372 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) |
1373 (ECMR_RE | ECMR_TE), ECMR);
dc19e4e5
NI		 1374}
1375
86a74ff2
NI		 1376/* error control function */
1377static void sh_eth_error(struct net_device *ndev, int intr_status)
1378{
1379 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2 1380 u32 felic_stat;
380af9e3
YS		 1381 u32 link_stat;
1382 u32 mask;
86a74ff2
NI		 1383
1384 if (intr_status & EESR_ECI) {
4a55530f
YS		 1385 felic_stat = sh_eth_read(ndev, ECSR);
1386 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */
86a74ff2 1387 if (felic_stat & ECSR_ICD)
bb7d92e3 1388 ndev->stats.tx_carrier_errors++;
86a74ff2
NI		 1389 if (felic_stat & ECSR_LCHNG) {
1390 /* Link Changed */
4923576b 1391 if (mdp->cd->no_psr || mdp->no_ether_link) {
1e1b812b 1392 goto ignore_link;
380af9e3 1393 } else {
4a55530f 1394 link_stat = (sh_eth_read(ndev, PSR));
4923576b
YS		 1395 if (mdp->ether_link_active_low)
1396 link_stat = ~link_stat;
380af9e3 1397 }
dc19e4e5 1398 if (!(link_stat & PHY_ST_LINK))
4a55530f 1399 sh_eth_rcv_snd_disable(ndev);
dc19e4e5 1400 else {
86a74ff2 1401 /* Link Up */
4a55530f
YS		 1402 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) &
1403 ~DMAC_M_ECI, EESIPR);
86a74ff2 1404 /*clear int */
4a55530f
YS		 1405 sh_eth_write(ndev, sh_eth_read(ndev, ECSR),
1406 ECSR);
1407 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) |
1408 DMAC_M_ECI, EESIPR);
86a74ff2 1409 /* enable tx and rx */
4a55530f 1410 sh_eth_rcv_snd_enable(ndev);
86a74ff2
NI		 1411 }
1412 }
1413 }
1414
1e1b812b 1415ignore_link:
86a74ff2
NI		 1416 if (intr_status & EESR_TWB) {
1417 /* Write buck end. unused write back interrupt */
1418 if (intr_status & EESR_TABT) /* Transmit Abort int */
bb7d92e3 1419 ndev->stats.tx_aborted_errors++;
dc19e4e5
NI		 1420 if (netif_msg_tx_err(mdp))
1421 dev_err(&ndev->dev, "Transmit Abort\n");
86a74ff2
NI		 1422 }
1423
1424 if (intr_status & EESR_RABT) {
1425 /* Receive Abort int */
1426 if (intr_status & EESR_RFRMER) {
1427 /* Receive Frame Overflow int */
bb7d92e3 1428 ndev->stats.rx_frame_errors++;
dc19e4e5
NI		 1429 if (netif_msg_rx_err(mdp))
1430 dev_err(&ndev->dev, "Receive Abort\n");
86a74ff2
NI		 1431 }
1432 }
380af9e3 1433
dc19e4e5
NI		 1434 if (intr_status & EESR_TDE) {
1435 /* Transmit Descriptor Empty int */
bb7d92e3 1436 ndev->stats.tx_fifo_errors++;
dc19e4e5
NI		 1437 if (netif_msg_tx_err(mdp))
1438 dev_err(&ndev->dev, "Transmit Descriptor Empty\n");
1439 }
1440
1441 if (intr_status & EESR_TFE) {
1442 /* FIFO under flow */
bb7d92e3 1443 ndev->stats.tx_fifo_errors++;
dc19e4e5
NI		 1444 if (netif_msg_tx_err(mdp))
1445 dev_err(&ndev->dev, "Transmit FIFO Under flow\n");
86a74ff2
NI		 1446 }
1447
1448 if (intr_status & EESR_RDE) {
1449 /* Receive Descriptor Empty int */
bb7d92e3 1450 ndev->stats.rx_over_errors++;
86a74ff2 1451
dc19e4e5
NI		 1452 if (netif_msg_rx_err(mdp))
1453 dev_err(&ndev->dev, "Receive Descriptor Empty\n");
86a74ff2 1454 }
dc19e4e5 1455
86a74ff2
NI		 1456 if (intr_status & EESR_RFE) {
1457 /* Receive FIFO Overflow int */
bb7d92e3 1458 ndev->stats.rx_fifo_errors++;
dc19e4e5
NI		 1459 if (netif_msg_rx_err(mdp))
1460 dev_err(&ndev->dev, "Receive FIFO Overflow\n");
1461 }
1462
1463 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1464 /* Address Error */
bb7d92e3 1465 ndev->stats.tx_fifo_errors++;
dc19e4e5
NI		 1466 if (netif_msg_tx_err(mdp))
1467 dev_err(&ndev->dev, "Address Error\n");
86a74ff2 1468 }
380af9e3
YS		 1469
1470 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1471 if (mdp->cd->no_ade)
1472 mask &= ~EESR_ADE;
1473 if (intr_status & mask) {
86a74ff2 1474 /* Tx error */
4a55530f 1475 u32 edtrr = sh_eth_read(ndev, EDTRR);
86a74ff2 1476 /* dmesg */
380af9e3
YS		 1477 dev_err(&ndev->dev, "TX error. status=%8.8x cur_tx=%8.8x ",
1478 intr_status, mdp->cur_tx);
1479 dev_err(&ndev->dev, "dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
86a74ff2
NI		 1480 mdp->dirty_tx, (u32) ndev->state, edtrr);
1481 /* dirty buffer free */
1482 sh_eth_txfree(ndev);
1483
1484 /* SH7712 BUG */
c5ed5368 1485 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
86a74ff2 1486 /* tx dma start */
c5ed5368 1487 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
86a74ff2
NI		 1488 }
1489 /* wakeup */
1490 netif_wake_queue(ndev);
1491 }
1492}
1493
1494static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1495{
1496 struct net_device *ndev = netdev;
1497 struct sh_eth_private *mdp = netdev_priv(ndev);
380af9e3 1498 struct sh_eth_cpu_data *cd = mdp->cd;
0e0fde3c 1499 irqreturn_t ret = IRQ_NONE;
3893b273 1500 unsigned long intr_status;
86a74ff2 1501
86a74ff2
NI		 1502 spin_lock(&mdp->lock);
1503
3893b273 1504 /* Get interrupt status */
4a55530f 1505 intr_status = sh_eth_read(ndev, EESR);
3893b273
SS		 1506 /* Mask it with the interrupt mask, forcing ECI interrupt to be always
1507 * enabled since it's the one that comes thru regardless of the mask,
1508 * and we need to fully handle it in sh_eth_error() in order to quench
1509 * it as it doesn't get cleared by just writing 1 to the ECI bit...
1510 */
1511 intr_status &= sh_eth_read(ndev, EESIPR) | DMAC_M_ECI;
86a74ff2 1512 /* Clear interrupt */
0e0fde3c
NI		 1513 if (intr_status & (EESR_FRC | EESR_RMAF | EESR_RRF |
1514 EESR_RTLF | EESR_RTSF | EESR_PRE | EESR_CERF |
380af9e3 1515 cd->tx_check | cd->eesr_err_check)) {
4a55530f 1516 sh_eth_write(ndev, intr_status, EESR);
0e0fde3c
NI		 1517 ret = IRQ_HANDLED;
1518 } else
1519 goto other_irq;
86a74ff2 1520
b0ca2a21
NI		 1521 if (intr_status & (EESR_FRC | /* Frame recv*/
1522 EESR_RMAF | /* Multi cast address recv*/
1523 EESR_RRF | /* Bit frame recv */
1524 EESR_RTLF | /* Long frame recv*/
1525 EESR_RTSF | /* short frame recv */
1526 EESR_PRE | /* PHY-LSI recv error */
1527 EESR_CERF)){ /* recv frame CRC error */
a18e08bd 1528 sh_eth_rx(ndev, intr_status);
b0ca2a21 1529 }
86a74ff2 1530
b0ca2a21 1531 /* Tx Check */
380af9e3 1532 if (intr_status & cd->tx_check) {
86a74ff2
NI		 1533 sh_eth_txfree(ndev);
1534 netif_wake_queue(ndev);
1535 }
1536
380af9e3 1537 if (intr_status & cd->eesr_err_check)
86a74ff2
NI		 1538 sh_eth_error(ndev, intr_status);
1539
0e0fde3c 1540other_irq:
86a74ff2
NI		 1541 spin_unlock(&mdp->lock);
1542
0e0fde3c 1543 return ret;
86a74ff2
NI		 1544}
1545
86a74ff2
NI		 1546/* PHY state control function */
1547static void sh_eth_adjust_link(struct net_device *ndev)
1548{
1549 struct sh_eth_private *mdp = netdev_priv(ndev);
1550 struct phy_device *phydev = mdp->phydev;
86a74ff2
NI		 1551 int new_state = 0;
1552
3340d2aa 1553 if (phydev->link) {
86a74ff2
NI		 1554 if (phydev->duplex != mdp->duplex) {
1555 new_state = 1;
1556 mdp->duplex = phydev->duplex;
380af9e3
YS		 1557 if (mdp->cd->set_duplex)
1558 mdp->cd->set_duplex(ndev);
86a74ff2
NI		 1559 }
1560
1561 if (phydev->speed != mdp->speed) {
1562 new_state = 1;
1563 mdp->speed = phydev->speed;
380af9e3
YS		 1564 if (mdp->cd->set_rate)
1565 mdp->cd->set_rate(ndev);
86a74ff2 1566 }
3340d2aa 1567 if (!mdp->link) {
91a56152
YS		 1568 sh_eth_write(ndev,
1569 (sh_eth_read(ndev, ECMR) & ~ECMR_TXF), ECMR);
86a74ff2
NI		 1570 new_state = 1;
1571 mdp->link = phydev->link;
1e1b812b
SS		 1572 if (mdp->cd->no_psr || mdp->no_ether_link)
1573 sh_eth_rcv_snd_enable(ndev);
86a74ff2
NI		 1574 }
1575 } else if (mdp->link) {
1576 new_state = 1;
3340d2aa 1577 mdp->link = 0;
86a74ff2
NI		 1578 mdp->speed = 0;
1579 mdp->duplex = -1;
1e1b812b
SS		 1580 if (mdp->cd->no_psr || mdp->no_ether_link)
1581 sh_eth_rcv_snd_disable(ndev);
86a74ff2
NI		 1582 }
1583
dc19e4e5 1584 if (new_state && netif_msg_link(mdp))
86a74ff2
NI		 1585 phy_print_status(phydev);
1586}
1587
1588/* PHY init function */
1589static int sh_eth_phy_init(struct net_device *ndev)
1590{
1591 struct sh_eth_private *mdp = netdev_priv(ndev);
0a372eb9 1592 char phy_id[MII_BUS_ID_SIZE + 3];
86a74ff2
NI		 1593 struct phy_device *phydev = NULL;
1594
fb28ad35 1595 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
86a74ff2
NI		 1596 mdp->mii_bus->id , mdp->phy_id);
1597
3340d2aa 1598 mdp->link = 0;
86a74ff2
NI		 1599 mdp->speed = 0;
1600 mdp->duplex = -1;
1601
1602 /* Try connect to PHY */
c061b18d 1603 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
f9a8f83b 1604 mdp->phy_interface);
86a74ff2
NI		 1605 if (IS_ERR(phydev)) {
1606 dev_err(&ndev->dev, "phy_connect failed\n");
1607 return PTR_ERR(phydev);
1608 }
380af9e3 1609
86a74ff2 1610 dev_info(&ndev->dev, "attached phy %i to driver %s\n",
380af9e3 1611 phydev->addr, phydev->drv->name);
86a74ff2
NI		 1612
1613 mdp->phydev = phydev;
1614
1615 return 0;
1616}
1617
1618/* PHY control start function */
1619static int sh_eth_phy_start(struct net_device *ndev)
1620{
1621 struct sh_eth_private *mdp = netdev_priv(ndev);
1622 int ret;
1623
1624 ret = sh_eth_phy_init(ndev);
1625 if (ret)
1626 return ret;
1627
1628 /* reset phy - this also wakes it from PDOWN */
1629 phy_write(mdp->phydev, MII_BMCR, BMCR_RESET);
1630 phy_start(mdp->phydev);
1631
1632 return 0;
1633}
1634
dc19e4e5
NI		 1635static int sh_eth_get_settings(struct net_device *ndev,
1636 struct ethtool_cmd *ecmd)
1637{
1638 struct sh_eth_private *mdp = netdev_priv(ndev);
1639 unsigned long flags;
1640 int ret;
1641
1642 spin_lock_irqsave(&mdp->lock, flags);
1643 ret = phy_ethtool_gset(mdp->phydev, ecmd);
1644 spin_unlock_irqrestore(&mdp->lock, flags);
1645
1646 return ret;
1647}
1648
1649static int sh_eth_set_settings(struct net_device *ndev,
1650 struct ethtool_cmd *ecmd)
1651{
1652 struct sh_eth_private *mdp = netdev_priv(ndev);
1653 unsigned long flags;
1654 int ret;
dc19e4e5
NI		 1655
1656 spin_lock_irqsave(&mdp->lock, flags);
1657
1658 /* disable tx and rx */
4a55530f 1659 sh_eth_rcv_snd_disable(ndev);
dc19e4e5
NI		 1660
1661 ret = phy_ethtool_sset(mdp->phydev, ecmd);
1662 if (ret)
1663 goto error_exit;
1664
1665 if (ecmd->duplex == DUPLEX_FULL)
1666 mdp->duplex = 1;
1667 else
1668 mdp->duplex = 0;
1669
1670 if (mdp->cd->set_duplex)
1671 mdp->cd->set_duplex(ndev);
1672
1673error_exit:
1674 mdelay(1);
1675
1676 /* enable tx and rx */
4a55530f 1677 sh_eth_rcv_snd_enable(ndev);
dc19e4e5
NI		 1678
1679 spin_unlock_irqrestore(&mdp->lock, flags);
1680
1681 return ret;
1682}
1683
1684static int sh_eth_nway_reset(struct net_device *ndev)
1685{
1686 struct sh_eth_private *mdp = netdev_priv(ndev);
1687 unsigned long flags;
1688 int ret;
1689
1690 spin_lock_irqsave(&mdp->lock, flags);
1691 ret = phy_start_aneg(mdp->phydev);
1692 spin_unlock_irqrestore(&mdp->lock, flags);
1693
1694 return ret;
1695}
1696
1697static u32 sh_eth_get_msglevel(struct net_device *ndev)
1698{
1699 struct sh_eth_private *mdp = netdev_priv(ndev);
1700 return mdp->msg_enable;
1701}
1702
1703static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
1704{
1705 struct sh_eth_private *mdp = netdev_priv(ndev);
1706 mdp->msg_enable = value;
1707}
1708
1709static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
1710 "rx_current", "tx_current",
1711 "rx_dirty", "tx_dirty",
1712};
1713#define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats)
1714
1715static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
1716{
1717 switch (sset) {
1718 case ETH_SS_STATS:
1719 return SH_ETH_STATS_LEN;
1720 default:
1721 return -EOPNOTSUPP;
1722 }
1723}
1724
1725static void sh_eth_get_ethtool_stats(struct net_device *ndev,
1726 struct ethtool_stats *stats, u64 *data)
1727{
1728 struct sh_eth_private *mdp = netdev_priv(ndev);
1729 int i = 0;
1730
1731 /* device-specific stats */
1732 data[i++] = mdp->cur_rx;
1733 data[i++] = mdp->cur_tx;
1734 data[i++] = mdp->dirty_rx;
1735 data[i++] = mdp->dirty_tx;
1736}
1737
1738static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1739{
1740 switch (stringset) {
1741 case ETH_SS_STATS:
1742 memcpy(data, *sh_eth_gstrings_stats,
1743 sizeof(sh_eth_gstrings_stats));
1744 break;
1745 }
1746}
1747
525b8075
YS		 1748static void sh_eth_get_ringparam(struct net_device *ndev,
1749 struct ethtool_ringparam *ring)
1750{
1751 struct sh_eth_private *mdp = netdev_priv(ndev);
1752
1753 ring->rx_max_pending = RX_RING_MAX;
1754 ring->tx_max_pending = TX_RING_MAX;
1755 ring->rx_pending = mdp->num_rx_ring;
1756 ring->tx_pending = mdp->num_tx_ring;
1757}
1758
1759static int sh_eth_set_ringparam(struct net_device *ndev,
1760 struct ethtool_ringparam *ring)
1761{
1762 struct sh_eth_private *mdp = netdev_priv(ndev);
1763 int ret;
1764
1765 if (ring->tx_pending > TX_RING_MAX ||
1766 ring->rx_pending > RX_RING_MAX ||
1767 ring->tx_pending < TX_RING_MIN ||
1768 ring->rx_pending < RX_RING_MIN)
1769 return -EINVAL;
1770 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
1771 return -EINVAL;
1772
1773 if (netif_running(ndev)) {
1774 netif_tx_disable(ndev);
1775 /* Disable interrupts by clearing the interrupt mask. */
1776 sh_eth_write(ndev, 0x0000, EESIPR);
1777 /* Stop the chip's Tx and Rx processes. */
1778 sh_eth_write(ndev, 0, EDTRR);
1779 sh_eth_write(ndev, 0, EDRRR);
1780 synchronize_irq(ndev->irq);
1781 }
1782
1783 /* Free all the skbuffs in the Rx queue. */
1784 sh_eth_ring_free(ndev);
1785 /* Free DMA buffer */
1786 sh_eth_free_dma_buffer(mdp);
1787
1788 /* Set new parameters */
1789 mdp->num_rx_ring = ring->rx_pending;
1790 mdp->num_tx_ring = ring->tx_pending;
1791
1792 ret = sh_eth_ring_init(ndev);
1793 if (ret < 0) {
1794 dev_err(&ndev->dev, "%s: sh_eth_ring_init failed.\n", __func__);
1795 return ret;
1796 }
1797 ret = sh_eth_dev_init(ndev, false);
1798 if (ret < 0) {
1799 dev_err(&ndev->dev, "%s: sh_eth_dev_init failed.\n", __func__);
1800 return ret;
1801 }
1802
1803 if (netif_running(ndev)) {
1804 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1805 /* Setting the Rx mode will start the Rx process. */
1806 sh_eth_write(ndev, EDRRR_R, EDRRR);
1807 netif_wake_queue(ndev);
1808 }
1809
1810 return 0;
1811}
1812
9b07be4b 1813static const struct ethtool_ops sh_eth_ethtool_ops = {
dc19e4e5
NI		 1814 .get_settings = sh_eth_get_settings,
1815 .set_settings = sh_eth_set_settings,
9b07be4b 1816 .nway_reset = sh_eth_nway_reset,
dc19e4e5
NI		 1817 .get_msglevel = sh_eth_get_msglevel,
1818 .set_msglevel = sh_eth_set_msglevel,
9b07be4b 1819 .get_link = ethtool_op_get_link,
dc19e4e5
NI		 1820 .get_strings = sh_eth_get_strings,
1821 .get_ethtool_stats = sh_eth_get_ethtool_stats,
1822 .get_sset_count = sh_eth_get_sset_count,
525b8075
YS		 1823 .get_ringparam = sh_eth_get_ringparam,
1824 .set_ringparam = sh_eth_set_ringparam,
dc19e4e5
NI		 1825};
1826
86a74ff2
NI		 1827/* network device open function */
1828static int sh_eth_open(struct net_device *ndev)
1829{
1830 int ret = 0;
1831 struct sh_eth_private *mdp = netdev_priv(ndev);
1832
bcd5149d
MD		 1833 pm_runtime_get_sync(&mdp->pdev->dev);
1834
a0607fd3 1835 ret = request_irq(ndev->irq, sh_eth_interrupt,
5b3dfd13 1836 mdp->cd->irq_flags, ndev->name, ndev);
86a74ff2 1837 if (ret) {
380af9e3 1838 dev_err(&ndev->dev, "Can not assign IRQ number\n");
86a74ff2
NI		 1839 return ret;
1840 }
1841
1842 /* Descriptor set */
1843 ret = sh_eth_ring_init(ndev);
1844 if (ret)
1845 goto out_free_irq;
1846
1847 /* device init */
525b8075 1848 ret = sh_eth_dev_init(ndev, true);
86a74ff2
NI		 1849 if (ret)
1850 goto out_free_irq;
1851
1852 /* PHY control start*/
1853 ret = sh_eth_phy_start(ndev);
1854 if (ret)
1855 goto out_free_irq;
1856
86a74ff2
NI		 1857 return ret;
1858
1859out_free_irq:
1860 free_irq(ndev->irq, ndev);
bcd5149d 1861 pm_runtime_put_sync(&mdp->pdev->dev);
86a74ff2
NI		 1862 return ret;
1863}
1864
1865/* Timeout function */
1866static void sh_eth_tx_timeout(struct net_device *ndev)
1867{
1868 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 1869 struct sh_eth_rxdesc *rxdesc;
1870 int i;
1871
1872 netif_stop_queue(ndev);
1873
dc19e4e5
NI		 1874 if (netif_msg_timer(mdp))
1875 dev_err(&ndev->dev, "%s: transmit timed out, status %8.8x,"
4a55530f 1876 " resetting...\n", ndev->name, (int)sh_eth_read(ndev, EESR));
86a74ff2
NI		 1877
1878 /* tx_errors count up */
bb7d92e3 1879 ndev->stats.tx_errors++;
86a74ff2 1880
86a74ff2 1881 /* Free all the skbuffs in the Rx queue. */
525b8075 1882 for (i = 0; i < mdp->num_rx_ring; i++) {
86a74ff2
NI		 1883 rxdesc = &mdp->rx_ring[i];
1884 rxdesc->status = 0;
1885 rxdesc->addr = 0xBADF00D0;
1886 if (mdp->rx_skbuff[i])
1887 dev_kfree_skb(mdp->rx_skbuff[i]);
1888 mdp->rx_skbuff[i] = NULL;
1889 }
525b8075 1890 for (i = 0; i < mdp->num_tx_ring; i++) {
86a74ff2
NI		 1891 if (mdp->tx_skbuff[i])
1892 dev_kfree_skb(mdp->tx_skbuff[i]);
1893 mdp->tx_skbuff[i] = NULL;
1894 }
1895
1896 /* device init */
525b8075 1897 sh_eth_dev_init(ndev, true);
86a74ff2
NI		 1898}
1899
1900/* Packet transmit function */
1901static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1902{
1903 struct sh_eth_private *mdp = netdev_priv(ndev);
1904 struct sh_eth_txdesc *txdesc;
1905 u32 entry;
fb5e2f9b 1906 unsigned long flags;
86a74ff2
NI		 1907
1908 spin_lock_irqsave(&mdp->lock, flags);
525b8075 1909 if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
86a74ff2 1910 if (!sh_eth_txfree(ndev)) {
dc19e4e5
NI		 1911 if (netif_msg_tx_queued(mdp))
1912 dev_warn(&ndev->dev, "TxFD exhausted.\n");
86a74ff2
NI		 1913 netif_stop_queue(ndev);
1914 spin_unlock_irqrestore(&mdp->lock, flags);
5b548140 1915 return NETDEV_TX_BUSY;
86a74ff2
NI		 1916 }
1917 }
1918 spin_unlock_irqrestore(&mdp->lock, flags);
1919
525b8075 1920 entry = mdp->cur_tx % mdp->num_tx_ring;
86a74ff2
NI		 1921 mdp->tx_skbuff[entry] = skb;
1922 txdesc = &mdp->tx_ring[entry];
86a74ff2 1923 /* soft swap. */
380af9e3
YS		 1924 if (!mdp->cd->hw_swap)
1925 sh_eth_soft_swap(phys_to_virt(ALIGN(txdesc->addr, 4)),
1926 skb->len + 2);
31fcb99d
YS		 1927 txdesc->addr = dma_map_single(&ndev->dev, skb->data, skb->len,
1928 DMA_TO_DEVICE);
86a74ff2
NI		 1929 if (skb->len < ETHERSMALL)
1930 txdesc->buffer_length = ETHERSMALL;
1931 else
1932 txdesc->buffer_length = skb->len;
1933
525b8075 1934 if (entry >= mdp->num_tx_ring - 1)
71557a37 1935 txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE);
86a74ff2 1936 else
71557a37 1937 txdesc->status |= cpu_to_edmac(mdp, TD_TACT);
86a74ff2
NI		 1938
1939 mdp->cur_tx++;
1940
c5ed5368
YS		 1941 if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
1942 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
b0ca2a21 1943
6ed10654 1944 return NETDEV_TX_OK;
86a74ff2
NI		 1945}
1946
1947/* device close function */
1948static int sh_eth_close(struct net_device *ndev)
1949{
1950 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 1951
1952 netif_stop_queue(ndev);
1953
1954 /* Disable interrupts by clearing the interrupt mask. */
4a55530f 1955 sh_eth_write(ndev, 0x0000, EESIPR);
86a74ff2
NI		 1956
1957 /* Stop the chip's Tx and Rx processes. */
4a55530f
YS		 1958 sh_eth_write(ndev, 0, EDTRR);
1959 sh_eth_write(ndev, 0, EDRRR);
86a74ff2
NI		 1960
1961 /* PHY Disconnect */
1962 if (mdp->phydev) {
1963 phy_stop(mdp->phydev);
1964 phy_disconnect(mdp->phydev);
1965 }
1966
1967 free_irq(ndev->irq, ndev);
1968
86a74ff2
NI		 1969 /* Free all the skbuffs in the Rx queue. */
1970 sh_eth_ring_free(ndev);
1971
1972 /* free DMA buffer */
91c77550 1973 sh_eth_free_dma_buffer(mdp);
86a74ff2 1974
bcd5149d
MD		 1975 pm_runtime_put_sync(&mdp->pdev->dev);
1976
86a74ff2
NI		 1977 return 0;
1978}
1979
1980static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
1981{
1982 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2 1983
bcd5149d
MD		 1984 pm_runtime_get_sync(&mdp->pdev->dev);
1985
bb7d92e3 1986 ndev->stats.tx_dropped += sh_eth_read(ndev, TROCR);
4a55530f 1987 sh_eth_write(ndev, 0, TROCR); /* (write clear) */
bb7d92e3 1988 ndev->stats.collisions += sh_eth_read(ndev, CDCR);
4a55530f 1989 sh_eth_write(ndev, 0, CDCR); /* (write clear) */
bb7d92e3 1990 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, LCCR);
4a55530f 1991 sh_eth_write(ndev, 0, LCCR); /* (write clear) */
c5ed5368 1992 if (sh_eth_is_gether(mdp)) {
bb7d92e3 1993 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CERCR);
c5ed5368 1994 sh_eth_write(ndev, 0, CERCR); /* (write clear) */
bb7d92e3 1995 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CEECR);
c5ed5368
YS		 1996 sh_eth_write(ndev, 0, CEECR); /* (write clear) */
1997 } else {
bb7d92e3 1998 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CNDCR);
c5ed5368
YS		 1999 sh_eth_write(ndev, 0, CNDCR); /* (write clear) */
2000 }
bcd5149d
MD		 2001 pm_runtime_put_sync(&mdp->pdev->dev);
2002
bb7d92e3 2003 return &ndev->stats;
86a74ff2
NI		 2004}
2005
bb7d92e3 2006/* ioctl to device function */
86a74ff2
NI		 2007static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq,
2008 int cmd)
2009{
2010 struct sh_eth_private *mdp = netdev_priv(ndev);
2011 struct phy_device *phydev = mdp->phydev;
2012
2013 if (!netif_running(ndev))
2014 return -EINVAL;
2015
2016 if (!phydev)
2017 return -ENODEV;
2018
28b04113 2019 return phy_mii_ioctl(phydev, rq, cmd);
86a74ff2
NI		 2020}
2021
6743fe6d
YS		 2022/* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
2023static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp,
2024 int entry)
2025{
2026 return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4);
2027}
2028
2029static u32 sh_eth_tsu_get_post_mask(int entry)
2030{
2031 return 0x0f << (28 - ((entry % 8) * 4));
2032}
2033
2034static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
2035{
2036 return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
2037}
2038
2039static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
2040 int entry)
2041{
2042 struct sh_eth_private *mdp = netdev_priv(ndev);
2043 u32 tmp;
2044 void *reg_offset;
2045
2046 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2047 tmp = ioread32(reg_offset);
2048 iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset);
2049}
2050
2051static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
2052 int entry)
2053{
2054 struct sh_eth_private *mdp = netdev_priv(ndev);
2055 u32 post_mask, ref_mask, tmp;
2056 void *reg_offset;
2057
2058 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2059 post_mask = sh_eth_tsu_get_post_mask(entry);
2060 ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
2061
2062 tmp = ioread32(reg_offset);
2063 iowrite32(tmp & ~post_mask, reg_offset);
2064
2065 /* If other port enables, the function returns "true" */
2066 return tmp & ref_mask;
2067}
2068
2069static int sh_eth_tsu_busy(struct net_device *ndev)
2070{
2071 int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
2072 struct sh_eth_private *mdp = netdev_priv(ndev);
2073
2074 while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
2075 udelay(10);
2076 timeout--;
2077 if (timeout <= 0) {
2078 dev_err(&ndev->dev, "%s: timeout\n", __func__);
2079 return -ETIMEDOUT;
2080 }
2081 }
2082
2083 return 0;
2084}
2085
2086static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg,
2087 const u8 *addr)
2088{
2089 u32 val;
2090
2091 val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
2092 iowrite32(val, reg);
2093 if (sh_eth_tsu_busy(ndev) < 0)
2094 return -EBUSY;
2095
2096 val = addr[4] << 8 | addr[5];
2097 iowrite32(val, reg + 4);
2098 if (sh_eth_tsu_busy(ndev) < 0)
2099 return -EBUSY;
2100
2101 return 0;
2102}
2103
2104static void sh_eth_tsu_read_entry(void *reg, u8 *addr)
2105{
2106 u32 val;
2107
2108 val = ioread32(reg);
2109 addr[0] = (val >> 24) & 0xff;
2110 addr[1] = (val >> 16) & 0xff;
2111 addr[2] = (val >> 8) & 0xff;
2112 addr[3] = val & 0xff;
2113 val = ioread32(reg + 4);
2114 addr[4] = (val >> 8) & 0xff;
2115 addr[5] = val & 0xff;
2116}
2117
2118
2119static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
2120{
2121 struct sh_eth_private *mdp = netdev_priv(ndev);
2122 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2123 int i;
2124 u8 c_addr[ETH_ALEN];
2125
2126 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2127 sh_eth_tsu_read_entry(reg_offset, c_addr);
2128 if (memcmp(addr, c_addr, ETH_ALEN) == 0)
2129 return i;
2130 }
2131
2132 return -ENOENT;
2133}
2134
2135static int sh_eth_tsu_find_empty(struct net_device *ndev)
2136{
2137 u8 blank[ETH_ALEN];
2138 int entry;
2139
2140 memset(blank, 0, sizeof(blank));
2141 entry = sh_eth_tsu_find_entry(ndev, blank);
2142 return (entry < 0) ? -ENOMEM : entry;
2143}
2144
2145static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
2146 int entry)
2147{
2148 struct sh_eth_private *mdp = netdev_priv(ndev);
2149 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2150 int ret;
2151 u8 blank[ETH_ALEN];
2152
2153 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
2154 ~(1 << (31 - entry)), TSU_TEN);
2155
2156 memset(blank, 0, sizeof(blank));
2157 ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
2158 if (ret < 0)
2159 return ret;
2160 return 0;
2161}
2162
2163static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
2164{
2165 struct sh_eth_private *mdp = netdev_priv(ndev);
2166 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2167 int i, ret;
2168
2169 if (!mdp->cd->tsu)
2170 return 0;
2171
2172 i = sh_eth_tsu_find_entry(ndev, addr);
2173 if (i < 0) {
2174 /* No entry found, create one */
2175 i = sh_eth_tsu_find_empty(ndev);
2176 if (i < 0)
2177 return -ENOMEM;
2178 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
2179 if (ret < 0)
2180 return ret;
2181
2182 /* Enable the entry */
2183 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
2184 (1 << (31 - i)), TSU_TEN);
2185 }
2186
2187 /* Entry found or created, enable POST */
2188 sh_eth_tsu_enable_cam_entry_post(ndev, i);
2189
2190 return 0;
2191}
2192
2193static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
2194{
2195 struct sh_eth_private *mdp = netdev_priv(ndev);
2196 int i, ret;
2197
2198 if (!mdp->cd->tsu)
2199 return 0;
2200
2201 i = sh_eth_tsu_find_entry(ndev, addr);
2202 if (i) {
2203 /* Entry found */
2204 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2205 goto done;
2206
2207 /* Disable the entry if both ports was disabled */
2208 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2209 if (ret < 0)
2210 return ret;
2211 }
2212done:
2213 return 0;
2214}
2215
2216static int sh_eth_tsu_purge_all(struct net_device *ndev)
2217{
2218 struct sh_eth_private *mdp = netdev_priv(ndev);
2219 int i, ret;
2220
2221 if (unlikely(!mdp->cd->tsu))
2222 return 0;
2223
2224 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
2225 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2226 continue;
2227
2228 /* Disable the entry if both ports was disabled */
2229 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2230 if (ret < 0)
2231 return ret;
2232 }
2233
2234 return 0;
2235}
2236
2237static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
2238{
2239 struct sh_eth_private *mdp = netdev_priv(ndev);
2240 u8 addr[ETH_ALEN];
2241 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2242 int i;
2243
2244 if (unlikely(!mdp->cd->tsu))
2245 return;
2246
2247 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2248 sh_eth_tsu_read_entry(reg_offset, addr);
2249 if (is_multicast_ether_addr(addr))
2250 sh_eth_tsu_del_entry(ndev, addr);
2251 }
2252}
2253
86a74ff2
NI		 2254/* Multicast reception directions set */
2255static void sh_eth_set_multicast_list(struct net_device *ndev)
2256{
6743fe6d
YS		 2257 struct sh_eth_private *mdp = netdev_priv(ndev);
2258 u32 ecmr_bits;
2259 int mcast_all = 0;
2260 unsigned long flags;
2261
2262 spin_lock_irqsave(&mdp->lock, flags);
2263 /*
2264 * Initial condition is MCT = 1, PRM = 0.
2265 * Depending on ndev->flags, set PRM or clear MCT
2266 */
2267 ecmr_bits = (sh_eth_read(ndev, ECMR) & ~ECMR_PRM) | ECMR_MCT;
2268
2269 if (!(ndev->flags & IFF_MULTICAST)) {
2270 sh_eth_tsu_purge_mcast(ndev);
2271 mcast_all = 1;
2272 }
2273 if (ndev->flags & IFF_ALLMULTI) {
2274 sh_eth_tsu_purge_mcast(ndev);
2275 ecmr_bits &= ~ECMR_MCT;
2276 mcast_all = 1;
2277 }
2278
86a74ff2 2279 if (ndev->flags & IFF_PROMISC) {
6743fe6d
YS		 2280 sh_eth_tsu_purge_all(ndev);
2281 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2282 } else if (mdp->cd->tsu) {
2283 struct netdev_hw_addr *ha;
2284 netdev_for_each_mc_addr(ha, ndev) {
2285 if (mcast_all && is_multicast_ether_addr(ha->addr))
2286 continue;
2287
2288 if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2289 if (!mcast_all) {
2290 sh_eth_tsu_purge_mcast(ndev);
2291 ecmr_bits &= ~ECMR_MCT;
2292 mcast_all = 1;
2293 }
2294 }
2295 }
86a74ff2
NI		 2296 } else {
2297 /* Normal, unicast/broadcast-only mode. */
6743fe6d 2298 ecmr_bits = (ecmr_bits & ~ECMR_PRM) | ECMR_MCT;
86a74ff2 2299 }
6743fe6d
YS		 2300
2301 /* update the ethernet mode */
2302 sh_eth_write(ndev, ecmr_bits, ECMR);
2303
2304 spin_unlock_irqrestore(&mdp->lock, flags);
86a74ff2 2305}
71cc7c37
YS		 2306
2307static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2308{
2309 if (!mdp->port)
2310 return TSU_VTAG0;
2311 else
2312 return TSU_VTAG1;
2313}
2314
80d5c368
PM		 2315static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
2316 __be16 proto, u16 vid)
71cc7c37
YS		 2317{
2318 struct sh_eth_private *mdp = netdev_priv(ndev);
2319 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2320
2321 if (unlikely(!mdp->cd->tsu))
2322 return -EPERM;
2323
2324 /* No filtering if vid = 0 */
2325 if (!vid)
2326 return 0;
2327
2328 mdp->vlan_num_ids++;
2329
2330 /*
2331 * The controller has one VLAN tag HW filter. So, if the filter is
2332 * already enabled, the driver disables it and the filte
2333 */
2334 if (mdp->vlan_num_ids > 1) {
2335 /* disable VLAN filter */
2336 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2337 return 0;
2338 }
2339
2340 sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
2341 vtag_reg_index);
2342
2343 return 0;
2344}
2345
80d5c368
PM		 2346static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
2347 __be16 proto, u16 vid)
71cc7c37
YS		 2348{
2349 struct sh_eth_private *mdp = netdev_priv(ndev);
2350 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2351
2352 if (unlikely(!mdp->cd->tsu))
2353 return -EPERM;
2354
2355 /* No filtering if vid = 0 */
2356 if (!vid)
2357 return 0;
2358
2359 mdp->vlan_num_ids--;
2360 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2361
2362 return 0;
2363}
86a74ff2
NI		 2364
2365/* SuperH's TSU register init function */
4a55530f 2366static void sh_eth_tsu_init(struct sh_eth_private *mdp)
86a74ff2 2367{
4a55530f
YS		 2368 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */
2369 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */
2370 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */
2371 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
2372 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
2373 sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
2374 sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
2375 sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
2376 sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
2377 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
c5ed5368
YS		 2378 if (sh_eth_is_gether(mdp)) {
2379 sh_eth_tsu_write(mdp, 0, TSU_QTAG0); /* Disable QTAG(0->1) */
2380 sh_eth_tsu_write(mdp, 0, TSU_QTAG1); /* Disable QTAG(1->0) */
2381 } else {
2382 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */
2383 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */
2384 }
4a55530f
YS		 2385 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */
2386 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */
2387 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2388 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */
2389 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */
2390 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */
2391 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */
86a74ff2
NI		 2392}
2393
2394/* MDIO bus release function */
2395static int sh_mdio_release(struct net_device *ndev)
2396{
2397 struct mii_bus *bus = dev_get_drvdata(&ndev->dev);
2398
2399 /* unregister mdio bus */
2400 mdiobus_unregister(bus);
2401
2402 /* remove mdio bus info from net_device */
2403 dev_set_drvdata(&ndev->dev, NULL);
2404
2405 /* free bitbang info */
2406 free_mdio_bitbang(bus);
2407
2408 return 0;
2409}
2410
2411/* MDIO bus init function */
b3017e6a
YS		 2412static int sh_mdio_init(struct net_device *ndev, int id,
2413 struct sh_eth_plat_data *pd)
86a74ff2
NI		 2414{
2415 int ret, i;
2416 struct bb_info *bitbang;
2417 struct sh_eth_private *mdp = netdev_priv(ndev);
2418
2419 /* create bit control struct for PHY */
d5e07e69
SS		 2420 bitbang = devm_kzalloc(&ndev->dev, sizeof(struct bb_info),
2421 GFP_KERNEL);
86a74ff2
NI		 2422 if (!bitbang) {
2423 ret = -ENOMEM;
2424 goto out;
2425 }
2426
2427 /* bitbang init */
ae70644d 2428 bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
b3017e6a 2429 bitbang->set_gate = pd->set_mdio_gate;
dfed5e7f
SS		 2430 bitbang->mdi_msk = PIR_MDI;
2431 bitbang->mdo_msk = PIR_MDO;
2432 bitbang->mmd_msk = PIR_MMD;
2433 bitbang->mdc_msk = PIR_MDC;
86a74ff2
NI		 2434 bitbang->ctrl.ops = &bb_ops;
2435
c2e07b3a 2436 /* MII controller setting */
86a74ff2
NI		 2437 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
2438 if (!mdp->mii_bus) {
2439 ret = -ENOMEM;
d5e07e69 2440 goto out;
86a74ff2
NI		 2441 }
2442
2443 /* Hook up MII support for ethtool */
2444 mdp->mii_bus->name = "sh_mii";
18ee49dd 2445 mdp->mii_bus->parent = &ndev->dev;
5278fb54 2446 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
34aa6f14 2447 mdp->pdev->name, id);
86a74ff2
NI		 2448
2449 /* PHY IRQ */
d5e07e69
SS		 2450 mdp->mii_bus->irq = devm_kzalloc(&ndev->dev,
2451 sizeof(int) * PHY_MAX_ADDR,
2452 GFP_KERNEL);
86a74ff2
NI		 2453 if (!mdp->mii_bus->irq) {
2454 ret = -ENOMEM;
2455 goto out_free_bus;
2456 }
2457
2458 for (i = 0; i < PHY_MAX_ADDR; i++)
2459 mdp->mii_bus->irq[i] = PHY_POLL;
2460
8f6352f2 2461 /* register mdio bus */
86a74ff2
NI		 2462 ret = mdiobus_register(mdp->mii_bus);
2463 if (ret)
d5e07e69 2464 goto out_free_bus;
86a74ff2
NI		 2465
2466 dev_set_drvdata(&ndev->dev, mdp->mii_bus);
2467
2468 return 0;
2469
86a74ff2 2470out_free_bus:
298cf9be 2471 free_mdio_bitbang(mdp->mii_bus);
86a74ff2 2472
86a74ff2
NI		 2473out:
2474 return ret;
2475}
2476
4a55530f
YS		 2477static const u16 *sh_eth_get_register_offset(int register_type)
2478{
2479 const u16 *reg_offset = NULL;
2480
2481 switch (register_type) {
2482 case SH_ETH_REG_GIGABIT:
2483 reg_offset = sh_eth_offset_gigabit;
2484 break;
a3f109bd
SS		 2485 case SH_ETH_REG_FAST_RCAR:
2486 reg_offset = sh_eth_offset_fast_rcar;
2487 break;
4a55530f
YS		 2488 case SH_ETH_REG_FAST_SH4:
2489 reg_offset = sh_eth_offset_fast_sh4;
2490 break;
2491 case SH_ETH_REG_FAST_SH3_SH2:
2492 reg_offset = sh_eth_offset_fast_sh3_sh2;
2493 break;
2494 default:
14c3326a 2495 pr_err("Unknown register type (%d)\n", register_type);
4a55530f
YS		 2496 break;
2497 }
2498
2499 return reg_offset;
2500}
2501
9f861341 2502static struct net_device_ops sh_eth_netdev_ops = {
ebf84eaa
AB		 2503 .ndo_open = sh_eth_open,
2504 .ndo_stop = sh_eth_close,
2505 .ndo_start_xmit = sh_eth_start_xmit,
2506 .ndo_get_stats = sh_eth_get_stats,
ebf84eaa
AB		 2507 .ndo_tx_timeout = sh_eth_tx_timeout,
2508 .ndo_do_ioctl = sh_eth_do_ioctl,
2509 .ndo_validate_addr = eth_validate_addr,
2510 .ndo_set_mac_address = eth_mac_addr,
2511 .ndo_change_mtu = eth_change_mtu,
2512};
2513
86a74ff2
NI		 2514static int sh_eth_drv_probe(struct platform_device *pdev)
2515{
9c38657c 2516 int ret, devno = 0;
86a74ff2
NI		 2517 struct resource *res;
2518 struct net_device *ndev = NULL;
ec0d7551 2519 struct sh_eth_private *mdp = NULL;
564044b0 2520 struct sh_eth_plat_data *pd = pdev->dev.platform_data;
afe391ad 2521 const struct platform_device_id *id = platform_get_device_id(pdev);
86a74ff2
NI		 2522
2523 /* get base addr */
2524 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2525 if (unlikely(res == NULL)) {
2526 dev_err(&pdev->dev, "invalid resource\n");
2527 ret = -EINVAL;
2528 goto out;
2529 }
2530
2531 ndev = alloc_etherdev(sizeof(struct sh_eth_private));
2532 if (!ndev) {
86a74ff2
NI		 2533 ret = -ENOMEM;
2534 goto out;
2535 }
2536
2537 /* The sh Ether-specific entries in the device structure. */
2538 ndev->base_addr = res->start;
2539 devno = pdev->id;
2540 if (devno < 0)
2541 devno = 0;
2542
2543 ndev->dma = -1;
cc3c080d 2544 ret = platform_get_irq(pdev, 0);
2545 if (ret < 0) {
86a74ff2
NI		 2546 ret = -ENODEV;
2547 goto out_release;
2548 }
cc3c080d 2549 ndev->irq = ret;
86a74ff2
NI		 2550
2551 SET_NETDEV_DEV(ndev, &pdev->dev);
2552
2553 /* Fill in the fields of the device structure with ethernet values. */
2554 ether_setup(ndev);
2555
2556 mdp = netdev_priv(ndev);
525b8075
YS		 2557 mdp->num_tx_ring = TX_RING_SIZE;
2558 mdp->num_rx_ring = RX_RING_SIZE;
d5e07e69
SS		 2559 mdp->addr = devm_ioremap_resource(&pdev->dev, res);
2560 if (IS_ERR(mdp->addr)) {
2561 ret = PTR_ERR(mdp->addr);
ae70644d
YS		 2562 goto out_release;
2563 }
2564
86a74ff2 2565 spin_lock_init(&mdp->lock);
bcd5149d
MD		 2566 mdp->pdev = pdev;
2567 pm_runtime_enable(&pdev->dev);
2568 pm_runtime_resume(&pdev->dev);
86a74ff2
NI		 2569
2570 /* get PHY ID */
71557a37 2571 mdp->phy_id = pd->phy;
e47c9052 2572 mdp->phy_interface = pd->phy_interface;
71557a37
YS		 2573 /* EDMAC endian */
2574 mdp->edmac_endian = pd->edmac_endian;
4923576b
YS		 2575 mdp->no_ether_link = pd->no_ether_link;
2576 mdp->ether_link_active_low = pd->ether_link_active_low;
4a55530f 2577 mdp->reg_offset = sh_eth_get_register_offset(pd->register_type);
86a74ff2 2578
380af9e3 2579 /* set cpu data */
8fcd4961
YS		 2580#if defined(SH_ETH_HAS_BOTH_MODULES)
2581 mdp->cd = sh_eth_get_cpu_data(mdp);
2582#else
380af9e3 2583 mdp->cd = &sh_eth_my_cpu_data;
8fcd4961 2584#endif
afe391ad
SS		 2585 if (id->driver_data)
2586 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data;
380af9e3
YS		 2587 sh_eth_set_default_cpu_data(mdp->cd);
2588
86a74ff2 2589 /* set function */
9f861341
NI		 2590 if (mdp->cd->tsu) {
2591 sh_eth_netdev_ops.ndo_set_rx_mode = sh_eth_set_multicast_list;
2592 sh_eth_netdev_ops.ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid;
2593 sh_eth_netdev_ops.ndo_vlan_rx_kill_vid =
2594 sh_eth_vlan_rx_kill_vid;
2595 }
2596
ebf84eaa 2597 ndev->netdev_ops = &sh_eth_netdev_ops;
dc19e4e5 2598 SET_ETHTOOL_OPS(ndev, &sh_eth_ethtool_ops);
86a74ff2
NI		 2599 ndev->watchdog_timeo = TX_TIMEOUT;
2600
dc19e4e5
NI		 2601 /* debug message level */
2602 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
86a74ff2
NI		 2603
2604 /* read and set MAC address */
748031f9 2605 read_mac_address(ndev, pd->mac_addr);
ff6e7228
SS		 2606 if (!is_valid_ether_addr(ndev->dev_addr)) {
2607 dev_warn(&pdev->dev,
2608 "no valid MAC address supplied, using a random one.\n");
2609 eth_hw_addr_random(ndev);
2610 }
86a74ff2 2611
6ba88021
YS		 2612 /* ioremap the TSU registers */
2613 if (mdp->cd->tsu) {
2614 struct resource *rtsu;
2615 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
d5e07e69
SS		 2616 mdp->tsu_addr = devm_ioremap_resource(&pdev->dev, rtsu);
2617 if (IS_ERR(mdp->tsu_addr)) {
2618 ret = PTR_ERR(mdp->tsu_addr);
fc0c0900
SS		 2619 goto out_release;
2620 }
6743fe6d 2621 mdp->port = devno % 2;
f646968f 2622 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER;
6ba88021
YS		 2623 }
2624
150647fb
YS		 2625 /* initialize first or needed device */
2626 if (!devno || pd->needs_init) {
380af9e3
YS		 2627 if (mdp->cd->chip_reset)
2628 mdp->cd->chip_reset(ndev);
86a74ff2 2629
4986b996
YS		 2630 if (mdp->cd->tsu) {
2631 /* TSU init (Init only)*/
2632 sh_eth_tsu_init(mdp);
2633 }
86a74ff2
NI		 2634 }
2635
2636 /* network device register */
2637 ret = register_netdev(ndev);
2638 if (ret)
2639 goto out_release;
2640
2641 /* mdio bus init */
b3017e6a 2642 ret = sh_mdio_init(ndev, pdev->id, pd);
86a74ff2
NI		 2643 if (ret)
2644 goto out_unregister;
2645
25985edc 2646 /* print device information */
6cd9b49d
HS		 2647 pr_info("Base address at 0x%x, %pM, IRQ %d.\n",
2648 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
86a74ff2
NI		 2649
2650 platform_set_drvdata(pdev, ndev);
2651
2652 return ret;
2653
2654out_unregister:
2655 unregister_netdev(ndev);
2656
2657out_release:
2658 /* net_dev free */
2659 if (ndev)
2660 free_netdev(ndev);
2661
2662out:
2663 return ret;
2664}
2665
2666static int sh_eth_drv_remove(struct platform_device *pdev)
2667{
2668 struct net_device *ndev = platform_get_drvdata(pdev);
2669
2670 sh_mdio_release(ndev);
2671 unregister_netdev(ndev);
bcd5149d 2672 pm_runtime_disable(&pdev->dev);
86a74ff2 2673 free_netdev(ndev);
86a74ff2
NI		 2674
2675 return 0;
2676}
2677
540ad1b8 2678#ifdef CONFIG_PM
bcd5149d
MD		 2679static int sh_eth_runtime_nop(struct device *dev)
2680{
2681 /*
2682 * Runtime PM callback shared between ->runtime_suspend()
2683 * and ->runtime_resume(). Simply returns success.
2684 *
2685 * This driver re-initializes all registers after
2686 * pm_runtime_get_sync() anyway so there is no need
2687 * to save and restore registers here.
2688 */
2689 return 0;
2690}
2691
540ad1b8 2692static const struct dev_pm_ops sh_eth_dev_pm_ops = {
bcd5149d
MD		 2693 .runtime_suspend = sh_eth_runtime_nop,
2694 .runtime_resume = sh_eth_runtime_nop,
2695};
540ad1b8
NI		 2696#define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
2697#else
2698#define SH_ETH_PM_OPS NULL
2699#endif
bcd5149d 2700
afe391ad 2701static struct platform_device_id sh_eth_id_table[] = {
c18a79ab 2702 { "sh7619-ether", (kernel_ulong_t)&sh7619_data },
7bbe150d 2703 { "sh771x-ether", (kernel_ulong_t)&sh771x_data },
f5d12767
SS		 2704 { "sh7734-gether", (kernel_ulong_t)&sh7734_data },
2705 { "sh7763-gether", (kernel_ulong_t)&sh7763_data },
e5c9b4cd 2706 { "r8a7740-gether", (kernel_ulong_t)&r8a7740_data },
afe391ad
SS		 2707 { CARDNAME },
2708 { }
2709};
2710MODULE_DEVICE_TABLE(platform, sh_eth_id_table);
2711
86a74ff2
NI		 2712static struct platform_driver sh_eth_driver = {
2713 .probe = sh_eth_drv_probe,
2714 .remove = sh_eth_drv_remove,
afe391ad 2715 .id_table = sh_eth_id_table,
86a74ff2
NI		 2716 .driver = {
2717 .name = CARDNAME,
540ad1b8 2718 .pm = SH_ETH_PM_OPS,
86a74ff2
NI		 2719 },
2720};
2721
db62f684 2722module_platform_driver(sh_eth_driver);
86a74ff2
NI		 2723
2724MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
2725MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
2726MODULE_LICENSE("GPL v2");
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