[mirror_ubuntu-zesty-kernel.git] / drivers / net / ethernet / rocker / rocker.h

/*
 * drivers/net/ethernet/rocker/rocker.h - Rocker switch device driver
 * Copyright (c) 2014 Jiri Pirko <jiri@resnulli.us>
 * Copyright (c) 2014 Scott Feldman <sfeldma@gmail.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#ifndef _ROCKER_H
#define _ROCKER_H

#include <linux/types.h>

/* Return codes */
enum {
	ROCKER_OK = 0,
	ROCKER_ENOENT = 2,
	ROCKER_ENXIO = 6,
	ROCKER_ENOMEM = 12,
	ROCKER_EEXIST = 17,
	ROCKER_EINVAL = 22,
	ROCKER_EMSGSIZE = 90,
	ROCKER_ENOTSUP = 95,
	ROCKER_ENOBUFS = 105,
};

#define PCI_VENDOR_ID_REDHAT		0x1b36
#define PCI_DEVICE_ID_REDHAT_ROCKER	0x0006

#define ROCKER_PCI_BAR0_SIZE		0x2000

/* MSI-X vectors */
enum {
	ROCKER_MSIX_VEC_CMD,
	ROCKER_MSIX_VEC_EVENT,
	ROCKER_MSIX_VEC_TEST,
	ROCKER_MSIX_VEC_RESERVED0,
	__ROCKER_MSIX_VEC_TX,
	__ROCKER_MSIX_VEC_RX,
#define ROCKER_MSIX_VEC_TX(port) \
	(__ROCKER_MSIX_VEC_TX + ((port) * 2))
#define ROCKER_MSIX_VEC_RX(port) \
	(__ROCKER_MSIX_VEC_RX + ((port) * 2))
#define ROCKER_MSIX_VEC_COUNT(portcnt) \
	(ROCKER_MSIX_VEC_RX((portcnt - 1)) + 1)
};

/* Rocker bogus registers */
#define ROCKER_BOGUS_REG0		0x0000
#define ROCKER_BOGUS_REG1		0x0004
#define ROCKER_BOGUS_REG2		0x0008
#define ROCKER_BOGUS_REG3		0x000c

/* Rocker test registers */
#define ROCKER_TEST_REG			0x0010
#define ROCKER_TEST_REG64		0x0018  /* 8-byte */
#define ROCKER_TEST_IRQ			0x0020
#define ROCKER_TEST_DMA_ADDR		0x0028  /* 8-byte */
#define ROCKER_TEST_DMA_SIZE		0x0030
#define ROCKER_TEST_DMA_CTRL		0x0034

/* Rocker test register ctrl */
#define ROCKER_TEST_DMA_CTRL_CLEAR	(1 << 0)
#define ROCKER_TEST_DMA_CTRL_FILL	(1 << 1)
#define ROCKER_TEST_DMA_CTRL_INVERT	(1 << 2)

/* Rocker DMA ring register offsets */
#define ROCKER_DMA_DESC_ADDR(x)		(0x1000 + (x) * 32)  /* 8-byte */
#define ROCKER_DMA_DESC_SIZE(x)		(0x1008 + (x) * 32)
#define ROCKER_DMA_DESC_HEAD(x)		(0x100c + (x) * 32)
#define ROCKER_DMA_DESC_TAIL(x)		(0x1010 + (x) * 32)
#define ROCKER_DMA_DESC_CTRL(x)		(0x1014 + (x) * 32)
#define ROCKER_DMA_DESC_CREDITS(x)	(0x1018 + (x) * 32)
#define ROCKER_DMA_DESC_RES1(x)		(0x101c + (x) * 32)

/* Rocker dma ctrl register bits */
#define ROCKER_DMA_DESC_CTRL_RESET	(1 << 0)

/* Rocker DMA ring types */
enum rocker_dma_type {
	ROCKER_DMA_CMD,
	ROCKER_DMA_EVENT,
	__ROCKER_DMA_TX,
	__ROCKER_DMA_RX,
#define ROCKER_DMA_TX(port) (__ROCKER_DMA_TX + (port) * 2)
#define ROCKER_DMA_RX(port) (__ROCKER_DMA_RX + (port) * 2)
};

/* Rocker DMA ring size limits and default sizes */
#define ROCKER_DMA_SIZE_MIN		2ul
#define ROCKER_DMA_SIZE_MAX		65536ul
#define ROCKER_DMA_CMD_DEFAULT_SIZE	32ul
#define ROCKER_DMA_EVENT_DEFAULT_SIZE	32ul
#define ROCKER_DMA_TX_DEFAULT_SIZE	64ul
#define ROCKER_DMA_TX_DESC_SIZE		256
#define ROCKER_DMA_RX_DEFAULT_SIZE	64ul
#define ROCKER_DMA_RX_DESC_SIZE		256

/* Rocker DMA descriptor struct */
struct rocker_desc {
	u64 buf_addr;
	u64 cookie;
	u16 buf_size;
	u16 tlv_size;
	u16 resv[5];
	u16 comp_err;
};

#define ROCKER_DMA_DESC_COMP_ERR_GEN	(1 << 15)

/* Rocker DMA TLV struct */
struct rocker_tlv {
	u32 type;
	u16 len;
};

/* TLVs */
enum {
	ROCKER_TLV_CMD_UNSPEC,
	ROCKER_TLV_CMD_TYPE,	/* u16 */
	ROCKER_TLV_CMD_INFO,	/* nest */

	__ROCKER_TLV_CMD_MAX,
	ROCKER_TLV_CMD_MAX = __ROCKER_TLV_CMD_MAX - 1,
};

enum {
	ROCKER_TLV_CMD_TYPE_UNSPEC,
	ROCKER_TLV_CMD_TYPE_GET_PORT_SETTINGS,
	ROCKER_TLV_CMD_TYPE_SET_PORT_SETTINGS,
	ROCKER_TLV_CMD_TYPE_OF_DPA_FLOW_ADD,
	ROCKER_TLV_CMD_TYPE_OF_DPA_FLOW_MOD,
	ROCKER_TLV_CMD_TYPE_OF_DPA_FLOW_DEL,
	ROCKER_TLV_CMD_TYPE_OF_DPA_FLOW_GET_STATS,
	ROCKER_TLV_CMD_TYPE_OF_DPA_GROUP_ADD,
	ROCKER_TLV_CMD_TYPE_OF_DPA_GROUP_MOD,
	ROCKER_TLV_CMD_TYPE_OF_DPA_GROUP_DEL,
	ROCKER_TLV_CMD_TYPE_OF_DPA_GROUP_GET_STATS,

	ROCKER_TLV_CMD_TYPE_CLEAR_PORT_STATS,
	ROCKER_TLV_CMD_TYPE_GET_PORT_STATS,

	__ROCKER_TLV_CMD_TYPE_MAX,
	ROCKER_TLV_CMD_TYPE_MAX = __ROCKER_TLV_CMD_TYPE_MAX - 1,
};

enum {
	ROCKER_TLV_CMD_PORT_SETTINGS_UNSPEC,
	ROCKER_TLV_CMD_PORT_SETTINGS_LPORT,		/* u32 */
	ROCKER_TLV_CMD_PORT_SETTINGS_SPEED,		/* u32 */
	ROCKER_TLV_CMD_PORT_SETTINGS_DUPLEX,		/* u8 */
	ROCKER_TLV_CMD_PORT_SETTINGS_AUTONEG,		/* u8 */
	ROCKER_TLV_CMD_PORT_SETTINGS_MACADDR,		/* binary */
	ROCKER_TLV_CMD_PORT_SETTINGS_MODE,		/* u8 */
	ROCKER_TLV_CMD_PORT_SETTINGS_LEARNING,		/* u8 */

	__ROCKER_TLV_CMD_PORT_SETTINGS_MAX,
	ROCKER_TLV_CMD_PORT_SETTINGS_MAX =
			__ROCKER_TLV_CMD_PORT_SETTINGS_MAX - 1,
};

enum {
	ROCKER_TLV_CMD_PORT_STATS_UNSPEC,
	ROCKER_TLV_CMD_PORT_STATS_LPORT,            /* u32 */

	ROCKER_TLV_CMD_PORT_STATS_RX_PKTS,          /* u64 */
	ROCKER_TLV_CMD_PORT_STATS_RX_BYTES,         /* u64 */
	ROCKER_TLV_CMD_PORT_STATS_RX_DROPPED,       /* u64 */
	ROCKER_TLV_CMD_PORT_STATS_RX_ERRORS,        /* u64 */

	ROCKER_TLV_CMD_PORT_STATS_TX_PKTS,          /* u64 */
	ROCKER_TLV_CMD_PORT_STATS_TX_BYTES,         /* u64 */
	ROCKER_TLV_CMD_PORT_STATS_TX_DROPPED,       /* u64 */
	ROCKER_TLV_CMD_PORT_STATS_TX_ERRORS,        /* u64 */

	__ROCKER_TLV_CMD_PORT_STATS_MAX,
	ROCKER_TLV_CMD_PORT_STATS_MAX = __ROCKER_TLV_CMD_PORT_STATS_MAX - 1,
};

enum rocker_port_mode {
	ROCKER_PORT_MODE_OF_DPA,
};

enum {
	ROCKER_TLV_EVENT_UNSPEC,
	ROCKER_TLV_EVENT_TYPE,	/* u16 */
	ROCKER_TLV_EVENT_INFO,	/* nest */

	__ROCKER_TLV_EVENT_MAX,
	ROCKER_TLV_EVENT_MAX = __ROCKER_TLV_EVENT_MAX - 1,
};

enum {
	ROCKER_TLV_EVENT_TYPE_UNSPEC,
	ROCKER_TLV_EVENT_TYPE_LINK_CHANGED,
	ROCKER_TLV_EVENT_TYPE_MAC_VLAN_SEEN,

	__ROCKER_TLV_EVENT_TYPE_MAX,
	ROCKER_TLV_EVENT_TYPE_MAX = __ROCKER_TLV_EVENT_TYPE_MAX - 1,
};

enum {
	ROCKER_TLV_EVENT_LINK_CHANGED_UNSPEC,
	ROCKER_TLV_EVENT_LINK_CHANGED_LPORT,	/* u32 */
	ROCKER_TLV_EVENT_LINK_CHANGED_LINKUP,	/* u8 */

	__ROCKER_TLV_EVENT_LINK_CHANGED_MAX,
	ROCKER_TLV_EVENT_LINK_CHANGED_MAX =
			__ROCKER_TLV_EVENT_LINK_CHANGED_MAX - 1,
};

enum {
	ROCKER_TLV_EVENT_MAC_VLAN_UNSPEC,
	ROCKER_TLV_EVENT_MAC_VLAN_LPORT,	/* u32 */
	ROCKER_TLV_EVENT_MAC_VLAN_MAC,		/* binary */
	ROCKER_TLV_EVENT_MAC_VLAN_VLAN_ID,	/* __be16 */

	__ROCKER_TLV_EVENT_MAC_VLAN_MAX,
	ROCKER_TLV_EVENT_MAC_VLAN_MAX = __ROCKER_TLV_EVENT_MAC_VLAN_MAX - 1,
};

enum {
	ROCKER_TLV_RX_UNSPEC,
	ROCKER_TLV_RX_FLAGS,		/* u16, see ROCKER_RX_FLAGS_ */
	ROCKER_TLV_RX_CSUM,		/* u16 */
	ROCKER_TLV_RX_FRAG_ADDR,	/* u64 */
	ROCKER_TLV_RX_FRAG_MAX_LEN,	/* u16 */
	ROCKER_TLV_RX_FRAG_LEN,		/* u16 */

	__ROCKER_TLV_RX_MAX,
	ROCKER_TLV_RX_MAX = __ROCKER_TLV_RX_MAX - 1,
};

#define ROCKER_RX_FLAGS_IPV4			(1 << 0)
#define ROCKER_RX_FLAGS_IPV6			(1 << 1)
#define ROCKER_RX_FLAGS_CSUM_CALC		(1 << 2)
#define ROCKER_RX_FLAGS_IPV4_CSUM_GOOD		(1 << 3)
#define ROCKER_RX_FLAGS_IP_FRAG			(1 << 4)
#define ROCKER_RX_FLAGS_TCP			(1 << 5)
#define ROCKER_RX_FLAGS_UDP			(1 << 6)
#define ROCKER_RX_FLAGS_TCP_UDP_CSUM_GOOD	(1 << 7)

enum {
	ROCKER_TLV_TX_UNSPEC,
	ROCKER_TLV_TX_OFFLOAD,		/* u8, see ROCKER_TX_OFFLOAD_ */
	ROCKER_TLV_TX_L3_CSUM_OFF,	/* u16 */
	ROCKER_TLV_TX_TSO_MSS,		/* u16 */
	ROCKER_TLV_TX_TSO_HDR_LEN,	/* u16 */
	ROCKER_TLV_TX_FRAGS,		/* array */

	__ROCKER_TLV_TX_MAX,
	ROCKER_TLV_TX_MAX = __ROCKER_TLV_TX_MAX - 1,
};

#define ROCKER_TX_OFFLOAD_NONE		0
#define ROCKER_TX_OFFLOAD_IP_CSUM	1
#define ROCKER_TX_OFFLOAD_TCP_UDP_CSUM	2
#define ROCKER_TX_OFFLOAD_L3_CSUM	3
#define ROCKER_TX_OFFLOAD_TSO		4

#define ROCKER_TX_FRAGS_MAX		16

enum {
	ROCKER_TLV_TX_FRAG_UNSPEC,
	ROCKER_TLV_TX_FRAG,		/* nest */

	__ROCKER_TLV_TX_FRAG_MAX,
	ROCKER_TLV_TX_FRAG_MAX = __ROCKER_TLV_TX_FRAG_MAX - 1,
};

enum {
	ROCKER_TLV_TX_FRAG_ATTR_UNSPEC,
	ROCKER_TLV_TX_FRAG_ATTR_ADDR,	/* u64 */
	ROCKER_TLV_TX_FRAG_ATTR_LEN,	/* u16 */

	__ROCKER_TLV_TX_FRAG_ATTR_MAX,
	ROCKER_TLV_TX_FRAG_ATTR_MAX = __ROCKER_TLV_TX_FRAG_ATTR_MAX - 1,
};

/* cmd info nested for OF-DPA msgs */
enum {
	ROCKER_TLV_OF_DPA_UNSPEC,
	ROCKER_TLV_OF_DPA_TABLE_ID,		/* u16 */
	ROCKER_TLV_OF_DPA_PRIORITY,		/* u32 */
	ROCKER_TLV_OF_DPA_HARDTIME,		/* u32 */
	ROCKER_TLV_OF_DPA_IDLETIME,		/* u32 */
	ROCKER_TLV_OF_DPA_COOKIE,		/* u64 */
	ROCKER_TLV_OF_DPA_IN_LPORT,		/* u32 */
	ROCKER_TLV_OF_DPA_IN_LPORT_MASK,	/* u32 */
	ROCKER_TLV_OF_DPA_OUT_LPORT,		/* u32 */
	ROCKER_TLV_OF_DPA_GOTO_TABLE_ID,	/* u16 */
	ROCKER_TLV_OF_DPA_GROUP_ID,		/* u32 */
	ROCKER_TLV_OF_DPA_GROUP_ID_LOWER,	/* u32 */
	ROCKER_TLV_OF_DPA_GROUP_COUNT,		/* u16 */
	ROCKER_TLV_OF_DPA_GROUP_IDS,		/* u32 array */
	ROCKER_TLV_OF_DPA_VLAN_ID,		/* __be16 */
	ROCKER_TLV_OF_DPA_VLAN_ID_MASK,		/* __be16 */
	ROCKER_TLV_OF_DPA_VLAN_PCP,		/* __be16 */
	ROCKER_TLV_OF_DPA_VLAN_PCP_MASK,	/* __be16 */
	ROCKER_TLV_OF_DPA_VLAN_PCP_ACTION,	/* u8 */
	ROCKER_TLV_OF_DPA_NEW_VLAN_ID,		/* __be16 */
	ROCKER_TLV_OF_DPA_NEW_VLAN_PCP,		/* u8 */
	ROCKER_TLV_OF_DPA_TUNNEL_ID,		/* u32 */
	ROCKER_TLV_OF_DPA_TUN_LOG_LPORT,	/* u32 */
	ROCKER_TLV_OF_DPA_ETHERTYPE,		/* __be16 */
	ROCKER_TLV_OF_DPA_DST_MAC,		/* binary */
	ROCKER_TLV_OF_DPA_DST_MAC_MASK,		/* binary */
	ROCKER_TLV_OF_DPA_SRC_MAC,		/* binary */
	ROCKER_TLV_OF_DPA_SRC_MAC_MASK,		/* binary */
	ROCKER_TLV_OF_DPA_IP_PROTO,		/* u8 */
	ROCKER_TLV_OF_DPA_IP_PROTO_MASK,	/* u8 */
	ROCKER_TLV_OF_DPA_IP_DSCP,		/* u8 */
	ROCKER_TLV_OF_DPA_IP_DSCP_MASK,		/* u8 */
	ROCKER_TLV_OF_DPA_IP_DSCP_ACTION,	/* u8 */
	ROCKER_TLV_OF_DPA_NEW_IP_DSCP,		/* u8 */
	ROCKER_TLV_OF_DPA_IP_ECN,		/* u8 */
	ROCKER_TLV_OF_DPA_IP_ECN_MASK,		/* u8 */
	ROCKER_TLV_OF_DPA_DST_IP,		/* __be32 */
	ROCKER_TLV_OF_DPA_DST_IP_MASK,		/* __be32 */
	ROCKER_TLV_OF_DPA_SRC_IP,		/* __be32 */
	ROCKER_TLV_OF_DPA_SRC_IP_MASK,		/* __be32 */
	ROCKER_TLV_OF_DPA_DST_IPV6,		/* binary */
	ROCKER_TLV_OF_DPA_DST_IPV6_MASK,	/* binary */
	ROCKER_TLV_OF_DPA_SRC_IPV6,		/* binary */
	ROCKER_TLV_OF_DPA_SRC_IPV6_MASK,	/* binary */
	ROCKER_TLV_OF_DPA_SRC_ARP_IP,		/* __be32 */
	ROCKER_TLV_OF_DPA_SRC_ARP_IP_MASK,	/* __be32 */
	ROCKER_TLV_OF_DPA_L4_DST_PORT,		/* __be16 */
	ROCKER_TLV_OF_DPA_L4_DST_PORT_MASK,	/* __be16 */
	ROCKER_TLV_OF_DPA_L4_SRC_PORT,		/* __be16 */
	ROCKER_TLV_OF_DPA_L4_SRC_PORT_MASK,	/* __be16 */
	ROCKER_TLV_OF_DPA_ICMP_TYPE,		/* u8 */
	ROCKER_TLV_OF_DPA_ICMP_TYPE_MASK,	/* u8 */
	ROCKER_TLV_OF_DPA_ICMP_CODE,		/* u8 */
	ROCKER_TLV_OF_DPA_ICMP_CODE_MASK,	/* u8 */
	ROCKER_TLV_OF_DPA_IPV6_LABEL,		/* __be32 */
	ROCKER_TLV_OF_DPA_IPV6_LABEL_MASK,	/* __be32 */
	ROCKER_TLV_OF_DPA_QUEUE_ID_ACTION,	/* u8 */
	ROCKER_TLV_OF_DPA_NEW_QUEUE_ID,		/* u8 */
	ROCKER_TLV_OF_DPA_CLEAR_ACTIONS,	/* u32 */
	ROCKER_TLV_OF_DPA_POP_VLAN,		/* u8 */
	ROCKER_TLV_OF_DPA_TTL_CHECK,		/* u8 */
	ROCKER_TLV_OF_DPA_COPY_CPU_ACTION,	/* u8 */

	__ROCKER_TLV_OF_DPA_MAX,
	ROCKER_TLV_OF_DPA_MAX = __ROCKER_TLV_OF_DPA_MAX - 1,
};

/* OF-DPA table IDs */

enum rocker_of_dpa_table_id {
	ROCKER_OF_DPA_TABLE_ID_INGRESS_PORT = 0,
	ROCKER_OF_DPA_TABLE_ID_VLAN = 10,
	ROCKER_OF_DPA_TABLE_ID_TERMINATION_MAC = 20,
	ROCKER_OF_DPA_TABLE_ID_UNICAST_ROUTING = 30,
	ROCKER_OF_DPA_TABLE_ID_MULTICAST_ROUTING = 40,
	ROCKER_OF_DPA_TABLE_ID_BRIDGING = 50,
	ROCKER_OF_DPA_TABLE_ID_ACL_POLICY = 60,
};

/* OF-DPA flow stats */
enum {
	ROCKER_TLV_OF_DPA_FLOW_STAT_UNSPEC,
	ROCKER_TLV_OF_DPA_FLOW_STAT_DURATION,	/* u32 */
	ROCKER_TLV_OF_DPA_FLOW_STAT_RX_PKTS,	/* u64 */
	ROCKER_TLV_OF_DPA_FLOW_STAT_TX_PKTS,	/* u64 */

	__ROCKER_TLV_OF_DPA_FLOW_STAT_MAX,
	ROCKER_TLV_OF_DPA_FLOW_STAT_MAX = __ROCKER_TLV_OF_DPA_FLOW_STAT_MAX - 1,
};

/* OF-DPA group types */
enum rocker_of_dpa_group_type {
	ROCKER_OF_DPA_GROUP_TYPE_L2_INTERFACE = 0,
	ROCKER_OF_DPA_GROUP_TYPE_L2_REWRITE,
	ROCKER_OF_DPA_GROUP_TYPE_L3_UCAST,
	ROCKER_OF_DPA_GROUP_TYPE_L2_MCAST,
	ROCKER_OF_DPA_GROUP_TYPE_L2_FLOOD,
	ROCKER_OF_DPA_GROUP_TYPE_L3_INTERFACE,
	ROCKER_OF_DPA_GROUP_TYPE_L3_MCAST,
	ROCKER_OF_DPA_GROUP_TYPE_L3_ECMP,
	ROCKER_OF_DPA_GROUP_TYPE_L2_OVERLAY,
};

/* OF-DPA group L2 overlay types */
enum rocker_of_dpa_overlay_type {
	ROCKER_OF_DPA_OVERLAY_TYPE_FLOOD_UCAST = 0,
	ROCKER_OF_DPA_OVERLAY_TYPE_FLOOD_MCAST,
	ROCKER_OF_DPA_OVERLAY_TYPE_MCAST_UCAST,
	ROCKER_OF_DPA_OVERLAY_TYPE_MCAST_MCAST,
};

/* OF-DPA group ID encoding */
#define ROCKER_GROUP_TYPE_SHIFT 28
#define ROCKER_GROUP_TYPE_MASK 0xf0000000
#define ROCKER_GROUP_VLAN_SHIFT 16
#define ROCKER_GROUP_VLAN_MASK 0x0fff0000
#define ROCKER_GROUP_PORT_SHIFT 0
#define ROCKER_GROUP_PORT_MASK 0x0000ffff
#define ROCKER_GROUP_TUNNEL_ID_SHIFT 12
#define ROCKER_GROUP_TUNNEL_ID_MASK 0x0ffff000
#define ROCKER_GROUP_SUBTYPE_SHIFT 10
#define ROCKER_GROUP_SUBTYPE_MASK 0x00000c00
#define ROCKER_GROUP_INDEX_SHIFT 0
#define ROCKER_GROUP_INDEX_MASK 0x0000ffff
#define ROCKER_GROUP_INDEX_LONG_SHIFT 0
#define ROCKER_GROUP_INDEX_LONG_MASK 0x0fffffff

#define ROCKER_GROUP_TYPE_GET(group_id) \
	(((group_id) & ROCKER_GROUP_TYPE_MASK) >> ROCKER_GROUP_TYPE_SHIFT)
#define ROCKER_GROUP_TYPE_SET(type) \
	(((type) << ROCKER_GROUP_TYPE_SHIFT) & ROCKER_GROUP_TYPE_MASK)
#define ROCKER_GROUP_VLAN_GET(group_id) \
	(((group_id) & ROCKER_GROUP_VLAN_ID_MASK) >> ROCKER_GROUP_VLAN_ID_SHIFT)
#define ROCKER_GROUP_VLAN_SET(vlan_id) \
	(((vlan_id) << ROCKER_GROUP_VLAN_SHIFT) & ROCKER_GROUP_VLAN_MASK)
#define ROCKER_GROUP_PORT_GET(group_id) \
	(((group_id) & ROCKER_GROUP_PORT_MASK) >> ROCKER_GROUP_PORT_SHIFT)
#define ROCKER_GROUP_PORT_SET(port) \
	(((port) << ROCKER_GROUP_PORT_SHIFT) & ROCKER_GROUP_PORT_MASK)
#define ROCKER_GROUP_INDEX_GET(group_id) \
	(((group_id) & ROCKER_GROUP_INDEX_MASK) >> ROCKER_GROUP_INDEX_SHIFT)
#define ROCKER_GROUP_INDEX_SET(index) \
	(((index) << ROCKER_GROUP_INDEX_SHIFT) & ROCKER_GROUP_INDEX_MASK)
#define ROCKER_GROUP_INDEX_LONG_GET(group_id) \
	(((group_id) & ROCKER_GROUP_INDEX_LONG_MASK) >> \
	 ROCKER_GROUP_INDEX_LONG_SHIFT)
#define ROCKER_GROUP_INDEX_LONG_SET(index) \
	(((index) << ROCKER_GROUP_INDEX_LONG_SHIFT) & \
	 ROCKER_GROUP_INDEX_LONG_MASK)

#define ROCKER_GROUP_NONE 0
#define ROCKER_GROUP_L2_INTERFACE(vlan_id, port) \
	(ROCKER_GROUP_TYPE_SET(ROCKER_OF_DPA_GROUP_TYPE_L2_INTERFACE) |\
	 ROCKER_GROUP_VLAN_SET(ntohs(vlan_id)) | ROCKER_GROUP_PORT_SET(port))
#define ROCKER_GROUP_L2_REWRITE(index) \
	(ROCKER_GROUP_TYPE_SET(ROCKER_OF_DPA_GROUP_TYPE_L2_REWRITE) |\
	 ROCKER_GROUP_INDEX_LONG_SET(index))
#define ROCKER_GROUP_L2_MCAST(vlan_id, index) \
	(ROCKER_GROUP_TYPE_SET(ROCKER_OF_DPA_GROUP_TYPE_L2_MCAST) |\
	 ROCKER_GROUP_VLAN_SET(ntohs(vlan_id)) | ROCKER_GROUP_INDEX_SET(index))
#define ROCKER_GROUP_L2_FLOOD(vlan_id, index) \
	(ROCKER_GROUP_TYPE_SET(ROCKER_OF_DPA_GROUP_TYPE_L2_FLOOD) |\
	ROCKER_GROUP_VLAN_SET(ntohs(vlan_id)) | ROCKER_GROUP_INDEX_SET(index))
#define ROCKER_GROUP_L3_UNICAST(index) \
	(ROCKER_GROUP_TYPE_SET(ROCKER_OF_DPA_GROUP_TYPE_L3_UCAST) |\
	 ROCKER_GROUP_INDEX_LONG_SET(index))

/* Rocker general purpose registers */
#define ROCKER_CONTROL			0x0300
#define ROCKER_PORT_PHYS_COUNT		0x0304
#define ROCKER_PORT_PHYS_LINK_STATUS	0x0310 /* 8-byte */
#define ROCKER_PORT_PHYS_ENABLE		0x0318 /* 8-byte */
#define ROCKER_SWITCH_ID		0x0320 /* 8-byte */

/* Rocker control bits */
#define ROCKER_CONTROL_RESET		(1 << 0)

#endif
Commit	Line	Data
4b8ac966 JP	1	/*
	2	* drivers/net/ethernet/rocker/rocker.h - Rocker switch device driver
	3	* Copyright (c) 2014 Jiri Pirko <jiri@resnulli.us>
	4	* Copyright (c) 2014 Scott Feldman <sfeldma@gmail.com>
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*/
	11
	12	#ifndef _ROCKER_H
	13	#define _ROCKER_H
	14
	15	#include <linux/types.h>
	16
7eb344f8 SF	17	/* Return codes */
	18	enum {
	19	ROCKER_OK = 0,
	20	ROCKER_ENOENT = 2,
	21	ROCKER_ENXIO = 6,
	22	ROCKER_ENOMEM = 12,
	23	ROCKER_EEXIST = 17,
	24	ROCKER_EINVAL = 22,
	25	ROCKER_EMSGSIZE = 90,
	26	ROCKER_ENOTSUP = 95,
	27	ROCKER_ENOBUFS = 105,
	28	};
	29
4b8ac966 JP	30	#define PCI_VENDOR_ID_REDHAT 0x1b36
	31	#define PCI_DEVICE_ID_REDHAT_ROCKER 0x0006
	32
	33	#define ROCKER_PCI_BAR0_SIZE 0x2000
	34
	35	/* MSI-X vectors */
	36	enum {
	37	ROCKER_MSIX_VEC_CMD,
	38	ROCKER_MSIX_VEC_EVENT,
	39	ROCKER_MSIX_VEC_TEST,
	40	ROCKER_MSIX_VEC_RESERVED0,
	41	__ROCKER_MSIX_VEC_TX,
	42	__ROCKER_MSIX_VEC_RX,
	43	#define ROCKER_MSIX_VEC_TX(port) \
	44	(__ROCKER_MSIX_VEC_TX + ((port) * 2))
	45	#define ROCKER_MSIX_VEC_RX(port) \
	46	(__ROCKER_MSIX_VEC_RX + ((port) * 2))
	47	#define ROCKER_MSIX_VEC_COUNT(portcnt) \
	48	(ROCKER_MSIX_VEC_RX((portcnt - 1)) + 1)
	49	};
	50
	51	/* Rocker bogus registers */
	52	#define ROCKER_BOGUS_REG0 0x0000
	53	#define ROCKER_BOGUS_REG1 0x0004
	54	#define ROCKER_BOGUS_REG2 0x0008
	55	#define ROCKER_BOGUS_REG3 0x000c
	56
	57	/* Rocker test registers */
	58	#define ROCKER_TEST_REG 0x0010
	59	#define ROCKER_TEST_REG64 0x0018 /* 8-byte */
	60	#define ROCKER_TEST_IRQ 0x0020
	61	#define ROCKER_TEST_DMA_ADDR 0x0028 /* 8-byte */
	62	#define ROCKER_TEST_DMA_SIZE 0x0030
	63	#define ROCKER_TEST_DMA_CTRL 0x0034
	64
	65	/* Rocker test register ctrl */
	66	#define ROCKER_TEST_DMA_CTRL_CLEAR (1 << 0)
	67	#define ROCKER_TEST_DMA_CTRL_FILL (1 << 1)
	68	#define ROCKER_TEST_DMA_CTRL_INVERT (1 << 2)
	69
	70	/* Rocker DMA ring register offsets */
	71	#define ROCKER_DMA_DESC_ADDR(x) (0x1000 + (x) * 32) /* 8-byte */
	72	#define ROCKER_DMA_DESC_SIZE(x) (0x1008 + (x) * 32)
	73	#define ROCKER_DMA_DESC_HEAD(x) (0x100c + (x) * 32)
	74	#define ROCKER_DMA_DESC_TAIL(x) (0x1010 + (x) * 32)
	75	#define ROCKER_DMA_DESC_CTRL(x) (0x1014 + (x) * 32)
	76	#define ROCKER_DMA_DESC_CREDITS(x) (0x1018 + (x) * 32)
	77	#define ROCKER_DMA_DESC_RES1(x) (0x101c + (x) * 32)
	78
	79	/* Rocker dma ctrl register bits */
	80	#define ROCKER_DMA_DESC_CTRL_RESET (1 << 0)
	81
	82	/* Rocker DMA ring types */
	83	enum rocker_dma_type {
	84	ROCKER_DMA_CMD,
	85	ROCKER_DMA_EVENT,
	86	__ROCKER_DMA_TX,
	87	__ROCKER_DMA_RX,
	88	#define ROCKER_DMA_TX(port) (__ROCKER_DMA_TX + (port) * 2)
	89	#define ROCKER_DMA_RX(port) (__ROCKER_DMA_RX + (port) * 2)
	90	};
	91
	92	/* Rocker DMA ring size limits and default sizes */
	93	#define ROCKER_DMA_SIZE_MIN 2ul
94	#define ROCKER_DMA_SIZE_MAX 65536ul
95	#define ROCKER_DMA_CMD_DEFAULT_SIZE 32ul
96	#define ROCKER_DMA_EVENT_DEFAULT_SIZE 32ul
97	#define ROCKER_DMA_TX_DEFAULT_SIZE 64ul
98	#define ROCKER_DMA_TX_DESC_SIZE 256
99	#define ROCKER_DMA_RX_DEFAULT_SIZE 64ul
100	#define ROCKER_DMA_RX_DESC_SIZE 256
101
102	/* Rocker DMA descriptor struct */
103	struct rocker_desc {
104	u64 buf_addr;
105	u64 cookie;
106	u16 buf_size;
107	u16 tlv_size;
108	u16 resv[5];
109	u16 comp_err;
110	};
111
112	#define ROCKER_DMA_DESC_COMP_ERR_GEN (1 << 15)
113
114	/* Rocker DMA TLV struct */
115	struct rocker_tlv {
116	u32 type;
117	u16 len;
118	};
119
120	/* TLVs */
121	enum {
122	ROCKER_TLV_CMD_UNSPEC,
123	ROCKER_TLV_CMD_TYPE, /* u16 */
124	ROCKER_TLV_CMD_INFO, /* nest */
125
126	__ROCKER_TLV_CMD_MAX,
127	ROCKER_TLV_CMD_MAX = __ROCKER_TLV_CMD_MAX - 1,
128	};
129
130	enum {
131	ROCKER_TLV_CMD_TYPE_UNSPEC,
132	ROCKER_TLV_CMD_TYPE_GET_PORT_SETTINGS,
133	ROCKER_TLV_CMD_TYPE_SET_PORT_SETTINGS,
134	ROCKER_TLV_CMD_TYPE_OF_DPA_FLOW_ADD,
135	ROCKER_TLV_CMD_TYPE_OF_DPA_FLOW_MOD,
136	ROCKER_TLV_CMD_TYPE_OF_DPA_FLOW_DEL,
137	ROCKER_TLV_CMD_TYPE_OF_DPA_FLOW_GET_STATS,
138	ROCKER_TLV_CMD_TYPE_OF_DPA_GROUP_ADD,
139	ROCKER_TLV_CMD_TYPE_OF_DPA_GROUP_MOD,
140	ROCKER_TLV_CMD_TYPE_OF_DPA_GROUP_DEL,
141	ROCKER_TLV_CMD_TYPE_OF_DPA_GROUP_GET_STATS,
142
9766e97a DA	143	ROCKER_TLV_CMD_TYPE_CLEAR_PORT_STATS,
	144	ROCKER_TLV_CMD_TYPE_GET_PORT_STATS,
	145
4b8ac966 JP	146	__ROCKER_TLV_CMD_TYPE_MAX,
	147	ROCKER_TLV_CMD_TYPE_MAX = __ROCKER_TLV_CMD_TYPE_MAX - 1,
	148	};
	149
	150	enum {
	151	ROCKER_TLV_CMD_PORT_SETTINGS_UNSPEC,
	152	ROCKER_TLV_CMD_PORT_SETTINGS_LPORT, /* u32 */
	153	ROCKER_TLV_CMD_PORT_SETTINGS_SPEED, /* u32 */
	154	ROCKER_TLV_CMD_PORT_SETTINGS_DUPLEX, /* u8 */
	155	ROCKER_TLV_CMD_PORT_SETTINGS_AUTONEG, /* u8 */
	156	ROCKER_TLV_CMD_PORT_SETTINGS_MACADDR, /* binary */
	157	ROCKER_TLV_CMD_PORT_SETTINGS_MODE, /* u8 */
5111f80c	158	ROCKER_TLV_CMD_PORT_SETTINGS_LEARNING, /* u8 */
4b8ac966 JP	159
	160	__ROCKER_TLV_CMD_PORT_SETTINGS_MAX,
	161	ROCKER_TLV_CMD_PORT_SETTINGS_MAX =
	162	__ROCKER_TLV_CMD_PORT_SETTINGS_MAX - 1,
	163	};
	164
9766e97a DA	165	enum {
	166	ROCKER_TLV_CMD_PORT_STATS_UNSPEC,
	167	ROCKER_TLV_CMD_PORT_STATS_LPORT, /* u32 */
	168
	169	ROCKER_TLV_CMD_PORT_STATS_RX_PKTS, /* u64 */
	170	ROCKER_TLV_CMD_PORT_STATS_RX_BYTES, /* u64 */
	171	ROCKER_TLV_CMD_PORT_STATS_RX_DROPPED, /* u64 */
	172	ROCKER_TLV_CMD_PORT_STATS_RX_ERRORS, /* u64 */
	173
	174	ROCKER_TLV_CMD_PORT_STATS_TX_PKTS, /* u64 */
	175	ROCKER_TLV_CMD_PORT_STATS_TX_BYTES, /* u64 */
	176	ROCKER_TLV_CMD_PORT_STATS_TX_DROPPED, /* u64 */
	177	ROCKER_TLV_CMD_PORT_STATS_TX_ERRORS, /* u64 */
	178
	179	__ROCKER_TLV_CMD_PORT_STATS_MAX,
	180	ROCKER_TLV_CMD_PORT_STATS_MAX = __ROCKER_TLV_CMD_PORT_STATS_MAX - 1,
	181	};
	182
4b8ac966 JP	183	enum rocker_port_mode {
	184	ROCKER_PORT_MODE_OF_DPA,
	185	};
	186
	187	enum {
	188	ROCKER_TLV_EVENT_UNSPEC,
	189	ROCKER_TLV_EVENT_TYPE, /* u16 */
	190	ROCKER_TLV_EVENT_INFO, /* nest */
	191
	192	__ROCKER_TLV_EVENT_MAX,
	193	ROCKER_TLV_EVENT_MAX = __ROCKER_TLV_EVENT_MAX - 1,
	194	};
	195
	196	enum {
	197	ROCKER_TLV_EVENT_TYPE_UNSPEC,
	198	ROCKER_TLV_EVENT_TYPE_LINK_CHANGED,
	199	ROCKER_TLV_EVENT_TYPE_MAC_VLAN_SEEN,
	200
	201	__ROCKER_TLV_EVENT_TYPE_MAX,
	202	ROCKER_TLV_EVENT_TYPE_MAX = __ROCKER_TLV_EVENT_TYPE_MAX - 1,
	203	};
	204
	205	enum {
	206	ROCKER_TLV_EVENT_LINK_CHANGED_UNSPEC,
	207	ROCKER_TLV_EVENT_LINK_CHANGED_LPORT, /* u32 */
	208	ROCKER_TLV_EVENT_LINK_CHANGED_LINKUP, /* u8 */
	209
	210	__ROCKER_TLV_EVENT_LINK_CHANGED_MAX,
	211	ROCKER_TLV_EVENT_LINK_CHANGED_MAX =
	212	__ROCKER_TLV_EVENT_LINK_CHANGED_MAX - 1,
	213	};
	214
	215	enum {
	216	ROCKER_TLV_EVENT_MAC_VLAN_UNSPEC,
	217	ROCKER_TLV_EVENT_MAC_VLAN_LPORT, /* u32 */
	218	ROCKER_TLV_EVENT_MAC_VLAN_MAC, /* binary */
	219	ROCKER_TLV_EVENT_MAC_VLAN_VLAN_ID, /* __be16 */
	220
	221	__ROCKER_TLV_EVENT_MAC_VLAN_MAX,
	222	ROCKER_TLV_EVENT_MAC_VLAN_MAX = __ROCKER_TLV_EVENT_MAC_VLAN_MAX - 1,
	223	};
	224
	225	enum {
	226	ROCKER_TLV_RX_UNSPEC,
	227	ROCKER_TLV_RX_FLAGS, /* u16, see ROCKER_RX_FLAGS_ */
	228	ROCKER_TLV_RX_CSUM, /* u16 */
	229	ROCKER_TLV_RX_FRAG_ADDR, /* u64 */
	230	ROCKER_TLV_RX_FRAG_MAX_LEN, /* u16 */
	231	ROCKER_TLV_RX_FRAG_LEN, /* u16 */
	232
	233	__ROCKER_TLV_RX_MAX,
	234	ROCKER_TLV_RX_MAX = __ROCKER_TLV_RX_MAX - 1,
	235	};
	236
	237	#define ROCKER_RX_FLAGS_IPV4 (1 << 0)
	238	#define ROCKER_RX_FLAGS_IPV6 (1 << 1)
	239	#define ROCKER_RX_FLAGS_CSUM_CALC (1 << 2)
	240	#define ROCKER_RX_FLAGS_IPV4_CSUM_GOOD (1 << 3)
	241	#define ROCKER_RX_FLAGS_IP_FRAG (1 << 4)
	242	#define ROCKER_RX_FLAGS_TCP (1 << 5)
	243	#define ROCKER_RX_FLAGS_UDP (1 << 6)
	244	#define ROCKER_RX_FLAGS_TCP_UDP_CSUM_GOOD (1 << 7)
	245
	246	enum {
247	ROCKER_TLV_TX_UNSPEC,
248	ROCKER_TLV_TX_OFFLOAD, /* u8, see ROCKER_TX_OFFLOAD_ */
249	ROCKER_TLV_TX_L3_CSUM_OFF, /* u16 */
250	ROCKER_TLV_TX_TSO_MSS, /* u16 */
251	ROCKER_TLV_TX_TSO_HDR_LEN, /* u16 */
252	ROCKER_TLV_TX_FRAGS, /* array */
253
254	__ROCKER_TLV_TX_MAX,
255	ROCKER_TLV_TX_MAX = __ROCKER_TLV_TX_MAX - 1,
256	};
257
258	#define ROCKER_TX_OFFLOAD_NONE 0
259	#define ROCKER_TX_OFFLOAD_IP_CSUM 1
260	#define ROCKER_TX_OFFLOAD_TCP_UDP_CSUM 2
261	#define ROCKER_TX_OFFLOAD_L3_CSUM 3
262	#define ROCKER_TX_OFFLOAD_TSO 4
263
264	#define ROCKER_TX_FRAGS_MAX 16
265
266	enum {
267	ROCKER_TLV_TX_FRAG_UNSPEC,
268	ROCKER_TLV_TX_FRAG, /* nest */
269
270	__ROCKER_TLV_TX_FRAG_MAX,
271	ROCKER_TLV_TX_FRAG_MAX = __ROCKER_TLV_TX_FRAG_MAX - 1,
272	};
273
274	enum {
275	ROCKER_TLV_TX_FRAG_ATTR_UNSPEC,
276	ROCKER_TLV_TX_FRAG_ATTR_ADDR, /* u64 */
277	ROCKER_TLV_TX_FRAG_ATTR_LEN, /* u16 */
278
279	__ROCKER_TLV_TX_FRAG_ATTR_MAX,
280	ROCKER_TLV_TX_FRAG_ATTR_MAX = __ROCKER_TLV_TX_FRAG_ATTR_MAX - 1,
281	};
282
283	/* cmd info nested for OF-DPA msgs */
284	enum {
285	ROCKER_TLV_OF_DPA_UNSPEC,
286	ROCKER_TLV_OF_DPA_TABLE_ID, /* u16 */
287	ROCKER_TLV_OF_DPA_PRIORITY, /* u32 */
288	ROCKER_TLV_OF_DPA_HARDTIME, /* u32 */
289	ROCKER_TLV_OF_DPA_IDLETIME, /* u32 */
290	ROCKER_TLV_OF_DPA_COOKIE, /* u64 */
291	ROCKER_TLV_OF_DPA_IN_LPORT, /* u32 */
292	ROCKER_TLV_OF_DPA_IN_LPORT_MASK, /* u32 */
293	ROCKER_TLV_OF_DPA_OUT_LPORT, /* u32 */
294	ROCKER_TLV_OF_DPA_GOTO_TABLE_ID, /* u16 */
295	ROCKER_TLV_OF_DPA_GROUP_ID, /* u32 */
296	ROCKER_TLV_OF_DPA_GROUP_ID_LOWER, /* u32 */
297	ROCKER_TLV_OF_DPA_GROUP_COUNT, /* u16 */
298	ROCKER_TLV_OF_DPA_GROUP_IDS, /* u32 array */
299	ROCKER_TLV_OF_DPA_VLAN_ID, /* __be16 */
300	ROCKER_TLV_OF_DPA_VLAN_ID_MASK, /* __be16 */
301	ROCKER_TLV_OF_DPA_VLAN_PCP, /* __be16 */
302	ROCKER_TLV_OF_DPA_VLAN_PCP_MASK, /* __be16 */
303	ROCKER_TLV_OF_DPA_VLAN_PCP_ACTION, /* u8 */
304	ROCKER_TLV_OF_DPA_NEW_VLAN_ID, /* __be16 */
305	ROCKER_TLV_OF_DPA_NEW_VLAN_PCP, /* u8 */
306	ROCKER_TLV_OF_DPA_TUNNEL_ID, /* u32 */
307	ROCKER_TLV_OF_DPA_TUN_LOG_LPORT, /* u32 */
308	ROCKER_TLV_OF_DPA_ETHERTYPE, /* __be16 */
309	ROCKER_TLV_OF_DPA_DST_MAC, /* binary */
310	ROCKER_TLV_OF_DPA_DST_MAC_MASK, /* binary */
311	ROCKER_TLV_OF_DPA_SRC_MAC, /* binary */
312	ROCKER_TLV_OF_DPA_SRC_MAC_MASK, /* binary */
313	ROCKER_TLV_OF_DPA_IP_PROTO, /* u8 */
314	ROCKER_TLV_OF_DPA_IP_PROTO_MASK, /* u8 */
315	ROCKER_TLV_OF_DPA_IP_DSCP, /* u8 */
316	ROCKER_TLV_OF_DPA_IP_DSCP_MASK, /* u8 */
317	ROCKER_TLV_OF_DPA_IP_DSCP_ACTION, /* u8 */
318	ROCKER_TLV_OF_DPA_NEW_IP_DSCP, /* u8 */
319	ROCKER_TLV_OF_DPA_IP_ECN, /* u8 */
320	ROCKER_TLV_OF_DPA_IP_ECN_MASK, /* u8 */
321	ROCKER_TLV_OF_DPA_DST_IP, /* __be32 */
322	ROCKER_TLV_OF_DPA_DST_IP_MASK, /* __be32 */
323	ROCKER_TLV_OF_DPA_SRC_IP, /* __be32 */
324	ROCKER_TLV_OF_DPA_SRC_IP_MASK, /* __be32 */
325	ROCKER_TLV_OF_DPA_DST_IPV6, /* binary */
326	ROCKER_TLV_OF_DPA_DST_IPV6_MASK, /* binary */
327	ROCKER_TLV_OF_DPA_SRC_IPV6, /* binary */
328	ROCKER_TLV_OF_DPA_SRC_IPV6_MASK, /* binary */
329	ROCKER_TLV_OF_DPA_SRC_ARP_IP, /* __be32 */
330	ROCKER_TLV_OF_DPA_SRC_ARP_IP_MASK, /* __be32 */
331	ROCKER_TLV_OF_DPA_L4_DST_PORT, /* __be16 */
332	ROCKER_TLV_OF_DPA_L4_DST_PORT_MASK, /* __be16 */
333	ROCKER_TLV_OF_DPA_L4_SRC_PORT, /* __be16 */
334	ROCKER_TLV_OF_DPA_L4_SRC_PORT_MASK, /* __be16 */
335	ROCKER_TLV_OF_DPA_ICMP_TYPE, /* u8 */
336	ROCKER_TLV_OF_DPA_ICMP_TYPE_MASK, /* u8 */
337	ROCKER_TLV_OF_DPA_ICMP_CODE, /* u8 */
338	ROCKER_TLV_OF_DPA_ICMP_CODE_MASK, /* u8 */
339	ROCKER_TLV_OF_DPA_IPV6_LABEL, /* __be32 */
340	ROCKER_TLV_OF_DPA_IPV6_LABEL_MASK, /* __be32 */
341	ROCKER_TLV_OF_DPA_QUEUE_ID_ACTION, /* u8 */
342	ROCKER_TLV_OF_DPA_NEW_QUEUE_ID, /* u8 */
343	ROCKER_TLV_OF_DPA_CLEAR_ACTIONS, /* u32 */
344	ROCKER_TLV_OF_DPA_POP_VLAN, /* u8 */
345	ROCKER_TLV_OF_DPA_TTL_CHECK, /* u8 */
346	ROCKER_TLV_OF_DPA_COPY_CPU_ACTION, /* u8 */
347
348	__ROCKER_TLV_OF_DPA_MAX,
349	ROCKER_TLV_OF_DPA_MAX = __ROCKER_TLV_OF_DPA_MAX - 1,
350	};
351
352	/* OF-DPA table IDs */
353
354	enum rocker_of_dpa_table_id {
355	ROCKER_OF_DPA_TABLE_ID_INGRESS_PORT = 0,
356	ROCKER_OF_DPA_TABLE_ID_VLAN = 10,
357	ROCKER_OF_DPA_TABLE_ID_TERMINATION_MAC = 20,
358	ROCKER_OF_DPA_TABLE_ID_UNICAST_ROUTING = 30,
359	ROCKER_OF_DPA_TABLE_ID_MULTICAST_ROUTING = 40,
360	ROCKER_OF_DPA_TABLE_ID_BRIDGING = 50,
361	ROCKER_OF_DPA_TABLE_ID_ACL_POLICY = 60,
362	};
363
364	/* OF-DPA flow stats */
365	enum {
366	ROCKER_TLV_OF_DPA_FLOW_STAT_UNSPEC,
367	ROCKER_TLV_OF_DPA_FLOW_STAT_DURATION, /* u32 */
368	ROCKER_TLV_OF_DPA_FLOW_STAT_RX_PKTS, /* u64 */
369	ROCKER_TLV_OF_DPA_FLOW_STAT_TX_PKTS, /* u64 */
370
371	__ROCKER_TLV_OF_DPA_FLOW_STAT_MAX,
372	ROCKER_TLV_OF_DPA_FLOW_STAT_MAX = __ROCKER_TLV_OF_DPA_FLOW_STAT_MAX - 1,
373	};
374
375	/* OF-DPA group types */
376	enum rocker_of_dpa_group_type {
377	ROCKER_OF_DPA_GROUP_TYPE_L2_INTERFACE = 0,
378	ROCKER_OF_DPA_GROUP_TYPE_L2_REWRITE,
379	ROCKER_OF_DPA_GROUP_TYPE_L3_UCAST,
380	ROCKER_OF_DPA_GROUP_TYPE_L2_MCAST,
381	ROCKER_OF_DPA_GROUP_TYPE_L2_FLOOD,
382	ROCKER_OF_DPA_GROUP_TYPE_L3_INTERFACE,
383	ROCKER_OF_DPA_GROUP_TYPE_L3_MCAST,
384	ROCKER_OF_DPA_GROUP_TYPE_L3_ECMP,
385	ROCKER_OF_DPA_GROUP_TYPE_L2_OVERLAY,
386	};
387
388	/* OF-DPA group L2 overlay types */
389	enum rocker_of_dpa_overlay_type {
390	ROCKER_OF_DPA_OVERLAY_TYPE_FLOOD_UCAST = 0,
391	ROCKER_OF_DPA_OVERLAY_TYPE_FLOOD_MCAST,
392	ROCKER_OF_DPA_OVERLAY_TYPE_MCAST_UCAST,
393	ROCKER_OF_DPA_OVERLAY_TYPE_MCAST_MCAST,
394	};
395
396	/* OF-DPA group ID encoding */
397	#define ROCKER_GROUP_TYPE_SHIFT 28
398	#define ROCKER_GROUP_TYPE_MASK 0xf0000000
399	#define ROCKER_GROUP_VLAN_SHIFT 16
400	#define ROCKER_GROUP_VLAN_MASK 0x0fff0000
401	#define ROCKER_GROUP_PORT_SHIFT 0
402	#define ROCKER_GROUP_PORT_MASK 0x0000ffff
403	#define ROCKER_GROUP_TUNNEL_ID_SHIFT 12
404	#define ROCKER_GROUP_TUNNEL_ID_MASK 0x0ffff000
405	#define ROCKER_GROUP_SUBTYPE_SHIFT 10
406	#define ROCKER_GROUP_SUBTYPE_MASK 0x00000c00
407	#define ROCKER_GROUP_INDEX_SHIFT 0
408	#define ROCKER_GROUP_INDEX_MASK 0x0000ffff
409	#define ROCKER_GROUP_INDEX_LONG_SHIFT 0
410	#define ROCKER_GROUP_INDEX_LONG_MASK 0x0fffffff
411
412	#define ROCKER_GROUP_TYPE_GET(group_id) \
413	(((group_id) & ROCKER_GROUP_TYPE_MASK) >> ROCKER_GROUP_TYPE_SHIFT)
414	#define ROCKER_GROUP_TYPE_SET(type) \
415	(((type) << ROCKER_GROUP_TYPE_SHIFT) & ROCKER_GROUP_TYPE_MASK)
416	#define ROCKER_GROUP_VLAN_GET(group_id) \
417	(((group_id) & ROCKER_GROUP_VLAN_ID_MASK) >> ROCKER_GROUP_VLAN_ID_SHIFT)
418	#define ROCKER_GROUP_VLAN_SET(vlan_id) \
419	(((vlan_id) << ROCKER_GROUP_VLAN_SHIFT) & ROCKER_GROUP_VLAN_MASK)
420	#define ROCKER_GROUP_PORT_GET(group_id) \
421	(((group_id) & ROCKER_GROUP_PORT_MASK) >> ROCKER_GROUP_PORT_SHIFT)
422	#define ROCKER_GROUP_PORT_SET(port) \
423	(((port) << ROCKER_GROUP_PORT_SHIFT) & ROCKER_GROUP_PORT_MASK)
424	#define ROCKER_GROUP_INDEX_GET(group_id) \
425	(((group_id) & ROCKER_GROUP_INDEX_MASK) >> ROCKER_GROUP_INDEX_SHIFT)
426	#define ROCKER_GROUP_INDEX_SET(index) \
427	(((index) << ROCKER_GROUP_INDEX_SHIFT) & ROCKER_GROUP_INDEX_MASK)
428	#define ROCKER_GROUP_INDEX_LONG_GET(group_id) \
429	(((group_id) & ROCKER_GROUP_INDEX_LONG_MASK) >> \
430	ROCKER_GROUP_INDEX_LONG_SHIFT)
431	#define ROCKER_GROUP_INDEX_LONG_SET(index) \
432	(((index) << ROCKER_GROUP_INDEX_LONG_SHIFT) & \
433	ROCKER_GROUP_INDEX_LONG_MASK)
434
435	#define ROCKER_GROUP_NONE 0
436	#define ROCKER_GROUP_L2_INTERFACE(vlan_id, port) \
437	(ROCKER_GROUP_TYPE_SET(ROCKER_OF_DPA_GROUP_TYPE_L2_INTERFACE) \|\
438	ROCKER_GROUP_VLAN_SET(ntohs(vlan_id)) \| ROCKER_GROUP_PORT_SET(port))
439	#define ROCKER_GROUP_L2_REWRITE(index) \
440	(ROCKER_GROUP_TYPE_SET(ROCKER_OF_DPA_GROUP_TYPE_L2_REWRITE) \|\
441	ROCKER_GROUP_INDEX_LONG_SET(index))
442	#define ROCKER_GROUP_L2_MCAST(vlan_id, index) \
443	(ROCKER_GROUP_TYPE_SET(ROCKER_OF_DPA_GROUP_TYPE_L2_MCAST) \|\
444	ROCKER_GROUP_VLAN_SET(ntohs(vlan_id)) \| ROCKER_GROUP_INDEX_SET(index))
445	#define ROCKER_GROUP_L2_FLOOD(vlan_id, index) \
446	(ROCKER_GROUP_TYPE_SET(ROCKER_OF_DPA_GROUP_TYPE_L2_FLOOD) \|\
447	ROCKER_GROUP_VLAN_SET(ntohs(vlan_id)) \| ROCKER_GROUP_INDEX_SET(index))
448	#define ROCKER_GROUP_L3_UNICAST(index) \
449	(ROCKER_GROUP_TYPE_SET(ROCKER_OF_DPA_GROUP_TYPE_L3_UCAST) \|\
450	ROCKER_GROUP_INDEX_LONG_SET(index))
451
452	/* Rocker general purpose registers */
453	#define ROCKER_CONTROL 0x0300
454	#define ROCKER_PORT_PHYS_COUNT 0x0304
455	#define ROCKER_PORT_PHYS_LINK_STATUS 0x0310 /* 8-byte */
456	#define ROCKER_PORT_PHYS_ENABLE 0x0318 /* 8-byte */
457	#define ROCKER_SWITCH_ID 0x0320 /* 8-byte */
458
459	/* Rocker control bits */
460	#define ROCKER_CONTROL_RESET (1 << 0)
461
462	#endif