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sfc: make mem_bar a function rather than a constant
[mirror_ubuntu-focal-kernel.git] / drivers / net / ethernet / sfc / ef10.c
CommitLineData
8127d661
BH		 1/****************************************************************************
2 * Driver for Solarflare network controllers and boards
3 * Copyright 2012-2013 Solarflare Communications Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published
7 * by the Free Software Foundation, incorporated herein by reference.
8 */
9
10#include "net_driver.h"
11#include "ef10_regs.h"
12#include "io.h"
13#include "mcdi.h"
14#include "mcdi_pcol.h"
15#include "nic.h"
16#include "workarounds.h"
74cd60a4 17#include "selftest.h"
7fa8d547 18#include "ef10_sriov.h"
8127d661
BH		 19#include <linux/in.h>
20#include <linux/jhash.h>
21#include <linux/wait.h>
22#include <linux/workqueue.h>
23
24/* Hardware control for EF10 architecture including 'Huntington'. */
25
26#define EFX_EF10_DRVGEN_EV 7
27enum {
28 EFX_EF10_TEST = 1,
29 EFX_EF10_REFILL,
30};
31
32/* The reserved RSS context value */
33#define EFX_EF10_RSS_CONTEXT_INVALID 0xffffffff
267c0157
JC		 34/* The maximum size of a shared RSS context */
35/* TODO: this should really be from the mcdi protocol export */
36#define EFX_EF10_MAX_SHARED_RSS_CONTEXT_SIZE 64UL
8127d661
BH		 37
38/* The filter table(s) are managed by firmware and we have write-only
39 * access. When removing filters we must identify them to the
40 * firmware by a 64-bit handle, but this is too wide for Linux kernel
41 * interfaces (32-bit for RX NFC, 16-bit for RFS). Also, we need to
42 * be able to tell in advance whether a requested insertion will
43 * replace an existing filter. Therefore we maintain a software hash
44 * table, which should be at least as large as the hardware hash
45 * table.
46 *
47 * Huntington has a single 8K filter table shared between all filter
48 * types and both ports.
49 */
50#define HUNT_FILTER_TBL_ROWS 8192
51
12fb0da4 52#define EFX_EF10_FILTER_ID_INVALID 0xffff
dc3273e0
AR		 53
54#define EFX_EF10_FILTER_DEV_UC_MAX 32
55#define EFX_EF10_FILTER_DEV_MC_MAX 256
56
34813fe2
AR		 57/* VLAN list entry */
58struct efx_ef10_vlan {
59 struct list_head list;
60 u16 vid;
61};
62
9b410801
EC		 63enum efx_ef10_default_filters {
64 EFX_EF10_BCAST,
65 EFX_EF10_UCDEF,
66 EFX_EF10_MCDEF,
67 EFX_EF10_VXLAN4_UCDEF,
68 EFX_EF10_VXLAN4_MCDEF,
69 EFX_EF10_VXLAN6_UCDEF,
70 EFX_EF10_VXLAN6_MCDEF,
71 EFX_EF10_NVGRE4_UCDEF,
72 EFX_EF10_NVGRE4_MCDEF,
73 EFX_EF10_NVGRE6_UCDEF,
74 EFX_EF10_NVGRE6_MCDEF,
75 EFX_EF10_GENEVE4_UCDEF,
76 EFX_EF10_GENEVE4_MCDEF,
77 EFX_EF10_GENEVE6_UCDEF,
78 EFX_EF10_GENEVE6_MCDEF,
79
80 EFX_EF10_NUM_DEFAULT_FILTERS
81};
82
dc3273e0
AR		 83/* Per-VLAN filters information */
84struct efx_ef10_filter_vlan {
34813fe2 85 struct list_head list;
b3a3c03c 86 u16 vid;
dc3273e0
AR		 87 u16 uc[EFX_EF10_FILTER_DEV_UC_MAX];
88 u16 mc[EFX_EF10_FILTER_DEV_MC_MAX];
9b410801 89 u16 default_filters[EFX_EF10_NUM_DEFAULT_FILTERS];
dc3273e0
AR		 90};
91
822b96f8
DP		 92struct efx_ef10_dev_addr {
93 u8 addr[ETH_ALEN];
822b96f8
DP		 94};
95
8127d661 96struct efx_ef10_filter_table {
7ac0dd9d
AR		 97/* The MCDI match masks supported by this fw & hw, in order of priority */
98 u32 rx_match_mcdi_flags[
9b410801 99 MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM * 2];
8127d661
BH		 100 unsigned int rx_match_count;
101
102 struct {
103 unsigned long spec; /* pointer to spec plus flag bits */
b59e6ef8
BH		 104/* BUSY flag indicates that an update is in progress. AUTO_OLD is
105 * used to mark and sweep MAC filters for the device address lists.
8127d661
BH		 106 */
107#define EFX_EF10_FILTER_FLAG_BUSY 1UL
b59e6ef8 108#define EFX_EF10_FILTER_FLAG_AUTO_OLD 2UL
8127d661
BH		 109#define EFX_EF10_FILTER_FLAGS 3UL
110 u64 handle; /* firmware handle */
111 } *entry;
112 wait_queue_head_t waitq;
113/* Shadow of net_device address lists, guarded by mac_lock */
822b96f8
DP		 114 struct efx_ef10_dev_addr dev_uc_list[EFX_EF10_FILTER_DEV_UC_MAX];
115 struct efx_ef10_dev_addr dev_mc_list[EFX_EF10_FILTER_DEV_MC_MAX];
12fb0da4
EC		 116 int dev_uc_count;
117 int dev_mc_count;
afa4ce12
AR		 118 bool uc_promisc;
119 bool mc_promisc;
b071c3a2
AR		 120/* Whether in multicast promiscuous mode when last changed */
121 bool mc_promisc_last;
148cbab6 122 bool mc_overflow; /* Too many MC addrs; should always imply mc_promisc */
4a53ea8a 123 bool vlan_filter;
34813fe2 124 struct list_head vlan_list;
8127d661
BH		 125};
126
127/* An arbitrary search limit for the software hash table */
128#define EFX_EF10_FILTER_SEARCH_LIMIT 200
129
8127d661
BH		 130static void efx_ef10_rx_free_indir_table(struct efx_nic *efx);
131static void efx_ef10_filter_table_remove(struct efx_nic *efx);
34813fe2
AR		 132static int efx_ef10_filter_add_vlan(struct efx_nic *efx, u16 vid);
133static void efx_ef10_filter_del_vlan_internal(struct efx_nic *efx,
134 struct efx_ef10_filter_vlan *vlan);
135static void efx_ef10_filter_del_vlan(struct efx_nic *efx, u16 vid);
e5fbd977 136static int efx_ef10_set_udp_tnl_ports(struct efx_nic *efx, bool unloading);
8127d661 137
0ccb998b
JC		 138static u32 efx_ef10_filter_get_unsafe_id(u32 filter_id)
139{
140 WARN_ON_ONCE(filter_id == EFX_EF10_FILTER_ID_INVALID);
141 return filter_id & (HUNT_FILTER_TBL_ROWS - 1);
142}
143
144static unsigned int efx_ef10_filter_get_unsafe_pri(u32 filter_id)
145{
146 return filter_id / (HUNT_FILTER_TBL_ROWS * 2);
147}
148
149static u32 efx_ef10_make_filter_id(unsigned int pri, u16 idx)
150{
151 return pri * HUNT_FILTER_TBL_ROWS * 2 + idx;
152}
153
8127d661
BH		 154static int efx_ef10_get_warm_boot_count(struct efx_nic *efx)
155{
156 efx_dword_t reg;
157
158 efx_readd(efx, &reg, ER_DZ_BIU_MC_SFT_STATUS);
159 return EFX_DWORD_FIELD(reg, EFX_WORD_1) == 0xb007 ?
160 EFX_DWORD_FIELD(reg, EFX_WORD_0) : -EIO;
161}
162
03714bbb
EC		 163/* On all EF10s up to and including SFC9220 (Medford1), all PFs use BAR 0 for
164 * I/O space and BAR 2(&3) for memory. On SFC9250 (Medford2), there is no I/O
165 * bar; PFs use BAR 0/1 for memory.
166 */
167static unsigned int efx_ef10_pf_mem_bar(struct efx_nic *efx)
168{
169 switch (efx->pci_dev->device) {
170 case 0x0b03: /* SFC9250 PF */
171 return 0;
172 default:
173 return 2;
174 }
175}
176
177/* All VFs use BAR 0/1 for memory */
178static unsigned int efx_ef10_vf_mem_bar(struct efx_nic *efx)
179{
180 return 0;
181}
182
8127d661
BH		 183static unsigned int efx_ef10_mem_map_size(struct efx_nic *efx)
184{
02246a7f
SS		 185 int bar;
186
03714bbb 187 bar = efx->type->mem_bar(efx);
02246a7f 188 return resource_size(&efx->pci_dev->resource[bar]);
8127d661
BH		 189}
190
7a186f47
DP		 191static bool efx_ef10_is_vf(struct efx_nic *efx)
192{
193 return efx->type->is_vf;
194}
195
1cd9ecbb
DP		 196static int efx_ef10_get_pf_index(struct efx_nic *efx)
197{
198 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN);
199 struct efx_ef10_nic_data *nic_data = efx->nic_data;
200 size_t outlen;
201 int rc;
202
203 rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf,
204 sizeof(outbuf), &outlen);
205 if (rc)
206 return rc;
207 if (outlen < sizeof(outbuf))
208 return -EIO;
209
210 nic_data->pf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_PF);
211 return 0;
212}
213
88a37de6
SS		 214#ifdef CONFIG_SFC_SRIOV
215static int efx_ef10_get_vf_index(struct efx_nic *efx)
216{
217 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN);
218 struct efx_ef10_nic_data *nic_data = efx->nic_data;
219 size_t outlen;
220 int rc;
221
222 rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf,
223 sizeof(outbuf), &outlen);
224 if (rc)
225 return rc;
226 if (outlen < sizeof(outbuf))
227 return -EIO;
228
229 nic_data->vf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_VF);
230 return 0;
231}
232#endif
233
e5a2538a 234static int efx_ef10_init_datapath_caps(struct efx_nic *efx)
8127d661 235{
ca889a05 236 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CAPABILITIES_V2_OUT_LEN);
8127d661
BH		 237 struct efx_ef10_nic_data *nic_data = efx->nic_data;
238 size_t outlen;
239 int rc;
240
241 BUILD_BUG_ON(MC_CMD_GET_CAPABILITIES_IN_LEN != 0);
242
243 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CAPABILITIES, NULL, 0,
244 outbuf, sizeof(outbuf), &outlen);
245 if (rc)
246 return rc;
ca889a05 247 if (outlen < MC_CMD_GET_CAPABILITIES_OUT_LEN) {
e5a2538a
BH		 248 netif_err(efx, drv, efx->net_dev,
249 "unable to read datapath firmware capabilities\n");
250 return -EIO;
251 }
252
253 nic_data->datapath_caps =
254 MCDI_DWORD(outbuf, GET_CAPABILITIES_OUT_FLAGS1);
8127d661 255
c634700f 256 if (outlen >= MC_CMD_GET_CAPABILITIES_V2_OUT_LEN) {
ca889a05
BK		 257 nic_data->datapath_caps2 = MCDI_DWORD(outbuf,
258 GET_CAPABILITIES_V2_OUT_FLAGS2);
c634700f
EC		 259 nic_data->piobuf_size = MCDI_WORD(outbuf,
260 GET_CAPABILITIES_V2_OUT_SIZE_PIO_BUFF);
261 } else {
ca889a05 262 nic_data->datapath_caps2 = 0;
c634700f
EC		 263 nic_data->piobuf_size = ER_DZ_TX_PIOBUF_SIZE;
264 }
ca889a05 265
8d9f9dd4
DP		 266 /* record the DPCPU firmware IDs to determine VEB vswitching support.
267 */
268 nic_data->rx_dpcpu_fw_id =
269 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID);
270 nic_data->tx_dpcpu_fw_id =
271 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID);
272
e5a2538a
BH		 273 if (!(nic_data->datapath_caps &
274 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN))) {
275 netif_err(efx, probe, efx->net_dev,
276 "current firmware does not support an RX prefix\n");
277 return -ENODEV;
8127d661
BH		 278 }
279
280 return 0;
281}
282
283static int efx_ef10_get_sysclk_freq(struct efx_nic *efx)
284{
285 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CLOCK_OUT_LEN);
286 int rc;
287
288 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CLOCK, NULL, 0,
289 outbuf, sizeof(outbuf), NULL);
290 if (rc)
291 return rc;
292 rc = MCDI_DWORD(outbuf, GET_CLOCK_OUT_SYS_FREQ);
293 return rc > 0 ? rc : -ERANGE;
294}
295
d95e329a
BK		 296static int efx_ef10_get_timer_workarounds(struct efx_nic *efx)
297{
298 struct efx_ef10_nic_data *nic_data = efx->nic_data;
299 unsigned int implemented;
300 unsigned int enabled;
301 int rc;
302
303 nic_data->workaround_35388 = false;
304 nic_data->workaround_61265 = false;
305
306 rc = efx_mcdi_get_workarounds(efx, &implemented, &enabled);
307
308 if (rc == -ENOSYS) {
309 /* Firmware without GET_WORKAROUNDS - not a problem. */
310 rc = 0;
311 } else if (rc == 0) {
312 /* Bug61265 workaround is always enabled if implemented. */
313 if (enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG61265)
314 nic_data->workaround_61265 = true;
315
316 if (enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG35388) {
317 nic_data->workaround_35388 = true;
318 } else if (implemented & MC_CMD_GET_WORKAROUNDS_OUT_BUG35388) {
319 /* Workaround is implemented but not enabled.
320 * Try to enable it.
321 */
322 rc = efx_mcdi_set_workaround(efx,
323 MC_CMD_WORKAROUND_BUG35388,
324 true, NULL);
325 if (rc == 0)
326 nic_data->workaround_35388 = true;
327 /* If we failed to set the workaround just carry on. */
328 rc = 0;
329 }
330 }
331
332 netif_dbg(efx, probe, efx->net_dev,
333 "workaround for bug 35388 is %sabled\n",
334 nic_data->workaround_35388 ? "en" : "dis");
335 netif_dbg(efx, probe, efx->net_dev,
336 "workaround for bug 61265 is %sabled\n",
337 nic_data->workaround_61265 ? "en" : "dis");
338
339 return rc;
340}
341
342static void efx_ef10_process_timer_config(struct efx_nic *efx,
343 const efx_dword_t *data)
344{
345 unsigned int max_count;
346
347 if (EFX_EF10_WORKAROUND_61265(efx)) {
348 efx->timer_quantum_ns = MCDI_DWORD(data,
349 GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_STEP_NS);
350 efx->timer_max_ns = MCDI_DWORD(data,
351 GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_MAX_NS);
352 } else if (EFX_EF10_WORKAROUND_35388(efx)) {
353 efx->timer_quantum_ns = MCDI_DWORD(data,
354 GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_NS_PER_COUNT);
355 max_count = MCDI_DWORD(data,
356 GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_MAX_COUNT);
357 efx->timer_max_ns = max_count * efx->timer_quantum_ns;
358 } else {
359 efx->timer_quantum_ns = MCDI_DWORD(data,
360 GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_NS_PER_COUNT);
361 max_count = MCDI_DWORD(data,
362 GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_MAX_COUNT);
363 efx->timer_max_ns = max_count * efx->timer_quantum_ns;
364 }
365
366 netif_dbg(efx, probe, efx->net_dev,
367 "got timer properties from MC: quantum %u ns; max %u ns\n",
368 efx->timer_quantum_ns, efx->timer_max_ns);
369}
370
371static int efx_ef10_get_timer_config(struct efx_nic *efx)
372{
373 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_LEN);
374 int rc;
375
376 rc = efx_ef10_get_timer_workarounds(efx);
377 if (rc)
378 return rc;
379
380 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_GET_EVQ_TMR_PROPERTIES, NULL, 0,
381 outbuf, sizeof(outbuf), NULL);
382
383 if (rc == 0) {
384 efx_ef10_process_timer_config(efx, outbuf);
385 } else if (rc == -ENOSYS || rc == -EPERM) {
386 /* Not available - fall back to Huntington defaults. */
387 unsigned int quantum;
388
389 rc = efx_ef10_get_sysclk_freq(efx);
390 if (rc < 0)
391 return rc;
392
393 quantum = 1536000 / rc; /* 1536 cycles */
394 efx->timer_quantum_ns = quantum;
395 efx->timer_max_ns = efx->type->timer_period_max * quantum;
396 rc = 0;
397 } else {
398 efx_mcdi_display_error(efx, MC_CMD_GET_EVQ_TMR_PROPERTIES,
399 MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_LEN,
400 NULL, 0, rc);
401 }
402
403 return rc;
404}
405
0d5e0fbb 406static int efx_ef10_get_mac_address_pf(struct efx_nic *efx, u8 *mac_address)
8127d661
BH		 407{
408 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_MAC_ADDRESSES_OUT_LEN);
409 size_t outlen;
410 int rc;
411
412 BUILD_BUG_ON(MC_CMD_GET_MAC_ADDRESSES_IN_LEN != 0);
413
414 rc = efx_mcdi_rpc(efx, MC_CMD_GET_MAC_ADDRESSES, NULL, 0,
415 outbuf, sizeof(outbuf), &outlen);
416 if (rc)
417 return rc;
418 if (outlen < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN)
419 return -EIO;
420
cd84ff4d
EC		 421 ether_addr_copy(mac_address,
422 MCDI_PTR(outbuf, GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE));
8127d661
BH		 423 return 0;
424}
425
0d5e0fbb
DP		 426static int efx_ef10_get_mac_address_vf(struct efx_nic *efx, u8 *mac_address)
427{
428 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN);
429 MCDI_DECLARE_BUF(outbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX);
430 size_t outlen;
431 int num_addrs, rc;
432
433 MCDI_SET_DWORD(inbuf, VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID,
434 EVB_PORT_ID_ASSIGNED);
435 rc = efx_mcdi_rpc(efx, MC_CMD_VPORT_GET_MAC_ADDRESSES, inbuf,
436 sizeof(inbuf), outbuf, sizeof(outbuf), &outlen);
437
438 if (rc)
439 return rc;
440 if (outlen < MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN)
441 return -EIO;
442
443 num_addrs = MCDI_DWORD(outbuf,
444 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT);
445
446 WARN_ON(num_addrs != 1);
447
448 ether_addr_copy(mac_address,
449 MCDI_PTR(outbuf, VPORT_GET_MAC_ADDRESSES_OUT_MACADDR));
450
451 return 0;
452}
453
0f5c0845
SS		 454static ssize_t efx_ef10_show_link_control_flag(struct device *dev,
455 struct device_attribute *attr,
456 char *buf)
457{
458 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
459
460 return sprintf(buf, "%d\n",
461 ((efx->mcdi->fn_flags) &
462 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL))
463 ? 1 : 0);
464}
465
466static ssize_t efx_ef10_show_primary_flag(struct device *dev,
467 struct device_attribute *attr,
468 char *buf)
469{
470 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
471
472 return sprintf(buf, "%d\n",
473 ((efx->mcdi->fn_flags) &
474 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY))
475 ? 1 : 0);
476}
477
34813fe2
AR		 478static struct efx_ef10_vlan *efx_ef10_find_vlan(struct efx_nic *efx, u16 vid)
479{
480 struct efx_ef10_nic_data *nic_data = efx->nic_data;
481 struct efx_ef10_vlan *vlan;
482
483 WARN_ON(!mutex_is_locked(&nic_data->vlan_lock));
484
485 list_for_each_entry(vlan, &nic_data->vlan_list, list) {
486 if (vlan->vid == vid)
487 return vlan;
488 }
489
490 return NULL;
491}
492
493static int efx_ef10_add_vlan(struct efx_nic *efx, u16 vid)
494{
495 struct efx_ef10_nic_data *nic_data = efx->nic_data;
496 struct efx_ef10_vlan *vlan;
497 int rc;
498
499 mutex_lock(&nic_data->vlan_lock);
500
501 vlan = efx_ef10_find_vlan(efx, vid);
502 if (vlan) {
4a53ea8a
AR		 503 /* We add VID 0 on init. 8021q adds it on module init
504 * for all interfaces with VLAN filtring feature.
505 */
506 if (vid == 0)
507 goto done_unlock;
34813fe2
AR		 508 netif_warn(efx, drv, efx->net_dev,
509 "VLAN %u already added\n", vid);
510 rc = -EALREADY;
511 goto fail_exist;
512 }
513
514 rc = -ENOMEM;
515 vlan = kzalloc(sizeof(*vlan), GFP_KERNEL);
516 if (!vlan)
517 goto fail_alloc;
518
519 vlan->vid = vid;
520
521 list_add_tail(&vlan->list, &nic_data->vlan_list);
522
523 if (efx->filter_state) {
524 mutex_lock(&efx->mac_lock);
525 down_write(&efx->filter_sem);
526 rc = efx_ef10_filter_add_vlan(efx, vlan->vid);
527 up_write(&efx->filter_sem);
528 mutex_unlock(&efx->mac_lock);
529 if (rc)
530 goto fail_filter_add_vlan;
531 }
532
4a53ea8a 533done_unlock:
34813fe2
AR		 534 mutex_unlock(&nic_data->vlan_lock);
535 return 0;
536
537fail_filter_add_vlan:
538 list_del(&vlan->list);
539 kfree(vlan);
540fail_alloc:
541fail_exist:
542 mutex_unlock(&nic_data->vlan_lock);
543 return rc;
544}
545
546static void efx_ef10_del_vlan_internal(struct efx_nic *efx,
547 struct efx_ef10_vlan *vlan)
548{
549 struct efx_ef10_nic_data *nic_data = efx->nic_data;
550
551 WARN_ON(!mutex_is_locked(&nic_data->vlan_lock));
552
553 if (efx->filter_state) {
554 down_write(&efx->filter_sem);
555 efx_ef10_filter_del_vlan(efx, vlan->vid);
556 up_write(&efx->filter_sem);
557 }
558
559 list_del(&vlan->list);
560 kfree(vlan);
561}
562
4a53ea8a
AR		 563static int efx_ef10_del_vlan(struct efx_nic *efx, u16 vid)
564{
565 struct efx_ef10_nic_data *nic_data = efx->nic_data;
566 struct efx_ef10_vlan *vlan;
567 int rc = 0;
568
569 /* 8021q removes VID 0 on module unload for all interfaces
570 * with VLAN filtering feature. We need to keep it to receive
571 * untagged traffic.
572 */
573 if (vid == 0)
574 return 0;
575
576 mutex_lock(&nic_data->vlan_lock);
577
578 vlan = efx_ef10_find_vlan(efx, vid);
579 if (!vlan) {
580 netif_err(efx, drv, efx->net_dev,
581 "VLAN %u to be deleted not found\n", vid);
582 rc = -ENOENT;
583 } else {
584 efx_ef10_del_vlan_internal(efx, vlan);
585 }
586
587 mutex_unlock(&nic_data->vlan_lock);
588
589 return rc;
590}
591
34813fe2
AR		 592static void efx_ef10_cleanup_vlans(struct efx_nic *efx)
593{
594 struct efx_ef10_nic_data *nic_data = efx->nic_data;
595 struct efx_ef10_vlan *vlan, *next_vlan;
596
597 mutex_lock(&nic_data->vlan_lock);
598 list_for_each_entry_safe(vlan, next_vlan, &nic_data->vlan_list, list)
599 efx_ef10_del_vlan_internal(efx, vlan);
600 mutex_unlock(&nic_data->vlan_lock);
601}
602
0f5c0845
SS		 603static DEVICE_ATTR(link_control_flag, 0444, efx_ef10_show_link_control_flag,
604 NULL);
605static DEVICE_ATTR(primary_flag, 0444, efx_ef10_show_primary_flag, NULL);
606
8127d661
BH		 607static int efx_ef10_probe(struct efx_nic *efx)
608{
609 struct efx_ef10_nic_data *nic_data;
610 int i, rc;
611
aa3930ee
BH		 612 /* We can have one VI for each 8K region. However, until we
613 * use TX option descriptors we need two TX queues per channel.
8127d661 614 */
b0fbdae1
SS		 615 efx->max_channels = min_t(unsigned int,
616 EFX_MAX_CHANNELS,
617 efx_ef10_mem_map_size(efx) /
618 (EFX_VI_PAGE_SIZE * EFX_TXQ_TYPES));
619 efx->max_tx_channels = efx->max_channels;
9fd3d3a4
EC		 620 if (WARN_ON(efx->max_channels == 0))
621 return -EIO;
8127d661
BH		 622
623 nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
624 if (!nic_data)
625 return -ENOMEM;
626 efx->nic_data = nic_data;
627
75aba2a5
EC		 628 /* we assume later that we can copy from this buffer in dwords */
629 BUILD_BUG_ON(MCDI_CTL_SDU_LEN_MAX_V2 % 4);
630
8127d661
BH		 631 rc = efx_nic_alloc_buffer(efx, &nic_data->mcdi_buf,
632 8 + MCDI_CTL_SDU_LEN_MAX_V2, GFP_KERNEL);
633 if (rc)
634 goto fail1;
635
636 /* Get the MC's warm boot count. In case it's rebooting right
637 * now, be prepared to retry.
638 */
639 i = 0;
640 for (;;) {
641 rc = efx_ef10_get_warm_boot_count(efx);
642 if (rc >= 0)
643 break;
644 if (++i == 5)
645 goto fail2;
646 ssleep(1);
647 }
648 nic_data->warm_boot_count = rc;
649
650 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
651
45b2449e
DP		 652 nic_data->vport_id = EVB_PORT_ID_ASSIGNED;
653
8127d661
BH		 654 /* In case we're recovering from a crash (kexec), we want to
655 * cancel any outstanding request by the previous user of this
656 * function. We send a special message using the least
657 * significant bits of the 'high' (doorbell) register.
658 */
659 _efx_writed(efx, cpu_to_le32(1), ER_DZ_MC_DB_HWRD);
660
661 rc = efx_mcdi_init(efx);
662 if (rc)
663 goto fail2;
664
e5fbd977
JC		 665 mutex_init(&nic_data->udp_tunnels_lock);
666
8127d661
BH		 667 /* Reset (most) configuration for this function */
668 rc = efx_mcdi_reset(efx, RESET_TYPE_ALL);
669 if (rc)
670 goto fail3;
671
672 /* Enable event logging */
673 rc = efx_mcdi_log_ctrl(efx, true, false, 0);
674 if (rc)
675 goto fail3;
676
0f5c0845
SS		 677 rc = device_create_file(&efx->pci_dev->dev,
678 &dev_attr_link_control_flag);
1cd9ecbb
DP		 679 if (rc)
680 goto fail3;
681
0f5c0845
SS		 682 rc = device_create_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
683 if (rc)
684 goto fail4;
685
686 rc = efx_ef10_get_pf_index(efx);
687 if (rc)
688 goto fail5;
689
e5a2538a 690 rc = efx_ef10_init_datapath_caps(efx);
8127d661 691 if (rc < 0)
0f5c0845 692 goto fail5;
8127d661
BH		 693
694 efx->rx_packet_len_offset =
695 ES_DZ_RX_PREFIX_PKTLEN_OFST - ES_DZ_RX_PREFIX_SIZE;
696
6978729f
EC		 697 if (nic_data->datapath_caps &
698 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_INCLUDE_FCS_LBN))
699 efx->net_dev->hw_features |= NETIF_F_RXFCS;
700
8127d661
BH		 701 rc = efx_mcdi_port_get_number(efx);
702 if (rc < 0)
0f5c0845 703 goto fail5;
8127d661
BH		 704 efx->port_num = rc;
705
0d5e0fbb 706 rc = efx->type->get_mac_address(efx, efx->net_dev->perm_addr);
8127d661 707 if (rc)
0f5c0845 708 goto fail5;
8127d661 709
d95e329a 710 rc = efx_ef10_get_timer_config(efx);
8127d661 711 if (rc < 0)
0f5c0845 712 goto fail5;
8127d661 713
8127d661 714 rc = efx_mcdi_mon_probe(efx);
267d9d73 715 if (rc && rc != -EPERM)
0f5c0845 716 goto fail5;
8127d661 717
9aecda95
BH		 718 efx_ptp_probe(efx, NULL);
719
1d051e00
SS		 720#ifdef CONFIG_SFC_SRIOV
721 if ((efx->pci_dev->physfn) && (!efx->pci_dev->is_physfn)) {
722 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn;
723 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
724
725 efx_pf->type->get_mac_address(efx_pf, nic_data->port_id);
726 } else
727#endif
728 ether_addr_copy(nic_data->port_id, efx->net_dev->perm_addr);
729
34813fe2
AR		 730 INIT_LIST_HEAD(&nic_data->vlan_list);
731 mutex_init(&nic_data->vlan_lock);
732
733 /* Add unspecified VID to support VLAN filtering being disabled */
734 rc = efx_ef10_add_vlan(efx, EFX_FILTER_VID_UNSPEC);
735 if (rc)
736 goto fail_add_vid_unspec;
737
4a53ea8a
AR		 738 /* If VLAN filtering is enabled, we need VID 0 to get untagged
739 * traffic. It is added automatically if 8021q module is loaded,
740 * but we can't rely on it since module may be not loaded.
741 */
742 rc = efx_ef10_add_vlan(efx, 0);
743 if (rc)
744 goto fail_add_vid_0;
745
8127d661
BH		 746 return 0;
747
4a53ea8a
AR		 748fail_add_vid_0:
749 efx_ef10_cleanup_vlans(efx);
34813fe2
AR		 750fail_add_vid_unspec:
751 mutex_destroy(&nic_data->vlan_lock);
752 efx_ptp_remove(efx);
753 efx_mcdi_mon_remove(efx);
0f5c0845
SS		 754fail5:
755 device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
756fail4:
757 device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag);
8127d661 758fail3:
e5fbd977
JC		 759 efx_mcdi_detach(efx);
760
761 mutex_lock(&nic_data->udp_tunnels_lock);
762 memset(nic_data->udp_tunnels, 0, sizeof(nic_data->udp_tunnels));
763 (void)efx_ef10_set_udp_tnl_ports(efx, true);
764 mutex_unlock(&nic_data->udp_tunnels_lock);
765 mutex_destroy(&nic_data->udp_tunnels_lock);
766
8127d661
BH		 767 efx_mcdi_fini(efx);
768fail2:
769 efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
770fail1:
771 kfree(nic_data);
772 efx->nic_data = NULL;
773 return rc;
774}
775
776static int efx_ef10_free_vis(struct efx_nic *efx)
777{
aa09a3da 778 MCDI_DECLARE_BUF_ERR(outbuf);
1e0b8120
EC		 779 size_t outlen;
780 int rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FREE_VIS, NULL, 0,
781 outbuf, sizeof(outbuf), &outlen);
8127d661
BH		 782
783 /* -EALREADY means nothing to free, so ignore */
784 if (rc == -EALREADY)
785 rc = 0;
1e0b8120
EC		 786 if (rc)
787 efx_mcdi_display_error(efx, MC_CMD_FREE_VIS, 0, outbuf, outlen,
788 rc);
8127d661
BH		 789 return rc;
790}
791
183233be
BH		 792#ifdef EFX_USE_PIO
793
794static void efx_ef10_free_piobufs(struct efx_nic *efx)
795{
796 struct efx_ef10_nic_data *nic_data = efx->nic_data;
797 MCDI_DECLARE_BUF(inbuf, MC_CMD_FREE_PIOBUF_IN_LEN);
798 unsigned int i;
799 int rc;
800
801 BUILD_BUG_ON(MC_CMD_FREE_PIOBUF_OUT_LEN != 0);
802
803 for (i = 0; i < nic_data->n_piobufs; i++) {
804 MCDI_SET_DWORD(inbuf, FREE_PIOBUF_IN_PIOBUF_HANDLE,
805 nic_data->piobuf_handle[i]);
806 rc = efx_mcdi_rpc(efx, MC_CMD_FREE_PIOBUF, inbuf, sizeof(inbuf),
807 NULL, 0, NULL);
808 WARN_ON(rc);
809 }
810
811 nic_data->n_piobufs = 0;
812}
813
814static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
815{
816 struct efx_ef10_nic_data *nic_data = efx->nic_data;
817 MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_PIOBUF_OUT_LEN);
818 unsigned int i;
819 size_t outlen;
820 int rc = 0;
821
822 BUILD_BUG_ON(MC_CMD_ALLOC_PIOBUF_IN_LEN != 0);
823
824 for (i = 0; i < n; i++) {
09a04204
BK		 825 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_ALLOC_PIOBUF, NULL, 0,
826 outbuf, sizeof(outbuf), &outlen);
827 if (rc) {
828 /* Don't display the MC error if we didn't have space
829 * for a VF.
830 */
831 if (!(efx_ef10_is_vf(efx) && rc == -ENOSPC))
832 efx_mcdi_display_error(efx, MC_CMD_ALLOC_PIOBUF,
833 0, outbuf, outlen, rc);
183233be 834 break;
09a04204 835 }
183233be
BH		 836 if (outlen < MC_CMD_ALLOC_PIOBUF_OUT_LEN) {
837 rc = -EIO;
838 break;
839 }
840 nic_data->piobuf_handle[i] =
841 MCDI_DWORD(outbuf, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE);
842 netif_dbg(efx, probe, efx->net_dev,
843 "allocated PIO buffer %u handle %x\n", i,
844 nic_data->piobuf_handle[i]);
845 }
846
847 nic_data->n_piobufs = i;
848 if (rc)
849 efx_ef10_free_piobufs(efx);
850 return rc;
851}
852
853static int efx_ef10_link_piobufs(struct efx_nic *efx)
854{
855 struct efx_ef10_nic_data *nic_data = efx->nic_data;
d0346b03 856 MCDI_DECLARE_BUF(inbuf, MC_CMD_LINK_PIOBUF_IN_LEN);
183233be
BH		 857 struct efx_channel *channel;
858 struct efx_tx_queue *tx_queue;
859 unsigned int offset, index;
860 int rc;
861
862 BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_OUT_LEN != 0);
863 BUILD_BUG_ON(MC_CMD_UNLINK_PIOBUF_OUT_LEN != 0);
864
865 /* Link a buffer to each VI in the write-combining mapping */
866 for (index = 0; index < nic_data->n_piobufs; ++index) {
867 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_PIOBUF_HANDLE,
868 nic_data->piobuf_handle[index]);
869 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_TXQ_INSTANCE,
870 nic_data->pio_write_vi_base + index);
871 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
872 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
873 NULL, 0, NULL);
874 if (rc) {
875 netif_err(efx, drv, efx->net_dev,
876 "failed to link VI %u to PIO buffer %u (%d)\n",
877 nic_data->pio_write_vi_base + index, index,
878 rc);
879 goto fail;
880 }
881 netif_dbg(efx, probe, efx->net_dev,
882 "linked VI %u to PIO buffer %u\n",
883 nic_data->pio_write_vi_base + index, index);
884 }
885
886 /* Link a buffer to each TX queue */
887 efx_for_each_channel(channel, efx) {
888 efx_for_each_channel_tx_queue(tx_queue, channel) {
889 /* We assign the PIO buffers to queues in
890 * reverse order to allow for the following
891 * special case.
892 */
893 offset = ((efx->tx_channel_offset + efx->n_tx_channels -
894 tx_queue->channel->channel - 1) *
895 efx_piobuf_size);
c634700f
EC		 896 index = offset / nic_data->piobuf_size;
897 offset = offset % nic_data->piobuf_size;
183233be
BH		 898
899 /* When the host page size is 4K, the first
900 * host page in the WC mapping may be within
901 * the same VI page as the last TX queue. We
902 * can only link one buffer to each VI.
903 */
904 if (tx_queue->queue == nic_data->pio_write_vi_base) {
905 BUG_ON(index != 0);
906 rc = 0;
907 } else {
908 MCDI_SET_DWORD(inbuf,
909 LINK_PIOBUF_IN_PIOBUF_HANDLE,
910 nic_data->piobuf_handle[index]);
911 MCDI_SET_DWORD(inbuf,
912 LINK_PIOBUF_IN_TXQ_INSTANCE,
913 tx_queue->queue);
914 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
915 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
916 NULL, 0, NULL);
917 }
918
919 if (rc) {
920 /* This is non-fatal; the TX path just
921 * won't use PIO for this queue
922 */
923 netif_err(efx, drv, efx->net_dev,
924 "failed to link VI %u to PIO buffer %u (%d)\n",
925 tx_queue->queue, index, rc);
926 tx_queue->piobuf = NULL;
927 } else {
928 tx_queue->piobuf =
929 nic_data->pio_write_base +
930 index * EFX_VI_PAGE_SIZE + offset;
931 tx_queue->piobuf_offset = offset;
932 netif_dbg(efx, probe, efx->net_dev,
933 "linked VI %u to PIO buffer %u offset %x addr %p\n",
934 tx_queue->queue, index,
935 tx_queue->piobuf_offset,
936 tx_queue->piobuf);
937 }
938 }
939 }
940
941 return 0;
942
943fail:
d0346b03
EC		 944 /* inbuf was defined for MC_CMD_LINK_PIOBUF. We can use the same
945 * buffer for MC_CMD_UNLINK_PIOBUF because it's shorter.
946 */
947 BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_IN_LEN < MC_CMD_UNLINK_PIOBUF_IN_LEN);
183233be
BH		 948 while (index--) {
949 MCDI_SET_DWORD(inbuf, UNLINK_PIOBUF_IN_TXQ_INSTANCE,
950 nic_data->pio_write_vi_base + index);
951 efx_mcdi_rpc(efx, MC_CMD_UNLINK_PIOBUF,
952 inbuf, MC_CMD_UNLINK_PIOBUF_IN_LEN,
953 NULL, 0, NULL);
954 }
955 return rc;
956}
957
c0795bf6
EC		 958static void efx_ef10_forget_old_piobufs(struct efx_nic *efx)
959{
960 struct efx_channel *channel;
961 struct efx_tx_queue *tx_queue;
962
963 /* All our existing PIO buffers went away */
964 efx_for_each_channel(channel, efx)
965 efx_for_each_channel_tx_queue(tx_queue, channel)
966 tx_queue->piobuf = NULL;
967}
968
183233be
BH		 969#else /* !EFX_USE_PIO */
970
971static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
972{
973 return n == 0 ? 0 : -ENOBUFS;
974}
975
976static int efx_ef10_link_piobufs(struct efx_nic *efx)
977{
978 return 0;
979}
980
981static void efx_ef10_free_piobufs(struct efx_nic *efx)
982{
983}
984
c0795bf6
EC		 985static void efx_ef10_forget_old_piobufs(struct efx_nic *efx)
986{
987}
988
183233be
BH		 989#endif /* EFX_USE_PIO */
990
8127d661
BH		 991static void efx_ef10_remove(struct efx_nic *efx)
992{
993 struct efx_ef10_nic_data *nic_data = efx->nic_data;
994 int rc;
995
f1122a34
SS		 996#ifdef CONFIG_SFC_SRIOV
997 struct efx_ef10_nic_data *nic_data_pf;
998 struct pci_dev *pci_dev_pf;
999 struct efx_nic *efx_pf;
1000 struct ef10_vf *vf;
1001
1002 if (efx->pci_dev->is_virtfn) {
1003 pci_dev_pf = efx->pci_dev->physfn;
1004 if (pci_dev_pf) {
1005 efx_pf = pci_get_drvdata(pci_dev_pf);
1006 nic_data_pf = efx_pf->nic_data;
1007 vf = nic_data_pf->vf + nic_data->vf_index;
1008 vf->efx = NULL;
1009 } else
1010 netif_info(efx, drv, efx->net_dev,
1011 "Could not get the PF id from VF\n");
1012 }
1013#endif
1014
34813fe2
AR		 1015 efx_ef10_cleanup_vlans(efx);
1016 mutex_destroy(&nic_data->vlan_lock);
1017
9aecda95
BH		 1018 efx_ptp_remove(efx);
1019
8127d661
BH		 1020 efx_mcdi_mon_remove(efx);
1021
8127d661
BH		 1022 efx_ef10_rx_free_indir_table(efx);
1023
183233be
BH		 1024 if (nic_data->wc_membase)
1025 iounmap(nic_data->wc_membase);
1026
8127d661
BH		 1027 rc = efx_ef10_free_vis(efx);
1028 WARN_ON(rc != 0);
1029
183233be
BH		 1030 if (!nic_data->must_restore_piobufs)
1031 efx_ef10_free_piobufs(efx);
1032
0f5c0845
SS		 1033 device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
1034 device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag);
1035
e5fbd977
JC		 1036 efx_mcdi_detach(efx);
1037
1038 memset(nic_data->udp_tunnels, 0, sizeof(nic_data->udp_tunnels));
1039 mutex_lock(&nic_data->udp_tunnels_lock);
1040 (void)efx_ef10_set_udp_tnl_ports(efx, true);
1041 mutex_unlock(&nic_data->udp_tunnels_lock);
1042
1043 mutex_destroy(&nic_data->udp_tunnels_lock);
1044
8127d661
BH		 1045 efx_mcdi_fini(efx);
1046 efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
1047 kfree(nic_data);
1048}
1049
88a37de6
SS		 1050static int efx_ef10_probe_pf(struct efx_nic *efx)
1051{
1052 return efx_ef10_probe(efx);
1053}
1054
38d27f38
AR		 1055int efx_ef10_vadaptor_query(struct efx_nic *efx, unsigned int port_id,
1056 u32 *port_flags, u32 *vadaptor_flags,
1057 unsigned int *vlan_tags)
1058{
1059 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1060 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_QUERY_IN_LEN);
1061 MCDI_DECLARE_BUF(outbuf, MC_CMD_VADAPTOR_QUERY_OUT_LEN);
1062 size_t outlen;
1063 int rc;
1064
1065 if (nic_data->datapath_caps &
1066 (1 << MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_LBN)) {
1067 MCDI_SET_DWORD(inbuf, VADAPTOR_QUERY_IN_UPSTREAM_PORT_ID,
1068 port_id);
1069
1070 rc = efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_QUERY, inbuf, sizeof(inbuf),
1071 outbuf, sizeof(outbuf), &outlen);
1072 if (rc)
1073 return rc;
1074
1075 if (outlen < sizeof(outbuf)) {
1076 rc = -EIO;
1077 return rc;
1078 }
1079 }
1080
1081 if (port_flags)
1082 *port_flags = MCDI_DWORD(outbuf, VADAPTOR_QUERY_OUT_PORT_FLAGS);
1083 if (vadaptor_flags)
1084 *vadaptor_flags =
1085 MCDI_DWORD(outbuf, VADAPTOR_QUERY_OUT_VADAPTOR_FLAGS);
1086 if (vlan_tags)
1087 *vlan_tags =
1088 MCDI_DWORD(outbuf,
1089 VADAPTOR_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS);
1090
1091 return 0;
1092}
1093
7a186f47
DP		 1094int efx_ef10_vadaptor_alloc(struct efx_nic *efx, unsigned int port_id)
1095{
1096 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_ALLOC_IN_LEN);
1097
1098 MCDI_SET_DWORD(inbuf, VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID, port_id);
1099 return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_ALLOC, inbuf, sizeof(inbuf),
1100 NULL, 0, NULL);
1101}
1102
1103int efx_ef10_vadaptor_free(struct efx_nic *efx, unsigned int port_id)
1104{
1105 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_FREE_IN_LEN);
1106
1107 MCDI_SET_DWORD(inbuf, VADAPTOR_FREE_IN_UPSTREAM_PORT_ID, port_id);
1108 return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_FREE, inbuf, sizeof(inbuf),
1109 NULL, 0, NULL);
1110}
1111
1112int efx_ef10_vport_add_mac(struct efx_nic *efx,
1113 unsigned int port_id, u8 *mac)
1114{
1115 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_LEN);
1116
1117 MCDI_SET_DWORD(inbuf, VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID, port_id);
1118 ether_addr_copy(MCDI_PTR(inbuf, VPORT_ADD_MAC_ADDRESS_IN_MACADDR), mac);
1119
1120 return efx_mcdi_rpc(efx, MC_CMD_VPORT_ADD_MAC_ADDRESS, inbuf,
1121 sizeof(inbuf), NULL, 0, NULL);
1122}
1123
1124int efx_ef10_vport_del_mac(struct efx_nic *efx,
1125 unsigned int port_id, u8 *mac)
1126{
1127 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_LEN);
1128
1129 MCDI_SET_DWORD(inbuf, VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID, port_id);
1130 ether_addr_copy(MCDI_PTR(inbuf, VPORT_DEL_MAC_ADDRESS_IN_MACADDR), mac);
1131
1132 return efx_mcdi_rpc(efx, MC_CMD_VPORT_DEL_MAC_ADDRESS, inbuf,
1133 sizeof(inbuf), NULL, 0, NULL);
1134}
1135
88a37de6
SS		 1136#ifdef CONFIG_SFC_SRIOV
1137static int efx_ef10_probe_vf(struct efx_nic *efx)
1138{
1139 int rc;
6598dad2
DP		 1140 struct pci_dev *pci_dev_pf;
1141
1142 /* If the parent PF has no VF data structure, it doesn't know about this
1143 * VF so fail probe. The VF needs to be re-created. This can happen
1144 * if the PF driver is unloaded while the VF is assigned to a guest.
1145 */
1146 pci_dev_pf = efx->pci_dev->physfn;
1147 if (pci_dev_pf) {
1148 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
1149 struct efx_ef10_nic_data *nic_data_pf = efx_pf->nic_data;
1150
1151 if (!nic_data_pf->vf) {
1152 netif_info(efx, drv, efx->net_dev,
1153 "The VF cannot link to its parent PF; "
1154 "please destroy and re-create the VF\n");
1155 return -EBUSY;
1156 }
1157 }
88a37de6
SS		 1158
1159 rc = efx_ef10_probe(efx);
1160 if (rc)
1161 return rc;
1162
1163 rc = efx_ef10_get_vf_index(efx);
1164 if (rc)
1165 goto fail;
1166
f1122a34
SS		 1167 if (efx->pci_dev->is_virtfn) {
1168 if (efx->pci_dev->physfn) {
1169 struct efx_nic *efx_pf =
1170 pci_get_drvdata(efx->pci_dev->physfn);
1171 struct efx_ef10_nic_data *nic_data_p = efx_pf->nic_data;
1172 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1173
1174 nic_data_p->vf[nic_data->vf_index].efx = efx;
6598dad2
DP		 1175 nic_data_p->vf[nic_data->vf_index].pci_dev =
1176 efx->pci_dev;
f1122a34
SS		 1177 } else
1178 netif_info(efx, drv, efx->net_dev,
1179 "Could not get the PF id from VF\n");
1180 }
1181
88a37de6
SS		 1182 return 0;
1183
1184fail:
1185 efx_ef10_remove(efx);
1186 return rc;
1187}
1188#else
1189static int efx_ef10_probe_vf(struct efx_nic *efx __attribute__ ((unused)))
1190{
1191 return 0;
1192}
1193#endif
1194
8127d661
BH		 1195static int efx_ef10_alloc_vis(struct efx_nic *efx,
1196 unsigned int min_vis, unsigned int max_vis)
1197{
1198 MCDI_DECLARE_BUF(inbuf, MC_CMD_ALLOC_VIS_IN_LEN);
1199 MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_VIS_OUT_LEN);
1200 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1201 size_t outlen;
1202 int rc;
1203
1204 MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MIN_VI_COUNT, min_vis);
1205 MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MAX_VI_COUNT, max_vis);
1206 rc = efx_mcdi_rpc(efx, MC_CMD_ALLOC_VIS, inbuf, sizeof(inbuf),
1207 outbuf, sizeof(outbuf), &outlen);
1208 if (rc != 0)
1209 return rc;
1210
1211 if (outlen < MC_CMD_ALLOC_VIS_OUT_LEN)
1212 return -EIO;
1213
1214 netif_dbg(efx, drv, efx->net_dev, "base VI is A0x%03x\n",
1215 MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE));
1216
1217 nic_data->vi_base = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE);
1218 nic_data->n_allocated_vis = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_COUNT);
1219 return 0;
1220}
1221
183233be
BH		 1222/* Note that the failure path of this function does not free
1223 * resources, as this will be done by efx_ef10_remove().
1224 */
8127d661
BH		 1225static int efx_ef10_dimension_resources(struct efx_nic *efx)
1226{
183233be
BH		 1227 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1228 unsigned int uc_mem_map_size, wc_mem_map_size;
b0fbdae1
SS		 1229 unsigned int min_vis = max(EFX_TXQ_TYPES,
1230 efx_separate_tx_channels ? 2 : 1);
1231 unsigned int channel_vis, pio_write_vi_base, max_vis;
183233be
BH		 1232 void __iomem *membase;
1233 int rc;
1234
b0fbdae1 1235 channel_vis = max(efx->n_channels, efx->n_tx_channels * EFX_TXQ_TYPES);
8127d661 1236
183233be
BH		 1237#ifdef EFX_USE_PIO
1238 /* Try to allocate PIO buffers if wanted and if the full
1239 * number of PIO buffers would be sufficient to allocate one
1240 * copy-buffer per TX channel. Failure is non-fatal, as there
1241 * are only a small number of PIO buffers shared between all
1242 * functions of the controller.
1243 */
1244 if (efx_piobuf_size != 0 &&
c634700f 1245 nic_data->piobuf_size / efx_piobuf_size * EF10_TX_PIOBUF_COUNT >=
183233be
BH		 1246 efx->n_tx_channels) {
1247 unsigned int n_piobufs =
1248 DIV_ROUND_UP(efx->n_tx_channels,
c634700f 1249 nic_data->piobuf_size / efx_piobuf_size);
183233be
BH		 1250
1251 rc = efx_ef10_alloc_piobufs(efx, n_piobufs);
6eacfb54
TP		 1252 if (rc == -ENOSPC)
1253 netif_dbg(efx, probe, efx->net_dev,
1254 "out of PIO buffers; cannot allocate more\n");
1255 else if (rc == -EPERM)
1256 netif_dbg(efx, probe, efx->net_dev,
1257 "not permitted to allocate PIO buffers\n");
1258 else if (rc)
183233be
BH		 1259 netif_err(efx, probe, efx->net_dev,
1260 "failed to allocate PIO buffers (%d)\n", rc);
1261 else
1262 netif_dbg(efx, probe, efx->net_dev,
1263 "allocated %u PIO buffers\n", n_piobufs);
1264 }
1265#else
1266 nic_data->n_piobufs = 0;
1267#endif
1268
1269 /* PIO buffers should be mapped with write-combining enabled,
1270 * and we want to make single UC and WC mappings rather than
1271 * several of each (in fact that's the only option if host
1272 * page size is >4K). So we may allocate some extra VIs just
1273 * for writing PIO buffers through.
52ad762b 1274 *
b0fbdae1 1275 * The UC mapping contains (channel_vis - 1) complete VIs and the
52ad762b
DP		 1276 * first half of the next VI. Then the WC mapping begins with
1277 * the second half of this last VI.
183233be 1278 */
b0fbdae1 1279 uc_mem_map_size = PAGE_ALIGN((channel_vis - 1) * EFX_VI_PAGE_SIZE +
183233be
BH		 1280 ER_DZ_TX_PIOBUF);
1281 if (nic_data->n_piobufs) {
52ad762b
DP		 1282 /* pio_write_vi_base rounds down to give the number of complete
1283 * VIs inside the UC mapping.
1284 */
183233be
BH		 1285 pio_write_vi_base = uc_mem_map_size / EFX_VI_PAGE_SIZE;
1286 wc_mem_map_size = (PAGE_ALIGN((pio_write_vi_base +
1287 nic_data->n_piobufs) *
1288 EFX_VI_PAGE_SIZE) -
1289 uc_mem_map_size);
1290 max_vis = pio_write_vi_base + nic_data->n_piobufs;
1291 } else {
1292 pio_write_vi_base = 0;
1293 wc_mem_map_size = 0;
b0fbdae1 1294 max_vis = channel_vis;
183233be
BH		 1295 }
1296
1297 /* In case the last attached driver failed to free VIs, do it now */
1298 rc = efx_ef10_free_vis(efx);
1299 if (rc != 0)
1300 return rc;
1301
1302 rc = efx_ef10_alloc_vis(efx, min_vis, max_vis);
1303 if (rc != 0)
1304 return rc;
1305
b0fbdae1
SS		 1306 if (nic_data->n_allocated_vis < channel_vis) {
1307 netif_info(efx, drv, efx->net_dev,
1308 "Could not allocate enough VIs to satisfy RSS"
1309 " requirements. Performance may not be optimal.\n");
1310 /* We didn't get the VIs to populate our channels.
1311 * We could keep what we got but then we'd have more
1312 * interrupts than we need.
1313 * Instead calculate new max_channels and restart
1314 */
1315 efx->max_channels = nic_data->n_allocated_vis;
1316 efx->max_tx_channels =
1317 nic_data->n_allocated_vis / EFX_TXQ_TYPES;
1318
1319 efx_ef10_free_vis(efx);
1320 return -EAGAIN;
1321 }
1322
183233be
BH		 1323 /* If we didn't get enough VIs to map all the PIO buffers, free the
1324 * PIO buffers
1325 */
1326 if (nic_data->n_piobufs &&
1327 nic_data->n_allocated_vis <
1328 pio_write_vi_base + nic_data->n_piobufs) {
1329 netif_dbg(efx, probe, efx->net_dev,
1330 "%u VIs are not sufficient to map %u PIO buffers\n",
1331 nic_data->n_allocated_vis, nic_data->n_piobufs);
1332 efx_ef10_free_piobufs(efx);
1333 }
1334
1335 /* Shrink the original UC mapping of the memory BAR */
1336 membase = ioremap_nocache(efx->membase_phys, uc_mem_map_size);
1337 if (!membase) {
1338 netif_err(efx, probe, efx->net_dev,
1339 "could not shrink memory BAR to %x\n",
1340 uc_mem_map_size);
1341 return -ENOMEM;
1342 }
1343 iounmap(efx->membase);
1344 efx->membase = membase;
1345
1346 /* Set up the WC mapping if needed */
1347 if (wc_mem_map_size) {
1348 nic_data->wc_membase = ioremap_wc(efx->membase_phys +
1349 uc_mem_map_size,
1350 wc_mem_map_size);
1351 if (!nic_data->wc_membase) {
1352 netif_err(efx, probe, efx->net_dev,
1353 "could not allocate WC mapping of size %x\n",
1354 wc_mem_map_size);
1355 return -ENOMEM;
1356 }
1357 nic_data->pio_write_vi_base = pio_write_vi_base;
1358 nic_data->pio_write_base =
1359 nic_data->wc_membase +
1360 (pio_write_vi_base * EFX_VI_PAGE_SIZE + ER_DZ_TX_PIOBUF -
1361 uc_mem_map_size);
1362
1363 rc = efx_ef10_link_piobufs(efx);
1364 if (rc)
1365 efx_ef10_free_piobufs(efx);
1366 }
1367
1368 netif_dbg(efx, probe, efx->net_dev,
1369 "memory BAR at %pa (virtual %p+%x UC, %p+%x WC)\n",
1370 &efx->membase_phys, efx->membase, uc_mem_map_size,
1371 nic_data->wc_membase, wc_mem_map_size);
1372
1373 return 0;
8127d661
BH		 1374}
1375
1376static int efx_ef10_init_nic(struct efx_nic *efx)
1377{
1378 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1379 int rc;
1380
a915ccc9
BH		 1381 if (nic_data->must_check_datapath_caps) {
1382 rc = efx_ef10_init_datapath_caps(efx);
1383 if (rc)
1384 return rc;
1385 nic_data->must_check_datapath_caps = false;
1386 }
1387
8127d661
BH		 1388 if (nic_data->must_realloc_vis) {
1389 /* We cannot let the number of VIs change now */
1390 rc = efx_ef10_alloc_vis(efx, nic_data->n_allocated_vis,
1391 nic_data->n_allocated_vis);
1392 if (rc)
1393 return rc;
1394 nic_data->must_realloc_vis = false;
1395 }
1396
183233be
BH		 1397 if (nic_data->must_restore_piobufs && nic_data->n_piobufs) {
1398 rc = efx_ef10_alloc_piobufs(efx, nic_data->n_piobufs);
1399 if (rc == 0) {
1400 rc = efx_ef10_link_piobufs(efx);
1401 if (rc)
1402 efx_ef10_free_piobufs(efx);
1403 }
1404
6eacfb54
TP		 1405 /* Log an error on failure, but this is non-fatal.
1406 * Permission errors are less important - we've presumably
1407 * had the PIO buffer licence removed.
1408 */
1409 if (rc == -EPERM)
1410 netif_dbg(efx, drv, efx->net_dev,
1411 "not permitted to restore PIO buffers\n");
1412 else if (rc)
183233be
BH		 1413 netif_err(efx, drv, efx->net_dev,
1414 "failed to restore PIO buffers (%d)\n", rc);
1415 nic_data->must_restore_piobufs = false;
1416 }
1417
267c0157 1418 /* don't fail init if RSS setup doesn't work */
f74d1995 1419 rc = efx->type->rx_push_rss_config(efx, false, efx->rx_indir_table, NULL);
4fdda958 1420 efx->rss_active = (rc == 0);
267c0157 1421
8127d661
BH		 1422 return 0;
1423}
1424
3e336261
JC		 1425static void efx_ef10_reset_mc_allocations(struct efx_nic *efx)
1426{
1427 struct efx_ef10_nic_data *nic_data = efx->nic_data;
774ad031
DP		 1428#ifdef CONFIG_SFC_SRIOV
1429 unsigned int i;
1430#endif
3e336261
JC		 1431
1432 /* All our allocations have been reset */
1433 nic_data->must_realloc_vis = true;
1434 nic_data->must_restore_filters = true;
1435 nic_data->must_restore_piobufs = true;
c0795bf6 1436 efx_ef10_forget_old_piobufs(efx);
3e336261 1437 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
774ad031
DP		 1438
1439 /* Driver-created vswitches and vports must be re-created */
1440 nic_data->must_probe_vswitching = true;
1441 nic_data->vport_id = EVB_PORT_ID_ASSIGNED;
1442#ifdef CONFIG_SFC_SRIOV
1443 if (nic_data->vf)
1444 for (i = 0; i < efx->vf_count; i++)
1445 nic_data->vf[i].vport_id = 0;
1446#endif
3e336261
JC		 1447}
1448
087e9025
JC		 1449static enum reset_type efx_ef10_map_reset_reason(enum reset_type reason)
1450{
1451 if (reason == RESET_TYPE_MC_FAILURE)
1452 return RESET_TYPE_DATAPATH;
1453
1454 return efx_mcdi_map_reset_reason(reason);
1455}
1456
8127d661
BH		 1457static int efx_ef10_map_reset_flags(u32 *flags)
1458{
1459 enum {
1460 EF10_RESET_PORT = ((ETH_RESET_MAC | ETH_RESET_PHY) <<
1461 ETH_RESET_SHARED_SHIFT),
1462 EF10_RESET_MC = ((ETH_RESET_DMA | ETH_RESET_FILTER |
1463 ETH_RESET_OFFLOAD | ETH_RESET_MAC |
1464 ETH_RESET_PHY | ETH_RESET_MGMT) <<
1465 ETH_RESET_SHARED_SHIFT)
1466 };
1467
1468 /* We assume for now that our PCI function is permitted to
1469 * reset everything.
1470 */
1471
1472 if ((*flags & EF10_RESET_MC) == EF10_RESET_MC) {
1473 *flags &= ~EF10_RESET_MC;
1474 return RESET_TYPE_WORLD;
1475 }
1476
1477 if ((*flags & EF10_RESET_PORT) == EF10_RESET_PORT) {
1478 *flags &= ~EF10_RESET_PORT;
1479 return RESET_TYPE_ALL;
1480 }
1481
1482 /* no invisible reset implemented */
1483
1484 return -EINVAL;
1485}
1486
3e336261
JC		 1487static int efx_ef10_reset(struct efx_nic *efx, enum reset_type reset_type)
1488{
1489 int rc = efx_mcdi_reset(efx, reset_type);
1490
27324820
DP		 1491 /* Unprivileged functions return -EPERM, but need to return success
1492 * here so that the datapath is brought back up.
1493 */
1494 if (reset_type == RESET_TYPE_WORLD && rc == -EPERM)
1495 rc = 0;
1496
3e336261
JC		 1497 /* If it was a port reset, trigger reallocation of MC resources.
1498 * Note that on an MC reset nothing needs to be done now because we'll
1499 * detect the MC reset later and handle it then.
e283546c
EC		 1500 * For an FLR, we never get an MC reset event, but the MC has reset all
1501 * resources assigned to us, so we have to trigger reallocation now.
3e336261 1502 */
e283546c
EC		 1503 if ((reset_type == RESET_TYPE_ALL ||
1504 reset_type == RESET_TYPE_MCDI_TIMEOUT) && !rc)
3e336261
JC		 1505 efx_ef10_reset_mc_allocations(efx);
1506 return rc;
1507}
1508
8127d661
BH		 1509#define EF10_DMA_STAT(ext_name, mcdi_name) \
1510 [EF10_STAT_ ## ext_name] = \
1511 { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
1512#define EF10_DMA_INVIS_STAT(int_name, mcdi_name) \
1513 [EF10_STAT_ ## int_name] = \
1514 { NULL, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
1515#define EF10_OTHER_STAT(ext_name) \
1516 [EF10_STAT_ ## ext_name] = { #ext_name, 0, 0 }
e4d112e4
EC		 1517#define GENERIC_SW_STAT(ext_name) \
1518 [GENERIC_STAT_ ## ext_name] = { #ext_name, 0, 0 }
8127d661
BH		 1519
1520static const struct efx_hw_stat_desc efx_ef10_stat_desc[EF10_STAT_COUNT] = {
e80ca013
DP		 1521 EF10_DMA_STAT(port_tx_bytes, TX_BYTES),
1522 EF10_DMA_STAT(port_tx_packets, TX_PKTS),
1523 EF10_DMA_STAT(port_tx_pause, TX_PAUSE_PKTS),
1524 EF10_DMA_STAT(port_tx_control, TX_CONTROL_PKTS),
1525 EF10_DMA_STAT(port_tx_unicast, TX_UNICAST_PKTS),
1526 EF10_DMA_STAT(port_tx_multicast, TX_MULTICAST_PKTS),
1527 EF10_DMA_STAT(port_tx_broadcast, TX_BROADCAST_PKTS),
1528 EF10_DMA_STAT(port_tx_lt64, TX_LT64_PKTS),
1529 EF10_DMA_STAT(port_tx_64, TX_64_PKTS),
1530 EF10_DMA_STAT(port_tx_65_to_127, TX_65_TO_127_PKTS),
1531 EF10_DMA_STAT(port_tx_128_to_255, TX_128_TO_255_PKTS),
1532 EF10_DMA_STAT(port_tx_256_to_511, TX_256_TO_511_PKTS),
1533 EF10_DMA_STAT(port_tx_512_to_1023, TX_512_TO_1023_PKTS),
1534 EF10_DMA_STAT(port_tx_1024_to_15xx, TX_1024_TO_15XX_PKTS),
1535 EF10_DMA_STAT(port_tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS),
1536 EF10_DMA_STAT(port_rx_bytes, RX_BYTES),
1537 EF10_DMA_INVIS_STAT(port_rx_bytes_minus_good_bytes, RX_BAD_BYTES),
1538 EF10_OTHER_STAT(port_rx_good_bytes),
1539 EF10_OTHER_STAT(port_rx_bad_bytes),
1540 EF10_DMA_STAT(port_rx_packets, RX_PKTS),
1541 EF10_DMA_STAT(port_rx_good, RX_GOOD_PKTS),
1542 EF10_DMA_STAT(port_rx_bad, RX_BAD_FCS_PKTS),
1543 EF10_DMA_STAT(port_rx_pause, RX_PAUSE_PKTS),
1544 EF10_DMA_STAT(port_rx_control, RX_CONTROL_PKTS),
1545 EF10_DMA_STAT(port_rx_unicast, RX_UNICAST_PKTS),
1546 EF10_DMA_STAT(port_rx_multicast, RX_MULTICAST_PKTS),
1547 EF10_DMA_STAT(port_rx_broadcast, RX_BROADCAST_PKTS),
1548 EF10_DMA_STAT(port_rx_lt64, RX_UNDERSIZE_PKTS),
1549 EF10_DMA_STAT(port_rx_64, RX_64_PKTS),
1550 EF10_DMA_STAT(port_rx_65_to_127, RX_65_TO_127_PKTS),
1551 EF10_DMA_STAT(port_rx_128_to_255, RX_128_TO_255_PKTS),
1552 EF10_DMA_STAT(port_rx_256_to_511, RX_256_TO_511_PKTS),
1553 EF10_DMA_STAT(port_rx_512_to_1023, RX_512_TO_1023_PKTS),
1554 EF10_DMA_STAT(port_rx_1024_to_15xx, RX_1024_TO_15XX_PKTS),
1555 EF10_DMA_STAT(port_rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS),
1556 EF10_DMA_STAT(port_rx_gtjumbo, RX_GTJUMBO_PKTS),
1557 EF10_DMA_STAT(port_rx_bad_gtjumbo, RX_JABBER_PKTS),
1558 EF10_DMA_STAT(port_rx_overflow, RX_OVERFLOW_PKTS),
1559 EF10_DMA_STAT(port_rx_align_error, RX_ALIGN_ERROR_PKTS),
1560 EF10_DMA_STAT(port_rx_length_error, RX_LENGTH_ERROR_PKTS),
1561 EF10_DMA_STAT(port_rx_nodesc_drops, RX_NODESC_DROPS),
e4d112e4
EC		 1562 GENERIC_SW_STAT(rx_nodesc_trunc),
1563 GENERIC_SW_STAT(rx_noskb_drops),
e80ca013
DP		 1564 EF10_DMA_STAT(port_rx_pm_trunc_bb_overflow, PM_TRUNC_BB_OVERFLOW),
1565 EF10_DMA_STAT(port_rx_pm_discard_bb_overflow, PM_DISCARD_BB_OVERFLOW),
1566 EF10_DMA_STAT(port_rx_pm_trunc_vfifo_full, PM_TRUNC_VFIFO_FULL),
1567 EF10_DMA_STAT(port_rx_pm_discard_vfifo_full, PM_DISCARD_VFIFO_FULL),
1568 EF10_DMA_STAT(port_rx_pm_trunc_qbb, PM_TRUNC_QBB),
1569 EF10_DMA_STAT(port_rx_pm_discard_qbb, PM_DISCARD_QBB),
1570 EF10_DMA_STAT(port_rx_pm_discard_mapping, PM_DISCARD_MAPPING),
1571 EF10_DMA_STAT(port_rx_dp_q_disabled_packets, RXDP_Q_DISABLED_PKTS),
1572 EF10_DMA_STAT(port_rx_dp_di_dropped_packets, RXDP_DI_DROPPED_PKTS),
1573 EF10_DMA_STAT(port_rx_dp_streaming_packets, RXDP_STREAMING_PKTS),
1574 EF10_DMA_STAT(port_rx_dp_hlb_fetch, RXDP_HLB_FETCH_CONDITIONS),
1575 EF10_DMA_STAT(port_rx_dp_hlb_wait, RXDP_HLB_WAIT_CONDITIONS),
3c36a2ad
DP		 1576 EF10_DMA_STAT(rx_unicast, VADAPTER_RX_UNICAST_PACKETS),
1577 EF10_DMA_STAT(rx_unicast_bytes, VADAPTER_RX_UNICAST_BYTES),
1578 EF10_DMA_STAT(rx_multicast, VADAPTER_RX_MULTICAST_PACKETS),
1579 EF10_DMA_STAT(rx_multicast_bytes, VADAPTER_RX_MULTICAST_BYTES),
1580 EF10_DMA_STAT(rx_broadcast, VADAPTER_RX_BROADCAST_PACKETS),
1581 EF10_DMA_STAT(rx_broadcast_bytes, VADAPTER_RX_BROADCAST_BYTES),
1582 EF10_DMA_STAT(rx_bad, VADAPTER_RX_BAD_PACKETS),
1583 EF10_DMA_STAT(rx_bad_bytes, VADAPTER_RX_BAD_BYTES),
1584 EF10_DMA_STAT(rx_overflow, VADAPTER_RX_OVERFLOW),
1585 EF10_DMA_STAT(tx_unicast, VADAPTER_TX_UNICAST_PACKETS),
1586 EF10_DMA_STAT(tx_unicast_bytes, VADAPTER_TX_UNICAST_BYTES),
1587 EF10_DMA_STAT(tx_multicast, VADAPTER_TX_MULTICAST_PACKETS),
1588 EF10_DMA_STAT(tx_multicast_bytes, VADAPTER_TX_MULTICAST_BYTES),
1589 EF10_DMA_STAT(tx_broadcast, VADAPTER_TX_BROADCAST_PACKETS),
1590 EF10_DMA_STAT(tx_broadcast_bytes, VADAPTER_TX_BROADCAST_BYTES),
1591 EF10_DMA_STAT(tx_bad, VADAPTER_TX_BAD_PACKETS),
1592 EF10_DMA_STAT(tx_bad_bytes, VADAPTER_TX_BAD_BYTES),
1593 EF10_DMA_STAT(tx_overflow, VADAPTER_TX_OVERFLOW),
8127d661
BH		 1594};
1595
e80ca013
DP		 1596#define HUNT_COMMON_STAT_MASK ((1ULL << EF10_STAT_port_tx_bytes) | \
1597 (1ULL << EF10_STAT_port_tx_packets) | \
1598 (1ULL << EF10_STAT_port_tx_pause) | \
1599 (1ULL << EF10_STAT_port_tx_unicast) | \
1600 (1ULL << EF10_STAT_port_tx_multicast) | \
1601 (1ULL << EF10_STAT_port_tx_broadcast) | \
1602 (1ULL << EF10_STAT_port_rx_bytes) | \
1603 (1ULL << \
1604 EF10_STAT_port_rx_bytes_minus_good_bytes) | \
1605 (1ULL << EF10_STAT_port_rx_good_bytes) | \
1606 (1ULL << EF10_STAT_port_rx_bad_bytes) | \
1607 (1ULL << EF10_STAT_port_rx_packets) | \
1608 (1ULL << EF10_STAT_port_rx_good) | \
1609 (1ULL << EF10_STAT_port_rx_bad) | \
1610 (1ULL << EF10_STAT_port_rx_pause) | \
1611 (1ULL << EF10_STAT_port_rx_control) | \
1612 (1ULL << EF10_STAT_port_rx_unicast) | \
1613 (1ULL << EF10_STAT_port_rx_multicast) | \
1614 (1ULL << EF10_STAT_port_rx_broadcast) | \
1615 (1ULL << EF10_STAT_port_rx_lt64) | \
1616 (1ULL << EF10_STAT_port_rx_64) | \
1617 (1ULL << EF10_STAT_port_rx_65_to_127) | \
1618 (1ULL << EF10_STAT_port_rx_128_to_255) | \
1619 (1ULL << EF10_STAT_port_rx_256_to_511) | \
1620 (1ULL << EF10_STAT_port_rx_512_to_1023) |\
1621 (1ULL << EF10_STAT_port_rx_1024_to_15xx) |\
1622 (1ULL << EF10_STAT_port_rx_15xx_to_jumbo) |\
1623 (1ULL << EF10_STAT_port_rx_gtjumbo) | \
1624 (1ULL << EF10_STAT_port_rx_bad_gtjumbo) |\
1625 (1ULL << EF10_STAT_port_rx_overflow) | \
1626 (1ULL << EF10_STAT_port_rx_nodesc_drops) |\
e4d112e4
EC		 1627 (1ULL << GENERIC_STAT_rx_nodesc_trunc) | \
1628 (1ULL << GENERIC_STAT_rx_noskb_drops))
8127d661 1629
69b365c3
EC		 1630/* On 7000 series NICs, these statistics are only provided by the 10G MAC.
1631 * For a 10G/40G switchable port we do not expose these because they might
1632 * not include all the packets they should.
1633 * On 8000 series NICs these statistics are always provided.
8127d661 1634 */
e80ca013
DP		 1635#define HUNT_10G_ONLY_STAT_MASK ((1ULL << EF10_STAT_port_tx_control) | \
1636 (1ULL << EF10_STAT_port_tx_lt64) | \
1637 (1ULL << EF10_STAT_port_tx_64) | \
1638 (1ULL << EF10_STAT_port_tx_65_to_127) |\
1639 (1ULL << EF10_STAT_port_tx_128_to_255) |\
1640 (1ULL << EF10_STAT_port_tx_256_to_511) |\
1641 (1ULL << EF10_STAT_port_tx_512_to_1023) |\
1642 (1ULL << EF10_STAT_port_tx_1024_to_15xx) |\
1643 (1ULL << EF10_STAT_port_tx_15xx_to_jumbo))
8127d661
BH		 1644
1645/* These statistics are only provided by the 40G MAC. For a 10G/40G
1646 * switchable port we do expose these because the errors will otherwise
1647 * be silent.
1648 */
e80ca013
DP		 1649#define HUNT_40G_EXTRA_STAT_MASK ((1ULL << EF10_STAT_port_rx_align_error) |\
1650 (1ULL << EF10_STAT_port_rx_length_error))
8127d661 1651
568d7a00
EC		 1652/* These statistics are only provided if the firmware supports the
1653 * capability PM_AND_RXDP_COUNTERS.
1654 */
1655#define HUNT_PM_AND_RXDP_STAT_MASK ( \
e80ca013
DP		 1656 (1ULL << EF10_STAT_port_rx_pm_trunc_bb_overflow) | \
1657 (1ULL << EF10_STAT_port_rx_pm_discard_bb_overflow) | \
1658 (1ULL << EF10_STAT_port_rx_pm_trunc_vfifo_full) | \
1659 (1ULL << EF10_STAT_port_rx_pm_discard_vfifo_full) | \
1660 (1ULL << EF10_STAT_port_rx_pm_trunc_qbb) | \
1661 (1ULL << EF10_STAT_port_rx_pm_discard_qbb) | \
1662 (1ULL << EF10_STAT_port_rx_pm_discard_mapping) | \
1663 (1ULL << EF10_STAT_port_rx_dp_q_disabled_packets) | \
1664 (1ULL << EF10_STAT_port_rx_dp_di_dropped_packets) | \
1665 (1ULL << EF10_STAT_port_rx_dp_streaming_packets) | \
1666 (1ULL << EF10_STAT_port_rx_dp_hlb_fetch) | \
1667 (1ULL << EF10_STAT_port_rx_dp_hlb_wait))
568d7a00 1668
4bae913b 1669static u64 efx_ef10_raw_stat_mask(struct efx_nic *efx)
8127d661 1670{
4bae913b 1671 u64 raw_mask = HUNT_COMMON_STAT_MASK;
8127d661 1672 u32 port_caps = efx_mcdi_phy_get_caps(efx);
568d7a00 1673 struct efx_ef10_nic_data *nic_data = efx->nic_data;
8127d661 1674
3c36a2ad
DP		 1675 if (!(efx->mcdi->fn_flags &
1676 1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL))
1677 return 0;
1678
69b365c3 1679 if (port_caps & (1 << MC_CMD_PHY_CAP_40000FDX_LBN)) {
4bae913b 1680 raw_mask |= HUNT_40G_EXTRA_STAT_MASK;
69b365c3
EC		 1681 /* 8000 series have everything even at 40G */
1682 if (nic_data->datapath_caps2 &
1683 (1 << MC_CMD_GET_CAPABILITIES_V2_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN))
1684 raw_mask |= HUNT_10G_ONLY_STAT_MASK;
1685 } else {
4bae913b 1686 raw_mask |= HUNT_10G_ONLY_STAT_MASK;
69b365c3 1687 }
568d7a00
EC		 1688
1689 if (nic_data->datapath_caps &
1690 (1 << MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN))
1691 raw_mask |= HUNT_PM_AND_RXDP_STAT_MASK;
1692
4bae913b
EC		 1693 return raw_mask;
1694}
1695
1696static void efx_ef10_get_stat_mask(struct efx_nic *efx, unsigned long *mask)
1697{
d94619cd 1698 struct efx_ef10_nic_data *nic_data = efx->nic_data;
3c36a2ad
DP		 1699 u64 raw_mask[2];
1700
1701 raw_mask[0] = efx_ef10_raw_stat_mask(efx);
1702
d94619cd
DP		 1703 /* Only show vadaptor stats when EVB capability is present */
1704 if (nic_data->datapath_caps &
1705 (1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN)) {
1706 raw_mask[0] |= ~((1ULL << EF10_STAT_rx_unicast) - 1);
1707 raw_mask[1] = (1ULL << (EF10_STAT_COUNT - 63)) - 1;
1708 } else {
1709 raw_mask[1] = 0;
1710 }
4bae913b
EC		 1711
1712#if BITS_PER_LONG == 64
e70c70c3 1713 BUILD_BUG_ON(BITS_TO_LONGS(EF10_STAT_COUNT) != 2);
3c36a2ad
DP		 1714 mask[0] = raw_mask[0];
1715 mask[1] = raw_mask[1];
4bae913b 1716#else
e70c70c3 1717 BUILD_BUG_ON(BITS_TO_LONGS(EF10_STAT_COUNT) != 3);
3c36a2ad
DP		 1718 mask[0] = raw_mask[0] & 0xffffffff;
1719 mask[1] = raw_mask[0] >> 32;
1720 mask[2] = raw_mask[1] & 0xffffffff;
4bae913b 1721#endif
8127d661
BH		 1722}
1723
1724static size_t efx_ef10_describe_stats(struct efx_nic *efx, u8 *names)
1725{
4bae913b
EC		 1726 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1727
1728 efx_ef10_get_stat_mask(efx, mask);
8127d661 1729 return efx_nic_describe_stats(efx_ef10_stat_desc, EF10_STAT_COUNT,
4bae913b 1730 mask, names);
8127d661
BH		 1731}
1732
d7788196
DP		 1733static size_t efx_ef10_update_stats_common(struct efx_nic *efx, u64 *full_stats,
1734 struct rtnl_link_stats64 *core_stats)
1735{
1736 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1737 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1738 u64 *stats = nic_data->stats;
1739 size_t stats_count = 0, index;
1740
1741 efx_ef10_get_stat_mask(efx, mask);
1742
1743 if (full_stats) {
1744 for_each_set_bit(index, mask, EF10_STAT_COUNT) {
1745 if (efx_ef10_stat_desc[index].name) {
1746 *full_stats++ = stats[index];
1747 ++stats_count;
1748 }
1749 }
1750 }
1751
fbe4307e
BK		 1752 if (!core_stats)
1753 return stats_count;
1754
1755 if (nic_data->datapath_caps &
1756 1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN) {
1757 /* Use vadaptor stats. */
0fc95fca
DP		 1758 core_stats->rx_packets = stats[EF10_STAT_rx_unicast] +
1759 stats[EF10_STAT_rx_multicast] +
1760 stats[EF10_STAT_rx_broadcast];
1761 core_stats->tx_packets = stats[EF10_STAT_tx_unicast] +
1762 stats[EF10_STAT_tx_multicast] +
1763 stats[EF10_STAT_tx_broadcast];
1764 core_stats->rx_bytes = stats[EF10_STAT_rx_unicast_bytes] +
1765 stats[EF10_STAT_rx_multicast_bytes] +
1766 stats[EF10_STAT_rx_broadcast_bytes];
1767 core_stats->tx_bytes = stats[EF10_STAT_tx_unicast_bytes] +
1768 stats[EF10_STAT_tx_multicast_bytes] +
1769 stats[EF10_STAT_tx_broadcast_bytes];
1770 core_stats->rx_dropped = stats[GENERIC_STAT_rx_nodesc_trunc] +
d7788196 1771 stats[GENERIC_STAT_rx_noskb_drops];
0fc95fca
DP		 1772 core_stats->multicast = stats[EF10_STAT_rx_multicast];
1773 core_stats->rx_crc_errors = stats[EF10_STAT_rx_bad];
1774 core_stats->rx_fifo_errors = stats[EF10_STAT_rx_overflow];
1775 core_stats->rx_errors = core_stats->rx_crc_errors;
1776 core_stats->tx_errors = stats[EF10_STAT_tx_bad];
fbe4307e
BK		 1777 } else {
1778 /* Use port stats. */
1779 core_stats->rx_packets = stats[EF10_STAT_port_rx_packets];
1780 core_stats->tx_packets = stats[EF10_STAT_port_tx_packets];
1781 core_stats->rx_bytes = stats[EF10_STAT_port_rx_bytes];
1782 core_stats->tx_bytes = stats[EF10_STAT_port_tx_bytes];
1783 core_stats->rx_dropped = stats[EF10_STAT_port_rx_nodesc_drops] +
1784 stats[GENERIC_STAT_rx_nodesc_trunc] +
1785 stats[GENERIC_STAT_rx_noskb_drops];
1786 core_stats->multicast = stats[EF10_STAT_port_rx_multicast];
1787 core_stats->rx_length_errors =
1788 stats[EF10_STAT_port_rx_gtjumbo] +
1789 stats[EF10_STAT_port_rx_length_error];
1790 core_stats->rx_crc_errors = stats[EF10_STAT_port_rx_bad];
1791 core_stats->rx_frame_errors =
1792 stats[EF10_STAT_port_rx_align_error];
1793 core_stats->rx_fifo_errors = stats[EF10_STAT_port_rx_overflow];
1794 core_stats->rx_errors = (core_stats->rx_length_errors +
1795 core_stats->rx_crc_errors +
1796 core_stats->rx_frame_errors);
d7788196
DP		 1797 }
1798
1799 return stats_count;
1800}
1801
1802static int efx_ef10_try_update_nic_stats_pf(struct efx_nic *efx)
8127d661
BH		 1803{
1804 struct efx_ef10_nic_data *nic_data = efx->nic_data;
4bae913b 1805 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
8127d661
BH		 1806 __le64 generation_start, generation_end;
1807 u64 *stats = nic_data->stats;
1808 __le64 *dma_stats;
1809
4bae913b
EC		 1810 efx_ef10_get_stat_mask(efx, mask);
1811
8127d661 1812 dma_stats = efx->stats_buffer.addr;
8127d661
BH		 1813
1814 generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
1815 if (generation_end == EFX_MC_STATS_GENERATION_INVALID)
1816 return 0;
1817 rmb();
4bae913b 1818 efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask,
8127d661 1819 stats, efx->stats_buffer.addr, false);
d546a893 1820 rmb();
8127d661
BH		 1821 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
1822 if (generation_end != generation_start)
1823 return -EAGAIN;
1824
1825 /* Update derived statistics */
e80ca013
DP		 1826 efx_nic_fix_nodesc_drop_stat(efx,
1827 &stats[EF10_STAT_port_rx_nodesc_drops]);
1828 stats[EF10_STAT_port_rx_good_bytes] =
1829 stats[EF10_STAT_port_rx_bytes] -
1830 stats[EF10_STAT_port_rx_bytes_minus_good_bytes];
1831 efx_update_diff_stat(&stats[EF10_STAT_port_rx_bad_bytes],
1832 stats[EF10_STAT_port_rx_bytes_minus_good_bytes]);
e4d112e4 1833 efx_update_sw_stats(efx, stats);
8127d661
BH		 1834 return 0;
1835}
1836
1837
d7788196
DP		 1838static size_t efx_ef10_update_stats_pf(struct efx_nic *efx, u64 *full_stats,
1839 struct rtnl_link_stats64 *core_stats)
8127d661 1840{
8127d661
BH		 1841 int retry;
1842
1843 /* If we're unlucky enough to read statistics during the DMA, wait
1844 * up to 10ms for it to finish (typically takes <500us)
1845 */
1846 for (retry = 0; retry < 100; ++retry) {
d7788196 1847 if (efx_ef10_try_update_nic_stats_pf(efx) == 0)
8127d661
BH		 1848 break;
1849 udelay(100);
1850 }
1851
d7788196
DP		 1852 return efx_ef10_update_stats_common(efx, full_stats, core_stats);
1853}
8127d661 1854
d7788196
DP		 1855static int efx_ef10_try_update_nic_stats_vf(struct efx_nic *efx)
1856{
1857 MCDI_DECLARE_BUF(inbuf, MC_CMD_MAC_STATS_IN_LEN);
1858 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1859 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1860 __le64 generation_start, generation_end;
1861 u64 *stats = nic_data->stats;
1862 u32 dma_len = MC_CMD_MAC_NSTATS * sizeof(u64);
1863 struct efx_buffer stats_buf;
1864 __le64 *dma_stats;
1865 int rc;
1866
f00bf230
DP		 1867 spin_unlock_bh(&efx->stats_lock);
1868
1869 if (in_interrupt()) {
1870 /* If in atomic context, cannot update stats. Just update the
1871 * software stats and return so the caller can continue.
1872 */
1873 spin_lock_bh(&efx->stats_lock);
1874 efx_update_sw_stats(efx, stats);
1875 return 0;
1876 }
1877
d7788196
DP		 1878 efx_ef10_get_stat_mask(efx, mask);
1879
1880 rc = efx_nic_alloc_buffer(efx, &stats_buf, dma_len, GFP_ATOMIC);
f00bf230
DP		 1881 if (rc) {
1882 spin_lock_bh(&efx->stats_lock);
d7788196 1883 return rc;
f00bf230 1884 }
d7788196
DP		 1885
1886 dma_stats = stats_buf.addr;
1887 dma_stats[MC_CMD_MAC_GENERATION_END] = EFX_MC_STATS_GENERATION_INVALID;
1888
1889 MCDI_SET_QWORD(inbuf, MAC_STATS_IN_DMA_ADDR, stats_buf.dma_addr);
1890 MCDI_POPULATE_DWORD_1(inbuf, MAC_STATS_IN_CMD,
0fc95fca 1891 MAC_STATS_IN_DMA, 1);
d7788196
DP		 1892 MCDI_SET_DWORD(inbuf, MAC_STATS_IN_DMA_LEN, dma_len);
1893 MCDI_SET_DWORD(inbuf, MAC_STATS_IN_PORT_ID, EVB_PORT_ID_ASSIGNED);
1894
6dd4859b
DP		 1895 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_MAC_STATS, inbuf, sizeof(inbuf),
1896 NULL, 0, NULL);
d7788196 1897 spin_lock_bh(&efx->stats_lock);
6dd4859b
DP		 1898 if (rc) {
1899 /* Expect ENOENT if DMA queues have not been set up */
1900 if (rc != -ENOENT || atomic_read(&efx->active_queues))
1901 efx_mcdi_display_error(efx, MC_CMD_MAC_STATS,
1902 sizeof(inbuf), NULL, 0, rc);
d7788196 1903 goto out;
6dd4859b 1904 }
d7788196
DP		 1905
1906 generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
0fc95fca
DP		 1907 if (generation_end == EFX_MC_STATS_GENERATION_INVALID) {
1908 WARN_ON_ONCE(1);
d7788196 1909 goto out;
0fc95fca 1910 }
d7788196
DP		 1911 rmb();
1912 efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask,
1913 stats, stats_buf.addr, false);
1914 rmb();
1915 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
1916 if (generation_end != generation_start) {
1917 rc = -EAGAIN;
1918 goto out;
8127d661
BH		 1919 }
1920
d7788196
DP		 1921 efx_update_sw_stats(efx, stats);
1922out:
1923 efx_nic_free_buffer(efx, &stats_buf);
1924 return rc;
1925}
1926
1927static size_t efx_ef10_update_stats_vf(struct efx_nic *efx, u64 *full_stats,
1928 struct rtnl_link_stats64 *core_stats)
1929{
1930 if (efx_ef10_try_update_nic_stats_vf(efx))
1931 return 0;
1932
1933 return efx_ef10_update_stats_common(efx, full_stats, core_stats);
8127d661
BH		 1934}
1935
1936static void efx_ef10_push_irq_moderation(struct efx_channel *channel)
1937{
1938 struct efx_nic *efx = channel->efx;
539de7c5 1939 unsigned int mode, usecs;
8127d661
BH		 1940 efx_dword_t timer_cmd;
1941
539de7c5 1942 if (channel->irq_moderation_us) {
8127d661 1943 mode = 3;
539de7c5 1944 usecs = channel->irq_moderation_us;
8127d661
BH		 1945 } else {
1946 mode = 0;
539de7c5 1947 usecs = 0;
8127d661
BH		 1948 }
1949
539de7c5
BK		 1950 if (EFX_EF10_WORKAROUND_61265(efx)) {
1951 MCDI_DECLARE_BUF(inbuf, MC_CMD_SET_EVQ_TMR_IN_LEN);
1952 unsigned int ns = usecs * 1000;
1953
1954 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_INSTANCE,
1955 channel->channel);
1956 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_LOAD_REQ_NS, ns);
1957 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_RELOAD_REQ_NS, ns);
1958 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_MODE, mode);
1959
1960 efx_mcdi_rpc_async(efx, MC_CMD_SET_EVQ_TMR,
1961 inbuf, sizeof(inbuf), 0, NULL, 0);
1962 } else if (EFX_EF10_WORKAROUND_35388(efx)) {
1963 unsigned int ticks = efx_usecs_to_ticks(efx, usecs);
1964
8127d661
BH		 1965 EFX_POPULATE_DWORD_3(timer_cmd, ERF_DD_EVQ_IND_TIMER_FLAGS,
1966 EFE_DD_EVQ_IND_TIMER_FLAGS,
1967 ERF_DD_EVQ_IND_TIMER_MODE, mode,
539de7c5 1968 ERF_DD_EVQ_IND_TIMER_VAL, ticks);
8127d661
BH		 1969 efx_writed_page(efx, &timer_cmd, ER_DD_EVQ_INDIRECT,
1970 channel->channel);
1971 } else {
539de7c5
BK		 1972 unsigned int ticks = efx_usecs_to_ticks(efx, usecs);
1973
8127d661 1974 EFX_POPULATE_DWORD_2(timer_cmd, ERF_DZ_TC_TIMER_MODE, mode,
539de7c5 1975 ERF_DZ_TC_TIMER_VAL, ticks);
8127d661
BH		 1976 efx_writed_page(efx, &timer_cmd, ER_DZ_EVQ_TMR,
1977 channel->channel);
1978 }
1979}
1980
02246a7f
SS		 1981static void efx_ef10_get_wol_vf(struct efx_nic *efx,
1982 struct ethtool_wolinfo *wol) {}
1983
1984static int efx_ef10_set_wol_vf(struct efx_nic *efx, u32 type)
1985{
1986 return -EOPNOTSUPP;
1987}
1988
8127d661
BH		 1989static void efx_ef10_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
1990{
1991 wol->supported = 0;
1992 wol->wolopts = 0;
1993 memset(&wol->sopass, 0, sizeof(wol->sopass));
1994}
1995
1996static int efx_ef10_set_wol(struct efx_nic *efx, u32 type)
1997{
1998 if (type != 0)
1999 return -EINVAL;
2000 return 0;
2001}
2002
2003static void efx_ef10_mcdi_request(struct efx_nic *efx,
2004 const efx_dword_t *hdr, size_t hdr_len,
2005 const efx_dword_t *sdu, size_t sdu_len)
2006{
2007 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2008 u8 *pdu = nic_data->mcdi_buf.addr;
2009
2010 memcpy(pdu, hdr, hdr_len);
2011 memcpy(pdu + hdr_len, sdu, sdu_len);
2012 wmb();
2013
2014 /* The hardware provides 'low' and 'high' (doorbell) registers
2015 * for passing the 64-bit address of an MCDI request to
2016 * firmware. However the dwords are swapped by firmware. The
2017 * least significant bits of the doorbell are then 0 for all
2018 * MCDI requests due to alignment.
2019 */
2020 _efx_writed(efx, cpu_to_le32((u64)nic_data->mcdi_buf.dma_addr >> 32),
2021 ER_DZ_MC_DB_LWRD);
2022 _efx_writed(efx, cpu_to_le32((u32)nic_data->mcdi_buf.dma_addr),
2023 ER_DZ_MC_DB_HWRD);
2024}
2025
2026static bool efx_ef10_mcdi_poll_response(struct efx_nic *efx)
2027{
2028 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2029 const efx_dword_t hdr = *(const efx_dword_t *)nic_data->mcdi_buf.addr;
2030
2031 rmb();
2032 return EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE);
2033}
2034
2035static void
2036efx_ef10_mcdi_read_response(struct efx_nic *efx, efx_dword_t *outbuf,
2037 size_t offset, size_t outlen)
2038{
2039 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2040 const u8 *pdu = nic_data->mcdi_buf.addr;
2041
2042 memcpy(outbuf, pdu + offset, outlen);
2043}
2044
c577e59e
DP		 2045static void efx_ef10_mcdi_reboot_detected(struct efx_nic *efx)
2046{
2047 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2048
2049 /* All our allocations have been reset */
2050 efx_ef10_reset_mc_allocations(efx);
2051
2052 /* The datapath firmware might have been changed */
2053 nic_data->must_check_datapath_caps = true;
2054
2055 /* MAC statistics have been cleared on the NIC; clear the local
2056 * statistic that we update with efx_update_diff_stat().
2057 */
2058 nic_data->stats[EF10_STAT_port_rx_bad_bytes] = 0;
2059}
2060
8127d661
BH		 2061static int efx_ef10_mcdi_poll_reboot(struct efx_nic *efx)
2062{
2063 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2064 int rc;
2065
2066 rc = efx_ef10_get_warm_boot_count(efx);
2067 if (rc < 0) {
2068 /* The firmware is presumably in the process of
2069 * rebooting. However, we are supposed to report each
2070 * reboot just once, so we must only do that once we
2071 * can read and store the updated warm boot count.
2072 */
2073 return 0;
2074 }
2075
2076 if (rc == nic_data->warm_boot_count)
2077 return 0;
2078
2079 nic_data->warm_boot_count = rc;
c577e59e 2080 efx_ef10_mcdi_reboot_detected(efx);
869070c5 2081
8127d661
BH		 2082 return -EIO;
2083}
2084
2085/* Handle an MSI interrupt
2086 *
2087 * Handle an MSI hardware interrupt. This routine schedules event
2088 * queue processing. No interrupt acknowledgement cycle is necessary.
2089 * Also, we never need to check that the interrupt is for us, since
2090 * MSI interrupts cannot be shared.
2091 */
2092static irqreturn_t efx_ef10_msi_interrupt(int irq, void *dev_id)
2093{
2094 struct efx_msi_context *context = dev_id;
2095 struct efx_nic *efx = context->efx;
2096
2097 netif_vdbg(efx, intr, efx->net_dev,
2098 "IRQ %d on CPU %d\n", irq, raw_smp_processor_id());
2099
6aa7de05 2100 if (likely(READ_ONCE(efx->irq_soft_enabled))) {
8127d661
BH		 2101 /* Note test interrupts */
2102 if (context->index == efx->irq_level)
2103 efx->last_irq_cpu = raw_smp_processor_id();
2104
2105 /* Schedule processing of the channel */
2106 efx_schedule_channel_irq(efx->channel[context->index]);
2107 }
2108
2109 return IRQ_HANDLED;
2110}
2111
2112static irqreturn_t efx_ef10_legacy_interrupt(int irq, void *dev_id)
2113{
2114 struct efx_nic *efx = dev_id;
6aa7de05 2115 bool soft_enabled = READ_ONCE(efx->irq_soft_enabled);
8127d661
BH		 2116 struct efx_channel *channel;
2117 efx_dword_t reg;
2118 u32 queues;
2119
2120 /* Read the ISR which also ACKs the interrupts */
2121 efx_readd(efx, &reg, ER_DZ_BIU_INT_ISR);
2122 queues = EFX_DWORD_FIELD(reg, ERF_DZ_ISR_REG);
2123
2124 if (queues == 0)
2125 return IRQ_NONE;
2126
2127 if (likely(soft_enabled)) {
2128 /* Note test interrupts */
2129 if (queues & (1U << efx->irq_level))
2130 efx->last_irq_cpu = raw_smp_processor_id();
2131
2132 efx_for_each_channel(channel, efx) {
2133 if (queues & 1)
2134 efx_schedule_channel_irq(channel);
2135 queues >>= 1;
2136 }
2137 }
2138
2139 netif_vdbg(efx, intr, efx->net_dev,
2140 "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
2141 irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
2142
2143 return IRQ_HANDLED;
2144}
2145
942e298e 2146static int efx_ef10_irq_test_generate(struct efx_nic *efx)
8127d661
BH		 2147{
2148 MCDI_DECLARE_BUF(inbuf, MC_CMD_TRIGGER_INTERRUPT_IN_LEN);
2149
942e298e
JC		 2150 if (efx_mcdi_set_workaround(efx, MC_CMD_WORKAROUND_BUG41750, true,
2151 NULL) == 0)
2152 return -ENOTSUPP;
2153
8127d661
BH		 2154 BUILD_BUG_ON(MC_CMD_TRIGGER_INTERRUPT_OUT_LEN != 0);
2155
2156 MCDI_SET_DWORD(inbuf, TRIGGER_INTERRUPT_IN_INTR_LEVEL, efx->irq_level);
942e298e 2157 return efx_mcdi_rpc(efx, MC_CMD_TRIGGER_INTERRUPT,
8127d661
BH		 2158 inbuf, sizeof(inbuf), NULL, 0, NULL);
2159}
2160
2161static int efx_ef10_tx_probe(struct efx_tx_queue *tx_queue)
2162{
2163 return efx_nic_alloc_buffer(tx_queue->efx, &tx_queue->txd.buf,
2164 (tx_queue->ptr_mask + 1) *
2165 sizeof(efx_qword_t),
2166 GFP_KERNEL);
2167}
2168
2169/* This writes to the TX_DESC_WPTR and also pushes data */
2170static inline void efx_ef10_push_tx_desc(struct efx_tx_queue *tx_queue,
2171 const efx_qword_t *txd)
2172{
2173 unsigned int write_ptr;
2174 efx_oword_t reg;
2175
2176 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
2177 EFX_POPULATE_OWORD_1(reg, ERF_DZ_TX_DESC_WPTR, write_ptr);
2178 reg.qword[0] = *txd;
2179 efx_writeo_page(tx_queue->efx, &reg,
2180 ER_DZ_TX_DESC_UPD, tx_queue->queue);
2181}
2182
e9117e50
BK		 2183/* Add Firmware-Assisted TSO v2 option descriptors to a queue.
2184 */
2185static int efx_ef10_tx_tso_desc(struct efx_tx_queue *tx_queue,
2186 struct sk_buff *skb,
2187 bool *data_mapped)
2188{
2189 struct efx_tx_buffer *buffer;
2190 struct tcphdr *tcp;
2191 struct iphdr *ip;
2192
2193 u16 ipv4_id;
2194 u32 seqnum;
2195 u32 mss;
2196
e01b16a7 2197 EFX_WARN_ON_ONCE_PARANOID(tx_queue->tso_version != 2);
e9117e50
BK		 2198
2199 mss = skb_shinfo(skb)->gso_size;
2200
2201 if (unlikely(mss < 4)) {
2202 WARN_ONCE(1, "MSS of %u is too small for TSO v2\n", mss);
2203 return -EINVAL;
2204 }
2205
2206 ip = ip_hdr(skb);
2207 if (ip->version == 4) {
2208 /* Modify IPv4 header if needed. */
2209 ip->tot_len = 0;
2210 ip->check = 0;
6d43131c 2211 ipv4_id = ntohs(ip->id);
e9117e50
BK		 2212 } else {
2213 /* Modify IPv6 header if needed. */
2214 struct ipv6hdr *ipv6 = ipv6_hdr(skb);
2215
2216 ipv6->payload_len = 0;
2217 ipv4_id = 0;
2218 }
2219
2220 tcp = tcp_hdr(skb);
2221 seqnum = ntohl(tcp->seq);
2222
2223 buffer = efx_tx_queue_get_insert_buffer(tx_queue);
2224
2225 buffer->flags = EFX_TX_BUF_OPTION;
2226 buffer->len = 0;
2227 buffer->unmap_len = 0;
2228 EFX_POPULATE_QWORD_5(buffer->option,
2229 ESF_DZ_TX_DESC_IS_OPT, 1,
2230 ESF_DZ_TX_OPTION_TYPE, ESE_DZ_TX_OPTION_DESC_TSO,
2231 ESF_DZ_TX_TSO_OPTION_TYPE,
2232 ESE_DZ_TX_TSO_OPTION_DESC_FATSO2A,
2233 ESF_DZ_TX_TSO_IP_ID, ipv4_id,
2234 ESF_DZ_TX_TSO_TCP_SEQNO, seqnum
2235 );
2236 ++tx_queue->insert_count;
2237
2238 buffer = efx_tx_queue_get_insert_buffer(tx_queue);
2239
2240 buffer->flags = EFX_TX_BUF_OPTION;
2241 buffer->len = 0;
2242 buffer->unmap_len = 0;
2243 EFX_POPULATE_QWORD_4(buffer->option,
2244 ESF_DZ_TX_DESC_IS_OPT, 1,
2245 ESF_DZ_TX_OPTION_TYPE, ESE_DZ_TX_OPTION_DESC_TSO,
2246 ESF_DZ_TX_TSO_OPTION_TYPE,
2247 ESE_DZ_TX_TSO_OPTION_DESC_FATSO2B,
2248 ESF_DZ_TX_TSO_TCP_MSS, mss
2249 );
2250 ++tx_queue->insert_count;
2251
2252 return 0;
2253}
2254
46d1efd8
EC		 2255static u32 efx_ef10_tso_versions(struct efx_nic *efx)
2256{
2257 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2258 u32 tso_versions = 0;
2259
2260 if (nic_data->datapath_caps &
2261 (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN))
2262 tso_versions |= BIT(1);
2263 if (nic_data->datapath_caps2 &
2264 (1 << MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_LBN))
2265 tso_versions |= BIT(2);
2266 return tso_versions;
2267}
2268
8127d661
BH		 2269static void efx_ef10_tx_init(struct efx_tx_queue *tx_queue)
2270{
2271 MCDI_DECLARE_BUF(inbuf, MC_CMD_INIT_TXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
2272 EFX_BUF_SIZE));
8127d661
BH		 2273 bool csum_offload = tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD;
2274 size_t entries = tx_queue->txd.buf.len / EFX_BUF_SIZE;
2275 struct efx_channel *channel = tx_queue->channel;
2276 struct efx_nic *efx = tx_queue->efx;
45b2449e 2277 struct efx_ef10_nic_data *nic_data = efx->nic_data;
e9117e50 2278 bool tso_v2 = false;
aa09a3da 2279 size_t inlen;
8127d661
BH		 2280 dma_addr_t dma_addr;
2281 efx_qword_t *txd;
2282 int rc;
2283 int i;
aa09a3da 2284 BUILD_BUG_ON(MC_CMD_INIT_TXQ_OUT_LEN != 0);
8127d661 2285
e9117e50
BK		 2286 /* TSOv2 is a limited resource that can only be configured on a limited
2287 * number of queues. TSO without checksum offload is not really a thing,
2288 * so we only enable it for those queues.
e9117e50
BK		 2289 */
2290 if (csum_offload && (nic_data->datapath_caps2 &
2291 (1 << MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_LBN))) {
2292 tso_v2 = true;
2293 netif_dbg(efx, hw, efx->net_dev, "Using TSOv2 for channel %u\n",
2294 channel->channel);
2295 }
2296
8127d661
BH		 2297 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_SIZE, tx_queue->ptr_mask + 1);
2298 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_TARGET_EVQ, channel->channel);
2299 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_LABEL, tx_queue->queue);
2300 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_INSTANCE, tx_queue->queue);
8127d661 2301 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_OWNER_ID, 0);
45b2449e 2302 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_PORT_ID, nic_data->vport_id);
8127d661
BH		 2303
2304 dma_addr = tx_queue->txd.buf.dma_addr;
2305
2306 netif_dbg(efx, hw, efx->net_dev, "pushing TXQ %d. %zu entries (%llx)\n",
2307 tx_queue->queue, entries, (u64)dma_addr);
2308
2309 for (i = 0; i < entries; ++i) {
2310 MCDI_SET_ARRAY_QWORD(inbuf, INIT_TXQ_IN_DMA_ADDR, i, dma_addr);
2311 dma_addr += EFX_BUF_SIZE;
2312 }
2313
2314 inlen = MC_CMD_INIT_TXQ_IN_LEN(entries);
2315
e638ee1d
EC		 2316 do {
2317 MCDI_POPULATE_DWORD_3(inbuf, INIT_TXQ_IN_FLAGS,
2318 /* This flag was removed from mcdi_pcol.h for
2319 * the non-_EXT version of INIT_TXQ. However,
2320 * firmware still honours it.
2321 */
2322 INIT_TXQ_EXT_IN_FLAG_TSOV2_EN, tso_v2,
2323 INIT_TXQ_IN_FLAG_IP_CSUM_DIS, !csum_offload,
2324 INIT_TXQ_IN_FLAG_TCP_CSUM_DIS, !csum_offload);
2325
2326 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_INIT_TXQ, inbuf, inlen,
2327 NULL, 0, NULL);
2328 if (rc == -ENOSPC && tso_v2) {
2329 /* Retry without TSOv2 if we're short on contexts. */
2330 tso_v2 = false;
2331 netif_warn(efx, probe, efx->net_dev,
2332 "TSOv2 context not available to segment in hardware. TCP performance may be reduced.\n");
2333 } else if (rc) {
2334 efx_mcdi_display_error(efx, MC_CMD_INIT_TXQ,
2335 MC_CMD_INIT_TXQ_EXT_IN_LEN,
2336 NULL, 0, rc);
2337 goto fail;
2338 }
2339 } while (rc);
8127d661
BH		 2340
2341 /* A previous user of this TX queue might have set us up the
2342 * bomb by writing a descriptor to the TX push collector but
2343 * not the doorbell. (Each collector belongs to a port, not a
2344 * queue or function, so cannot easily be reset.) We must
2345 * attempt to push a no-op descriptor in its place.
2346 */
2347 tx_queue->buffer[0].flags = EFX_TX_BUF_OPTION;
2348 tx_queue->insert_count = 1;
2349 txd = efx_tx_desc(tx_queue, 0);
2350 EFX_POPULATE_QWORD_4(*txd,
2351 ESF_DZ_TX_DESC_IS_OPT, true,
2352 ESF_DZ_TX_OPTION_TYPE,
2353 ESE_DZ_TX_OPTION_DESC_CRC_CSUM,
2354 ESF_DZ_TX_OPTION_UDP_TCP_CSUM, csum_offload,
2355 ESF_DZ_TX_OPTION_IP_CSUM, csum_offload);
2356 tx_queue->write_count = 1;
93171b14 2357
e9117e50
BK		 2358 if (tso_v2) {
2359 tx_queue->handle_tso = efx_ef10_tx_tso_desc;
2360 tx_queue->tso_version = 2;
2361 } else if (nic_data->datapath_caps &
2362 (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN)) {
93171b14
BK		 2363 tx_queue->tso_version = 1;
2364 }
2365
8127d661
BH		 2366 wmb();
2367 efx_ef10_push_tx_desc(tx_queue, txd);
2368
2369 return;
2370
2371fail:
48ce5634
BH		 2372 netdev_WARN(efx->net_dev, "failed to initialise TXQ %d\n",
2373 tx_queue->queue);
8127d661
BH		 2374}
2375
2376static void efx_ef10_tx_fini(struct efx_tx_queue *tx_queue)
2377{
2378 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_TXQ_IN_LEN);
aa09a3da 2379 MCDI_DECLARE_BUF_ERR(outbuf);
8127d661
BH		 2380 struct efx_nic *efx = tx_queue->efx;
2381 size_t outlen;
2382 int rc;
2383
2384 MCDI_SET_DWORD(inbuf, FINI_TXQ_IN_INSTANCE,
2385 tx_queue->queue);
2386
1e0b8120 2387 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_TXQ, inbuf, sizeof(inbuf),
8127d661
BH		 2388 outbuf, sizeof(outbuf), &outlen);
2389
2390 if (rc && rc != -EALREADY)
2391 goto fail;
2392
2393 return;
2394
2395fail:
1e0b8120
EC		 2396 efx_mcdi_display_error(efx, MC_CMD_FINI_TXQ, MC_CMD_FINI_TXQ_IN_LEN,
2397 outbuf, outlen, rc);
8127d661
BH		 2398}
2399
2400static void efx_ef10_tx_remove(struct efx_tx_queue *tx_queue)
2401{
2402 efx_nic_free_buffer(tx_queue->efx, &tx_queue->txd.buf);
2403}
2404
2405/* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
2406static inline void efx_ef10_notify_tx_desc(struct efx_tx_queue *tx_queue)
2407{
2408 unsigned int write_ptr;
2409 efx_dword_t reg;
2410
2411 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
2412 EFX_POPULATE_DWORD_1(reg, ERF_DZ_TX_DESC_WPTR_DWORD, write_ptr);
2413 efx_writed_page(tx_queue->efx, &reg,
2414 ER_DZ_TX_DESC_UPD_DWORD, tx_queue->queue);
2415}
2416
e9117e50
BK		 2417#define EFX_EF10_MAX_TX_DESCRIPTOR_LEN 0x3fff
2418
2419static unsigned int efx_ef10_tx_limit_len(struct efx_tx_queue *tx_queue,
2420 dma_addr_t dma_addr, unsigned int len)
2421{
2422 if (len > EFX_EF10_MAX_TX_DESCRIPTOR_LEN) {
2423 /* If we need to break across multiple descriptors we should
2424 * stop at a page boundary. This assumes the length limit is
2425 * greater than the page size.
2426 */
2427 dma_addr_t end = dma_addr + EFX_EF10_MAX_TX_DESCRIPTOR_LEN;
2428
2429 BUILD_BUG_ON(EFX_EF10_MAX_TX_DESCRIPTOR_LEN < EFX_PAGE_SIZE);
2430 len = (end & (~(EFX_PAGE_SIZE - 1))) - dma_addr;
2431 }
2432
2433 return len;
2434}
2435
8127d661
BH		 2436static void efx_ef10_tx_write(struct efx_tx_queue *tx_queue)
2437{
2438 unsigned int old_write_count = tx_queue->write_count;
2439 struct efx_tx_buffer *buffer;
2440 unsigned int write_ptr;
2441 efx_qword_t *txd;
2442
b2663a4f
MH		 2443 tx_queue->xmit_more_available = false;
2444 if (unlikely(tx_queue->write_count == tx_queue->insert_count))
2445 return;
8127d661
BH		 2446
2447 do {
2448 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
2449 buffer = &tx_queue->buffer[write_ptr];
2450 txd = efx_tx_desc(tx_queue, write_ptr);
2451 ++tx_queue->write_count;
2452
2453 /* Create TX descriptor ring entry */
2454 if (buffer->flags & EFX_TX_BUF_OPTION) {
2455 *txd = buffer->option;
de1deff9
EC		 2456 if (EFX_QWORD_FIELD(*txd, ESF_DZ_TX_OPTION_TYPE) == 1)
2457 /* PIO descriptor */
2458 tx_queue->packet_write_count = tx_queue->write_count;
8127d661 2459 } else {
de1deff9 2460 tx_queue->packet_write_count = tx_queue->write_count;
8127d661
BH		 2461 BUILD_BUG_ON(EFX_TX_BUF_CONT != 1);
2462 EFX_POPULATE_QWORD_3(
2463 *txd,
2464 ESF_DZ_TX_KER_CONT,
2465 buffer->flags & EFX_TX_BUF_CONT,
2466 ESF_DZ_TX_KER_BYTE_CNT, buffer->len,
2467 ESF_DZ_TX_KER_BUF_ADDR, buffer->dma_addr);
2468 }
2469 } while (tx_queue->write_count != tx_queue->insert_count);
2470
2471 wmb(); /* Ensure descriptors are written before they are fetched */
2472
2473 if (efx_nic_may_push_tx_desc(tx_queue, old_write_count)) {
2474 txd = efx_tx_desc(tx_queue,
2475 old_write_count & tx_queue->ptr_mask);
2476 efx_ef10_push_tx_desc(tx_queue, txd);
2477 ++tx_queue->pushes;
2478 } else {
2479 efx_ef10_notify_tx_desc(tx_queue);
2480 }
2481}
2482
a33a4c73
EC		 2483#define RSS_MODE_HASH_ADDRS (1 << RSS_MODE_HASH_SRC_ADDR_LBN |\
2484 1 << RSS_MODE_HASH_DST_ADDR_LBN)
2485#define RSS_MODE_HASH_PORTS (1 << RSS_MODE_HASH_SRC_PORT_LBN |\
2486 1 << RSS_MODE_HASH_DST_PORT_LBN)
2487#define RSS_CONTEXT_FLAGS_DEFAULT (1 << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_LBN |\
2488 1 << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_LBN |\
2489 1 << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_LBN |\
2490 1 << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_LBN |\
2491 (RSS_MODE_HASH_ADDRS | RSS_MODE_HASH_PORTS) << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV4_RSS_MODE_LBN |\
2492 RSS_MODE_HASH_ADDRS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_LBN |\
2493 RSS_MODE_HASH_ADDRS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV4_RSS_MODE_LBN |\
2494 (RSS_MODE_HASH_ADDRS | RSS_MODE_HASH_PORTS) << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV6_RSS_MODE_LBN |\
2495 RSS_MODE_HASH_ADDRS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_LBN |\
2496 RSS_MODE_HASH_ADDRS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV6_RSS_MODE_LBN)
2497
2498static int efx_ef10_get_rss_flags(struct efx_nic *efx, u32 context, u32 *flags)
2499{
2500 /* Firmware had a bug (sfc bug 61952) where it would not actually
2501 * fill in the flags field in the response to MC_CMD_RSS_CONTEXT_GET_FLAGS.
2502 * This meant that it would always contain whatever was previously
2503 * in the MCDI buffer. Fortunately, all firmware versions with
2504 * this bug have the same default flags value for a newly-allocated
2505 * RSS context, and the only time we want to get the flags is just
2506 * after allocating. Moreover, the response has a 32-bit hole
2507 * where the context ID would be in the request, so we can use an
2508 * overlength buffer in the request and pre-fill the flags field
2509 * with what we believe the default to be. Thus if the firmware
2510 * has the bug, it will leave our pre-filled value in the flags
2511 * field of the response, and we will get the right answer.
2512 *
2513 * However, this does mean that this function should NOT be used if
2514 * the RSS context flags might not be their defaults - it is ONLY
2515 * reliably correct for a newly-allocated RSS context.
2516 */
2517 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_LEN);
2518 MCDI_DECLARE_BUF(outbuf, MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_LEN);
2519 size_t outlen;
2520 int rc;
2521
2522 /* Check we have a hole for the context ID */
2523 BUILD_BUG_ON(MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_LEN != MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_FLAGS_OFST);
2524 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_GET_FLAGS_IN_RSS_CONTEXT_ID, context);
2525 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_GET_FLAGS_OUT_FLAGS,
2526 RSS_CONTEXT_FLAGS_DEFAULT);
2527 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_GET_FLAGS, inbuf,
2528 sizeof(inbuf), outbuf, sizeof(outbuf), &outlen);
2529 if (rc == 0) {
2530 if (outlen < MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_LEN)
2531 rc = -EIO;
2532 else
2533 *flags = MCDI_DWORD(outbuf, RSS_CONTEXT_GET_FLAGS_OUT_FLAGS);
2534 }
2535 return rc;
2536}
2537
2538/* Attempt to enable 4-tuple UDP hashing on the specified RSS context.
2539 * If we fail, we just leave the RSS context at its default hash settings,
2540 * which is safe but may slightly reduce performance.
2541 * Defaults are 4-tuple for TCP and 2-tuple for UDP and other-IP, so we
2542 * just need to set the UDP ports flags (for both IP versions).
2543 */
2544static void efx_ef10_set_rss_flags(struct efx_nic *efx, u32 context)
2545{
2546 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_LEN);
2547 u32 flags;
2548
2549 BUILD_BUG_ON(MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT_LEN != 0);
2550
2551 if (efx_ef10_get_rss_flags(efx, context, &flags) != 0)
2552 return;
2553 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_SET_FLAGS_IN_RSS_CONTEXT_ID, context);
2554 flags |= RSS_MODE_HASH_PORTS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_LBN;
2555 flags |= RSS_MODE_HASH_PORTS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_LBN;
2556 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_SET_FLAGS_IN_FLAGS, flags);
b718c88a
EC		 2557 if (!efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_FLAGS, inbuf, sizeof(inbuf),
2558 NULL, 0, NULL))
2559 /* Succeeded, so UDP 4-tuple is now enabled */
2560 efx->rx_hash_udp_4tuple = true;
a33a4c73
EC		 2561}
2562
267c0157
JC		 2563static int efx_ef10_alloc_rss_context(struct efx_nic *efx, u32 *context,
2564 bool exclusive, unsigned *context_size)
8127d661
BH		 2565{
2566 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN);
2567 MCDI_DECLARE_BUF(outbuf, MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN);
45b2449e 2568 struct efx_ef10_nic_data *nic_data = efx->nic_data;
8127d661
BH		 2569 size_t outlen;
2570 int rc;
267c0157
JC		 2571 u32 alloc_type = exclusive ?
2572 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE :
2573 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED;
2574 unsigned rss_spread = exclusive ?
2575 efx->rss_spread :
2576 min(rounddown_pow_of_two(efx->rss_spread),
2577 EFX_EF10_MAX_SHARED_RSS_CONTEXT_SIZE);
2578
2579 if (!exclusive && rss_spread == 1) {
2580 *context = EFX_EF10_RSS_CONTEXT_INVALID;
2581 if (context_size)
2582 *context_size = 1;
2583 return 0;
2584 }
8127d661 2585
dcb4123c
JC		 2586 if (nic_data->datapath_caps &
2587 1 << MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_LBN)
2588 return -EOPNOTSUPP;
2589
8127d661 2590 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID,
45b2449e 2591 nic_data->vport_id);
267c0157
JC		 2592 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_TYPE, alloc_type);
2593 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_NUM_QUEUES, rss_spread);
8127d661
BH		 2594
2595 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_ALLOC, inbuf, sizeof(inbuf),
2596 outbuf, sizeof(outbuf), &outlen);
2597 if (rc != 0)
2598 return rc;
2599
2600 if (outlen < MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN)
2601 return -EIO;
2602
2603 *context = MCDI_DWORD(outbuf, RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID);
2604
267c0157
JC		 2605 if (context_size)
2606 *context_size = rss_spread;
2607
a33a4c73
EC		 2608 if (nic_data->datapath_caps &
2609 1 << MC_CMD_GET_CAPABILITIES_OUT_ADDITIONAL_RSS_MODES_LBN)
2610 efx_ef10_set_rss_flags(efx, *context);
2611
8127d661
BH		 2612 return 0;
2613}
2614
2615static void efx_ef10_free_rss_context(struct efx_nic *efx, u32 context)
2616{
2617 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_FREE_IN_LEN);
2618 int rc;
2619
2620 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID,
2621 context);
2622
2623 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_FREE, inbuf, sizeof(inbuf),
2624 NULL, 0, NULL);
2625 WARN_ON(rc != 0);
2626}
2627
267c0157 2628static int efx_ef10_populate_rss_table(struct efx_nic *efx, u32 context,
f74d1995 2629 const u32 *rx_indir_table, const u8 *key)
8127d661
BH		 2630{
2631 MCDI_DECLARE_BUF(tablebuf, MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN);
2632 MCDI_DECLARE_BUF(keybuf, MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN);
2633 int i, rc;
2634
2635 MCDI_SET_DWORD(tablebuf, RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID,
2636 context);
2637 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_indir_table) !=
2638 MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN);
2639
f74d1995
EC		 2640 /* This iterates over the length of efx->rx_indir_table, but copies
2641 * bytes from rx_indir_table. That's because the latter is a pointer
2642 * rather than an array, but should have the same length.
2643 * The efx->rx_hash_key loop below is similar.
2644 */
8127d661
BH		 2645 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); ++i)
2646 MCDI_PTR(tablebuf,
2647 RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE)[i] =
267c0157 2648 (u8) rx_indir_table[i];
8127d661
BH		 2649
2650 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_TABLE, tablebuf,
2651 sizeof(tablebuf), NULL, 0, NULL);
2652 if (rc != 0)
2653 return rc;
2654
2655 MCDI_SET_DWORD(keybuf, RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID,
2656 context);
2657 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_hash_key) !=
2658 MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN);
2659 for (i = 0; i < ARRAY_SIZE(efx->rx_hash_key); ++i)
f74d1995 2660 MCDI_PTR(keybuf, RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY)[i] = key[i];
8127d661
BH		 2661
2662 return efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_KEY, keybuf,
2663 sizeof(keybuf), NULL, 0, NULL);
2664}
2665
2666static void efx_ef10_rx_free_indir_table(struct efx_nic *efx)
2667{
2668 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2669
2670 if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID)
2671 efx_ef10_free_rss_context(efx, nic_data->rx_rss_context);
2672 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
2673}
2674
267c0157
JC		 2675static int efx_ef10_rx_push_shared_rss_config(struct efx_nic *efx,
2676 unsigned *context_size)
8127d661 2677{
267c0157 2678 u32 new_rx_rss_context;
8127d661 2679 struct efx_ef10_nic_data *nic_data = efx->nic_data;
267c0157
JC		 2680 int rc = efx_ef10_alloc_rss_context(efx, &new_rx_rss_context,
2681 false, context_size);
2682
2683 if (rc != 0)
2684 return rc;
8127d661 2685
267c0157
JC		 2686 nic_data->rx_rss_context = new_rx_rss_context;
2687 nic_data->rx_rss_context_exclusive = false;
2688 efx_set_default_rx_indir_table(efx);
2689 return 0;
2690}
8127d661 2691
267c0157 2692static int efx_ef10_rx_push_exclusive_rss_config(struct efx_nic *efx,
f74d1995
EC		 2693 const u32 *rx_indir_table,
2694 const u8 *key)
267c0157
JC		 2695{
2696 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2697 int rc;
2698 u32 new_rx_rss_context;
2699
2700 if (nic_data->rx_rss_context == EFX_EF10_RSS_CONTEXT_INVALID ||
2701 !nic_data->rx_rss_context_exclusive) {
2702 rc = efx_ef10_alloc_rss_context(efx, &new_rx_rss_context,
2703 true, NULL);
2704 if (rc == -EOPNOTSUPP)
2705 return rc;
2706 else if (rc != 0)
2707 goto fail1;
2708 } else {
2709 new_rx_rss_context = nic_data->rx_rss_context;
8127d661
BH		 2710 }
2711
267c0157 2712 rc = efx_ef10_populate_rss_table(efx, new_rx_rss_context,
f74d1995 2713 rx_indir_table, key);
8127d661 2714 if (rc != 0)
267c0157 2715 goto fail2;
8127d661 2716
267c0157
JC		 2717 if (nic_data->rx_rss_context != new_rx_rss_context)
2718 efx_ef10_rx_free_indir_table(efx);
2719 nic_data->rx_rss_context = new_rx_rss_context;
2720 nic_data->rx_rss_context_exclusive = true;
2721 if (rx_indir_table != efx->rx_indir_table)
2722 memcpy(efx->rx_indir_table, rx_indir_table,
2723 sizeof(efx->rx_indir_table));
f74d1995
EC		 2724 if (key != efx->rx_hash_key)
2725 memcpy(efx->rx_hash_key, key, efx->type->rx_hash_key_size);
2726
267c0157 2727 return 0;
8127d661 2728
267c0157
JC		 2729fail2:
2730 if (new_rx_rss_context != nic_data->rx_rss_context)
2731 efx_ef10_free_rss_context(efx, new_rx_rss_context);
2732fail1:
8127d661 2733 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
267c0157
JC		 2734 return rc;
2735}
2736
a707d188
EC		 2737static int efx_ef10_rx_pull_rss_config(struct efx_nic *efx)
2738{
2739 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2740 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_GET_TABLE_IN_LEN);
2741 MCDI_DECLARE_BUF(tablebuf, MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_LEN);
2742 MCDI_DECLARE_BUF(keybuf, MC_CMD_RSS_CONTEXT_GET_KEY_OUT_LEN);
2743 size_t outlen;
2744 int rc, i;
2745
2746 BUILD_BUG_ON(MC_CMD_RSS_CONTEXT_GET_TABLE_IN_LEN !=
2747 MC_CMD_RSS_CONTEXT_GET_KEY_IN_LEN);
2748
2749 if (nic_data->rx_rss_context == EFX_EF10_RSS_CONTEXT_INVALID)
2750 return -ENOENT;
2751
2752 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_GET_TABLE_IN_RSS_CONTEXT_ID,
2753 nic_data->rx_rss_context);
2754 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_indir_table) !=
2755 MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE_LEN);
2756 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_GET_TABLE, inbuf, sizeof(inbuf),
2757 tablebuf, sizeof(tablebuf), &outlen);
2758 if (rc != 0)
2759 return rc;
2760
2761 if (WARN_ON(outlen != MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_LEN))
2762 return -EIO;
2763
2764 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); i++)
2765 efx->rx_indir_table[i] = MCDI_PTR(tablebuf,
2766 RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE)[i];
2767
2768 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_GET_KEY_IN_RSS_CONTEXT_ID,
2769 nic_data->rx_rss_context);
2770 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_hash_key) !=
2771 MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN);
2772 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_GET_KEY, inbuf, sizeof(inbuf),
2773 keybuf, sizeof(keybuf), &outlen);
2774 if (rc != 0)
2775 return rc;
2776
2777 if (WARN_ON(outlen != MC_CMD_RSS_CONTEXT_GET_KEY_OUT_LEN))
2778 return -EIO;
2779
2780 for (i = 0; i < ARRAY_SIZE(efx->rx_hash_key); ++i)
2781 efx->rx_hash_key[i] = MCDI_PTR(
2782 keybuf, RSS_CONTEXT_GET_KEY_OUT_TOEPLITZ_KEY)[i];
2783
2784 return 0;
2785}
2786
267c0157 2787static int efx_ef10_pf_rx_push_rss_config(struct efx_nic *efx, bool user,
f74d1995
EC		 2788 const u32 *rx_indir_table,
2789 const u8 *key)
267c0157
JC		 2790{
2791 int rc;
2792
2793 if (efx->rss_spread == 1)
2794 return 0;
2795
f74d1995
EC		 2796 if (!key)
2797 key = efx->rx_hash_key;
2798
2799 rc = efx_ef10_rx_push_exclusive_rss_config(efx, rx_indir_table, key);
267c0157
JC		 2800
2801 if (rc == -ENOBUFS && !user) {
2802 unsigned context_size;
2803 bool mismatch = false;
2804 size_t i;
2805
2806 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table) && !mismatch;
2807 i++)
2808 mismatch = rx_indir_table[i] !=
2809 ethtool_rxfh_indir_default(i, efx->rss_spread);
2810
2811 rc = efx_ef10_rx_push_shared_rss_config(efx, &context_size);
2812 if (rc == 0) {
2813 if (context_size != efx->rss_spread)
2814 netif_warn(efx, probe, efx->net_dev,
2815 "Could not allocate an exclusive RSS"
2816 " context; allocated a shared one of"
2817 " different size."
2818 " Wanted %u, got %u.\n",
2819 efx->rss_spread, context_size);
2820 else if (mismatch)
2821 netif_warn(efx, probe, efx->net_dev,
2822 "Could not allocate an exclusive RSS"
2823 " context; allocated a shared one but"
2824 " could not apply custom"
2825 " indirection.\n");
2826 else
2827 netif_info(efx, probe, efx->net_dev,
2828 "Could not allocate an exclusive RSS"
2829 " context; allocated a shared one.\n");
2830 }
2831 }
2832 return rc;
2833}
2834
2835static int efx_ef10_vf_rx_push_rss_config(struct efx_nic *efx, bool user,
2836 const u32 *rx_indir_table
f74d1995
EC		 2837 __attribute__ ((unused)),
2838 const u8 *key
267c0157
JC		 2839 __attribute__ ((unused)))
2840{
2841 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2842
2843 if (user)
2844 return -EOPNOTSUPP;
2845 if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID)
2846 return 0;
2847 return efx_ef10_rx_push_shared_rss_config(efx, NULL);
8127d661
BH		 2848}
2849
2850static int efx_ef10_rx_probe(struct efx_rx_queue *rx_queue)
2851{
2852 return efx_nic_alloc_buffer(rx_queue->efx, &rx_queue->rxd.buf,
2853 (rx_queue->ptr_mask + 1) *
2854 sizeof(efx_qword_t),
2855 GFP_KERNEL);
2856}
2857
2858static void efx_ef10_rx_init(struct efx_rx_queue *rx_queue)
2859{
2860 MCDI_DECLARE_BUF(inbuf,
2861 MC_CMD_INIT_RXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
2862 EFX_BUF_SIZE));
8127d661
BH		 2863 struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
2864 size_t entries = rx_queue->rxd.buf.len / EFX_BUF_SIZE;
2865 struct efx_nic *efx = rx_queue->efx;
45b2449e 2866 struct efx_ef10_nic_data *nic_data = efx->nic_data;
aa09a3da 2867 size_t inlen;
8127d661
BH		 2868 dma_addr_t dma_addr;
2869 int rc;
2870 int i;
aa09a3da 2871 BUILD_BUG_ON(MC_CMD_INIT_RXQ_OUT_LEN != 0);
8127d661
BH		 2872
2873 rx_queue->scatter_n = 0;
2874 rx_queue->scatter_len = 0;
2875
2876 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_SIZE, rx_queue->ptr_mask + 1);
2877 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_TARGET_EVQ, channel->channel);
2878 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_LABEL, efx_rx_queue_index(rx_queue));
2879 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_INSTANCE,
2880 efx_rx_queue_index(rx_queue));
bd9a265d
JC		 2881 MCDI_POPULATE_DWORD_2(inbuf, INIT_RXQ_IN_FLAGS,
2882 INIT_RXQ_IN_FLAG_PREFIX, 1,
2883 INIT_RXQ_IN_FLAG_TIMESTAMP, 1);
8127d661 2884 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_OWNER_ID, 0);
45b2449e 2885 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_PORT_ID, nic_data->vport_id);
8127d661
BH		 2886
2887 dma_addr = rx_queue->rxd.buf.dma_addr;
2888
2889 netif_dbg(efx, hw, efx->net_dev, "pushing RXQ %d. %zu entries (%llx)\n",
2890 efx_rx_queue_index(rx_queue), entries, (u64)dma_addr);
2891
2892 for (i = 0; i < entries; ++i) {
2893 MCDI_SET_ARRAY_QWORD(inbuf, INIT_RXQ_IN_DMA_ADDR, i, dma_addr);
2894 dma_addr += EFX_BUF_SIZE;
2895 }
2896
2897 inlen = MC_CMD_INIT_RXQ_IN_LEN(entries);
2898
2899 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_RXQ, inbuf, inlen,
aa09a3da 2900 NULL, 0, NULL);
48ce5634
BH		 2901 if (rc)
2902 netdev_WARN(efx->net_dev, "failed to initialise RXQ %d\n",
2903 efx_rx_queue_index(rx_queue));
8127d661
BH		 2904}
2905
2906static void efx_ef10_rx_fini(struct efx_rx_queue *rx_queue)
2907{
2908 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_RXQ_IN_LEN);
aa09a3da 2909 MCDI_DECLARE_BUF_ERR(outbuf);
8127d661
BH		 2910 struct efx_nic *efx = rx_queue->efx;
2911 size_t outlen;
2912 int rc;
2913
2914 MCDI_SET_DWORD(inbuf, FINI_RXQ_IN_INSTANCE,
2915 efx_rx_queue_index(rx_queue));
2916
1e0b8120 2917 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_RXQ, inbuf, sizeof(inbuf),
8127d661
BH		 2918 outbuf, sizeof(outbuf), &outlen);
2919
2920 if (rc && rc != -EALREADY)
2921 goto fail;
2922
2923 return;
2924
2925fail:
1e0b8120
EC		 2926 efx_mcdi_display_error(efx, MC_CMD_FINI_RXQ, MC_CMD_FINI_RXQ_IN_LEN,
2927 outbuf, outlen, rc);
8127d661
BH		 2928}
2929
2930static void efx_ef10_rx_remove(struct efx_rx_queue *rx_queue)
2931{
2932 efx_nic_free_buffer(rx_queue->efx, &rx_queue->rxd.buf);
2933}
2934
2935/* This creates an entry in the RX descriptor queue */
2936static inline void
2937efx_ef10_build_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index)
2938{
2939 struct efx_rx_buffer *rx_buf;
2940 efx_qword_t *rxd;
2941
2942 rxd = efx_rx_desc(rx_queue, index);
2943 rx_buf = efx_rx_buffer(rx_queue, index);
2944 EFX_POPULATE_QWORD_2(*rxd,
2945 ESF_DZ_RX_KER_BYTE_CNT, rx_buf->len,
2946 ESF_DZ_RX_KER_BUF_ADDR, rx_buf->dma_addr);
2947}
2948
2949static void efx_ef10_rx_write(struct efx_rx_queue *rx_queue)
2950{
2951 struct efx_nic *efx = rx_queue->efx;
2952 unsigned int write_count;
2953 efx_dword_t reg;
2954
2955 /* Firmware requires that RX_DESC_WPTR be a multiple of 8 */
2956 write_count = rx_queue->added_count & ~7;
2957 if (rx_queue->notified_count == write_count)
2958 return;
2959
2960 do
2961 efx_ef10_build_rx_desc(
2962 rx_queue,
2963 rx_queue->notified_count & rx_queue->ptr_mask);
2964 while (++rx_queue->notified_count != write_count);
2965
2966 wmb();
2967 EFX_POPULATE_DWORD_1(reg, ERF_DZ_RX_DESC_WPTR,
2968 write_count & rx_queue->ptr_mask);
2969 efx_writed_page(efx, &reg, ER_DZ_RX_DESC_UPD,
2970 efx_rx_queue_index(rx_queue));
2971}
2972
2973static efx_mcdi_async_completer efx_ef10_rx_defer_refill_complete;
2974
2975static void efx_ef10_rx_defer_refill(struct efx_rx_queue *rx_queue)
2976{
2977 struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
2978 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
2979 efx_qword_t event;
2980
2981 EFX_POPULATE_QWORD_2(event,
2982 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
2983 ESF_DZ_EV_DATA, EFX_EF10_REFILL);
2984
2985 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
2986
2987 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
2988 * already swapped the data to little-endian order.
2989 */
2990 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
2991 sizeof(efx_qword_t));
2992
2993 efx_mcdi_rpc_async(channel->efx, MC_CMD_DRIVER_EVENT,
2994 inbuf, sizeof(inbuf), 0,
2995 efx_ef10_rx_defer_refill_complete, 0);
2996}
2997
2998static void
2999efx_ef10_rx_defer_refill_complete(struct efx_nic *efx, unsigned long cookie,
3000 int rc, efx_dword_t *outbuf,
3001 size_t outlen_actual)
3002{
3003 /* nothing to do */
3004}
3005
3006static int efx_ef10_ev_probe(struct efx_channel *channel)
3007{
3008 return efx_nic_alloc_buffer(channel->efx, &channel->eventq.buf,
3009 (channel->eventq_mask + 1) *
3010 sizeof(efx_qword_t),
3011 GFP_KERNEL);
3012}
3013
46e612b0
DP		 3014static void efx_ef10_ev_fini(struct efx_channel *channel)
3015{
3016 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_EVQ_IN_LEN);
3017 MCDI_DECLARE_BUF_ERR(outbuf);
3018 struct efx_nic *efx = channel->efx;
3019 size_t outlen;
3020 int rc;
3021
3022 MCDI_SET_DWORD(inbuf, FINI_EVQ_IN_INSTANCE, channel->channel);
3023
3024 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_EVQ, inbuf, sizeof(inbuf),
3025 outbuf, sizeof(outbuf), &outlen);
3026
3027 if (rc && rc != -EALREADY)
3028 goto fail;
3029
3030 return;
3031
3032fail:
3033 efx_mcdi_display_error(efx, MC_CMD_FINI_EVQ, MC_CMD_FINI_EVQ_IN_LEN,
3034 outbuf, outlen, rc);
3035}
3036
8127d661
BH		 3037static int efx_ef10_ev_init(struct efx_channel *channel)
3038{
3039 MCDI_DECLARE_BUF(inbuf,
a995560a
BK		 3040 MC_CMD_INIT_EVQ_V2_IN_LEN(EFX_MAX_EVQ_SIZE * 8 /
3041 EFX_BUF_SIZE));
3042 MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_EVQ_V2_OUT_LEN);
8127d661
BH		 3043 size_t entries = channel->eventq.buf.len / EFX_BUF_SIZE;
3044 struct efx_nic *efx = channel->efx;
3045 struct efx_ef10_nic_data *nic_data;
8127d661 3046 size_t inlen, outlen;
46e612b0 3047 unsigned int enabled, implemented;
8127d661
BH		 3048 dma_addr_t dma_addr;
3049 int rc;
3050 int i;
3051
3052 nic_data = efx->nic_data;
8127d661
BH		 3053
3054 /* Fill event queue with all ones (i.e. empty events) */
3055 memset(channel->eventq.buf.addr, 0xff, channel->eventq.buf.len);
3056
3057 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_SIZE, channel->eventq_mask + 1);
3058 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_INSTANCE, channel->channel);
3059 /* INIT_EVQ expects index in vector table, not absolute */
3060 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_IRQ_NUM, channel->channel);
8127d661
BH		 3061 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_MODE,
3062 MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS);
3063 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_LOAD, 0);
3064 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_RELOAD, 0);
3065 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_MODE,
3066 MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS);
3067 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_THRSHLD, 0);
3068
a995560a
BK		 3069 if (nic_data->datapath_caps2 &
3070 1 << MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_V2_LBN) {
3071 /* Use the new generic approach to specifying event queue
3072 * configuration, requesting lower latency or higher throughput.
3073 * The options that actually get used appear in the output.
3074 */
3075 MCDI_POPULATE_DWORD_2(inbuf, INIT_EVQ_V2_IN_FLAGS,
3076 INIT_EVQ_V2_IN_FLAG_INTERRUPTING, 1,
3077 INIT_EVQ_V2_IN_FLAG_TYPE,
3078 MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_AUTO);
3079 } else {
3080 bool cut_thru = !(nic_data->datapath_caps &
3081 1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN);
3082
3083 MCDI_POPULATE_DWORD_4(inbuf, INIT_EVQ_IN_FLAGS,
3084 INIT_EVQ_IN_FLAG_INTERRUPTING, 1,
3085 INIT_EVQ_IN_FLAG_RX_MERGE, 1,
3086 INIT_EVQ_IN_FLAG_TX_MERGE, 1,
3087 INIT_EVQ_IN_FLAG_CUT_THRU, cut_thru);
3088 }
3089
8127d661
BH		 3090 dma_addr = channel->eventq.buf.dma_addr;
3091 for (i = 0; i < entries; ++i) {
3092 MCDI_SET_ARRAY_QWORD(inbuf, INIT_EVQ_IN_DMA_ADDR, i, dma_addr);
3093 dma_addr += EFX_BUF_SIZE;
3094 }
3095
3096 inlen = MC_CMD_INIT_EVQ_IN_LEN(entries);
3097
3098 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_EVQ, inbuf, inlen,
3099 outbuf, sizeof(outbuf), &outlen);
a995560a
BK		 3100
3101 if (outlen >= MC_CMD_INIT_EVQ_V2_OUT_LEN)
3102 netif_dbg(efx, drv, efx->net_dev,
3103 "Channel %d using event queue flags %08x\n",
3104 channel->channel,
3105 MCDI_DWORD(outbuf, INIT_EVQ_V2_OUT_FLAGS));
3106
8127d661 3107 /* IRQ return is ignored */
46e612b0
DP		 3108 if (channel->channel || rc)
3109 return rc;
8127d661 3110
46e612b0
DP		 3111 /* Successfully created event queue on channel 0 */
3112 rc = efx_mcdi_get_workarounds(efx, &implemented, &enabled);
832dc9ed 3113 if (rc == -ENOSYS) {
d95e329a
BK		 3114 /* GET_WORKAROUNDS was implemented before this workaround,
3115 * thus it must be unavailable in this firmware.
832dc9ed
EC		 3116 */
3117 nic_data->workaround_26807 = false;
3118 rc = 0;
3119 } else if (rc) {
8127d661 3120 goto fail;
832dc9ed
EC		 3121 } else {
3122 nic_data->workaround_26807 =
3123 !!(enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807);
3124
3125 if (implemented & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807 &&
3126 !nic_data->workaround_26807) {
5a55a72a
DP		 3127 unsigned int flags;
3128
34ccfe6f
DP		 3129 rc = efx_mcdi_set_workaround(efx,
3130 MC_CMD_WORKAROUND_BUG26807,
5a55a72a
DP		 3131 true, &flags);
3132
3133 if (!rc) {
3134 if (flags &
3135 1 << MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN) {
3136 netif_info(efx, drv, efx->net_dev,
3137 "other functions on NIC have been reset\n");
abd86a55
DP		 3138
3139 /* With MCFW v4.6.x and earlier, the
3140 * boot count will have incremented,
3141 * so re-read the warm_boot_count
3142 * value now to ensure this function
3143 * doesn't think it has changed next
3144 * time it checks.
3145 */
3146 rc = efx_ef10_get_warm_boot_count(efx);
3147 if (rc >= 0) {
3148 nic_data->warm_boot_count = rc;
3149 rc = 0;
3150 }
5a55a72a 3151 }
832dc9ed 3152 nic_data->workaround_26807 = true;
5a55a72a 3153 } else if (rc == -EPERM) {
832dc9ed 3154 rc = 0;
5a55a72a 3155 }
832dc9ed 3156 }
46e612b0
DP		 3157 }
3158
3159 if (!rc)
3160 return 0;
8127d661
BH		 3161
3162fail:
46e612b0
DP		 3163 efx_ef10_ev_fini(channel);
3164 return rc;
8127d661
BH		 3165}
3166
3167static void efx_ef10_ev_remove(struct efx_channel *channel)
3168{
3169 efx_nic_free_buffer(channel->efx, &channel->eventq.buf);
3170}
3171
3172static void efx_ef10_handle_rx_wrong_queue(struct efx_rx_queue *rx_queue,
3173 unsigned int rx_queue_label)
3174{
3175 struct efx_nic *efx = rx_queue->efx;
3176
3177 netif_info(efx, hw, efx->net_dev,
3178 "rx event arrived on queue %d labeled as queue %u\n",
3179 efx_rx_queue_index(rx_queue), rx_queue_label);
3180
3181 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
3182}
3183
3184static void
3185efx_ef10_handle_rx_bad_lbits(struct efx_rx_queue *rx_queue,
3186 unsigned int actual, unsigned int expected)
3187{
3188 unsigned int dropped = (actual - expected) & rx_queue->ptr_mask;
3189 struct efx_nic *efx = rx_queue->efx;
3190
3191 netif_info(efx, hw, efx->net_dev,
3192 "dropped %d events (index=%d expected=%d)\n",
3193 dropped, actual, expected);
3194
3195 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
3196}
3197
3198/* partially received RX was aborted. clean up. */
3199static void efx_ef10_handle_rx_abort(struct efx_rx_queue *rx_queue)
3200{
3201 unsigned int rx_desc_ptr;
3202
8127d661
BH		 3203 netif_dbg(rx_queue->efx, hw, rx_queue->efx->net_dev,
3204 "scattered RX aborted (dropping %u buffers)\n",
3205 rx_queue->scatter_n);
3206
3207 rx_desc_ptr = rx_queue->removed_count & rx_queue->ptr_mask;
3208
3209 efx_rx_packet(rx_queue, rx_desc_ptr, rx_queue->scatter_n,
3210 0, EFX_RX_PKT_DISCARD);
3211
3212 rx_queue->removed_count += rx_queue->scatter_n;
3213 rx_queue->scatter_n = 0;
3214 rx_queue->scatter_len = 0;
3215 ++efx_rx_queue_channel(rx_queue)->n_rx_nodesc_trunc;
3216}
3217
a0ee3541
JC		 3218static u16 efx_ef10_handle_rx_event_errors(struct efx_channel *channel,
3219 unsigned int n_packets,
3220 unsigned int rx_encap_hdr,
3221 unsigned int rx_l3_class,
3222 unsigned int rx_l4_class,
3223 const efx_qword_t *event)
3224{
3225 struct efx_nic *efx = channel->efx;
6978729f 3226 bool handled = false;
a0ee3541
JC		 3227
3228 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_ECRC_ERR)) {
6978729f
EC		 3229 if (!(efx->net_dev->features & NETIF_F_RXALL)) {
3230 if (!efx->loopback_selftest)
3231 channel->n_rx_eth_crc_err += n_packets;
3232 return EFX_RX_PKT_DISCARD;
3233 }
3234 handled = true;
a0ee3541
JC		 3235 }
3236 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_IPCKSUM_ERR)) {
3237 if (unlikely(rx_encap_hdr != ESE_EZ_ENCAP_HDR_VXLAN &&
3238 rx_l3_class != ESE_DZ_L3_CLASS_IP4 &&
3239 rx_l3_class != ESE_DZ_L3_CLASS_IP4_FRAG &&
3240 rx_l3_class != ESE_DZ_L3_CLASS_IP6 &&
3241 rx_l3_class != ESE_DZ_L3_CLASS_IP6_FRAG))
3242 netdev_WARN(efx->net_dev,
3243 "invalid class for RX_IPCKSUM_ERR: event="
3244 EFX_QWORD_FMT "\n",
3245 EFX_QWORD_VAL(*event));
3246 if (!efx->loopback_selftest)
3247 *(rx_encap_hdr ?
3248 &channel->n_rx_outer_ip_hdr_chksum_err :
3249 &channel->n_rx_ip_hdr_chksum_err) += n_packets;
3250 return 0;
3251 }
3252 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_TCPUDP_CKSUM_ERR)) {
3253 if (unlikely(rx_encap_hdr != ESE_EZ_ENCAP_HDR_VXLAN &&
3254 ((rx_l3_class != ESE_DZ_L3_CLASS_IP4 &&
3255 rx_l3_class != ESE_DZ_L3_CLASS_IP6) ||
3256 (rx_l4_class != ESE_DZ_L4_CLASS_TCP &&
3257 rx_l4_class != ESE_DZ_L4_CLASS_UDP))))
3258 netdev_WARN(efx->net_dev,
3259 "invalid class for RX_TCPUDP_CKSUM_ERR: event="
3260 EFX_QWORD_FMT "\n",
3261 EFX_QWORD_VAL(*event));
3262 if (!efx->loopback_selftest)
3263 *(rx_encap_hdr ?
3264 &channel->n_rx_outer_tcp_udp_chksum_err :
3265 &channel->n_rx_tcp_udp_chksum_err) += n_packets;
3266 return 0;
3267 }
3268 if (EFX_QWORD_FIELD(*event, ESF_EZ_RX_IP_INNER_CHKSUM_ERR)) {
3269 if (unlikely(!rx_encap_hdr))
3270 netdev_WARN(efx->net_dev,
3271 "invalid encapsulation type for RX_IP_INNER_CHKSUM_ERR: event="
3272 EFX_QWORD_FMT "\n",
3273 EFX_QWORD_VAL(*event));
3274 else if (unlikely(rx_l3_class != ESE_DZ_L3_CLASS_IP4 &&
3275 rx_l3_class != ESE_DZ_L3_CLASS_IP4_FRAG &&
3276 rx_l3_class != ESE_DZ_L3_CLASS_IP6 &&
3277 rx_l3_class != ESE_DZ_L3_CLASS_IP6_FRAG))
3278 netdev_WARN(efx->net_dev,
3279 "invalid class for RX_IP_INNER_CHKSUM_ERR: event="
3280 EFX_QWORD_FMT "\n",
3281 EFX_QWORD_VAL(*event));
3282 if (!efx->loopback_selftest)
3283 channel->n_rx_inner_ip_hdr_chksum_err += n_packets;
3284 return 0;
3285 }
3286 if (EFX_QWORD_FIELD(*event, ESF_EZ_RX_TCP_UDP_INNER_CHKSUM_ERR)) {
3287 if (unlikely(!rx_encap_hdr))
3288 netdev_WARN(efx->net_dev,
3289 "invalid encapsulation type for RX_TCP_UDP_INNER_CHKSUM_ERR: event="
3290 EFX_QWORD_FMT "\n",
3291 EFX_QWORD_VAL(*event));
3292 else if (unlikely((rx_l3_class != ESE_DZ_L3_CLASS_IP4 &&
3293 rx_l3_class != ESE_DZ_L3_CLASS_IP6) ||
3294 (rx_l4_class != ESE_DZ_L4_CLASS_TCP &&
3295 rx_l4_class != ESE_DZ_L4_CLASS_UDP)))
3296 netdev_WARN(efx->net_dev,
3297 "invalid class for RX_TCP_UDP_INNER_CHKSUM_ERR: event="
3298 EFX_QWORD_FMT "\n",
3299 EFX_QWORD_VAL(*event));
3300 if (!efx->loopback_selftest)
3301 channel->n_rx_inner_tcp_udp_chksum_err += n_packets;
3302 return 0;
3303 }
3304
6978729f 3305 WARN_ON(!handled); /* No error bits were recognised */
a0ee3541
JC		 3306 return 0;
3307}
3308
8127d661
BH		 3309static int efx_ef10_handle_rx_event(struct efx_channel *channel,
3310 const efx_qword_t *event)
3311{
a0ee3541
JC		 3312 unsigned int rx_bytes, next_ptr_lbits, rx_queue_label;
3313 unsigned int rx_l3_class, rx_l4_class, rx_encap_hdr;
8127d661
BH		 3314 unsigned int n_descs, n_packets, i;
3315 struct efx_nic *efx = channel->efx;
a0ee3541 3316 struct efx_ef10_nic_data *nic_data = efx->nic_data;
8127d661 3317 struct efx_rx_queue *rx_queue;
a0ee3541 3318 efx_qword_t errors;
8127d661
BH		 3319 bool rx_cont;
3320 u16 flags = 0;
3321
6aa7de05 3322 if (unlikely(READ_ONCE(efx->reset_pending)))
8127d661
BH		 3323 return 0;
3324
3325 /* Basic packet information */
3326 rx_bytes = EFX_QWORD_FIELD(*event, ESF_DZ_RX_BYTES);
3327 next_ptr_lbits = EFX_QWORD_FIELD(*event, ESF_DZ_RX_DSC_PTR_LBITS);
3328 rx_queue_label = EFX_QWORD_FIELD(*event, ESF_DZ_RX_QLABEL);
a0ee3541 3329 rx_l3_class = EFX_QWORD_FIELD(*event, ESF_DZ_RX_L3_CLASS);
8127d661
BH		 3330 rx_l4_class = EFX_QWORD_FIELD(*event, ESF_DZ_RX_L4_CLASS);
3331 rx_cont = EFX_QWORD_FIELD(*event, ESF_DZ_RX_CONT);
a0ee3541
JC		 3332 rx_encap_hdr =
3333 nic_data->datapath_caps &
3334 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN) ?
3335 EFX_QWORD_FIELD(*event, ESF_EZ_RX_ENCAP_HDR) :
3336 ESE_EZ_ENCAP_HDR_NONE;
8127d661 3337
48ce5634
BH		 3338 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_DROP_EVENT))
3339 netdev_WARN(efx->net_dev, "saw RX_DROP_EVENT: event="
3340 EFX_QWORD_FMT "\n",
3341 EFX_QWORD_VAL(*event));
8127d661
BH		 3342
3343 rx_queue = efx_channel_get_rx_queue(channel);
3344
3345 if (unlikely(rx_queue_label != efx_rx_queue_index(rx_queue)))
3346 efx_ef10_handle_rx_wrong_queue(rx_queue, rx_queue_label);
3347
3348 n_descs = ((next_ptr_lbits - rx_queue->removed_count) &
3349 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
3350
3351 if (n_descs != rx_queue->scatter_n + 1) {
92a04168
BH		 3352 struct efx_ef10_nic_data *nic_data = efx->nic_data;
3353
8127d661
BH		 3354 /* detect rx abort */
3355 if (unlikely(n_descs == rx_queue->scatter_n)) {
48ce5634
BH		 3356 if (rx_queue->scatter_n == 0 || rx_bytes != 0)
3357 netdev_WARN(efx->net_dev,
3358 "invalid RX abort: scatter_n=%u event="
3359 EFX_QWORD_FMT "\n",
3360 rx_queue->scatter_n,
3361 EFX_QWORD_VAL(*event));
8127d661
BH		 3362 efx_ef10_handle_rx_abort(rx_queue);
3363 return 0;
3364 }
3365
92a04168
BH		 3366 /* Check that RX completion merging is valid, i.e.
3367 * the current firmware supports it and this is a
3368 * non-scattered packet.
3369 */
3370 if (!(nic_data->datapath_caps &
3371 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN)) ||
3372 rx_queue->scatter_n != 0 || rx_cont) {
8127d661
BH		 3373 efx_ef10_handle_rx_bad_lbits(
3374 rx_queue, next_ptr_lbits,
3375 (rx_queue->removed_count +
3376 rx_queue->scatter_n + 1) &
3377 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
3378 return 0;
3379 }
3380
3381 /* Merged completion for multiple non-scattered packets */
3382 rx_queue->scatter_n = 1;
3383 rx_queue->scatter_len = 0;
3384 n_packets = n_descs;
3385 ++channel->n_rx_merge_events;
3386 channel->n_rx_merge_packets += n_packets;
3387 flags |= EFX_RX_PKT_PREFIX_LEN;
3388 } else {
3389 ++rx_queue->scatter_n;
3390 rx_queue->scatter_len += rx_bytes;
3391 if (rx_cont)
3392 return 0;
3393 n_packets = 1;
3394 }
3395
a0ee3541
JC		 3396 EFX_POPULATE_QWORD_5(errors, ESF_DZ_RX_ECRC_ERR, 1,
3397 ESF_DZ_RX_IPCKSUM_ERR, 1,
3398 ESF_DZ_RX_TCPUDP_CKSUM_ERR, 1,
3399 ESF_EZ_RX_IP_INNER_CHKSUM_ERR, 1,
3400 ESF_EZ_RX_TCP_UDP_INNER_CHKSUM_ERR, 1);
3401 EFX_AND_QWORD(errors, *event, errors);
3402 if (unlikely(!EFX_QWORD_IS_ZERO(errors))) {
3403 flags |= efx_ef10_handle_rx_event_errors(channel, n_packets,
90d2ea9f 3404 rx_encap_hdr,
a0ee3541 3405 rx_l3_class, rx_l4_class,
90d2ea9f 3406 event);
a0ee3541 3407 } else {
da50ae2e
JC		 3408 bool tcpudp = rx_l4_class == ESE_DZ_L4_CLASS_TCP ||
3409 rx_l4_class == ESE_DZ_L4_CLASS_UDP;
3410
3411 switch (rx_encap_hdr) {
3412 case ESE_EZ_ENCAP_HDR_VXLAN: /* VxLAN or GENEVE */
3413 flags |= EFX_RX_PKT_CSUMMED; /* outer UDP csum */
3414 if (tcpudp)
3415 flags |= EFX_RX_PKT_CSUM_LEVEL; /* inner L4 */
3416 break;
3417 case ESE_EZ_ENCAP_HDR_GRE:
3418 case ESE_EZ_ENCAP_HDR_NONE:
3419 if (tcpudp)
3420 flags |= EFX_RX_PKT_CSUMMED;
3421 break;
3422 default:
3423 netdev_WARN(efx->net_dev,
3424 "unknown encapsulation type: event="
3425 EFX_QWORD_FMT "\n",
3426 EFX_QWORD_VAL(*event));
3427 }
8127d661
BH		 3428 }
3429
3430 if (rx_l4_class == ESE_DZ_L4_CLASS_TCP)
3431 flags |= EFX_RX_PKT_TCP;
3432
3433 channel->irq_mod_score += 2 * n_packets;
3434
3435 /* Handle received packet(s) */
3436 for (i = 0; i < n_packets; i++) {
3437 efx_rx_packet(rx_queue,
3438 rx_queue->removed_count & rx_queue->ptr_mask,
3439 rx_queue->scatter_n, rx_queue->scatter_len,
3440 flags);
3441 rx_queue->removed_count += rx_queue->scatter_n;
3442 }
3443
3444 rx_queue->scatter_n = 0;
3445 rx_queue->scatter_len = 0;
3446
3447 return n_packets;
3448}
3449
3450static int
3451efx_ef10_handle_tx_event(struct efx_channel *channel, efx_qword_t *event)
3452{
3453 struct efx_nic *efx = channel->efx;
3454 struct efx_tx_queue *tx_queue;
3455 unsigned int tx_ev_desc_ptr;
3456 unsigned int tx_ev_q_label;
3457 int tx_descs = 0;
3458
6aa7de05 3459 if (unlikely(READ_ONCE(efx->reset_pending)))
8127d661
BH		 3460 return 0;
3461
3462 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_TX_DROP_EVENT)))
3463 return 0;
3464
3465 /* Transmit completion */
3466 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, ESF_DZ_TX_DESCR_INDX);
3467 tx_ev_q_label = EFX_QWORD_FIELD(*event, ESF_DZ_TX_QLABEL);
3468 tx_queue = efx_channel_get_tx_queue(channel,
3469 tx_ev_q_label % EFX_TXQ_TYPES);
3470 tx_descs = ((tx_ev_desc_ptr + 1 - tx_queue->read_count) &
3471 tx_queue->ptr_mask);
3472 efx_xmit_done(tx_queue, tx_ev_desc_ptr & tx_queue->ptr_mask);
3473
3474 return tx_descs;
3475}
3476
3477static void
3478efx_ef10_handle_driver_event(struct efx_channel *channel, efx_qword_t *event)
3479{
3480 struct efx_nic *efx = channel->efx;
3481 int subcode;
3482
3483 subcode = EFX_QWORD_FIELD(*event, ESF_DZ_DRV_SUB_CODE);
3484
3485 switch (subcode) {
3486 case ESE_DZ_DRV_TIMER_EV:
3487 case ESE_DZ_DRV_WAKE_UP_EV:
3488 break;
3489 case ESE_DZ_DRV_START_UP_EV:
3490 /* event queue init complete. ok. */
3491 break;
3492 default:
3493 netif_err(efx, hw, efx->net_dev,
3494 "channel %d unknown driver event type %d"
3495 " (data " EFX_QWORD_FMT ")\n",
3496 channel->channel, subcode,
3497 EFX_QWORD_VAL(*event));
3498
3499 }
3500}
3501
3502static void efx_ef10_handle_driver_generated_event(struct efx_channel *channel,
3503 efx_qword_t *event)
3504{
3505 struct efx_nic *efx = channel->efx;
3506 u32 subcode;
3507
3508 subcode = EFX_QWORD_FIELD(*event, EFX_DWORD_0);
3509
3510 switch (subcode) {
3511 case EFX_EF10_TEST:
3512 channel->event_test_cpu = raw_smp_processor_id();
3513 break;
3514 case EFX_EF10_REFILL:
3515 /* The queue must be empty, so we won't receive any rx
3516 * events, so efx_process_channel() won't refill the
3517 * queue. Refill it here
3518 */
cce28794 3519 efx_fast_push_rx_descriptors(&channel->rx_queue, true);
8127d661
BH		 3520 break;
3521 default:
3522 netif_err(efx, hw, efx->net_dev,
3523 "channel %d unknown driver event type %u"
3524 " (data " EFX_QWORD_FMT ")\n",
3525 channel->channel, (unsigned) subcode,
3526 EFX_QWORD_VAL(*event));
3527 }
3528}
3529
3530static int efx_ef10_ev_process(struct efx_channel *channel, int quota)
3531{
3532 struct efx_nic *efx = channel->efx;
3533 efx_qword_t event, *p_event;
3534 unsigned int read_ptr;
3535 int ev_code;
3536 int tx_descs = 0;
3537 int spent = 0;
3538
75363a46
EB		 3539 if (quota <= 0)
3540 return spent;
3541
8127d661
BH		 3542 read_ptr = channel->eventq_read_ptr;
3543
3544 for (;;) {
3545 p_event = efx_event(channel, read_ptr);
3546 event = *p_event;
3547
3548 if (!efx_event_present(&event))
3549 break;
3550
3551 EFX_SET_QWORD(*p_event);
3552
3553 ++read_ptr;
3554
3555 ev_code = EFX_QWORD_FIELD(event, ESF_DZ_EV_CODE);
3556
3557 netif_vdbg(efx, drv, efx->net_dev,
3558 "processing event on %d " EFX_QWORD_FMT "\n",
3559 channel->channel, EFX_QWORD_VAL(event));
3560
3561 switch (ev_code) {
3562 case ESE_DZ_EV_CODE_MCDI_EV:
3563 efx_mcdi_process_event(channel, &event);
3564 break;
3565 case ESE_DZ_EV_CODE_RX_EV:
3566 spent += efx_ef10_handle_rx_event(channel, &event);
3567 if (spent >= quota) {
3568 /* XXX can we split a merged event to
3569 * avoid going over-quota?
3570 */
3571 spent = quota;
3572 goto out;
3573 }
3574 break;
3575 case ESE_DZ_EV_CODE_TX_EV:
3576 tx_descs += efx_ef10_handle_tx_event(channel, &event);
3577 if (tx_descs > efx->txq_entries) {
3578 spent = quota;
3579 goto out;
3580 } else if (++spent == quota) {
3581 goto out;
3582 }
3583 break;
3584 case ESE_DZ_EV_CODE_DRIVER_EV:
3585 efx_ef10_handle_driver_event(channel, &event);
3586 if (++spent == quota)
3587 goto out;
3588 break;
3589 case EFX_EF10_DRVGEN_EV:
3590 efx_ef10_handle_driver_generated_event(channel, &event);
3591 break;
3592 default:
3593 netif_err(efx, hw, efx->net_dev,
3594 "channel %d unknown event type %d"
3595 " (data " EFX_QWORD_FMT ")\n",
3596 channel->channel, ev_code,
3597 EFX_QWORD_VAL(event));
3598 }
3599 }
3600
3601out:
3602 channel->eventq_read_ptr = read_ptr;
3603 return spent;
3604}
3605
3606static void efx_ef10_ev_read_ack(struct efx_channel *channel)
3607{
3608 struct efx_nic *efx = channel->efx;
3609 efx_dword_t rptr;
3610
3611 if (EFX_EF10_WORKAROUND_35388(efx)) {
3612 BUILD_BUG_ON(EFX_MIN_EVQ_SIZE <
3613 (1 << ERF_DD_EVQ_IND_RPTR_WIDTH));
3614 BUILD_BUG_ON(EFX_MAX_EVQ_SIZE >
3615 (1 << 2 * ERF_DD_EVQ_IND_RPTR_WIDTH));
3616
3617 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
3618 EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH,
3619 ERF_DD_EVQ_IND_RPTR,
3620 (channel->eventq_read_ptr &
3621 channel->eventq_mask) >>
3622 ERF_DD_EVQ_IND_RPTR_WIDTH);
3623 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
3624 channel->channel);
3625 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
3626 EFE_DD_EVQ_IND_RPTR_FLAGS_LOW,
3627 ERF_DD_EVQ_IND_RPTR,
3628 channel->eventq_read_ptr &
3629 ((1 << ERF_DD_EVQ_IND_RPTR_WIDTH) - 1));
3630 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
3631 channel->channel);
3632 } else {
3633 EFX_POPULATE_DWORD_1(rptr, ERF_DZ_EVQ_RPTR,
3634 channel->eventq_read_ptr &
3635 channel->eventq_mask);
3636 efx_writed_page(efx, &rptr, ER_DZ_EVQ_RPTR, channel->channel);
3637 }
3638}
3639
3640static void efx_ef10_ev_test_generate(struct efx_channel *channel)
3641{
3642 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
3643 struct efx_nic *efx = channel->efx;
3644 efx_qword_t event;
3645 int rc;
3646
3647 EFX_POPULATE_QWORD_2(event,
3648 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
3649 ESF_DZ_EV_DATA, EFX_EF10_TEST);
3650
3651 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
3652
3653 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
3654 * already swapped the data to little-endian order.
3655 */
3656 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
3657 sizeof(efx_qword_t));
3658
3659 rc = efx_mcdi_rpc(efx, MC_CMD_DRIVER_EVENT, inbuf, sizeof(inbuf),
3660 NULL, 0, NULL);
3661 if (rc != 0)
3662 goto fail;
3663
3664 return;
3665
3666fail:
3667 WARN_ON(true);
3668 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
3669}
3670
3671void efx_ef10_handle_drain_event(struct efx_nic *efx)
3672{
3673 if (atomic_dec_and_test(&efx->active_queues))
3674 wake_up(&efx->flush_wq);
3675
3676 WARN_ON(atomic_read(&efx->active_queues) < 0);
3677}
3678
3679static int efx_ef10_fini_dmaq(struct efx_nic *efx)
3680{
3681 struct efx_ef10_nic_data *nic_data = efx->nic_data;
3682 struct efx_channel *channel;
3683 struct efx_tx_queue *tx_queue;
3684 struct efx_rx_queue *rx_queue;
3685 int pending;
3686
3687 /* If the MC has just rebooted, the TX/RX queues will have already been
3688 * torn down, but efx->active_queues needs to be set to zero.
3689 */
3690 if (nic_data->must_realloc_vis) {
3691 atomic_set(&efx->active_queues, 0);
3692 return 0;
3693 }
3694
3695 /* Do not attempt to write to the NIC during EEH recovery */
3696 if (efx->state != STATE_RECOVERY) {
3697 efx_for_each_channel(channel, efx) {
3698 efx_for_each_channel_rx_queue(rx_queue, channel)
3699 efx_ef10_rx_fini(rx_queue);
3700 efx_for_each_channel_tx_queue(tx_queue, channel)
3701 efx_ef10_tx_fini(tx_queue);
3702 }
3703
3704 wait_event_timeout(efx->flush_wq,
3705 atomic_read(&efx->active_queues) == 0,
3706 msecs_to_jiffies(EFX_MAX_FLUSH_TIME));
3707 pending = atomic_read(&efx->active_queues);
3708 if (pending) {
3709 netif_err(efx, hw, efx->net_dev, "failed to flush %d queues\n",
3710 pending);
3711 return -ETIMEDOUT;
3712 }
3713 }
3714
3715 return 0;
3716}
3717
e283546c
EC		 3718static void efx_ef10_prepare_flr(struct efx_nic *efx)
3719{
3720 atomic_set(&efx->active_queues, 0);
3721}
3722
8127d661
BH		 3723static bool efx_ef10_filter_equal(const struct efx_filter_spec *left,
3724 const struct efx_filter_spec *right)
3725{
3726 if ((left->match_flags ^ right->match_flags) |
3727 ((left->flags ^ right->flags) &
3728 (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)))
3729 return false;
3730
3731 return memcmp(&left->outer_vid, &right->outer_vid,
3732 sizeof(struct efx_filter_spec) -
3733 offsetof(struct efx_filter_spec, outer_vid)) == 0;
3734}
3735
3736static unsigned int efx_ef10_filter_hash(const struct efx_filter_spec *spec)
3737{
3738 BUILD_BUG_ON(offsetof(struct efx_filter_spec, outer_vid) & 3);
3739 return jhash2((const u32 *)&spec->outer_vid,
3740 (sizeof(struct efx_filter_spec) -
3741 offsetof(struct efx_filter_spec, outer_vid)) / 4,
3742 0);
3743 /* XXX should we randomise the initval? */
3744}
3745
3746/* Decide whether a filter should be exclusive or else should allow
3747 * delivery to additional recipients. Currently we decide that
3748 * filters for specific local unicast MAC and IP addresses are
3749 * exclusive.
3750 */
3751static bool efx_ef10_filter_is_exclusive(const struct efx_filter_spec *spec)
3752{
3753 if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC &&
3754 !is_multicast_ether_addr(spec->loc_mac))
3755 return true;
3756
3757 if ((spec->match_flags &
3758 (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) ==
3759 (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) {
3760 if (spec->ether_type == htons(ETH_P_IP) &&
3761 !ipv4_is_multicast(spec->loc_host[0]))
3762 return true;
3763 if (spec->ether_type == htons(ETH_P_IPV6) &&
3764 ((const u8 *)spec->loc_host)[0] != 0xff)
3765 return true;
3766 }
3767
3768 return false;
3769}
3770
3771static struct efx_filter_spec *
3772efx_ef10_filter_entry_spec(const struct efx_ef10_filter_table *table,
3773 unsigned int filter_idx)
3774{
3775 return (struct efx_filter_spec *)(table->entry[filter_idx].spec &
3776 ~EFX_EF10_FILTER_FLAGS);
3777}
3778
3779static unsigned int
3780efx_ef10_filter_entry_flags(const struct efx_ef10_filter_table *table,
3781 unsigned int filter_idx)
3782{
3783 return table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAGS;
3784}
3785
3786static void
3787efx_ef10_filter_set_entry(struct efx_ef10_filter_table *table,
3788 unsigned int filter_idx,
3789 const struct efx_filter_spec *spec,
3790 unsigned int flags)
3791{
3792 table->entry[filter_idx].spec = (unsigned long)spec | flags;
3793}
3794
9b410801
EC		 3795static void
3796efx_ef10_filter_push_prep_set_match_fields(struct efx_nic *efx,
3797 const struct efx_filter_spec *spec,
3798 efx_dword_t *inbuf)
3799{
3800 enum efx_encap_type encap_type = efx_filter_get_encap_type(spec);
3801 u32 match_fields = 0, uc_match, mc_match;
3802
3803 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3804 efx_ef10_filter_is_exclusive(spec) ?
3805 MC_CMD_FILTER_OP_IN_OP_INSERT :
3806 MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE);
3807
3808 /* Convert match flags and values. Unlike almost
3809 * everything else in MCDI, these fields are in
3810 * network byte order.
3811 */
3812#define COPY_VALUE(value, mcdi_field) \
3813 do { \
3814 match_fields |= \
3815 1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \
3816 mcdi_field ## _LBN; \
3817 BUILD_BUG_ON( \
3818 MC_CMD_FILTER_OP_IN_ ## mcdi_field ## _LEN < \
3819 sizeof(value)); \
3820 memcpy(MCDI_PTR(inbuf, FILTER_OP_IN_ ## mcdi_field), \
3821 &value, sizeof(value)); \
3822 } while (0)
3823#define COPY_FIELD(gen_flag, gen_field, mcdi_field) \
3824 if (spec->match_flags & EFX_FILTER_MATCH_ ## gen_flag) { \
3825 COPY_VALUE(spec->gen_field, mcdi_field); \
3826 }
3827 /* Handle encap filters first. They will always be mismatch
3828 * (unknown UC or MC) filters
3829 */
3830 if (encap_type) {
3831 /* ether_type and outer_ip_proto need to be variables
3832 * because COPY_VALUE wants to memcpy them
3833 */
3834 __be16 ether_type =
3835 htons(encap_type & EFX_ENCAP_FLAG_IPV6 ?
3836 ETH_P_IPV6 : ETH_P_IP);
3837 u8 vni_type = MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_GENEVE;
3838 u8 outer_ip_proto;
3839
3840 switch (encap_type & EFX_ENCAP_TYPES_MASK) {
3841 case EFX_ENCAP_TYPE_VXLAN:
3842 vni_type = MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_VXLAN;
3843 /* fallthrough */
3844 case EFX_ENCAP_TYPE_GENEVE:
3845 COPY_VALUE(ether_type, ETHER_TYPE);
3846 outer_ip_proto = IPPROTO_UDP;
3847 COPY_VALUE(outer_ip_proto, IP_PROTO);
3848 /* We always need to set the type field, even
3849 * though we're not matching on the TNI.
3850 */
3851 MCDI_POPULATE_DWORD_1(inbuf,
3852 FILTER_OP_EXT_IN_VNI_OR_VSID,
3853 FILTER_OP_EXT_IN_VNI_TYPE,
3854 vni_type);
3855 break;
3856 case EFX_ENCAP_TYPE_NVGRE:
3857 COPY_VALUE(ether_type, ETHER_TYPE);
3858 outer_ip_proto = IPPROTO_GRE;
3859 COPY_VALUE(outer_ip_proto, IP_PROTO);
3860 break;
3861 default:
3862 WARN_ON(1);
3863 }
3864
3865 uc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_LBN;
3866 mc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_LBN;
3867 } else {
3868 uc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_LBN;
3869 mc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_LBN;
3870 }
3871
3872 if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC_IG)
3873 match_fields |=
3874 is_multicast_ether_addr(spec->loc_mac) ?
3875 1 << mc_match :
3876 1 << uc_match;
3877 COPY_FIELD(REM_HOST, rem_host, SRC_IP);
3878 COPY_FIELD(LOC_HOST, loc_host, DST_IP);
3879 COPY_FIELD(REM_MAC, rem_mac, SRC_MAC);
3880 COPY_FIELD(REM_PORT, rem_port, SRC_PORT);
3881 COPY_FIELD(LOC_MAC, loc_mac, DST_MAC);
3882 COPY_FIELD(LOC_PORT, loc_port, DST_PORT);
3883 COPY_FIELD(ETHER_TYPE, ether_type, ETHER_TYPE);
3884 COPY_FIELD(INNER_VID, inner_vid, INNER_VLAN);
3885 COPY_FIELD(OUTER_VID, outer_vid, OUTER_VLAN);
3886 COPY_FIELD(IP_PROTO, ip_proto, IP_PROTO);
3887#undef COPY_FIELD
3888#undef COPY_VALUE
3889 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_MATCH_FIELDS,
3890 match_fields);
3891}
3892
8127d661
BH		 3893static void efx_ef10_filter_push_prep(struct efx_nic *efx,
3894 const struct efx_filter_spec *spec,
3895 efx_dword_t *inbuf, u64 handle,
3896 bool replacing)
3897{
3898 struct efx_ef10_nic_data *nic_data = efx->nic_data;
dcb4123c 3899 u32 flags = spec->flags;
8127d661 3900
9b410801 3901 memset(inbuf, 0, MC_CMD_FILTER_OP_EXT_IN_LEN);
8127d661 3902
dcb4123c
JC		 3903 /* Remove RSS flag if we don't have an RSS context. */
3904 if (flags & EFX_FILTER_FLAG_RX_RSS &&
3905 spec->rss_context == EFX_FILTER_RSS_CONTEXT_DEFAULT &&
3906 nic_data->rx_rss_context == EFX_EF10_RSS_CONTEXT_INVALID)
3907 flags &= ~EFX_FILTER_FLAG_RX_RSS;
3908
8127d661
BH		 3909 if (replacing) {
3910 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3911 MC_CMD_FILTER_OP_IN_OP_REPLACE);
3912 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, handle);
3913 } else {
9b410801 3914 efx_ef10_filter_push_prep_set_match_fields(efx, spec, inbuf);
8127d661
BH		 3915 }
3916
45b2449e 3917 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_PORT_ID, nic_data->vport_id);
8127d661
BH		 3918 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_DEST,
3919 spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ?
3920 MC_CMD_FILTER_OP_IN_RX_DEST_DROP :
3921 MC_CMD_FILTER_OP_IN_RX_DEST_HOST);
e3d36293 3922 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DOMAIN, 0);
8127d661
BH		 3923 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DEST,
3924 MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT);
a0bc3487
BH		 3925 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_QUEUE,
3926 spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ?
3927 0 : spec->dmaq_id);
8127d661 3928 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_MODE,
dcb4123c 3929 (flags & EFX_FILTER_FLAG_RX_RSS) ?
8127d661
BH		 3930 MC_CMD_FILTER_OP_IN_RX_MODE_RSS :
3931 MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE);
dcb4123c 3932 if (flags & EFX_FILTER_FLAG_RX_RSS)
8127d661
BH		 3933 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_CONTEXT,
3934 spec->rss_context !=
3935 EFX_FILTER_RSS_CONTEXT_DEFAULT ?
3936 spec->rss_context : nic_data->rx_rss_context);
3937}
3938
3939static int efx_ef10_filter_push(struct efx_nic *efx,
3940 const struct efx_filter_spec *spec,
3941 u64 *handle, bool replacing)
3942{
9b410801
EC		 3943 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_EXT_IN_LEN);
3944 MCDI_DECLARE_BUF(outbuf, MC_CMD_FILTER_OP_EXT_OUT_LEN);
8127d661
BH		 3945 int rc;
3946
3947 efx_ef10_filter_push_prep(efx, spec, inbuf, *handle, replacing);
3948 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
3949 outbuf, sizeof(outbuf), NULL);
3950 if (rc == 0)
3951 *handle = MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE);
065e64c4
BH		 3952 if (rc == -ENOSPC)
3953 rc = -EBUSY; /* to match efx_farch_filter_insert() */
8127d661
BH		 3954 return rc;
3955}
3956
7ac0dd9d 3957static u32 efx_ef10_filter_mcdi_flags_from_spec(const struct efx_filter_spec *spec)
8127d661 3958{
9b410801 3959 enum efx_encap_type encap_type = efx_filter_get_encap_type(spec);
7ac0dd9d 3960 unsigned int match_flags = spec->match_flags;
9b410801 3961 unsigned int uc_match, mc_match;
7ac0dd9d
AR		 3962 u32 mcdi_flags = 0;
3963
9b410801
EC		 3964#define MAP_FILTER_TO_MCDI_FLAG(gen_flag, mcdi_field, encap) { \
3965 unsigned int old_match_flags = match_flags; \
7ac0dd9d
AR		 3966 match_flags &= ~EFX_FILTER_MATCH_ ## gen_flag; \
3967 if (match_flags != old_match_flags) \
3968 mcdi_flags |= \
9b410801
EC		 3969 (1 << ((encap) ? \
3970 MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_ ## \
3971 mcdi_field ## _LBN : \
3972 MC_CMD_FILTER_OP_EXT_IN_MATCH_ ##\
3973 mcdi_field ## _LBN)); \
7ac0dd9d 3974 }
9b410801
EC		 3975 /* inner or outer based on encap type */
3976 MAP_FILTER_TO_MCDI_FLAG(REM_HOST, SRC_IP, encap_type);
3977 MAP_FILTER_TO_MCDI_FLAG(LOC_HOST, DST_IP, encap_type);
3978 MAP_FILTER_TO_MCDI_FLAG(REM_MAC, SRC_MAC, encap_type);
3979 MAP_FILTER_TO_MCDI_FLAG(REM_PORT, SRC_PORT, encap_type);
3980 MAP_FILTER_TO_MCDI_FLAG(LOC_MAC, DST_MAC, encap_type);
3981 MAP_FILTER_TO_MCDI_FLAG(LOC_PORT, DST_PORT, encap_type);
3982 MAP_FILTER_TO_MCDI_FLAG(ETHER_TYPE, ETHER_TYPE, encap_type);
3983 MAP_FILTER_TO_MCDI_FLAG(IP_PROTO, IP_PROTO, encap_type);
3984 /* always outer */
3985 MAP_FILTER_TO_MCDI_FLAG(INNER_VID, INNER_VLAN, false);
3986 MAP_FILTER_TO_MCDI_FLAG(OUTER_VID, OUTER_VLAN, false);
7ac0dd9d
AR		 3987#undef MAP_FILTER_TO_MCDI_FLAG
3988
9b410801
EC		 3989 /* special handling for encap type, and mismatch */
3990 if (encap_type) {
3991 match_flags &= ~EFX_FILTER_MATCH_ENCAP_TYPE;
3992 mcdi_flags |=
3993 (1 << MC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_LBN);
3994 mcdi_flags |= (1 << MC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_LBN);
3995
3996 uc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_LBN;
3997 mc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_LBN;
3998 } else {
3999 uc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_LBN;
4000 mc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_LBN;
4001 }
4002
4003 if (match_flags & EFX_FILTER_MATCH_LOC_MAC_IG) {
4004 match_flags &= ~EFX_FILTER_MATCH_LOC_MAC_IG;
4005 mcdi_flags |=
4006 is_multicast_ether_addr(spec->loc_mac) ?
4007 1 << mc_match :
4008 1 << uc_match;
4009 }
4010
7ac0dd9d
AR		 4011 /* Did we map them all? */
4012 WARN_ON_ONCE(match_flags);
4013
4014 return mcdi_flags;
4015}
4016
4017static int efx_ef10_filter_pri(struct efx_ef10_filter_table *table,
4018 const struct efx_filter_spec *spec)
4019{
4020 u32 mcdi_flags = efx_ef10_filter_mcdi_flags_from_spec(spec);
8127d661
BH		 4021 unsigned int match_pri;
4022
4023 for (match_pri = 0;
4024 match_pri < table->rx_match_count;
4025 match_pri++)
7ac0dd9d 4026 if (table->rx_match_mcdi_flags[match_pri] == mcdi_flags)
8127d661
BH		 4027 return match_pri;
4028
4029 return -EPROTONOSUPPORT;
4030}
4031
4032static s32 efx_ef10_filter_insert(struct efx_nic *efx,
4033 struct efx_filter_spec *spec,
4034 bool replace_equal)
4035{
4036 struct efx_ef10_filter_table *table = efx->filter_state;
4037 DECLARE_BITMAP(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
4038 struct efx_filter_spec *saved_spec;
4039 unsigned int match_pri, hash;
4040 unsigned int priv_flags;
4041 bool replacing = false;
4042 int ins_index = -1;
4043 DEFINE_WAIT(wait);
4044 bool is_mc_recip;
4045 s32 rc;
4046
4047 /* For now, only support RX filters */
4048 if ((spec->flags & (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)) !=
4049 EFX_FILTER_FLAG_RX)
4050 return -EINVAL;
4051
7ac0dd9d 4052 rc = efx_ef10_filter_pri(table, spec);
8127d661
BH		 4053 if (rc < 0)
4054 return rc;
4055 match_pri = rc;
4056
4057 hash = efx_ef10_filter_hash(spec);
4058 is_mc_recip = efx_filter_is_mc_recipient(spec);
4059 if (is_mc_recip)
4060 bitmap_zero(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
4061
4062 /* Find any existing filters with the same match tuple or
4063 * else a free slot to insert at. If any of them are busy,
4064 * we have to wait and retry.
4065 */
4066 for (;;) {
4067 unsigned int depth = 1;
4068 unsigned int i;
4069
4070 spin_lock_bh(&efx->filter_lock);
4071
4072 for (;;) {
4073 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
4074 saved_spec = efx_ef10_filter_entry_spec(table, i);
4075
4076 if (!saved_spec) {
4077 if (ins_index < 0)
4078 ins_index = i;
4079 } else if (efx_ef10_filter_equal(spec, saved_spec)) {
4080 if (table->entry[i].spec &
4081 EFX_EF10_FILTER_FLAG_BUSY)
4082 break;
4083 if (spec->priority < saved_spec->priority &&
7665d1ab 4084 spec->priority != EFX_FILTER_PRI_AUTO) {
8127d661
BH		 4085 rc = -EPERM;
4086 goto out_unlock;
4087 }
4088 if (!is_mc_recip) {
4089 /* This is the only one */
4090 if (spec->priority ==
4091 saved_spec->priority &&
4092 !replace_equal) {
4093 rc = -EEXIST;
4094 goto out_unlock;
4095 }
4096 ins_index = i;
4097 goto found;
4098 } else if (spec->priority >
4099 saved_spec->priority ||
4100 (spec->priority ==
4101 saved_spec->priority &&
4102 replace_equal)) {
4103 if (ins_index < 0)
4104 ins_index = i;
4105 else
4106 __set_bit(depth, mc_rem_map);
4107 }
4108 }
4109
4110 /* Once we reach the maximum search depth, use
4111 * the first suitable slot or return -EBUSY if
4112 * there was none
4113 */
4114 if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) {
4115 if (ins_index < 0) {
4116 rc = -EBUSY;
4117 goto out_unlock;
4118 }
4119 goto found;
4120 }
4121
4122 ++depth;
4123 }
4124
4125 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE);
4126 spin_unlock_bh(&efx->filter_lock);
4127 schedule();
4128 }
4129
4130found:
4131 /* Create a software table entry if necessary, and mark it
4132 * busy. We might yet fail to insert, but any attempt to
4133 * insert a conflicting filter while we're waiting for the
4134 * firmware must find the busy entry.
4135 */
4136 saved_spec = efx_ef10_filter_entry_spec(table, ins_index);
4137 if (saved_spec) {
7665d1ab
BH		 4138 if (spec->priority == EFX_FILTER_PRI_AUTO &&
4139 saved_spec->priority >= EFX_FILTER_PRI_AUTO) {
8127d661 4140 /* Just make sure it won't be removed */
7665d1ab
BH		 4141 if (saved_spec->priority > EFX_FILTER_PRI_AUTO)
4142 saved_spec->flags |= EFX_FILTER_FLAG_RX_OVER_AUTO;
8127d661 4143 table->entry[ins_index].spec &=
b59e6ef8 4144 ~EFX_EF10_FILTER_FLAG_AUTO_OLD;
8127d661
BH		 4145 rc = ins_index;
4146 goto out_unlock;
4147 }
4148 replacing = true;
4149 priv_flags = efx_ef10_filter_entry_flags(table, ins_index);
4150 } else {
4151 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC);
4152 if (!saved_spec) {
4153 rc = -ENOMEM;
4154 goto out_unlock;
4155 }
4156 *saved_spec = *spec;
4157 priv_flags = 0;
4158 }
4159 efx_ef10_filter_set_entry(table, ins_index, saved_spec,
4160 priv_flags | EFX_EF10_FILTER_FLAG_BUSY);
4161
4162 /* Mark lower-priority multicast recipients busy prior to removal */
4163 if (is_mc_recip) {
4164 unsigned int depth, i;
4165
4166 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
4167 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
4168 if (test_bit(depth, mc_rem_map))
4169 table->entry[i].spec |=
4170 EFX_EF10_FILTER_FLAG_BUSY;
4171 }
4172 }
4173
4174 spin_unlock_bh(&efx->filter_lock);
4175
4176 rc = efx_ef10_filter_push(efx, spec, &table->entry[ins_index].handle,
4177 replacing);
4178
4179 /* Finalise the software table entry */
4180 spin_lock_bh(&efx->filter_lock);
4181 if (rc == 0) {
4182 if (replacing) {
4183 /* Update the fields that may differ */
7665d1ab
BH		 4184 if (saved_spec->priority == EFX_FILTER_PRI_AUTO)
4185 saved_spec->flags |=
4186 EFX_FILTER_FLAG_RX_OVER_AUTO;
8127d661 4187 saved_spec->priority = spec->priority;
7665d1ab 4188 saved_spec->flags &= EFX_FILTER_FLAG_RX_OVER_AUTO;
8127d661
BH		 4189 saved_spec->flags |= spec->flags;
4190 saved_spec->rss_context = spec->rss_context;
4191 saved_spec->dmaq_id = spec->dmaq_id;
4192 }
4193 } else if (!replacing) {
4194 kfree(saved_spec);
4195 saved_spec = NULL;
4196 }
4197 efx_ef10_filter_set_entry(table, ins_index, saved_spec, priv_flags);
4198
4199 /* Remove and finalise entries for lower-priority multicast
4200 * recipients
4201 */
4202 if (is_mc_recip) {
bb53f4d4 4203 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_EXT_IN_LEN);
8127d661
BH		 4204 unsigned int depth, i;
4205
4206 memset(inbuf, 0, sizeof(inbuf));
4207
4208 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
4209 if (!test_bit(depth, mc_rem_map))
4210 continue;
4211
4212 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
4213 saved_spec = efx_ef10_filter_entry_spec(table, i);
4214 priv_flags = efx_ef10_filter_entry_flags(table, i);
4215
4216 if (rc == 0) {
4217 spin_unlock_bh(&efx->filter_lock);
4218 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
4219 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
4220 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
4221 table->entry[i].handle);
4222 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP,
4223 inbuf, sizeof(inbuf),
4224 NULL, 0, NULL);
4225 spin_lock_bh(&efx->filter_lock);
4226 }
4227
4228 if (rc == 0) {
4229 kfree(saved_spec);
4230 saved_spec = NULL;
4231 priv_flags = 0;
4232 } else {
4233 priv_flags &= ~EFX_EF10_FILTER_FLAG_BUSY;
4234 }
4235 efx_ef10_filter_set_entry(table, i, saved_spec,
4236 priv_flags);
4237 }
4238 }
4239
4240 /* If successful, return the inserted filter ID */
4241 if (rc == 0)
0ccb998b 4242 rc = efx_ef10_make_filter_id(match_pri, ins_index);
8127d661
BH		 4243
4244 wake_up_all(&table->waitq);
4245out_unlock:
4246 spin_unlock_bh(&efx->filter_lock);
4247 finish_wait(&table->waitq, &wait);
4248 return rc;
4249}
4250
9fd8095d 4251static void efx_ef10_filter_update_rx_scatter(struct efx_nic *efx)
8127d661
BH		 4252{
4253 /* no need to do anything here on EF10 */
4254}
4255
4256/* Remove a filter.
b59e6ef8
BH		 4257 * If !by_index, remove by ID
4258 * If by_index, remove by index
8127d661
BH		 4259 * Filter ID may come from userland and must be range-checked.
4260 */
4261static int efx_ef10_filter_remove_internal(struct efx_nic *efx,
fbd79120 4262 unsigned int priority_mask,
b59e6ef8 4263 u32 filter_id, bool by_index)
8127d661 4264{
0ccb998b 4265 unsigned int filter_idx = efx_ef10_filter_get_unsafe_id(filter_id);
8127d661
BH		 4266 struct efx_ef10_filter_table *table = efx->filter_state;
4267 MCDI_DECLARE_BUF(inbuf,
4268 MC_CMD_FILTER_OP_IN_HANDLE_OFST +
4269 MC_CMD_FILTER_OP_IN_HANDLE_LEN);
4270 struct efx_filter_spec *spec;
4271 DEFINE_WAIT(wait);
4272 int rc;
4273
4274 /* Find the software table entry and mark it busy. Don't
4275 * remove it yet; any attempt to update while we're waiting
4276 * for the firmware must find the busy entry.
4277 */
4278 for (;;) {
4279 spin_lock_bh(&efx->filter_lock);
4280 if (!(table->entry[filter_idx].spec &
4281 EFX_EF10_FILTER_FLAG_BUSY))
4282 break;
4283 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE);
4284 spin_unlock_bh(&efx->filter_lock);
4285 schedule();
4286 }
7665d1ab 4287
8127d661 4288 spec = efx_ef10_filter_entry_spec(table, filter_idx);
7665d1ab 4289 if (!spec ||
b59e6ef8 4290 (!by_index &&
7ac0dd9d 4291 efx_ef10_filter_pri(table, spec) !=
0ccb998b 4292 efx_ef10_filter_get_unsafe_pri(filter_id))) {
8127d661
BH		 4293 rc = -ENOENT;
4294 goto out_unlock;
4295 }
7665d1ab
BH		 4296
4297 if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO &&
fbd79120 4298 priority_mask == (1U << EFX_FILTER_PRI_AUTO)) {
7665d1ab
BH		 4299 /* Just remove flags */
4300 spec->flags &= ~EFX_FILTER_FLAG_RX_OVER_AUTO;
b59e6ef8 4301 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_AUTO_OLD;
7665d1ab
BH		 4302 rc = 0;
4303 goto out_unlock;
4304 }
4305
fbd79120 4306 if (!(priority_mask & (1U << spec->priority))) {
7665d1ab
BH		 4307 rc = -ENOENT;
4308 goto out_unlock;
4309 }
4310
8127d661
BH		 4311 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
4312 spin_unlock_bh(&efx->filter_lock);
4313
7665d1ab 4314 if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO) {
b59e6ef8 4315 /* Reset to an automatic filter */
8127d661
BH		 4316
4317 struct efx_filter_spec new_spec = *spec;
4318
7665d1ab 4319 new_spec.priority = EFX_FILTER_PRI_AUTO;
8127d661 4320 new_spec.flags = (EFX_FILTER_FLAG_RX |
f1c2ef40
BK		 4321 (efx_rss_enabled(efx) ?
4322 EFX_FILTER_FLAG_RX_RSS : 0));
8127d661
BH		 4323 new_spec.dmaq_id = 0;
4324 new_spec.rss_context = EFX_FILTER_RSS_CONTEXT_DEFAULT;
4325 rc = efx_ef10_filter_push(efx, &new_spec,
4326 &table->entry[filter_idx].handle,
4327 true);
4328
4329 spin_lock_bh(&efx->filter_lock);
4330 if (rc == 0)
4331 *spec = new_spec;
4332 } else {
4333 /* Really remove the filter */
4334
4335 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
4336 efx_ef10_filter_is_exclusive(spec) ?
4337 MC_CMD_FILTER_OP_IN_OP_REMOVE :
4338 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
4339 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
4340 table->entry[filter_idx].handle);
105eac6c
BK		 4341 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FILTER_OP,
4342 inbuf, sizeof(inbuf), NULL, 0, NULL);
8127d661
BH		 4343
4344 spin_lock_bh(&efx->filter_lock);
105eac6c
BK		 4345 if ((rc == 0) || (rc == -ENOENT)) {
4346 /* Filter removed OK or didn't actually exist */
8127d661
BH		 4347 kfree(spec);
4348 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
105eac6c
BK		 4349 } else {
4350 efx_mcdi_display_error(efx, MC_CMD_FILTER_OP,
bb53f4d4 4351 MC_CMD_FILTER_OP_EXT_IN_LEN,
105eac6c 4352 NULL, 0, rc);
8127d661
BH		 4353 }
4354 }
7665d1ab 4355
8127d661
BH		 4356 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY;
4357 wake_up_all(&table->waitq);
4358out_unlock:
4359 spin_unlock_bh(&efx->filter_lock);
4360 finish_wait(&table->waitq, &wait);
4361 return rc;
4362}
4363
4364static int efx_ef10_filter_remove_safe(struct efx_nic *efx,
4365 enum efx_filter_priority priority,
4366 u32 filter_id)
4367{
fbd79120
BH		 4368 return efx_ef10_filter_remove_internal(efx, 1U << priority,
4369 filter_id, false);
8127d661
BH		 4370}
4371
8c915620
EC		 4372static void efx_ef10_filter_remove_unsafe(struct efx_nic *efx,
4373 enum efx_filter_priority priority,
4374 u32 filter_id)
12fb0da4 4375{
8c915620
EC		 4376 if (filter_id == EFX_EF10_FILTER_ID_INVALID)
4377 return;
4378 efx_ef10_filter_remove_internal(efx, 1U << priority, filter_id, true);
12fb0da4
EC		 4379}
4380
8127d661
BH		 4381static int efx_ef10_filter_get_safe(struct efx_nic *efx,
4382 enum efx_filter_priority priority,
4383 u32 filter_id, struct efx_filter_spec *spec)
4384{
0ccb998b 4385 unsigned int filter_idx = efx_ef10_filter_get_unsafe_id(filter_id);
8127d661
BH		 4386 struct efx_ef10_filter_table *table = efx->filter_state;
4387 const struct efx_filter_spec *saved_spec;
4388 int rc;
4389
4390 spin_lock_bh(&efx->filter_lock);
4391 saved_spec = efx_ef10_filter_entry_spec(table, filter_idx);
4392 if (saved_spec && saved_spec->priority == priority &&
7ac0dd9d 4393 efx_ef10_filter_pri(table, saved_spec) ==
0ccb998b 4394 efx_ef10_filter_get_unsafe_pri(filter_id)) {
8127d661
BH		 4395 *spec = *saved_spec;
4396 rc = 0;
4397 } else {
4398 rc = -ENOENT;
4399 }
4400 spin_unlock_bh(&efx->filter_lock);
4401 return rc;
4402}
4403
fbd79120 4404static int efx_ef10_filter_clear_rx(struct efx_nic *efx,
8127d661
BH		 4405 enum efx_filter_priority priority)
4406{
fbd79120
BH		 4407 unsigned int priority_mask;
4408 unsigned int i;
4409 int rc;
4410
4411 priority_mask = (((1U << (priority + 1)) - 1) &
4412 ~(1U << EFX_FILTER_PRI_AUTO));
4413
4414 for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) {
4415 rc = efx_ef10_filter_remove_internal(efx, priority_mask,
4416 i, true);
4417 if (rc && rc != -ENOENT)
4418 return rc;
4419 }
4420
4421 return 0;
8127d661
BH		 4422}
4423
4424static u32 efx_ef10_filter_count_rx_used(struct efx_nic *efx,
4425 enum efx_filter_priority priority)
4426{
4427 struct efx_ef10_filter_table *table = efx->filter_state;
4428 unsigned int filter_idx;
4429 s32 count = 0;
4430
4431 spin_lock_bh(&efx->filter_lock);
4432 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
4433 if (table->entry[filter_idx].spec &&
4434 efx_ef10_filter_entry_spec(table, filter_idx)->priority ==
4435 priority)
4436 ++count;
4437 }
4438 spin_unlock_bh(&efx->filter_lock);
4439 return count;
4440}
4441
4442static u32 efx_ef10_filter_get_rx_id_limit(struct efx_nic *efx)
4443{
4444 struct efx_ef10_filter_table *table = efx->filter_state;
4445
0ccb998b 4446 return table->rx_match_count * HUNT_FILTER_TBL_ROWS * 2;
8127d661
BH		 4447}
4448
4449static s32 efx_ef10_filter_get_rx_ids(struct efx_nic *efx,
4450 enum efx_filter_priority priority,
4451 u32 *buf, u32 size)
4452{
4453 struct efx_ef10_filter_table *table = efx->filter_state;
4454 struct efx_filter_spec *spec;
4455 unsigned int filter_idx;
4456 s32 count = 0;
4457
4458 spin_lock_bh(&efx->filter_lock);
4459 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
4460 spec = efx_ef10_filter_entry_spec(table, filter_idx);
4461 if (spec && spec->priority == priority) {
4462 if (count == size) {
4463 count = -EMSGSIZE;
4464 break;
4465 }
0ccb998b
JC		 4466 buf[count++] =
4467 efx_ef10_make_filter_id(
4468 efx_ef10_filter_pri(table, spec),
8127d661
BH		 4469 filter_idx);
4470 }
4471 }
4472 spin_unlock_bh(&efx->filter_lock);
4473 return count;
4474}
4475
4476#ifdef CONFIG_RFS_ACCEL
4477
4478static efx_mcdi_async_completer efx_ef10_filter_rfs_insert_complete;
4479
4480static s32 efx_ef10_filter_rfs_insert(struct efx_nic *efx,
4481 struct efx_filter_spec *spec)
4482{
4483 struct efx_ef10_filter_table *table = efx->filter_state;
bb53f4d4 4484 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_EXT_IN_LEN);
8127d661
BH		 4485 struct efx_filter_spec *saved_spec;
4486 unsigned int hash, i, depth = 1;
4487 bool replacing = false;
4488 int ins_index = -1;
4489 u64 cookie;
4490 s32 rc;
4491
4492 /* Must be an RX filter without RSS and not for a multicast
4493 * destination address (RFS only works for connected sockets).
4494 * These restrictions allow us to pass only a tiny amount of
4495 * data through to the completion function.
4496 */
4497 EFX_WARN_ON_PARANOID(spec->flags !=
4498 (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_RX_SCATTER));
4499 EFX_WARN_ON_PARANOID(spec->priority != EFX_FILTER_PRI_HINT);
4500 EFX_WARN_ON_PARANOID(efx_filter_is_mc_recipient(spec));
4501
4502 hash = efx_ef10_filter_hash(spec);
4503
4504 spin_lock_bh(&efx->filter_lock);
4505
4506 /* Find any existing filter with the same match tuple or else
4507 * a free slot to insert at. If an existing filter is busy,
4508 * we have to give up.
4509 */
4510 for (;;) {
4511 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
4512 saved_spec = efx_ef10_filter_entry_spec(table, i);
4513
4514 if (!saved_spec) {
4515 if (ins_index < 0)
4516 ins_index = i;
4517 } else if (efx_ef10_filter_equal(spec, saved_spec)) {
4518 if (table->entry[i].spec & EFX_EF10_FILTER_FLAG_BUSY) {
4519 rc = -EBUSY;
4520 goto fail_unlock;
4521 }
8127d661
BH		 4522 if (spec->priority < saved_spec->priority) {
4523 rc = -EPERM;
4524 goto fail_unlock;
4525 }
4526 ins_index = i;
4527 break;
4528 }
4529
4530 /* Once we reach the maximum search depth, use the
4531 * first suitable slot or return -EBUSY if there was
4532 * none
4533 */
4534 if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) {
4535 if (ins_index < 0) {
4536 rc = -EBUSY;
4537 goto fail_unlock;
4538 }
4539 break;
4540 }
4541
4542 ++depth;
4543 }
4544
4545 /* Create a software table entry if necessary, and mark it
4546 * busy. We might yet fail to insert, but any attempt to
4547 * insert a conflicting filter while we're waiting for the
4548 * firmware must find the busy entry.
4549 */
4550 saved_spec = efx_ef10_filter_entry_spec(table, ins_index);
4551 if (saved_spec) {
4552 replacing = true;
4553 } else {
4554 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC);
4555 if (!saved_spec) {
4556 rc = -ENOMEM;
4557 goto fail_unlock;
4558 }
4559 *saved_spec = *spec;
4560 }
4561 efx_ef10_filter_set_entry(table, ins_index, saved_spec,
4562 EFX_EF10_FILTER_FLAG_BUSY);
4563
4564 spin_unlock_bh(&efx->filter_lock);
4565
4566 /* Pack up the variables needed on completion */
4567 cookie = replacing << 31 | ins_index << 16 | spec->dmaq_id;
4568
4569 efx_ef10_filter_push_prep(efx, spec, inbuf,
4570 table->entry[ins_index].handle, replacing);
4571 efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
4572 MC_CMD_FILTER_OP_OUT_LEN,
4573 efx_ef10_filter_rfs_insert_complete, cookie);
4574
4575 return ins_index;
4576
4577fail_unlock:
4578 spin_unlock_bh(&efx->filter_lock);
4579 return rc;
4580}
4581
4582static void
4583efx_ef10_filter_rfs_insert_complete(struct efx_nic *efx, unsigned long cookie,
4584 int rc, efx_dword_t *outbuf,
4585 size_t outlen_actual)
4586{
4587 struct efx_ef10_filter_table *table = efx->filter_state;
4588 unsigned int ins_index, dmaq_id;
4589 struct efx_filter_spec *spec;
4590 bool replacing;
4591
4592 /* Unpack the cookie */
4593 replacing = cookie >> 31;
4594 ins_index = (cookie >> 16) & (HUNT_FILTER_TBL_ROWS - 1);
4595 dmaq_id = cookie & 0xffff;
4596
4597 spin_lock_bh(&efx->filter_lock);
4598 spec = efx_ef10_filter_entry_spec(table, ins_index);
4599 if (rc == 0) {
4600 table->entry[ins_index].handle =
4601 MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE);
4602 if (replacing)
4603 spec->dmaq_id = dmaq_id;
4604 } else if (!replacing) {
4605 kfree(spec);
4606 spec = NULL;
4607 }
4608 efx_ef10_filter_set_entry(table, ins_index, spec, 0);
4609 spin_unlock_bh(&efx->filter_lock);
4610
4611 wake_up_all(&table->waitq);
4612}
4613
4614static void
4615efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx,
4616 unsigned long filter_idx,
4617 int rc, efx_dword_t *outbuf,
4618 size_t outlen_actual);
4619
4620static bool efx_ef10_filter_rfs_expire_one(struct efx_nic *efx, u32 flow_id,
4621 unsigned int filter_idx)
4622{
4623 struct efx_ef10_filter_table *table = efx->filter_state;
4624 struct efx_filter_spec *spec =
4625 efx_ef10_filter_entry_spec(table, filter_idx);
4626 MCDI_DECLARE_BUF(inbuf,
4627 MC_CMD_FILTER_OP_IN_HANDLE_OFST +
4628 MC_CMD_FILTER_OP_IN_HANDLE_LEN);
4629
4630 if (!spec ||
4631 (table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAG_BUSY) ||
4632 spec->priority != EFX_FILTER_PRI_HINT ||
4633 !rps_may_expire_flow(efx->net_dev, spec->dmaq_id,
4634 flow_id, filter_idx))
4635 return false;
4636
4637 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
4638 MC_CMD_FILTER_OP_IN_OP_REMOVE);
4639 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
4640 table->entry[filter_idx].handle);
4641 if (efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf), 0,
4642 efx_ef10_filter_rfs_expire_complete, filter_idx))
4643 return false;
4644
4645 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
4646 return true;
4647}
4648
4649static void
4650efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx,
4651 unsigned long filter_idx,
4652 int rc, efx_dword_t *outbuf,
4653 size_t outlen_actual)
4654{
4655 struct efx_ef10_filter_table *table = efx->filter_state;
4656 struct efx_filter_spec *spec =
4657 efx_ef10_filter_entry_spec(table, filter_idx);
4658
4659 spin_lock_bh(&efx->filter_lock);
4660 if (rc == 0) {
4661 kfree(spec);
4662 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
4663 }
4664 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY;
4665 wake_up_all(&table->waitq);
4666 spin_unlock_bh(&efx->filter_lock);
4667}
4668
4669#endif /* CONFIG_RFS_ACCEL */
4670
9b410801 4671static int efx_ef10_filter_match_flags_from_mcdi(bool encap, u32 mcdi_flags)
8127d661
BH		 4672{
4673 int match_flags = 0;
4674
9b410801 4675#define MAP_FLAG(gen_flag, mcdi_field) do { \
8127d661 4676 u32 old_mcdi_flags = mcdi_flags; \
9b410801
EC		 4677 mcdi_flags &= ~(1 << MC_CMD_FILTER_OP_EXT_IN_MATCH_ ## \
4678 mcdi_field ## _LBN); \
8127d661
BH		 4679 if (mcdi_flags != old_mcdi_flags) \
4680 match_flags |= EFX_FILTER_MATCH_ ## gen_flag; \
9b410801
EC		 4681 } while (0)
4682
4683 if (encap) {
4684 /* encap filters must specify encap type */
4685 match_flags |= EFX_FILTER_MATCH_ENCAP_TYPE;
4686 /* and imply ethertype and ip proto */
4687 mcdi_flags &=
4688 ~(1 << MC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_LBN);
4689 mcdi_flags &=
4690 ~(1 << MC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_LBN);
4691 /* VLAN tags refer to the outer packet */
4692 MAP_FLAG(INNER_VID, INNER_VLAN);
4693 MAP_FLAG(OUTER_VID, OUTER_VLAN);
4694 /* everything else refers to the inner packet */
4695 MAP_FLAG(LOC_MAC_IG, IFRM_UNKNOWN_UCAST_DST);
4696 MAP_FLAG(LOC_MAC_IG, IFRM_UNKNOWN_MCAST_DST);
4697 MAP_FLAG(REM_HOST, IFRM_SRC_IP);
4698 MAP_FLAG(LOC_HOST, IFRM_DST_IP);
4699 MAP_FLAG(REM_MAC, IFRM_SRC_MAC);
4700 MAP_FLAG(REM_PORT, IFRM_SRC_PORT);
4701 MAP_FLAG(LOC_MAC, IFRM_DST_MAC);
4702 MAP_FLAG(LOC_PORT, IFRM_DST_PORT);
4703 MAP_FLAG(ETHER_TYPE, IFRM_ETHER_TYPE);
4704 MAP_FLAG(IP_PROTO, IFRM_IP_PROTO);
4705 } else {
4706 MAP_FLAG(LOC_MAC_IG, UNKNOWN_UCAST_DST);
4707 MAP_FLAG(LOC_MAC_IG, UNKNOWN_MCAST_DST);
4708 MAP_FLAG(REM_HOST, SRC_IP);
4709 MAP_FLAG(LOC_HOST, DST_IP);
4710 MAP_FLAG(REM_MAC, SRC_MAC);
4711 MAP_FLAG(REM_PORT, SRC_PORT);
4712 MAP_FLAG(LOC_MAC, DST_MAC);
4713 MAP_FLAG(LOC_PORT, DST_PORT);
4714 MAP_FLAG(ETHER_TYPE, ETHER_TYPE);
4715 MAP_FLAG(INNER_VID, INNER_VLAN);
4716 MAP_FLAG(OUTER_VID, OUTER_VLAN);
4717 MAP_FLAG(IP_PROTO, IP_PROTO);
8127d661 4718 }
8127d661
BH		 4719#undef MAP_FLAG
4720
4721 /* Did we map them all? */
4722 if (mcdi_flags)
4723 return -EINVAL;
4724
4725 return match_flags;
4726}
4727
34813fe2
AR		 4728static void efx_ef10_filter_cleanup_vlans(struct efx_nic *efx)
4729{
4730 struct efx_ef10_filter_table *table = efx->filter_state;
4731 struct efx_ef10_filter_vlan *vlan, *next_vlan;
4732
4733 /* See comment in efx_ef10_filter_table_remove() */
4734 if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
4735 return;
4736
4737 if (!table)
4738 return;
4739
4740 list_for_each_entry_safe(vlan, next_vlan, &table->vlan_list, list)
4741 efx_ef10_filter_del_vlan_internal(efx, vlan);
4742}
4743
7ac0dd9d 4744static bool efx_ef10_filter_match_supported(struct efx_ef10_filter_table *table,
9b410801 4745 bool encap,
7ac0dd9d
AR		 4746 enum efx_filter_match_flags match_flags)
4747{
4748 unsigned int match_pri;
4749 int mf;
4750
4751 for (match_pri = 0;
4752 match_pri < table->rx_match_count;
4753 match_pri++) {
9b410801 4754 mf = efx_ef10_filter_match_flags_from_mcdi(encap,
7ac0dd9d
AR		 4755 table->rx_match_mcdi_flags[match_pri]);
4756 if (mf == match_flags)
4757 return true;
4758 }
4759
4760 return false;
4761}
4762
9b410801
EC		 4763static int
4764efx_ef10_filter_table_probe_matches(struct efx_nic *efx,
4765 struct efx_ef10_filter_table *table,
4766 bool encap)
8127d661
BH		 4767{
4768 MCDI_DECLARE_BUF(inbuf, MC_CMD_GET_PARSER_DISP_INFO_IN_LEN);
4769 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX);
4770 unsigned int pd_match_pri, pd_match_count;
8127d661
BH		 4771 size_t outlen;
4772 int rc;
4773
8127d661
BH		 4774 /* Find out which RX filter types are supported, and their priorities */
4775 MCDI_SET_DWORD(inbuf, GET_PARSER_DISP_INFO_IN_OP,
9b410801
EC		 4776 encap ?
4777 MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_ENCAP_RX_MATCHES :
8127d661
BH		 4778 MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES);
4779 rc = efx_mcdi_rpc(efx, MC_CMD_GET_PARSER_DISP_INFO,
4780 inbuf, sizeof(inbuf), outbuf, sizeof(outbuf),
4781 &outlen);
4782 if (rc)
9b410801
EC		 4783 return rc;
4784
8127d661
BH		 4785 pd_match_count = MCDI_VAR_ARRAY_LEN(
4786 outlen, GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES);
8127d661
BH		 4787
4788 for (pd_match_pri = 0; pd_match_pri < pd_match_count; pd_match_pri++) {
4789 u32 mcdi_flags =
4790 MCDI_ARRAY_DWORD(
4791 outbuf,
4792 GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES,
4793 pd_match_pri);
9b410801 4794 rc = efx_ef10_filter_match_flags_from_mcdi(encap, mcdi_flags);
8127d661
BH		 4795 if (rc < 0) {
4796 netif_dbg(efx, probe, efx->net_dev,
4797 "%s: fw flags %#x pri %u not supported in driver\n",
4798 __func__, mcdi_flags, pd_match_pri);
4799 } else {
4800 netif_dbg(efx, probe, efx->net_dev,
4801 "%s: fw flags %#x pri %u supported as driver flags %#x pri %u\n",
4802 __func__, mcdi_flags, pd_match_pri,
4803 rc, table->rx_match_count);
7ac0dd9d
AR		 4804 table->rx_match_mcdi_flags[table->rx_match_count] = mcdi_flags;
4805 table->rx_match_count++;
8127d661
BH		 4806 }
4807 }
4808
9b410801
EC		 4809 return 0;
4810}
4811
4812static int efx_ef10_filter_table_probe(struct efx_nic *efx)
4813{
4814 struct efx_ef10_nic_data *nic_data = efx->nic_data;
4815 struct net_device *net_dev = efx->net_dev;
4816 struct efx_ef10_filter_table *table;
4817 struct efx_ef10_vlan *vlan;
4818 int rc;
4819
4820 if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
4821 return -EINVAL;
4822
4823 if (efx->filter_state) /* already probed */
4824 return 0;
4825
4826 table = kzalloc(sizeof(*table), GFP_KERNEL);
4827 if (!table)
4828 return -ENOMEM;
4829
4830 table->rx_match_count = 0;
4831 rc = efx_ef10_filter_table_probe_matches(efx, table, false);
4832 if (rc)
4833 goto fail;
4834 if (nic_data->datapath_caps &
4835 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN))
4836 rc = efx_ef10_filter_table_probe_matches(efx, table, true);
4837 if (rc)
4838 goto fail;
e4478ad1 4839 if ((efx_supported_features(efx) & NETIF_F_HW_VLAN_CTAG_FILTER) &&
9b410801 4840 !(efx_ef10_filter_match_supported(table, false,
e4478ad1 4841 (EFX_FILTER_MATCH_OUTER_VID | EFX_FILTER_MATCH_LOC_MAC)) &&
9b410801 4842 efx_ef10_filter_match_supported(table, false,
e4478ad1
MH		 4843 (EFX_FILTER_MATCH_OUTER_VID | EFX_FILTER_MATCH_LOC_MAC_IG)))) {
4844 netif_info(efx, probe, net_dev,
4845 "VLAN filters are not supported in this firmware variant\n");
4846 net_dev->features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
4847 efx->fixed_features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
4848 net_dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
4849 }
4850
8127d661
BH		 4851 table->entry = vzalloc(HUNT_FILTER_TBL_ROWS * sizeof(*table->entry));
4852 if (!table->entry) {
4853 rc = -ENOMEM;
4854 goto fail;
4855 }
4856
b071c3a2 4857 table->mc_promisc_last = false;
4a53ea8a
AR		 4858 table->vlan_filter =
4859 !!(efx->net_dev->features & NETIF_F_HW_VLAN_CTAG_FILTER);
34813fe2 4860 INIT_LIST_HEAD(&table->vlan_list);
12fb0da4 4861
8127d661
BH		 4862 efx->filter_state = table;
4863 init_waitqueue_head(&table->waitq);
34813fe2
AR		 4864
4865 list_for_each_entry(vlan, &nic_data->vlan_list, list) {
4866 rc = efx_ef10_filter_add_vlan(efx, vlan->vid);
4867 if (rc)
4868 goto fail_add_vlan;
4869 }
4870
8127d661
BH		 4871 return 0;
4872
34813fe2
AR		 4873fail_add_vlan:
4874 efx_ef10_filter_cleanup_vlans(efx);
4875 efx->filter_state = NULL;
8127d661
BH		 4876fail:
4877 kfree(table);
4878 return rc;
4879}
4880
0d322413
EC		 4881/* Caller must hold efx->filter_sem for read if race against
4882 * efx_ef10_filter_table_remove() is possible
4883 */
8127d661
BH		 4884static void efx_ef10_filter_table_restore(struct efx_nic *efx)
4885{
4886 struct efx_ef10_filter_table *table = efx->filter_state;
4887 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2d3d4ec0
JC		 4888 unsigned int invalid_filters = 0, failed = 0;
4889 struct efx_ef10_filter_vlan *vlan;
8127d661
BH		 4890 struct efx_filter_spec *spec;
4891 unsigned int filter_idx;
2d3d4ec0
JC		 4892 u32 mcdi_flags;
4893 int match_pri;
9b410801 4894 int rc, i;
8127d661 4895
0d322413
EC		 4896 WARN_ON(!rwsem_is_locked(&efx->filter_sem));
4897
8127d661
BH		 4898 if (!nic_data->must_restore_filters)
4899 return;
4900
0d322413
EC		 4901 if (!table)
4902 return;
4903
8127d661
BH		 4904 spin_lock_bh(&efx->filter_lock);
4905
4906 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
4907 spec = efx_ef10_filter_entry_spec(table, filter_idx);
4908 if (!spec)
4909 continue;
4910
2d3d4ec0
JC		 4911 mcdi_flags = efx_ef10_filter_mcdi_flags_from_spec(spec);
4912 match_pri = 0;
4913 while (match_pri < table->rx_match_count &&
4914 table->rx_match_mcdi_flags[match_pri] != mcdi_flags)
4915 ++match_pri;
4916 if (match_pri >= table->rx_match_count) {
4917 invalid_filters++;
4918 goto not_restored;
4919 }
4920 if (spec->rss_context != EFX_FILTER_RSS_CONTEXT_DEFAULT &&
4921 spec->rss_context != nic_data->rx_rss_context)
4922 netif_warn(efx, drv, efx->net_dev,
4923 "Warning: unable to restore a filter with specific RSS context.\n");
4924
8127d661
BH		 4925 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
4926 spin_unlock_bh(&efx->filter_lock);
4927
4928 rc = efx_ef10_filter_push(efx, spec,
4929 &table->entry[filter_idx].handle,
4930 false);
4931 if (rc)
2d3d4ec0 4932 failed++;
8127d661 4933 spin_lock_bh(&efx->filter_lock);
2d3d4ec0 4934
8127d661 4935 if (rc) {
2d3d4ec0 4936not_restored:
9b410801
EC		 4937 list_for_each_entry(vlan, &table->vlan_list, list)
4938 for (i = 0; i < EFX_EF10_NUM_DEFAULT_FILTERS; ++i)
4939 if (vlan->default_filters[i] == filter_idx)
4940 vlan->default_filters[i] =
4941 EFX_EF10_FILTER_ID_INVALID;
4942
8127d661
BH		 4943 kfree(spec);
4944 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
4945 } else {
4946 table->entry[filter_idx].spec &=
4947 ~EFX_EF10_FILTER_FLAG_BUSY;
4948 }
4949 }
4950
4951 spin_unlock_bh(&efx->filter_lock);
4952
2d3d4ec0
JC		 4953 /* This can happen validly if the MC's capabilities have changed, so
4954 * is not an error.
4955 */
4956 if (invalid_filters)
4957 netif_dbg(efx, drv, efx->net_dev,
4958 "Did not restore %u filters that are now unsupported.\n",
4959 invalid_filters);
4960
8127d661
BH		 4961 if (failed)
4962 netif_err(efx, hw, efx->net_dev,
2d3d4ec0 4963 "unable to restore %u filters\n", failed);
8127d661
BH		 4964 else
4965 nic_data->must_restore_filters = false;
4966}
4967
4968static void efx_ef10_filter_table_remove(struct efx_nic *efx)
4969{
4970 struct efx_ef10_filter_table *table = efx->filter_state;
bb53f4d4 4971 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_EXT_IN_LEN);
8127d661
BH		 4972 struct efx_filter_spec *spec;
4973 unsigned int filter_idx;
4974 int rc;
4975
34813fe2 4976 efx_ef10_filter_cleanup_vlans(efx);
0d322413 4977 efx->filter_state = NULL;
dd98708c
EC		 4978 /* If we were called without locking, then it's not safe to free
4979 * the table as others might be using it. So we just WARN, leak
4980 * the memory, and potentially get an inconsistent filter table
4981 * state.
4982 * This should never actually happen.
4983 */
4984 if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
4985 return;
4986
0d322413
EC		 4987 if (!table)
4988 return;
4989
8127d661
BH		 4990 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
4991 spec = efx_ef10_filter_entry_spec(table, filter_idx);
4992 if (!spec)
4993 continue;
4994
4995 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
4996 efx_ef10_filter_is_exclusive(spec) ?
4997 MC_CMD_FILTER_OP_IN_OP_REMOVE :
4998 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
4999 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
5000 table->entry[filter_idx].handle);
e65a5109
BK		 5001 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FILTER_OP, inbuf,
5002 sizeof(inbuf), NULL, 0, NULL);
48ce5634 5003 if (rc)
e65a5109
BK		 5004 netif_info(efx, drv, efx->net_dev,
5005 "%s: filter %04x remove failed\n",
5006 __func__, filter_idx);
8127d661
BH		 5007 kfree(spec);
5008 }
5009
5010 vfree(table->entry);
5011 kfree(table);
5012}
5013
6a37958b
AR		 5014static void efx_ef10_filter_mark_one_old(struct efx_nic *efx, uint16_t *id)
5015{
5016 struct efx_ef10_filter_table *table = efx->filter_state;
5017 unsigned int filter_idx;
5018
5019 if (*id != EFX_EF10_FILTER_ID_INVALID) {
0ccb998b 5020 filter_idx = efx_ef10_filter_get_unsafe_id(*id);
6a37958b
AR		 5021 if (!table->entry[filter_idx].spec)
5022 netif_dbg(efx, drv, efx->net_dev,
5023 "marked null spec old %04x:%04x\n", *id,
5024 filter_idx);
5025 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_AUTO_OLD;
5026 *id = EFX_EF10_FILTER_ID_INVALID;
e65a5109 5027 }
6a37958b
AR		 5028}
5029
b3a3c03c
AR		 5030/* Mark old per-VLAN filters that may need to be removed */
5031static void _efx_ef10_filter_vlan_mark_old(struct efx_nic *efx,
5032 struct efx_ef10_filter_vlan *vlan)
8127d661
BH		 5033{
5034 struct efx_ef10_filter_table *table = efx->filter_state;
6a37958b 5035 unsigned int i;
8127d661 5036
12fb0da4 5037 for (i = 0; i < table->dev_uc_count; i++)
dc3273e0 5038 efx_ef10_filter_mark_one_old(efx, &vlan->uc[i]);
12fb0da4 5039 for (i = 0; i < table->dev_mc_count; i++)
dc3273e0 5040 efx_ef10_filter_mark_one_old(efx, &vlan->mc[i]);
9b410801
EC		 5041 for (i = 0; i < EFX_EF10_NUM_DEFAULT_FILTERS; i++)
5042 efx_ef10_filter_mark_one_old(efx, &vlan->default_filters[i]);
b3a3c03c
AR		 5043}
5044
34813fe2
AR		 5045/* Mark old filters that may need to be removed.
5046 * Caller must hold efx->filter_sem for read if race against
5047 * efx_ef10_filter_table_remove() is possible
5048 */
b3a3c03c
AR		 5049static void efx_ef10_filter_mark_old(struct efx_nic *efx)
5050{
5051 struct efx_ef10_filter_table *table = efx->filter_state;
34813fe2 5052 struct efx_ef10_filter_vlan *vlan;
b3a3c03c
AR		 5053
5054 spin_lock_bh(&efx->filter_lock);
34813fe2
AR		 5055 list_for_each_entry(vlan, &table->vlan_list, list)
5056 _efx_ef10_filter_vlan_mark_old(efx, vlan);
8127d661 5057 spin_unlock_bh(&efx->filter_lock);
822b96f8
DP		 5058}
5059
afa4ce12 5060static void efx_ef10_filter_uc_addr_list(struct efx_nic *efx)
822b96f8
DP		 5061{
5062 struct efx_ef10_filter_table *table = efx->filter_state;
5063 struct net_device *net_dev = efx->net_dev;
5064 struct netdev_hw_addr *uc;
5065 unsigned int i;
8127d661 5066
afa4ce12 5067 table->uc_promisc = !!(net_dev->flags & IFF_PROMISC);
822b96f8
DP		 5068 ether_addr_copy(table->dev_uc_list[0].addr, net_dev->dev_addr);
5069 i = 1;
5070 netdev_for_each_uc_addr(uc, net_dev) {
12fb0da4 5071 if (i >= EFX_EF10_FILTER_DEV_UC_MAX) {
afa4ce12 5072 table->uc_promisc = true;
12fb0da4
EC		 5073 break;
5074 }
822b96f8
DP		 5075 ether_addr_copy(table->dev_uc_list[i].addr, uc->addr);
5076 i++;
5077 }
c70d6815
BK		 5078
5079 table->dev_uc_count = i;
822b96f8
DP		 5080}
5081
afa4ce12 5082static void efx_ef10_filter_mc_addr_list(struct efx_nic *efx)
822b96f8
DP		 5083{
5084 struct efx_ef10_filter_table *table = efx->filter_state;
5085 struct net_device *net_dev = efx->net_dev;
5086 struct netdev_hw_addr *mc;
c70d6815 5087 unsigned int i;
822b96f8 5088
148cbab6 5089 table->mc_overflow = false;
afa4ce12 5090 table->mc_promisc = !!(net_dev->flags & (IFF_PROMISC | IFF_ALLMULTI));
ab8b1f7c 5091
12fb0da4 5092 i = 0;
ab8b1f7c 5093 netdev_for_each_mc_addr(mc, net_dev) {
12fb0da4 5094 if (i >= EFX_EF10_FILTER_DEV_MC_MAX) {
afa4ce12 5095 table->mc_promisc = true;
148cbab6 5096 table->mc_overflow = true;
12fb0da4
EC		 5097 break;
5098 }
ab8b1f7c
DP		 5099 ether_addr_copy(table->dev_mc_list[i].addr, mc->addr);
5100 i++;
8127d661 5101 }
12fb0da4
EC		 5102
5103 table->dev_mc_count = i;
822b96f8 5104}
8127d661 5105
12fb0da4 5106static int efx_ef10_filter_insert_addr_list(struct efx_nic *efx,
b3a3c03c
AR		 5107 struct efx_ef10_filter_vlan *vlan,
5108 bool multicast, bool rollback)
822b96f8
DP		 5109{
5110 struct efx_ef10_filter_table *table = efx->filter_state;
5111 struct efx_ef10_dev_addr *addr_list;
f1c2ef40 5112 enum efx_filter_flags filter_flags;
822b96f8 5113 struct efx_filter_spec spec;
12fb0da4
EC		 5114 u8 baddr[ETH_ALEN];
5115 unsigned int i, j;
5116 int addr_count;
dc3273e0 5117 u16 *ids;
822b96f8
DP		 5118 int rc;
5119
5120 if (multicast) {
5121 addr_list = table->dev_mc_list;
12fb0da4 5122 addr_count = table->dev_mc_count;
dc3273e0 5123 ids = vlan->mc;
822b96f8
DP		 5124 } else {
5125 addr_list = table->dev_uc_list;
12fb0da4 5126 addr_count = table->dev_uc_count;
dc3273e0 5127 ids = vlan->uc;
8127d661
BH		 5128 }
5129
f1c2ef40
BK		 5130 filter_flags = efx_rss_enabled(efx) ? EFX_FILTER_FLAG_RX_RSS : 0;
5131
822b96f8 5132 /* Insert/renew filters */
12fb0da4 5133 for (i = 0; i < addr_count; i++) {
d58299a4 5134 EFX_WARN_ON_PARANOID(ids[i] != EFX_EF10_FILTER_ID_INVALID);
f1c2ef40 5135 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, 0);
b3a3c03c 5136 efx_filter_set_eth_local(&spec, vlan->vid, addr_list[i].addr);
b6f568e2
JC		 5137 rc = efx_ef10_filter_insert(efx, &spec, true);
5138 if (rc < 0) {
12fb0da4
EC		 5139 if (rollback) {
5140 netif_info(efx, drv, efx->net_dev,
5141 "efx_ef10_filter_insert failed rc=%d\n",
5142 rc);
5143 /* Fall back to promiscuous */
5144 for (j = 0; j < i; j++) {
12fb0da4
EC		 5145 efx_ef10_filter_remove_unsafe(
5146 efx, EFX_FILTER_PRI_AUTO,
dc3273e0
AR		 5147 ids[j]);
5148 ids[j] = EFX_EF10_FILTER_ID_INVALID;
12fb0da4
EC		 5149 }
5150 return rc;
5151 } else {
d58299a4 5152 /* keep invalid ID, and carry on */
822b96f8 5153 }
d58299a4
EC		 5154 } else {
5155 ids[i] = efx_ef10_filter_get_unsafe_id(rc);
8127d661
BH		 5156 }
5157 }
822b96f8 5158
12fb0da4
EC		 5159 if (multicast && rollback) {
5160 /* Also need an Ethernet broadcast filter */
9b410801
EC		 5161 EFX_WARN_ON_PARANOID(vlan->default_filters[EFX_EF10_BCAST] !=
5162 EFX_EF10_FILTER_ID_INVALID);
f1c2ef40 5163 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, 0);
12fb0da4 5164 eth_broadcast_addr(baddr);
b3a3c03c 5165 efx_filter_set_eth_local(&spec, vlan->vid, baddr);
8127d661 5166 rc = efx_ef10_filter_insert(efx, &spec, true);
12fb0da4 5167 if (rc < 0) {
822b96f8 5168 netif_warn(efx, drv, efx->net_dev,
12fb0da4
EC		 5169 "Broadcast filter insert failed rc=%d\n", rc);
5170 /* Fall back to promiscuous */
5171 for (j = 0; j < i; j++) {
12fb0da4
EC		 5172 efx_ef10_filter_remove_unsafe(
5173 efx, EFX_FILTER_PRI_AUTO,
dc3273e0
AR		 5174 ids[j]);
5175 ids[j] = EFX_EF10_FILTER_ID_INVALID;
12fb0da4
EC		 5176 }
5177 return rc;
5178 } else {
9b410801 5179 vlan->default_filters[EFX_EF10_BCAST] =
0ccb998b 5180 efx_ef10_filter_get_unsafe_id(rc);
12fb0da4 5181 }
8127d661 5182 }
12fb0da4
EC		 5183
5184 return 0;
5185}
5186
b3a3c03c
AR		 5187static int efx_ef10_filter_insert_def(struct efx_nic *efx,
5188 struct efx_ef10_filter_vlan *vlan,
9b410801 5189 enum efx_encap_type encap_type,
b3a3c03c 5190 bool multicast, bool rollback)
12fb0da4 5191{
12fb0da4 5192 struct efx_ef10_nic_data *nic_data = efx->nic_data;
f1c2ef40 5193 enum efx_filter_flags filter_flags;
12fb0da4
EC		 5194 struct efx_filter_spec spec;
5195 u8 baddr[ETH_ALEN];
5196 int rc;
9b410801 5197 u16 *id;
12fb0da4 5198
f1c2ef40
BK		 5199 filter_flags = efx_rss_enabled(efx) ? EFX_FILTER_FLAG_RX_RSS : 0;
5200
5201 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, 0);
12fb0da4
EC		 5202
5203 if (multicast)
5204 efx_filter_set_mc_def(&spec);
5205 else
5206 efx_filter_set_uc_def(&spec);
5207
9b410801
EC		 5208 if (encap_type) {
5209 if (nic_data->datapath_caps &
5210 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN))
5211 efx_filter_set_encap_type(&spec, encap_type);
5212 else
5213 /* don't insert encap filters on non-supporting
5214 * platforms. ID will be left as INVALID.
5215 */
5216 return 0;
5217 }
5218
b3a3c03c
AR		 5219 if (vlan->vid != EFX_FILTER_VID_UNSPEC)
5220 efx_filter_set_eth_local(&spec, vlan->vid, NULL);
5221
12fb0da4
EC		 5222 rc = efx_ef10_filter_insert(efx, &spec, true);
5223 if (rc < 0) {
9b410801
EC		 5224 const char *um = multicast ? "Multicast" : "Unicast";
5225 const char *encap_name = "";
5226 const char *encap_ipv = "";
5227
5228 if ((encap_type & EFX_ENCAP_TYPES_MASK) ==
5229 EFX_ENCAP_TYPE_VXLAN)
5230 encap_name = "VXLAN ";
5231 else if ((encap_type & EFX_ENCAP_TYPES_MASK) ==
5232 EFX_ENCAP_TYPE_NVGRE)
5233 encap_name = "NVGRE ";
5234 else if ((encap_type & EFX_ENCAP_TYPES_MASK) ==
5235 EFX_ENCAP_TYPE_GENEVE)
5236 encap_name = "GENEVE ";
5237 if (encap_type & EFX_ENCAP_FLAG_IPV6)
5238 encap_ipv = "IPv6 ";
5239 else if (encap_type)
5240 encap_ipv = "IPv4 ";
5241
5242 /* unprivileged functions can't insert mismatch filters
5243 * for encapsulated or unicast traffic, so downgrade
5244 * those warnings to debug.
5245 */
34e7aefb 5246 netif_cond_dbg(efx, drv, efx->net_dev,
9b410801
EC		 5247 rc == -EPERM && (encap_type || !multicast), warn,
5248 "%s%s%s mismatch filter insert failed rc=%d\n",
5249 encap_name, encap_ipv, um, rc);
12fb0da4 5250 } else if (multicast) {
9b410801
EC		 5251 /* mapping from encap types to default filter IDs (multicast) */
5252 static enum efx_ef10_default_filters map[] = {
5253 [EFX_ENCAP_TYPE_NONE] = EFX_EF10_MCDEF,
5254 [EFX_ENCAP_TYPE_VXLAN] = EFX_EF10_VXLAN4_MCDEF,
5255 [EFX_ENCAP_TYPE_NVGRE] = EFX_EF10_NVGRE4_MCDEF,
5256 [EFX_ENCAP_TYPE_GENEVE] = EFX_EF10_GENEVE4_MCDEF,
5257 [EFX_ENCAP_TYPE_VXLAN | EFX_ENCAP_FLAG_IPV6] =
5258 EFX_EF10_VXLAN6_MCDEF,
5259 [EFX_ENCAP_TYPE_NVGRE | EFX_ENCAP_FLAG_IPV6] =
5260 EFX_EF10_NVGRE6_MCDEF,
5261 [EFX_ENCAP_TYPE_GENEVE | EFX_ENCAP_FLAG_IPV6] =
5262 EFX_EF10_GENEVE6_MCDEF,
5263 };
5264
5265 /* quick bounds check (BCAST result impossible) */
5266 BUILD_BUG_ON(EFX_EF10_BCAST != 0);
e9904990 5267 if (encap_type >= ARRAY_SIZE(map) || map[encap_type] == 0) {
9b410801
EC		 5268 WARN_ON(1);
5269 return -EINVAL;
5270 }
5271 /* then follow map */
5272 id = &vlan->default_filters[map[encap_type]];
5273
5274 EFX_WARN_ON_PARANOID(*id != EFX_EF10_FILTER_ID_INVALID);
0ccb998b 5275 *id = efx_ef10_filter_get_unsafe_id(rc);
9b410801 5276 if (!nic_data->workaround_26807 && !encap_type) {
12fb0da4
EC		 5277 /* Also need an Ethernet broadcast filter */
5278 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
f1c2ef40 5279 filter_flags, 0);
12fb0da4 5280 eth_broadcast_addr(baddr);
b3a3c03c 5281 efx_filter_set_eth_local(&spec, vlan->vid, baddr);
12fb0da4
EC		 5282 rc = efx_ef10_filter_insert(efx, &spec, true);
5283 if (rc < 0) {
5284 netif_warn(efx, drv, efx->net_dev,
5285 "Broadcast filter insert failed rc=%d\n",
5286 rc);
5287 if (rollback) {
5288 /* Roll back the mc_def filter */
5289 efx_ef10_filter_remove_unsafe(
5290 efx, EFX_FILTER_PRI_AUTO,
9b410801
EC		 5291 *id);
5292 *id = EFX_EF10_FILTER_ID_INVALID;
12fb0da4
EC		 5293 return rc;
5294 }
5295 } else {
9b410801
EC		 5296 EFX_WARN_ON_PARANOID(
5297 vlan->default_filters[EFX_EF10_BCAST] !=
5298 EFX_EF10_FILTER_ID_INVALID);
5299 vlan->default_filters[EFX_EF10_BCAST] =
0ccb998b 5300 efx_ef10_filter_get_unsafe_id(rc);
12fb0da4
EC		 5301 }
5302 }
5303 rc = 0;
5304 } else {
9b410801
EC		 5305 /* mapping from encap types to default filter IDs (unicast) */
5306 static enum efx_ef10_default_filters map[] = {
5307 [EFX_ENCAP_TYPE_NONE] = EFX_EF10_UCDEF,
5308 [EFX_ENCAP_TYPE_VXLAN] = EFX_EF10_VXLAN4_UCDEF,
5309 [EFX_ENCAP_TYPE_NVGRE] = EFX_EF10_NVGRE4_UCDEF,
5310 [EFX_ENCAP_TYPE_GENEVE] = EFX_EF10_GENEVE4_UCDEF,
5311 [EFX_ENCAP_TYPE_VXLAN | EFX_ENCAP_FLAG_IPV6] =
5312 EFX_EF10_VXLAN6_UCDEF,
5313 [EFX_ENCAP_TYPE_NVGRE | EFX_ENCAP_FLAG_IPV6] =
5314 EFX_EF10_NVGRE6_UCDEF,
5315 [EFX_ENCAP_TYPE_GENEVE | EFX_ENCAP_FLAG_IPV6] =
5316 EFX_EF10_GENEVE6_UCDEF,
5317 };
5318
5319 /* quick bounds check (BCAST result impossible) */
5320 BUILD_BUG_ON(EFX_EF10_BCAST != 0);
ee467fba 5321 if (encap_type >= ARRAY_SIZE(map) || map[encap_type] == 0) {
9b410801
EC		 5322 WARN_ON(1);
5323 return -EINVAL;
5324 }
5325 /* then follow map */
5326 id = &vlan->default_filters[map[encap_type]];
5327 EFX_WARN_ON_PARANOID(*id != EFX_EF10_FILTER_ID_INVALID);
5328 *id = rc;
12fb0da4
EC		 5329 rc = 0;
5330 }
5331 return rc;
822b96f8
DP		 5332}
5333
5334/* Remove filters that weren't renewed. Since nothing else changes the AUTO_OLD
5335 * flag or removes these filters, we don't need to hold the filter_lock while
5336 * scanning for these filters.
5337 */
5338static void efx_ef10_filter_remove_old(struct efx_nic *efx)
5339{
5340 struct efx_ef10_filter_table *table = efx->filter_state;
e65a5109
BK		 5341 int remove_failed = 0;
5342 int remove_noent = 0;
5343 int rc;
822b96f8 5344 int i;
8127d661 5345
8127d661 5346 for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) {
6aa7de05 5347 if (READ_ONCE(table->entry[i].spec) &
b59e6ef8 5348 EFX_EF10_FILTER_FLAG_AUTO_OLD) {
e65a5109
BK		 5349 rc = efx_ef10_filter_remove_internal(efx,
5350 1U << EFX_FILTER_PRI_AUTO, i, true);
5351 if (rc == -ENOENT)
5352 remove_noent++;
5353 else if (rc)
5354 remove_failed++;
8127d661
BH		 5355 }
5356 }
e65a5109
BK		 5357
5358 if (remove_failed)
5359 netif_info(efx, drv, efx->net_dev,
5360 "%s: failed to remove %d filters\n",
5361 __func__, remove_failed);
5362 if (remove_noent)
5363 netif_info(efx, drv, efx->net_dev,
5364 "%s: failed to remove %d non-existent filters\n",
5365 __func__, remove_noent);
8127d661
BH		 5366}
5367
7a186f47
DP		 5368static int efx_ef10_vport_set_mac_address(struct efx_nic *efx)
5369{
5370 struct efx_ef10_nic_data *nic_data = efx->nic_data;
5371 u8 mac_old[ETH_ALEN];
5372 int rc, rc2;
5373
5374 /* Only reconfigure a PF-created vport */
5375 if (is_zero_ether_addr(nic_data->vport_mac))
5376 return 0;
5377
5378 efx_device_detach_sync(efx);
5379 efx_net_stop(efx->net_dev);
5380 down_write(&efx->filter_sem);
5381 efx_ef10_filter_table_remove(efx);
5382 up_write(&efx->filter_sem);
5383
5384 rc = efx_ef10_vadaptor_free(efx, nic_data->vport_id);
5385 if (rc)
5386 goto restore_filters;
5387
5388 ether_addr_copy(mac_old, nic_data->vport_mac);
5389 rc = efx_ef10_vport_del_mac(efx, nic_data->vport_id,
5390 nic_data->vport_mac);
5391 if (rc)
5392 goto restore_vadaptor;
5393
5394 rc = efx_ef10_vport_add_mac(efx, nic_data->vport_id,
5395 efx->net_dev->dev_addr);
5396 if (!rc) {
5397 ether_addr_copy(nic_data->vport_mac, efx->net_dev->dev_addr);
5398 } else {
5399 rc2 = efx_ef10_vport_add_mac(efx, nic_data->vport_id, mac_old);
5400 if (rc2) {
5401 /* Failed to add original MAC, so clear vport_mac */
5402 eth_zero_addr(nic_data->vport_mac);
5403 goto reset_nic;
5404 }
5405 }
5406
5407restore_vadaptor:
5408 rc2 = efx_ef10_vadaptor_alloc(efx, nic_data->vport_id);
5409 if (rc2)
5410 goto reset_nic;
5411restore_filters:
5412 down_write(&efx->filter_sem);
5413 rc2 = efx_ef10_filter_table_probe(efx);
5414 up_write(&efx->filter_sem);
5415 if (rc2)
5416 goto reset_nic;
5417
5418 rc2 = efx_net_open(efx->net_dev);
5419 if (rc2)
5420 goto reset_nic;
5421
9c568fd8 5422 efx_device_attach_if_not_resetting(efx);
7a186f47
DP		 5423
5424 return rc;
5425
5426reset_nic:
5427 netif_err(efx, drv, efx->net_dev,
5428 "Failed to restore when changing MAC address - scheduling reset\n");
5429 efx_schedule_reset(efx, RESET_TYPE_DATAPATH);
5430
5431 return rc ? rc : rc2;
5432}
5433
822b96f8
DP		 5434/* Caller must hold efx->filter_sem for read if race against
5435 * efx_ef10_filter_table_remove() is possible
5436 */
34813fe2
AR		 5437static void efx_ef10_filter_vlan_sync_rx_mode(struct efx_nic *efx,
5438 struct efx_ef10_filter_vlan *vlan)
822b96f8
DP		 5439{
5440 struct efx_ef10_filter_table *table = efx->filter_state;
ab8b1f7c 5441 struct efx_ef10_nic_data *nic_data = efx->nic_data;
b3a3c03c 5442
4a53ea8a
AR		 5443 /* Do not install unspecified VID if VLAN filtering is enabled.
5444 * Do not install all specified VIDs if VLAN filtering is disabled.
5445 */
5446 if ((vlan->vid == EFX_FILTER_VID_UNSPEC) == table->vlan_filter)
5447 return;
5448
12fb0da4 5449 /* Insert/renew unicast filters */
afa4ce12 5450 if (table->uc_promisc) {
9b410801
EC		 5451 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_NONE,
5452 false, false);
b3a3c03c 5453 efx_ef10_filter_insert_addr_list(efx, vlan, false, false);
12fb0da4
EC		 5454 } else {
5455 /* If any of the filters failed to insert, fall back to
5456 * promiscuous mode - add in the uc_def filter. But keep
5457 * our individual unicast filters.
5458 */
b3a3c03c 5459 if (efx_ef10_filter_insert_addr_list(efx, vlan, false, false))
9b410801
EC		 5460 efx_ef10_filter_insert_def(efx, vlan,
5461 EFX_ENCAP_TYPE_NONE,
5462 false, false);
12fb0da4 5463 }
9b410801
EC		 5464 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_VXLAN,
5465 false, false);
5466 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_VXLAN |
5467 EFX_ENCAP_FLAG_IPV6,
5468 false, false);
5469 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_NVGRE,
5470 false, false);
5471 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_NVGRE |
5472 EFX_ENCAP_FLAG_IPV6,
5473 false, false);
5474 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_GENEVE,
5475 false, false);
5476 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_GENEVE |
5477 EFX_ENCAP_FLAG_IPV6,
5478 false, false);
ab8b1f7c 5479
12fb0da4 5480 /* Insert/renew multicast filters */
ab8b1f7c
DP		 5481 /* If changing promiscuous state with cascaded multicast filters, remove
5482 * old filters first, so that packets are dropped rather than duplicated
5483 */
afa4ce12
AR		 5484 if (nic_data->workaround_26807 &&
5485 table->mc_promisc_last != table->mc_promisc)
ab8b1f7c 5486 efx_ef10_filter_remove_old(efx);
afa4ce12 5487 if (table->mc_promisc) {
12fb0da4
EC		 5488 if (nic_data->workaround_26807) {
5489 /* If we failed to insert promiscuous filters, rollback
5490 * and fall back to individual multicast filters
5491 */
9b410801
EC		 5492 if (efx_ef10_filter_insert_def(efx, vlan,
5493 EFX_ENCAP_TYPE_NONE,
5494 true, true)) {
12fb0da4
EC		 5495 /* Changing promisc state, so remove old filters */
5496 efx_ef10_filter_remove_old(efx);
b3a3c03c
AR		 5497 efx_ef10_filter_insert_addr_list(efx, vlan,
5498 true, false);
12fb0da4
EC		 5499 }
5500 } else {
5501 /* If we failed to insert promiscuous filters, don't
148cbab6
EC		 5502 * rollback. Regardless, also insert the mc_list,
5503 * unless it's incomplete due to overflow
12fb0da4 5504 */
9b410801
EC		 5505 efx_ef10_filter_insert_def(efx, vlan,
5506 EFX_ENCAP_TYPE_NONE,
5507 true, false);
148cbab6
EC		 5508 if (!table->mc_overflow)
5509 efx_ef10_filter_insert_addr_list(efx, vlan,
5510 true, false);
12fb0da4
EC		 5511 }
5512 } else {
5513 /* If any filters failed to insert, rollback and fall back to
5514 * promiscuous mode - mc_def filter and maybe broadcast. If
5515 * that fails, roll back again and insert as many of our
5516 * individual multicast filters as we can.
5517 */
b3a3c03c 5518 if (efx_ef10_filter_insert_addr_list(efx, vlan, true, true)) {
12fb0da4
EC		 5519 /* Changing promisc state, so remove old filters */
5520 if (nic_data->workaround_26807)
5521 efx_ef10_filter_remove_old(efx);
9b410801
EC		 5522 if (efx_ef10_filter_insert_def(efx, vlan,
5523 EFX_ENCAP_TYPE_NONE,
5524 true, true))
b3a3c03c
AR		 5525 efx_ef10_filter_insert_addr_list(efx, vlan,
5526 true, false);
12fb0da4
EC		 5527 }
5528 }
9b410801
EC		 5529 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_VXLAN,
5530 true, false);
5531 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_VXLAN |
5532 EFX_ENCAP_FLAG_IPV6,
5533 true, false);
5534 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_NVGRE,
5535 true, false);
5536 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_NVGRE |
5537 EFX_ENCAP_FLAG_IPV6,
5538 true, false);
5539 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_GENEVE,
5540 true, false);
5541 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_GENEVE |
5542 EFX_ENCAP_FLAG_IPV6,
5543 true, false);
34813fe2
AR		 5544}
5545
5546/* Caller must hold efx->filter_sem for read if race against
5547 * efx_ef10_filter_table_remove() is possible
5548 */
5549static void efx_ef10_filter_sync_rx_mode(struct efx_nic *efx)
5550{
5551 struct efx_ef10_filter_table *table = efx->filter_state;
5552 struct net_device *net_dev = efx->net_dev;
5553 struct efx_ef10_filter_vlan *vlan;
4a53ea8a 5554 bool vlan_filter;
34813fe2
AR		 5555
5556 if (!efx_dev_registered(efx))
5557 return;
5558
5559 if (!table)
5560 return;
5561
5562 efx_ef10_filter_mark_old(efx);
5563
5564 /* Copy/convert the address lists; add the primary station
5565 * address and broadcast address
5566 */
5567 netif_addr_lock_bh(net_dev);
5568 efx_ef10_filter_uc_addr_list(efx);
5569 efx_ef10_filter_mc_addr_list(efx);
5570 netif_addr_unlock_bh(net_dev);
5571
4a53ea8a
AR		 5572 /* If VLAN filtering changes, all old filters are finally removed.
5573 * Do it in advance to avoid conflicts for unicast untagged and
5574 * VLAN 0 tagged filters.
5575 */
5576 vlan_filter = !!(net_dev->features & NETIF_F_HW_VLAN_CTAG_FILTER);
5577 if (table->vlan_filter != vlan_filter) {
5578 table->vlan_filter = vlan_filter;
5579 efx_ef10_filter_remove_old(efx);
5580 }
5581
34813fe2
AR		 5582 list_for_each_entry(vlan, &table->vlan_list, list)
5583 efx_ef10_filter_vlan_sync_rx_mode(efx, vlan);
822b96f8
DP		 5584
5585 efx_ef10_filter_remove_old(efx);
afa4ce12 5586 table->mc_promisc_last = table->mc_promisc;
822b96f8
DP		 5587}
5588
34813fe2
AR		 5589static struct efx_ef10_filter_vlan *efx_ef10_filter_find_vlan(struct efx_nic *efx, u16 vid)
5590{
5591 struct efx_ef10_filter_table *table = efx->filter_state;
5592 struct efx_ef10_filter_vlan *vlan;
5593
5594 WARN_ON(!rwsem_is_locked(&efx->filter_sem));
5595
5596 list_for_each_entry(vlan, &table->vlan_list, list) {
5597 if (vlan->vid == vid)
5598 return vlan;
5599 }
5600
5601 return NULL;
5602}
5603
5604static int efx_ef10_filter_add_vlan(struct efx_nic *efx, u16 vid)
5605{
5606 struct efx_ef10_filter_table *table = efx->filter_state;
5607 struct efx_ef10_filter_vlan *vlan;
5608 unsigned int i;
5609
5610 if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
5611 return -EINVAL;
5612
5613 vlan = efx_ef10_filter_find_vlan(efx, vid);
5614 if (WARN_ON(vlan)) {
5615 netif_err(efx, drv, efx->net_dev,
5616 "VLAN %u already added\n", vid);
5617 return -EALREADY;
5618 }
5619
5620 vlan = kzalloc(sizeof(*vlan), GFP_KERNEL);
5621 if (!vlan)
5622 return -ENOMEM;
5623
5624 vlan->vid = vid;
5625
5626 for (i = 0; i < ARRAY_SIZE(vlan->uc); i++)
5627 vlan->uc[i] = EFX_EF10_FILTER_ID_INVALID;
5628 for (i = 0; i < ARRAY_SIZE(vlan->mc); i++)
5629 vlan->mc[i] = EFX_EF10_FILTER_ID_INVALID;
9b410801
EC		 5630 for (i = 0; i < EFX_EF10_NUM_DEFAULT_FILTERS; i++)
5631 vlan->default_filters[i] = EFX_EF10_FILTER_ID_INVALID;
34813fe2
AR		 5632
5633 list_add_tail(&vlan->list, &table->vlan_list);
5634
5635 if (efx_dev_registered(efx))
5636 efx_ef10_filter_vlan_sync_rx_mode(efx, vlan);
5637
5638 return 0;
5639}
5640
5641static void efx_ef10_filter_del_vlan_internal(struct efx_nic *efx,
5642 struct efx_ef10_filter_vlan *vlan)
5643{
5644 unsigned int i;
5645
5646 /* See comment in efx_ef10_filter_table_remove() */
5647 if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
5648 return;
5649
5650 list_del(&vlan->list);
5651
8c915620 5652 for (i = 0; i < ARRAY_SIZE(vlan->uc); i++)
34813fe2 5653 efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO,
8c915620
EC		 5654 vlan->uc[i]);
5655 for (i = 0; i < ARRAY_SIZE(vlan->mc); i++)
34813fe2 5656 efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO,
8c915620 5657 vlan->mc[i]);
9b410801
EC		 5658 for (i = 0; i < EFX_EF10_NUM_DEFAULT_FILTERS; i++)
5659 if (vlan->default_filters[i] != EFX_EF10_FILTER_ID_INVALID)
5660 efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO,
5661 vlan->default_filters[i]);
34813fe2
AR		 5662
5663 kfree(vlan);
5664}
5665
5666static void efx_ef10_filter_del_vlan(struct efx_nic *efx, u16 vid)
5667{
5668 struct efx_ef10_filter_vlan *vlan;
5669
5670 /* See comment in efx_ef10_filter_table_remove() */
5671 if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
5672 return;
5673
5674 vlan = efx_ef10_filter_find_vlan(efx, vid);
5675 if (!vlan) {
5676 netif_err(efx, drv, efx->net_dev,
5677 "VLAN %u not found in filter state\n", vid);
5678 return;
5679 }
5680
5681 efx_ef10_filter_del_vlan_internal(efx, vlan);
5682}
5683
910c8789
SS		 5684static int efx_ef10_set_mac_address(struct efx_nic *efx)
5685{
5686 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_SET_MAC_IN_LEN);
5687 struct efx_ef10_nic_data *nic_data = efx->nic_data;
5688 bool was_enabled = efx->port_enabled;
5689 int rc;
5690
5691 efx_device_detach_sync(efx);
5692 efx_net_stop(efx->net_dev);
d248953a
MH		 5693
5694 mutex_lock(&efx->mac_lock);
910c8789
SS		 5695 down_write(&efx->filter_sem);
5696 efx_ef10_filter_table_remove(efx);
5697
5698 ether_addr_copy(MCDI_PTR(inbuf, VADAPTOR_SET_MAC_IN_MACADDR),
5699 efx->net_dev->dev_addr);
5700 MCDI_SET_DWORD(inbuf, VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID,
5701 nic_data->vport_id);
535a6177
DP		 5702 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_VADAPTOR_SET_MAC, inbuf,
5703 sizeof(inbuf), NULL, 0, NULL);
910c8789
SS		 5704
5705 efx_ef10_filter_table_probe(efx);
5706 up_write(&efx->filter_sem);
d248953a
MH		 5707 mutex_unlock(&efx->mac_lock);
5708
910c8789
SS		 5709 if (was_enabled)
5710 efx_net_open(efx->net_dev);
9c568fd8 5711 efx_device_attach_if_not_resetting(efx);
910c8789 5712
9e9f665a
DP		 5713#ifdef CONFIG_SFC_SRIOV
5714 if (efx->pci_dev->is_virtfn && efx->pci_dev->physfn) {
910c8789
SS		 5715 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn;
5716
9e9f665a
DP		 5717 if (rc == -EPERM) {
5718 struct efx_nic *efx_pf;
910c8789 5719
9e9f665a
DP		 5720 /* Switch to PF and change MAC address on vport */
5721 efx_pf = pci_get_drvdata(pci_dev_pf);
910c8789 5722
9e9f665a
DP		 5723 rc = efx_ef10_sriov_set_vf_mac(efx_pf,
5724 nic_data->vf_index,
5725 efx->net_dev->dev_addr);
5726 } else if (!rc) {
910c8789
SS		 5727 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
5728 struct efx_ef10_nic_data *nic_data = efx_pf->nic_data;
5729 unsigned int i;
5730
9e9f665a
DP		 5731 /* MAC address successfully changed by VF (with MAC
5732 * spoofing) so update the parent PF if possible.
5733 */
910c8789
SS		 5734 for (i = 0; i < efx_pf->vf_count; ++i) {
5735 struct ef10_vf *vf = nic_data->vf + i;
5736
5737 if (vf->efx == efx) {
5738 ether_addr_copy(vf->mac,
5739 efx->net_dev->dev_addr);
5740 return 0;
5741 }
5742 }
5743 }
9e9f665a 5744 } else
910c8789 5745#endif
9e9f665a
DP		 5746 if (rc == -EPERM) {
5747 netif_err(efx, drv, efx->net_dev,
5748 "Cannot change MAC address; use sfboot to enable"
5749 " mac-spoofing on this interface\n");
7a186f47
DP		 5750 } else if (rc == -ENOSYS && !efx_ef10_is_vf(efx)) {
5751 /* If the active MCFW does not support MC_CMD_VADAPTOR_SET_MAC
5752 * fall-back to the method of changing the MAC address on the
5753 * vport. This only applies to PFs because such versions of
5754 * MCFW do not support VFs.
5755 */
5756 rc = efx_ef10_vport_set_mac_address(efx);
cbad52e9 5757 } else if (rc) {
535a6177
DP		 5758 efx_mcdi_display_error(efx, MC_CMD_VADAPTOR_SET_MAC,
5759 sizeof(inbuf), NULL, 0, rc);
9e9f665a
DP		 5760 }
5761
910c8789
SS		 5762 return rc;
5763}
5764
8127d661
BH		 5765static int efx_ef10_mac_reconfigure(struct efx_nic *efx)
5766{
5767 efx_ef10_filter_sync_rx_mode(efx);
5768
5769 return efx_mcdi_set_mac(efx);
5770}
5771
862f894c
SS		 5772static int efx_ef10_mac_reconfigure_vf(struct efx_nic *efx)
5773{
5774 efx_ef10_filter_sync_rx_mode(efx);
5775
5776 return 0;
5777}
5778
74cd60a4
JC		 5779static int efx_ef10_start_bist(struct efx_nic *efx, u32 bist_type)
5780{
5781 MCDI_DECLARE_BUF(inbuf, MC_CMD_START_BIST_IN_LEN);
5782
5783 MCDI_SET_DWORD(inbuf, START_BIST_IN_TYPE, bist_type);
5784 return efx_mcdi_rpc(efx, MC_CMD_START_BIST, inbuf, sizeof(inbuf),
5785 NULL, 0, NULL);
5786}
5787
5788/* MC BISTs follow a different poll mechanism to phy BISTs.
5789 * The BIST is done in the poll handler on the MC, and the MCDI command
5790 * will block until the BIST is done.
5791 */
5792static int efx_ef10_poll_bist(struct efx_nic *efx)
5793{
5794 int rc;
5795 MCDI_DECLARE_BUF(outbuf, MC_CMD_POLL_BIST_OUT_LEN);
5796 size_t outlen;
5797 u32 result;
5798
5799 rc = efx_mcdi_rpc(efx, MC_CMD_POLL_BIST, NULL, 0,
5800 outbuf, sizeof(outbuf), &outlen);
5801 if (rc != 0)
5802 return rc;
5803
5804 if (outlen < MC_CMD_POLL_BIST_OUT_LEN)
5805 return -EIO;
5806
5807 result = MCDI_DWORD(outbuf, POLL_BIST_OUT_RESULT);
5808 switch (result) {
5809 case MC_CMD_POLL_BIST_PASSED:
5810 netif_dbg(efx, hw, efx->net_dev, "BIST passed.\n");
5811 return 0;
5812 case MC_CMD_POLL_BIST_TIMEOUT:
5813 netif_err(efx, hw, efx->net_dev, "BIST timed out\n");
5814 return -EIO;
5815 case MC_CMD_POLL_BIST_FAILED:
5816 netif_err(efx, hw, efx->net_dev, "BIST failed.\n");
5817 return -EIO;
5818 default:
5819 netif_err(efx, hw, efx->net_dev,
5820 "BIST returned unknown result %u", result);
5821 return -EIO;
5822 }
5823}
5824
5825static int efx_ef10_run_bist(struct efx_nic *efx, u32 bist_type)
5826{
5827 int rc;
5828
5829 netif_dbg(efx, drv, efx->net_dev, "starting BIST type %u\n", bist_type);
5830
5831 rc = efx_ef10_start_bist(efx, bist_type);
5832 if (rc != 0)
5833 return rc;
5834
5835 return efx_ef10_poll_bist(efx);
5836}
5837
5838static int
5839efx_ef10_test_chip(struct efx_nic *efx, struct efx_self_tests *tests)
5840{
5841 int rc, rc2;
5842
5843 efx_reset_down(efx, RESET_TYPE_WORLD);
5844
5845 rc = efx_mcdi_rpc(efx, MC_CMD_ENABLE_OFFLINE_BIST,
5846 NULL, 0, NULL, 0, NULL);
5847 if (rc != 0)
5848 goto out;
5849
5850 tests->memory = efx_ef10_run_bist(efx, MC_CMD_MC_MEM_BIST) ? -1 : 1;
5851 tests->registers = efx_ef10_run_bist(efx, MC_CMD_REG_BIST) ? -1 : 1;
5852
5853 rc = efx_mcdi_reset(efx, RESET_TYPE_WORLD);
5854
5855out:
27324820
DP		 5856 if (rc == -EPERM)
5857 rc = 0;
74cd60a4
JC		 5858 rc2 = efx_reset_up(efx, RESET_TYPE_WORLD, rc == 0);
5859 return rc ? rc : rc2;
5860}
5861
8127d661
BH		 5862#ifdef CONFIG_SFC_MTD
5863
5864struct efx_ef10_nvram_type_info {
5865 u16 type, type_mask;
5866 u8 port;
5867 const char *name;
5868};
5869
5870static const struct efx_ef10_nvram_type_info efx_ef10_nvram_types[] = {
5871 { NVRAM_PARTITION_TYPE_MC_FIRMWARE, 0, 0, "sfc_mcfw" },
5872 { NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 0, 0, "sfc_mcfw_backup" },
5873 { NVRAM_PARTITION_TYPE_EXPANSION_ROM, 0, 0, "sfc_exp_rom" },
5874 { NVRAM_PARTITION_TYPE_STATIC_CONFIG, 0, 0, "sfc_static_cfg" },
5875 { NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG, 0, 0, "sfc_dynamic_cfg" },
5876 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0, 0, 0, "sfc_exp_rom_cfg" },
5877 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1, 0, 1, "sfc_exp_rom_cfg" },
5878 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2, 0, 2, "sfc_exp_rom_cfg" },
5879 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3, 0, 3, "sfc_exp_rom_cfg" },
a84f3bf9 5880 { NVRAM_PARTITION_TYPE_LICENSE, 0, 0, "sfc_license" },
8127d661
BH		 5881 { NVRAM_PARTITION_TYPE_PHY_MIN, 0xff, 0, "sfc_phy_fw" },
5882};
5883
5884static int efx_ef10_mtd_probe_partition(struct efx_nic *efx,
5885 struct efx_mcdi_mtd_partition *part,
5886 unsigned int type)
5887{
5888 MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_METADATA_IN_LEN);
5889 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_METADATA_OUT_LENMAX);
5890 const struct efx_ef10_nvram_type_info *info;
5891 size_t size, erase_size, outlen;
5892 bool protected;
5893 int rc;
5894
5895 for (info = efx_ef10_nvram_types; ; info++) {
5896 if (info ==
5897 efx_ef10_nvram_types + ARRAY_SIZE(efx_ef10_nvram_types))
5898 return -ENODEV;
5899 if ((type & ~info->type_mask) == info->type)
5900 break;
5901 }
5902 if (info->port != efx_port_num(efx))
5903 return -ENODEV;
5904
5905 rc = efx_mcdi_nvram_info(efx, type, &size, &erase_size, &protected);
5906 if (rc)
5907 return rc;
5908 if (protected)
5909 return -ENODEV; /* hide it */
5910
5911 part->nvram_type = type;
5912
5913 MCDI_SET_DWORD(inbuf, NVRAM_METADATA_IN_TYPE, type);
5914 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_METADATA, inbuf, sizeof(inbuf),
5915 outbuf, sizeof(outbuf), &outlen);
5916 if (rc)
5917 return rc;
5918 if (outlen < MC_CMD_NVRAM_METADATA_OUT_LENMIN)
5919 return -EIO;
5920 if (MCDI_DWORD(outbuf, NVRAM_METADATA_OUT_FLAGS) &
5921 (1 << MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN))
5922 part->fw_subtype = MCDI_DWORD(outbuf,
5923 NVRAM_METADATA_OUT_SUBTYPE);
5924
5925 part->common.dev_type_name = "EF10 NVRAM manager";
5926 part->common.type_name = info->name;
5927
5928 part->common.mtd.type = MTD_NORFLASH;
5929 part->common.mtd.flags = MTD_CAP_NORFLASH;
5930 part->common.mtd.size = size;
5931 part->common.mtd.erasesize = erase_size;
5932
5933 return 0;
5934}
5935
5936static int efx_ef10_mtd_probe(struct efx_nic *efx)
5937{
5938 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX);
5939 struct efx_mcdi_mtd_partition *parts;
5940 size_t outlen, n_parts_total, i, n_parts;
5941 unsigned int type;
5942 int rc;
5943
5944 ASSERT_RTNL();
5945
5946 BUILD_BUG_ON(MC_CMD_NVRAM_PARTITIONS_IN_LEN != 0);
5947 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_PARTITIONS, NULL, 0,
5948 outbuf, sizeof(outbuf), &outlen);
5949 if (rc)
5950 return rc;
5951 if (outlen < MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN)
5952 return -EIO;
5953
5954 n_parts_total = MCDI_DWORD(outbuf, NVRAM_PARTITIONS_OUT_NUM_PARTITIONS);
5955 if (n_parts_total >
5956 MCDI_VAR_ARRAY_LEN(outlen, NVRAM_PARTITIONS_OUT_TYPE_ID))
5957 return -EIO;
5958
5959 parts = kcalloc(n_parts_total, sizeof(*parts), GFP_KERNEL);
5960 if (!parts)
5961 return -ENOMEM;
5962
5963 n_parts = 0;
5964 for (i = 0; i < n_parts_total; i++) {
5965 type = MCDI_ARRAY_DWORD(outbuf, NVRAM_PARTITIONS_OUT_TYPE_ID,
5966 i);
5967 rc = efx_ef10_mtd_probe_partition(efx, &parts[n_parts], type);
5968 if (rc == 0)
5969 n_parts++;
5970 else if (rc != -ENODEV)
5971 goto fail;
5972 }
5973
5974 rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts));
5975fail:
5976 if (rc)
5977 kfree(parts);
5978 return rc;
5979}
5980
5981#endif /* CONFIG_SFC_MTD */
5982
5983static void efx_ef10_ptp_write_host_time(struct efx_nic *efx, u32 host_time)
5984{
5985 _efx_writed(efx, cpu_to_le32(host_time), ER_DZ_MC_DB_LWRD);
5986}
5987
02246a7f
SS		 5988static void efx_ef10_ptp_write_host_time_vf(struct efx_nic *efx,
5989 u32 host_time) {}
5990
bd9a265d
JC		 5991static int efx_ef10_rx_enable_timestamping(struct efx_channel *channel,
5992 bool temp)
5993{
5994 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN);
5995 int rc;
5996
5997 if (channel->sync_events_state == SYNC_EVENTS_REQUESTED ||
5998 channel->sync_events_state == SYNC_EVENTS_VALID ||
5999 (temp && channel->sync_events_state == SYNC_EVENTS_DISABLED))
6000 return 0;
6001 channel->sync_events_state = SYNC_EVENTS_REQUESTED;
6002
6003 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE);
6004 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
6005 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE,
6006 channel->channel);
6007
6008 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
6009 inbuf, sizeof(inbuf), NULL, 0, NULL);
6010
6011 if (rc != 0)
6012 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
6013 SYNC_EVENTS_DISABLED;
6014
6015 return rc;
6016}
6017
6018static int efx_ef10_rx_disable_timestamping(struct efx_channel *channel,
6019 bool temp)
6020{
6021 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN);
6022 int rc;
6023
6024 if (channel->sync_events_state == SYNC_EVENTS_DISABLED ||
6025 (temp && channel->sync_events_state == SYNC_EVENTS_QUIESCENT))
6026 return 0;
6027 if (channel->sync_events_state == SYNC_EVENTS_QUIESCENT) {
6028 channel->sync_events_state = SYNC_EVENTS_DISABLED;
6029 return 0;
6030 }
6031 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
6032 SYNC_EVENTS_DISABLED;
6033
6034 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE);
6035 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
6036 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL,
6037 MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE);
6038 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE,
6039 channel->channel);
6040
6041 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
6042 inbuf, sizeof(inbuf), NULL, 0, NULL);
6043
6044 return rc;
6045}
6046
6047static int efx_ef10_ptp_set_ts_sync_events(struct efx_nic *efx, bool en,
6048 bool temp)
6049{
6050 int (*set)(struct efx_channel *channel, bool temp);
6051 struct efx_channel *channel;
6052
6053 set = en ?
6054 efx_ef10_rx_enable_timestamping :
6055 efx_ef10_rx_disable_timestamping;
6056
6057 efx_for_each_channel(channel, efx) {
6058 int rc = set(channel, temp);
6059 if (en && rc != 0) {
6060 efx_ef10_ptp_set_ts_sync_events(efx, false, temp);
6061 return rc;
6062 }
6063 }
6064
6065 return 0;
6066}
6067
02246a7f
SS		 6068static int efx_ef10_ptp_set_ts_config_vf(struct efx_nic *efx,
6069 struct hwtstamp_config *init)
6070{
6071 return -EOPNOTSUPP;
6072}
6073
bd9a265d
JC		 6074static int efx_ef10_ptp_set_ts_config(struct efx_nic *efx,
6075 struct hwtstamp_config *init)
6076{
6077 int rc;
6078
6079 switch (init->rx_filter) {
6080 case HWTSTAMP_FILTER_NONE:
6081 efx_ef10_ptp_set_ts_sync_events(efx, false, false);
6082 /* if TX timestamping is still requested then leave PTP on */
6083 return efx_ptp_change_mode(efx,
6084 init->tx_type != HWTSTAMP_TX_OFF, 0);
6085 case HWTSTAMP_FILTER_ALL:
6086 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
6087 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
6088 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
6089 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
6090 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
6091 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
6092 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
6093 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
6094 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
6095 case HWTSTAMP_FILTER_PTP_V2_EVENT:
6096 case HWTSTAMP_FILTER_PTP_V2_SYNC:
6097 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
e3412575 6098 case HWTSTAMP_FILTER_NTP_ALL:
bd9a265d
JC		 6099 init->rx_filter = HWTSTAMP_FILTER_ALL;
6100 rc = efx_ptp_change_mode(efx, true, 0);
6101 if (!rc)
6102 rc = efx_ef10_ptp_set_ts_sync_events(efx, true, false);
6103 if (rc)
6104 efx_ptp_change_mode(efx, false, 0);
6105 return rc;
6106 default:
6107 return -ERANGE;
6108 }
6109}
6110
08a7b29b
BK		 6111static int efx_ef10_get_phys_port_id(struct efx_nic *efx,
6112 struct netdev_phys_item_id *ppid)
6113{
6114 struct efx_ef10_nic_data *nic_data = efx->nic_data;
6115
6116 if (!is_valid_ether_addr(nic_data->port_id))
6117 return -EOPNOTSUPP;
6118
6119 ppid->id_len = ETH_ALEN;
6120 memcpy(ppid->id, nic_data->port_id, ppid->id_len);
6121
6122 return 0;
6123}
6124
4a53ea8a
AR		 6125static int efx_ef10_vlan_rx_add_vid(struct efx_nic *efx, __be16 proto, u16 vid)
6126{
6127 if (proto != htons(ETH_P_8021Q))
6128 return -EINVAL;
6129
6130 return efx_ef10_add_vlan(efx, vid);
6131}
6132
6133static int efx_ef10_vlan_rx_kill_vid(struct efx_nic *efx, __be16 proto, u16 vid)
6134{
6135 if (proto != htons(ETH_P_8021Q))
6136 return -EINVAL;
6137
6138 return efx_ef10_del_vlan(efx, vid);
6139}
6140
e5fbd977
JC		 6141/* We rely on the MCDI wiping out our TX rings if it made any changes to the
6142 * ports table, ensuring that any TSO descriptors that were made on a now-
6143 * removed tunnel port will be blown away and won't break things when we try
6144 * to transmit them using the new ports table.
6145 */
6146static int efx_ef10_set_udp_tnl_ports(struct efx_nic *efx, bool unloading)
6147{
6148 struct efx_ef10_nic_data *nic_data = efx->nic_data;
6149 MCDI_DECLARE_BUF(inbuf, MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LENMAX);
6150 MCDI_DECLARE_BUF(outbuf, MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_LEN);
6151 bool will_reset = false;
6152 size_t num_entries = 0;
6153 size_t inlen, outlen;
6154 size_t i;
6155 int rc;
6156 efx_dword_t flags_and_num_entries;
6157
6158 WARN_ON(!mutex_is_locked(&nic_data->udp_tunnels_lock));
6159
6160 nic_data->udp_tunnels_dirty = false;
6161
6162 if (!(nic_data->datapath_caps &
6163 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN))) {
9c568fd8 6164 efx_device_attach_if_not_resetting(efx);
e5fbd977
JC		 6165 return 0;
6166 }
6167
6168 BUILD_BUG_ON(ARRAY_SIZE(nic_data->udp_tunnels) >
6169 MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MAXNUM);
6170
6171 for (i = 0; i < ARRAY_SIZE(nic_data->udp_tunnels); ++i) {
6172 if (nic_data->udp_tunnels[i].count &&
6173 nic_data->udp_tunnels[i].port) {
6174 efx_dword_t entry;
6175
6176 EFX_POPULATE_DWORD_2(entry,
6177 TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT,
6178 ntohs(nic_data->udp_tunnels[i].port),
6179 TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL,
6180 nic_data->udp_tunnels[i].type);
6181 *_MCDI_ARRAY_DWORD(inbuf,
6182 SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES,
6183 num_entries++) = entry;
6184 }
6185 }
6186
6187 BUILD_BUG_ON((MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_NUM_ENTRIES_OFST -
6188 MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS_OFST) * 8 !=
6189 EFX_WORD_1_LBN);
6190 BUILD_BUG_ON(MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_NUM_ENTRIES_LEN * 8 !=
6191 EFX_WORD_1_WIDTH);
6192 EFX_POPULATE_DWORD_2(flags_and_num_entries,
6193 MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_UNLOADING,
6194 !!unloading,
6195 EFX_WORD_1, num_entries);
6196 *_MCDI_DWORD(inbuf, SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS) =
6197 flags_and_num_entries;
6198
6199 inlen = MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LEN(num_entries);
6200
6201 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS,
6202 inbuf, inlen, outbuf, sizeof(outbuf), &outlen);
6203 if (rc == -EIO) {
6204 /* Most likely the MC rebooted due to another function also
6205 * setting its tunnel port list. Mark the tunnel port list as
6206 * dirty, so it will be pushed upon coming up from the reboot.
6207 */
6208 nic_data->udp_tunnels_dirty = true;
6209 return 0;
6210 }
6211
6212 if (rc) {
6213 /* expected not available on unprivileged functions */
6214 if (rc != -EPERM)
6215 netif_warn(efx, drv, efx->net_dev,
6216 "Unable to set UDP tunnel ports; rc=%d.\n", rc);
6217 } else if (MCDI_DWORD(outbuf, SET_TUNNEL_ENCAP_UDP_PORTS_OUT_FLAGS) &
6218 (1 << MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_RESETTING_LBN)) {
6219 netif_info(efx, drv, efx->net_dev,
6220 "Rebooting MC due to UDP tunnel port list change\n");
6221 will_reset = true;
6222 if (unloading)
6223 /* Delay for the MC reset to complete. This will make
6224 * unloading other functions a bit smoother. This is a
6225 * race, but the other unload will work whichever way
6226 * it goes, this just avoids an unnecessary error
6227 * message.
6228 */
6229 msleep(100);
6230 }
6231 if (!will_reset && !unloading) {
6232 /* The caller will have detached, relying on the MC reset to
6233 * trigger a re-attach. Since there won't be an MC reset, we
6234 * have to do the attach ourselves.
6235 */
9c568fd8 6236 efx_device_attach_if_not_resetting(efx);
e5fbd977
JC		 6237 }
6238
6239 return rc;
6240}
6241
6242static int efx_ef10_udp_tnl_push_ports(struct efx_nic *efx)
6243{
6244 struct efx_ef10_nic_data *nic_data = efx->nic_data;
6245 int rc = 0;
6246
6247 mutex_lock(&nic_data->udp_tunnels_lock);
6248 if (nic_data->udp_tunnels_dirty) {
6249 /* Make sure all TX are stopped while we modify the table, else
6250 * we might race against an efx_features_check().
6251 */
6252 efx_device_detach_sync(efx);
6253 rc = efx_ef10_set_udp_tnl_ports(efx, false);
6254 }
6255 mutex_unlock(&nic_data->udp_tunnels_lock);
6256 return rc;
6257}
6258
6259static struct efx_udp_tunnel *__efx_ef10_udp_tnl_lookup_port(struct efx_nic *efx,
6260 __be16 port)
6261{
6262 struct efx_ef10_nic_data *nic_data = efx->nic_data;
6263 size_t i;
6264
6265 for (i = 0; i < ARRAY_SIZE(nic_data->udp_tunnels); ++i) {
6266 if (!nic_data->udp_tunnels[i].count)
6267 continue;
6268 if (nic_data->udp_tunnels[i].port == port)
6269 return &nic_data->udp_tunnels[i];
6270 }
6271 return NULL;
6272}
6273
6274static int efx_ef10_udp_tnl_add_port(struct efx_nic *efx,
6275 struct efx_udp_tunnel tnl)
6276{
6277 struct efx_ef10_nic_data *nic_data = efx->nic_data;
6278 struct efx_udp_tunnel *match;
6279 char typebuf[8];
6280 size_t i;
6281 int rc;
6282
6283 if (!(nic_data->datapath_caps &
6284 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN)))
6285 return 0;
6286
6287 efx_get_udp_tunnel_type_name(tnl.type, typebuf, sizeof(typebuf));
6288 netif_dbg(efx, drv, efx->net_dev, "Adding UDP tunnel (%s) port %d\n",
6289 typebuf, ntohs(tnl.port));
6290
6291 mutex_lock(&nic_data->udp_tunnels_lock);
6292 /* Make sure all TX are stopped while we add to the table, else we
6293 * might race against an efx_features_check().
6294 */
6295 efx_device_detach_sync(efx);
6296
6297 match = __efx_ef10_udp_tnl_lookup_port(efx, tnl.port);
6298 if (match != NULL) {
6299 if (match->type == tnl.type) {
6300 netif_dbg(efx, drv, efx->net_dev,
6301 "Referencing existing tunnel entry\n");
6302 match->count++;
6303 /* No need to cause an MCDI update */
6304 rc = 0;
6305 goto unlock_out;
6306 }
6307 efx_get_udp_tunnel_type_name(match->type,
6308 typebuf, sizeof(typebuf));
6309 netif_dbg(efx, drv, efx->net_dev,
6310 "UDP port %d is already in use by %s\n",
6311 ntohs(tnl.port), typebuf);
6312 rc = -EEXIST;
6313 goto unlock_out;
6314 }
6315
6316 for (i = 0; i < ARRAY_SIZE(nic_data->udp_tunnels); ++i)
6317 if (!nic_data->udp_tunnels[i].count) {
6318 nic_data->udp_tunnels[i] = tnl;
6319 nic_data->udp_tunnels[i].count = 1;
6320 rc = efx_ef10_set_udp_tnl_ports(efx, false);
6321 goto unlock_out;
6322 }
6323
6324 netif_dbg(efx, drv, efx->net_dev,
6325 "Unable to add UDP tunnel (%s) port %d; insufficient resources.\n",
6326 typebuf, ntohs(tnl.port));
6327
6328 rc = -ENOMEM;
6329
6330unlock_out:
6331 mutex_unlock(&nic_data->udp_tunnels_lock);
6332 return rc;
6333}
6334
6335/* Called under the TX lock with the TX queue running, hence no-one can be
6336 * in the middle of updating the UDP tunnels table. However, they could
6337 * have tried and failed the MCDI, in which case they'll have set the dirty
6338 * flag before dropping their locks.
6339 */
6340static bool efx_ef10_udp_tnl_has_port(struct efx_nic *efx, __be16 port)
6341{
6342 struct efx_ef10_nic_data *nic_data = efx->nic_data;
6343
6344 if (!(nic_data->datapath_caps &
6345 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN)))
6346 return false;
6347
6348 if (nic_data->udp_tunnels_dirty)
6349 /* SW table may not match HW state, so just assume we can't
6350 * use any UDP tunnel offloads.
6351 */
6352 return false;
6353
6354 return __efx_ef10_udp_tnl_lookup_port(efx, port) != NULL;
6355}
6356
6357static int efx_ef10_udp_tnl_del_port(struct efx_nic *efx,
6358 struct efx_udp_tunnel tnl)
6359{
6360 struct efx_ef10_nic_data *nic_data = efx->nic_data;
6361 struct efx_udp_tunnel *match;
6362 char typebuf[8];
6363 int rc;
6364
6365 if (!(nic_data->datapath_caps &
6366 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN)))
6367 return 0;
6368
6369 efx_get_udp_tunnel_type_name(tnl.type, typebuf, sizeof(typebuf));
6370 netif_dbg(efx, drv, efx->net_dev, "Removing UDP tunnel (%s) port %d\n",
6371 typebuf, ntohs(tnl.port));
6372
6373 mutex_lock(&nic_data->udp_tunnels_lock);
6374 /* Make sure all TX are stopped while we remove from the table, else we
6375 * might race against an efx_features_check().
6376 */
6377 efx_device_detach_sync(efx);
6378
6379 match = __efx_ef10_udp_tnl_lookup_port(efx, tnl.port);
6380 if (match != NULL) {
6381 if (match->type == tnl.type) {
6382 if (--match->count) {
6383 /* Port is still in use, so nothing to do */
6384 netif_dbg(efx, drv, efx->net_dev,
6385 "UDP tunnel port %d remains active\n",
6386 ntohs(tnl.port));
6387 rc = 0;
6388 goto out_unlock;
6389 }
6390 rc = efx_ef10_set_udp_tnl_ports(efx, false);
6391 goto out_unlock;
6392 }
6393 efx_get_udp_tunnel_type_name(match->type,
6394 typebuf, sizeof(typebuf));
6395 netif_warn(efx, drv, efx->net_dev,
6396 "UDP port %d is actually in use by %s, not removing\n",
6397 ntohs(tnl.port), typebuf);
6398 }
6399 rc = -ENOENT;
6400
6401out_unlock:
6402 mutex_unlock(&nic_data->udp_tunnels_lock);
6403 return rc;
6404}
6405
100a9db5
AR		 6406#define EF10_OFFLOAD_FEATURES \
6407 (NETIF_F_IP_CSUM | \
4a53ea8a 6408 NETIF_F_HW_VLAN_CTAG_FILTER | \
100a9db5
AR		 6409 NETIF_F_IPV6_CSUM | \
6410 NETIF_F_RXHASH | \
6411 NETIF_F_NTUPLE)
6412
02246a7f 6413const struct efx_nic_type efx_hunt_a0_vf_nic_type = {
6f7f8aa6 6414 .is_vf = true,
03714bbb 6415 .mem_bar = efx_ef10_vf_mem_bar,
02246a7f
SS		 6416 .mem_map_size = efx_ef10_mem_map_size,
6417 .probe = efx_ef10_probe_vf,
6418 .remove = efx_ef10_remove,
6419 .dimension_resources = efx_ef10_dimension_resources,
6420 .init = efx_ef10_init_nic,
6421 .fini = efx_port_dummy_op_void,
087e9025 6422 .map_reset_reason = efx_ef10_map_reset_reason,
02246a7f
SS		 6423 .map_reset_flags = efx_ef10_map_reset_flags,
6424 .reset = efx_ef10_reset,
6425 .probe_port = efx_mcdi_port_probe,
6426 .remove_port = efx_mcdi_port_remove,
6427 .fini_dmaq = efx_ef10_fini_dmaq,
6428 .prepare_flr = efx_ef10_prepare_flr,
6429 .finish_flr = efx_port_dummy_op_void,
6430 .describe_stats = efx_ef10_describe_stats,
d7788196 6431 .update_stats = efx_ef10_update_stats_vf,
02246a7f
SS		 6432 .start_stats = efx_port_dummy_op_void,
6433 .pull_stats = efx_port_dummy_op_void,
6434 .stop_stats = efx_port_dummy_op_void,
6435 .set_id_led = efx_mcdi_set_id_led,
6436 .push_irq_moderation = efx_ef10_push_irq_moderation,
862f894c 6437 .reconfigure_mac = efx_ef10_mac_reconfigure_vf,
02246a7f
SS		 6438 .check_mac_fault = efx_mcdi_mac_check_fault,
6439 .reconfigure_port = efx_mcdi_port_reconfigure,
6440 .get_wol = efx_ef10_get_wol_vf,
6441 .set_wol = efx_ef10_set_wol_vf,
6442 .resume_wol = efx_port_dummy_op_void,
6443 .mcdi_request = efx_ef10_mcdi_request,
6444 .mcdi_poll_response = efx_ef10_mcdi_poll_response,
6445 .mcdi_read_response = efx_ef10_mcdi_read_response,
6446 .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot,
c577e59e 6447 .mcdi_reboot_detected = efx_ef10_mcdi_reboot_detected,
02246a7f
SS		 6448 .irq_enable_master = efx_port_dummy_op_void,
6449 .irq_test_generate = efx_ef10_irq_test_generate,
6450 .irq_disable_non_ev = efx_port_dummy_op_void,
6451 .irq_handle_msi = efx_ef10_msi_interrupt,
6452 .irq_handle_legacy = efx_ef10_legacy_interrupt,
6453 .tx_probe = efx_ef10_tx_probe,
6454 .tx_init = efx_ef10_tx_init,
6455 .tx_remove = efx_ef10_tx_remove,
6456 .tx_write = efx_ef10_tx_write,
e9117e50 6457 .tx_limit_len = efx_ef10_tx_limit_len,
267c0157 6458 .rx_push_rss_config = efx_ef10_vf_rx_push_rss_config,
a707d188 6459 .rx_pull_rss_config = efx_ef10_rx_pull_rss_config,
02246a7f
SS		 6460 .rx_probe = efx_ef10_rx_probe,
6461 .rx_init = efx_ef10_rx_init,
6462 .rx_remove = efx_ef10_rx_remove,
6463 .rx_write = efx_ef10_rx_write,
6464 .rx_defer_refill = efx_ef10_rx_defer_refill,
6465 .ev_probe = efx_ef10_ev_probe,
6466 .ev_init = efx_ef10_ev_init,
6467 .ev_fini = efx_ef10_ev_fini,
6468 .ev_remove = efx_ef10_ev_remove,
6469 .ev_process = efx_ef10_ev_process,
6470 .ev_read_ack = efx_ef10_ev_read_ack,
6471 .ev_test_generate = efx_ef10_ev_test_generate,
6472 .filter_table_probe = efx_ef10_filter_table_probe,
6473 .filter_table_restore = efx_ef10_filter_table_restore,
6474 .filter_table_remove = efx_ef10_filter_table_remove,
6475 .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter,
6476 .filter_insert = efx_ef10_filter_insert,
6477 .filter_remove_safe = efx_ef10_filter_remove_safe,
6478 .filter_get_safe = efx_ef10_filter_get_safe,
6479 .filter_clear_rx = efx_ef10_filter_clear_rx,
6480 .filter_count_rx_used = efx_ef10_filter_count_rx_used,
6481 .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit,
6482 .filter_get_rx_ids = efx_ef10_filter_get_rx_ids,
6483#ifdef CONFIG_RFS_ACCEL
6484 .filter_rfs_insert = efx_ef10_filter_rfs_insert,
6485 .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one,
6486#endif
6487#ifdef CONFIG_SFC_MTD
6488 .mtd_probe = efx_port_dummy_op_int,
6489#endif
6490 .ptp_write_host_time = efx_ef10_ptp_write_host_time_vf,
6491 .ptp_set_ts_config = efx_ef10_ptp_set_ts_config_vf,
4a53ea8a
AR		 6492 .vlan_rx_add_vid = efx_ef10_vlan_rx_add_vid,
6493 .vlan_rx_kill_vid = efx_ef10_vlan_rx_kill_vid,
02246a7f 6494#ifdef CONFIG_SFC_SRIOV
7b8c7b54
SS		 6495 .vswitching_probe = efx_ef10_vswitching_probe_vf,
6496 .vswitching_restore = efx_ef10_vswitching_restore_vf,
6497 .vswitching_remove = efx_ef10_vswitching_remove_vf,
02246a7f 6498#endif
0d5e0fbb 6499 .get_mac_address = efx_ef10_get_mac_address_vf,
910c8789 6500 .set_mac_address = efx_ef10_set_mac_address,
0d5e0fbb 6501
08a7b29b 6502 .get_phys_port_id = efx_ef10_get_phys_port_id,
02246a7f
SS		 6503 .revision = EFX_REV_HUNT_A0,
6504 .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH),
6505 .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE,
6506 .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST,
6507 .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST,
6508 .can_rx_scatter = true,
6509 .always_rx_scatter = true,
6f9f6ec2 6510 .min_interrupt_mode = EFX_INT_MODE_MSIX,
02246a7f
SS		 6511 .max_interrupt_mode = EFX_INT_MODE_MSIX,
6512 .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH,
100a9db5 6513 .offload_features = EF10_OFFLOAD_FEATURES,
02246a7f
SS		 6514 .mcdi_max_ver = 2,
6515 .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS,
6516 .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE |
6517 1 << HWTSTAMP_FILTER_ALL,
f74d1995 6518 .rx_hash_key_size = 40,
02246a7f
SS		 6519};
6520
8127d661 6521const struct efx_nic_type efx_hunt_a0_nic_type = {
6f7f8aa6 6522 .is_vf = false,
03714bbb 6523 .mem_bar = efx_ef10_pf_mem_bar,
8127d661 6524 .mem_map_size = efx_ef10_mem_map_size,
02246a7f 6525 .probe = efx_ef10_probe_pf,
8127d661
BH		 6526 .remove = efx_ef10_remove,
6527 .dimension_resources = efx_ef10_dimension_resources,
6528 .init = efx_ef10_init_nic,
6529 .fini = efx_port_dummy_op_void,
087e9025 6530 .map_reset_reason = efx_ef10_map_reset_reason,
8127d661 6531 .map_reset_flags = efx_ef10_map_reset_flags,
3e336261 6532 .reset = efx_ef10_reset,
8127d661
BH		 6533 .probe_port = efx_mcdi_port_probe,
6534 .remove_port = efx_mcdi_port_remove,
6535 .fini_dmaq = efx_ef10_fini_dmaq,
e283546c
EC		 6536 .prepare_flr = efx_ef10_prepare_flr,
6537 .finish_flr = efx_port_dummy_op_void,
8127d661 6538 .describe_stats = efx_ef10_describe_stats,
d7788196 6539 .update_stats = efx_ef10_update_stats_pf,
8127d661 6540 .start_stats = efx_mcdi_mac_start_stats,
f8f3b5ae 6541 .pull_stats = efx_mcdi_mac_pull_stats,
8127d661
BH		 6542 .stop_stats = efx_mcdi_mac_stop_stats,
6543 .set_id_led = efx_mcdi_set_id_led,
6544 .push_irq_moderation = efx_ef10_push_irq_moderation,
6545 .reconfigure_mac = efx_ef10_mac_reconfigure,
6546 .check_mac_fault = efx_mcdi_mac_check_fault,
6547 .reconfigure_port = efx_mcdi_port_reconfigure,
6548 .get_wol = efx_ef10_get_wol,
6549 .set_wol = efx_ef10_set_wol,
6550 .resume_wol = efx_port_dummy_op_void,
74cd60a4 6551 .test_chip = efx_ef10_test_chip,
8127d661
BH		 6552 .test_nvram = efx_mcdi_nvram_test_all,
6553 .mcdi_request = efx_ef10_mcdi_request,
6554 .mcdi_poll_response = efx_ef10_mcdi_poll_response,
6555 .mcdi_read_response = efx_ef10_mcdi_read_response,
6556 .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot,
c577e59e 6557 .mcdi_reboot_detected = efx_ef10_mcdi_reboot_detected,
8127d661
BH		 6558 .irq_enable_master = efx_port_dummy_op_void,
6559 .irq_test_generate = efx_ef10_irq_test_generate,
6560 .irq_disable_non_ev = efx_port_dummy_op_void,
6561 .irq_handle_msi = efx_ef10_msi_interrupt,
6562 .irq_handle_legacy = efx_ef10_legacy_interrupt,
6563 .tx_probe = efx_ef10_tx_probe,
6564 .tx_init = efx_ef10_tx_init,
6565 .tx_remove = efx_ef10_tx_remove,
6566 .tx_write = efx_ef10_tx_write,
e9117e50 6567 .tx_limit_len = efx_ef10_tx_limit_len,
267c0157 6568 .rx_push_rss_config = efx_ef10_pf_rx_push_rss_config,
a707d188 6569 .rx_pull_rss_config = efx_ef10_rx_pull_rss_config,
8127d661
BH		 6570 .rx_probe = efx_ef10_rx_probe,
6571 .rx_init = efx_ef10_rx_init,
6572 .rx_remove = efx_ef10_rx_remove,
6573 .rx_write = efx_ef10_rx_write,
6574 .rx_defer_refill = efx_ef10_rx_defer_refill,
6575 .ev_probe = efx_ef10_ev_probe,
6576 .ev_init = efx_ef10_ev_init,
6577 .ev_fini = efx_ef10_ev_fini,
6578 .ev_remove = efx_ef10_ev_remove,
6579 .ev_process = efx_ef10_ev_process,
6580 .ev_read_ack = efx_ef10_ev_read_ack,
6581 .ev_test_generate = efx_ef10_ev_test_generate,
6582 .filter_table_probe = efx_ef10_filter_table_probe,
6583 .filter_table_restore = efx_ef10_filter_table_restore,
6584 .filter_table_remove = efx_ef10_filter_table_remove,
6585 .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter,
6586 .filter_insert = efx_ef10_filter_insert,
6587 .filter_remove_safe = efx_ef10_filter_remove_safe,
6588 .filter_get_safe = efx_ef10_filter_get_safe,
6589 .filter_clear_rx = efx_ef10_filter_clear_rx,
6590 .filter_count_rx_used = efx_ef10_filter_count_rx_used,
6591 .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit,
6592 .filter_get_rx_ids = efx_ef10_filter_get_rx_ids,
6593#ifdef CONFIG_RFS_ACCEL
6594 .filter_rfs_insert = efx_ef10_filter_rfs_insert,
6595 .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one,
6596#endif
6597#ifdef CONFIG_SFC_MTD
6598 .mtd_probe = efx_ef10_mtd_probe,
6599 .mtd_rename = efx_mcdi_mtd_rename,
6600 .mtd_read = efx_mcdi_mtd_read,
6601 .mtd_erase = efx_mcdi_mtd_erase,
6602 .mtd_write = efx_mcdi_mtd_write,
6603 .mtd_sync = efx_mcdi_mtd_sync,
6604#endif
6605 .ptp_write_host_time = efx_ef10_ptp_write_host_time,
bd9a265d
JC		 6606 .ptp_set_ts_sync_events = efx_ef10_ptp_set_ts_sync_events,
6607 .ptp_set_ts_config = efx_ef10_ptp_set_ts_config,
4a53ea8a
AR		 6608 .vlan_rx_add_vid = efx_ef10_vlan_rx_add_vid,
6609 .vlan_rx_kill_vid = efx_ef10_vlan_rx_kill_vid,
e5fbd977
JC		 6610 .udp_tnl_push_ports = efx_ef10_udp_tnl_push_ports,
6611 .udp_tnl_add_port = efx_ef10_udp_tnl_add_port,
6612 .udp_tnl_has_port = efx_ef10_udp_tnl_has_port,
6613 .udp_tnl_del_port = efx_ef10_udp_tnl_del_port,
7fa8d547 6614#ifdef CONFIG_SFC_SRIOV
834e23dd 6615 .sriov_configure = efx_ef10_sriov_configure,
d98a4ffe
SS		 6616 .sriov_init = efx_ef10_sriov_init,
6617 .sriov_fini = efx_ef10_sriov_fini,
d98a4ffe
SS		 6618 .sriov_wanted = efx_ef10_sriov_wanted,
6619 .sriov_reset = efx_ef10_sriov_reset,
7fa8d547
SS		 6620 .sriov_flr = efx_ef10_sriov_flr,
6621 .sriov_set_vf_mac = efx_ef10_sriov_set_vf_mac,
6622 .sriov_set_vf_vlan = efx_ef10_sriov_set_vf_vlan,
6623 .sriov_set_vf_spoofchk = efx_ef10_sriov_set_vf_spoofchk,
6624 .sriov_get_vf_config = efx_ef10_sriov_get_vf_config,
4392dc69 6625 .sriov_set_vf_link_state = efx_ef10_sriov_set_vf_link_state,
7b8c7b54
SS		 6626 .vswitching_probe = efx_ef10_vswitching_probe_pf,
6627 .vswitching_restore = efx_ef10_vswitching_restore_pf,
6628 .vswitching_remove = efx_ef10_vswitching_remove_pf,
7fa8d547 6629#endif
0d5e0fbb 6630 .get_mac_address = efx_ef10_get_mac_address_pf,
910c8789 6631 .set_mac_address = efx_ef10_set_mac_address,
46d1efd8 6632 .tso_versions = efx_ef10_tso_versions,
8127d661 6633
08a7b29b 6634 .get_phys_port_id = efx_ef10_get_phys_port_id,
8127d661
BH		 6635 .revision = EFX_REV_HUNT_A0,
6636 .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH),
6637 .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE,
6638 .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST,
bd9a265d 6639 .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST,
8127d661
BH		 6640 .can_rx_scatter = true,
6641 .always_rx_scatter = true,
de1deff9 6642 .option_descriptors = true,
6f9f6ec2 6643 .min_interrupt_mode = EFX_INT_MODE_LEGACY,
8127d661
BH		 6644 .max_interrupt_mode = EFX_INT_MODE_MSIX,
6645 .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH,
100a9db5 6646 .offload_features = EF10_OFFLOAD_FEATURES,
8127d661
BH		 6647 .mcdi_max_ver = 2,
6648 .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS,
bd9a265d
JC		 6649 .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE |
6650 1 << HWTSTAMP_FILTER_ALL,
f74d1995 6651 .rx_hash_key_size = 40,
8127d661 6652};
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