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sfc: Record [rt]x_dpcpu_fw_id in EF10 nic_data
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / sfc / ef10.c
CommitLineData
8127d661
BH		 1/****************************************************************************
2 * Driver for Solarflare network controllers and boards
3 * Copyright 2012-2013 Solarflare Communications Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published
7 * by the Free Software Foundation, incorporated herein by reference.
8 */
9
10#include "net_driver.h"
11#include "ef10_regs.h"
12#include "io.h"
13#include "mcdi.h"
14#include "mcdi_pcol.h"
15#include "nic.h"
16#include "workarounds.h"
74cd60a4 17#include "selftest.h"
7fa8d547 18#include "ef10_sriov.h"
8127d661
BH		 19#include <linux/in.h>
20#include <linux/jhash.h>
21#include <linux/wait.h>
22#include <linux/workqueue.h>
23
24/* Hardware control for EF10 architecture including 'Huntington'. */
25
26#define EFX_EF10_DRVGEN_EV 7
27enum {
28 EFX_EF10_TEST = 1,
29 EFX_EF10_REFILL,
30};
31
32/* The reserved RSS context value */
33#define EFX_EF10_RSS_CONTEXT_INVALID 0xffffffff
34
35/* The filter table(s) are managed by firmware and we have write-only
36 * access. When removing filters we must identify them to the
37 * firmware by a 64-bit handle, but this is too wide for Linux kernel
38 * interfaces (32-bit for RX NFC, 16-bit for RFS). Also, we need to
39 * be able to tell in advance whether a requested insertion will
40 * replace an existing filter. Therefore we maintain a software hash
41 * table, which should be at least as large as the hardware hash
42 * table.
43 *
44 * Huntington has a single 8K filter table shared between all filter
45 * types and both ports.
46 */
47#define HUNT_FILTER_TBL_ROWS 8192
48
49struct efx_ef10_filter_table {
50/* The RX match field masks supported by this fw & hw, in order of priority */
51 enum efx_filter_match_flags rx_match_flags[
52 MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM];
53 unsigned int rx_match_count;
54
55 struct {
56 unsigned long spec; /* pointer to spec plus flag bits */
b59e6ef8
BH		 57/* BUSY flag indicates that an update is in progress. AUTO_OLD is
58 * used to mark and sweep MAC filters for the device address lists.
8127d661
BH		 59 */
60#define EFX_EF10_FILTER_FLAG_BUSY 1UL
b59e6ef8 61#define EFX_EF10_FILTER_FLAG_AUTO_OLD 2UL
8127d661
BH		 62#define EFX_EF10_FILTER_FLAGS 3UL
63 u64 handle; /* firmware handle */
64 } *entry;
65 wait_queue_head_t waitq;
66/* Shadow of net_device address lists, guarded by mac_lock */
b59e6ef8
BH		 67#define EFX_EF10_FILTER_DEV_UC_MAX 32
68#define EFX_EF10_FILTER_DEV_MC_MAX 256
8127d661
BH		 69 struct {
70 u8 addr[ETH_ALEN];
71 u16 id;
b59e6ef8
BH		 72 } dev_uc_list[EFX_EF10_FILTER_DEV_UC_MAX],
73 dev_mc_list[EFX_EF10_FILTER_DEV_MC_MAX];
74 int dev_uc_count; /* negative for PROMISC */
75 int dev_mc_count; /* negative for PROMISC/ALLMULTI */
8127d661
BH		 76};
77
78/* An arbitrary search limit for the software hash table */
79#define EFX_EF10_FILTER_SEARCH_LIMIT 200
80
d43050c0 81static void efx_ef10_rx_push_rss_config(struct efx_nic *efx);
8127d661
BH		 82static void efx_ef10_rx_free_indir_table(struct efx_nic *efx);
83static void efx_ef10_filter_table_remove(struct efx_nic *efx);
84
85static int efx_ef10_get_warm_boot_count(struct efx_nic *efx)
86{
87 efx_dword_t reg;
88
89 efx_readd(efx, &reg, ER_DZ_BIU_MC_SFT_STATUS);
90 return EFX_DWORD_FIELD(reg, EFX_WORD_1) == 0xb007 ?
91 EFX_DWORD_FIELD(reg, EFX_WORD_0) : -EIO;
92}
93
94static unsigned int efx_ef10_mem_map_size(struct efx_nic *efx)
95{
96 return resource_size(&efx->pci_dev->resource[EFX_MEM_BAR]);
97}
98
e5a2538a 99static int efx_ef10_init_datapath_caps(struct efx_nic *efx)
8127d661
BH		 100{
101 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CAPABILITIES_OUT_LEN);
102 struct efx_ef10_nic_data *nic_data = efx->nic_data;
103 size_t outlen;
104 int rc;
105
106 BUILD_BUG_ON(MC_CMD_GET_CAPABILITIES_IN_LEN != 0);
107
108 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CAPABILITIES, NULL, 0,
109 outbuf, sizeof(outbuf), &outlen);
110 if (rc)
111 return rc;
e5a2538a
BH		 112 if (outlen < sizeof(outbuf)) {
113 netif_err(efx, drv, efx->net_dev,
114 "unable to read datapath firmware capabilities\n");
115 return -EIO;
116 }
117
118 nic_data->datapath_caps =
119 MCDI_DWORD(outbuf, GET_CAPABILITIES_OUT_FLAGS1);
8127d661 120
8d9f9dd4
DP		 121 /* record the DPCPU firmware IDs to determine VEB vswitching support.
122 */
123 nic_data->rx_dpcpu_fw_id =
124 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID);
125 nic_data->tx_dpcpu_fw_id =
126 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID);
127
e5a2538a
BH		 128 if (!(nic_data->datapath_caps &
129 (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN))) {
130 netif_err(efx, drv, efx->net_dev,
131 "current firmware does not support TSO\n");
132 return -ENODEV;
133 }
134
135 if (!(nic_data->datapath_caps &
136 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN))) {
137 netif_err(efx, probe, efx->net_dev,
138 "current firmware does not support an RX prefix\n");
139 return -ENODEV;
8127d661
BH		 140 }
141
142 return 0;
143}
144
145static int efx_ef10_get_sysclk_freq(struct efx_nic *efx)
146{
147 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CLOCK_OUT_LEN);
148 int rc;
149
150 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CLOCK, NULL, 0,
151 outbuf, sizeof(outbuf), NULL);
152 if (rc)
153 return rc;
154 rc = MCDI_DWORD(outbuf, GET_CLOCK_OUT_SYS_FREQ);
155 return rc > 0 ? rc : -ERANGE;
156}
157
158static int efx_ef10_get_mac_address(struct efx_nic *efx, u8 *mac_address)
159{
160 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_MAC_ADDRESSES_OUT_LEN);
161 size_t outlen;
162 int rc;
163
164 BUILD_BUG_ON(MC_CMD_GET_MAC_ADDRESSES_IN_LEN != 0);
165
166 rc = efx_mcdi_rpc(efx, MC_CMD_GET_MAC_ADDRESSES, NULL, 0,
167 outbuf, sizeof(outbuf), &outlen);
168 if (rc)
169 return rc;
170 if (outlen < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN)
171 return -EIO;
172
cd84ff4d
EC		 173 ether_addr_copy(mac_address,
174 MCDI_PTR(outbuf, GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE));
8127d661
BH		 175 return 0;
176}
177
178static int efx_ef10_probe(struct efx_nic *efx)
179{
180 struct efx_ef10_nic_data *nic_data;
181 int i, rc;
182
aa3930ee
BH		 183 /* We can have one VI for each 8K region. However, until we
184 * use TX option descriptors we need two TX queues per channel.
8127d661
BH		 185 */
186 efx->max_channels =
187 min_t(unsigned int,
188 EFX_MAX_CHANNELS,
189 resource_size(&efx->pci_dev->resource[EFX_MEM_BAR]) /
190 (EFX_VI_PAGE_SIZE * EFX_TXQ_TYPES));
9fd3d3a4
EC		 191 if (WARN_ON(efx->max_channels == 0))
192 return -EIO;
8127d661
BH		 193
194 nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
195 if (!nic_data)
196 return -ENOMEM;
197 efx->nic_data = nic_data;
198
199 rc = efx_nic_alloc_buffer(efx, &nic_data->mcdi_buf,
200 8 + MCDI_CTL_SDU_LEN_MAX_V2, GFP_KERNEL);
201 if (rc)
202 goto fail1;
203
204 /* Get the MC's warm boot count. In case it's rebooting right
205 * now, be prepared to retry.
206 */
207 i = 0;
208 for (;;) {
209 rc = efx_ef10_get_warm_boot_count(efx);
210 if (rc >= 0)
211 break;
212 if (++i == 5)
213 goto fail2;
214 ssleep(1);
215 }
216 nic_data->warm_boot_count = rc;
217
218 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
219
220 /* In case we're recovering from a crash (kexec), we want to
221 * cancel any outstanding request by the previous user of this
222 * function. We send a special message using the least
223 * significant bits of the 'high' (doorbell) register.
224 */
225 _efx_writed(efx, cpu_to_le32(1), ER_DZ_MC_DB_HWRD);
226
227 rc = efx_mcdi_init(efx);
228 if (rc)
229 goto fail2;
230
231 /* Reset (most) configuration for this function */
232 rc = efx_mcdi_reset(efx, RESET_TYPE_ALL);
233 if (rc)
234 goto fail3;
235
236 /* Enable event logging */
237 rc = efx_mcdi_log_ctrl(efx, true, false, 0);
238 if (rc)
239 goto fail3;
240
e5a2538a 241 rc = efx_ef10_init_datapath_caps(efx);
8127d661
BH		 242 if (rc < 0)
243 goto fail3;
244
245 efx->rx_packet_len_offset =
246 ES_DZ_RX_PREFIX_PKTLEN_OFST - ES_DZ_RX_PREFIX_SIZE;
247
8127d661
BH		 248 rc = efx_mcdi_port_get_number(efx);
249 if (rc < 0)
250 goto fail3;
251 efx->port_num = rc;
252
253 rc = efx_ef10_get_mac_address(efx, efx->net_dev->perm_addr);
254 if (rc)
255 goto fail3;
256
257 rc = efx_ef10_get_sysclk_freq(efx);
258 if (rc < 0)
259 goto fail3;
260 efx->timer_quantum_ns = 1536000 / rc; /* 1536 cycles */
261
262 /* Check whether firmware supports bug 35388 workaround */
263 rc = efx_mcdi_set_workaround(efx, MC_CMD_WORKAROUND_BUG35388, true);
264 if (rc == 0)
265 nic_data->workaround_35388 = true;
266 else if (rc != -ENOSYS && rc != -ENOENT)
267 goto fail3;
268 netif_dbg(efx, probe, efx->net_dev,
269 "workaround for bug 35388 is %sabled\n",
270 nic_data->workaround_35388 ? "en" : "dis");
271
272 rc = efx_mcdi_mon_probe(efx);
273 if (rc)
274 goto fail3;
275
9aecda95
BH		 276 efx_ptp_probe(efx, NULL);
277
8127d661
BH		 278 return 0;
279
280fail3:
281 efx_mcdi_fini(efx);
282fail2:
283 efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
284fail1:
285 kfree(nic_data);
286 efx->nic_data = NULL;
287 return rc;
288}
289
290static int efx_ef10_free_vis(struct efx_nic *efx)
291{
1e0b8120
EC		 292 MCDI_DECLARE_BUF_OUT_OR_ERR(outbuf, 0);
293 size_t outlen;
294 int rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FREE_VIS, NULL, 0,
295 outbuf, sizeof(outbuf), &outlen);
8127d661
BH		 296
297 /* -EALREADY means nothing to free, so ignore */
298 if (rc == -EALREADY)
299 rc = 0;
1e0b8120
EC		 300 if (rc)
301 efx_mcdi_display_error(efx, MC_CMD_FREE_VIS, 0, outbuf, outlen,
302 rc);
8127d661
BH		 303 return rc;
304}
305
183233be
BH		 306#ifdef EFX_USE_PIO
307
308static void efx_ef10_free_piobufs(struct efx_nic *efx)
309{
310 struct efx_ef10_nic_data *nic_data = efx->nic_data;
311 MCDI_DECLARE_BUF(inbuf, MC_CMD_FREE_PIOBUF_IN_LEN);
312 unsigned int i;
313 int rc;
314
315 BUILD_BUG_ON(MC_CMD_FREE_PIOBUF_OUT_LEN != 0);
316
317 for (i = 0; i < nic_data->n_piobufs; i++) {
318 MCDI_SET_DWORD(inbuf, FREE_PIOBUF_IN_PIOBUF_HANDLE,
319 nic_data->piobuf_handle[i]);
320 rc = efx_mcdi_rpc(efx, MC_CMD_FREE_PIOBUF, inbuf, sizeof(inbuf),
321 NULL, 0, NULL);
322 WARN_ON(rc);
323 }
324
325 nic_data->n_piobufs = 0;
326}
327
328static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
329{
330 struct efx_ef10_nic_data *nic_data = efx->nic_data;
331 MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_PIOBUF_OUT_LEN);
332 unsigned int i;
333 size_t outlen;
334 int rc = 0;
335
336 BUILD_BUG_ON(MC_CMD_ALLOC_PIOBUF_IN_LEN != 0);
337
338 for (i = 0; i < n; i++) {
339 rc = efx_mcdi_rpc(efx, MC_CMD_ALLOC_PIOBUF, NULL, 0,
340 outbuf, sizeof(outbuf), &outlen);
341 if (rc)
342 break;
343 if (outlen < MC_CMD_ALLOC_PIOBUF_OUT_LEN) {
344 rc = -EIO;
345 break;
346 }
347 nic_data->piobuf_handle[i] =
348 MCDI_DWORD(outbuf, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE);
349 netif_dbg(efx, probe, efx->net_dev,
350 "allocated PIO buffer %u handle %x\n", i,
351 nic_data->piobuf_handle[i]);
352 }
353
354 nic_data->n_piobufs = i;
355 if (rc)
356 efx_ef10_free_piobufs(efx);
357 return rc;
358}
359
360static int efx_ef10_link_piobufs(struct efx_nic *efx)
361{
362 struct efx_ef10_nic_data *nic_data = efx->nic_data;
363 MCDI_DECLARE_BUF(inbuf,
364 max(MC_CMD_LINK_PIOBUF_IN_LEN,
365 MC_CMD_UNLINK_PIOBUF_IN_LEN));
366 struct efx_channel *channel;
367 struct efx_tx_queue *tx_queue;
368 unsigned int offset, index;
369 int rc;
370
371 BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_OUT_LEN != 0);
372 BUILD_BUG_ON(MC_CMD_UNLINK_PIOBUF_OUT_LEN != 0);
373
374 /* Link a buffer to each VI in the write-combining mapping */
375 for (index = 0; index < nic_data->n_piobufs; ++index) {
376 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_PIOBUF_HANDLE,
377 nic_data->piobuf_handle[index]);
378 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_TXQ_INSTANCE,
379 nic_data->pio_write_vi_base + index);
380 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
381 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
382 NULL, 0, NULL);
383 if (rc) {
384 netif_err(efx, drv, efx->net_dev,
385 "failed to link VI %u to PIO buffer %u (%d)\n",
386 nic_data->pio_write_vi_base + index, index,
387 rc);
388 goto fail;
389 }
390 netif_dbg(efx, probe, efx->net_dev,
391 "linked VI %u to PIO buffer %u\n",
392 nic_data->pio_write_vi_base + index, index);
393 }
394
395 /* Link a buffer to each TX queue */
396 efx_for_each_channel(channel, efx) {
397 efx_for_each_channel_tx_queue(tx_queue, channel) {
398 /* We assign the PIO buffers to queues in
399 * reverse order to allow for the following
400 * special case.
401 */
402 offset = ((efx->tx_channel_offset + efx->n_tx_channels -
403 tx_queue->channel->channel - 1) *
404 efx_piobuf_size);
405 index = offset / ER_DZ_TX_PIOBUF_SIZE;
406 offset = offset % ER_DZ_TX_PIOBUF_SIZE;
407
408 /* When the host page size is 4K, the first
409 * host page in the WC mapping may be within
410 * the same VI page as the last TX queue. We
411 * can only link one buffer to each VI.
412 */
413 if (tx_queue->queue == nic_data->pio_write_vi_base) {
414 BUG_ON(index != 0);
415 rc = 0;
416 } else {
417 MCDI_SET_DWORD(inbuf,
418 LINK_PIOBUF_IN_PIOBUF_HANDLE,
419 nic_data->piobuf_handle[index]);
420 MCDI_SET_DWORD(inbuf,
421 LINK_PIOBUF_IN_TXQ_INSTANCE,
422 tx_queue->queue);
423 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
424 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
425 NULL, 0, NULL);
426 }
427
428 if (rc) {
429 /* This is non-fatal; the TX path just
430 * won't use PIO for this queue
431 */
432 netif_err(efx, drv, efx->net_dev,
433 "failed to link VI %u to PIO buffer %u (%d)\n",
434 tx_queue->queue, index, rc);
435 tx_queue->piobuf = NULL;
436 } else {
437 tx_queue->piobuf =
438 nic_data->pio_write_base +
439 index * EFX_VI_PAGE_SIZE + offset;
440 tx_queue->piobuf_offset = offset;
441 netif_dbg(efx, probe, efx->net_dev,
442 "linked VI %u to PIO buffer %u offset %x addr %p\n",
443 tx_queue->queue, index,
444 tx_queue->piobuf_offset,
445 tx_queue->piobuf);
446 }
447 }
448 }
449
450 return 0;
451
452fail:
453 while (index--) {
454 MCDI_SET_DWORD(inbuf, UNLINK_PIOBUF_IN_TXQ_INSTANCE,
455 nic_data->pio_write_vi_base + index);
456 efx_mcdi_rpc(efx, MC_CMD_UNLINK_PIOBUF,
457 inbuf, MC_CMD_UNLINK_PIOBUF_IN_LEN,
458 NULL, 0, NULL);
459 }
460 return rc;
461}
462
463#else /* !EFX_USE_PIO */
464
465static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
466{
467 return n == 0 ? 0 : -ENOBUFS;
468}
469
470static int efx_ef10_link_piobufs(struct efx_nic *efx)
471{
472 return 0;
473}
474
475static void efx_ef10_free_piobufs(struct efx_nic *efx)
476{
477}
478
479#endif /* EFX_USE_PIO */
480
8127d661
BH		 481static void efx_ef10_remove(struct efx_nic *efx)
482{
483 struct efx_ef10_nic_data *nic_data = efx->nic_data;
484 int rc;
485
9aecda95
BH		 486 efx_ptp_remove(efx);
487
8127d661
BH		 488 efx_mcdi_mon_remove(efx);
489
8127d661
BH		 490 efx_ef10_rx_free_indir_table(efx);
491
183233be
BH		 492 if (nic_data->wc_membase)
493 iounmap(nic_data->wc_membase);
494
8127d661
BH		 495 rc = efx_ef10_free_vis(efx);
496 WARN_ON(rc != 0);
497
183233be
BH		 498 if (!nic_data->must_restore_piobufs)
499 efx_ef10_free_piobufs(efx);
500
8127d661
BH		 501 efx_mcdi_fini(efx);
502 efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
503 kfree(nic_data);
504}
505
506static int efx_ef10_alloc_vis(struct efx_nic *efx,
507 unsigned int min_vis, unsigned int max_vis)
508{
509 MCDI_DECLARE_BUF(inbuf, MC_CMD_ALLOC_VIS_IN_LEN);
510 MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_VIS_OUT_LEN);
511 struct efx_ef10_nic_data *nic_data = efx->nic_data;
512 size_t outlen;
513 int rc;
514
515 MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MIN_VI_COUNT, min_vis);
516 MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MAX_VI_COUNT, max_vis);
517 rc = efx_mcdi_rpc(efx, MC_CMD_ALLOC_VIS, inbuf, sizeof(inbuf),
518 outbuf, sizeof(outbuf), &outlen);
519 if (rc != 0)
520 return rc;
521
522 if (outlen < MC_CMD_ALLOC_VIS_OUT_LEN)
523 return -EIO;
524
525 netif_dbg(efx, drv, efx->net_dev, "base VI is A0x%03x\n",
526 MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE));
527
528 nic_data->vi_base = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE);
529 nic_data->n_allocated_vis = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_COUNT);
530 return 0;
531}
532
183233be
BH		 533/* Note that the failure path of this function does not free
534 * resources, as this will be done by efx_ef10_remove().
535 */
8127d661
BH		 536static int efx_ef10_dimension_resources(struct efx_nic *efx)
537{
183233be
BH		 538 struct efx_ef10_nic_data *nic_data = efx->nic_data;
539 unsigned int uc_mem_map_size, wc_mem_map_size;
540 unsigned int min_vis, pio_write_vi_base, max_vis;
541 void __iomem *membase;
542 int rc;
543
544 min_vis = max(efx->n_channels, efx->n_tx_channels * EFX_TXQ_TYPES);
8127d661 545
183233be
BH		 546#ifdef EFX_USE_PIO
547 /* Try to allocate PIO buffers if wanted and if the full
548 * number of PIO buffers would be sufficient to allocate one
549 * copy-buffer per TX channel. Failure is non-fatal, as there
550 * are only a small number of PIO buffers shared between all
551 * functions of the controller.
552 */
553 if (efx_piobuf_size != 0 &&
554 ER_DZ_TX_PIOBUF_SIZE / efx_piobuf_size * EF10_TX_PIOBUF_COUNT >=
555 efx->n_tx_channels) {
556 unsigned int n_piobufs =
557 DIV_ROUND_UP(efx->n_tx_channels,
558 ER_DZ_TX_PIOBUF_SIZE / efx_piobuf_size);
559
560 rc = efx_ef10_alloc_piobufs(efx, n_piobufs);
561 if (rc)
562 netif_err(efx, probe, efx->net_dev,
563 "failed to allocate PIO buffers (%d)\n", rc);
564 else
565 netif_dbg(efx, probe, efx->net_dev,
566 "allocated %u PIO buffers\n", n_piobufs);
567 }
568#else
569 nic_data->n_piobufs = 0;
570#endif
571
572 /* PIO buffers should be mapped with write-combining enabled,
573 * and we want to make single UC and WC mappings rather than
574 * several of each (in fact that's the only option if host
575 * page size is >4K). So we may allocate some extra VIs just
576 * for writing PIO buffers through.
52ad762b
DP		 577 *
578 * The UC mapping contains (min_vis - 1) complete VIs and the
579 * first half of the next VI. Then the WC mapping begins with
580 * the second half of this last VI.
183233be
BH		 581 */
582 uc_mem_map_size = PAGE_ALIGN((min_vis - 1) * EFX_VI_PAGE_SIZE +
583 ER_DZ_TX_PIOBUF);
584 if (nic_data->n_piobufs) {
52ad762b
DP		 585 /* pio_write_vi_base rounds down to give the number of complete
586 * VIs inside the UC mapping.
587 */
183233be
BH		 588 pio_write_vi_base = uc_mem_map_size / EFX_VI_PAGE_SIZE;
589 wc_mem_map_size = (PAGE_ALIGN((pio_write_vi_base +
590 nic_data->n_piobufs) *
591 EFX_VI_PAGE_SIZE) -
592 uc_mem_map_size);
593 max_vis = pio_write_vi_base + nic_data->n_piobufs;
594 } else {
595 pio_write_vi_base = 0;
596 wc_mem_map_size = 0;
597 max_vis = min_vis;
598 }
599
600 /* In case the last attached driver failed to free VIs, do it now */
601 rc = efx_ef10_free_vis(efx);
602 if (rc != 0)
603 return rc;
604
605 rc = efx_ef10_alloc_vis(efx, min_vis, max_vis);
606 if (rc != 0)
607 return rc;
608
609 /* If we didn't get enough VIs to map all the PIO buffers, free the
610 * PIO buffers
611 */
612 if (nic_data->n_piobufs &&
613 nic_data->n_allocated_vis <
614 pio_write_vi_base + nic_data->n_piobufs) {
615 netif_dbg(efx, probe, efx->net_dev,
616 "%u VIs are not sufficient to map %u PIO buffers\n",
617 nic_data->n_allocated_vis, nic_data->n_piobufs);
618 efx_ef10_free_piobufs(efx);
619 }
620
621 /* Shrink the original UC mapping of the memory BAR */
622 membase = ioremap_nocache(efx->membase_phys, uc_mem_map_size);
623 if (!membase) {
624 netif_err(efx, probe, efx->net_dev,
625 "could not shrink memory BAR to %x\n",
626 uc_mem_map_size);
627 return -ENOMEM;
628 }
629 iounmap(efx->membase);
630 efx->membase = membase;
631
632 /* Set up the WC mapping if needed */
633 if (wc_mem_map_size) {
634 nic_data->wc_membase = ioremap_wc(efx->membase_phys +
635 uc_mem_map_size,
636 wc_mem_map_size);
637 if (!nic_data->wc_membase) {
638 netif_err(efx, probe, efx->net_dev,
639 "could not allocate WC mapping of size %x\n",
640 wc_mem_map_size);
641 return -ENOMEM;
642 }
643 nic_data->pio_write_vi_base = pio_write_vi_base;
644 nic_data->pio_write_base =
645 nic_data->wc_membase +
646 (pio_write_vi_base * EFX_VI_PAGE_SIZE + ER_DZ_TX_PIOBUF -
647 uc_mem_map_size);
648
649 rc = efx_ef10_link_piobufs(efx);
650 if (rc)
651 efx_ef10_free_piobufs(efx);
652 }
653
654 netif_dbg(efx, probe, efx->net_dev,
655 "memory BAR at %pa (virtual %p+%x UC, %p+%x WC)\n",
656 &efx->membase_phys, efx->membase, uc_mem_map_size,
657 nic_data->wc_membase, wc_mem_map_size);
658
659 return 0;
8127d661
BH		 660}
661
662static int efx_ef10_init_nic(struct efx_nic *efx)
663{
664 struct efx_ef10_nic_data *nic_data = efx->nic_data;
665 int rc;
666
a915ccc9
BH		 667 if (nic_data->must_check_datapath_caps) {
668 rc = efx_ef10_init_datapath_caps(efx);
669 if (rc)
670 return rc;
671 nic_data->must_check_datapath_caps = false;
672 }
673
8127d661
BH		 674 if (nic_data->must_realloc_vis) {
675 /* We cannot let the number of VIs change now */
676 rc = efx_ef10_alloc_vis(efx, nic_data->n_allocated_vis,
677 nic_data->n_allocated_vis);
678 if (rc)
679 return rc;
680 nic_data->must_realloc_vis = false;
681 }
682
183233be
BH		 683 if (nic_data->must_restore_piobufs && nic_data->n_piobufs) {
684 rc = efx_ef10_alloc_piobufs(efx, nic_data->n_piobufs);
685 if (rc == 0) {
686 rc = efx_ef10_link_piobufs(efx);
687 if (rc)
688 efx_ef10_free_piobufs(efx);
689 }
690
691 /* Log an error on failure, but this is non-fatal */
692 if (rc)
693 netif_err(efx, drv, efx->net_dev,
694 "failed to restore PIO buffers (%d)\n", rc);
695 nic_data->must_restore_piobufs = false;
696 }
697
d43050c0 698 efx_ef10_rx_push_rss_config(efx);
8127d661
BH		 699 return 0;
700}
701
3e336261
JC		 702static void efx_ef10_reset_mc_allocations(struct efx_nic *efx)
703{
704 struct efx_ef10_nic_data *nic_data = efx->nic_data;
705
706 /* All our allocations have been reset */
707 nic_data->must_realloc_vis = true;
708 nic_data->must_restore_filters = true;
709 nic_data->must_restore_piobufs = true;
710 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
711}
712
8127d661
BH		 713static int efx_ef10_map_reset_flags(u32 *flags)
714{
715 enum {
716 EF10_RESET_PORT = ((ETH_RESET_MAC | ETH_RESET_PHY) <<
717 ETH_RESET_SHARED_SHIFT),
718 EF10_RESET_MC = ((ETH_RESET_DMA | ETH_RESET_FILTER |
719 ETH_RESET_OFFLOAD | ETH_RESET_MAC |
720 ETH_RESET_PHY | ETH_RESET_MGMT) <<
721 ETH_RESET_SHARED_SHIFT)
722 };
723
724 /* We assume for now that our PCI function is permitted to
725 * reset everything.
726 */
727
728 if ((*flags & EF10_RESET_MC) == EF10_RESET_MC) {
729 *flags &= ~EF10_RESET_MC;
730 return RESET_TYPE_WORLD;
731 }
732
733 if ((*flags & EF10_RESET_PORT) == EF10_RESET_PORT) {
734 *flags &= ~EF10_RESET_PORT;
735 return RESET_TYPE_ALL;
736 }
737
738 /* no invisible reset implemented */
739
740 return -EINVAL;
741}
742
3e336261
JC		 743static int efx_ef10_reset(struct efx_nic *efx, enum reset_type reset_type)
744{
745 int rc = efx_mcdi_reset(efx, reset_type);
746
747 /* If it was a port reset, trigger reallocation of MC resources.
748 * Note that on an MC reset nothing needs to be done now because we'll
749 * detect the MC reset later and handle it then.
e283546c
EC		 750 * For an FLR, we never get an MC reset event, but the MC has reset all
751 * resources assigned to us, so we have to trigger reallocation now.
3e336261 752 */
e283546c
EC		 753 if ((reset_type == RESET_TYPE_ALL ||
754 reset_type == RESET_TYPE_MCDI_TIMEOUT) && !rc)
3e336261
JC		 755 efx_ef10_reset_mc_allocations(efx);
756 return rc;
757}
758
8127d661
BH		 759#define EF10_DMA_STAT(ext_name, mcdi_name) \
760 [EF10_STAT_ ## ext_name] = \
761 { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
762#define EF10_DMA_INVIS_STAT(int_name, mcdi_name) \
763 [EF10_STAT_ ## int_name] = \
764 { NULL, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
765#define EF10_OTHER_STAT(ext_name) \
766 [EF10_STAT_ ## ext_name] = { #ext_name, 0, 0 }
e4d112e4
EC		 767#define GENERIC_SW_STAT(ext_name) \
768 [GENERIC_STAT_ ## ext_name] = { #ext_name, 0, 0 }
8127d661
BH		 769
770static const struct efx_hw_stat_desc efx_ef10_stat_desc[EF10_STAT_COUNT] = {
771 EF10_DMA_STAT(tx_bytes, TX_BYTES),
772 EF10_DMA_STAT(tx_packets, TX_PKTS),
773 EF10_DMA_STAT(tx_pause, TX_PAUSE_PKTS),
774 EF10_DMA_STAT(tx_control, TX_CONTROL_PKTS),
775 EF10_DMA_STAT(tx_unicast, TX_UNICAST_PKTS),
776 EF10_DMA_STAT(tx_multicast, TX_MULTICAST_PKTS),
777 EF10_DMA_STAT(tx_broadcast, TX_BROADCAST_PKTS),
778 EF10_DMA_STAT(tx_lt64, TX_LT64_PKTS),
779 EF10_DMA_STAT(tx_64, TX_64_PKTS),
780 EF10_DMA_STAT(tx_65_to_127, TX_65_TO_127_PKTS),
781 EF10_DMA_STAT(tx_128_to_255, TX_128_TO_255_PKTS),
782 EF10_DMA_STAT(tx_256_to_511, TX_256_TO_511_PKTS),
783 EF10_DMA_STAT(tx_512_to_1023, TX_512_TO_1023_PKTS),
784 EF10_DMA_STAT(tx_1024_to_15xx, TX_1024_TO_15XX_PKTS),
785 EF10_DMA_STAT(tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS),
786 EF10_DMA_STAT(rx_bytes, RX_BYTES),
787 EF10_DMA_INVIS_STAT(rx_bytes_minus_good_bytes, RX_BAD_BYTES),
788 EF10_OTHER_STAT(rx_good_bytes),
789 EF10_OTHER_STAT(rx_bad_bytes),
790 EF10_DMA_STAT(rx_packets, RX_PKTS),
791 EF10_DMA_STAT(rx_good, RX_GOOD_PKTS),
792 EF10_DMA_STAT(rx_bad, RX_BAD_FCS_PKTS),
793 EF10_DMA_STAT(rx_pause, RX_PAUSE_PKTS),
794 EF10_DMA_STAT(rx_control, RX_CONTROL_PKTS),
795 EF10_DMA_STAT(rx_unicast, RX_UNICAST_PKTS),
796 EF10_DMA_STAT(rx_multicast, RX_MULTICAST_PKTS),
797 EF10_DMA_STAT(rx_broadcast, RX_BROADCAST_PKTS),
798 EF10_DMA_STAT(rx_lt64, RX_UNDERSIZE_PKTS),
799 EF10_DMA_STAT(rx_64, RX_64_PKTS),
800 EF10_DMA_STAT(rx_65_to_127, RX_65_TO_127_PKTS),
801 EF10_DMA_STAT(rx_128_to_255, RX_128_TO_255_PKTS),
802 EF10_DMA_STAT(rx_256_to_511, RX_256_TO_511_PKTS),
803 EF10_DMA_STAT(rx_512_to_1023, RX_512_TO_1023_PKTS),
804 EF10_DMA_STAT(rx_1024_to_15xx, RX_1024_TO_15XX_PKTS),
805 EF10_DMA_STAT(rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS),
806 EF10_DMA_STAT(rx_gtjumbo, RX_GTJUMBO_PKTS),
807 EF10_DMA_STAT(rx_bad_gtjumbo, RX_JABBER_PKTS),
808 EF10_DMA_STAT(rx_overflow, RX_OVERFLOW_PKTS),
809 EF10_DMA_STAT(rx_align_error, RX_ALIGN_ERROR_PKTS),
810 EF10_DMA_STAT(rx_length_error, RX_LENGTH_ERROR_PKTS),
811 EF10_DMA_STAT(rx_nodesc_drops, RX_NODESC_DROPS),
e4d112e4
EC		 812 GENERIC_SW_STAT(rx_nodesc_trunc),
813 GENERIC_SW_STAT(rx_noskb_drops),
568d7a00
EC		 814 EF10_DMA_STAT(rx_pm_trunc_bb_overflow, PM_TRUNC_BB_OVERFLOW),
815 EF10_DMA_STAT(rx_pm_discard_bb_overflow, PM_DISCARD_BB_OVERFLOW),
816 EF10_DMA_STAT(rx_pm_trunc_vfifo_full, PM_TRUNC_VFIFO_FULL),
817 EF10_DMA_STAT(rx_pm_discard_vfifo_full, PM_DISCARD_VFIFO_FULL),
818 EF10_DMA_STAT(rx_pm_trunc_qbb, PM_TRUNC_QBB),
819 EF10_DMA_STAT(rx_pm_discard_qbb, PM_DISCARD_QBB),
820 EF10_DMA_STAT(rx_pm_discard_mapping, PM_DISCARD_MAPPING),
821 EF10_DMA_STAT(rx_dp_q_disabled_packets, RXDP_Q_DISABLED_PKTS),
822 EF10_DMA_STAT(rx_dp_di_dropped_packets, RXDP_DI_DROPPED_PKTS),
823 EF10_DMA_STAT(rx_dp_streaming_packets, RXDP_STREAMING_PKTS),
79ac47ae
SS		 824 EF10_DMA_STAT(rx_dp_hlb_fetch, RXDP_EMERGENCY_FETCH_CONDITIONS),
825 EF10_DMA_STAT(rx_dp_hlb_wait, RXDP_EMERGENCY_WAIT_CONDITIONS),
8127d661
BH		 826};
827
828#define HUNT_COMMON_STAT_MASK ((1ULL << EF10_STAT_tx_bytes) | \
829 (1ULL << EF10_STAT_tx_packets) | \
830 (1ULL << EF10_STAT_tx_pause) | \
831 (1ULL << EF10_STAT_tx_unicast) | \
832 (1ULL << EF10_STAT_tx_multicast) | \
833 (1ULL << EF10_STAT_tx_broadcast) | \
834 (1ULL << EF10_STAT_rx_bytes) | \
835 (1ULL << EF10_STAT_rx_bytes_minus_good_bytes) | \
836 (1ULL << EF10_STAT_rx_good_bytes) | \
837 (1ULL << EF10_STAT_rx_bad_bytes) | \
838 (1ULL << EF10_STAT_rx_packets) | \
839 (1ULL << EF10_STAT_rx_good) | \
840 (1ULL << EF10_STAT_rx_bad) | \
841 (1ULL << EF10_STAT_rx_pause) | \
842 (1ULL << EF10_STAT_rx_control) | \
843 (1ULL << EF10_STAT_rx_unicast) | \
844 (1ULL << EF10_STAT_rx_multicast) | \
845 (1ULL << EF10_STAT_rx_broadcast) | \
846 (1ULL << EF10_STAT_rx_lt64) | \
847 (1ULL << EF10_STAT_rx_64) | \
848 (1ULL << EF10_STAT_rx_65_to_127) | \
849 (1ULL << EF10_STAT_rx_128_to_255) | \
850 (1ULL << EF10_STAT_rx_256_to_511) | \
851 (1ULL << EF10_STAT_rx_512_to_1023) | \
852 (1ULL << EF10_STAT_rx_1024_to_15xx) | \
853 (1ULL << EF10_STAT_rx_15xx_to_jumbo) | \
854 (1ULL << EF10_STAT_rx_gtjumbo) | \
855 (1ULL << EF10_STAT_rx_bad_gtjumbo) | \
856 (1ULL << EF10_STAT_rx_overflow) | \
e4d112e4
EC		 857 (1ULL << EF10_STAT_rx_nodesc_drops) | \
858 (1ULL << GENERIC_STAT_rx_nodesc_trunc) | \
859 (1ULL << GENERIC_STAT_rx_noskb_drops))
8127d661
BH		 860
861/* These statistics are only provided by the 10G MAC. For a 10G/40G
862 * switchable port we do not expose these because they might not
863 * include all the packets they should.
864 */
865#define HUNT_10G_ONLY_STAT_MASK ((1ULL << EF10_STAT_tx_control) | \
866 (1ULL << EF10_STAT_tx_lt64) | \
867 (1ULL << EF10_STAT_tx_64) | \
868 (1ULL << EF10_STAT_tx_65_to_127) | \
869 (1ULL << EF10_STAT_tx_128_to_255) | \
870 (1ULL << EF10_STAT_tx_256_to_511) | \
871 (1ULL << EF10_STAT_tx_512_to_1023) | \
872 (1ULL << EF10_STAT_tx_1024_to_15xx) | \
873 (1ULL << EF10_STAT_tx_15xx_to_jumbo))
874
875/* These statistics are only provided by the 40G MAC. For a 10G/40G
876 * switchable port we do expose these because the errors will otherwise
877 * be silent.
878 */
879#define HUNT_40G_EXTRA_STAT_MASK ((1ULL << EF10_STAT_rx_align_error) | \
880 (1ULL << EF10_STAT_rx_length_error))
881
568d7a00
EC		 882/* These statistics are only provided if the firmware supports the
883 * capability PM_AND_RXDP_COUNTERS.
884 */
885#define HUNT_PM_AND_RXDP_STAT_MASK ( \
886 (1ULL << EF10_STAT_rx_pm_trunc_bb_overflow) | \
887 (1ULL << EF10_STAT_rx_pm_discard_bb_overflow) | \
888 (1ULL << EF10_STAT_rx_pm_trunc_vfifo_full) | \
889 (1ULL << EF10_STAT_rx_pm_discard_vfifo_full) | \
890 (1ULL << EF10_STAT_rx_pm_trunc_qbb) | \
891 (1ULL << EF10_STAT_rx_pm_discard_qbb) | \
892 (1ULL << EF10_STAT_rx_pm_discard_mapping) | \
893 (1ULL << EF10_STAT_rx_dp_q_disabled_packets) | \
894 (1ULL << EF10_STAT_rx_dp_di_dropped_packets) | \
895 (1ULL << EF10_STAT_rx_dp_streaming_packets) | \
79ac47ae
SS		 896 (1ULL << EF10_STAT_rx_dp_hlb_fetch) | \
897 (1ULL << EF10_STAT_rx_dp_hlb_wait))
568d7a00 898
4bae913b 899static u64 efx_ef10_raw_stat_mask(struct efx_nic *efx)
8127d661 900{
4bae913b 901 u64 raw_mask = HUNT_COMMON_STAT_MASK;
8127d661 902 u32 port_caps = efx_mcdi_phy_get_caps(efx);
568d7a00 903 struct efx_ef10_nic_data *nic_data = efx->nic_data;
8127d661
BH		 904
905 if (port_caps & (1 << MC_CMD_PHY_CAP_40000FDX_LBN))
4bae913b 906 raw_mask |= HUNT_40G_EXTRA_STAT_MASK;
8127d661 907 else
4bae913b 908 raw_mask |= HUNT_10G_ONLY_STAT_MASK;
568d7a00
EC		 909
910 if (nic_data->datapath_caps &
911 (1 << MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN))
912 raw_mask |= HUNT_PM_AND_RXDP_STAT_MASK;
913
4bae913b
EC		 914 return raw_mask;
915}
916
917static void efx_ef10_get_stat_mask(struct efx_nic *efx, unsigned long *mask)
918{
919 u64 raw_mask = efx_ef10_raw_stat_mask(efx);
920
921#if BITS_PER_LONG == 64
922 mask[0] = raw_mask;
923#else
924 mask[0] = raw_mask & 0xffffffff;
925 mask[1] = raw_mask >> 32;
926#endif
8127d661
BH		 927}
928
929static size_t efx_ef10_describe_stats(struct efx_nic *efx, u8 *names)
930{
4bae913b
EC		 931 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
932
933 efx_ef10_get_stat_mask(efx, mask);
8127d661 934 return efx_nic_describe_stats(efx_ef10_stat_desc, EF10_STAT_COUNT,
4bae913b 935 mask, names);
8127d661
BH		 936}
937
938static int efx_ef10_try_update_nic_stats(struct efx_nic *efx)
939{
940 struct efx_ef10_nic_data *nic_data = efx->nic_data;
4bae913b 941 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
8127d661
BH		 942 __le64 generation_start, generation_end;
943 u64 *stats = nic_data->stats;
944 __le64 *dma_stats;
945
4bae913b
EC		 946 efx_ef10_get_stat_mask(efx, mask);
947
8127d661
BH		 948 dma_stats = efx->stats_buffer.addr;
949 nic_data = efx->nic_data;
950
951 generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
952 if (generation_end == EFX_MC_STATS_GENERATION_INVALID)
953 return 0;
954 rmb();
4bae913b 955 efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask,
8127d661 956 stats, efx->stats_buffer.addr, false);
d546a893 957 rmb();
8127d661
BH		 958 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
959 if (generation_end != generation_start)
960 return -EAGAIN;
961
962 /* Update derived statistics */
f8f3b5ae 963 efx_nic_fix_nodesc_drop_stat(efx, &stats[EF10_STAT_rx_nodesc_drops]);
8127d661
BH		 964 stats[EF10_STAT_rx_good_bytes] =
965 stats[EF10_STAT_rx_bytes] -
966 stats[EF10_STAT_rx_bytes_minus_good_bytes];
967 efx_update_diff_stat(&stats[EF10_STAT_rx_bad_bytes],
968 stats[EF10_STAT_rx_bytes_minus_good_bytes]);
e4d112e4 969 efx_update_sw_stats(efx, stats);
8127d661
BH		 970 return 0;
971}
972
973
974static size_t efx_ef10_update_stats(struct efx_nic *efx, u64 *full_stats,
975 struct rtnl_link_stats64 *core_stats)
976{
4bae913b 977 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
8127d661
BH		 978 struct efx_ef10_nic_data *nic_data = efx->nic_data;
979 u64 *stats = nic_data->stats;
980 size_t stats_count = 0, index;
981 int retry;
982
4bae913b
EC		 983 efx_ef10_get_stat_mask(efx, mask);
984
8127d661
BH		 985 /* If we're unlucky enough to read statistics during the DMA, wait
986 * up to 10ms for it to finish (typically takes <500us)
987 */
988 for (retry = 0; retry < 100; ++retry) {
989 if (efx_ef10_try_update_nic_stats(efx) == 0)
990 break;
991 udelay(100);
992 }
993
994 if (full_stats) {
995 for_each_set_bit(index, mask, EF10_STAT_COUNT) {
996 if (efx_ef10_stat_desc[index].name) {
997 *full_stats++ = stats[index];
998 ++stats_count;
999 }
1000 }
1001 }
1002
1003 if (core_stats) {
1004 core_stats->rx_packets = stats[EF10_STAT_rx_packets];
1005 core_stats->tx_packets = stats[EF10_STAT_tx_packets];
1006 core_stats->rx_bytes = stats[EF10_STAT_rx_bytes];
1007 core_stats->tx_bytes = stats[EF10_STAT_tx_bytes];
e4d112e4
EC		 1008 core_stats->rx_dropped = stats[EF10_STAT_rx_nodesc_drops] +
1009 stats[GENERIC_STAT_rx_nodesc_trunc] +
1010 stats[GENERIC_STAT_rx_noskb_drops];
8127d661
BH		 1011 core_stats->multicast = stats[EF10_STAT_rx_multicast];
1012 core_stats->rx_length_errors =
1013 stats[EF10_STAT_rx_gtjumbo] +
1014 stats[EF10_STAT_rx_length_error];
1015 core_stats->rx_crc_errors = stats[EF10_STAT_rx_bad];
1016 core_stats->rx_frame_errors = stats[EF10_STAT_rx_align_error];
1017 core_stats->rx_fifo_errors = stats[EF10_STAT_rx_overflow];
1018 core_stats->rx_errors = (core_stats->rx_length_errors +
1019 core_stats->rx_crc_errors +
1020 core_stats->rx_frame_errors);
1021 }
1022
1023 return stats_count;
1024}
1025
1026static void efx_ef10_push_irq_moderation(struct efx_channel *channel)
1027{
1028 struct efx_nic *efx = channel->efx;
1029 unsigned int mode, value;
1030 efx_dword_t timer_cmd;
1031
1032 if (channel->irq_moderation) {
1033 mode = 3;
1034 value = channel->irq_moderation - 1;
1035 } else {
1036 mode = 0;
1037 value = 0;
1038 }
1039
1040 if (EFX_EF10_WORKAROUND_35388(efx)) {
1041 EFX_POPULATE_DWORD_3(timer_cmd, ERF_DD_EVQ_IND_TIMER_FLAGS,
1042 EFE_DD_EVQ_IND_TIMER_FLAGS,
1043 ERF_DD_EVQ_IND_TIMER_MODE, mode,
1044 ERF_DD_EVQ_IND_TIMER_VAL, value);
1045 efx_writed_page(efx, &timer_cmd, ER_DD_EVQ_INDIRECT,
1046 channel->channel);
1047 } else {
1048 EFX_POPULATE_DWORD_2(timer_cmd, ERF_DZ_TC_TIMER_MODE, mode,
1049 ERF_DZ_TC_TIMER_VAL, value);
1050 efx_writed_page(efx, &timer_cmd, ER_DZ_EVQ_TMR,
1051 channel->channel);
1052 }
1053}
1054
1055static void efx_ef10_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
1056{
1057 wol->supported = 0;
1058 wol->wolopts = 0;
1059 memset(&wol->sopass, 0, sizeof(wol->sopass));
1060}
1061
1062static int efx_ef10_set_wol(struct efx_nic *efx, u32 type)
1063{
1064 if (type != 0)
1065 return -EINVAL;
1066 return 0;
1067}
1068
1069static void efx_ef10_mcdi_request(struct efx_nic *efx,
1070 const efx_dword_t *hdr, size_t hdr_len,
1071 const efx_dword_t *sdu, size_t sdu_len)
1072{
1073 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1074 u8 *pdu = nic_data->mcdi_buf.addr;
1075
1076 memcpy(pdu, hdr, hdr_len);
1077 memcpy(pdu + hdr_len, sdu, sdu_len);
1078 wmb();
1079
1080 /* The hardware provides 'low' and 'high' (doorbell) registers
1081 * for passing the 64-bit address of an MCDI request to
1082 * firmware. However the dwords are swapped by firmware. The
1083 * least significant bits of the doorbell are then 0 for all
1084 * MCDI requests due to alignment.
1085 */
1086 _efx_writed(efx, cpu_to_le32((u64)nic_data->mcdi_buf.dma_addr >> 32),
1087 ER_DZ_MC_DB_LWRD);
1088 _efx_writed(efx, cpu_to_le32((u32)nic_data->mcdi_buf.dma_addr),
1089 ER_DZ_MC_DB_HWRD);
1090}
1091
1092static bool efx_ef10_mcdi_poll_response(struct efx_nic *efx)
1093{
1094 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1095 const efx_dword_t hdr = *(const efx_dword_t *)nic_data->mcdi_buf.addr;
1096
1097 rmb();
1098 return EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE);
1099}
1100
1101static void
1102efx_ef10_mcdi_read_response(struct efx_nic *efx, efx_dword_t *outbuf,
1103 size_t offset, size_t outlen)
1104{
1105 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1106 const u8 *pdu = nic_data->mcdi_buf.addr;
1107
1108 memcpy(outbuf, pdu + offset, outlen);
1109}
1110
1111static int efx_ef10_mcdi_poll_reboot(struct efx_nic *efx)
1112{
1113 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1114 int rc;
1115
1116 rc = efx_ef10_get_warm_boot_count(efx);
1117 if (rc < 0) {
1118 /* The firmware is presumably in the process of
1119 * rebooting. However, we are supposed to report each
1120 * reboot just once, so we must only do that once we
1121 * can read and store the updated warm boot count.
1122 */
1123 return 0;
1124 }
1125
1126 if (rc == nic_data->warm_boot_count)
1127 return 0;
1128
1129 nic_data->warm_boot_count = rc;
1130
1131 /* All our allocations have been reset */
3e336261 1132 efx_ef10_reset_mc_allocations(efx);
8127d661 1133
a915ccc9
BH		 1134 /* The datapath firmware might have been changed */
1135 nic_data->must_check_datapath_caps = true;
1136
869070c5
BH		 1137 /* MAC statistics have been cleared on the NIC; clear the local
1138 * statistic that we update with efx_update_diff_stat().
1139 */
1140 nic_data->stats[EF10_STAT_rx_bad_bytes] = 0;
1141
8127d661
BH		 1142 return -EIO;
1143}
1144
1145/* Handle an MSI interrupt
1146 *
1147 * Handle an MSI hardware interrupt. This routine schedules event
1148 * queue processing. No interrupt acknowledgement cycle is necessary.
1149 * Also, we never need to check that the interrupt is for us, since
1150 * MSI interrupts cannot be shared.
1151 */
1152static irqreturn_t efx_ef10_msi_interrupt(int irq, void *dev_id)
1153{
1154 struct efx_msi_context *context = dev_id;
1155 struct efx_nic *efx = context->efx;
1156
1157 netif_vdbg(efx, intr, efx->net_dev,
1158 "IRQ %d on CPU %d\n", irq, raw_smp_processor_id());
1159
1160 if (likely(ACCESS_ONCE(efx->irq_soft_enabled))) {
1161 /* Note test interrupts */
1162 if (context->index == efx->irq_level)
1163 efx->last_irq_cpu = raw_smp_processor_id();
1164
1165 /* Schedule processing of the channel */
1166 efx_schedule_channel_irq(efx->channel[context->index]);
1167 }
1168
1169 return IRQ_HANDLED;
1170}
1171
1172static irqreturn_t efx_ef10_legacy_interrupt(int irq, void *dev_id)
1173{
1174 struct efx_nic *efx = dev_id;
1175 bool soft_enabled = ACCESS_ONCE(efx->irq_soft_enabled);
1176 struct efx_channel *channel;
1177 efx_dword_t reg;
1178 u32 queues;
1179
1180 /* Read the ISR which also ACKs the interrupts */
1181 efx_readd(efx, &reg, ER_DZ_BIU_INT_ISR);
1182 queues = EFX_DWORD_FIELD(reg, ERF_DZ_ISR_REG);
1183
1184 if (queues == 0)
1185 return IRQ_NONE;
1186
1187 if (likely(soft_enabled)) {
1188 /* Note test interrupts */
1189 if (queues & (1U << efx->irq_level))
1190 efx->last_irq_cpu = raw_smp_processor_id();
1191
1192 efx_for_each_channel(channel, efx) {
1193 if (queues & 1)
1194 efx_schedule_channel_irq(channel);
1195 queues >>= 1;
1196 }
1197 }
1198
1199 netif_vdbg(efx, intr, efx->net_dev,
1200 "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
1201 irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
1202
1203 return IRQ_HANDLED;
1204}
1205
1206static void efx_ef10_irq_test_generate(struct efx_nic *efx)
1207{
1208 MCDI_DECLARE_BUF(inbuf, MC_CMD_TRIGGER_INTERRUPT_IN_LEN);
1209
1210 BUILD_BUG_ON(MC_CMD_TRIGGER_INTERRUPT_OUT_LEN != 0);
1211
1212 MCDI_SET_DWORD(inbuf, TRIGGER_INTERRUPT_IN_INTR_LEVEL, efx->irq_level);
1213 (void) efx_mcdi_rpc(efx, MC_CMD_TRIGGER_INTERRUPT,
1214 inbuf, sizeof(inbuf), NULL, 0, NULL);
1215}
1216
1217static int efx_ef10_tx_probe(struct efx_tx_queue *tx_queue)
1218{
1219 return efx_nic_alloc_buffer(tx_queue->efx, &tx_queue->txd.buf,
1220 (tx_queue->ptr_mask + 1) *
1221 sizeof(efx_qword_t),
1222 GFP_KERNEL);
1223}
1224
1225/* This writes to the TX_DESC_WPTR and also pushes data */
1226static inline void efx_ef10_push_tx_desc(struct efx_tx_queue *tx_queue,
1227 const efx_qword_t *txd)
1228{
1229 unsigned int write_ptr;
1230 efx_oword_t reg;
1231
1232 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
1233 EFX_POPULATE_OWORD_1(reg, ERF_DZ_TX_DESC_WPTR, write_ptr);
1234 reg.qword[0] = *txd;
1235 efx_writeo_page(tx_queue->efx, &reg,
1236 ER_DZ_TX_DESC_UPD, tx_queue->queue);
1237}
1238
1239static void efx_ef10_tx_init(struct efx_tx_queue *tx_queue)
1240{
1241 MCDI_DECLARE_BUF(inbuf, MC_CMD_INIT_TXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
1242 EFX_BUF_SIZE));
1243 MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_TXQ_OUT_LEN);
1244 bool csum_offload = tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD;
1245 size_t entries = tx_queue->txd.buf.len / EFX_BUF_SIZE;
1246 struct efx_channel *channel = tx_queue->channel;
1247 struct efx_nic *efx = tx_queue->efx;
1248 size_t inlen, outlen;
1249 dma_addr_t dma_addr;
1250 efx_qword_t *txd;
1251 int rc;
1252 int i;
1253
1254 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_SIZE, tx_queue->ptr_mask + 1);
1255 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_TARGET_EVQ, channel->channel);
1256 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_LABEL, tx_queue->queue);
1257 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_INSTANCE, tx_queue->queue);
1258 MCDI_POPULATE_DWORD_2(inbuf, INIT_TXQ_IN_FLAGS,
1259 INIT_TXQ_IN_FLAG_IP_CSUM_DIS, !csum_offload,
1260 INIT_TXQ_IN_FLAG_TCP_CSUM_DIS, !csum_offload);
1261 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_OWNER_ID, 0);
1262 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_PORT_ID, EVB_PORT_ID_ASSIGNED);
1263
1264 dma_addr = tx_queue->txd.buf.dma_addr;
1265
1266 netif_dbg(efx, hw, efx->net_dev, "pushing TXQ %d. %zu entries (%llx)\n",
1267 tx_queue->queue, entries, (u64)dma_addr);
1268
1269 for (i = 0; i < entries; ++i) {
1270 MCDI_SET_ARRAY_QWORD(inbuf, INIT_TXQ_IN_DMA_ADDR, i, dma_addr);
1271 dma_addr += EFX_BUF_SIZE;
1272 }
1273
1274 inlen = MC_CMD_INIT_TXQ_IN_LEN(entries);
1275
1276 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_TXQ, inbuf, inlen,
1277 outbuf, sizeof(outbuf), &outlen);
1278 if (rc)
1279 goto fail;
1280
1281 /* A previous user of this TX queue might have set us up the
1282 * bomb by writing a descriptor to the TX push collector but
1283 * not the doorbell. (Each collector belongs to a port, not a
1284 * queue or function, so cannot easily be reset.) We must
1285 * attempt to push a no-op descriptor in its place.
1286 */
1287 tx_queue->buffer[0].flags = EFX_TX_BUF_OPTION;
1288 tx_queue->insert_count = 1;
1289 txd = efx_tx_desc(tx_queue, 0);
1290 EFX_POPULATE_QWORD_4(*txd,
1291 ESF_DZ_TX_DESC_IS_OPT, true,
1292 ESF_DZ_TX_OPTION_TYPE,
1293 ESE_DZ_TX_OPTION_DESC_CRC_CSUM,
1294 ESF_DZ_TX_OPTION_UDP_TCP_CSUM, csum_offload,
1295 ESF_DZ_TX_OPTION_IP_CSUM, csum_offload);
1296 tx_queue->write_count = 1;
1297 wmb();
1298 efx_ef10_push_tx_desc(tx_queue, txd);
1299
1300 return;
1301
1302fail:
48ce5634
BH		 1303 netdev_WARN(efx->net_dev, "failed to initialise TXQ %d\n",
1304 tx_queue->queue);
8127d661
BH		 1305}
1306
1307static void efx_ef10_tx_fini(struct efx_tx_queue *tx_queue)
1308{
1309 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_TXQ_IN_LEN);
1310 MCDI_DECLARE_BUF(outbuf, MC_CMD_FINI_TXQ_OUT_LEN);
1311 struct efx_nic *efx = tx_queue->efx;
1312 size_t outlen;
1313 int rc;
1314
1315 MCDI_SET_DWORD(inbuf, FINI_TXQ_IN_INSTANCE,
1316 tx_queue->queue);
1317
1e0b8120 1318 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_TXQ, inbuf, sizeof(inbuf),
8127d661
BH		 1319 outbuf, sizeof(outbuf), &outlen);
1320
1321 if (rc && rc != -EALREADY)
1322 goto fail;
1323
1324 return;
1325
1326fail:
1e0b8120
EC		 1327 efx_mcdi_display_error(efx, MC_CMD_FINI_TXQ, MC_CMD_FINI_TXQ_IN_LEN,
1328 outbuf, outlen, rc);
8127d661
BH		 1329}
1330
1331static void efx_ef10_tx_remove(struct efx_tx_queue *tx_queue)
1332{
1333 efx_nic_free_buffer(tx_queue->efx, &tx_queue->txd.buf);
1334}
1335
1336/* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
1337static inline void efx_ef10_notify_tx_desc(struct efx_tx_queue *tx_queue)
1338{
1339 unsigned int write_ptr;
1340 efx_dword_t reg;
1341
1342 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
1343 EFX_POPULATE_DWORD_1(reg, ERF_DZ_TX_DESC_WPTR_DWORD, write_ptr);
1344 efx_writed_page(tx_queue->efx, &reg,
1345 ER_DZ_TX_DESC_UPD_DWORD, tx_queue->queue);
1346}
1347
1348static void efx_ef10_tx_write(struct efx_tx_queue *tx_queue)
1349{
1350 unsigned int old_write_count = tx_queue->write_count;
1351 struct efx_tx_buffer *buffer;
1352 unsigned int write_ptr;
1353 efx_qword_t *txd;
1354
1355 BUG_ON(tx_queue->write_count == tx_queue->insert_count);
1356
1357 do {
1358 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
1359 buffer = &tx_queue->buffer[write_ptr];
1360 txd = efx_tx_desc(tx_queue, write_ptr);
1361 ++tx_queue->write_count;
1362
1363 /* Create TX descriptor ring entry */
1364 if (buffer->flags & EFX_TX_BUF_OPTION) {
1365 *txd = buffer->option;
1366 } else {
1367 BUILD_BUG_ON(EFX_TX_BUF_CONT != 1);
1368 EFX_POPULATE_QWORD_3(
1369 *txd,
1370 ESF_DZ_TX_KER_CONT,
1371 buffer->flags & EFX_TX_BUF_CONT,
1372 ESF_DZ_TX_KER_BYTE_CNT, buffer->len,
1373 ESF_DZ_TX_KER_BUF_ADDR, buffer->dma_addr);
1374 }
1375 } while (tx_queue->write_count != tx_queue->insert_count);
1376
1377 wmb(); /* Ensure descriptors are written before they are fetched */
1378
1379 if (efx_nic_may_push_tx_desc(tx_queue, old_write_count)) {
1380 txd = efx_tx_desc(tx_queue,
1381 old_write_count & tx_queue->ptr_mask);
1382 efx_ef10_push_tx_desc(tx_queue, txd);
1383 ++tx_queue->pushes;
1384 } else {
1385 efx_ef10_notify_tx_desc(tx_queue);
1386 }
1387}
1388
1389static int efx_ef10_alloc_rss_context(struct efx_nic *efx, u32 *context)
1390{
1391 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN);
1392 MCDI_DECLARE_BUF(outbuf, MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN);
1393 size_t outlen;
1394 int rc;
1395
1396 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID,
1397 EVB_PORT_ID_ASSIGNED);
1398 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_TYPE,
1399 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE);
1400 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_NUM_QUEUES,
1401 EFX_MAX_CHANNELS);
1402
1403 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_ALLOC, inbuf, sizeof(inbuf),
1404 outbuf, sizeof(outbuf), &outlen);
1405 if (rc != 0)
1406 return rc;
1407
1408 if (outlen < MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN)
1409 return -EIO;
1410
1411 *context = MCDI_DWORD(outbuf, RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID);
1412
1413 return 0;
1414}
1415
1416static void efx_ef10_free_rss_context(struct efx_nic *efx, u32 context)
1417{
1418 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_FREE_IN_LEN);
1419 int rc;
1420
1421 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID,
1422 context);
1423
1424 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_FREE, inbuf, sizeof(inbuf),
1425 NULL, 0, NULL);
1426 WARN_ON(rc != 0);
1427}
1428
1429static int efx_ef10_populate_rss_table(struct efx_nic *efx, u32 context)
1430{
1431 MCDI_DECLARE_BUF(tablebuf, MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN);
1432 MCDI_DECLARE_BUF(keybuf, MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN);
1433 int i, rc;
1434
1435 MCDI_SET_DWORD(tablebuf, RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID,
1436 context);
1437 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_indir_table) !=
1438 MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN);
1439
1440 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); ++i)
1441 MCDI_PTR(tablebuf,
1442 RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE)[i] =
1443 (u8) efx->rx_indir_table[i];
1444
1445 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_TABLE, tablebuf,
1446 sizeof(tablebuf), NULL, 0, NULL);
1447 if (rc != 0)
1448 return rc;
1449
1450 MCDI_SET_DWORD(keybuf, RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID,
1451 context);
1452 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_hash_key) !=
1453 MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN);
1454 for (i = 0; i < ARRAY_SIZE(efx->rx_hash_key); ++i)
1455 MCDI_PTR(keybuf, RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY)[i] =
1456 efx->rx_hash_key[i];
1457
1458 return efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_KEY, keybuf,
1459 sizeof(keybuf), NULL, 0, NULL);
1460}
1461
1462static void efx_ef10_rx_free_indir_table(struct efx_nic *efx)
1463{
1464 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1465
1466 if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID)
1467 efx_ef10_free_rss_context(efx, nic_data->rx_rss_context);
1468 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
1469}
1470
d43050c0 1471static void efx_ef10_rx_push_rss_config(struct efx_nic *efx)
8127d661
BH		 1472{
1473 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1474 int rc;
1475
d43050c0 1476 netif_dbg(efx, drv, efx->net_dev, "pushing RSS config\n");
8127d661
BH		 1477
1478 if (nic_data->rx_rss_context == EFX_EF10_RSS_CONTEXT_INVALID) {
1479 rc = efx_ef10_alloc_rss_context(efx, &nic_data->rx_rss_context);
1480 if (rc != 0)
1481 goto fail;
1482 }
1483
1484 rc = efx_ef10_populate_rss_table(efx, nic_data->rx_rss_context);
1485 if (rc != 0)
1486 goto fail;
1487
1488 return;
1489
1490fail:
1491 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
1492}
1493
1494static int efx_ef10_rx_probe(struct efx_rx_queue *rx_queue)
1495{
1496 return efx_nic_alloc_buffer(rx_queue->efx, &rx_queue->rxd.buf,
1497 (rx_queue->ptr_mask + 1) *
1498 sizeof(efx_qword_t),
1499 GFP_KERNEL);
1500}
1501
1502static void efx_ef10_rx_init(struct efx_rx_queue *rx_queue)
1503{
1504 MCDI_DECLARE_BUF(inbuf,
1505 MC_CMD_INIT_RXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
1506 EFX_BUF_SIZE));
1507 MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_RXQ_OUT_LEN);
1508 struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
1509 size_t entries = rx_queue->rxd.buf.len / EFX_BUF_SIZE;
1510 struct efx_nic *efx = rx_queue->efx;
1511 size_t inlen, outlen;
1512 dma_addr_t dma_addr;
1513 int rc;
1514 int i;
1515
1516 rx_queue->scatter_n = 0;
1517 rx_queue->scatter_len = 0;
1518
1519 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_SIZE, rx_queue->ptr_mask + 1);
1520 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_TARGET_EVQ, channel->channel);
1521 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_LABEL, efx_rx_queue_index(rx_queue));
1522 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_INSTANCE,
1523 efx_rx_queue_index(rx_queue));
bd9a265d
JC		 1524 MCDI_POPULATE_DWORD_2(inbuf, INIT_RXQ_IN_FLAGS,
1525 INIT_RXQ_IN_FLAG_PREFIX, 1,
1526 INIT_RXQ_IN_FLAG_TIMESTAMP, 1);
8127d661
BH		 1527 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_OWNER_ID, 0);
1528 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_PORT_ID, EVB_PORT_ID_ASSIGNED);
1529
1530 dma_addr = rx_queue->rxd.buf.dma_addr;
1531
1532 netif_dbg(efx, hw, efx->net_dev, "pushing RXQ %d. %zu entries (%llx)\n",
1533 efx_rx_queue_index(rx_queue), entries, (u64)dma_addr);
1534
1535 for (i = 0; i < entries; ++i) {
1536 MCDI_SET_ARRAY_QWORD(inbuf, INIT_RXQ_IN_DMA_ADDR, i, dma_addr);
1537 dma_addr += EFX_BUF_SIZE;
1538 }
1539
1540 inlen = MC_CMD_INIT_RXQ_IN_LEN(entries);
1541
1542 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_RXQ, inbuf, inlen,
1543 outbuf, sizeof(outbuf), &outlen);
48ce5634
BH		 1544 if (rc)
1545 netdev_WARN(efx->net_dev, "failed to initialise RXQ %d\n",
1546 efx_rx_queue_index(rx_queue));
8127d661
BH		 1547}
1548
1549static void efx_ef10_rx_fini(struct efx_rx_queue *rx_queue)
1550{
1551 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_RXQ_IN_LEN);
1552 MCDI_DECLARE_BUF(outbuf, MC_CMD_FINI_RXQ_OUT_LEN);
1553 struct efx_nic *efx = rx_queue->efx;
1554 size_t outlen;
1555 int rc;
1556
1557 MCDI_SET_DWORD(inbuf, FINI_RXQ_IN_INSTANCE,
1558 efx_rx_queue_index(rx_queue));
1559
1e0b8120 1560 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_RXQ, inbuf, sizeof(inbuf),
8127d661
BH		 1561 outbuf, sizeof(outbuf), &outlen);
1562
1563 if (rc && rc != -EALREADY)
1564 goto fail;
1565
1566 return;
1567
1568fail:
1e0b8120
EC		 1569 efx_mcdi_display_error(efx, MC_CMD_FINI_RXQ, MC_CMD_FINI_RXQ_IN_LEN,
1570 outbuf, outlen, rc);
8127d661
BH		 1571}
1572
1573static void efx_ef10_rx_remove(struct efx_rx_queue *rx_queue)
1574{
1575 efx_nic_free_buffer(rx_queue->efx, &rx_queue->rxd.buf);
1576}
1577
1578/* This creates an entry in the RX descriptor queue */
1579static inline void
1580efx_ef10_build_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index)
1581{
1582 struct efx_rx_buffer *rx_buf;
1583 efx_qword_t *rxd;
1584
1585 rxd = efx_rx_desc(rx_queue, index);
1586 rx_buf = efx_rx_buffer(rx_queue, index);
1587 EFX_POPULATE_QWORD_2(*rxd,
1588 ESF_DZ_RX_KER_BYTE_CNT, rx_buf->len,
1589 ESF_DZ_RX_KER_BUF_ADDR, rx_buf->dma_addr);
1590}
1591
1592static void efx_ef10_rx_write(struct efx_rx_queue *rx_queue)
1593{
1594 struct efx_nic *efx = rx_queue->efx;
1595 unsigned int write_count;
1596 efx_dword_t reg;
1597
1598 /* Firmware requires that RX_DESC_WPTR be a multiple of 8 */
1599 write_count = rx_queue->added_count & ~7;
1600 if (rx_queue->notified_count == write_count)
1601 return;
1602
1603 do
1604 efx_ef10_build_rx_desc(
1605 rx_queue,
1606 rx_queue->notified_count & rx_queue->ptr_mask);
1607 while (++rx_queue->notified_count != write_count);
1608
1609 wmb();
1610 EFX_POPULATE_DWORD_1(reg, ERF_DZ_RX_DESC_WPTR,
1611 write_count & rx_queue->ptr_mask);
1612 efx_writed_page(efx, &reg, ER_DZ_RX_DESC_UPD,
1613 efx_rx_queue_index(rx_queue));
1614}
1615
1616static efx_mcdi_async_completer efx_ef10_rx_defer_refill_complete;
1617
1618static void efx_ef10_rx_defer_refill(struct efx_rx_queue *rx_queue)
1619{
1620 struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
1621 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
1622 efx_qword_t event;
1623
1624 EFX_POPULATE_QWORD_2(event,
1625 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
1626 ESF_DZ_EV_DATA, EFX_EF10_REFILL);
1627
1628 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
1629
1630 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
1631 * already swapped the data to little-endian order.
1632 */
1633 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
1634 sizeof(efx_qword_t));
1635
1636 efx_mcdi_rpc_async(channel->efx, MC_CMD_DRIVER_EVENT,
1637 inbuf, sizeof(inbuf), 0,
1638 efx_ef10_rx_defer_refill_complete, 0);
1639}
1640
1641static void
1642efx_ef10_rx_defer_refill_complete(struct efx_nic *efx, unsigned long cookie,
1643 int rc, efx_dword_t *outbuf,
1644 size_t outlen_actual)
1645{
1646 /* nothing to do */
1647}
1648
1649static int efx_ef10_ev_probe(struct efx_channel *channel)
1650{
1651 return efx_nic_alloc_buffer(channel->efx, &channel->eventq.buf,
1652 (channel->eventq_mask + 1) *
1653 sizeof(efx_qword_t),
1654 GFP_KERNEL);
1655}
1656
1657static int efx_ef10_ev_init(struct efx_channel *channel)
1658{
1659 MCDI_DECLARE_BUF(inbuf,
1660 MC_CMD_INIT_EVQ_IN_LEN(EFX_MAX_EVQ_SIZE * 8 /
1661 EFX_BUF_SIZE));
1662 MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_EVQ_OUT_LEN);
1663 size_t entries = channel->eventq.buf.len / EFX_BUF_SIZE;
1664 struct efx_nic *efx = channel->efx;
1665 struct efx_ef10_nic_data *nic_data;
1666 bool supports_rx_merge;
1667 size_t inlen, outlen;
1668 dma_addr_t dma_addr;
1669 int rc;
1670 int i;
1671
1672 nic_data = efx->nic_data;
1673 supports_rx_merge =
1674 !!(nic_data->datapath_caps &
1675 1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN);
1676
1677 /* Fill event queue with all ones (i.e. empty events) */
1678 memset(channel->eventq.buf.addr, 0xff, channel->eventq.buf.len);
1679
1680 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_SIZE, channel->eventq_mask + 1);
1681 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_INSTANCE, channel->channel);
1682 /* INIT_EVQ expects index in vector table, not absolute */
1683 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_IRQ_NUM, channel->channel);
1684 MCDI_POPULATE_DWORD_4(inbuf, INIT_EVQ_IN_FLAGS,
1685 INIT_EVQ_IN_FLAG_INTERRUPTING, 1,
1686 INIT_EVQ_IN_FLAG_RX_MERGE, 1,
1687 INIT_EVQ_IN_FLAG_TX_MERGE, 1,
1688 INIT_EVQ_IN_FLAG_CUT_THRU, !supports_rx_merge);
1689 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_MODE,
1690 MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS);
1691 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_LOAD, 0);
1692 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_RELOAD, 0);
1693 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_MODE,
1694 MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS);
1695 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_THRSHLD, 0);
1696
1697 dma_addr = channel->eventq.buf.dma_addr;
1698 for (i = 0; i < entries; ++i) {
1699 MCDI_SET_ARRAY_QWORD(inbuf, INIT_EVQ_IN_DMA_ADDR, i, dma_addr);
1700 dma_addr += EFX_BUF_SIZE;
1701 }
1702
1703 inlen = MC_CMD_INIT_EVQ_IN_LEN(entries);
1704
1705 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_EVQ, inbuf, inlen,
1706 outbuf, sizeof(outbuf), &outlen);
8127d661 1707 /* IRQ return is ignored */
8127d661
BH		 1708 return rc;
1709}
1710
1711static void efx_ef10_ev_fini(struct efx_channel *channel)
1712{
1713 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_EVQ_IN_LEN);
1714 MCDI_DECLARE_BUF(outbuf, MC_CMD_FINI_EVQ_OUT_LEN);
1715 struct efx_nic *efx = channel->efx;
1716 size_t outlen;
1717 int rc;
1718
1719 MCDI_SET_DWORD(inbuf, FINI_EVQ_IN_INSTANCE, channel->channel);
1720
1e0b8120 1721 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_EVQ, inbuf, sizeof(inbuf),
8127d661
BH		 1722 outbuf, sizeof(outbuf), &outlen);
1723
1724 if (rc && rc != -EALREADY)
1725 goto fail;
1726
1727 return;
1728
1729fail:
1e0b8120
EC		 1730 efx_mcdi_display_error(efx, MC_CMD_FINI_EVQ, MC_CMD_FINI_EVQ_IN_LEN,
1731 outbuf, outlen, rc);
8127d661
BH		 1732}
1733
1734static void efx_ef10_ev_remove(struct efx_channel *channel)
1735{
1736 efx_nic_free_buffer(channel->efx, &channel->eventq.buf);
1737}
1738
1739static void efx_ef10_handle_rx_wrong_queue(struct efx_rx_queue *rx_queue,
1740 unsigned int rx_queue_label)
1741{
1742 struct efx_nic *efx = rx_queue->efx;
1743
1744 netif_info(efx, hw, efx->net_dev,
1745 "rx event arrived on queue %d labeled as queue %u\n",
1746 efx_rx_queue_index(rx_queue), rx_queue_label);
1747
1748 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
1749}
1750
1751static void
1752efx_ef10_handle_rx_bad_lbits(struct efx_rx_queue *rx_queue,
1753 unsigned int actual, unsigned int expected)
1754{
1755 unsigned int dropped = (actual - expected) & rx_queue->ptr_mask;
1756 struct efx_nic *efx = rx_queue->efx;
1757
1758 netif_info(efx, hw, efx->net_dev,
1759 "dropped %d events (index=%d expected=%d)\n",
1760 dropped, actual, expected);
1761
1762 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
1763}
1764
1765/* partially received RX was aborted. clean up. */
1766static void efx_ef10_handle_rx_abort(struct efx_rx_queue *rx_queue)
1767{
1768 unsigned int rx_desc_ptr;
1769
8127d661
BH		 1770 netif_dbg(rx_queue->efx, hw, rx_queue->efx->net_dev,
1771 "scattered RX aborted (dropping %u buffers)\n",
1772 rx_queue->scatter_n);
1773
1774 rx_desc_ptr = rx_queue->removed_count & rx_queue->ptr_mask;
1775
1776 efx_rx_packet(rx_queue, rx_desc_ptr, rx_queue->scatter_n,
1777 0, EFX_RX_PKT_DISCARD);
1778
1779 rx_queue->removed_count += rx_queue->scatter_n;
1780 rx_queue->scatter_n = 0;
1781 rx_queue->scatter_len = 0;
1782 ++efx_rx_queue_channel(rx_queue)->n_rx_nodesc_trunc;
1783}
1784
1785static int efx_ef10_handle_rx_event(struct efx_channel *channel,
1786 const efx_qword_t *event)
1787{
1788 unsigned int rx_bytes, next_ptr_lbits, rx_queue_label, rx_l4_class;
1789 unsigned int n_descs, n_packets, i;
1790 struct efx_nic *efx = channel->efx;
1791 struct efx_rx_queue *rx_queue;
1792 bool rx_cont;
1793 u16 flags = 0;
1794
1795 if (unlikely(ACCESS_ONCE(efx->reset_pending)))
1796 return 0;
1797
1798 /* Basic packet information */
1799 rx_bytes = EFX_QWORD_FIELD(*event, ESF_DZ_RX_BYTES);
1800 next_ptr_lbits = EFX_QWORD_FIELD(*event, ESF_DZ_RX_DSC_PTR_LBITS);
1801 rx_queue_label = EFX_QWORD_FIELD(*event, ESF_DZ_RX_QLABEL);
1802 rx_l4_class = EFX_QWORD_FIELD(*event, ESF_DZ_RX_L4_CLASS);
1803 rx_cont = EFX_QWORD_FIELD(*event, ESF_DZ_RX_CONT);
1804
48ce5634
BH		 1805 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_DROP_EVENT))
1806 netdev_WARN(efx->net_dev, "saw RX_DROP_EVENT: event="
1807 EFX_QWORD_FMT "\n",
1808 EFX_QWORD_VAL(*event));
8127d661
BH		 1809
1810 rx_queue = efx_channel_get_rx_queue(channel);
1811
1812 if (unlikely(rx_queue_label != efx_rx_queue_index(rx_queue)))
1813 efx_ef10_handle_rx_wrong_queue(rx_queue, rx_queue_label);
1814
1815 n_descs = ((next_ptr_lbits - rx_queue->removed_count) &
1816 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
1817
1818 if (n_descs != rx_queue->scatter_n + 1) {
92a04168
BH		 1819 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1820
8127d661
BH		 1821 /* detect rx abort */
1822 if (unlikely(n_descs == rx_queue->scatter_n)) {
48ce5634
BH		 1823 if (rx_queue->scatter_n == 0 || rx_bytes != 0)
1824 netdev_WARN(efx->net_dev,
1825 "invalid RX abort: scatter_n=%u event="
1826 EFX_QWORD_FMT "\n",
1827 rx_queue->scatter_n,
1828 EFX_QWORD_VAL(*event));
8127d661
BH		 1829 efx_ef10_handle_rx_abort(rx_queue);
1830 return 0;
1831 }
1832
92a04168
BH		 1833 /* Check that RX completion merging is valid, i.e.
1834 * the current firmware supports it and this is a
1835 * non-scattered packet.
1836 */
1837 if (!(nic_data->datapath_caps &
1838 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN)) ||
1839 rx_queue->scatter_n != 0 || rx_cont) {
8127d661
BH		 1840 efx_ef10_handle_rx_bad_lbits(
1841 rx_queue, next_ptr_lbits,
1842 (rx_queue->removed_count +
1843 rx_queue->scatter_n + 1) &
1844 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
1845 return 0;
1846 }
1847
1848 /* Merged completion for multiple non-scattered packets */
1849 rx_queue->scatter_n = 1;
1850 rx_queue->scatter_len = 0;
1851 n_packets = n_descs;
1852 ++channel->n_rx_merge_events;
1853 channel->n_rx_merge_packets += n_packets;
1854 flags |= EFX_RX_PKT_PREFIX_LEN;
1855 } else {
1856 ++rx_queue->scatter_n;
1857 rx_queue->scatter_len += rx_bytes;
1858 if (rx_cont)
1859 return 0;
1860 n_packets = 1;
1861 }
1862
1863 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_ECRC_ERR)))
1864 flags |= EFX_RX_PKT_DISCARD;
1865
1866 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_IPCKSUM_ERR))) {
1867 channel->n_rx_ip_hdr_chksum_err += n_packets;
1868 } else if (unlikely(EFX_QWORD_FIELD(*event,
1869 ESF_DZ_RX_TCPUDP_CKSUM_ERR))) {
1870 channel->n_rx_tcp_udp_chksum_err += n_packets;
1871 } else if (rx_l4_class == ESE_DZ_L4_CLASS_TCP ||
1872 rx_l4_class == ESE_DZ_L4_CLASS_UDP) {
1873 flags |= EFX_RX_PKT_CSUMMED;
1874 }
1875
1876 if (rx_l4_class == ESE_DZ_L4_CLASS_TCP)
1877 flags |= EFX_RX_PKT_TCP;
1878
1879 channel->irq_mod_score += 2 * n_packets;
1880
1881 /* Handle received packet(s) */
1882 for (i = 0; i < n_packets; i++) {
1883 efx_rx_packet(rx_queue,
1884 rx_queue->removed_count & rx_queue->ptr_mask,
1885 rx_queue->scatter_n, rx_queue->scatter_len,
1886 flags);
1887 rx_queue->removed_count += rx_queue->scatter_n;
1888 }
1889
1890 rx_queue->scatter_n = 0;
1891 rx_queue->scatter_len = 0;
1892
1893 return n_packets;
1894}
1895
1896static int
1897efx_ef10_handle_tx_event(struct efx_channel *channel, efx_qword_t *event)
1898{
1899 struct efx_nic *efx = channel->efx;
1900 struct efx_tx_queue *tx_queue;
1901 unsigned int tx_ev_desc_ptr;
1902 unsigned int tx_ev_q_label;
1903 int tx_descs = 0;
1904
1905 if (unlikely(ACCESS_ONCE(efx->reset_pending)))
1906 return 0;
1907
1908 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_TX_DROP_EVENT)))
1909 return 0;
1910
1911 /* Transmit completion */
1912 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, ESF_DZ_TX_DESCR_INDX);
1913 tx_ev_q_label = EFX_QWORD_FIELD(*event, ESF_DZ_TX_QLABEL);
1914 tx_queue = efx_channel_get_tx_queue(channel,
1915 tx_ev_q_label % EFX_TXQ_TYPES);
1916 tx_descs = ((tx_ev_desc_ptr + 1 - tx_queue->read_count) &
1917 tx_queue->ptr_mask);
1918 efx_xmit_done(tx_queue, tx_ev_desc_ptr & tx_queue->ptr_mask);
1919
1920 return tx_descs;
1921}
1922
1923static void
1924efx_ef10_handle_driver_event(struct efx_channel *channel, efx_qword_t *event)
1925{
1926 struct efx_nic *efx = channel->efx;
1927 int subcode;
1928
1929 subcode = EFX_QWORD_FIELD(*event, ESF_DZ_DRV_SUB_CODE);
1930
1931 switch (subcode) {
1932 case ESE_DZ_DRV_TIMER_EV:
1933 case ESE_DZ_DRV_WAKE_UP_EV:
1934 break;
1935 case ESE_DZ_DRV_START_UP_EV:
1936 /* event queue init complete. ok. */
1937 break;
1938 default:
1939 netif_err(efx, hw, efx->net_dev,
1940 "channel %d unknown driver event type %d"
1941 " (data " EFX_QWORD_FMT ")\n",
1942 channel->channel, subcode,
1943 EFX_QWORD_VAL(*event));
1944
1945 }
1946}
1947
1948static void efx_ef10_handle_driver_generated_event(struct efx_channel *channel,
1949 efx_qword_t *event)
1950{
1951 struct efx_nic *efx = channel->efx;
1952 u32 subcode;
1953
1954 subcode = EFX_QWORD_FIELD(*event, EFX_DWORD_0);
1955
1956 switch (subcode) {
1957 case EFX_EF10_TEST:
1958 channel->event_test_cpu = raw_smp_processor_id();
1959 break;
1960 case EFX_EF10_REFILL:
1961 /* The queue must be empty, so we won't receive any rx
1962 * events, so efx_process_channel() won't refill the
1963 * queue. Refill it here
1964 */
cce28794 1965 efx_fast_push_rx_descriptors(&channel->rx_queue, true);
8127d661
BH		 1966 break;
1967 default:
1968 netif_err(efx, hw, efx->net_dev,
1969 "channel %d unknown driver event type %u"
1970 " (data " EFX_QWORD_FMT ")\n",
1971 channel->channel, (unsigned) subcode,
1972 EFX_QWORD_VAL(*event));
1973 }
1974}
1975
1976static int efx_ef10_ev_process(struct efx_channel *channel, int quota)
1977{
1978 struct efx_nic *efx = channel->efx;
1979 efx_qword_t event, *p_event;
1980 unsigned int read_ptr;
1981 int ev_code;
1982 int tx_descs = 0;
1983 int spent = 0;
1984
75363a46
EB		 1985 if (quota <= 0)
1986 return spent;
1987
8127d661
BH		 1988 read_ptr = channel->eventq_read_ptr;
1989
1990 for (;;) {
1991 p_event = efx_event(channel, read_ptr);
1992 event = *p_event;
1993
1994 if (!efx_event_present(&event))
1995 break;
1996
1997 EFX_SET_QWORD(*p_event);
1998
1999 ++read_ptr;
2000
2001 ev_code = EFX_QWORD_FIELD(event, ESF_DZ_EV_CODE);
2002
2003 netif_vdbg(efx, drv, efx->net_dev,
2004 "processing event on %d " EFX_QWORD_FMT "\n",
2005 channel->channel, EFX_QWORD_VAL(event));
2006
2007 switch (ev_code) {
2008 case ESE_DZ_EV_CODE_MCDI_EV:
2009 efx_mcdi_process_event(channel, &event);
2010 break;
2011 case ESE_DZ_EV_CODE_RX_EV:
2012 spent += efx_ef10_handle_rx_event(channel, &event);
2013 if (spent >= quota) {
2014 /* XXX can we split a merged event to
2015 * avoid going over-quota?
2016 */
2017 spent = quota;
2018 goto out;
2019 }
2020 break;
2021 case ESE_DZ_EV_CODE_TX_EV:
2022 tx_descs += efx_ef10_handle_tx_event(channel, &event);
2023 if (tx_descs > efx->txq_entries) {
2024 spent = quota;
2025 goto out;
2026 } else if (++spent == quota) {
2027 goto out;
2028 }
2029 break;
2030 case ESE_DZ_EV_CODE_DRIVER_EV:
2031 efx_ef10_handle_driver_event(channel, &event);
2032 if (++spent == quota)
2033 goto out;
2034 break;
2035 case EFX_EF10_DRVGEN_EV:
2036 efx_ef10_handle_driver_generated_event(channel, &event);
2037 break;
2038 default:
2039 netif_err(efx, hw, efx->net_dev,
2040 "channel %d unknown event type %d"
2041 " (data " EFX_QWORD_FMT ")\n",
2042 channel->channel, ev_code,
2043 EFX_QWORD_VAL(event));
2044 }
2045 }
2046
2047out:
2048 channel->eventq_read_ptr = read_ptr;
2049 return spent;
2050}
2051
2052static void efx_ef10_ev_read_ack(struct efx_channel *channel)
2053{
2054 struct efx_nic *efx = channel->efx;
2055 efx_dword_t rptr;
2056
2057 if (EFX_EF10_WORKAROUND_35388(efx)) {
2058 BUILD_BUG_ON(EFX_MIN_EVQ_SIZE <
2059 (1 << ERF_DD_EVQ_IND_RPTR_WIDTH));
2060 BUILD_BUG_ON(EFX_MAX_EVQ_SIZE >
2061 (1 << 2 * ERF_DD_EVQ_IND_RPTR_WIDTH));
2062
2063 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
2064 EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH,
2065 ERF_DD_EVQ_IND_RPTR,
2066 (channel->eventq_read_ptr &
2067 channel->eventq_mask) >>
2068 ERF_DD_EVQ_IND_RPTR_WIDTH);
2069 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
2070 channel->channel);
2071 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
2072 EFE_DD_EVQ_IND_RPTR_FLAGS_LOW,
2073 ERF_DD_EVQ_IND_RPTR,
2074 channel->eventq_read_ptr &
2075 ((1 << ERF_DD_EVQ_IND_RPTR_WIDTH) - 1));
2076 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
2077 channel->channel);
2078 } else {
2079 EFX_POPULATE_DWORD_1(rptr, ERF_DZ_EVQ_RPTR,
2080 channel->eventq_read_ptr &
2081 channel->eventq_mask);
2082 efx_writed_page(efx, &rptr, ER_DZ_EVQ_RPTR, channel->channel);
2083 }
2084}
2085
2086static void efx_ef10_ev_test_generate(struct efx_channel *channel)
2087{
2088 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
2089 struct efx_nic *efx = channel->efx;
2090 efx_qword_t event;
2091 int rc;
2092
2093 EFX_POPULATE_QWORD_2(event,
2094 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
2095 ESF_DZ_EV_DATA, EFX_EF10_TEST);
2096
2097 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
2098
2099 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
2100 * already swapped the data to little-endian order.
2101 */
2102 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
2103 sizeof(efx_qword_t));
2104
2105 rc = efx_mcdi_rpc(efx, MC_CMD_DRIVER_EVENT, inbuf, sizeof(inbuf),
2106 NULL, 0, NULL);
2107 if (rc != 0)
2108 goto fail;
2109
2110 return;
2111
2112fail:
2113 WARN_ON(true);
2114 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
2115}
2116
2117void efx_ef10_handle_drain_event(struct efx_nic *efx)
2118{
2119 if (atomic_dec_and_test(&efx->active_queues))
2120 wake_up(&efx->flush_wq);
2121
2122 WARN_ON(atomic_read(&efx->active_queues) < 0);
2123}
2124
2125static int efx_ef10_fini_dmaq(struct efx_nic *efx)
2126{
2127 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2128 struct efx_channel *channel;
2129 struct efx_tx_queue *tx_queue;
2130 struct efx_rx_queue *rx_queue;
2131 int pending;
2132
2133 /* If the MC has just rebooted, the TX/RX queues will have already been
2134 * torn down, but efx->active_queues needs to be set to zero.
2135 */
2136 if (nic_data->must_realloc_vis) {
2137 atomic_set(&efx->active_queues, 0);
2138 return 0;
2139 }
2140
2141 /* Do not attempt to write to the NIC during EEH recovery */
2142 if (efx->state != STATE_RECOVERY) {
2143 efx_for_each_channel(channel, efx) {
2144 efx_for_each_channel_rx_queue(rx_queue, channel)
2145 efx_ef10_rx_fini(rx_queue);
2146 efx_for_each_channel_tx_queue(tx_queue, channel)
2147 efx_ef10_tx_fini(tx_queue);
2148 }
2149
2150 wait_event_timeout(efx->flush_wq,
2151 atomic_read(&efx->active_queues) == 0,
2152 msecs_to_jiffies(EFX_MAX_FLUSH_TIME));
2153 pending = atomic_read(&efx->active_queues);
2154 if (pending) {
2155 netif_err(efx, hw, efx->net_dev, "failed to flush %d queues\n",
2156 pending);
2157 return -ETIMEDOUT;
2158 }
2159 }
2160
2161 return 0;
2162}
2163
e283546c
EC		 2164static void efx_ef10_prepare_flr(struct efx_nic *efx)
2165{
2166 atomic_set(&efx->active_queues, 0);
2167}
2168
8127d661
BH		 2169static bool efx_ef10_filter_equal(const struct efx_filter_spec *left,
2170 const struct efx_filter_spec *right)
2171{
2172 if ((left->match_flags ^ right->match_flags) |
2173 ((left->flags ^ right->flags) &
2174 (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)))
2175 return false;
2176
2177 return memcmp(&left->outer_vid, &right->outer_vid,
2178 sizeof(struct efx_filter_spec) -
2179 offsetof(struct efx_filter_spec, outer_vid)) == 0;
2180}
2181
2182static unsigned int efx_ef10_filter_hash(const struct efx_filter_spec *spec)
2183{
2184 BUILD_BUG_ON(offsetof(struct efx_filter_spec, outer_vid) & 3);
2185 return jhash2((const u32 *)&spec->outer_vid,
2186 (sizeof(struct efx_filter_spec) -
2187 offsetof(struct efx_filter_spec, outer_vid)) / 4,
2188 0);
2189 /* XXX should we randomise the initval? */
2190}
2191
2192/* Decide whether a filter should be exclusive or else should allow
2193 * delivery to additional recipients. Currently we decide that
2194 * filters for specific local unicast MAC and IP addresses are
2195 * exclusive.
2196 */
2197static bool efx_ef10_filter_is_exclusive(const struct efx_filter_spec *spec)
2198{
2199 if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC &&
2200 !is_multicast_ether_addr(spec->loc_mac))
2201 return true;
2202
2203 if ((spec->match_flags &
2204 (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) ==
2205 (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) {
2206 if (spec->ether_type == htons(ETH_P_IP) &&
2207 !ipv4_is_multicast(spec->loc_host[0]))
2208 return true;
2209 if (spec->ether_type == htons(ETH_P_IPV6) &&
2210 ((const u8 *)spec->loc_host)[0] != 0xff)
2211 return true;
2212 }
2213
2214 return false;
2215}
2216
2217static struct efx_filter_spec *
2218efx_ef10_filter_entry_spec(const struct efx_ef10_filter_table *table,
2219 unsigned int filter_idx)
2220{
2221 return (struct efx_filter_spec *)(table->entry[filter_idx].spec &
2222 ~EFX_EF10_FILTER_FLAGS);
2223}
2224
2225static unsigned int
2226efx_ef10_filter_entry_flags(const struct efx_ef10_filter_table *table,
2227 unsigned int filter_idx)
2228{
2229 return table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAGS;
2230}
2231
2232static void
2233efx_ef10_filter_set_entry(struct efx_ef10_filter_table *table,
2234 unsigned int filter_idx,
2235 const struct efx_filter_spec *spec,
2236 unsigned int flags)
2237{
2238 table->entry[filter_idx].spec = (unsigned long)spec | flags;
2239}
2240
2241static void efx_ef10_filter_push_prep(struct efx_nic *efx,
2242 const struct efx_filter_spec *spec,
2243 efx_dword_t *inbuf, u64 handle,
2244 bool replacing)
2245{
2246 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2247
2248 memset(inbuf, 0, MC_CMD_FILTER_OP_IN_LEN);
2249
2250 if (replacing) {
2251 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
2252 MC_CMD_FILTER_OP_IN_OP_REPLACE);
2253 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, handle);
2254 } else {
2255 u32 match_fields = 0;
2256
2257 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
2258 efx_ef10_filter_is_exclusive(spec) ?
2259 MC_CMD_FILTER_OP_IN_OP_INSERT :
2260 MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE);
2261
2262 /* Convert match flags and values. Unlike almost
2263 * everything else in MCDI, these fields are in
2264 * network byte order.
2265 */
2266 if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC_IG)
2267 match_fields |=
2268 is_multicast_ether_addr(spec->loc_mac) ?
2269 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN :
2270 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN;
2271#define COPY_FIELD(gen_flag, gen_field, mcdi_field) \
2272 if (spec->match_flags & EFX_FILTER_MATCH_ ## gen_flag) { \
2273 match_fields |= \
2274 1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \
2275 mcdi_field ## _LBN; \
2276 BUILD_BUG_ON( \
2277 MC_CMD_FILTER_OP_IN_ ## mcdi_field ## _LEN < \
2278 sizeof(spec->gen_field)); \
2279 memcpy(MCDI_PTR(inbuf, FILTER_OP_IN_ ## mcdi_field), \
2280 &spec->gen_field, sizeof(spec->gen_field)); \
2281 }
2282 COPY_FIELD(REM_HOST, rem_host, SRC_IP);
2283 COPY_FIELD(LOC_HOST, loc_host, DST_IP);
2284 COPY_FIELD(REM_MAC, rem_mac, SRC_MAC);
2285 COPY_FIELD(REM_PORT, rem_port, SRC_PORT);
2286 COPY_FIELD(LOC_MAC, loc_mac, DST_MAC);
2287 COPY_FIELD(LOC_PORT, loc_port, DST_PORT);
2288 COPY_FIELD(ETHER_TYPE, ether_type, ETHER_TYPE);
2289 COPY_FIELD(INNER_VID, inner_vid, INNER_VLAN);
2290 COPY_FIELD(OUTER_VID, outer_vid, OUTER_VLAN);
2291 COPY_FIELD(IP_PROTO, ip_proto, IP_PROTO);
2292#undef COPY_FIELD
2293 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_MATCH_FIELDS,
2294 match_fields);
2295 }
2296
2297 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_PORT_ID, EVB_PORT_ID_ASSIGNED);
2298 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_DEST,
2299 spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ?
2300 MC_CMD_FILTER_OP_IN_RX_DEST_DROP :
2301 MC_CMD_FILTER_OP_IN_RX_DEST_HOST);
e3d36293 2302 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DOMAIN, 0);
8127d661
BH		 2303 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DEST,
2304 MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT);
a0bc3487
BH		 2305 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_QUEUE,
2306 spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ?
2307 0 : spec->dmaq_id);
8127d661
BH		 2308 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_MODE,
2309 (spec->flags & EFX_FILTER_FLAG_RX_RSS) ?
2310 MC_CMD_FILTER_OP_IN_RX_MODE_RSS :
2311 MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE);
2312 if (spec->flags & EFX_FILTER_FLAG_RX_RSS)
2313 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_CONTEXT,
2314 spec->rss_context !=
2315 EFX_FILTER_RSS_CONTEXT_DEFAULT ?
2316 spec->rss_context : nic_data->rx_rss_context);
2317}
2318
2319static int efx_ef10_filter_push(struct efx_nic *efx,
2320 const struct efx_filter_spec *spec,
2321 u64 *handle, bool replacing)
2322{
2323 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
2324 MCDI_DECLARE_BUF(outbuf, MC_CMD_FILTER_OP_OUT_LEN);
2325 int rc;
2326
2327 efx_ef10_filter_push_prep(efx, spec, inbuf, *handle, replacing);
2328 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
2329 outbuf, sizeof(outbuf), NULL);
2330 if (rc == 0)
2331 *handle = MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE);
065e64c4
BH		 2332 if (rc == -ENOSPC)
2333 rc = -EBUSY; /* to match efx_farch_filter_insert() */
8127d661
BH		 2334 return rc;
2335}
2336
2337static int efx_ef10_filter_rx_match_pri(struct efx_ef10_filter_table *table,
2338 enum efx_filter_match_flags match_flags)
2339{
2340 unsigned int match_pri;
2341
2342 for (match_pri = 0;
2343 match_pri < table->rx_match_count;
2344 match_pri++)
2345 if (table->rx_match_flags[match_pri] == match_flags)
2346 return match_pri;
2347
2348 return -EPROTONOSUPPORT;
2349}
2350
2351static s32 efx_ef10_filter_insert(struct efx_nic *efx,
2352 struct efx_filter_spec *spec,
2353 bool replace_equal)
2354{
2355 struct efx_ef10_filter_table *table = efx->filter_state;
2356 DECLARE_BITMAP(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
2357 struct efx_filter_spec *saved_spec;
2358 unsigned int match_pri, hash;
2359 unsigned int priv_flags;
2360 bool replacing = false;
2361 int ins_index = -1;
2362 DEFINE_WAIT(wait);
2363 bool is_mc_recip;
2364 s32 rc;
2365
2366 /* For now, only support RX filters */
2367 if ((spec->flags & (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)) !=
2368 EFX_FILTER_FLAG_RX)
2369 return -EINVAL;
2370
2371 rc = efx_ef10_filter_rx_match_pri(table, spec->match_flags);
2372 if (rc < 0)
2373 return rc;
2374 match_pri = rc;
2375
2376 hash = efx_ef10_filter_hash(spec);
2377 is_mc_recip = efx_filter_is_mc_recipient(spec);
2378 if (is_mc_recip)
2379 bitmap_zero(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
2380
2381 /* Find any existing filters with the same match tuple or
2382 * else a free slot to insert at. If any of them are busy,
2383 * we have to wait and retry.
2384 */
2385 for (;;) {
2386 unsigned int depth = 1;
2387 unsigned int i;
2388
2389 spin_lock_bh(&efx->filter_lock);
2390
2391 for (;;) {
2392 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
2393 saved_spec = efx_ef10_filter_entry_spec(table, i);
2394
2395 if (!saved_spec) {
2396 if (ins_index < 0)
2397 ins_index = i;
2398 } else if (efx_ef10_filter_equal(spec, saved_spec)) {
2399 if (table->entry[i].spec &
2400 EFX_EF10_FILTER_FLAG_BUSY)
2401 break;
2402 if (spec->priority < saved_spec->priority &&
7665d1ab 2403 spec->priority != EFX_FILTER_PRI_AUTO) {
8127d661
BH		 2404 rc = -EPERM;
2405 goto out_unlock;
2406 }
2407 if (!is_mc_recip) {
2408 /* This is the only one */
2409 if (spec->priority ==
2410 saved_spec->priority &&
2411 !replace_equal) {
2412 rc = -EEXIST;
2413 goto out_unlock;
2414 }
2415 ins_index = i;
2416 goto found;
2417 } else if (spec->priority >
2418 saved_spec->priority ||
2419 (spec->priority ==
2420 saved_spec->priority &&
2421 replace_equal)) {
2422 if (ins_index < 0)
2423 ins_index = i;
2424 else
2425 __set_bit(depth, mc_rem_map);
2426 }
2427 }
2428
2429 /* Once we reach the maximum search depth, use
2430 * the first suitable slot or return -EBUSY if
2431 * there was none
2432 */
2433 if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) {
2434 if (ins_index < 0) {
2435 rc = -EBUSY;
2436 goto out_unlock;
2437 }
2438 goto found;
2439 }
2440
2441 ++depth;
2442 }
2443
2444 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE);
2445 spin_unlock_bh(&efx->filter_lock);
2446 schedule();
2447 }
2448
2449found:
2450 /* Create a software table entry if necessary, and mark it
2451 * busy. We might yet fail to insert, but any attempt to
2452 * insert a conflicting filter while we're waiting for the
2453 * firmware must find the busy entry.
2454 */
2455 saved_spec = efx_ef10_filter_entry_spec(table, ins_index);
2456 if (saved_spec) {
7665d1ab
BH		 2457 if (spec->priority == EFX_FILTER_PRI_AUTO &&
2458 saved_spec->priority >= EFX_FILTER_PRI_AUTO) {
8127d661 2459 /* Just make sure it won't be removed */
7665d1ab
BH		 2460 if (saved_spec->priority > EFX_FILTER_PRI_AUTO)
2461 saved_spec->flags |= EFX_FILTER_FLAG_RX_OVER_AUTO;
8127d661 2462 table->entry[ins_index].spec &=
b59e6ef8 2463 ~EFX_EF10_FILTER_FLAG_AUTO_OLD;
8127d661
BH		 2464 rc = ins_index;
2465 goto out_unlock;
2466 }
2467 replacing = true;
2468 priv_flags = efx_ef10_filter_entry_flags(table, ins_index);
2469 } else {
2470 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC);
2471 if (!saved_spec) {
2472 rc = -ENOMEM;
2473 goto out_unlock;
2474 }
2475 *saved_spec = *spec;
2476 priv_flags = 0;
2477 }
2478 efx_ef10_filter_set_entry(table, ins_index, saved_spec,
2479 priv_flags | EFX_EF10_FILTER_FLAG_BUSY);
2480
2481 /* Mark lower-priority multicast recipients busy prior to removal */
2482 if (is_mc_recip) {
2483 unsigned int depth, i;
2484
2485 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
2486 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
2487 if (test_bit(depth, mc_rem_map))
2488 table->entry[i].spec |=
2489 EFX_EF10_FILTER_FLAG_BUSY;
2490 }
2491 }
2492
2493 spin_unlock_bh(&efx->filter_lock);
2494
2495 rc = efx_ef10_filter_push(efx, spec, &table->entry[ins_index].handle,
2496 replacing);
2497
2498 /* Finalise the software table entry */
2499 spin_lock_bh(&efx->filter_lock);
2500 if (rc == 0) {
2501 if (replacing) {
2502 /* Update the fields that may differ */
7665d1ab
BH		 2503 if (saved_spec->priority == EFX_FILTER_PRI_AUTO)
2504 saved_spec->flags |=
2505 EFX_FILTER_FLAG_RX_OVER_AUTO;
8127d661 2506 saved_spec->priority = spec->priority;
7665d1ab 2507 saved_spec->flags &= EFX_FILTER_FLAG_RX_OVER_AUTO;
8127d661
BH		 2508 saved_spec->flags |= spec->flags;
2509 saved_spec->rss_context = spec->rss_context;
2510 saved_spec->dmaq_id = spec->dmaq_id;
2511 }
2512 } else if (!replacing) {
2513 kfree(saved_spec);
2514 saved_spec = NULL;
2515 }
2516 efx_ef10_filter_set_entry(table, ins_index, saved_spec, priv_flags);
2517
2518 /* Remove and finalise entries for lower-priority multicast
2519 * recipients
2520 */
2521 if (is_mc_recip) {
2522 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
2523 unsigned int depth, i;
2524
2525 memset(inbuf, 0, sizeof(inbuf));
2526
2527 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
2528 if (!test_bit(depth, mc_rem_map))
2529 continue;
2530
2531 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
2532 saved_spec = efx_ef10_filter_entry_spec(table, i);
2533 priv_flags = efx_ef10_filter_entry_flags(table, i);
2534
2535 if (rc == 0) {
2536 spin_unlock_bh(&efx->filter_lock);
2537 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
2538 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
2539 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
2540 table->entry[i].handle);
2541 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP,
2542 inbuf, sizeof(inbuf),
2543 NULL, 0, NULL);
2544 spin_lock_bh(&efx->filter_lock);
2545 }
2546
2547 if (rc == 0) {
2548 kfree(saved_spec);
2549 saved_spec = NULL;
2550 priv_flags = 0;
2551 } else {
2552 priv_flags &= ~EFX_EF10_FILTER_FLAG_BUSY;
2553 }
2554 efx_ef10_filter_set_entry(table, i, saved_spec,
2555 priv_flags);
2556 }
2557 }
2558
2559 /* If successful, return the inserted filter ID */
2560 if (rc == 0)
2561 rc = match_pri * HUNT_FILTER_TBL_ROWS + ins_index;
2562
2563 wake_up_all(&table->waitq);
2564out_unlock:
2565 spin_unlock_bh(&efx->filter_lock);
2566 finish_wait(&table->waitq, &wait);
2567 return rc;
2568}
2569
9fd8095d 2570static void efx_ef10_filter_update_rx_scatter(struct efx_nic *efx)
8127d661
BH		 2571{
2572 /* no need to do anything here on EF10 */
2573}
2574
2575/* Remove a filter.
b59e6ef8
BH		 2576 * If !by_index, remove by ID
2577 * If by_index, remove by index
8127d661
BH		 2578 * Filter ID may come from userland and must be range-checked.
2579 */
2580static int efx_ef10_filter_remove_internal(struct efx_nic *efx,
fbd79120 2581 unsigned int priority_mask,
b59e6ef8 2582 u32 filter_id, bool by_index)
8127d661
BH		 2583{
2584 unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS;
2585 struct efx_ef10_filter_table *table = efx->filter_state;
2586 MCDI_DECLARE_BUF(inbuf,
2587 MC_CMD_FILTER_OP_IN_HANDLE_OFST +
2588 MC_CMD_FILTER_OP_IN_HANDLE_LEN);
2589 struct efx_filter_spec *spec;
2590 DEFINE_WAIT(wait);
2591 int rc;
2592
2593 /* Find the software table entry and mark it busy. Don't
2594 * remove it yet; any attempt to update while we're waiting
2595 * for the firmware must find the busy entry.
2596 */
2597 for (;;) {
2598 spin_lock_bh(&efx->filter_lock);
2599 if (!(table->entry[filter_idx].spec &
2600 EFX_EF10_FILTER_FLAG_BUSY))
2601 break;
2602 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE);
2603 spin_unlock_bh(&efx->filter_lock);
2604 schedule();
2605 }
7665d1ab 2606
8127d661 2607 spec = efx_ef10_filter_entry_spec(table, filter_idx);
7665d1ab 2608 if (!spec ||
b59e6ef8 2609 (!by_index &&
8127d661
BH		 2610 efx_ef10_filter_rx_match_pri(table, spec->match_flags) !=
2611 filter_id / HUNT_FILTER_TBL_ROWS)) {
2612 rc = -ENOENT;
2613 goto out_unlock;
2614 }
7665d1ab
BH		 2615
2616 if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO &&
fbd79120 2617 priority_mask == (1U << EFX_FILTER_PRI_AUTO)) {
7665d1ab
BH		 2618 /* Just remove flags */
2619 spec->flags &= ~EFX_FILTER_FLAG_RX_OVER_AUTO;
b59e6ef8 2620 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_AUTO_OLD;
7665d1ab
BH		 2621 rc = 0;
2622 goto out_unlock;
2623 }
2624
fbd79120 2625 if (!(priority_mask & (1U << spec->priority))) {
7665d1ab
BH		 2626 rc = -ENOENT;
2627 goto out_unlock;
2628 }
2629
8127d661
BH		 2630 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
2631 spin_unlock_bh(&efx->filter_lock);
2632
7665d1ab 2633 if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO) {
b59e6ef8 2634 /* Reset to an automatic filter */
8127d661
BH		 2635
2636 struct efx_filter_spec new_spec = *spec;
2637
7665d1ab 2638 new_spec.priority = EFX_FILTER_PRI_AUTO;
8127d661 2639 new_spec.flags = (EFX_FILTER_FLAG_RX |
7665d1ab 2640 EFX_FILTER_FLAG_RX_RSS);
8127d661
BH		 2641 new_spec.dmaq_id = 0;
2642 new_spec.rss_context = EFX_FILTER_RSS_CONTEXT_DEFAULT;
2643 rc = efx_ef10_filter_push(efx, &new_spec,
2644 &table->entry[filter_idx].handle,
2645 true);
2646
2647 spin_lock_bh(&efx->filter_lock);
2648 if (rc == 0)
2649 *spec = new_spec;
2650 } else {
2651 /* Really remove the filter */
2652
2653 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
2654 efx_ef10_filter_is_exclusive(spec) ?
2655 MC_CMD_FILTER_OP_IN_OP_REMOVE :
2656 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
2657 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
2658 table->entry[filter_idx].handle);
2659 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP,
2660 inbuf, sizeof(inbuf), NULL, 0, NULL);
2661
2662 spin_lock_bh(&efx->filter_lock);
2663 if (rc == 0) {
2664 kfree(spec);
2665 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
2666 }
2667 }
7665d1ab 2668
8127d661
BH		 2669 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY;
2670 wake_up_all(&table->waitq);
2671out_unlock:
2672 spin_unlock_bh(&efx->filter_lock);
2673 finish_wait(&table->waitq, &wait);
2674 return rc;
2675}
2676
2677static int efx_ef10_filter_remove_safe(struct efx_nic *efx,
2678 enum efx_filter_priority priority,
2679 u32 filter_id)
2680{
fbd79120
BH		 2681 return efx_ef10_filter_remove_internal(efx, 1U << priority,
2682 filter_id, false);
8127d661
BH		 2683}
2684
2685static int efx_ef10_filter_get_safe(struct efx_nic *efx,
2686 enum efx_filter_priority priority,
2687 u32 filter_id, struct efx_filter_spec *spec)
2688{
2689 unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS;
2690 struct efx_ef10_filter_table *table = efx->filter_state;
2691 const struct efx_filter_spec *saved_spec;
2692 int rc;
2693
2694 spin_lock_bh(&efx->filter_lock);
2695 saved_spec = efx_ef10_filter_entry_spec(table, filter_idx);
2696 if (saved_spec && saved_spec->priority == priority &&
2697 efx_ef10_filter_rx_match_pri(table, saved_spec->match_flags) ==
2698 filter_id / HUNT_FILTER_TBL_ROWS) {
2699 *spec = *saved_spec;
2700 rc = 0;
2701 } else {
2702 rc = -ENOENT;
2703 }
2704 spin_unlock_bh(&efx->filter_lock);
2705 return rc;
2706}
2707
fbd79120 2708static int efx_ef10_filter_clear_rx(struct efx_nic *efx,
8127d661
BH		 2709 enum efx_filter_priority priority)
2710{
fbd79120
BH		 2711 unsigned int priority_mask;
2712 unsigned int i;
2713 int rc;
2714
2715 priority_mask = (((1U << (priority + 1)) - 1) &
2716 ~(1U << EFX_FILTER_PRI_AUTO));
2717
2718 for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) {
2719 rc = efx_ef10_filter_remove_internal(efx, priority_mask,
2720 i, true);
2721 if (rc && rc != -ENOENT)
2722 return rc;
2723 }
2724
2725 return 0;
8127d661
BH		 2726}
2727
2728static u32 efx_ef10_filter_count_rx_used(struct efx_nic *efx,
2729 enum efx_filter_priority priority)
2730{
2731 struct efx_ef10_filter_table *table = efx->filter_state;
2732 unsigned int filter_idx;
2733 s32 count = 0;
2734
2735 spin_lock_bh(&efx->filter_lock);
2736 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
2737 if (table->entry[filter_idx].spec &&
2738 efx_ef10_filter_entry_spec(table, filter_idx)->priority ==
2739 priority)
2740 ++count;
2741 }
2742 spin_unlock_bh(&efx->filter_lock);
2743 return count;
2744}
2745
2746static u32 efx_ef10_filter_get_rx_id_limit(struct efx_nic *efx)
2747{
2748 struct efx_ef10_filter_table *table = efx->filter_state;
2749
2750 return table->rx_match_count * HUNT_FILTER_TBL_ROWS;
2751}
2752
2753static s32 efx_ef10_filter_get_rx_ids(struct efx_nic *efx,
2754 enum efx_filter_priority priority,
2755 u32 *buf, u32 size)
2756{
2757 struct efx_ef10_filter_table *table = efx->filter_state;
2758 struct efx_filter_spec *spec;
2759 unsigned int filter_idx;
2760 s32 count = 0;
2761
2762 spin_lock_bh(&efx->filter_lock);
2763 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
2764 spec = efx_ef10_filter_entry_spec(table, filter_idx);
2765 if (spec && spec->priority == priority) {
2766 if (count == size) {
2767 count = -EMSGSIZE;
2768 break;
2769 }
2770 buf[count++] = (efx_ef10_filter_rx_match_pri(
2771 table, spec->match_flags) *
2772 HUNT_FILTER_TBL_ROWS +
2773 filter_idx);
2774 }
2775 }
2776 spin_unlock_bh(&efx->filter_lock);
2777 return count;
2778}
2779
2780#ifdef CONFIG_RFS_ACCEL
2781
2782static efx_mcdi_async_completer efx_ef10_filter_rfs_insert_complete;
2783
2784static s32 efx_ef10_filter_rfs_insert(struct efx_nic *efx,
2785 struct efx_filter_spec *spec)
2786{
2787 struct efx_ef10_filter_table *table = efx->filter_state;
2788 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
2789 struct efx_filter_spec *saved_spec;
2790 unsigned int hash, i, depth = 1;
2791 bool replacing = false;
2792 int ins_index = -1;
2793 u64 cookie;
2794 s32 rc;
2795
2796 /* Must be an RX filter without RSS and not for a multicast
2797 * destination address (RFS only works for connected sockets).
2798 * These restrictions allow us to pass only a tiny amount of
2799 * data through to the completion function.
2800 */
2801 EFX_WARN_ON_PARANOID(spec->flags !=
2802 (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_RX_SCATTER));
2803 EFX_WARN_ON_PARANOID(spec->priority != EFX_FILTER_PRI_HINT);
2804 EFX_WARN_ON_PARANOID(efx_filter_is_mc_recipient(spec));
2805
2806 hash = efx_ef10_filter_hash(spec);
2807
2808 spin_lock_bh(&efx->filter_lock);
2809
2810 /* Find any existing filter with the same match tuple or else
2811 * a free slot to insert at. If an existing filter is busy,
2812 * we have to give up.
2813 */
2814 for (;;) {
2815 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
2816 saved_spec = efx_ef10_filter_entry_spec(table, i);
2817
2818 if (!saved_spec) {
2819 if (ins_index < 0)
2820 ins_index = i;
2821 } else if (efx_ef10_filter_equal(spec, saved_spec)) {
2822 if (table->entry[i].spec & EFX_EF10_FILTER_FLAG_BUSY) {
2823 rc = -EBUSY;
2824 goto fail_unlock;
2825 }
8127d661
BH		 2826 if (spec->priority < saved_spec->priority) {
2827 rc = -EPERM;
2828 goto fail_unlock;
2829 }
2830 ins_index = i;
2831 break;
2832 }
2833
2834 /* Once we reach the maximum search depth, use the
2835 * first suitable slot or return -EBUSY if there was
2836 * none
2837 */
2838 if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) {
2839 if (ins_index < 0) {
2840 rc = -EBUSY;
2841 goto fail_unlock;
2842 }
2843 break;
2844 }
2845
2846 ++depth;
2847 }
2848
2849 /* Create a software table entry if necessary, and mark it
2850 * busy. We might yet fail to insert, but any attempt to
2851 * insert a conflicting filter while we're waiting for the
2852 * firmware must find the busy entry.
2853 */
2854 saved_spec = efx_ef10_filter_entry_spec(table, ins_index);
2855 if (saved_spec) {
2856 replacing = true;
2857 } else {
2858 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC);
2859 if (!saved_spec) {
2860 rc = -ENOMEM;
2861 goto fail_unlock;
2862 }
2863 *saved_spec = *spec;
2864 }
2865 efx_ef10_filter_set_entry(table, ins_index, saved_spec,
2866 EFX_EF10_FILTER_FLAG_BUSY);
2867
2868 spin_unlock_bh(&efx->filter_lock);
2869
2870 /* Pack up the variables needed on completion */
2871 cookie = replacing << 31 | ins_index << 16 | spec->dmaq_id;
2872
2873 efx_ef10_filter_push_prep(efx, spec, inbuf,
2874 table->entry[ins_index].handle, replacing);
2875 efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
2876 MC_CMD_FILTER_OP_OUT_LEN,
2877 efx_ef10_filter_rfs_insert_complete, cookie);
2878
2879 return ins_index;
2880
2881fail_unlock:
2882 spin_unlock_bh(&efx->filter_lock);
2883 return rc;
2884}
2885
2886static void
2887efx_ef10_filter_rfs_insert_complete(struct efx_nic *efx, unsigned long cookie,
2888 int rc, efx_dword_t *outbuf,
2889 size_t outlen_actual)
2890{
2891 struct efx_ef10_filter_table *table = efx->filter_state;
2892 unsigned int ins_index, dmaq_id;
2893 struct efx_filter_spec *spec;
2894 bool replacing;
2895
2896 /* Unpack the cookie */
2897 replacing = cookie >> 31;
2898 ins_index = (cookie >> 16) & (HUNT_FILTER_TBL_ROWS - 1);
2899 dmaq_id = cookie & 0xffff;
2900
2901 spin_lock_bh(&efx->filter_lock);
2902 spec = efx_ef10_filter_entry_spec(table, ins_index);
2903 if (rc == 0) {
2904 table->entry[ins_index].handle =
2905 MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE);
2906 if (replacing)
2907 spec->dmaq_id = dmaq_id;
2908 } else if (!replacing) {
2909 kfree(spec);
2910 spec = NULL;
2911 }
2912 efx_ef10_filter_set_entry(table, ins_index, spec, 0);
2913 spin_unlock_bh(&efx->filter_lock);
2914
2915 wake_up_all(&table->waitq);
2916}
2917
2918static void
2919efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx,
2920 unsigned long filter_idx,
2921 int rc, efx_dword_t *outbuf,
2922 size_t outlen_actual);
2923
2924static bool efx_ef10_filter_rfs_expire_one(struct efx_nic *efx, u32 flow_id,
2925 unsigned int filter_idx)
2926{
2927 struct efx_ef10_filter_table *table = efx->filter_state;
2928 struct efx_filter_spec *spec =
2929 efx_ef10_filter_entry_spec(table, filter_idx);
2930 MCDI_DECLARE_BUF(inbuf,
2931 MC_CMD_FILTER_OP_IN_HANDLE_OFST +
2932 MC_CMD_FILTER_OP_IN_HANDLE_LEN);
2933
2934 if (!spec ||
2935 (table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAG_BUSY) ||
2936 spec->priority != EFX_FILTER_PRI_HINT ||
2937 !rps_may_expire_flow(efx->net_dev, spec->dmaq_id,
2938 flow_id, filter_idx))
2939 return false;
2940
2941 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
2942 MC_CMD_FILTER_OP_IN_OP_REMOVE);
2943 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
2944 table->entry[filter_idx].handle);
2945 if (efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf), 0,
2946 efx_ef10_filter_rfs_expire_complete, filter_idx))
2947 return false;
2948
2949 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
2950 return true;
2951}
2952
2953static void
2954efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx,
2955 unsigned long filter_idx,
2956 int rc, efx_dword_t *outbuf,
2957 size_t outlen_actual)
2958{
2959 struct efx_ef10_filter_table *table = efx->filter_state;
2960 struct efx_filter_spec *spec =
2961 efx_ef10_filter_entry_spec(table, filter_idx);
2962
2963 spin_lock_bh(&efx->filter_lock);
2964 if (rc == 0) {
2965 kfree(spec);
2966 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
2967 }
2968 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY;
2969 wake_up_all(&table->waitq);
2970 spin_unlock_bh(&efx->filter_lock);
2971}
2972
2973#endif /* CONFIG_RFS_ACCEL */
2974
2975static int efx_ef10_filter_match_flags_from_mcdi(u32 mcdi_flags)
2976{
2977 int match_flags = 0;
2978
2979#define MAP_FLAG(gen_flag, mcdi_field) { \
2980 u32 old_mcdi_flags = mcdi_flags; \
2981 mcdi_flags &= ~(1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \
2982 mcdi_field ## _LBN); \
2983 if (mcdi_flags != old_mcdi_flags) \
2984 match_flags |= EFX_FILTER_MATCH_ ## gen_flag; \
2985 }
2986 MAP_FLAG(LOC_MAC_IG, UNKNOWN_UCAST_DST);
2987 MAP_FLAG(LOC_MAC_IG, UNKNOWN_MCAST_DST);
2988 MAP_FLAG(REM_HOST, SRC_IP);
2989 MAP_FLAG(LOC_HOST, DST_IP);
2990 MAP_FLAG(REM_MAC, SRC_MAC);
2991 MAP_FLAG(REM_PORT, SRC_PORT);
2992 MAP_FLAG(LOC_MAC, DST_MAC);
2993 MAP_FLAG(LOC_PORT, DST_PORT);
2994 MAP_FLAG(ETHER_TYPE, ETHER_TYPE);
2995 MAP_FLAG(INNER_VID, INNER_VLAN);
2996 MAP_FLAG(OUTER_VID, OUTER_VLAN);
2997 MAP_FLAG(IP_PROTO, IP_PROTO);
2998#undef MAP_FLAG
2999
3000 /* Did we map them all? */
3001 if (mcdi_flags)
3002 return -EINVAL;
3003
3004 return match_flags;
3005}
3006
3007static int efx_ef10_filter_table_probe(struct efx_nic *efx)
3008{
3009 MCDI_DECLARE_BUF(inbuf, MC_CMD_GET_PARSER_DISP_INFO_IN_LEN);
3010 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX);
3011 unsigned int pd_match_pri, pd_match_count;
3012 struct efx_ef10_filter_table *table;
3013 size_t outlen;
3014 int rc;
3015
3016 table = kzalloc(sizeof(*table), GFP_KERNEL);
3017 if (!table)
3018 return -ENOMEM;
3019
3020 /* Find out which RX filter types are supported, and their priorities */
3021 MCDI_SET_DWORD(inbuf, GET_PARSER_DISP_INFO_IN_OP,
3022 MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES);
3023 rc = efx_mcdi_rpc(efx, MC_CMD_GET_PARSER_DISP_INFO,
3024 inbuf, sizeof(inbuf), outbuf, sizeof(outbuf),
3025 &outlen);
3026 if (rc)
3027 goto fail;
3028 pd_match_count = MCDI_VAR_ARRAY_LEN(
3029 outlen, GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES);
3030 table->rx_match_count = 0;
3031
3032 for (pd_match_pri = 0; pd_match_pri < pd_match_count; pd_match_pri++) {
3033 u32 mcdi_flags =
3034 MCDI_ARRAY_DWORD(
3035 outbuf,
3036 GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES,
3037 pd_match_pri);
3038 rc = efx_ef10_filter_match_flags_from_mcdi(mcdi_flags);
3039 if (rc < 0) {
3040 netif_dbg(efx, probe, efx->net_dev,
3041 "%s: fw flags %#x pri %u not supported in driver\n",
3042 __func__, mcdi_flags, pd_match_pri);
3043 } else {
3044 netif_dbg(efx, probe, efx->net_dev,
3045 "%s: fw flags %#x pri %u supported as driver flags %#x pri %u\n",
3046 __func__, mcdi_flags, pd_match_pri,
3047 rc, table->rx_match_count);
3048 table->rx_match_flags[table->rx_match_count++] = rc;
3049 }
3050 }
3051
3052 table->entry = vzalloc(HUNT_FILTER_TBL_ROWS * sizeof(*table->entry));
3053 if (!table->entry) {
3054 rc = -ENOMEM;
3055 goto fail;
3056 }
3057
3058 efx->filter_state = table;
3059 init_waitqueue_head(&table->waitq);
3060 return 0;
3061
3062fail:
3063 kfree(table);
3064 return rc;
3065}
3066
3067static void efx_ef10_filter_table_restore(struct efx_nic *efx)
3068{
3069 struct efx_ef10_filter_table *table = efx->filter_state;
3070 struct efx_ef10_nic_data *nic_data = efx->nic_data;
3071 struct efx_filter_spec *spec;
3072 unsigned int filter_idx;
3073 bool failed = false;
3074 int rc;
3075
3076 if (!nic_data->must_restore_filters)
3077 return;
3078
3079 spin_lock_bh(&efx->filter_lock);
3080
3081 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
3082 spec = efx_ef10_filter_entry_spec(table, filter_idx);
3083 if (!spec)
3084 continue;
3085
3086 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
3087 spin_unlock_bh(&efx->filter_lock);
3088
3089 rc = efx_ef10_filter_push(efx, spec,
3090 &table->entry[filter_idx].handle,
3091 false);
3092 if (rc)
3093 failed = true;
3094
3095 spin_lock_bh(&efx->filter_lock);
3096 if (rc) {
3097 kfree(spec);
3098 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
3099 } else {
3100 table->entry[filter_idx].spec &=
3101 ~EFX_EF10_FILTER_FLAG_BUSY;
3102 }
3103 }
3104
3105 spin_unlock_bh(&efx->filter_lock);
3106
3107 if (failed)
3108 netif_err(efx, hw, efx->net_dev,
3109 "unable to restore all filters\n");
3110 else
3111 nic_data->must_restore_filters = false;
3112}
3113
3114static void efx_ef10_filter_table_remove(struct efx_nic *efx)
3115{
3116 struct efx_ef10_filter_table *table = efx->filter_state;
3117 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
3118 struct efx_filter_spec *spec;
3119 unsigned int filter_idx;
3120 int rc;
3121
3122 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
3123 spec = efx_ef10_filter_entry_spec(table, filter_idx);
3124 if (!spec)
3125 continue;
3126
3127 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3128 efx_ef10_filter_is_exclusive(spec) ?
3129 MC_CMD_FILTER_OP_IN_OP_REMOVE :
3130 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
3131 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
3132 table->entry[filter_idx].handle);
3133 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
3134 NULL, 0, NULL);
48ce5634
BH		 3135 if (rc)
3136 netdev_WARN(efx->net_dev,
3137 "filter_idx=%#x handle=%#llx\n",
3138 filter_idx,
3139 table->entry[filter_idx].handle);
8127d661
BH		 3140 kfree(spec);
3141 }
3142
3143 vfree(table->entry);
3144 kfree(table);
3145}
3146
3147static void efx_ef10_filter_sync_rx_mode(struct efx_nic *efx)
3148{
3149 struct efx_ef10_filter_table *table = efx->filter_state;
3150 struct net_device *net_dev = efx->net_dev;
3151 struct efx_filter_spec spec;
3152 bool remove_failed = false;
3153 struct netdev_hw_addr *uc;
3154 struct netdev_hw_addr *mc;
3155 unsigned int filter_idx;
3156 int i, n, rc;
3157
3158 if (!efx_dev_registered(efx))
3159 return;
3160
3161 /* Mark old filters that may need to be removed */
3162 spin_lock_bh(&efx->filter_lock);
b59e6ef8 3163 n = table->dev_uc_count < 0 ? 1 : table->dev_uc_count;
8127d661 3164 for (i = 0; i < n; i++) {
b59e6ef8
BH		 3165 filter_idx = table->dev_uc_list[i].id % HUNT_FILTER_TBL_ROWS;
3166 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_AUTO_OLD;
8127d661 3167 }
b59e6ef8 3168 n = table->dev_mc_count < 0 ? 1 : table->dev_mc_count;
8127d661 3169 for (i = 0; i < n; i++) {
b59e6ef8
BH		 3170 filter_idx = table->dev_mc_list[i].id % HUNT_FILTER_TBL_ROWS;
3171 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_AUTO_OLD;
8127d661
BH		 3172 }
3173 spin_unlock_bh(&efx->filter_lock);
3174
3175 /* Copy/convert the address lists; add the primary station
3176 * address and broadcast address
3177 */
3178 netif_addr_lock_bh(net_dev);
3179 if (net_dev->flags & IFF_PROMISC ||
b59e6ef8
BH		 3180 netdev_uc_count(net_dev) >= EFX_EF10_FILTER_DEV_UC_MAX) {
3181 table->dev_uc_count = -1;
8127d661 3182 } else {
b59e6ef8 3183 table->dev_uc_count = 1 + netdev_uc_count(net_dev);
cd84ff4d 3184 ether_addr_copy(table->dev_uc_list[0].addr, net_dev->dev_addr);
8127d661
BH		 3185 i = 1;
3186 netdev_for_each_uc_addr(uc, net_dev) {
cd84ff4d 3187 ether_addr_copy(table->dev_uc_list[i].addr, uc->addr);
8127d661
BH		 3188 i++;
3189 }
3190 }
3191 if (net_dev->flags & (IFF_PROMISC | IFF_ALLMULTI) ||
b59e6ef8
BH		 3192 netdev_mc_count(net_dev) >= EFX_EF10_FILTER_DEV_MC_MAX) {
3193 table->dev_mc_count = -1;
8127d661 3194 } else {
b59e6ef8
BH		 3195 table->dev_mc_count = 1 + netdev_mc_count(net_dev);
3196 eth_broadcast_addr(table->dev_mc_list[0].addr);
8127d661
BH		 3197 i = 1;
3198 netdev_for_each_mc_addr(mc, net_dev) {
cd84ff4d 3199 ether_addr_copy(table->dev_mc_list[i].addr, mc->addr);
8127d661
BH		 3200 i++;
3201 }
3202 }
3203 netif_addr_unlock_bh(net_dev);
3204
3205 /* Insert/renew unicast filters */
b59e6ef8
BH		 3206 if (table->dev_uc_count >= 0) {
3207 for (i = 0; i < table->dev_uc_count; i++) {
7665d1ab
BH		 3208 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
3209 EFX_FILTER_FLAG_RX_RSS,
8127d661
BH		 3210 0);
3211 efx_filter_set_eth_local(&spec, EFX_FILTER_VID_UNSPEC,
b59e6ef8 3212 table->dev_uc_list[i].addr);
8127d661
BH		 3213 rc = efx_ef10_filter_insert(efx, &spec, true);
3214 if (rc < 0) {
3215 /* Fall back to unicast-promisc */
3216 while (i--)
3217 efx_ef10_filter_remove_safe(
7665d1ab 3218 efx, EFX_FILTER_PRI_AUTO,
b59e6ef8
BH		 3219 table->dev_uc_list[i].id);
3220 table->dev_uc_count = -1;
8127d661
BH		 3221 break;
3222 }
b59e6ef8 3223 table->dev_uc_list[i].id = rc;
8127d661
BH		 3224 }
3225 }
b59e6ef8 3226 if (table->dev_uc_count < 0) {
7665d1ab
BH		 3227 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
3228 EFX_FILTER_FLAG_RX_RSS,
8127d661
BH		 3229 0);
3230 efx_filter_set_uc_def(&spec);
3231 rc = efx_ef10_filter_insert(efx, &spec, true);
3232 if (rc < 0) {
3233 WARN_ON(1);
b59e6ef8 3234 table->dev_uc_count = 0;
8127d661 3235 } else {
b59e6ef8 3236 table->dev_uc_list[0].id = rc;
8127d661
BH		 3237 }
3238 }
3239
3240 /* Insert/renew multicast filters */
b59e6ef8
BH		 3241 if (table->dev_mc_count >= 0) {
3242 for (i = 0; i < table->dev_mc_count; i++) {
7665d1ab
BH		 3243 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
3244 EFX_FILTER_FLAG_RX_RSS,
8127d661
BH		 3245 0);
3246 efx_filter_set_eth_local(&spec, EFX_FILTER_VID_UNSPEC,
b59e6ef8 3247 table->dev_mc_list[i].addr);
8127d661
BH		 3248 rc = efx_ef10_filter_insert(efx, &spec, true);
3249 if (rc < 0) {
3250 /* Fall back to multicast-promisc */
3251 while (i--)
3252 efx_ef10_filter_remove_safe(
7665d1ab 3253 efx, EFX_FILTER_PRI_AUTO,
b59e6ef8
BH		 3254 table->dev_mc_list[i].id);
3255 table->dev_mc_count = -1;
8127d661
BH		 3256 break;
3257 }
b59e6ef8 3258 table->dev_mc_list[i].id = rc;
8127d661
BH		 3259 }
3260 }
b59e6ef8 3261 if (table->dev_mc_count < 0) {
7665d1ab
BH		 3262 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
3263 EFX_FILTER_FLAG_RX_RSS,
8127d661
BH		 3264 0);
3265 efx_filter_set_mc_def(&spec);
3266 rc = efx_ef10_filter_insert(efx, &spec, true);
3267 if (rc < 0) {
3268 WARN_ON(1);
b59e6ef8 3269 table->dev_mc_count = 0;
8127d661 3270 } else {
b59e6ef8 3271 table->dev_mc_list[0].id = rc;
8127d661
BH		 3272 }
3273 }
3274
3275 /* Remove filters that weren't renewed. Since nothing else
b59e6ef8 3276 * changes the AUTO_OLD flag or removes these filters, we
8127d661
BH		 3277 * don't need to hold the filter_lock while scanning for
3278 * these filters.
3279 */
3280 for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) {
3281 if (ACCESS_ONCE(table->entry[i].spec) &
b59e6ef8 3282 EFX_EF10_FILTER_FLAG_AUTO_OLD) {
7665d1ab 3283 if (efx_ef10_filter_remove_internal(
fbd79120
BH		 3284 efx, 1U << EFX_FILTER_PRI_AUTO,
3285 i, true) < 0)
8127d661
BH		 3286 remove_failed = true;
3287 }
3288 }
3289 WARN_ON(remove_failed);
3290}
3291
3292static int efx_ef10_mac_reconfigure(struct efx_nic *efx)
3293{
3294 efx_ef10_filter_sync_rx_mode(efx);
3295
3296 return efx_mcdi_set_mac(efx);
3297}
3298
74cd60a4
JC		 3299static int efx_ef10_start_bist(struct efx_nic *efx, u32 bist_type)
3300{
3301 MCDI_DECLARE_BUF(inbuf, MC_CMD_START_BIST_IN_LEN);
3302
3303 MCDI_SET_DWORD(inbuf, START_BIST_IN_TYPE, bist_type);
3304 return efx_mcdi_rpc(efx, MC_CMD_START_BIST, inbuf, sizeof(inbuf),
3305 NULL, 0, NULL);
3306}
3307
3308/* MC BISTs follow a different poll mechanism to phy BISTs.
3309 * The BIST is done in the poll handler on the MC, and the MCDI command
3310 * will block until the BIST is done.
3311 */
3312static int efx_ef10_poll_bist(struct efx_nic *efx)
3313{
3314 int rc;
3315 MCDI_DECLARE_BUF(outbuf, MC_CMD_POLL_BIST_OUT_LEN);
3316 size_t outlen;
3317 u32 result;
3318
3319 rc = efx_mcdi_rpc(efx, MC_CMD_POLL_BIST, NULL, 0,
3320 outbuf, sizeof(outbuf), &outlen);
3321 if (rc != 0)
3322 return rc;
3323
3324 if (outlen < MC_CMD_POLL_BIST_OUT_LEN)
3325 return -EIO;
3326
3327 result = MCDI_DWORD(outbuf, POLL_BIST_OUT_RESULT);
3328 switch (result) {
3329 case MC_CMD_POLL_BIST_PASSED:
3330 netif_dbg(efx, hw, efx->net_dev, "BIST passed.\n");
3331 return 0;
3332 case MC_CMD_POLL_BIST_TIMEOUT:
3333 netif_err(efx, hw, efx->net_dev, "BIST timed out\n");
3334 return -EIO;
3335 case MC_CMD_POLL_BIST_FAILED:
3336 netif_err(efx, hw, efx->net_dev, "BIST failed.\n");
3337 return -EIO;
3338 default:
3339 netif_err(efx, hw, efx->net_dev,
3340 "BIST returned unknown result %u", result);
3341 return -EIO;
3342 }
3343}
3344
3345static int efx_ef10_run_bist(struct efx_nic *efx, u32 bist_type)
3346{
3347 int rc;
3348
3349 netif_dbg(efx, drv, efx->net_dev, "starting BIST type %u\n", bist_type);
3350
3351 rc = efx_ef10_start_bist(efx, bist_type);
3352 if (rc != 0)
3353 return rc;
3354
3355 return efx_ef10_poll_bist(efx);
3356}
3357
3358static int
3359efx_ef10_test_chip(struct efx_nic *efx, struct efx_self_tests *tests)
3360{
3361 int rc, rc2;
3362
3363 efx_reset_down(efx, RESET_TYPE_WORLD);
3364
3365 rc = efx_mcdi_rpc(efx, MC_CMD_ENABLE_OFFLINE_BIST,
3366 NULL, 0, NULL, 0, NULL);
3367 if (rc != 0)
3368 goto out;
3369
3370 tests->memory = efx_ef10_run_bist(efx, MC_CMD_MC_MEM_BIST) ? -1 : 1;
3371 tests->registers = efx_ef10_run_bist(efx, MC_CMD_REG_BIST) ? -1 : 1;
3372
3373 rc = efx_mcdi_reset(efx, RESET_TYPE_WORLD);
3374
3375out:
3376 rc2 = efx_reset_up(efx, RESET_TYPE_WORLD, rc == 0);
3377 return rc ? rc : rc2;
3378}
3379
8127d661
BH		 3380#ifdef CONFIG_SFC_MTD
3381
3382struct efx_ef10_nvram_type_info {
3383 u16 type, type_mask;
3384 u8 port;
3385 const char *name;
3386};
3387
3388static const struct efx_ef10_nvram_type_info efx_ef10_nvram_types[] = {
3389 { NVRAM_PARTITION_TYPE_MC_FIRMWARE, 0, 0, "sfc_mcfw" },
3390 { NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 0, 0, "sfc_mcfw_backup" },
3391 { NVRAM_PARTITION_TYPE_EXPANSION_ROM, 0, 0, "sfc_exp_rom" },
3392 { NVRAM_PARTITION_TYPE_STATIC_CONFIG, 0, 0, "sfc_static_cfg" },
3393 { NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG, 0, 0, "sfc_dynamic_cfg" },
3394 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0, 0, 0, "sfc_exp_rom_cfg" },
3395 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1, 0, 1, "sfc_exp_rom_cfg" },
3396 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2, 0, 2, "sfc_exp_rom_cfg" },
3397 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3, 0, 3, "sfc_exp_rom_cfg" },
a84f3bf9 3398 { NVRAM_PARTITION_TYPE_LICENSE, 0, 0, "sfc_license" },
8127d661
BH		 3399 { NVRAM_PARTITION_TYPE_PHY_MIN, 0xff, 0, "sfc_phy_fw" },
3400};
3401
3402static int efx_ef10_mtd_probe_partition(struct efx_nic *efx,
3403 struct efx_mcdi_mtd_partition *part,
3404 unsigned int type)
3405{
3406 MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_METADATA_IN_LEN);
3407 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_METADATA_OUT_LENMAX);
3408 const struct efx_ef10_nvram_type_info *info;
3409 size_t size, erase_size, outlen;
3410 bool protected;
3411 int rc;
3412
3413 for (info = efx_ef10_nvram_types; ; info++) {
3414 if (info ==
3415 efx_ef10_nvram_types + ARRAY_SIZE(efx_ef10_nvram_types))
3416 return -ENODEV;
3417 if ((type & ~info->type_mask) == info->type)
3418 break;
3419 }
3420 if (info->port != efx_port_num(efx))
3421 return -ENODEV;
3422
3423 rc = efx_mcdi_nvram_info(efx, type, &size, &erase_size, &protected);
3424 if (rc)
3425 return rc;
3426 if (protected)
3427 return -ENODEV; /* hide it */
3428
3429 part->nvram_type = type;
3430
3431 MCDI_SET_DWORD(inbuf, NVRAM_METADATA_IN_TYPE, type);
3432 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_METADATA, inbuf, sizeof(inbuf),
3433 outbuf, sizeof(outbuf), &outlen);
3434 if (rc)
3435 return rc;
3436 if (outlen < MC_CMD_NVRAM_METADATA_OUT_LENMIN)
3437 return -EIO;
3438 if (MCDI_DWORD(outbuf, NVRAM_METADATA_OUT_FLAGS) &
3439 (1 << MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN))
3440 part->fw_subtype = MCDI_DWORD(outbuf,
3441 NVRAM_METADATA_OUT_SUBTYPE);
3442
3443 part->common.dev_type_name = "EF10 NVRAM manager";
3444 part->common.type_name = info->name;
3445
3446 part->common.mtd.type = MTD_NORFLASH;
3447 part->common.mtd.flags = MTD_CAP_NORFLASH;
3448 part->common.mtd.size = size;
3449 part->common.mtd.erasesize = erase_size;
3450
3451 return 0;
3452}
3453
3454static int efx_ef10_mtd_probe(struct efx_nic *efx)
3455{
3456 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX);
3457 struct efx_mcdi_mtd_partition *parts;
3458 size_t outlen, n_parts_total, i, n_parts;
3459 unsigned int type;
3460 int rc;
3461
3462 ASSERT_RTNL();
3463
3464 BUILD_BUG_ON(MC_CMD_NVRAM_PARTITIONS_IN_LEN != 0);
3465 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_PARTITIONS, NULL, 0,
3466 outbuf, sizeof(outbuf), &outlen);
3467 if (rc)
3468 return rc;
3469 if (outlen < MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN)
3470 return -EIO;
3471
3472 n_parts_total = MCDI_DWORD(outbuf, NVRAM_PARTITIONS_OUT_NUM_PARTITIONS);
3473 if (n_parts_total >
3474 MCDI_VAR_ARRAY_LEN(outlen, NVRAM_PARTITIONS_OUT_TYPE_ID))
3475 return -EIO;
3476
3477 parts = kcalloc(n_parts_total, sizeof(*parts), GFP_KERNEL);
3478 if (!parts)
3479 return -ENOMEM;
3480
3481 n_parts = 0;
3482 for (i = 0; i < n_parts_total; i++) {
3483 type = MCDI_ARRAY_DWORD(outbuf, NVRAM_PARTITIONS_OUT_TYPE_ID,
3484 i);
3485 rc = efx_ef10_mtd_probe_partition(efx, &parts[n_parts], type);
3486 if (rc == 0)
3487 n_parts++;
3488 else if (rc != -ENODEV)
3489 goto fail;
3490 }
3491
3492 rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts));
3493fail:
3494 if (rc)
3495 kfree(parts);
3496 return rc;
3497}
3498
3499#endif /* CONFIG_SFC_MTD */
3500
3501static void efx_ef10_ptp_write_host_time(struct efx_nic *efx, u32 host_time)
3502{
3503 _efx_writed(efx, cpu_to_le32(host_time), ER_DZ_MC_DB_LWRD);
3504}
3505
bd9a265d
JC		 3506static int efx_ef10_rx_enable_timestamping(struct efx_channel *channel,
3507 bool temp)
3508{
3509 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN);
3510 int rc;
3511
3512 if (channel->sync_events_state == SYNC_EVENTS_REQUESTED ||
3513 channel->sync_events_state == SYNC_EVENTS_VALID ||
3514 (temp && channel->sync_events_state == SYNC_EVENTS_DISABLED))
3515 return 0;
3516 channel->sync_events_state = SYNC_EVENTS_REQUESTED;
3517
3518 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE);
3519 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
3520 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE,
3521 channel->channel);
3522
3523 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
3524 inbuf, sizeof(inbuf), NULL, 0, NULL);
3525
3526 if (rc != 0)
3527 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
3528 SYNC_EVENTS_DISABLED;
3529
3530 return rc;
3531}
3532
3533static int efx_ef10_rx_disable_timestamping(struct efx_channel *channel,
3534 bool temp)
3535{
3536 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN);
3537 int rc;
3538
3539 if (channel->sync_events_state == SYNC_EVENTS_DISABLED ||
3540 (temp && channel->sync_events_state == SYNC_EVENTS_QUIESCENT))
3541 return 0;
3542 if (channel->sync_events_state == SYNC_EVENTS_QUIESCENT) {
3543 channel->sync_events_state = SYNC_EVENTS_DISABLED;
3544 return 0;
3545 }
3546 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
3547 SYNC_EVENTS_DISABLED;
3548
3549 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE);
3550 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
3551 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL,
3552 MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE);
3553 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE,
3554 channel->channel);
3555
3556 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
3557 inbuf, sizeof(inbuf), NULL, 0, NULL);
3558
3559 return rc;
3560}
3561
3562static int efx_ef10_ptp_set_ts_sync_events(struct efx_nic *efx, bool en,
3563 bool temp)
3564{
3565 int (*set)(struct efx_channel *channel, bool temp);
3566 struct efx_channel *channel;
3567
3568 set = en ?
3569 efx_ef10_rx_enable_timestamping :
3570 efx_ef10_rx_disable_timestamping;
3571
3572 efx_for_each_channel(channel, efx) {
3573 int rc = set(channel, temp);
3574 if (en && rc != 0) {
3575 efx_ef10_ptp_set_ts_sync_events(efx, false, temp);
3576 return rc;
3577 }
3578 }
3579
3580 return 0;
3581}
3582
3583static int efx_ef10_ptp_set_ts_config(struct efx_nic *efx,
3584 struct hwtstamp_config *init)
3585{
3586 int rc;
3587
3588 switch (init->rx_filter) {
3589 case HWTSTAMP_FILTER_NONE:
3590 efx_ef10_ptp_set_ts_sync_events(efx, false, false);
3591 /* if TX timestamping is still requested then leave PTP on */
3592 return efx_ptp_change_mode(efx,
3593 init->tx_type != HWTSTAMP_TX_OFF, 0);
3594 case HWTSTAMP_FILTER_ALL:
3595 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
3596 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
3597 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
3598 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3599 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3600 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3601 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3602 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3603 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3604 case HWTSTAMP_FILTER_PTP_V2_EVENT:
3605 case HWTSTAMP_FILTER_PTP_V2_SYNC:
3606 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3607 init->rx_filter = HWTSTAMP_FILTER_ALL;
3608 rc = efx_ptp_change_mode(efx, true, 0);
3609 if (!rc)
3610 rc = efx_ef10_ptp_set_ts_sync_events(efx, true, false);
3611 if (rc)
3612 efx_ptp_change_mode(efx, false, 0);
3613 return rc;
3614 default:
3615 return -ERANGE;
3616 }
3617}
3618
8127d661
BH		 3619const struct efx_nic_type efx_hunt_a0_nic_type = {
3620 .mem_map_size = efx_ef10_mem_map_size,
3621 .probe = efx_ef10_probe,
3622 .remove = efx_ef10_remove,
3623 .dimension_resources = efx_ef10_dimension_resources,
3624 .init = efx_ef10_init_nic,
3625 .fini = efx_port_dummy_op_void,
3626 .map_reset_reason = efx_mcdi_map_reset_reason,
3627 .map_reset_flags = efx_ef10_map_reset_flags,
3e336261 3628 .reset = efx_ef10_reset,
8127d661
BH		 3629 .probe_port = efx_mcdi_port_probe,
3630 .remove_port = efx_mcdi_port_remove,
3631 .fini_dmaq = efx_ef10_fini_dmaq,
e283546c
EC		 3632 .prepare_flr = efx_ef10_prepare_flr,
3633 .finish_flr = efx_port_dummy_op_void,
8127d661
BH		 3634 .describe_stats = efx_ef10_describe_stats,
3635 .update_stats = efx_ef10_update_stats,
3636 .start_stats = efx_mcdi_mac_start_stats,
f8f3b5ae 3637 .pull_stats = efx_mcdi_mac_pull_stats,
8127d661
BH		 3638 .stop_stats = efx_mcdi_mac_stop_stats,
3639 .set_id_led = efx_mcdi_set_id_led,
3640 .push_irq_moderation = efx_ef10_push_irq_moderation,
3641 .reconfigure_mac = efx_ef10_mac_reconfigure,
3642 .check_mac_fault = efx_mcdi_mac_check_fault,
3643 .reconfigure_port = efx_mcdi_port_reconfigure,
3644 .get_wol = efx_ef10_get_wol,
3645 .set_wol = efx_ef10_set_wol,
3646 .resume_wol = efx_port_dummy_op_void,
74cd60a4 3647 .test_chip = efx_ef10_test_chip,
8127d661
BH		 3648 .test_nvram = efx_mcdi_nvram_test_all,
3649 .mcdi_request = efx_ef10_mcdi_request,
3650 .mcdi_poll_response = efx_ef10_mcdi_poll_response,
3651 .mcdi_read_response = efx_ef10_mcdi_read_response,
3652 .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot,
3653 .irq_enable_master = efx_port_dummy_op_void,
3654 .irq_test_generate = efx_ef10_irq_test_generate,
3655 .irq_disable_non_ev = efx_port_dummy_op_void,
3656 .irq_handle_msi = efx_ef10_msi_interrupt,
3657 .irq_handle_legacy = efx_ef10_legacy_interrupt,
3658 .tx_probe = efx_ef10_tx_probe,
3659 .tx_init = efx_ef10_tx_init,
3660 .tx_remove = efx_ef10_tx_remove,
3661 .tx_write = efx_ef10_tx_write,
d43050c0 3662 .rx_push_rss_config = efx_ef10_rx_push_rss_config,
8127d661
BH		 3663 .rx_probe = efx_ef10_rx_probe,
3664 .rx_init = efx_ef10_rx_init,
3665 .rx_remove = efx_ef10_rx_remove,
3666 .rx_write = efx_ef10_rx_write,
3667 .rx_defer_refill = efx_ef10_rx_defer_refill,
3668 .ev_probe = efx_ef10_ev_probe,
3669 .ev_init = efx_ef10_ev_init,
3670 .ev_fini = efx_ef10_ev_fini,
3671 .ev_remove = efx_ef10_ev_remove,
3672 .ev_process = efx_ef10_ev_process,
3673 .ev_read_ack = efx_ef10_ev_read_ack,
3674 .ev_test_generate = efx_ef10_ev_test_generate,
3675 .filter_table_probe = efx_ef10_filter_table_probe,
3676 .filter_table_restore = efx_ef10_filter_table_restore,
3677 .filter_table_remove = efx_ef10_filter_table_remove,
3678 .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter,
3679 .filter_insert = efx_ef10_filter_insert,
3680 .filter_remove_safe = efx_ef10_filter_remove_safe,
3681 .filter_get_safe = efx_ef10_filter_get_safe,
3682 .filter_clear_rx = efx_ef10_filter_clear_rx,
3683 .filter_count_rx_used = efx_ef10_filter_count_rx_used,
3684 .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit,
3685 .filter_get_rx_ids = efx_ef10_filter_get_rx_ids,
3686#ifdef CONFIG_RFS_ACCEL
3687 .filter_rfs_insert = efx_ef10_filter_rfs_insert,
3688 .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one,
3689#endif
3690#ifdef CONFIG_SFC_MTD
3691 .mtd_probe = efx_ef10_mtd_probe,
3692 .mtd_rename = efx_mcdi_mtd_rename,
3693 .mtd_read = efx_mcdi_mtd_read,
3694 .mtd_erase = efx_mcdi_mtd_erase,
3695 .mtd_write = efx_mcdi_mtd_write,
3696 .mtd_sync = efx_mcdi_mtd_sync,
3697#endif
3698 .ptp_write_host_time = efx_ef10_ptp_write_host_time,
bd9a265d
JC		 3699 .ptp_set_ts_sync_events = efx_ef10_ptp_set_ts_sync_events,
3700 .ptp_set_ts_config = efx_ef10_ptp_set_ts_config,
7fa8d547 3701#ifdef CONFIG_SFC_SRIOV
834e23dd 3702 .sriov_configure = efx_ef10_sriov_configure,
d98a4ffe
SS		 3703 .sriov_init = efx_ef10_sriov_init,
3704 .sriov_fini = efx_ef10_sriov_fini,
3705 .sriov_mac_address_changed = efx_ef10_sriov_mac_address_changed,
3706 .sriov_wanted = efx_ef10_sriov_wanted,
3707 .sriov_reset = efx_ef10_sriov_reset,
7fa8d547
SS		 3708 .sriov_flr = efx_ef10_sriov_flr,
3709 .sriov_set_vf_mac = efx_ef10_sriov_set_vf_mac,
3710 .sriov_set_vf_vlan = efx_ef10_sriov_set_vf_vlan,
3711 .sriov_set_vf_spoofchk = efx_ef10_sriov_set_vf_spoofchk,
3712 .sriov_get_vf_config = efx_ef10_sriov_get_vf_config,
3713#endif
8127d661
BH		 3714
3715 .revision = EFX_REV_HUNT_A0,
3716 .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH),
3717 .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE,
3718 .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST,
bd9a265d 3719 .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST,
8127d661
BH		 3720 .can_rx_scatter = true,
3721 .always_rx_scatter = true,
3722 .max_interrupt_mode = EFX_INT_MODE_MSIX,
3723 .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH,
3724 .offload_features = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
3725 NETIF_F_RXHASH | NETIF_F_NTUPLE),
3726 .mcdi_max_ver = 2,
3727 .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS,
bd9a265d
JC		 3728 .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE |
3729 1 << HWTSTAMP_FILTER_ALL,
8127d661 3730};
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