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sfc: support variable number of MAC stats
[mirror_ubuntu-focal-kernel.git] / drivers / net / ethernet / sfc / ef10.c
CommitLineData
8127d661
BH		 1/****************************************************************************
2 * Driver for Solarflare network controllers and boards
3 * Copyright 2012-2013 Solarflare Communications Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published
7 * by the Free Software Foundation, incorporated herein by reference.
8 */
9
10#include "net_driver.h"
11#include "ef10_regs.h"
12#include "io.h"
13#include "mcdi.h"
14#include "mcdi_pcol.h"
15#include "nic.h"
16#include "workarounds.h"
74cd60a4 17#include "selftest.h"
7fa8d547 18#include "ef10_sriov.h"
8127d661
BH		 19#include <linux/in.h>
20#include <linux/jhash.h>
21#include <linux/wait.h>
22#include <linux/workqueue.h>
23
24/* Hardware control for EF10 architecture including 'Huntington'. */
25
26#define EFX_EF10_DRVGEN_EV 7
27enum {
28 EFX_EF10_TEST = 1,
29 EFX_EF10_REFILL,
30};
31
32/* The reserved RSS context value */
33#define EFX_EF10_RSS_CONTEXT_INVALID 0xffffffff
267c0157
JC		 34/* The maximum size of a shared RSS context */
35/* TODO: this should really be from the mcdi protocol export */
36#define EFX_EF10_MAX_SHARED_RSS_CONTEXT_SIZE 64UL
8127d661
BH		 37
38/* The filter table(s) are managed by firmware and we have write-only
39 * access. When removing filters we must identify them to the
40 * firmware by a 64-bit handle, but this is too wide for Linux kernel
41 * interfaces (32-bit for RX NFC, 16-bit for RFS). Also, we need to
42 * be able to tell in advance whether a requested insertion will
43 * replace an existing filter. Therefore we maintain a software hash
44 * table, which should be at least as large as the hardware hash
45 * table.
46 *
47 * Huntington has a single 8K filter table shared between all filter
48 * types and both ports.
49 */
50#define HUNT_FILTER_TBL_ROWS 8192
51
12fb0da4 52#define EFX_EF10_FILTER_ID_INVALID 0xffff
dc3273e0
AR		 53
54#define EFX_EF10_FILTER_DEV_UC_MAX 32
55#define EFX_EF10_FILTER_DEV_MC_MAX 256
56
34813fe2
AR		 57/* VLAN list entry */
58struct efx_ef10_vlan {
59 struct list_head list;
60 u16 vid;
61};
62
9b410801
EC		 63enum efx_ef10_default_filters {
64 EFX_EF10_BCAST,
65 EFX_EF10_UCDEF,
66 EFX_EF10_MCDEF,
67 EFX_EF10_VXLAN4_UCDEF,
68 EFX_EF10_VXLAN4_MCDEF,
69 EFX_EF10_VXLAN6_UCDEF,
70 EFX_EF10_VXLAN6_MCDEF,
71 EFX_EF10_NVGRE4_UCDEF,
72 EFX_EF10_NVGRE4_MCDEF,
73 EFX_EF10_NVGRE6_UCDEF,
74 EFX_EF10_NVGRE6_MCDEF,
75 EFX_EF10_GENEVE4_UCDEF,
76 EFX_EF10_GENEVE4_MCDEF,
77 EFX_EF10_GENEVE6_UCDEF,
78 EFX_EF10_GENEVE6_MCDEF,
79
80 EFX_EF10_NUM_DEFAULT_FILTERS
81};
82
dc3273e0
AR		 83/* Per-VLAN filters information */
84struct efx_ef10_filter_vlan {
34813fe2 85 struct list_head list;
b3a3c03c 86 u16 vid;
dc3273e0
AR		 87 u16 uc[EFX_EF10_FILTER_DEV_UC_MAX];
88 u16 mc[EFX_EF10_FILTER_DEV_MC_MAX];
9b410801 89 u16 default_filters[EFX_EF10_NUM_DEFAULT_FILTERS];
dc3273e0
AR		 90};
91
822b96f8
DP		 92struct efx_ef10_dev_addr {
93 u8 addr[ETH_ALEN];
822b96f8
DP		 94};
95
8127d661 96struct efx_ef10_filter_table {
7ac0dd9d
AR		 97/* The MCDI match masks supported by this fw & hw, in order of priority */
98 u32 rx_match_mcdi_flags[
9b410801 99 MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM * 2];
8127d661
BH		 100 unsigned int rx_match_count;
101
102 struct {
103 unsigned long spec; /* pointer to spec plus flag bits */
b59e6ef8
BH		 104/* BUSY flag indicates that an update is in progress. AUTO_OLD is
105 * used to mark and sweep MAC filters for the device address lists.
8127d661
BH		 106 */
107#define EFX_EF10_FILTER_FLAG_BUSY 1UL
b59e6ef8 108#define EFX_EF10_FILTER_FLAG_AUTO_OLD 2UL
8127d661
BH		 109#define EFX_EF10_FILTER_FLAGS 3UL
110 u64 handle; /* firmware handle */
111 } *entry;
112 wait_queue_head_t waitq;
113/* Shadow of net_device address lists, guarded by mac_lock */
822b96f8
DP		 114 struct efx_ef10_dev_addr dev_uc_list[EFX_EF10_FILTER_DEV_UC_MAX];
115 struct efx_ef10_dev_addr dev_mc_list[EFX_EF10_FILTER_DEV_MC_MAX];
12fb0da4
EC		 116 int dev_uc_count;
117 int dev_mc_count;
afa4ce12
AR		 118 bool uc_promisc;
119 bool mc_promisc;
b071c3a2
AR		 120/* Whether in multicast promiscuous mode when last changed */
121 bool mc_promisc_last;
148cbab6 122 bool mc_overflow; /* Too many MC addrs; should always imply mc_promisc */
4a53ea8a 123 bool vlan_filter;
34813fe2 124 struct list_head vlan_list;
8127d661
BH		 125};
126
127/* An arbitrary search limit for the software hash table */
128#define EFX_EF10_FILTER_SEARCH_LIMIT 200
129
8127d661
BH		 130static void efx_ef10_rx_free_indir_table(struct efx_nic *efx);
131static void efx_ef10_filter_table_remove(struct efx_nic *efx);
34813fe2
AR		 132static int efx_ef10_filter_add_vlan(struct efx_nic *efx, u16 vid);
133static void efx_ef10_filter_del_vlan_internal(struct efx_nic *efx,
134 struct efx_ef10_filter_vlan *vlan);
135static void efx_ef10_filter_del_vlan(struct efx_nic *efx, u16 vid);
e5fbd977 136static int efx_ef10_set_udp_tnl_ports(struct efx_nic *efx, bool unloading);
8127d661 137
0ccb998b
JC		 138static u32 efx_ef10_filter_get_unsafe_id(u32 filter_id)
139{
140 WARN_ON_ONCE(filter_id == EFX_EF10_FILTER_ID_INVALID);
141 return filter_id & (HUNT_FILTER_TBL_ROWS - 1);
142}
143
144static unsigned int efx_ef10_filter_get_unsafe_pri(u32 filter_id)
145{
146 return filter_id / (HUNT_FILTER_TBL_ROWS * 2);
147}
148
149static u32 efx_ef10_make_filter_id(unsigned int pri, u16 idx)
150{
151 return pri * HUNT_FILTER_TBL_ROWS * 2 + idx;
152}
153
8127d661
BH		 154static int efx_ef10_get_warm_boot_count(struct efx_nic *efx)
155{
156 efx_dword_t reg;
157
158 efx_readd(efx, &reg, ER_DZ_BIU_MC_SFT_STATUS);
159 return EFX_DWORD_FIELD(reg, EFX_WORD_1) == 0xb007 ?
160 EFX_DWORD_FIELD(reg, EFX_WORD_0) : -EIO;
161}
162
03714bbb
EC		 163/* On all EF10s up to and including SFC9220 (Medford1), all PFs use BAR 0 for
164 * I/O space and BAR 2(&3) for memory. On SFC9250 (Medford2), there is no I/O
165 * bar; PFs use BAR 0/1 for memory.
166 */
167static unsigned int efx_ef10_pf_mem_bar(struct efx_nic *efx)
168{
169 switch (efx->pci_dev->device) {
170 case 0x0b03: /* SFC9250 PF */
171 return 0;
172 default:
173 return 2;
174 }
175}
176
177/* All VFs use BAR 0/1 for memory */
178static unsigned int efx_ef10_vf_mem_bar(struct efx_nic *efx)
179{
180 return 0;
181}
182
8127d661
BH		 183static unsigned int efx_ef10_mem_map_size(struct efx_nic *efx)
184{
02246a7f
SS		 185 int bar;
186
03714bbb 187 bar = efx->type->mem_bar(efx);
02246a7f 188 return resource_size(&efx->pci_dev->resource[bar]);
8127d661
BH		 189}
190
7a186f47
DP		 191static bool efx_ef10_is_vf(struct efx_nic *efx)
192{
193 return efx->type->is_vf;
194}
195
1cd9ecbb
DP		 196static int efx_ef10_get_pf_index(struct efx_nic *efx)
197{
198 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN);
199 struct efx_ef10_nic_data *nic_data = efx->nic_data;
200 size_t outlen;
201 int rc;
202
203 rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf,
204 sizeof(outbuf), &outlen);
205 if (rc)
206 return rc;
207 if (outlen < sizeof(outbuf))
208 return -EIO;
209
210 nic_data->pf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_PF);
211 return 0;
212}
213
88a37de6
SS		 214#ifdef CONFIG_SFC_SRIOV
215static int efx_ef10_get_vf_index(struct efx_nic *efx)
216{
217 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN);
218 struct efx_ef10_nic_data *nic_data = efx->nic_data;
219 size_t outlen;
220 int rc;
221
222 rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf,
223 sizeof(outbuf), &outlen);
224 if (rc)
225 return rc;
226 if (outlen < sizeof(outbuf))
227 return -EIO;
228
229 nic_data->vf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_VF);
230 return 0;
231}
232#endif
233
e5a2538a 234static int efx_ef10_init_datapath_caps(struct efx_nic *efx)
8127d661 235{
c1be4821 236 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CAPABILITIES_V4_OUT_LEN);
8127d661
BH		 237 struct efx_ef10_nic_data *nic_data = efx->nic_data;
238 size_t outlen;
239 int rc;
240
241 BUILD_BUG_ON(MC_CMD_GET_CAPABILITIES_IN_LEN != 0);
242
243 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CAPABILITIES, NULL, 0,
244 outbuf, sizeof(outbuf), &outlen);
245 if (rc)
246 return rc;
ca889a05 247 if (outlen < MC_CMD_GET_CAPABILITIES_OUT_LEN) {
e5a2538a
BH		 248 netif_err(efx, drv, efx->net_dev,
249 "unable to read datapath firmware capabilities\n");
250 return -EIO;
251 }
252
253 nic_data->datapath_caps =
254 MCDI_DWORD(outbuf, GET_CAPABILITIES_OUT_FLAGS1);
8127d661 255
c634700f 256 if (outlen >= MC_CMD_GET_CAPABILITIES_V2_OUT_LEN) {
ca889a05
BK		 257 nic_data->datapath_caps2 = MCDI_DWORD(outbuf,
258 GET_CAPABILITIES_V2_OUT_FLAGS2);
c634700f
EC		 259 nic_data->piobuf_size = MCDI_WORD(outbuf,
260 GET_CAPABILITIES_V2_OUT_SIZE_PIO_BUFF);
261 } else {
ca889a05 262 nic_data->datapath_caps2 = 0;
c634700f
EC		 263 nic_data->piobuf_size = ER_DZ_TX_PIOBUF_SIZE;
264 }
ca889a05 265
8d9f9dd4
DP		 266 /* record the DPCPU firmware IDs to determine VEB vswitching support.
267 */
268 nic_data->rx_dpcpu_fw_id =
269 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID);
270 nic_data->tx_dpcpu_fw_id =
271 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID);
272
e5a2538a
BH		 273 if (!(nic_data->datapath_caps &
274 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN))) {
275 netif_err(efx, probe, efx->net_dev,
276 "current firmware does not support an RX prefix\n");
277 return -ENODEV;
8127d661
BH		 278 }
279
71827443
EC		 280 if (outlen >= MC_CMD_GET_CAPABILITIES_V3_OUT_LEN) {
281 u8 vi_window_mode = MCDI_BYTE(outbuf,
282 GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE);
283
284 switch (vi_window_mode) {
285 case MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_8K:
286 efx->vi_stride = 8192;
287 break;
288 case MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_16K:
289 efx->vi_stride = 16384;
290 break;
291 case MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_64K:
292 efx->vi_stride = 65536;
293 break;
294 default:
295 netif_err(efx, probe, efx->net_dev,
296 "Unrecognised VI window mode %d\n",
297 vi_window_mode);
298 return -EIO;
299 }
300 netif_dbg(efx, probe, efx->net_dev, "vi_stride = %u\n",
301 efx->vi_stride);
302 } else {
303 /* keep default VI stride */
304 netif_dbg(efx, probe, efx->net_dev,
305 "firmware did not report VI window mode, assuming vi_stride = %u\n",
306 efx->vi_stride);
307 }
308
c1be4821
EC		 309 if (outlen >= MC_CMD_GET_CAPABILITIES_V4_OUT_LEN) {
310 efx->num_mac_stats = MCDI_WORD(outbuf,
311 GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS);
312 netif_dbg(efx, probe, efx->net_dev,
313 "firmware reports num_mac_stats = %u\n",
314 efx->num_mac_stats);
315 } else {
316 /* leave num_mac_stats as the default value, MC_CMD_MAC_NSTATS */
317 netif_dbg(efx, probe, efx->net_dev,
318 "firmware did not report num_mac_stats, assuming %u\n",
319 efx->num_mac_stats);
320 }
321
8127d661
BH		 322 return 0;
323}
324
325static int efx_ef10_get_sysclk_freq(struct efx_nic *efx)
326{
327 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CLOCK_OUT_LEN);
328 int rc;
329
330 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CLOCK, NULL, 0,
331 outbuf, sizeof(outbuf), NULL);
332 if (rc)
333 return rc;
334 rc = MCDI_DWORD(outbuf, GET_CLOCK_OUT_SYS_FREQ);
335 return rc > 0 ? rc : -ERANGE;
336}
337
d95e329a
BK		 338static int efx_ef10_get_timer_workarounds(struct efx_nic *efx)
339{
340 struct efx_ef10_nic_data *nic_data = efx->nic_data;
341 unsigned int implemented;
342 unsigned int enabled;
343 int rc;
344
345 nic_data->workaround_35388 = false;
346 nic_data->workaround_61265 = false;
347
348 rc = efx_mcdi_get_workarounds(efx, &implemented, &enabled);
349
350 if (rc == -ENOSYS) {
351 /* Firmware without GET_WORKAROUNDS - not a problem. */
352 rc = 0;
353 } else if (rc == 0) {
354 /* Bug61265 workaround is always enabled if implemented. */
355 if (enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG61265)
356 nic_data->workaround_61265 = true;
357
358 if (enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG35388) {
359 nic_data->workaround_35388 = true;
360 } else if (implemented & MC_CMD_GET_WORKAROUNDS_OUT_BUG35388) {
361 /* Workaround is implemented but not enabled.
362 * Try to enable it.
363 */
364 rc = efx_mcdi_set_workaround(efx,
365 MC_CMD_WORKAROUND_BUG35388,
366 true, NULL);
367 if (rc == 0)
368 nic_data->workaround_35388 = true;
369 /* If we failed to set the workaround just carry on. */
370 rc = 0;
371 }
372 }
373
374 netif_dbg(efx, probe, efx->net_dev,
375 "workaround for bug 35388 is %sabled\n",
376 nic_data->workaround_35388 ? "en" : "dis");
377 netif_dbg(efx, probe, efx->net_dev,
378 "workaround for bug 61265 is %sabled\n",
379 nic_data->workaround_61265 ? "en" : "dis");
380
381 return rc;
382}
383
384static void efx_ef10_process_timer_config(struct efx_nic *efx,
385 const efx_dword_t *data)
386{
387 unsigned int max_count;
388
389 if (EFX_EF10_WORKAROUND_61265(efx)) {
390 efx->timer_quantum_ns = MCDI_DWORD(data,
391 GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_STEP_NS);
392 efx->timer_max_ns = MCDI_DWORD(data,
393 GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_MAX_NS);
394 } else if (EFX_EF10_WORKAROUND_35388(efx)) {
395 efx->timer_quantum_ns = MCDI_DWORD(data,
396 GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_NS_PER_COUNT);
397 max_count = MCDI_DWORD(data,
398 GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_MAX_COUNT);
399 efx->timer_max_ns = max_count * efx->timer_quantum_ns;
400 } else {
401 efx->timer_quantum_ns = MCDI_DWORD(data,
402 GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_NS_PER_COUNT);
403 max_count = MCDI_DWORD(data,
404 GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_MAX_COUNT);
405 efx->timer_max_ns = max_count * efx->timer_quantum_ns;
406 }
407
408 netif_dbg(efx, probe, efx->net_dev,
409 "got timer properties from MC: quantum %u ns; max %u ns\n",
410 efx->timer_quantum_ns, efx->timer_max_ns);
411}
412
413static int efx_ef10_get_timer_config(struct efx_nic *efx)
414{
415 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_LEN);
416 int rc;
417
418 rc = efx_ef10_get_timer_workarounds(efx);
419 if (rc)
420 return rc;
421
422 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_GET_EVQ_TMR_PROPERTIES, NULL, 0,
423 outbuf, sizeof(outbuf), NULL);
424
425 if (rc == 0) {
426 efx_ef10_process_timer_config(efx, outbuf);
427 } else if (rc == -ENOSYS || rc == -EPERM) {
428 /* Not available - fall back to Huntington defaults. */
429 unsigned int quantum;
430
431 rc = efx_ef10_get_sysclk_freq(efx);
432 if (rc < 0)
433 return rc;
434
435 quantum = 1536000 / rc; /* 1536 cycles */
436 efx->timer_quantum_ns = quantum;
437 efx->timer_max_ns = efx->type->timer_period_max * quantum;
438 rc = 0;
439 } else {
440 efx_mcdi_display_error(efx, MC_CMD_GET_EVQ_TMR_PROPERTIES,
441 MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_LEN,
442 NULL, 0, rc);
443 }
444
445 return rc;
446}
447
0d5e0fbb 448static int efx_ef10_get_mac_address_pf(struct efx_nic *efx, u8 *mac_address)
8127d661
BH		 449{
450 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_MAC_ADDRESSES_OUT_LEN);
451 size_t outlen;
452 int rc;
453
454 BUILD_BUG_ON(MC_CMD_GET_MAC_ADDRESSES_IN_LEN != 0);
455
456 rc = efx_mcdi_rpc(efx, MC_CMD_GET_MAC_ADDRESSES, NULL, 0,
457 outbuf, sizeof(outbuf), &outlen);
458 if (rc)
459 return rc;
460 if (outlen < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN)
461 return -EIO;
462
cd84ff4d
EC		 463 ether_addr_copy(mac_address,
464 MCDI_PTR(outbuf, GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE));
8127d661
BH		 465 return 0;
466}
467
0d5e0fbb
DP		 468static int efx_ef10_get_mac_address_vf(struct efx_nic *efx, u8 *mac_address)
469{
470 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN);
471 MCDI_DECLARE_BUF(outbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX);
472 size_t outlen;
473 int num_addrs, rc;
474
475 MCDI_SET_DWORD(inbuf, VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID,
476 EVB_PORT_ID_ASSIGNED);
477 rc = efx_mcdi_rpc(efx, MC_CMD_VPORT_GET_MAC_ADDRESSES, inbuf,
478 sizeof(inbuf), outbuf, sizeof(outbuf), &outlen);
479
480 if (rc)
481 return rc;
482 if (outlen < MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN)
483 return -EIO;
484
485 num_addrs = MCDI_DWORD(outbuf,
486 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT);
487
488 WARN_ON(num_addrs != 1);
489
490 ether_addr_copy(mac_address,
491 MCDI_PTR(outbuf, VPORT_GET_MAC_ADDRESSES_OUT_MACADDR));
492
493 return 0;
494}
495
0f5c0845
SS		 496static ssize_t efx_ef10_show_link_control_flag(struct device *dev,
497 struct device_attribute *attr,
498 char *buf)
499{
500 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
501
502 return sprintf(buf, "%d\n",
503 ((efx->mcdi->fn_flags) &
504 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL))
505 ? 1 : 0);
506}
507
508static ssize_t efx_ef10_show_primary_flag(struct device *dev,
509 struct device_attribute *attr,
510 char *buf)
511{
512 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
513
514 return sprintf(buf, "%d\n",
515 ((efx->mcdi->fn_flags) &
516 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY))
517 ? 1 : 0);
518}
519
34813fe2
AR		 520static struct efx_ef10_vlan *efx_ef10_find_vlan(struct efx_nic *efx, u16 vid)
521{
522 struct efx_ef10_nic_data *nic_data = efx->nic_data;
523 struct efx_ef10_vlan *vlan;
524
525 WARN_ON(!mutex_is_locked(&nic_data->vlan_lock));
526
527 list_for_each_entry(vlan, &nic_data->vlan_list, list) {
528 if (vlan->vid == vid)
529 return vlan;
530 }
531
532 return NULL;
533}
534
535static int efx_ef10_add_vlan(struct efx_nic *efx, u16 vid)
536{
537 struct efx_ef10_nic_data *nic_data = efx->nic_data;
538 struct efx_ef10_vlan *vlan;
539 int rc;
540
541 mutex_lock(&nic_data->vlan_lock);
542
543 vlan = efx_ef10_find_vlan(efx, vid);
544 if (vlan) {
4a53ea8a
AR		 545 /* We add VID 0 on init. 8021q adds it on module init
546 * for all interfaces with VLAN filtring feature.
547 */
548 if (vid == 0)
549 goto done_unlock;
34813fe2
AR		 550 netif_warn(efx, drv, efx->net_dev,
551 "VLAN %u already added\n", vid);
552 rc = -EALREADY;
553 goto fail_exist;
554 }
555
556 rc = -ENOMEM;
557 vlan = kzalloc(sizeof(*vlan), GFP_KERNEL);
558 if (!vlan)
559 goto fail_alloc;
560
561 vlan->vid = vid;
562
563 list_add_tail(&vlan->list, &nic_data->vlan_list);
564
565 if (efx->filter_state) {
566 mutex_lock(&efx->mac_lock);
567 down_write(&efx->filter_sem);
568 rc = efx_ef10_filter_add_vlan(efx, vlan->vid);
569 up_write(&efx->filter_sem);
570 mutex_unlock(&efx->mac_lock);
571 if (rc)
572 goto fail_filter_add_vlan;
573 }
574
4a53ea8a 575done_unlock:
34813fe2
AR		 576 mutex_unlock(&nic_data->vlan_lock);
577 return 0;
578
579fail_filter_add_vlan:
580 list_del(&vlan->list);
581 kfree(vlan);
582fail_alloc:
583fail_exist:
584 mutex_unlock(&nic_data->vlan_lock);
585 return rc;
586}
587
588static void efx_ef10_del_vlan_internal(struct efx_nic *efx,
589 struct efx_ef10_vlan *vlan)
590{
591 struct efx_ef10_nic_data *nic_data = efx->nic_data;
592
593 WARN_ON(!mutex_is_locked(&nic_data->vlan_lock));
594
595 if (efx->filter_state) {
596 down_write(&efx->filter_sem);
597 efx_ef10_filter_del_vlan(efx, vlan->vid);
598 up_write(&efx->filter_sem);
599 }
600
601 list_del(&vlan->list);
602 kfree(vlan);
603}
604
4a53ea8a
AR		 605static int efx_ef10_del_vlan(struct efx_nic *efx, u16 vid)
606{
607 struct efx_ef10_nic_data *nic_data = efx->nic_data;
608 struct efx_ef10_vlan *vlan;
609 int rc = 0;
610
611 /* 8021q removes VID 0 on module unload for all interfaces
612 * with VLAN filtering feature. We need to keep it to receive
613 * untagged traffic.
614 */
615 if (vid == 0)
616 return 0;
617
618 mutex_lock(&nic_data->vlan_lock);
619
620 vlan = efx_ef10_find_vlan(efx, vid);
621 if (!vlan) {
622 netif_err(efx, drv, efx->net_dev,
623 "VLAN %u to be deleted not found\n", vid);
624 rc = -ENOENT;
625 } else {
626 efx_ef10_del_vlan_internal(efx, vlan);
627 }
628
629 mutex_unlock(&nic_data->vlan_lock);
630
631 return rc;
632}
633
34813fe2
AR		 634static void efx_ef10_cleanup_vlans(struct efx_nic *efx)
635{
636 struct efx_ef10_nic_data *nic_data = efx->nic_data;
637 struct efx_ef10_vlan *vlan, *next_vlan;
638
639 mutex_lock(&nic_data->vlan_lock);
640 list_for_each_entry_safe(vlan, next_vlan, &nic_data->vlan_list, list)
641 efx_ef10_del_vlan_internal(efx, vlan);
642 mutex_unlock(&nic_data->vlan_lock);
643}
644
0f5c0845
SS		 645static DEVICE_ATTR(link_control_flag, 0444, efx_ef10_show_link_control_flag,
646 NULL);
647static DEVICE_ATTR(primary_flag, 0444, efx_ef10_show_primary_flag, NULL);
648
8127d661
BH		 649static int efx_ef10_probe(struct efx_nic *efx)
650{
651 struct efx_ef10_nic_data *nic_data;
652 int i, rc;
653
8127d661
BH		 654 nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
655 if (!nic_data)
656 return -ENOMEM;
657 efx->nic_data = nic_data;
658
75aba2a5
EC		 659 /* we assume later that we can copy from this buffer in dwords */
660 BUILD_BUG_ON(MCDI_CTL_SDU_LEN_MAX_V2 % 4);
661
8127d661
BH		 662 rc = efx_nic_alloc_buffer(efx, &nic_data->mcdi_buf,
663 8 + MCDI_CTL_SDU_LEN_MAX_V2, GFP_KERNEL);
664 if (rc)
665 goto fail1;
666
667 /* Get the MC's warm boot count. In case it's rebooting right
668 * now, be prepared to retry.
669 */
670 i = 0;
671 for (;;) {
672 rc = efx_ef10_get_warm_boot_count(efx);
673 if (rc >= 0)
674 break;
675 if (++i == 5)
676 goto fail2;
677 ssleep(1);
678 }
679 nic_data->warm_boot_count = rc;
680
681 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
682
45b2449e
DP		 683 nic_data->vport_id = EVB_PORT_ID_ASSIGNED;
684
8127d661
BH		 685 /* In case we're recovering from a crash (kexec), we want to
686 * cancel any outstanding request by the previous user of this
687 * function. We send a special message using the least
688 * significant bits of the 'high' (doorbell) register.
689 */
690 _efx_writed(efx, cpu_to_le32(1), ER_DZ_MC_DB_HWRD);
691
692 rc = efx_mcdi_init(efx);
693 if (rc)
694 goto fail2;
695
e5fbd977
JC		 696 mutex_init(&nic_data->udp_tunnels_lock);
697
8127d661
BH		 698 /* Reset (most) configuration for this function */
699 rc = efx_mcdi_reset(efx, RESET_TYPE_ALL);
700 if (rc)
701 goto fail3;
702
703 /* Enable event logging */
704 rc = efx_mcdi_log_ctrl(efx, true, false, 0);
705 if (rc)
706 goto fail3;
707
0f5c0845
SS		 708 rc = device_create_file(&efx->pci_dev->dev,
709 &dev_attr_link_control_flag);
1cd9ecbb
DP		 710 if (rc)
711 goto fail3;
712
0f5c0845
SS		 713 rc = device_create_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
714 if (rc)
715 goto fail4;
716
717 rc = efx_ef10_get_pf_index(efx);
718 if (rc)
719 goto fail5;
720
e5a2538a 721 rc = efx_ef10_init_datapath_caps(efx);
8127d661 722 if (rc < 0)
0f5c0845 723 goto fail5;
8127d661 724
71827443
EC		 725 /* We can have one VI for each vi_stride-byte region.
726 * However, until we use TX option descriptors we need two TX queues
727 * per channel.
728 */
729 efx->max_channels = min_t(unsigned int,
730 EFX_MAX_CHANNELS,
731 efx_ef10_mem_map_size(efx) /
732 (efx->vi_stride * EFX_TXQ_TYPES));
733 efx->max_tx_channels = efx->max_channels;
734 if (WARN_ON(efx->max_channels == 0)) {
735 rc = -EIO;
736 goto fail5;
737 }
738
8127d661
BH		 739 efx->rx_packet_len_offset =
740 ES_DZ_RX_PREFIX_PKTLEN_OFST - ES_DZ_RX_PREFIX_SIZE;
741
6978729f
EC		 742 if (nic_data->datapath_caps &
743 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_INCLUDE_FCS_LBN))
744 efx->net_dev->hw_features |= NETIF_F_RXFCS;
745
8127d661
BH		 746 rc = efx_mcdi_port_get_number(efx);
747 if (rc < 0)
0f5c0845 748 goto fail5;
8127d661
BH		 749 efx->port_num = rc;
750
0d5e0fbb 751 rc = efx->type->get_mac_address(efx, efx->net_dev->perm_addr);
8127d661 752 if (rc)
0f5c0845 753 goto fail5;
8127d661 754
d95e329a 755 rc = efx_ef10_get_timer_config(efx);
8127d661 756 if (rc < 0)
0f5c0845 757 goto fail5;
8127d661 758
8127d661 759 rc = efx_mcdi_mon_probe(efx);
267d9d73 760 if (rc && rc != -EPERM)
0f5c0845 761 goto fail5;
8127d661 762
acaef3c1
EC		 763 rc = efx_ptp_probe(efx, NULL);
764 /* Failure to probe PTP is not fatal.
765 * In the case of EPERM, efx_ptp_probe will print its own message (in
766 * efx_ptp_get_attributes()), so we don't need to.
767 */
768 if (rc && rc != -EPERM)
769 netif_warn(efx, drv, efx->net_dev,
770 "Failed to probe PTP, rc=%d\n", rc);
9aecda95 771
1d051e00
SS		 772#ifdef CONFIG_SFC_SRIOV
773 if ((efx->pci_dev->physfn) && (!efx->pci_dev->is_physfn)) {
774 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn;
775 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
776
777 efx_pf->type->get_mac_address(efx_pf, nic_data->port_id);
778 } else
779#endif
780 ether_addr_copy(nic_data->port_id, efx->net_dev->perm_addr);
781
34813fe2
AR		 782 INIT_LIST_HEAD(&nic_data->vlan_list);
783 mutex_init(&nic_data->vlan_lock);
784
785 /* Add unspecified VID to support VLAN filtering being disabled */
786 rc = efx_ef10_add_vlan(efx, EFX_FILTER_VID_UNSPEC);
787 if (rc)
788 goto fail_add_vid_unspec;
789
4a53ea8a
AR		 790 /* If VLAN filtering is enabled, we need VID 0 to get untagged
791 * traffic. It is added automatically if 8021q module is loaded,
792 * but we can't rely on it since module may be not loaded.
793 */
794 rc = efx_ef10_add_vlan(efx, 0);
795 if (rc)
796 goto fail_add_vid_0;
797
8127d661
BH		 798 return 0;
799
4a53ea8a
AR		 800fail_add_vid_0:
801 efx_ef10_cleanup_vlans(efx);
34813fe2
AR		 802fail_add_vid_unspec:
803 mutex_destroy(&nic_data->vlan_lock);
804 efx_ptp_remove(efx);
805 efx_mcdi_mon_remove(efx);
0f5c0845
SS		 806fail5:
807 device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
808fail4:
809 device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag);
8127d661 810fail3:
e5fbd977
JC		 811 efx_mcdi_detach(efx);
812
813 mutex_lock(&nic_data->udp_tunnels_lock);
814 memset(nic_data->udp_tunnels, 0, sizeof(nic_data->udp_tunnels));
815 (void)efx_ef10_set_udp_tnl_ports(efx, true);
816 mutex_unlock(&nic_data->udp_tunnels_lock);
817 mutex_destroy(&nic_data->udp_tunnels_lock);
818
8127d661
BH		 819 efx_mcdi_fini(efx);
820fail2:
821 efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
822fail1:
823 kfree(nic_data);
824 efx->nic_data = NULL;
825 return rc;
826}
827
828static int efx_ef10_free_vis(struct efx_nic *efx)
829{
aa09a3da 830 MCDI_DECLARE_BUF_ERR(outbuf);
1e0b8120
EC		 831 size_t outlen;
832 int rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FREE_VIS, NULL, 0,
833 outbuf, sizeof(outbuf), &outlen);
8127d661
BH		 834
835 /* -EALREADY means nothing to free, so ignore */
836 if (rc == -EALREADY)
837 rc = 0;
1e0b8120
EC		 838 if (rc)
839 efx_mcdi_display_error(efx, MC_CMD_FREE_VIS, 0, outbuf, outlen,
840 rc);
8127d661
BH		 841 return rc;
842}
843
183233be
BH		 844#ifdef EFX_USE_PIO
845
846static void efx_ef10_free_piobufs(struct efx_nic *efx)
847{
848 struct efx_ef10_nic_data *nic_data = efx->nic_data;
849 MCDI_DECLARE_BUF(inbuf, MC_CMD_FREE_PIOBUF_IN_LEN);
850 unsigned int i;
851 int rc;
852
853 BUILD_BUG_ON(MC_CMD_FREE_PIOBUF_OUT_LEN != 0);
854
855 for (i = 0; i < nic_data->n_piobufs; i++) {
856 MCDI_SET_DWORD(inbuf, FREE_PIOBUF_IN_PIOBUF_HANDLE,
857 nic_data->piobuf_handle[i]);
858 rc = efx_mcdi_rpc(efx, MC_CMD_FREE_PIOBUF, inbuf, sizeof(inbuf),
859 NULL, 0, NULL);
860 WARN_ON(rc);
861 }
862
863 nic_data->n_piobufs = 0;
864}
865
866static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
867{
868 struct efx_ef10_nic_data *nic_data = efx->nic_data;
869 MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_PIOBUF_OUT_LEN);
870 unsigned int i;
871 size_t outlen;
872 int rc = 0;
873
874 BUILD_BUG_ON(MC_CMD_ALLOC_PIOBUF_IN_LEN != 0);
875
876 for (i = 0; i < n; i++) {
09a04204
BK		 877 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_ALLOC_PIOBUF, NULL, 0,
878 outbuf, sizeof(outbuf), &outlen);
879 if (rc) {
880 /* Don't display the MC error if we didn't have space
881 * for a VF.
882 */
883 if (!(efx_ef10_is_vf(efx) && rc == -ENOSPC))
884 efx_mcdi_display_error(efx, MC_CMD_ALLOC_PIOBUF,
885 0, outbuf, outlen, rc);
183233be 886 break;
09a04204 887 }
183233be
BH		 888 if (outlen < MC_CMD_ALLOC_PIOBUF_OUT_LEN) {
889 rc = -EIO;
890 break;
891 }
892 nic_data->piobuf_handle[i] =
893 MCDI_DWORD(outbuf, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE);
894 netif_dbg(efx, probe, efx->net_dev,
895 "allocated PIO buffer %u handle %x\n", i,
896 nic_data->piobuf_handle[i]);
897 }
898
899 nic_data->n_piobufs = i;
900 if (rc)
901 efx_ef10_free_piobufs(efx);
902 return rc;
903}
904
905static int efx_ef10_link_piobufs(struct efx_nic *efx)
906{
907 struct efx_ef10_nic_data *nic_data = efx->nic_data;
d0346b03 908 MCDI_DECLARE_BUF(inbuf, MC_CMD_LINK_PIOBUF_IN_LEN);
183233be
BH		 909 struct efx_channel *channel;
910 struct efx_tx_queue *tx_queue;
911 unsigned int offset, index;
912 int rc;
913
914 BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_OUT_LEN != 0);
915 BUILD_BUG_ON(MC_CMD_UNLINK_PIOBUF_OUT_LEN != 0);
916
917 /* Link a buffer to each VI in the write-combining mapping */
918 for (index = 0; index < nic_data->n_piobufs; ++index) {
919 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_PIOBUF_HANDLE,
920 nic_data->piobuf_handle[index]);
921 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_TXQ_INSTANCE,
922 nic_data->pio_write_vi_base + index);
923 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
924 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
925 NULL, 0, NULL);
926 if (rc) {
927 netif_err(efx, drv, efx->net_dev,
928 "failed to link VI %u to PIO buffer %u (%d)\n",
929 nic_data->pio_write_vi_base + index, index,
930 rc);
931 goto fail;
932 }
933 netif_dbg(efx, probe, efx->net_dev,
934 "linked VI %u to PIO buffer %u\n",
935 nic_data->pio_write_vi_base + index, index);
936 }
937
938 /* Link a buffer to each TX queue */
939 efx_for_each_channel(channel, efx) {
940 efx_for_each_channel_tx_queue(tx_queue, channel) {
941 /* We assign the PIO buffers to queues in
942 * reverse order to allow for the following
943 * special case.
944 */
945 offset = ((efx->tx_channel_offset + efx->n_tx_channels -
946 tx_queue->channel->channel - 1) *
947 efx_piobuf_size);
c634700f
EC		 948 index = offset / nic_data->piobuf_size;
949 offset = offset % nic_data->piobuf_size;
183233be
BH		 950
951 /* When the host page size is 4K, the first
952 * host page in the WC mapping may be within
953 * the same VI page as the last TX queue. We
954 * can only link one buffer to each VI.
955 */
956 if (tx_queue->queue == nic_data->pio_write_vi_base) {
957 BUG_ON(index != 0);
958 rc = 0;
959 } else {
960 MCDI_SET_DWORD(inbuf,
961 LINK_PIOBUF_IN_PIOBUF_HANDLE,
962 nic_data->piobuf_handle[index]);
963 MCDI_SET_DWORD(inbuf,
964 LINK_PIOBUF_IN_TXQ_INSTANCE,
965 tx_queue->queue);
966 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
967 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
968 NULL, 0, NULL);
969 }
970
971 if (rc) {
972 /* This is non-fatal; the TX path just
973 * won't use PIO for this queue
974 */
975 netif_err(efx, drv, efx->net_dev,
976 "failed to link VI %u to PIO buffer %u (%d)\n",
977 tx_queue->queue, index, rc);
978 tx_queue->piobuf = NULL;
979 } else {
980 tx_queue->piobuf =
981 nic_data->pio_write_base +
71827443 982 index * efx->vi_stride + offset;
183233be
BH		 983 tx_queue->piobuf_offset = offset;
984 netif_dbg(efx, probe, efx->net_dev,
985 "linked VI %u to PIO buffer %u offset %x addr %p\n",
986 tx_queue->queue, index,
987 tx_queue->piobuf_offset,
988 tx_queue->piobuf);
989 }
990 }
991 }
992
993 return 0;
994
995fail:
d0346b03
EC		 996 /* inbuf was defined for MC_CMD_LINK_PIOBUF. We can use the same
997 * buffer for MC_CMD_UNLINK_PIOBUF because it's shorter.
998 */
999 BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_IN_LEN < MC_CMD_UNLINK_PIOBUF_IN_LEN);
183233be
BH		 1000 while (index--) {
1001 MCDI_SET_DWORD(inbuf, UNLINK_PIOBUF_IN_TXQ_INSTANCE,
1002 nic_data->pio_write_vi_base + index);
1003 efx_mcdi_rpc(efx, MC_CMD_UNLINK_PIOBUF,
1004 inbuf, MC_CMD_UNLINK_PIOBUF_IN_LEN,
1005 NULL, 0, NULL);
1006 }
1007 return rc;
1008}
1009
c0795bf6
EC		 1010static void efx_ef10_forget_old_piobufs(struct efx_nic *efx)
1011{
1012 struct efx_channel *channel;
1013 struct efx_tx_queue *tx_queue;
1014
1015 /* All our existing PIO buffers went away */
1016 efx_for_each_channel(channel, efx)
1017 efx_for_each_channel_tx_queue(tx_queue, channel)
1018 tx_queue->piobuf = NULL;
1019}
1020
183233be
BH		 1021#else /* !EFX_USE_PIO */
1022
1023static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
1024{
1025 return n == 0 ? 0 : -ENOBUFS;
1026}
1027
1028static int efx_ef10_link_piobufs(struct efx_nic *efx)
1029{
1030 return 0;
1031}
1032
1033static void efx_ef10_free_piobufs(struct efx_nic *efx)
1034{
1035}
1036
c0795bf6
EC		 1037static void efx_ef10_forget_old_piobufs(struct efx_nic *efx)
1038{
1039}
1040
183233be
BH		 1041#endif /* EFX_USE_PIO */
1042
8127d661
BH		 1043static void efx_ef10_remove(struct efx_nic *efx)
1044{
1045 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1046 int rc;
1047
f1122a34
SS		 1048#ifdef CONFIG_SFC_SRIOV
1049 struct efx_ef10_nic_data *nic_data_pf;
1050 struct pci_dev *pci_dev_pf;
1051 struct efx_nic *efx_pf;
1052 struct ef10_vf *vf;
1053
1054 if (efx->pci_dev->is_virtfn) {
1055 pci_dev_pf = efx->pci_dev->physfn;
1056 if (pci_dev_pf) {
1057 efx_pf = pci_get_drvdata(pci_dev_pf);
1058 nic_data_pf = efx_pf->nic_data;
1059 vf = nic_data_pf->vf + nic_data->vf_index;
1060 vf->efx = NULL;
1061 } else
1062 netif_info(efx, drv, efx->net_dev,
1063 "Could not get the PF id from VF\n");
1064 }
1065#endif
1066
34813fe2
AR		 1067 efx_ef10_cleanup_vlans(efx);
1068 mutex_destroy(&nic_data->vlan_lock);
1069
9aecda95
BH		 1070 efx_ptp_remove(efx);
1071
8127d661
BH		 1072 efx_mcdi_mon_remove(efx);
1073
8127d661
BH		 1074 efx_ef10_rx_free_indir_table(efx);
1075
183233be
BH		 1076 if (nic_data->wc_membase)
1077 iounmap(nic_data->wc_membase);
1078
8127d661
BH		 1079 rc = efx_ef10_free_vis(efx);
1080 WARN_ON(rc != 0);
1081
183233be
BH		 1082 if (!nic_data->must_restore_piobufs)
1083 efx_ef10_free_piobufs(efx);
1084
0f5c0845
SS		 1085 device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
1086 device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag);
1087
e5fbd977
JC		 1088 efx_mcdi_detach(efx);
1089
1090 memset(nic_data->udp_tunnels, 0, sizeof(nic_data->udp_tunnels));
1091 mutex_lock(&nic_data->udp_tunnels_lock);
1092 (void)efx_ef10_set_udp_tnl_ports(efx, true);
1093 mutex_unlock(&nic_data->udp_tunnels_lock);
1094
1095 mutex_destroy(&nic_data->udp_tunnels_lock);
1096
8127d661
BH		 1097 efx_mcdi_fini(efx);
1098 efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
1099 kfree(nic_data);
1100}
1101
88a37de6
SS		 1102static int efx_ef10_probe_pf(struct efx_nic *efx)
1103{
1104 return efx_ef10_probe(efx);
1105}
1106
38d27f38
AR		 1107int efx_ef10_vadaptor_query(struct efx_nic *efx, unsigned int port_id,
1108 u32 *port_flags, u32 *vadaptor_flags,
1109 unsigned int *vlan_tags)
1110{
1111 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1112 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_QUERY_IN_LEN);
1113 MCDI_DECLARE_BUF(outbuf, MC_CMD_VADAPTOR_QUERY_OUT_LEN);
1114 size_t outlen;
1115 int rc;
1116
1117 if (nic_data->datapath_caps &
1118 (1 << MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_LBN)) {
1119 MCDI_SET_DWORD(inbuf, VADAPTOR_QUERY_IN_UPSTREAM_PORT_ID,
1120 port_id);
1121
1122 rc = efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_QUERY, inbuf, sizeof(inbuf),
1123 outbuf, sizeof(outbuf), &outlen);
1124 if (rc)
1125 return rc;
1126
1127 if (outlen < sizeof(outbuf)) {
1128 rc = -EIO;
1129 return rc;
1130 }
1131 }
1132
1133 if (port_flags)
1134 *port_flags = MCDI_DWORD(outbuf, VADAPTOR_QUERY_OUT_PORT_FLAGS);
1135 if (vadaptor_flags)
1136 *vadaptor_flags =
1137 MCDI_DWORD(outbuf, VADAPTOR_QUERY_OUT_VADAPTOR_FLAGS);
1138 if (vlan_tags)
1139 *vlan_tags =
1140 MCDI_DWORD(outbuf,
1141 VADAPTOR_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS);
1142
1143 return 0;
1144}
1145
7a186f47
DP		 1146int efx_ef10_vadaptor_alloc(struct efx_nic *efx, unsigned int port_id)
1147{
1148 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_ALLOC_IN_LEN);
1149
1150 MCDI_SET_DWORD(inbuf, VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID, port_id);
1151 return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_ALLOC, inbuf, sizeof(inbuf),
1152 NULL, 0, NULL);
1153}
1154
1155int efx_ef10_vadaptor_free(struct efx_nic *efx, unsigned int port_id)
1156{
1157 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_FREE_IN_LEN);
1158
1159 MCDI_SET_DWORD(inbuf, VADAPTOR_FREE_IN_UPSTREAM_PORT_ID, port_id);
1160 return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_FREE, inbuf, sizeof(inbuf),
1161 NULL, 0, NULL);
1162}
1163
1164int efx_ef10_vport_add_mac(struct efx_nic *efx,
1165 unsigned int port_id, u8 *mac)
1166{
1167 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_LEN);
1168
1169 MCDI_SET_DWORD(inbuf, VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID, port_id);
1170 ether_addr_copy(MCDI_PTR(inbuf, VPORT_ADD_MAC_ADDRESS_IN_MACADDR), mac);
1171
1172 return efx_mcdi_rpc(efx, MC_CMD_VPORT_ADD_MAC_ADDRESS, inbuf,
1173 sizeof(inbuf), NULL, 0, NULL);
1174}
1175
1176int efx_ef10_vport_del_mac(struct efx_nic *efx,
1177 unsigned int port_id, u8 *mac)
1178{
1179 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_LEN);
1180
1181 MCDI_SET_DWORD(inbuf, VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID, port_id);
1182 ether_addr_copy(MCDI_PTR(inbuf, VPORT_DEL_MAC_ADDRESS_IN_MACADDR), mac);
1183
1184 return efx_mcdi_rpc(efx, MC_CMD_VPORT_DEL_MAC_ADDRESS, inbuf,
1185 sizeof(inbuf), NULL, 0, NULL);
1186}
1187
88a37de6
SS		 1188#ifdef CONFIG_SFC_SRIOV
1189static int efx_ef10_probe_vf(struct efx_nic *efx)
1190{
1191 int rc;
6598dad2
DP		 1192 struct pci_dev *pci_dev_pf;
1193
1194 /* If the parent PF has no VF data structure, it doesn't know about this
1195 * VF so fail probe. The VF needs to be re-created. This can happen
1196 * if the PF driver is unloaded while the VF is assigned to a guest.
1197 */
1198 pci_dev_pf = efx->pci_dev->physfn;
1199 if (pci_dev_pf) {
1200 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
1201 struct efx_ef10_nic_data *nic_data_pf = efx_pf->nic_data;
1202
1203 if (!nic_data_pf->vf) {
1204 netif_info(efx, drv, efx->net_dev,
1205 "The VF cannot link to its parent PF; "
1206 "please destroy and re-create the VF\n");
1207 return -EBUSY;
1208 }
1209 }
88a37de6
SS		 1210
1211 rc = efx_ef10_probe(efx);
1212 if (rc)
1213 return rc;
1214
1215 rc = efx_ef10_get_vf_index(efx);
1216 if (rc)
1217 goto fail;
1218
f1122a34
SS		 1219 if (efx->pci_dev->is_virtfn) {
1220 if (efx->pci_dev->physfn) {
1221 struct efx_nic *efx_pf =
1222 pci_get_drvdata(efx->pci_dev->physfn);
1223 struct efx_ef10_nic_data *nic_data_p = efx_pf->nic_data;
1224 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1225
1226 nic_data_p->vf[nic_data->vf_index].efx = efx;
6598dad2
DP		 1227 nic_data_p->vf[nic_data->vf_index].pci_dev =
1228 efx->pci_dev;
f1122a34
SS		 1229 } else
1230 netif_info(efx, drv, efx->net_dev,
1231 "Could not get the PF id from VF\n");
1232 }
1233
88a37de6
SS		 1234 return 0;
1235
1236fail:
1237 efx_ef10_remove(efx);
1238 return rc;
1239}
1240#else
1241static int efx_ef10_probe_vf(struct efx_nic *efx __attribute__ ((unused)))
1242{
1243 return 0;
1244}
1245#endif
1246
8127d661
BH		 1247static int efx_ef10_alloc_vis(struct efx_nic *efx,
1248 unsigned int min_vis, unsigned int max_vis)
1249{
1250 MCDI_DECLARE_BUF(inbuf, MC_CMD_ALLOC_VIS_IN_LEN);
1251 MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_VIS_OUT_LEN);
1252 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1253 size_t outlen;
1254 int rc;
1255
1256 MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MIN_VI_COUNT, min_vis);
1257 MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MAX_VI_COUNT, max_vis);
1258 rc = efx_mcdi_rpc(efx, MC_CMD_ALLOC_VIS, inbuf, sizeof(inbuf),
1259 outbuf, sizeof(outbuf), &outlen);
1260 if (rc != 0)
1261 return rc;
1262
1263 if (outlen < MC_CMD_ALLOC_VIS_OUT_LEN)
1264 return -EIO;
1265
1266 netif_dbg(efx, drv, efx->net_dev, "base VI is A0x%03x\n",
1267 MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE));
1268
1269 nic_data->vi_base = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE);
1270 nic_data->n_allocated_vis = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_COUNT);
1271 return 0;
1272}
1273
183233be
BH		 1274/* Note that the failure path of this function does not free
1275 * resources, as this will be done by efx_ef10_remove().
1276 */
8127d661
BH		 1277static int efx_ef10_dimension_resources(struct efx_nic *efx)
1278{
183233be
BH		 1279 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1280 unsigned int uc_mem_map_size, wc_mem_map_size;
b0fbdae1
SS		 1281 unsigned int min_vis = max(EFX_TXQ_TYPES,
1282 efx_separate_tx_channels ? 2 : 1);
1283 unsigned int channel_vis, pio_write_vi_base, max_vis;
183233be
BH		 1284 void __iomem *membase;
1285 int rc;
1286
b0fbdae1 1287 channel_vis = max(efx->n_channels, efx->n_tx_channels * EFX_TXQ_TYPES);
8127d661 1288
183233be
BH		 1289#ifdef EFX_USE_PIO
1290 /* Try to allocate PIO buffers if wanted and if the full
1291 * number of PIO buffers would be sufficient to allocate one
1292 * copy-buffer per TX channel. Failure is non-fatal, as there
1293 * are only a small number of PIO buffers shared between all
1294 * functions of the controller.
1295 */
1296 if (efx_piobuf_size != 0 &&
c634700f 1297 nic_data->piobuf_size / efx_piobuf_size * EF10_TX_PIOBUF_COUNT >=
183233be
BH		 1298 efx->n_tx_channels) {
1299 unsigned int n_piobufs =
1300 DIV_ROUND_UP(efx->n_tx_channels,
c634700f 1301 nic_data->piobuf_size / efx_piobuf_size);
183233be
BH		 1302
1303 rc = efx_ef10_alloc_piobufs(efx, n_piobufs);
6eacfb54
TP		 1304 if (rc == -ENOSPC)
1305 netif_dbg(efx, probe, efx->net_dev,
1306 "out of PIO buffers; cannot allocate more\n");
1307 else if (rc == -EPERM)
1308 netif_dbg(efx, probe, efx->net_dev,
1309 "not permitted to allocate PIO buffers\n");
1310 else if (rc)
183233be
BH		 1311 netif_err(efx, probe, efx->net_dev,
1312 "failed to allocate PIO buffers (%d)\n", rc);
1313 else
1314 netif_dbg(efx, probe, efx->net_dev,
1315 "allocated %u PIO buffers\n", n_piobufs);
1316 }
1317#else
1318 nic_data->n_piobufs = 0;
1319#endif
1320
1321 /* PIO buffers should be mapped with write-combining enabled,
1322 * and we want to make single UC and WC mappings rather than
1323 * several of each (in fact that's the only option if host
1324 * page size is >4K). So we may allocate some extra VIs just
1325 * for writing PIO buffers through.
52ad762b 1326 *
b0fbdae1 1327 * The UC mapping contains (channel_vis - 1) complete VIs and the
71827443
EC		 1328 * first 4K of the next VI. Then the WC mapping begins with
1329 * the remainder of this last VI.
183233be 1330 */
71827443 1331 uc_mem_map_size = PAGE_ALIGN((channel_vis - 1) * efx->vi_stride +
183233be
BH		 1332 ER_DZ_TX_PIOBUF);
1333 if (nic_data->n_piobufs) {
52ad762b
DP		 1334 /* pio_write_vi_base rounds down to give the number of complete
1335 * VIs inside the UC mapping.
1336 */
71827443 1337 pio_write_vi_base = uc_mem_map_size / efx->vi_stride;
183233be
BH		 1338 wc_mem_map_size = (PAGE_ALIGN((pio_write_vi_base +
1339 nic_data->n_piobufs) *
71827443 1340 efx->vi_stride) -
183233be
BH		 1341 uc_mem_map_size);
1342 max_vis = pio_write_vi_base + nic_data->n_piobufs;
1343 } else {
1344 pio_write_vi_base = 0;
1345 wc_mem_map_size = 0;
b0fbdae1 1346 max_vis = channel_vis;
183233be
BH		 1347 }
1348
1349 /* In case the last attached driver failed to free VIs, do it now */
1350 rc = efx_ef10_free_vis(efx);
1351 if (rc != 0)
1352 return rc;
1353
1354 rc = efx_ef10_alloc_vis(efx, min_vis, max_vis);
1355 if (rc != 0)
1356 return rc;
1357
b0fbdae1
SS		 1358 if (nic_data->n_allocated_vis < channel_vis) {
1359 netif_info(efx, drv, efx->net_dev,
1360 "Could not allocate enough VIs to satisfy RSS"
1361 " requirements. Performance may not be optimal.\n");
1362 /* We didn't get the VIs to populate our channels.
1363 * We could keep what we got but then we'd have more
1364 * interrupts than we need.
1365 * Instead calculate new max_channels and restart
1366 */
1367 efx->max_channels = nic_data->n_allocated_vis;
1368 efx->max_tx_channels =
1369 nic_data->n_allocated_vis / EFX_TXQ_TYPES;
1370
1371 efx_ef10_free_vis(efx);
1372 return -EAGAIN;
1373 }
1374
183233be
BH		 1375 /* If we didn't get enough VIs to map all the PIO buffers, free the
1376 * PIO buffers
1377 */
1378 if (nic_data->n_piobufs &&
1379 nic_data->n_allocated_vis <
1380 pio_write_vi_base + nic_data->n_piobufs) {
1381 netif_dbg(efx, probe, efx->net_dev,
1382 "%u VIs are not sufficient to map %u PIO buffers\n",
1383 nic_data->n_allocated_vis, nic_data->n_piobufs);
1384 efx_ef10_free_piobufs(efx);
1385 }
1386
1387 /* Shrink the original UC mapping of the memory BAR */
1388 membase = ioremap_nocache(efx->membase_phys, uc_mem_map_size);
1389 if (!membase) {
1390 netif_err(efx, probe, efx->net_dev,
1391 "could not shrink memory BAR to %x\n",
1392 uc_mem_map_size);
1393 return -ENOMEM;
1394 }
1395 iounmap(efx->membase);
1396 efx->membase = membase;
1397
1398 /* Set up the WC mapping if needed */
1399 if (wc_mem_map_size) {
1400 nic_data->wc_membase = ioremap_wc(efx->membase_phys +
1401 uc_mem_map_size,
1402 wc_mem_map_size);
1403 if (!nic_data->wc_membase) {
1404 netif_err(efx, probe, efx->net_dev,
1405 "could not allocate WC mapping of size %x\n",
1406 wc_mem_map_size);
1407 return -ENOMEM;
1408 }
1409 nic_data->pio_write_vi_base = pio_write_vi_base;
1410 nic_data->pio_write_base =
1411 nic_data->wc_membase +
71827443 1412 (pio_write_vi_base * efx->vi_stride + ER_DZ_TX_PIOBUF -
183233be
BH		 1413 uc_mem_map_size);
1414
1415 rc = efx_ef10_link_piobufs(efx);
1416 if (rc)
1417 efx_ef10_free_piobufs(efx);
1418 }
1419
1420 netif_dbg(efx, probe, efx->net_dev,
1421 "memory BAR at %pa (virtual %p+%x UC, %p+%x WC)\n",
1422 &efx->membase_phys, efx->membase, uc_mem_map_size,
1423 nic_data->wc_membase, wc_mem_map_size);
1424
1425 return 0;
8127d661
BH		 1426}
1427
1428static int efx_ef10_init_nic(struct efx_nic *efx)
1429{
1430 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1431 int rc;
1432
a915ccc9
BH		 1433 if (nic_data->must_check_datapath_caps) {
1434 rc = efx_ef10_init_datapath_caps(efx);
1435 if (rc)
1436 return rc;
1437 nic_data->must_check_datapath_caps = false;
1438 }
1439
8127d661
BH		 1440 if (nic_data->must_realloc_vis) {
1441 /* We cannot let the number of VIs change now */
1442 rc = efx_ef10_alloc_vis(efx, nic_data->n_allocated_vis,
1443 nic_data->n_allocated_vis);
1444 if (rc)
1445 return rc;
1446 nic_data->must_realloc_vis = false;
1447 }
1448
183233be
BH		 1449 if (nic_data->must_restore_piobufs && nic_data->n_piobufs) {
1450 rc = efx_ef10_alloc_piobufs(efx, nic_data->n_piobufs);
1451 if (rc == 0) {
1452 rc = efx_ef10_link_piobufs(efx);
1453 if (rc)
1454 efx_ef10_free_piobufs(efx);
1455 }
1456
6eacfb54
TP		 1457 /* Log an error on failure, but this is non-fatal.
1458 * Permission errors are less important - we've presumably
1459 * had the PIO buffer licence removed.
1460 */
1461 if (rc == -EPERM)
1462 netif_dbg(efx, drv, efx->net_dev,
1463 "not permitted to restore PIO buffers\n");
1464 else if (rc)
183233be
BH		 1465 netif_err(efx, drv, efx->net_dev,
1466 "failed to restore PIO buffers (%d)\n", rc);
1467 nic_data->must_restore_piobufs = false;
1468 }
1469
267c0157 1470 /* don't fail init if RSS setup doesn't work */
f74d1995 1471 rc = efx->type->rx_push_rss_config(efx, false, efx->rx_indir_table, NULL);
4fdda958 1472 efx->rss_active = (rc == 0);
267c0157 1473
8127d661
BH		 1474 return 0;
1475}
1476
3e336261
JC		 1477static void efx_ef10_reset_mc_allocations(struct efx_nic *efx)
1478{
1479 struct efx_ef10_nic_data *nic_data = efx->nic_data;
774ad031
DP		 1480#ifdef CONFIG_SFC_SRIOV
1481 unsigned int i;
1482#endif
3e336261
JC		 1483
1484 /* All our allocations have been reset */
1485 nic_data->must_realloc_vis = true;
1486 nic_data->must_restore_filters = true;
1487 nic_data->must_restore_piobufs = true;
c0795bf6 1488 efx_ef10_forget_old_piobufs(efx);
3e336261 1489 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
774ad031
DP		 1490
1491 /* Driver-created vswitches and vports must be re-created */
1492 nic_data->must_probe_vswitching = true;
1493 nic_data->vport_id = EVB_PORT_ID_ASSIGNED;
1494#ifdef CONFIG_SFC_SRIOV
1495 if (nic_data->vf)
1496 for (i = 0; i < efx->vf_count; i++)
1497 nic_data->vf[i].vport_id = 0;
1498#endif
3e336261
JC		 1499}
1500
087e9025
JC		 1501static enum reset_type efx_ef10_map_reset_reason(enum reset_type reason)
1502{
1503 if (reason == RESET_TYPE_MC_FAILURE)
1504 return RESET_TYPE_DATAPATH;
1505
1506 return efx_mcdi_map_reset_reason(reason);
1507}
1508
8127d661
BH		 1509static int efx_ef10_map_reset_flags(u32 *flags)
1510{
1511 enum {
1512 EF10_RESET_PORT = ((ETH_RESET_MAC | ETH_RESET_PHY) <<
1513 ETH_RESET_SHARED_SHIFT),
1514 EF10_RESET_MC = ((ETH_RESET_DMA | ETH_RESET_FILTER |
1515 ETH_RESET_OFFLOAD | ETH_RESET_MAC |
1516 ETH_RESET_PHY | ETH_RESET_MGMT) <<
1517 ETH_RESET_SHARED_SHIFT)
1518 };
1519
1520 /* We assume for now that our PCI function is permitted to
1521 * reset everything.
1522 */
1523
1524 if ((*flags & EF10_RESET_MC) == EF10_RESET_MC) {
1525 *flags &= ~EF10_RESET_MC;
1526 return RESET_TYPE_WORLD;
1527 }
1528
1529 if ((*flags & EF10_RESET_PORT) == EF10_RESET_PORT) {
1530 *flags &= ~EF10_RESET_PORT;
1531 return RESET_TYPE_ALL;
1532 }
1533
1534 /* no invisible reset implemented */
1535
1536 return -EINVAL;
1537}
1538
3e336261
JC		 1539static int efx_ef10_reset(struct efx_nic *efx, enum reset_type reset_type)
1540{
1541 int rc = efx_mcdi_reset(efx, reset_type);
1542
27324820
DP		 1543 /* Unprivileged functions return -EPERM, but need to return success
1544 * here so that the datapath is brought back up.
1545 */
1546 if (reset_type == RESET_TYPE_WORLD && rc == -EPERM)
1547 rc = 0;
1548
3e336261
JC		 1549 /* If it was a port reset, trigger reallocation of MC resources.
1550 * Note that on an MC reset nothing needs to be done now because we'll
1551 * detect the MC reset later and handle it then.
e283546c
EC		 1552 * For an FLR, we never get an MC reset event, but the MC has reset all
1553 * resources assigned to us, so we have to trigger reallocation now.
3e336261 1554 */
e283546c
EC		 1555 if ((reset_type == RESET_TYPE_ALL ||
1556 reset_type == RESET_TYPE_MCDI_TIMEOUT) && !rc)
3e336261
JC		 1557 efx_ef10_reset_mc_allocations(efx);
1558 return rc;
1559}
1560
8127d661
BH		 1561#define EF10_DMA_STAT(ext_name, mcdi_name) \
1562 [EF10_STAT_ ## ext_name] = \
1563 { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
1564#define EF10_DMA_INVIS_STAT(int_name, mcdi_name) \
1565 [EF10_STAT_ ## int_name] = \
1566 { NULL, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
1567#define EF10_OTHER_STAT(ext_name) \
1568 [EF10_STAT_ ## ext_name] = { #ext_name, 0, 0 }
e4d112e4
EC		 1569#define GENERIC_SW_STAT(ext_name) \
1570 [GENERIC_STAT_ ## ext_name] = { #ext_name, 0, 0 }
8127d661
BH		 1571
1572static const struct efx_hw_stat_desc efx_ef10_stat_desc[EF10_STAT_COUNT] = {
e80ca013
DP		 1573 EF10_DMA_STAT(port_tx_bytes, TX_BYTES),
1574 EF10_DMA_STAT(port_tx_packets, TX_PKTS),
1575 EF10_DMA_STAT(port_tx_pause, TX_PAUSE_PKTS),
1576 EF10_DMA_STAT(port_tx_control, TX_CONTROL_PKTS),
1577 EF10_DMA_STAT(port_tx_unicast, TX_UNICAST_PKTS),
1578 EF10_DMA_STAT(port_tx_multicast, TX_MULTICAST_PKTS),
1579 EF10_DMA_STAT(port_tx_broadcast, TX_BROADCAST_PKTS),
1580 EF10_DMA_STAT(port_tx_lt64, TX_LT64_PKTS),
1581 EF10_DMA_STAT(port_tx_64, TX_64_PKTS),
1582 EF10_DMA_STAT(port_tx_65_to_127, TX_65_TO_127_PKTS),
1583 EF10_DMA_STAT(port_tx_128_to_255, TX_128_TO_255_PKTS),
1584 EF10_DMA_STAT(port_tx_256_to_511, TX_256_TO_511_PKTS),
1585 EF10_DMA_STAT(port_tx_512_to_1023, TX_512_TO_1023_PKTS),
1586 EF10_DMA_STAT(port_tx_1024_to_15xx, TX_1024_TO_15XX_PKTS),
1587 EF10_DMA_STAT(port_tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS),
1588 EF10_DMA_STAT(port_rx_bytes, RX_BYTES),
1589 EF10_DMA_INVIS_STAT(port_rx_bytes_minus_good_bytes, RX_BAD_BYTES),
1590 EF10_OTHER_STAT(port_rx_good_bytes),
1591 EF10_OTHER_STAT(port_rx_bad_bytes),
1592 EF10_DMA_STAT(port_rx_packets, RX_PKTS),
1593 EF10_DMA_STAT(port_rx_good, RX_GOOD_PKTS),
1594 EF10_DMA_STAT(port_rx_bad, RX_BAD_FCS_PKTS),
1595 EF10_DMA_STAT(port_rx_pause, RX_PAUSE_PKTS),
1596 EF10_DMA_STAT(port_rx_control, RX_CONTROL_PKTS),
1597 EF10_DMA_STAT(port_rx_unicast, RX_UNICAST_PKTS),
1598 EF10_DMA_STAT(port_rx_multicast, RX_MULTICAST_PKTS),
1599 EF10_DMA_STAT(port_rx_broadcast, RX_BROADCAST_PKTS),
1600 EF10_DMA_STAT(port_rx_lt64, RX_UNDERSIZE_PKTS),
1601 EF10_DMA_STAT(port_rx_64, RX_64_PKTS),
1602 EF10_DMA_STAT(port_rx_65_to_127, RX_65_TO_127_PKTS),
1603 EF10_DMA_STAT(port_rx_128_to_255, RX_128_TO_255_PKTS),
1604 EF10_DMA_STAT(port_rx_256_to_511, RX_256_TO_511_PKTS),
1605 EF10_DMA_STAT(port_rx_512_to_1023, RX_512_TO_1023_PKTS),
1606 EF10_DMA_STAT(port_rx_1024_to_15xx, RX_1024_TO_15XX_PKTS),
1607 EF10_DMA_STAT(port_rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS),
1608 EF10_DMA_STAT(port_rx_gtjumbo, RX_GTJUMBO_PKTS),
1609 EF10_DMA_STAT(port_rx_bad_gtjumbo, RX_JABBER_PKTS),
1610 EF10_DMA_STAT(port_rx_overflow, RX_OVERFLOW_PKTS),
1611 EF10_DMA_STAT(port_rx_align_error, RX_ALIGN_ERROR_PKTS),
1612 EF10_DMA_STAT(port_rx_length_error, RX_LENGTH_ERROR_PKTS),
1613 EF10_DMA_STAT(port_rx_nodesc_drops, RX_NODESC_DROPS),
e4d112e4
EC		 1614 GENERIC_SW_STAT(rx_nodesc_trunc),
1615 GENERIC_SW_STAT(rx_noskb_drops),
e80ca013
DP		 1616 EF10_DMA_STAT(port_rx_pm_trunc_bb_overflow, PM_TRUNC_BB_OVERFLOW),
1617 EF10_DMA_STAT(port_rx_pm_discard_bb_overflow, PM_DISCARD_BB_OVERFLOW),
1618 EF10_DMA_STAT(port_rx_pm_trunc_vfifo_full, PM_TRUNC_VFIFO_FULL),
1619 EF10_DMA_STAT(port_rx_pm_discard_vfifo_full, PM_DISCARD_VFIFO_FULL),
1620 EF10_DMA_STAT(port_rx_pm_trunc_qbb, PM_TRUNC_QBB),
1621 EF10_DMA_STAT(port_rx_pm_discard_qbb, PM_DISCARD_QBB),
1622 EF10_DMA_STAT(port_rx_pm_discard_mapping, PM_DISCARD_MAPPING),
1623 EF10_DMA_STAT(port_rx_dp_q_disabled_packets, RXDP_Q_DISABLED_PKTS),
1624 EF10_DMA_STAT(port_rx_dp_di_dropped_packets, RXDP_DI_DROPPED_PKTS),
1625 EF10_DMA_STAT(port_rx_dp_streaming_packets, RXDP_STREAMING_PKTS),
1626 EF10_DMA_STAT(port_rx_dp_hlb_fetch, RXDP_HLB_FETCH_CONDITIONS),
1627 EF10_DMA_STAT(port_rx_dp_hlb_wait, RXDP_HLB_WAIT_CONDITIONS),
3c36a2ad
DP		 1628 EF10_DMA_STAT(rx_unicast, VADAPTER_RX_UNICAST_PACKETS),
1629 EF10_DMA_STAT(rx_unicast_bytes, VADAPTER_RX_UNICAST_BYTES),
1630 EF10_DMA_STAT(rx_multicast, VADAPTER_RX_MULTICAST_PACKETS),
1631 EF10_DMA_STAT(rx_multicast_bytes, VADAPTER_RX_MULTICAST_BYTES),
1632 EF10_DMA_STAT(rx_broadcast, VADAPTER_RX_BROADCAST_PACKETS),
1633 EF10_DMA_STAT(rx_broadcast_bytes, VADAPTER_RX_BROADCAST_BYTES),
1634 EF10_DMA_STAT(rx_bad, VADAPTER_RX_BAD_PACKETS),
1635 EF10_DMA_STAT(rx_bad_bytes, VADAPTER_RX_BAD_BYTES),
1636 EF10_DMA_STAT(rx_overflow, VADAPTER_RX_OVERFLOW),
1637 EF10_DMA_STAT(tx_unicast, VADAPTER_TX_UNICAST_PACKETS),
1638 EF10_DMA_STAT(tx_unicast_bytes, VADAPTER_TX_UNICAST_BYTES),
1639 EF10_DMA_STAT(tx_multicast, VADAPTER_TX_MULTICAST_PACKETS),
1640 EF10_DMA_STAT(tx_multicast_bytes, VADAPTER_TX_MULTICAST_BYTES),
1641 EF10_DMA_STAT(tx_broadcast, VADAPTER_TX_BROADCAST_PACKETS),
1642 EF10_DMA_STAT(tx_broadcast_bytes, VADAPTER_TX_BROADCAST_BYTES),
1643 EF10_DMA_STAT(tx_bad, VADAPTER_TX_BAD_PACKETS),
1644 EF10_DMA_STAT(tx_bad_bytes, VADAPTER_TX_BAD_BYTES),
1645 EF10_DMA_STAT(tx_overflow, VADAPTER_TX_OVERFLOW),
8127d661
BH		 1646};
1647
e80ca013
DP		 1648#define HUNT_COMMON_STAT_MASK ((1ULL << EF10_STAT_port_tx_bytes) | \
1649 (1ULL << EF10_STAT_port_tx_packets) | \
1650 (1ULL << EF10_STAT_port_tx_pause) | \
1651 (1ULL << EF10_STAT_port_tx_unicast) | \
1652 (1ULL << EF10_STAT_port_tx_multicast) | \
1653 (1ULL << EF10_STAT_port_tx_broadcast) | \
1654 (1ULL << EF10_STAT_port_rx_bytes) | \
1655 (1ULL << \
1656 EF10_STAT_port_rx_bytes_minus_good_bytes) | \
1657 (1ULL << EF10_STAT_port_rx_good_bytes) | \
1658 (1ULL << EF10_STAT_port_rx_bad_bytes) | \
1659 (1ULL << EF10_STAT_port_rx_packets) | \
1660 (1ULL << EF10_STAT_port_rx_good) | \
1661 (1ULL << EF10_STAT_port_rx_bad) | \
1662 (1ULL << EF10_STAT_port_rx_pause) | \
1663 (1ULL << EF10_STAT_port_rx_control) | \
1664 (1ULL << EF10_STAT_port_rx_unicast) | \
1665 (1ULL << EF10_STAT_port_rx_multicast) | \
1666 (1ULL << EF10_STAT_port_rx_broadcast) | \
1667 (1ULL << EF10_STAT_port_rx_lt64) | \
1668 (1ULL << EF10_STAT_port_rx_64) | \
1669 (1ULL << EF10_STAT_port_rx_65_to_127) | \
1670 (1ULL << EF10_STAT_port_rx_128_to_255) | \
1671 (1ULL << EF10_STAT_port_rx_256_to_511) | \
1672 (1ULL << EF10_STAT_port_rx_512_to_1023) |\
1673 (1ULL << EF10_STAT_port_rx_1024_to_15xx) |\
1674 (1ULL << EF10_STAT_port_rx_15xx_to_jumbo) |\
1675 (1ULL << EF10_STAT_port_rx_gtjumbo) | \
1676 (1ULL << EF10_STAT_port_rx_bad_gtjumbo) |\
1677 (1ULL << EF10_STAT_port_rx_overflow) | \
1678 (1ULL << EF10_STAT_port_rx_nodesc_drops) |\
e4d112e4
EC		 1679 (1ULL << GENERIC_STAT_rx_nodesc_trunc) | \
1680 (1ULL << GENERIC_STAT_rx_noskb_drops))
8127d661 1681
69b365c3
EC		 1682/* On 7000 series NICs, these statistics are only provided by the 10G MAC.
1683 * For a 10G/40G switchable port we do not expose these because they might
1684 * not include all the packets they should.
1685 * On 8000 series NICs these statistics are always provided.
8127d661 1686 */
e80ca013
DP		 1687#define HUNT_10G_ONLY_STAT_MASK ((1ULL << EF10_STAT_port_tx_control) | \
1688 (1ULL << EF10_STAT_port_tx_lt64) | \
1689 (1ULL << EF10_STAT_port_tx_64) | \
1690 (1ULL << EF10_STAT_port_tx_65_to_127) |\
1691 (1ULL << EF10_STAT_port_tx_128_to_255) |\
1692 (1ULL << EF10_STAT_port_tx_256_to_511) |\
1693 (1ULL << EF10_STAT_port_tx_512_to_1023) |\
1694 (1ULL << EF10_STAT_port_tx_1024_to_15xx) |\
1695 (1ULL << EF10_STAT_port_tx_15xx_to_jumbo))
8127d661
BH		 1696
1697/* These statistics are only provided by the 40G MAC. For a 10G/40G
1698 * switchable port we do expose these because the errors will otherwise
1699 * be silent.
1700 */
e80ca013
DP		 1701#define HUNT_40G_EXTRA_STAT_MASK ((1ULL << EF10_STAT_port_rx_align_error) |\
1702 (1ULL << EF10_STAT_port_rx_length_error))
8127d661 1703
568d7a00
EC		 1704/* These statistics are only provided if the firmware supports the
1705 * capability PM_AND_RXDP_COUNTERS.
1706 */
1707#define HUNT_PM_AND_RXDP_STAT_MASK ( \
e80ca013
DP		 1708 (1ULL << EF10_STAT_port_rx_pm_trunc_bb_overflow) | \
1709 (1ULL << EF10_STAT_port_rx_pm_discard_bb_overflow) | \
1710 (1ULL << EF10_STAT_port_rx_pm_trunc_vfifo_full) | \
1711 (1ULL << EF10_STAT_port_rx_pm_discard_vfifo_full) | \
1712 (1ULL << EF10_STAT_port_rx_pm_trunc_qbb) | \
1713 (1ULL << EF10_STAT_port_rx_pm_discard_qbb) | \
1714 (1ULL << EF10_STAT_port_rx_pm_discard_mapping) | \
1715 (1ULL << EF10_STAT_port_rx_dp_q_disabled_packets) | \
1716 (1ULL << EF10_STAT_port_rx_dp_di_dropped_packets) | \
1717 (1ULL << EF10_STAT_port_rx_dp_streaming_packets) | \
1718 (1ULL << EF10_STAT_port_rx_dp_hlb_fetch) | \
1719 (1ULL << EF10_STAT_port_rx_dp_hlb_wait))
568d7a00 1720
4bae913b 1721static u64 efx_ef10_raw_stat_mask(struct efx_nic *efx)
8127d661 1722{
4bae913b 1723 u64 raw_mask = HUNT_COMMON_STAT_MASK;
8127d661 1724 u32 port_caps = efx_mcdi_phy_get_caps(efx);
568d7a00 1725 struct efx_ef10_nic_data *nic_data = efx->nic_data;
8127d661 1726
3c36a2ad
DP		 1727 if (!(efx->mcdi->fn_flags &
1728 1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL))
1729 return 0;
1730
69b365c3 1731 if (port_caps & (1 << MC_CMD_PHY_CAP_40000FDX_LBN)) {
4bae913b 1732 raw_mask |= HUNT_40G_EXTRA_STAT_MASK;
69b365c3
EC		 1733 /* 8000 series have everything even at 40G */
1734 if (nic_data->datapath_caps2 &
1735 (1 << MC_CMD_GET_CAPABILITIES_V2_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN))
1736 raw_mask |= HUNT_10G_ONLY_STAT_MASK;
1737 } else {
4bae913b 1738 raw_mask |= HUNT_10G_ONLY_STAT_MASK;
69b365c3 1739 }
568d7a00
EC		 1740
1741 if (nic_data->datapath_caps &
1742 (1 << MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN))
1743 raw_mask |= HUNT_PM_AND_RXDP_STAT_MASK;
1744
4bae913b
EC		 1745 return raw_mask;
1746}
1747
1748static void efx_ef10_get_stat_mask(struct efx_nic *efx, unsigned long *mask)
1749{
d94619cd 1750 struct efx_ef10_nic_data *nic_data = efx->nic_data;
3c36a2ad
DP		 1751 u64 raw_mask[2];
1752
1753 raw_mask[0] = efx_ef10_raw_stat_mask(efx);
1754
d94619cd
DP		 1755 /* Only show vadaptor stats when EVB capability is present */
1756 if (nic_data->datapath_caps &
1757 (1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN)) {
1758 raw_mask[0] |= ~((1ULL << EF10_STAT_rx_unicast) - 1);
1759 raw_mask[1] = (1ULL << (EF10_STAT_COUNT - 63)) - 1;
1760 } else {
1761 raw_mask[1] = 0;
1762 }
4bae913b
EC		 1763
1764#if BITS_PER_LONG == 64
e70c70c3 1765 BUILD_BUG_ON(BITS_TO_LONGS(EF10_STAT_COUNT) != 2);
3c36a2ad
DP		 1766 mask[0] = raw_mask[0];
1767 mask[1] = raw_mask[1];
4bae913b 1768#else
e70c70c3 1769 BUILD_BUG_ON(BITS_TO_LONGS(EF10_STAT_COUNT) != 3);
3c36a2ad
DP		 1770 mask[0] = raw_mask[0] & 0xffffffff;
1771 mask[1] = raw_mask[0] >> 32;
1772 mask[2] = raw_mask[1] & 0xffffffff;
4bae913b 1773#endif
8127d661
BH		 1774}
1775
1776static size_t efx_ef10_describe_stats(struct efx_nic *efx, u8 *names)
1777{
4bae913b
EC		 1778 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1779
1780 efx_ef10_get_stat_mask(efx, mask);
8127d661 1781 return efx_nic_describe_stats(efx_ef10_stat_desc, EF10_STAT_COUNT,
4bae913b 1782 mask, names);
8127d661
BH		 1783}
1784
d7788196
DP		 1785static size_t efx_ef10_update_stats_common(struct efx_nic *efx, u64 *full_stats,
1786 struct rtnl_link_stats64 *core_stats)
1787{
1788 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1789 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1790 u64 *stats = nic_data->stats;
1791 size_t stats_count = 0, index;
1792
1793 efx_ef10_get_stat_mask(efx, mask);
1794
1795 if (full_stats) {
1796 for_each_set_bit(index, mask, EF10_STAT_COUNT) {
1797 if (efx_ef10_stat_desc[index].name) {
1798 *full_stats++ = stats[index];
1799 ++stats_count;
1800 }
1801 }
1802 }
1803
fbe4307e
BK		 1804 if (!core_stats)
1805 return stats_count;
1806
1807 if (nic_data->datapath_caps &
1808 1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN) {
1809 /* Use vadaptor stats. */
0fc95fca
DP		 1810 core_stats->rx_packets = stats[EF10_STAT_rx_unicast] +
1811 stats[EF10_STAT_rx_multicast] +
1812 stats[EF10_STAT_rx_broadcast];
1813 core_stats->tx_packets = stats[EF10_STAT_tx_unicast] +
1814 stats[EF10_STAT_tx_multicast] +
1815 stats[EF10_STAT_tx_broadcast];
1816 core_stats->rx_bytes = stats[EF10_STAT_rx_unicast_bytes] +
1817 stats[EF10_STAT_rx_multicast_bytes] +
1818 stats[EF10_STAT_rx_broadcast_bytes];
1819 core_stats->tx_bytes = stats[EF10_STAT_tx_unicast_bytes] +
1820 stats[EF10_STAT_tx_multicast_bytes] +
1821 stats[EF10_STAT_tx_broadcast_bytes];
1822 core_stats->rx_dropped = stats[GENERIC_STAT_rx_nodesc_trunc] +
d7788196 1823 stats[GENERIC_STAT_rx_noskb_drops];
0fc95fca
DP		 1824 core_stats->multicast = stats[EF10_STAT_rx_multicast];
1825 core_stats->rx_crc_errors = stats[EF10_STAT_rx_bad];
1826 core_stats->rx_fifo_errors = stats[EF10_STAT_rx_overflow];
1827 core_stats->rx_errors = core_stats->rx_crc_errors;
1828 core_stats->tx_errors = stats[EF10_STAT_tx_bad];
fbe4307e
BK		 1829 } else {
1830 /* Use port stats. */
1831 core_stats->rx_packets = stats[EF10_STAT_port_rx_packets];
1832 core_stats->tx_packets = stats[EF10_STAT_port_tx_packets];
1833 core_stats->rx_bytes = stats[EF10_STAT_port_rx_bytes];
1834 core_stats->tx_bytes = stats[EF10_STAT_port_tx_bytes];
1835 core_stats->rx_dropped = stats[EF10_STAT_port_rx_nodesc_drops] +
1836 stats[GENERIC_STAT_rx_nodesc_trunc] +
1837 stats[GENERIC_STAT_rx_noskb_drops];
1838 core_stats->multicast = stats[EF10_STAT_port_rx_multicast];
1839 core_stats->rx_length_errors =
1840 stats[EF10_STAT_port_rx_gtjumbo] +
1841 stats[EF10_STAT_port_rx_length_error];
1842 core_stats->rx_crc_errors = stats[EF10_STAT_port_rx_bad];
1843 core_stats->rx_frame_errors =
1844 stats[EF10_STAT_port_rx_align_error];
1845 core_stats->rx_fifo_errors = stats[EF10_STAT_port_rx_overflow];
1846 core_stats->rx_errors = (core_stats->rx_length_errors +
1847 core_stats->rx_crc_errors +
1848 core_stats->rx_frame_errors);
d7788196
DP		 1849 }
1850
1851 return stats_count;
1852}
1853
1854static int efx_ef10_try_update_nic_stats_pf(struct efx_nic *efx)
8127d661
BH		 1855{
1856 struct efx_ef10_nic_data *nic_data = efx->nic_data;
4bae913b 1857 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
8127d661
BH		 1858 __le64 generation_start, generation_end;
1859 u64 *stats = nic_data->stats;
1860 __le64 *dma_stats;
1861
4bae913b
EC		 1862 efx_ef10_get_stat_mask(efx, mask);
1863
8127d661 1864 dma_stats = efx->stats_buffer.addr;
8127d661 1865
c1be4821 1866 generation_end = dma_stats[efx->num_mac_stats - 1];
8127d661
BH		 1867 if (generation_end == EFX_MC_STATS_GENERATION_INVALID)
1868 return 0;
1869 rmb();
4bae913b 1870 efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask,
8127d661 1871 stats, efx->stats_buffer.addr, false);
d546a893 1872 rmb();
8127d661
BH		 1873 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
1874 if (generation_end != generation_start)
1875 return -EAGAIN;
1876
1877 /* Update derived statistics */
e80ca013
DP		 1878 efx_nic_fix_nodesc_drop_stat(efx,
1879 &stats[EF10_STAT_port_rx_nodesc_drops]);
1880 stats[EF10_STAT_port_rx_good_bytes] =
1881 stats[EF10_STAT_port_rx_bytes] -
1882 stats[EF10_STAT_port_rx_bytes_minus_good_bytes];
1883 efx_update_diff_stat(&stats[EF10_STAT_port_rx_bad_bytes],
1884 stats[EF10_STAT_port_rx_bytes_minus_good_bytes]);
e4d112e4 1885 efx_update_sw_stats(efx, stats);
8127d661
BH		 1886 return 0;
1887}
1888
1889
d7788196
DP		 1890static size_t efx_ef10_update_stats_pf(struct efx_nic *efx, u64 *full_stats,
1891 struct rtnl_link_stats64 *core_stats)
8127d661 1892{
8127d661
BH		 1893 int retry;
1894
1895 /* If we're unlucky enough to read statistics during the DMA, wait
1896 * up to 10ms for it to finish (typically takes <500us)
1897 */
1898 for (retry = 0; retry < 100; ++retry) {
d7788196 1899 if (efx_ef10_try_update_nic_stats_pf(efx) == 0)
8127d661
BH		 1900 break;
1901 udelay(100);
1902 }
1903
d7788196
DP		 1904 return efx_ef10_update_stats_common(efx, full_stats, core_stats);
1905}
8127d661 1906
d7788196
DP		 1907static int efx_ef10_try_update_nic_stats_vf(struct efx_nic *efx)
1908{
1909 MCDI_DECLARE_BUF(inbuf, MC_CMD_MAC_STATS_IN_LEN);
1910 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1911 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1912 __le64 generation_start, generation_end;
1913 u64 *stats = nic_data->stats;
c1be4821 1914 u32 dma_len = efx->num_mac_stats * sizeof(u64);
d7788196
DP		 1915 struct efx_buffer stats_buf;
1916 __le64 *dma_stats;
1917 int rc;
1918
f00bf230
DP		 1919 spin_unlock_bh(&efx->stats_lock);
1920
1921 if (in_interrupt()) {
1922 /* If in atomic context, cannot update stats. Just update the
1923 * software stats and return so the caller can continue.
1924 */
1925 spin_lock_bh(&efx->stats_lock);
1926 efx_update_sw_stats(efx, stats);
1927 return 0;
1928 }
1929
d7788196
DP		 1930 efx_ef10_get_stat_mask(efx, mask);
1931
1932 rc = efx_nic_alloc_buffer(efx, &stats_buf, dma_len, GFP_ATOMIC);
f00bf230
DP		 1933 if (rc) {
1934 spin_lock_bh(&efx->stats_lock);
d7788196 1935 return rc;
f00bf230 1936 }
d7788196
DP		 1937
1938 dma_stats = stats_buf.addr;
c1be4821 1939 dma_stats[efx->num_mac_stats - 1] = EFX_MC_STATS_GENERATION_INVALID;
d7788196
DP		 1940
1941 MCDI_SET_QWORD(inbuf, MAC_STATS_IN_DMA_ADDR, stats_buf.dma_addr);
1942 MCDI_POPULATE_DWORD_1(inbuf, MAC_STATS_IN_CMD,
0fc95fca 1943 MAC_STATS_IN_DMA, 1);
d7788196
DP		 1944 MCDI_SET_DWORD(inbuf, MAC_STATS_IN_DMA_LEN, dma_len);
1945 MCDI_SET_DWORD(inbuf, MAC_STATS_IN_PORT_ID, EVB_PORT_ID_ASSIGNED);
1946
6dd4859b
DP		 1947 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_MAC_STATS, inbuf, sizeof(inbuf),
1948 NULL, 0, NULL);
d7788196 1949 spin_lock_bh(&efx->stats_lock);
6dd4859b
DP		 1950 if (rc) {
1951 /* Expect ENOENT if DMA queues have not been set up */
1952 if (rc != -ENOENT || atomic_read(&efx->active_queues))
1953 efx_mcdi_display_error(efx, MC_CMD_MAC_STATS,
1954 sizeof(inbuf), NULL, 0, rc);
d7788196 1955 goto out;
6dd4859b 1956 }
d7788196 1957
c1be4821 1958 generation_end = dma_stats[efx->num_mac_stats - 1];
0fc95fca
DP		 1959 if (generation_end == EFX_MC_STATS_GENERATION_INVALID) {
1960 WARN_ON_ONCE(1);
d7788196 1961 goto out;
0fc95fca 1962 }
d7788196
DP		 1963 rmb();
1964 efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask,
1965 stats, stats_buf.addr, false);
1966 rmb();
1967 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
1968 if (generation_end != generation_start) {
1969 rc = -EAGAIN;
1970 goto out;
8127d661
BH		 1971 }
1972
d7788196
DP		 1973 efx_update_sw_stats(efx, stats);
1974out:
1975 efx_nic_free_buffer(efx, &stats_buf);
1976 return rc;
1977}
1978
1979static size_t efx_ef10_update_stats_vf(struct efx_nic *efx, u64 *full_stats,
1980 struct rtnl_link_stats64 *core_stats)
1981{
1982 if (efx_ef10_try_update_nic_stats_vf(efx))
1983 return 0;
1984
1985 return efx_ef10_update_stats_common(efx, full_stats, core_stats);
8127d661
BH		 1986}
1987
1988static void efx_ef10_push_irq_moderation(struct efx_channel *channel)
1989{
1990 struct efx_nic *efx = channel->efx;
539de7c5 1991 unsigned int mode, usecs;
8127d661
BH		 1992 efx_dword_t timer_cmd;
1993
539de7c5 1994 if (channel->irq_moderation_us) {
8127d661 1995 mode = 3;
539de7c5 1996 usecs = channel->irq_moderation_us;
8127d661
BH		 1997 } else {
1998 mode = 0;
539de7c5 1999 usecs = 0;
8127d661
BH		 2000 }
2001
539de7c5
BK		 2002 if (EFX_EF10_WORKAROUND_61265(efx)) {
2003 MCDI_DECLARE_BUF(inbuf, MC_CMD_SET_EVQ_TMR_IN_LEN);
2004 unsigned int ns = usecs * 1000;
2005
2006 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_INSTANCE,
2007 channel->channel);
2008 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_LOAD_REQ_NS, ns);
2009 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_RELOAD_REQ_NS, ns);
2010 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_MODE, mode);
2011
2012 efx_mcdi_rpc_async(efx, MC_CMD_SET_EVQ_TMR,
2013 inbuf, sizeof(inbuf), 0, NULL, 0);
2014 } else if (EFX_EF10_WORKAROUND_35388(efx)) {
2015 unsigned int ticks = efx_usecs_to_ticks(efx, usecs);
2016
8127d661
BH		 2017 EFX_POPULATE_DWORD_3(timer_cmd, ERF_DD_EVQ_IND_TIMER_FLAGS,
2018 EFE_DD_EVQ_IND_TIMER_FLAGS,
2019 ERF_DD_EVQ_IND_TIMER_MODE, mode,
539de7c5 2020 ERF_DD_EVQ_IND_TIMER_VAL, ticks);
8127d661
BH		 2021 efx_writed_page(efx, &timer_cmd, ER_DD_EVQ_INDIRECT,
2022 channel->channel);
2023 } else {
539de7c5
BK		 2024 unsigned int ticks = efx_usecs_to_ticks(efx, usecs);
2025
0bc959a9
BK		 2026 EFX_POPULATE_DWORD_3(timer_cmd, ERF_DZ_TC_TIMER_MODE, mode,
2027 ERF_DZ_TC_TIMER_VAL, ticks,
2028 ERF_FZ_TC_TMR_REL_VAL, ticks);
8127d661
BH		 2029 efx_writed_page(efx, &timer_cmd, ER_DZ_EVQ_TMR,
2030 channel->channel);
2031 }
2032}
2033
02246a7f
SS		 2034static void efx_ef10_get_wol_vf(struct efx_nic *efx,
2035 struct ethtool_wolinfo *wol) {}
2036
2037static int efx_ef10_set_wol_vf(struct efx_nic *efx, u32 type)
2038{
2039 return -EOPNOTSUPP;
2040}
2041
8127d661
BH		 2042static void efx_ef10_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
2043{
2044 wol->supported = 0;
2045 wol->wolopts = 0;
2046 memset(&wol->sopass, 0, sizeof(wol->sopass));
2047}
2048
2049static int efx_ef10_set_wol(struct efx_nic *efx, u32 type)
2050{
2051 if (type != 0)
2052 return -EINVAL;
2053 return 0;
2054}
2055
2056static void efx_ef10_mcdi_request(struct efx_nic *efx,
2057 const efx_dword_t *hdr, size_t hdr_len,
2058 const efx_dword_t *sdu, size_t sdu_len)
2059{
2060 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2061 u8 *pdu = nic_data->mcdi_buf.addr;
2062
2063 memcpy(pdu, hdr, hdr_len);
2064 memcpy(pdu + hdr_len, sdu, sdu_len);
2065 wmb();
2066
2067 /* The hardware provides 'low' and 'high' (doorbell) registers
2068 * for passing the 64-bit address of an MCDI request to
2069 * firmware. However the dwords are swapped by firmware. The
2070 * least significant bits of the doorbell are then 0 for all
2071 * MCDI requests due to alignment.
2072 */
2073 _efx_writed(efx, cpu_to_le32((u64)nic_data->mcdi_buf.dma_addr >> 32),
2074 ER_DZ_MC_DB_LWRD);
2075 _efx_writed(efx, cpu_to_le32((u32)nic_data->mcdi_buf.dma_addr),
2076 ER_DZ_MC_DB_HWRD);
2077}
2078
2079static bool efx_ef10_mcdi_poll_response(struct efx_nic *efx)
2080{
2081 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2082 const efx_dword_t hdr = *(const efx_dword_t *)nic_data->mcdi_buf.addr;
2083
2084 rmb();
2085 return EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE);
2086}
2087
2088static void
2089efx_ef10_mcdi_read_response(struct efx_nic *efx, efx_dword_t *outbuf,
2090 size_t offset, size_t outlen)
2091{
2092 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2093 const u8 *pdu = nic_data->mcdi_buf.addr;
2094
2095 memcpy(outbuf, pdu + offset, outlen);
2096}
2097
c577e59e
DP		 2098static void efx_ef10_mcdi_reboot_detected(struct efx_nic *efx)
2099{
2100 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2101
2102 /* All our allocations have been reset */
2103 efx_ef10_reset_mc_allocations(efx);
2104
2105 /* The datapath firmware might have been changed */
2106 nic_data->must_check_datapath_caps = true;
2107
2108 /* MAC statistics have been cleared on the NIC; clear the local
2109 * statistic that we update with efx_update_diff_stat().
2110 */
2111 nic_data->stats[EF10_STAT_port_rx_bad_bytes] = 0;
2112}
2113
8127d661
BH		 2114static int efx_ef10_mcdi_poll_reboot(struct efx_nic *efx)
2115{
2116 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2117 int rc;
2118
2119 rc = efx_ef10_get_warm_boot_count(efx);
2120 if (rc < 0) {
2121 /* The firmware is presumably in the process of
2122 * rebooting. However, we are supposed to report each
2123 * reboot just once, so we must only do that once we
2124 * can read and store the updated warm boot count.
2125 */
2126 return 0;
2127 }
2128
2129 if (rc == nic_data->warm_boot_count)
2130 return 0;
2131
2132 nic_data->warm_boot_count = rc;
c577e59e 2133 efx_ef10_mcdi_reboot_detected(efx);
869070c5 2134
8127d661
BH		 2135 return -EIO;
2136}
2137
2138/* Handle an MSI interrupt
2139 *
2140 * Handle an MSI hardware interrupt. This routine schedules event
2141 * queue processing. No interrupt acknowledgement cycle is necessary.
2142 * Also, we never need to check that the interrupt is for us, since
2143 * MSI interrupts cannot be shared.
2144 */
2145static irqreturn_t efx_ef10_msi_interrupt(int irq, void *dev_id)
2146{
2147 struct efx_msi_context *context = dev_id;
2148 struct efx_nic *efx = context->efx;
2149
2150 netif_vdbg(efx, intr, efx->net_dev,
2151 "IRQ %d on CPU %d\n", irq, raw_smp_processor_id());
2152
6aa7de05 2153 if (likely(READ_ONCE(efx->irq_soft_enabled))) {
8127d661
BH		 2154 /* Note test interrupts */
2155 if (context->index == efx->irq_level)
2156 efx->last_irq_cpu = raw_smp_processor_id();
2157
2158 /* Schedule processing of the channel */
2159 efx_schedule_channel_irq(efx->channel[context->index]);
2160 }
2161
2162 return IRQ_HANDLED;
2163}
2164
2165static irqreturn_t efx_ef10_legacy_interrupt(int irq, void *dev_id)
2166{
2167 struct efx_nic *efx = dev_id;
6aa7de05 2168 bool soft_enabled = READ_ONCE(efx->irq_soft_enabled);
8127d661
BH		 2169 struct efx_channel *channel;
2170 efx_dword_t reg;
2171 u32 queues;
2172
2173 /* Read the ISR which also ACKs the interrupts */
2174 efx_readd(efx, &reg, ER_DZ_BIU_INT_ISR);
2175 queues = EFX_DWORD_FIELD(reg, ERF_DZ_ISR_REG);
2176
2177 if (queues == 0)
2178 return IRQ_NONE;
2179
2180 if (likely(soft_enabled)) {
2181 /* Note test interrupts */
2182 if (queues & (1U << efx->irq_level))
2183 efx->last_irq_cpu = raw_smp_processor_id();
2184
2185 efx_for_each_channel(channel, efx) {
2186 if (queues & 1)
2187 efx_schedule_channel_irq(channel);
2188 queues >>= 1;
2189 }
2190 }
2191
2192 netif_vdbg(efx, intr, efx->net_dev,
2193 "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
2194 irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
2195
2196 return IRQ_HANDLED;
2197}
2198
942e298e 2199static int efx_ef10_irq_test_generate(struct efx_nic *efx)
8127d661
BH		 2200{
2201 MCDI_DECLARE_BUF(inbuf, MC_CMD_TRIGGER_INTERRUPT_IN_LEN);
2202
942e298e
JC		 2203 if (efx_mcdi_set_workaround(efx, MC_CMD_WORKAROUND_BUG41750, true,
2204 NULL) == 0)
2205 return -ENOTSUPP;
2206
8127d661
BH		 2207 BUILD_BUG_ON(MC_CMD_TRIGGER_INTERRUPT_OUT_LEN != 0);
2208
2209 MCDI_SET_DWORD(inbuf, TRIGGER_INTERRUPT_IN_INTR_LEVEL, efx->irq_level);
942e298e 2210 return efx_mcdi_rpc(efx, MC_CMD_TRIGGER_INTERRUPT,
8127d661
BH		 2211 inbuf, sizeof(inbuf), NULL, 0, NULL);
2212}
2213
2214static int efx_ef10_tx_probe(struct efx_tx_queue *tx_queue)
2215{
2216 return efx_nic_alloc_buffer(tx_queue->efx, &tx_queue->txd.buf,
2217 (tx_queue->ptr_mask + 1) *
2218 sizeof(efx_qword_t),
2219 GFP_KERNEL);
2220}
2221
2222/* This writes to the TX_DESC_WPTR and also pushes data */
2223static inline void efx_ef10_push_tx_desc(struct efx_tx_queue *tx_queue,
2224 const efx_qword_t *txd)
2225{
2226 unsigned int write_ptr;
2227 efx_oword_t reg;
2228
2229 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
2230 EFX_POPULATE_OWORD_1(reg, ERF_DZ_TX_DESC_WPTR, write_ptr);
2231 reg.qword[0] = *txd;
2232 efx_writeo_page(tx_queue->efx, &reg,
2233 ER_DZ_TX_DESC_UPD, tx_queue->queue);
2234}
2235
e9117e50
BK		 2236/* Add Firmware-Assisted TSO v2 option descriptors to a queue.
2237 */
2238static int efx_ef10_tx_tso_desc(struct efx_tx_queue *tx_queue,
2239 struct sk_buff *skb,
2240 bool *data_mapped)
2241{
2242 struct efx_tx_buffer *buffer;
2243 struct tcphdr *tcp;
2244 struct iphdr *ip;
2245
2246 u16 ipv4_id;
2247 u32 seqnum;
2248 u32 mss;
2249
e01b16a7 2250 EFX_WARN_ON_ONCE_PARANOID(tx_queue->tso_version != 2);
e9117e50
BK		 2251
2252 mss = skb_shinfo(skb)->gso_size;
2253
2254 if (unlikely(mss < 4)) {
2255 WARN_ONCE(1, "MSS of %u is too small for TSO v2\n", mss);
2256 return -EINVAL;
2257 }
2258
2259 ip = ip_hdr(skb);
2260 if (ip->version == 4) {
2261 /* Modify IPv4 header if needed. */
2262 ip->tot_len = 0;
2263 ip->check = 0;
6d43131c 2264 ipv4_id = ntohs(ip->id);
e9117e50
BK		 2265 } else {
2266 /* Modify IPv6 header if needed. */
2267 struct ipv6hdr *ipv6 = ipv6_hdr(skb);
2268
2269 ipv6->payload_len = 0;
2270 ipv4_id = 0;
2271 }
2272
2273 tcp = tcp_hdr(skb);
2274 seqnum = ntohl(tcp->seq);
2275
2276 buffer = efx_tx_queue_get_insert_buffer(tx_queue);
2277
2278 buffer->flags = EFX_TX_BUF_OPTION;
2279 buffer->len = 0;
2280 buffer->unmap_len = 0;
2281 EFX_POPULATE_QWORD_5(buffer->option,
2282 ESF_DZ_TX_DESC_IS_OPT, 1,
2283 ESF_DZ_TX_OPTION_TYPE, ESE_DZ_TX_OPTION_DESC_TSO,
2284 ESF_DZ_TX_TSO_OPTION_TYPE,
2285 ESE_DZ_TX_TSO_OPTION_DESC_FATSO2A,
2286 ESF_DZ_TX_TSO_IP_ID, ipv4_id,
2287 ESF_DZ_TX_TSO_TCP_SEQNO, seqnum
2288 );
2289 ++tx_queue->insert_count;
2290
2291 buffer = efx_tx_queue_get_insert_buffer(tx_queue);
2292
2293 buffer->flags = EFX_TX_BUF_OPTION;
2294 buffer->len = 0;
2295 buffer->unmap_len = 0;
2296 EFX_POPULATE_QWORD_4(buffer->option,
2297 ESF_DZ_TX_DESC_IS_OPT, 1,
2298 ESF_DZ_TX_OPTION_TYPE, ESE_DZ_TX_OPTION_DESC_TSO,
2299 ESF_DZ_TX_TSO_OPTION_TYPE,
2300 ESE_DZ_TX_TSO_OPTION_DESC_FATSO2B,
2301 ESF_DZ_TX_TSO_TCP_MSS, mss
2302 );
2303 ++tx_queue->insert_count;
2304
2305 return 0;
2306}
2307
46d1efd8
EC		 2308static u32 efx_ef10_tso_versions(struct efx_nic *efx)
2309{
2310 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2311 u32 tso_versions = 0;
2312
2313 if (nic_data->datapath_caps &
2314 (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN))
2315 tso_versions |= BIT(1);
2316 if (nic_data->datapath_caps2 &
2317 (1 << MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_LBN))
2318 tso_versions |= BIT(2);
2319 return tso_versions;
2320}
2321
8127d661
BH		 2322static void efx_ef10_tx_init(struct efx_tx_queue *tx_queue)
2323{
2324 MCDI_DECLARE_BUF(inbuf, MC_CMD_INIT_TXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
2325 EFX_BUF_SIZE));
8127d661
BH		 2326 bool csum_offload = tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD;
2327 size_t entries = tx_queue->txd.buf.len / EFX_BUF_SIZE;
2328 struct efx_channel *channel = tx_queue->channel;
2329 struct efx_nic *efx = tx_queue->efx;
45b2449e 2330 struct efx_ef10_nic_data *nic_data = efx->nic_data;
e9117e50 2331 bool tso_v2 = false;
aa09a3da 2332 size_t inlen;
8127d661
BH		 2333 dma_addr_t dma_addr;
2334 efx_qword_t *txd;
2335 int rc;
2336 int i;
aa09a3da 2337 BUILD_BUG_ON(MC_CMD_INIT_TXQ_OUT_LEN != 0);
8127d661 2338
e9117e50
BK		 2339 /* TSOv2 is a limited resource that can only be configured on a limited
2340 * number of queues. TSO without checksum offload is not really a thing,
2341 * so we only enable it for those queues.
e9117e50
BK		 2342 */
2343 if (csum_offload && (nic_data->datapath_caps2 &
2344 (1 << MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_LBN))) {
2345 tso_v2 = true;
2346 netif_dbg(efx, hw, efx->net_dev, "Using TSOv2 for channel %u\n",
2347 channel->channel);
2348 }
2349
8127d661
BH		 2350 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_SIZE, tx_queue->ptr_mask + 1);
2351 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_TARGET_EVQ, channel->channel);
2352 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_LABEL, tx_queue->queue);
2353 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_INSTANCE, tx_queue->queue);
8127d661 2354 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_OWNER_ID, 0);
45b2449e 2355 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_PORT_ID, nic_data->vport_id);
8127d661
BH		 2356
2357 dma_addr = tx_queue->txd.buf.dma_addr;
2358
2359 netif_dbg(efx, hw, efx->net_dev, "pushing TXQ %d. %zu entries (%llx)\n",
2360 tx_queue->queue, entries, (u64)dma_addr);
2361
2362 for (i = 0; i < entries; ++i) {
2363 MCDI_SET_ARRAY_QWORD(inbuf, INIT_TXQ_IN_DMA_ADDR, i, dma_addr);
2364 dma_addr += EFX_BUF_SIZE;
2365 }
2366
2367 inlen = MC_CMD_INIT_TXQ_IN_LEN(entries);
2368
e638ee1d
EC		 2369 do {
2370 MCDI_POPULATE_DWORD_3(inbuf, INIT_TXQ_IN_FLAGS,
2371 /* This flag was removed from mcdi_pcol.h for
2372 * the non-_EXT version of INIT_TXQ. However,
2373 * firmware still honours it.
2374 */
2375 INIT_TXQ_EXT_IN_FLAG_TSOV2_EN, tso_v2,
2376 INIT_TXQ_IN_FLAG_IP_CSUM_DIS, !csum_offload,
2377 INIT_TXQ_IN_FLAG_TCP_CSUM_DIS, !csum_offload);
2378
2379 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_INIT_TXQ, inbuf, inlen,
2380 NULL, 0, NULL);
2381 if (rc == -ENOSPC && tso_v2) {
2382 /* Retry without TSOv2 if we're short on contexts. */
2383 tso_v2 = false;
2384 netif_warn(efx, probe, efx->net_dev,
2385 "TSOv2 context not available to segment in hardware. TCP performance may be reduced.\n");
2386 } else if (rc) {
2387 efx_mcdi_display_error(efx, MC_CMD_INIT_TXQ,
2388 MC_CMD_INIT_TXQ_EXT_IN_LEN,
2389 NULL, 0, rc);
2390 goto fail;
2391 }
2392 } while (rc);
8127d661
BH		 2393
2394 /* A previous user of this TX queue might have set us up the
2395 * bomb by writing a descriptor to the TX push collector but
2396 * not the doorbell. (Each collector belongs to a port, not a
2397 * queue or function, so cannot easily be reset.) We must
2398 * attempt to push a no-op descriptor in its place.
2399 */
2400 tx_queue->buffer[0].flags = EFX_TX_BUF_OPTION;
2401 tx_queue->insert_count = 1;
2402 txd = efx_tx_desc(tx_queue, 0);
2403 EFX_POPULATE_QWORD_4(*txd,
2404 ESF_DZ_TX_DESC_IS_OPT, true,
2405 ESF_DZ_TX_OPTION_TYPE,
2406 ESE_DZ_TX_OPTION_DESC_CRC_CSUM,
2407 ESF_DZ_TX_OPTION_UDP_TCP_CSUM, csum_offload,
2408 ESF_DZ_TX_OPTION_IP_CSUM, csum_offload);
2409 tx_queue->write_count = 1;
93171b14 2410
e9117e50
BK		 2411 if (tso_v2) {
2412 tx_queue->handle_tso = efx_ef10_tx_tso_desc;
2413 tx_queue->tso_version = 2;
2414 } else if (nic_data->datapath_caps &
2415 (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN)) {
93171b14
BK		 2416 tx_queue->tso_version = 1;
2417 }
2418
8127d661
BH		 2419 wmb();
2420 efx_ef10_push_tx_desc(tx_queue, txd);
2421
2422 return;
2423
2424fail:
48ce5634
BH		 2425 netdev_WARN(efx->net_dev, "failed to initialise TXQ %d\n",
2426 tx_queue->queue);
8127d661
BH		 2427}
2428
2429static void efx_ef10_tx_fini(struct efx_tx_queue *tx_queue)
2430{
2431 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_TXQ_IN_LEN);
aa09a3da 2432 MCDI_DECLARE_BUF_ERR(outbuf);
8127d661
BH		 2433 struct efx_nic *efx = tx_queue->efx;
2434 size_t outlen;
2435 int rc;
2436
2437 MCDI_SET_DWORD(inbuf, FINI_TXQ_IN_INSTANCE,
2438 tx_queue->queue);
2439
1e0b8120 2440 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_TXQ, inbuf, sizeof(inbuf),
8127d661
BH		 2441 outbuf, sizeof(outbuf), &outlen);
2442
2443 if (rc && rc != -EALREADY)
2444 goto fail;
2445
2446 return;
2447
2448fail:
1e0b8120
EC		 2449 efx_mcdi_display_error(efx, MC_CMD_FINI_TXQ, MC_CMD_FINI_TXQ_IN_LEN,
2450 outbuf, outlen, rc);
8127d661
BH		 2451}
2452
2453static void efx_ef10_tx_remove(struct efx_tx_queue *tx_queue)
2454{
2455 efx_nic_free_buffer(tx_queue->efx, &tx_queue->txd.buf);
2456}
2457
2458/* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
2459static inline void efx_ef10_notify_tx_desc(struct efx_tx_queue *tx_queue)
2460{
2461 unsigned int write_ptr;
2462 efx_dword_t reg;
2463
2464 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
2465 EFX_POPULATE_DWORD_1(reg, ERF_DZ_TX_DESC_WPTR_DWORD, write_ptr);
2466 efx_writed_page(tx_queue->efx, &reg,
2467 ER_DZ_TX_DESC_UPD_DWORD, tx_queue->queue);
2468}
2469
e9117e50
BK		 2470#define EFX_EF10_MAX_TX_DESCRIPTOR_LEN 0x3fff
2471
2472static unsigned int efx_ef10_tx_limit_len(struct efx_tx_queue *tx_queue,
2473 dma_addr_t dma_addr, unsigned int len)
2474{
2475 if (len > EFX_EF10_MAX_TX_DESCRIPTOR_LEN) {
2476 /* If we need to break across multiple descriptors we should
2477 * stop at a page boundary. This assumes the length limit is
2478 * greater than the page size.
2479 */
2480 dma_addr_t end = dma_addr + EFX_EF10_MAX_TX_DESCRIPTOR_LEN;
2481
2482 BUILD_BUG_ON(EFX_EF10_MAX_TX_DESCRIPTOR_LEN < EFX_PAGE_SIZE);
2483 len = (end & (~(EFX_PAGE_SIZE - 1))) - dma_addr;
2484 }
2485
2486 return len;
2487}
2488
8127d661
BH		 2489static void efx_ef10_tx_write(struct efx_tx_queue *tx_queue)
2490{
2491 unsigned int old_write_count = tx_queue->write_count;
2492 struct efx_tx_buffer *buffer;
2493 unsigned int write_ptr;
2494 efx_qword_t *txd;
2495
b2663a4f
MH		 2496 tx_queue->xmit_more_available = false;
2497 if (unlikely(tx_queue->write_count == tx_queue->insert_count))
2498 return;
8127d661
BH		 2499
2500 do {
2501 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
2502 buffer = &tx_queue->buffer[write_ptr];
2503 txd = efx_tx_desc(tx_queue, write_ptr);
2504 ++tx_queue->write_count;
2505
2506 /* Create TX descriptor ring entry */
2507 if (buffer->flags & EFX_TX_BUF_OPTION) {
2508 *txd = buffer->option;
de1deff9
EC		 2509 if (EFX_QWORD_FIELD(*txd, ESF_DZ_TX_OPTION_TYPE) == 1)
2510 /* PIO descriptor */
2511 tx_queue->packet_write_count = tx_queue->write_count;
8127d661 2512 } else {
de1deff9 2513 tx_queue->packet_write_count = tx_queue->write_count;
8127d661
BH		 2514 BUILD_BUG_ON(EFX_TX_BUF_CONT != 1);
2515 EFX_POPULATE_QWORD_3(
2516 *txd,
2517 ESF_DZ_TX_KER_CONT,
2518 buffer->flags & EFX_TX_BUF_CONT,
2519 ESF_DZ_TX_KER_BYTE_CNT, buffer->len,
2520 ESF_DZ_TX_KER_BUF_ADDR, buffer->dma_addr);
2521 }
2522 } while (tx_queue->write_count != tx_queue->insert_count);
2523
2524 wmb(); /* Ensure descriptors are written before they are fetched */
2525
2526 if (efx_nic_may_push_tx_desc(tx_queue, old_write_count)) {
2527 txd = efx_tx_desc(tx_queue,
2528 old_write_count & tx_queue->ptr_mask);
2529 efx_ef10_push_tx_desc(tx_queue, txd);
2530 ++tx_queue->pushes;
2531 } else {
2532 efx_ef10_notify_tx_desc(tx_queue);
2533 }
2534}
2535
a33a4c73
EC		 2536#define RSS_MODE_HASH_ADDRS (1 << RSS_MODE_HASH_SRC_ADDR_LBN |\
2537 1 << RSS_MODE_HASH_DST_ADDR_LBN)
2538#define RSS_MODE_HASH_PORTS (1 << RSS_MODE_HASH_SRC_PORT_LBN |\
2539 1 << RSS_MODE_HASH_DST_PORT_LBN)
2540#define RSS_CONTEXT_FLAGS_DEFAULT (1 << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_LBN |\
2541 1 << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_LBN |\
2542 1 << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_LBN |\
2543 1 << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_LBN |\
2544 (RSS_MODE_HASH_ADDRS | RSS_MODE_HASH_PORTS) << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV4_RSS_MODE_LBN |\
2545 RSS_MODE_HASH_ADDRS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_LBN |\
2546 RSS_MODE_HASH_ADDRS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV4_RSS_MODE_LBN |\
2547 (RSS_MODE_HASH_ADDRS | RSS_MODE_HASH_PORTS) << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV6_RSS_MODE_LBN |\
2548 RSS_MODE_HASH_ADDRS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_LBN |\
2549 RSS_MODE_HASH_ADDRS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV6_RSS_MODE_LBN)
2550
2551static int efx_ef10_get_rss_flags(struct efx_nic *efx, u32 context, u32 *flags)
2552{
2553 /* Firmware had a bug (sfc bug 61952) where it would not actually
2554 * fill in the flags field in the response to MC_CMD_RSS_CONTEXT_GET_FLAGS.
2555 * This meant that it would always contain whatever was previously
2556 * in the MCDI buffer. Fortunately, all firmware versions with
2557 * this bug have the same default flags value for a newly-allocated
2558 * RSS context, and the only time we want to get the flags is just
2559 * after allocating. Moreover, the response has a 32-bit hole
2560 * where the context ID would be in the request, so we can use an
2561 * overlength buffer in the request and pre-fill the flags field
2562 * with what we believe the default to be. Thus if the firmware
2563 * has the bug, it will leave our pre-filled value in the flags
2564 * field of the response, and we will get the right answer.
2565 *
2566 * However, this does mean that this function should NOT be used if
2567 * the RSS context flags might not be their defaults - it is ONLY
2568 * reliably correct for a newly-allocated RSS context.
2569 */
2570 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_LEN);
2571 MCDI_DECLARE_BUF(outbuf, MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_LEN);
2572 size_t outlen;
2573 int rc;
2574
2575 /* Check we have a hole for the context ID */
2576 BUILD_BUG_ON(MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_LEN != MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_FLAGS_OFST);
2577 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_GET_FLAGS_IN_RSS_CONTEXT_ID, context);
2578 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_GET_FLAGS_OUT_FLAGS,
2579 RSS_CONTEXT_FLAGS_DEFAULT);
2580 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_GET_FLAGS, inbuf,
2581 sizeof(inbuf), outbuf, sizeof(outbuf), &outlen);
2582 if (rc == 0) {
2583 if (outlen < MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_LEN)
2584 rc = -EIO;
2585 else
2586 *flags = MCDI_DWORD(outbuf, RSS_CONTEXT_GET_FLAGS_OUT_FLAGS);
2587 }
2588 return rc;
2589}
2590
2591/* Attempt to enable 4-tuple UDP hashing on the specified RSS context.
2592 * If we fail, we just leave the RSS context at its default hash settings,
2593 * which is safe but may slightly reduce performance.
2594 * Defaults are 4-tuple for TCP and 2-tuple for UDP and other-IP, so we
2595 * just need to set the UDP ports flags (for both IP versions).
2596 */
2597static void efx_ef10_set_rss_flags(struct efx_nic *efx, u32 context)
2598{
2599 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_LEN);
2600 u32 flags;
2601
2602 BUILD_BUG_ON(MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT_LEN != 0);
2603
2604 if (efx_ef10_get_rss_flags(efx, context, &flags) != 0)
2605 return;
2606 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_SET_FLAGS_IN_RSS_CONTEXT_ID, context);
2607 flags |= RSS_MODE_HASH_PORTS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_LBN;
2608 flags |= RSS_MODE_HASH_PORTS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_LBN;
2609 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_SET_FLAGS_IN_FLAGS, flags);
b718c88a
EC		 2610 if (!efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_FLAGS, inbuf, sizeof(inbuf),
2611 NULL, 0, NULL))
2612 /* Succeeded, so UDP 4-tuple is now enabled */
2613 efx->rx_hash_udp_4tuple = true;
a33a4c73
EC		 2614}
2615
267c0157
JC		 2616static int efx_ef10_alloc_rss_context(struct efx_nic *efx, u32 *context,
2617 bool exclusive, unsigned *context_size)
8127d661
BH		 2618{
2619 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN);
2620 MCDI_DECLARE_BUF(outbuf, MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN);
45b2449e 2621 struct efx_ef10_nic_data *nic_data = efx->nic_data;
8127d661
BH		 2622 size_t outlen;
2623 int rc;
267c0157
JC		 2624 u32 alloc_type = exclusive ?
2625 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE :
2626 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED;
2627 unsigned rss_spread = exclusive ?
2628 efx->rss_spread :
2629 min(rounddown_pow_of_two(efx->rss_spread),
2630 EFX_EF10_MAX_SHARED_RSS_CONTEXT_SIZE);
2631
2632 if (!exclusive && rss_spread == 1) {
2633 *context = EFX_EF10_RSS_CONTEXT_INVALID;
2634 if (context_size)
2635 *context_size = 1;
2636 return 0;
2637 }
8127d661 2638
dcb4123c
JC		 2639 if (nic_data->datapath_caps &
2640 1 << MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_LBN)
2641 return -EOPNOTSUPP;
2642
8127d661 2643 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID,
45b2449e 2644 nic_data->vport_id);
267c0157
JC		 2645 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_TYPE, alloc_type);
2646 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_NUM_QUEUES, rss_spread);
8127d661
BH		 2647
2648 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_ALLOC, inbuf, sizeof(inbuf),
2649 outbuf, sizeof(outbuf), &outlen);
2650 if (rc != 0)
2651 return rc;
2652
2653 if (outlen < MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN)
2654 return -EIO;
2655
2656 *context = MCDI_DWORD(outbuf, RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID);
2657
267c0157
JC		 2658 if (context_size)
2659 *context_size = rss_spread;
2660
a33a4c73
EC		 2661 if (nic_data->datapath_caps &
2662 1 << MC_CMD_GET_CAPABILITIES_OUT_ADDITIONAL_RSS_MODES_LBN)
2663 efx_ef10_set_rss_flags(efx, *context);
2664
8127d661
BH		 2665 return 0;
2666}
2667
2668static void efx_ef10_free_rss_context(struct efx_nic *efx, u32 context)
2669{
2670 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_FREE_IN_LEN);
2671 int rc;
2672
2673 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID,
2674 context);
2675
2676 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_FREE, inbuf, sizeof(inbuf),
2677 NULL, 0, NULL);
2678 WARN_ON(rc != 0);
2679}
2680
267c0157 2681static int efx_ef10_populate_rss_table(struct efx_nic *efx, u32 context,
f74d1995 2682 const u32 *rx_indir_table, const u8 *key)
8127d661
BH		 2683{
2684 MCDI_DECLARE_BUF(tablebuf, MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN);
2685 MCDI_DECLARE_BUF(keybuf, MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN);
2686 int i, rc;
2687
2688 MCDI_SET_DWORD(tablebuf, RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID,
2689 context);
2690 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_indir_table) !=
2691 MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN);
2692
f74d1995
EC		 2693 /* This iterates over the length of efx->rx_indir_table, but copies
2694 * bytes from rx_indir_table. That's because the latter is a pointer
2695 * rather than an array, but should have the same length.
2696 * The efx->rx_hash_key loop below is similar.
2697 */
8127d661
BH		 2698 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); ++i)
2699 MCDI_PTR(tablebuf,
2700 RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE)[i] =
267c0157 2701 (u8) rx_indir_table[i];
8127d661
BH		 2702
2703 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_TABLE, tablebuf,
2704 sizeof(tablebuf), NULL, 0, NULL);
2705 if (rc != 0)
2706 return rc;
2707
2708 MCDI_SET_DWORD(keybuf, RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID,
2709 context);
2710 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_hash_key) !=
2711 MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN);
2712 for (i = 0; i < ARRAY_SIZE(efx->rx_hash_key); ++i)
f74d1995 2713 MCDI_PTR(keybuf, RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY)[i] = key[i];
8127d661
BH		 2714
2715 return efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_KEY, keybuf,
2716 sizeof(keybuf), NULL, 0, NULL);
2717}
2718
2719static void efx_ef10_rx_free_indir_table(struct efx_nic *efx)
2720{
2721 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2722
2723 if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID)
2724 efx_ef10_free_rss_context(efx, nic_data->rx_rss_context);
2725 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
2726}
2727
267c0157
JC		 2728static int efx_ef10_rx_push_shared_rss_config(struct efx_nic *efx,
2729 unsigned *context_size)
8127d661 2730{
267c0157 2731 u32 new_rx_rss_context;
8127d661 2732 struct efx_ef10_nic_data *nic_data = efx->nic_data;
267c0157
JC		 2733 int rc = efx_ef10_alloc_rss_context(efx, &new_rx_rss_context,
2734 false, context_size);
2735
2736 if (rc != 0)
2737 return rc;
8127d661 2738
267c0157
JC		 2739 nic_data->rx_rss_context = new_rx_rss_context;
2740 nic_data->rx_rss_context_exclusive = false;
2741 efx_set_default_rx_indir_table(efx);
2742 return 0;
2743}
8127d661 2744
267c0157 2745static int efx_ef10_rx_push_exclusive_rss_config(struct efx_nic *efx,
f74d1995
EC		 2746 const u32 *rx_indir_table,
2747 const u8 *key)
267c0157
JC		 2748{
2749 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2750 int rc;
2751 u32 new_rx_rss_context;
2752
2753 if (nic_data->rx_rss_context == EFX_EF10_RSS_CONTEXT_INVALID ||
2754 !nic_data->rx_rss_context_exclusive) {
2755 rc = efx_ef10_alloc_rss_context(efx, &new_rx_rss_context,
2756 true, NULL);
2757 if (rc == -EOPNOTSUPP)
2758 return rc;
2759 else if (rc != 0)
2760 goto fail1;
2761 } else {
2762 new_rx_rss_context = nic_data->rx_rss_context;
8127d661
BH		 2763 }
2764
267c0157 2765 rc = efx_ef10_populate_rss_table(efx, new_rx_rss_context,
f74d1995 2766 rx_indir_table, key);
8127d661 2767 if (rc != 0)
267c0157 2768 goto fail2;
8127d661 2769
267c0157
JC		 2770 if (nic_data->rx_rss_context != new_rx_rss_context)
2771 efx_ef10_rx_free_indir_table(efx);
2772 nic_data->rx_rss_context = new_rx_rss_context;
2773 nic_data->rx_rss_context_exclusive = true;
2774 if (rx_indir_table != efx->rx_indir_table)
2775 memcpy(efx->rx_indir_table, rx_indir_table,
2776 sizeof(efx->rx_indir_table));
f74d1995
EC		 2777 if (key != efx->rx_hash_key)
2778 memcpy(efx->rx_hash_key, key, efx->type->rx_hash_key_size);
2779
267c0157 2780 return 0;
8127d661 2781
267c0157
JC		 2782fail2:
2783 if (new_rx_rss_context != nic_data->rx_rss_context)
2784 efx_ef10_free_rss_context(efx, new_rx_rss_context);
2785fail1:
8127d661 2786 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
267c0157
JC		 2787 return rc;
2788}
2789
a707d188
EC		 2790static int efx_ef10_rx_pull_rss_config(struct efx_nic *efx)
2791{
2792 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2793 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_GET_TABLE_IN_LEN);
2794 MCDI_DECLARE_BUF(tablebuf, MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_LEN);
2795 MCDI_DECLARE_BUF(keybuf, MC_CMD_RSS_CONTEXT_GET_KEY_OUT_LEN);
2796 size_t outlen;
2797 int rc, i;
2798
2799 BUILD_BUG_ON(MC_CMD_RSS_CONTEXT_GET_TABLE_IN_LEN !=
2800 MC_CMD_RSS_CONTEXT_GET_KEY_IN_LEN);
2801
2802 if (nic_data->rx_rss_context == EFX_EF10_RSS_CONTEXT_INVALID)
2803 return -ENOENT;
2804
2805 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_GET_TABLE_IN_RSS_CONTEXT_ID,
2806 nic_data->rx_rss_context);
2807 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_indir_table) !=
2808 MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE_LEN);
2809 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_GET_TABLE, inbuf, sizeof(inbuf),
2810 tablebuf, sizeof(tablebuf), &outlen);
2811 if (rc != 0)
2812 return rc;
2813
2814 if (WARN_ON(outlen != MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_LEN))
2815 return -EIO;
2816
2817 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); i++)
2818 efx->rx_indir_table[i] = MCDI_PTR(tablebuf,
2819 RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE)[i];
2820
2821 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_GET_KEY_IN_RSS_CONTEXT_ID,
2822 nic_data->rx_rss_context);
2823 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_hash_key) !=
2824 MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN);
2825 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_GET_KEY, inbuf, sizeof(inbuf),
2826 keybuf, sizeof(keybuf), &outlen);
2827 if (rc != 0)
2828 return rc;
2829
2830 if (WARN_ON(outlen != MC_CMD_RSS_CONTEXT_GET_KEY_OUT_LEN))
2831 return -EIO;
2832
2833 for (i = 0; i < ARRAY_SIZE(efx->rx_hash_key); ++i)
2834 efx->rx_hash_key[i] = MCDI_PTR(
2835 keybuf, RSS_CONTEXT_GET_KEY_OUT_TOEPLITZ_KEY)[i];
2836
2837 return 0;
2838}
2839
267c0157 2840static int efx_ef10_pf_rx_push_rss_config(struct efx_nic *efx, bool user,
f74d1995
EC		 2841 const u32 *rx_indir_table,
2842 const u8 *key)
267c0157
JC		 2843{
2844 int rc;
2845
2846 if (efx->rss_spread == 1)
2847 return 0;
2848
f74d1995
EC		 2849 if (!key)
2850 key = efx->rx_hash_key;
2851
2852 rc = efx_ef10_rx_push_exclusive_rss_config(efx, rx_indir_table, key);
267c0157
JC		 2853
2854 if (rc == -ENOBUFS && !user) {
2855 unsigned context_size;
2856 bool mismatch = false;
2857 size_t i;
2858
2859 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table) && !mismatch;
2860 i++)
2861 mismatch = rx_indir_table[i] !=
2862 ethtool_rxfh_indir_default(i, efx->rss_spread);
2863
2864 rc = efx_ef10_rx_push_shared_rss_config(efx, &context_size);
2865 if (rc == 0) {
2866 if (context_size != efx->rss_spread)
2867 netif_warn(efx, probe, efx->net_dev,
2868 "Could not allocate an exclusive RSS"
2869 " context; allocated a shared one of"
2870 " different size."
2871 " Wanted %u, got %u.\n",
2872 efx->rss_spread, context_size);
2873 else if (mismatch)
2874 netif_warn(efx, probe, efx->net_dev,
2875 "Could not allocate an exclusive RSS"
2876 " context; allocated a shared one but"
2877 " could not apply custom"
2878 " indirection.\n");
2879 else
2880 netif_info(efx, probe, efx->net_dev,
2881 "Could not allocate an exclusive RSS"
2882 " context; allocated a shared one.\n");
2883 }
2884 }
2885 return rc;
2886}
2887
2888static int efx_ef10_vf_rx_push_rss_config(struct efx_nic *efx, bool user,
2889 const u32 *rx_indir_table
f74d1995
EC		 2890 __attribute__ ((unused)),
2891 const u8 *key
267c0157
JC		 2892 __attribute__ ((unused)))
2893{
2894 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2895
2896 if (user)
2897 return -EOPNOTSUPP;
2898 if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID)
2899 return 0;
2900 return efx_ef10_rx_push_shared_rss_config(efx, NULL);
8127d661
BH		 2901}
2902
2903static int efx_ef10_rx_probe(struct efx_rx_queue *rx_queue)
2904{
2905 return efx_nic_alloc_buffer(rx_queue->efx, &rx_queue->rxd.buf,
2906 (rx_queue->ptr_mask + 1) *
2907 sizeof(efx_qword_t),
2908 GFP_KERNEL);
2909}
2910
2911static void efx_ef10_rx_init(struct efx_rx_queue *rx_queue)
2912{
2913 MCDI_DECLARE_BUF(inbuf,
2914 MC_CMD_INIT_RXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
2915 EFX_BUF_SIZE));
8127d661
BH		 2916 struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
2917 size_t entries = rx_queue->rxd.buf.len / EFX_BUF_SIZE;
2918 struct efx_nic *efx = rx_queue->efx;
45b2449e 2919 struct efx_ef10_nic_data *nic_data = efx->nic_data;
aa09a3da 2920 size_t inlen;
8127d661
BH		 2921 dma_addr_t dma_addr;
2922 int rc;
2923 int i;
aa09a3da 2924 BUILD_BUG_ON(MC_CMD_INIT_RXQ_OUT_LEN != 0);
8127d661
BH		 2925
2926 rx_queue->scatter_n = 0;
2927 rx_queue->scatter_len = 0;
2928
2929 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_SIZE, rx_queue->ptr_mask + 1);
2930 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_TARGET_EVQ, channel->channel);
2931 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_LABEL, efx_rx_queue_index(rx_queue));
2932 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_INSTANCE,
2933 efx_rx_queue_index(rx_queue));
bd9a265d
JC		 2934 MCDI_POPULATE_DWORD_2(inbuf, INIT_RXQ_IN_FLAGS,
2935 INIT_RXQ_IN_FLAG_PREFIX, 1,
2936 INIT_RXQ_IN_FLAG_TIMESTAMP, 1);
8127d661 2937 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_OWNER_ID, 0);
45b2449e 2938 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_PORT_ID, nic_data->vport_id);
8127d661
BH		 2939
2940 dma_addr = rx_queue->rxd.buf.dma_addr;
2941
2942 netif_dbg(efx, hw, efx->net_dev, "pushing RXQ %d. %zu entries (%llx)\n",
2943 efx_rx_queue_index(rx_queue), entries, (u64)dma_addr);
2944
2945 for (i = 0; i < entries; ++i) {
2946 MCDI_SET_ARRAY_QWORD(inbuf, INIT_RXQ_IN_DMA_ADDR, i, dma_addr);
2947 dma_addr += EFX_BUF_SIZE;
2948 }
2949
2950 inlen = MC_CMD_INIT_RXQ_IN_LEN(entries);
2951
2952 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_RXQ, inbuf, inlen,
aa09a3da 2953 NULL, 0, NULL);
48ce5634
BH		 2954 if (rc)
2955 netdev_WARN(efx->net_dev, "failed to initialise RXQ %d\n",
2956 efx_rx_queue_index(rx_queue));
8127d661
BH		 2957}
2958
2959static void efx_ef10_rx_fini(struct efx_rx_queue *rx_queue)
2960{
2961 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_RXQ_IN_LEN);
aa09a3da 2962 MCDI_DECLARE_BUF_ERR(outbuf);
8127d661
BH		 2963 struct efx_nic *efx = rx_queue->efx;
2964 size_t outlen;
2965 int rc;
2966
2967 MCDI_SET_DWORD(inbuf, FINI_RXQ_IN_INSTANCE,
2968 efx_rx_queue_index(rx_queue));
2969
1e0b8120 2970 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_RXQ, inbuf, sizeof(inbuf),
8127d661
BH		 2971 outbuf, sizeof(outbuf), &outlen);
2972
2973 if (rc && rc != -EALREADY)
2974 goto fail;
2975
2976 return;
2977
2978fail:
1e0b8120
EC		 2979 efx_mcdi_display_error(efx, MC_CMD_FINI_RXQ, MC_CMD_FINI_RXQ_IN_LEN,
2980 outbuf, outlen, rc);
8127d661
BH		 2981}
2982
2983static void efx_ef10_rx_remove(struct efx_rx_queue *rx_queue)
2984{
2985 efx_nic_free_buffer(rx_queue->efx, &rx_queue->rxd.buf);
2986}
2987
2988/* This creates an entry in the RX descriptor queue */
2989static inline void
2990efx_ef10_build_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index)
2991{
2992 struct efx_rx_buffer *rx_buf;
2993 efx_qword_t *rxd;
2994
2995 rxd = efx_rx_desc(rx_queue, index);
2996 rx_buf = efx_rx_buffer(rx_queue, index);
2997 EFX_POPULATE_QWORD_2(*rxd,
2998 ESF_DZ_RX_KER_BYTE_CNT, rx_buf->len,
2999 ESF_DZ_RX_KER_BUF_ADDR, rx_buf->dma_addr);
3000}
3001
3002static void efx_ef10_rx_write(struct efx_rx_queue *rx_queue)
3003{
3004 struct efx_nic *efx = rx_queue->efx;
3005 unsigned int write_count;
3006 efx_dword_t reg;
3007
3008 /* Firmware requires that RX_DESC_WPTR be a multiple of 8 */
3009 write_count = rx_queue->added_count & ~7;
3010 if (rx_queue->notified_count == write_count)
3011 return;
3012
3013 do
3014 efx_ef10_build_rx_desc(
3015 rx_queue,
3016 rx_queue->notified_count & rx_queue->ptr_mask);
3017 while (++rx_queue->notified_count != write_count);
3018
3019 wmb();
3020 EFX_POPULATE_DWORD_1(reg, ERF_DZ_RX_DESC_WPTR,
3021 write_count & rx_queue->ptr_mask);
3022 efx_writed_page(efx, &reg, ER_DZ_RX_DESC_UPD,
3023 efx_rx_queue_index(rx_queue));
3024}
3025
3026static efx_mcdi_async_completer efx_ef10_rx_defer_refill_complete;
3027
3028static void efx_ef10_rx_defer_refill(struct efx_rx_queue *rx_queue)
3029{
3030 struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
3031 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
3032 efx_qword_t event;
3033
3034 EFX_POPULATE_QWORD_2(event,
3035 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
3036 ESF_DZ_EV_DATA, EFX_EF10_REFILL);
3037
3038 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
3039
3040 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
3041 * already swapped the data to little-endian order.
3042 */
3043 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
3044 sizeof(efx_qword_t));
3045
3046 efx_mcdi_rpc_async(channel->efx, MC_CMD_DRIVER_EVENT,
3047 inbuf, sizeof(inbuf), 0,
3048 efx_ef10_rx_defer_refill_complete, 0);
3049}
3050
3051static void
3052efx_ef10_rx_defer_refill_complete(struct efx_nic *efx, unsigned long cookie,
3053 int rc, efx_dword_t *outbuf,
3054 size_t outlen_actual)
3055{
3056 /* nothing to do */
3057}
3058
3059static int efx_ef10_ev_probe(struct efx_channel *channel)
3060{
3061 return efx_nic_alloc_buffer(channel->efx, &channel->eventq.buf,
3062 (channel->eventq_mask + 1) *
3063 sizeof(efx_qword_t),
3064 GFP_KERNEL);
3065}
3066
46e612b0
DP		 3067static void efx_ef10_ev_fini(struct efx_channel *channel)
3068{
3069 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_EVQ_IN_LEN);
3070 MCDI_DECLARE_BUF_ERR(outbuf);
3071 struct efx_nic *efx = channel->efx;
3072 size_t outlen;
3073 int rc;
3074
3075 MCDI_SET_DWORD(inbuf, FINI_EVQ_IN_INSTANCE, channel->channel);
3076
3077 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_EVQ, inbuf, sizeof(inbuf),
3078 outbuf, sizeof(outbuf), &outlen);
3079
3080 if (rc && rc != -EALREADY)
3081 goto fail;
3082
3083 return;
3084
3085fail:
3086 efx_mcdi_display_error(efx, MC_CMD_FINI_EVQ, MC_CMD_FINI_EVQ_IN_LEN,
3087 outbuf, outlen, rc);
3088}
3089
8127d661
BH		 3090static int efx_ef10_ev_init(struct efx_channel *channel)
3091{
3092 MCDI_DECLARE_BUF(inbuf,
a995560a
BK		 3093 MC_CMD_INIT_EVQ_V2_IN_LEN(EFX_MAX_EVQ_SIZE * 8 /
3094 EFX_BUF_SIZE));
3095 MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_EVQ_V2_OUT_LEN);
8127d661
BH		 3096 size_t entries = channel->eventq.buf.len / EFX_BUF_SIZE;
3097 struct efx_nic *efx = channel->efx;
3098 struct efx_ef10_nic_data *nic_data;
8127d661 3099 size_t inlen, outlen;
46e612b0 3100 unsigned int enabled, implemented;
8127d661
BH		 3101 dma_addr_t dma_addr;
3102 int rc;
3103 int i;
3104
3105 nic_data = efx->nic_data;
8127d661
BH		 3106
3107 /* Fill event queue with all ones (i.e. empty events) */
3108 memset(channel->eventq.buf.addr, 0xff, channel->eventq.buf.len);
3109
3110 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_SIZE, channel->eventq_mask + 1);
3111 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_INSTANCE, channel->channel);
3112 /* INIT_EVQ expects index in vector table, not absolute */
3113 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_IRQ_NUM, channel->channel);
8127d661
BH		 3114 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_MODE,
3115 MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS);
3116 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_LOAD, 0);
3117 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_RELOAD, 0);
3118 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_MODE,
3119 MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS);
3120 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_THRSHLD, 0);
3121
a995560a
BK		 3122 if (nic_data->datapath_caps2 &
3123 1 << MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_V2_LBN) {
3124 /* Use the new generic approach to specifying event queue
3125 * configuration, requesting lower latency or higher throughput.
3126 * The options that actually get used appear in the output.
3127 */
3128 MCDI_POPULATE_DWORD_2(inbuf, INIT_EVQ_V2_IN_FLAGS,
3129 INIT_EVQ_V2_IN_FLAG_INTERRUPTING, 1,
3130 INIT_EVQ_V2_IN_FLAG_TYPE,
3131 MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_AUTO);
3132 } else {
3133 bool cut_thru = !(nic_data->datapath_caps &
3134 1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN);
3135
3136 MCDI_POPULATE_DWORD_4(inbuf, INIT_EVQ_IN_FLAGS,
3137 INIT_EVQ_IN_FLAG_INTERRUPTING, 1,
3138 INIT_EVQ_IN_FLAG_RX_MERGE, 1,
3139 INIT_EVQ_IN_FLAG_TX_MERGE, 1,
3140 INIT_EVQ_IN_FLAG_CUT_THRU, cut_thru);
3141 }
3142
8127d661
BH		 3143 dma_addr = channel->eventq.buf.dma_addr;
3144 for (i = 0; i < entries; ++i) {
3145 MCDI_SET_ARRAY_QWORD(inbuf, INIT_EVQ_IN_DMA_ADDR, i, dma_addr);
3146 dma_addr += EFX_BUF_SIZE;
3147 }
3148
3149 inlen = MC_CMD_INIT_EVQ_IN_LEN(entries);
3150
3151 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_EVQ, inbuf, inlen,
3152 outbuf, sizeof(outbuf), &outlen);
a995560a
BK		 3153
3154 if (outlen >= MC_CMD_INIT_EVQ_V2_OUT_LEN)
3155 netif_dbg(efx, drv, efx->net_dev,
3156 "Channel %d using event queue flags %08x\n",
3157 channel->channel,
3158 MCDI_DWORD(outbuf, INIT_EVQ_V2_OUT_FLAGS));
3159
8127d661 3160 /* IRQ return is ignored */
46e612b0
DP		 3161 if (channel->channel || rc)
3162 return rc;
8127d661 3163
46e612b0
DP		 3164 /* Successfully created event queue on channel 0 */
3165 rc = efx_mcdi_get_workarounds(efx, &implemented, &enabled);
832dc9ed 3166 if (rc == -ENOSYS) {
d95e329a
BK		 3167 /* GET_WORKAROUNDS was implemented before this workaround,
3168 * thus it must be unavailable in this firmware.
832dc9ed
EC		 3169 */
3170 nic_data->workaround_26807 = false;
3171 rc = 0;
3172 } else if (rc) {
8127d661 3173 goto fail;
832dc9ed
EC		 3174 } else {
3175 nic_data->workaround_26807 =
3176 !!(enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807);
3177
3178 if (implemented & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807 &&
3179 !nic_data->workaround_26807) {
5a55a72a
DP		 3180 unsigned int flags;
3181
34ccfe6f
DP		 3182 rc = efx_mcdi_set_workaround(efx,
3183 MC_CMD_WORKAROUND_BUG26807,
5a55a72a
DP		 3184 true, &flags);
3185
3186 if (!rc) {
3187 if (flags &
3188 1 << MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN) {
3189 netif_info(efx, drv, efx->net_dev,
3190 "other functions on NIC have been reset\n");
abd86a55
DP		 3191
3192 /* With MCFW v4.6.x and earlier, the
3193 * boot count will have incremented,
3194 * so re-read the warm_boot_count
3195 * value now to ensure this function
3196 * doesn't think it has changed next
3197 * time it checks.
3198 */
3199 rc = efx_ef10_get_warm_boot_count(efx);
3200 if (rc >= 0) {
3201 nic_data->warm_boot_count = rc;
3202 rc = 0;
3203 }
5a55a72a 3204 }
832dc9ed 3205 nic_data->workaround_26807 = true;
5a55a72a 3206 } else if (rc == -EPERM) {
832dc9ed 3207 rc = 0;
5a55a72a 3208 }
832dc9ed 3209 }
46e612b0
DP		 3210 }
3211
3212 if (!rc)
3213 return 0;
8127d661
BH		 3214
3215fail:
46e612b0
DP		 3216 efx_ef10_ev_fini(channel);
3217 return rc;
8127d661
BH		 3218}
3219
3220static void efx_ef10_ev_remove(struct efx_channel *channel)
3221{
3222 efx_nic_free_buffer(channel->efx, &channel->eventq.buf);
3223}
3224
3225static void efx_ef10_handle_rx_wrong_queue(struct efx_rx_queue *rx_queue,
3226 unsigned int rx_queue_label)
3227{
3228 struct efx_nic *efx = rx_queue->efx;
3229
3230 netif_info(efx, hw, efx->net_dev,
3231 "rx event arrived on queue %d labeled as queue %u\n",
3232 efx_rx_queue_index(rx_queue), rx_queue_label);
3233
3234 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
3235}
3236
3237static void
3238efx_ef10_handle_rx_bad_lbits(struct efx_rx_queue *rx_queue,
3239 unsigned int actual, unsigned int expected)
3240{
3241 unsigned int dropped = (actual - expected) & rx_queue->ptr_mask;
3242 struct efx_nic *efx = rx_queue->efx;
3243
3244 netif_info(efx, hw, efx->net_dev,
3245 "dropped %d events (index=%d expected=%d)\n",
3246 dropped, actual, expected);
3247
3248 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
3249}
3250
3251/* partially received RX was aborted. clean up. */
3252static void efx_ef10_handle_rx_abort(struct efx_rx_queue *rx_queue)
3253{
3254 unsigned int rx_desc_ptr;
3255
8127d661
BH		 3256 netif_dbg(rx_queue->efx, hw, rx_queue->efx->net_dev,
3257 "scattered RX aborted (dropping %u buffers)\n",
3258 rx_queue->scatter_n);
3259
3260 rx_desc_ptr = rx_queue->removed_count & rx_queue->ptr_mask;
3261
3262 efx_rx_packet(rx_queue, rx_desc_ptr, rx_queue->scatter_n,
3263 0, EFX_RX_PKT_DISCARD);
3264
3265 rx_queue->removed_count += rx_queue->scatter_n;
3266 rx_queue->scatter_n = 0;
3267 rx_queue->scatter_len = 0;
3268 ++efx_rx_queue_channel(rx_queue)->n_rx_nodesc_trunc;
3269}
3270
a0ee3541
JC		 3271static u16 efx_ef10_handle_rx_event_errors(struct efx_channel *channel,
3272 unsigned int n_packets,
3273 unsigned int rx_encap_hdr,
3274 unsigned int rx_l3_class,
3275 unsigned int rx_l4_class,
3276 const efx_qword_t *event)
3277{
3278 struct efx_nic *efx = channel->efx;
6978729f 3279 bool handled = false;
a0ee3541
JC		 3280
3281 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_ECRC_ERR)) {
6978729f
EC		 3282 if (!(efx->net_dev->features & NETIF_F_RXALL)) {
3283 if (!efx->loopback_selftest)
3284 channel->n_rx_eth_crc_err += n_packets;
3285 return EFX_RX_PKT_DISCARD;
3286 }
3287 handled = true;
a0ee3541
JC		 3288 }
3289 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_IPCKSUM_ERR)) {
3290 if (unlikely(rx_encap_hdr != ESE_EZ_ENCAP_HDR_VXLAN &&
3291 rx_l3_class != ESE_DZ_L3_CLASS_IP4 &&
3292 rx_l3_class != ESE_DZ_L3_CLASS_IP4_FRAG &&
3293 rx_l3_class != ESE_DZ_L3_CLASS_IP6 &&
3294 rx_l3_class != ESE_DZ_L3_CLASS_IP6_FRAG))
3295 netdev_WARN(efx->net_dev,
3296 "invalid class for RX_IPCKSUM_ERR: event="
3297 EFX_QWORD_FMT "\n",
3298 EFX_QWORD_VAL(*event));
3299 if (!efx->loopback_selftest)
3300 *(rx_encap_hdr ?
3301 &channel->n_rx_outer_ip_hdr_chksum_err :
3302 &channel->n_rx_ip_hdr_chksum_err) += n_packets;
3303 return 0;
3304 }
3305 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_TCPUDP_CKSUM_ERR)) {
3306 if (unlikely(rx_encap_hdr != ESE_EZ_ENCAP_HDR_VXLAN &&
3307 ((rx_l3_class != ESE_DZ_L3_CLASS_IP4 &&
3308 rx_l3_class != ESE_DZ_L3_CLASS_IP6) ||
d8d8ccf2
BK		 3309 (rx_l4_class != ESE_FZ_L4_CLASS_TCP &&
3310 rx_l4_class != ESE_FZ_L4_CLASS_UDP))))
a0ee3541
JC		 3311 netdev_WARN(efx->net_dev,
3312 "invalid class for RX_TCPUDP_CKSUM_ERR: event="
3313 EFX_QWORD_FMT "\n",
3314 EFX_QWORD_VAL(*event));
3315 if (!efx->loopback_selftest)
3316 *(rx_encap_hdr ?
3317 &channel->n_rx_outer_tcp_udp_chksum_err :
3318 &channel->n_rx_tcp_udp_chksum_err) += n_packets;
3319 return 0;
3320 }
3321 if (EFX_QWORD_FIELD(*event, ESF_EZ_RX_IP_INNER_CHKSUM_ERR)) {
3322 if (unlikely(!rx_encap_hdr))
3323 netdev_WARN(efx->net_dev,
3324 "invalid encapsulation type for RX_IP_INNER_CHKSUM_ERR: event="
3325 EFX_QWORD_FMT "\n",
3326 EFX_QWORD_VAL(*event));
3327 else if (unlikely(rx_l3_class != ESE_DZ_L3_CLASS_IP4 &&
3328 rx_l3_class != ESE_DZ_L3_CLASS_IP4_FRAG &&
3329 rx_l3_class != ESE_DZ_L3_CLASS_IP6 &&
3330 rx_l3_class != ESE_DZ_L3_CLASS_IP6_FRAG))
3331 netdev_WARN(efx->net_dev,
3332 "invalid class for RX_IP_INNER_CHKSUM_ERR: event="
3333 EFX_QWORD_FMT "\n",
3334 EFX_QWORD_VAL(*event));
3335 if (!efx->loopback_selftest)
3336 channel->n_rx_inner_ip_hdr_chksum_err += n_packets;
3337 return 0;
3338 }
3339 if (EFX_QWORD_FIELD(*event, ESF_EZ_RX_TCP_UDP_INNER_CHKSUM_ERR)) {
3340 if (unlikely(!rx_encap_hdr))
3341 netdev_WARN(efx->net_dev,
3342 "invalid encapsulation type for RX_TCP_UDP_INNER_CHKSUM_ERR: event="
3343 EFX_QWORD_FMT "\n",
3344 EFX_QWORD_VAL(*event));
3345 else if (unlikely((rx_l3_class != ESE_DZ_L3_CLASS_IP4 &&
3346 rx_l3_class != ESE_DZ_L3_CLASS_IP6) ||
d8d8ccf2
BK		 3347 (rx_l4_class != ESE_FZ_L4_CLASS_TCP &&
3348 rx_l4_class != ESE_FZ_L4_CLASS_UDP)))
a0ee3541
JC		 3349 netdev_WARN(efx->net_dev,
3350 "invalid class for RX_TCP_UDP_INNER_CHKSUM_ERR: event="
3351 EFX_QWORD_FMT "\n",
3352 EFX_QWORD_VAL(*event));
3353 if (!efx->loopback_selftest)
3354 channel->n_rx_inner_tcp_udp_chksum_err += n_packets;
3355 return 0;
3356 }
3357
6978729f 3358 WARN_ON(!handled); /* No error bits were recognised */
a0ee3541
JC		 3359 return 0;
3360}
3361
8127d661
BH		 3362static int efx_ef10_handle_rx_event(struct efx_channel *channel,
3363 const efx_qword_t *event)
3364{
a0ee3541
JC		 3365 unsigned int rx_bytes, next_ptr_lbits, rx_queue_label;
3366 unsigned int rx_l3_class, rx_l4_class, rx_encap_hdr;
8127d661
BH		 3367 unsigned int n_descs, n_packets, i;
3368 struct efx_nic *efx = channel->efx;
a0ee3541 3369 struct efx_ef10_nic_data *nic_data = efx->nic_data;
8127d661 3370 struct efx_rx_queue *rx_queue;
a0ee3541 3371 efx_qword_t errors;
8127d661
BH		 3372 bool rx_cont;
3373 u16 flags = 0;
3374
6aa7de05 3375 if (unlikely(READ_ONCE(efx->reset_pending)))
8127d661
BH		 3376 return 0;
3377
3378 /* Basic packet information */
3379 rx_bytes = EFX_QWORD_FIELD(*event, ESF_DZ_RX_BYTES);
3380 next_ptr_lbits = EFX_QWORD_FIELD(*event, ESF_DZ_RX_DSC_PTR_LBITS);
3381 rx_queue_label = EFX_QWORD_FIELD(*event, ESF_DZ_RX_QLABEL);
a0ee3541 3382 rx_l3_class = EFX_QWORD_FIELD(*event, ESF_DZ_RX_L3_CLASS);
d8d8ccf2 3383 rx_l4_class = EFX_QWORD_FIELD(*event, ESF_FZ_RX_L4_CLASS);
8127d661 3384 rx_cont = EFX_QWORD_FIELD(*event, ESF_DZ_RX_CONT);
a0ee3541
JC		 3385 rx_encap_hdr =
3386 nic_data->datapath_caps &
3387 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN) ?
3388 EFX_QWORD_FIELD(*event, ESF_EZ_RX_ENCAP_HDR) :
3389 ESE_EZ_ENCAP_HDR_NONE;
8127d661 3390
48ce5634
BH		 3391 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_DROP_EVENT))
3392 netdev_WARN(efx->net_dev, "saw RX_DROP_EVENT: event="
3393 EFX_QWORD_FMT "\n",
3394 EFX_QWORD_VAL(*event));
8127d661
BH		 3395
3396 rx_queue = efx_channel_get_rx_queue(channel);
3397
3398 if (unlikely(rx_queue_label != efx_rx_queue_index(rx_queue)))
3399 efx_ef10_handle_rx_wrong_queue(rx_queue, rx_queue_label);
3400
3401 n_descs = ((next_ptr_lbits - rx_queue->removed_count) &
3402 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
3403
3404 if (n_descs != rx_queue->scatter_n + 1) {
92a04168
BH		 3405 struct efx_ef10_nic_data *nic_data = efx->nic_data;
3406
8127d661
BH		 3407 /* detect rx abort */
3408 if (unlikely(n_descs == rx_queue->scatter_n)) {
48ce5634
BH		 3409 if (rx_queue->scatter_n == 0 || rx_bytes != 0)
3410 netdev_WARN(efx->net_dev,
3411 "invalid RX abort: scatter_n=%u event="
3412 EFX_QWORD_FMT "\n",
3413 rx_queue->scatter_n,
3414 EFX_QWORD_VAL(*event));
8127d661
BH		 3415 efx_ef10_handle_rx_abort(rx_queue);
3416 return 0;
3417 }
3418
92a04168
BH		 3419 /* Check that RX completion merging is valid, i.e.
3420 * the current firmware supports it and this is a
3421 * non-scattered packet.
3422 */
3423 if (!(nic_data->datapath_caps &
3424 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN)) ||
3425 rx_queue->scatter_n != 0 || rx_cont) {
8127d661
BH		 3426 efx_ef10_handle_rx_bad_lbits(
3427 rx_queue, next_ptr_lbits,
3428 (rx_queue->removed_count +
3429 rx_queue->scatter_n + 1) &
3430 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
3431 return 0;
3432 }
3433
3434 /* Merged completion for multiple non-scattered packets */
3435 rx_queue->scatter_n = 1;
3436 rx_queue->scatter_len = 0;
3437 n_packets = n_descs;
3438 ++channel->n_rx_merge_events;
3439 channel->n_rx_merge_packets += n_packets;
3440 flags |= EFX_RX_PKT_PREFIX_LEN;
3441 } else {
3442 ++rx_queue->scatter_n;
3443 rx_queue->scatter_len += rx_bytes;
3444 if (rx_cont)
3445 return 0;
3446 n_packets = 1;
3447 }
3448
a0ee3541
JC		 3449 EFX_POPULATE_QWORD_5(errors, ESF_DZ_RX_ECRC_ERR, 1,
3450 ESF_DZ_RX_IPCKSUM_ERR, 1,
3451 ESF_DZ_RX_TCPUDP_CKSUM_ERR, 1,
3452 ESF_EZ_RX_IP_INNER_CHKSUM_ERR, 1,
3453 ESF_EZ_RX_TCP_UDP_INNER_CHKSUM_ERR, 1);
3454 EFX_AND_QWORD(errors, *event, errors);
3455 if (unlikely(!EFX_QWORD_IS_ZERO(errors))) {
3456 flags |= efx_ef10_handle_rx_event_errors(channel, n_packets,
90d2ea9f 3457 rx_encap_hdr,
a0ee3541 3458 rx_l3_class, rx_l4_class,
90d2ea9f 3459 event);
a0ee3541 3460 } else {
d8d8ccf2
BK		 3461 bool tcpudp = rx_l4_class == ESE_FZ_L4_CLASS_TCP ||
3462 rx_l4_class == ESE_FZ_L4_CLASS_UDP;
da50ae2e
JC		 3463
3464 switch (rx_encap_hdr) {
3465 case ESE_EZ_ENCAP_HDR_VXLAN: /* VxLAN or GENEVE */
3466 flags |= EFX_RX_PKT_CSUMMED; /* outer UDP csum */
3467 if (tcpudp)
3468 flags |= EFX_RX_PKT_CSUM_LEVEL; /* inner L4 */
3469 break;
3470 case ESE_EZ_ENCAP_HDR_GRE:
3471 case ESE_EZ_ENCAP_HDR_NONE:
3472 if (tcpudp)
3473 flags |= EFX_RX_PKT_CSUMMED;
3474 break;
3475 default:
3476 netdev_WARN(efx->net_dev,
3477 "unknown encapsulation type: event="
3478 EFX_QWORD_FMT "\n",
3479 EFX_QWORD_VAL(*event));
3480 }
8127d661
BH		 3481 }
3482
d8d8ccf2 3483 if (rx_l4_class == ESE_FZ_L4_CLASS_TCP)
8127d661
BH		 3484 flags |= EFX_RX_PKT_TCP;
3485
3486 channel->irq_mod_score += 2 * n_packets;
3487
3488 /* Handle received packet(s) */
3489 for (i = 0; i < n_packets; i++) {
3490 efx_rx_packet(rx_queue,
3491 rx_queue->removed_count & rx_queue->ptr_mask,
3492 rx_queue->scatter_n, rx_queue->scatter_len,
3493 flags);
3494 rx_queue->removed_count += rx_queue->scatter_n;
3495 }
3496
3497 rx_queue->scatter_n = 0;
3498 rx_queue->scatter_len = 0;
3499
3500 return n_packets;
3501}
3502
3503static int
3504efx_ef10_handle_tx_event(struct efx_channel *channel, efx_qword_t *event)
3505{
3506 struct efx_nic *efx = channel->efx;
3507 struct efx_tx_queue *tx_queue;
3508 unsigned int tx_ev_desc_ptr;
3509 unsigned int tx_ev_q_label;
3510 int tx_descs = 0;
3511
6aa7de05 3512 if (unlikely(READ_ONCE(efx->reset_pending)))
8127d661
BH		 3513 return 0;
3514
3515 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_TX_DROP_EVENT)))
3516 return 0;
3517
3518 /* Transmit completion */
3519 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, ESF_DZ_TX_DESCR_INDX);
3520 tx_ev_q_label = EFX_QWORD_FIELD(*event, ESF_DZ_TX_QLABEL);
3521 tx_queue = efx_channel_get_tx_queue(channel,
3522 tx_ev_q_label % EFX_TXQ_TYPES);
3523 tx_descs = ((tx_ev_desc_ptr + 1 - tx_queue->read_count) &
3524 tx_queue->ptr_mask);
3525 efx_xmit_done(tx_queue, tx_ev_desc_ptr & tx_queue->ptr_mask);
3526
3527 return tx_descs;
3528}
3529
3530static void
3531efx_ef10_handle_driver_event(struct efx_channel *channel, efx_qword_t *event)
3532{
3533 struct efx_nic *efx = channel->efx;
3534 int subcode;
3535
3536 subcode = EFX_QWORD_FIELD(*event, ESF_DZ_DRV_SUB_CODE);
3537
3538 switch (subcode) {
3539 case ESE_DZ_DRV_TIMER_EV:
3540 case ESE_DZ_DRV_WAKE_UP_EV:
3541 break;
3542 case ESE_DZ_DRV_START_UP_EV:
3543 /* event queue init complete. ok. */
3544 break;
3545 default:
3546 netif_err(efx, hw, efx->net_dev,
3547 "channel %d unknown driver event type %d"
3548 " (data " EFX_QWORD_FMT ")\n",
3549 channel->channel, subcode,
3550 EFX_QWORD_VAL(*event));
3551
3552 }
3553}
3554
3555static void efx_ef10_handle_driver_generated_event(struct efx_channel *channel,
3556 efx_qword_t *event)
3557{
3558 struct efx_nic *efx = channel->efx;
3559 u32 subcode;
3560
3561 subcode = EFX_QWORD_FIELD(*event, EFX_DWORD_0);
3562
3563 switch (subcode) {
3564 case EFX_EF10_TEST:
3565 channel->event_test_cpu = raw_smp_processor_id();
3566 break;
3567 case EFX_EF10_REFILL:
3568 /* The queue must be empty, so we won't receive any rx
3569 * events, so efx_process_channel() won't refill the
3570 * queue. Refill it here
3571 */
cce28794 3572 efx_fast_push_rx_descriptors(&channel->rx_queue, true);
8127d661
BH		 3573 break;
3574 default:
3575 netif_err(efx, hw, efx->net_dev,
3576 "channel %d unknown driver event type %u"
3577 " (data " EFX_QWORD_FMT ")\n",
3578 channel->channel, (unsigned) subcode,
3579 EFX_QWORD_VAL(*event));
3580 }
3581}
3582
3583static int efx_ef10_ev_process(struct efx_channel *channel, int quota)
3584{
3585 struct efx_nic *efx = channel->efx;
3586 efx_qword_t event, *p_event;
3587 unsigned int read_ptr;
3588 int ev_code;
3589 int tx_descs = 0;
3590 int spent = 0;
3591
75363a46
EB		 3592 if (quota <= 0)
3593 return spent;
3594
8127d661
BH		 3595 read_ptr = channel->eventq_read_ptr;
3596
3597 for (;;) {
3598 p_event = efx_event(channel, read_ptr);
3599 event = *p_event;
3600
3601 if (!efx_event_present(&event))
3602 break;
3603
3604 EFX_SET_QWORD(*p_event);
3605
3606 ++read_ptr;
3607
3608 ev_code = EFX_QWORD_FIELD(event, ESF_DZ_EV_CODE);
3609
3610 netif_vdbg(efx, drv, efx->net_dev,
3611 "processing event on %d " EFX_QWORD_FMT "\n",
3612 channel->channel, EFX_QWORD_VAL(event));
3613
3614 switch (ev_code) {
3615 case ESE_DZ_EV_CODE_MCDI_EV:
3616 efx_mcdi_process_event(channel, &event);
3617 break;
3618 case ESE_DZ_EV_CODE_RX_EV:
3619 spent += efx_ef10_handle_rx_event(channel, &event);
3620 if (spent >= quota) {
3621 /* XXX can we split a merged event to
3622 * avoid going over-quota?
3623 */
3624 spent = quota;
3625 goto out;
3626 }
3627 break;
3628 case ESE_DZ_EV_CODE_TX_EV:
3629 tx_descs += efx_ef10_handle_tx_event(channel, &event);
3630 if (tx_descs > efx->txq_entries) {
3631 spent = quota;
3632 goto out;
3633 } else if (++spent == quota) {
3634 goto out;
3635 }
3636 break;
3637 case ESE_DZ_EV_CODE_DRIVER_EV:
3638 efx_ef10_handle_driver_event(channel, &event);
3639 if (++spent == quota)
3640 goto out;
3641 break;
3642 case EFX_EF10_DRVGEN_EV:
3643 efx_ef10_handle_driver_generated_event(channel, &event);
3644 break;
3645 default:
3646 netif_err(efx, hw, efx->net_dev,
3647 "channel %d unknown event type %d"
3648 " (data " EFX_QWORD_FMT ")\n",
3649 channel->channel, ev_code,
3650 EFX_QWORD_VAL(event));
3651 }
3652 }
3653
3654out:
3655 channel->eventq_read_ptr = read_ptr;
3656 return spent;
3657}
3658
3659static void efx_ef10_ev_read_ack(struct efx_channel *channel)
3660{
3661 struct efx_nic *efx = channel->efx;
3662 efx_dword_t rptr;
3663
3664 if (EFX_EF10_WORKAROUND_35388(efx)) {
3665 BUILD_BUG_ON(EFX_MIN_EVQ_SIZE <
3666 (1 << ERF_DD_EVQ_IND_RPTR_WIDTH));
3667 BUILD_BUG_ON(EFX_MAX_EVQ_SIZE >
3668 (1 << 2 * ERF_DD_EVQ_IND_RPTR_WIDTH));
3669
3670 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
3671 EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH,
3672 ERF_DD_EVQ_IND_RPTR,
3673 (channel->eventq_read_ptr &
3674 channel->eventq_mask) >>
3675 ERF_DD_EVQ_IND_RPTR_WIDTH);
3676 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
3677 channel->channel);
3678 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
3679 EFE_DD_EVQ_IND_RPTR_FLAGS_LOW,
3680 ERF_DD_EVQ_IND_RPTR,
3681 channel->eventq_read_ptr &
3682 ((1 << ERF_DD_EVQ_IND_RPTR_WIDTH) - 1));
3683 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
3684 channel->channel);
3685 } else {
3686 EFX_POPULATE_DWORD_1(rptr, ERF_DZ_EVQ_RPTR,
3687 channel->eventq_read_ptr &
3688 channel->eventq_mask);
3689 efx_writed_page(efx, &rptr, ER_DZ_EVQ_RPTR, channel->channel);
3690 }
3691}
3692
3693static void efx_ef10_ev_test_generate(struct efx_channel *channel)
3694{
3695 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
3696 struct efx_nic *efx = channel->efx;
3697 efx_qword_t event;
3698 int rc;
3699
3700 EFX_POPULATE_QWORD_2(event,
3701 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
3702 ESF_DZ_EV_DATA, EFX_EF10_TEST);
3703
3704 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
3705
3706 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
3707 * already swapped the data to little-endian order.
3708 */
3709 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
3710 sizeof(efx_qword_t));
3711
3712 rc = efx_mcdi_rpc(efx, MC_CMD_DRIVER_EVENT, inbuf, sizeof(inbuf),
3713 NULL, 0, NULL);
3714 if (rc != 0)
3715 goto fail;
3716
3717 return;
3718
3719fail:
3720 WARN_ON(true);
3721 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
3722}
3723
3724void efx_ef10_handle_drain_event(struct efx_nic *efx)
3725{
3726 if (atomic_dec_and_test(&efx->active_queues))
3727 wake_up(&efx->flush_wq);
3728
3729 WARN_ON(atomic_read(&efx->active_queues) < 0);
3730}
3731
3732static int efx_ef10_fini_dmaq(struct efx_nic *efx)
3733{
3734 struct efx_ef10_nic_data *nic_data = efx->nic_data;
3735 struct efx_channel *channel;
3736 struct efx_tx_queue *tx_queue;
3737 struct efx_rx_queue *rx_queue;
3738 int pending;
3739
3740 /* If the MC has just rebooted, the TX/RX queues will have already been
3741 * torn down, but efx->active_queues needs to be set to zero.
3742 */
3743 if (nic_data->must_realloc_vis) {
3744 atomic_set(&efx->active_queues, 0);
3745 return 0;
3746 }
3747
3748 /* Do not attempt to write to the NIC during EEH recovery */
3749 if (efx->state != STATE_RECOVERY) {
3750 efx_for_each_channel(channel, efx) {
3751 efx_for_each_channel_rx_queue(rx_queue, channel)
3752 efx_ef10_rx_fini(rx_queue);
3753 efx_for_each_channel_tx_queue(tx_queue, channel)
3754 efx_ef10_tx_fini(tx_queue);
3755 }
3756
3757 wait_event_timeout(efx->flush_wq,
3758 atomic_read(&efx->active_queues) == 0,
3759 msecs_to_jiffies(EFX_MAX_FLUSH_TIME));
3760 pending = atomic_read(&efx->active_queues);
3761 if (pending) {
3762 netif_err(efx, hw, efx->net_dev, "failed to flush %d queues\n",
3763 pending);
3764 return -ETIMEDOUT;
3765 }
3766 }
3767
3768 return 0;
3769}
3770
e283546c
EC		 3771static void efx_ef10_prepare_flr(struct efx_nic *efx)
3772{
3773 atomic_set(&efx->active_queues, 0);
3774}
3775
8127d661
BH		 3776static bool efx_ef10_filter_equal(const struct efx_filter_spec *left,
3777 const struct efx_filter_spec *right)
3778{
3779 if ((left->match_flags ^ right->match_flags) |
3780 ((left->flags ^ right->flags) &
3781 (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)))
3782 return false;
3783
3784 return memcmp(&left->outer_vid, &right->outer_vid,
3785 sizeof(struct efx_filter_spec) -
3786 offsetof(struct efx_filter_spec, outer_vid)) == 0;
3787}
3788
3789static unsigned int efx_ef10_filter_hash(const struct efx_filter_spec *spec)
3790{
3791 BUILD_BUG_ON(offsetof(struct efx_filter_spec, outer_vid) & 3);
3792 return jhash2((const u32 *)&spec->outer_vid,
3793 (sizeof(struct efx_filter_spec) -
3794 offsetof(struct efx_filter_spec, outer_vid)) / 4,
3795 0);
3796 /* XXX should we randomise the initval? */
3797}
3798
3799/* Decide whether a filter should be exclusive or else should allow
3800 * delivery to additional recipients. Currently we decide that
3801 * filters for specific local unicast MAC and IP addresses are
3802 * exclusive.
3803 */
3804static bool efx_ef10_filter_is_exclusive(const struct efx_filter_spec *spec)
3805{
3806 if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC &&
3807 !is_multicast_ether_addr(spec->loc_mac))
3808 return true;
3809
3810 if ((spec->match_flags &
3811 (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) ==
3812 (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) {
3813 if (spec->ether_type == htons(ETH_P_IP) &&
3814 !ipv4_is_multicast(spec->loc_host[0]))
3815 return true;
3816 if (spec->ether_type == htons(ETH_P_IPV6) &&
3817 ((const u8 *)spec->loc_host)[0] != 0xff)
3818 return true;
3819 }
3820
3821 return false;
3822}
3823
3824static struct efx_filter_spec *
3825efx_ef10_filter_entry_spec(const struct efx_ef10_filter_table *table,
3826 unsigned int filter_idx)
3827{
3828 return (struct efx_filter_spec *)(table->entry[filter_idx].spec &
3829 ~EFX_EF10_FILTER_FLAGS);
3830}
3831
3832static unsigned int
3833efx_ef10_filter_entry_flags(const struct efx_ef10_filter_table *table,
3834 unsigned int filter_idx)
3835{
3836 return table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAGS;
3837}
3838
3839static void
3840efx_ef10_filter_set_entry(struct efx_ef10_filter_table *table,
3841 unsigned int filter_idx,
3842 const struct efx_filter_spec *spec,
3843 unsigned int flags)
3844{
3845 table->entry[filter_idx].spec = (unsigned long)spec | flags;
3846}
3847
9b410801
EC		 3848static void
3849efx_ef10_filter_push_prep_set_match_fields(struct efx_nic *efx,
3850 const struct efx_filter_spec *spec,
3851 efx_dword_t *inbuf)
3852{
3853 enum efx_encap_type encap_type = efx_filter_get_encap_type(spec);
3854 u32 match_fields = 0, uc_match, mc_match;
3855
3856 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3857 efx_ef10_filter_is_exclusive(spec) ?
3858 MC_CMD_FILTER_OP_IN_OP_INSERT :
3859 MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE);
3860
3861 /* Convert match flags and values. Unlike almost
3862 * everything else in MCDI, these fields are in
3863 * network byte order.
3864 */
3865#define COPY_VALUE(value, mcdi_field) \
3866 do { \
3867 match_fields |= \
3868 1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \
3869 mcdi_field ## _LBN; \
3870 BUILD_BUG_ON( \
3871 MC_CMD_FILTER_OP_IN_ ## mcdi_field ## _LEN < \
3872 sizeof(value)); \
3873 memcpy(MCDI_PTR(inbuf, FILTER_OP_IN_ ## mcdi_field), \
3874 &value, sizeof(value)); \
3875 } while (0)
3876#define COPY_FIELD(gen_flag, gen_field, mcdi_field) \
3877 if (spec->match_flags & EFX_FILTER_MATCH_ ## gen_flag) { \
3878 COPY_VALUE(spec->gen_field, mcdi_field); \
3879 }
3880 /* Handle encap filters first. They will always be mismatch
3881 * (unknown UC or MC) filters
3882 */
3883 if (encap_type) {
3884 /* ether_type and outer_ip_proto need to be variables
3885 * because COPY_VALUE wants to memcpy them
3886 */
3887 __be16 ether_type =
3888 htons(encap_type & EFX_ENCAP_FLAG_IPV6 ?
3889 ETH_P_IPV6 : ETH_P_IP);
3890 u8 vni_type = MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_GENEVE;
3891 u8 outer_ip_proto;
3892
3893 switch (encap_type & EFX_ENCAP_TYPES_MASK) {
3894 case EFX_ENCAP_TYPE_VXLAN:
3895 vni_type = MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_VXLAN;
3896 /* fallthrough */
3897 case EFX_ENCAP_TYPE_GENEVE:
3898 COPY_VALUE(ether_type, ETHER_TYPE);
3899 outer_ip_proto = IPPROTO_UDP;
3900 COPY_VALUE(outer_ip_proto, IP_PROTO);
3901 /* We always need to set the type field, even
3902 * though we're not matching on the TNI.
3903 */
3904 MCDI_POPULATE_DWORD_1(inbuf,
3905 FILTER_OP_EXT_IN_VNI_OR_VSID,
3906 FILTER_OP_EXT_IN_VNI_TYPE,
3907 vni_type);
3908 break;
3909 case EFX_ENCAP_TYPE_NVGRE:
3910 COPY_VALUE(ether_type, ETHER_TYPE);
3911 outer_ip_proto = IPPROTO_GRE;
3912 COPY_VALUE(outer_ip_proto, IP_PROTO);
3913 break;
3914 default:
3915 WARN_ON(1);
3916 }
3917
3918 uc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_LBN;
3919 mc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_LBN;
3920 } else {
3921 uc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_LBN;
3922 mc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_LBN;
3923 }
3924
3925 if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC_IG)
3926 match_fields |=
3927 is_multicast_ether_addr(spec->loc_mac) ?
3928 1 << mc_match :
3929 1 << uc_match;
3930 COPY_FIELD(REM_HOST, rem_host, SRC_IP);
3931 COPY_FIELD(LOC_HOST, loc_host, DST_IP);
3932 COPY_FIELD(REM_MAC, rem_mac, SRC_MAC);
3933 COPY_FIELD(REM_PORT, rem_port, SRC_PORT);
3934 COPY_FIELD(LOC_MAC, loc_mac, DST_MAC);
3935 COPY_FIELD(LOC_PORT, loc_port, DST_PORT);
3936 COPY_FIELD(ETHER_TYPE, ether_type, ETHER_TYPE);
3937 COPY_FIELD(INNER_VID, inner_vid, INNER_VLAN);
3938 COPY_FIELD(OUTER_VID, outer_vid, OUTER_VLAN);
3939 COPY_FIELD(IP_PROTO, ip_proto, IP_PROTO);
3940#undef COPY_FIELD
3941#undef COPY_VALUE
3942 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_MATCH_FIELDS,
3943 match_fields);
3944}
3945
8127d661
BH		 3946static void efx_ef10_filter_push_prep(struct efx_nic *efx,
3947 const struct efx_filter_spec *spec,
3948 efx_dword_t *inbuf, u64 handle,
3949 bool replacing)
3950{
3951 struct efx_ef10_nic_data *nic_data = efx->nic_data;
dcb4123c 3952 u32 flags = spec->flags;
8127d661 3953
9b410801 3954 memset(inbuf, 0, MC_CMD_FILTER_OP_EXT_IN_LEN);
8127d661 3955
dcb4123c
JC		 3956 /* Remove RSS flag if we don't have an RSS context. */
3957 if (flags & EFX_FILTER_FLAG_RX_RSS &&
3958 spec->rss_context == EFX_FILTER_RSS_CONTEXT_DEFAULT &&
3959 nic_data->rx_rss_context == EFX_EF10_RSS_CONTEXT_INVALID)
3960 flags &= ~EFX_FILTER_FLAG_RX_RSS;
3961
8127d661
BH		 3962 if (replacing) {
3963 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3964 MC_CMD_FILTER_OP_IN_OP_REPLACE);
3965 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, handle);
3966 } else {
9b410801 3967 efx_ef10_filter_push_prep_set_match_fields(efx, spec, inbuf);
8127d661
BH		 3968 }
3969
45b2449e 3970 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_PORT_ID, nic_data->vport_id);
8127d661
BH		 3971 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_DEST,
3972 spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ?
3973 MC_CMD_FILTER_OP_IN_RX_DEST_DROP :
3974 MC_CMD_FILTER_OP_IN_RX_DEST_HOST);
e3d36293 3975 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DOMAIN, 0);
8127d661
BH		 3976 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DEST,
3977 MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT);
a0bc3487
BH		 3978 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_QUEUE,
3979 spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ?
3980 0 : spec->dmaq_id);
8127d661 3981 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_MODE,
dcb4123c 3982 (flags & EFX_FILTER_FLAG_RX_RSS) ?
8127d661
BH		 3983 MC_CMD_FILTER_OP_IN_RX_MODE_RSS :
3984 MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE);
dcb4123c 3985 if (flags & EFX_FILTER_FLAG_RX_RSS)
8127d661
BH		 3986 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_CONTEXT,
3987 spec->rss_context !=
3988 EFX_FILTER_RSS_CONTEXT_DEFAULT ?
3989 spec->rss_context : nic_data->rx_rss_context);
3990}
3991
3992static int efx_ef10_filter_push(struct efx_nic *efx,
3993 const struct efx_filter_spec *spec,
3994 u64 *handle, bool replacing)
3995{
9b410801
EC		 3996 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_EXT_IN_LEN);
3997 MCDI_DECLARE_BUF(outbuf, MC_CMD_FILTER_OP_EXT_OUT_LEN);
8127d661
BH		 3998 int rc;
3999
4000 efx_ef10_filter_push_prep(efx, spec, inbuf, *handle, replacing);
4001 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
4002 outbuf, sizeof(outbuf), NULL);
4003 if (rc == 0)
4004 *handle = MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE);
065e64c4
BH		 4005 if (rc == -ENOSPC)
4006 rc = -EBUSY; /* to match efx_farch_filter_insert() */
8127d661
BH		 4007 return rc;
4008}
4009
7ac0dd9d 4010static u32 efx_ef10_filter_mcdi_flags_from_spec(const struct efx_filter_spec *spec)
8127d661 4011{
9b410801 4012 enum efx_encap_type encap_type = efx_filter_get_encap_type(spec);
7ac0dd9d 4013 unsigned int match_flags = spec->match_flags;
9b410801 4014 unsigned int uc_match, mc_match;
7ac0dd9d
AR		 4015 u32 mcdi_flags = 0;
4016
9b410801
EC		 4017#define MAP_FILTER_TO_MCDI_FLAG(gen_flag, mcdi_field, encap) { \
4018 unsigned int old_match_flags = match_flags; \
7ac0dd9d
AR		 4019 match_flags &= ~EFX_FILTER_MATCH_ ## gen_flag; \
4020 if (match_flags != old_match_flags) \
4021 mcdi_flags |= \
9b410801
EC		 4022 (1 << ((encap) ? \
4023 MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_ ## \
4024 mcdi_field ## _LBN : \
4025 MC_CMD_FILTER_OP_EXT_IN_MATCH_ ##\
4026 mcdi_field ## _LBN)); \
7ac0dd9d 4027 }
9b410801
EC		 4028 /* inner or outer based on encap type */
4029 MAP_FILTER_TO_MCDI_FLAG(REM_HOST, SRC_IP, encap_type);
4030 MAP_FILTER_TO_MCDI_FLAG(LOC_HOST, DST_IP, encap_type);
4031 MAP_FILTER_TO_MCDI_FLAG(REM_MAC, SRC_MAC, encap_type);
4032 MAP_FILTER_TO_MCDI_FLAG(REM_PORT, SRC_PORT, encap_type);
4033 MAP_FILTER_TO_MCDI_FLAG(LOC_MAC, DST_MAC, encap_type);
4034 MAP_FILTER_TO_MCDI_FLAG(LOC_PORT, DST_PORT, encap_type);
4035 MAP_FILTER_TO_MCDI_FLAG(ETHER_TYPE, ETHER_TYPE, encap_type);
4036 MAP_FILTER_TO_MCDI_FLAG(IP_PROTO, IP_PROTO, encap_type);
4037 /* always outer */
4038 MAP_FILTER_TO_MCDI_FLAG(INNER_VID, INNER_VLAN, false);
4039 MAP_FILTER_TO_MCDI_FLAG(OUTER_VID, OUTER_VLAN, false);
7ac0dd9d
AR		 4040#undef MAP_FILTER_TO_MCDI_FLAG
4041
9b410801
EC		 4042 /* special handling for encap type, and mismatch */
4043 if (encap_type) {
4044 match_flags &= ~EFX_FILTER_MATCH_ENCAP_TYPE;
4045 mcdi_flags |=
4046 (1 << MC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_LBN);
4047 mcdi_flags |= (1 << MC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_LBN);
4048
4049 uc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_LBN;
4050 mc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_LBN;
4051 } else {
4052 uc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_LBN;
4053 mc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_LBN;
4054 }
4055
4056 if (match_flags & EFX_FILTER_MATCH_LOC_MAC_IG) {
4057 match_flags &= ~EFX_FILTER_MATCH_LOC_MAC_IG;
4058 mcdi_flags |=
4059 is_multicast_ether_addr(spec->loc_mac) ?
4060 1 << mc_match :
4061 1 << uc_match;
4062 }
4063
7ac0dd9d
AR		 4064 /* Did we map them all? */
4065 WARN_ON_ONCE(match_flags);
4066
4067 return mcdi_flags;
4068}
4069
4070static int efx_ef10_filter_pri(struct efx_ef10_filter_table *table,
4071 const struct efx_filter_spec *spec)
4072{
4073 u32 mcdi_flags = efx_ef10_filter_mcdi_flags_from_spec(spec);
8127d661
BH		 4074 unsigned int match_pri;
4075
4076 for (match_pri = 0;
4077 match_pri < table->rx_match_count;
4078 match_pri++)
7ac0dd9d 4079 if (table->rx_match_mcdi_flags[match_pri] == mcdi_flags)
8127d661
BH		 4080 return match_pri;
4081
4082 return -EPROTONOSUPPORT;
4083}
4084
4085static s32 efx_ef10_filter_insert(struct efx_nic *efx,
4086 struct efx_filter_spec *spec,
4087 bool replace_equal)
4088{
4089 struct efx_ef10_filter_table *table = efx->filter_state;
4090 DECLARE_BITMAP(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
4091 struct efx_filter_spec *saved_spec;
4092 unsigned int match_pri, hash;
4093 unsigned int priv_flags;
4094 bool replacing = false;
4095 int ins_index = -1;
4096 DEFINE_WAIT(wait);
4097 bool is_mc_recip;
4098 s32 rc;
4099
4100 /* For now, only support RX filters */
4101 if ((spec->flags & (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)) !=
4102 EFX_FILTER_FLAG_RX)
4103 return -EINVAL;
4104
7ac0dd9d 4105 rc = efx_ef10_filter_pri(table, spec);
8127d661
BH		 4106 if (rc < 0)
4107 return rc;
4108 match_pri = rc;
4109
4110 hash = efx_ef10_filter_hash(spec);
4111 is_mc_recip = efx_filter_is_mc_recipient(spec);
4112 if (is_mc_recip)
4113 bitmap_zero(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
4114
4115 /* Find any existing filters with the same match tuple or
4116 * else a free slot to insert at. If any of them are busy,
4117 * we have to wait and retry.
4118 */
4119 for (;;) {
4120 unsigned int depth = 1;
4121 unsigned int i;
4122
4123 spin_lock_bh(&efx->filter_lock);
4124
4125 for (;;) {
4126 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
4127 saved_spec = efx_ef10_filter_entry_spec(table, i);
4128
4129 if (!saved_spec) {
4130 if (ins_index < 0)
4131 ins_index = i;
4132 } else if (efx_ef10_filter_equal(spec, saved_spec)) {
4133 if (table->entry[i].spec &
4134 EFX_EF10_FILTER_FLAG_BUSY)
4135 break;
4136 if (spec->priority < saved_spec->priority &&
7665d1ab 4137 spec->priority != EFX_FILTER_PRI_AUTO) {
8127d661
BH		 4138 rc = -EPERM;
4139 goto out_unlock;
4140 }
4141 if (!is_mc_recip) {
4142 /* This is the only one */
4143 if (spec->priority ==
4144 saved_spec->priority &&
4145 !replace_equal) {
4146 rc = -EEXIST;
4147 goto out_unlock;
4148 }
4149 ins_index = i;
4150 goto found;
4151 } else if (spec->priority >
4152 saved_spec->priority ||
4153 (spec->priority ==
4154 saved_spec->priority &&
4155 replace_equal)) {
4156 if (ins_index < 0)
4157 ins_index = i;
4158 else
4159 __set_bit(depth, mc_rem_map);
4160 }
4161 }
4162
4163 /* Once we reach the maximum search depth, use
4164 * the first suitable slot or return -EBUSY if
4165 * there was none
4166 */
4167 if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) {
4168 if (ins_index < 0) {
4169 rc = -EBUSY;
4170 goto out_unlock;
4171 }
4172 goto found;
4173 }
4174
4175 ++depth;
4176 }
4177
4178 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE);
4179 spin_unlock_bh(&efx->filter_lock);
4180 schedule();
4181 }
4182
4183found:
4184 /* Create a software table entry if necessary, and mark it
4185 * busy. We might yet fail to insert, but any attempt to
4186 * insert a conflicting filter while we're waiting for the
4187 * firmware must find the busy entry.
4188 */
4189 saved_spec = efx_ef10_filter_entry_spec(table, ins_index);
4190 if (saved_spec) {
7665d1ab
BH		 4191 if (spec->priority == EFX_FILTER_PRI_AUTO &&
4192 saved_spec->priority >= EFX_FILTER_PRI_AUTO) {
8127d661 4193 /* Just make sure it won't be removed */
7665d1ab
BH		 4194 if (saved_spec->priority > EFX_FILTER_PRI_AUTO)
4195 saved_spec->flags |= EFX_FILTER_FLAG_RX_OVER_AUTO;
8127d661 4196 table->entry[ins_index].spec &=
b59e6ef8 4197 ~EFX_EF10_FILTER_FLAG_AUTO_OLD;
8127d661
BH		 4198 rc = ins_index;
4199 goto out_unlock;
4200 }
4201 replacing = true;
4202 priv_flags = efx_ef10_filter_entry_flags(table, ins_index);
4203 } else {
4204 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC);
4205 if (!saved_spec) {
4206 rc = -ENOMEM;
4207 goto out_unlock;
4208 }
4209 *saved_spec = *spec;
4210 priv_flags = 0;
4211 }
4212 efx_ef10_filter_set_entry(table, ins_index, saved_spec,
4213 priv_flags | EFX_EF10_FILTER_FLAG_BUSY);
4214
4215 /* Mark lower-priority multicast recipients busy prior to removal */
4216 if (is_mc_recip) {
4217 unsigned int depth, i;
4218
4219 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
4220 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
4221 if (test_bit(depth, mc_rem_map))
4222 table->entry[i].spec |=
4223 EFX_EF10_FILTER_FLAG_BUSY;
4224 }
4225 }
4226
4227 spin_unlock_bh(&efx->filter_lock);
4228
4229 rc = efx_ef10_filter_push(efx, spec, &table->entry[ins_index].handle,
4230 replacing);
4231
4232 /* Finalise the software table entry */
4233 spin_lock_bh(&efx->filter_lock);
4234 if (rc == 0) {
4235 if (replacing) {
4236 /* Update the fields that may differ */
7665d1ab
BH		 4237 if (saved_spec->priority == EFX_FILTER_PRI_AUTO)
4238 saved_spec->flags |=
4239 EFX_FILTER_FLAG_RX_OVER_AUTO;
8127d661 4240 saved_spec->priority = spec->priority;
7665d1ab 4241 saved_spec->flags &= EFX_FILTER_FLAG_RX_OVER_AUTO;
8127d661
BH		 4242 saved_spec->flags |= spec->flags;
4243 saved_spec->rss_context = spec->rss_context;
4244 saved_spec->dmaq_id = spec->dmaq_id;
4245 }
4246 } else if (!replacing) {
4247 kfree(saved_spec);
4248 saved_spec = NULL;
4249 }
4250 efx_ef10_filter_set_entry(table, ins_index, saved_spec, priv_flags);
4251
4252 /* Remove and finalise entries for lower-priority multicast
4253 * recipients
4254 */
4255 if (is_mc_recip) {
bb53f4d4 4256 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_EXT_IN_LEN);
8127d661
BH		 4257 unsigned int depth, i;
4258
4259 memset(inbuf, 0, sizeof(inbuf));
4260
4261 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
4262 if (!test_bit(depth, mc_rem_map))
4263 continue;
4264
4265 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
4266 saved_spec = efx_ef10_filter_entry_spec(table, i);
4267 priv_flags = efx_ef10_filter_entry_flags(table, i);
4268
4269 if (rc == 0) {
4270 spin_unlock_bh(&efx->filter_lock);
4271 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
4272 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
4273 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
4274 table->entry[i].handle);
4275 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP,
4276 inbuf, sizeof(inbuf),
4277 NULL, 0, NULL);
4278 spin_lock_bh(&efx->filter_lock);
4279 }
4280
4281 if (rc == 0) {
4282 kfree(saved_spec);
4283 saved_spec = NULL;
4284 priv_flags = 0;
4285 } else {
4286 priv_flags &= ~EFX_EF10_FILTER_FLAG_BUSY;
4287 }
4288 efx_ef10_filter_set_entry(table, i, saved_spec,
4289 priv_flags);
4290 }
4291 }
4292
4293 /* If successful, return the inserted filter ID */
4294 if (rc == 0)
0ccb998b 4295 rc = efx_ef10_make_filter_id(match_pri, ins_index);
8127d661
BH		 4296
4297 wake_up_all(&table->waitq);
4298out_unlock:
4299 spin_unlock_bh(&efx->filter_lock);
4300 finish_wait(&table->waitq, &wait);
4301 return rc;
4302}
4303
9fd8095d 4304static void efx_ef10_filter_update_rx_scatter(struct efx_nic *efx)
8127d661
BH		 4305{
4306 /* no need to do anything here on EF10 */
4307}
4308
4309/* Remove a filter.
b59e6ef8
BH		 4310 * If !by_index, remove by ID
4311 * If by_index, remove by index
8127d661
BH		 4312 * Filter ID may come from userland and must be range-checked.
4313 */
4314static int efx_ef10_filter_remove_internal(struct efx_nic *efx,
fbd79120 4315 unsigned int priority_mask,
b59e6ef8 4316 u32 filter_id, bool by_index)
8127d661 4317{
0ccb998b 4318 unsigned int filter_idx = efx_ef10_filter_get_unsafe_id(filter_id);
8127d661
BH		 4319 struct efx_ef10_filter_table *table = efx->filter_state;
4320 MCDI_DECLARE_BUF(inbuf,
4321 MC_CMD_FILTER_OP_IN_HANDLE_OFST +
4322 MC_CMD_FILTER_OP_IN_HANDLE_LEN);
4323 struct efx_filter_spec *spec;
4324 DEFINE_WAIT(wait);
4325 int rc;
4326
4327 /* Find the software table entry and mark it busy. Don't
4328 * remove it yet; any attempt to update while we're waiting
4329 * for the firmware must find the busy entry.
4330 */
4331 for (;;) {
4332 spin_lock_bh(&efx->filter_lock);
4333 if (!(table->entry[filter_idx].spec &
4334 EFX_EF10_FILTER_FLAG_BUSY))
4335 break;
4336 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE);
4337 spin_unlock_bh(&efx->filter_lock);
4338 schedule();
4339 }
7665d1ab 4340
8127d661 4341 spec = efx_ef10_filter_entry_spec(table, filter_idx);
7665d1ab 4342 if (!spec ||
b59e6ef8 4343 (!by_index &&
7ac0dd9d 4344 efx_ef10_filter_pri(table, spec) !=
0ccb998b 4345 efx_ef10_filter_get_unsafe_pri(filter_id))) {
8127d661
BH		 4346 rc = -ENOENT;
4347 goto out_unlock;
4348 }
7665d1ab
BH		 4349
4350 if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO &&
fbd79120 4351 priority_mask == (1U << EFX_FILTER_PRI_AUTO)) {
7665d1ab
BH		 4352 /* Just remove flags */
4353 spec->flags &= ~EFX_FILTER_FLAG_RX_OVER_AUTO;
b59e6ef8 4354 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_AUTO_OLD;
7665d1ab
BH		 4355 rc = 0;
4356 goto out_unlock;
4357 }
4358
fbd79120 4359 if (!(priority_mask & (1U << spec->priority))) {
7665d1ab
BH		 4360 rc = -ENOENT;
4361 goto out_unlock;
4362 }
4363
8127d661
BH		 4364 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
4365 spin_unlock_bh(&efx->filter_lock);
4366
7665d1ab 4367 if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO) {
b59e6ef8 4368 /* Reset to an automatic filter */
8127d661
BH		 4369
4370 struct efx_filter_spec new_spec = *spec;
4371
7665d1ab 4372 new_spec.priority = EFX_FILTER_PRI_AUTO;
8127d661 4373 new_spec.flags = (EFX_FILTER_FLAG_RX |
f1c2ef40
BK		 4374 (efx_rss_enabled(efx) ?
4375 EFX_FILTER_FLAG_RX_RSS : 0));
8127d661
BH		 4376 new_spec.dmaq_id = 0;
4377 new_spec.rss_context = EFX_FILTER_RSS_CONTEXT_DEFAULT;
4378 rc = efx_ef10_filter_push(efx, &new_spec,
4379 &table->entry[filter_idx].handle,
4380 true);
4381
4382 spin_lock_bh(&efx->filter_lock);
4383 if (rc == 0)
4384 *spec = new_spec;
4385 } else {
4386 /* Really remove the filter */
4387
4388 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
4389 efx_ef10_filter_is_exclusive(spec) ?
4390 MC_CMD_FILTER_OP_IN_OP_REMOVE :
4391 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
4392 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
4393 table->entry[filter_idx].handle);
105eac6c
BK		 4394 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FILTER_OP,
4395 inbuf, sizeof(inbuf), NULL, 0, NULL);
8127d661
BH		 4396
4397 spin_lock_bh(&efx->filter_lock);
105eac6c
BK		 4398 if ((rc == 0) || (rc == -ENOENT)) {
4399 /* Filter removed OK or didn't actually exist */
8127d661
BH		 4400 kfree(spec);
4401 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
105eac6c
BK		 4402 } else {
4403 efx_mcdi_display_error(efx, MC_CMD_FILTER_OP,
bb53f4d4 4404 MC_CMD_FILTER_OP_EXT_IN_LEN,
105eac6c 4405 NULL, 0, rc);
8127d661
BH		 4406 }
4407 }
7665d1ab 4408
8127d661
BH		 4409 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY;
4410 wake_up_all(&table->waitq);
4411out_unlock:
4412 spin_unlock_bh(&efx->filter_lock);
4413 finish_wait(&table->waitq, &wait);
4414 return rc;
4415}
4416
4417static int efx_ef10_filter_remove_safe(struct efx_nic *efx,
4418 enum efx_filter_priority priority,
4419 u32 filter_id)
4420{
fbd79120
BH		 4421 return efx_ef10_filter_remove_internal(efx, 1U << priority,
4422 filter_id, false);
8127d661
BH		 4423}
4424
8c915620
EC		 4425static void efx_ef10_filter_remove_unsafe(struct efx_nic *efx,
4426 enum efx_filter_priority priority,
4427 u32 filter_id)
12fb0da4 4428{
8c915620
EC		 4429 if (filter_id == EFX_EF10_FILTER_ID_INVALID)
4430 return;
4431 efx_ef10_filter_remove_internal(efx, 1U << priority, filter_id, true);
12fb0da4
EC		 4432}
4433
8127d661
BH		 4434static int efx_ef10_filter_get_safe(struct efx_nic *efx,
4435 enum efx_filter_priority priority,
4436 u32 filter_id, struct efx_filter_spec *spec)
4437{
0ccb998b 4438 unsigned int filter_idx = efx_ef10_filter_get_unsafe_id(filter_id);
8127d661
BH		 4439 struct efx_ef10_filter_table *table = efx->filter_state;
4440 const struct efx_filter_spec *saved_spec;
4441 int rc;
4442
4443 spin_lock_bh(&efx->filter_lock);
4444 saved_spec = efx_ef10_filter_entry_spec(table, filter_idx);
4445 if (saved_spec && saved_spec->priority == priority &&
7ac0dd9d 4446 efx_ef10_filter_pri(table, saved_spec) ==
0ccb998b 4447 efx_ef10_filter_get_unsafe_pri(filter_id)) {
8127d661
BH		 4448 *spec = *saved_spec;
4449 rc = 0;
4450 } else {
4451 rc = -ENOENT;
4452 }
4453 spin_unlock_bh(&efx->filter_lock);
4454 return rc;
4455}
4456
fbd79120 4457static int efx_ef10_filter_clear_rx(struct efx_nic *efx,
8127d661
BH		 4458 enum efx_filter_priority priority)
4459{
fbd79120
BH		 4460 unsigned int priority_mask;
4461 unsigned int i;
4462 int rc;
4463
4464 priority_mask = (((1U << (priority + 1)) - 1) &
4465 ~(1U << EFX_FILTER_PRI_AUTO));
4466
4467 for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) {
4468 rc = efx_ef10_filter_remove_internal(efx, priority_mask,
4469 i, true);
4470 if (rc && rc != -ENOENT)
4471 return rc;
4472 }
4473
4474 return 0;
8127d661
BH		 4475}
4476
4477static u32 efx_ef10_filter_count_rx_used(struct efx_nic *efx,
4478 enum efx_filter_priority priority)
4479{
4480 struct efx_ef10_filter_table *table = efx->filter_state;
4481 unsigned int filter_idx;
4482 s32 count = 0;
4483
4484 spin_lock_bh(&efx->filter_lock);
4485 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
4486 if (table->entry[filter_idx].spec &&
4487 efx_ef10_filter_entry_spec(table, filter_idx)->priority ==
4488 priority)
4489 ++count;
4490 }
4491 spin_unlock_bh(&efx->filter_lock);
4492 return count;
4493}
4494
4495static u32 efx_ef10_filter_get_rx_id_limit(struct efx_nic *efx)
4496{
4497 struct efx_ef10_filter_table *table = efx->filter_state;
4498
0ccb998b 4499 return table->rx_match_count * HUNT_FILTER_TBL_ROWS * 2;
8127d661
BH		 4500}
4501
4502static s32 efx_ef10_filter_get_rx_ids(struct efx_nic *efx,
4503 enum efx_filter_priority priority,
4504 u32 *buf, u32 size)
4505{
4506 struct efx_ef10_filter_table *table = efx->filter_state;
4507 struct efx_filter_spec *spec;
4508 unsigned int filter_idx;
4509 s32 count = 0;
4510
4511 spin_lock_bh(&efx->filter_lock);
4512 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
4513 spec = efx_ef10_filter_entry_spec(table, filter_idx);
4514 if (spec && spec->priority == priority) {
4515 if (count == size) {
4516 count = -EMSGSIZE;
4517 break;
4518 }
0ccb998b
JC		 4519 buf[count++] =
4520 efx_ef10_make_filter_id(
4521 efx_ef10_filter_pri(table, spec),
8127d661
BH		 4522 filter_idx);
4523 }
4524 }
4525 spin_unlock_bh(&efx->filter_lock);
4526 return count;
4527}
4528
4529#ifdef CONFIG_RFS_ACCEL
4530
4531static efx_mcdi_async_completer efx_ef10_filter_rfs_insert_complete;
4532
4533static s32 efx_ef10_filter_rfs_insert(struct efx_nic *efx,
4534 struct efx_filter_spec *spec)
4535{
4536 struct efx_ef10_filter_table *table = efx->filter_state;
bb53f4d4 4537 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_EXT_IN_LEN);
8127d661
BH		 4538 struct efx_filter_spec *saved_spec;
4539 unsigned int hash, i, depth = 1;
4540 bool replacing = false;
4541 int ins_index = -1;
4542 u64 cookie;
4543 s32 rc;
4544
4545 /* Must be an RX filter without RSS and not for a multicast
4546 * destination address (RFS only works for connected sockets).
4547 * These restrictions allow us to pass only a tiny amount of
4548 * data through to the completion function.
4549 */
4550 EFX_WARN_ON_PARANOID(spec->flags !=
4551 (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_RX_SCATTER));
4552 EFX_WARN_ON_PARANOID(spec->priority != EFX_FILTER_PRI_HINT);
4553 EFX_WARN_ON_PARANOID(efx_filter_is_mc_recipient(spec));
4554
4555 hash = efx_ef10_filter_hash(spec);
4556
4557 spin_lock_bh(&efx->filter_lock);
4558
4559 /* Find any existing filter with the same match tuple or else
4560 * a free slot to insert at. If an existing filter is busy,
4561 * we have to give up.
4562 */
4563 for (;;) {
4564 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
4565 saved_spec = efx_ef10_filter_entry_spec(table, i);
4566
4567 if (!saved_spec) {
4568 if (ins_index < 0)
4569 ins_index = i;
4570 } else if (efx_ef10_filter_equal(spec, saved_spec)) {
4571 if (table->entry[i].spec & EFX_EF10_FILTER_FLAG_BUSY) {
4572 rc = -EBUSY;
4573 goto fail_unlock;
4574 }
8127d661
BH		 4575 if (spec->priority < saved_spec->priority) {
4576 rc = -EPERM;
4577 goto fail_unlock;
4578 }
4579 ins_index = i;
4580 break;
4581 }
4582
4583 /* Once we reach the maximum search depth, use the
4584 * first suitable slot or return -EBUSY if there was
4585 * none
4586 */
4587 if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) {
4588 if (ins_index < 0) {
4589 rc = -EBUSY;
4590 goto fail_unlock;
4591 }
4592 break;
4593 }
4594
4595 ++depth;
4596 }
4597
4598 /* Create a software table entry if necessary, and mark it
4599 * busy. We might yet fail to insert, but any attempt to
4600 * insert a conflicting filter while we're waiting for the
4601 * firmware must find the busy entry.
4602 */
4603 saved_spec = efx_ef10_filter_entry_spec(table, ins_index);
4604 if (saved_spec) {
4605 replacing = true;
4606 } else {
4607 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC);
4608 if (!saved_spec) {
4609 rc = -ENOMEM;
4610 goto fail_unlock;
4611 }
4612 *saved_spec = *spec;
4613 }
4614 efx_ef10_filter_set_entry(table, ins_index, saved_spec,
4615 EFX_EF10_FILTER_FLAG_BUSY);
4616
4617 spin_unlock_bh(&efx->filter_lock);
4618
4619 /* Pack up the variables needed on completion */
4620 cookie = replacing << 31 | ins_index << 16 | spec->dmaq_id;
4621
4622 efx_ef10_filter_push_prep(efx, spec, inbuf,
4623 table->entry[ins_index].handle, replacing);
4624 efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
4625 MC_CMD_FILTER_OP_OUT_LEN,
4626 efx_ef10_filter_rfs_insert_complete, cookie);
4627
4628 return ins_index;
4629
4630fail_unlock:
4631 spin_unlock_bh(&efx->filter_lock);
4632 return rc;
4633}
4634
4635static void
4636efx_ef10_filter_rfs_insert_complete(struct efx_nic *efx, unsigned long cookie,
4637 int rc, efx_dword_t *outbuf,
4638 size_t outlen_actual)
4639{
4640 struct efx_ef10_filter_table *table = efx->filter_state;
4641 unsigned int ins_index, dmaq_id;
4642 struct efx_filter_spec *spec;
4643 bool replacing;
4644
4645 /* Unpack the cookie */
4646 replacing = cookie >> 31;
4647 ins_index = (cookie >> 16) & (HUNT_FILTER_TBL_ROWS - 1);
4648 dmaq_id = cookie & 0xffff;
4649
4650 spin_lock_bh(&efx->filter_lock);
4651 spec = efx_ef10_filter_entry_spec(table, ins_index);
4652 if (rc == 0) {
4653 table->entry[ins_index].handle =
4654 MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE);
4655 if (replacing)
4656 spec->dmaq_id = dmaq_id;
4657 } else if (!replacing) {
4658 kfree(spec);
4659 spec = NULL;
4660 }
4661 efx_ef10_filter_set_entry(table, ins_index, spec, 0);
4662 spin_unlock_bh(&efx->filter_lock);
4663
4664 wake_up_all(&table->waitq);
4665}
4666
4667static void
4668efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx,
4669 unsigned long filter_idx,
4670 int rc, efx_dword_t *outbuf,
4671 size_t outlen_actual);
4672
4673static bool efx_ef10_filter_rfs_expire_one(struct efx_nic *efx, u32 flow_id,
4674 unsigned int filter_idx)
4675{
4676 struct efx_ef10_filter_table *table = efx->filter_state;
4677 struct efx_filter_spec *spec =
4678 efx_ef10_filter_entry_spec(table, filter_idx);
4679 MCDI_DECLARE_BUF(inbuf,
4680 MC_CMD_FILTER_OP_IN_HANDLE_OFST +
4681 MC_CMD_FILTER_OP_IN_HANDLE_LEN);
4682
4683 if (!spec ||
4684 (table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAG_BUSY) ||
4685 spec->priority != EFX_FILTER_PRI_HINT ||
4686 !rps_may_expire_flow(efx->net_dev, spec->dmaq_id,
4687 flow_id, filter_idx))
4688 return false;
4689
4690 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
4691 MC_CMD_FILTER_OP_IN_OP_REMOVE);
4692 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
4693 table->entry[filter_idx].handle);
4694 if (efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf), 0,
4695 efx_ef10_filter_rfs_expire_complete, filter_idx))
4696 return false;
4697
4698 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
4699 return true;
4700}
4701
4702static void
4703efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx,
4704 unsigned long filter_idx,
4705 int rc, efx_dword_t *outbuf,
4706 size_t outlen_actual)
4707{
4708 struct efx_ef10_filter_table *table = efx->filter_state;
4709 struct efx_filter_spec *spec =
4710 efx_ef10_filter_entry_spec(table, filter_idx);
4711
4712 spin_lock_bh(&efx->filter_lock);
4713 if (rc == 0) {
4714 kfree(spec);
4715 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
4716 }
4717 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY;
4718 wake_up_all(&table->waitq);
4719 spin_unlock_bh(&efx->filter_lock);
4720}
4721
4722#endif /* CONFIG_RFS_ACCEL */
4723
9b410801 4724static int efx_ef10_filter_match_flags_from_mcdi(bool encap, u32 mcdi_flags)
8127d661
BH		 4725{
4726 int match_flags = 0;
4727
9b410801 4728#define MAP_FLAG(gen_flag, mcdi_field) do { \
8127d661 4729 u32 old_mcdi_flags = mcdi_flags; \
9b410801
EC		 4730 mcdi_flags &= ~(1 << MC_CMD_FILTER_OP_EXT_IN_MATCH_ ## \
4731 mcdi_field ## _LBN); \
8127d661
BH		 4732 if (mcdi_flags != old_mcdi_flags) \
4733 match_flags |= EFX_FILTER_MATCH_ ## gen_flag; \
9b410801
EC		 4734 } while (0)
4735
4736 if (encap) {
4737 /* encap filters must specify encap type */
4738 match_flags |= EFX_FILTER_MATCH_ENCAP_TYPE;
4739 /* and imply ethertype and ip proto */
4740 mcdi_flags &=
4741 ~(1 << MC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_LBN);
4742 mcdi_flags &=
4743 ~(1 << MC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_LBN);
4744 /* VLAN tags refer to the outer packet */
4745 MAP_FLAG(INNER_VID, INNER_VLAN);
4746 MAP_FLAG(OUTER_VID, OUTER_VLAN);
4747 /* everything else refers to the inner packet */
4748 MAP_FLAG(LOC_MAC_IG, IFRM_UNKNOWN_UCAST_DST);
4749 MAP_FLAG(LOC_MAC_IG, IFRM_UNKNOWN_MCAST_DST);
4750 MAP_FLAG(REM_HOST, IFRM_SRC_IP);
4751 MAP_FLAG(LOC_HOST, IFRM_DST_IP);
4752 MAP_FLAG(REM_MAC, IFRM_SRC_MAC);
4753 MAP_FLAG(REM_PORT, IFRM_SRC_PORT);
4754 MAP_FLAG(LOC_MAC, IFRM_DST_MAC);
4755 MAP_FLAG(LOC_PORT, IFRM_DST_PORT);
4756 MAP_FLAG(ETHER_TYPE, IFRM_ETHER_TYPE);
4757 MAP_FLAG(IP_PROTO, IFRM_IP_PROTO);
4758 } else {
4759 MAP_FLAG(LOC_MAC_IG, UNKNOWN_UCAST_DST);
4760 MAP_FLAG(LOC_MAC_IG, UNKNOWN_MCAST_DST);
4761 MAP_FLAG(REM_HOST, SRC_IP);
4762 MAP_FLAG(LOC_HOST, DST_IP);
4763 MAP_FLAG(REM_MAC, SRC_MAC);
4764 MAP_FLAG(REM_PORT, SRC_PORT);
4765 MAP_FLAG(LOC_MAC, DST_MAC);
4766 MAP_FLAG(LOC_PORT, DST_PORT);
4767 MAP_FLAG(ETHER_TYPE, ETHER_TYPE);
4768 MAP_FLAG(INNER_VID, INNER_VLAN);
4769 MAP_FLAG(OUTER_VID, OUTER_VLAN);
4770 MAP_FLAG(IP_PROTO, IP_PROTO);
8127d661 4771 }
8127d661
BH		 4772#undef MAP_FLAG
4773
4774 /* Did we map them all? */
4775 if (mcdi_flags)
4776 return -EINVAL;
4777
4778 return match_flags;
4779}
4780
34813fe2
AR		 4781static void efx_ef10_filter_cleanup_vlans(struct efx_nic *efx)
4782{
4783 struct efx_ef10_filter_table *table = efx->filter_state;
4784 struct efx_ef10_filter_vlan *vlan, *next_vlan;
4785
4786 /* See comment in efx_ef10_filter_table_remove() */
4787 if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
4788 return;
4789
4790 if (!table)
4791 return;
4792
4793 list_for_each_entry_safe(vlan, next_vlan, &table->vlan_list, list)
4794 efx_ef10_filter_del_vlan_internal(efx, vlan);
4795}
4796
7ac0dd9d 4797static bool efx_ef10_filter_match_supported(struct efx_ef10_filter_table *table,
9b410801 4798 bool encap,
7ac0dd9d
AR		 4799 enum efx_filter_match_flags match_flags)
4800{
4801 unsigned int match_pri;
4802 int mf;
4803
4804 for (match_pri = 0;
4805 match_pri < table->rx_match_count;
4806 match_pri++) {
9b410801 4807 mf = efx_ef10_filter_match_flags_from_mcdi(encap,
7ac0dd9d
AR		 4808 table->rx_match_mcdi_flags[match_pri]);
4809 if (mf == match_flags)
4810 return true;
4811 }
4812
4813 return false;
4814}
4815
9b410801
EC		 4816static int
4817efx_ef10_filter_table_probe_matches(struct efx_nic *efx,
4818 struct efx_ef10_filter_table *table,
4819 bool encap)
8127d661
BH		 4820{
4821 MCDI_DECLARE_BUF(inbuf, MC_CMD_GET_PARSER_DISP_INFO_IN_LEN);
4822 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX);
4823 unsigned int pd_match_pri, pd_match_count;
8127d661
BH		 4824 size_t outlen;
4825 int rc;
4826
8127d661
BH		 4827 /* Find out which RX filter types are supported, and their priorities */
4828 MCDI_SET_DWORD(inbuf, GET_PARSER_DISP_INFO_IN_OP,
9b410801
EC		 4829 encap ?
4830 MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_ENCAP_RX_MATCHES :
8127d661
BH		 4831 MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES);
4832 rc = efx_mcdi_rpc(efx, MC_CMD_GET_PARSER_DISP_INFO,
4833 inbuf, sizeof(inbuf), outbuf, sizeof(outbuf),
4834 &outlen);
4835 if (rc)
9b410801
EC		 4836 return rc;
4837
8127d661
BH		 4838 pd_match_count = MCDI_VAR_ARRAY_LEN(
4839 outlen, GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES);
8127d661
BH		 4840
4841 for (pd_match_pri = 0; pd_match_pri < pd_match_count; pd_match_pri++) {
4842 u32 mcdi_flags =
4843 MCDI_ARRAY_DWORD(
4844 outbuf,
4845 GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES,
4846 pd_match_pri);
9b410801 4847 rc = efx_ef10_filter_match_flags_from_mcdi(encap, mcdi_flags);
8127d661
BH		 4848 if (rc < 0) {
4849 netif_dbg(efx, probe, efx->net_dev,
4850 "%s: fw flags %#x pri %u not supported in driver\n",
4851 __func__, mcdi_flags, pd_match_pri);
4852 } else {
4853 netif_dbg(efx, probe, efx->net_dev,
4854 "%s: fw flags %#x pri %u supported as driver flags %#x pri %u\n",
4855 __func__, mcdi_flags, pd_match_pri,
4856 rc, table->rx_match_count);
7ac0dd9d
AR		 4857 table->rx_match_mcdi_flags[table->rx_match_count] = mcdi_flags;
4858 table->rx_match_count++;
8127d661
BH		 4859 }
4860 }
4861
9b410801
EC		 4862 return 0;
4863}
4864
4865static int efx_ef10_filter_table_probe(struct efx_nic *efx)
4866{
4867 struct efx_ef10_nic_data *nic_data = efx->nic_data;
4868 struct net_device *net_dev = efx->net_dev;
4869 struct efx_ef10_filter_table *table;
4870 struct efx_ef10_vlan *vlan;
4871 int rc;
4872
4873 if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
4874 return -EINVAL;
4875
4876 if (efx->filter_state) /* already probed */
4877 return 0;
4878
4879 table = kzalloc(sizeof(*table), GFP_KERNEL);
4880 if (!table)
4881 return -ENOMEM;
4882
4883 table->rx_match_count = 0;
4884 rc = efx_ef10_filter_table_probe_matches(efx, table, false);
4885 if (rc)
4886 goto fail;
4887 if (nic_data->datapath_caps &
4888 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN))
4889 rc = efx_ef10_filter_table_probe_matches(efx, table, true);
4890 if (rc)
4891 goto fail;
e4478ad1 4892 if ((efx_supported_features(efx) & NETIF_F_HW_VLAN_CTAG_FILTER) &&
9b410801 4893 !(efx_ef10_filter_match_supported(table, false,
e4478ad1 4894 (EFX_FILTER_MATCH_OUTER_VID | EFX_FILTER_MATCH_LOC_MAC)) &&
9b410801 4895 efx_ef10_filter_match_supported(table, false,
e4478ad1
MH		 4896 (EFX_FILTER_MATCH_OUTER_VID | EFX_FILTER_MATCH_LOC_MAC_IG)))) {
4897 netif_info(efx, probe, net_dev,
4898 "VLAN filters are not supported in this firmware variant\n");
4899 net_dev->features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
4900 efx->fixed_features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
4901 net_dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
4902 }
4903
8127d661
BH		 4904 table->entry = vzalloc(HUNT_FILTER_TBL_ROWS * sizeof(*table->entry));
4905 if (!table->entry) {
4906 rc = -ENOMEM;
4907 goto fail;
4908 }
4909
b071c3a2 4910 table->mc_promisc_last = false;
4a53ea8a
AR		 4911 table->vlan_filter =
4912 !!(efx->net_dev->features & NETIF_F_HW_VLAN_CTAG_FILTER);
34813fe2 4913 INIT_LIST_HEAD(&table->vlan_list);
12fb0da4 4914
8127d661
BH		 4915 efx->filter_state = table;
4916 init_waitqueue_head(&table->waitq);
34813fe2
AR		 4917
4918 list_for_each_entry(vlan, &nic_data->vlan_list, list) {
4919 rc = efx_ef10_filter_add_vlan(efx, vlan->vid);
4920 if (rc)
4921 goto fail_add_vlan;
4922 }
4923
8127d661
BH		 4924 return 0;
4925
34813fe2
AR		 4926fail_add_vlan:
4927 efx_ef10_filter_cleanup_vlans(efx);
4928 efx->filter_state = NULL;
8127d661
BH		 4929fail:
4930 kfree(table);
4931 return rc;
4932}
4933
0d322413
EC		 4934/* Caller must hold efx->filter_sem for read if race against
4935 * efx_ef10_filter_table_remove() is possible
4936 */
8127d661
BH		 4937static void efx_ef10_filter_table_restore(struct efx_nic *efx)
4938{
4939 struct efx_ef10_filter_table *table = efx->filter_state;
4940 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2d3d4ec0
JC		 4941 unsigned int invalid_filters = 0, failed = 0;
4942 struct efx_ef10_filter_vlan *vlan;
8127d661
BH		 4943 struct efx_filter_spec *spec;
4944 unsigned int filter_idx;
2d3d4ec0
JC		 4945 u32 mcdi_flags;
4946 int match_pri;
9b410801 4947 int rc, i;
8127d661 4948
0d322413
EC		 4949 WARN_ON(!rwsem_is_locked(&efx->filter_sem));
4950
8127d661
BH		 4951 if (!nic_data->must_restore_filters)
4952 return;
4953
0d322413
EC		 4954 if (!table)
4955 return;
4956
8127d661
BH		 4957 spin_lock_bh(&efx->filter_lock);
4958
4959 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
4960 spec = efx_ef10_filter_entry_spec(table, filter_idx);
4961 if (!spec)
4962 continue;
4963
2d3d4ec0
JC		 4964 mcdi_flags = efx_ef10_filter_mcdi_flags_from_spec(spec);
4965 match_pri = 0;
4966 while (match_pri < table->rx_match_count &&
4967 table->rx_match_mcdi_flags[match_pri] != mcdi_flags)
4968 ++match_pri;
4969 if (match_pri >= table->rx_match_count) {
4970 invalid_filters++;
4971 goto not_restored;
4972 }
4973 if (spec->rss_context != EFX_FILTER_RSS_CONTEXT_DEFAULT &&
4974 spec->rss_context != nic_data->rx_rss_context)
4975 netif_warn(efx, drv, efx->net_dev,
4976 "Warning: unable to restore a filter with specific RSS context.\n");
4977
8127d661
BH		 4978 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
4979 spin_unlock_bh(&efx->filter_lock);
4980
4981 rc = efx_ef10_filter_push(efx, spec,
4982 &table->entry[filter_idx].handle,
4983 false);
4984 if (rc)
2d3d4ec0 4985 failed++;
8127d661 4986 spin_lock_bh(&efx->filter_lock);
2d3d4ec0 4987
8127d661 4988 if (rc) {
2d3d4ec0 4989not_restored:
9b410801
EC		 4990 list_for_each_entry(vlan, &table->vlan_list, list)
4991 for (i = 0; i < EFX_EF10_NUM_DEFAULT_FILTERS; ++i)
4992 if (vlan->default_filters[i] == filter_idx)
4993 vlan->default_filters[i] =
4994 EFX_EF10_FILTER_ID_INVALID;
4995
8127d661
BH		 4996 kfree(spec);
4997 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
4998 } else {
4999 table->entry[filter_idx].spec &=
5000 ~EFX_EF10_FILTER_FLAG_BUSY;
5001 }
5002 }
5003
5004 spin_unlock_bh(&efx->filter_lock);
5005
2d3d4ec0
JC		 5006 /* This can happen validly if the MC's capabilities have changed, so
5007 * is not an error.
5008 */
5009 if (invalid_filters)
5010 netif_dbg(efx, drv, efx->net_dev,
5011 "Did not restore %u filters that are now unsupported.\n",
5012 invalid_filters);
5013
8127d661
BH		 5014 if (failed)
5015 netif_err(efx, hw, efx->net_dev,
2d3d4ec0 5016 "unable to restore %u filters\n", failed);
8127d661
BH		 5017 else
5018 nic_data->must_restore_filters = false;
5019}
5020
5021static void efx_ef10_filter_table_remove(struct efx_nic *efx)
5022{
5023 struct efx_ef10_filter_table *table = efx->filter_state;
bb53f4d4 5024 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_EXT_IN_LEN);
8127d661
BH		 5025 struct efx_filter_spec *spec;
5026 unsigned int filter_idx;
5027 int rc;
5028
34813fe2 5029 efx_ef10_filter_cleanup_vlans(efx);
0d322413 5030 efx->filter_state = NULL;
dd98708c
EC		 5031 /* If we were called without locking, then it's not safe to free
5032 * the table as others might be using it. So we just WARN, leak
5033 * the memory, and potentially get an inconsistent filter table
5034 * state.
5035 * This should never actually happen.
5036 */
5037 if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
5038 return;
5039
0d322413
EC		 5040 if (!table)
5041 return;
5042
8127d661
BH		 5043 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
5044 spec = efx_ef10_filter_entry_spec(table, filter_idx);
5045 if (!spec)
5046 continue;
5047
5048 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
5049 efx_ef10_filter_is_exclusive(spec) ?
5050 MC_CMD_FILTER_OP_IN_OP_REMOVE :
5051 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
5052 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
5053 table->entry[filter_idx].handle);
e65a5109
BK		 5054 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FILTER_OP, inbuf,
5055 sizeof(inbuf), NULL, 0, NULL);
48ce5634 5056 if (rc)
e65a5109
BK		 5057 netif_info(efx, drv, efx->net_dev,
5058 "%s: filter %04x remove failed\n",
5059 __func__, filter_idx);
8127d661
BH		 5060 kfree(spec);
5061 }
5062
5063 vfree(table->entry);
5064 kfree(table);
5065}
5066
6a37958b
AR		 5067static void efx_ef10_filter_mark_one_old(struct efx_nic *efx, uint16_t *id)
5068{
5069 struct efx_ef10_filter_table *table = efx->filter_state;
5070 unsigned int filter_idx;
5071
5072 if (*id != EFX_EF10_FILTER_ID_INVALID) {
0ccb998b 5073 filter_idx = efx_ef10_filter_get_unsafe_id(*id);
6a37958b
AR		 5074 if (!table->entry[filter_idx].spec)
5075 netif_dbg(efx, drv, efx->net_dev,
5076 "marked null spec old %04x:%04x\n", *id,
5077 filter_idx);
5078 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_AUTO_OLD;
5079 *id = EFX_EF10_FILTER_ID_INVALID;
e65a5109 5080 }
6a37958b
AR		 5081}
5082
b3a3c03c
AR		 5083/* Mark old per-VLAN filters that may need to be removed */
5084static void _efx_ef10_filter_vlan_mark_old(struct efx_nic *efx,
5085 struct efx_ef10_filter_vlan *vlan)
8127d661
BH		 5086{
5087 struct efx_ef10_filter_table *table = efx->filter_state;
6a37958b 5088 unsigned int i;
8127d661 5089
12fb0da4 5090 for (i = 0; i < table->dev_uc_count; i++)
dc3273e0 5091 efx_ef10_filter_mark_one_old(efx, &vlan->uc[i]);
12fb0da4 5092 for (i = 0; i < table->dev_mc_count; i++)
dc3273e0 5093 efx_ef10_filter_mark_one_old(efx, &vlan->mc[i]);
9b410801
EC		 5094 for (i = 0; i < EFX_EF10_NUM_DEFAULT_FILTERS; i++)
5095 efx_ef10_filter_mark_one_old(efx, &vlan->default_filters[i]);
b3a3c03c
AR		 5096}
5097
34813fe2
AR		 5098/* Mark old filters that may need to be removed.
5099 * Caller must hold efx->filter_sem for read if race against
5100 * efx_ef10_filter_table_remove() is possible
5101 */
b3a3c03c
AR		 5102static void efx_ef10_filter_mark_old(struct efx_nic *efx)
5103{
5104 struct efx_ef10_filter_table *table = efx->filter_state;
34813fe2 5105 struct efx_ef10_filter_vlan *vlan;
b3a3c03c
AR		 5106
5107 spin_lock_bh(&efx->filter_lock);
34813fe2
AR		 5108 list_for_each_entry(vlan, &table->vlan_list, list)
5109 _efx_ef10_filter_vlan_mark_old(efx, vlan);
8127d661 5110 spin_unlock_bh(&efx->filter_lock);
822b96f8
DP		 5111}
5112
afa4ce12 5113static void efx_ef10_filter_uc_addr_list(struct efx_nic *efx)
822b96f8
DP		 5114{
5115 struct efx_ef10_filter_table *table = efx->filter_state;
5116 struct net_device *net_dev = efx->net_dev;
5117 struct netdev_hw_addr *uc;
5118 unsigned int i;
8127d661 5119
afa4ce12 5120 table->uc_promisc = !!(net_dev->flags & IFF_PROMISC);
822b96f8
DP		 5121 ether_addr_copy(table->dev_uc_list[0].addr, net_dev->dev_addr);
5122 i = 1;
5123 netdev_for_each_uc_addr(uc, net_dev) {
12fb0da4 5124 if (i >= EFX_EF10_FILTER_DEV_UC_MAX) {
afa4ce12 5125 table->uc_promisc = true;
12fb0da4
EC		 5126 break;
5127 }
822b96f8
DP		 5128 ether_addr_copy(table->dev_uc_list[i].addr, uc->addr);
5129 i++;
5130 }
c70d6815
BK		 5131
5132 table->dev_uc_count = i;
822b96f8
DP		 5133}
5134
afa4ce12 5135static void efx_ef10_filter_mc_addr_list(struct efx_nic *efx)
822b96f8
DP		 5136{
5137 struct efx_ef10_filter_table *table = efx->filter_state;
5138 struct net_device *net_dev = efx->net_dev;
5139 struct netdev_hw_addr *mc;
c70d6815 5140 unsigned int i;
822b96f8 5141
148cbab6 5142 table->mc_overflow = false;
afa4ce12 5143 table->mc_promisc = !!(net_dev->flags & (IFF_PROMISC | IFF_ALLMULTI));
ab8b1f7c 5144
12fb0da4 5145 i = 0;
ab8b1f7c 5146 netdev_for_each_mc_addr(mc, net_dev) {
12fb0da4 5147 if (i >= EFX_EF10_FILTER_DEV_MC_MAX) {
afa4ce12 5148 table->mc_promisc = true;
148cbab6 5149 table->mc_overflow = true;
12fb0da4
EC		 5150 break;
5151 }
ab8b1f7c
DP		 5152 ether_addr_copy(table->dev_mc_list[i].addr, mc->addr);
5153 i++;
8127d661 5154 }
12fb0da4
EC		 5155
5156 table->dev_mc_count = i;
822b96f8 5157}
8127d661 5158
12fb0da4 5159static int efx_ef10_filter_insert_addr_list(struct efx_nic *efx,
b3a3c03c
AR		 5160 struct efx_ef10_filter_vlan *vlan,
5161 bool multicast, bool rollback)
822b96f8
DP		 5162{
5163 struct efx_ef10_filter_table *table = efx->filter_state;
5164 struct efx_ef10_dev_addr *addr_list;
f1c2ef40 5165 enum efx_filter_flags filter_flags;
822b96f8 5166 struct efx_filter_spec spec;
12fb0da4
EC		 5167 u8 baddr[ETH_ALEN];
5168 unsigned int i, j;
5169 int addr_count;
dc3273e0 5170 u16 *ids;
822b96f8
DP		 5171 int rc;
5172
5173 if (multicast) {
5174 addr_list = table->dev_mc_list;
12fb0da4 5175 addr_count = table->dev_mc_count;
dc3273e0 5176 ids = vlan->mc;
822b96f8
DP		 5177 } else {
5178 addr_list = table->dev_uc_list;
12fb0da4 5179 addr_count = table->dev_uc_count;
dc3273e0 5180 ids = vlan->uc;
8127d661
BH		 5181 }
5182
f1c2ef40
BK		 5183 filter_flags = efx_rss_enabled(efx) ? EFX_FILTER_FLAG_RX_RSS : 0;
5184
822b96f8 5185 /* Insert/renew filters */
12fb0da4 5186 for (i = 0; i < addr_count; i++) {
d58299a4 5187 EFX_WARN_ON_PARANOID(ids[i] != EFX_EF10_FILTER_ID_INVALID);
f1c2ef40 5188 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, 0);
b3a3c03c 5189 efx_filter_set_eth_local(&spec, vlan->vid, addr_list[i].addr);
b6f568e2
JC		 5190 rc = efx_ef10_filter_insert(efx, &spec, true);
5191 if (rc < 0) {
12fb0da4
EC		 5192 if (rollback) {
5193 netif_info(efx, drv, efx->net_dev,
5194 "efx_ef10_filter_insert failed rc=%d\n",
5195 rc);
5196 /* Fall back to promiscuous */
5197 for (j = 0; j < i; j++) {
12fb0da4
EC		 5198 efx_ef10_filter_remove_unsafe(
5199 efx, EFX_FILTER_PRI_AUTO,
dc3273e0
AR		 5200 ids[j]);
5201 ids[j] = EFX_EF10_FILTER_ID_INVALID;
12fb0da4
EC		 5202 }
5203 return rc;
5204 } else {
d58299a4 5205 /* keep invalid ID, and carry on */
822b96f8 5206 }
d58299a4
EC		 5207 } else {
5208 ids[i] = efx_ef10_filter_get_unsafe_id(rc);
8127d661
BH		 5209 }
5210 }
822b96f8 5211
12fb0da4
EC		 5212 if (multicast && rollback) {
5213 /* Also need an Ethernet broadcast filter */
9b410801
EC		 5214 EFX_WARN_ON_PARANOID(vlan->default_filters[EFX_EF10_BCAST] !=
5215 EFX_EF10_FILTER_ID_INVALID);
f1c2ef40 5216 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, 0);
12fb0da4 5217 eth_broadcast_addr(baddr);
b3a3c03c 5218 efx_filter_set_eth_local(&spec, vlan->vid, baddr);
8127d661 5219 rc = efx_ef10_filter_insert(efx, &spec, true);
12fb0da4 5220 if (rc < 0) {
822b96f8 5221 netif_warn(efx, drv, efx->net_dev,
12fb0da4
EC		 5222 "Broadcast filter insert failed rc=%d\n", rc);
5223 /* Fall back to promiscuous */
5224 for (j = 0; j < i; j++) {
12fb0da4
EC		 5225 efx_ef10_filter_remove_unsafe(
5226 efx, EFX_FILTER_PRI_AUTO,
dc3273e0
AR		 5227 ids[j]);
5228 ids[j] = EFX_EF10_FILTER_ID_INVALID;
12fb0da4
EC		 5229 }
5230 return rc;
5231 } else {
9b410801 5232 vlan->default_filters[EFX_EF10_BCAST] =
0ccb998b 5233 efx_ef10_filter_get_unsafe_id(rc);
12fb0da4 5234 }
8127d661 5235 }
12fb0da4
EC		 5236
5237 return 0;
5238}
5239
b3a3c03c
AR		 5240static int efx_ef10_filter_insert_def(struct efx_nic *efx,
5241 struct efx_ef10_filter_vlan *vlan,
9b410801 5242 enum efx_encap_type encap_type,
b3a3c03c 5243 bool multicast, bool rollback)
12fb0da4 5244{
12fb0da4 5245 struct efx_ef10_nic_data *nic_data = efx->nic_data;
f1c2ef40 5246 enum efx_filter_flags filter_flags;
12fb0da4
EC		 5247 struct efx_filter_spec spec;
5248 u8 baddr[ETH_ALEN];
5249 int rc;
9b410801 5250 u16 *id;
12fb0da4 5251
f1c2ef40
BK		 5252 filter_flags = efx_rss_enabled(efx) ? EFX_FILTER_FLAG_RX_RSS : 0;
5253
5254 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, 0);
12fb0da4
EC		 5255
5256 if (multicast)
5257 efx_filter_set_mc_def(&spec);
5258 else
5259 efx_filter_set_uc_def(&spec);
5260
9b410801
EC		 5261 if (encap_type) {
5262 if (nic_data->datapath_caps &
5263 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN))
5264 efx_filter_set_encap_type(&spec, encap_type);
5265 else
5266 /* don't insert encap filters on non-supporting
5267 * platforms. ID will be left as INVALID.
5268 */
5269 return 0;
5270 }
5271
b3a3c03c
AR		 5272 if (vlan->vid != EFX_FILTER_VID_UNSPEC)
5273 efx_filter_set_eth_local(&spec, vlan->vid, NULL);
5274
12fb0da4
EC		 5275 rc = efx_ef10_filter_insert(efx, &spec, true);
5276 if (rc < 0) {
9b410801
EC		 5277 const char *um = multicast ? "Multicast" : "Unicast";
5278 const char *encap_name = "";
5279 const char *encap_ipv = "";
5280
5281 if ((encap_type & EFX_ENCAP_TYPES_MASK) ==
5282 EFX_ENCAP_TYPE_VXLAN)
5283 encap_name = "VXLAN ";
5284 else if ((encap_type & EFX_ENCAP_TYPES_MASK) ==
5285 EFX_ENCAP_TYPE_NVGRE)
5286 encap_name = "NVGRE ";
5287 else if ((encap_type & EFX_ENCAP_TYPES_MASK) ==
5288 EFX_ENCAP_TYPE_GENEVE)
5289 encap_name = "GENEVE ";
5290 if (encap_type & EFX_ENCAP_FLAG_IPV6)
5291 encap_ipv = "IPv6 ";
5292 else if (encap_type)
5293 encap_ipv = "IPv4 ";
5294
5295 /* unprivileged functions can't insert mismatch filters
5296 * for encapsulated or unicast traffic, so downgrade
5297 * those warnings to debug.
5298 */
34e7aefb 5299 netif_cond_dbg(efx, drv, efx->net_dev,
9b410801
EC		 5300 rc == -EPERM && (encap_type || !multicast), warn,
5301 "%s%s%s mismatch filter insert failed rc=%d\n",
5302 encap_name, encap_ipv, um, rc);
12fb0da4 5303 } else if (multicast) {
9b410801
EC		 5304 /* mapping from encap types to default filter IDs (multicast) */
5305 static enum efx_ef10_default_filters map[] = {
5306 [EFX_ENCAP_TYPE_NONE] = EFX_EF10_MCDEF,
5307 [EFX_ENCAP_TYPE_VXLAN] = EFX_EF10_VXLAN4_MCDEF,
5308 [EFX_ENCAP_TYPE_NVGRE] = EFX_EF10_NVGRE4_MCDEF,
5309 [EFX_ENCAP_TYPE_GENEVE] = EFX_EF10_GENEVE4_MCDEF,
5310 [EFX_ENCAP_TYPE_VXLAN | EFX_ENCAP_FLAG_IPV6] =
5311 EFX_EF10_VXLAN6_MCDEF,
5312 [EFX_ENCAP_TYPE_NVGRE | EFX_ENCAP_FLAG_IPV6] =
5313 EFX_EF10_NVGRE6_MCDEF,
5314 [EFX_ENCAP_TYPE_GENEVE | EFX_ENCAP_FLAG_IPV6] =
5315 EFX_EF10_GENEVE6_MCDEF,
5316 };
5317
5318 /* quick bounds check (BCAST result impossible) */
5319 BUILD_BUG_ON(EFX_EF10_BCAST != 0);
e9904990 5320 if (encap_type >= ARRAY_SIZE(map) || map[encap_type] == 0) {
9b410801
EC		 5321 WARN_ON(1);
5322 return -EINVAL;
5323 }
5324 /* then follow map */
5325 id = &vlan->default_filters[map[encap_type]];
5326
5327 EFX_WARN_ON_PARANOID(*id != EFX_EF10_FILTER_ID_INVALID);
0ccb998b 5328 *id = efx_ef10_filter_get_unsafe_id(rc);
9b410801 5329 if (!nic_data->workaround_26807 && !encap_type) {
12fb0da4
EC		 5330 /* Also need an Ethernet broadcast filter */
5331 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
f1c2ef40 5332 filter_flags, 0);
12fb0da4 5333 eth_broadcast_addr(baddr);
b3a3c03c 5334 efx_filter_set_eth_local(&spec, vlan->vid, baddr);
12fb0da4
EC		 5335 rc = efx_ef10_filter_insert(efx, &spec, true);
5336 if (rc < 0) {
5337 netif_warn(efx, drv, efx->net_dev,
5338 "Broadcast filter insert failed rc=%d\n",
5339 rc);
5340 if (rollback) {
5341 /* Roll back the mc_def filter */
5342 efx_ef10_filter_remove_unsafe(
5343 efx, EFX_FILTER_PRI_AUTO,
9b410801
EC		 5344 *id);
5345 *id = EFX_EF10_FILTER_ID_INVALID;
12fb0da4
EC		 5346 return rc;
5347 }
5348 } else {
9b410801
EC		 5349 EFX_WARN_ON_PARANOID(
5350 vlan->default_filters[EFX_EF10_BCAST] !=
5351 EFX_EF10_FILTER_ID_INVALID);
5352 vlan->default_filters[EFX_EF10_BCAST] =
0ccb998b 5353 efx_ef10_filter_get_unsafe_id(rc);
12fb0da4
EC		 5354 }
5355 }
5356 rc = 0;
5357 } else {
9b410801
EC		 5358 /* mapping from encap types to default filter IDs (unicast) */
5359 static enum efx_ef10_default_filters map[] = {
5360 [EFX_ENCAP_TYPE_NONE] = EFX_EF10_UCDEF,
5361 [EFX_ENCAP_TYPE_VXLAN] = EFX_EF10_VXLAN4_UCDEF,
5362 [EFX_ENCAP_TYPE_NVGRE] = EFX_EF10_NVGRE4_UCDEF,
5363 [EFX_ENCAP_TYPE_GENEVE] = EFX_EF10_GENEVE4_UCDEF,
5364 [EFX_ENCAP_TYPE_VXLAN | EFX_ENCAP_FLAG_IPV6] =
5365 EFX_EF10_VXLAN6_UCDEF,
5366 [EFX_ENCAP_TYPE_NVGRE | EFX_ENCAP_FLAG_IPV6] =
5367 EFX_EF10_NVGRE6_UCDEF,
5368 [EFX_ENCAP_TYPE_GENEVE | EFX_ENCAP_FLAG_IPV6] =
5369 EFX_EF10_GENEVE6_UCDEF,
5370 };
5371
5372 /* quick bounds check (BCAST result impossible) */
5373 BUILD_BUG_ON(EFX_EF10_BCAST != 0);
ee467fba 5374 if (encap_type >= ARRAY_SIZE(map) || map[encap_type] == 0) {
9b410801
EC		 5375 WARN_ON(1);
5376 return -EINVAL;
5377 }
5378 /* then follow map */
5379 id = &vlan->default_filters[map[encap_type]];
5380 EFX_WARN_ON_PARANOID(*id != EFX_EF10_FILTER_ID_INVALID);
5381 *id = rc;
12fb0da4
EC		 5382 rc = 0;
5383 }
5384 return rc;
822b96f8
DP		 5385}
5386
5387/* Remove filters that weren't renewed. Since nothing else changes the AUTO_OLD
5388 * flag or removes these filters, we don't need to hold the filter_lock while
5389 * scanning for these filters.
5390 */
5391static void efx_ef10_filter_remove_old(struct efx_nic *efx)
5392{
5393 struct efx_ef10_filter_table *table = efx->filter_state;
e65a5109
BK		 5394 int remove_failed = 0;
5395 int remove_noent = 0;
5396 int rc;
822b96f8 5397 int i;
8127d661 5398
8127d661 5399 for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) {
6aa7de05 5400 if (READ_ONCE(table->entry[i].spec) &
b59e6ef8 5401 EFX_EF10_FILTER_FLAG_AUTO_OLD) {
e65a5109
BK		 5402 rc = efx_ef10_filter_remove_internal(efx,
5403 1U << EFX_FILTER_PRI_AUTO, i, true);
5404 if (rc == -ENOENT)
5405 remove_noent++;
5406 else if (rc)
5407 remove_failed++;
8127d661
BH		 5408 }
5409 }
e65a5109
BK		 5410
5411 if (remove_failed)
5412 netif_info(efx, drv, efx->net_dev,
5413 "%s: failed to remove %d filters\n",
5414 __func__, remove_failed);
5415 if (remove_noent)
5416 netif_info(efx, drv, efx->net_dev,
5417 "%s: failed to remove %d non-existent filters\n",
5418 __func__, remove_noent);
8127d661
BH		 5419}
5420
7a186f47
DP		 5421static int efx_ef10_vport_set_mac_address(struct efx_nic *efx)
5422{
5423 struct efx_ef10_nic_data *nic_data = efx->nic_data;
5424 u8 mac_old[ETH_ALEN];
5425 int rc, rc2;
5426
5427 /* Only reconfigure a PF-created vport */
5428 if (is_zero_ether_addr(nic_data->vport_mac))
5429 return 0;
5430
5431 efx_device_detach_sync(efx);
5432 efx_net_stop(efx->net_dev);
5433 down_write(&efx->filter_sem);
5434 efx_ef10_filter_table_remove(efx);
5435 up_write(&efx->filter_sem);
5436
5437 rc = efx_ef10_vadaptor_free(efx, nic_data->vport_id);
5438 if (rc)
5439 goto restore_filters;
5440
5441 ether_addr_copy(mac_old, nic_data->vport_mac);
5442 rc = efx_ef10_vport_del_mac(efx, nic_data->vport_id,
5443 nic_data->vport_mac);
5444 if (rc)
5445 goto restore_vadaptor;
5446
5447 rc = efx_ef10_vport_add_mac(efx, nic_data->vport_id,
5448 efx->net_dev->dev_addr);
5449 if (!rc) {
5450 ether_addr_copy(nic_data->vport_mac, efx->net_dev->dev_addr);
5451 } else {
5452 rc2 = efx_ef10_vport_add_mac(efx, nic_data->vport_id, mac_old);
5453 if (rc2) {
5454 /* Failed to add original MAC, so clear vport_mac */
5455 eth_zero_addr(nic_data->vport_mac);
5456 goto reset_nic;
5457 }
5458 }
5459
5460restore_vadaptor:
5461 rc2 = efx_ef10_vadaptor_alloc(efx, nic_data->vport_id);
5462 if (rc2)
5463 goto reset_nic;
5464restore_filters:
5465 down_write(&efx->filter_sem);
5466 rc2 = efx_ef10_filter_table_probe(efx);
5467 up_write(&efx->filter_sem);
5468 if (rc2)
5469 goto reset_nic;
5470
5471 rc2 = efx_net_open(efx->net_dev);
5472 if (rc2)
5473 goto reset_nic;
5474
9c568fd8 5475 efx_device_attach_if_not_resetting(efx);
7a186f47
DP		 5476
5477 return rc;
5478
5479reset_nic:
5480 netif_err(efx, drv, efx->net_dev,
5481 "Failed to restore when changing MAC address - scheduling reset\n");
5482 efx_schedule_reset(efx, RESET_TYPE_DATAPATH);
5483
5484 return rc ? rc : rc2;
5485}
5486
822b96f8
DP		 5487/* Caller must hold efx->filter_sem for read if race against
5488 * efx_ef10_filter_table_remove() is possible
5489 */
34813fe2
AR		 5490static void efx_ef10_filter_vlan_sync_rx_mode(struct efx_nic *efx,
5491 struct efx_ef10_filter_vlan *vlan)
822b96f8
DP		 5492{
5493 struct efx_ef10_filter_table *table = efx->filter_state;
ab8b1f7c 5494 struct efx_ef10_nic_data *nic_data = efx->nic_data;
b3a3c03c 5495
4a53ea8a
AR		 5496 /* Do not install unspecified VID if VLAN filtering is enabled.
5497 * Do not install all specified VIDs if VLAN filtering is disabled.
5498 */
5499 if ((vlan->vid == EFX_FILTER_VID_UNSPEC) == table->vlan_filter)
5500 return;
5501
12fb0da4 5502 /* Insert/renew unicast filters */
afa4ce12 5503 if (table->uc_promisc) {
9b410801
EC		 5504 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_NONE,
5505 false, false);
b3a3c03c 5506 efx_ef10_filter_insert_addr_list(efx, vlan, false, false);
12fb0da4
EC		 5507 } else {
5508 /* If any of the filters failed to insert, fall back to
5509 * promiscuous mode - add in the uc_def filter. But keep
5510 * our individual unicast filters.
5511 */
b3a3c03c 5512 if (efx_ef10_filter_insert_addr_list(efx, vlan, false, false))
9b410801
EC		 5513 efx_ef10_filter_insert_def(efx, vlan,
5514 EFX_ENCAP_TYPE_NONE,
5515 false, false);
12fb0da4 5516 }
9b410801
EC		 5517 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_VXLAN,
5518 false, false);
5519 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_VXLAN |
5520 EFX_ENCAP_FLAG_IPV6,
5521 false, false);
5522 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_NVGRE,
5523 false, false);
5524 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_NVGRE |
5525 EFX_ENCAP_FLAG_IPV6,
5526 false, false);
5527 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_GENEVE,
5528 false, false);
5529 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_GENEVE |
5530 EFX_ENCAP_FLAG_IPV6,
5531 false, false);
ab8b1f7c 5532
12fb0da4 5533 /* Insert/renew multicast filters */
ab8b1f7c
DP		 5534 /* If changing promiscuous state with cascaded multicast filters, remove
5535 * old filters first, so that packets are dropped rather than duplicated
5536 */
afa4ce12
AR		 5537 if (nic_data->workaround_26807 &&
5538 table->mc_promisc_last != table->mc_promisc)
ab8b1f7c 5539 efx_ef10_filter_remove_old(efx);
afa4ce12 5540 if (table->mc_promisc) {
12fb0da4
EC		 5541 if (nic_data->workaround_26807) {
5542 /* If we failed to insert promiscuous filters, rollback
5543 * and fall back to individual multicast filters
5544 */
9b410801
EC		 5545 if (efx_ef10_filter_insert_def(efx, vlan,
5546 EFX_ENCAP_TYPE_NONE,
5547 true, true)) {
12fb0da4
EC		 5548 /* Changing promisc state, so remove old filters */
5549 efx_ef10_filter_remove_old(efx);
b3a3c03c
AR		 5550 efx_ef10_filter_insert_addr_list(efx, vlan,
5551 true, false);
12fb0da4
EC		 5552 }
5553 } else {
5554 /* If we failed to insert promiscuous filters, don't
148cbab6
EC		 5555 * rollback. Regardless, also insert the mc_list,
5556 * unless it's incomplete due to overflow
12fb0da4 5557 */
9b410801
EC		 5558 efx_ef10_filter_insert_def(efx, vlan,
5559 EFX_ENCAP_TYPE_NONE,
5560 true, false);
148cbab6
EC		 5561 if (!table->mc_overflow)
5562 efx_ef10_filter_insert_addr_list(efx, vlan,
5563 true, false);
12fb0da4
EC		 5564 }
5565 } else {
5566 /* If any filters failed to insert, rollback and fall back to
5567 * promiscuous mode - mc_def filter and maybe broadcast. If
5568 * that fails, roll back again and insert as many of our
5569 * individual multicast filters as we can.
5570 */
b3a3c03c 5571 if (efx_ef10_filter_insert_addr_list(efx, vlan, true, true)) {
12fb0da4
EC		 5572 /* Changing promisc state, so remove old filters */
5573 if (nic_data->workaround_26807)
5574 efx_ef10_filter_remove_old(efx);
9b410801
EC		 5575 if (efx_ef10_filter_insert_def(efx, vlan,
5576 EFX_ENCAP_TYPE_NONE,
5577 true, true))
b3a3c03c
AR		 5578 efx_ef10_filter_insert_addr_list(efx, vlan,
5579 true, false);
12fb0da4
EC		 5580 }
5581 }
9b410801
EC		 5582 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_VXLAN,
5583 true, false);
5584 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_VXLAN |
5585 EFX_ENCAP_FLAG_IPV6,
5586 true, false);
5587 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_NVGRE,
5588 true, false);
5589 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_NVGRE |
5590 EFX_ENCAP_FLAG_IPV6,
5591 true, false);
5592 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_GENEVE,
5593 true, false);
5594 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_GENEVE |
5595 EFX_ENCAP_FLAG_IPV6,
5596 true, false);
34813fe2
AR		 5597}
5598
5599/* Caller must hold efx->filter_sem for read if race against
5600 * efx_ef10_filter_table_remove() is possible
5601 */
5602static void efx_ef10_filter_sync_rx_mode(struct efx_nic *efx)
5603{
5604 struct efx_ef10_filter_table *table = efx->filter_state;
5605 struct net_device *net_dev = efx->net_dev;
5606 struct efx_ef10_filter_vlan *vlan;
4a53ea8a 5607 bool vlan_filter;
34813fe2
AR		 5608
5609 if (!efx_dev_registered(efx))
5610 return;
5611
5612 if (!table)
5613 return;
5614
5615 efx_ef10_filter_mark_old(efx);
5616
5617 /* Copy/convert the address lists; add the primary station
5618 * address and broadcast address
5619 */
5620 netif_addr_lock_bh(net_dev);
5621 efx_ef10_filter_uc_addr_list(efx);
5622 efx_ef10_filter_mc_addr_list(efx);
5623 netif_addr_unlock_bh(net_dev);
5624
4a53ea8a
AR		 5625 /* If VLAN filtering changes, all old filters are finally removed.
5626 * Do it in advance to avoid conflicts for unicast untagged and
5627 * VLAN 0 tagged filters.
5628 */
5629 vlan_filter = !!(net_dev->features & NETIF_F_HW_VLAN_CTAG_FILTER);
5630 if (table->vlan_filter != vlan_filter) {
5631 table->vlan_filter = vlan_filter;
5632 efx_ef10_filter_remove_old(efx);
5633 }
5634
34813fe2
AR		 5635 list_for_each_entry(vlan, &table->vlan_list, list)
5636 efx_ef10_filter_vlan_sync_rx_mode(efx, vlan);
822b96f8
DP		 5637
5638 efx_ef10_filter_remove_old(efx);
afa4ce12 5639 table->mc_promisc_last = table->mc_promisc;
822b96f8
DP		 5640}
5641
34813fe2
AR		 5642static struct efx_ef10_filter_vlan *efx_ef10_filter_find_vlan(struct efx_nic *efx, u16 vid)
5643{
5644 struct efx_ef10_filter_table *table = efx->filter_state;
5645 struct efx_ef10_filter_vlan *vlan;
5646
5647 WARN_ON(!rwsem_is_locked(&efx->filter_sem));
5648
5649 list_for_each_entry(vlan, &table->vlan_list, list) {
5650 if (vlan->vid == vid)
5651 return vlan;
5652 }
5653
5654 return NULL;
5655}
5656
5657static int efx_ef10_filter_add_vlan(struct efx_nic *efx, u16 vid)
5658{
5659 struct efx_ef10_filter_table *table = efx->filter_state;
5660 struct efx_ef10_filter_vlan *vlan;
5661 unsigned int i;
5662
5663 if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
5664 return -EINVAL;
5665
5666 vlan = efx_ef10_filter_find_vlan(efx, vid);
5667 if (WARN_ON(vlan)) {
5668 netif_err(efx, drv, efx->net_dev,
5669 "VLAN %u already added\n", vid);
5670 return -EALREADY;
5671 }
5672
5673 vlan = kzalloc(sizeof(*vlan), GFP_KERNEL);
5674 if (!vlan)
5675 return -ENOMEM;
5676
5677 vlan->vid = vid;
5678
5679 for (i = 0; i < ARRAY_SIZE(vlan->uc); i++)
5680 vlan->uc[i] = EFX_EF10_FILTER_ID_INVALID;
5681 for (i = 0; i < ARRAY_SIZE(vlan->mc); i++)
5682 vlan->mc[i] = EFX_EF10_FILTER_ID_INVALID;
9b410801
EC		 5683 for (i = 0; i < EFX_EF10_NUM_DEFAULT_FILTERS; i++)
5684 vlan->default_filters[i] = EFX_EF10_FILTER_ID_INVALID;
34813fe2
AR		 5685
5686 list_add_tail(&vlan->list, &table->vlan_list);
5687
5688 if (efx_dev_registered(efx))
5689 efx_ef10_filter_vlan_sync_rx_mode(efx, vlan);
5690
5691 return 0;
5692}
5693
5694static void efx_ef10_filter_del_vlan_internal(struct efx_nic *efx,
5695 struct efx_ef10_filter_vlan *vlan)
5696{
5697 unsigned int i;
5698
5699 /* See comment in efx_ef10_filter_table_remove() */
5700 if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
5701 return;
5702
5703 list_del(&vlan->list);
5704
8c915620 5705 for (i = 0; i < ARRAY_SIZE(vlan->uc); i++)
34813fe2 5706 efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO,
8c915620
EC		 5707 vlan->uc[i]);
5708 for (i = 0; i < ARRAY_SIZE(vlan->mc); i++)
34813fe2 5709 efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO,
8c915620 5710 vlan->mc[i]);
9b410801
EC		 5711 for (i = 0; i < EFX_EF10_NUM_DEFAULT_FILTERS; i++)
5712 if (vlan->default_filters[i] != EFX_EF10_FILTER_ID_INVALID)
5713 efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO,
5714 vlan->default_filters[i]);
34813fe2
AR		 5715
5716 kfree(vlan);
5717}
5718
5719static void efx_ef10_filter_del_vlan(struct efx_nic *efx, u16 vid)
5720{
5721 struct efx_ef10_filter_vlan *vlan;
5722
5723 /* See comment in efx_ef10_filter_table_remove() */
5724 if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
5725 return;
5726
5727 vlan = efx_ef10_filter_find_vlan(efx, vid);
5728 if (!vlan) {
5729 netif_err(efx, drv, efx->net_dev,
5730 "VLAN %u not found in filter state\n", vid);
5731 return;
5732 }
5733
5734 efx_ef10_filter_del_vlan_internal(efx, vlan);
5735}
5736
910c8789
SS		 5737static int efx_ef10_set_mac_address(struct efx_nic *efx)
5738{
5739 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_SET_MAC_IN_LEN);
5740 struct efx_ef10_nic_data *nic_data = efx->nic_data;
5741 bool was_enabled = efx->port_enabled;
5742 int rc;
5743
5744 efx_device_detach_sync(efx);
5745 efx_net_stop(efx->net_dev);
d248953a
MH		 5746
5747 mutex_lock(&efx->mac_lock);
910c8789
SS		 5748 down_write(&efx->filter_sem);
5749 efx_ef10_filter_table_remove(efx);
5750
5751 ether_addr_copy(MCDI_PTR(inbuf, VADAPTOR_SET_MAC_IN_MACADDR),
5752 efx->net_dev->dev_addr);
5753 MCDI_SET_DWORD(inbuf, VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID,
5754 nic_data->vport_id);
535a6177
DP		 5755 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_VADAPTOR_SET_MAC, inbuf,
5756 sizeof(inbuf), NULL, 0, NULL);
910c8789
SS		 5757
5758 efx_ef10_filter_table_probe(efx);
5759 up_write(&efx->filter_sem);
d248953a
MH		 5760 mutex_unlock(&efx->mac_lock);
5761
910c8789
SS		 5762 if (was_enabled)
5763 efx_net_open(efx->net_dev);
9c568fd8 5764 efx_device_attach_if_not_resetting(efx);
910c8789 5765
9e9f665a
DP		 5766#ifdef CONFIG_SFC_SRIOV
5767 if (efx->pci_dev->is_virtfn && efx->pci_dev->physfn) {
910c8789
SS		 5768 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn;
5769
9e9f665a
DP		 5770 if (rc == -EPERM) {
5771 struct efx_nic *efx_pf;
910c8789 5772
9e9f665a
DP		 5773 /* Switch to PF and change MAC address on vport */
5774 efx_pf = pci_get_drvdata(pci_dev_pf);
910c8789 5775
9e9f665a
DP		 5776 rc = efx_ef10_sriov_set_vf_mac(efx_pf,
5777 nic_data->vf_index,
5778 efx->net_dev->dev_addr);
5779 } else if (!rc) {
910c8789
SS		 5780 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
5781 struct efx_ef10_nic_data *nic_data = efx_pf->nic_data;
5782 unsigned int i;
5783
9e9f665a
DP		 5784 /* MAC address successfully changed by VF (with MAC
5785 * spoofing) so update the parent PF if possible.
5786 */
910c8789
SS		 5787 for (i = 0; i < efx_pf->vf_count; ++i) {
5788 struct ef10_vf *vf = nic_data->vf + i;
5789
5790 if (vf->efx == efx) {
5791 ether_addr_copy(vf->mac,
5792 efx->net_dev->dev_addr);
5793 return 0;
5794 }
5795 }
5796 }
9e9f665a 5797 } else
910c8789 5798#endif
9e9f665a
DP		 5799 if (rc == -EPERM) {
5800 netif_err(efx, drv, efx->net_dev,
5801 "Cannot change MAC address; use sfboot to enable"
5802 " mac-spoofing on this interface\n");
7a186f47
DP		 5803 } else if (rc == -ENOSYS && !efx_ef10_is_vf(efx)) {
5804 /* If the active MCFW does not support MC_CMD_VADAPTOR_SET_MAC
5805 * fall-back to the method of changing the MAC address on the
5806 * vport. This only applies to PFs because such versions of
5807 * MCFW do not support VFs.
5808 */
5809 rc = efx_ef10_vport_set_mac_address(efx);
cbad52e9 5810 } else if (rc) {
535a6177
DP		 5811 efx_mcdi_display_error(efx, MC_CMD_VADAPTOR_SET_MAC,
5812 sizeof(inbuf), NULL, 0, rc);
9e9f665a
DP		 5813 }
5814
910c8789
SS		 5815 return rc;
5816}
5817
8127d661
BH		 5818static int efx_ef10_mac_reconfigure(struct efx_nic *efx)
5819{
5820 efx_ef10_filter_sync_rx_mode(efx);
5821
5822 return efx_mcdi_set_mac(efx);
5823}
5824
862f894c
SS		 5825static int efx_ef10_mac_reconfigure_vf(struct efx_nic *efx)
5826{
5827 efx_ef10_filter_sync_rx_mode(efx);
5828
5829 return 0;
5830}
5831
74cd60a4
JC		 5832static int efx_ef10_start_bist(struct efx_nic *efx, u32 bist_type)
5833{
5834 MCDI_DECLARE_BUF(inbuf, MC_CMD_START_BIST_IN_LEN);
5835
5836 MCDI_SET_DWORD(inbuf, START_BIST_IN_TYPE, bist_type);
5837 return efx_mcdi_rpc(efx, MC_CMD_START_BIST, inbuf, sizeof(inbuf),
5838 NULL, 0, NULL);
5839}
5840
5841/* MC BISTs follow a different poll mechanism to phy BISTs.
5842 * The BIST is done in the poll handler on the MC, and the MCDI command
5843 * will block until the BIST is done.
5844 */
5845static int efx_ef10_poll_bist(struct efx_nic *efx)
5846{
5847 int rc;
5848 MCDI_DECLARE_BUF(outbuf, MC_CMD_POLL_BIST_OUT_LEN);
5849 size_t outlen;
5850 u32 result;
5851
5852 rc = efx_mcdi_rpc(efx, MC_CMD_POLL_BIST, NULL, 0,
5853 outbuf, sizeof(outbuf), &outlen);
5854 if (rc != 0)
5855 return rc;
5856
5857 if (outlen < MC_CMD_POLL_BIST_OUT_LEN)
5858 return -EIO;
5859
5860 result = MCDI_DWORD(outbuf, POLL_BIST_OUT_RESULT);
5861 switch (result) {
5862 case MC_CMD_POLL_BIST_PASSED:
5863 netif_dbg(efx, hw, efx->net_dev, "BIST passed.\n");
5864 return 0;
5865 case MC_CMD_POLL_BIST_TIMEOUT:
5866 netif_err(efx, hw, efx->net_dev, "BIST timed out\n");
5867 return -EIO;
5868 case MC_CMD_POLL_BIST_FAILED:
5869 netif_err(efx, hw, efx->net_dev, "BIST failed.\n");
5870 return -EIO;
5871 default:
5872 netif_err(efx, hw, efx->net_dev,
5873 "BIST returned unknown result %u", result);
5874 return -EIO;
5875 }
5876}
5877
5878static int efx_ef10_run_bist(struct efx_nic *efx, u32 bist_type)
5879{
5880 int rc;
5881
5882 netif_dbg(efx, drv, efx->net_dev, "starting BIST type %u\n", bist_type);
5883
5884 rc = efx_ef10_start_bist(efx, bist_type);
5885 if (rc != 0)
5886 return rc;
5887
5888 return efx_ef10_poll_bist(efx);
5889}
5890
5891static int
5892efx_ef10_test_chip(struct efx_nic *efx, struct efx_self_tests *tests)
5893{
5894 int rc, rc2;
5895
5896 efx_reset_down(efx, RESET_TYPE_WORLD);
5897
5898 rc = efx_mcdi_rpc(efx, MC_CMD_ENABLE_OFFLINE_BIST,
5899 NULL, 0, NULL, 0, NULL);
5900 if (rc != 0)
5901 goto out;
5902
5903 tests->memory = efx_ef10_run_bist(efx, MC_CMD_MC_MEM_BIST) ? -1 : 1;
5904 tests->registers = efx_ef10_run_bist(efx, MC_CMD_REG_BIST) ? -1 : 1;
5905
5906 rc = efx_mcdi_reset(efx, RESET_TYPE_WORLD);
5907
5908out:
27324820
DP		 5909 if (rc == -EPERM)
5910 rc = 0;
74cd60a4
JC		 5911 rc2 = efx_reset_up(efx, RESET_TYPE_WORLD, rc == 0);
5912 return rc ? rc : rc2;
5913}
5914
8127d661
BH		 5915#ifdef CONFIG_SFC_MTD
5916
5917struct efx_ef10_nvram_type_info {
5918 u16 type, type_mask;
5919 u8 port;
5920 const char *name;
5921};
5922
5923static const struct efx_ef10_nvram_type_info efx_ef10_nvram_types[] = {
5924 { NVRAM_PARTITION_TYPE_MC_FIRMWARE, 0, 0, "sfc_mcfw" },
5925 { NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 0, 0, "sfc_mcfw_backup" },
5926 { NVRAM_PARTITION_TYPE_EXPANSION_ROM, 0, 0, "sfc_exp_rom" },
5927 { NVRAM_PARTITION_TYPE_STATIC_CONFIG, 0, 0, "sfc_static_cfg" },
5928 { NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG, 0, 0, "sfc_dynamic_cfg" },
5929 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0, 0, 0, "sfc_exp_rom_cfg" },
5930 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1, 0, 1, "sfc_exp_rom_cfg" },
5931 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2, 0, 2, "sfc_exp_rom_cfg" },
5932 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3, 0, 3, "sfc_exp_rom_cfg" },
a84f3bf9 5933 { NVRAM_PARTITION_TYPE_LICENSE, 0, 0, "sfc_license" },
8127d661
BH		 5934 { NVRAM_PARTITION_TYPE_PHY_MIN, 0xff, 0, "sfc_phy_fw" },
5935};
5936
5937static int efx_ef10_mtd_probe_partition(struct efx_nic *efx,
5938 struct efx_mcdi_mtd_partition *part,
5939 unsigned int type)
5940{
5941 MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_METADATA_IN_LEN);
5942 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_METADATA_OUT_LENMAX);
5943 const struct efx_ef10_nvram_type_info *info;
5944 size_t size, erase_size, outlen;
5945 bool protected;
5946 int rc;
5947
5948 for (info = efx_ef10_nvram_types; ; info++) {
5949 if (info ==
5950 efx_ef10_nvram_types + ARRAY_SIZE(efx_ef10_nvram_types))
5951 return -ENODEV;
5952 if ((type & ~info->type_mask) == info->type)
5953 break;
5954 }
5955 if (info->port != efx_port_num(efx))
5956 return -ENODEV;
5957
5958 rc = efx_mcdi_nvram_info(efx, type, &size, &erase_size, &protected);
5959 if (rc)
5960 return rc;
5961 if (protected)
5962 return -ENODEV; /* hide it */
5963
5964 part->nvram_type = type;
5965
5966 MCDI_SET_DWORD(inbuf, NVRAM_METADATA_IN_TYPE, type);
5967 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_METADATA, inbuf, sizeof(inbuf),
5968 outbuf, sizeof(outbuf), &outlen);
5969 if (rc)
5970 return rc;
5971 if (outlen < MC_CMD_NVRAM_METADATA_OUT_LENMIN)
5972 return -EIO;
5973 if (MCDI_DWORD(outbuf, NVRAM_METADATA_OUT_FLAGS) &
5974 (1 << MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN))
5975 part->fw_subtype = MCDI_DWORD(outbuf,
5976 NVRAM_METADATA_OUT_SUBTYPE);
5977
5978 part->common.dev_type_name = "EF10 NVRAM manager";
5979 part->common.type_name = info->name;
5980
5981 part->common.mtd.type = MTD_NORFLASH;
5982 part->common.mtd.flags = MTD_CAP_NORFLASH;
5983 part->common.mtd.size = size;
5984 part->common.mtd.erasesize = erase_size;
5985
5986 return 0;
5987}
5988
5989static int efx_ef10_mtd_probe(struct efx_nic *efx)
5990{
5991 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX);
5992 struct efx_mcdi_mtd_partition *parts;
5993 size_t outlen, n_parts_total, i, n_parts;
5994 unsigned int type;
5995 int rc;
5996
5997 ASSERT_RTNL();
5998
5999 BUILD_BUG_ON(MC_CMD_NVRAM_PARTITIONS_IN_LEN != 0);
6000 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_PARTITIONS, NULL, 0,
6001 outbuf, sizeof(outbuf), &outlen);
6002 if (rc)
6003 return rc;
6004 if (outlen < MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN)
6005 return -EIO;
6006
6007 n_parts_total = MCDI_DWORD(outbuf, NVRAM_PARTITIONS_OUT_NUM_PARTITIONS);
6008 if (n_parts_total >
6009 MCDI_VAR_ARRAY_LEN(outlen, NVRAM_PARTITIONS_OUT_TYPE_ID))
6010 return -EIO;
6011
6012 parts = kcalloc(n_parts_total, sizeof(*parts), GFP_KERNEL);
6013 if (!parts)
6014 return -ENOMEM;
6015
6016 n_parts = 0;
6017 for (i = 0; i < n_parts_total; i++) {
6018 type = MCDI_ARRAY_DWORD(outbuf, NVRAM_PARTITIONS_OUT_TYPE_ID,
6019 i);
6020 rc = efx_ef10_mtd_probe_partition(efx, &parts[n_parts], type);
6021 if (rc == 0)
6022 n_parts++;
6023 else if (rc != -ENODEV)
6024 goto fail;
6025 }
6026
6027 rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts));
6028fail:
6029 if (rc)
6030 kfree(parts);
6031 return rc;
6032}
6033
6034#endif /* CONFIG_SFC_MTD */
6035
6036static void efx_ef10_ptp_write_host_time(struct efx_nic *efx, u32 host_time)
6037{
6038 _efx_writed(efx, cpu_to_le32(host_time), ER_DZ_MC_DB_LWRD);
6039}
6040
02246a7f
SS		 6041static void efx_ef10_ptp_write_host_time_vf(struct efx_nic *efx,
6042 u32 host_time) {}
6043
bd9a265d
JC		 6044static int efx_ef10_rx_enable_timestamping(struct efx_channel *channel,
6045 bool temp)
6046{
6047 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN);
6048 int rc;
6049
6050 if (channel->sync_events_state == SYNC_EVENTS_REQUESTED ||
6051 channel->sync_events_state == SYNC_EVENTS_VALID ||
6052 (temp && channel->sync_events_state == SYNC_EVENTS_DISABLED))
6053 return 0;
6054 channel->sync_events_state = SYNC_EVENTS_REQUESTED;
6055
6056 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE);
6057 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
6058 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE,
6059 channel->channel);
6060
6061 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
6062 inbuf, sizeof(inbuf), NULL, 0, NULL);
6063
6064 if (rc != 0)
6065 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
6066 SYNC_EVENTS_DISABLED;
6067
6068 return rc;
6069}
6070
6071static int efx_ef10_rx_disable_timestamping(struct efx_channel *channel,
6072 bool temp)
6073{
6074 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN);
6075 int rc;
6076
6077 if (channel->sync_events_state == SYNC_EVENTS_DISABLED ||
6078 (temp && channel->sync_events_state == SYNC_EVENTS_QUIESCENT))
6079 return 0;
6080 if (channel->sync_events_state == SYNC_EVENTS_QUIESCENT) {
6081 channel->sync_events_state = SYNC_EVENTS_DISABLED;
6082 return 0;
6083 }
6084 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
6085 SYNC_EVENTS_DISABLED;
6086
6087 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE);
6088 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
6089 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL,
6090 MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE);
6091 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE,
6092 channel->channel);
6093
6094 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
6095 inbuf, sizeof(inbuf), NULL, 0, NULL);
6096
6097 return rc;
6098}
6099
6100static int efx_ef10_ptp_set_ts_sync_events(struct efx_nic *efx, bool en,
6101 bool temp)
6102{
6103 int (*set)(struct efx_channel *channel, bool temp);
6104 struct efx_channel *channel;
6105
6106 set = en ?
6107 efx_ef10_rx_enable_timestamping :
6108 efx_ef10_rx_disable_timestamping;
6109
6110 efx_for_each_channel(channel, efx) {
6111 int rc = set(channel, temp);
6112 if (en && rc != 0) {
6113 efx_ef10_ptp_set_ts_sync_events(efx, false, temp);
6114 return rc;
6115 }
6116 }
6117
6118 return 0;
6119}
6120
02246a7f
SS		 6121static int efx_ef10_ptp_set_ts_config_vf(struct efx_nic *efx,
6122 struct hwtstamp_config *init)
6123{
6124 return -EOPNOTSUPP;
6125}
6126
bd9a265d
JC		 6127static int efx_ef10_ptp_set_ts_config(struct efx_nic *efx,
6128 struct hwtstamp_config *init)
6129{
6130 int rc;
6131
6132 switch (init->rx_filter) {
6133 case HWTSTAMP_FILTER_NONE:
6134 efx_ef10_ptp_set_ts_sync_events(efx, false, false);
6135 /* if TX timestamping is still requested then leave PTP on */
6136 return efx_ptp_change_mode(efx,
6137 init->tx_type != HWTSTAMP_TX_OFF, 0);
6138 case HWTSTAMP_FILTER_ALL:
6139 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
6140 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
6141 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
6142 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
6143 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
6144 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
6145 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
6146 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
6147 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
6148 case HWTSTAMP_FILTER_PTP_V2_EVENT:
6149 case HWTSTAMP_FILTER_PTP_V2_SYNC:
6150 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
e3412575 6151 case HWTSTAMP_FILTER_NTP_ALL:
bd9a265d
JC		 6152 init->rx_filter = HWTSTAMP_FILTER_ALL;
6153 rc = efx_ptp_change_mode(efx, true, 0);
6154 if (!rc)
6155 rc = efx_ef10_ptp_set_ts_sync_events(efx, true, false);
6156 if (rc)
6157 efx_ptp_change_mode(efx, false, 0);
6158 return rc;
6159 default:
6160 return -ERANGE;
6161 }
6162}
6163
08a7b29b
BK		 6164static int efx_ef10_get_phys_port_id(struct efx_nic *efx,
6165 struct netdev_phys_item_id *ppid)
6166{
6167 struct efx_ef10_nic_data *nic_data = efx->nic_data;
6168
6169 if (!is_valid_ether_addr(nic_data->port_id))
6170 return -EOPNOTSUPP;
6171
6172 ppid->id_len = ETH_ALEN;
6173 memcpy(ppid->id, nic_data->port_id, ppid->id_len);
6174
6175 return 0;
6176}
6177
4a53ea8a
AR		 6178static int efx_ef10_vlan_rx_add_vid(struct efx_nic *efx, __be16 proto, u16 vid)
6179{
6180 if (proto != htons(ETH_P_8021Q))
6181 return -EINVAL;
6182
6183 return efx_ef10_add_vlan(efx, vid);
6184}
6185
6186static int efx_ef10_vlan_rx_kill_vid(struct efx_nic *efx, __be16 proto, u16 vid)
6187{
6188 if (proto != htons(ETH_P_8021Q))
6189 return -EINVAL;
6190
6191 return efx_ef10_del_vlan(efx, vid);
6192}
6193
e5fbd977
JC		 6194/* We rely on the MCDI wiping out our TX rings if it made any changes to the
6195 * ports table, ensuring that any TSO descriptors that were made on a now-
6196 * removed tunnel port will be blown away and won't break things when we try
6197 * to transmit them using the new ports table.
6198 */
6199static int efx_ef10_set_udp_tnl_ports(struct efx_nic *efx, bool unloading)
6200{
6201 struct efx_ef10_nic_data *nic_data = efx->nic_data;
6202 MCDI_DECLARE_BUF(inbuf, MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LENMAX);
6203 MCDI_DECLARE_BUF(outbuf, MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_LEN);
6204 bool will_reset = false;
6205 size_t num_entries = 0;
6206 size_t inlen, outlen;
6207 size_t i;
6208 int rc;
6209 efx_dword_t flags_and_num_entries;
6210
6211 WARN_ON(!mutex_is_locked(&nic_data->udp_tunnels_lock));
6212
6213 nic_data->udp_tunnels_dirty = false;
6214
6215 if (!(nic_data->datapath_caps &
6216 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN))) {
9c568fd8 6217 efx_device_attach_if_not_resetting(efx);
e5fbd977
JC		 6218 return 0;
6219 }
6220
6221 BUILD_BUG_ON(ARRAY_SIZE(nic_data->udp_tunnels) >
6222 MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MAXNUM);
6223
6224 for (i = 0; i < ARRAY_SIZE(nic_data->udp_tunnels); ++i) {
6225 if (nic_data->udp_tunnels[i].count &&
6226 nic_data->udp_tunnels[i].port) {
6227 efx_dword_t entry;
6228
6229 EFX_POPULATE_DWORD_2(entry,
6230 TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT,
6231 ntohs(nic_data->udp_tunnels[i].port),
6232 TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL,
6233 nic_data->udp_tunnels[i].type);
6234 *_MCDI_ARRAY_DWORD(inbuf,
6235 SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES,
6236 num_entries++) = entry;
6237 }
6238 }
6239
6240 BUILD_BUG_ON((MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_NUM_ENTRIES_OFST -
6241 MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS_OFST) * 8 !=
6242 EFX_WORD_1_LBN);
6243 BUILD_BUG_ON(MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_NUM_ENTRIES_LEN * 8 !=
6244 EFX_WORD_1_WIDTH);
6245 EFX_POPULATE_DWORD_2(flags_and_num_entries,
6246 MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_UNLOADING,
6247 !!unloading,
6248 EFX_WORD_1, num_entries);
6249 *_MCDI_DWORD(inbuf, SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS) =
6250 flags_and_num_entries;
6251
6252 inlen = MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LEN(num_entries);
6253
6254 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS,
6255 inbuf, inlen, outbuf, sizeof(outbuf), &outlen);
6256 if (rc == -EIO) {
6257 /* Most likely the MC rebooted due to another function also
6258 * setting its tunnel port list. Mark the tunnel port list as
6259 * dirty, so it will be pushed upon coming up from the reboot.
6260 */
6261 nic_data->udp_tunnels_dirty = true;
6262 return 0;
6263 }
6264
6265 if (rc) {
6266 /* expected not available on unprivileged functions */
6267 if (rc != -EPERM)
6268 netif_warn(efx, drv, efx->net_dev,
6269 "Unable to set UDP tunnel ports; rc=%d.\n", rc);
6270 } else if (MCDI_DWORD(outbuf, SET_TUNNEL_ENCAP_UDP_PORTS_OUT_FLAGS) &
6271 (1 << MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_RESETTING_LBN)) {
6272 netif_info(efx, drv, efx->net_dev,
6273 "Rebooting MC due to UDP tunnel port list change\n");
6274 will_reset = true;
6275 if (unloading)
6276 /* Delay for the MC reset to complete. This will make
6277 * unloading other functions a bit smoother. This is a
6278 * race, but the other unload will work whichever way
6279 * it goes, this just avoids an unnecessary error
6280 * message.
6281 */
6282 msleep(100);
6283 }
6284 if (!will_reset && !unloading) {
6285 /* The caller will have detached, relying on the MC reset to
6286 * trigger a re-attach. Since there won't be an MC reset, we
6287 * have to do the attach ourselves.
6288 */
9c568fd8 6289 efx_device_attach_if_not_resetting(efx);
e5fbd977
JC		 6290 }
6291
6292 return rc;
6293}
6294
6295static int efx_ef10_udp_tnl_push_ports(struct efx_nic *efx)
6296{
6297 struct efx_ef10_nic_data *nic_data = efx->nic_data;
6298 int rc = 0;
6299
6300 mutex_lock(&nic_data->udp_tunnels_lock);
6301 if (nic_data->udp_tunnels_dirty) {
6302 /* Make sure all TX are stopped while we modify the table, else
6303 * we might race against an efx_features_check().
6304 */
6305 efx_device_detach_sync(efx);
6306 rc = efx_ef10_set_udp_tnl_ports(efx, false);
6307 }
6308 mutex_unlock(&nic_data->udp_tunnels_lock);
6309 return rc;
6310}
6311
6312static struct efx_udp_tunnel *__efx_ef10_udp_tnl_lookup_port(struct efx_nic *efx,
6313 __be16 port)
6314{
6315 struct efx_ef10_nic_data *nic_data = efx->nic_data;
6316 size_t i;
6317
6318 for (i = 0; i < ARRAY_SIZE(nic_data->udp_tunnels); ++i) {
6319 if (!nic_data->udp_tunnels[i].count)
6320 continue;
6321 if (nic_data->udp_tunnels[i].port == port)
6322 return &nic_data->udp_tunnels[i];
6323 }
6324 return NULL;
6325}
6326
6327static int efx_ef10_udp_tnl_add_port(struct efx_nic *efx,
6328 struct efx_udp_tunnel tnl)
6329{
6330 struct efx_ef10_nic_data *nic_data = efx->nic_data;
6331 struct efx_udp_tunnel *match;
6332 char typebuf[8];
6333 size_t i;
6334 int rc;
6335
6336 if (!(nic_data->datapath_caps &
6337 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN)))
6338 return 0;
6339
6340 efx_get_udp_tunnel_type_name(tnl.type, typebuf, sizeof(typebuf));
6341 netif_dbg(efx, drv, efx->net_dev, "Adding UDP tunnel (%s) port %d\n",
6342 typebuf, ntohs(tnl.port));
6343
6344 mutex_lock(&nic_data->udp_tunnels_lock);
6345 /* Make sure all TX are stopped while we add to the table, else we
6346 * might race against an efx_features_check().
6347 */
6348 efx_device_detach_sync(efx);
6349
6350 match = __efx_ef10_udp_tnl_lookup_port(efx, tnl.port);
6351 if (match != NULL) {
6352 if (match->type == tnl.type) {
6353 netif_dbg(efx, drv, efx->net_dev,
6354 "Referencing existing tunnel entry\n");
6355 match->count++;
6356 /* No need to cause an MCDI update */
6357 rc = 0;
6358 goto unlock_out;
6359 }
6360 efx_get_udp_tunnel_type_name(match->type,
6361 typebuf, sizeof(typebuf));
6362 netif_dbg(efx, drv, efx->net_dev,
6363 "UDP port %d is already in use by %s\n",
6364 ntohs(tnl.port), typebuf);
6365 rc = -EEXIST;
6366 goto unlock_out;
6367 }
6368
6369 for (i = 0; i < ARRAY_SIZE(nic_data->udp_tunnels); ++i)
6370 if (!nic_data->udp_tunnels[i].count) {
6371 nic_data->udp_tunnels[i] = tnl;
6372 nic_data->udp_tunnels[i].count = 1;
6373 rc = efx_ef10_set_udp_tnl_ports(efx, false);
6374 goto unlock_out;
6375 }
6376
6377 netif_dbg(efx, drv, efx->net_dev,
6378 "Unable to add UDP tunnel (%s) port %d; insufficient resources.\n",
6379 typebuf, ntohs(tnl.port));
6380
6381 rc = -ENOMEM;
6382
6383unlock_out:
6384 mutex_unlock(&nic_data->udp_tunnels_lock);
6385 return rc;
6386}
6387
6388/* Called under the TX lock with the TX queue running, hence no-one can be
6389 * in the middle of updating the UDP tunnels table. However, they could
6390 * have tried and failed the MCDI, in which case they'll have set the dirty
6391 * flag before dropping their locks.
6392 */
6393static bool efx_ef10_udp_tnl_has_port(struct efx_nic *efx, __be16 port)
6394{
6395 struct efx_ef10_nic_data *nic_data = efx->nic_data;
6396
6397 if (!(nic_data->datapath_caps &
6398 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN)))
6399 return false;
6400
6401 if (nic_data->udp_tunnels_dirty)
6402 /* SW table may not match HW state, so just assume we can't
6403 * use any UDP tunnel offloads.
6404 */
6405 return false;
6406
6407 return __efx_ef10_udp_tnl_lookup_port(efx, port) != NULL;
6408}
6409
6410static int efx_ef10_udp_tnl_del_port(struct efx_nic *efx,
6411 struct efx_udp_tunnel tnl)
6412{
6413 struct efx_ef10_nic_data *nic_data = efx->nic_data;
6414 struct efx_udp_tunnel *match;
6415 char typebuf[8];
6416 int rc;
6417
6418 if (!(nic_data->datapath_caps &
6419 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN)))
6420 return 0;
6421
6422 efx_get_udp_tunnel_type_name(tnl.type, typebuf, sizeof(typebuf));
6423 netif_dbg(efx, drv, efx->net_dev, "Removing UDP tunnel (%s) port %d\n",
6424 typebuf, ntohs(tnl.port));
6425
6426 mutex_lock(&nic_data->udp_tunnels_lock);
6427 /* Make sure all TX are stopped while we remove from the table, else we
6428 * might race against an efx_features_check().
6429 */
6430 efx_device_detach_sync(efx);
6431
6432 match = __efx_ef10_udp_tnl_lookup_port(efx, tnl.port);
6433 if (match != NULL) {
6434 if (match->type == tnl.type) {
6435 if (--match->count) {
6436 /* Port is still in use, so nothing to do */
6437 netif_dbg(efx, drv, efx->net_dev,
6438 "UDP tunnel port %d remains active\n",
6439 ntohs(tnl.port));
6440 rc = 0;
6441 goto out_unlock;
6442 }
6443 rc = efx_ef10_set_udp_tnl_ports(efx, false);
6444 goto out_unlock;
6445 }
6446 efx_get_udp_tunnel_type_name(match->type,
6447 typebuf, sizeof(typebuf));
6448 netif_warn(efx, drv, efx->net_dev,
6449 "UDP port %d is actually in use by %s, not removing\n",
6450 ntohs(tnl.port), typebuf);
6451 }
6452 rc = -ENOENT;
6453
6454out_unlock:
6455 mutex_unlock(&nic_data->udp_tunnels_lock);
6456 return rc;
6457}
6458
100a9db5
AR		 6459#define EF10_OFFLOAD_FEATURES \
6460 (NETIF_F_IP_CSUM | \
4a53ea8a 6461 NETIF_F_HW_VLAN_CTAG_FILTER | \
100a9db5
AR		 6462 NETIF_F_IPV6_CSUM | \
6463 NETIF_F_RXHASH | \
6464 NETIF_F_NTUPLE)
6465
02246a7f 6466const struct efx_nic_type efx_hunt_a0_vf_nic_type = {
6f7f8aa6 6467 .is_vf = true,
03714bbb 6468 .mem_bar = efx_ef10_vf_mem_bar,
02246a7f
SS		 6469 .mem_map_size = efx_ef10_mem_map_size,
6470 .probe = efx_ef10_probe_vf,
6471 .remove = efx_ef10_remove,
6472 .dimension_resources = efx_ef10_dimension_resources,
6473 .init = efx_ef10_init_nic,
6474 .fini = efx_port_dummy_op_void,
087e9025 6475 .map_reset_reason = efx_ef10_map_reset_reason,
02246a7f
SS		 6476 .map_reset_flags = efx_ef10_map_reset_flags,
6477 .reset = efx_ef10_reset,
6478 .probe_port = efx_mcdi_port_probe,
6479 .remove_port = efx_mcdi_port_remove,
6480 .fini_dmaq = efx_ef10_fini_dmaq,
6481 .prepare_flr = efx_ef10_prepare_flr,
6482 .finish_flr = efx_port_dummy_op_void,
6483 .describe_stats = efx_ef10_describe_stats,
d7788196 6484 .update_stats = efx_ef10_update_stats_vf,
02246a7f
SS		 6485 .start_stats = efx_port_dummy_op_void,
6486 .pull_stats = efx_port_dummy_op_void,
6487 .stop_stats = efx_port_dummy_op_void,
6488 .set_id_led = efx_mcdi_set_id_led,
6489 .push_irq_moderation = efx_ef10_push_irq_moderation,
862f894c 6490 .reconfigure_mac = efx_ef10_mac_reconfigure_vf,
02246a7f
SS		 6491 .check_mac_fault = efx_mcdi_mac_check_fault,
6492 .reconfigure_port = efx_mcdi_port_reconfigure,
6493 .get_wol = efx_ef10_get_wol_vf,
6494 .set_wol = efx_ef10_set_wol_vf,
6495 .resume_wol = efx_port_dummy_op_void,
6496 .mcdi_request = efx_ef10_mcdi_request,
6497 .mcdi_poll_response = efx_ef10_mcdi_poll_response,
6498 .mcdi_read_response = efx_ef10_mcdi_read_response,
6499 .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot,
c577e59e 6500 .mcdi_reboot_detected = efx_ef10_mcdi_reboot_detected,
02246a7f
SS		 6501 .irq_enable_master = efx_port_dummy_op_void,
6502 .irq_test_generate = efx_ef10_irq_test_generate,
6503 .irq_disable_non_ev = efx_port_dummy_op_void,
6504 .irq_handle_msi = efx_ef10_msi_interrupt,
6505 .irq_handle_legacy = efx_ef10_legacy_interrupt,
6506 .tx_probe = efx_ef10_tx_probe,
6507 .tx_init = efx_ef10_tx_init,
6508 .tx_remove = efx_ef10_tx_remove,
6509 .tx_write = efx_ef10_tx_write,
e9117e50 6510 .tx_limit_len = efx_ef10_tx_limit_len,
267c0157 6511 .rx_push_rss_config = efx_ef10_vf_rx_push_rss_config,
a707d188 6512 .rx_pull_rss_config = efx_ef10_rx_pull_rss_config,
02246a7f
SS		 6513 .rx_probe = efx_ef10_rx_probe,
6514 .rx_init = efx_ef10_rx_init,
6515 .rx_remove = efx_ef10_rx_remove,
6516 .rx_write = efx_ef10_rx_write,
6517 .rx_defer_refill = efx_ef10_rx_defer_refill,
6518 .ev_probe = efx_ef10_ev_probe,
6519 .ev_init = efx_ef10_ev_init,
6520 .ev_fini = efx_ef10_ev_fini,
6521 .ev_remove = efx_ef10_ev_remove,
6522 .ev_process = efx_ef10_ev_process,
6523 .ev_read_ack = efx_ef10_ev_read_ack,
6524 .ev_test_generate = efx_ef10_ev_test_generate,
6525 .filter_table_probe = efx_ef10_filter_table_probe,
6526 .filter_table_restore = efx_ef10_filter_table_restore,
6527 .filter_table_remove = efx_ef10_filter_table_remove,
6528 .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter,
6529 .filter_insert = efx_ef10_filter_insert,
6530 .filter_remove_safe = efx_ef10_filter_remove_safe,
6531 .filter_get_safe = efx_ef10_filter_get_safe,
6532 .filter_clear_rx = efx_ef10_filter_clear_rx,
6533 .filter_count_rx_used = efx_ef10_filter_count_rx_used,
6534 .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit,
6535 .filter_get_rx_ids = efx_ef10_filter_get_rx_ids,
6536#ifdef CONFIG_RFS_ACCEL
6537 .filter_rfs_insert = efx_ef10_filter_rfs_insert,
6538 .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one,
6539#endif
6540#ifdef CONFIG_SFC_MTD
6541 .mtd_probe = efx_port_dummy_op_int,
6542#endif
6543 .ptp_write_host_time = efx_ef10_ptp_write_host_time_vf,
6544 .ptp_set_ts_config = efx_ef10_ptp_set_ts_config_vf,
4a53ea8a
AR		 6545 .vlan_rx_add_vid = efx_ef10_vlan_rx_add_vid,
6546 .vlan_rx_kill_vid = efx_ef10_vlan_rx_kill_vid,
02246a7f 6547#ifdef CONFIG_SFC_SRIOV
7b8c7b54
SS		 6548 .vswitching_probe = efx_ef10_vswitching_probe_vf,
6549 .vswitching_restore = efx_ef10_vswitching_restore_vf,
6550 .vswitching_remove = efx_ef10_vswitching_remove_vf,
02246a7f 6551#endif
0d5e0fbb 6552 .get_mac_address = efx_ef10_get_mac_address_vf,
910c8789 6553 .set_mac_address = efx_ef10_set_mac_address,
0d5e0fbb 6554
08a7b29b 6555 .get_phys_port_id = efx_ef10_get_phys_port_id,
02246a7f
SS		 6556 .revision = EFX_REV_HUNT_A0,
6557 .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH),
6558 .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE,
6559 .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST,
6560 .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST,
6561 .can_rx_scatter = true,
6562 .always_rx_scatter = true,
6f9f6ec2 6563 .min_interrupt_mode = EFX_INT_MODE_MSIX,
02246a7f
SS		 6564 .max_interrupt_mode = EFX_INT_MODE_MSIX,
6565 .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH,
100a9db5 6566 .offload_features = EF10_OFFLOAD_FEATURES,
02246a7f
SS		 6567 .mcdi_max_ver = 2,
6568 .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS,
6569 .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE |
6570 1 << HWTSTAMP_FILTER_ALL,
f74d1995 6571 .rx_hash_key_size = 40,
02246a7f
SS		 6572};
6573
8127d661 6574const struct efx_nic_type efx_hunt_a0_nic_type = {
6f7f8aa6 6575 .is_vf = false,
03714bbb 6576 .mem_bar = efx_ef10_pf_mem_bar,
8127d661 6577 .mem_map_size = efx_ef10_mem_map_size,
02246a7f 6578 .probe = efx_ef10_probe_pf,
8127d661
BH		 6579 .remove = efx_ef10_remove,
6580 .dimension_resources = efx_ef10_dimension_resources,
6581 .init = efx_ef10_init_nic,
6582 .fini = efx_port_dummy_op_void,
087e9025 6583 .map_reset_reason = efx_ef10_map_reset_reason,
8127d661 6584 .map_reset_flags = efx_ef10_map_reset_flags,
3e336261 6585 .reset = efx_ef10_reset,
8127d661
BH		 6586 .probe_port = efx_mcdi_port_probe,
6587 .remove_port = efx_mcdi_port_remove,
6588 .fini_dmaq = efx_ef10_fini_dmaq,
e283546c
EC		 6589 .prepare_flr = efx_ef10_prepare_flr,
6590 .finish_flr = efx_port_dummy_op_void,
8127d661 6591 .describe_stats = efx_ef10_describe_stats,
d7788196 6592 .update_stats = efx_ef10_update_stats_pf,
8127d661 6593 .start_stats = efx_mcdi_mac_start_stats,
f8f3b5ae 6594 .pull_stats = efx_mcdi_mac_pull_stats,
8127d661
BH		 6595 .stop_stats = efx_mcdi_mac_stop_stats,
6596 .set_id_led = efx_mcdi_set_id_led,
6597 .push_irq_moderation = efx_ef10_push_irq_moderation,
6598 .reconfigure_mac = efx_ef10_mac_reconfigure,
6599 .check_mac_fault = efx_mcdi_mac_check_fault,
6600 .reconfigure_port = efx_mcdi_port_reconfigure,
6601 .get_wol = efx_ef10_get_wol,
6602 .set_wol = efx_ef10_set_wol,
6603 .resume_wol = efx_port_dummy_op_void,
74cd60a4 6604 .test_chip = efx_ef10_test_chip,
8127d661
BH		 6605 .test_nvram = efx_mcdi_nvram_test_all,
6606 .mcdi_request = efx_ef10_mcdi_request,
6607 .mcdi_poll_response = efx_ef10_mcdi_poll_response,
6608 .mcdi_read_response = efx_ef10_mcdi_read_response,
6609 .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot,
c577e59e 6610 .mcdi_reboot_detected = efx_ef10_mcdi_reboot_detected,
8127d661
BH		 6611 .irq_enable_master = efx_port_dummy_op_void,
6612 .irq_test_generate = efx_ef10_irq_test_generate,
6613 .irq_disable_non_ev = efx_port_dummy_op_void,
6614 .irq_handle_msi = efx_ef10_msi_interrupt,
6615 .irq_handle_legacy = efx_ef10_legacy_interrupt,
6616 .tx_probe = efx_ef10_tx_probe,
6617 .tx_init = efx_ef10_tx_init,
6618 .tx_remove = efx_ef10_tx_remove,
6619 .tx_write = efx_ef10_tx_write,
e9117e50 6620 .tx_limit_len = efx_ef10_tx_limit_len,
267c0157 6621 .rx_push_rss_config = efx_ef10_pf_rx_push_rss_config,
a707d188 6622 .rx_pull_rss_config = efx_ef10_rx_pull_rss_config,
8127d661
BH		 6623 .rx_probe = efx_ef10_rx_probe,
6624 .rx_init = efx_ef10_rx_init,
6625 .rx_remove = efx_ef10_rx_remove,
6626 .rx_write = efx_ef10_rx_write,
6627 .rx_defer_refill = efx_ef10_rx_defer_refill,
6628 .ev_probe = efx_ef10_ev_probe,
6629 .ev_init = efx_ef10_ev_init,
6630 .ev_fini = efx_ef10_ev_fini,
6631 .ev_remove = efx_ef10_ev_remove,
6632 .ev_process = efx_ef10_ev_process,
6633 .ev_read_ack = efx_ef10_ev_read_ack,
6634 .ev_test_generate = efx_ef10_ev_test_generate,
6635 .filter_table_probe = efx_ef10_filter_table_probe,
6636 .filter_table_restore = efx_ef10_filter_table_restore,
6637 .filter_table_remove = efx_ef10_filter_table_remove,
6638 .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter,
6639 .filter_insert = efx_ef10_filter_insert,
6640 .filter_remove_safe = efx_ef10_filter_remove_safe,
6641 .filter_get_safe = efx_ef10_filter_get_safe,
6642 .filter_clear_rx = efx_ef10_filter_clear_rx,
6643 .filter_count_rx_used = efx_ef10_filter_count_rx_used,
6644 .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit,
6645 .filter_get_rx_ids = efx_ef10_filter_get_rx_ids,
6646#ifdef CONFIG_RFS_ACCEL
6647 .filter_rfs_insert = efx_ef10_filter_rfs_insert,
6648 .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one,
6649#endif
6650#ifdef CONFIG_SFC_MTD
6651 .mtd_probe = efx_ef10_mtd_probe,
6652 .mtd_rename = efx_mcdi_mtd_rename,
6653 .mtd_read = efx_mcdi_mtd_read,
6654 .mtd_erase = efx_mcdi_mtd_erase,
6655 .mtd_write = efx_mcdi_mtd_write,
6656 .mtd_sync = efx_mcdi_mtd_sync,
6657#endif
6658 .ptp_write_host_time = efx_ef10_ptp_write_host_time,
bd9a265d
JC		 6659 .ptp_set_ts_sync_events = efx_ef10_ptp_set_ts_sync_events,
6660 .ptp_set_ts_config = efx_ef10_ptp_set_ts_config,
4a53ea8a
AR		 6661 .vlan_rx_add_vid = efx_ef10_vlan_rx_add_vid,
6662 .vlan_rx_kill_vid = efx_ef10_vlan_rx_kill_vid,
e5fbd977
JC		 6663 .udp_tnl_push_ports = efx_ef10_udp_tnl_push_ports,
6664 .udp_tnl_add_port = efx_ef10_udp_tnl_add_port,
6665 .udp_tnl_has_port = efx_ef10_udp_tnl_has_port,
6666 .udp_tnl_del_port = efx_ef10_udp_tnl_del_port,
7fa8d547 6667#ifdef CONFIG_SFC_SRIOV
834e23dd 6668 .sriov_configure = efx_ef10_sriov_configure,
d98a4ffe
SS		 6669 .sriov_init = efx_ef10_sriov_init,
6670 .sriov_fini = efx_ef10_sriov_fini,
d98a4ffe
SS		 6671 .sriov_wanted = efx_ef10_sriov_wanted,
6672 .sriov_reset = efx_ef10_sriov_reset,
7fa8d547
SS		 6673 .sriov_flr = efx_ef10_sriov_flr,
6674 .sriov_set_vf_mac = efx_ef10_sriov_set_vf_mac,
6675 .sriov_set_vf_vlan = efx_ef10_sriov_set_vf_vlan,
6676 .sriov_set_vf_spoofchk = efx_ef10_sriov_set_vf_spoofchk,
6677 .sriov_get_vf_config = efx_ef10_sriov_get_vf_config,
4392dc69 6678 .sriov_set_vf_link_state = efx_ef10_sriov_set_vf_link_state,
7b8c7b54
SS		 6679 .vswitching_probe = efx_ef10_vswitching_probe_pf,
6680 .vswitching_restore = efx_ef10_vswitching_restore_pf,
6681 .vswitching_remove = efx_ef10_vswitching_remove_pf,
7fa8d547 6682#endif
0d5e0fbb 6683 .get_mac_address = efx_ef10_get_mac_address_pf,
910c8789 6684 .set_mac_address = efx_ef10_set_mac_address,
46d1efd8 6685 .tso_versions = efx_ef10_tso_versions,
8127d661 6686
08a7b29b 6687 .get_phys_port_id = efx_ef10_get_phys_port_id,
8127d661
BH		 6688 .revision = EFX_REV_HUNT_A0,
6689 .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH),
6690 .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE,
6691 .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST,
bd9a265d 6692 .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST,
8127d661
BH		 6693 .can_rx_scatter = true,
6694 .always_rx_scatter = true,
de1deff9 6695 .option_descriptors = true,
6f9f6ec2 6696 .min_interrupt_mode = EFX_INT_MODE_LEGACY,
8127d661
BH		 6697 .max_interrupt_mode = EFX_INT_MODE_MSIX,
6698 .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH,
100a9db5 6699 .offload_features = EF10_OFFLOAD_FEATURES,
8127d661
BH		 6700 .mcdi_max_ver = 2,
6701 .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS,
bd9a265d
JC		 6702 .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE |
6703 1 << HWTSTAMP_FILTER_ALL,
f74d1995 6704 .rx_hash_key_size = 40,
8127d661 6705};
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