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sfc: retrieve second word of datapath capabilities
[mirror_ubuntu-focal-kernel.git] / drivers / net / ethernet / sfc / ef10.c
CommitLineData
8127d661
BH		 1/****************************************************************************
2 * Driver for Solarflare network controllers and boards
3 * Copyright 2012-2013 Solarflare Communications Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published
7 * by the Free Software Foundation, incorporated herein by reference.
8 */
9
10#include "net_driver.h"
11#include "ef10_regs.h"
12#include "io.h"
13#include "mcdi.h"
14#include "mcdi_pcol.h"
15#include "nic.h"
16#include "workarounds.h"
74cd60a4 17#include "selftest.h"
7fa8d547 18#include "ef10_sriov.h"
8127d661
BH		 19#include <linux/in.h>
20#include <linux/jhash.h>
21#include <linux/wait.h>
22#include <linux/workqueue.h>
23
24/* Hardware control for EF10 architecture including 'Huntington'. */
25
26#define EFX_EF10_DRVGEN_EV 7
27enum {
28 EFX_EF10_TEST = 1,
29 EFX_EF10_REFILL,
30};
31
32/* The reserved RSS context value */
33#define EFX_EF10_RSS_CONTEXT_INVALID 0xffffffff
267c0157
JC		 34/* The maximum size of a shared RSS context */
35/* TODO: this should really be from the mcdi protocol export */
36#define EFX_EF10_MAX_SHARED_RSS_CONTEXT_SIZE 64UL
8127d661
BH		 37
38/* The filter table(s) are managed by firmware and we have write-only
39 * access. When removing filters we must identify them to the
40 * firmware by a 64-bit handle, but this is too wide for Linux kernel
41 * interfaces (32-bit for RX NFC, 16-bit for RFS). Also, we need to
42 * be able to tell in advance whether a requested insertion will
43 * replace an existing filter. Therefore we maintain a software hash
44 * table, which should be at least as large as the hardware hash
45 * table.
46 *
47 * Huntington has a single 8K filter table shared between all filter
48 * types and both ports.
49 */
50#define HUNT_FILTER_TBL_ROWS 8192
51
12fb0da4 52#define EFX_EF10_FILTER_ID_INVALID 0xffff
dc3273e0
AR		 53
54#define EFX_EF10_FILTER_DEV_UC_MAX 32
55#define EFX_EF10_FILTER_DEV_MC_MAX 256
56
34813fe2
AR		 57/* VLAN list entry */
58struct efx_ef10_vlan {
59 struct list_head list;
60 u16 vid;
61};
62
dc3273e0
AR		 63/* Per-VLAN filters information */
64struct efx_ef10_filter_vlan {
34813fe2 65 struct list_head list;
b3a3c03c 66 u16 vid;
dc3273e0
AR		 67 u16 uc[EFX_EF10_FILTER_DEV_UC_MAX];
68 u16 mc[EFX_EF10_FILTER_DEV_MC_MAX];
69 u16 ucdef;
70 u16 bcast;
71 u16 mcdef;
72};
73
822b96f8
DP		 74struct efx_ef10_dev_addr {
75 u8 addr[ETH_ALEN];
822b96f8
DP		 76};
77
8127d661 78struct efx_ef10_filter_table {
7ac0dd9d
AR		 79/* The MCDI match masks supported by this fw & hw, in order of priority */
80 u32 rx_match_mcdi_flags[
8127d661
BH		 81 MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM];
82 unsigned int rx_match_count;
83
84 struct {
85 unsigned long spec; /* pointer to spec plus flag bits */
b59e6ef8
BH		 86/* BUSY flag indicates that an update is in progress. AUTO_OLD is
87 * used to mark and sweep MAC filters for the device address lists.
8127d661
BH		 88 */
89#define EFX_EF10_FILTER_FLAG_BUSY 1UL
b59e6ef8 90#define EFX_EF10_FILTER_FLAG_AUTO_OLD 2UL
8127d661
BH		 91#define EFX_EF10_FILTER_FLAGS 3UL
92 u64 handle; /* firmware handle */
93 } *entry;
94 wait_queue_head_t waitq;
95/* Shadow of net_device address lists, guarded by mac_lock */
822b96f8
DP		 96 struct efx_ef10_dev_addr dev_uc_list[EFX_EF10_FILTER_DEV_UC_MAX];
97 struct efx_ef10_dev_addr dev_mc_list[EFX_EF10_FILTER_DEV_MC_MAX];
12fb0da4
EC		 98 int dev_uc_count;
99 int dev_mc_count;
afa4ce12
AR		 100 bool uc_promisc;
101 bool mc_promisc;
b071c3a2
AR		 102/* Whether in multicast promiscuous mode when last changed */
103 bool mc_promisc_last;
4a53ea8a 104 bool vlan_filter;
34813fe2 105 struct list_head vlan_list;
8127d661
BH		 106};
107
108/* An arbitrary search limit for the software hash table */
109#define EFX_EF10_FILTER_SEARCH_LIMIT 200
110
8127d661
BH		 111static void efx_ef10_rx_free_indir_table(struct efx_nic *efx);
112static void efx_ef10_filter_table_remove(struct efx_nic *efx);
34813fe2
AR		 113static int efx_ef10_filter_add_vlan(struct efx_nic *efx, u16 vid);
114static void efx_ef10_filter_del_vlan_internal(struct efx_nic *efx,
115 struct efx_ef10_filter_vlan *vlan);
116static void efx_ef10_filter_del_vlan(struct efx_nic *efx, u16 vid);
8127d661
BH		 117
118static int efx_ef10_get_warm_boot_count(struct efx_nic *efx)
119{
120 efx_dword_t reg;
121
122 efx_readd(efx, &reg, ER_DZ_BIU_MC_SFT_STATUS);
123 return EFX_DWORD_FIELD(reg, EFX_WORD_1) == 0xb007 ?
124 EFX_DWORD_FIELD(reg, EFX_WORD_0) : -EIO;
125}
126
127static unsigned int efx_ef10_mem_map_size(struct efx_nic *efx)
128{
02246a7f
SS		 129 int bar;
130
131 bar = efx->type->mem_bar;
132 return resource_size(&efx->pci_dev->resource[bar]);
8127d661
BH		 133}
134
7a186f47
DP		 135static bool efx_ef10_is_vf(struct efx_nic *efx)
136{
137 return efx->type->is_vf;
138}
139
1cd9ecbb
DP		 140static int efx_ef10_get_pf_index(struct efx_nic *efx)
141{
142 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN);
143 struct efx_ef10_nic_data *nic_data = efx->nic_data;
144 size_t outlen;
145 int rc;
146
147 rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf,
148 sizeof(outbuf), &outlen);
149 if (rc)
150 return rc;
151 if (outlen < sizeof(outbuf))
152 return -EIO;
153
154 nic_data->pf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_PF);
155 return 0;
156}
157
88a37de6
SS		 158#ifdef CONFIG_SFC_SRIOV
159static int efx_ef10_get_vf_index(struct efx_nic *efx)
160{
161 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN);
162 struct efx_ef10_nic_data *nic_data = efx->nic_data;
163 size_t outlen;
164 int rc;
165
166 rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf,
167 sizeof(outbuf), &outlen);
168 if (rc)
169 return rc;
170 if (outlen < sizeof(outbuf))
171 return -EIO;
172
173 nic_data->vf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_VF);
174 return 0;
175}
176#endif
177
e5a2538a 178static int efx_ef10_init_datapath_caps(struct efx_nic *efx)
8127d661 179{
ca889a05 180 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CAPABILITIES_V2_OUT_LEN);
8127d661
BH		 181 struct efx_ef10_nic_data *nic_data = efx->nic_data;
182 size_t outlen;
183 int rc;
184
185 BUILD_BUG_ON(MC_CMD_GET_CAPABILITIES_IN_LEN != 0);
186
187 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CAPABILITIES, NULL, 0,
188 outbuf, sizeof(outbuf), &outlen);
189 if (rc)
190 return rc;
ca889a05 191 if (outlen < MC_CMD_GET_CAPABILITIES_OUT_LEN) {
e5a2538a
BH		 192 netif_err(efx, drv, efx->net_dev,
193 "unable to read datapath firmware capabilities\n");
194 return -EIO;
195 }
196
197 nic_data->datapath_caps =
198 MCDI_DWORD(outbuf, GET_CAPABILITIES_OUT_FLAGS1);
8127d661 199
ca889a05
BK		 200 if (outlen >= MC_CMD_GET_CAPABILITIES_V2_OUT_LEN)
201 nic_data->datapath_caps2 = MCDI_DWORD(outbuf,
202 GET_CAPABILITIES_V2_OUT_FLAGS2);
203 else
204 nic_data->datapath_caps2 = 0;
205
8d9f9dd4
DP		 206 /* record the DPCPU firmware IDs to determine VEB vswitching support.
207 */
208 nic_data->rx_dpcpu_fw_id =
209 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID);
210 nic_data->tx_dpcpu_fw_id =
211 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID);
212
e5a2538a
BH		 213 if (!(nic_data->datapath_caps &
214 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN))) {
215 netif_err(efx, probe, efx->net_dev,
216 "current firmware does not support an RX prefix\n");
217 return -ENODEV;
8127d661
BH		 218 }
219
220 return 0;
221}
222
223static int efx_ef10_get_sysclk_freq(struct efx_nic *efx)
224{
225 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CLOCK_OUT_LEN);
226 int rc;
227
228 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CLOCK, NULL, 0,
229 outbuf, sizeof(outbuf), NULL);
230 if (rc)
231 return rc;
232 rc = MCDI_DWORD(outbuf, GET_CLOCK_OUT_SYS_FREQ);
233 return rc > 0 ? rc : -ERANGE;
234}
235
0d5e0fbb 236static int efx_ef10_get_mac_address_pf(struct efx_nic *efx, u8 *mac_address)
8127d661
BH		 237{
238 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_MAC_ADDRESSES_OUT_LEN);
239 size_t outlen;
240 int rc;
241
242 BUILD_BUG_ON(MC_CMD_GET_MAC_ADDRESSES_IN_LEN != 0);
243
244 rc = efx_mcdi_rpc(efx, MC_CMD_GET_MAC_ADDRESSES, NULL, 0,
245 outbuf, sizeof(outbuf), &outlen);
246 if (rc)
247 return rc;
248 if (outlen < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN)
249 return -EIO;
250
cd84ff4d
EC		 251 ether_addr_copy(mac_address,
252 MCDI_PTR(outbuf, GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE));
8127d661
BH		 253 return 0;
254}
255
0d5e0fbb
DP		 256static int efx_ef10_get_mac_address_vf(struct efx_nic *efx, u8 *mac_address)
257{
258 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN);
259 MCDI_DECLARE_BUF(outbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX);
260 size_t outlen;
261 int num_addrs, rc;
262
263 MCDI_SET_DWORD(inbuf, VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID,
264 EVB_PORT_ID_ASSIGNED);
265 rc = efx_mcdi_rpc(efx, MC_CMD_VPORT_GET_MAC_ADDRESSES, inbuf,
266 sizeof(inbuf), outbuf, sizeof(outbuf), &outlen);
267
268 if (rc)
269 return rc;
270 if (outlen < MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN)
271 return -EIO;
272
273 num_addrs = MCDI_DWORD(outbuf,
274 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT);
275
276 WARN_ON(num_addrs != 1);
277
278 ether_addr_copy(mac_address,
279 MCDI_PTR(outbuf, VPORT_GET_MAC_ADDRESSES_OUT_MACADDR));
280
281 return 0;
282}
283
0f5c0845
SS		 284static ssize_t efx_ef10_show_link_control_flag(struct device *dev,
285 struct device_attribute *attr,
286 char *buf)
287{
288 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
289
290 return sprintf(buf, "%d\n",
291 ((efx->mcdi->fn_flags) &
292 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL))
293 ? 1 : 0);
294}
295
296static ssize_t efx_ef10_show_primary_flag(struct device *dev,
297 struct device_attribute *attr,
298 char *buf)
299{
300 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
301
302 return sprintf(buf, "%d\n",
303 ((efx->mcdi->fn_flags) &
304 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY))
305 ? 1 : 0);
306}
307
34813fe2
AR		 308static struct efx_ef10_vlan *efx_ef10_find_vlan(struct efx_nic *efx, u16 vid)
309{
310 struct efx_ef10_nic_data *nic_data = efx->nic_data;
311 struct efx_ef10_vlan *vlan;
312
313 WARN_ON(!mutex_is_locked(&nic_data->vlan_lock));
314
315 list_for_each_entry(vlan, &nic_data->vlan_list, list) {
316 if (vlan->vid == vid)
317 return vlan;
318 }
319
320 return NULL;
321}
322
323static int efx_ef10_add_vlan(struct efx_nic *efx, u16 vid)
324{
325 struct efx_ef10_nic_data *nic_data = efx->nic_data;
326 struct efx_ef10_vlan *vlan;
327 int rc;
328
329 mutex_lock(&nic_data->vlan_lock);
330
331 vlan = efx_ef10_find_vlan(efx, vid);
332 if (vlan) {
4a53ea8a
AR		 333 /* We add VID 0 on init. 8021q adds it on module init
334 * for all interfaces with VLAN filtring feature.
335 */
336 if (vid == 0)
337 goto done_unlock;
34813fe2
AR		 338 netif_warn(efx, drv, efx->net_dev,
339 "VLAN %u already added\n", vid);
340 rc = -EALREADY;
341 goto fail_exist;
342 }
343
344 rc = -ENOMEM;
345 vlan = kzalloc(sizeof(*vlan), GFP_KERNEL);
346 if (!vlan)
347 goto fail_alloc;
348
349 vlan->vid = vid;
350
351 list_add_tail(&vlan->list, &nic_data->vlan_list);
352
353 if (efx->filter_state) {
354 mutex_lock(&efx->mac_lock);
355 down_write(&efx->filter_sem);
356 rc = efx_ef10_filter_add_vlan(efx, vlan->vid);
357 up_write(&efx->filter_sem);
358 mutex_unlock(&efx->mac_lock);
359 if (rc)
360 goto fail_filter_add_vlan;
361 }
362
4a53ea8a 363done_unlock:
34813fe2
AR		 364 mutex_unlock(&nic_data->vlan_lock);
365 return 0;
366
367fail_filter_add_vlan:
368 list_del(&vlan->list);
369 kfree(vlan);
370fail_alloc:
371fail_exist:
372 mutex_unlock(&nic_data->vlan_lock);
373 return rc;
374}
375
376static void efx_ef10_del_vlan_internal(struct efx_nic *efx,
377 struct efx_ef10_vlan *vlan)
378{
379 struct efx_ef10_nic_data *nic_data = efx->nic_data;
380
381 WARN_ON(!mutex_is_locked(&nic_data->vlan_lock));
382
383 if (efx->filter_state) {
384 down_write(&efx->filter_sem);
385 efx_ef10_filter_del_vlan(efx, vlan->vid);
386 up_write(&efx->filter_sem);
387 }
388
389 list_del(&vlan->list);
390 kfree(vlan);
391}
392
4a53ea8a
AR		 393static int efx_ef10_del_vlan(struct efx_nic *efx, u16 vid)
394{
395 struct efx_ef10_nic_data *nic_data = efx->nic_data;
396 struct efx_ef10_vlan *vlan;
397 int rc = 0;
398
399 /* 8021q removes VID 0 on module unload for all interfaces
400 * with VLAN filtering feature. We need to keep it to receive
401 * untagged traffic.
402 */
403 if (vid == 0)
404 return 0;
405
406 mutex_lock(&nic_data->vlan_lock);
407
408 vlan = efx_ef10_find_vlan(efx, vid);
409 if (!vlan) {
410 netif_err(efx, drv, efx->net_dev,
411 "VLAN %u to be deleted not found\n", vid);
412 rc = -ENOENT;
413 } else {
414 efx_ef10_del_vlan_internal(efx, vlan);
415 }
416
417 mutex_unlock(&nic_data->vlan_lock);
418
419 return rc;
420}
421
34813fe2
AR		 422static void efx_ef10_cleanup_vlans(struct efx_nic *efx)
423{
424 struct efx_ef10_nic_data *nic_data = efx->nic_data;
425 struct efx_ef10_vlan *vlan, *next_vlan;
426
427 mutex_lock(&nic_data->vlan_lock);
428 list_for_each_entry_safe(vlan, next_vlan, &nic_data->vlan_list, list)
429 efx_ef10_del_vlan_internal(efx, vlan);
430 mutex_unlock(&nic_data->vlan_lock);
431}
432
0f5c0845
SS		 433static DEVICE_ATTR(link_control_flag, 0444, efx_ef10_show_link_control_flag,
434 NULL);
435static DEVICE_ATTR(primary_flag, 0444, efx_ef10_show_primary_flag, NULL);
436
8127d661
BH		 437static int efx_ef10_probe(struct efx_nic *efx)
438{
439 struct efx_ef10_nic_data *nic_data;
8be41320 440 struct net_device *net_dev = efx->net_dev;
8127d661
BH		 441 int i, rc;
442
aa3930ee
BH		 443 /* We can have one VI for each 8K region. However, until we
444 * use TX option descriptors we need two TX queues per channel.
8127d661 445 */
b0fbdae1
SS		 446 efx->max_channels = min_t(unsigned int,
447 EFX_MAX_CHANNELS,
448 efx_ef10_mem_map_size(efx) /
449 (EFX_VI_PAGE_SIZE * EFX_TXQ_TYPES));
450 efx->max_tx_channels = efx->max_channels;
9fd3d3a4
EC		 451 if (WARN_ON(efx->max_channels == 0))
452 return -EIO;
8127d661
BH		 453
454 nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
455 if (!nic_data)
456 return -ENOMEM;
457 efx->nic_data = nic_data;
458
75aba2a5
EC		 459 /* we assume later that we can copy from this buffer in dwords */
460 BUILD_BUG_ON(MCDI_CTL_SDU_LEN_MAX_V2 % 4);
461
8127d661
BH		 462 rc = efx_nic_alloc_buffer(efx, &nic_data->mcdi_buf,
463 8 + MCDI_CTL_SDU_LEN_MAX_V2, GFP_KERNEL);
464 if (rc)
465 goto fail1;
466
467 /* Get the MC's warm boot count. In case it's rebooting right
468 * now, be prepared to retry.
469 */
470 i = 0;
471 for (;;) {
472 rc = efx_ef10_get_warm_boot_count(efx);
473 if (rc >= 0)
474 break;
475 if (++i == 5)
476 goto fail2;
477 ssleep(1);
478 }
479 nic_data->warm_boot_count = rc;
480
481 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
482
45b2449e
DP		 483 nic_data->vport_id = EVB_PORT_ID_ASSIGNED;
484
8127d661
BH		 485 /* In case we're recovering from a crash (kexec), we want to
486 * cancel any outstanding request by the previous user of this
487 * function. We send a special message using the least
488 * significant bits of the 'high' (doorbell) register.
489 */
490 _efx_writed(efx, cpu_to_le32(1), ER_DZ_MC_DB_HWRD);
491
492 rc = efx_mcdi_init(efx);
493 if (rc)
494 goto fail2;
495
496 /* Reset (most) configuration for this function */
497 rc = efx_mcdi_reset(efx, RESET_TYPE_ALL);
498 if (rc)
499 goto fail3;
500
501 /* Enable event logging */
502 rc = efx_mcdi_log_ctrl(efx, true, false, 0);
503 if (rc)
504 goto fail3;
505
0f5c0845
SS		 506 rc = device_create_file(&efx->pci_dev->dev,
507 &dev_attr_link_control_flag);
1cd9ecbb
DP		 508 if (rc)
509 goto fail3;
510
0f5c0845
SS		 511 rc = device_create_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
512 if (rc)
513 goto fail4;
514
515 rc = efx_ef10_get_pf_index(efx);
516 if (rc)
517 goto fail5;
518
e5a2538a 519 rc = efx_ef10_init_datapath_caps(efx);
8127d661 520 if (rc < 0)
0f5c0845 521 goto fail5;
8127d661
BH		 522
523 efx->rx_packet_len_offset =
524 ES_DZ_RX_PREFIX_PKTLEN_OFST - ES_DZ_RX_PREFIX_SIZE;
525
8127d661
BH		 526 rc = efx_mcdi_port_get_number(efx);
527 if (rc < 0)
0f5c0845 528 goto fail5;
8127d661 529 efx->port_num = rc;
8be41320 530 net_dev->dev_port = rc;
8127d661 531
0d5e0fbb 532 rc = efx->type->get_mac_address(efx, efx->net_dev->perm_addr);
8127d661 533 if (rc)
0f5c0845 534 goto fail5;
8127d661
BH		 535
536 rc = efx_ef10_get_sysclk_freq(efx);
537 if (rc < 0)
0f5c0845 538 goto fail5;
8127d661
BH		 539 efx->timer_quantum_ns = 1536000 / rc; /* 1536 cycles */
540
267d9d73
EC		 541 /* Check whether firmware supports bug 35388 workaround.
542 * First try to enable it, then if we get EPERM, just
543 * ask if it's already enabled
544 */
34ccfe6f 545 rc = efx_mcdi_set_workaround(efx, MC_CMD_WORKAROUND_BUG35388, true, NULL);
c9012e00 546 if (rc == 0) {
8127d661 547 nic_data->workaround_35388 = true;
c9012e00 548 } else if (rc == -EPERM) {
267d9d73
EC		 549 unsigned int enabled;
550
551 rc = efx_mcdi_get_workarounds(efx, NULL, &enabled);
552 if (rc)
553 goto fail3;
554 nic_data->workaround_35388 = enabled &
555 MC_CMD_GET_WORKAROUNDS_OUT_BUG35388;
c9012e00 556 } else if (rc != -ENOSYS && rc != -ENOENT) {
0f5c0845 557 goto fail5;
c9012e00 558 }
8127d661
BH		 559 netif_dbg(efx, probe, efx->net_dev,
560 "workaround for bug 35388 is %sabled\n",
561 nic_data->workaround_35388 ? "en" : "dis");
562
563 rc = efx_mcdi_mon_probe(efx);
267d9d73 564 if (rc && rc != -EPERM)
0f5c0845 565 goto fail5;
8127d661 566
9aecda95
BH		 567 efx_ptp_probe(efx, NULL);
568
1d051e00
SS		 569#ifdef CONFIG_SFC_SRIOV
570 if ((efx->pci_dev->physfn) && (!efx->pci_dev->is_physfn)) {
571 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn;
572 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
573
574 efx_pf->type->get_mac_address(efx_pf, nic_data->port_id);
575 } else
576#endif
577 ether_addr_copy(nic_data->port_id, efx->net_dev->perm_addr);
578
34813fe2
AR		 579 INIT_LIST_HEAD(&nic_data->vlan_list);
580 mutex_init(&nic_data->vlan_lock);
581
582 /* Add unspecified VID to support VLAN filtering being disabled */
583 rc = efx_ef10_add_vlan(efx, EFX_FILTER_VID_UNSPEC);
584 if (rc)
585 goto fail_add_vid_unspec;
586
4a53ea8a
AR		 587 /* If VLAN filtering is enabled, we need VID 0 to get untagged
588 * traffic. It is added automatically if 8021q module is loaded,
589 * but we can't rely on it since module may be not loaded.
590 */
591 rc = efx_ef10_add_vlan(efx, 0);
592 if (rc)
593 goto fail_add_vid_0;
594
8127d661
BH		 595 return 0;
596
4a53ea8a
AR		 597fail_add_vid_0:
598 efx_ef10_cleanup_vlans(efx);
34813fe2
AR		 599fail_add_vid_unspec:
600 mutex_destroy(&nic_data->vlan_lock);
601 efx_ptp_remove(efx);
602 efx_mcdi_mon_remove(efx);
0f5c0845
SS		 603fail5:
604 device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
605fail4:
606 device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag);
8127d661
BH		 607fail3:
608 efx_mcdi_fini(efx);
609fail2:
610 efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
611fail1:
612 kfree(nic_data);
613 efx->nic_data = NULL;
614 return rc;
615}
616
617static int efx_ef10_free_vis(struct efx_nic *efx)
618{
aa09a3da 619 MCDI_DECLARE_BUF_ERR(outbuf);
1e0b8120
EC		 620 size_t outlen;
621 int rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FREE_VIS, NULL, 0,
622 outbuf, sizeof(outbuf), &outlen);
8127d661
BH		 623
624 /* -EALREADY means nothing to free, so ignore */
625 if (rc == -EALREADY)
626 rc = 0;
1e0b8120
EC		 627 if (rc)
628 efx_mcdi_display_error(efx, MC_CMD_FREE_VIS, 0, outbuf, outlen,
629 rc);
8127d661
BH		 630 return rc;
631}
632
183233be
BH		 633#ifdef EFX_USE_PIO
634
635static void efx_ef10_free_piobufs(struct efx_nic *efx)
636{
637 struct efx_ef10_nic_data *nic_data = efx->nic_data;
638 MCDI_DECLARE_BUF(inbuf, MC_CMD_FREE_PIOBUF_IN_LEN);
639 unsigned int i;
640 int rc;
641
642 BUILD_BUG_ON(MC_CMD_FREE_PIOBUF_OUT_LEN != 0);
643
644 for (i = 0; i < nic_data->n_piobufs; i++) {
645 MCDI_SET_DWORD(inbuf, FREE_PIOBUF_IN_PIOBUF_HANDLE,
646 nic_data->piobuf_handle[i]);
647 rc = efx_mcdi_rpc(efx, MC_CMD_FREE_PIOBUF, inbuf, sizeof(inbuf),
648 NULL, 0, NULL);
649 WARN_ON(rc);
650 }
651
652 nic_data->n_piobufs = 0;
653}
654
655static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
656{
657 struct efx_ef10_nic_data *nic_data = efx->nic_data;
658 MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_PIOBUF_OUT_LEN);
659 unsigned int i;
660 size_t outlen;
661 int rc = 0;
662
663 BUILD_BUG_ON(MC_CMD_ALLOC_PIOBUF_IN_LEN != 0);
664
665 for (i = 0; i < n; i++) {
09a04204
BK		 666 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_ALLOC_PIOBUF, NULL, 0,
667 outbuf, sizeof(outbuf), &outlen);
668 if (rc) {
669 /* Don't display the MC error if we didn't have space
670 * for a VF.
671 */
672 if (!(efx_ef10_is_vf(efx) && rc == -ENOSPC))
673 efx_mcdi_display_error(efx, MC_CMD_ALLOC_PIOBUF,
674 0, outbuf, outlen, rc);
183233be 675 break;
09a04204 676 }
183233be
BH		 677 if (outlen < MC_CMD_ALLOC_PIOBUF_OUT_LEN) {
678 rc = -EIO;
679 break;
680 }
681 nic_data->piobuf_handle[i] =
682 MCDI_DWORD(outbuf, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE);
683 netif_dbg(efx, probe, efx->net_dev,
684 "allocated PIO buffer %u handle %x\n", i,
685 nic_data->piobuf_handle[i]);
686 }
687
688 nic_data->n_piobufs = i;
689 if (rc)
690 efx_ef10_free_piobufs(efx);
691 return rc;
692}
693
694static int efx_ef10_link_piobufs(struct efx_nic *efx)
695{
696 struct efx_ef10_nic_data *nic_data = efx->nic_data;
aa09a3da
JC		 697 _MCDI_DECLARE_BUF(inbuf,
698 max(MC_CMD_LINK_PIOBUF_IN_LEN,
699 MC_CMD_UNLINK_PIOBUF_IN_LEN));
183233be
BH		 700 struct efx_channel *channel;
701 struct efx_tx_queue *tx_queue;
702 unsigned int offset, index;
703 int rc;
704
705 BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_OUT_LEN != 0);
706 BUILD_BUG_ON(MC_CMD_UNLINK_PIOBUF_OUT_LEN != 0);
707
aa09a3da
JC		 708 memset(inbuf, 0, sizeof(inbuf));
709
183233be
BH		 710 /* Link a buffer to each VI in the write-combining mapping */
711 for (index = 0; index < nic_data->n_piobufs; ++index) {
712 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_PIOBUF_HANDLE,
713 nic_data->piobuf_handle[index]);
714 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_TXQ_INSTANCE,
715 nic_data->pio_write_vi_base + index);
716 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
717 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
718 NULL, 0, NULL);
719 if (rc) {
720 netif_err(efx, drv, efx->net_dev,
721 "failed to link VI %u to PIO buffer %u (%d)\n",
722 nic_data->pio_write_vi_base + index, index,
723 rc);
724 goto fail;
725 }
726 netif_dbg(efx, probe, efx->net_dev,
727 "linked VI %u to PIO buffer %u\n",
728 nic_data->pio_write_vi_base + index, index);
729 }
730
731 /* Link a buffer to each TX queue */
732 efx_for_each_channel(channel, efx) {
733 efx_for_each_channel_tx_queue(tx_queue, channel) {
734 /* We assign the PIO buffers to queues in
735 * reverse order to allow for the following
736 * special case.
737 */
738 offset = ((efx->tx_channel_offset + efx->n_tx_channels -
739 tx_queue->channel->channel - 1) *
740 efx_piobuf_size);
741 index = offset / ER_DZ_TX_PIOBUF_SIZE;
742 offset = offset % ER_DZ_TX_PIOBUF_SIZE;
743
744 /* When the host page size is 4K, the first
745 * host page in the WC mapping may be within
746 * the same VI page as the last TX queue. We
747 * can only link one buffer to each VI.
748 */
749 if (tx_queue->queue == nic_data->pio_write_vi_base) {
750 BUG_ON(index != 0);
751 rc = 0;
752 } else {
753 MCDI_SET_DWORD(inbuf,
754 LINK_PIOBUF_IN_PIOBUF_HANDLE,
755 nic_data->piobuf_handle[index]);
756 MCDI_SET_DWORD(inbuf,
757 LINK_PIOBUF_IN_TXQ_INSTANCE,
758 tx_queue->queue);
759 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
760 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
761 NULL, 0, NULL);
762 }
763
764 if (rc) {
765 /* This is non-fatal; the TX path just
766 * won't use PIO for this queue
767 */
768 netif_err(efx, drv, efx->net_dev,
769 "failed to link VI %u to PIO buffer %u (%d)\n",
770 tx_queue->queue, index, rc);
771 tx_queue->piobuf = NULL;
772 } else {
773 tx_queue->piobuf =
774 nic_data->pio_write_base +
775 index * EFX_VI_PAGE_SIZE + offset;
776 tx_queue->piobuf_offset = offset;
777 netif_dbg(efx, probe, efx->net_dev,
778 "linked VI %u to PIO buffer %u offset %x addr %p\n",
779 tx_queue->queue, index,
780 tx_queue->piobuf_offset,
781 tx_queue->piobuf);
782 }
783 }
784 }
785
786 return 0;
787
788fail:
789 while (index--) {
790 MCDI_SET_DWORD(inbuf, UNLINK_PIOBUF_IN_TXQ_INSTANCE,
791 nic_data->pio_write_vi_base + index);
792 efx_mcdi_rpc(efx, MC_CMD_UNLINK_PIOBUF,
793 inbuf, MC_CMD_UNLINK_PIOBUF_IN_LEN,
794 NULL, 0, NULL);
795 }
796 return rc;
797}
798
c0795bf6
EC		 799static void efx_ef10_forget_old_piobufs(struct efx_nic *efx)
800{
801 struct efx_channel *channel;
802 struct efx_tx_queue *tx_queue;
803
804 /* All our existing PIO buffers went away */
805 efx_for_each_channel(channel, efx)
806 efx_for_each_channel_tx_queue(tx_queue, channel)
807 tx_queue->piobuf = NULL;
808}
809
183233be
BH		 810#else /* !EFX_USE_PIO */
811
812static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
813{
814 return n == 0 ? 0 : -ENOBUFS;
815}
816
817static int efx_ef10_link_piobufs(struct efx_nic *efx)
818{
819 return 0;
820}
821
822static void efx_ef10_free_piobufs(struct efx_nic *efx)
823{
824}
825
c0795bf6
EC		 826static void efx_ef10_forget_old_piobufs(struct efx_nic *efx)
827{
828}
829
183233be
BH		 830#endif /* EFX_USE_PIO */
831
8127d661
BH		 832static void efx_ef10_remove(struct efx_nic *efx)
833{
834 struct efx_ef10_nic_data *nic_data = efx->nic_data;
835 int rc;
836
f1122a34
SS		 837#ifdef CONFIG_SFC_SRIOV
838 struct efx_ef10_nic_data *nic_data_pf;
839 struct pci_dev *pci_dev_pf;
840 struct efx_nic *efx_pf;
841 struct ef10_vf *vf;
842
843 if (efx->pci_dev->is_virtfn) {
844 pci_dev_pf = efx->pci_dev->physfn;
845 if (pci_dev_pf) {
846 efx_pf = pci_get_drvdata(pci_dev_pf);
847 nic_data_pf = efx_pf->nic_data;
848 vf = nic_data_pf->vf + nic_data->vf_index;
849 vf->efx = NULL;
850 } else
851 netif_info(efx, drv, efx->net_dev,
852 "Could not get the PF id from VF\n");
853 }
854#endif
855
34813fe2
AR		 856 efx_ef10_cleanup_vlans(efx);
857 mutex_destroy(&nic_data->vlan_lock);
858
9aecda95
BH		 859 efx_ptp_remove(efx);
860
8127d661
BH		 861 efx_mcdi_mon_remove(efx);
862
8127d661
BH		 863 efx_ef10_rx_free_indir_table(efx);
864
183233be
BH		 865 if (nic_data->wc_membase)
866 iounmap(nic_data->wc_membase);
867
8127d661
BH		 868 rc = efx_ef10_free_vis(efx);
869 WARN_ON(rc != 0);
870
183233be
BH		 871 if (!nic_data->must_restore_piobufs)
872 efx_ef10_free_piobufs(efx);
873
0f5c0845
SS		 874 device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
875 device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag);
876
8127d661
BH		 877 efx_mcdi_fini(efx);
878 efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
879 kfree(nic_data);
880}
881
88a37de6
SS		 882static int efx_ef10_probe_pf(struct efx_nic *efx)
883{
884 return efx_ef10_probe(efx);
885}
886
38d27f38
AR		 887int efx_ef10_vadaptor_query(struct efx_nic *efx, unsigned int port_id,
888 u32 *port_flags, u32 *vadaptor_flags,
889 unsigned int *vlan_tags)
890{
891 struct efx_ef10_nic_data *nic_data = efx->nic_data;
892 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_QUERY_IN_LEN);
893 MCDI_DECLARE_BUF(outbuf, MC_CMD_VADAPTOR_QUERY_OUT_LEN);
894 size_t outlen;
895 int rc;
896
897 if (nic_data->datapath_caps &
898 (1 << MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_LBN)) {
899 MCDI_SET_DWORD(inbuf, VADAPTOR_QUERY_IN_UPSTREAM_PORT_ID,
900 port_id);
901
902 rc = efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_QUERY, inbuf, sizeof(inbuf),
903 outbuf, sizeof(outbuf), &outlen);
904 if (rc)
905 return rc;
906
907 if (outlen < sizeof(outbuf)) {
908 rc = -EIO;
909 return rc;
910 }
911 }
912
913 if (port_flags)
914 *port_flags = MCDI_DWORD(outbuf, VADAPTOR_QUERY_OUT_PORT_FLAGS);
915 if (vadaptor_flags)
916 *vadaptor_flags =
917 MCDI_DWORD(outbuf, VADAPTOR_QUERY_OUT_VADAPTOR_FLAGS);
918 if (vlan_tags)
919 *vlan_tags =
920 MCDI_DWORD(outbuf,
921 VADAPTOR_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS);
922
923 return 0;
924}
925
7a186f47
DP		 926int efx_ef10_vadaptor_alloc(struct efx_nic *efx, unsigned int port_id)
927{
928 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_ALLOC_IN_LEN);
929
930 MCDI_SET_DWORD(inbuf, VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID, port_id);
931 return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_ALLOC, inbuf, sizeof(inbuf),
932 NULL, 0, NULL);
933}
934
935int efx_ef10_vadaptor_free(struct efx_nic *efx, unsigned int port_id)
936{
937 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_FREE_IN_LEN);
938
939 MCDI_SET_DWORD(inbuf, VADAPTOR_FREE_IN_UPSTREAM_PORT_ID, port_id);
940 return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_FREE, inbuf, sizeof(inbuf),
941 NULL, 0, NULL);
942}
943
944int efx_ef10_vport_add_mac(struct efx_nic *efx,
945 unsigned int port_id, u8 *mac)
946{
947 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_LEN);
948
949 MCDI_SET_DWORD(inbuf, VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID, port_id);
950 ether_addr_copy(MCDI_PTR(inbuf, VPORT_ADD_MAC_ADDRESS_IN_MACADDR), mac);
951
952 return efx_mcdi_rpc(efx, MC_CMD_VPORT_ADD_MAC_ADDRESS, inbuf,
953 sizeof(inbuf), NULL, 0, NULL);
954}
955
956int efx_ef10_vport_del_mac(struct efx_nic *efx,
957 unsigned int port_id, u8 *mac)
958{
959 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_LEN);
960
961 MCDI_SET_DWORD(inbuf, VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID, port_id);
962 ether_addr_copy(MCDI_PTR(inbuf, VPORT_DEL_MAC_ADDRESS_IN_MACADDR), mac);
963
964 return efx_mcdi_rpc(efx, MC_CMD_VPORT_DEL_MAC_ADDRESS, inbuf,
965 sizeof(inbuf), NULL, 0, NULL);
966}
967
88a37de6
SS		 968#ifdef CONFIG_SFC_SRIOV
969static int efx_ef10_probe_vf(struct efx_nic *efx)
970{
971 int rc;
6598dad2
DP		 972 struct pci_dev *pci_dev_pf;
973
974 /* If the parent PF has no VF data structure, it doesn't know about this
975 * VF so fail probe. The VF needs to be re-created. This can happen
976 * if the PF driver is unloaded while the VF is assigned to a guest.
977 */
978 pci_dev_pf = efx->pci_dev->physfn;
979 if (pci_dev_pf) {
980 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
981 struct efx_ef10_nic_data *nic_data_pf = efx_pf->nic_data;
982
983 if (!nic_data_pf->vf) {
984 netif_info(efx, drv, efx->net_dev,
985 "The VF cannot link to its parent PF; "
986 "please destroy and re-create the VF\n");
987 return -EBUSY;
988 }
989 }
88a37de6
SS		 990
991 rc = efx_ef10_probe(efx);
992 if (rc)
993 return rc;
994
995 rc = efx_ef10_get_vf_index(efx);
996 if (rc)
997 goto fail;
998
f1122a34
SS		 999 if (efx->pci_dev->is_virtfn) {
1000 if (efx->pci_dev->physfn) {
1001 struct efx_nic *efx_pf =
1002 pci_get_drvdata(efx->pci_dev->physfn);
1003 struct efx_ef10_nic_data *nic_data_p = efx_pf->nic_data;
1004 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1005
1006 nic_data_p->vf[nic_data->vf_index].efx = efx;
6598dad2
DP		 1007 nic_data_p->vf[nic_data->vf_index].pci_dev =
1008 efx->pci_dev;
f1122a34
SS		 1009 } else
1010 netif_info(efx, drv, efx->net_dev,
1011 "Could not get the PF id from VF\n");
1012 }
1013
88a37de6
SS		 1014 return 0;
1015
1016fail:
1017 efx_ef10_remove(efx);
1018 return rc;
1019}
1020#else
1021static int efx_ef10_probe_vf(struct efx_nic *efx __attribute__ ((unused)))
1022{
1023 return 0;
1024}
1025#endif
1026
8127d661
BH		 1027static int efx_ef10_alloc_vis(struct efx_nic *efx,
1028 unsigned int min_vis, unsigned int max_vis)
1029{
1030 MCDI_DECLARE_BUF(inbuf, MC_CMD_ALLOC_VIS_IN_LEN);
1031 MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_VIS_OUT_LEN);
1032 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1033 size_t outlen;
1034 int rc;
1035
1036 MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MIN_VI_COUNT, min_vis);
1037 MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MAX_VI_COUNT, max_vis);
1038 rc = efx_mcdi_rpc(efx, MC_CMD_ALLOC_VIS, inbuf, sizeof(inbuf),
1039 outbuf, sizeof(outbuf), &outlen);
1040 if (rc != 0)
1041 return rc;
1042
1043 if (outlen < MC_CMD_ALLOC_VIS_OUT_LEN)
1044 return -EIO;
1045
1046 netif_dbg(efx, drv, efx->net_dev, "base VI is A0x%03x\n",
1047 MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE));
1048
1049 nic_data->vi_base = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE);
1050 nic_data->n_allocated_vis = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_COUNT);
1051 return 0;
1052}
1053
183233be
BH		 1054/* Note that the failure path of this function does not free
1055 * resources, as this will be done by efx_ef10_remove().
1056 */
8127d661
BH		 1057static int efx_ef10_dimension_resources(struct efx_nic *efx)
1058{
183233be
BH		 1059 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1060 unsigned int uc_mem_map_size, wc_mem_map_size;
b0fbdae1
SS		 1061 unsigned int min_vis = max(EFX_TXQ_TYPES,
1062 efx_separate_tx_channels ? 2 : 1);
1063 unsigned int channel_vis, pio_write_vi_base, max_vis;
183233be
BH		 1064 void __iomem *membase;
1065 int rc;
1066
b0fbdae1 1067 channel_vis = max(efx->n_channels, efx->n_tx_channels * EFX_TXQ_TYPES);
8127d661 1068
183233be
BH		 1069#ifdef EFX_USE_PIO
1070 /* Try to allocate PIO buffers if wanted and if the full
1071 * number of PIO buffers would be sufficient to allocate one
1072 * copy-buffer per TX channel. Failure is non-fatal, as there
1073 * are only a small number of PIO buffers shared between all
1074 * functions of the controller.
1075 */
1076 if (efx_piobuf_size != 0 &&
1077 ER_DZ_TX_PIOBUF_SIZE / efx_piobuf_size * EF10_TX_PIOBUF_COUNT >=
1078 efx->n_tx_channels) {
1079 unsigned int n_piobufs =
1080 DIV_ROUND_UP(efx->n_tx_channels,
1081 ER_DZ_TX_PIOBUF_SIZE / efx_piobuf_size);
1082
1083 rc = efx_ef10_alloc_piobufs(efx, n_piobufs);
1084 if (rc)
1085 netif_err(efx, probe, efx->net_dev,
1086 "failed to allocate PIO buffers (%d)\n", rc);
1087 else
1088 netif_dbg(efx, probe, efx->net_dev,
1089 "allocated %u PIO buffers\n", n_piobufs);
1090 }
1091#else
1092 nic_data->n_piobufs = 0;
1093#endif
1094
1095 /* PIO buffers should be mapped with write-combining enabled,
1096 * and we want to make single UC and WC mappings rather than
1097 * several of each (in fact that's the only option if host
1098 * page size is >4K). So we may allocate some extra VIs just
1099 * for writing PIO buffers through.
52ad762b 1100 *
b0fbdae1 1101 * The UC mapping contains (channel_vis - 1) complete VIs and the
52ad762b
DP		 1102 * first half of the next VI. Then the WC mapping begins with
1103 * the second half of this last VI.
183233be 1104 */
b0fbdae1 1105 uc_mem_map_size = PAGE_ALIGN((channel_vis - 1) * EFX_VI_PAGE_SIZE +
183233be
BH		 1106 ER_DZ_TX_PIOBUF);
1107 if (nic_data->n_piobufs) {
52ad762b
DP		 1108 /* pio_write_vi_base rounds down to give the number of complete
1109 * VIs inside the UC mapping.
1110 */
183233be
BH		 1111 pio_write_vi_base = uc_mem_map_size / EFX_VI_PAGE_SIZE;
1112 wc_mem_map_size = (PAGE_ALIGN((pio_write_vi_base +
1113 nic_data->n_piobufs) *
1114 EFX_VI_PAGE_SIZE) -
1115 uc_mem_map_size);
1116 max_vis = pio_write_vi_base + nic_data->n_piobufs;
1117 } else {
1118 pio_write_vi_base = 0;
1119 wc_mem_map_size = 0;
b0fbdae1 1120 max_vis = channel_vis;
183233be
BH		 1121 }
1122
1123 /* In case the last attached driver failed to free VIs, do it now */
1124 rc = efx_ef10_free_vis(efx);
1125 if (rc != 0)
1126 return rc;
1127
1128 rc = efx_ef10_alloc_vis(efx, min_vis, max_vis);
1129 if (rc != 0)
1130 return rc;
1131
b0fbdae1
SS		 1132 if (nic_data->n_allocated_vis < channel_vis) {
1133 netif_info(efx, drv, efx->net_dev,
1134 "Could not allocate enough VIs to satisfy RSS"
1135 " requirements. Performance may not be optimal.\n");
1136 /* We didn't get the VIs to populate our channels.
1137 * We could keep what we got but then we'd have more
1138 * interrupts than we need.
1139 * Instead calculate new max_channels and restart
1140 */
1141 efx->max_channels = nic_data->n_allocated_vis;
1142 efx->max_tx_channels =
1143 nic_data->n_allocated_vis / EFX_TXQ_TYPES;
1144
1145 efx_ef10_free_vis(efx);
1146 return -EAGAIN;
1147 }
1148
183233be
BH		 1149 /* If we didn't get enough VIs to map all the PIO buffers, free the
1150 * PIO buffers
1151 */
1152 if (nic_data->n_piobufs &&
1153 nic_data->n_allocated_vis <
1154 pio_write_vi_base + nic_data->n_piobufs) {
1155 netif_dbg(efx, probe, efx->net_dev,
1156 "%u VIs are not sufficient to map %u PIO buffers\n",
1157 nic_data->n_allocated_vis, nic_data->n_piobufs);
1158 efx_ef10_free_piobufs(efx);
1159 }
1160
1161 /* Shrink the original UC mapping of the memory BAR */
1162 membase = ioremap_nocache(efx->membase_phys, uc_mem_map_size);
1163 if (!membase) {
1164 netif_err(efx, probe, efx->net_dev,
1165 "could not shrink memory BAR to %x\n",
1166 uc_mem_map_size);
1167 return -ENOMEM;
1168 }
1169 iounmap(efx->membase);
1170 efx->membase = membase;
1171
1172 /* Set up the WC mapping if needed */
1173 if (wc_mem_map_size) {
1174 nic_data->wc_membase = ioremap_wc(efx->membase_phys +
1175 uc_mem_map_size,
1176 wc_mem_map_size);
1177 if (!nic_data->wc_membase) {
1178 netif_err(efx, probe, efx->net_dev,
1179 "could not allocate WC mapping of size %x\n",
1180 wc_mem_map_size);
1181 return -ENOMEM;
1182 }
1183 nic_data->pio_write_vi_base = pio_write_vi_base;
1184 nic_data->pio_write_base =
1185 nic_data->wc_membase +
1186 (pio_write_vi_base * EFX_VI_PAGE_SIZE + ER_DZ_TX_PIOBUF -
1187 uc_mem_map_size);
1188
1189 rc = efx_ef10_link_piobufs(efx);
1190 if (rc)
1191 efx_ef10_free_piobufs(efx);
1192 }
1193
1194 netif_dbg(efx, probe, efx->net_dev,
1195 "memory BAR at %pa (virtual %p+%x UC, %p+%x WC)\n",
1196 &efx->membase_phys, efx->membase, uc_mem_map_size,
1197 nic_data->wc_membase, wc_mem_map_size);
1198
1199 return 0;
8127d661
BH		 1200}
1201
1202static int efx_ef10_init_nic(struct efx_nic *efx)
1203{
1204 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1205 int rc;
1206
a915ccc9
BH		 1207 if (nic_data->must_check_datapath_caps) {
1208 rc = efx_ef10_init_datapath_caps(efx);
1209 if (rc)
1210 return rc;
1211 nic_data->must_check_datapath_caps = false;
1212 }
1213
8127d661
BH		 1214 if (nic_data->must_realloc_vis) {
1215 /* We cannot let the number of VIs change now */
1216 rc = efx_ef10_alloc_vis(efx, nic_data->n_allocated_vis,
1217 nic_data->n_allocated_vis);
1218 if (rc)
1219 return rc;
1220 nic_data->must_realloc_vis = false;
1221 }
1222
183233be
BH		 1223 if (nic_data->must_restore_piobufs && nic_data->n_piobufs) {
1224 rc = efx_ef10_alloc_piobufs(efx, nic_data->n_piobufs);
1225 if (rc == 0) {
1226 rc = efx_ef10_link_piobufs(efx);
1227 if (rc)
1228 efx_ef10_free_piobufs(efx);
1229 }
1230
1231 /* Log an error on failure, but this is non-fatal */
1232 if (rc)
1233 netif_err(efx, drv, efx->net_dev,
1234 "failed to restore PIO buffers (%d)\n", rc);
1235 nic_data->must_restore_piobufs = false;
1236 }
1237
267c0157
JC		 1238 /* don't fail init if RSS setup doesn't work */
1239 efx->type->rx_push_rss_config(efx, false, efx->rx_indir_table);
1240
8127d661
BH		 1241 return 0;
1242}
1243
3e336261
JC		 1244static void efx_ef10_reset_mc_allocations(struct efx_nic *efx)
1245{
1246 struct efx_ef10_nic_data *nic_data = efx->nic_data;
774ad031
DP		 1247#ifdef CONFIG_SFC_SRIOV
1248 unsigned int i;
1249#endif
3e336261
JC		 1250
1251 /* All our allocations have been reset */
1252 nic_data->must_realloc_vis = true;
1253 nic_data->must_restore_filters = true;
1254 nic_data->must_restore_piobufs = true;
c0795bf6 1255 efx_ef10_forget_old_piobufs(efx);
3e336261 1256 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
774ad031
DP		 1257
1258 /* Driver-created vswitches and vports must be re-created */
1259 nic_data->must_probe_vswitching = true;
1260 nic_data->vport_id = EVB_PORT_ID_ASSIGNED;
1261#ifdef CONFIG_SFC_SRIOV
1262 if (nic_data->vf)
1263 for (i = 0; i < efx->vf_count; i++)
1264 nic_data->vf[i].vport_id = 0;
1265#endif
3e336261
JC		 1266}
1267
087e9025
JC		 1268static enum reset_type efx_ef10_map_reset_reason(enum reset_type reason)
1269{
1270 if (reason == RESET_TYPE_MC_FAILURE)
1271 return RESET_TYPE_DATAPATH;
1272
1273 return efx_mcdi_map_reset_reason(reason);
1274}
1275
8127d661
BH		 1276static int efx_ef10_map_reset_flags(u32 *flags)
1277{
1278 enum {
1279 EF10_RESET_PORT = ((ETH_RESET_MAC | ETH_RESET_PHY) <<
1280 ETH_RESET_SHARED_SHIFT),
1281 EF10_RESET_MC = ((ETH_RESET_DMA | ETH_RESET_FILTER |
1282 ETH_RESET_OFFLOAD | ETH_RESET_MAC |
1283 ETH_RESET_PHY | ETH_RESET_MGMT) <<
1284 ETH_RESET_SHARED_SHIFT)
1285 };
1286
1287 /* We assume for now that our PCI function is permitted to
1288 * reset everything.
1289 */
1290
1291 if ((*flags & EF10_RESET_MC) == EF10_RESET_MC) {
1292 *flags &= ~EF10_RESET_MC;
1293 return RESET_TYPE_WORLD;
1294 }
1295
1296 if ((*flags & EF10_RESET_PORT) == EF10_RESET_PORT) {
1297 *flags &= ~EF10_RESET_PORT;
1298 return RESET_TYPE_ALL;
1299 }
1300
1301 /* no invisible reset implemented */
1302
1303 return -EINVAL;
1304}
1305
3e336261
JC		 1306static int efx_ef10_reset(struct efx_nic *efx, enum reset_type reset_type)
1307{
1308 int rc = efx_mcdi_reset(efx, reset_type);
1309
27324820
DP		 1310 /* Unprivileged functions return -EPERM, but need to return success
1311 * here so that the datapath is brought back up.
1312 */
1313 if (reset_type == RESET_TYPE_WORLD && rc == -EPERM)
1314 rc = 0;
1315
3e336261
JC		 1316 /* If it was a port reset, trigger reallocation of MC resources.
1317 * Note that on an MC reset nothing needs to be done now because we'll
1318 * detect the MC reset later and handle it then.
e283546c
EC		 1319 * For an FLR, we never get an MC reset event, but the MC has reset all
1320 * resources assigned to us, so we have to trigger reallocation now.
3e336261 1321 */
e283546c
EC		 1322 if ((reset_type == RESET_TYPE_ALL ||
1323 reset_type == RESET_TYPE_MCDI_TIMEOUT) && !rc)
3e336261
JC		 1324 efx_ef10_reset_mc_allocations(efx);
1325 return rc;
1326}
1327
8127d661
BH		 1328#define EF10_DMA_STAT(ext_name, mcdi_name) \
1329 [EF10_STAT_ ## ext_name] = \
1330 { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
1331#define EF10_DMA_INVIS_STAT(int_name, mcdi_name) \
1332 [EF10_STAT_ ## int_name] = \
1333 { NULL, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
1334#define EF10_OTHER_STAT(ext_name) \
1335 [EF10_STAT_ ## ext_name] = { #ext_name, 0, 0 }
e4d112e4
EC		 1336#define GENERIC_SW_STAT(ext_name) \
1337 [GENERIC_STAT_ ## ext_name] = { #ext_name, 0, 0 }
8127d661
BH		 1338
1339static const struct efx_hw_stat_desc efx_ef10_stat_desc[EF10_STAT_COUNT] = {
e80ca013
DP		 1340 EF10_DMA_STAT(port_tx_bytes, TX_BYTES),
1341 EF10_DMA_STAT(port_tx_packets, TX_PKTS),
1342 EF10_DMA_STAT(port_tx_pause, TX_PAUSE_PKTS),
1343 EF10_DMA_STAT(port_tx_control, TX_CONTROL_PKTS),
1344 EF10_DMA_STAT(port_tx_unicast, TX_UNICAST_PKTS),
1345 EF10_DMA_STAT(port_tx_multicast, TX_MULTICAST_PKTS),
1346 EF10_DMA_STAT(port_tx_broadcast, TX_BROADCAST_PKTS),
1347 EF10_DMA_STAT(port_tx_lt64, TX_LT64_PKTS),
1348 EF10_DMA_STAT(port_tx_64, TX_64_PKTS),
1349 EF10_DMA_STAT(port_tx_65_to_127, TX_65_TO_127_PKTS),
1350 EF10_DMA_STAT(port_tx_128_to_255, TX_128_TO_255_PKTS),
1351 EF10_DMA_STAT(port_tx_256_to_511, TX_256_TO_511_PKTS),
1352 EF10_DMA_STAT(port_tx_512_to_1023, TX_512_TO_1023_PKTS),
1353 EF10_DMA_STAT(port_tx_1024_to_15xx, TX_1024_TO_15XX_PKTS),
1354 EF10_DMA_STAT(port_tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS),
1355 EF10_DMA_STAT(port_rx_bytes, RX_BYTES),
1356 EF10_DMA_INVIS_STAT(port_rx_bytes_minus_good_bytes, RX_BAD_BYTES),
1357 EF10_OTHER_STAT(port_rx_good_bytes),
1358 EF10_OTHER_STAT(port_rx_bad_bytes),
1359 EF10_DMA_STAT(port_rx_packets, RX_PKTS),
1360 EF10_DMA_STAT(port_rx_good, RX_GOOD_PKTS),
1361 EF10_DMA_STAT(port_rx_bad, RX_BAD_FCS_PKTS),
1362 EF10_DMA_STAT(port_rx_pause, RX_PAUSE_PKTS),
1363 EF10_DMA_STAT(port_rx_control, RX_CONTROL_PKTS),
1364 EF10_DMA_STAT(port_rx_unicast, RX_UNICAST_PKTS),
1365 EF10_DMA_STAT(port_rx_multicast, RX_MULTICAST_PKTS),
1366 EF10_DMA_STAT(port_rx_broadcast, RX_BROADCAST_PKTS),
1367 EF10_DMA_STAT(port_rx_lt64, RX_UNDERSIZE_PKTS),
1368 EF10_DMA_STAT(port_rx_64, RX_64_PKTS),
1369 EF10_DMA_STAT(port_rx_65_to_127, RX_65_TO_127_PKTS),
1370 EF10_DMA_STAT(port_rx_128_to_255, RX_128_TO_255_PKTS),
1371 EF10_DMA_STAT(port_rx_256_to_511, RX_256_TO_511_PKTS),
1372 EF10_DMA_STAT(port_rx_512_to_1023, RX_512_TO_1023_PKTS),
1373 EF10_DMA_STAT(port_rx_1024_to_15xx, RX_1024_TO_15XX_PKTS),
1374 EF10_DMA_STAT(port_rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS),
1375 EF10_DMA_STAT(port_rx_gtjumbo, RX_GTJUMBO_PKTS),
1376 EF10_DMA_STAT(port_rx_bad_gtjumbo, RX_JABBER_PKTS),
1377 EF10_DMA_STAT(port_rx_overflow, RX_OVERFLOW_PKTS),
1378 EF10_DMA_STAT(port_rx_align_error, RX_ALIGN_ERROR_PKTS),
1379 EF10_DMA_STAT(port_rx_length_error, RX_LENGTH_ERROR_PKTS),
1380 EF10_DMA_STAT(port_rx_nodesc_drops, RX_NODESC_DROPS),
e4d112e4
EC		 1381 GENERIC_SW_STAT(rx_nodesc_trunc),
1382 GENERIC_SW_STAT(rx_noskb_drops),
e80ca013
DP		 1383 EF10_DMA_STAT(port_rx_pm_trunc_bb_overflow, PM_TRUNC_BB_OVERFLOW),
1384 EF10_DMA_STAT(port_rx_pm_discard_bb_overflow, PM_DISCARD_BB_OVERFLOW),
1385 EF10_DMA_STAT(port_rx_pm_trunc_vfifo_full, PM_TRUNC_VFIFO_FULL),
1386 EF10_DMA_STAT(port_rx_pm_discard_vfifo_full, PM_DISCARD_VFIFO_FULL),
1387 EF10_DMA_STAT(port_rx_pm_trunc_qbb, PM_TRUNC_QBB),
1388 EF10_DMA_STAT(port_rx_pm_discard_qbb, PM_DISCARD_QBB),
1389 EF10_DMA_STAT(port_rx_pm_discard_mapping, PM_DISCARD_MAPPING),
1390 EF10_DMA_STAT(port_rx_dp_q_disabled_packets, RXDP_Q_DISABLED_PKTS),
1391 EF10_DMA_STAT(port_rx_dp_di_dropped_packets, RXDP_DI_DROPPED_PKTS),
1392 EF10_DMA_STAT(port_rx_dp_streaming_packets, RXDP_STREAMING_PKTS),
1393 EF10_DMA_STAT(port_rx_dp_hlb_fetch, RXDP_HLB_FETCH_CONDITIONS),
1394 EF10_DMA_STAT(port_rx_dp_hlb_wait, RXDP_HLB_WAIT_CONDITIONS),
3c36a2ad
DP		 1395 EF10_DMA_STAT(rx_unicast, VADAPTER_RX_UNICAST_PACKETS),
1396 EF10_DMA_STAT(rx_unicast_bytes, VADAPTER_RX_UNICAST_BYTES),
1397 EF10_DMA_STAT(rx_multicast, VADAPTER_RX_MULTICAST_PACKETS),
1398 EF10_DMA_STAT(rx_multicast_bytes, VADAPTER_RX_MULTICAST_BYTES),
1399 EF10_DMA_STAT(rx_broadcast, VADAPTER_RX_BROADCAST_PACKETS),
1400 EF10_DMA_STAT(rx_broadcast_bytes, VADAPTER_RX_BROADCAST_BYTES),
1401 EF10_DMA_STAT(rx_bad, VADAPTER_RX_BAD_PACKETS),
1402 EF10_DMA_STAT(rx_bad_bytes, VADAPTER_RX_BAD_BYTES),
1403 EF10_DMA_STAT(rx_overflow, VADAPTER_RX_OVERFLOW),
1404 EF10_DMA_STAT(tx_unicast, VADAPTER_TX_UNICAST_PACKETS),
1405 EF10_DMA_STAT(tx_unicast_bytes, VADAPTER_TX_UNICAST_BYTES),
1406 EF10_DMA_STAT(tx_multicast, VADAPTER_TX_MULTICAST_PACKETS),
1407 EF10_DMA_STAT(tx_multicast_bytes, VADAPTER_TX_MULTICAST_BYTES),
1408 EF10_DMA_STAT(tx_broadcast, VADAPTER_TX_BROADCAST_PACKETS),
1409 EF10_DMA_STAT(tx_broadcast_bytes, VADAPTER_TX_BROADCAST_BYTES),
1410 EF10_DMA_STAT(tx_bad, VADAPTER_TX_BAD_PACKETS),
1411 EF10_DMA_STAT(tx_bad_bytes, VADAPTER_TX_BAD_BYTES),
1412 EF10_DMA_STAT(tx_overflow, VADAPTER_TX_OVERFLOW),
8127d661
BH		 1413};
1414
e80ca013
DP		 1415#define HUNT_COMMON_STAT_MASK ((1ULL << EF10_STAT_port_tx_bytes) | \
1416 (1ULL << EF10_STAT_port_tx_packets) | \
1417 (1ULL << EF10_STAT_port_tx_pause) | \
1418 (1ULL << EF10_STAT_port_tx_unicast) | \
1419 (1ULL << EF10_STAT_port_tx_multicast) | \
1420 (1ULL << EF10_STAT_port_tx_broadcast) | \
1421 (1ULL << EF10_STAT_port_rx_bytes) | \
1422 (1ULL << \
1423 EF10_STAT_port_rx_bytes_minus_good_bytes) | \
1424 (1ULL << EF10_STAT_port_rx_good_bytes) | \
1425 (1ULL << EF10_STAT_port_rx_bad_bytes) | \
1426 (1ULL << EF10_STAT_port_rx_packets) | \
1427 (1ULL << EF10_STAT_port_rx_good) | \
1428 (1ULL << EF10_STAT_port_rx_bad) | \
1429 (1ULL << EF10_STAT_port_rx_pause) | \
1430 (1ULL << EF10_STAT_port_rx_control) | \
1431 (1ULL << EF10_STAT_port_rx_unicast) | \
1432 (1ULL << EF10_STAT_port_rx_multicast) | \
1433 (1ULL << EF10_STAT_port_rx_broadcast) | \
1434 (1ULL << EF10_STAT_port_rx_lt64) | \
1435 (1ULL << EF10_STAT_port_rx_64) | \
1436 (1ULL << EF10_STAT_port_rx_65_to_127) | \
1437 (1ULL << EF10_STAT_port_rx_128_to_255) | \
1438 (1ULL << EF10_STAT_port_rx_256_to_511) | \
1439 (1ULL << EF10_STAT_port_rx_512_to_1023) |\
1440 (1ULL << EF10_STAT_port_rx_1024_to_15xx) |\
1441 (1ULL << EF10_STAT_port_rx_15xx_to_jumbo) |\
1442 (1ULL << EF10_STAT_port_rx_gtjumbo) | \
1443 (1ULL << EF10_STAT_port_rx_bad_gtjumbo) |\
1444 (1ULL << EF10_STAT_port_rx_overflow) | \
1445 (1ULL << EF10_STAT_port_rx_nodesc_drops) |\
e4d112e4
EC		 1446 (1ULL << GENERIC_STAT_rx_nodesc_trunc) | \
1447 (1ULL << GENERIC_STAT_rx_noskb_drops))
8127d661
BH		 1448
1449/* These statistics are only provided by the 10G MAC. For a 10G/40G
1450 * switchable port we do not expose these because they might not
1451 * include all the packets they should.
1452 */
e80ca013
DP		 1453#define HUNT_10G_ONLY_STAT_MASK ((1ULL << EF10_STAT_port_tx_control) | \
1454 (1ULL << EF10_STAT_port_tx_lt64) | \
1455 (1ULL << EF10_STAT_port_tx_64) | \
1456 (1ULL << EF10_STAT_port_tx_65_to_127) |\
1457 (1ULL << EF10_STAT_port_tx_128_to_255) |\
1458 (1ULL << EF10_STAT_port_tx_256_to_511) |\
1459 (1ULL << EF10_STAT_port_tx_512_to_1023) |\
1460 (1ULL << EF10_STAT_port_tx_1024_to_15xx) |\
1461 (1ULL << EF10_STAT_port_tx_15xx_to_jumbo))
8127d661
BH		 1462
1463/* These statistics are only provided by the 40G MAC. For a 10G/40G
1464 * switchable port we do expose these because the errors will otherwise
1465 * be silent.
1466 */
e80ca013
DP		 1467#define HUNT_40G_EXTRA_STAT_MASK ((1ULL << EF10_STAT_port_rx_align_error) |\
1468 (1ULL << EF10_STAT_port_rx_length_error))
8127d661 1469
568d7a00
EC		 1470/* These statistics are only provided if the firmware supports the
1471 * capability PM_AND_RXDP_COUNTERS.
1472 */
1473#define HUNT_PM_AND_RXDP_STAT_MASK ( \
e80ca013
DP		 1474 (1ULL << EF10_STAT_port_rx_pm_trunc_bb_overflow) | \
1475 (1ULL << EF10_STAT_port_rx_pm_discard_bb_overflow) | \
1476 (1ULL << EF10_STAT_port_rx_pm_trunc_vfifo_full) | \
1477 (1ULL << EF10_STAT_port_rx_pm_discard_vfifo_full) | \
1478 (1ULL << EF10_STAT_port_rx_pm_trunc_qbb) | \
1479 (1ULL << EF10_STAT_port_rx_pm_discard_qbb) | \
1480 (1ULL << EF10_STAT_port_rx_pm_discard_mapping) | \
1481 (1ULL << EF10_STAT_port_rx_dp_q_disabled_packets) | \
1482 (1ULL << EF10_STAT_port_rx_dp_di_dropped_packets) | \
1483 (1ULL << EF10_STAT_port_rx_dp_streaming_packets) | \
1484 (1ULL << EF10_STAT_port_rx_dp_hlb_fetch) | \
1485 (1ULL << EF10_STAT_port_rx_dp_hlb_wait))
568d7a00 1486
4bae913b 1487static u64 efx_ef10_raw_stat_mask(struct efx_nic *efx)
8127d661 1488{
4bae913b 1489 u64 raw_mask = HUNT_COMMON_STAT_MASK;
8127d661 1490 u32 port_caps = efx_mcdi_phy_get_caps(efx);
568d7a00 1491 struct efx_ef10_nic_data *nic_data = efx->nic_data;
8127d661 1492
3c36a2ad
DP		 1493 if (!(efx->mcdi->fn_flags &
1494 1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL))
1495 return 0;
1496
8127d661 1497 if (port_caps & (1 << MC_CMD_PHY_CAP_40000FDX_LBN))
4bae913b 1498 raw_mask |= HUNT_40G_EXTRA_STAT_MASK;
8127d661 1499 else
4bae913b 1500 raw_mask |= HUNT_10G_ONLY_STAT_MASK;
568d7a00
EC		 1501
1502 if (nic_data->datapath_caps &
1503 (1 << MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN))
1504 raw_mask |= HUNT_PM_AND_RXDP_STAT_MASK;
1505
4bae913b
EC		 1506 return raw_mask;
1507}
1508
1509static void efx_ef10_get_stat_mask(struct efx_nic *efx, unsigned long *mask)
1510{
d94619cd 1511 struct efx_ef10_nic_data *nic_data = efx->nic_data;
3c36a2ad
DP		 1512 u64 raw_mask[2];
1513
1514 raw_mask[0] = efx_ef10_raw_stat_mask(efx);
1515
d94619cd
DP		 1516 /* Only show vadaptor stats when EVB capability is present */
1517 if (nic_data->datapath_caps &
1518 (1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN)) {
1519 raw_mask[0] |= ~((1ULL << EF10_STAT_rx_unicast) - 1);
1520 raw_mask[1] = (1ULL << (EF10_STAT_COUNT - 63)) - 1;
1521 } else {
1522 raw_mask[1] = 0;
1523 }
4bae913b
EC		 1524
1525#if BITS_PER_LONG == 64
3c36a2ad
DP		 1526 mask[0] = raw_mask[0];
1527 mask[1] = raw_mask[1];
4bae913b 1528#else
3c36a2ad
DP		 1529 mask[0] = raw_mask[0] & 0xffffffff;
1530 mask[1] = raw_mask[0] >> 32;
1531 mask[2] = raw_mask[1] & 0xffffffff;
1532 mask[3] = raw_mask[1] >> 32;
4bae913b 1533#endif
8127d661
BH		 1534}
1535
1536static size_t efx_ef10_describe_stats(struct efx_nic *efx, u8 *names)
1537{
4bae913b
EC		 1538 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1539
1540 efx_ef10_get_stat_mask(efx, mask);
8127d661 1541 return efx_nic_describe_stats(efx_ef10_stat_desc, EF10_STAT_COUNT,
4bae913b 1542 mask, names);
8127d661
BH		 1543}
1544
d7788196
DP		 1545static size_t efx_ef10_update_stats_common(struct efx_nic *efx, u64 *full_stats,
1546 struct rtnl_link_stats64 *core_stats)
1547{
1548 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1549 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1550 u64 *stats = nic_data->stats;
1551 size_t stats_count = 0, index;
1552
1553 efx_ef10_get_stat_mask(efx, mask);
1554
1555 if (full_stats) {
1556 for_each_set_bit(index, mask, EF10_STAT_COUNT) {
1557 if (efx_ef10_stat_desc[index].name) {
1558 *full_stats++ = stats[index];
1559 ++stats_count;
1560 }
1561 }
1562 }
1563
fbe4307e
BK		 1564 if (!core_stats)
1565 return stats_count;
1566
1567 if (nic_data->datapath_caps &
1568 1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN) {
1569 /* Use vadaptor stats. */
0fc95fca
DP		 1570 core_stats->rx_packets = stats[EF10_STAT_rx_unicast] +
1571 stats[EF10_STAT_rx_multicast] +
1572 stats[EF10_STAT_rx_broadcast];
1573 core_stats->tx_packets = stats[EF10_STAT_tx_unicast] +
1574 stats[EF10_STAT_tx_multicast] +
1575 stats[EF10_STAT_tx_broadcast];
1576 core_stats->rx_bytes = stats[EF10_STAT_rx_unicast_bytes] +
1577 stats[EF10_STAT_rx_multicast_bytes] +
1578 stats[EF10_STAT_rx_broadcast_bytes];
1579 core_stats->tx_bytes = stats[EF10_STAT_tx_unicast_bytes] +
1580 stats[EF10_STAT_tx_multicast_bytes] +
1581 stats[EF10_STAT_tx_broadcast_bytes];
1582 core_stats->rx_dropped = stats[GENERIC_STAT_rx_nodesc_trunc] +
d7788196 1583 stats[GENERIC_STAT_rx_noskb_drops];
0fc95fca
DP		 1584 core_stats->multicast = stats[EF10_STAT_rx_multicast];
1585 core_stats->rx_crc_errors = stats[EF10_STAT_rx_bad];
1586 core_stats->rx_fifo_errors = stats[EF10_STAT_rx_overflow];
1587 core_stats->rx_errors = core_stats->rx_crc_errors;
1588 core_stats->tx_errors = stats[EF10_STAT_tx_bad];
fbe4307e
BK		 1589 } else {
1590 /* Use port stats. */
1591 core_stats->rx_packets = stats[EF10_STAT_port_rx_packets];
1592 core_stats->tx_packets = stats[EF10_STAT_port_tx_packets];
1593 core_stats->rx_bytes = stats[EF10_STAT_port_rx_bytes];
1594 core_stats->tx_bytes = stats[EF10_STAT_port_tx_bytes];
1595 core_stats->rx_dropped = stats[EF10_STAT_port_rx_nodesc_drops] +
1596 stats[GENERIC_STAT_rx_nodesc_trunc] +
1597 stats[GENERIC_STAT_rx_noskb_drops];
1598 core_stats->multicast = stats[EF10_STAT_port_rx_multicast];
1599 core_stats->rx_length_errors =
1600 stats[EF10_STAT_port_rx_gtjumbo] +
1601 stats[EF10_STAT_port_rx_length_error];
1602 core_stats->rx_crc_errors = stats[EF10_STAT_port_rx_bad];
1603 core_stats->rx_frame_errors =
1604 stats[EF10_STAT_port_rx_align_error];
1605 core_stats->rx_fifo_errors = stats[EF10_STAT_port_rx_overflow];
1606 core_stats->rx_errors = (core_stats->rx_length_errors +
1607 core_stats->rx_crc_errors +
1608 core_stats->rx_frame_errors);
d7788196
DP		 1609 }
1610
1611 return stats_count;
1612}
1613
1614static int efx_ef10_try_update_nic_stats_pf(struct efx_nic *efx)
8127d661
BH		 1615{
1616 struct efx_ef10_nic_data *nic_data = efx->nic_data;
4bae913b 1617 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
8127d661
BH		 1618 __le64 generation_start, generation_end;
1619 u64 *stats = nic_data->stats;
1620 __le64 *dma_stats;
1621
4bae913b
EC		 1622 efx_ef10_get_stat_mask(efx, mask);
1623
8127d661
BH		 1624 dma_stats = efx->stats_buffer.addr;
1625 nic_data = efx->nic_data;
1626
1627 generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
1628 if (generation_end == EFX_MC_STATS_GENERATION_INVALID)
1629 return 0;
1630 rmb();
4bae913b 1631 efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask,
8127d661 1632 stats, efx->stats_buffer.addr, false);
d546a893 1633 rmb();
8127d661
BH		 1634 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
1635 if (generation_end != generation_start)
1636 return -EAGAIN;
1637
1638 /* Update derived statistics */
e80ca013
DP		 1639 efx_nic_fix_nodesc_drop_stat(efx,
1640 &stats[EF10_STAT_port_rx_nodesc_drops]);
1641 stats[EF10_STAT_port_rx_good_bytes] =
1642 stats[EF10_STAT_port_rx_bytes] -
1643 stats[EF10_STAT_port_rx_bytes_minus_good_bytes];
1644 efx_update_diff_stat(&stats[EF10_STAT_port_rx_bad_bytes],
1645 stats[EF10_STAT_port_rx_bytes_minus_good_bytes]);
e4d112e4 1646 efx_update_sw_stats(efx, stats);
8127d661
BH		 1647 return 0;
1648}
1649
1650
d7788196
DP		 1651static size_t efx_ef10_update_stats_pf(struct efx_nic *efx, u64 *full_stats,
1652 struct rtnl_link_stats64 *core_stats)
8127d661 1653{
8127d661
BH		 1654 int retry;
1655
1656 /* If we're unlucky enough to read statistics during the DMA, wait
1657 * up to 10ms for it to finish (typically takes <500us)
1658 */
1659 for (retry = 0; retry < 100; ++retry) {
d7788196 1660 if (efx_ef10_try_update_nic_stats_pf(efx) == 0)
8127d661
BH		 1661 break;
1662 udelay(100);
1663 }
1664
d7788196
DP		 1665 return efx_ef10_update_stats_common(efx, full_stats, core_stats);
1666}
8127d661 1667
d7788196
DP		 1668static int efx_ef10_try_update_nic_stats_vf(struct efx_nic *efx)
1669{
1670 MCDI_DECLARE_BUF(inbuf, MC_CMD_MAC_STATS_IN_LEN);
1671 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1672 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1673 __le64 generation_start, generation_end;
1674 u64 *stats = nic_data->stats;
1675 u32 dma_len = MC_CMD_MAC_NSTATS * sizeof(u64);
1676 struct efx_buffer stats_buf;
1677 __le64 *dma_stats;
1678 int rc;
1679
f00bf230
DP		 1680 spin_unlock_bh(&efx->stats_lock);
1681
1682 if (in_interrupt()) {
1683 /* If in atomic context, cannot update stats. Just update the
1684 * software stats and return so the caller can continue.
1685 */
1686 spin_lock_bh(&efx->stats_lock);
1687 efx_update_sw_stats(efx, stats);
1688 return 0;
1689 }
1690
d7788196
DP		 1691 efx_ef10_get_stat_mask(efx, mask);
1692
1693 rc = efx_nic_alloc_buffer(efx, &stats_buf, dma_len, GFP_ATOMIC);
f00bf230
DP		 1694 if (rc) {
1695 spin_lock_bh(&efx->stats_lock);
d7788196 1696 return rc;
f00bf230 1697 }
d7788196
DP		 1698
1699 dma_stats = stats_buf.addr;
1700 dma_stats[MC_CMD_MAC_GENERATION_END] = EFX_MC_STATS_GENERATION_INVALID;
1701
1702 MCDI_SET_QWORD(inbuf, MAC_STATS_IN_DMA_ADDR, stats_buf.dma_addr);
1703 MCDI_POPULATE_DWORD_1(inbuf, MAC_STATS_IN_CMD,
0fc95fca 1704 MAC_STATS_IN_DMA, 1);
d7788196
DP		 1705 MCDI_SET_DWORD(inbuf, MAC_STATS_IN_DMA_LEN, dma_len);
1706 MCDI_SET_DWORD(inbuf, MAC_STATS_IN_PORT_ID, EVB_PORT_ID_ASSIGNED);
1707
6dd4859b
DP		 1708 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_MAC_STATS, inbuf, sizeof(inbuf),
1709 NULL, 0, NULL);
d7788196 1710 spin_lock_bh(&efx->stats_lock);
6dd4859b
DP		 1711 if (rc) {
1712 /* Expect ENOENT if DMA queues have not been set up */
1713 if (rc != -ENOENT || atomic_read(&efx->active_queues))
1714 efx_mcdi_display_error(efx, MC_CMD_MAC_STATS,
1715 sizeof(inbuf), NULL, 0, rc);
d7788196 1716 goto out;
6dd4859b 1717 }
d7788196
DP		 1718
1719 generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
0fc95fca
DP		 1720 if (generation_end == EFX_MC_STATS_GENERATION_INVALID) {
1721 WARN_ON_ONCE(1);
d7788196 1722 goto out;
0fc95fca 1723 }
d7788196
DP		 1724 rmb();
1725 efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask,
1726 stats, stats_buf.addr, false);
1727 rmb();
1728 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
1729 if (generation_end != generation_start) {
1730 rc = -EAGAIN;
1731 goto out;
8127d661
BH		 1732 }
1733
d7788196
DP		 1734 efx_update_sw_stats(efx, stats);
1735out:
1736 efx_nic_free_buffer(efx, &stats_buf);
1737 return rc;
1738}
1739
1740static size_t efx_ef10_update_stats_vf(struct efx_nic *efx, u64 *full_stats,
1741 struct rtnl_link_stats64 *core_stats)
1742{
1743 if (efx_ef10_try_update_nic_stats_vf(efx))
1744 return 0;
1745
1746 return efx_ef10_update_stats_common(efx, full_stats, core_stats);
8127d661
BH		 1747}
1748
1749static void efx_ef10_push_irq_moderation(struct efx_channel *channel)
1750{
1751 struct efx_nic *efx = channel->efx;
1752 unsigned int mode, value;
1753 efx_dword_t timer_cmd;
1754
1755 if (channel->irq_moderation) {
1756 mode = 3;
1757 value = channel->irq_moderation - 1;
1758 } else {
1759 mode = 0;
1760 value = 0;
1761 }
1762
1763 if (EFX_EF10_WORKAROUND_35388(efx)) {
1764 EFX_POPULATE_DWORD_3(timer_cmd, ERF_DD_EVQ_IND_TIMER_FLAGS,
1765 EFE_DD_EVQ_IND_TIMER_FLAGS,
1766 ERF_DD_EVQ_IND_TIMER_MODE, mode,
1767 ERF_DD_EVQ_IND_TIMER_VAL, value);
1768 efx_writed_page(efx, &timer_cmd, ER_DD_EVQ_INDIRECT,
1769 channel->channel);
1770 } else {
1771 EFX_POPULATE_DWORD_2(timer_cmd, ERF_DZ_TC_TIMER_MODE, mode,
1772 ERF_DZ_TC_TIMER_VAL, value);
1773 efx_writed_page(efx, &timer_cmd, ER_DZ_EVQ_TMR,
1774 channel->channel);
1775 }
1776}
1777
02246a7f
SS		 1778static void efx_ef10_get_wol_vf(struct efx_nic *efx,
1779 struct ethtool_wolinfo *wol) {}
1780
1781static int efx_ef10_set_wol_vf(struct efx_nic *efx, u32 type)
1782{
1783 return -EOPNOTSUPP;
1784}
1785
8127d661
BH		 1786static void efx_ef10_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
1787{
1788 wol->supported = 0;
1789 wol->wolopts = 0;
1790 memset(&wol->sopass, 0, sizeof(wol->sopass));
1791}
1792
1793static int efx_ef10_set_wol(struct efx_nic *efx, u32 type)
1794{
1795 if (type != 0)
1796 return -EINVAL;
1797 return 0;
1798}
1799
1800static void efx_ef10_mcdi_request(struct efx_nic *efx,
1801 const efx_dword_t *hdr, size_t hdr_len,
1802 const efx_dword_t *sdu, size_t sdu_len)
1803{
1804 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1805 u8 *pdu = nic_data->mcdi_buf.addr;
1806
1807 memcpy(pdu, hdr, hdr_len);
1808 memcpy(pdu + hdr_len, sdu, sdu_len);
1809 wmb();
1810
1811 /* The hardware provides 'low' and 'high' (doorbell) registers
1812 * for passing the 64-bit address of an MCDI request to
1813 * firmware. However the dwords are swapped by firmware. The
1814 * least significant bits of the doorbell are then 0 for all
1815 * MCDI requests due to alignment.
1816 */
1817 _efx_writed(efx, cpu_to_le32((u64)nic_data->mcdi_buf.dma_addr >> 32),
1818 ER_DZ_MC_DB_LWRD);
1819 _efx_writed(efx, cpu_to_le32((u32)nic_data->mcdi_buf.dma_addr),
1820 ER_DZ_MC_DB_HWRD);
1821}
1822
1823static bool efx_ef10_mcdi_poll_response(struct efx_nic *efx)
1824{
1825 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1826 const efx_dword_t hdr = *(const efx_dword_t *)nic_data->mcdi_buf.addr;
1827
1828 rmb();
1829 return EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE);
1830}
1831
1832static void
1833efx_ef10_mcdi_read_response(struct efx_nic *efx, efx_dword_t *outbuf,
1834 size_t offset, size_t outlen)
1835{
1836 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1837 const u8 *pdu = nic_data->mcdi_buf.addr;
1838
1839 memcpy(outbuf, pdu + offset, outlen);
1840}
1841
c577e59e
DP		 1842static void efx_ef10_mcdi_reboot_detected(struct efx_nic *efx)
1843{
1844 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1845
1846 /* All our allocations have been reset */
1847 efx_ef10_reset_mc_allocations(efx);
1848
1849 /* The datapath firmware might have been changed */
1850 nic_data->must_check_datapath_caps = true;
1851
1852 /* MAC statistics have been cleared on the NIC; clear the local
1853 * statistic that we update with efx_update_diff_stat().
1854 */
1855 nic_data->stats[EF10_STAT_port_rx_bad_bytes] = 0;
1856}
1857
8127d661
BH		 1858static int efx_ef10_mcdi_poll_reboot(struct efx_nic *efx)
1859{
1860 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1861 int rc;
1862
1863 rc = efx_ef10_get_warm_boot_count(efx);
1864 if (rc < 0) {
1865 /* The firmware is presumably in the process of
1866 * rebooting. However, we are supposed to report each
1867 * reboot just once, so we must only do that once we
1868 * can read and store the updated warm boot count.
1869 */
1870 return 0;
1871 }
1872
1873 if (rc == nic_data->warm_boot_count)
1874 return 0;
1875
1876 nic_data->warm_boot_count = rc;
c577e59e 1877 efx_ef10_mcdi_reboot_detected(efx);
869070c5 1878
8127d661
BH		 1879 return -EIO;
1880}
1881
1882/* Handle an MSI interrupt
1883 *
1884 * Handle an MSI hardware interrupt. This routine schedules event
1885 * queue processing. No interrupt acknowledgement cycle is necessary.
1886 * Also, we never need to check that the interrupt is for us, since
1887 * MSI interrupts cannot be shared.
1888 */
1889static irqreturn_t efx_ef10_msi_interrupt(int irq, void *dev_id)
1890{
1891 struct efx_msi_context *context = dev_id;
1892 struct efx_nic *efx = context->efx;
1893
1894 netif_vdbg(efx, intr, efx->net_dev,
1895 "IRQ %d on CPU %d\n", irq, raw_smp_processor_id());
1896
1897 if (likely(ACCESS_ONCE(efx->irq_soft_enabled))) {
1898 /* Note test interrupts */
1899 if (context->index == efx->irq_level)
1900 efx->last_irq_cpu = raw_smp_processor_id();
1901
1902 /* Schedule processing of the channel */
1903 efx_schedule_channel_irq(efx->channel[context->index]);
1904 }
1905
1906 return IRQ_HANDLED;
1907}
1908
1909static irqreturn_t efx_ef10_legacy_interrupt(int irq, void *dev_id)
1910{
1911 struct efx_nic *efx = dev_id;
1912 bool soft_enabled = ACCESS_ONCE(efx->irq_soft_enabled);
1913 struct efx_channel *channel;
1914 efx_dword_t reg;
1915 u32 queues;
1916
1917 /* Read the ISR which also ACKs the interrupts */
1918 efx_readd(efx, &reg, ER_DZ_BIU_INT_ISR);
1919 queues = EFX_DWORD_FIELD(reg, ERF_DZ_ISR_REG);
1920
1921 if (queues == 0)
1922 return IRQ_NONE;
1923
1924 if (likely(soft_enabled)) {
1925 /* Note test interrupts */
1926 if (queues & (1U << efx->irq_level))
1927 efx->last_irq_cpu = raw_smp_processor_id();
1928
1929 efx_for_each_channel(channel, efx) {
1930 if (queues & 1)
1931 efx_schedule_channel_irq(channel);
1932 queues >>= 1;
1933 }
1934 }
1935
1936 netif_vdbg(efx, intr, efx->net_dev,
1937 "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
1938 irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
1939
1940 return IRQ_HANDLED;
1941}
1942
1943static void efx_ef10_irq_test_generate(struct efx_nic *efx)
1944{
1945 MCDI_DECLARE_BUF(inbuf, MC_CMD_TRIGGER_INTERRUPT_IN_LEN);
1946
1947 BUILD_BUG_ON(MC_CMD_TRIGGER_INTERRUPT_OUT_LEN != 0);
1948
1949 MCDI_SET_DWORD(inbuf, TRIGGER_INTERRUPT_IN_INTR_LEVEL, efx->irq_level);
1950 (void) efx_mcdi_rpc(efx, MC_CMD_TRIGGER_INTERRUPT,
1951 inbuf, sizeof(inbuf), NULL, 0, NULL);
1952}
1953
1954static int efx_ef10_tx_probe(struct efx_tx_queue *tx_queue)
1955{
1956 return efx_nic_alloc_buffer(tx_queue->efx, &tx_queue->txd.buf,
1957 (tx_queue->ptr_mask + 1) *
1958 sizeof(efx_qword_t),
1959 GFP_KERNEL);
1960}
1961
1962/* This writes to the TX_DESC_WPTR and also pushes data */
1963static inline void efx_ef10_push_tx_desc(struct efx_tx_queue *tx_queue,
1964 const efx_qword_t *txd)
1965{
1966 unsigned int write_ptr;
1967 efx_oword_t reg;
1968
1969 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
1970 EFX_POPULATE_OWORD_1(reg, ERF_DZ_TX_DESC_WPTR, write_ptr);
1971 reg.qword[0] = *txd;
1972 efx_writeo_page(tx_queue->efx, &reg,
1973 ER_DZ_TX_DESC_UPD, tx_queue->queue);
1974}
1975
1976static void efx_ef10_tx_init(struct efx_tx_queue *tx_queue)
1977{
1978 MCDI_DECLARE_BUF(inbuf, MC_CMD_INIT_TXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
1979 EFX_BUF_SIZE));
8127d661
BH		 1980 bool csum_offload = tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD;
1981 size_t entries = tx_queue->txd.buf.len / EFX_BUF_SIZE;
1982 struct efx_channel *channel = tx_queue->channel;
1983 struct efx_nic *efx = tx_queue->efx;
45b2449e 1984 struct efx_ef10_nic_data *nic_data = efx->nic_data;
aa09a3da 1985 size_t inlen;
8127d661
BH		 1986 dma_addr_t dma_addr;
1987 efx_qword_t *txd;
1988 int rc;
1989 int i;
aa09a3da 1990 BUILD_BUG_ON(MC_CMD_INIT_TXQ_OUT_LEN != 0);
8127d661
BH		 1991
1992 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_SIZE, tx_queue->ptr_mask + 1);
1993 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_TARGET_EVQ, channel->channel);
1994 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_LABEL, tx_queue->queue);
1995 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_INSTANCE, tx_queue->queue);
1996 MCDI_POPULATE_DWORD_2(inbuf, INIT_TXQ_IN_FLAGS,
1997 INIT_TXQ_IN_FLAG_IP_CSUM_DIS, !csum_offload,
1998 INIT_TXQ_IN_FLAG_TCP_CSUM_DIS, !csum_offload);
1999 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_OWNER_ID, 0);
45b2449e 2000 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_PORT_ID, nic_data->vport_id);
8127d661
BH		 2001
2002 dma_addr = tx_queue->txd.buf.dma_addr;
2003
2004 netif_dbg(efx, hw, efx->net_dev, "pushing TXQ %d. %zu entries (%llx)\n",
2005 tx_queue->queue, entries, (u64)dma_addr);
2006
2007 for (i = 0; i < entries; ++i) {
2008 MCDI_SET_ARRAY_QWORD(inbuf, INIT_TXQ_IN_DMA_ADDR, i, dma_addr);
2009 dma_addr += EFX_BUF_SIZE;
2010 }
2011
2012 inlen = MC_CMD_INIT_TXQ_IN_LEN(entries);
2013
2014 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_TXQ, inbuf, inlen,
aa09a3da 2015 NULL, 0, NULL);
8127d661
BH		 2016 if (rc)
2017 goto fail;
2018
2019 /* A previous user of this TX queue might have set us up the
2020 * bomb by writing a descriptor to the TX push collector but
2021 * not the doorbell. (Each collector belongs to a port, not a
2022 * queue or function, so cannot easily be reset.) We must
2023 * attempt to push a no-op descriptor in its place.
2024 */
2025 tx_queue->buffer[0].flags = EFX_TX_BUF_OPTION;
2026 tx_queue->insert_count = 1;
2027 txd = efx_tx_desc(tx_queue, 0);
2028 EFX_POPULATE_QWORD_4(*txd,
2029 ESF_DZ_TX_DESC_IS_OPT, true,
2030 ESF_DZ_TX_OPTION_TYPE,
2031 ESE_DZ_TX_OPTION_DESC_CRC_CSUM,
2032 ESF_DZ_TX_OPTION_UDP_TCP_CSUM, csum_offload,
2033 ESF_DZ_TX_OPTION_IP_CSUM, csum_offload);
2034 tx_queue->write_count = 1;
93171b14
BK		 2035
2036 if (nic_data->datapath_caps &
2037 (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN)) {
2038 tx_queue->tso_version = 1;
2039 }
2040
8127d661
BH		 2041 wmb();
2042 efx_ef10_push_tx_desc(tx_queue, txd);
2043
2044 return;
2045
2046fail:
48ce5634
BH		 2047 netdev_WARN(efx->net_dev, "failed to initialise TXQ %d\n",
2048 tx_queue->queue);
8127d661
BH		 2049}
2050
2051static void efx_ef10_tx_fini(struct efx_tx_queue *tx_queue)
2052{
2053 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_TXQ_IN_LEN);
aa09a3da 2054 MCDI_DECLARE_BUF_ERR(outbuf);
8127d661
BH		 2055 struct efx_nic *efx = tx_queue->efx;
2056 size_t outlen;
2057 int rc;
2058
2059 MCDI_SET_DWORD(inbuf, FINI_TXQ_IN_INSTANCE,
2060 tx_queue->queue);
2061
1e0b8120 2062 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_TXQ, inbuf, sizeof(inbuf),
8127d661
BH		 2063 outbuf, sizeof(outbuf), &outlen);
2064
2065 if (rc && rc != -EALREADY)
2066 goto fail;
2067
2068 return;
2069
2070fail:
1e0b8120
EC		 2071 efx_mcdi_display_error(efx, MC_CMD_FINI_TXQ, MC_CMD_FINI_TXQ_IN_LEN,
2072 outbuf, outlen, rc);
8127d661
BH		 2073}
2074
2075static void efx_ef10_tx_remove(struct efx_tx_queue *tx_queue)
2076{
2077 efx_nic_free_buffer(tx_queue->efx, &tx_queue->txd.buf);
2078}
2079
2080/* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
2081static inline void efx_ef10_notify_tx_desc(struct efx_tx_queue *tx_queue)
2082{
2083 unsigned int write_ptr;
2084 efx_dword_t reg;
2085
2086 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
2087 EFX_POPULATE_DWORD_1(reg, ERF_DZ_TX_DESC_WPTR_DWORD, write_ptr);
2088 efx_writed_page(tx_queue->efx, &reg,
2089 ER_DZ_TX_DESC_UPD_DWORD, tx_queue->queue);
2090}
2091
2092static void efx_ef10_tx_write(struct efx_tx_queue *tx_queue)
2093{
2094 unsigned int old_write_count = tx_queue->write_count;
2095 struct efx_tx_buffer *buffer;
2096 unsigned int write_ptr;
2097 efx_qword_t *txd;
2098
b2663a4f
MH		 2099 tx_queue->xmit_more_available = false;
2100 if (unlikely(tx_queue->write_count == tx_queue->insert_count))
2101 return;
8127d661
BH		 2102
2103 do {
2104 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
2105 buffer = &tx_queue->buffer[write_ptr];
2106 txd = efx_tx_desc(tx_queue, write_ptr);
2107 ++tx_queue->write_count;
2108
2109 /* Create TX descriptor ring entry */
2110 if (buffer->flags & EFX_TX_BUF_OPTION) {
2111 *txd = buffer->option;
2112 } else {
2113 BUILD_BUG_ON(EFX_TX_BUF_CONT != 1);
2114 EFX_POPULATE_QWORD_3(
2115 *txd,
2116 ESF_DZ_TX_KER_CONT,
2117 buffer->flags & EFX_TX_BUF_CONT,
2118 ESF_DZ_TX_KER_BYTE_CNT, buffer->len,
2119 ESF_DZ_TX_KER_BUF_ADDR, buffer->dma_addr);
2120 }
2121 } while (tx_queue->write_count != tx_queue->insert_count);
2122
2123 wmb(); /* Ensure descriptors are written before they are fetched */
2124
2125 if (efx_nic_may_push_tx_desc(tx_queue, old_write_count)) {
2126 txd = efx_tx_desc(tx_queue,
2127 old_write_count & tx_queue->ptr_mask);
2128 efx_ef10_push_tx_desc(tx_queue, txd);
2129 ++tx_queue->pushes;
2130 } else {
2131 efx_ef10_notify_tx_desc(tx_queue);
2132 }
2133}
2134
267c0157
JC		 2135static int efx_ef10_alloc_rss_context(struct efx_nic *efx, u32 *context,
2136 bool exclusive, unsigned *context_size)
8127d661
BH		 2137{
2138 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN);
2139 MCDI_DECLARE_BUF(outbuf, MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN);
45b2449e 2140 struct efx_ef10_nic_data *nic_data = efx->nic_data;
8127d661
BH		 2141 size_t outlen;
2142 int rc;
267c0157
JC		 2143 u32 alloc_type = exclusive ?
2144 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE :
2145 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED;
2146 unsigned rss_spread = exclusive ?
2147 efx->rss_spread :
2148 min(rounddown_pow_of_two(efx->rss_spread),
2149 EFX_EF10_MAX_SHARED_RSS_CONTEXT_SIZE);
2150
2151 if (!exclusive && rss_spread == 1) {
2152 *context = EFX_EF10_RSS_CONTEXT_INVALID;
2153 if (context_size)
2154 *context_size = 1;
2155 return 0;
2156 }
8127d661 2157
dcb4123c
JC		 2158 if (nic_data->datapath_caps &
2159 1 << MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_LBN)
2160 return -EOPNOTSUPP;
2161
8127d661 2162 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID,
45b2449e 2163 nic_data->vport_id);
267c0157
JC		 2164 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_TYPE, alloc_type);
2165 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_NUM_QUEUES, rss_spread);
8127d661
BH		 2166
2167 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_ALLOC, inbuf, sizeof(inbuf),
2168 outbuf, sizeof(outbuf), &outlen);
2169 if (rc != 0)
2170 return rc;
2171
2172 if (outlen < MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN)
2173 return -EIO;
2174
2175 *context = MCDI_DWORD(outbuf, RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID);
2176
267c0157
JC		 2177 if (context_size)
2178 *context_size = rss_spread;
2179
8127d661
BH		 2180 return 0;
2181}
2182
2183static void efx_ef10_free_rss_context(struct efx_nic *efx, u32 context)
2184{
2185 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_FREE_IN_LEN);
2186 int rc;
2187
2188 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID,
2189 context);
2190
2191 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_FREE, inbuf, sizeof(inbuf),
2192 NULL, 0, NULL);
2193 WARN_ON(rc != 0);
2194}
2195
267c0157
JC		 2196static int efx_ef10_populate_rss_table(struct efx_nic *efx, u32 context,
2197 const u32 *rx_indir_table)
8127d661
BH		 2198{
2199 MCDI_DECLARE_BUF(tablebuf, MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN);
2200 MCDI_DECLARE_BUF(keybuf, MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN);
2201 int i, rc;
2202
2203 MCDI_SET_DWORD(tablebuf, RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID,
2204 context);
2205 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_indir_table) !=
2206 MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN);
2207
2208 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); ++i)
2209 MCDI_PTR(tablebuf,
2210 RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE)[i] =
267c0157 2211 (u8) rx_indir_table[i];
8127d661
BH		 2212
2213 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_TABLE, tablebuf,
2214 sizeof(tablebuf), NULL, 0, NULL);
2215 if (rc != 0)
2216 return rc;
2217
2218 MCDI_SET_DWORD(keybuf, RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID,
2219 context);
2220 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_hash_key) !=
2221 MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN);
2222 for (i = 0; i < ARRAY_SIZE(efx->rx_hash_key); ++i)
2223 MCDI_PTR(keybuf, RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY)[i] =
2224 efx->rx_hash_key[i];
2225
2226 return efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_KEY, keybuf,
2227 sizeof(keybuf), NULL, 0, NULL);
2228}
2229
2230static void efx_ef10_rx_free_indir_table(struct efx_nic *efx)
2231{
2232 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2233
2234 if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID)
2235 efx_ef10_free_rss_context(efx, nic_data->rx_rss_context);
2236 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
2237}
2238
267c0157
JC		 2239static int efx_ef10_rx_push_shared_rss_config(struct efx_nic *efx,
2240 unsigned *context_size)
8127d661 2241{
267c0157 2242 u32 new_rx_rss_context;
8127d661 2243 struct efx_ef10_nic_data *nic_data = efx->nic_data;
267c0157
JC		 2244 int rc = efx_ef10_alloc_rss_context(efx, &new_rx_rss_context,
2245 false, context_size);
2246
2247 if (rc != 0)
2248 return rc;
8127d661 2249
267c0157
JC		 2250 nic_data->rx_rss_context = new_rx_rss_context;
2251 nic_data->rx_rss_context_exclusive = false;
2252 efx_set_default_rx_indir_table(efx);
2253 return 0;
2254}
8127d661 2255
267c0157
JC		 2256static int efx_ef10_rx_push_exclusive_rss_config(struct efx_nic *efx,
2257 const u32 *rx_indir_table)
2258{
2259 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2260 int rc;
2261 u32 new_rx_rss_context;
2262
2263 if (nic_data->rx_rss_context == EFX_EF10_RSS_CONTEXT_INVALID ||
2264 !nic_data->rx_rss_context_exclusive) {
2265 rc = efx_ef10_alloc_rss_context(efx, &new_rx_rss_context,
2266 true, NULL);
2267 if (rc == -EOPNOTSUPP)
2268 return rc;
2269 else if (rc != 0)
2270 goto fail1;
2271 } else {
2272 new_rx_rss_context = nic_data->rx_rss_context;
8127d661
BH		 2273 }
2274
267c0157
JC		 2275 rc = efx_ef10_populate_rss_table(efx, new_rx_rss_context,
2276 rx_indir_table);
8127d661 2277 if (rc != 0)
267c0157 2278 goto fail2;
8127d661 2279
267c0157
JC		 2280 if (nic_data->rx_rss_context != new_rx_rss_context)
2281 efx_ef10_rx_free_indir_table(efx);
2282 nic_data->rx_rss_context = new_rx_rss_context;
2283 nic_data->rx_rss_context_exclusive = true;
2284 if (rx_indir_table != efx->rx_indir_table)
2285 memcpy(efx->rx_indir_table, rx_indir_table,
2286 sizeof(efx->rx_indir_table));
2287 return 0;
8127d661 2288
267c0157
JC		 2289fail2:
2290 if (new_rx_rss_context != nic_data->rx_rss_context)
2291 efx_ef10_free_rss_context(efx, new_rx_rss_context);
2292fail1:
8127d661 2293 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
267c0157
JC		 2294 return rc;
2295}
2296
2297static int efx_ef10_pf_rx_push_rss_config(struct efx_nic *efx, bool user,
2298 const u32 *rx_indir_table)
2299{
2300 int rc;
2301
2302 if (efx->rss_spread == 1)
2303 return 0;
2304
2305 rc = efx_ef10_rx_push_exclusive_rss_config(efx, rx_indir_table);
2306
2307 if (rc == -ENOBUFS && !user) {
2308 unsigned context_size;
2309 bool mismatch = false;
2310 size_t i;
2311
2312 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table) && !mismatch;
2313 i++)
2314 mismatch = rx_indir_table[i] !=
2315 ethtool_rxfh_indir_default(i, efx->rss_spread);
2316
2317 rc = efx_ef10_rx_push_shared_rss_config(efx, &context_size);
2318 if (rc == 0) {
2319 if (context_size != efx->rss_spread)
2320 netif_warn(efx, probe, efx->net_dev,
2321 "Could not allocate an exclusive RSS"
2322 " context; allocated a shared one of"
2323 " different size."
2324 " Wanted %u, got %u.\n",
2325 efx->rss_spread, context_size);
2326 else if (mismatch)
2327 netif_warn(efx, probe, efx->net_dev,
2328 "Could not allocate an exclusive RSS"
2329 " context; allocated a shared one but"
2330 " could not apply custom"
2331 " indirection.\n");
2332 else
2333 netif_info(efx, probe, efx->net_dev,
2334 "Could not allocate an exclusive RSS"
2335 " context; allocated a shared one.\n");
2336 }
2337 }
2338 return rc;
2339}
2340
2341static int efx_ef10_vf_rx_push_rss_config(struct efx_nic *efx, bool user,
2342 const u32 *rx_indir_table
2343 __attribute__ ((unused)))
2344{
2345 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2346
2347 if (user)
2348 return -EOPNOTSUPP;
2349 if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID)
2350 return 0;
2351 return efx_ef10_rx_push_shared_rss_config(efx, NULL);
8127d661
BH		 2352}
2353
2354static int efx_ef10_rx_probe(struct efx_rx_queue *rx_queue)
2355{
2356 return efx_nic_alloc_buffer(rx_queue->efx, &rx_queue->rxd.buf,
2357 (rx_queue->ptr_mask + 1) *
2358 sizeof(efx_qword_t),
2359 GFP_KERNEL);
2360}
2361
2362static void efx_ef10_rx_init(struct efx_rx_queue *rx_queue)
2363{
2364 MCDI_DECLARE_BUF(inbuf,
2365 MC_CMD_INIT_RXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
2366 EFX_BUF_SIZE));
8127d661
BH		 2367 struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
2368 size_t entries = rx_queue->rxd.buf.len / EFX_BUF_SIZE;
2369 struct efx_nic *efx = rx_queue->efx;
45b2449e 2370 struct efx_ef10_nic_data *nic_data = efx->nic_data;
aa09a3da 2371 size_t inlen;
8127d661
BH		 2372 dma_addr_t dma_addr;
2373 int rc;
2374 int i;
aa09a3da 2375 BUILD_BUG_ON(MC_CMD_INIT_RXQ_OUT_LEN != 0);
8127d661
BH		 2376
2377 rx_queue->scatter_n = 0;
2378 rx_queue->scatter_len = 0;
2379
2380 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_SIZE, rx_queue->ptr_mask + 1);
2381 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_TARGET_EVQ, channel->channel);
2382 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_LABEL, efx_rx_queue_index(rx_queue));
2383 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_INSTANCE,
2384 efx_rx_queue_index(rx_queue));
bd9a265d
JC		 2385 MCDI_POPULATE_DWORD_2(inbuf, INIT_RXQ_IN_FLAGS,
2386 INIT_RXQ_IN_FLAG_PREFIX, 1,
2387 INIT_RXQ_IN_FLAG_TIMESTAMP, 1);
8127d661 2388 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_OWNER_ID, 0);
45b2449e 2389 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_PORT_ID, nic_data->vport_id);
8127d661
BH		 2390
2391 dma_addr = rx_queue->rxd.buf.dma_addr;
2392
2393 netif_dbg(efx, hw, efx->net_dev, "pushing RXQ %d. %zu entries (%llx)\n",
2394 efx_rx_queue_index(rx_queue), entries, (u64)dma_addr);
2395
2396 for (i = 0; i < entries; ++i) {
2397 MCDI_SET_ARRAY_QWORD(inbuf, INIT_RXQ_IN_DMA_ADDR, i, dma_addr);
2398 dma_addr += EFX_BUF_SIZE;
2399 }
2400
2401 inlen = MC_CMD_INIT_RXQ_IN_LEN(entries);
2402
2403 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_RXQ, inbuf, inlen,
aa09a3da 2404 NULL, 0, NULL);
48ce5634
BH		 2405 if (rc)
2406 netdev_WARN(efx->net_dev, "failed to initialise RXQ %d\n",
2407 efx_rx_queue_index(rx_queue));
8127d661
BH		 2408}
2409
2410static void efx_ef10_rx_fini(struct efx_rx_queue *rx_queue)
2411{
2412 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_RXQ_IN_LEN);
aa09a3da 2413 MCDI_DECLARE_BUF_ERR(outbuf);
8127d661
BH		 2414 struct efx_nic *efx = rx_queue->efx;
2415 size_t outlen;
2416 int rc;
2417
2418 MCDI_SET_DWORD(inbuf, FINI_RXQ_IN_INSTANCE,
2419 efx_rx_queue_index(rx_queue));
2420
1e0b8120 2421 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_RXQ, inbuf, sizeof(inbuf),
8127d661
BH		 2422 outbuf, sizeof(outbuf), &outlen);
2423
2424 if (rc && rc != -EALREADY)
2425 goto fail;
2426
2427 return;
2428
2429fail:
1e0b8120
EC		 2430 efx_mcdi_display_error(efx, MC_CMD_FINI_RXQ, MC_CMD_FINI_RXQ_IN_LEN,
2431 outbuf, outlen, rc);
8127d661
BH		 2432}
2433
2434static void efx_ef10_rx_remove(struct efx_rx_queue *rx_queue)
2435{
2436 efx_nic_free_buffer(rx_queue->efx, &rx_queue->rxd.buf);
2437}
2438
2439/* This creates an entry in the RX descriptor queue */
2440static inline void
2441efx_ef10_build_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index)
2442{
2443 struct efx_rx_buffer *rx_buf;
2444 efx_qword_t *rxd;
2445
2446 rxd = efx_rx_desc(rx_queue, index);
2447 rx_buf = efx_rx_buffer(rx_queue, index);
2448 EFX_POPULATE_QWORD_2(*rxd,
2449 ESF_DZ_RX_KER_BYTE_CNT, rx_buf->len,
2450 ESF_DZ_RX_KER_BUF_ADDR, rx_buf->dma_addr);
2451}
2452
2453static void efx_ef10_rx_write(struct efx_rx_queue *rx_queue)
2454{
2455 struct efx_nic *efx = rx_queue->efx;
2456 unsigned int write_count;
2457 efx_dword_t reg;
2458
2459 /* Firmware requires that RX_DESC_WPTR be a multiple of 8 */
2460 write_count = rx_queue->added_count & ~7;
2461 if (rx_queue->notified_count == write_count)
2462 return;
2463
2464 do
2465 efx_ef10_build_rx_desc(
2466 rx_queue,
2467 rx_queue->notified_count & rx_queue->ptr_mask);
2468 while (++rx_queue->notified_count != write_count);
2469
2470 wmb();
2471 EFX_POPULATE_DWORD_1(reg, ERF_DZ_RX_DESC_WPTR,
2472 write_count & rx_queue->ptr_mask);
2473 efx_writed_page(efx, &reg, ER_DZ_RX_DESC_UPD,
2474 efx_rx_queue_index(rx_queue));
2475}
2476
2477static efx_mcdi_async_completer efx_ef10_rx_defer_refill_complete;
2478
2479static void efx_ef10_rx_defer_refill(struct efx_rx_queue *rx_queue)
2480{
2481 struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
2482 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
2483 efx_qword_t event;
2484
2485 EFX_POPULATE_QWORD_2(event,
2486 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
2487 ESF_DZ_EV_DATA, EFX_EF10_REFILL);
2488
2489 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
2490
2491 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
2492 * already swapped the data to little-endian order.
2493 */
2494 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
2495 sizeof(efx_qword_t));
2496
2497 efx_mcdi_rpc_async(channel->efx, MC_CMD_DRIVER_EVENT,
2498 inbuf, sizeof(inbuf), 0,
2499 efx_ef10_rx_defer_refill_complete, 0);
2500}
2501
2502static void
2503efx_ef10_rx_defer_refill_complete(struct efx_nic *efx, unsigned long cookie,
2504 int rc, efx_dword_t *outbuf,
2505 size_t outlen_actual)
2506{
2507 /* nothing to do */
2508}
2509
2510static int efx_ef10_ev_probe(struct efx_channel *channel)
2511{
2512 return efx_nic_alloc_buffer(channel->efx, &channel->eventq.buf,
2513 (channel->eventq_mask + 1) *
2514 sizeof(efx_qword_t),
2515 GFP_KERNEL);
2516}
2517
46e612b0
DP		 2518static void efx_ef10_ev_fini(struct efx_channel *channel)
2519{
2520 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_EVQ_IN_LEN);
2521 MCDI_DECLARE_BUF_ERR(outbuf);
2522 struct efx_nic *efx = channel->efx;
2523 size_t outlen;
2524 int rc;
2525
2526 MCDI_SET_DWORD(inbuf, FINI_EVQ_IN_INSTANCE, channel->channel);
2527
2528 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_EVQ, inbuf, sizeof(inbuf),
2529 outbuf, sizeof(outbuf), &outlen);
2530
2531 if (rc && rc != -EALREADY)
2532 goto fail;
2533
2534 return;
2535
2536fail:
2537 efx_mcdi_display_error(efx, MC_CMD_FINI_EVQ, MC_CMD_FINI_EVQ_IN_LEN,
2538 outbuf, outlen, rc);
2539}
2540
8127d661
BH		 2541static int efx_ef10_ev_init(struct efx_channel *channel)
2542{
2543 MCDI_DECLARE_BUF(inbuf,
2544 MC_CMD_INIT_EVQ_IN_LEN(EFX_MAX_EVQ_SIZE * 8 /
2545 EFX_BUF_SIZE));
2546 MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_EVQ_OUT_LEN);
2547 size_t entries = channel->eventq.buf.len / EFX_BUF_SIZE;
2548 struct efx_nic *efx = channel->efx;
2549 struct efx_ef10_nic_data *nic_data;
2550 bool supports_rx_merge;
2551 size_t inlen, outlen;
46e612b0 2552 unsigned int enabled, implemented;
8127d661
BH		 2553 dma_addr_t dma_addr;
2554 int rc;
2555 int i;
2556
2557 nic_data = efx->nic_data;
2558 supports_rx_merge =
2559 !!(nic_data->datapath_caps &
2560 1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN);
2561
2562 /* Fill event queue with all ones (i.e. empty events) */
2563 memset(channel->eventq.buf.addr, 0xff, channel->eventq.buf.len);
2564
2565 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_SIZE, channel->eventq_mask + 1);
2566 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_INSTANCE, channel->channel);
2567 /* INIT_EVQ expects index in vector table, not absolute */
2568 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_IRQ_NUM, channel->channel);
2569 MCDI_POPULATE_DWORD_4(inbuf, INIT_EVQ_IN_FLAGS,
2570 INIT_EVQ_IN_FLAG_INTERRUPTING, 1,
2571 INIT_EVQ_IN_FLAG_RX_MERGE, 1,
2572 INIT_EVQ_IN_FLAG_TX_MERGE, 1,
2573 INIT_EVQ_IN_FLAG_CUT_THRU, !supports_rx_merge);
2574 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_MODE,
2575 MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS);
2576 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_LOAD, 0);
2577 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_RELOAD, 0);
2578 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_MODE,
2579 MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS);
2580 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_THRSHLD, 0);
2581
2582 dma_addr = channel->eventq.buf.dma_addr;
2583 for (i = 0; i < entries; ++i) {
2584 MCDI_SET_ARRAY_QWORD(inbuf, INIT_EVQ_IN_DMA_ADDR, i, dma_addr);
2585 dma_addr += EFX_BUF_SIZE;
2586 }
2587
2588 inlen = MC_CMD_INIT_EVQ_IN_LEN(entries);
2589
2590 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_EVQ, inbuf, inlen,
2591 outbuf, sizeof(outbuf), &outlen);
8127d661 2592 /* IRQ return is ignored */
46e612b0
DP		 2593 if (channel->channel || rc)
2594 return rc;
8127d661 2595
46e612b0
DP		 2596 /* Successfully created event queue on channel 0 */
2597 rc = efx_mcdi_get_workarounds(efx, &implemented, &enabled);
832dc9ed
EC		 2598 if (rc == -ENOSYS) {
2599 /* GET_WORKAROUNDS was implemented before the bug26807
2600 * workaround, thus the latter must be unavailable in this fw
2601 */
2602 nic_data->workaround_26807 = false;
2603 rc = 0;
2604 } else if (rc) {
8127d661 2605 goto fail;
832dc9ed
EC		 2606 } else {
2607 nic_data->workaround_26807 =
2608 !!(enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807);
2609
2610 if (implemented & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807 &&
2611 !nic_data->workaround_26807) {
5a55a72a
DP		 2612 unsigned int flags;
2613
34ccfe6f
DP		 2614 rc = efx_mcdi_set_workaround(efx,
2615 MC_CMD_WORKAROUND_BUG26807,
5a55a72a
DP		 2616 true, &flags);
2617
2618 if (!rc) {
2619 if (flags &
2620 1 << MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN) {
2621 netif_info(efx, drv, efx->net_dev,
2622 "other functions on NIC have been reset\n");
abd86a55
DP		 2623
2624 /* With MCFW v4.6.x and earlier, the
2625 * boot count will have incremented,
2626 * so re-read the warm_boot_count
2627 * value now to ensure this function
2628 * doesn't think it has changed next
2629 * time it checks.
2630 */
2631 rc = efx_ef10_get_warm_boot_count(efx);
2632 if (rc >= 0) {
2633 nic_data->warm_boot_count = rc;
2634 rc = 0;
2635 }
5a55a72a 2636 }
832dc9ed 2637 nic_data->workaround_26807 = true;
5a55a72a 2638 } else if (rc == -EPERM) {
832dc9ed 2639 rc = 0;
5a55a72a 2640 }
832dc9ed 2641 }
46e612b0
DP		 2642 }
2643
2644 if (!rc)
2645 return 0;
8127d661
BH		 2646
2647fail:
46e612b0
DP		 2648 efx_ef10_ev_fini(channel);
2649 return rc;
8127d661
BH		 2650}
2651
2652static void efx_ef10_ev_remove(struct efx_channel *channel)
2653{
2654 efx_nic_free_buffer(channel->efx, &channel->eventq.buf);
2655}
2656
2657static void efx_ef10_handle_rx_wrong_queue(struct efx_rx_queue *rx_queue,
2658 unsigned int rx_queue_label)
2659{
2660 struct efx_nic *efx = rx_queue->efx;
2661
2662 netif_info(efx, hw, efx->net_dev,
2663 "rx event arrived on queue %d labeled as queue %u\n",
2664 efx_rx_queue_index(rx_queue), rx_queue_label);
2665
2666 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
2667}
2668
2669static void
2670efx_ef10_handle_rx_bad_lbits(struct efx_rx_queue *rx_queue,
2671 unsigned int actual, unsigned int expected)
2672{
2673 unsigned int dropped = (actual - expected) & rx_queue->ptr_mask;
2674 struct efx_nic *efx = rx_queue->efx;
2675
2676 netif_info(efx, hw, efx->net_dev,
2677 "dropped %d events (index=%d expected=%d)\n",
2678 dropped, actual, expected);
2679
2680 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
2681}
2682
2683/* partially received RX was aborted. clean up. */
2684static void efx_ef10_handle_rx_abort(struct efx_rx_queue *rx_queue)
2685{
2686 unsigned int rx_desc_ptr;
2687
8127d661
BH		 2688 netif_dbg(rx_queue->efx, hw, rx_queue->efx->net_dev,
2689 "scattered RX aborted (dropping %u buffers)\n",
2690 rx_queue->scatter_n);
2691
2692 rx_desc_ptr = rx_queue->removed_count & rx_queue->ptr_mask;
2693
2694 efx_rx_packet(rx_queue, rx_desc_ptr, rx_queue->scatter_n,
2695 0, EFX_RX_PKT_DISCARD);
2696
2697 rx_queue->removed_count += rx_queue->scatter_n;
2698 rx_queue->scatter_n = 0;
2699 rx_queue->scatter_len = 0;
2700 ++efx_rx_queue_channel(rx_queue)->n_rx_nodesc_trunc;
2701}
2702
2703static int efx_ef10_handle_rx_event(struct efx_channel *channel,
2704 const efx_qword_t *event)
2705{
2706 unsigned int rx_bytes, next_ptr_lbits, rx_queue_label, rx_l4_class;
2707 unsigned int n_descs, n_packets, i;
2708 struct efx_nic *efx = channel->efx;
2709 struct efx_rx_queue *rx_queue;
2710 bool rx_cont;
2711 u16 flags = 0;
2712
2713 if (unlikely(ACCESS_ONCE(efx->reset_pending)))
2714 return 0;
2715
2716 /* Basic packet information */
2717 rx_bytes = EFX_QWORD_FIELD(*event, ESF_DZ_RX_BYTES);
2718 next_ptr_lbits = EFX_QWORD_FIELD(*event, ESF_DZ_RX_DSC_PTR_LBITS);
2719 rx_queue_label = EFX_QWORD_FIELD(*event, ESF_DZ_RX_QLABEL);
2720 rx_l4_class = EFX_QWORD_FIELD(*event, ESF_DZ_RX_L4_CLASS);
2721 rx_cont = EFX_QWORD_FIELD(*event, ESF_DZ_RX_CONT);
2722
48ce5634
BH		 2723 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_DROP_EVENT))
2724 netdev_WARN(efx->net_dev, "saw RX_DROP_EVENT: event="
2725 EFX_QWORD_FMT "\n",
2726 EFX_QWORD_VAL(*event));
8127d661
BH		 2727
2728 rx_queue = efx_channel_get_rx_queue(channel);
2729
2730 if (unlikely(rx_queue_label != efx_rx_queue_index(rx_queue)))
2731 efx_ef10_handle_rx_wrong_queue(rx_queue, rx_queue_label);
2732
2733 n_descs = ((next_ptr_lbits - rx_queue->removed_count) &
2734 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
2735
2736 if (n_descs != rx_queue->scatter_n + 1) {
92a04168
BH		 2737 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2738
8127d661
BH		 2739 /* detect rx abort */
2740 if (unlikely(n_descs == rx_queue->scatter_n)) {
48ce5634
BH		 2741 if (rx_queue->scatter_n == 0 || rx_bytes != 0)
2742 netdev_WARN(efx->net_dev,
2743 "invalid RX abort: scatter_n=%u event="
2744 EFX_QWORD_FMT "\n",
2745 rx_queue->scatter_n,
2746 EFX_QWORD_VAL(*event));
8127d661
BH		 2747 efx_ef10_handle_rx_abort(rx_queue);
2748 return 0;
2749 }
2750
92a04168
BH		 2751 /* Check that RX completion merging is valid, i.e.
2752 * the current firmware supports it and this is a
2753 * non-scattered packet.
2754 */
2755 if (!(nic_data->datapath_caps &
2756 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN)) ||
2757 rx_queue->scatter_n != 0 || rx_cont) {
8127d661
BH		 2758 efx_ef10_handle_rx_bad_lbits(
2759 rx_queue, next_ptr_lbits,
2760 (rx_queue->removed_count +
2761 rx_queue->scatter_n + 1) &
2762 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
2763 return 0;
2764 }
2765
2766 /* Merged completion for multiple non-scattered packets */
2767 rx_queue->scatter_n = 1;
2768 rx_queue->scatter_len = 0;
2769 n_packets = n_descs;
2770 ++channel->n_rx_merge_events;
2771 channel->n_rx_merge_packets += n_packets;
2772 flags |= EFX_RX_PKT_PREFIX_LEN;
2773 } else {
2774 ++rx_queue->scatter_n;
2775 rx_queue->scatter_len += rx_bytes;
2776 if (rx_cont)
2777 return 0;
2778 n_packets = 1;
2779 }
2780
2781 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_ECRC_ERR)))
2782 flags |= EFX_RX_PKT_DISCARD;
2783
2784 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_IPCKSUM_ERR))) {
2785 channel->n_rx_ip_hdr_chksum_err += n_packets;
2786 } else if (unlikely(EFX_QWORD_FIELD(*event,
2787 ESF_DZ_RX_TCPUDP_CKSUM_ERR))) {
2788 channel->n_rx_tcp_udp_chksum_err += n_packets;
2789 } else if (rx_l4_class == ESE_DZ_L4_CLASS_TCP ||
2790 rx_l4_class == ESE_DZ_L4_CLASS_UDP) {
2791 flags |= EFX_RX_PKT_CSUMMED;
2792 }
2793
2794 if (rx_l4_class == ESE_DZ_L4_CLASS_TCP)
2795 flags |= EFX_RX_PKT_TCP;
2796
2797 channel->irq_mod_score += 2 * n_packets;
2798
2799 /* Handle received packet(s) */
2800 for (i = 0; i < n_packets; i++) {
2801 efx_rx_packet(rx_queue,
2802 rx_queue->removed_count & rx_queue->ptr_mask,
2803 rx_queue->scatter_n, rx_queue->scatter_len,
2804 flags);
2805 rx_queue->removed_count += rx_queue->scatter_n;
2806 }
2807
2808 rx_queue->scatter_n = 0;
2809 rx_queue->scatter_len = 0;
2810
2811 return n_packets;
2812}
2813
2814static int
2815efx_ef10_handle_tx_event(struct efx_channel *channel, efx_qword_t *event)
2816{
2817 struct efx_nic *efx = channel->efx;
2818 struct efx_tx_queue *tx_queue;
2819 unsigned int tx_ev_desc_ptr;
2820 unsigned int tx_ev_q_label;
2821 int tx_descs = 0;
2822
2823 if (unlikely(ACCESS_ONCE(efx->reset_pending)))
2824 return 0;
2825
2826 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_TX_DROP_EVENT)))
2827 return 0;
2828
2829 /* Transmit completion */
2830 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, ESF_DZ_TX_DESCR_INDX);
2831 tx_ev_q_label = EFX_QWORD_FIELD(*event, ESF_DZ_TX_QLABEL);
2832 tx_queue = efx_channel_get_tx_queue(channel,
2833 tx_ev_q_label % EFX_TXQ_TYPES);
2834 tx_descs = ((tx_ev_desc_ptr + 1 - tx_queue->read_count) &
2835 tx_queue->ptr_mask);
2836 efx_xmit_done(tx_queue, tx_ev_desc_ptr & tx_queue->ptr_mask);
2837
2838 return tx_descs;
2839}
2840
2841static void
2842efx_ef10_handle_driver_event(struct efx_channel *channel, efx_qword_t *event)
2843{
2844 struct efx_nic *efx = channel->efx;
2845 int subcode;
2846
2847 subcode = EFX_QWORD_FIELD(*event, ESF_DZ_DRV_SUB_CODE);
2848
2849 switch (subcode) {
2850 case ESE_DZ_DRV_TIMER_EV:
2851 case ESE_DZ_DRV_WAKE_UP_EV:
2852 break;
2853 case ESE_DZ_DRV_START_UP_EV:
2854 /* event queue init complete. ok. */
2855 break;
2856 default:
2857 netif_err(efx, hw, efx->net_dev,
2858 "channel %d unknown driver event type %d"
2859 " (data " EFX_QWORD_FMT ")\n",
2860 channel->channel, subcode,
2861 EFX_QWORD_VAL(*event));
2862
2863 }
2864}
2865
2866static void efx_ef10_handle_driver_generated_event(struct efx_channel *channel,
2867 efx_qword_t *event)
2868{
2869 struct efx_nic *efx = channel->efx;
2870 u32 subcode;
2871
2872 subcode = EFX_QWORD_FIELD(*event, EFX_DWORD_0);
2873
2874 switch (subcode) {
2875 case EFX_EF10_TEST:
2876 channel->event_test_cpu = raw_smp_processor_id();
2877 break;
2878 case EFX_EF10_REFILL:
2879 /* The queue must be empty, so we won't receive any rx
2880 * events, so efx_process_channel() won't refill the
2881 * queue. Refill it here
2882 */
cce28794 2883 efx_fast_push_rx_descriptors(&channel->rx_queue, true);
8127d661
BH		 2884 break;
2885 default:
2886 netif_err(efx, hw, efx->net_dev,
2887 "channel %d unknown driver event type %u"
2888 " (data " EFX_QWORD_FMT ")\n",
2889 channel->channel, (unsigned) subcode,
2890 EFX_QWORD_VAL(*event));
2891 }
2892}
2893
2894static int efx_ef10_ev_process(struct efx_channel *channel, int quota)
2895{
2896 struct efx_nic *efx = channel->efx;
2897 efx_qword_t event, *p_event;
2898 unsigned int read_ptr;
2899 int ev_code;
2900 int tx_descs = 0;
2901 int spent = 0;
2902
75363a46
EB		 2903 if (quota <= 0)
2904 return spent;
2905
8127d661
BH		 2906 read_ptr = channel->eventq_read_ptr;
2907
2908 for (;;) {
2909 p_event = efx_event(channel, read_ptr);
2910 event = *p_event;
2911
2912 if (!efx_event_present(&event))
2913 break;
2914
2915 EFX_SET_QWORD(*p_event);
2916
2917 ++read_ptr;
2918
2919 ev_code = EFX_QWORD_FIELD(event, ESF_DZ_EV_CODE);
2920
2921 netif_vdbg(efx, drv, efx->net_dev,
2922 "processing event on %d " EFX_QWORD_FMT "\n",
2923 channel->channel, EFX_QWORD_VAL(event));
2924
2925 switch (ev_code) {
2926 case ESE_DZ_EV_CODE_MCDI_EV:
2927 efx_mcdi_process_event(channel, &event);
2928 break;
2929 case ESE_DZ_EV_CODE_RX_EV:
2930 spent += efx_ef10_handle_rx_event(channel, &event);
2931 if (spent >= quota) {
2932 /* XXX can we split a merged event to
2933 * avoid going over-quota?
2934 */
2935 spent = quota;
2936 goto out;
2937 }
2938 break;
2939 case ESE_DZ_EV_CODE_TX_EV:
2940 tx_descs += efx_ef10_handle_tx_event(channel, &event);
2941 if (tx_descs > efx->txq_entries) {
2942 spent = quota;
2943 goto out;
2944 } else if (++spent == quota) {
2945 goto out;
2946 }
2947 break;
2948 case ESE_DZ_EV_CODE_DRIVER_EV:
2949 efx_ef10_handle_driver_event(channel, &event);
2950 if (++spent == quota)
2951 goto out;
2952 break;
2953 case EFX_EF10_DRVGEN_EV:
2954 efx_ef10_handle_driver_generated_event(channel, &event);
2955 break;
2956 default:
2957 netif_err(efx, hw, efx->net_dev,
2958 "channel %d unknown event type %d"
2959 " (data " EFX_QWORD_FMT ")\n",
2960 channel->channel, ev_code,
2961 EFX_QWORD_VAL(event));
2962 }
2963 }
2964
2965out:
2966 channel->eventq_read_ptr = read_ptr;
2967 return spent;
2968}
2969
2970static void efx_ef10_ev_read_ack(struct efx_channel *channel)
2971{
2972 struct efx_nic *efx = channel->efx;
2973 efx_dword_t rptr;
2974
2975 if (EFX_EF10_WORKAROUND_35388(efx)) {
2976 BUILD_BUG_ON(EFX_MIN_EVQ_SIZE <
2977 (1 << ERF_DD_EVQ_IND_RPTR_WIDTH));
2978 BUILD_BUG_ON(EFX_MAX_EVQ_SIZE >
2979 (1 << 2 * ERF_DD_EVQ_IND_RPTR_WIDTH));
2980
2981 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
2982 EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH,
2983 ERF_DD_EVQ_IND_RPTR,
2984 (channel->eventq_read_ptr &
2985 channel->eventq_mask) >>
2986 ERF_DD_EVQ_IND_RPTR_WIDTH);
2987 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
2988 channel->channel);
2989 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
2990 EFE_DD_EVQ_IND_RPTR_FLAGS_LOW,
2991 ERF_DD_EVQ_IND_RPTR,
2992 channel->eventq_read_ptr &
2993 ((1 << ERF_DD_EVQ_IND_RPTR_WIDTH) - 1));
2994 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
2995 channel->channel);
2996 } else {
2997 EFX_POPULATE_DWORD_1(rptr, ERF_DZ_EVQ_RPTR,
2998 channel->eventq_read_ptr &
2999 channel->eventq_mask);
3000 efx_writed_page(efx, &rptr, ER_DZ_EVQ_RPTR, channel->channel);
3001 }
3002}
3003
3004static void efx_ef10_ev_test_generate(struct efx_channel *channel)
3005{
3006 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
3007 struct efx_nic *efx = channel->efx;
3008 efx_qword_t event;
3009 int rc;
3010
3011 EFX_POPULATE_QWORD_2(event,
3012 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
3013 ESF_DZ_EV_DATA, EFX_EF10_TEST);
3014
3015 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
3016
3017 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
3018 * already swapped the data to little-endian order.
3019 */
3020 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
3021 sizeof(efx_qword_t));
3022
3023 rc = efx_mcdi_rpc(efx, MC_CMD_DRIVER_EVENT, inbuf, sizeof(inbuf),
3024 NULL, 0, NULL);
3025 if (rc != 0)
3026 goto fail;
3027
3028 return;
3029
3030fail:
3031 WARN_ON(true);
3032 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
3033}
3034
3035void efx_ef10_handle_drain_event(struct efx_nic *efx)
3036{
3037 if (atomic_dec_and_test(&efx->active_queues))
3038 wake_up(&efx->flush_wq);
3039
3040 WARN_ON(atomic_read(&efx->active_queues) < 0);
3041}
3042
3043static int efx_ef10_fini_dmaq(struct efx_nic *efx)
3044{
3045 struct efx_ef10_nic_data *nic_data = efx->nic_data;
3046 struct efx_channel *channel;
3047 struct efx_tx_queue *tx_queue;
3048 struct efx_rx_queue *rx_queue;
3049 int pending;
3050
3051 /* If the MC has just rebooted, the TX/RX queues will have already been
3052 * torn down, but efx->active_queues needs to be set to zero.
3053 */
3054 if (nic_data->must_realloc_vis) {
3055 atomic_set(&efx->active_queues, 0);
3056 return 0;
3057 }
3058
3059 /* Do not attempt to write to the NIC during EEH recovery */
3060 if (efx->state != STATE_RECOVERY) {
3061 efx_for_each_channel(channel, efx) {
3062 efx_for_each_channel_rx_queue(rx_queue, channel)
3063 efx_ef10_rx_fini(rx_queue);
3064 efx_for_each_channel_tx_queue(tx_queue, channel)
3065 efx_ef10_tx_fini(tx_queue);
3066 }
3067
3068 wait_event_timeout(efx->flush_wq,
3069 atomic_read(&efx->active_queues) == 0,
3070 msecs_to_jiffies(EFX_MAX_FLUSH_TIME));
3071 pending = atomic_read(&efx->active_queues);
3072 if (pending) {
3073 netif_err(efx, hw, efx->net_dev, "failed to flush %d queues\n",
3074 pending);
3075 return -ETIMEDOUT;
3076 }
3077 }
3078
3079 return 0;
3080}
3081
e283546c
EC		 3082static void efx_ef10_prepare_flr(struct efx_nic *efx)
3083{
3084 atomic_set(&efx->active_queues, 0);
3085}
3086
8127d661
BH		 3087static bool efx_ef10_filter_equal(const struct efx_filter_spec *left,
3088 const struct efx_filter_spec *right)
3089{
3090 if ((left->match_flags ^ right->match_flags) |
3091 ((left->flags ^ right->flags) &
3092 (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)))
3093 return false;
3094
3095 return memcmp(&left->outer_vid, &right->outer_vid,
3096 sizeof(struct efx_filter_spec) -
3097 offsetof(struct efx_filter_spec, outer_vid)) == 0;
3098}
3099
3100static unsigned int efx_ef10_filter_hash(const struct efx_filter_spec *spec)
3101{
3102 BUILD_BUG_ON(offsetof(struct efx_filter_spec, outer_vid) & 3);
3103 return jhash2((const u32 *)&spec->outer_vid,
3104 (sizeof(struct efx_filter_spec) -
3105 offsetof(struct efx_filter_spec, outer_vid)) / 4,
3106 0);
3107 /* XXX should we randomise the initval? */
3108}
3109
3110/* Decide whether a filter should be exclusive or else should allow
3111 * delivery to additional recipients. Currently we decide that
3112 * filters for specific local unicast MAC and IP addresses are
3113 * exclusive.
3114 */
3115static bool efx_ef10_filter_is_exclusive(const struct efx_filter_spec *spec)
3116{
3117 if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC &&
3118 !is_multicast_ether_addr(spec->loc_mac))
3119 return true;
3120
3121 if ((spec->match_flags &
3122 (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) ==
3123 (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) {
3124 if (spec->ether_type == htons(ETH_P_IP) &&
3125 !ipv4_is_multicast(spec->loc_host[0]))
3126 return true;
3127 if (spec->ether_type == htons(ETH_P_IPV6) &&
3128 ((const u8 *)spec->loc_host)[0] != 0xff)
3129 return true;
3130 }
3131
3132 return false;
3133}
3134
3135static struct efx_filter_spec *
3136efx_ef10_filter_entry_spec(const struct efx_ef10_filter_table *table,
3137 unsigned int filter_idx)
3138{
3139 return (struct efx_filter_spec *)(table->entry[filter_idx].spec &
3140 ~EFX_EF10_FILTER_FLAGS);
3141}
3142
3143static unsigned int
3144efx_ef10_filter_entry_flags(const struct efx_ef10_filter_table *table,
3145 unsigned int filter_idx)
3146{
3147 return table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAGS;
3148}
3149
3150static void
3151efx_ef10_filter_set_entry(struct efx_ef10_filter_table *table,
3152 unsigned int filter_idx,
3153 const struct efx_filter_spec *spec,
3154 unsigned int flags)
3155{
3156 table->entry[filter_idx].spec = (unsigned long)spec | flags;
3157}
3158
3159static void efx_ef10_filter_push_prep(struct efx_nic *efx,
3160 const struct efx_filter_spec *spec,
3161 efx_dword_t *inbuf, u64 handle,
3162 bool replacing)
3163{
3164 struct efx_ef10_nic_data *nic_data = efx->nic_data;
dcb4123c 3165 u32 flags = spec->flags;
8127d661
BH		 3166
3167 memset(inbuf, 0, MC_CMD_FILTER_OP_IN_LEN);
3168
dcb4123c
JC		 3169 /* Remove RSS flag if we don't have an RSS context. */
3170 if (flags & EFX_FILTER_FLAG_RX_RSS &&
3171 spec->rss_context == EFX_FILTER_RSS_CONTEXT_DEFAULT &&
3172 nic_data->rx_rss_context == EFX_EF10_RSS_CONTEXT_INVALID)
3173 flags &= ~EFX_FILTER_FLAG_RX_RSS;
3174
8127d661
BH		 3175 if (replacing) {
3176 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3177 MC_CMD_FILTER_OP_IN_OP_REPLACE);
3178 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, handle);
3179 } else {
3180 u32 match_fields = 0;
3181
3182 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3183 efx_ef10_filter_is_exclusive(spec) ?
3184 MC_CMD_FILTER_OP_IN_OP_INSERT :
3185 MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE);
3186
3187 /* Convert match flags and values. Unlike almost
3188 * everything else in MCDI, these fields are in
3189 * network byte order.
3190 */
3191 if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC_IG)
3192 match_fields |=
3193 is_multicast_ether_addr(spec->loc_mac) ?
3194 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN :
3195 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN;
3196#define COPY_FIELD(gen_flag, gen_field, mcdi_field) \
3197 if (spec->match_flags & EFX_FILTER_MATCH_ ## gen_flag) { \
3198 match_fields |= \
3199 1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \
3200 mcdi_field ## _LBN; \
3201 BUILD_BUG_ON( \
3202 MC_CMD_FILTER_OP_IN_ ## mcdi_field ## _LEN < \
3203 sizeof(spec->gen_field)); \
3204 memcpy(MCDI_PTR(inbuf, FILTER_OP_IN_ ## mcdi_field), \
3205 &spec->gen_field, sizeof(spec->gen_field)); \
3206 }
3207 COPY_FIELD(REM_HOST, rem_host, SRC_IP);
3208 COPY_FIELD(LOC_HOST, loc_host, DST_IP);
3209 COPY_FIELD(REM_MAC, rem_mac, SRC_MAC);
3210 COPY_FIELD(REM_PORT, rem_port, SRC_PORT);
3211 COPY_FIELD(LOC_MAC, loc_mac, DST_MAC);
3212 COPY_FIELD(LOC_PORT, loc_port, DST_PORT);
3213 COPY_FIELD(ETHER_TYPE, ether_type, ETHER_TYPE);
3214 COPY_FIELD(INNER_VID, inner_vid, INNER_VLAN);
3215 COPY_FIELD(OUTER_VID, outer_vid, OUTER_VLAN);
3216 COPY_FIELD(IP_PROTO, ip_proto, IP_PROTO);
3217#undef COPY_FIELD
3218 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_MATCH_FIELDS,
3219 match_fields);
3220 }
3221
45b2449e 3222 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_PORT_ID, nic_data->vport_id);
8127d661
BH		 3223 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_DEST,
3224 spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ?
3225 MC_CMD_FILTER_OP_IN_RX_DEST_DROP :
3226 MC_CMD_FILTER_OP_IN_RX_DEST_HOST);
e3d36293 3227 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DOMAIN, 0);
8127d661
BH		 3228 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DEST,
3229 MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT);
a0bc3487
BH		 3230 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_QUEUE,
3231 spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ?
3232 0 : spec->dmaq_id);
8127d661 3233 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_MODE,
dcb4123c 3234 (flags & EFX_FILTER_FLAG_RX_RSS) ?
8127d661
BH		 3235 MC_CMD_FILTER_OP_IN_RX_MODE_RSS :
3236 MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE);
dcb4123c 3237 if (flags & EFX_FILTER_FLAG_RX_RSS)
8127d661
BH		 3238 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_CONTEXT,
3239 spec->rss_context !=
3240 EFX_FILTER_RSS_CONTEXT_DEFAULT ?
3241 spec->rss_context : nic_data->rx_rss_context);
3242}
3243
3244static int efx_ef10_filter_push(struct efx_nic *efx,
3245 const struct efx_filter_spec *spec,
3246 u64 *handle, bool replacing)
3247{
3248 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
3249 MCDI_DECLARE_BUF(outbuf, MC_CMD_FILTER_OP_OUT_LEN);
3250 int rc;
3251
3252 efx_ef10_filter_push_prep(efx, spec, inbuf, *handle, replacing);
3253 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
3254 outbuf, sizeof(outbuf), NULL);
3255 if (rc == 0)
3256 *handle = MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE);
065e64c4
BH		 3257 if (rc == -ENOSPC)
3258 rc = -EBUSY; /* to match efx_farch_filter_insert() */
8127d661
BH		 3259 return rc;
3260}
3261
7ac0dd9d 3262static u32 efx_ef10_filter_mcdi_flags_from_spec(const struct efx_filter_spec *spec)
8127d661 3263{
7ac0dd9d
AR		 3264 unsigned int match_flags = spec->match_flags;
3265 u32 mcdi_flags = 0;
3266
3267 if (match_flags & EFX_FILTER_MATCH_LOC_MAC_IG) {
3268 match_flags &= ~EFX_FILTER_MATCH_LOC_MAC_IG;
3269 mcdi_flags |=
3270 is_multicast_ether_addr(spec->loc_mac) ?
3271 (1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN) :
3272 (1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN);
3273 }
3274
3275#define MAP_FILTER_TO_MCDI_FLAG(gen_flag, mcdi_field) { \
3276 unsigned int old_match_flags = match_flags; \
3277 match_flags &= ~EFX_FILTER_MATCH_ ## gen_flag; \
3278 if (match_flags != old_match_flags) \
3279 mcdi_flags |= \
3280 (1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \
3281 mcdi_field ## _LBN); \
3282 }
3283 MAP_FILTER_TO_MCDI_FLAG(REM_HOST, SRC_IP);
3284 MAP_FILTER_TO_MCDI_FLAG(LOC_HOST, DST_IP);
3285 MAP_FILTER_TO_MCDI_FLAG(REM_MAC, SRC_MAC);
3286 MAP_FILTER_TO_MCDI_FLAG(REM_PORT, SRC_PORT);
3287 MAP_FILTER_TO_MCDI_FLAG(LOC_MAC, DST_MAC);
3288 MAP_FILTER_TO_MCDI_FLAG(LOC_PORT, DST_PORT);
3289 MAP_FILTER_TO_MCDI_FLAG(ETHER_TYPE, ETHER_TYPE);
3290 MAP_FILTER_TO_MCDI_FLAG(INNER_VID, INNER_VLAN);
3291 MAP_FILTER_TO_MCDI_FLAG(OUTER_VID, OUTER_VLAN);
3292 MAP_FILTER_TO_MCDI_FLAG(IP_PROTO, IP_PROTO);
3293#undef MAP_FILTER_TO_MCDI_FLAG
3294
3295 /* Did we map them all? */
3296 WARN_ON_ONCE(match_flags);
3297
3298 return mcdi_flags;
3299}
3300
3301static int efx_ef10_filter_pri(struct efx_ef10_filter_table *table,
3302 const struct efx_filter_spec *spec)
3303{
3304 u32 mcdi_flags = efx_ef10_filter_mcdi_flags_from_spec(spec);
8127d661
BH		 3305 unsigned int match_pri;
3306
3307 for (match_pri = 0;
3308 match_pri < table->rx_match_count;
3309 match_pri++)
7ac0dd9d 3310 if (table->rx_match_mcdi_flags[match_pri] == mcdi_flags)
8127d661
BH		 3311 return match_pri;
3312
3313 return -EPROTONOSUPPORT;
3314}
3315
3316static s32 efx_ef10_filter_insert(struct efx_nic *efx,
3317 struct efx_filter_spec *spec,
3318 bool replace_equal)
3319{
3320 struct efx_ef10_filter_table *table = efx->filter_state;
3321 DECLARE_BITMAP(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
3322 struct efx_filter_spec *saved_spec;
3323 unsigned int match_pri, hash;
3324 unsigned int priv_flags;
3325 bool replacing = false;
3326 int ins_index = -1;
3327 DEFINE_WAIT(wait);
3328 bool is_mc_recip;
3329 s32 rc;
3330
3331 /* For now, only support RX filters */
3332 if ((spec->flags & (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)) !=
3333 EFX_FILTER_FLAG_RX)
3334 return -EINVAL;
3335
7ac0dd9d 3336 rc = efx_ef10_filter_pri(table, spec);
8127d661
BH		 3337 if (rc < 0)
3338 return rc;
3339 match_pri = rc;
3340
3341 hash = efx_ef10_filter_hash(spec);
3342 is_mc_recip = efx_filter_is_mc_recipient(spec);
3343 if (is_mc_recip)
3344 bitmap_zero(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
3345
3346 /* Find any existing filters with the same match tuple or
3347 * else a free slot to insert at. If any of them are busy,
3348 * we have to wait and retry.
3349 */
3350 for (;;) {
3351 unsigned int depth = 1;
3352 unsigned int i;
3353
3354 spin_lock_bh(&efx->filter_lock);
3355
3356 for (;;) {
3357 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
3358 saved_spec = efx_ef10_filter_entry_spec(table, i);
3359
3360 if (!saved_spec) {
3361 if (ins_index < 0)
3362 ins_index = i;
3363 } else if (efx_ef10_filter_equal(spec, saved_spec)) {
3364 if (table->entry[i].spec &
3365 EFX_EF10_FILTER_FLAG_BUSY)
3366 break;
3367 if (spec->priority < saved_spec->priority &&
7665d1ab 3368 spec->priority != EFX_FILTER_PRI_AUTO) {
8127d661
BH		 3369 rc = -EPERM;
3370 goto out_unlock;
3371 }
3372 if (!is_mc_recip) {
3373 /* This is the only one */
3374 if (spec->priority ==
3375 saved_spec->priority &&
3376 !replace_equal) {
3377 rc = -EEXIST;
3378 goto out_unlock;
3379 }
3380 ins_index = i;
3381 goto found;
3382 } else if (spec->priority >
3383 saved_spec->priority ||
3384 (spec->priority ==
3385 saved_spec->priority &&
3386 replace_equal)) {
3387 if (ins_index < 0)
3388 ins_index = i;
3389 else
3390 __set_bit(depth, mc_rem_map);
3391 }
3392 }
3393
3394 /* Once we reach the maximum search depth, use
3395 * the first suitable slot or return -EBUSY if
3396 * there was none
3397 */
3398 if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) {
3399 if (ins_index < 0) {
3400 rc = -EBUSY;
3401 goto out_unlock;
3402 }
3403 goto found;
3404 }
3405
3406 ++depth;
3407 }
3408
3409 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE);
3410 spin_unlock_bh(&efx->filter_lock);
3411 schedule();
3412 }
3413
3414found:
3415 /* Create a software table entry if necessary, and mark it
3416 * busy. We might yet fail to insert, but any attempt to
3417 * insert a conflicting filter while we're waiting for the
3418 * firmware must find the busy entry.
3419 */
3420 saved_spec = efx_ef10_filter_entry_spec(table, ins_index);
3421 if (saved_spec) {
7665d1ab
BH		 3422 if (spec->priority == EFX_FILTER_PRI_AUTO &&
3423 saved_spec->priority >= EFX_FILTER_PRI_AUTO) {
8127d661 3424 /* Just make sure it won't be removed */
7665d1ab
BH		 3425 if (saved_spec->priority > EFX_FILTER_PRI_AUTO)
3426 saved_spec->flags |= EFX_FILTER_FLAG_RX_OVER_AUTO;
8127d661 3427 table->entry[ins_index].spec &=
b59e6ef8 3428 ~EFX_EF10_FILTER_FLAG_AUTO_OLD;
8127d661
BH		 3429 rc = ins_index;
3430 goto out_unlock;
3431 }
3432 replacing = true;
3433 priv_flags = efx_ef10_filter_entry_flags(table, ins_index);
3434 } else {
3435 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC);
3436 if (!saved_spec) {
3437 rc = -ENOMEM;
3438 goto out_unlock;
3439 }
3440 *saved_spec = *spec;
3441 priv_flags = 0;
3442 }
3443 efx_ef10_filter_set_entry(table, ins_index, saved_spec,
3444 priv_flags | EFX_EF10_FILTER_FLAG_BUSY);
3445
3446 /* Mark lower-priority multicast recipients busy prior to removal */
3447 if (is_mc_recip) {
3448 unsigned int depth, i;
3449
3450 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
3451 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
3452 if (test_bit(depth, mc_rem_map))
3453 table->entry[i].spec |=
3454 EFX_EF10_FILTER_FLAG_BUSY;
3455 }
3456 }
3457
3458 spin_unlock_bh(&efx->filter_lock);
3459
3460 rc = efx_ef10_filter_push(efx, spec, &table->entry[ins_index].handle,
3461 replacing);
3462
3463 /* Finalise the software table entry */
3464 spin_lock_bh(&efx->filter_lock);
3465 if (rc == 0) {
3466 if (replacing) {
3467 /* Update the fields that may differ */
7665d1ab
BH		 3468 if (saved_spec->priority == EFX_FILTER_PRI_AUTO)
3469 saved_spec->flags |=
3470 EFX_FILTER_FLAG_RX_OVER_AUTO;
8127d661 3471 saved_spec->priority = spec->priority;
7665d1ab 3472 saved_spec->flags &= EFX_FILTER_FLAG_RX_OVER_AUTO;
8127d661
BH		 3473 saved_spec->flags |= spec->flags;
3474 saved_spec->rss_context = spec->rss_context;
3475 saved_spec->dmaq_id = spec->dmaq_id;
3476 }
3477 } else if (!replacing) {
3478 kfree(saved_spec);
3479 saved_spec = NULL;
3480 }
3481 efx_ef10_filter_set_entry(table, ins_index, saved_spec, priv_flags);
3482
3483 /* Remove and finalise entries for lower-priority multicast
3484 * recipients
3485 */
3486 if (is_mc_recip) {
3487 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
3488 unsigned int depth, i;
3489
3490 memset(inbuf, 0, sizeof(inbuf));
3491
3492 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
3493 if (!test_bit(depth, mc_rem_map))
3494 continue;
3495
3496 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
3497 saved_spec = efx_ef10_filter_entry_spec(table, i);
3498 priv_flags = efx_ef10_filter_entry_flags(table, i);
3499
3500 if (rc == 0) {
3501 spin_unlock_bh(&efx->filter_lock);
3502 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3503 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
3504 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
3505 table->entry[i].handle);
3506 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP,
3507 inbuf, sizeof(inbuf),
3508 NULL, 0, NULL);
3509 spin_lock_bh(&efx->filter_lock);
3510 }
3511
3512 if (rc == 0) {
3513 kfree(saved_spec);
3514 saved_spec = NULL;
3515 priv_flags = 0;
3516 } else {
3517 priv_flags &= ~EFX_EF10_FILTER_FLAG_BUSY;
3518 }
3519 efx_ef10_filter_set_entry(table, i, saved_spec,
3520 priv_flags);
3521 }
3522 }
3523
3524 /* If successful, return the inserted filter ID */
3525 if (rc == 0)
3526 rc = match_pri * HUNT_FILTER_TBL_ROWS + ins_index;
3527
3528 wake_up_all(&table->waitq);
3529out_unlock:
3530 spin_unlock_bh(&efx->filter_lock);
3531 finish_wait(&table->waitq, &wait);
3532 return rc;
3533}
3534
9fd8095d 3535static void efx_ef10_filter_update_rx_scatter(struct efx_nic *efx)
8127d661
BH		 3536{
3537 /* no need to do anything here on EF10 */
3538}
3539
3540/* Remove a filter.
b59e6ef8
BH		 3541 * If !by_index, remove by ID
3542 * If by_index, remove by index
8127d661
BH		 3543 * Filter ID may come from userland and must be range-checked.
3544 */
3545static int efx_ef10_filter_remove_internal(struct efx_nic *efx,
fbd79120 3546 unsigned int priority_mask,
b59e6ef8 3547 u32 filter_id, bool by_index)
8127d661
BH		 3548{
3549 unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS;
3550 struct efx_ef10_filter_table *table = efx->filter_state;
3551 MCDI_DECLARE_BUF(inbuf,
3552 MC_CMD_FILTER_OP_IN_HANDLE_OFST +
3553 MC_CMD_FILTER_OP_IN_HANDLE_LEN);
3554 struct efx_filter_spec *spec;
3555 DEFINE_WAIT(wait);
3556 int rc;
3557
3558 /* Find the software table entry and mark it busy. Don't
3559 * remove it yet; any attempt to update while we're waiting
3560 * for the firmware must find the busy entry.
3561 */
3562 for (;;) {
3563 spin_lock_bh(&efx->filter_lock);
3564 if (!(table->entry[filter_idx].spec &
3565 EFX_EF10_FILTER_FLAG_BUSY))
3566 break;
3567 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE);
3568 spin_unlock_bh(&efx->filter_lock);
3569 schedule();
3570 }
7665d1ab 3571
8127d661 3572 spec = efx_ef10_filter_entry_spec(table, filter_idx);
7665d1ab 3573 if (!spec ||
b59e6ef8 3574 (!by_index &&
7ac0dd9d 3575 efx_ef10_filter_pri(table, spec) !=
8127d661
BH		 3576 filter_id / HUNT_FILTER_TBL_ROWS)) {
3577 rc = -ENOENT;
3578 goto out_unlock;
3579 }
7665d1ab
BH		 3580
3581 if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO &&
fbd79120 3582 priority_mask == (1U << EFX_FILTER_PRI_AUTO)) {
7665d1ab
BH		 3583 /* Just remove flags */
3584 spec->flags &= ~EFX_FILTER_FLAG_RX_OVER_AUTO;
b59e6ef8 3585 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_AUTO_OLD;
7665d1ab
BH		 3586 rc = 0;
3587 goto out_unlock;
3588 }
3589
fbd79120 3590 if (!(priority_mask & (1U << spec->priority))) {
7665d1ab
BH		 3591 rc = -ENOENT;
3592 goto out_unlock;
3593 }
3594
8127d661
BH		 3595 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
3596 spin_unlock_bh(&efx->filter_lock);
3597
7665d1ab 3598 if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO) {
b59e6ef8 3599 /* Reset to an automatic filter */
8127d661
BH		 3600
3601 struct efx_filter_spec new_spec = *spec;
3602
7665d1ab 3603 new_spec.priority = EFX_FILTER_PRI_AUTO;
8127d661 3604 new_spec.flags = (EFX_FILTER_FLAG_RX |
f1c2ef40
BK		 3605 (efx_rss_enabled(efx) ?
3606 EFX_FILTER_FLAG_RX_RSS : 0));
8127d661
BH		 3607 new_spec.dmaq_id = 0;
3608 new_spec.rss_context = EFX_FILTER_RSS_CONTEXT_DEFAULT;
3609 rc = efx_ef10_filter_push(efx, &new_spec,
3610 &table->entry[filter_idx].handle,
3611 true);
3612
3613 spin_lock_bh(&efx->filter_lock);
3614 if (rc == 0)
3615 *spec = new_spec;
3616 } else {
3617 /* Really remove the filter */
3618
3619 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3620 efx_ef10_filter_is_exclusive(spec) ?
3621 MC_CMD_FILTER_OP_IN_OP_REMOVE :
3622 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
3623 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
3624 table->entry[filter_idx].handle);
3625 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP,
3626 inbuf, sizeof(inbuf), NULL, 0, NULL);
3627
3628 spin_lock_bh(&efx->filter_lock);
3629 if (rc == 0) {
3630 kfree(spec);
3631 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
3632 }
3633 }
7665d1ab 3634
8127d661
BH		 3635 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY;
3636 wake_up_all(&table->waitq);
3637out_unlock:
3638 spin_unlock_bh(&efx->filter_lock);
3639 finish_wait(&table->waitq, &wait);
3640 return rc;
3641}
3642
3643static int efx_ef10_filter_remove_safe(struct efx_nic *efx,
3644 enum efx_filter_priority priority,
3645 u32 filter_id)
3646{
fbd79120
BH		 3647 return efx_ef10_filter_remove_internal(efx, 1U << priority,
3648 filter_id, false);
8127d661
BH		 3649}
3650
12fb0da4
EC		 3651static u32 efx_ef10_filter_get_unsafe_id(struct efx_nic *efx, u32 filter_id)
3652{
3653 return filter_id % HUNT_FILTER_TBL_ROWS;
3654}
3655
8c915620
EC		 3656static void efx_ef10_filter_remove_unsafe(struct efx_nic *efx,
3657 enum efx_filter_priority priority,
3658 u32 filter_id)
12fb0da4 3659{
8c915620
EC		 3660 if (filter_id == EFX_EF10_FILTER_ID_INVALID)
3661 return;
3662 efx_ef10_filter_remove_internal(efx, 1U << priority, filter_id, true);
12fb0da4
EC		 3663}
3664
8127d661
BH		 3665static int efx_ef10_filter_get_safe(struct efx_nic *efx,
3666 enum efx_filter_priority priority,
3667 u32 filter_id, struct efx_filter_spec *spec)
3668{
3669 unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS;
3670 struct efx_ef10_filter_table *table = efx->filter_state;
3671 const struct efx_filter_spec *saved_spec;
3672 int rc;
3673
3674 spin_lock_bh(&efx->filter_lock);
3675 saved_spec = efx_ef10_filter_entry_spec(table, filter_idx);
3676 if (saved_spec && saved_spec->priority == priority &&
7ac0dd9d 3677 efx_ef10_filter_pri(table, saved_spec) ==
8127d661
BH		 3678 filter_id / HUNT_FILTER_TBL_ROWS) {
3679 *spec = *saved_spec;
3680 rc = 0;
3681 } else {
3682 rc = -ENOENT;
3683 }
3684 spin_unlock_bh(&efx->filter_lock);
3685 return rc;
3686}
3687
fbd79120 3688static int efx_ef10_filter_clear_rx(struct efx_nic *efx,
8127d661
BH		 3689 enum efx_filter_priority priority)
3690{
fbd79120
BH		 3691 unsigned int priority_mask;
3692 unsigned int i;
3693 int rc;
3694
3695 priority_mask = (((1U << (priority + 1)) - 1) &
3696 ~(1U << EFX_FILTER_PRI_AUTO));
3697
3698 for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) {
3699 rc = efx_ef10_filter_remove_internal(efx, priority_mask,
3700 i, true);
3701 if (rc && rc != -ENOENT)
3702 return rc;
3703 }
3704
3705 return 0;
8127d661
BH		 3706}
3707
3708static u32 efx_ef10_filter_count_rx_used(struct efx_nic *efx,
3709 enum efx_filter_priority priority)
3710{
3711 struct efx_ef10_filter_table *table = efx->filter_state;
3712 unsigned int filter_idx;
3713 s32 count = 0;
3714
3715 spin_lock_bh(&efx->filter_lock);
3716 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
3717 if (table->entry[filter_idx].spec &&
3718 efx_ef10_filter_entry_spec(table, filter_idx)->priority ==
3719 priority)
3720 ++count;
3721 }
3722 spin_unlock_bh(&efx->filter_lock);
3723 return count;
3724}
3725
3726static u32 efx_ef10_filter_get_rx_id_limit(struct efx_nic *efx)
3727{
3728 struct efx_ef10_filter_table *table = efx->filter_state;
3729
3730 return table->rx_match_count * HUNT_FILTER_TBL_ROWS;
3731}
3732
3733static s32 efx_ef10_filter_get_rx_ids(struct efx_nic *efx,
3734 enum efx_filter_priority priority,
3735 u32 *buf, u32 size)
3736{
3737 struct efx_ef10_filter_table *table = efx->filter_state;
3738 struct efx_filter_spec *spec;
3739 unsigned int filter_idx;
3740 s32 count = 0;
3741
3742 spin_lock_bh(&efx->filter_lock);
3743 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
3744 spec = efx_ef10_filter_entry_spec(table, filter_idx);
3745 if (spec && spec->priority == priority) {
3746 if (count == size) {
3747 count = -EMSGSIZE;
3748 break;
3749 }
7ac0dd9d 3750 buf[count++] = (efx_ef10_filter_pri(table, spec) *
8127d661
BH		 3751 HUNT_FILTER_TBL_ROWS +
3752 filter_idx);
3753 }
3754 }
3755 spin_unlock_bh(&efx->filter_lock);
3756 return count;
3757}
3758
3759#ifdef CONFIG_RFS_ACCEL
3760
3761static efx_mcdi_async_completer efx_ef10_filter_rfs_insert_complete;
3762
3763static s32 efx_ef10_filter_rfs_insert(struct efx_nic *efx,
3764 struct efx_filter_spec *spec)
3765{
3766 struct efx_ef10_filter_table *table = efx->filter_state;
3767 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
3768 struct efx_filter_spec *saved_spec;
3769 unsigned int hash, i, depth = 1;
3770 bool replacing = false;
3771 int ins_index = -1;
3772 u64 cookie;
3773 s32 rc;
3774
3775 /* Must be an RX filter without RSS and not for a multicast
3776 * destination address (RFS only works for connected sockets).
3777 * These restrictions allow us to pass only a tiny amount of
3778 * data through to the completion function.
3779 */
3780 EFX_WARN_ON_PARANOID(spec->flags !=
3781 (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_RX_SCATTER));
3782 EFX_WARN_ON_PARANOID(spec->priority != EFX_FILTER_PRI_HINT);
3783 EFX_WARN_ON_PARANOID(efx_filter_is_mc_recipient(spec));
3784
3785 hash = efx_ef10_filter_hash(spec);
3786
3787 spin_lock_bh(&efx->filter_lock);
3788
3789 /* Find any existing filter with the same match tuple or else
3790 * a free slot to insert at. If an existing filter is busy,
3791 * we have to give up.
3792 */
3793 for (;;) {
3794 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
3795 saved_spec = efx_ef10_filter_entry_spec(table, i);
3796
3797 if (!saved_spec) {
3798 if (ins_index < 0)
3799 ins_index = i;
3800 } else if (efx_ef10_filter_equal(spec, saved_spec)) {
3801 if (table->entry[i].spec & EFX_EF10_FILTER_FLAG_BUSY) {
3802 rc = -EBUSY;
3803 goto fail_unlock;
3804 }
8127d661
BH		 3805 if (spec->priority < saved_spec->priority) {
3806 rc = -EPERM;
3807 goto fail_unlock;
3808 }
3809 ins_index = i;
3810 break;
3811 }
3812
3813 /* Once we reach the maximum search depth, use the
3814 * first suitable slot or return -EBUSY if there was
3815 * none
3816 */
3817 if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) {
3818 if (ins_index < 0) {
3819 rc = -EBUSY;
3820 goto fail_unlock;
3821 }
3822 break;
3823 }
3824
3825 ++depth;
3826 }
3827
3828 /* Create a software table entry if necessary, and mark it
3829 * busy. We might yet fail to insert, but any attempt to
3830 * insert a conflicting filter while we're waiting for the
3831 * firmware must find the busy entry.
3832 */
3833 saved_spec = efx_ef10_filter_entry_spec(table, ins_index);
3834 if (saved_spec) {
3835 replacing = true;
3836 } else {
3837 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC);
3838 if (!saved_spec) {
3839 rc = -ENOMEM;
3840 goto fail_unlock;
3841 }
3842 *saved_spec = *spec;
3843 }
3844 efx_ef10_filter_set_entry(table, ins_index, saved_spec,
3845 EFX_EF10_FILTER_FLAG_BUSY);
3846
3847 spin_unlock_bh(&efx->filter_lock);
3848
3849 /* Pack up the variables needed on completion */
3850 cookie = replacing << 31 | ins_index << 16 | spec->dmaq_id;
3851
3852 efx_ef10_filter_push_prep(efx, spec, inbuf,
3853 table->entry[ins_index].handle, replacing);
3854 efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
3855 MC_CMD_FILTER_OP_OUT_LEN,
3856 efx_ef10_filter_rfs_insert_complete, cookie);
3857
3858 return ins_index;
3859
3860fail_unlock:
3861 spin_unlock_bh(&efx->filter_lock);
3862 return rc;
3863}
3864
3865static void
3866efx_ef10_filter_rfs_insert_complete(struct efx_nic *efx, unsigned long cookie,
3867 int rc, efx_dword_t *outbuf,
3868 size_t outlen_actual)
3869{
3870 struct efx_ef10_filter_table *table = efx->filter_state;
3871 unsigned int ins_index, dmaq_id;
3872 struct efx_filter_spec *spec;
3873 bool replacing;
3874
3875 /* Unpack the cookie */
3876 replacing = cookie >> 31;
3877 ins_index = (cookie >> 16) & (HUNT_FILTER_TBL_ROWS - 1);
3878 dmaq_id = cookie & 0xffff;
3879
3880 spin_lock_bh(&efx->filter_lock);
3881 spec = efx_ef10_filter_entry_spec(table, ins_index);
3882 if (rc == 0) {
3883 table->entry[ins_index].handle =
3884 MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE);
3885 if (replacing)
3886 spec->dmaq_id = dmaq_id;
3887 } else if (!replacing) {
3888 kfree(spec);
3889 spec = NULL;
3890 }
3891 efx_ef10_filter_set_entry(table, ins_index, spec, 0);
3892 spin_unlock_bh(&efx->filter_lock);
3893
3894 wake_up_all(&table->waitq);
3895}
3896
3897static void
3898efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx,
3899 unsigned long filter_idx,
3900 int rc, efx_dword_t *outbuf,
3901 size_t outlen_actual);
3902
3903static bool efx_ef10_filter_rfs_expire_one(struct efx_nic *efx, u32 flow_id,
3904 unsigned int filter_idx)
3905{
3906 struct efx_ef10_filter_table *table = efx->filter_state;
3907 struct efx_filter_spec *spec =
3908 efx_ef10_filter_entry_spec(table, filter_idx);
3909 MCDI_DECLARE_BUF(inbuf,
3910 MC_CMD_FILTER_OP_IN_HANDLE_OFST +
3911 MC_CMD_FILTER_OP_IN_HANDLE_LEN);
3912
3913 if (!spec ||
3914 (table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAG_BUSY) ||
3915 spec->priority != EFX_FILTER_PRI_HINT ||
3916 !rps_may_expire_flow(efx->net_dev, spec->dmaq_id,
3917 flow_id, filter_idx))
3918 return false;
3919
3920 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3921 MC_CMD_FILTER_OP_IN_OP_REMOVE);
3922 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
3923 table->entry[filter_idx].handle);
3924 if (efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf), 0,
3925 efx_ef10_filter_rfs_expire_complete, filter_idx))
3926 return false;
3927
3928 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
3929 return true;
3930}
3931
3932static void
3933efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx,
3934 unsigned long filter_idx,
3935 int rc, efx_dword_t *outbuf,
3936 size_t outlen_actual)
3937{
3938 struct efx_ef10_filter_table *table = efx->filter_state;
3939 struct efx_filter_spec *spec =
3940 efx_ef10_filter_entry_spec(table, filter_idx);
3941
3942 spin_lock_bh(&efx->filter_lock);
3943 if (rc == 0) {
3944 kfree(spec);
3945 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
3946 }
3947 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY;
3948 wake_up_all(&table->waitq);
3949 spin_unlock_bh(&efx->filter_lock);
3950}
3951
3952#endif /* CONFIG_RFS_ACCEL */
3953
3954static int efx_ef10_filter_match_flags_from_mcdi(u32 mcdi_flags)
3955{
3956 int match_flags = 0;
3957
3958#define MAP_FLAG(gen_flag, mcdi_field) { \
3959 u32 old_mcdi_flags = mcdi_flags; \
3960 mcdi_flags &= ~(1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \
3961 mcdi_field ## _LBN); \
3962 if (mcdi_flags != old_mcdi_flags) \
3963 match_flags |= EFX_FILTER_MATCH_ ## gen_flag; \
3964 }
3965 MAP_FLAG(LOC_MAC_IG, UNKNOWN_UCAST_DST);
3966 MAP_FLAG(LOC_MAC_IG, UNKNOWN_MCAST_DST);
3967 MAP_FLAG(REM_HOST, SRC_IP);
3968 MAP_FLAG(LOC_HOST, DST_IP);
3969 MAP_FLAG(REM_MAC, SRC_MAC);
3970 MAP_FLAG(REM_PORT, SRC_PORT);
3971 MAP_FLAG(LOC_MAC, DST_MAC);
3972 MAP_FLAG(LOC_PORT, DST_PORT);
3973 MAP_FLAG(ETHER_TYPE, ETHER_TYPE);
3974 MAP_FLAG(INNER_VID, INNER_VLAN);
3975 MAP_FLAG(OUTER_VID, OUTER_VLAN);
3976 MAP_FLAG(IP_PROTO, IP_PROTO);
3977#undef MAP_FLAG
3978
3979 /* Did we map them all? */
3980 if (mcdi_flags)
3981 return -EINVAL;
3982
3983 return match_flags;
3984}
3985
34813fe2
AR		 3986static void efx_ef10_filter_cleanup_vlans(struct efx_nic *efx)
3987{
3988 struct efx_ef10_filter_table *table = efx->filter_state;
3989 struct efx_ef10_filter_vlan *vlan, *next_vlan;
3990
3991 /* See comment in efx_ef10_filter_table_remove() */
3992 if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
3993 return;
3994
3995 if (!table)
3996 return;
3997
3998 list_for_each_entry_safe(vlan, next_vlan, &table->vlan_list, list)
3999 efx_ef10_filter_del_vlan_internal(efx, vlan);
4000}
4001
7ac0dd9d
AR		 4002static bool efx_ef10_filter_match_supported(struct efx_ef10_filter_table *table,
4003 enum efx_filter_match_flags match_flags)
4004{
4005 unsigned int match_pri;
4006 int mf;
4007
4008 for (match_pri = 0;
4009 match_pri < table->rx_match_count;
4010 match_pri++) {
4011 mf = efx_ef10_filter_match_flags_from_mcdi(
4012 table->rx_match_mcdi_flags[match_pri]);
4013 if (mf == match_flags)
4014 return true;
4015 }
4016
4017 return false;
4018}
4019
8127d661
BH		 4020static int efx_ef10_filter_table_probe(struct efx_nic *efx)
4021{
4022 MCDI_DECLARE_BUF(inbuf, MC_CMD_GET_PARSER_DISP_INFO_IN_LEN);
4023 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX);
34813fe2 4024 struct efx_ef10_nic_data *nic_data = efx->nic_data;
e4478ad1 4025 struct net_device *net_dev = efx->net_dev;
8127d661
BH		 4026 unsigned int pd_match_pri, pd_match_count;
4027 struct efx_ef10_filter_table *table;
34813fe2 4028 struct efx_ef10_vlan *vlan;
8127d661
BH		 4029 size_t outlen;
4030 int rc;
4031
dd98708c
EC		 4032 if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
4033 return -EINVAL;
4034
4035 if (efx->filter_state) /* already probed */
4036 return 0;
4037
8127d661
BH		 4038 table = kzalloc(sizeof(*table), GFP_KERNEL);
4039 if (!table)
4040 return -ENOMEM;
4041
4042 /* Find out which RX filter types are supported, and their priorities */
4043 MCDI_SET_DWORD(inbuf, GET_PARSER_DISP_INFO_IN_OP,
4044 MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES);
4045 rc = efx_mcdi_rpc(efx, MC_CMD_GET_PARSER_DISP_INFO,
4046 inbuf, sizeof(inbuf), outbuf, sizeof(outbuf),
4047 &outlen);
4048 if (rc)
4049 goto fail;
4050 pd_match_count = MCDI_VAR_ARRAY_LEN(
4051 outlen, GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES);
4052 table->rx_match_count = 0;
4053
4054 for (pd_match_pri = 0; pd_match_pri < pd_match_count; pd_match_pri++) {
4055 u32 mcdi_flags =
4056 MCDI_ARRAY_DWORD(
4057 outbuf,
4058 GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES,
4059 pd_match_pri);
4060 rc = efx_ef10_filter_match_flags_from_mcdi(mcdi_flags);
4061 if (rc < 0) {
4062 netif_dbg(efx, probe, efx->net_dev,
4063 "%s: fw flags %#x pri %u not supported in driver\n",
4064 __func__, mcdi_flags, pd_match_pri);
4065 } else {
4066 netif_dbg(efx, probe, efx->net_dev,
4067 "%s: fw flags %#x pri %u supported as driver flags %#x pri %u\n",
4068 __func__, mcdi_flags, pd_match_pri,
4069 rc, table->rx_match_count);
7ac0dd9d
AR		 4070 table->rx_match_mcdi_flags[table->rx_match_count] = mcdi_flags;
4071 table->rx_match_count++;
8127d661
BH		 4072 }
4073 }
4074
e4478ad1
MH		 4075 if ((efx_supported_features(efx) & NETIF_F_HW_VLAN_CTAG_FILTER) &&
4076 !(efx_ef10_filter_match_supported(table,
4077 (EFX_FILTER_MATCH_OUTER_VID | EFX_FILTER_MATCH_LOC_MAC)) &&
4078 efx_ef10_filter_match_supported(table,
4079 (EFX_FILTER_MATCH_OUTER_VID | EFX_FILTER_MATCH_LOC_MAC_IG)))) {
4080 netif_info(efx, probe, net_dev,
4081 "VLAN filters are not supported in this firmware variant\n");
4082 net_dev->features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
4083 efx->fixed_features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
4084 net_dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
4085 }
4086
8127d661
BH		 4087 table->entry = vzalloc(HUNT_FILTER_TBL_ROWS * sizeof(*table->entry));
4088 if (!table->entry) {
4089 rc = -ENOMEM;
4090 goto fail;
4091 }
4092
b071c3a2 4093 table->mc_promisc_last = false;
4a53ea8a
AR		 4094 table->vlan_filter =
4095 !!(efx->net_dev->features & NETIF_F_HW_VLAN_CTAG_FILTER);
34813fe2 4096 INIT_LIST_HEAD(&table->vlan_list);
12fb0da4 4097
8127d661
BH		 4098 efx->filter_state = table;
4099 init_waitqueue_head(&table->waitq);
34813fe2
AR		 4100
4101 list_for_each_entry(vlan, &nic_data->vlan_list, list) {
4102 rc = efx_ef10_filter_add_vlan(efx, vlan->vid);
4103 if (rc)
4104 goto fail_add_vlan;
4105 }
4106
8127d661
BH		 4107 return 0;
4108
34813fe2
AR		 4109fail_add_vlan:
4110 efx_ef10_filter_cleanup_vlans(efx);
4111 efx->filter_state = NULL;
8127d661
BH		 4112fail:
4113 kfree(table);
4114 return rc;
4115}
4116
0d322413
EC		 4117/* Caller must hold efx->filter_sem for read if race against
4118 * efx_ef10_filter_table_remove() is possible
4119 */
8127d661
BH		 4120static void efx_ef10_filter_table_restore(struct efx_nic *efx)
4121{
4122 struct efx_ef10_filter_table *table = efx->filter_state;
4123 struct efx_ef10_nic_data *nic_data = efx->nic_data;
4124 struct efx_filter_spec *spec;
4125 unsigned int filter_idx;
4126 bool failed = false;
4127 int rc;
4128
0d322413
EC		 4129 WARN_ON(!rwsem_is_locked(&efx->filter_sem));
4130
8127d661
BH		 4131 if (!nic_data->must_restore_filters)
4132 return;
4133
0d322413
EC		 4134 if (!table)
4135 return;
4136
8127d661
BH		 4137 spin_lock_bh(&efx->filter_lock);
4138
4139 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
4140 spec = efx_ef10_filter_entry_spec(table, filter_idx);
4141 if (!spec)
4142 continue;
4143
4144 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
4145 spin_unlock_bh(&efx->filter_lock);
4146
4147 rc = efx_ef10_filter_push(efx, spec,
4148 &table->entry[filter_idx].handle,
4149 false);
4150 if (rc)
4151 failed = true;
4152
4153 spin_lock_bh(&efx->filter_lock);
4154 if (rc) {
4155 kfree(spec);
4156 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
4157 } else {
4158 table->entry[filter_idx].spec &=
4159 ~EFX_EF10_FILTER_FLAG_BUSY;
4160 }
4161 }
4162
4163 spin_unlock_bh(&efx->filter_lock);
4164
4165 if (failed)
4166 netif_err(efx, hw, efx->net_dev,
4167 "unable to restore all filters\n");
4168 else
4169 nic_data->must_restore_filters = false;
4170}
4171
4172static void efx_ef10_filter_table_remove(struct efx_nic *efx)
4173{
4174 struct efx_ef10_filter_table *table = efx->filter_state;
4175 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
4176 struct efx_filter_spec *spec;
4177 unsigned int filter_idx;
4178 int rc;
4179
34813fe2 4180 efx_ef10_filter_cleanup_vlans(efx);
0d322413 4181 efx->filter_state = NULL;
dd98708c
EC		 4182 /* If we were called without locking, then it's not safe to free
4183 * the table as others might be using it. So we just WARN, leak
4184 * the memory, and potentially get an inconsistent filter table
4185 * state.
4186 * This should never actually happen.
4187 */
4188 if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
4189 return;
4190
0d322413
EC		 4191 if (!table)
4192 return;
4193
8127d661
BH		 4194 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
4195 spec = efx_ef10_filter_entry_spec(table, filter_idx);
4196 if (!spec)
4197 continue;
4198
4199 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
4200 efx_ef10_filter_is_exclusive(spec) ?
4201 MC_CMD_FILTER_OP_IN_OP_REMOVE :
4202 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
4203 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
4204 table->entry[filter_idx].handle);
e65a5109
BK		 4205 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FILTER_OP, inbuf,
4206 sizeof(inbuf), NULL, 0, NULL);
48ce5634 4207 if (rc)
e65a5109
BK		 4208 netif_info(efx, drv, efx->net_dev,
4209 "%s: filter %04x remove failed\n",
4210 __func__, filter_idx);
8127d661
BH		 4211 kfree(spec);
4212 }
4213
4214 vfree(table->entry);
4215 kfree(table);
4216}
4217
6a37958b
AR		 4218static void efx_ef10_filter_mark_one_old(struct efx_nic *efx, uint16_t *id)
4219{
4220 struct efx_ef10_filter_table *table = efx->filter_state;
4221 unsigned int filter_idx;
4222
4223 if (*id != EFX_EF10_FILTER_ID_INVALID) {
4224 filter_idx = efx_ef10_filter_get_unsafe_id(efx, *id);
4225 if (!table->entry[filter_idx].spec)
4226 netif_dbg(efx, drv, efx->net_dev,
4227 "marked null spec old %04x:%04x\n", *id,
4228 filter_idx);
4229 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_AUTO_OLD;
4230 *id = EFX_EF10_FILTER_ID_INVALID;
e65a5109 4231 }
6a37958b
AR		 4232}
4233
b3a3c03c
AR		 4234/* Mark old per-VLAN filters that may need to be removed */
4235static void _efx_ef10_filter_vlan_mark_old(struct efx_nic *efx,
4236 struct efx_ef10_filter_vlan *vlan)
8127d661
BH		 4237{
4238 struct efx_ef10_filter_table *table = efx->filter_state;
6a37958b 4239 unsigned int i;
8127d661 4240
12fb0da4 4241 for (i = 0; i < table->dev_uc_count; i++)
dc3273e0 4242 efx_ef10_filter_mark_one_old(efx, &vlan->uc[i]);
12fb0da4 4243 for (i = 0; i < table->dev_mc_count; i++)
dc3273e0
AR		 4244 efx_ef10_filter_mark_one_old(efx, &vlan->mc[i]);
4245 efx_ef10_filter_mark_one_old(efx, &vlan->ucdef);
4246 efx_ef10_filter_mark_one_old(efx, &vlan->bcast);
4247 efx_ef10_filter_mark_one_old(efx, &vlan->mcdef);
b3a3c03c
AR		 4248}
4249
34813fe2
AR		 4250/* Mark old filters that may need to be removed.
4251 * Caller must hold efx->filter_sem for read if race against
4252 * efx_ef10_filter_table_remove() is possible
4253 */
b3a3c03c
AR		 4254static void efx_ef10_filter_mark_old(struct efx_nic *efx)
4255{
4256 struct efx_ef10_filter_table *table = efx->filter_state;
34813fe2 4257 struct efx_ef10_filter_vlan *vlan;
b3a3c03c
AR		 4258
4259 spin_lock_bh(&efx->filter_lock);
34813fe2
AR		 4260 list_for_each_entry(vlan, &table->vlan_list, list)
4261 _efx_ef10_filter_vlan_mark_old(efx, vlan);
8127d661 4262 spin_unlock_bh(&efx->filter_lock);
822b96f8
DP		 4263}
4264
afa4ce12 4265static void efx_ef10_filter_uc_addr_list(struct efx_nic *efx)
822b96f8
DP		 4266{
4267 struct efx_ef10_filter_table *table = efx->filter_state;
4268 struct net_device *net_dev = efx->net_dev;
4269 struct netdev_hw_addr *uc;
12fb0da4 4270 int addr_count;
822b96f8 4271 unsigned int i;
8127d661 4272
12fb0da4 4273 addr_count = netdev_uc_count(net_dev);
afa4ce12 4274 table->uc_promisc = !!(net_dev->flags & IFF_PROMISC);
12fb0da4 4275 table->dev_uc_count = 1 + addr_count;
822b96f8
DP		 4276 ether_addr_copy(table->dev_uc_list[0].addr, net_dev->dev_addr);
4277 i = 1;
4278 netdev_for_each_uc_addr(uc, net_dev) {
12fb0da4 4279 if (i >= EFX_EF10_FILTER_DEV_UC_MAX) {
afa4ce12 4280 table->uc_promisc = true;
12fb0da4
EC		 4281 break;
4282 }
822b96f8
DP		 4283 ether_addr_copy(table->dev_uc_list[i].addr, uc->addr);
4284 i++;
4285 }
4286}
4287
afa4ce12 4288static void efx_ef10_filter_mc_addr_list(struct efx_nic *efx)
822b96f8
DP		 4289{
4290 struct efx_ef10_filter_table *table = efx->filter_state;
4291 struct net_device *net_dev = efx->net_dev;
4292 struct netdev_hw_addr *mc;
ab8b1f7c 4293 unsigned int i, addr_count;
822b96f8 4294
afa4ce12 4295 table->mc_promisc = !!(net_dev->flags & (IFF_PROMISC | IFF_ALLMULTI));
ab8b1f7c 4296
12fb0da4
EC		 4297 addr_count = netdev_mc_count(net_dev);
4298 i = 0;
ab8b1f7c 4299 netdev_for_each_mc_addr(mc, net_dev) {
12fb0da4 4300 if (i >= EFX_EF10_FILTER_DEV_MC_MAX) {
afa4ce12 4301 table->mc_promisc = true;
12fb0da4
EC		 4302 break;
4303 }
ab8b1f7c
DP		 4304 ether_addr_copy(table->dev_mc_list[i].addr, mc->addr);
4305 i++;
8127d661 4306 }
12fb0da4
EC		 4307
4308 table->dev_mc_count = i;
822b96f8 4309}
8127d661 4310
12fb0da4 4311static int efx_ef10_filter_insert_addr_list(struct efx_nic *efx,
b3a3c03c
AR		 4312 struct efx_ef10_filter_vlan *vlan,
4313 bool multicast, bool rollback)
822b96f8
DP		 4314{
4315 struct efx_ef10_filter_table *table = efx->filter_state;
4316 struct efx_ef10_dev_addr *addr_list;
f1c2ef40 4317 enum efx_filter_flags filter_flags;
822b96f8 4318 struct efx_filter_spec spec;
12fb0da4
EC		 4319 u8 baddr[ETH_ALEN];
4320 unsigned int i, j;
4321 int addr_count;
dc3273e0 4322 u16 *ids;
822b96f8
DP		 4323 int rc;
4324
4325 if (multicast) {
4326 addr_list = table->dev_mc_list;
12fb0da4 4327 addr_count = table->dev_mc_count;
dc3273e0 4328 ids = vlan->mc;
822b96f8
DP		 4329 } else {
4330 addr_list = table->dev_uc_list;
12fb0da4 4331 addr_count = table->dev_uc_count;
dc3273e0 4332 ids = vlan->uc;
8127d661
BH		 4333 }
4334
f1c2ef40
BK		 4335 filter_flags = efx_rss_enabled(efx) ? EFX_FILTER_FLAG_RX_RSS : 0;
4336
822b96f8 4337 /* Insert/renew filters */
12fb0da4 4338 for (i = 0; i < addr_count; i++) {
f1c2ef40 4339 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, 0);
b3a3c03c 4340 efx_filter_set_eth_local(&spec, vlan->vid, addr_list[i].addr);
b6f568e2
JC		 4341 rc = efx_ef10_filter_insert(efx, &spec, true);
4342 if (rc < 0) {
12fb0da4
EC		 4343 if (rollback) {
4344 netif_info(efx, drv, efx->net_dev,
4345 "efx_ef10_filter_insert failed rc=%d\n",
4346 rc);
4347 /* Fall back to promiscuous */
4348 for (j = 0; j < i; j++) {
12fb0da4
EC		 4349 efx_ef10_filter_remove_unsafe(
4350 efx, EFX_FILTER_PRI_AUTO,
dc3273e0
AR		 4351 ids[j]);
4352 ids[j] = EFX_EF10_FILTER_ID_INVALID;
12fb0da4
EC		 4353 }
4354 return rc;
4355 } else {
4356 /* mark as not inserted, and carry on */
4357 rc = EFX_EF10_FILTER_ID_INVALID;
822b96f8 4358 }
8127d661 4359 }
dc3273e0 4360 ids[i] = efx_ef10_filter_get_unsafe_id(efx, rc);
8127d661 4361 }
822b96f8 4362
12fb0da4
EC		 4363 if (multicast && rollback) {
4364 /* Also need an Ethernet broadcast filter */
f1c2ef40 4365 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, 0);
12fb0da4 4366 eth_broadcast_addr(baddr);
b3a3c03c 4367 efx_filter_set_eth_local(&spec, vlan->vid, baddr);
8127d661 4368 rc = efx_ef10_filter_insert(efx, &spec, true);
12fb0da4 4369 if (rc < 0) {
822b96f8 4370 netif_warn(efx, drv, efx->net_dev,
12fb0da4
EC		 4371 "Broadcast filter insert failed rc=%d\n", rc);
4372 /* Fall back to promiscuous */
4373 for (j = 0; j < i; j++) {
12fb0da4
EC		 4374 efx_ef10_filter_remove_unsafe(
4375 efx, EFX_FILTER_PRI_AUTO,
dc3273e0
AR		 4376 ids[j]);
4377 ids[j] = EFX_EF10_FILTER_ID_INVALID;
12fb0da4
EC		 4378 }
4379 return rc;
4380 } else {
dc3273e0 4381 EFX_WARN_ON_PARANOID(vlan->bcast !=
6a37958b 4382 EFX_EF10_FILTER_ID_INVALID);
dc3273e0 4383 vlan->bcast = efx_ef10_filter_get_unsafe_id(efx, rc);
12fb0da4 4384 }
8127d661 4385 }
12fb0da4
EC		 4386
4387 return 0;
4388}
4389
b3a3c03c
AR		 4390static int efx_ef10_filter_insert_def(struct efx_nic *efx,
4391 struct efx_ef10_filter_vlan *vlan,
4392 bool multicast, bool rollback)
12fb0da4 4393{
12fb0da4 4394 struct efx_ef10_nic_data *nic_data = efx->nic_data;
f1c2ef40 4395 enum efx_filter_flags filter_flags;
12fb0da4
EC		 4396 struct efx_filter_spec spec;
4397 u8 baddr[ETH_ALEN];
4398 int rc;
4399
f1c2ef40
BK		 4400 filter_flags = efx_rss_enabled(efx) ? EFX_FILTER_FLAG_RX_RSS : 0;
4401
4402 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, 0);
12fb0da4
EC		 4403
4404 if (multicast)
4405 efx_filter_set_mc_def(&spec);
4406 else
4407 efx_filter_set_uc_def(&spec);
4408
b3a3c03c
AR		 4409 if (vlan->vid != EFX_FILTER_VID_UNSPEC)
4410 efx_filter_set_eth_local(&spec, vlan->vid, NULL);
4411
12fb0da4
EC		 4412 rc = efx_ef10_filter_insert(efx, &spec, true);
4413 if (rc < 0) {
09a04204
BK		 4414 netif_printk(efx, drv, rc == -EPERM ? KERN_DEBUG : KERN_WARNING,
4415 efx->net_dev,
4416 "%scast mismatch filter insert failed rc=%d\n",
4417 multicast ? "Multi" : "Uni", rc);
12fb0da4 4418 } else if (multicast) {
dc3273e0
AR		 4419 EFX_WARN_ON_PARANOID(vlan->mcdef != EFX_EF10_FILTER_ID_INVALID);
4420 vlan->mcdef = efx_ef10_filter_get_unsafe_id(efx, rc);
12fb0da4
EC		 4421 if (!nic_data->workaround_26807) {
4422 /* Also need an Ethernet broadcast filter */
4423 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
f1c2ef40 4424 filter_flags, 0);
12fb0da4 4425 eth_broadcast_addr(baddr);
b3a3c03c 4426 efx_filter_set_eth_local(&spec, vlan->vid, baddr);
12fb0da4
EC		 4427 rc = efx_ef10_filter_insert(efx, &spec, true);
4428 if (rc < 0) {
4429 netif_warn(efx, drv, efx->net_dev,
4430 "Broadcast filter insert failed rc=%d\n",
4431 rc);
4432 if (rollback) {
4433 /* Roll back the mc_def filter */
4434 efx_ef10_filter_remove_unsafe(
4435 efx, EFX_FILTER_PRI_AUTO,
dc3273e0
AR		 4436 vlan->mcdef);
4437 vlan->mcdef = EFX_EF10_FILTER_ID_INVALID;
12fb0da4
EC		 4438 return rc;
4439 }
4440 } else {
dc3273e0 4441 EFX_WARN_ON_PARANOID(vlan->bcast !=
6a37958b 4442 EFX_EF10_FILTER_ID_INVALID);
dc3273e0 4443 vlan->bcast = efx_ef10_filter_get_unsafe_id(efx, rc);
12fb0da4
EC		 4444 }
4445 }
4446 rc = 0;
4447 } else {
dc3273e0
AR		 4448 EFX_WARN_ON_PARANOID(vlan->ucdef != EFX_EF10_FILTER_ID_INVALID);
4449 vlan->ucdef = rc;
12fb0da4
EC		 4450 rc = 0;
4451 }
4452 return rc;
822b96f8
DP		 4453}
4454
4455/* Remove filters that weren't renewed. Since nothing else changes the AUTO_OLD
4456 * flag or removes these filters, we don't need to hold the filter_lock while
4457 * scanning for these filters.
4458 */
4459static void efx_ef10_filter_remove_old(struct efx_nic *efx)
4460{
4461 struct efx_ef10_filter_table *table = efx->filter_state;
e65a5109
BK		 4462 int remove_failed = 0;
4463 int remove_noent = 0;
4464 int rc;
822b96f8 4465 int i;
8127d661 4466
8127d661
BH		 4467 for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) {
4468 if (ACCESS_ONCE(table->entry[i].spec) &
b59e6ef8 4469 EFX_EF10_FILTER_FLAG_AUTO_OLD) {
e65a5109
BK		 4470 rc = efx_ef10_filter_remove_internal(efx,
4471 1U << EFX_FILTER_PRI_AUTO, i, true);
4472 if (rc == -ENOENT)
4473 remove_noent++;
4474 else if (rc)
4475 remove_failed++;
8127d661
BH		 4476 }
4477 }
e65a5109
BK		 4478
4479 if (remove_failed)
4480 netif_info(efx, drv, efx->net_dev,
4481 "%s: failed to remove %d filters\n",
4482 __func__, remove_failed);
4483 if (remove_noent)
4484 netif_info(efx, drv, efx->net_dev,
4485 "%s: failed to remove %d non-existent filters\n",
4486 __func__, remove_noent);
8127d661
BH		 4487}
4488
7a186f47
DP		 4489static int efx_ef10_vport_set_mac_address(struct efx_nic *efx)
4490{
4491 struct efx_ef10_nic_data *nic_data = efx->nic_data;
4492 u8 mac_old[ETH_ALEN];
4493 int rc, rc2;
4494
4495 /* Only reconfigure a PF-created vport */
4496 if (is_zero_ether_addr(nic_data->vport_mac))
4497 return 0;
4498
4499 efx_device_detach_sync(efx);
4500 efx_net_stop(efx->net_dev);
4501 down_write(&efx->filter_sem);
4502 efx_ef10_filter_table_remove(efx);
4503 up_write(&efx->filter_sem);
4504
4505 rc = efx_ef10_vadaptor_free(efx, nic_data->vport_id);
4506 if (rc)
4507 goto restore_filters;
4508
4509 ether_addr_copy(mac_old, nic_data->vport_mac);
4510 rc = efx_ef10_vport_del_mac(efx, nic_data->vport_id,
4511 nic_data->vport_mac);
4512 if (rc)
4513 goto restore_vadaptor;
4514
4515 rc = efx_ef10_vport_add_mac(efx, nic_data->vport_id,
4516 efx->net_dev->dev_addr);
4517 if (!rc) {
4518 ether_addr_copy(nic_data->vport_mac, efx->net_dev->dev_addr);
4519 } else {
4520 rc2 = efx_ef10_vport_add_mac(efx, nic_data->vport_id, mac_old);
4521 if (rc2) {
4522 /* Failed to add original MAC, so clear vport_mac */
4523 eth_zero_addr(nic_data->vport_mac);
4524 goto reset_nic;
4525 }
4526 }
4527
4528restore_vadaptor:
4529 rc2 = efx_ef10_vadaptor_alloc(efx, nic_data->vport_id);
4530 if (rc2)
4531 goto reset_nic;
4532restore_filters:
4533 down_write(&efx->filter_sem);
4534 rc2 = efx_ef10_filter_table_probe(efx);
4535 up_write(&efx->filter_sem);
4536 if (rc2)
4537 goto reset_nic;
4538
4539 rc2 = efx_net_open(efx->net_dev);
4540 if (rc2)
4541 goto reset_nic;
4542
4543 netif_device_attach(efx->net_dev);
4544
4545 return rc;
4546
4547reset_nic:
4548 netif_err(efx, drv, efx->net_dev,
4549 "Failed to restore when changing MAC address - scheduling reset\n");
4550 efx_schedule_reset(efx, RESET_TYPE_DATAPATH);
4551
4552 return rc ? rc : rc2;
4553}
4554
822b96f8
DP		 4555/* Caller must hold efx->filter_sem for read if race against
4556 * efx_ef10_filter_table_remove() is possible
4557 */
34813fe2
AR		 4558static void efx_ef10_filter_vlan_sync_rx_mode(struct efx_nic *efx,
4559 struct efx_ef10_filter_vlan *vlan)
822b96f8
DP		 4560{
4561 struct efx_ef10_filter_table *table = efx->filter_state;
ab8b1f7c 4562 struct efx_ef10_nic_data *nic_data = efx->nic_data;
b3a3c03c 4563
4a53ea8a
AR		 4564 /* Do not install unspecified VID if VLAN filtering is enabled.
4565 * Do not install all specified VIDs if VLAN filtering is disabled.
4566 */
4567 if ((vlan->vid == EFX_FILTER_VID_UNSPEC) == table->vlan_filter)
4568 return;
4569
12fb0da4 4570 /* Insert/renew unicast filters */
afa4ce12 4571 if (table->uc_promisc) {
b3a3c03c
AR		 4572 efx_ef10_filter_insert_def(efx, vlan, false, false);
4573 efx_ef10_filter_insert_addr_list(efx, vlan, false, false);
12fb0da4
EC		 4574 } else {
4575 /* If any of the filters failed to insert, fall back to
4576 * promiscuous mode - add in the uc_def filter. But keep
4577 * our individual unicast filters.
4578 */
b3a3c03c
AR		 4579 if (efx_ef10_filter_insert_addr_list(efx, vlan, false, false))
4580 efx_ef10_filter_insert_def(efx, vlan, false, false);
12fb0da4 4581 }
ab8b1f7c 4582
12fb0da4 4583 /* Insert/renew multicast filters */
ab8b1f7c
DP		 4584 /* If changing promiscuous state with cascaded multicast filters, remove
4585 * old filters first, so that packets are dropped rather than duplicated
4586 */
afa4ce12
AR		 4587 if (nic_data->workaround_26807 &&
4588 table->mc_promisc_last != table->mc_promisc)
ab8b1f7c 4589 efx_ef10_filter_remove_old(efx);
afa4ce12 4590 if (table->mc_promisc) {
12fb0da4
EC		 4591 if (nic_data->workaround_26807) {
4592 /* If we failed to insert promiscuous filters, rollback
4593 * and fall back to individual multicast filters
4594 */
b3a3c03c 4595 if (efx_ef10_filter_insert_def(efx, vlan, true, true)) {
12fb0da4
EC		 4596 /* Changing promisc state, so remove old filters */
4597 efx_ef10_filter_remove_old(efx);
b3a3c03c
AR		 4598 efx_ef10_filter_insert_addr_list(efx, vlan,
4599 true, false);
12fb0da4
EC		 4600 }
4601 } else {
4602 /* If we failed to insert promiscuous filters, don't
4603 * rollback. Regardless, also insert the mc_list
4604 */
b3a3c03c
AR		 4605 efx_ef10_filter_insert_def(efx, vlan, true, false);
4606 efx_ef10_filter_insert_addr_list(efx, vlan, true, false);
12fb0da4
EC		 4607 }
4608 } else {
4609 /* If any filters failed to insert, rollback and fall back to
4610 * promiscuous mode - mc_def filter and maybe broadcast. If
4611 * that fails, roll back again and insert as many of our
4612 * individual multicast filters as we can.
4613 */
b3a3c03c 4614 if (efx_ef10_filter_insert_addr_list(efx, vlan, true, true)) {
12fb0da4
EC		 4615 /* Changing promisc state, so remove old filters */
4616 if (nic_data->workaround_26807)
4617 efx_ef10_filter_remove_old(efx);
b3a3c03c
AR		 4618 if (efx_ef10_filter_insert_def(efx, vlan, true, true))
4619 efx_ef10_filter_insert_addr_list(efx, vlan,
4620 true, false);
12fb0da4
EC		 4621 }
4622 }
34813fe2
AR		 4623}
4624
4625/* Caller must hold efx->filter_sem for read if race against
4626 * efx_ef10_filter_table_remove() is possible
4627 */
4628static void efx_ef10_filter_sync_rx_mode(struct efx_nic *efx)
4629{
4630 struct efx_ef10_filter_table *table = efx->filter_state;
4631 struct net_device *net_dev = efx->net_dev;
4632 struct efx_ef10_filter_vlan *vlan;
4a53ea8a 4633 bool vlan_filter;
34813fe2
AR		 4634
4635 if (!efx_dev_registered(efx))
4636 return;
4637
4638 if (!table)
4639 return;
4640
4641 efx_ef10_filter_mark_old(efx);
4642
4643 /* Copy/convert the address lists; add the primary station
4644 * address and broadcast address
4645 */
4646 netif_addr_lock_bh(net_dev);
4647 efx_ef10_filter_uc_addr_list(efx);
4648 efx_ef10_filter_mc_addr_list(efx);
4649 netif_addr_unlock_bh(net_dev);
4650
4a53ea8a
AR		 4651 /* If VLAN filtering changes, all old filters are finally removed.
4652 * Do it in advance to avoid conflicts for unicast untagged and
4653 * VLAN 0 tagged filters.
4654 */
4655 vlan_filter = !!(net_dev->features & NETIF_F_HW_VLAN_CTAG_FILTER);
4656 if (table->vlan_filter != vlan_filter) {
4657 table->vlan_filter = vlan_filter;
4658 efx_ef10_filter_remove_old(efx);
4659 }
4660
34813fe2
AR		 4661 list_for_each_entry(vlan, &table->vlan_list, list)
4662 efx_ef10_filter_vlan_sync_rx_mode(efx, vlan);
822b96f8
DP		 4663
4664 efx_ef10_filter_remove_old(efx);
afa4ce12 4665 table->mc_promisc_last = table->mc_promisc;
822b96f8
DP		 4666}
4667
34813fe2
AR		 4668static struct efx_ef10_filter_vlan *efx_ef10_filter_find_vlan(struct efx_nic *efx, u16 vid)
4669{
4670 struct efx_ef10_filter_table *table = efx->filter_state;
4671 struct efx_ef10_filter_vlan *vlan;
4672
4673 WARN_ON(!rwsem_is_locked(&efx->filter_sem));
4674
4675 list_for_each_entry(vlan, &table->vlan_list, list) {
4676 if (vlan->vid == vid)
4677 return vlan;
4678 }
4679
4680 return NULL;
4681}
4682
4683static int efx_ef10_filter_add_vlan(struct efx_nic *efx, u16 vid)
4684{
4685 struct efx_ef10_filter_table *table = efx->filter_state;
4686 struct efx_ef10_filter_vlan *vlan;
4687 unsigned int i;
4688
4689 if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
4690 return -EINVAL;
4691
4692 vlan = efx_ef10_filter_find_vlan(efx, vid);
4693 if (WARN_ON(vlan)) {
4694 netif_err(efx, drv, efx->net_dev,
4695 "VLAN %u already added\n", vid);
4696 return -EALREADY;
4697 }
4698
4699 vlan = kzalloc(sizeof(*vlan), GFP_KERNEL);
4700 if (!vlan)
4701 return -ENOMEM;
4702
4703 vlan->vid = vid;
4704
4705 for (i = 0; i < ARRAY_SIZE(vlan->uc); i++)
4706 vlan->uc[i] = EFX_EF10_FILTER_ID_INVALID;
4707 for (i = 0; i < ARRAY_SIZE(vlan->mc); i++)
4708 vlan->mc[i] = EFX_EF10_FILTER_ID_INVALID;
4709 vlan->ucdef = EFX_EF10_FILTER_ID_INVALID;
4710 vlan->bcast = EFX_EF10_FILTER_ID_INVALID;
4711 vlan->mcdef = EFX_EF10_FILTER_ID_INVALID;
4712
4713 list_add_tail(&vlan->list, &table->vlan_list);
4714
4715 if (efx_dev_registered(efx))
4716 efx_ef10_filter_vlan_sync_rx_mode(efx, vlan);
4717
4718 return 0;
4719}
4720
4721static void efx_ef10_filter_del_vlan_internal(struct efx_nic *efx,
4722 struct efx_ef10_filter_vlan *vlan)
4723{
4724 unsigned int i;
4725
4726 /* See comment in efx_ef10_filter_table_remove() */
4727 if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
4728 return;
4729
4730 list_del(&vlan->list);
4731
8c915620 4732 for (i = 0; i < ARRAY_SIZE(vlan->uc); i++)
34813fe2 4733 efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO,
8c915620
EC		 4734 vlan->uc[i]);
4735 for (i = 0; i < ARRAY_SIZE(vlan->mc); i++)
34813fe2 4736 efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO,
8c915620
EC		 4737 vlan->mc[i]);
4738 efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO, vlan->ucdef);
4739 efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO, vlan->bcast);
4740 efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO, vlan->mcdef);
34813fe2
AR		 4741
4742 kfree(vlan);
4743}
4744
4745static void efx_ef10_filter_del_vlan(struct efx_nic *efx, u16 vid)
4746{
4747 struct efx_ef10_filter_vlan *vlan;
4748
4749 /* See comment in efx_ef10_filter_table_remove() */
4750 if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
4751 return;
4752
4753 vlan = efx_ef10_filter_find_vlan(efx, vid);
4754 if (!vlan) {
4755 netif_err(efx, drv, efx->net_dev,
4756 "VLAN %u not found in filter state\n", vid);
4757 return;
4758 }
4759
4760 efx_ef10_filter_del_vlan_internal(efx, vlan);
4761}
4762
910c8789
SS		 4763static int efx_ef10_set_mac_address(struct efx_nic *efx)
4764{
4765 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_SET_MAC_IN_LEN);
4766 struct efx_ef10_nic_data *nic_data = efx->nic_data;
4767 bool was_enabled = efx->port_enabled;
4768 int rc;
4769
4770 efx_device_detach_sync(efx);
4771 efx_net_stop(efx->net_dev);
d248953a
MH		 4772
4773 mutex_lock(&efx->mac_lock);
910c8789
SS		 4774 down_write(&efx->filter_sem);
4775 efx_ef10_filter_table_remove(efx);
4776
4777 ether_addr_copy(MCDI_PTR(inbuf, VADAPTOR_SET_MAC_IN_MACADDR),
4778 efx->net_dev->dev_addr);
4779 MCDI_SET_DWORD(inbuf, VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID,
4780 nic_data->vport_id);
535a6177
DP		 4781 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_VADAPTOR_SET_MAC, inbuf,
4782 sizeof(inbuf), NULL, 0, NULL);
910c8789
SS		 4783
4784 efx_ef10_filter_table_probe(efx);
4785 up_write(&efx->filter_sem);
d248953a
MH		 4786 mutex_unlock(&efx->mac_lock);
4787
910c8789
SS		 4788 if (was_enabled)
4789 efx_net_open(efx->net_dev);
4790 netif_device_attach(efx->net_dev);
4791
9e9f665a
DP		 4792#ifdef CONFIG_SFC_SRIOV
4793 if (efx->pci_dev->is_virtfn && efx->pci_dev->physfn) {
910c8789
SS		 4794 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn;
4795
9e9f665a
DP		 4796 if (rc == -EPERM) {
4797 struct efx_nic *efx_pf;
910c8789 4798
9e9f665a
DP		 4799 /* Switch to PF and change MAC address on vport */
4800 efx_pf = pci_get_drvdata(pci_dev_pf);
910c8789 4801
9e9f665a
DP		 4802 rc = efx_ef10_sriov_set_vf_mac(efx_pf,
4803 nic_data->vf_index,
4804 efx->net_dev->dev_addr);
4805 } else if (!rc) {
910c8789
SS		 4806 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
4807 struct efx_ef10_nic_data *nic_data = efx_pf->nic_data;
4808 unsigned int i;
4809
9e9f665a
DP		 4810 /* MAC address successfully changed by VF (with MAC
4811 * spoofing) so update the parent PF if possible.
4812 */
910c8789
SS		 4813 for (i = 0; i < efx_pf->vf_count; ++i) {
4814 struct ef10_vf *vf = nic_data->vf + i;
4815
4816 if (vf->efx == efx) {
4817 ether_addr_copy(vf->mac,
4818 efx->net_dev->dev_addr);
4819 return 0;
4820 }
4821 }
4822 }
9e9f665a 4823 } else
910c8789 4824#endif
9e9f665a
DP		 4825 if (rc == -EPERM) {
4826 netif_err(efx, drv, efx->net_dev,
4827 "Cannot change MAC address; use sfboot to enable"
4828 " mac-spoofing on this interface\n");
7a186f47
DP		 4829 } else if (rc == -ENOSYS && !efx_ef10_is_vf(efx)) {
4830 /* If the active MCFW does not support MC_CMD_VADAPTOR_SET_MAC
4831 * fall-back to the method of changing the MAC address on the
4832 * vport. This only applies to PFs because such versions of
4833 * MCFW do not support VFs.
4834 */
4835 rc = efx_ef10_vport_set_mac_address(efx);
535a6177
DP		 4836 } else {
4837 efx_mcdi_display_error(efx, MC_CMD_VADAPTOR_SET_MAC,
4838 sizeof(inbuf), NULL, 0, rc);
9e9f665a
DP		 4839 }
4840
910c8789
SS		 4841 return rc;
4842}
4843
8127d661
BH		 4844static int efx_ef10_mac_reconfigure(struct efx_nic *efx)
4845{
4846 efx_ef10_filter_sync_rx_mode(efx);
4847
4848 return efx_mcdi_set_mac(efx);
4849}
4850
862f894c
SS		 4851static int efx_ef10_mac_reconfigure_vf(struct efx_nic *efx)
4852{
4853 efx_ef10_filter_sync_rx_mode(efx);
4854
4855 return 0;
4856}
4857
74cd60a4
JC		 4858static int efx_ef10_start_bist(struct efx_nic *efx, u32 bist_type)
4859{
4860 MCDI_DECLARE_BUF(inbuf, MC_CMD_START_BIST_IN_LEN);
4861
4862 MCDI_SET_DWORD(inbuf, START_BIST_IN_TYPE, bist_type);
4863 return efx_mcdi_rpc(efx, MC_CMD_START_BIST, inbuf, sizeof(inbuf),
4864 NULL, 0, NULL);
4865}
4866
4867/* MC BISTs follow a different poll mechanism to phy BISTs.
4868 * The BIST is done in the poll handler on the MC, and the MCDI command
4869 * will block until the BIST is done.
4870 */
4871static int efx_ef10_poll_bist(struct efx_nic *efx)
4872{
4873 int rc;
4874 MCDI_DECLARE_BUF(outbuf, MC_CMD_POLL_BIST_OUT_LEN);
4875 size_t outlen;
4876 u32 result;
4877
4878 rc = efx_mcdi_rpc(efx, MC_CMD_POLL_BIST, NULL, 0,
4879 outbuf, sizeof(outbuf), &outlen);
4880 if (rc != 0)
4881 return rc;
4882
4883 if (outlen < MC_CMD_POLL_BIST_OUT_LEN)
4884 return -EIO;
4885
4886 result = MCDI_DWORD(outbuf, POLL_BIST_OUT_RESULT);
4887 switch (result) {
4888 case MC_CMD_POLL_BIST_PASSED:
4889 netif_dbg(efx, hw, efx->net_dev, "BIST passed.\n");
4890 return 0;
4891 case MC_CMD_POLL_BIST_TIMEOUT:
4892 netif_err(efx, hw, efx->net_dev, "BIST timed out\n");
4893 return -EIO;
4894 case MC_CMD_POLL_BIST_FAILED:
4895 netif_err(efx, hw, efx->net_dev, "BIST failed.\n");
4896 return -EIO;
4897 default:
4898 netif_err(efx, hw, efx->net_dev,
4899 "BIST returned unknown result %u", result);
4900 return -EIO;
4901 }
4902}
4903
4904static int efx_ef10_run_bist(struct efx_nic *efx, u32 bist_type)
4905{
4906 int rc;
4907
4908 netif_dbg(efx, drv, efx->net_dev, "starting BIST type %u\n", bist_type);
4909
4910 rc = efx_ef10_start_bist(efx, bist_type);
4911 if (rc != 0)
4912 return rc;
4913
4914 return efx_ef10_poll_bist(efx);
4915}
4916
4917static int
4918efx_ef10_test_chip(struct efx_nic *efx, struct efx_self_tests *tests)
4919{
4920 int rc, rc2;
4921
4922 efx_reset_down(efx, RESET_TYPE_WORLD);
4923
4924 rc = efx_mcdi_rpc(efx, MC_CMD_ENABLE_OFFLINE_BIST,
4925 NULL, 0, NULL, 0, NULL);
4926 if (rc != 0)
4927 goto out;
4928
4929 tests->memory = efx_ef10_run_bist(efx, MC_CMD_MC_MEM_BIST) ? -1 : 1;
4930 tests->registers = efx_ef10_run_bist(efx, MC_CMD_REG_BIST) ? -1 : 1;
4931
4932 rc = efx_mcdi_reset(efx, RESET_TYPE_WORLD);
4933
4934out:
27324820
DP		 4935 if (rc == -EPERM)
4936 rc = 0;
74cd60a4
JC		 4937 rc2 = efx_reset_up(efx, RESET_TYPE_WORLD, rc == 0);
4938 return rc ? rc : rc2;
4939}
4940
8127d661
BH		 4941#ifdef CONFIG_SFC_MTD
4942
4943struct efx_ef10_nvram_type_info {
4944 u16 type, type_mask;
4945 u8 port;
4946 const char *name;
4947};
4948
4949static const struct efx_ef10_nvram_type_info efx_ef10_nvram_types[] = {
4950 { NVRAM_PARTITION_TYPE_MC_FIRMWARE, 0, 0, "sfc_mcfw" },
4951 { NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 0, 0, "sfc_mcfw_backup" },
4952 { NVRAM_PARTITION_TYPE_EXPANSION_ROM, 0, 0, "sfc_exp_rom" },
4953 { NVRAM_PARTITION_TYPE_STATIC_CONFIG, 0, 0, "sfc_static_cfg" },
4954 { NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG, 0, 0, "sfc_dynamic_cfg" },
4955 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0, 0, 0, "sfc_exp_rom_cfg" },
4956 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1, 0, 1, "sfc_exp_rom_cfg" },
4957 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2, 0, 2, "sfc_exp_rom_cfg" },
4958 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3, 0, 3, "sfc_exp_rom_cfg" },
a84f3bf9 4959 { NVRAM_PARTITION_TYPE_LICENSE, 0, 0, "sfc_license" },
8127d661
BH		 4960 { NVRAM_PARTITION_TYPE_PHY_MIN, 0xff, 0, "sfc_phy_fw" },
4961};
4962
4963static int efx_ef10_mtd_probe_partition(struct efx_nic *efx,
4964 struct efx_mcdi_mtd_partition *part,
4965 unsigned int type)
4966{
4967 MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_METADATA_IN_LEN);
4968 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_METADATA_OUT_LENMAX);
4969 const struct efx_ef10_nvram_type_info *info;
4970 size_t size, erase_size, outlen;
4971 bool protected;
4972 int rc;
4973
4974 for (info = efx_ef10_nvram_types; ; info++) {
4975 if (info ==
4976 efx_ef10_nvram_types + ARRAY_SIZE(efx_ef10_nvram_types))
4977 return -ENODEV;
4978 if ((type & ~info->type_mask) == info->type)
4979 break;
4980 }
4981 if (info->port != efx_port_num(efx))
4982 return -ENODEV;
4983
4984 rc = efx_mcdi_nvram_info(efx, type, &size, &erase_size, &protected);
4985 if (rc)
4986 return rc;
4987 if (protected)
4988 return -ENODEV; /* hide it */
4989
4990 part->nvram_type = type;
4991
4992 MCDI_SET_DWORD(inbuf, NVRAM_METADATA_IN_TYPE, type);
4993 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_METADATA, inbuf, sizeof(inbuf),
4994 outbuf, sizeof(outbuf), &outlen);
4995 if (rc)
4996 return rc;
4997 if (outlen < MC_CMD_NVRAM_METADATA_OUT_LENMIN)
4998 return -EIO;
4999 if (MCDI_DWORD(outbuf, NVRAM_METADATA_OUT_FLAGS) &
5000 (1 << MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN))
5001 part->fw_subtype = MCDI_DWORD(outbuf,
5002 NVRAM_METADATA_OUT_SUBTYPE);
5003
5004 part->common.dev_type_name = "EF10 NVRAM manager";
5005 part->common.type_name = info->name;
5006
5007 part->common.mtd.type = MTD_NORFLASH;
5008 part->common.mtd.flags = MTD_CAP_NORFLASH;
5009 part->common.mtd.size = size;
5010 part->common.mtd.erasesize = erase_size;
5011
5012 return 0;
5013}
5014
5015static int efx_ef10_mtd_probe(struct efx_nic *efx)
5016{
5017 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX);
5018 struct efx_mcdi_mtd_partition *parts;
5019 size_t outlen, n_parts_total, i, n_parts;
5020 unsigned int type;
5021 int rc;
5022
5023 ASSERT_RTNL();
5024
5025 BUILD_BUG_ON(MC_CMD_NVRAM_PARTITIONS_IN_LEN != 0);
5026 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_PARTITIONS, NULL, 0,
5027 outbuf, sizeof(outbuf), &outlen);
5028 if (rc)
5029 return rc;
5030 if (outlen < MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN)
5031 return -EIO;
5032
5033 n_parts_total = MCDI_DWORD(outbuf, NVRAM_PARTITIONS_OUT_NUM_PARTITIONS);
5034 if (n_parts_total >
5035 MCDI_VAR_ARRAY_LEN(outlen, NVRAM_PARTITIONS_OUT_TYPE_ID))
5036 return -EIO;
5037
5038 parts = kcalloc(n_parts_total, sizeof(*parts), GFP_KERNEL);
5039 if (!parts)
5040 return -ENOMEM;
5041
5042 n_parts = 0;
5043 for (i = 0; i < n_parts_total; i++) {
5044 type = MCDI_ARRAY_DWORD(outbuf, NVRAM_PARTITIONS_OUT_TYPE_ID,
5045 i);
5046 rc = efx_ef10_mtd_probe_partition(efx, &parts[n_parts], type);
5047 if (rc == 0)
5048 n_parts++;
5049 else if (rc != -ENODEV)
5050 goto fail;
5051 }
5052
5053 rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts));
5054fail:
5055 if (rc)
5056 kfree(parts);
5057 return rc;
5058}
5059
5060#endif /* CONFIG_SFC_MTD */
5061
5062static void efx_ef10_ptp_write_host_time(struct efx_nic *efx, u32 host_time)
5063{
5064 _efx_writed(efx, cpu_to_le32(host_time), ER_DZ_MC_DB_LWRD);
5065}
5066
02246a7f
SS		 5067static void efx_ef10_ptp_write_host_time_vf(struct efx_nic *efx,
5068 u32 host_time) {}
5069
bd9a265d
JC		 5070static int efx_ef10_rx_enable_timestamping(struct efx_channel *channel,
5071 bool temp)
5072{
5073 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN);
5074 int rc;
5075
5076 if (channel->sync_events_state == SYNC_EVENTS_REQUESTED ||
5077 channel->sync_events_state == SYNC_EVENTS_VALID ||
5078 (temp && channel->sync_events_state == SYNC_EVENTS_DISABLED))
5079 return 0;
5080 channel->sync_events_state = SYNC_EVENTS_REQUESTED;
5081
5082 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE);
5083 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
5084 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE,
5085 channel->channel);
5086
5087 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
5088 inbuf, sizeof(inbuf), NULL, 0, NULL);
5089
5090 if (rc != 0)
5091 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
5092 SYNC_EVENTS_DISABLED;
5093
5094 return rc;
5095}
5096
5097static int efx_ef10_rx_disable_timestamping(struct efx_channel *channel,
5098 bool temp)
5099{
5100 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN);
5101 int rc;
5102
5103 if (channel->sync_events_state == SYNC_EVENTS_DISABLED ||
5104 (temp && channel->sync_events_state == SYNC_EVENTS_QUIESCENT))
5105 return 0;
5106 if (channel->sync_events_state == SYNC_EVENTS_QUIESCENT) {
5107 channel->sync_events_state = SYNC_EVENTS_DISABLED;
5108 return 0;
5109 }
5110 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
5111 SYNC_EVENTS_DISABLED;
5112
5113 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE);
5114 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
5115 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL,
5116 MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE);
5117 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE,
5118 channel->channel);
5119
5120 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
5121 inbuf, sizeof(inbuf), NULL, 0, NULL);
5122
5123 return rc;
5124}
5125
5126static int efx_ef10_ptp_set_ts_sync_events(struct efx_nic *efx, bool en,
5127 bool temp)
5128{
5129 int (*set)(struct efx_channel *channel, bool temp);
5130 struct efx_channel *channel;
5131
5132 set = en ?
5133 efx_ef10_rx_enable_timestamping :
5134 efx_ef10_rx_disable_timestamping;
5135
5136 efx_for_each_channel(channel, efx) {
5137 int rc = set(channel, temp);
5138 if (en && rc != 0) {
5139 efx_ef10_ptp_set_ts_sync_events(efx, false, temp);
5140 return rc;
5141 }
5142 }
5143
5144 return 0;
5145}
5146
02246a7f
SS		 5147static int efx_ef10_ptp_set_ts_config_vf(struct efx_nic *efx,
5148 struct hwtstamp_config *init)
5149{
5150 return -EOPNOTSUPP;
5151}
5152
bd9a265d
JC		 5153static int efx_ef10_ptp_set_ts_config(struct efx_nic *efx,
5154 struct hwtstamp_config *init)
5155{
5156 int rc;
5157
5158 switch (init->rx_filter) {
5159 case HWTSTAMP_FILTER_NONE:
5160 efx_ef10_ptp_set_ts_sync_events(efx, false, false);
5161 /* if TX timestamping is still requested then leave PTP on */
5162 return efx_ptp_change_mode(efx,
5163 init->tx_type != HWTSTAMP_TX_OFF, 0);
5164 case HWTSTAMP_FILTER_ALL:
5165 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
5166 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
5167 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
5168 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
5169 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
5170 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
5171 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
5172 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
5173 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
5174 case HWTSTAMP_FILTER_PTP_V2_EVENT:
5175 case HWTSTAMP_FILTER_PTP_V2_SYNC:
5176 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
5177 init->rx_filter = HWTSTAMP_FILTER_ALL;
5178 rc = efx_ptp_change_mode(efx, true, 0);
5179 if (!rc)
5180 rc = efx_ef10_ptp_set_ts_sync_events(efx, true, false);
5181 if (rc)
5182 efx_ptp_change_mode(efx, false, 0);
5183 return rc;
5184 default:
5185 return -ERANGE;
5186 }
5187}
5188
4a53ea8a
AR		 5189static int efx_ef10_vlan_rx_add_vid(struct efx_nic *efx, __be16 proto, u16 vid)
5190{
5191 if (proto != htons(ETH_P_8021Q))
5192 return -EINVAL;
5193
5194 return efx_ef10_add_vlan(efx, vid);
5195}
5196
5197static int efx_ef10_vlan_rx_kill_vid(struct efx_nic *efx, __be16 proto, u16 vid)
5198{
5199 if (proto != htons(ETH_P_8021Q))
5200 return -EINVAL;
5201
5202 return efx_ef10_del_vlan(efx, vid);
5203}
5204
100a9db5
AR		 5205#define EF10_OFFLOAD_FEATURES \
5206 (NETIF_F_IP_CSUM | \
4a53ea8a 5207 NETIF_F_HW_VLAN_CTAG_FILTER | \
100a9db5
AR		 5208 NETIF_F_IPV6_CSUM | \
5209 NETIF_F_RXHASH | \
5210 NETIF_F_NTUPLE)
5211
02246a7f 5212const struct efx_nic_type efx_hunt_a0_vf_nic_type = {
6f7f8aa6 5213 .is_vf = true,
02246a7f
SS		 5214 .mem_bar = EFX_MEM_VF_BAR,
5215 .mem_map_size = efx_ef10_mem_map_size,
5216 .probe = efx_ef10_probe_vf,
5217 .remove = efx_ef10_remove,
5218 .dimension_resources = efx_ef10_dimension_resources,
5219 .init = efx_ef10_init_nic,
5220 .fini = efx_port_dummy_op_void,
087e9025 5221 .map_reset_reason = efx_ef10_map_reset_reason,
02246a7f
SS		 5222 .map_reset_flags = efx_ef10_map_reset_flags,
5223 .reset = efx_ef10_reset,
5224 .probe_port = efx_mcdi_port_probe,
5225 .remove_port = efx_mcdi_port_remove,
5226 .fini_dmaq = efx_ef10_fini_dmaq,
5227 .prepare_flr = efx_ef10_prepare_flr,
5228 .finish_flr = efx_port_dummy_op_void,
5229 .describe_stats = efx_ef10_describe_stats,
d7788196 5230 .update_stats = efx_ef10_update_stats_vf,
02246a7f
SS		 5231 .start_stats = efx_port_dummy_op_void,
5232 .pull_stats = efx_port_dummy_op_void,
5233 .stop_stats = efx_port_dummy_op_void,
5234 .set_id_led = efx_mcdi_set_id_led,
5235 .push_irq_moderation = efx_ef10_push_irq_moderation,
862f894c 5236 .reconfigure_mac = efx_ef10_mac_reconfigure_vf,
02246a7f
SS		 5237 .check_mac_fault = efx_mcdi_mac_check_fault,
5238 .reconfigure_port = efx_mcdi_port_reconfigure,
5239 .get_wol = efx_ef10_get_wol_vf,
5240 .set_wol = efx_ef10_set_wol_vf,
5241 .resume_wol = efx_port_dummy_op_void,
5242 .mcdi_request = efx_ef10_mcdi_request,
5243 .mcdi_poll_response = efx_ef10_mcdi_poll_response,
5244 .mcdi_read_response = efx_ef10_mcdi_read_response,
5245 .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot,
c577e59e 5246 .mcdi_reboot_detected = efx_ef10_mcdi_reboot_detected,
02246a7f
SS		 5247 .irq_enable_master = efx_port_dummy_op_void,
5248 .irq_test_generate = efx_ef10_irq_test_generate,
5249 .irq_disable_non_ev = efx_port_dummy_op_void,
5250 .irq_handle_msi = efx_ef10_msi_interrupt,
5251 .irq_handle_legacy = efx_ef10_legacy_interrupt,
5252 .tx_probe = efx_ef10_tx_probe,
5253 .tx_init = efx_ef10_tx_init,
5254 .tx_remove = efx_ef10_tx_remove,
5255 .tx_write = efx_ef10_tx_write,
267c0157 5256 .rx_push_rss_config = efx_ef10_vf_rx_push_rss_config,
02246a7f
SS		 5257 .rx_probe = efx_ef10_rx_probe,
5258 .rx_init = efx_ef10_rx_init,
5259 .rx_remove = efx_ef10_rx_remove,
5260 .rx_write = efx_ef10_rx_write,
5261 .rx_defer_refill = efx_ef10_rx_defer_refill,
5262 .ev_probe = efx_ef10_ev_probe,
5263 .ev_init = efx_ef10_ev_init,
5264 .ev_fini = efx_ef10_ev_fini,
5265 .ev_remove = efx_ef10_ev_remove,
5266 .ev_process = efx_ef10_ev_process,
5267 .ev_read_ack = efx_ef10_ev_read_ack,
5268 .ev_test_generate = efx_ef10_ev_test_generate,
5269 .filter_table_probe = efx_ef10_filter_table_probe,
5270 .filter_table_restore = efx_ef10_filter_table_restore,
5271 .filter_table_remove = efx_ef10_filter_table_remove,
5272 .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter,
5273 .filter_insert = efx_ef10_filter_insert,
5274 .filter_remove_safe = efx_ef10_filter_remove_safe,
5275 .filter_get_safe = efx_ef10_filter_get_safe,
5276 .filter_clear_rx = efx_ef10_filter_clear_rx,
5277 .filter_count_rx_used = efx_ef10_filter_count_rx_used,
5278 .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit,
5279 .filter_get_rx_ids = efx_ef10_filter_get_rx_ids,
5280#ifdef CONFIG_RFS_ACCEL
5281 .filter_rfs_insert = efx_ef10_filter_rfs_insert,
5282 .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one,
5283#endif
5284#ifdef CONFIG_SFC_MTD
5285 .mtd_probe = efx_port_dummy_op_int,
5286#endif
5287 .ptp_write_host_time = efx_ef10_ptp_write_host_time_vf,
5288 .ptp_set_ts_config = efx_ef10_ptp_set_ts_config_vf,
4a53ea8a
AR		 5289 .vlan_rx_add_vid = efx_ef10_vlan_rx_add_vid,
5290 .vlan_rx_kill_vid = efx_ef10_vlan_rx_kill_vid,
02246a7f 5291#ifdef CONFIG_SFC_SRIOV
7b8c7b54
SS		 5292 .vswitching_probe = efx_ef10_vswitching_probe_vf,
5293 .vswitching_restore = efx_ef10_vswitching_restore_vf,
5294 .vswitching_remove = efx_ef10_vswitching_remove_vf,
1d051e00 5295 .sriov_get_phys_port_id = efx_ef10_sriov_get_phys_port_id,
02246a7f 5296#endif
0d5e0fbb 5297 .get_mac_address = efx_ef10_get_mac_address_vf,
910c8789 5298 .set_mac_address = efx_ef10_set_mac_address,
0d5e0fbb 5299
02246a7f
SS		 5300 .revision = EFX_REV_HUNT_A0,
5301 .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH),
5302 .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE,
5303 .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST,
5304 .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST,
5305 .can_rx_scatter = true,
5306 .always_rx_scatter = true,
5307 .max_interrupt_mode = EFX_INT_MODE_MSIX,
5308 .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH,
100a9db5 5309 .offload_features = EF10_OFFLOAD_FEATURES,
02246a7f
SS		 5310 .mcdi_max_ver = 2,
5311 .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS,
5312 .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE |
5313 1 << HWTSTAMP_FILTER_ALL,
5314};
5315
8127d661 5316const struct efx_nic_type efx_hunt_a0_nic_type = {
6f7f8aa6 5317 .is_vf = false,
02246a7f 5318 .mem_bar = EFX_MEM_BAR,
8127d661 5319 .mem_map_size = efx_ef10_mem_map_size,
02246a7f 5320 .probe = efx_ef10_probe_pf,
8127d661
BH		 5321 .remove = efx_ef10_remove,
5322 .dimension_resources = efx_ef10_dimension_resources,
5323 .init = efx_ef10_init_nic,
5324 .fini = efx_port_dummy_op_void,
087e9025 5325 .map_reset_reason = efx_ef10_map_reset_reason,
8127d661 5326 .map_reset_flags = efx_ef10_map_reset_flags,
3e336261 5327 .reset = efx_ef10_reset,
8127d661
BH		 5328 .probe_port = efx_mcdi_port_probe,
5329 .remove_port = efx_mcdi_port_remove,
5330 .fini_dmaq = efx_ef10_fini_dmaq,
e283546c
EC		 5331 .prepare_flr = efx_ef10_prepare_flr,
5332 .finish_flr = efx_port_dummy_op_void,
8127d661 5333 .describe_stats = efx_ef10_describe_stats,
d7788196 5334 .update_stats = efx_ef10_update_stats_pf,
8127d661 5335 .start_stats = efx_mcdi_mac_start_stats,
f8f3b5ae 5336 .pull_stats = efx_mcdi_mac_pull_stats,
8127d661
BH		 5337 .stop_stats = efx_mcdi_mac_stop_stats,
5338 .set_id_led = efx_mcdi_set_id_led,
5339 .push_irq_moderation = efx_ef10_push_irq_moderation,
5340 .reconfigure_mac = efx_ef10_mac_reconfigure,
5341 .check_mac_fault = efx_mcdi_mac_check_fault,
5342 .reconfigure_port = efx_mcdi_port_reconfigure,
5343 .get_wol = efx_ef10_get_wol,
5344 .set_wol = efx_ef10_set_wol,
5345 .resume_wol = efx_port_dummy_op_void,
74cd60a4 5346 .test_chip = efx_ef10_test_chip,
8127d661
BH		 5347 .test_nvram = efx_mcdi_nvram_test_all,
5348 .mcdi_request = efx_ef10_mcdi_request,
5349 .mcdi_poll_response = efx_ef10_mcdi_poll_response,
5350 .mcdi_read_response = efx_ef10_mcdi_read_response,
5351 .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot,
c577e59e 5352 .mcdi_reboot_detected = efx_ef10_mcdi_reboot_detected,
8127d661
BH		 5353 .irq_enable_master = efx_port_dummy_op_void,
5354 .irq_test_generate = efx_ef10_irq_test_generate,
5355 .irq_disable_non_ev = efx_port_dummy_op_void,
5356 .irq_handle_msi = efx_ef10_msi_interrupt,
5357 .irq_handle_legacy = efx_ef10_legacy_interrupt,
5358 .tx_probe = efx_ef10_tx_probe,
5359 .tx_init = efx_ef10_tx_init,
5360 .tx_remove = efx_ef10_tx_remove,
5361 .tx_write = efx_ef10_tx_write,
267c0157 5362 .rx_push_rss_config = efx_ef10_pf_rx_push_rss_config,
8127d661
BH		 5363 .rx_probe = efx_ef10_rx_probe,
5364 .rx_init = efx_ef10_rx_init,
5365 .rx_remove = efx_ef10_rx_remove,
5366 .rx_write = efx_ef10_rx_write,
5367 .rx_defer_refill = efx_ef10_rx_defer_refill,
5368 .ev_probe = efx_ef10_ev_probe,
5369 .ev_init = efx_ef10_ev_init,
5370 .ev_fini = efx_ef10_ev_fini,
5371 .ev_remove = efx_ef10_ev_remove,
5372 .ev_process = efx_ef10_ev_process,
5373 .ev_read_ack = efx_ef10_ev_read_ack,
5374 .ev_test_generate = efx_ef10_ev_test_generate,
5375 .filter_table_probe = efx_ef10_filter_table_probe,
5376 .filter_table_restore = efx_ef10_filter_table_restore,
5377 .filter_table_remove = efx_ef10_filter_table_remove,
5378 .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter,
5379 .filter_insert = efx_ef10_filter_insert,
5380 .filter_remove_safe = efx_ef10_filter_remove_safe,
5381 .filter_get_safe = efx_ef10_filter_get_safe,
5382 .filter_clear_rx = efx_ef10_filter_clear_rx,
5383 .filter_count_rx_used = efx_ef10_filter_count_rx_used,
5384 .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit,
5385 .filter_get_rx_ids = efx_ef10_filter_get_rx_ids,
5386#ifdef CONFIG_RFS_ACCEL
5387 .filter_rfs_insert = efx_ef10_filter_rfs_insert,
5388 .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one,
5389#endif
5390#ifdef CONFIG_SFC_MTD
5391 .mtd_probe = efx_ef10_mtd_probe,
5392 .mtd_rename = efx_mcdi_mtd_rename,
5393 .mtd_read = efx_mcdi_mtd_read,
5394 .mtd_erase = efx_mcdi_mtd_erase,
5395 .mtd_write = efx_mcdi_mtd_write,
5396 .mtd_sync = efx_mcdi_mtd_sync,
5397#endif
5398 .ptp_write_host_time = efx_ef10_ptp_write_host_time,
bd9a265d
JC		 5399 .ptp_set_ts_sync_events = efx_ef10_ptp_set_ts_sync_events,
5400 .ptp_set_ts_config = efx_ef10_ptp_set_ts_config,
4a53ea8a
AR		 5401 .vlan_rx_add_vid = efx_ef10_vlan_rx_add_vid,
5402 .vlan_rx_kill_vid = efx_ef10_vlan_rx_kill_vid,
7fa8d547 5403#ifdef CONFIG_SFC_SRIOV
834e23dd 5404 .sriov_configure = efx_ef10_sriov_configure,
d98a4ffe
SS		 5405 .sriov_init = efx_ef10_sriov_init,
5406 .sriov_fini = efx_ef10_sriov_fini,
d98a4ffe
SS		 5407 .sriov_wanted = efx_ef10_sriov_wanted,
5408 .sriov_reset = efx_ef10_sriov_reset,
7fa8d547
SS		 5409 .sriov_flr = efx_ef10_sriov_flr,
5410 .sriov_set_vf_mac = efx_ef10_sriov_set_vf_mac,
5411 .sriov_set_vf_vlan = efx_ef10_sriov_set_vf_vlan,
5412 .sriov_set_vf_spoofchk = efx_ef10_sriov_set_vf_spoofchk,
5413 .sriov_get_vf_config = efx_ef10_sriov_get_vf_config,
4392dc69 5414 .sriov_set_vf_link_state = efx_ef10_sriov_set_vf_link_state,
7b8c7b54
SS		 5415 .vswitching_probe = efx_ef10_vswitching_probe_pf,
5416 .vswitching_restore = efx_ef10_vswitching_restore_pf,
5417 .vswitching_remove = efx_ef10_vswitching_remove_pf,
7fa8d547 5418#endif
0d5e0fbb 5419 .get_mac_address = efx_ef10_get_mac_address_pf,
910c8789 5420 .set_mac_address = efx_ef10_set_mac_address,
8127d661
BH		 5421
5422 .revision = EFX_REV_HUNT_A0,
5423 .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH),
5424 .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE,
5425 .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST,
bd9a265d 5426 .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST,
8127d661
BH		 5427 .can_rx_scatter = true,
5428 .always_rx_scatter = true,
5429 .max_interrupt_mode = EFX_INT_MODE_MSIX,
5430 .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH,
100a9db5 5431 .offload_features = EF10_OFFLOAD_FEATURES,
8127d661
BH		 5432 .mcdi_max_ver = 2,
5433 .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS,
bd9a265d
JC		 5434 .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE |
5435 1 << HWTSTAMP_FILTER_ALL,
8127d661 5436};
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