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sfc: update MCDI protocol headers
[mirror_ubuntu-focal-kernel.git] / drivers / net / ethernet / sfc / ef10.c
CommitLineData
8127d661
BH		 1/****************************************************************************
2 * Driver for Solarflare network controllers and boards
3 * Copyright 2012-2013 Solarflare Communications Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published
7 * by the Free Software Foundation, incorporated herein by reference.
8 */
9
10#include "net_driver.h"
11#include "ef10_regs.h"
12#include "io.h"
13#include "mcdi.h"
14#include "mcdi_pcol.h"
15#include "nic.h"
16#include "workarounds.h"
74cd60a4 17#include "selftest.h"
7fa8d547 18#include "ef10_sriov.h"
8127d661
BH		 19#include <linux/in.h>
20#include <linux/jhash.h>
21#include <linux/wait.h>
22#include <linux/workqueue.h>
23
24/* Hardware control for EF10 architecture including 'Huntington'. */
25
26#define EFX_EF10_DRVGEN_EV 7
27enum {
28 EFX_EF10_TEST = 1,
29 EFX_EF10_REFILL,
30};
31
32/* The reserved RSS context value */
33#define EFX_EF10_RSS_CONTEXT_INVALID 0xffffffff
267c0157
JC		 34/* The maximum size of a shared RSS context */
35/* TODO: this should really be from the mcdi protocol export */
36#define EFX_EF10_MAX_SHARED_RSS_CONTEXT_SIZE 64UL
8127d661
BH		 37
38/* The filter table(s) are managed by firmware and we have write-only
39 * access. When removing filters we must identify them to the
40 * firmware by a 64-bit handle, but this is too wide for Linux kernel
41 * interfaces (32-bit for RX NFC, 16-bit for RFS). Also, we need to
42 * be able to tell in advance whether a requested insertion will
43 * replace an existing filter. Therefore we maintain a software hash
44 * table, which should be at least as large as the hardware hash
45 * table.
46 *
47 * Huntington has a single 8K filter table shared between all filter
48 * types and both ports.
49 */
50#define HUNT_FILTER_TBL_ROWS 8192
51
12fb0da4 52#define EFX_EF10_FILTER_ID_INVALID 0xffff
dc3273e0
AR		 53
54#define EFX_EF10_FILTER_DEV_UC_MAX 32
55#define EFX_EF10_FILTER_DEV_MC_MAX 256
56
34813fe2
AR		 57/* VLAN list entry */
58struct efx_ef10_vlan {
59 struct list_head list;
60 u16 vid;
61};
62
9b410801
EC		 63enum efx_ef10_default_filters {
64 EFX_EF10_BCAST,
65 EFX_EF10_UCDEF,
66 EFX_EF10_MCDEF,
67 EFX_EF10_VXLAN4_UCDEF,
68 EFX_EF10_VXLAN4_MCDEF,
69 EFX_EF10_VXLAN6_UCDEF,
70 EFX_EF10_VXLAN6_MCDEF,
71 EFX_EF10_NVGRE4_UCDEF,
72 EFX_EF10_NVGRE4_MCDEF,
73 EFX_EF10_NVGRE6_UCDEF,
74 EFX_EF10_NVGRE6_MCDEF,
75 EFX_EF10_GENEVE4_UCDEF,
76 EFX_EF10_GENEVE4_MCDEF,
77 EFX_EF10_GENEVE6_UCDEF,
78 EFX_EF10_GENEVE6_MCDEF,
79
80 EFX_EF10_NUM_DEFAULT_FILTERS
81};
82
dc3273e0
AR		 83/* Per-VLAN filters information */
84struct efx_ef10_filter_vlan {
34813fe2 85 struct list_head list;
b3a3c03c 86 u16 vid;
dc3273e0
AR		 87 u16 uc[EFX_EF10_FILTER_DEV_UC_MAX];
88 u16 mc[EFX_EF10_FILTER_DEV_MC_MAX];
9b410801 89 u16 default_filters[EFX_EF10_NUM_DEFAULT_FILTERS];
dc3273e0
AR		 90};
91
822b96f8
DP		 92struct efx_ef10_dev_addr {
93 u8 addr[ETH_ALEN];
822b96f8
DP		 94};
95
8127d661 96struct efx_ef10_filter_table {
7ac0dd9d
AR		 97/* The MCDI match masks supported by this fw & hw, in order of priority */
98 u32 rx_match_mcdi_flags[
9b410801 99 MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM * 2];
8127d661
BH		 100 unsigned int rx_match_count;
101
102 struct {
103 unsigned long spec; /* pointer to spec plus flag bits */
b59e6ef8
BH		 104/* BUSY flag indicates that an update is in progress. AUTO_OLD is
105 * used to mark and sweep MAC filters for the device address lists.
8127d661
BH		 106 */
107#define EFX_EF10_FILTER_FLAG_BUSY 1UL
b59e6ef8 108#define EFX_EF10_FILTER_FLAG_AUTO_OLD 2UL
8127d661
BH		 109#define EFX_EF10_FILTER_FLAGS 3UL
110 u64 handle; /* firmware handle */
111 } *entry;
112 wait_queue_head_t waitq;
113/* Shadow of net_device address lists, guarded by mac_lock */
822b96f8
DP		 114 struct efx_ef10_dev_addr dev_uc_list[EFX_EF10_FILTER_DEV_UC_MAX];
115 struct efx_ef10_dev_addr dev_mc_list[EFX_EF10_FILTER_DEV_MC_MAX];
12fb0da4
EC		 116 int dev_uc_count;
117 int dev_mc_count;
afa4ce12
AR		 118 bool uc_promisc;
119 bool mc_promisc;
b071c3a2
AR		 120/* Whether in multicast promiscuous mode when last changed */
121 bool mc_promisc_last;
148cbab6 122 bool mc_overflow; /* Too many MC addrs; should always imply mc_promisc */
4a53ea8a 123 bool vlan_filter;
34813fe2 124 struct list_head vlan_list;
8127d661
BH		 125};
126
127/* An arbitrary search limit for the software hash table */
128#define EFX_EF10_FILTER_SEARCH_LIMIT 200
129
8127d661
BH		 130static void efx_ef10_rx_free_indir_table(struct efx_nic *efx);
131static void efx_ef10_filter_table_remove(struct efx_nic *efx);
34813fe2
AR		 132static int efx_ef10_filter_add_vlan(struct efx_nic *efx, u16 vid);
133static void efx_ef10_filter_del_vlan_internal(struct efx_nic *efx,
134 struct efx_ef10_filter_vlan *vlan);
135static void efx_ef10_filter_del_vlan(struct efx_nic *efx, u16 vid);
e5fbd977 136static int efx_ef10_set_udp_tnl_ports(struct efx_nic *efx, bool unloading);
8127d661 137
0ccb998b
JC		 138static u32 efx_ef10_filter_get_unsafe_id(u32 filter_id)
139{
140 WARN_ON_ONCE(filter_id == EFX_EF10_FILTER_ID_INVALID);
141 return filter_id & (HUNT_FILTER_TBL_ROWS - 1);
142}
143
144static unsigned int efx_ef10_filter_get_unsafe_pri(u32 filter_id)
145{
146 return filter_id / (HUNT_FILTER_TBL_ROWS * 2);
147}
148
149static u32 efx_ef10_make_filter_id(unsigned int pri, u16 idx)
150{
151 return pri * HUNT_FILTER_TBL_ROWS * 2 + idx;
152}
153
8127d661
BH		 154static int efx_ef10_get_warm_boot_count(struct efx_nic *efx)
155{
156 efx_dword_t reg;
157
158 efx_readd(efx, &reg, ER_DZ_BIU_MC_SFT_STATUS);
159 return EFX_DWORD_FIELD(reg, EFX_WORD_1) == 0xb007 ?
160 EFX_DWORD_FIELD(reg, EFX_WORD_0) : -EIO;
161}
162
03714bbb
EC		 163/* On all EF10s up to and including SFC9220 (Medford1), all PFs use BAR 0 for
164 * I/O space and BAR 2(&3) for memory. On SFC9250 (Medford2), there is no I/O
165 * bar; PFs use BAR 0/1 for memory.
166 */
167static unsigned int efx_ef10_pf_mem_bar(struct efx_nic *efx)
168{
169 switch (efx->pci_dev->device) {
170 case 0x0b03: /* SFC9250 PF */
171 return 0;
172 default:
173 return 2;
174 }
175}
176
177/* All VFs use BAR 0/1 for memory */
178static unsigned int efx_ef10_vf_mem_bar(struct efx_nic *efx)
179{
180 return 0;
181}
182
8127d661
BH		 183static unsigned int efx_ef10_mem_map_size(struct efx_nic *efx)
184{
02246a7f
SS		 185 int bar;
186
03714bbb 187 bar = efx->type->mem_bar(efx);
02246a7f 188 return resource_size(&efx->pci_dev->resource[bar]);
8127d661
BH		 189}
190
7a186f47
DP		 191static bool efx_ef10_is_vf(struct efx_nic *efx)
192{
193 return efx->type->is_vf;
194}
195
1cd9ecbb
DP		 196static int efx_ef10_get_pf_index(struct efx_nic *efx)
197{
198 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN);
199 struct efx_ef10_nic_data *nic_data = efx->nic_data;
200 size_t outlen;
201 int rc;
202
203 rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf,
204 sizeof(outbuf), &outlen);
205 if (rc)
206 return rc;
207 if (outlen < sizeof(outbuf))
208 return -EIO;
209
210 nic_data->pf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_PF);
211 return 0;
212}
213
88a37de6
SS		 214#ifdef CONFIG_SFC_SRIOV
215static int efx_ef10_get_vf_index(struct efx_nic *efx)
216{
217 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN);
218 struct efx_ef10_nic_data *nic_data = efx->nic_data;
219 size_t outlen;
220 int rc;
221
222 rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf,
223 sizeof(outbuf), &outlen);
224 if (rc)
225 return rc;
226 if (outlen < sizeof(outbuf))
227 return -EIO;
228
229 nic_data->vf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_VF);
230 return 0;
231}
232#endif
233
e5a2538a 234static int efx_ef10_init_datapath_caps(struct efx_nic *efx)
8127d661 235{
71827443 236 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CAPABILITIES_V3_OUT_LEN);
8127d661
BH		 237 struct efx_ef10_nic_data *nic_data = efx->nic_data;
238 size_t outlen;
239 int rc;
240
241 BUILD_BUG_ON(MC_CMD_GET_CAPABILITIES_IN_LEN != 0);
242
243 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CAPABILITIES, NULL, 0,
244 outbuf, sizeof(outbuf), &outlen);
245 if (rc)
246 return rc;
ca889a05 247 if (outlen < MC_CMD_GET_CAPABILITIES_OUT_LEN) {
e5a2538a
BH		 248 netif_err(efx, drv, efx->net_dev,
249 "unable to read datapath firmware capabilities\n");
250 return -EIO;
251 }
252
253 nic_data->datapath_caps =
254 MCDI_DWORD(outbuf, GET_CAPABILITIES_OUT_FLAGS1);
8127d661 255
c634700f 256 if (outlen >= MC_CMD_GET_CAPABILITIES_V2_OUT_LEN) {
ca889a05
BK		 257 nic_data->datapath_caps2 = MCDI_DWORD(outbuf,
258 GET_CAPABILITIES_V2_OUT_FLAGS2);
c634700f
EC		 259 nic_data->piobuf_size = MCDI_WORD(outbuf,
260 GET_CAPABILITIES_V2_OUT_SIZE_PIO_BUFF);
261 } else {
ca889a05 262 nic_data->datapath_caps2 = 0;
c634700f
EC		 263 nic_data->piobuf_size = ER_DZ_TX_PIOBUF_SIZE;
264 }
ca889a05 265
8d9f9dd4
DP		 266 /* record the DPCPU firmware IDs to determine VEB vswitching support.
267 */
268 nic_data->rx_dpcpu_fw_id =
269 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID);
270 nic_data->tx_dpcpu_fw_id =
271 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID);
272
e5a2538a
BH		 273 if (!(nic_data->datapath_caps &
274 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN))) {
275 netif_err(efx, probe, efx->net_dev,
276 "current firmware does not support an RX prefix\n");
277 return -ENODEV;
8127d661
BH		 278 }
279
71827443
EC		 280 if (outlen >= MC_CMD_GET_CAPABILITIES_V3_OUT_LEN) {
281 u8 vi_window_mode = MCDI_BYTE(outbuf,
282 GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE);
283
284 switch (vi_window_mode) {
285 case MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_8K:
286 efx->vi_stride = 8192;
287 break;
288 case MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_16K:
289 efx->vi_stride = 16384;
290 break;
291 case MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_64K:
292 efx->vi_stride = 65536;
293 break;
294 default:
295 netif_err(efx, probe, efx->net_dev,
296 "Unrecognised VI window mode %d\n",
297 vi_window_mode);
298 return -EIO;
299 }
300 netif_dbg(efx, probe, efx->net_dev, "vi_stride = %u\n",
301 efx->vi_stride);
302 } else {
303 /* keep default VI stride */
304 netif_dbg(efx, probe, efx->net_dev,
305 "firmware did not report VI window mode, assuming vi_stride = %u\n",
306 efx->vi_stride);
307 }
308
8127d661
BH		 309 return 0;
310}
311
312static int efx_ef10_get_sysclk_freq(struct efx_nic *efx)
313{
314 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CLOCK_OUT_LEN);
315 int rc;
316
317 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CLOCK, NULL, 0,
318 outbuf, sizeof(outbuf), NULL);
319 if (rc)
320 return rc;
321 rc = MCDI_DWORD(outbuf, GET_CLOCK_OUT_SYS_FREQ);
322 return rc > 0 ? rc : -ERANGE;
323}
324
d95e329a
BK		 325static int efx_ef10_get_timer_workarounds(struct efx_nic *efx)
326{
327 struct efx_ef10_nic_data *nic_data = efx->nic_data;
328 unsigned int implemented;
329 unsigned int enabled;
330 int rc;
331
332 nic_data->workaround_35388 = false;
333 nic_data->workaround_61265 = false;
334
335 rc = efx_mcdi_get_workarounds(efx, &implemented, &enabled);
336
337 if (rc == -ENOSYS) {
338 /* Firmware without GET_WORKAROUNDS - not a problem. */
339 rc = 0;
340 } else if (rc == 0) {
341 /* Bug61265 workaround is always enabled if implemented. */
342 if (enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG61265)
343 nic_data->workaround_61265 = true;
344
345 if (enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG35388) {
346 nic_data->workaround_35388 = true;
347 } else if (implemented & MC_CMD_GET_WORKAROUNDS_OUT_BUG35388) {
348 /* Workaround is implemented but not enabled.
349 * Try to enable it.
350 */
351 rc = efx_mcdi_set_workaround(efx,
352 MC_CMD_WORKAROUND_BUG35388,
353 true, NULL);
354 if (rc == 0)
355 nic_data->workaround_35388 = true;
356 /* If we failed to set the workaround just carry on. */
357 rc = 0;
358 }
359 }
360
361 netif_dbg(efx, probe, efx->net_dev,
362 "workaround for bug 35388 is %sabled\n",
363 nic_data->workaround_35388 ? "en" : "dis");
364 netif_dbg(efx, probe, efx->net_dev,
365 "workaround for bug 61265 is %sabled\n",
366 nic_data->workaround_61265 ? "en" : "dis");
367
368 return rc;
369}
370
371static void efx_ef10_process_timer_config(struct efx_nic *efx,
372 const efx_dword_t *data)
373{
374 unsigned int max_count;
375
376 if (EFX_EF10_WORKAROUND_61265(efx)) {
377 efx->timer_quantum_ns = MCDI_DWORD(data,
378 GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_STEP_NS);
379 efx->timer_max_ns = MCDI_DWORD(data,
380 GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_MAX_NS);
381 } else if (EFX_EF10_WORKAROUND_35388(efx)) {
382 efx->timer_quantum_ns = MCDI_DWORD(data,
383 GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_NS_PER_COUNT);
384 max_count = MCDI_DWORD(data,
385 GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_MAX_COUNT);
386 efx->timer_max_ns = max_count * efx->timer_quantum_ns;
387 } else {
388 efx->timer_quantum_ns = MCDI_DWORD(data,
389 GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_NS_PER_COUNT);
390 max_count = MCDI_DWORD(data,
391 GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_MAX_COUNT);
392 efx->timer_max_ns = max_count * efx->timer_quantum_ns;
393 }
394
395 netif_dbg(efx, probe, efx->net_dev,
396 "got timer properties from MC: quantum %u ns; max %u ns\n",
397 efx->timer_quantum_ns, efx->timer_max_ns);
398}
399
400static int efx_ef10_get_timer_config(struct efx_nic *efx)
401{
402 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_LEN);
403 int rc;
404
405 rc = efx_ef10_get_timer_workarounds(efx);
406 if (rc)
407 return rc;
408
409 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_GET_EVQ_TMR_PROPERTIES, NULL, 0,
410 outbuf, sizeof(outbuf), NULL);
411
412 if (rc == 0) {
413 efx_ef10_process_timer_config(efx, outbuf);
414 } else if (rc == -ENOSYS || rc == -EPERM) {
415 /* Not available - fall back to Huntington defaults. */
416 unsigned int quantum;
417
418 rc = efx_ef10_get_sysclk_freq(efx);
419 if (rc < 0)
420 return rc;
421
422 quantum = 1536000 / rc; /* 1536 cycles */
423 efx->timer_quantum_ns = quantum;
424 efx->timer_max_ns = efx->type->timer_period_max * quantum;
425 rc = 0;
426 } else {
427 efx_mcdi_display_error(efx, MC_CMD_GET_EVQ_TMR_PROPERTIES,
428 MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_LEN,
429 NULL, 0, rc);
430 }
431
432 return rc;
433}
434
0d5e0fbb 435static int efx_ef10_get_mac_address_pf(struct efx_nic *efx, u8 *mac_address)
8127d661
BH		 436{
437 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_MAC_ADDRESSES_OUT_LEN);
438 size_t outlen;
439 int rc;
440
441 BUILD_BUG_ON(MC_CMD_GET_MAC_ADDRESSES_IN_LEN != 0);
442
443 rc = efx_mcdi_rpc(efx, MC_CMD_GET_MAC_ADDRESSES, NULL, 0,
444 outbuf, sizeof(outbuf), &outlen);
445 if (rc)
446 return rc;
447 if (outlen < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN)
448 return -EIO;
449
cd84ff4d
EC		 450 ether_addr_copy(mac_address,
451 MCDI_PTR(outbuf, GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE));
8127d661
BH		 452 return 0;
453}
454
0d5e0fbb
DP		 455static int efx_ef10_get_mac_address_vf(struct efx_nic *efx, u8 *mac_address)
456{
457 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN);
458 MCDI_DECLARE_BUF(outbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX);
459 size_t outlen;
460 int num_addrs, rc;
461
462 MCDI_SET_DWORD(inbuf, VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID,
463 EVB_PORT_ID_ASSIGNED);
464 rc = efx_mcdi_rpc(efx, MC_CMD_VPORT_GET_MAC_ADDRESSES, inbuf,
465 sizeof(inbuf), outbuf, sizeof(outbuf), &outlen);
466
467 if (rc)
468 return rc;
469 if (outlen < MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN)
470 return -EIO;
471
472 num_addrs = MCDI_DWORD(outbuf,
473 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT);
474
475 WARN_ON(num_addrs != 1);
476
477 ether_addr_copy(mac_address,
478 MCDI_PTR(outbuf, VPORT_GET_MAC_ADDRESSES_OUT_MACADDR));
479
480 return 0;
481}
482
0f5c0845
SS		 483static ssize_t efx_ef10_show_link_control_flag(struct device *dev,
484 struct device_attribute *attr,
485 char *buf)
486{
487 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
488
489 return sprintf(buf, "%d\n",
490 ((efx->mcdi->fn_flags) &
491 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL))
492 ? 1 : 0);
493}
494
495static ssize_t efx_ef10_show_primary_flag(struct device *dev,
496 struct device_attribute *attr,
497 char *buf)
498{
499 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
500
501 return sprintf(buf, "%d\n",
502 ((efx->mcdi->fn_flags) &
503 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY))
504 ? 1 : 0);
505}
506
34813fe2
AR		 507static struct efx_ef10_vlan *efx_ef10_find_vlan(struct efx_nic *efx, u16 vid)
508{
509 struct efx_ef10_nic_data *nic_data = efx->nic_data;
510 struct efx_ef10_vlan *vlan;
511
512 WARN_ON(!mutex_is_locked(&nic_data->vlan_lock));
513
514 list_for_each_entry(vlan, &nic_data->vlan_list, list) {
515 if (vlan->vid == vid)
516 return vlan;
517 }
518
519 return NULL;
520}
521
522static int efx_ef10_add_vlan(struct efx_nic *efx, u16 vid)
523{
524 struct efx_ef10_nic_data *nic_data = efx->nic_data;
525 struct efx_ef10_vlan *vlan;
526 int rc;
527
528 mutex_lock(&nic_data->vlan_lock);
529
530 vlan = efx_ef10_find_vlan(efx, vid);
531 if (vlan) {
4a53ea8a
AR		 532 /* We add VID 0 on init. 8021q adds it on module init
533 * for all interfaces with VLAN filtring feature.
534 */
535 if (vid == 0)
536 goto done_unlock;
34813fe2
AR		 537 netif_warn(efx, drv, efx->net_dev,
538 "VLAN %u already added\n", vid);
539 rc = -EALREADY;
540 goto fail_exist;
541 }
542
543 rc = -ENOMEM;
544 vlan = kzalloc(sizeof(*vlan), GFP_KERNEL);
545 if (!vlan)
546 goto fail_alloc;
547
548 vlan->vid = vid;
549
550 list_add_tail(&vlan->list, &nic_data->vlan_list);
551
552 if (efx->filter_state) {
553 mutex_lock(&efx->mac_lock);
554 down_write(&efx->filter_sem);
555 rc = efx_ef10_filter_add_vlan(efx, vlan->vid);
556 up_write(&efx->filter_sem);
557 mutex_unlock(&efx->mac_lock);
558 if (rc)
559 goto fail_filter_add_vlan;
560 }
561
4a53ea8a 562done_unlock:
34813fe2
AR		 563 mutex_unlock(&nic_data->vlan_lock);
564 return 0;
565
566fail_filter_add_vlan:
567 list_del(&vlan->list);
568 kfree(vlan);
569fail_alloc:
570fail_exist:
571 mutex_unlock(&nic_data->vlan_lock);
572 return rc;
573}
574
575static void efx_ef10_del_vlan_internal(struct efx_nic *efx,
576 struct efx_ef10_vlan *vlan)
577{
578 struct efx_ef10_nic_data *nic_data = efx->nic_data;
579
580 WARN_ON(!mutex_is_locked(&nic_data->vlan_lock));
581
582 if (efx->filter_state) {
583 down_write(&efx->filter_sem);
584 efx_ef10_filter_del_vlan(efx, vlan->vid);
585 up_write(&efx->filter_sem);
586 }
587
588 list_del(&vlan->list);
589 kfree(vlan);
590}
591
4a53ea8a
AR		 592static int efx_ef10_del_vlan(struct efx_nic *efx, u16 vid)
593{
594 struct efx_ef10_nic_data *nic_data = efx->nic_data;
595 struct efx_ef10_vlan *vlan;
596 int rc = 0;
597
598 /* 8021q removes VID 0 on module unload for all interfaces
599 * with VLAN filtering feature. We need to keep it to receive
600 * untagged traffic.
601 */
602 if (vid == 0)
603 return 0;
604
605 mutex_lock(&nic_data->vlan_lock);
606
607 vlan = efx_ef10_find_vlan(efx, vid);
608 if (!vlan) {
609 netif_err(efx, drv, efx->net_dev,
610 "VLAN %u to be deleted not found\n", vid);
611 rc = -ENOENT;
612 } else {
613 efx_ef10_del_vlan_internal(efx, vlan);
614 }
615
616 mutex_unlock(&nic_data->vlan_lock);
617
618 return rc;
619}
620
34813fe2
AR		 621static void efx_ef10_cleanup_vlans(struct efx_nic *efx)
622{
623 struct efx_ef10_nic_data *nic_data = efx->nic_data;
624 struct efx_ef10_vlan *vlan, *next_vlan;
625
626 mutex_lock(&nic_data->vlan_lock);
627 list_for_each_entry_safe(vlan, next_vlan, &nic_data->vlan_list, list)
628 efx_ef10_del_vlan_internal(efx, vlan);
629 mutex_unlock(&nic_data->vlan_lock);
630}
631
0f5c0845
SS		 632static DEVICE_ATTR(link_control_flag, 0444, efx_ef10_show_link_control_flag,
633 NULL);
634static DEVICE_ATTR(primary_flag, 0444, efx_ef10_show_primary_flag, NULL);
635
8127d661
BH		 636static int efx_ef10_probe(struct efx_nic *efx)
637{
638 struct efx_ef10_nic_data *nic_data;
639 int i, rc;
640
8127d661
BH		 641 nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
642 if (!nic_data)
643 return -ENOMEM;
644 efx->nic_data = nic_data;
645
75aba2a5
EC		 646 /* we assume later that we can copy from this buffer in dwords */
647 BUILD_BUG_ON(MCDI_CTL_SDU_LEN_MAX_V2 % 4);
648
8127d661
BH		 649 rc = efx_nic_alloc_buffer(efx, &nic_data->mcdi_buf,
650 8 + MCDI_CTL_SDU_LEN_MAX_V2, GFP_KERNEL);
651 if (rc)
652 goto fail1;
653
654 /* Get the MC's warm boot count. In case it's rebooting right
655 * now, be prepared to retry.
656 */
657 i = 0;
658 for (;;) {
659 rc = efx_ef10_get_warm_boot_count(efx);
660 if (rc >= 0)
661 break;
662 if (++i == 5)
663 goto fail2;
664 ssleep(1);
665 }
666 nic_data->warm_boot_count = rc;
667
668 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
669
45b2449e
DP		 670 nic_data->vport_id = EVB_PORT_ID_ASSIGNED;
671
8127d661
BH		 672 /* In case we're recovering from a crash (kexec), we want to
673 * cancel any outstanding request by the previous user of this
674 * function. We send a special message using the least
675 * significant bits of the 'high' (doorbell) register.
676 */
677 _efx_writed(efx, cpu_to_le32(1), ER_DZ_MC_DB_HWRD);
678
679 rc = efx_mcdi_init(efx);
680 if (rc)
681 goto fail2;
682
e5fbd977
JC		 683 mutex_init(&nic_data->udp_tunnels_lock);
684
8127d661
BH		 685 /* Reset (most) configuration for this function */
686 rc = efx_mcdi_reset(efx, RESET_TYPE_ALL);
687 if (rc)
688 goto fail3;
689
690 /* Enable event logging */
691 rc = efx_mcdi_log_ctrl(efx, true, false, 0);
692 if (rc)
693 goto fail3;
694
0f5c0845
SS		 695 rc = device_create_file(&efx->pci_dev->dev,
696 &dev_attr_link_control_flag);
1cd9ecbb
DP		 697 if (rc)
698 goto fail3;
699
0f5c0845
SS		 700 rc = device_create_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
701 if (rc)
702 goto fail4;
703
704 rc = efx_ef10_get_pf_index(efx);
705 if (rc)
706 goto fail5;
707
e5a2538a 708 rc = efx_ef10_init_datapath_caps(efx);
8127d661 709 if (rc < 0)
0f5c0845 710 goto fail5;
8127d661 711
71827443
EC		 712 /* We can have one VI for each vi_stride-byte region.
713 * However, until we use TX option descriptors we need two TX queues
714 * per channel.
715 */
716 efx->max_channels = min_t(unsigned int,
717 EFX_MAX_CHANNELS,
718 efx_ef10_mem_map_size(efx) /
719 (efx->vi_stride * EFX_TXQ_TYPES));
720 efx->max_tx_channels = efx->max_channels;
721 if (WARN_ON(efx->max_channels == 0)) {
722 rc = -EIO;
723 goto fail5;
724 }
725
8127d661
BH		 726 efx->rx_packet_len_offset =
727 ES_DZ_RX_PREFIX_PKTLEN_OFST - ES_DZ_RX_PREFIX_SIZE;
728
6978729f
EC		 729 if (nic_data->datapath_caps &
730 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_INCLUDE_FCS_LBN))
731 efx->net_dev->hw_features |= NETIF_F_RXFCS;
732
8127d661
BH		 733 rc = efx_mcdi_port_get_number(efx);
734 if (rc < 0)
0f5c0845 735 goto fail5;
8127d661
BH		 736 efx->port_num = rc;
737
0d5e0fbb 738 rc = efx->type->get_mac_address(efx, efx->net_dev->perm_addr);
8127d661 739 if (rc)
0f5c0845 740 goto fail5;
8127d661 741
d95e329a 742 rc = efx_ef10_get_timer_config(efx);
8127d661 743 if (rc < 0)
0f5c0845 744 goto fail5;
8127d661 745
8127d661 746 rc = efx_mcdi_mon_probe(efx);
267d9d73 747 if (rc && rc != -EPERM)
0f5c0845 748 goto fail5;
8127d661 749
acaef3c1
EC		 750 rc = efx_ptp_probe(efx, NULL);
751 /* Failure to probe PTP is not fatal.
752 * In the case of EPERM, efx_ptp_probe will print its own message (in
753 * efx_ptp_get_attributes()), so we don't need to.
754 */
755 if (rc && rc != -EPERM)
756 netif_warn(efx, drv, efx->net_dev,
757 "Failed to probe PTP, rc=%d\n", rc);
9aecda95 758
1d051e00
SS		 759#ifdef CONFIG_SFC_SRIOV
760 if ((efx->pci_dev->physfn) && (!efx->pci_dev->is_physfn)) {
761 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn;
762 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
763
764 efx_pf->type->get_mac_address(efx_pf, nic_data->port_id);
765 } else
766#endif
767 ether_addr_copy(nic_data->port_id, efx->net_dev->perm_addr);
768
34813fe2
AR		 769 INIT_LIST_HEAD(&nic_data->vlan_list);
770 mutex_init(&nic_data->vlan_lock);
771
772 /* Add unspecified VID to support VLAN filtering being disabled */
773 rc = efx_ef10_add_vlan(efx, EFX_FILTER_VID_UNSPEC);
774 if (rc)
775 goto fail_add_vid_unspec;
776
4a53ea8a
AR		 777 /* If VLAN filtering is enabled, we need VID 0 to get untagged
778 * traffic. It is added automatically if 8021q module is loaded,
779 * but we can't rely on it since module may be not loaded.
780 */
781 rc = efx_ef10_add_vlan(efx, 0);
782 if (rc)
783 goto fail_add_vid_0;
784
8127d661
BH		 785 return 0;
786
4a53ea8a
AR		 787fail_add_vid_0:
788 efx_ef10_cleanup_vlans(efx);
34813fe2
AR		 789fail_add_vid_unspec:
790 mutex_destroy(&nic_data->vlan_lock);
791 efx_ptp_remove(efx);
792 efx_mcdi_mon_remove(efx);
0f5c0845
SS		 793fail5:
794 device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
795fail4:
796 device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag);
8127d661 797fail3:
e5fbd977
JC		 798 efx_mcdi_detach(efx);
799
800 mutex_lock(&nic_data->udp_tunnels_lock);
801 memset(nic_data->udp_tunnels, 0, sizeof(nic_data->udp_tunnels));
802 (void)efx_ef10_set_udp_tnl_ports(efx, true);
803 mutex_unlock(&nic_data->udp_tunnels_lock);
804 mutex_destroy(&nic_data->udp_tunnels_lock);
805
8127d661
BH		 806 efx_mcdi_fini(efx);
807fail2:
808 efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
809fail1:
810 kfree(nic_data);
811 efx->nic_data = NULL;
812 return rc;
813}
814
815static int efx_ef10_free_vis(struct efx_nic *efx)
816{
aa09a3da 817 MCDI_DECLARE_BUF_ERR(outbuf);
1e0b8120
EC		 818 size_t outlen;
819 int rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FREE_VIS, NULL, 0,
820 outbuf, sizeof(outbuf), &outlen);
8127d661
BH		 821
822 /* -EALREADY means nothing to free, so ignore */
823 if (rc == -EALREADY)
824 rc = 0;
1e0b8120
EC		 825 if (rc)
826 efx_mcdi_display_error(efx, MC_CMD_FREE_VIS, 0, outbuf, outlen,
827 rc);
8127d661
BH		 828 return rc;
829}
830
183233be
BH		 831#ifdef EFX_USE_PIO
832
833static void efx_ef10_free_piobufs(struct efx_nic *efx)
834{
835 struct efx_ef10_nic_data *nic_data = efx->nic_data;
836 MCDI_DECLARE_BUF(inbuf, MC_CMD_FREE_PIOBUF_IN_LEN);
837 unsigned int i;
838 int rc;
839
840 BUILD_BUG_ON(MC_CMD_FREE_PIOBUF_OUT_LEN != 0);
841
842 for (i = 0; i < nic_data->n_piobufs; i++) {
843 MCDI_SET_DWORD(inbuf, FREE_PIOBUF_IN_PIOBUF_HANDLE,
844 nic_data->piobuf_handle[i]);
845 rc = efx_mcdi_rpc(efx, MC_CMD_FREE_PIOBUF, inbuf, sizeof(inbuf),
846 NULL, 0, NULL);
847 WARN_ON(rc);
848 }
849
850 nic_data->n_piobufs = 0;
851}
852
853static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
854{
855 struct efx_ef10_nic_data *nic_data = efx->nic_data;
856 MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_PIOBUF_OUT_LEN);
857 unsigned int i;
858 size_t outlen;
859 int rc = 0;
860
861 BUILD_BUG_ON(MC_CMD_ALLOC_PIOBUF_IN_LEN != 0);
862
863 for (i = 0; i < n; i++) {
09a04204
BK		 864 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_ALLOC_PIOBUF, NULL, 0,
865 outbuf, sizeof(outbuf), &outlen);
866 if (rc) {
867 /* Don't display the MC error if we didn't have space
868 * for a VF.
869 */
870 if (!(efx_ef10_is_vf(efx) && rc == -ENOSPC))
871 efx_mcdi_display_error(efx, MC_CMD_ALLOC_PIOBUF,
872 0, outbuf, outlen, rc);
183233be 873 break;
09a04204 874 }
183233be
BH		 875 if (outlen < MC_CMD_ALLOC_PIOBUF_OUT_LEN) {
876 rc = -EIO;
877 break;
878 }
879 nic_data->piobuf_handle[i] =
880 MCDI_DWORD(outbuf, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE);
881 netif_dbg(efx, probe, efx->net_dev,
882 "allocated PIO buffer %u handle %x\n", i,
883 nic_data->piobuf_handle[i]);
884 }
885
886 nic_data->n_piobufs = i;
887 if (rc)
888 efx_ef10_free_piobufs(efx);
889 return rc;
890}
891
892static int efx_ef10_link_piobufs(struct efx_nic *efx)
893{
894 struct efx_ef10_nic_data *nic_data = efx->nic_data;
d0346b03 895 MCDI_DECLARE_BUF(inbuf, MC_CMD_LINK_PIOBUF_IN_LEN);
183233be
BH		 896 struct efx_channel *channel;
897 struct efx_tx_queue *tx_queue;
898 unsigned int offset, index;
899 int rc;
900
901 BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_OUT_LEN != 0);
902 BUILD_BUG_ON(MC_CMD_UNLINK_PIOBUF_OUT_LEN != 0);
903
904 /* Link a buffer to each VI in the write-combining mapping */
905 for (index = 0; index < nic_data->n_piobufs; ++index) {
906 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_PIOBUF_HANDLE,
907 nic_data->piobuf_handle[index]);
908 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_TXQ_INSTANCE,
909 nic_data->pio_write_vi_base + index);
910 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
911 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
912 NULL, 0, NULL);
913 if (rc) {
914 netif_err(efx, drv, efx->net_dev,
915 "failed to link VI %u to PIO buffer %u (%d)\n",
916 nic_data->pio_write_vi_base + index, index,
917 rc);
918 goto fail;
919 }
920 netif_dbg(efx, probe, efx->net_dev,
921 "linked VI %u to PIO buffer %u\n",
922 nic_data->pio_write_vi_base + index, index);
923 }
924
925 /* Link a buffer to each TX queue */
926 efx_for_each_channel(channel, efx) {
927 efx_for_each_channel_tx_queue(tx_queue, channel) {
928 /* We assign the PIO buffers to queues in
929 * reverse order to allow for the following
930 * special case.
931 */
932 offset = ((efx->tx_channel_offset + efx->n_tx_channels -
933 tx_queue->channel->channel - 1) *
934 efx_piobuf_size);
c634700f
EC		 935 index = offset / nic_data->piobuf_size;
936 offset = offset % nic_data->piobuf_size;
183233be
BH		 937
938 /* When the host page size is 4K, the first
939 * host page in the WC mapping may be within
940 * the same VI page as the last TX queue. We
941 * can only link one buffer to each VI.
942 */
943 if (tx_queue->queue == nic_data->pio_write_vi_base) {
944 BUG_ON(index != 0);
945 rc = 0;
946 } else {
947 MCDI_SET_DWORD(inbuf,
948 LINK_PIOBUF_IN_PIOBUF_HANDLE,
949 nic_data->piobuf_handle[index]);
950 MCDI_SET_DWORD(inbuf,
951 LINK_PIOBUF_IN_TXQ_INSTANCE,
952 tx_queue->queue);
953 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
954 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
955 NULL, 0, NULL);
956 }
957
958 if (rc) {
959 /* This is non-fatal; the TX path just
960 * won't use PIO for this queue
961 */
962 netif_err(efx, drv, efx->net_dev,
963 "failed to link VI %u to PIO buffer %u (%d)\n",
964 tx_queue->queue, index, rc);
965 tx_queue->piobuf = NULL;
966 } else {
967 tx_queue->piobuf =
968 nic_data->pio_write_base +
71827443 969 index * efx->vi_stride + offset;
183233be
BH		 970 tx_queue->piobuf_offset = offset;
971 netif_dbg(efx, probe, efx->net_dev,
972 "linked VI %u to PIO buffer %u offset %x addr %p\n",
973 tx_queue->queue, index,
974 tx_queue->piobuf_offset,
975 tx_queue->piobuf);
976 }
977 }
978 }
979
980 return 0;
981
982fail:
d0346b03
EC		 983 /* inbuf was defined for MC_CMD_LINK_PIOBUF. We can use the same
984 * buffer for MC_CMD_UNLINK_PIOBUF because it's shorter.
985 */
986 BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_IN_LEN < MC_CMD_UNLINK_PIOBUF_IN_LEN);
183233be
BH		 987 while (index--) {
988 MCDI_SET_DWORD(inbuf, UNLINK_PIOBUF_IN_TXQ_INSTANCE,
989 nic_data->pio_write_vi_base + index);
990 efx_mcdi_rpc(efx, MC_CMD_UNLINK_PIOBUF,
991 inbuf, MC_CMD_UNLINK_PIOBUF_IN_LEN,
992 NULL, 0, NULL);
993 }
994 return rc;
995}
996
c0795bf6
EC		 997static void efx_ef10_forget_old_piobufs(struct efx_nic *efx)
998{
999 struct efx_channel *channel;
1000 struct efx_tx_queue *tx_queue;
1001
1002 /* All our existing PIO buffers went away */
1003 efx_for_each_channel(channel, efx)
1004 efx_for_each_channel_tx_queue(tx_queue, channel)
1005 tx_queue->piobuf = NULL;
1006}
1007
183233be
BH		 1008#else /* !EFX_USE_PIO */
1009
1010static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
1011{
1012 return n == 0 ? 0 : -ENOBUFS;
1013}
1014
1015static int efx_ef10_link_piobufs(struct efx_nic *efx)
1016{
1017 return 0;
1018}
1019
1020static void efx_ef10_free_piobufs(struct efx_nic *efx)
1021{
1022}
1023
c0795bf6
EC		 1024static void efx_ef10_forget_old_piobufs(struct efx_nic *efx)
1025{
1026}
1027
183233be
BH		 1028#endif /* EFX_USE_PIO */
1029
8127d661
BH		 1030static void efx_ef10_remove(struct efx_nic *efx)
1031{
1032 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1033 int rc;
1034
f1122a34
SS		 1035#ifdef CONFIG_SFC_SRIOV
1036 struct efx_ef10_nic_data *nic_data_pf;
1037 struct pci_dev *pci_dev_pf;
1038 struct efx_nic *efx_pf;
1039 struct ef10_vf *vf;
1040
1041 if (efx->pci_dev->is_virtfn) {
1042 pci_dev_pf = efx->pci_dev->physfn;
1043 if (pci_dev_pf) {
1044 efx_pf = pci_get_drvdata(pci_dev_pf);
1045 nic_data_pf = efx_pf->nic_data;
1046 vf = nic_data_pf->vf + nic_data->vf_index;
1047 vf->efx = NULL;
1048 } else
1049 netif_info(efx, drv, efx->net_dev,
1050 "Could not get the PF id from VF\n");
1051 }
1052#endif
1053
34813fe2
AR		 1054 efx_ef10_cleanup_vlans(efx);
1055 mutex_destroy(&nic_data->vlan_lock);
1056
9aecda95
BH		 1057 efx_ptp_remove(efx);
1058
8127d661
BH		 1059 efx_mcdi_mon_remove(efx);
1060
8127d661
BH		 1061 efx_ef10_rx_free_indir_table(efx);
1062
183233be
BH		 1063 if (nic_data->wc_membase)
1064 iounmap(nic_data->wc_membase);
1065
8127d661
BH		 1066 rc = efx_ef10_free_vis(efx);
1067 WARN_ON(rc != 0);
1068
183233be
BH		 1069 if (!nic_data->must_restore_piobufs)
1070 efx_ef10_free_piobufs(efx);
1071
0f5c0845
SS		 1072 device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
1073 device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag);
1074
e5fbd977
JC		 1075 efx_mcdi_detach(efx);
1076
1077 memset(nic_data->udp_tunnels, 0, sizeof(nic_data->udp_tunnels));
1078 mutex_lock(&nic_data->udp_tunnels_lock);
1079 (void)efx_ef10_set_udp_tnl_ports(efx, true);
1080 mutex_unlock(&nic_data->udp_tunnels_lock);
1081
1082 mutex_destroy(&nic_data->udp_tunnels_lock);
1083
8127d661
BH		 1084 efx_mcdi_fini(efx);
1085 efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
1086 kfree(nic_data);
1087}
1088
88a37de6
SS		 1089static int efx_ef10_probe_pf(struct efx_nic *efx)
1090{
1091 return efx_ef10_probe(efx);
1092}
1093
38d27f38
AR		 1094int efx_ef10_vadaptor_query(struct efx_nic *efx, unsigned int port_id,
1095 u32 *port_flags, u32 *vadaptor_flags,
1096 unsigned int *vlan_tags)
1097{
1098 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1099 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_QUERY_IN_LEN);
1100 MCDI_DECLARE_BUF(outbuf, MC_CMD_VADAPTOR_QUERY_OUT_LEN);
1101 size_t outlen;
1102 int rc;
1103
1104 if (nic_data->datapath_caps &
1105 (1 << MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_LBN)) {
1106 MCDI_SET_DWORD(inbuf, VADAPTOR_QUERY_IN_UPSTREAM_PORT_ID,
1107 port_id);
1108
1109 rc = efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_QUERY, inbuf, sizeof(inbuf),
1110 outbuf, sizeof(outbuf), &outlen);
1111 if (rc)
1112 return rc;
1113
1114 if (outlen < sizeof(outbuf)) {
1115 rc = -EIO;
1116 return rc;
1117 }
1118 }
1119
1120 if (port_flags)
1121 *port_flags = MCDI_DWORD(outbuf, VADAPTOR_QUERY_OUT_PORT_FLAGS);
1122 if (vadaptor_flags)
1123 *vadaptor_flags =
1124 MCDI_DWORD(outbuf, VADAPTOR_QUERY_OUT_VADAPTOR_FLAGS);
1125 if (vlan_tags)
1126 *vlan_tags =
1127 MCDI_DWORD(outbuf,
1128 VADAPTOR_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS);
1129
1130 return 0;
1131}
1132
7a186f47
DP		 1133int efx_ef10_vadaptor_alloc(struct efx_nic *efx, unsigned int port_id)
1134{
1135 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_ALLOC_IN_LEN);
1136
1137 MCDI_SET_DWORD(inbuf, VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID, port_id);
1138 return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_ALLOC, inbuf, sizeof(inbuf),
1139 NULL, 0, NULL);
1140}
1141
1142int efx_ef10_vadaptor_free(struct efx_nic *efx, unsigned int port_id)
1143{
1144 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_FREE_IN_LEN);
1145
1146 MCDI_SET_DWORD(inbuf, VADAPTOR_FREE_IN_UPSTREAM_PORT_ID, port_id);
1147 return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_FREE, inbuf, sizeof(inbuf),
1148 NULL, 0, NULL);
1149}
1150
1151int efx_ef10_vport_add_mac(struct efx_nic *efx,
1152 unsigned int port_id, u8 *mac)
1153{
1154 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_LEN);
1155
1156 MCDI_SET_DWORD(inbuf, VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID, port_id);
1157 ether_addr_copy(MCDI_PTR(inbuf, VPORT_ADD_MAC_ADDRESS_IN_MACADDR), mac);
1158
1159 return efx_mcdi_rpc(efx, MC_CMD_VPORT_ADD_MAC_ADDRESS, inbuf,
1160 sizeof(inbuf), NULL, 0, NULL);
1161}
1162
1163int efx_ef10_vport_del_mac(struct efx_nic *efx,
1164 unsigned int port_id, u8 *mac)
1165{
1166 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_LEN);
1167
1168 MCDI_SET_DWORD(inbuf, VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID, port_id);
1169 ether_addr_copy(MCDI_PTR(inbuf, VPORT_DEL_MAC_ADDRESS_IN_MACADDR), mac);
1170
1171 return efx_mcdi_rpc(efx, MC_CMD_VPORT_DEL_MAC_ADDRESS, inbuf,
1172 sizeof(inbuf), NULL, 0, NULL);
1173}
1174
88a37de6
SS		 1175#ifdef CONFIG_SFC_SRIOV
1176static int efx_ef10_probe_vf(struct efx_nic *efx)
1177{
1178 int rc;
6598dad2
DP		 1179 struct pci_dev *pci_dev_pf;
1180
1181 /* If the parent PF has no VF data structure, it doesn't know about this
1182 * VF so fail probe. The VF needs to be re-created. This can happen
1183 * if the PF driver is unloaded while the VF is assigned to a guest.
1184 */
1185 pci_dev_pf = efx->pci_dev->physfn;
1186 if (pci_dev_pf) {
1187 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
1188 struct efx_ef10_nic_data *nic_data_pf = efx_pf->nic_data;
1189
1190 if (!nic_data_pf->vf) {
1191 netif_info(efx, drv, efx->net_dev,
1192 "The VF cannot link to its parent PF; "
1193 "please destroy and re-create the VF\n");
1194 return -EBUSY;
1195 }
1196 }
88a37de6
SS		 1197
1198 rc = efx_ef10_probe(efx);
1199 if (rc)
1200 return rc;
1201
1202 rc = efx_ef10_get_vf_index(efx);
1203 if (rc)
1204 goto fail;
1205
f1122a34
SS		 1206 if (efx->pci_dev->is_virtfn) {
1207 if (efx->pci_dev->physfn) {
1208 struct efx_nic *efx_pf =
1209 pci_get_drvdata(efx->pci_dev->physfn);
1210 struct efx_ef10_nic_data *nic_data_p = efx_pf->nic_data;
1211 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1212
1213 nic_data_p->vf[nic_data->vf_index].efx = efx;
6598dad2
DP		 1214 nic_data_p->vf[nic_data->vf_index].pci_dev =
1215 efx->pci_dev;
f1122a34
SS		 1216 } else
1217 netif_info(efx, drv, efx->net_dev,
1218 "Could not get the PF id from VF\n");
1219 }
1220
88a37de6
SS		 1221 return 0;
1222
1223fail:
1224 efx_ef10_remove(efx);
1225 return rc;
1226}
1227#else
1228static int efx_ef10_probe_vf(struct efx_nic *efx __attribute__ ((unused)))
1229{
1230 return 0;
1231}
1232#endif
1233
8127d661
BH		 1234static int efx_ef10_alloc_vis(struct efx_nic *efx,
1235 unsigned int min_vis, unsigned int max_vis)
1236{
1237 MCDI_DECLARE_BUF(inbuf, MC_CMD_ALLOC_VIS_IN_LEN);
1238 MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_VIS_OUT_LEN);
1239 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1240 size_t outlen;
1241 int rc;
1242
1243 MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MIN_VI_COUNT, min_vis);
1244 MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MAX_VI_COUNT, max_vis);
1245 rc = efx_mcdi_rpc(efx, MC_CMD_ALLOC_VIS, inbuf, sizeof(inbuf),
1246 outbuf, sizeof(outbuf), &outlen);
1247 if (rc != 0)
1248 return rc;
1249
1250 if (outlen < MC_CMD_ALLOC_VIS_OUT_LEN)
1251 return -EIO;
1252
1253 netif_dbg(efx, drv, efx->net_dev, "base VI is A0x%03x\n",
1254 MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE));
1255
1256 nic_data->vi_base = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE);
1257 nic_data->n_allocated_vis = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_COUNT);
1258 return 0;
1259}
1260
183233be
BH		 1261/* Note that the failure path of this function does not free
1262 * resources, as this will be done by efx_ef10_remove().
1263 */
8127d661
BH		 1264static int efx_ef10_dimension_resources(struct efx_nic *efx)
1265{
183233be
BH		 1266 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1267 unsigned int uc_mem_map_size, wc_mem_map_size;
b0fbdae1
SS		 1268 unsigned int min_vis = max(EFX_TXQ_TYPES,
1269 efx_separate_tx_channels ? 2 : 1);
1270 unsigned int channel_vis, pio_write_vi_base, max_vis;
183233be
BH		 1271 void __iomem *membase;
1272 int rc;
1273
b0fbdae1 1274 channel_vis = max(efx->n_channels, efx->n_tx_channels * EFX_TXQ_TYPES);
8127d661 1275
183233be
BH		 1276#ifdef EFX_USE_PIO
1277 /* Try to allocate PIO buffers if wanted and if the full
1278 * number of PIO buffers would be sufficient to allocate one
1279 * copy-buffer per TX channel. Failure is non-fatal, as there
1280 * are only a small number of PIO buffers shared between all
1281 * functions of the controller.
1282 */
1283 if (efx_piobuf_size != 0 &&
c634700f 1284 nic_data->piobuf_size / efx_piobuf_size * EF10_TX_PIOBUF_COUNT >=
183233be
BH		 1285 efx->n_tx_channels) {
1286 unsigned int n_piobufs =
1287 DIV_ROUND_UP(efx->n_tx_channels,
c634700f 1288 nic_data->piobuf_size / efx_piobuf_size);
183233be
BH		 1289
1290 rc = efx_ef10_alloc_piobufs(efx, n_piobufs);
6eacfb54
TP		 1291 if (rc == -ENOSPC)
1292 netif_dbg(efx, probe, efx->net_dev,
1293 "out of PIO buffers; cannot allocate more\n");
1294 else if (rc == -EPERM)
1295 netif_dbg(efx, probe, efx->net_dev,
1296 "not permitted to allocate PIO buffers\n");
1297 else if (rc)
183233be
BH		 1298 netif_err(efx, probe, efx->net_dev,
1299 "failed to allocate PIO buffers (%d)\n", rc);
1300 else
1301 netif_dbg(efx, probe, efx->net_dev,
1302 "allocated %u PIO buffers\n", n_piobufs);
1303 }
1304#else
1305 nic_data->n_piobufs = 0;
1306#endif
1307
1308 /* PIO buffers should be mapped with write-combining enabled,
1309 * and we want to make single UC and WC mappings rather than
1310 * several of each (in fact that's the only option if host
1311 * page size is >4K). So we may allocate some extra VIs just
1312 * for writing PIO buffers through.
52ad762b 1313 *
b0fbdae1 1314 * The UC mapping contains (channel_vis - 1) complete VIs and the
71827443
EC		 1315 * first 4K of the next VI. Then the WC mapping begins with
1316 * the remainder of this last VI.
183233be 1317 */
71827443 1318 uc_mem_map_size = PAGE_ALIGN((channel_vis - 1) * efx->vi_stride +
183233be
BH		 1319 ER_DZ_TX_PIOBUF);
1320 if (nic_data->n_piobufs) {
52ad762b
DP		 1321 /* pio_write_vi_base rounds down to give the number of complete
1322 * VIs inside the UC mapping.
1323 */
71827443 1324 pio_write_vi_base = uc_mem_map_size / efx->vi_stride;
183233be
BH		 1325 wc_mem_map_size = (PAGE_ALIGN((pio_write_vi_base +
1326 nic_data->n_piobufs) *
71827443 1327 efx->vi_stride) -
183233be
BH		 1328 uc_mem_map_size);
1329 max_vis = pio_write_vi_base + nic_data->n_piobufs;
1330 } else {
1331 pio_write_vi_base = 0;
1332 wc_mem_map_size = 0;
b0fbdae1 1333 max_vis = channel_vis;
183233be
BH		 1334 }
1335
1336 /* In case the last attached driver failed to free VIs, do it now */
1337 rc = efx_ef10_free_vis(efx);
1338 if (rc != 0)
1339 return rc;
1340
1341 rc = efx_ef10_alloc_vis(efx, min_vis, max_vis);
1342 if (rc != 0)
1343 return rc;
1344
b0fbdae1
SS		 1345 if (nic_data->n_allocated_vis < channel_vis) {
1346 netif_info(efx, drv, efx->net_dev,
1347 "Could not allocate enough VIs to satisfy RSS"
1348 " requirements. Performance may not be optimal.\n");
1349 /* We didn't get the VIs to populate our channels.
1350 * We could keep what we got but then we'd have more
1351 * interrupts than we need.
1352 * Instead calculate new max_channels and restart
1353 */
1354 efx->max_channels = nic_data->n_allocated_vis;
1355 efx->max_tx_channels =
1356 nic_data->n_allocated_vis / EFX_TXQ_TYPES;
1357
1358 efx_ef10_free_vis(efx);
1359 return -EAGAIN;
1360 }
1361
183233be
BH		 1362 /* If we didn't get enough VIs to map all the PIO buffers, free the
1363 * PIO buffers
1364 */
1365 if (nic_data->n_piobufs &&
1366 nic_data->n_allocated_vis <
1367 pio_write_vi_base + nic_data->n_piobufs) {
1368 netif_dbg(efx, probe, efx->net_dev,
1369 "%u VIs are not sufficient to map %u PIO buffers\n",
1370 nic_data->n_allocated_vis, nic_data->n_piobufs);
1371 efx_ef10_free_piobufs(efx);
1372 }
1373
1374 /* Shrink the original UC mapping of the memory BAR */
1375 membase = ioremap_nocache(efx->membase_phys, uc_mem_map_size);
1376 if (!membase) {
1377 netif_err(efx, probe, efx->net_dev,
1378 "could not shrink memory BAR to %x\n",
1379 uc_mem_map_size);
1380 return -ENOMEM;
1381 }
1382 iounmap(efx->membase);
1383 efx->membase = membase;
1384
1385 /* Set up the WC mapping if needed */
1386 if (wc_mem_map_size) {
1387 nic_data->wc_membase = ioremap_wc(efx->membase_phys +
1388 uc_mem_map_size,
1389 wc_mem_map_size);
1390 if (!nic_data->wc_membase) {
1391 netif_err(efx, probe, efx->net_dev,
1392 "could not allocate WC mapping of size %x\n",
1393 wc_mem_map_size);
1394 return -ENOMEM;
1395 }
1396 nic_data->pio_write_vi_base = pio_write_vi_base;
1397 nic_data->pio_write_base =
1398 nic_data->wc_membase +
71827443 1399 (pio_write_vi_base * efx->vi_stride + ER_DZ_TX_PIOBUF -
183233be
BH		 1400 uc_mem_map_size);
1401
1402 rc = efx_ef10_link_piobufs(efx);
1403 if (rc)
1404 efx_ef10_free_piobufs(efx);
1405 }
1406
1407 netif_dbg(efx, probe, efx->net_dev,
1408 "memory BAR at %pa (virtual %p+%x UC, %p+%x WC)\n",
1409 &efx->membase_phys, efx->membase, uc_mem_map_size,
1410 nic_data->wc_membase, wc_mem_map_size);
1411
1412 return 0;
8127d661
BH		 1413}
1414
1415static int efx_ef10_init_nic(struct efx_nic *efx)
1416{
1417 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1418 int rc;
1419
a915ccc9
BH		 1420 if (nic_data->must_check_datapath_caps) {
1421 rc = efx_ef10_init_datapath_caps(efx);
1422 if (rc)
1423 return rc;
1424 nic_data->must_check_datapath_caps = false;
1425 }
1426
8127d661
BH		 1427 if (nic_data->must_realloc_vis) {
1428 /* We cannot let the number of VIs change now */
1429 rc = efx_ef10_alloc_vis(efx, nic_data->n_allocated_vis,
1430 nic_data->n_allocated_vis);
1431 if (rc)
1432 return rc;
1433 nic_data->must_realloc_vis = false;
1434 }
1435
183233be
BH		 1436 if (nic_data->must_restore_piobufs && nic_data->n_piobufs) {
1437 rc = efx_ef10_alloc_piobufs(efx, nic_data->n_piobufs);
1438 if (rc == 0) {
1439 rc = efx_ef10_link_piobufs(efx);
1440 if (rc)
1441 efx_ef10_free_piobufs(efx);
1442 }
1443
6eacfb54
TP		 1444 /* Log an error on failure, but this is non-fatal.
1445 * Permission errors are less important - we've presumably
1446 * had the PIO buffer licence removed.
1447 */
1448 if (rc == -EPERM)
1449 netif_dbg(efx, drv, efx->net_dev,
1450 "not permitted to restore PIO buffers\n");
1451 else if (rc)
183233be
BH		 1452 netif_err(efx, drv, efx->net_dev,
1453 "failed to restore PIO buffers (%d)\n", rc);
1454 nic_data->must_restore_piobufs = false;
1455 }
1456
267c0157 1457 /* don't fail init if RSS setup doesn't work */
f74d1995 1458 rc = efx->type->rx_push_rss_config(efx, false, efx->rx_indir_table, NULL);
4fdda958 1459 efx->rss_active = (rc == 0);
267c0157 1460
8127d661
BH		 1461 return 0;
1462}
1463
3e336261
JC		 1464static void efx_ef10_reset_mc_allocations(struct efx_nic *efx)
1465{
1466 struct efx_ef10_nic_data *nic_data = efx->nic_data;
774ad031
DP		 1467#ifdef CONFIG_SFC_SRIOV
1468 unsigned int i;
1469#endif
3e336261
JC		 1470
1471 /* All our allocations have been reset */
1472 nic_data->must_realloc_vis = true;
1473 nic_data->must_restore_filters = true;
1474 nic_data->must_restore_piobufs = true;
c0795bf6 1475 efx_ef10_forget_old_piobufs(efx);
3e336261 1476 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
774ad031
DP		 1477
1478 /* Driver-created vswitches and vports must be re-created */
1479 nic_data->must_probe_vswitching = true;
1480 nic_data->vport_id = EVB_PORT_ID_ASSIGNED;
1481#ifdef CONFIG_SFC_SRIOV
1482 if (nic_data->vf)
1483 for (i = 0; i < efx->vf_count; i++)
1484 nic_data->vf[i].vport_id = 0;
1485#endif
3e336261
JC		 1486}
1487
087e9025
JC		 1488static enum reset_type efx_ef10_map_reset_reason(enum reset_type reason)
1489{
1490 if (reason == RESET_TYPE_MC_FAILURE)
1491 return RESET_TYPE_DATAPATH;
1492
1493 return efx_mcdi_map_reset_reason(reason);
1494}
1495
8127d661
BH		 1496static int efx_ef10_map_reset_flags(u32 *flags)
1497{
1498 enum {
1499 EF10_RESET_PORT = ((ETH_RESET_MAC | ETH_RESET_PHY) <<
1500 ETH_RESET_SHARED_SHIFT),
1501 EF10_RESET_MC = ((ETH_RESET_DMA | ETH_RESET_FILTER |
1502 ETH_RESET_OFFLOAD | ETH_RESET_MAC |
1503 ETH_RESET_PHY | ETH_RESET_MGMT) <<
1504 ETH_RESET_SHARED_SHIFT)
1505 };
1506
1507 /* We assume for now that our PCI function is permitted to
1508 * reset everything.
1509 */
1510
1511 if ((*flags & EF10_RESET_MC) == EF10_RESET_MC) {
1512 *flags &= ~EF10_RESET_MC;
1513 return RESET_TYPE_WORLD;
1514 }
1515
1516 if ((*flags & EF10_RESET_PORT) == EF10_RESET_PORT) {
1517 *flags &= ~EF10_RESET_PORT;
1518 return RESET_TYPE_ALL;
1519 }
1520
1521 /* no invisible reset implemented */
1522
1523 return -EINVAL;
1524}
1525
3e336261
JC		 1526static int efx_ef10_reset(struct efx_nic *efx, enum reset_type reset_type)
1527{
1528 int rc = efx_mcdi_reset(efx, reset_type);
1529
27324820
DP		 1530 /* Unprivileged functions return -EPERM, but need to return success
1531 * here so that the datapath is brought back up.
1532 */
1533 if (reset_type == RESET_TYPE_WORLD && rc == -EPERM)
1534 rc = 0;
1535
3e336261
JC		 1536 /* If it was a port reset, trigger reallocation of MC resources.
1537 * Note that on an MC reset nothing needs to be done now because we'll
1538 * detect the MC reset later and handle it then.
e283546c
EC		 1539 * For an FLR, we never get an MC reset event, but the MC has reset all
1540 * resources assigned to us, so we have to trigger reallocation now.
3e336261 1541 */
e283546c
EC		 1542 if ((reset_type == RESET_TYPE_ALL ||
1543 reset_type == RESET_TYPE_MCDI_TIMEOUT) && !rc)
3e336261
JC		 1544 efx_ef10_reset_mc_allocations(efx);
1545 return rc;
1546}
1547
8127d661
BH		 1548#define EF10_DMA_STAT(ext_name, mcdi_name) \
1549 [EF10_STAT_ ## ext_name] = \
1550 { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
1551#define EF10_DMA_INVIS_STAT(int_name, mcdi_name) \
1552 [EF10_STAT_ ## int_name] = \
1553 { NULL, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
1554#define EF10_OTHER_STAT(ext_name) \
1555 [EF10_STAT_ ## ext_name] = { #ext_name, 0, 0 }
e4d112e4
EC		 1556#define GENERIC_SW_STAT(ext_name) \
1557 [GENERIC_STAT_ ## ext_name] = { #ext_name, 0, 0 }
8127d661
BH		 1558
1559static const struct efx_hw_stat_desc efx_ef10_stat_desc[EF10_STAT_COUNT] = {
e80ca013
DP		 1560 EF10_DMA_STAT(port_tx_bytes, TX_BYTES),
1561 EF10_DMA_STAT(port_tx_packets, TX_PKTS),
1562 EF10_DMA_STAT(port_tx_pause, TX_PAUSE_PKTS),
1563 EF10_DMA_STAT(port_tx_control, TX_CONTROL_PKTS),
1564 EF10_DMA_STAT(port_tx_unicast, TX_UNICAST_PKTS),
1565 EF10_DMA_STAT(port_tx_multicast, TX_MULTICAST_PKTS),
1566 EF10_DMA_STAT(port_tx_broadcast, TX_BROADCAST_PKTS),
1567 EF10_DMA_STAT(port_tx_lt64, TX_LT64_PKTS),
1568 EF10_DMA_STAT(port_tx_64, TX_64_PKTS),
1569 EF10_DMA_STAT(port_tx_65_to_127, TX_65_TO_127_PKTS),
1570 EF10_DMA_STAT(port_tx_128_to_255, TX_128_TO_255_PKTS),
1571 EF10_DMA_STAT(port_tx_256_to_511, TX_256_TO_511_PKTS),
1572 EF10_DMA_STAT(port_tx_512_to_1023, TX_512_TO_1023_PKTS),
1573 EF10_DMA_STAT(port_tx_1024_to_15xx, TX_1024_TO_15XX_PKTS),
1574 EF10_DMA_STAT(port_tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS),
1575 EF10_DMA_STAT(port_rx_bytes, RX_BYTES),
1576 EF10_DMA_INVIS_STAT(port_rx_bytes_minus_good_bytes, RX_BAD_BYTES),
1577 EF10_OTHER_STAT(port_rx_good_bytes),
1578 EF10_OTHER_STAT(port_rx_bad_bytes),
1579 EF10_DMA_STAT(port_rx_packets, RX_PKTS),
1580 EF10_DMA_STAT(port_rx_good, RX_GOOD_PKTS),
1581 EF10_DMA_STAT(port_rx_bad, RX_BAD_FCS_PKTS),
1582 EF10_DMA_STAT(port_rx_pause, RX_PAUSE_PKTS),
1583 EF10_DMA_STAT(port_rx_control, RX_CONTROL_PKTS),
1584 EF10_DMA_STAT(port_rx_unicast, RX_UNICAST_PKTS),
1585 EF10_DMA_STAT(port_rx_multicast, RX_MULTICAST_PKTS),
1586 EF10_DMA_STAT(port_rx_broadcast, RX_BROADCAST_PKTS),
1587 EF10_DMA_STAT(port_rx_lt64, RX_UNDERSIZE_PKTS),
1588 EF10_DMA_STAT(port_rx_64, RX_64_PKTS),
1589 EF10_DMA_STAT(port_rx_65_to_127, RX_65_TO_127_PKTS),
1590 EF10_DMA_STAT(port_rx_128_to_255, RX_128_TO_255_PKTS),
1591 EF10_DMA_STAT(port_rx_256_to_511, RX_256_TO_511_PKTS),
1592 EF10_DMA_STAT(port_rx_512_to_1023, RX_512_TO_1023_PKTS),
1593 EF10_DMA_STAT(port_rx_1024_to_15xx, RX_1024_TO_15XX_PKTS),
1594 EF10_DMA_STAT(port_rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS),
1595 EF10_DMA_STAT(port_rx_gtjumbo, RX_GTJUMBO_PKTS),
1596 EF10_DMA_STAT(port_rx_bad_gtjumbo, RX_JABBER_PKTS),
1597 EF10_DMA_STAT(port_rx_overflow, RX_OVERFLOW_PKTS),
1598 EF10_DMA_STAT(port_rx_align_error, RX_ALIGN_ERROR_PKTS),
1599 EF10_DMA_STAT(port_rx_length_error, RX_LENGTH_ERROR_PKTS),
1600 EF10_DMA_STAT(port_rx_nodesc_drops, RX_NODESC_DROPS),
e4d112e4
EC		 1601 GENERIC_SW_STAT(rx_nodesc_trunc),
1602 GENERIC_SW_STAT(rx_noskb_drops),
e80ca013
DP		 1603 EF10_DMA_STAT(port_rx_pm_trunc_bb_overflow, PM_TRUNC_BB_OVERFLOW),
1604 EF10_DMA_STAT(port_rx_pm_discard_bb_overflow, PM_DISCARD_BB_OVERFLOW),
1605 EF10_DMA_STAT(port_rx_pm_trunc_vfifo_full, PM_TRUNC_VFIFO_FULL),
1606 EF10_DMA_STAT(port_rx_pm_discard_vfifo_full, PM_DISCARD_VFIFO_FULL),
1607 EF10_DMA_STAT(port_rx_pm_trunc_qbb, PM_TRUNC_QBB),
1608 EF10_DMA_STAT(port_rx_pm_discard_qbb, PM_DISCARD_QBB),
1609 EF10_DMA_STAT(port_rx_pm_discard_mapping, PM_DISCARD_MAPPING),
1610 EF10_DMA_STAT(port_rx_dp_q_disabled_packets, RXDP_Q_DISABLED_PKTS),
1611 EF10_DMA_STAT(port_rx_dp_di_dropped_packets, RXDP_DI_DROPPED_PKTS),
1612 EF10_DMA_STAT(port_rx_dp_streaming_packets, RXDP_STREAMING_PKTS),
1613 EF10_DMA_STAT(port_rx_dp_hlb_fetch, RXDP_HLB_FETCH_CONDITIONS),
1614 EF10_DMA_STAT(port_rx_dp_hlb_wait, RXDP_HLB_WAIT_CONDITIONS),
3c36a2ad
DP		 1615 EF10_DMA_STAT(rx_unicast, VADAPTER_RX_UNICAST_PACKETS),
1616 EF10_DMA_STAT(rx_unicast_bytes, VADAPTER_RX_UNICAST_BYTES),
1617 EF10_DMA_STAT(rx_multicast, VADAPTER_RX_MULTICAST_PACKETS),
1618 EF10_DMA_STAT(rx_multicast_bytes, VADAPTER_RX_MULTICAST_BYTES),
1619 EF10_DMA_STAT(rx_broadcast, VADAPTER_RX_BROADCAST_PACKETS),
1620 EF10_DMA_STAT(rx_broadcast_bytes, VADAPTER_RX_BROADCAST_BYTES),
1621 EF10_DMA_STAT(rx_bad, VADAPTER_RX_BAD_PACKETS),
1622 EF10_DMA_STAT(rx_bad_bytes, VADAPTER_RX_BAD_BYTES),
1623 EF10_DMA_STAT(rx_overflow, VADAPTER_RX_OVERFLOW),
1624 EF10_DMA_STAT(tx_unicast, VADAPTER_TX_UNICAST_PACKETS),
1625 EF10_DMA_STAT(tx_unicast_bytes, VADAPTER_TX_UNICAST_BYTES),
1626 EF10_DMA_STAT(tx_multicast, VADAPTER_TX_MULTICAST_PACKETS),
1627 EF10_DMA_STAT(tx_multicast_bytes, VADAPTER_TX_MULTICAST_BYTES),
1628 EF10_DMA_STAT(tx_broadcast, VADAPTER_TX_BROADCAST_PACKETS),
1629 EF10_DMA_STAT(tx_broadcast_bytes, VADAPTER_TX_BROADCAST_BYTES),
1630 EF10_DMA_STAT(tx_bad, VADAPTER_TX_BAD_PACKETS),
1631 EF10_DMA_STAT(tx_bad_bytes, VADAPTER_TX_BAD_BYTES),
1632 EF10_DMA_STAT(tx_overflow, VADAPTER_TX_OVERFLOW),
8127d661
BH		 1633};
1634
e80ca013
DP		 1635#define HUNT_COMMON_STAT_MASK ((1ULL << EF10_STAT_port_tx_bytes) | \
1636 (1ULL << EF10_STAT_port_tx_packets) | \
1637 (1ULL << EF10_STAT_port_tx_pause) | \
1638 (1ULL << EF10_STAT_port_tx_unicast) | \
1639 (1ULL << EF10_STAT_port_tx_multicast) | \
1640 (1ULL << EF10_STAT_port_tx_broadcast) | \
1641 (1ULL << EF10_STAT_port_rx_bytes) | \
1642 (1ULL << \
1643 EF10_STAT_port_rx_bytes_minus_good_bytes) | \
1644 (1ULL << EF10_STAT_port_rx_good_bytes) | \
1645 (1ULL << EF10_STAT_port_rx_bad_bytes) | \
1646 (1ULL << EF10_STAT_port_rx_packets) | \
1647 (1ULL << EF10_STAT_port_rx_good) | \
1648 (1ULL << EF10_STAT_port_rx_bad) | \
1649 (1ULL << EF10_STAT_port_rx_pause) | \
1650 (1ULL << EF10_STAT_port_rx_control) | \
1651 (1ULL << EF10_STAT_port_rx_unicast) | \
1652 (1ULL << EF10_STAT_port_rx_multicast) | \
1653 (1ULL << EF10_STAT_port_rx_broadcast) | \
1654 (1ULL << EF10_STAT_port_rx_lt64) | \
1655 (1ULL << EF10_STAT_port_rx_64) | \
1656 (1ULL << EF10_STAT_port_rx_65_to_127) | \
1657 (1ULL << EF10_STAT_port_rx_128_to_255) | \
1658 (1ULL << EF10_STAT_port_rx_256_to_511) | \
1659 (1ULL << EF10_STAT_port_rx_512_to_1023) |\
1660 (1ULL << EF10_STAT_port_rx_1024_to_15xx) |\
1661 (1ULL << EF10_STAT_port_rx_15xx_to_jumbo) |\
1662 (1ULL << EF10_STAT_port_rx_gtjumbo) | \
1663 (1ULL << EF10_STAT_port_rx_bad_gtjumbo) |\
1664 (1ULL << EF10_STAT_port_rx_overflow) | \
1665 (1ULL << EF10_STAT_port_rx_nodesc_drops) |\
e4d112e4
EC		 1666 (1ULL << GENERIC_STAT_rx_nodesc_trunc) | \
1667 (1ULL << GENERIC_STAT_rx_noskb_drops))
8127d661 1668
69b365c3
EC		 1669/* On 7000 series NICs, these statistics are only provided by the 10G MAC.
1670 * For a 10G/40G switchable port we do not expose these because they might
1671 * not include all the packets they should.
1672 * On 8000 series NICs these statistics are always provided.
8127d661 1673 */
e80ca013
DP		 1674#define HUNT_10G_ONLY_STAT_MASK ((1ULL << EF10_STAT_port_tx_control) | \
1675 (1ULL << EF10_STAT_port_tx_lt64) | \
1676 (1ULL << EF10_STAT_port_tx_64) | \
1677 (1ULL << EF10_STAT_port_tx_65_to_127) |\
1678 (1ULL << EF10_STAT_port_tx_128_to_255) |\
1679 (1ULL << EF10_STAT_port_tx_256_to_511) |\
1680 (1ULL << EF10_STAT_port_tx_512_to_1023) |\
1681 (1ULL << EF10_STAT_port_tx_1024_to_15xx) |\
1682 (1ULL << EF10_STAT_port_tx_15xx_to_jumbo))
8127d661
BH		 1683
1684/* These statistics are only provided by the 40G MAC. For a 10G/40G
1685 * switchable port we do expose these because the errors will otherwise
1686 * be silent.
1687 */
e80ca013
DP		 1688#define HUNT_40G_EXTRA_STAT_MASK ((1ULL << EF10_STAT_port_rx_align_error) |\
1689 (1ULL << EF10_STAT_port_rx_length_error))
8127d661 1690
568d7a00
EC		 1691/* These statistics are only provided if the firmware supports the
1692 * capability PM_AND_RXDP_COUNTERS.
1693 */
1694#define HUNT_PM_AND_RXDP_STAT_MASK ( \
e80ca013
DP		 1695 (1ULL << EF10_STAT_port_rx_pm_trunc_bb_overflow) | \
1696 (1ULL << EF10_STAT_port_rx_pm_discard_bb_overflow) | \
1697 (1ULL << EF10_STAT_port_rx_pm_trunc_vfifo_full) | \
1698 (1ULL << EF10_STAT_port_rx_pm_discard_vfifo_full) | \
1699 (1ULL << EF10_STAT_port_rx_pm_trunc_qbb) | \
1700 (1ULL << EF10_STAT_port_rx_pm_discard_qbb) | \
1701 (1ULL << EF10_STAT_port_rx_pm_discard_mapping) | \
1702 (1ULL << EF10_STAT_port_rx_dp_q_disabled_packets) | \
1703 (1ULL << EF10_STAT_port_rx_dp_di_dropped_packets) | \
1704 (1ULL << EF10_STAT_port_rx_dp_streaming_packets) | \
1705 (1ULL << EF10_STAT_port_rx_dp_hlb_fetch) | \
1706 (1ULL << EF10_STAT_port_rx_dp_hlb_wait))
568d7a00 1707
4bae913b 1708static u64 efx_ef10_raw_stat_mask(struct efx_nic *efx)
8127d661 1709{
4bae913b 1710 u64 raw_mask = HUNT_COMMON_STAT_MASK;
8127d661 1711 u32 port_caps = efx_mcdi_phy_get_caps(efx);
568d7a00 1712 struct efx_ef10_nic_data *nic_data = efx->nic_data;
8127d661 1713
3c36a2ad
DP		 1714 if (!(efx->mcdi->fn_flags &
1715 1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL))
1716 return 0;
1717
69b365c3 1718 if (port_caps & (1 << MC_CMD_PHY_CAP_40000FDX_LBN)) {
4bae913b 1719 raw_mask |= HUNT_40G_EXTRA_STAT_MASK;
69b365c3
EC		 1720 /* 8000 series have everything even at 40G */
1721 if (nic_data->datapath_caps2 &
1722 (1 << MC_CMD_GET_CAPABILITIES_V2_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN))
1723 raw_mask |= HUNT_10G_ONLY_STAT_MASK;
1724 } else {
4bae913b 1725 raw_mask |= HUNT_10G_ONLY_STAT_MASK;
69b365c3 1726 }
568d7a00
EC		 1727
1728 if (nic_data->datapath_caps &
1729 (1 << MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN))
1730 raw_mask |= HUNT_PM_AND_RXDP_STAT_MASK;
1731
4bae913b
EC		 1732 return raw_mask;
1733}
1734
1735static void efx_ef10_get_stat_mask(struct efx_nic *efx, unsigned long *mask)
1736{
d94619cd 1737 struct efx_ef10_nic_data *nic_data = efx->nic_data;
3c36a2ad
DP		 1738 u64 raw_mask[2];
1739
1740 raw_mask[0] = efx_ef10_raw_stat_mask(efx);
1741
d94619cd
DP		 1742 /* Only show vadaptor stats when EVB capability is present */
1743 if (nic_data->datapath_caps &
1744 (1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN)) {
1745 raw_mask[0] |= ~((1ULL << EF10_STAT_rx_unicast) - 1);
1746 raw_mask[1] = (1ULL << (EF10_STAT_COUNT - 63)) - 1;
1747 } else {
1748 raw_mask[1] = 0;
1749 }
4bae913b
EC		 1750
1751#if BITS_PER_LONG == 64
e70c70c3 1752 BUILD_BUG_ON(BITS_TO_LONGS(EF10_STAT_COUNT) != 2);
3c36a2ad
DP		 1753 mask[0] = raw_mask[0];
1754 mask[1] = raw_mask[1];
4bae913b 1755#else
e70c70c3 1756 BUILD_BUG_ON(BITS_TO_LONGS(EF10_STAT_COUNT) != 3);
3c36a2ad
DP		 1757 mask[0] = raw_mask[0] & 0xffffffff;
1758 mask[1] = raw_mask[0] >> 32;
1759 mask[2] = raw_mask[1] & 0xffffffff;
4bae913b 1760#endif
8127d661
BH		 1761}
1762
1763static size_t efx_ef10_describe_stats(struct efx_nic *efx, u8 *names)
1764{
4bae913b
EC		 1765 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1766
1767 efx_ef10_get_stat_mask(efx, mask);
8127d661 1768 return efx_nic_describe_stats(efx_ef10_stat_desc, EF10_STAT_COUNT,
4bae913b 1769 mask, names);
8127d661
BH		 1770}
1771
d7788196
DP		 1772static size_t efx_ef10_update_stats_common(struct efx_nic *efx, u64 *full_stats,
1773 struct rtnl_link_stats64 *core_stats)
1774{
1775 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1776 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1777 u64 *stats = nic_data->stats;
1778 size_t stats_count = 0, index;
1779
1780 efx_ef10_get_stat_mask(efx, mask);
1781
1782 if (full_stats) {
1783 for_each_set_bit(index, mask, EF10_STAT_COUNT) {
1784 if (efx_ef10_stat_desc[index].name) {
1785 *full_stats++ = stats[index];
1786 ++stats_count;
1787 }
1788 }
1789 }
1790
fbe4307e
BK		 1791 if (!core_stats)
1792 return stats_count;
1793
1794 if (nic_data->datapath_caps &
1795 1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN) {
1796 /* Use vadaptor stats. */
0fc95fca
DP		 1797 core_stats->rx_packets = stats[EF10_STAT_rx_unicast] +
1798 stats[EF10_STAT_rx_multicast] +
1799 stats[EF10_STAT_rx_broadcast];
1800 core_stats->tx_packets = stats[EF10_STAT_tx_unicast] +
1801 stats[EF10_STAT_tx_multicast] +
1802 stats[EF10_STAT_tx_broadcast];
1803 core_stats->rx_bytes = stats[EF10_STAT_rx_unicast_bytes] +
1804 stats[EF10_STAT_rx_multicast_bytes] +
1805 stats[EF10_STAT_rx_broadcast_bytes];
1806 core_stats->tx_bytes = stats[EF10_STAT_tx_unicast_bytes] +
1807 stats[EF10_STAT_tx_multicast_bytes] +
1808 stats[EF10_STAT_tx_broadcast_bytes];
1809 core_stats->rx_dropped = stats[GENERIC_STAT_rx_nodesc_trunc] +
d7788196 1810 stats[GENERIC_STAT_rx_noskb_drops];
0fc95fca
DP		 1811 core_stats->multicast = stats[EF10_STAT_rx_multicast];
1812 core_stats->rx_crc_errors = stats[EF10_STAT_rx_bad];
1813 core_stats->rx_fifo_errors = stats[EF10_STAT_rx_overflow];
1814 core_stats->rx_errors = core_stats->rx_crc_errors;
1815 core_stats->tx_errors = stats[EF10_STAT_tx_bad];
fbe4307e
BK		 1816 } else {
1817 /* Use port stats. */
1818 core_stats->rx_packets = stats[EF10_STAT_port_rx_packets];
1819 core_stats->tx_packets = stats[EF10_STAT_port_tx_packets];
1820 core_stats->rx_bytes = stats[EF10_STAT_port_rx_bytes];
1821 core_stats->tx_bytes = stats[EF10_STAT_port_tx_bytes];
1822 core_stats->rx_dropped = stats[EF10_STAT_port_rx_nodesc_drops] +
1823 stats[GENERIC_STAT_rx_nodesc_trunc] +
1824 stats[GENERIC_STAT_rx_noskb_drops];
1825 core_stats->multicast = stats[EF10_STAT_port_rx_multicast];
1826 core_stats->rx_length_errors =
1827 stats[EF10_STAT_port_rx_gtjumbo] +
1828 stats[EF10_STAT_port_rx_length_error];
1829 core_stats->rx_crc_errors = stats[EF10_STAT_port_rx_bad];
1830 core_stats->rx_frame_errors =
1831 stats[EF10_STAT_port_rx_align_error];
1832 core_stats->rx_fifo_errors = stats[EF10_STAT_port_rx_overflow];
1833 core_stats->rx_errors = (core_stats->rx_length_errors +
1834 core_stats->rx_crc_errors +
1835 core_stats->rx_frame_errors);
d7788196
DP		 1836 }
1837
1838 return stats_count;
1839}
1840
1841static int efx_ef10_try_update_nic_stats_pf(struct efx_nic *efx)
8127d661
BH		 1842{
1843 struct efx_ef10_nic_data *nic_data = efx->nic_data;
4bae913b 1844 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
8127d661
BH		 1845 __le64 generation_start, generation_end;
1846 u64 *stats = nic_data->stats;
1847 __le64 *dma_stats;
1848
4bae913b
EC		 1849 efx_ef10_get_stat_mask(efx, mask);
1850
8127d661 1851 dma_stats = efx->stats_buffer.addr;
8127d661
BH		 1852
1853 generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
1854 if (generation_end == EFX_MC_STATS_GENERATION_INVALID)
1855 return 0;
1856 rmb();
4bae913b 1857 efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask,
8127d661 1858 stats, efx->stats_buffer.addr, false);
d546a893 1859 rmb();
8127d661
BH		 1860 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
1861 if (generation_end != generation_start)
1862 return -EAGAIN;
1863
1864 /* Update derived statistics */
e80ca013
DP		 1865 efx_nic_fix_nodesc_drop_stat(efx,
1866 &stats[EF10_STAT_port_rx_nodesc_drops]);
1867 stats[EF10_STAT_port_rx_good_bytes] =
1868 stats[EF10_STAT_port_rx_bytes] -
1869 stats[EF10_STAT_port_rx_bytes_minus_good_bytes];
1870 efx_update_diff_stat(&stats[EF10_STAT_port_rx_bad_bytes],
1871 stats[EF10_STAT_port_rx_bytes_minus_good_bytes]);
e4d112e4 1872 efx_update_sw_stats(efx, stats);
8127d661
BH		 1873 return 0;
1874}
1875
1876
d7788196
DP		 1877static size_t efx_ef10_update_stats_pf(struct efx_nic *efx, u64 *full_stats,
1878 struct rtnl_link_stats64 *core_stats)
8127d661 1879{
8127d661
BH		 1880 int retry;
1881
1882 /* If we're unlucky enough to read statistics during the DMA, wait
1883 * up to 10ms for it to finish (typically takes <500us)
1884 */
1885 for (retry = 0; retry < 100; ++retry) {
d7788196 1886 if (efx_ef10_try_update_nic_stats_pf(efx) == 0)
8127d661
BH		 1887 break;
1888 udelay(100);
1889 }
1890
d7788196
DP		 1891 return efx_ef10_update_stats_common(efx, full_stats, core_stats);
1892}
8127d661 1893
d7788196
DP		 1894static int efx_ef10_try_update_nic_stats_vf(struct efx_nic *efx)
1895{
1896 MCDI_DECLARE_BUF(inbuf, MC_CMD_MAC_STATS_IN_LEN);
1897 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1898 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1899 __le64 generation_start, generation_end;
1900 u64 *stats = nic_data->stats;
1901 u32 dma_len = MC_CMD_MAC_NSTATS * sizeof(u64);
1902 struct efx_buffer stats_buf;
1903 __le64 *dma_stats;
1904 int rc;
1905
f00bf230
DP		 1906 spin_unlock_bh(&efx->stats_lock);
1907
1908 if (in_interrupt()) {
1909 /* If in atomic context, cannot update stats. Just update the
1910 * software stats and return so the caller can continue.
1911 */
1912 spin_lock_bh(&efx->stats_lock);
1913 efx_update_sw_stats(efx, stats);
1914 return 0;
1915 }
1916
d7788196
DP		 1917 efx_ef10_get_stat_mask(efx, mask);
1918
1919 rc = efx_nic_alloc_buffer(efx, &stats_buf, dma_len, GFP_ATOMIC);
f00bf230
DP		 1920 if (rc) {
1921 spin_lock_bh(&efx->stats_lock);
d7788196 1922 return rc;
f00bf230 1923 }
d7788196
DP		 1924
1925 dma_stats = stats_buf.addr;
1926 dma_stats[MC_CMD_MAC_GENERATION_END] = EFX_MC_STATS_GENERATION_INVALID;
1927
1928 MCDI_SET_QWORD(inbuf, MAC_STATS_IN_DMA_ADDR, stats_buf.dma_addr);
1929 MCDI_POPULATE_DWORD_1(inbuf, MAC_STATS_IN_CMD,
0fc95fca 1930 MAC_STATS_IN_DMA, 1);
d7788196
DP		 1931 MCDI_SET_DWORD(inbuf, MAC_STATS_IN_DMA_LEN, dma_len);
1932 MCDI_SET_DWORD(inbuf, MAC_STATS_IN_PORT_ID, EVB_PORT_ID_ASSIGNED);
1933
6dd4859b
DP		 1934 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_MAC_STATS, inbuf, sizeof(inbuf),
1935 NULL, 0, NULL);
d7788196 1936 spin_lock_bh(&efx->stats_lock);
6dd4859b
DP		 1937 if (rc) {
1938 /* Expect ENOENT if DMA queues have not been set up */
1939 if (rc != -ENOENT || atomic_read(&efx->active_queues))
1940 efx_mcdi_display_error(efx, MC_CMD_MAC_STATS,
1941 sizeof(inbuf), NULL, 0, rc);
d7788196 1942 goto out;
6dd4859b 1943 }
d7788196
DP		 1944
1945 generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
0fc95fca
DP		 1946 if (generation_end == EFX_MC_STATS_GENERATION_INVALID) {
1947 WARN_ON_ONCE(1);
d7788196 1948 goto out;
0fc95fca 1949 }
d7788196
DP		 1950 rmb();
1951 efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask,
1952 stats, stats_buf.addr, false);
1953 rmb();
1954 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
1955 if (generation_end != generation_start) {
1956 rc = -EAGAIN;
1957 goto out;
8127d661
BH		 1958 }
1959
d7788196
DP		 1960 efx_update_sw_stats(efx, stats);
1961out:
1962 efx_nic_free_buffer(efx, &stats_buf);
1963 return rc;
1964}
1965
1966static size_t efx_ef10_update_stats_vf(struct efx_nic *efx, u64 *full_stats,
1967 struct rtnl_link_stats64 *core_stats)
1968{
1969 if (efx_ef10_try_update_nic_stats_vf(efx))
1970 return 0;
1971
1972 return efx_ef10_update_stats_common(efx, full_stats, core_stats);
8127d661
BH		 1973}
1974
1975static void efx_ef10_push_irq_moderation(struct efx_channel *channel)
1976{
1977 struct efx_nic *efx = channel->efx;
539de7c5 1978 unsigned int mode, usecs;
8127d661
BH		 1979 efx_dword_t timer_cmd;
1980
539de7c5 1981 if (channel->irq_moderation_us) {
8127d661 1982 mode = 3;
539de7c5 1983 usecs = channel->irq_moderation_us;
8127d661
BH		 1984 } else {
1985 mode = 0;
539de7c5 1986 usecs = 0;
8127d661
BH		 1987 }
1988
539de7c5
BK		 1989 if (EFX_EF10_WORKAROUND_61265(efx)) {
1990 MCDI_DECLARE_BUF(inbuf, MC_CMD_SET_EVQ_TMR_IN_LEN);
1991 unsigned int ns = usecs * 1000;
1992
1993 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_INSTANCE,
1994 channel->channel);
1995 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_LOAD_REQ_NS, ns);
1996 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_RELOAD_REQ_NS, ns);
1997 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_MODE, mode);
1998
1999 efx_mcdi_rpc_async(efx, MC_CMD_SET_EVQ_TMR,
2000 inbuf, sizeof(inbuf), 0, NULL, 0);
2001 } else if (EFX_EF10_WORKAROUND_35388(efx)) {
2002 unsigned int ticks = efx_usecs_to_ticks(efx, usecs);
2003
8127d661
BH		 2004 EFX_POPULATE_DWORD_3(timer_cmd, ERF_DD_EVQ_IND_TIMER_FLAGS,
2005 EFE_DD_EVQ_IND_TIMER_FLAGS,
2006 ERF_DD_EVQ_IND_TIMER_MODE, mode,
539de7c5 2007 ERF_DD_EVQ_IND_TIMER_VAL, ticks);
8127d661
BH		 2008 efx_writed_page(efx, &timer_cmd, ER_DD_EVQ_INDIRECT,
2009 channel->channel);
2010 } else {
539de7c5
BK		 2011 unsigned int ticks = efx_usecs_to_ticks(efx, usecs);
2012
0bc959a9
BK		 2013 EFX_POPULATE_DWORD_3(timer_cmd, ERF_DZ_TC_TIMER_MODE, mode,
2014 ERF_DZ_TC_TIMER_VAL, ticks,
2015 ERF_FZ_TC_TMR_REL_VAL, ticks);
8127d661
BH		 2016 efx_writed_page(efx, &timer_cmd, ER_DZ_EVQ_TMR,
2017 channel->channel);
2018 }
2019}
2020
02246a7f
SS		 2021static void efx_ef10_get_wol_vf(struct efx_nic *efx,
2022 struct ethtool_wolinfo *wol) {}
2023
2024static int efx_ef10_set_wol_vf(struct efx_nic *efx, u32 type)
2025{
2026 return -EOPNOTSUPP;
2027}
2028
8127d661
BH		 2029static void efx_ef10_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
2030{
2031 wol->supported = 0;
2032 wol->wolopts = 0;
2033 memset(&wol->sopass, 0, sizeof(wol->sopass));
2034}
2035
2036static int efx_ef10_set_wol(struct efx_nic *efx, u32 type)
2037{
2038 if (type != 0)
2039 return -EINVAL;
2040 return 0;
2041}
2042
2043static void efx_ef10_mcdi_request(struct efx_nic *efx,
2044 const efx_dword_t *hdr, size_t hdr_len,
2045 const efx_dword_t *sdu, size_t sdu_len)
2046{
2047 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2048 u8 *pdu = nic_data->mcdi_buf.addr;
2049
2050 memcpy(pdu, hdr, hdr_len);
2051 memcpy(pdu + hdr_len, sdu, sdu_len);
2052 wmb();
2053
2054 /* The hardware provides 'low' and 'high' (doorbell) registers
2055 * for passing the 64-bit address of an MCDI request to
2056 * firmware. However the dwords are swapped by firmware. The
2057 * least significant bits of the doorbell are then 0 for all
2058 * MCDI requests due to alignment.
2059 */
2060 _efx_writed(efx, cpu_to_le32((u64)nic_data->mcdi_buf.dma_addr >> 32),
2061 ER_DZ_MC_DB_LWRD);
2062 _efx_writed(efx, cpu_to_le32((u32)nic_data->mcdi_buf.dma_addr),
2063 ER_DZ_MC_DB_HWRD);
2064}
2065
2066static bool efx_ef10_mcdi_poll_response(struct efx_nic *efx)
2067{
2068 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2069 const efx_dword_t hdr = *(const efx_dword_t *)nic_data->mcdi_buf.addr;
2070
2071 rmb();
2072 return EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE);
2073}
2074
2075static void
2076efx_ef10_mcdi_read_response(struct efx_nic *efx, efx_dword_t *outbuf,
2077 size_t offset, size_t outlen)
2078{
2079 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2080 const u8 *pdu = nic_data->mcdi_buf.addr;
2081
2082 memcpy(outbuf, pdu + offset, outlen);
2083}
2084
c577e59e
DP		 2085static void efx_ef10_mcdi_reboot_detected(struct efx_nic *efx)
2086{
2087 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2088
2089 /* All our allocations have been reset */
2090 efx_ef10_reset_mc_allocations(efx);
2091
2092 /* The datapath firmware might have been changed */
2093 nic_data->must_check_datapath_caps = true;
2094
2095 /* MAC statistics have been cleared on the NIC; clear the local
2096 * statistic that we update with efx_update_diff_stat().
2097 */
2098 nic_data->stats[EF10_STAT_port_rx_bad_bytes] = 0;
2099}
2100
8127d661
BH		 2101static int efx_ef10_mcdi_poll_reboot(struct efx_nic *efx)
2102{
2103 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2104 int rc;
2105
2106 rc = efx_ef10_get_warm_boot_count(efx);
2107 if (rc < 0) {
2108 /* The firmware is presumably in the process of
2109 * rebooting. However, we are supposed to report each
2110 * reboot just once, so we must only do that once we
2111 * can read and store the updated warm boot count.
2112 */
2113 return 0;
2114 }
2115
2116 if (rc == nic_data->warm_boot_count)
2117 return 0;
2118
2119 nic_data->warm_boot_count = rc;
c577e59e 2120 efx_ef10_mcdi_reboot_detected(efx);
869070c5 2121
8127d661
BH		 2122 return -EIO;
2123}
2124
2125/* Handle an MSI interrupt
2126 *
2127 * Handle an MSI hardware interrupt. This routine schedules event
2128 * queue processing. No interrupt acknowledgement cycle is necessary.
2129 * Also, we never need to check that the interrupt is for us, since
2130 * MSI interrupts cannot be shared.
2131 */
2132static irqreturn_t efx_ef10_msi_interrupt(int irq, void *dev_id)
2133{
2134 struct efx_msi_context *context = dev_id;
2135 struct efx_nic *efx = context->efx;
2136
2137 netif_vdbg(efx, intr, efx->net_dev,
2138 "IRQ %d on CPU %d\n", irq, raw_smp_processor_id());
2139
6aa7de05 2140 if (likely(READ_ONCE(efx->irq_soft_enabled))) {
8127d661
BH		 2141 /* Note test interrupts */
2142 if (context->index == efx->irq_level)
2143 efx->last_irq_cpu = raw_smp_processor_id();
2144
2145 /* Schedule processing of the channel */
2146 efx_schedule_channel_irq(efx->channel[context->index]);
2147 }
2148
2149 return IRQ_HANDLED;
2150}
2151
2152static irqreturn_t efx_ef10_legacy_interrupt(int irq, void *dev_id)
2153{
2154 struct efx_nic *efx = dev_id;
6aa7de05 2155 bool soft_enabled = READ_ONCE(efx->irq_soft_enabled);
8127d661
BH		 2156 struct efx_channel *channel;
2157 efx_dword_t reg;
2158 u32 queues;
2159
2160 /* Read the ISR which also ACKs the interrupts */
2161 efx_readd(efx, &reg, ER_DZ_BIU_INT_ISR);
2162 queues = EFX_DWORD_FIELD(reg, ERF_DZ_ISR_REG);
2163
2164 if (queues == 0)
2165 return IRQ_NONE;
2166
2167 if (likely(soft_enabled)) {
2168 /* Note test interrupts */
2169 if (queues & (1U << efx->irq_level))
2170 efx->last_irq_cpu = raw_smp_processor_id();
2171
2172 efx_for_each_channel(channel, efx) {
2173 if (queues & 1)
2174 efx_schedule_channel_irq(channel);
2175 queues >>= 1;
2176 }
2177 }
2178
2179 netif_vdbg(efx, intr, efx->net_dev,
2180 "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
2181 irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
2182
2183 return IRQ_HANDLED;
2184}
2185
942e298e 2186static int efx_ef10_irq_test_generate(struct efx_nic *efx)
8127d661
BH		 2187{
2188 MCDI_DECLARE_BUF(inbuf, MC_CMD_TRIGGER_INTERRUPT_IN_LEN);
2189
942e298e
JC		 2190 if (efx_mcdi_set_workaround(efx, MC_CMD_WORKAROUND_BUG41750, true,
2191 NULL) == 0)
2192 return -ENOTSUPP;
2193
8127d661
BH		 2194 BUILD_BUG_ON(MC_CMD_TRIGGER_INTERRUPT_OUT_LEN != 0);
2195
2196 MCDI_SET_DWORD(inbuf, TRIGGER_INTERRUPT_IN_INTR_LEVEL, efx->irq_level);
942e298e 2197 return efx_mcdi_rpc(efx, MC_CMD_TRIGGER_INTERRUPT,
8127d661
BH		 2198 inbuf, sizeof(inbuf), NULL, 0, NULL);
2199}
2200
2201static int efx_ef10_tx_probe(struct efx_tx_queue *tx_queue)
2202{
2203 return efx_nic_alloc_buffer(tx_queue->efx, &tx_queue->txd.buf,
2204 (tx_queue->ptr_mask + 1) *
2205 sizeof(efx_qword_t),
2206 GFP_KERNEL);
2207}
2208
2209/* This writes to the TX_DESC_WPTR and also pushes data */
2210static inline void efx_ef10_push_tx_desc(struct efx_tx_queue *tx_queue,
2211 const efx_qword_t *txd)
2212{
2213 unsigned int write_ptr;
2214 efx_oword_t reg;
2215
2216 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
2217 EFX_POPULATE_OWORD_1(reg, ERF_DZ_TX_DESC_WPTR, write_ptr);
2218 reg.qword[0] = *txd;
2219 efx_writeo_page(tx_queue->efx, &reg,
2220 ER_DZ_TX_DESC_UPD, tx_queue->queue);
2221}
2222
e9117e50
BK		 2223/* Add Firmware-Assisted TSO v2 option descriptors to a queue.
2224 */
2225static int efx_ef10_tx_tso_desc(struct efx_tx_queue *tx_queue,
2226 struct sk_buff *skb,
2227 bool *data_mapped)
2228{
2229 struct efx_tx_buffer *buffer;
2230 struct tcphdr *tcp;
2231 struct iphdr *ip;
2232
2233 u16 ipv4_id;
2234 u32 seqnum;
2235 u32 mss;
2236
e01b16a7 2237 EFX_WARN_ON_ONCE_PARANOID(tx_queue->tso_version != 2);
e9117e50
BK		 2238
2239 mss = skb_shinfo(skb)->gso_size;
2240
2241 if (unlikely(mss < 4)) {
2242 WARN_ONCE(1, "MSS of %u is too small for TSO v2\n", mss);
2243 return -EINVAL;
2244 }
2245
2246 ip = ip_hdr(skb);
2247 if (ip->version == 4) {
2248 /* Modify IPv4 header if needed. */
2249 ip->tot_len = 0;
2250 ip->check = 0;
6d43131c 2251 ipv4_id = ntohs(ip->id);
e9117e50
BK		 2252 } else {
2253 /* Modify IPv6 header if needed. */
2254 struct ipv6hdr *ipv6 = ipv6_hdr(skb);
2255
2256 ipv6->payload_len = 0;
2257 ipv4_id = 0;
2258 }
2259
2260 tcp = tcp_hdr(skb);
2261 seqnum = ntohl(tcp->seq);
2262
2263 buffer = efx_tx_queue_get_insert_buffer(tx_queue);
2264
2265 buffer->flags = EFX_TX_BUF_OPTION;
2266 buffer->len = 0;
2267 buffer->unmap_len = 0;
2268 EFX_POPULATE_QWORD_5(buffer->option,
2269 ESF_DZ_TX_DESC_IS_OPT, 1,
2270 ESF_DZ_TX_OPTION_TYPE, ESE_DZ_TX_OPTION_DESC_TSO,
2271 ESF_DZ_TX_TSO_OPTION_TYPE,
2272 ESE_DZ_TX_TSO_OPTION_DESC_FATSO2A,
2273 ESF_DZ_TX_TSO_IP_ID, ipv4_id,
2274 ESF_DZ_TX_TSO_TCP_SEQNO, seqnum
2275 );
2276 ++tx_queue->insert_count;
2277
2278 buffer = efx_tx_queue_get_insert_buffer(tx_queue);
2279
2280 buffer->flags = EFX_TX_BUF_OPTION;
2281 buffer->len = 0;
2282 buffer->unmap_len = 0;
2283 EFX_POPULATE_QWORD_4(buffer->option,
2284 ESF_DZ_TX_DESC_IS_OPT, 1,
2285 ESF_DZ_TX_OPTION_TYPE, ESE_DZ_TX_OPTION_DESC_TSO,
2286 ESF_DZ_TX_TSO_OPTION_TYPE,
2287 ESE_DZ_TX_TSO_OPTION_DESC_FATSO2B,
2288 ESF_DZ_TX_TSO_TCP_MSS, mss
2289 );
2290 ++tx_queue->insert_count;
2291
2292 return 0;
2293}
2294
46d1efd8
EC		 2295static u32 efx_ef10_tso_versions(struct efx_nic *efx)
2296{
2297 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2298 u32 tso_versions = 0;
2299
2300 if (nic_data->datapath_caps &
2301 (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN))
2302 tso_versions |= BIT(1);
2303 if (nic_data->datapath_caps2 &
2304 (1 << MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_LBN))
2305 tso_versions |= BIT(2);
2306 return tso_versions;
2307}
2308
8127d661
BH		 2309static void efx_ef10_tx_init(struct efx_tx_queue *tx_queue)
2310{
2311 MCDI_DECLARE_BUF(inbuf, MC_CMD_INIT_TXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
2312 EFX_BUF_SIZE));
8127d661
BH		 2313 bool csum_offload = tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD;
2314 size_t entries = tx_queue->txd.buf.len / EFX_BUF_SIZE;
2315 struct efx_channel *channel = tx_queue->channel;
2316 struct efx_nic *efx = tx_queue->efx;
45b2449e 2317 struct efx_ef10_nic_data *nic_data = efx->nic_data;
e9117e50 2318 bool tso_v2 = false;
aa09a3da 2319 size_t inlen;
8127d661
BH		 2320 dma_addr_t dma_addr;
2321 efx_qword_t *txd;
2322 int rc;
2323 int i;
aa09a3da 2324 BUILD_BUG_ON(MC_CMD_INIT_TXQ_OUT_LEN != 0);
8127d661 2325
e9117e50
BK		 2326 /* TSOv2 is a limited resource that can only be configured on a limited
2327 * number of queues. TSO without checksum offload is not really a thing,
2328 * so we only enable it for those queues.
e9117e50
BK		 2329 */
2330 if (csum_offload && (nic_data->datapath_caps2 &
2331 (1 << MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_LBN))) {
2332 tso_v2 = true;
2333 netif_dbg(efx, hw, efx->net_dev, "Using TSOv2 for channel %u\n",
2334 channel->channel);
2335 }
2336
8127d661
BH		 2337 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_SIZE, tx_queue->ptr_mask + 1);
2338 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_TARGET_EVQ, channel->channel);
2339 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_LABEL, tx_queue->queue);
2340 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_INSTANCE, tx_queue->queue);
8127d661 2341 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_OWNER_ID, 0);
45b2449e 2342 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_PORT_ID, nic_data->vport_id);
8127d661
BH		 2343
2344 dma_addr = tx_queue->txd.buf.dma_addr;
2345
2346 netif_dbg(efx, hw, efx->net_dev, "pushing TXQ %d. %zu entries (%llx)\n",
2347 tx_queue->queue, entries, (u64)dma_addr);
2348
2349 for (i = 0; i < entries; ++i) {
2350 MCDI_SET_ARRAY_QWORD(inbuf, INIT_TXQ_IN_DMA_ADDR, i, dma_addr);
2351 dma_addr += EFX_BUF_SIZE;
2352 }
2353
2354 inlen = MC_CMD_INIT_TXQ_IN_LEN(entries);
2355
e638ee1d
EC		 2356 do {
2357 MCDI_POPULATE_DWORD_3(inbuf, INIT_TXQ_IN_FLAGS,
2358 /* This flag was removed from mcdi_pcol.h for
2359 * the non-_EXT version of INIT_TXQ. However,
2360 * firmware still honours it.
2361 */
2362 INIT_TXQ_EXT_IN_FLAG_TSOV2_EN, tso_v2,
2363 INIT_TXQ_IN_FLAG_IP_CSUM_DIS, !csum_offload,
2364 INIT_TXQ_IN_FLAG_TCP_CSUM_DIS, !csum_offload);
2365
2366 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_INIT_TXQ, inbuf, inlen,
2367 NULL, 0, NULL);
2368 if (rc == -ENOSPC && tso_v2) {
2369 /* Retry without TSOv2 if we're short on contexts. */
2370 tso_v2 = false;
2371 netif_warn(efx, probe, efx->net_dev,
2372 "TSOv2 context not available to segment in hardware. TCP performance may be reduced.\n");
2373 } else if (rc) {
2374 efx_mcdi_display_error(efx, MC_CMD_INIT_TXQ,
2375 MC_CMD_INIT_TXQ_EXT_IN_LEN,
2376 NULL, 0, rc);
2377 goto fail;
2378 }
2379 } while (rc);
8127d661
BH		 2380
2381 /* A previous user of this TX queue might have set us up the
2382 * bomb by writing a descriptor to the TX push collector but
2383 * not the doorbell. (Each collector belongs to a port, not a
2384 * queue or function, so cannot easily be reset.) We must
2385 * attempt to push a no-op descriptor in its place.
2386 */
2387 tx_queue->buffer[0].flags = EFX_TX_BUF_OPTION;
2388 tx_queue->insert_count = 1;
2389 txd = efx_tx_desc(tx_queue, 0);
2390 EFX_POPULATE_QWORD_4(*txd,
2391 ESF_DZ_TX_DESC_IS_OPT, true,
2392 ESF_DZ_TX_OPTION_TYPE,
2393 ESE_DZ_TX_OPTION_DESC_CRC_CSUM,
2394 ESF_DZ_TX_OPTION_UDP_TCP_CSUM, csum_offload,
2395 ESF_DZ_TX_OPTION_IP_CSUM, csum_offload);
2396 tx_queue->write_count = 1;
93171b14 2397
e9117e50
BK		 2398 if (tso_v2) {
2399 tx_queue->handle_tso = efx_ef10_tx_tso_desc;
2400 tx_queue->tso_version = 2;
2401 } else if (nic_data->datapath_caps &
2402 (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN)) {
93171b14
BK		 2403 tx_queue->tso_version = 1;
2404 }
2405
8127d661
BH		 2406 wmb();
2407 efx_ef10_push_tx_desc(tx_queue, txd);
2408
2409 return;
2410
2411fail:
48ce5634
BH		 2412 netdev_WARN(efx->net_dev, "failed to initialise TXQ %d\n",
2413 tx_queue->queue);
8127d661
BH		 2414}
2415
2416static void efx_ef10_tx_fini(struct efx_tx_queue *tx_queue)
2417{
2418 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_TXQ_IN_LEN);
aa09a3da 2419 MCDI_DECLARE_BUF_ERR(outbuf);
8127d661
BH		 2420 struct efx_nic *efx = tx_queue->efx;
2421 size_t outlen;
2422 int rc;
2423
2424 MCDI_SET_DWORD(inbuf, FINI_TXQ_IN_INSTANCE,
2425 tx_queue->queue);
2426
1e0b8120 2427 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_TXQ, inbuf, sizeof(inbuf),
8127d661
BH		 2428 outbuf, sizeof(outbuf), &outlen);
2429
2430 if (rc && rc != -EALREADY)
2431 goto fail;
2432
2433 return;
2434
2435fail:
1e0b8120
EC		 2436 efx_mcdi_display_error(efx, MC_CMD_FINI_TXQ, MC_CMD_FINI_TXQ_IN_LEN,
2437 outbuf, outlen, rc);
8127d661
BH		 2438}
2439
2440static void efx_ef10_tx_remove(struct efx_tx_queue *tx_queue)
2441{
2442 efx_nic_free_buffer(tx_queue->efx, &tx_queue->txd.buf);
2443}
2444
2445/* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
2446static inline void efx_ef10_notify_tx_desc(struct efx_tx_queue *tx_queue)
2447{
2448 unsigned int write_ptr;
2449 efx_dword_t reg;
2450
2451 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
2452 EFX_POPULATE_DWORD_1(reg, ERF_DZ_TX_DESC_WPTR_DWORD, write_ptr);
2453 efx_writed_page(tx_queue->efx, &reg,
2454 ER_DZ_TX_DESC_UPD_DWORD, tx_queue->queue);
2455}
2456
e9117e50
BK		 2457#define EFX_EF10_MAX_TX_DESCRIPTOR_LEN 0x3fff
2458
2459static unsigned int efx_ef10_tx_limit_len(struct efx_tx_queue *tx_queue,
2460 dma_addr_t dma_addr, unsigned int len)
2461{
2462 if (len > EFX_EF10_MAX_TX_DESCRIPTOR_LEN) {
2463 /* If we need to break across multiple descriptors we should
2464 * stop at a page boundary. This assumes the length limit is
2465 * greater than the page size.
2466 */
2467 dma_addr_t end = dma_addr + EFX_EF10_MAX_TX_DESCRIPTOR_LEN;
2468
2469 BUILD_BUG_ON(EFX_EF10_MAX_TX_DESCRIPTOR_LEN < EFX_PAGE_SIZE);
2470 len = (end & (~(EFX_PAGE_SIZE - 1))) - dma_addr;
2471 }
2472
2473 return len;
2474}
2475
8127d661
BH		 2476static void efx_ef10_tx_write(struct efx_tx_queue *tx_queue)
2477{
2478 unsigned int old_write_count = tx_queue->write_count;
2479 struct efx_tx_buffer *buffer;
2480 unsigned int write_ptr;
2481 efx_qword_t *txd;
2482
b2663a4f
MH		 2483 tx_queue->xmit_more_available = false;
2484 if (unlikely(tx_queue->write_count == tx_queue->insert_count))
2485 return;
8127d661
BH		 2486
2487 do {
2488 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
2489 buffer = &tx_queue->buffer[write_ptr];
2490 txd = efx_tx_desc(tx_queue, write_ptr);
2491 ++tx_queue->write_count;
2492
2493 /* Create TX descriptor ring entry */
2494 if (buffer->flags & EFX_TX_BUF_OPTION) {
2495 *txd = buffer->option;
de1deff9
EC		 2496 if (EFX_QWORD_FIELD(*txd, ESF_DZ_TX_OPTION_TYPE) == 1)
2497 /* PIO descriptor */
2498 tx_queue->packet_write_count = tx_queue->write_count;
8127d661 2499 } else {
de1deff9 2500 tx_queue->packet_write_count = tx_queue->write_count;
8127d661
BH		 2501 BUILD_BUG_ON(EFX_TX_BUF_CONT != 1);
2502 EFX_POPULATE_QWORD_3(
2503 *txd,
2504 ESF_DZ_TX_KER_CONT,
2505 buffer->flags & EFX_TX_BUF_CONT,
2506 ESF_DZ_TX_KER_BYTE_CNT, buffer->len,
2507 ESF_DZ_TX_KER_BUF_ADDR, buffer->dma_addr);
2508 }
2509 } while (tx_queue->write_count != tx_queue->insert_count);
2510
2511 wmb(); /* Ensure descriptors are written before they are fetched */
2512
2513 if (efx_nic_may_push_tx_desc(tx_queue, old_write_count)) {
2514 txd = efx_tx_desc(tx_queue,
2515 old_write_count & tx_queue->ptr_mask);
2516 efx_ef10_push_tx_desc(tx_queue, txd);
2517 ++tx_queue->pushes;
2518 } else {
2519 efx_ef10_notify_tx_desc(tx_queue);
2520 }
2521}
2522
a33a4c73
EC		 2523#define RSS_MODE_HASH_ADDRS (1 << RSS_MODE_HASH_SRC_ADDR_LBN |\
2524 1 << RSS_MODE_HASH_DST_ADDR_LBN)
2525#define RSS_MODE_HASH_PORTS (1 << RSS_MODE_HASH_SRC_PORT_LBN |\
2526 1 << RSS_MODE_HASH_DST_PORT_LBN)
2527#define RSS_CONTEXT_FLAGS_DEFAULT (1 << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_LBN |\
2528 1 << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_LBN |\
2529 1 << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_LBN |\
2530 1 << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_LBN |\
2531 (RSS_MODE_HASH_ADDRS | RSS_MODE_HASH_PORTS) << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV4_RSS_MODE_LBN |\
2532 RSS_MODE_HASH_ADDRS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_LBN |\
2533 RSS_MODE_HASH_ADDRS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV4_RSS_MODE_LBN |\
2534 (RSS_MODE_HASH_ADDRS | RSS_MODE_HASH_PORTS) << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV6_RSS_MODE_LBN |\
2535 RSS_MODE_HASH_ADDRS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_LBN |\
2536 RSS_MODE_HASH_ADDRS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV6_RSS_MODE_LBN)
2537
2538static int efx_ef10_get_rss_flags(struct efx_nic *efx, u32 context, u32 *flags)
2539{
2540 /* Firmware had a bug (sfc bug 61952) where it would not actually
2541 * fill in the flags field in the response to MC_CMD_RSS_CONTEXT_GET_FLAGS.
2542 * This meant that it would always contain whatever was previously
2543 * in the MCDI buffer. Fortunately, all firmware versions with
2544 * this bug have the same default flags value for a newly-allocated
2545 * RSS context, and the only time we want to get the flags is just
2546 * after allocating. Moreover, the response has a 32-bit hole
2547 * where the context ID would be in the request, so we can use an
2548 * overlength buffer in the request and pre-fill the flags field
2549 * with what we believe the default to be. Thus if the firmware
2550 * has the bug, it will leave our pre-filled value in the flags
2551 * field of the response, and we will get the right answer.
2552 *
2553 * However, this does mean that this function should NOT be used if
2554 * the RSS context flags might not be their defaults - it is ONLY
2555 * reliably correct for a newly-allocated RSS context.
2556 */
2557 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_LEN);
2558 MCDI_DECLARE_BUF(outbuf, MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_LEN);
2559 size_t outlen;
2560 int rc;
2561
2562 /* Check we have a hole for the context ID */
2563 BUILD_BUG_ON(MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_LEN != MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_FLAGS_OFST);
2564 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_GET_FLAGS_IN_RSS_CONTEXT_ID, context);
2565 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_GET_FLAGS_OUT_FLAGS,
2566 RSS_CONTEXT_FLAGS_DEFAULT);
2567 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_GET_FLAGS, inbuf,
2568 sizeof(inbuf), outbuf, sizeof(outbuf), &outlen);
2569 if (rc == 0) {
2570 if (outlen < MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_LEN)
2571 rc = -EIO;
2572 else
2573 *flags = MCDI_DWORD(outbuf, RSS_CONTEXT_GET_FLAGS_OUT_FLAGS);
2574 }
2575 return rc;
2576}
2577
2578/* Attempt to enable 4-tuple UDP hashing on the specified RSS context.
2579 * If we fail, we just leave the RSS context at its default hash settings,
2580 * which is safe but may slightly reduce performance.
2581 * Defaults are 4-tuple for TCP and 2-tuple for UDP and other-IP, so we
2582 * just need to set the UDP ports flags (for both IP versions).
2583 */
2584static void efx_ef10_set_rss_flags(struct efx_nic *efx, u32 context)
2585{
2586 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_LEN);
2587 u32 flags;
2588
2589 BUILD_BUG_ON(MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT_LEN != 0);
2590
2591 if (efx_ef10_get_rss_flags(efx, context, &flags) != 0)
2592 return;
2593 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_SET_FLAGS_IN_RSS_CONTEXT_ID, context);
2594 flags |= RSS_MODE_HASH_PORTS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_LBN;
2595 flags |= RSS_MODE_HASH_PORTS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_LBN;
2596 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_SET_FLAGS_IN_FLAGS, flags);
b718c88a
EC		 2597 if (!efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_FLAGS, inbuf, sizeof(inbuf),
2598 NULL, 0, NULL))
2599 /* Succeeded, so UDP 4-tuple is now enabled */
2600 efx->rx_hash_udp_4tuple = true;
a33a4c73
EC		 2601}
2602
267c0157
JC		 2603static int efx_ef10_alloc_rss_context(struct efx_nic *efx, u32 *context,
2604 bool exclusive, unsigned *context_size)
8127d661
BH		 2605{
2606 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN);
2607 MCDI_DECLARE_BUF(outbuf, MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN);
45b2449e 2608 struct efx_ef10_nic_data *nic_data = efx->nic_data;
8127d661
BH		 2609 size_t outlen;
2610 int rc;
267c0157
JC		 2611 u32 alloc_type = exclusive ?
2612 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE :
2613 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED;
2614 unsigned rss_spread = exclusive ?
2615 efx->rss_spread :
2616 min(rounddown_pow_of_two(efx->rss_spread),
2617 EFX_EF10_MAX_SHARED_RSS_CONTEXT_SIZE);
2618
2619 if (!exclusive && rss_spread == 1) {
2620 *context = EFX_EF10_RSS_CONTEXT_INVALID;
2621 if (context_size)
2622 *context_size = 1;
2623 return 0;
2624 }
8127d661 2625
dcb4123c
JC		 2626 if (nic_data->datapath_caps &
2627 1 << MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_LBN)
2628 return -EOPNOTSUPP;
2629
8127d661 2630 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID,
45b2449e 2631 nic_data->vport_id);
267c0157
JC		 2632 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_TYPE, alloc_type);
2633 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_NUM_QUEUES, rss_spread);
8127d661
BH		 2634
2635 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_ALLOC, inbuf, sizeof(inbuf),
2636 outbuf, sizeof(outbuf), &outlen);
2637 if (rc != 0)
2638 return rc;
2639
2640 if (outlen < MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN)
2641 return -EIO;
2642
2643 *context = MCDI_DWORD(outbuf, RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID);
2644
267c0157
JC		 2645 if (context_size)
2646 *context_size = rss_spread;
2647
a33a4c73
EC		 2648 if (nic_data->datapath_caps &
2649 1 << MC_CMD_GET_CAPABILITIES_OUT_ADDITIONAL_RSS_MODES_LBN)
2650 efx_ef10_set_rss_flags(efx, *context);
2651
8127d661
BH		 2652 return 0;
2653}
2654
2655static void efx_ef10_free_rss_context(struct efx_nic *efx, u32 context)
2656{
2657 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_FREE_IN_LEN);
2658 int rc;
2659
2660 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID,
2661 context);
2662
2663 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_FREE, inbuf, sizeof(inbuf),
2664 NULL, 0, NULL);
2665 WARN_ON(rc != 0);
2666}
2667
267c0157 2668static int efx_ef10_populate_rss_table(struct efx_nic *efx, u32 context,
f74d1995 2669 const u32 *rx_indir_table, const u8 *key)
8127d661
BH		 2670{
2671 MCDI_DECLARE_BUF(tablebuf, MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN);
2672 MCDI_DECLARE_BUF(keybuf, MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN);
2673 int i, rc;
2674
2675 MCDI_SET_DWORD(tablebuf, RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID,
2676 context);
2677 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_indir_table) !=
2678 MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN);
2679
f74d1995
EC		 2680 /* This iterates over the length of efx->rx_indir_table, but copies
2681 * bytes from rx_indir_table. That's because the latter is a pointer
2682 * rather than an array, but should have the same length.
2683 * The efx->rx_hash_key loop below is similar.
2684 */
8127d661
BH		 2685 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); ++i)
2686 MCDI_PTR(tablebuf,
2687 RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE)[i] =
267c0157 2688 (u8) rx_indir_table[i];
8127d661
BH		 2689
2690 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_TABLE, tablebuf,
2691 sizeof(tablebuf), NULL, 0, NULL);
2692 if (rc != 0)
2693 return rc;
2694
2695 MCDI_SET_DWORD(keybuf, RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID,
2696 context);
2697 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_hash_key) !=
2698 MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN);
2699 for (i = 0; i < ARRAY_SIZE(efx->rx_hash_key); ++i)
f74d1995 2700 MCDI_PTR(keybuf, RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY)[i] = key[i];
8127d661
BH		 2701
2702 return efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_KEY, keybuf,
2703 sizeof(keybuf), NULL, 0, NULL);
2704}
2705
2706static void efx_ef10_rx_free_indir_table(struct efx_nic *efx)
2707{
2708 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2709
2710 if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID)
2711 efx_ef10_free_rss_context(efx, nic_data->rx_rss_context);
2712 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
2713}
2714
267c0157
JC		 2715static int efx_ef10_rx_push_shared_rss_config(struct efx_nic *efx,
2716 unsigned *context_size)
8127d661 2717{
267c0157 2718 u32 new_rx_rss_context;
8127d661 2719 struct efx_ef10_nic_data *nic_data = efx->nic_data;
267c0157
JC		 2720 int rc = efx_ef10_alloc_rss_context(efx, &new_rx_rss_context,
2721 false, context_size);
2722
2723 if (rc != 0)
2724 return rc;
8127d661 2725
267c0157
JC		 2726 nic_data->rx_rss_context = new_rx_rss_context;
2727 nic_data->rx_rss_context_exclusive = false;
2728 efx_set_default_rx_indir_table(efx);
2729 return 0;
2730}
8127d661 2731
267c0157 2732static int efx_ef10_rx_push_exclusive_rss_config(struct efx_nic *efx,
f74d1995
EC		 2733 const u32 *rx_indir_table,
2734 const u8 *key)
267c0157
JC		 2735{
2736 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2737 int rc;
2738 u32 new_rx_rss_context;
2739
2740 if (nic_data->rx_rss_context == EFX_EF10_RSS_CONTEXT_INVALID ||
2741 !nic_data->rx_rss_context_exclusive) {
2742 rc = efx_ef10_alloc_rss_context(efx, &new_rx_rss_context,
2743 true, NULL);
2744 if (rc == -EOPNOTSUPP)
2745 return rc;
2746 else if (rc != 0)
2747 goto fail1;
2748 } else {
2749 new_rx_rss_context = nic_data->rx_rss_context;
8127d661
BH		 2750 }
2751
267c0157 2752 rc = efx_ef10_populate_rss_table(efx, new_rx_rss_context,
f74d1995 2753 rx_indir_table, key);
8127d661 2754 if (rc != 0)
267c0157 2755 goto fail2;
8127d661 2756
267c0157
JC		 2757 if (nic_data->rx_rss_context != new_rx_rss_context)
2758 efx_ef10_rx_free_indir_table(efx);
2759 nic_data->rx_rss_context = new_rx_rss_context;
2760 nic_data->rx_rss_context_exclusive = true;
2761 if (rx_indir_table != efx->rx_indir_table)
2762 memcpy(efx->rx_indir_table, rx_indir_table,
2763 sizeof(efx->rx_indir_table));
f74d1995
EC		 2764 if (key != efx->rx_hash_key)
2765 memcpy(efx->rx_hash_key, key, efx->type->rx_hash_key_size);
2766
267c0157 2767 return 0;
8127d661 2768
267c0157
JC		 2769fail2:
2770 if (new_rx_rss_context != nic_data->rx_rss_context)
2771 efx_ef10_free_rss_context(efx, new_rx_rss_context);
2772fail1:
8127d661 2773 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
267c0157
JC		 2774 return rc;
2775}
2776
a707d188
EC		 2777static int efx_ef10_rx_pull_rss_config(struct efx_nic *efx)
2778{
2779 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2780 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_GET_TABLE_IN_LEN);
2781 MCDI_DECLARE_BUF(tablebuf, MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_LEN);
2782 MCDI_DECLARE_BUF(keybuf, MC_CMD_RSS_CONTEXT_GET_KEY_OUT_LEN);
2783 size_t outlen;
2784 int rc, i;
2785
2786 BUILD_BUG_ON(MC_CMD_RSS_CONTEXT_GET_TABLE_IN_LEN !=
2787 MC_CMD_RSS_CONTEXT_GET_KEY_IN_LEN);
2788
2789 if (nic_data->rx_rss_context == EFX_EF10_RSS_CONTEXT_INVALID)
2790 return -ENOENT;
2791
2792 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_GET_TABLE_IN_RSS_CONTEXT_ID,
2793 nic_data->rx_rss_context);
2794 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_indir_table) !=
2795 MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE_LEN);
2796 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_GET_TABLE, inbuf, sizeof(inbuf),
2797 tablebuf, sizeof(tablebuf), &outlen);
2798 if (rc != 0)
2799 return rc;
2800
2801 if (WARN_ON(outlen != MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_LEN))
2802 return -EIO;
2803
2804 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); i++)
2805 efx->rx_indir_table[i] = MCDI_PTR(tablebuf,
2806 RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE)[i];
2807
2808 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_GET_KEY_IN_RSS_CONTEXT_ID,
2809 nic_data->rx_rss_context);
2810 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_hash_key) !=
2811 MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN);
2812 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_GET_KEY, inbuf, sizeof(inbuf),
2813 keybuf, sizeof(keybuf), &outlen);
2814 if (rc != 0)
2815 return rc;
2816
2817 if (WARN_ON(outlen != MC_CMD_RSS_CONTEXT_GET_KEY_OUT_LEN))
2818 return -EIO;
2819
2820 for (i = 0; i < ARRAY_SIZE(efx->rx_hash_key); ++i)
2821 efx->rx_hash_key[i] = MCDI_PTR(
2822 keybuf, RSS_CONTEXT_GET_KEY_OUT_TOEPLITZ_KEY)[i];
2823
2824 return 0;
2825}
2826
267c0157 2827static int efx_ef10_pf_rx_push_rss_config(struct efx_nic *efx, bool user,
f74d1995
EC		 2828 const u32 *rx_indir_table,
2829 const u8 *key)
267c0157
JC		 2830{
2831 int rc;
2832
2833 if (efx->rss_spread == 1)
2834 return 0;
2835
f74d1995
EC		 2836 if (!key)
2837 key = efx->rx_hash_key;
2838
2839 rc = efx_ef10_rx_push_exclusive_rss_config(efx, rx_indir_table, key);
267c0157
JC		 2840
2841 if (rc == -ENOBUFS && !user) {
2842 unsigned context_size;
2843 bool mismatch = false;
2844 size_t i;
2845
2846 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table) && !mismatch;
2847 i++)
2848 mismatch = rx_indir_table[i] !=
2849 ethtool_rxfh_indir_default(i, efx->rss_spread);
2850
2851 rc = efx_ef10_rx_push_shared_rss_config(efx, &context_size);
2852 if (rc == 0) {
2853 if (context_size != efx->rss_spread)
2854 netif_warn(efx, probe, efx->net_dev,
2855 "Could not allocate an exclusive RSS"
2856 " context; allocated a shared one of"
2857 " different size."
2858 " Wanted %u, got %u.\n",
2859 efx->rss_spread, context_size);
2860 else if (mismatch)
2861 netif_warn(efx, probe, efx->net_dev,
2862 "Could not allocate an exclusive RSS"
2863 " context; allocated a shared one but"
2864 " could not apply custom"
2865 " indirection.\n");
2866 else
2867 netif_info(efx, probe, efx->net_dev,
2868 "Could not allocate an exclusive RSS"
2869 " context; allocated a shared one.\n");
2870 }
2871 }
2872 return rc;
2873}
2874
2875static int efx_ef10_vf_rx_push_rss_config(struct efx_nic *efx, bool user,
2876 const u32 *rx_indir_table
f74d1995
EC		 2877 __attribute__ ((unused)),
2878 const u8 *key
267c0157
JC		 2879 __attribute__ ((unused)))
2880{
2881 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2882
2883 if (user)
2884 return -EOPNOTSUPP;
2885 if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID)
2886 return 0;
2887 return efx_ef10_rx_push_shared_rss_config(efx, NULL);
8127d661
BH		 2888}
2889
2890static int efx_ef10_rx_probe(struct efx_rx_queue *rx_queue)
2891{
2892 return efx_nic_alloc_buffer(rx_queue->efx, &rx_queue->rxd.buf,
2893 (rx_queue->ptr_mask + 1) *
2894 sizeof(efx_qword_t),
2895 GFP_KERNEL);
2896}
2897
2898static void efx_ef10_rx_init(struct efx_rx_queue *rx_queue)
2899{
2900 MCDI_DECLARE_BUF(inbuf,
2901 MC_CMD_INIT_RXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
2902 EFX_BUF_SIZE));
8127d661
BH		 2903 struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
2904 size_t entries = rx_queue->rxd.buf.len / EFX_BUF_SIZE;
2905 struct efx_nic *efx = rx_queue->efx;
45b2449e 2906 struct efx_ef10_nic_data *nic_data = efx->nic_data;
aa09a3da 2907 size_t inlen;
8127d661
BH		 2908 dma_addr_t dma_addr;
2909 int rc;
2910 int i;
aa09a3da 2911 BUILD_BUG_ON(MC_CMD_INIT_RXQ_OUT_LEN != 0);
8127d661
BH		 2912
2913 rx_queue->scatter_n = 0;
2914 rx_queue->scatter_len = 0;
2915
2916 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_SIZE, rx_queue->ptr_mask + 1);
2917 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_TARGET_EVQ, channel->channel);
2918 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_LABEL, efx_rx_queue_index(rx_queue));
2919 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_INSTANCE,
2920 efx_rx_queue_index(rx_queue));
bd9a265d
JC		 2921 MCDI_POPULATE_DWORD_2(inbuf, INIT_RXQ_IN_FLAGS,
2922 INIT_RXQ_IN_FLAG_PREFIX, 1,
2923 INIT_RXQ_IN_FLAG_TIMESTAMP, 1);
8127d661 2924 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_OWNER_ID, 0);
45b2449e 2925 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_PORT_ID, nic_data->vport_id);
8127d661
BH		 2926
2927 dma_addr = rx_queue->rxd.buf.dma_addr;
2928
2929 netif_dbg(efx, hw, efx->net_dev, "pushing RXQ %d. %zu entries (%llx)\n",
2930 efx_rx_queue_index(rx_queue), entries, (u64)dma_addr);
2931
2932 for (i = 0; i < entries; ++i) {
2933 MCDI_SET_ARRAY_QWORD(inbuf, INIT_RXQ_IN_DMA_ADDR, i, dma_addr);
2934 dma_addr += EFX_BUF_SIZE;
2935 }
2936
2937 inlen = MC_CMD_INIT_RXQ_IN_LEN(entries);
2938
2939 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_RXQ, inbuf, inlen,
aa09a3da 2940 NULL, 0, NULL);
48ce5634
BH		 2941 if (rc)
2942 netdev_WARN(efx->net_dev, "failed to initialise RXQ %d\n",
2943 efx_rx_queue_index(rx_queue));
8127d661
BH		 2944}
2945
2946static void efx_ef10_rx_fini(struct efx_rx_queue *rx_queue)
2947{
2948 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_RXQ_IN_LEN);
aa09a3da 2949 MCDI_DECLARE_BUF_ERR(outbuf);
8127d661
BH		 2950 struct efx_nic *efx = rx_queue->efx;
2951 size_t outlen;
2952 int rc;
2953
2954 MCDI_SET_DWORD(inbuf, FINI_RXQ_IN_INSTANCE,
2955 efx_rx_queue_index(rx_queue));
2956
1e0b8120 2957 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_RXQ, inbuf, sizeof(inbuf),
8127d661
BH		 2958 outbuf, sizeof(outbuf), &outlen);
2959
2960 if (rc && rc != -EALREADY)
2961 goto fail;
2962
2963 return;
2964
2965fail:
1e0b8120
EC		 2966 efx_mcdi_display_error(efx, MC_CMD_FINI_RXQ, MC_CMD_FINI_RXQ_IN_LEN,
2967 outbuf, outlen, rc);
8127d661
BH		 2968}
2969
2970static void efx_ef10_rx_remove(struct efx_rx_queue *rx_queue)
2971{
2972 efx_nic_free_buffer(rx_queue->efx, &rx_queue->rxd.buf);
2973}
2974
2975/* This creates an entry in the RX descriptor queue */
2976static inline void
2977efx_ef10_build_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index)
2978{
2979 struct efx_rx_buffer *rx_buf;
2980 efx_qword_t *rxd;
2981
2982 rxd = efx_rx_desc(rx_queue, index);
2983 rx_buf = efx_rx_buffer(rx_queue, index);
2984 EFX_POPULATE_QWORD_2(*rxd,
2985 ESF_DZ_RX_KER_BYTE_CNT, rx_buf->len,
2986 ESF_DZ_RX_KER_BUF_ADDR, rx_buf->dma_addr);
2987}
2988
2989static void efx_ef10_rx_write(struct efx_rx_queue *rx_queue)
2990{
2991 struct efx_nic *efx = rx_queue->efx;
2992 unsigned int write_count;
2993 efx_dword_t reg;
2994
2995 /* Firmware requires that RX_DESC_WPTR be a multiple of 8 */
2996 write_count = rx_queue->added_count & ~7;
2997 if (rx_queue->notified_count == write_count)
2998 return;
2999
3000 do
3001 efx_ef10_build_rx_desc(
3002 rx_queue,
3003 rx_queue->notified_count & rx_queue->ptr_mask);
3004 while (++rx_queue->notified_count != write_count);
3005
3006 wmb();
3007 EFX_POPULATE_DWORD_1(reg, ERF_DZ_RX_DESC_WPTR,
3008 write_count & rx_queue->ptr_mask);
3009 efx_writed_page(efx, &reg, ER_DZ_RX_DESC_UPD,
3010 efx_rx_queue_index(rx_queue));
3011}
3012
3013static efx_mcdi_async_completer efx_ef10_rx_defer_refill_complete;
3014
3015static void efx_ef10_rx_defer_refill(struct efx_rx_queue *rx_queue)
3016{
3017 struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
3018 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
3019 efx_qword_t event;
3020
3021 EFX_POPULATE_QWORD_2(event,
3022 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
3023 ESF_DZ_EV_DATA, EFX_EF10_REFILL);
3024
3025 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
3026
3027 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
3028 * already swapped the data to little-endian order.
3029 */
3030 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
3031 sizeof(efx_qword_t));
3032
3033 efx_mcdi_rpc_async(channel->efx, MC_CMD_DRIVER_EVENT,
3034 inbuf, sizeof(inbuf), 0,
3035 efx_ef10_rx_defer_refill_complete, 0);
3036}
3037
3038static void
3039efx_ef10_rx_defer_refill_complete(struct efx_nic *efx, unsigned long cookie,
3040 int rc, efx_dword_t *outbuf,
3041 size_t outlen_actual)
3042{
3043 /* nothing to do */
3044}
3045
3046static int efx_ef10_ev_probe(struct efx_channel *channel)
3047{
3048 return efx_nic_alloc_buffer(channel->efx, &channel->eventq.buf,
3049 (channel->eventq_mask + 1) *
3050 sizeof(efx_qword_t),
3051 GFP_KERNEL);
3052}
3053
46e612b0
DP		 3054static void efx_ef10_ev_fini(struct efx_channel *channel)
3055{
3056 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_EVQ_IN_LEN);
3057 MCDI_DECLARE_BUF_ERR(outbuf);
3058 struct efx_nic *efx = channel->efx;
3059 size_t outlen;
3060 int rc;
3061
3062 MCDI_SET_DWORD(inbuf, FINI_EVQ_IN_INSTANCE, channel->channel);
3063
3064 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_EVQ, inbuf, sizeof(inbuf),
3065 outbuf, sizeof(outbuf), &outlen);
3066
3067 if (rc && rc != -EALREADY)
3068 goto fail;
3069
3070 return;
3071
3072fail:
3073 efx_mcdi_display_error(efx, MC_CMD_FINI_EVQ, MC_CMD_FINI_EVQ_IN_LEN,
3074 outbuf, outlen, rc);
3075}
3076
8127d661
BH		 3077static int efx_ef10_ev_init(struct efx_channel *channel)
3078{
3079 MCDI_DECLARE_BUF(inbuf,
a995560a
BK		 3080 MC_CMD_INIT_EVQ_V2_IN_LEN(EFX_MAX_EVQ_SIZE * 8 /
3081 EFX_BUF_SIZE));
3082 MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_EVQ_V2_OUT_LEN);
8127d661
BH		 3083 size_t entries = channel->eventq.buf.len / EFX_BUF_SIZE;
3084 struct efx_nic *efx = channel->efx;
3085 struct efx_ef10_nic_data *nic_data;
8127d661 3086 size_t inlen, outlen;
46e612b0 3087 unsigned int enabled, implemented;
8127d661
BH		 3088 dma_addr_t dma_addr;
3089 int rc;
3090 int i;
3091
3092 nic_data = efx->nic_data;
8127d661
BH		 3093
3094 /* Fill event queue with all ones (i.e. empty events) */
3095 memset(channel->eventq.buf.addr, 0xff, channel->eventq.buf.len);
3096
3097 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_SIZE, channel->eventq_mask + 1);
3098 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_INSTANCE, channel->channel);
3099 /* INIT_EVQ expects index in vector table, not absolute */
3100 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_IRQ_NUM, channel->channel);
8127d661
BH		 3101 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_MODE,
3102 MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS);
3103 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_LOAD, 0);
3104 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_RELOAD, 0);
3105 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_MODE,
3106 MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS);
3107 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_THRSHLD, 0);
3108
a995560a
BK		 3109 if (nic_data->datapath_caps2 &
3110 1 << MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_V2_LBN) {
3111 /* Use the new generic approach to specifying event queue
3112 * configuration, requesting lower latency or higher throughput.
3113 * The options that actually get used appear in the output.
3114 */
3115 MCDI_POPULATE_DWORD_2(inbuf, INIT_EVQ_V2_IN_FLAGS,
3116 INIT_EVQ_V2_IN_FLAG_INTERRUPTING, 1,
3117 INIT_EVQ_V2_IN_FLAG_TYPE,
3118 MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_AUTO);
3119 } else {
3120 bool cut_thru = !(nic_data->datapath_caps &
3121 1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN);
3122
3123 MCDI_POPULATE_DWORD_4(inbuf, INIT_EVQ_IN_FLAGS,
3124 INIT_EVQ_IN_FLAG_INTERRUPTING, 1,
3125 INIT_EVQ_IN_FLAG_RX_MERGE, 1,
3126 INIT_EVQ_IN_FLAG_TX_MERGE, 1,
3127 INIT_EVQ_IN_FLAG_CUT_THRU, cut_thru);
3128 }
3129
8127d661
BH		 3130 dma_addr = channel->eventq.buf.dma_addr;
3131 for (i = 0; i < entries; ++i) {
3132 MCDI_SET_ARRAY_QWORD(inbuf, INIT_EVQ_IN_DMA_ADDR, i, dma_addr);
3133 dma_addr += EFX_BUF_SIZE;
3134 }
3135
3136 inlen = MC_CMD_INIT_EVQ_IN_LEN(entries);
3137
3138 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_EVQ, inbuf, inlen,
3139 outbuf, sizeof(outbuf), &outlen);
a995560a
BK		 3140
3141 if (outlen >= MC_CMD_INIT_EVQ_V2_OUT_LEN)
3142 netif_dbg(efx, drv, efx->net_dev,
3143 "Channel %d using event queue flags %08x\n",
3144 channel->channel,
3145 MCDI_DWORD(outbuf, INIT_EVQ_V2_OUT_FLAGS));
3146
8127d661 3147 /* IRQ return is ignored */
46e612b0
DP		 3148 if (channel->channel || rc)
3149 return rc;
8127d661 3150
46e612b0
DP		 3151 /* Successfully created event queue on channel 0 */
3152 rc = efx_mcdi_get_workarounds(efx, &implemented, &enabled);
832dc9ed 3153 if (rc == -ENOSYS) {
d95e329a
BK		 3154 /* GET_WORKAROUNDS was implemented before this workaround,
3155 * thus it must be unavailable in this firmware.
832dc9ed
EC		 3156 */
3157 nic_data->workaround_26807 = false;
3158 rc = 0;
3159 } else if (rc) {
8127d661 3160 goto fail;
832dc9ed
EC		 3161 } else {
3162 nic_data->workaround_26807 =
3163 !!(enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807);
3164
3165 if (implemented & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807 &&
3166 !nic_data->workaround_26807) {
5a55a72a
DP		 3167 unsigned int flags;
3168
34ccfe6f
DP		 3169 rc = efx_mcdi_set_workaround(efx,
3170 MC_CMD_WORKAROUND_BUG26807,
5a55a72a
DP		 3171 true, &flags);
3172
3173 if (!rc) {
3174 if (flags &
3175 1 << MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN) {
3176 netif_info(efx, drv, efx->net_dev,
3177 "other functions on NIC have been reset\n");
abd86a55
DP		 3178
3179 /* With MCFW v4.6.x and earlier, the
3180 * boot count will have incremented,
3181 * so re-read the warm_boot_count
3182 * value now to ensure this function
3183 * doesn't think it has changed next
3184 * time it checks.
3185 */
3186 rc = efx_ef10_get_warm_boot_count(efx);
3187 if (rc >= 0) {
3188 nic_data->warm_boot_count = rc;
3189 rc = 0;
3190 }
5a55a72a 3191 }
832dc9ed 3192 nic_data->workaround_26807 = true;
5a55a72a 3193 } else if (rc == -EPERM) {
832dc9ed 3194 rc = 0;
5a55a72a 3195 }
832dc9ed 3196 }
46e612b0
DP		 3197 }
3198
3199 if (!rc)
3200 return 0;
8127d661
BH		 3201
3202fail:
46e612b0
DP		 3203 efx_ef10_ev_fini(channel);
3204 return rc;
8127d661
BH		 3205}
3206
3207static void efx_ef10_ev_remove(struct efx_channel *channel)
3208{
3209 efx_nic_free_buffer(channel->efx, &channel->eventq.buf);
3210}
3211
3212static void efx_ef10_handle_rx_wrong_queue(struct efx_rx_queue *rx_queue,
3213 unsigned int rx_queue_label)
3214{
3215 struct efx_nic *efx = rx_queue->efx;
3216
3217 netif_info(efx, hw, efx->net_dev,
3218 "rx event arrived on queue %d labeled as queue %u\n",
3219 efx_rx_queue_index(rx_queue), rx_queue_label);
3220
3221 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
3222}
3223
3224static void
3225efx_ef10_handle_rx_bad_lbits(struct efx_rx_queue *rx_queue,
3226 unsigned int actual, unsigned int expected)
3227{
3228 unsigned int dropped = (actual - expected) & rx_queue->ptr_mask;
3229 struct efx_nic *efx = rx_queue->efx;
3230
3231 netif_info(efx, hw, efx->net_dev,
3232 "dropped %d events (index=%d expected=%d)\n",
3233 dropped, actual, expected);
3234
3235 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
3236}
3237
3238/* partially received RX was aborted. clean up. */
3239static void efx_ef10_handle_rx_abort(struct efx_rx_queue *rx_queue)
3240{
3241 unsigned int rx_desc_ptr;
3242
8127d661
BH		 3243 netif_dbg(rx_queue->efx, hw, rx_queue->efx->net_dev,
3244 "scattered RX aborted (dropping %u buffers)\n",
3245 rx_queue->scatter_n);
3246
3247 rx_desc_ptr = rx_queue->removed_count & rx_queue->ptr_mask;
3248
3249 efx_rx_packet(rx_queue, rx_desc_ptr, rx_queue->scatter_n,
3250 0, EFX_RX_PKT_DISCARD);
3251
3252 rx_queue->removed_count += rx_queue->scatter_n;
3253 rx_queue->scatter_n = 0;
3254 rx_queue->scatter_len = 0;
3255 ++efx_rx_queue_channel(rx_queue)->n_rx_nodesc_trunc;
3256}
3257
a0ee3541
JC		 3258static u16 efx_ef10_handle_rx_event_errors(struct efx_channel *channel,
3259 unsigned int n_packets,
3260 unsigned int rx_encap_hdr,
3261 unsigned int rx_l3_class,
3262 unsigned int rx_l4_class,
3263 const efx_qword_t *event)
3264{
3265 struct efx_nic *efx = channel->efx;
6978729f 3266 bool handled = false;
a0ee3541
JC		 3267
3268 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_ECRC_ERR)) {
6978729f
EC		 3269 if (!(efx->net_dev->features & NETIF_F_RXALL)) {
3270 if (!efx->loopback_selftest)
3271 channel->n_rx_eth_crc_err += n_packets;
3272 return EFX_RX_PKT_DISCARD;
3273 }
3274 handled = true;
a0ee3541
JC		 3275 }
3276 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_IPCKSUM_ERR)) {
3277 if (unlikely(rx_encap_hdr != ESE_EZ_ENCAP_HDR_VXLAN &&
3278 rx_l3_class != ESE_DZ_L3_CLASS_IP4 &&
3279 rx_l3_class != ESE_DZ_L3_CLASS_IP4_FRAG &&
3280 rx_l3_class != ESE_DZ_L3_CLASS_IP6 &&
3281 rx_l3_class != ESE_DZ_L3_CLASS_IP6_FRAG))
3282 netdev_WARN(efx->net_dev,
3283 "invalid class for RX_IPCKSUM_ERR: event="
3284 EFX_QWORD_FMT "\n",
3285 EFX_QWORD_VAL(*event));
3286 if (!efx->loopback_selftest)
3287 *(rx_encap_hdr ?
3288 &channel->n_rx_outer_ip_hdr_chksum_err :
3289 &channel->n_rx_ip_hdr_chksum_err) += n_packets;
3290 return 0;
3291 }
3292 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_TCPUDP_CKSUM_ERR)) {
3293 if (unlikely(rx_encap_hdr != ESE_EZ_ENCAP_HDR_VXLAN &&
3294 ((rx_l3_class != ESE_DZ_L3_CLASS_IP4 &&
3295 rx_l3_class != ESE_DZ_L3_CLASS_IP6) ||
d8d8ccf2
BK		 3296 (rx_l4_class != ESE_FZ_L4_CLASS_TCP &&
3297 rx_l4_class != ESE_FZ_L4_CLASS_UDP))))
a0ee3541
JC		 3298 netdev_WARN(efx->net_dev,
3299 "invalid class for RX_TCPUDP_CKSUM_ERR: event="
3300 EFX_QWORD_FMT "\n",
3301 EFX_QWORD_VAL(*event));
3302 if (!efx->loopback_selftest)
3303 *(rx_encap_hdr ?
3304 &channel->n_rx_outer_tcp_udp_chksum_err :
3305 &channel->n_rx_tcp_udp_chksum_err) += n_packets;
3306 return 0;
3307 }
3308 if (EFX_QWORD_FIELD(*event, ESF_EZ_RX_IP_INNER_CHKSUM_ERR)) {
3309 if (unlikely(!rx_encap_hdr))
3310 netdev_WARN(efx->net_dev,
3311 "invalid encapsulation type for RX_IP_INNER_CHKSUM_ERR: event="
3312 EFX_QWORD_FMT "\n",
3313 EFX_QWORD_VAL(*event));
3314 else if (unlikely(rx_l3_class != ESE_DZ_L3_CLASS_IP4 &&
3315 rx_l3_class != ESE_DZ_L3_CLASS_IP4_FRAG &&
3316 rx_l3_class != ESE_DZ_L3_CLASS_IP6 &&
3317 rx_l3_class != ESE_DZ_L3_CLASS_IP6_FRAG))
3318 netdev_WARN(efx->net_dev,
3319 "invalid class for RX_IP_INNER_CHKSUM_ERR: event="
3320 EFX_QWORD_FMT "\n",
3321 EFX_QWORD_VAL(*event));
3322 if (!efx->loopback_selftest)
3323 channel->n_rx_inner_ip_hdr_chksum_err += n_packets;
3324 return 0;
3325 }
3326 if (EFX_QWORD_FIELD(*event, ESF_EZ_RX_TCP_UDP_INNER_CHKSUM_ERR)) {
3327 if (unlikely(!rx_encap_hdr))
3328 netdev_WARN(efx->net_dev,
3329 "invalid encapsulation type for RX_TCP_UDP_INNER_CHKSUM_ERR: event="
3330 EFX_QWORD_FMT "\n",
3331 EFX_QWORD_VAL(*event));
3332 else if (unlikely((rx_l3_class != ESE_DZ_L3_CLASS_IP4 &&
3333 rx_l3_class != ESE_DZ_L3_CLASS_IP6) ||
d8d8ccf2
BK		 3334 (rx_l4_class != ESE_FZ_L4_CLASS_TCP &&
3335 rx_l4_class != ESE_FZ_L4_CLASS_UDP)))
a0ee3541
JC		 3336 netdev_WARN(efx->net_dev,
3337 "invalid class for RX_TCP_UDP_INNER_CHKSUM_ERR: event="
3338 EFX_QWORD_FMT "\n",
3339 EFX_QWORD_VAL(*event));
3340 if (!efx->loopback_selftest)
3341 channel->n_rx_inner_tcp_udp_chksum_err += n_packets;
3342 return 0;
3343 }
3344
6978729f 3345 WARN_ON(!handled); /* No error bits were recognised */
a0ee3541
JC		 3346 return 0;
3347}
3348
8127d661
BH		 3349static int efx_ef10_handle_rx_event(struct efx_channel *channel,
3350 const efx_qword_t *event)
3351{
a0ee3541
JC		 3352 unsigned int rx_bytes, next_ptr_lbits, rx_queue_label;
3353 unsigned int rx_l3_class, rx_l4_class, rx_encap_hdr;
8127d661
BH		 3354 unsigned int n_descs, n_packets, i;
3355 struct efx_nic *efx = channel->efx;
a0ee3541 3356 struct efx_ef10_nic_data *nic_data = efx->nic_data;
8127d661 3357 struct efx_rx_queue *rx_queue;
a0ee3541 3358 efx_qword_t errors;
8127d661
BH		 3359 bool rx_cont;
3360 u16 flags = 0;
3361
6aa7de05 3362 if (unlikely(READ_ONCE(efx->reset_pending)))
8127d661
BH		 3363 return 0;
3364
3365 /* Basic packet information */
3366 rx_bytes = EFX_QWORD_FIELD(*event, ESF_DZ_RX_BYTES);
3367 next_ptr_lbits = EFX_QWORD_FIELD(*event, ESF_DZ_RX_DSC_PTR_LBITS);
3368 rx_queue_label = EFX_QWORD_FIELD(*event, ESF_DZ_RX_QLABEL);
a0ee3541 3369 rx_l3_class = EFX_QWORD_FIELD(*event, ESF_DZ_RX_L3_CLASS);
d8d8ccf2 3370 rx_l4_class = EFX_QWORD_FIELD(*event, ESF_FZ_RX_L4_CLASS);
8127d661 3371 rx_cont = EFX_QWORD_FIELD(*event, ESF_DZ_RX_CONT);
a0ee3541
JC		 3372 rx_encap_hdr =
3373 nic_data->datapath_caps &
3374 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN) ?
3375 EFX_QWORD_FIELD(*event, ESF_EZ_RX_ENCAP_HDR) :
3376 ESE_EZ_ENCAP_HDR_NONE;
8127d661 3377
48ce5634
BH		 3378 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_DROP_EVENT))
3379 netdev_WARN(efx->net_dev, "saw RX_DROP_EVENT: event="
3380 EFX_QWORD_FMT "\n",
3381 EFX_QWORD_VAL(*event));
8127d661
BH		 3382
3383 rx_queue = efx_channel_get_rx_queue(channel);
3384
3385 if (unlikely(rx_queue_label != efx_rx_queue_index(rx_queue)))
3386 efx_ef10_handle_rx_wrong_queue(rx_queue, rx_queue_label);
3387
3388 n_descs = ((next_ptr_lbits - rx_queue->removed_count) &
3389 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
3390
3391 if (n_descs != rx_queue->scatter_n + 1) {
92a04168
BH		 3392 struct efx_ef10_nic_data *nic_data = efx->nic_data;
3393
8127d661
BH		 3394 /* detect rx abort */
3395 if (unlikely(n_descs == rx_queue->scatter_n)) {
48ce5634
BH		 3396 if (rx_queue->scatter_n == 0 || rx_bytes != 0)
3397 netdev_WARN(efx->net_dev,
3398 "invalid RX abort: scatter_n=%u event="
3399 EFX_QWORD_FMT "\n",
3400 rx_queue->scatter_n,
3401 EFX_QWORD_VAL(*event));
8127d661
BH		 3402 efx_ef10_handle_rx_abort(rx_queue);
3403 return 0;
3404 }
3405
92a04168
BH		 3406 /* Check that RX completion merging is valid, i.e.
3407 * the current firmware supports it and this is a
3408 * non-scattered packet.
3409 */
3410 if (!(nic_data->datapath_caps &
3411 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN)) ||
3412 rx_queue->scatter_n != 0 || rx_cont) {
8127d661
BH		 3413 efx_ef10_handle_rx_bad_lbits(
3414 rx_queue, next_ptr_lbits,
3415 (rx_queue->removed_count +
3416 rx_queue->scatter_n + 1) &
3417 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
3418 return 0;
3419 }
3420
3421 /* Merged completion for multiple non-scattered packets */
3422 rx_queue->scatter_n = 1;
3423 rx_queue->scatter_len = 0;
3424 n_packets = n_descs;
3425 ++channel->n_rx_merge_events;
3426 channel->n_rx_merge_packets += n_packets;
3427 flags |= EFX_RX_PKT_PREFIX_LEN;
3428 } else {
3429 ++rx_queue->scatter_n;
3430 rx_queue->scatter_len += rx_bytes;
3431 if (rx_cont)
3432 return 0;
3433 n_packets = 1;
3434 }
3435
a0ee3541
JC		 3436 EFX_POPULATE_QWORD_5(errors, ESF_DZ_RX_ECRC_ERR, 1,
3437 ESF_DZ_RX_IPCKSUM_ERR, 1,
3438 ESF_DZ_RX_TCPUDP_CKSUM_ERR, 1,
3439 ESF_EZ_RX_IP_INNER_CHKSUM_ERR, 1,
3440 ESF_EZ_RX_TCP_UDP_INNER_CHKSUM_ERR, 1);
3441 EFX_AND_QWORD(errors, *event, errors);
3442 if (unlikely(!EFX_QWORD_IS_ZERO(errors))) {
3443 flags |= efx_ef10_handle_rx_event_errors(channel, n_packets,
90d2ea9f 3444 rx_encap_hdr,
a0ee3541 3445 rx_l3_class, rx_l4_class,
90d2ea9f 3446 event);
a0ee3541 3447 } else {
d8d8ccf2
BK		 3448 bool tcpudp = rx_l4_class == ESE_FZ_L4_CLASS_TCP ||
3449 rx_l4_class == ESE_FZ_L4_CLASS_UDP;
da50ae2e
JC		 3450
3451 switch (rx_encap_hdr) {
3452 case ESE_EZ_ENCAP_HDR_VXLAN: /* VxLAN or GENEVE */
3453 flags |= EFX_RX_PKT_CSUMMED; /* outer UDP csum */
3454 if (tcpudp)
3455 flags |= EFX_RX_PKT_CSUM_LEVEL; /* inner L4 */
3456 break;
3457 case ESE_EZ_ENCAP_HDR_GRE:
3458 case ESE_EZ_ENCAP_HDR_NONE:
3459 if (tcpudp)
3460 flags |= EFX_RX_PKT_CSUMMED;
3461 break;
3462 default:
3463 netdev_WARN(efx->net_dev,
3464 "unknown encapsulation type: event="
3465 EFX_QWORD_FMT "\n",
3466 EFX_QWORD_VAL(*event));
3467 }
8127d661
BH		 3468 }
3469
d8d8ccf2 3470 if (rx_l4_class == ESE_FZ_L4_CLASS_TCP)
8127d661
BH		 3471 flags |= EFX_RX_PKT_TCP;
3472
3473 channel->irq_mod_score += 2 * n_packets;
3474
3475 /* Handle received packet(s) */
3476 for (i = 0; i < n_packets; i++) {
3477 efx_rx_packet(rx_queue,
3478 rx_queue->removed_count & rx_queue->ptr_mask,
3479 rx_queue->scatter_n, rx_queue->scatter_len,
3480 flags);
3481 rx_queue->removed_count += rx_queue->scatter_n;
3482 }
3483
3484 rx_queue->scatter_n = 0;
3485 rx_queue->scatter_len = 0;
3486
3487 return n_packets;
3488}
3489
3490static int
3491efx_ef10_handle_tx_event(struct efx_channel *channel, efx_qword_t *event)
3492{
3493 struct efx_nic *efx = channel->efx;
3494 struct efx_tx_queue *tx_queue;
3495 unsigned int tx_ev_desc_ptr;
3496 unsigned int tx_ev_q_label;
3497 int tx_descs = 0;
3498
6aa7de05 3499 if (unlikely(READ_ONCE(efx->reset_pending)))
8127d661
BH		 3500 return 0;
3501
3502 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_TX_DROP_EVENT)))
3503 return 0;
3504
3505 /* Transmit completion */
3506 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, ESF_DZ_TX_DESCR_INDX);
3507 tx_ev_q_label = EFX_QWORD_FIELD(*event, ESF_DZ_TX_QLABEL);
3508 tx_queue = efx_channel_get_tx_queue(channel,
3509 tx_ev_q_label % EFX_TXQ_TYPES);
3510 tx_descs = ((tx_ev_desc_ptr + 1 - tx_queue->read_count) &
3511 tx_queue->ptr_mask);
3512 efx_xmit_done(tx_queue, tx_ev_desc_ptr & tx_queue->ptr_mask);
3513
3514 return tx_descs;
3515}
3516
3517static void
3518efx_ef10_handle_driver_event(struct efx_channel *channel, efx_qword_t *event)
3519{
3520 struct efx_nic *efx = channel->efx;
3521 int subcode;
3522
3523 subcode = EFX_QWORD_FIELD(*event, ESF_DZ_DRV_SUB_CODE);
3524
3525 switch (subcode) {
3526 case ESE_DZ_DRV_TIMER_EV:
3527 case ESE_DZ_DRV_WAKE_UP_EV:
3528 break;
3529 case ESE_DZ_DRV_START_UP_EV:
3530 /* event queue init complete. ok. */
3531 break;
3532 default:
3533 netif_err(efx, hw, efx->net_dev,
3534 "channel %d unknown driver event type %d"
3535 " (data " EFX_QWORD_FMT ")\n",
3536 channel->channel, subcode,
3537 EFX_QWORD_VAL(*event));
3538
3539 }
3540}
3541
3542static void efx_ef10_handle_driver_generated_event(struct efx_channel *channel,
3543 efx_qword_t *event)
3544{
3545 struct efx_nic *efx = channel->efx;
3546 u32 subcode;
3547
3548 subcode = EFX_QWORD_FIELD(*event, EFX_DWORD_0);
3549
3550 switch (subcode) {
3551 case EFX_EF10_TEST:
3552 channel->event_test_cpu = raw_smp_processor_id();
3553 break;
3554 case EFX_EF10_REFILL:
3555 /* The queue must be empty, so we won't receive any rx
3556 * events, so efx_process_channel() won't refill the
3557 * queue. Refill it here
3558 */
cce28794 3559 efx_fast_push_rx_descriptors(&channel->rx_queue, true);
8127d661
BH		 3560 break;
3561 default:
3562 netif_err(efx, hw, efx->net_dev,
3563 "channel %d unknown driver event type %u"
3564 " (data " EFX_QWORD_FMT ")\n",
3565 channel->channel, (unsigned) subcode,
3566 EFX_QWORD_VAL(*event));
3567 }
3568}
3569
3570static int efx_ef10_ev_process(struct efx_channel *channel, int quota)
3571{
3572 struct efx_nic *efx = channel->efx;
3573 efx_qword_t event, *p_event;
3574 unsigned int read_ptr;
3575 int ev_code;
3576 int tx_descs = 0;
3577 int spent = 0;
3578
75363a46
EB		 3579 if (quota <= 0)
3580 return spent;
3581
8127d661
BH		 3582 read_ptr = channel->eventq_read_ptr;
3583
3584 for (;;) {
3585 p_event = efx_event(channel, read_ptr);
3586 event = *p_event;
3587
3588 if (!efx_event_present(&event))
3589 break;
3590
3591 EFX_SET_QWORD(*p_event);
3592
3593 ++read_ptr;
3594
3595 ev_code = EFX_QWORD_FIELD(event, ESF_DZ_EV_CODE);
3596
3597 netif_vdbg(efx, drv, efx->net_dev,
3598 "processing event on %d " EFX_QWORD_FMT "\n",
3599 channel->channel, EFX_QWORD_VAL(event));
3600
3601 switch (ev_code) {
3602 case ESE_DZ_EV_CODE_MCDI_EV:
3603 efx_mcdi_process_event(channel, &event);
3604 break;
3605 case ESE_DZ_EV_CODE_RX_EV:
3606 spent += efx_ef10_handle_rx_event(channel, &event);
3607 if (spent >= quota) {
3608 /* XXX can we split a merged event to
3609 * avoid going over-quota?
3610 */
3611 spent = quota;
3612 goto out;
3613 }
3614 break;
3615 case ESE_DZ_EV_CODE_TX_EV:
3616 tx_descs += efx_ef10_handle_tx_event(channel, &event);
3617 if (tx_descs > efx->txq_entries) {
3618 spent = quota;
3619 goto out;
3620 } else if (++spent == quota) {
3621 goto out;
3622 }
3623 break;
3624 case ESE_DZ_EV_CODE_DRIVER_EV:
3625 efx_ef10_handle_driver_event(channel, &event);
3626 if (++spent == quota)
3627 goto out;
3628 break;
3629 case EFX_EF10_DRVGEN_EV:
3630 efx_ef10_handle_driver_generated_event(channel, &event);
3631 break;
3632 default:
3633 netif_err(efx, hw, efx->net_dev,
3634 "channel %d unknown event type %d"
3635 " (data " EFX_QWORD_FMT ")\n",
3636 channel->channel, ev_code,
3637 EFX_QWORD_VAL(event));
3638 }
3639 }
3640
3641out:
3642 channel->eventq_read_ptr = read_ptr;
3643 return spent;
3644}
3645
3646static void efx_ef10_ev_read_ack(struct efx_channel *channel)
3647{
3648 struct efx_nic *efx = channel->efx;
3649 efx_dword_t rptr;
3650
3651 if (EFX_EF10_WORKAROUND_35388(efx)) {
3652 BUILD_BUG_ON(EFX_MIN_EVQ_SIZE <
3653 (1 << ERF_DD_EVQ_IND_RPTR_WIDTH));
3654 BUILD_BUG_ON(EFX_MAX_EVQ_SIZE >
3655 (1 << 2 * ERF_DD_EVQ_IND_RPTR_WIDTH));
3656
3657 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
3658 EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH,
3659 ERF_DD_EVQ_IND_RPTR,
3660 (channel->eventq_read_ptr &
3661 channel->eventq_mask) >>
3662 ERF_DD_EVQ_IND_RPTR_WIDTH);
3663 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
3664 channel->channel);
3665 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
3666 EFE_DD_EVQ_IND_RPTR_FLAGS_LOW,
3667 ERF_DD_EVQ_IND_RPTR,
3668 channel->eventq_read_ptr &
3669 ((1 << ERF_DD_EVQ_IND_RPTR_WIDTH) - 1));
3670 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
3671 channel->channel);
3672 } else {
3673 EFX_POPULATE_DWORD_1(rptr, ERF_DZ_EVQ_RPTR,
3674 channel->eventq_read_ptr &
3675 channel->eventq_mask);
3676 efx_writed_page(efx, &rptr, ER_DZ_EVQ_RPTR, channel->channel);
3677 }
3678}
3679
3680static void efx_ef10_ev_test_generate(struct efx_channel *channel)
3681{
3682 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
3683 struct efx_nic *efx = channel->efx;
3684 efx_qword_t event;
3685 int rc;
3686
3687 EFX_POPULATE_QWORD_2(event,
3688 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
3689 ESF_DZ_EV_DATA, EFX_EF10_TEST);
3690
3691 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
3692
3693 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
3694 * already swapped the data to little-endian order.
3695 */
3696 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
3697 sizeof(efx_qword_t));
3698
3699 rc = efx_mcdi_rpc(efx, MC_CMD_DRIVER_EVENT, inbuf, sizeof(inbuf),
3700 NULL, 0, NULL);
3701 if (rc != 0)
3702 goto fail;
3703
3704 return;
3705
3706fail:
3707 WARN_ON(true);
3708 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
3709}
3710
3711void efx_ef10_handle_drain_event(struct efx_nic *efx)
3712{
3713 if (atomic_dec_and_test(&efx->active_queues))
3714 wake_up(&efx->flush_wq);
3715
3716 WARN_ON(atomic_read(&efx->active_queues) < 0);
3717}
3718
3719static int efx_ef10_fini_dmaq(struct efx_nic *efx)
3720{
3721 struct efx_ef10_nic_data *nic_data = efx->nic_data;
3722 struct efx_channel *channel;
3723 struct efx_tx_queue *tx_queue;
3724 struct efx_rx_queue *rx_queue;
3725 int pending;
3726
3727 /* If the MC has just rebooted, the TX/RX queues will have already been
3728 * torn down, but efx->active_queues needs to be set to zero.
3729 */
3730 if (nic_data->must_realloc_vis) {
3731 atomic_set(&efx->active_queues, 0);
3732 return 0;
3733 }
3734
3735 /* Do not attempt to write to the NIC during EEH recovery */
3736 if (efx->state != STATE_RECOVERY) {
3737 efx_for_each_channel(channel, efx) {
3738 efx_for_each_channel_rx_queue(rx_queue, channel)
3739 efx_ef10_rx_fini(rx_queue);
3740 efx_for_each_channel_tx_queue(tx_queue, channel)
3741 efx_ef10_tx_fini(tx_queue);
3742 }
3743
3744 wait_event_timeout(efx->flush_wq,
3745 atomic_read(&efx->active_queues) == 0,
3746 msecs_to_jiffies(EFX_MAX_FLUSH_TIME));
3747 pending = atomic_read(&efx->active_queues);
3748 if (pending) {
3749 netif_err(efx, hw, efx->net_dev, "failed to flush %d queues\n",
3750 pending);
3751 return -ETIMEDOUT;
3752 }
3753 }
3754
3755 return 0;
3756}
3757
e283546c
EC		 3758static void efx_ef10_prepare_flr(struct efx_nic *efx)
3759{
3760 atomic_set(&efx->active_queues, 0);
3761}
3762
8127d661
BH		 3763static bool efx_ef10_filter_equal(const struct efx_filter_spec *left,
3764 const struct efx_filter_spec *right)
3765{
3766 if ((left->match_flags ^ right->match_flags) |
3767 ((left->flags ^ right->flags) &
3768 (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)))
3769 return false;
3770
3771 return memcmp(&left->outer_vid, &right->outer_vid,
3772 sizeof(struct efx_filter_spec) -
3773 offsetof(struct efx_filter_spec, outer_vid)) == 0;
3774}
3775
3776static unsigned int efx_ef10_filter_hash(const struct efx_filter_spec *spec)
3777{
3778 BUILD_BUG_ON(offsetof(struct efx_filter_spec, outer_vid) & 3);
3779 return jhash2((const u32 *)&spec->outer_vid,
3780 (sizeof(struct efx_filter_spec) -
3781 offsetof(struct efx_filter_spec, outer_vid)) / 4,
3782 0);
3783 /* XXX should we randomise the initval? */
3784}
3785
3786/* Decide whether a filter should be exclusive or else should allow
3787 * delivery to additional recipients. Currently we decide that
3788 * filters for specific local unicast MAC and IP addresses are
3789 * exclusive.
3790 */
3791static bool efx_ef10_filter_is_exclusive(const struct efx_filter_spec *spec)
3792{
3793 if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC &&
3794 !is_multicast_ether_addr(spec->loc_mac))
3795 return true;
3796
3797 if ((spec->match_flags &
3798 (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) ==
3799 (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) {
3800 if (spec->ether_type == htons(ETH_P_IP) &&
3801 !ipv4_is_multicast(spec->loc_host[0]))
3802 return true;
3803 if (spec->ether_type == htons(ETH_P_IPV6) &&
3804 ((const u8 *)spec->loc_host)[0] != 0xff)
3805 return true;
3806 }
3807
3808 return false;
3809}
3810
3811static struct efx_filter_spec *
3812efx_ef10_filter_entry_spec(const struct efx_ef10_filter_table *table,
3813 unsigned int filter_idx)
3814{
3815 return (struct efx_filter_spec *)(table->entry[filter_idx].spec &
3816 ~EFX_EF10_FILTER_FLAGS);
3817}
3818
3819static unsigned int
3820efx_ef10_filter_entry_flags(const struct efx_ef10_filter_table *table,
3821 unsigned int filter_idx)
3822{
3823 return table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAGS;
3824}
3825
3826static void
3827efx_ef10_filter_set_entry(struct efx_ef10_filter_table *table,
3828 unsigned int filter_idx,
3829 const struct efx_filter_spec *spec,
3830 unsigned int flags)
3831{
3832 table->entry[filter_idx].spec = (unsigned long)spec | flags;
3833}
3834
9b410801
EC		 3835static void
3836efx_ef10_filter_push_prep_set_match_fields(struct efx_nic *efx,
3837 const struct efx_filter_spec *spec,
3838 efx_dword_t *inbuf)
3839{
3840 enum efx_encap_type encap_type = efx_filter_get_encap_type(spec);
3841 u32 match_fields = 0, uc_match, mc_match;
3842
3843 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3844 efx_ef10_filter_is_exclusive(spec) ?
3845 MC_CMD_FILTER_OP_IN_OP_INSERT :
3846 MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE);
3847
3848 /* Convert match flags and values. Unlike almost
3849 * everything else in MCDI, these fields are in
3850 * network byte order.
3851 */
3852#define COPY_VALUE(value, mcdi_field) \
3853 do { \
3854 match_fields |= \
3855 1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \
3856 mcdi_field ## _LBN; \
3857 BUILD_BUG_ON( \
3858 MC_CMD_FILTER_OP_IN_ ## mcdi_field ## _LEN < \
3859 sizeof(value)); \
3860 memcpy(MCDI_PTR(inbuf, FILTER_OP_IN_ ## mcdi_field), \
3861 &value, sizeof(value)); \
3862 } while (0)
3863#define COPY_FIELD(gen_flag, gen_field, mcdi_field) \
3864 if (spec->match_flags & EFX_FILTER_MATCH_ ## gen_flag) { \
3865 COPY_VALUE(spec->gen_field, mcdi_field); \
3866 }
3867 /* Handle encap filters first. They will always be mismatch
3868 * (unknown UC or MC) filters
3869 */
3870 if (encap_type) {
3871 /* ether_type and outer_ip_proto need to be variables
3872 * because COPY_VALUE wants to memcpy them
3873 */
3874 __be16 ether_type =
3875 htons(encap_type & EFX_ENCAP_FLAG_IPV6 ?
3876 ETH_P_IPV6 : ETH_P_IP);
3877 u8 vni_type = MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_GENEVE;
3878 u8 outer_ip_proto;
3879
3880 switch (encap_type & EFX_ENCAP_TYPES_MASK) {
3881 case EFX_ENCAP_TYPE_VXLAN:
3882 vni_type = MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_VXLAN;
3883 /* fallthrough */
3884 case EFX_ENCAP_TYPE_GENEVE:
3885 COPY_VALUE(ether_type, ETHER_TYPE);
3886 outer_ip_proto = IPPROTO_UDP;
3887 COPY_VALUE(outer_ip_proto, IP_PROTO);
3888 /* We always need to set the type field, even
3889 * though we're not matching on the TNI.
3890 */
3891 MCDI_POPULATE_DWORD_1(inbuf,
3892 FILTER_OP_EXT_IN_VNI_OR_VSID,
3893 FILTER_OP_EXT_IN_VNI_TYPE,
3894 vni_type);
3895 break;
3896 case EFX_ENCAP_TYPE_NVGRE:
3897 COPY_VALUE(ether_type, ETHER_TYPE);
3898 outer_ip_proto = IPPROTO_GRE;
3899 COPY_VALUE(outer_ip_proto, IP_PROTO);
3900 break;
3901 default:
3902 WARN_ON(1);
3903 }
3904
3905 uc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_LBN;
3906 mc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_LBN;
3907 } else {
3908 uc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_LBN;
3909 mc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_LBN;
3910 }
3911
3912 if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC_IG)
3913 match_fields |=
3914 is_multicast_ether_addr(spec->loc_mac) ?
3915 1 << mc_match :
3916 1 << uc_match;
3917 COPY_FIELD(REM_HOST, rem_host, SRC_IP);
3918 COPY_FIELD(LOC_HOST, loc_host, DST_IP);
3919 COPY_FIELD(REM_MAC, rem_mac, SRC_MAC);
3920 COPY_FIELD(REM_PORT, rem_port, SRC_PORT);
3921 COPY_FIELD(LOC_MAC, loc_mac, DST_MAC);
3922 COPY_FIELD(LOC_PORT, loc_port, DST_PORT);
3923 COPY_FIELD(ETHER_TYPE, ether_type, ETHER_TYPE);
3924 COPY_FIELD(INNER_VID, inner_vid, INNER_VLAN);
3925 COPY_FIELD(OUTER_VID, outer_vid, OUTER_VLAN);
3926 COPY_FIELD(IP_PROTO, ip_proto, IP_PROTO);
3927#undef COPY_FIELD
3928#undef COPY_VALUE
3929 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_MATCH_FIELDS,
3930 match_fields);
3931}
3932
8127d661
BH		 3933static void efx_ef10_filter_push_prep(struct efx_nic *efx,
3934 const struct efx_filter_spec *spec,
3935 efx_dword_t *inbuf, u64 handle,
3936 bool replacing)
3937{
3938 struct efx_ef10_nic_data *nic_data = efx->nic_data;
dcb4123c 3939 u32 flags = spec->flags;
8127d661 3940
9b410801 3941 memset(inbuf, 0, MC_CMD_FILTER_OP_EXT_IN_LEN);
8127d661 3942
dcb4123c
JC		 3943 /* Remove RSS flag if we don't have an RSS context. */
3944 if (flags & EFX_FILTER_FLAG_RX_RSS &&
3945 spec->rss_context == EFX_FILTER_RSS_CONTEXT_DEFAULT &&
3946 nic_data->rx_rss_context == EFX_EF10_RSS_CONTEXT_INVALID)
3947 flags &= ~EFX_FILTER_FLAG_RX_RSS;
3948
8127d661
BH		 3949 if (replacing) {
3950 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3951 MC_CMD_FILTER_OP_IN_OP_REPLACE);
3952 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, handle);
3953 } else {
9b410801 3954 efx_ef10_filter_push_prep_set_match_fields(efx, spec, inbuf);
8127d661
BH		 3955 }
3956
45b2449e 3957 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_PORT_ID, nic_data->vport_id);
8127d661
BH		 3958 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_DEST,
3959 spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ?
3960 MC_CMD_FILTER_OP_IN_RX_DEST_DROP :
3961 MC_CMD_FILTER_OP_IN_RX_DEST_HOST);
e3d36293 3962 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DOMAIN, 0);
8127d661
BH		 3963 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DEST,
3964 MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT);
a0bc3487
BH		 3965 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_QUEUE,
3966 spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ?
3967 0 : spec->dmaq_id);
8127d661 3968 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_MODE,
dcb4123c 3969 (flags & EFX_FILTER_FLAG_RX_RSS) ?
8127d661
BH		 3970 MC_CMD_FILTER_OP_IN_RX_MODE_RSS :
3971 MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE);
dcb4123c 3972 if (flags & EFX_FILTER_FLAG_RX_RSS)
8127d661
BH		 3973 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_CONTEXT,
3974 spec->rss_context !=
3975 EFX_FILTER_RSS_CONTEXT_DEFAULT ?
3976 spec->rss_context : nic_data->rx_rss_context);
3977}
3978
3979static int efx_ef10_filter_push(struct efx_nic *efx,
3980 const struct efx_filter_spec *spec,
3981 u64 *handle, bool replacing)
3982{
9b410801
EC		 3983 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_EXT_IN_LEN);
3984 MCDI_DECLARE_BUF(outbuf, MC_CMD_FILTER_OP_EXT_OUT_LEN);
8127d661
BH		 3985 int rc;
3986
3987 efx_ef10_filter_push_prep(efx, spec, inbuf, *handle, replacing);
3988 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
3989 outbuf, sizeof(outbuf), NULL);
3990 if (rc == 0)
3991 *handle = MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE);
065e64c4
BH		 3992 if (rc == -ENOSPC)
3993 rc = -EBUSY; /* to match efx_farch_filter_insert() */
8127d661
BH		 3994 return rc;
3995}
3996
7ac0dd9d 3997static u32 efx_ef10_filter_mcdi_flags_from_spec(const struct efx_filter_spec *spec)
8127d661 3998{
9b410801 3999 enum efx_encap_type encap_type = efx_filter_get_encap_type(spec);
7ac0dd9d 4000 unsigned int match_flags = spec->match_flags;
9b410801 4001 unsigned int uc_match, mc_match;
7ac0dd9d
AR		 4002 u32 mcdi_flags = 0;
4003
9b410801
EC		 4004#define MAP_FILTER_TO_MCDI_FLAG(gen_flag, mcdi_field, encap) { \
4005 unsigned int old_match_flags = match_flags; \
7ac0dd9d
AR		 4006 match_flags &= ~EFX_FILTER_MATCH_ ## gen_flag; \
4007 if (match_flags != old_match_flags) \
4008 mcdi_flags |= \
9b410801
EC		 4009 (1 << ((encap) ? \
4010 MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_ ## \
4011 mcdi_field ## _LBN : \
4012 MC_CMD_FILTER_OP_EXT_IN_MATCH_ ##\
4013 mcdi_field ## _LBN)); \
7ac0dd9d 4014 }
9b410801
EC		 4015 /* inner or outer based on encap type */
4016 MAP_FILTER_TO_MCDI_FLAG(REM_HOST, SRC_IP, encap_type);
4017 MAP_FILTER_TO_MCDI_FLAG(LOC_HOST, DST_IP, encap_type);
4018 MAP_FILTER_TO_MCDI_FLAG(REM_MAC, SRC_MAC, encap_type);
4019 MAP_FILTER_TO_MCDI_FLAG(REM_PORT, SRC_PORT, encap_type);
4020 MAP_FILTER_TO_MCDI_FLAG(LOC_MAC, DST_MAC, encap_type);
4021 MAP_FILTER_TO_MCDI_FLAG(LOC_PORT, DST_PORT, encap_type);
4022 MAP_FILTER_TO_MCDI_FLAG(ETHER_TYPE, ETHER_TYPE, encap_type);
4023 MAP_FILTER_TO_MCDI_FLAG(IP_PROTO, IP_PROTO, encap_type);
4024 /* always outer */
4025 MAP_FILTER_TO_MCDI_FLAG(INNER_VID, INNER_VLAN, false);
4026 MAP_FILTER_TO_MCDI_FLAG(OUTER_VID, OUTER_VLAN, false);
7ac0dd9d
AR		 4027#undef MAP_FILTER_TO_MCDI_FLAG
4028
9b410801
EC		 4029 /* special handling for encap type, and mismatch */
4030 if (encap_type) {
4031 match_flags &= ~EFX_FILTER_MATCH_ENCAP_TYPE;
4032 mcdi_flags |=
4033 (1 << MC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_LBN);
4034 mcdi_flags |= (1 << MC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_LBN);
4035
4036 uc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_LBN;
4037 mc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_LBN;
4038 } else {
4039 uc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_LBN;
4040 mc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_LBN;
4041 }
4042
4043 if (match_flags & EFX_FILTER_MATCH_LOC_MAC_IG) {
4044 match_flags &= ~EFX_FILTER_MATCH_LOC_MAC_IG;
4045 mcdi_flags |=
4046 is_multicast_ether_addr(spec->loc_mac) ?
4047 1 << mc_match :
4048 1 << uc_match;
4049 }
4050
7ac0dd9d
AR		 4051 /* Did we map them all? */
4052 WARN_ON_ONCE(match_flags);
4053
4054 return mcdi_flags;
4055}
4056
4057static int efx_ef10_filter_pri(struct efx_ef10_filter_table *table,
4058 const struct efx_filter_spec *spec)
4059{
4060 u32 mcdi_flags = efx_ef10_filter_mcdi_flags_from_spec(spec);
8127d661
BH		 4061 unsigned int match_pri;
4062
4063 for (match_pri = 0;
4064 match_pri < table->rx_match_count;
4065 match_pri++)
7ac0dd9d 4066 if (table->rx_match_mcdi_flags[match_pri] == mcdi_flags)
8127d661
BH		 4067 return match_pri;
4068
4069 return -EPROTONOSUPPORT;
4070}
4071
4072static s32 efx_ef10_filter_insert(struct efx_nic *efx,
4073 struct efx_filter_spec *spec,
4074 bool replace_equal)
4075{
4076 struct efx_ef10_filter_table *table = efx->filter_state;
4077 DECLARE_BITMAP(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
4078 struct efx_filter_spec *saved_spec;
4079 unsigned int match_pri, hash;
4080 unsigned int priv_flags;
4081 bool replacing = false;
4082 int ins_index = -1;
4083 DEFINE_WAIT(wait);
4084 bool is_mc_recip;
4085 s32 rc;
4086
4087 /* For now, only support RX filters */
4088 if ((spec->flags & (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)) !=
4089 EFX_FILTER_FLAG_RX)
4090 return -EINVAL;
4091
7ac0dd9d 4092 rc = efx_ef10_filter_pri(table, spec);
8127d661
BH		 4093 if (rc < 0)
4094 return rc;
4095 match_pri = rc;
4096
4097 hash = efx_ef10_filter_hash(spec);
4098 is_mc_recip = efx_filter_is_mc_recipient(spec);
4099 if (is_mc_recip)
4100 bitmap_zero(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
4101
4102 /* Find any existing filters with the same match tuple or
4103 * else a free slot to insert at. If any of them are busy,
4104 * we have to wait and retry.
4105 */
4106 for (;;) {
4107 unsigned int depth = 1;
4108 unsigned int i;
4109
4110 spin_lock_bh(&efx->filter_lock);
4111
4112 for (;;) {
4113 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
4114 saved_spec = efx_ef10_filter_entry_spec(table, i);
4115
4116 if (!saved_spec) {
4117 if (ins_index < 0)
4118 ins_index = i;
4119 } else if (efx_ef10_filter_equal(spec, saved_spec)) {
4120 if (table->entry[i].spec &
4121 EFX_EF10_FILTER_FLAG_BUSY)
4122 break;
4123 if (spec->priority < saved_spec->priority &&
7665d1ab 4124 spec->priority != EFX_FILTER_PRI_AUTO) {
8127d661
BH		 4125 rc = -EPERM;
4126 goto out_unlock;
4127 }
4128 if (!is_mc_recip) {
4129 /* This is the only one */
4130 if (spec->priority ==
4131 saved_spec->priority &&
4132 !replace_equal) {
4133 rc = -EEXIST;
4134 goto out_unlock;
4135 }
4136 ins_index = i;
4137 goto found;
4138 } else if (spec->priority >
4139 saved_spec->priority ||
4140 (spec->priority ==
4141 saved_spec->priority &&
4142 replace_equal)) {
4143 if (ins_index < 0)
4144 ins_index = i;
4145 else
4146 __set_bit(depth, mc_rem_map);
4147 }
4148 }
4149
4150 /* Once we reach the maximum search depth, use
4151 * the first suitable slot or return -EBUSY if
4152 * there was none
4153 */
4154 if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) {
4155 if (ins_index < 0) {
4156 rc = -EBUSY;
4157 goto out_unlock;
4158 }
4159 goto found;
4160 }
4161
4162 ++depth;
4163 }
4164
4165 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE);
4166 spin_unlock_bh(&efx->filter_lock);
4167 schedule();
4168 }
4169
4170found:
4171 /* Create a software table entry if necessary, and mark it
4172 * busy. We might yet fail to insert, but any attempt to
4173 * insert a conflicting filter while we're waiting for the
4174 * firmware must find the busy entry.
4175 */
4176 saved_spec = efx_ef10_filter_entry_spec(table, ins_index);
4177 if (saved_spec) {
7665d1ab
BH		 4178 if (spec->priority == EFX_FILTER_PRI_AUTO &&
4179 saved_spec->priority >= EFX_FILTER_PRI_AUTO) {
8127d661 4180 /* Just make sure it won't be removed */
7665d1ab
BH		 4181 if (saved_spec->priority > EFX_FILTER_PRI_AUTO)
4182 saved_spec->flags |= EFX_FILTER_FLAG_RX_OVER_AUTO;
8127d661 4183 table->entry[ins_index].spec &=
b59e6ef8 4184 ~EFX_EF10_FILTER_FLAG_AUTO_OLD;
8127d661
BH		 4185 rc = ins_index;
4186 goto out_unlock;
4187 }
4188 replacing = true;
4189 priv_flags = efx_ef10_filter_entry_flags(table, ins_index);
4190 } else {
4191 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC);
4192 if (!saved_spec) {
4193 rc = -ENOMEM;
4194 goto out_unlock;
4195 }
4196 *saved_spec = *spec;
4197 priv_flags = 0;
4198 }
4199 efx_ef10_filter_set_entry(table, ins_index, saved_spec,
4200 priv_flags | EFX_EF10_FILTER_FLAG_BUSY);
4201
4202 /* Mark lower-priority multicast recipients busy prior to removal */
4203 if (is_mc_recip) {
4204 unsigned int depth, i;
4205
4206 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
4207 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
4208 if (test_bit(depth, mc_rem_map))
4209 table->entry[i].spec |=
4210 EFX_EF10_FILTER_FLAG_BUSY;
4211 }
4212 }
4213
4214 spin_unlock_bh(&efx->filter_lock);
4215
4216 rc = efx_ef10_filter_push(efx, spec, &table->entry[ins_index].handle,
4217 replacing);
4218
4219 /* Finalise the software table entry */
4220 spin_lock_bh(&efx->filter_lock);
4221 if (rc == 0) {
4222 if (replacing) {
4223 /* Update the fields that may differ */
7665d1ab
BH		 4224 if (saved_spec->priority == EFX_FILTER_PRI_AUTO)
4225 saved_spec->flags |=
4226 EFX_FILTER_FLAG_RX_OVER_AUTO;
8127d661 4227 saved_spec->priority = spec->priority;
7665d1ab 4228 saved_spec->flags &= EFX_FILTER_FLAG_RX_OVER_AUTO;
8127d661
BH		 4229 saved_spec->flags |= spec->flags;
4230 saved_spec->rss_context = spec->rss_context;
4231 saved_spec->dmaq_id = spec->dmaq_id;
4232 }
4233 } else if (!replacing) {
4234 kfree(saved_spec);
4235 saved_spec = NULL;
4236 }
4237 efx_ef10_filter_set_entry(table, ins_index, saved_spec, priv_flags);
4238
4239 /* Remove and finalise entries for lower-priority multicast
4240 * recipients
4241 */
4242 if (is_mc_recip) {
bb53f4d4 4243 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_EXT_IN_LEN);
8127d661
BH		 4244 unsigned int depth, i;
4245
4246 memset(inbuf, 0, sizeof(inbuf));
4247
4248 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
4249 if (!test_bit(depth, mc_rem_map))
4250 continue;
4251
4252 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
4253 saved_spec = efx_ef10_filter_entry_spec(table, i);
4254 priv_flags = efx_ef10_filter_entry_flags(table, i);
4255
4256 if (rc == 0) {
4257 spin_unlock_bh(&efx->filter_lock);
4258 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
4259 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
4260 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
4261 table->entry[i].handle);
4262 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP,
4263 inbuf, sizeof(inbuf),
4264 NULL, 0, NULL);
4265 spin_lock_bh(&efx->filter_lock);
4266 }
4267
4268 if (rc == 0) {
4269 kfree(saved_spec);
4270 saved_spec = NULL;
4271 priv_flags = 0;
4272 } else {
4273 priv_flags &= ~EFX_EF10_FILTER_FLAG_BUSY;
4274 }
4275 efx_ef10_filter_set_entry(table, i, saved_spec,
4276 priv_flags);
4277 }
4278 }
4279
4280 /* If successful, return the inserted filter ID */
4281 if (rc == 0)
0ccb998b 4282 rc = efx_ef10_make_filter_id(match_pri, ins_index);
8127d661
BH		 4283
4284 wake_up_all(&table->waitq);
4285out_unlock:
4286 spin_unlock_bh(&efx->filter_lock);
4287 finish_wait(&table->waitq, &wait);
4288 return rc;
4289}
4290
9fd8095d 4291static void efx_ef10_filter_update_rx_scatter(struct efx_nic *efx)
8127d661
BH		 4292{
4293 /* no need to do anything here on EF10 */
4294}
4295
4296/* Remove a filter.
b59e6ef8
BH		 4297 * If !by_index, remove by ID
4298 * If by_index, remove by index
8127d661
BH		 4299 * Filter ID may come from userland and must be range-checked.
4300 */
4301static int efx_ef10_filter_remove_internal(struct efx_nic *efx,
fbd79120 4302 unsigned int priority_mask,
b59e6ef8 4303 u32 filter_id, bool by_index)
8127d661 4304{
0ccb998b 4305 unsigned int filter_idx = efx_ef10_filter_get_unsafe_id(filter_id);
8127d661
BH		 4306 struct efx_ef10_filter_table *table = efx->filter_state;
4307 MCDI_DECLARE_BUF(inbuf,
4308 MC_CMD_FILTER_OP_IN_HANDLE_OFST +
4309 MC_CMD_FILTER_OP_IN_HANDLE_LEN);
4310 struct efx_filter_spec *spec;
4311 DEFINE_WAIT(wait);
4312 int rc;
4313
4314 /* Find the software table entry and mark it busy. Don't
4315 * remove it yet; any attempt to update while we're waiting
4316 * for the firmware must find the busy entry.
4317 */
4318 for (;;) {
4319 spin_lock_bh(&efx->filter_lock);
4320 if (!(table->entry[filter_idx].spec &
4321 EFX_EF10_FILTER_FLAG_BUSY))
4322 break;
4323 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE);
4324 spin_unlock_bh(&efx->filter_lock);
4325 schedule();
4326 }
7665d1ab 4327
8127d661 4328 spec = efx_ef10_filter_entry_spec(table, filter_idx);
7665d1ab 4329 if (!spec ||
b59e6ef8 4330 (!by_index &&
7ac0dd9d 4331 efx_ef10_filter_pri(table, spec) !=
0ccb998b 4332 efx_ef10_filter_get_unsafe_pri(filter_id))) {
8127d661
BH		 4333 rc = -ENOENT;
4334 goto out_unlock;
4335 }
7665d1ab
BH		 4336
4337 if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO &&
fbd79120 4338 priority_mask == (1U << EFX_FILTER_PRI_AUTO)) {
7665d1ab
BH		 4339 /* Just remove flags */
4340 spec->flags &= ~EFX_FILTER_FLAG_RX_OVER_AUTO;
b59e6ef8 4341 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_AUTO_OLD;
7665d1ab
BH		 4342 rc = 0;
4343 goto out_unlock;
4344 }
4345
fbd79120 4346 if (!(priority_mask & (1U << spec->priority))) {
7665d1ab
BH		 4347 rc = -ENOENT;
4348 goto out_unlock;
4349 }
4350
8127d661
BH		 4351 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
4352 spin_unlock_bh(&efx->filter_lock);
4353
7665d1ab 4354 if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO) {
b59e6ef8 4355 /* Reset to an automatic filter */
8127d661
BH		 4356
4357 struct efx_filter_spec new_spec = *spec;
4358
7665d1ab 4359 new_spec.priority = EFX_FILTER_PRI_AUTO;
8127d661 4360 new_spec.flags = (EFX_FILTER_FLAG_RX |
f1c2ef40
BK		 4361 (efx_rss_enabled(efx) ?
4362 EFX_FILTER_FLAG_RX_RSS : 0));
8127d661
BH		 4363 new_spec.dmaq_id = 0;
4364 new_spec.rss_context = EFX_FILTER_RSS_CONTEXT_DEFAULT;
4365 rc = efx_ef10_filter_push(efx, &new_spec,
4366 &table->entry[filter_idx].handle,
4367 true);
4368
4369 spin_lock_bh(&efx->filter_lock);
4370 if (rc == 0)
4371 *spec = new_spec;
4372 } else {
4373 /* Really remove the filter */
4374
4375 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
4376 efx_ef10_filter_is_exclusive(spec) ?
4377 MC_CMD_FILTER_OP_IN_OP_REMOVE :
4378 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
4379 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
4380 table->entry[filter_idx].handle);
105eac6c
BK		 4381 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FILTER_OP,
4382 inbuf, sizeof(inbuf), NULL, 0, NULL);
8127d661
BH		 4383
4384 spin_lock_bh(&efx->filter_lock);
105eac6c
BK		 4385 if ((rc == 0) || (rc == -ENOENT)) {
4386 /* Filter removed OK or didn't actually exist */
8127d661
BH		 4387 kfree(spec);
4388 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
105eac6c
BK		 4389 } else {
4390 efx_mcdi_display_error(efx, MC_CMD_FILTER_OP,
bb53f4d4 4391 MC_CMD_FILTER_OP_EXT_IN_LEN,
105eac6c 4392 NULL, 0, rc);
8127d661
BH		 4393 }
4394 }
7665d1ab 4395
8127d661
BH		 4396 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY;
4397 wake_up_all(&table->waitq);
4398out_unlock:
4399 spin_unlock_bh(&efx->filter_lock);
4400 finish_wait(&table->waitq, &wait);
4401 return rc;
4402}
4403
4404static int efx_ef10_filter_remove_safe(struct efx_nic *efx,
4405 enum efx_filter_priority priority,
4406 u32 filter_id)
4407{
fbd79120
BH		 4408 return efx_ef10_filter_remove_internal(efx, 1U << priority,
4409 filter_id, false);
8127d661
BH		 4410}
4411
8c915620
EC		 4412static void efx_ef10_filter_remove_unsafe(struct efx_nic *efx,
4413 enum efx_filter_priority priority,
4414 u32 filter_id)
12fb0da4 4415{
8c915620
EC		 4416 if (filter_id == EFX_EF10_FILTER_ID_INVALID)
4417 return;
4418 efx_ef10_filter_remove_internal(efx, 1U << priority, filter_id, true);
12fb0da4
EC		 4419}
4420
8127d661
BH		 4421static int efx_ef10_filter_get_safe(struct efx_nic *efx,
4422 enum efx_filter_priority priority,
4423 u32 filter_id, struct efx_filter_spec *spec)
4424{
0ccb998b 4425 unsigned int filter_idx = efx_ef10_filter_get_unsafe_id(filter_id);
8127d661
BH		 4426 struct efx_ef10_filter_table *table = efx->filter_state;
4427 const struct efx_filter_spec *saved_spec;
4428 int rc;
4429
4430 spin_lock_bh(&efx->filter_lock);
4431 saved_spec = efx_ef10_filter_entry_spec(table, filter_idx);
4432 if (saved_spec && saved_spec->priority == priority &&
7ac0dd9d 4433 efx_ef10_filter_pri(table, saved_spec) ==
0ccb998b 4434 efx_ef10_filter_get_unsafe_pri(filter_id)) {
8127d661
BH		 4435 *spec = *saved_spec;
4436 rc = 0;
4437 } else {
4438 rc = -ENOENT;
4439 }
4440 spin_unlock_bh(&efx->filter_lock);
4441 return rc;
4442}
4443
fbd79120 4444static int efx_ef10_filter_clear_rx(struct efx_nic *efx,
8127d661
BH		 4445 enum efx_filter_priority priority)
4446{
fbd79120
BH		 4447 unsigned int priority_mask;
4448 unsigned int i;
4449 int rc;
4450
4451 priority_mask = (((1U << (priority + 1)) - 1) &
4452 ~(1U << EFX_FILTER_PRI_AUTO));
4453
4454 for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) {
4455 rc = efx_ef10_filter_remove_internal(efx, priority_mask,
4456 i, true);
4457 if (rc && rc != -ENOENT)
4458 return rc;
4459 }
4460
4461 return 0;
8127d661
BH		 4462}
4463
4464static u32 efx_ef10_filter_count_rx_used(struct efx_nic *efx,
4465 enum efx_filter_priority priority)
4466{
4467 struct efx_ef10_filter_table *table = efx->filter_state;
4468 unsigned int filter_idx;
4469 s32 count = 0;
4470
4471 spin_lock_bh(&efx->filter_lock);
4472 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
4473 if (table->entry[filter_idx].spec &&
4474 efx_ef10_filter_entry_spec(table, filter_idx)->priority ==
4475 priority)
4476 ++count;
4477 }
4478 spin_unlock_bh(&efx->filter_lock);
4479 return count;
4480}
4481
4482static u32 efx_ef10_filter_get_rx_id_limit(struct efx_nic *efx)
4483{
4484 struct efx_ef10_filter_table *table = efx->filter_state;
4485
0ccb998b 4486 return table->rx_match_count * HUNT_FILTER_TBL_ROWS * 2;
8127d661
BH		 4487}
4488
4489static s32 efx_ef10_filter_get_rx_ids(struct efx_nic *efx,
4490 enum efx_filter_priority priority,
4491 u32 *buf, u32 size)
4492{
4493 struct efx_ef10_filter_table *table = efx->filter_state;
4494 struct efx_filter_spec *spec;
4495 unsigned int filter_idx;
4496 s32 count = 0;
4497
4498 spin_lock_bh(&efx->filter_lock);
4499 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
4500 spec = efx_ef10_filter_entry_spec(table, filter_idx);
4501 if (spec && spec->priority == priority) {
4502 if (count == size) {
4503 count = -EMSGSIZE;
4504 break;
4505 }
0ccb998b
JC		 4506 buf[count++] =
4507 efx_ef10_make_filter_id(
4508 efx_ef10_filter_pri(table, spec),
8127d661
BH		 4509 filter_idx);
4510 }
4511 }
4512 spin_unlock_bh(&efx->filter_lock);
4513 return count;
4514}
4515
4516#ifdef CONFIG_RFS_ACCEL
4517
4518static efx_mcdi_async_completer efx_ef10_filter_rfs_insert_complete;
4519
4520static s32 efx_ef10_filter_rfs_insert(struct efx_nic *efx,
4521 struct efx_filter_spec *spec)
4522{
4523 struct efx_ef10_filter_table *table = efx->filter_state;
bb53f4d4 4524 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_EXT_IN_LEN);
8127d661
BH		 4525 struct efx_filter_spec *saved_spec;
4526 unsigned int hash, i, depth = 1;
4527 bool replacing = false;
4528 int ins_index = -1;
4529 u64 cookie;
4530 s32 rc;
4531
4532 /* Must be an RX filter without RSS and not for a multicast
4533 * destination address (RFS only works for connected sockets).
4534 * These restrictions allow us to pass only a tiny amount of
4535 * data through to the completion function.
4536 */
4537 EFX_WARN_ON_PARANOID(spec->flags !=
4538 (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_RX_SCATTER));
4539 EFX_WARN_ON_PARANOID(spec->priority != EFX_FILTER_PRI_HINT);
4540 EFX_WARN_ON_PARANOID(efx_filter_is_mc_recipient(spec));
4541
4542 hash = efx_ef10_filter_hash(spec);
4543
4544 spin_lock_bh(&efx->filter_lock);
4545
4546 /* Find any existing filter with the same match tuple or else
4547 * a free slot to insert at. If an existing filter is busy,
4548 * we have to give up.
4549 */
4550 for (;;) {
4551 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
4552 saved_spec = efx_ef10_filter_entry_spec(table, i);
4553
4554 if (!saved_spec) {
4555 if (ins_index < 0)
4556 ins_index = i;
4557 } else if (efx_ef10_filter_equal(spec, saved_spec)) {
4558 if (table->entry[i].spec & EFX_EF10_FILTER_FLAG_BUSY) {
4559 rc = -EBUSY;
4560 goto fail_unlock;
4561 }
8127d661
BH		 4562 if (spec->priority < saved_spec->priority) {
4563 rc = -EPERM;
4564 goto fail_unlock;
4565 }
4566 ins_index = i;
4567 break;
4568 }
4569
4570 /* Once we reach the maximum search depth, use the
4571 * first suitable slot or return -EBUSY if there was
4572 * none
4573 */
4574 if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) {
4575 if (ins_index < 0) {
4576 rc = -EBUSY;
4577 goto fail_unlock;
4578 }
4579 break;
4580 }
4581
4582 ++depth;
4583 }
4584
4585 /* Create a software table entry if necessary, and mark it
4586 * busy. We might yet fail to insert, but any attempt to
4587 * insert a conflicting filter while we're waiting for the
4588 * firmware must find the busy entry.
4589 */
4590 saved_spec = efx_ef10_filter_entry_spec(table, ins_index);
4591 if (saved_spec) {
4592 replacing = true;
4593 } else {
4594 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC);
4595 if (!saved_spec) {
4596 rc = -ENOMEM;
4597 goto fail_unlock;
4598 }
4599 *saved_spec = *spec;
4600 }
4601 efx_ef10_filter_set_entry(table, ins_index, saved_spec,
4602 EFX_EF10_FILTER_FLAG_BUSY);
4603
4604 spin_unlock_bh(&efx->filter_lock);
4605
4606 /* Pack up the variables needed on completion */
4607 cookie = replacing << 31 | ins_index << 16 | spec->dmaq_id;
4608
4609 efx_ef10_filter_push_prep(efx, spec, inbuf,
4610 table->entry[ins_index].handle, replacing);
4611 efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
4612 MC_CMD_FILTER_OP_OUT_LEN,
4613 efx_ef10_filter_rfs_insert_complete, cookie);
4614
4615 return ins_index;
4616
4617fail_unlock:
4618 spin_unlock_bh(&efx->filter_lock);
4619 return rc;
4620}
4621
4622static void
4623efx_ef10_filter_rfs_insert_complete(struct efx_nic *efx, unsigned long cookie,
4624 int rc, efx_dword_t *outbuf,
4625 size_t outlen_actual)
4626{
4627 struct efx_ef10_filter_table *table = efx->filter_state;
4628 unsigned int ins_index, dmaq_id;
4629 struct efx_filter_spec *spec;
4630 bool replacing;
4631
4632 /* Unpack the cookie */
4633 replacing = cookie >> 31;
4634 ins_index = (cookie >> 16) & (HUNT_FILTER_TBL_ROWS - 1);
4635 dmaq_id = cookie & 0xffff;
4636
4637 spin_lock_bh(&efx->filter_lock);
4638 spec = efx_ef10_filter_entry_spec(table, ins_index);
4639 if (rc == 0) {
4640 table->entry[ins_index].handle =
4641 MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE);
4642 if (replacing)
4643 spec->dmaq_id = dmaq_id;
4644 } else if (!replacing) {
4645 kfree(spec);
4646 spec = NULL;
4647 }
4648 efx_ef10_filter_set_entry(table, ins_index, spec, 0);
4649 spin_unlock_bh(&efx->filter_lock);
4650
4651 wake_up_all(&table->waitq);
4652}
4653
4654static void
4655efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx,
4656 unsigned long filter_idx,
4657 int rc, efx_dword_t *outbuf,
4658 size_t outlen_actual);
4659
4660static bool efx_ef10_filter_rfs_expire_one(struct efx_nic *efx, u32 flow_id,
4661 unsigned int filter_idx)
4662{
4663 struct efx_ef10_filter_table *table = efx->filter_state;
4664 struct efx_filter_spec *spec =
4665 efx_ef10_filter_entry_spec(table, filter_idx);
4666 MCDI_DECLARE_BUF(inbuf,
4667 MC_CMD_FILTER_OP_IN_HANDLE_OFST +
4668 MC_CMD_FILTER_OP_IN_HANDLE_LEN);
4669
4670 if (!spec ||
4671 (table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAG_BUSY) ||
4672 spec->priority != EFX_FILTER_PRI_HINT ||
4673 !rps_may_expire_flow(efx->net_dev, spec->dmaq_id,
4674 flow_id, filter_idx))
4675 return false;
4676
4677 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
4678 MC_CMD_FILTER_OP_IN_OP_REMOVE);
4679 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
4680 table->entry[filter_idx].handle);
4681 if (efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf), 0,
4682 efx_ef10_filter_rfs_expire_complete, filter_idx))
4683 return false;
4684
4685 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
4686 return true;
4687}
4688
4689static void
4690efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx,
4691 unsigned long filter_idx,
4692 int rc, efx_dword_t *outbuf,
4693 size_t outlen_actual)
4694{
4695 struct efx_ef10_filter_table *table = efx->filter_state;
4696 struct efx_filter_spec *spec =
4697 efx_ef10_filter_entry_spec(table, filter_idx);
4698
4699 spin_lock_bh(&efx->filter_lock);
4700 if (rc == 0) {
4701 kfree(spec);
4702 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
4703 }
4704 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY;
4705 wake_up_all(&table->waitq);
4706 spin_unlock_bh(&efx->filter_lock);
4707}
4708
4709#endif /* CONFIG_RFS_ACCEL */
4710
9b410801 4711static int efx_ef10_filter_match_flags_from_mcdi(bool encap, u32 mcdi_flags)
8127d661
BH		 4712{
4713 int match_flags = 0;
4714
9b410801 4715#define MAP_FLAG(gen_flag, mcdi_field) do { \
8127d661 4716 u32 old_mcdi_flags = mcdi_flags; \
9b410801
EC		 4717 mcdi_flags &= ~(1 << MC_CMD_FILTER_OP_EXT_IN_MATCH_ ## \
4718 mcdi_field ## _LBN); \
8127d661
BH		 4719 if (mcdi_flags != old_mcdi_flags) \
4720 match_flags |= EFX_FILTER_MATCH_ ## gen_flag; \
9b410801
EC		 4721 } while (0)
4722
4723 if (encap) {
4724 /* encap filters must specify encap type */
4725 match_flags |= EFX_FILTER_MATCH_ENCAP_TYPE;
4726 /* and imply ethertype and ip proto */
4727 mcdi_flags &=
4728 ~(1 << MC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_LBN);
4729 mcdi_flags &=
4730 ~(1 << MC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_LBN);
4731 /* VLAN tags refer to the outer packet */
4732 MAP_FLAG(INNER_VID, INNER_VLAN);
4733 MAP_FLAG(OUTER_VID, OUTER_VLAN);
4734 /* everything else refers to the inner packet */
4735 MAP_FLAG(LOC_MAC_IG, IFRM_UNKNOWN_UCAST_DST);
4736 MAP_FLAG(LOC_MAC_IG, IFRM_UNKNOWN_MCAST_DST);
4737 MAP_FLAG(REM_HOST, IFRM_SRC_IP);
4738 MAP_FLAG(LOC_HOST, IFRM_DST_IP);
4739 MAP_FLAG(REM_MAC, IFRM_SRC_MAC);
4740 MAP_FLAG(REM_PORT, IFRM_SRC_PORT);
4741 MAP_FLAG(LOC_MAC, IFRM_DST_MAC);
4742 MAP_FLAG(LOC_PORT, IFRM_DST_PORT);
4743 MAP_FLAG(ETHER_TYPE, IFRM_ETHER_TYPE);
4744 MAP_FLAG(IP_PROTO, IFRM_IP_PROTO);
4745 } else {
4746 MAP_FLAG(LOC_MAC_IG, UNKNOWN_UCAST_DST);
4747 MAP_FLAG(LOC_MAC_IG, UNKNOWN_MCAST_DST);
4748 MAP_FLAG(REM_HOST, SRC_IP);
4749 MAP_FLAG(LOC_HOST, DST_IP);
4750 MAP_FLAG(REM_MAC, SRC_MAC);
4751 MAP_FLAG(REM_PORT, SRC_PORT);
4752 MAP_FLAG(LOC_MAC, DST_MAC);
4753 MAP_FLAG(LOC_PORT, DST_PORT);
4754 MAP_FLAG(ETHER_TYPE, ETHER_TYPE);
4755 MAP_FLAG(INNER_VID, INNER_VLAN);
4756 MAP_FLAG(OUTER_VID, OUTER_VLAN);
4757 MAP_FLAG(IP_PROTO, IP_PROTO);
8127d661 4758 }
8127d661
BH		 4759#undef MAP_FLAG
4760
4761 /* Did we map them all? */
4762 if (mcdi_flags)
4763 return -EINVAL;
4764
4765 return match_flags;
4766}
4767
34813fe2
AR		 4768static void efx_ef10_filter_cleanup_vlans(struct efx_nic *efx)
4769{
4770 struct efx_ef10_filter_table *table = efx->filter_state;
4771 struct efx_ef10_filter_vlan *vlan, *next_vlan;
4772
4773 /* See comment in efx_ef10_filter_table_remove() */
4774 if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
4775 return;
4776
4777 if (!table)
4778 return;
4779
4780 list_for_each_entry_safe(vlan, next_vlan, &table->vlan_list, list)
4781 efx_ef10_filter_del_vlan_internal(efx, vlan);
4782}
4783
7ac0dd9d 4784static bool efx_ef10_filter_match_supported(struct efx_ef10_filter_table *table,
9b410801 4785 bool encap,
7ac0dd9d
AR		 4786 enum efx_filter_match_flags match_flags)
4787{
4788 unsigned int match_pri;
4789 int mf;
4790
4791 for (match_pri = 0;
4792 match_pri < table->rx_match_count;
4793 match_pri++) {
9b410801 4794 mf = efx_ef10_filter_match_flags_from_mcdi(encap,
7ac0dd9d
AR		 4795 table->rx_match_mcdi_flags[match_pri]);
4796 if (mf == match_flags)
4797 return true;
4798 }
4799
4800 return false;
4801}
4802
9b410801
EC		 4803static int
4804efx_ef10_filter_table_probe_matches(struct efx_nic *efx,
4805 struct efx_ef10_filter_table *table,
4806 bool encap)
8127d661
BH		 4807{
4808 MCDI_DECLARE_BUF(inbuf, MC_CMD_GET_PARSER_DISP_INFO_IN_LEN);
4809 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX);
4810 unsigned int pd_match_pri, pd_match_count;
8127d661
BH		 4811 size_t outlen;
4812 int rc;
4813
8127d661
BH		 4814 /* Find out which RX filter types are supported, and their priorities */
4815 MCDI_SET_DWORD(inbuf, GET_PARSER_DISP_INFO_IN_OP,
9b410801
EC		 4816 encap ?
4817 MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_ENCAP_RX_MATCHES :
8127d661
BH		 4818 MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES);
4819 rc = efx_mcdi_rpc(efx, MC_CMD_GET_PARSER_DISP_INFO,
4820 inbuf, sizeof(inbuf), outbuf, sizeof(outbuf),
4821 &outlen);
4822 if (rc)
9b410801
EC		 4823 return rc;
4824
8127d661
BH		 4825 pd_match_count = MCDI_VAR_ARRAY_LEN(
4826 outlen, GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES);
8127d661
BH		 4827
4828 for (pd_match_pri = 0; pd_match_pri < pd_match_count; pd_match_pri++) {
4829 u32 mcdi_flags =
4830 MCDI_ARRAY_DWORD(
4831 outbuf,
4832 GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES,
4833 pd_match_pri);
9b410801 4834 rc = efx_ef10_filter_match_flags_from_mcdi(encap, mcdi_flags);
8127d661
BH		 4835 if (rc < 0) {
4836 netif_dbg(efx, probe, efx->net_dev,
4837 "%s: fw flags %#x pri %u not supported in driver\n",
4838 __func__, mcdi_flags, pd_match_pri);
4839 } else {
4840 netif_dbg(efx, probe, efx->net_dev,
4841 "%s: fw flags %#x pri %u supported as driver flags %#x pri %u\n",
4842 __func__, mcdi_flags, pd_match_pri,
4843 rc, table->rx_match_count);
7ac0dd9d
AR		 4844 table->rx_match_mcdi_flags[table->rx_match_count] = mcdi_flags;
4845 table->rx_match_count++;
8127d661
BH		 4846 }
4847 }
4848
9b410801
EC		 4849 return 0;
4850}
4851
4852static int efx_ef10_filter_table_probe(struct efx_nic *efx)
4853{
4854 struct efx_ef10_nic_data *nic_data = efx->nic_data;
4855 struct net_device *net_dev = efx->net_dev;
4856 struct efx_ef10_filter_table *table;
4857 struct efx_ef10_vlan *vlan;
4858 int rc;
4859
4860 if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
4861 return -EINVAL;
4862
4863 if (efx->filter_state) /* already probed */
4864 return 0;
4865
4866 table = kzalloc(sizeof(*table), GFP_KERNEL);
4867 if (!table)
4868 return -ENOMEM;
4869
4870 table->rx_match_count = 0;
4871 rc = efx_ef10_filter_table_probe_matches(efx, table, false);
4872 if (rc)
4873 goto fail;
4874 if (nic_data->datapath_caps &
4875 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN))
4876 rc = efx_ef10_filter_table_probe_matches(efx, table, true);
4877 if (rc)
4878 goto fail;
e4478ad1 4879 if ((efx_supported_features(efx) & NETIF_F_HW_VLAN_CTAG_FILTER) &&
9b410801 4880 !(efx_ef10_filter_match_supported(table, false,
e4478ad1 4881 (EFX_FILTER_MATCH_OUTER_VID | EFX_FILTER_MATCH_LOC_MAC)) &&
9b410801 4882 efx_ef10_filter_match_supported(table, false,
e4478ad1
MH		 4883 (EFX_FILTER_MATCH_OUTER_VID | EFX_FILTER_MATCH_LOC_MAC_IG)))) {
4884 netif_info(efx, probe, net_dev,
4885 "VLAN filters are not supported in this firmware variant\n");
4886 net_dev->features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
4887 efx->fixed_features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
4888 net_dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
4889 }
4890
8127d661
BH		 4891 table->entry = vzalloc(HUNT_FILTER_TBL_ROWS * sizeof(*table->entry));
4892 if (!table->entry) {
4893 rc = -ENOMEM;
4894 goto fail;
4895 }
4896
b071c3a2 4897 table->mc_promisc_last = false;
4a53ea8a
AR		 4898 table->vlan_filter =
4899 !!(efx->net_dev->features & NETIF_F_HW_VLAN_CTAG_FILTER);
34813fe2 4900 INIT_LIST_HEAD(&table->vlan_list);
12fb0da4 4901
8127d661
BH		 4902 efx->filter_state = table;
4903 init_waitqueue_head(&table->waitq);
34813fe2
AR		 4904
4905 list_for_each_entry(vlan, &nic_data->vlan_list, list) {
4906 rc = efx_ef10_filter_add_vlan(efx, vlan->vid);
4907 if (rc)
4908 goto fail_add_vlan;
4909 }
4910
8127d661
BH		 4911 return 0;
4912
34813fe2
AR		 4913fail_add_vlan:
4914 efx_ef10_filter_cleanup_vlans(efx);
4915 efx->filter_state = NULL;
8127d661
BH		 4916fail:
4917 kfree(table);
4918 return rc;
4919}
4920
0d322413
EC		 4921/* Caller must hold efx->filter_sem for read if race against
4922 * efx_ef10_filter_table_remove() is possible
4923 */
8127d661
BH		 4924static void efx_ef10_filter_table_restore(struct efx_nic *efx)
4925{
4926 struct efx_ef10_filter_table *table = efx->filter_state;
4927 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2d3d4ec0
JC		 4928 unsigned int invalid_filters = 0, failed = 0;
4929 struct efx_ef10_filter_vlan *vlan;
8127d661
BH		 4930 struct efx_filter_spec *spec;
4931 unsigned int filter_idx;
2d3d4ec0
JC		 4932 u32 mcdi_flags;
4933 int match_pri;
9b410801 4934 int rc, i;
8127d661 4935
0d322413
EC		 4936 WARN_ON(!rwsem_is_locked(&efx->filter_sem));
4937
8127d661
BH		 4938 if (!nic_data->must_restore_filters)
4939 return;
4940
0d322413
EC		 4941 if (!table)
4942 return;
4943
8127d661
BH		 4944 spin_lock_bh(&efx->filter_lock);
4945
4946 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
4947 spec = efx_ef10_filter_entry_spec(table, filter_idx);
4948 if (!spec)
4949 continue;
4950
2d3d4ec0
JC		 4951 mcdi_flags = efx_ef10_filter_mcdi_flags_from_spec(spec);
4952 match_pri = 0;
4953 while (match_pri < table->rx_match_count &&
4954 table->rx_match_mcdi_flags[match_pri] != mcdi_flags)
4955 ++match_pri;
4956 if (match_pri >= table->rx_match_count) {
4957 invalid_filters++;
4958 goto not_restored;
4959 }
4960 if (spec->rss_context != EFX_FILTER_RSS_CONTEXT_DEFAULT &&
4961 spec->rss_context != nic_data->rx_rss_context)
4962 netif_warn(efx, drv, efx->net_dev,
4963 "Warning: unable to restore a filter with specific RSS context.\n");
4964
8127d661
BH		 4965 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
4966 spin_unlock_bh(&efx->filter_lock);
4967
4968 rc = efx_ef10_filter_push(efx, spec,
4969 &table->entry[filter_idx].handle,
4970 false);
4971 if (rc)
2d3d4ec0 4972 failed++;
8127d661 4973 spin_lock_bh(&efx->filter_lock);
2d3d4ec0 4974
8127d661 4975 if (rc) {
2d3d4ec0 4976not_restored:
9b410801
EC		 4977 list_for_each_entry(vlan, &table->vlan_list, list)
4978 for (i = 0; i < EFX_EF10_NUM_DEFAULT_FILTERS; ++i)
4979 if (vlan->default_filters[i] == filter_idx)
4980 vlan->default_filters[i] =
4981 EFX_EF10_FILTER_ID_INVALID;
4982
8127d661
BH		 4983 kfree(spec);
4984 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
4985 } else {
4986 table->entry[filter_idx].spec &=
4987 ~EFX_EF10_FILTER_FLAG_BUSY;
4988 }
4989 }
4990
4991 spin_unlock_bh(&efx->filter_lock);
4992
2d3d4ec0
JC		 4993 /* This can happen validly if the MC's capabilities have changed, so
4994 * is not an error.
4995 */
4996 if (invalid_filters)
4997 netif_dbg(efx, drv, efx->net_dev,
4998 "Did not restore %u filters that are now unsupported.\n",
4999 invalid_filters);
5000
8127d661
BH		 5001 if (failed)
5002 netif_err(efx, hw, efx->net_dev,
2d3d4ec0 5003 "unable to restore %u filters\n", failed);
8127d661
BH		 5004 else
5005 nic_data->must_restore_filters = false;
5006}
5007
5008static void efx_ef10_filter_table_remove(struct efx_nic *efx)
5009{
5010 struct efx_ef10_filter_table *table = efx->filter_state;
bb53f4d4 5011 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_EXT_IN_LEN);
8127d661
BH		 5012 struct efx_filter_spec *spec;
5013 unsigned int filter_idx;
5014 int rc;
5015
34813fe2 5016 efx_ef10_filter_cleanup_vlans(efx);
0d322413 5017 efx->filter_state = NULL;
dd98708c
EC		 5018 /* If we were called without locking, then it's not safe to free
5019 * the table as others might be using it. So we just WARN, leak
5020 * the memory, and potentially get an inconsistent filter table
5021 * state.
5022 * This should never actually happen.
5023 */
5024 if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
5025 return;
5026
0d322413
EC		 5027 if (!table)
5028 return;
5029
8127d661
BH		 5030 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
5031 spec = efx_ef10_filter_entry_spec(table, filter_idx);
5032 if (!spec)
5033 continue;
5034
5035 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
5036 efx_ef10_filter_is_exclusive(spec) ?
5037 MC_CMD_FILTER_OP_IN_OP_REMOVE :
5038 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
5039 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
5040 table->entry[filter_idx].handle);
e65a5109
BK		 5041 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FILTER_OP, inbuf,
5042 sizeof(inbuf), NULL, 0, NULL);
48ce5634 5043 if (rc)
e65a5109
BK		 5044 netif_info(efx, drv, efx->net_dev,
5045 "%s: filter %04x remove failed\n",
5046 __func__, filter_idx);
8127d661
BH		 5047 kfree(spec);
5048 }
5049
5050 vfree(table->entry);
5051 kfree(table);
5052}
5053
6a37958b
AR		 5054static void efx_ef10_filter_mark_one_old(struct efx_nic *efx, uint16_t *id)
5055{
5056 struct efx_ef10_filter_table *table = efx->filter_state;
5057 unsigned int filter_idx;
5058
5059 if (*id != EFX_EF10_FILTER_ID_INVALID) {
0ccb998b 5060 filter_idx = efx_ef10_filter_get_unsafe_id(*id);
6a37958b
AR		 5061 if (!table->entry[filter_idx].spec)
5062 netif_dbg(efx, drv, efx->net_dev,
5063 "marked null spec old %04x:%04x\n", *id,
5064 filter_idx);
5065 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_AUTO_OLD;
5066 *id = EFX_EF10_FILTER_ID_INVALID;
e65a5109 5067 }
6a37958b
AR		 5068}
5069
b3a3c03c
AR		 5070/* Mark old per-VLAN filters that may need to be removed */
5071static void _efx_ef10_filter_vlan_mark_old(struct efx_nic *efx,
5072 struct efx_ef10_filter_vlan *vlan)
8127d661
BH		 5073{
5074 struct efx_ef10_filter_table *table = efx->filter_state;
6a37958b 5075 unsigned int i;
8127d661 5076
12fb0da4 5077 for (i = 0; i < table->dev_uc_count; i++)
dc3273e0 5078 efx_ef10_filter_mark_one_old(efx, &vlan->uc[i]);
12fb0da4 5079 for (i = 0; i < table->dev_mc_count; i++)
dc3273e0 5080 efx_ef10_filter_mark_one_old(efx, &vlan->mc[i]);
9b410801
EC		 5081 for (i = 0; i < EFX_EF10_NUM_DEFAULT_FILTERS; i++)
5082 efx_ef10_filter_mark_one_old(efx, &vlan->default_filters[i]);
b3a3c03c
AR		 5083}
5084
34813fe2
AR		 5085/* Mark old filters that may need to be removed.
5086 * Caller must hold efx->filter_sem for read if race against
5087 * efx_ef10_filter_table_remove() is possible
5088 */
b3a3c03c
AR		 5089static void efx_ef10_filter_mark_old(struct efx_nic *efx)
5090{
5091 struct efx_ef10_filter_table *table = efx->filter_state;
34813fe2 5092 struct efx_ef10_filter_vlan *vlan;
b3a3c03c
AR		 5093
5094 spin_lock_bh(&efx->filter_lock);
34813fe2
AR		 5095 list_for_each_entry(vlan, &table->vlan_list, list)
5096 _efx_ef10_filter_vlan_mark_old(efx, vlan);
8127d661 5097 spin_unlock_bh(&efx->filter_lock);
822b96f8
DP		 5098}
5099
afa4ce12 5100static void efx_ef10_filter_uc_addr_list(struct efx_nic *efx)
822b96f8
DP		 5101{
5102 struct efx_ef10_filter_table *table = efx->filter_state;
5103 struct net_device *net_dev = efx->net_dev;
5104 struct netdev_hw_addr *uc;
5105 unsigned int i;
8127d661 5106
afa4ce12 5107 table->uc_promisc = !!(net_dev->flags & IFF_PROMISC);
822b96f8
DP		 5108 ether_addr_copy(table->dev_uc_list[0].addr, net_dev->dev_addr);
5109 i = 1;
5110 netdev_for_each_uc_addr(uc, net_dev) {
12fb0da4 5111 if (i >= EFX_EF10_FILTER_DEV_UC_MAX) {
afa4ce12 5112 table->uc_promisc = true;
12fb0da4
EC		 5113 break;
5114 }
822b96f8
DP		 5115 ether_addr_copy(table->dev_uc_list[i].addr, uc->addr);
5116 i++;
5117 }
c70d6815
BK		 5118
5119 table->dev_uc_count = i;
822b96f8
DP		 5120}
5121
afa4ce12 5122static void efx_ef10_filter_mc_addr_list(struct efx_nic *efx)
822b96f8
DP		 5123{
5124 struct efx_ef10_filter_table *table = efx->filter_state;
5125 struct net_device *net_dev = efx->net_dev;
5126 struct netdev_hw_addr *mc;
c70d6815 5127 unsigned int i;
822b96f8 5128
148cbab6 5129 table->mc_overflow = false;
afa4ce12 5130 table->mc_promisc = !!(net_dev->flags & (IFF_PROMISC | IFF_ALLMULTI));
ab8b1f7c 5131
12fb0da4 5132 i = 0;
ab8b1f7c 5133 netdev_for_each_mc_addr(mc, net_dev) {
12fb0da4 5134 if (i >= EFX_EF10_FILTER_DEV_MC_MAX) {
afa4ce12 5135 table->mc_promisc = true;
148cbab6 5136 table->mc_overflow = true;
12fb0da4
EC		 5137 break;
5138 }
ab8b1f7c
DP		 5139 ether_addr_copy(table->dev_mc_list[i].addr, mc->addr);
5140 i++;
8127d661 5141 }
12fb0da4
EC		 5142
5143 table->dev_mc_count = i;
822b96f8 5144}
8127d661 5145
12fb0da4 5146static int efx_ef10_filter_insert_addr_list(struct efx_nic *efx,
b3a3c03c
AR		 5147 struct efx_ef10_filter_vlan *vlan,
5148 bool multicast, bool rollback)
822b96f8
DP		 5149{
5150 struct efx_ef10_filter_table *table = efx->filter_state;
5151 struct efx_ef10_dev_addr *addr_list;
f1c2ef40 5152 enum efx_filter_flags filter_flags;
822b96f8 5153 struct efx_filter_spec spec;
12fb0da4
EC		 5154 u8 baddr[ETH_ALEN];
5155 unsigned int i, j;
5156 int addr_count;
dc3273e0 5157 u16 *ids;
822b96f8
DP		 5158 int rc;
5159
5160 if (multicast) {
5161 addr_list = table->dev_mc_list;
12fb0da4 5162 addr_count = table->dev_mc_count;
dc3273e0 5163 ids = vlan->mc;
822b96f8
DP		 5164 } else {
5165 addr_list = table->dev_uc_list;
12fb0da4 5166 addr_count = table->dev_uc_count;
dc3273e0 5167 ids = vlan->uc;
8127d661
BH		 5168 }
5169
f1c2ef40
BK		 5170 filter_flags = efx_rss_enabled(efx) ? EFX_FILTER_FLAG_RX_RSS : 0;
5171
822b96f8 5172 /* Insert/renew filters */
12fb0da4 5173 for (i = 0; i < addr_count; i++) {
d58299a4 5174 EFX_WARN_ON_PARANOID(ids[i] != EFX_EF10_FILTER_ID_INVALID);
f1c2ef40 5175 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, 0);
b3a3c03c 5176 efx_filter_set_eth_local(&spec, vlan->vid, addr_list[i].addr);
b6f568e2
JC		 5177 rc = efx_ef10_filter_insert(efx, &spec, true);
5178 if (rc < 0) {
12fb0da4
EC		 5179 if (rollback) {
5180 netif_info(efx, drv, efx->net_dev,
5181 "efx_ef10_filter_insert failed rc=%d\n",
5182 rc);
5183 /* Fall back to promiscuous */
5184 for (j = 0; j < i; j++) {
12fb0da4
EC		 5185 efx_ef10_filter_remove_unsafe(
5186 efx, EFX_FILTER_PRI_AUTO,
dc3273e0
AR		 5187 ids[j]);
5188 ids[j] = EFX_EF10_FILTER_ID_INVALID;
12fb0da4
EC		 5189 }
5190 return rc;
5191 } else {
d58299a4 5192 /* keep invalid ID, and carry on */
822b96f8 5193 }
d58299a4
EC		 5194 } else {
5195 ids[i] = efx_ef10_filter_get_unsafe_id(rc);
8127d661
BH		 5196 }
5197 }
822b96f8 5198
12fb0da4
EC		 5199 if (multicast && rollback) {
5200 /* Also need an Ethernet broadcast filter */
9b410801
EC		 5201 EFX_WARN_ON_PARANOID(vlan->default_filters[EFX_EF10_BCAST] !=
5202 EFX_EF10_FILTER_ID_INVALID);
f1c2ef40 5203 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, 0);
12fb0da4 5204 eth_broadcast_addr(baddr);
b3a3c03c 5205 efx_filter_set_eth_local(&spec, vlan->vid, baddr);
8127d661 5206 rc = efx_ef10_filter_insert(efx, &spec, true);
12fb0da4 5207 if (rc < 0) {
822b96f8 5208 netif_warn(efx, drv, efx->net_dev,
12fb0da4
EC		 5209 "Broadcast filter insert failed rc=%d\n", rc);
5210 /* Fall back to promiscuous */
5211 for (j = 0; j < i; j++) {
12fb0da4
EC		 5212 efx_ef10_filter_remove_unsafe(
5213 efx, EFX_FILTER_PRI_AUTO,
dc3273e0
AR		 5214 ids[j]);
5215 ids[j] = EFX_EF10_FILTER_ID_INVALID;
12fb0da4
EC		 5216 }
5217 return rc;
5218 } else {
9b410801 5219 vlan->default_filters[EFX_EF10_BCAST] =
0ccb998b 5220 efx_ef10_filter_get_unsafe_id(rc);
12fb0da4 5221 }
8127d661 5222 }
12fb0da4
EC		 5223
5224 return 0;
5225}
5226
b3a3c03c
AR		 5227static int efx_ef10_filter_insert_def(struct efx_nic *efx,
5228 struct efx_ef10_filter_vlan *vlan,
9b410801 5229 enum efx_encap_type encap_type,
b3a3c03c 5230 bool multicast, bool rollback)
12fb0da4 5231{
12fb0da4 5232 struct efx_ef10_nic_data *nic_data = efx->nic_data;
f1c2ef40 5233 enum efx_filter_flags filter_flags;
12fb0da4
EC		 5234 struct efx_filter_spec spec;
5235 u8 baddr[ETH_ALEN];
5236 int rc;
9b410801 5237 u16 *id;
12fb0da4 5238
f1c2ef40
BK		 5239 filter_flags = efx_rss_enabled(efx) ? EFX_FILTER_FLAG_RX_RSS : 0;
5240
5241 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, 0);
12fb0da4
EC		 5242
5243 if (multicast)
5244 efx_filter_set_mc_def(&spec);
5245 else
5246 efx_filter_set_uc_def(&spec);
5247
9b410801
EC		 5248 if (encap_type) {
5249 if (nic_data->datapath_caps &
5250 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN))
5251 efx_filter_set_encap_type(&spec, encap_type);
5252 else
5253 /* don't insert encap filters on non-supporting
5254 * platforms. ID will be left as INVALID.
5255 */
5256 return 0;
5257 }
5258
b3a3c03c
AR		 5259 if (vlan->vid != EFX_FILTER_VID_UNSPEC)
5260 efx_filter_set_eth_local(&spec, vlan->vid, NULL);
5261
12fb0da4
EC		 5262 rc = efx_ef10_filter_insert(efx, &spec, true);
5263 if (rc < 0) {
9b410801
EC		 5264 const char *um = multicast ? "Multicast" : "Unicast";
5265 const char *encap_name = "";
5266 const char *encap_ipv = "";
5267
5268 if ((encap_type & EFX_ENCAP_TYPES_MASK) ==
5269 EFX_ENCAP_TYPE_VXLAN)
5270 encap_name = "VXLAN ";
5271 else if ((encap_type & EFX_ENCAP_TYPES_MASK) ==
5272 EFX_ENCAP_TYPE_NVGRE)
5273 encap_name = "NVGRE ";
5274 else if ((encap_type & EFX_ENCAP_TYPES_MASK) ==
5275 EFX_ENCAP_TYPE_GENEVE)
5276 encap_name = "GENEVE ";
5277 if (encap_type & EFX_ENCAP_FLAG_IPV6)
5278 encap_ipv = "IPv6 ";
5279 else if (encap_type)
5280 encap_ipv = "IPv4 ";
5281
5282 /* unprivileged functions can't insert mismatch filters
5283 * for encapsulated or unicast traffic, so downgrade
5284 * those warnings to debug.
5285 */
34e7aefb 5286 netif_cond_dbg(efx, drv, efx->net_dev,
9b410801
EC		 5287 rc == -EPERM && (encap_type || !multicast), warn,
5288 "%s%s%s mismatch filter insert failed rc=%d\n",
5289 encap_name, encap_ipv, um, rc);
12fb0da4 5290 } else if (multicast) {
9b410801
EC		 5291 /* mapping from encap types to default filter IDs (multicast) */
5292 static enum efx_ef10_default_filters map[] = {
5293 [EFX_ENCAP_TYPE_NONE] = EFX_EF10_MCDEF,
5294 [EFX_ENCAP_TYPE_VXLAN] = EFX_EF10_VXLAN4_MCDEF,
5295 [EFX_ENCAP_TYPE_NVGRE] = EFX_EF10_NVGRE4_MCDEF,
5296 [EFX_ENCAP_TYPE_GENEVE] = EFX_EF10_GENEVE4_MCDEF,
5297 [EFX_ENCAP_TYPE_VXLAN | EFX_ENCAP_FLAG_IPV6] =
5298 EFX_EF10_VXLAN6_MCDEF,
5299 [EFX_ENCAP_TYPE_NVGRE | EFX_ENCAP_FLAG_IPV6] =
5300 EFX_EF10_NVGRE6_MCDEF,
5301 [EFX_ENCAP_TYPE_GENEVE | EFX_ENCAP_FLAG_IPV6] =
5302 EFX_EF10_GENEVE6_MCDEF,
5303 };
5304
5305 /* quick bounds check (BCAST result impossible) */
5306 BUILD_BUG_ON(EFX_EF10_BCAST != 0);
e9904990 5307 if (encap_type >= ARRAY_SIZE(map) || map[encap_type] == 0) {
9b410801
EC		 5308 WARN_ON(1);
5309 return -EINVAL;
5310 }
5311 /* then follow map */
5312 id = &vlan->default_filters[map[encap_type]];
5313
5314 EFX_WARN_ON_PARANOID(*id != EFX_EF10_FILTER_ID_INVALID);
0ccb998b 5315 *id = efx_ef10_filter_get_unsafe_id(rc);
9b410801 5316 if (!nic_data->workaround_26807 && !encap_type) {
12fb0da4
EC		 5317 /* Also need an Ethernet broadcast filter */
5318 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
f1c2ef40 5319 filter_flags, 0);
12fb0da4 5320 eth_broadcast_addr(baddr);
b3a3c03c 5321 efx_filter_set_eth_local(&spec, vlan->vid, baddr);
12fb0da4
EC		 5322 rc = efx_ef10_filter_insert(efx, &spec, true);
5323 if (rc < 0) {
5324 netif_warn(efx, drv, efx->net_dev,
5325 "Broadcast filter insert failed rc=%d\n",
5326 rc);
5327 if (rollback) {
5328 /* Roll back the mc_def filter */
5329 efx_ef10_filter_remove_unsafe(
5330 efx, EFX_FILTER_PRI_AUTO,
9b410801
EC		 5331 *id);
5332 *id = EFX_EF10_FILTER_ID_INVALID;
12fb0da4
EC		 5333 return rc;
5334 }
5335 } else {
9b410801
EC		 5336 EFX_WARN_ON_PARANOID(
5337 vlan->default_filters[EFX_EF10_BCAST] !=
5338 EFX_EF10_FILTER_ID_INVALID);
5339 vlan->default_filters[EFX_EF10_BCAST] =
0ccb998b 5340 efx_ef10_filter_get_unsafe_id(rc);
12fb0da4
EC		 5341 }
5342 }
5343 rc = 0;
5344 } else {
9b410801
EC		 5345 /* mapping from encap types to default filter IDs (unicast) */
5346 static enum efx_ef10_default_filters map[] = {
5347 [EFX_ENCAP_TYPE_NONE] = EFX_EF10_UCDEF,
5348 [EFX_ENCAP_TYPE_VXLAN] = EFX_EF10_VXLAN4_UCDEF,
5349 [EFX_ENCAP_TYPE_NVGRE] = EFX_EF10_NVGRE4_UCDEF,
5350 [EFX_ENCAP_TYPE_GENEVE] = EFX_EF10_GENEVE4_UCDEF,
5351 [EFX_ENCAP_TYPE_VXLAN | EFX_ENCAP_FLAG_IPV6] =
5352 EFX_EF10_VXLAN6_UCDEF,
5353 [EFX_ENCAP_TYPE_NVGRE | EFX_ENCAP_FLAG_IPV6] =
5354 EFX_EF10_NVGRE6_UCDEF,
5355 [EFX_ENCAP_TYPE_GENEVE | EFX_ENCAP_FLAG_IPV6] =
5356 EFX_EF10_GENEVE6_UCDEF,
5357 };
5358
5359 /* quick bounds check (BCAST result impossible) */
5360 BUILD_BUG_ON(EFX_EF10_BCAST != 0);
ee467fba 5361 if (encap_type >= ARRAY_SIZE(map) || map[encap_type] == 0) {
9b410801
EC		 5362 WARN_ON(1);
5363 return -EINVAL;
5364 }
5365 /* then follow map */
5366 id = &vlan->default_filters[map[encap_type]];
5367 EFX_WARN_ON_PARANOID(*id != EFX_EF10_FILTER_ID_INVALID);
5368 *id = rc;
12fb0da4
EC		 5369 rc = 0;
5370 }
5371 return rc;
822b96f8
DP		 5372}
5373
5374/* Remove filters that weren't renewed. Since nothing else changes the AUTO_OLD
5375 * flag or removes these filters, we don't need to hold the filter_lock while
5376 * scanning for these filters.
5377 */
5378static void efx_ef10_filter_remove_old(struct efx_nic *efx)
5379{
5380 struct efx_ef10_filter_table *table = efx->filter_state;
e65a5109
BK		 5381 int remove_failed = 0;
5382 int remove_noent = 0;
5383 int rc;
822b96f8 5384 int i;
8127d661 5385
8127d661 5386 for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) {
6aa7de05 5387 if (READ_ONCE(table->entry[i].spec) &
b59e6ef8 5388 EFX_EF10_FILTER_FLAG_AUTO_OLD) {
e65a5109
BK		 5389 rc = efx_ef10_filter_remove_internal(efx,
5390 1U << EFX_FILTER_PRI_AUTO, i, true);
5391 if (rc == -ENOENT)
5392 remove_noent++;
5393 else if (rc)
5394 remove_failed++;
8127d661
BH		 5395 }
5396 }
e65a5109
BK		 5397
5398 if (remove_failed)
5399 netif_info(efx, drv, efx->net_dev,
5400 "%s: failed to remove %d filters\n",
5401 __func__, remove_failed);
5402 if (remove_noent)
5403 netif_info(efx, drv, efx->net_dev,
5404 "%s: failed to remove %d non-existent filters\n",
5405 __func__, remove_noent);
8127d661
BH		 5406}
5407
7a186f47
DP		 5408static int efx_ef10_vport_set_mac_address(struct efx_nic *efx)
5409{
5410 struct efx_ef10_nic_data *nic_data = efx->nic_data;
5411 u8 mac_old[ETH_ALEN];
5412 int rc, rc2;
5413
5414 /* Only reconfigure a PF-created vport */
5415 if (is_zero_ether_addr(nic_data->vport_mac))
5416 return 0;
5417
5418 efx_device_detach_sync(efx);
5419 efx_net_stop(efx->net_dev);
5420 down_write(&efx->filter_sem);
5421 efx_ef10_filter_table_remove(efx);
5422 up_write(&efx->filter_sem);
5423
5424 rc = efx_ef10_vadaptor_free(efx, nic_data->vport_id);
5425 if (rc)
5426 goto restore_filters;
5427
5428 ether_addr_copy(mac_old, nic_data->vport_mac);
5429 rc = efx_ef10_vport_del_mac(efx, nic_data->vport_id,
5430 nic_data->vport_mac);
5431 if (rc)
5432 goto restore_vadaptor;
5433
5434 rc = efx_ef10_vport_add_mac(efx, nic_data->vport_id,
5435 efx->net_dev->dev_addr);
5436 if (!rc) {
5437 ether_addr_copy(nic_data->vport_mac, efx->net_dev->dev_addr);
5438 } else {
5439 rc2 = efx_ef10_vport_add_mac(efx, nic_data->vport_id, mac_old);
5440 if (rc2) {
5441 /* Failed to add original MAC, so clear vport_mac */
5442 eth_zero_addr(nic_data->vport_mac);
5443 goto reset_nic;
5444 }
5445 }
5446
5447restore_vadaptor:
5448 rc2 = efx_ef10_vadaptor_alloc(efx, nic_data->vport_id);
5449 if (rc2)
5450 goto reset_nic;
5451restore_filters:
5452 down_write(&efx->filter_sem);
5453 rc2 = efx_ef10_filter_table_probe(efx);
5454 up_write(&efx->filter_sem);
5455 if (rc2)
5456 goto reset_nic;
5457
5458 rc2 = efx_net_open(efx->net_dev);
5459 if (rc2)
5460 goto reset_nic;
5461
9c568fd8 5462 efx_device_attach_if_not_resetting(efx);
7a186f47
DP		 5463
5464 return rc;
5465
5466reset_nic:
5467 netif_err(efx, drv, efx->net_dev,
5468 "Failed to restore when changing MAC address - scheduling reset\n");
5469 efx_schedule_reset(efx, RESET_TYPE_DATAPATH);
5470
5471 return rc ? rc : rc2;
5472}
5473
822b96f8
DP		 5474/* Caller must hold efx->filter_sem for read if race against
5475 * efx_ef10_filter_table_remove() is possible
5476 */
34813fe2
AR		 5477static void efx_ef10_filter_vlan_sync_rx_mode(struct efx_nic *efx,
5478 struct efx_ef10_filter_vlan *vlan)
822b96f8
DP		 5479{
5480 struct efx_ef10_filter_table *table = efx->filter_state;
ab8b1f7c 5481 struct efx_ef10_nic_data *nic_data = efx->nic_data;
b3a3c03c 5482
4a53ea8a
AR		 5483 /* Do not install unspecified VID if VLAN filtering is enabled.
5484 * Do not install all specified VIDs if VLAN filtering is disabled.
5485 */
5486 if ((vlan->vid == EFX_FILTER_VID_UNSPEC) == table->vlan_filter)
5487 return;
5488
12fb0da4 5489 /* Insert/renew unicast filters */
afa4ce12 5490 if (table->uc_promisc) {
9b410801
EC		 5491 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_NONE,
5492 false, false);
b3a3c03c 5493 efx_ef10_filter_insert_addr_list(efx, vlan, false, false);
12fb0da4
EC		 5494 } else {
5495 /* If any of the filters failed to insert, fall back to
5496 * promiscuous mode - add in the uc_def filter. But keep
5497 * our individual unicast filters.
5498 */
b3a3c03c 5499 if (efx_ef10_filter_insert_addr_list(efx, vlan, false, false))
9b410801
EC		 5500 efx_ef10_filter_insert_def(efx, vlan,
5501 EFX_ENCAP_TYPE_NONE,
5502 false, false);
12fb0da4 5503 }
9b410801
EC		 5504 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_VXLAN,
5505 false, false);
5506 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_VXLAN |
5507 EFX_ENCAP_FLAG_IPV6,
5508 false, false);
5509 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_NVGRE,
5510 false, false);
5511 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_NVGRE |
5512 EFX_ENCAP_FLAG_IPV6,
5513 false, false);
5514 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_GENEVE,
5515 false, false);
5516 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_GENEVE |
5517 EFX_ENCAP_FLAG_IPV6,
5518 false, false);
ab8b1f7c 5519
12fb0da4 5520 /* Insert/renew multicast filters */
ab8b1f7c
DP		 5521 /* If changing promiscuous state with cascaded multicast filters, remove
5522 * old filters first, so that packets are dropped rather than duplicated
5523 */
afa4ce12
AR		 5524 if (nic_data->workaround_26807 &&
5525 table->mc_promisc_last != table->mc_promisc)
ab8b1f7c 5526 efx_ef10_filter_remove_old(efx);
afa4ce12 5527 if (table->mc_promisc) {
12fb0da4
EC		 5528 if (nic_data->workaround_26807) {
5529 /* If we failed to insert promiscuous filters, rollback
5530 * and fall back to individual multicast filters
5531 */
9b410801
EC		 5532 if (efx_ef10_filter_insert_def(efx, vlan,
5533 EFX_ENCAP_TYPE_NONE,
5534 true, true)) {
12fb0da4
EC		 5535 /* Changing promisc state, so remove old filters */
5536 efx_ef10_filter_remove_old(efx);
b3a3c03c
AR		 5537 efx_ef10_filter_insert_addr_list(efx, vlan,
5538 true, false);
12fb0da4
EC		 5539 }
5540 } else {
5541 /* If we failed to insert promiscuous filters, don't
148cbab6
EC		 5542 * rollback. Regardless, also insert the mc_list,
5543 * unless it's incomplete due to overflow
12fb0da4 5544 */
9b410801
EC		 5545 efx_ef10_filter_insert_def(efx, vlan,
5546 EFX_ENCAP_TYPE_NONE,
5547 true, false);
148cbab6
EC		 5548 if (!table->mc_overflow)
5549 efx_ef10_filter_insert_addr_list(efx, vlan,
5550 true, false);
12fb0da4
EC		 5551 }
5552 } else {
5553 /* If any filters failed to insert, rollback and fall back to
5554 * promiscuous mode - mc_def filter and maybe broadcast. If
5555 * that fails, roll back again and insert as many of our
5556 * individual multicast filters as we can.
5557 */
b3a3c03c 5558 if (efx_ef10_filter_insert_addr_list(efx, vlan, true, true)) {
12fb0da4
EC		 5559 /* Changing promisc state, so remove old filters */
5560 if (nic_data->workaround_26807)
5561 efx_ef10_filter_remove_old(efx);
9b410801
EC		 5562 if (efx_ef10_filter_insert_def(efx, vlan,
5563 EFX_ENCAP_TYPE_NONE,
5564 true, true))
b3a3c03c
AR		 5565 efx_ef10_filter_insert_addr_list(efx, vlan,
5566 true, false);
12fb0da4
EC		 5567 }
5568 }
9b410801
EC		 5569 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_VXLAN,
5570 true, false);
5571 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_VXLAN |
5572 EFX_ENCAP_FLAG_IPV6,
5573 true, false);
5574 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_NVGRE,
5575 true, false);
5576 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_NVGRE |
5577 EFX_ENCAP_FLAG_IPV6,
5578 true, false);
5579 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_GENEVE,
5580 true, false);
5581 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_GENEVE |
5582 EFX_ENCAP_FLAG_IPV6,
5583 true, false);
34813fe2
AR		 5584}
5585
5586/* Caller must hold efx->filter_sem for read if race against
5587 * efx_ef10_filter_table_remove() is possible
5588 */
5589static void efx_ef10_filter_sync_rx_mode(struct efx_nic *efx)
5590{
5591 struct efx_ef10_filter_table *table = efx->filter_state;
5592 struct net_device *net_dev = efx->net_dev;
5593 struct efx_ef10_filter_vlan *vlan;
4a53ea8a 5594 bool vlan_filter;
34813fe2
AR		 5595
5596 if (!efx_dev_registered(efx))
5597 return;
5598
5599 if (!table)
5600 return;
5601
5602 efx_ef10_filter_mark_old(efx);
5603
5604 /* Copy/convert the address lists; add the primary station
5605 * address and broadcast address
5606 */
5607 netif_addr_lock_bh(net_dev);
5608 efx_ef10_filter_uc_addr_list(efx);
5609 efx_ef10_filter_mc_addr_list(efx);
5610 netif_addr_unlock_bh(net_dev);
5611
4a53ea8a
AR		 5612 /* If VLAN filtering changes, all old filters are finally removed.
5613 * Do it in advance to avoid conflicts for unicast untagged and
5614 * VLAN 0 tagged filters.
5615 */
5616 vlan_filter = !!(net_dev->features & NETIF_F_HW_VLAN_CTAG_FILTER);
5617 if (table->vlan_filter != vlan_filter) {
5618 table->vlan_filter = vlan_filter;
5619 efx_ef10_filter_remove_old(efx);
5620 }
5621
34813fe2
AR		 5622 list_for_each_entry(vlan, &table->vlan_list, list)
5623 efx_ef10_filter_vlan_sync_rx_mode(efx, vlan);
822b96f8
DP		 5624
5625 efx_ef10_filter_remove_old(efx);
afa4ce12 5626 table->mc_promisc_last = table->mc_promisc;
822b96f8
DP		 5627}
5628
34813fe2
AR		 5629static struct efx_ef10_filter_vlan *efx_ef10_filter_find_vlan(struct efx_nic *efx, u16 vid)
5630{
5631 struct efx_ef10_filter_table *table = efx->filter_state;
5632 struct efx_ef10_filter_vlan *vlan;
5633
5634 WARN_ON(!rwsem_is_locked(&efx->filter_sem));
5635
5636 list_for_each_entry(vlan, &table->vlan_list, list) {
5637 if (vlan->vid == vid)
5638 return vlan;
5639 }
5640
5641 return NULL;
5642}
5643
5644static int efx_ef10_filter_add_vlan(struct efx_nic *efx, u16 vid)
5645{
5646 struct efx_ef10_filter_table *table = efx->filter_state;
5647 struct efx_ef10_filter_vlan *vlan;
5648 unsigned int i;
5649
5650 if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
5651 return -EINVAL;
5652
5653 vlan = efx_ef10_filter_find_vlan(efx, vid);
5654 if (WARN_ON(vlan)) {
5655 netif_err(efx, drv, efx->net_dev,
5656 "VLAN %u already added\n", vid);
5657 return -EALREADY;
5658 }
5659
5660 vlan = kzalloc(sizeof(*vlan), GFP_KERNEL);
5661 if (!vlan)
5662 return -ENOMEM;
5663
5664 vlan->vid = vid;
5665
5666 for (i = 0; i < ARRAY_SIZE(vlan->uc); i++)
5667 vlan->uc[i] = EFX_EF10_FILTER_ID_INVALID;
5668 for (i = 0; i < ARRAY_SIZE(vlan->mc); i++)
5669 vlan->mc[i] = EFX_EF10_FILTER_ID_INVALID;
9b410801
EC		 5670 for (i = 0; i < EFX_EF10_NUM_DEFAULT_FILTERS; i++)
5671 vlan->default_filters[i] = EFX_EF10_FILTER_ID_INVALID;
34813fe2
AR		 5672
5673 list_add_tail(&vlan->list, &table->vlan_list);
5674
5675 if (efx_dev_registered(efx))
5676 efx_ef10_filter_vlan_sync_rx_mode(efx, vlan);
5677
5678 return 0;
5679}
5680
5681static void efx_ef10_filter_del_vlan_internal(struct efx_nic *efx,
5682 struct efx_ef10_filter_vlan *vlan)
5683{
5684 unsigned int i;
5685
5686 /* See comment in efx_ef10_filter_table_remove() */
5687 if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
5688 return;
5689
5690 list_del(&vlan->list);
5691
8c915620 5692 for (i = 0; i < ARRAY_SIZE(vlan->uc); i++)
34813fe2 5693 efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO,
8c915620
EC		 5694 vlan->uc[i]);
5695 for (i = 0; i < ARRAY_SIZE(vlan->mc); i++)
34813fe2 5696 efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO,
8c915620 5697 vlan->mc[i]);
9b410801
EC		 5698 for (i = 0; i < EFX_EF10_NUM_DEFAULT_FILTERS; i++)
5699 if (vlan->default_filters[i] != EFX_EF10_FILTER_ID_INVALID)
5700 efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO,
5701 vlan->default_filters[i]);
34813fe2
AR		 5702
5703 kfree(vlan);
5704}
5705
5706static void efx_ef10_filter_del_vlan(struct efx_nic *efx, u16 vid)
5707{
5708 struct efx_ef10_filter_vlan *vlan;
5709
5710 /* See comment in efx_ef10_filter_table_remove() */
5711 if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
5712 return;
5713
5714 vlan = efx_ef10_filter_find_vlan(efx, vid);
5715 if (!vlan) {
5716 netif_err(efx, drv, efx->net_dev,
5717 "VLAN %u not found in filter state\n", vid);
5718 return;
5719 }
5720
5721 efx_ef10_filter_del_vlan_internal(efx, vlan);
5722}
5723
910c8789
SS		 5724static int efx_ef10_set_mac_address(struct efx_nic *efx)
5725{
5726 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_SET_MAC_IN_LEN);
5727 struct efx_ef10_nic_data *nic_data = efx->nic_data;
5728 bool was_enabled = efx->port_enabled;
5729 int rc;
5730
5731 efx_device_detach_sync(efx);
5732 efx_net_stop(efx->net_dev);
d248953a
MH		 5733
5734 mutex_lock(&efx->mac_lock);
910c8789
SS		 5735 down_write(&efx->filter_sem);
5736 efx_ef10_filter_table_remove(efx);
5737
5738 ether_addr_copy(MCDI_PTR(inbuf, VADAPTOR_SET_MAC_IN_MACADDR),
5739 efx->net_dev->dev_addr);
5740 MCDI_SET_DWORD(inbuf, VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID,
5741 nic_data->vport_id);
535a6177
DP		 5742 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_VADAPTOR_SET_MAC, inbuf,
5743 sizeof(inbuf), NULL, 0, NULL);
910c8789
SS		 5744
5745 efx_ef10_filter_table_probe(efx);
5746 up_write(&efx->filter_sem);
d248953a
MH		 5747 mutex_unlock(&efx->mac_lock);
5748
910c8789
SS		 5749 if (was_enabled)
5750 efx_net_open(efx->net_dev);
9c568fd8 5751 efx_device_attach_if_not_resetting(efx);
910c8789 5752
9e9f665a
DP		 5753#ifdef CONFIG_SFC_SRIOV
5754 if (efx->pci_dev->is_virtfn && efx->pci_dev->physfn) {
910c8789
SS		 5755 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn;
5756
9e9f665a
DP		 5757 if (rc == -EPERM) {
5758 struct efx_nic *efx_pf;
910c8789 5759
9e9f665a
DP		 5760 /* Switch to PF and change MAC address on vport */
5761 efx_pf = pci_get_drvdata(pci_dev_pf);
910c8789 5762
9e9f665a
DP		 5763 rc = efx_ef10_sriov_set_vf_mac(efx_pf,
5764 nic_data->vf_index,
5765 efx->net_dev->dev_addr);
5766 } else if (!rc) {
910c8789
SS		 5767 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
5768 struct efx_ef10_nic_data *nic_data = efx_pf->nic_data;
5769 unsigned int i;
5770
9e9f665a
DP		 5771 /* MAC address successfully changed by VF (with MAC
5772 * spoofing) so update the parent PF if possible.
5773 */
910c8789
SS		 5774 for (i = 0; i < efx_pf->vf_count; ++i) {
5775 struct ef10_vf *vf = nic_data->vf + i;
5776
5777 if (vf->efx == efx) {
5778 ether_addr_copy(vf->mac,
5779 efx->net_dev->dev_addr);
5780 return 0;
5781 }
5782 }
5783 }
9e9f665a 5784 } else
910c8789 5785#endif
9e9f665a
DP		 5786 if (rc == -EPERM) {
5787 netif_err(efx, drv, efx->net_dev,
5788 "Cannot change MAC address; use sfboot to enable"
5789 " mac-spoofing on this interface\n");
7a186f47
DP		 5790 } else if (rc == -ENOSYS && !efx_ef10_is_vf(efx)) {
5791 /* If the active MCFW does not support MC_CMD_VADAPTOR_SET_MAC
5792 * fall-back to the method of changing the MAC address on the
5793 * vport. This only applies to PFs because such versions of
5794 * MCFW do not support VFs.
5795 */
5796 rc = efx_ef10_vport_set_mac_address(efx);
cbad52e9 5797 } else if (rc) {
535a6177
DP		 5798 efx_mcdi_display_error(efx, MC_CMD_VADAPTOR_SET_MAC,
5799 sizeof(inbuf), NULL, 0, rc);
9e9f665a
DP		 5800 }
5801
910c8789
SS		 5802 return rc;
5803}
5804
8127d661
BH		 5805static int efx_ef10_mac_reconfigure(struct efx_nic *efx)
5806{
5807 efx_ef10_filter_sync_rx_mode(efx);
5808
5809 return efx_mcdi_set_mac(efx);
5810}
5811
862f894c
SS		 5812static int efx_ef10_mac_reconfigure_vf(struct efx_nic *efx)
5813{
5814 efx_ef10_filter_sync_rx_mode(efx);
5815
5816 return 0;
5817}
5818
74cd60a4
JC		 5819static int efx_ef10_start_bist(struct efx_nic *efx, u32 bist_type)
5820{
5821 MCDI_DECLARE_BUF(inbuf, MC_CMD_START_BIST_IN_LEN);
5822
5823 MCDI_SET_DWORD(inbuf, START_BIST_IN_TYPE, bist_type);
5824 return efx_mcdi_rpc(efx, MC_CMD_START_BIST, inbuf, sizeof(inbuf),
5825 NULL, 0, NULL);
5826}
5827
5828/* MC BISTs follow a different poll mechanism to phy BISTs.
5829 * The BIST is done in the poll handler on the MC, and the MCDI command
5830 * will block until the BIST is done.
5831 */
5832static int efx_ef10_poll_bist(struct efx_nic *efx)
5833{
5834 int rc;
5835 MCDI_DECLARE_BUF(outbuf, MC_CMD_POLL_BIST_OUT_LEN);
5836 size_t outlen;
5837 u32 result;
5838
5839 rc = efx_mcdi_rpc(efx, MC_CMD_POLL_BIST, NULL, 0,
5840 outbuf, sizeof(outbuf), &outlen);
5841 if (rc != 0)
5842 return rc;
5843
5844 if (outlen < MC_CMD_POLL_BIST_OUT_LEN)
5845 return -EIO;
5846
5847 result = MCDI_DWORD(outbuf, POLL_BIST_OUT_RESULT);
5848 switch (result) {
5849 case MC_CMD_POLL_BIST_PASSED:
5850 netif_dbg(efx, hw, efx->net_dev, "BIST passed.\n");
5851 return 0;
5852 case MC_CMD_POLL_BIST_TIMEOUT:
5853 netif_err(efx, hw, efx->net_dev, "BIST timed out\n");
5854 return -EIO;
5855 case MC_CMD_POLL_BIST_FAILED:
5856 netif_err(efx, hw, efx->net_dev, "BIST failed.\n");
5857 return -EIO;
5858 default:
5859 netif_err(efx, hw, efx->net_dev,
5860 "BIST returned unknown result %u", result);
5861 return -EIO;
5862 }
5863}
5864
5865static int efx_ef10_run_bist(struct efx_nic *efx, u32 bist_type)
5866{
5867 int rc;
5868
5869 netif_dbg(efx, drv, efx->net_dev, "starting BIST type %u\n", bist_type);
5870
5871 rc = efx_ef10_start_bist(efx, bist_type);
5872 if (rc != 0)
5873 return rc;
5874
5875 return efx_ef10_poll_bist(efx);
5876}
5877
5878static int
5879efx_ef10_test_chip(struct efx_nic *efx, struct efx_self_tests *tests)
5880{
5881 int rc, rc2;
5882
5883 efx_reset_down(efx, RESET_TYPE_WORLD);
5884
5885 rc = efx_mcdi_rpc(efx, MC_CMD_ENABLE_OFFLINE_BIST,
5886 NULL, 0, NULL, 0, NULL);
5887 if (rc != 0)
5888 goto out;
5889
5890 tests->memory = efx_ef10_run_bist(efx, MC_CMD_MC_MEM_BIST) ? -1 : 1;
5891 tests->registers = efx_ef10_run_bist(efx, MC_CMD_REG_BIST) ? -1 : 1;
5892
5893 rc = efx_mcdi_reset(efx, RESET_TYPE_WORLD);
5894
5895out:
27324820
DP		 5896 if (rc == -EPERM)
5897 rc = 0;
74cd60a4
JC		 5898 rc2 = efx_reset_up(efx, RESET_TYPE_WORLD, rc == 0);
5899 return rc ? rc : rc2;
5900}
5901
8127d661
BH		 5902#ifdef CONFIG_SFC_MTD
5903
5904struct efx_ef10_nvram_type_info {
5905 u16 type, type_mask;
5906 u8 port;
5907 const char *name;
5908};
5909
5910static const struct efx_ef10_nvram_type_info efx_ef10_nvram_types[] = {
5911 { NVRAM_PARTITION_TYPE_MC_FIRMWARE, 0, 0, "sfc_mcfw" },
5912 { NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 0, 0, "sfc_mcfw_backup" },
5913 { NVRAM_PARTITION_TYPE_EXPANSION_ROM, 0, 0, "sfc_exp_rom" },
5914 { NVRAM_PARTITION_TYPE_STATIC_CONFIG, 0, 0, "sfc_static_cfg" },
5915 { NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG, 0, 0, "sfc_dynamic_cfg" },
5916 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0, 0, 0, "sfc_exp_rom_cfg" },
5917 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1, 0, 1, "sfc_exp_rom_cfg" },
5918 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2, 0, 2, "sfc_exp_rom_cfg" },
5919 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3, 0, 3, "sfc_exp_rom_cfg" },
a84f3bf9 5920 { NVRAM_PARTITION_TYPE_LICENSE, 0, 0, "sfc_license" },
8127d661
BH		 5921 { NVRAM_PARTITION_TYPE_PHY_MIN, 0xff, 0, "sfc_phy_fw" },
5922};
5923
5924static int efx_ef10_mtd_probe_partition(struct efx_nic *efx,
5925 struct efx_mcdi_mtd_partition *part,
5926 unsigned int type)
5927{
5928 MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_METADATA_IN_LEN);
5929 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_METADATA_OUT_LENMAX);
5930 const struct efx_ef10_nvram_type_info *info;
5931 size_t size, erase_size, outlen;
5932 bool protected;
5933 int rc;
5934
5935 for (info = efx_ef10_nvram_types; ; info++) {
5936 if (info ==
5937 efx_ef10_nvram_types + ARRAY_SIZE(efx_ef10_nvram_types))
5938 return -ENODEV;
5939 if ((type & ~info->type_mask) == info->type)
5940 break;
5941 }
5942 if (info->port != efx_port_num(efx))
5943 return -ENODEV;
5944
5945 rc = efx_mcdi_nvram_info(efx, type, &size, &erase_size, &protected);
5946 if (rc)
5947 return rc;
5948 if (protected)
5949 return -ENODEV; /* hide it */
5950
5951 part->nvram_type = type;
5952
5953 MCDI_SET_DWORD(inbuf, NVRAM_METADATA_IN_TYPE, type);
5954 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_METADATA, inbuf, sizeof(inbuf),
5955 outbuf, sizeof(outbuf), &outlen);
5956 if (rc)
5957 return rc;
5958 if (outlen < MC_CMD_NVRAM_METADATA_OUT_LENMIN)
5959 return -EIO;
5960 if (MCDI_DWORD(outbuf, NVRAM_METADATA_OUT_FLAGS) &
5961 (1 << MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN))
5962 part->fw_subtype = MCDI_DWORD(outbuf,
5963 NVRAM_METADATA_OUT_SUBTYPE);
5964
5965 part->common.dev_type_name = "EF10 NVRAM manager";
5966 part->common.type_name = info->name;
5967
5968 part->common.mtd.type = MTD_NORFLASH;
5969 part->common.mtd.flags = MTD_CAP_NORFLASH;
5970 part->common.mtd.size = size;
5971 part->common.mtd.erasesize = erase_size;
5972
5973 return 0;
5974}
5975
5976static int efx_ef10_mtd_probe(struct efx_nic *efx)
5977{
5978 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX);
5979 struct efx_mcdi_mtd_partition *parts;
5980 size_t outlen, n_parts_total, i, n_parts;
5981 unsigned int type;
5982 int rc;
5983
5984 ASSERT_RTNL();
5985
5986 BUILD_BUG_ON(MC_CMD_NVRAM_PARTITIONS_IN_LEN != 0);
5987 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_PARTITIONS, NULL, 0,
5988 outbuf, sizeof(outbuf), &outlen);
5989 if (rc)
5990 return rc;
5991 if (outlen < MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN)
5992 return -EIO;
5993
5994 n_parts_total = MCDI_DWORD(outbuf, NVRAM_PARTITIONS_OUT_NUM_PARTITIONS);
5995 if (n_parts_total >
5996 MCDI_VAR_ARRAY_LEN(outlen, NVRAM_PARTITIONS_OUT_TYPE_ID))
5997 return -EIO;
5998
5999 parts = kcalloc(n_parts_total, sizeof(*parts), GFP_KERNEL);
6000 if (!parts)
6001 return -ENOMEM;
6002
6003 n_parts = 0;
6004 for (i = 0; i < n_parts_total; i++) {
6005 type = MCDI_ARRAY_DWORD(outbuf, NVRAM_PARTITIONS_OUT_TYPE_ID,
6006 i);
6007 rc = efx_ef10_mtd_probe_partition(efx, &parts[n_parts], type);
6008 if (rc == 0)
6009 n_parts++;
6010 else if (rc != -ENODEV)
6011 goto fail;
6012 }
6013
6014 rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts));
6015fail:
6016 if (rc)
6017 kfree(parts);
6018 return rc;
6019}
6020
6021#endif /* CONFIG_SFC_MTD */
6022
6023static void efx_ef10_ptp_write_host_time(struct efx_nic *efx, u32 host_time)
6024{
6025 _efx_writed(efx, cpu_to_le32(host_time), ER_DZ_MC_DB_LWRD);
6026}
6027
02246a7f
SS		 6028static void efx_ef10_ptp_write_host_time_vf(struct efx_nic *efx,
6029 u32 host_time) {}
6030
bd9a265d
JC		 6031static int efx_ef10_rx_enable_timestamping(struct efx_channel *channel,
6032 bool temp)
6033{
6034 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN);
6035 int rc;
6036
6037 if (channel->sync_events_state == SYNC_EVENTS_REQUESTED ||
6038 channel->sync_events_state == SYNC_EVENTS_VALID ||
6039 (temp && channel->sync_events_state == SYNC_EVENTS_DISABLED))
6040 return 0;
6041 channel->sync_events_state = SYNC_EVENTS_REQUESTED;
6042
6043 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE);
6044 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
6045 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE,
6046 channel->channel);
6047
6048 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
6049 inbuf, sizeof(inbuf), NULL, 0, NULL);
6050
6051 if (rc != 0)
6052 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
6053 SYNC_EVENTS_DISABLED;
6054
6055 return rc;
6056}
6057
6058static int efx_ef10_rx_disable_timestamping(struct efx_channel *channel,
6059 bool temp)
6060{
6061 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN);
6062 int rc;
6063
6064 if (channel->sync_events_state == SYNC_EVENTS_DISABLED ||
6065 (temp && channel->sync_events_state == SYNC_EVENTS_QUIESCENT))
6066 return 0;
6067 if (channel->sync_events_state == SYNC_EVENTS_QUIESCENT) {
6068 channel->sync_events_state = SYNC_EVENTS_DISABLED;
6069 return 0;
6070 }
6071 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
6072 SYNC_EVENTS_DISABLED;
6073
6074 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE);
6075 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
6076 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL,
6077 MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE);
6078 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE,
6079 channel->channel);
6080
6081 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
6082 inbuf, sizeof(inbuf), NULL, 0, NULL);
6083
6084 return rc;
6085}
6086
6087static int efx_ef10_ptp_set_ts_sync_events(struct efx_nic *efx, bool en,
6088 bool temp)
6089{
6090 int (*set)(struct efx_channel *channel, bool temp);
6091 struct efx_channel *channel;
6092
6093 set = en ?
6094 efx_ef10_rx_enable_timestamping :
6095 efx_ef10_rx_disable_timestamping;
6096
6097 efx_for_each_channel(channel, efx) {
6098 int rc = set(channel, temp);
6099 if (en && rc != 0) {
6100 efx_ef10_ptp_set_ts_sync_events(efx, false, temp);
6101 return rc;
6102 }
6103 }
6104
6105 return 0;
6106}
6107
02246a7f
SS		 6108static int efx_ef10_ptp_set_ts_config_vf(struct efx_nic *efx,
6109 struct hwtstamp_config *init)
6110{
6111 return -EOPNOTSUPP;
6112}
6113
bd9a265d
JC		 6114static int efx_ef10_ptp_set_ts_config(struct efx_nic *efx,
6115 struct hwtstamp_config *init)
6116{
6117 int rc;
6118
6119 switch (init->rx_filter) {
6120 case HWTSTAMP_FILTER_NONE:
6121 efx_ef10_ptp_set_ts_sync_events(efx, false, false);
6122 /* if TX timestamping is still requested then leave PTP on */
6123 return efx_ptp_change_mode(efx,
6124 init->tx_type != HWTSTAMP_TX_OFF, 0);
6125 case HWTSTAMP_FILTER_ALL:
6126 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
6127 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
6128 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
6129 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
6130 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
6131 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
6132 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
6133 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
6134 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
6135 case HWTSTAMP_FILTER_PTP_V2_EVENT:
6136 case HWTSTAMP_FILTER_PTP_V2_SYNC:
6137 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
e3412575 6138 case HWTSTAMP_FILTER_NTP_ALL:
bd9a265d
JC		 6139 init->rx_filter = HWTSTAMP_FILTER_ALL;
6140 rc = efx_ptp_change_mode(efx, true, 0);
6141 if (!rc)
6142 rc = efx_ef10_ptp_set_ts_sync_events(efx, true, false);
6143 if (rc)
6144 efx_ptp_change_mode(efx, false, 0);
6145 return rc;
6146 default:
6147 return -ERANGE;
6148 }
6149}
6150
08a7b29b
BK		 6151static int efx_ef10_get_phys_port_id(struct efx_nic *efx,
6152 struct netdev_phys_item_id *ppid)
6153{
6154 struct efx_ef10_nic_data *nic_data = efx->nic_data;
6155
6156 if (!is_valid_ether_addr(nic_data->port_id))
6157 return -EOPNOTSUPP;
6158
6159 ppid->id_len = ETH_ALEN;
6160 memcpy(ppid->id, nic_data->port_id, ppid->id_len);
6161
6162 return 0;
6163}
6164
4a53ea8a
AR		 6165static int efx_ef10_vlan_rx_add_vid(struct efx_nic *efx, __be16 proto, u16 vid)
6166{
6167 if (proto != htons(ETH_P_8021Q))
6168 return -EINVAL;
6169
6170 return efx_ef10_add_vlan(efx, vid);
6171}
6172
6173static int efx_ef10_vlan_rx_kill_vid(struct efx_nic *efx, __be16 proto, u16 vid)
6174{
6175 if (proto != htons(ETH_P_8021Q))
6176 return -EINVAL;
6177
6178 return efx_ef10_del_vlan(efx, vid);
6179}
6180
e5fbd977
JC		 6181/* We rely on the MCDI wiping out our TX rings if it made any changes to the
6182 * ports table, ensuring that any TSO descriptors that were made on a now-
6183 * removed tunnel port will be blown away and won't break things when we try
6184 * to transmit them using the new ports table.
6185 */
6186static int efx_ef10_set_udp_tnl_ports(struct efx_nic *efx, bool unloading)
6187{
6188 struct efx_ef10_nic_data *nic_data = efx->nic_data;
6189 MCDI_DECLARE_BUF(inbuf, MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LENMAX);
6190 MCDI_DECLARE_BUF(outbuf, MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_LEN);
6191 bool will_reset = false;
6192 size_t num_entries = 0;
6193 size_t inlen, outlen;
6194 size_t i;
6195 int rc;
6196 efx_dword_t flags_and_num_entries;
6197
6198 WARN_ON(!mutex_is_locked(&nic_data->udp_tunnels_lock));
6199
6200 nic_data->udp_tunnels_dirty = false;
6201
6202 if (!(nic_data->datapath_caps &
6203 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN))) {
9c568fd8 6204 efx_device_attach_if_not_resetting(efx);
e5fbd977
JC		 6205 return 0;
6206 }
6207
6208 BUILD_BUG_ON(ARRAY_SIZE(nic_data->udp_tunnels) >
6209 MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MAXNUM);
6210
6211 for (i = 0; i < ARRAY_SIZE(nic_data->udp_tunnels); ++i) {
6212 if (nic_data->udp_tunnels[i].count &&
6213 nic_data->udp_tunnels[i].port) {
6214 efx_dword_t entry;
6215
6216 EFX_POPULATE_DWORD_2(entry,
6217 TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT,
6218 ntohs(nic_data->udp_tunnels[i].port),
6219 TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL,
6220 nic_data->udp_tunnels[i].type);
6221 *_MCDI_ARRAY_DWORD(inbuf,
6222 SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES,
6223 num_entries++) = entry;
6224 }
6225 }
6226
6227 BUILD_BUG_ON((MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_NUM_ENTRIES_OFST -
6228 MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS_OFST) * 8 !=
6229 EFX_WORD_1_LBN);
6230 BUILD_BUG_ON(MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_NUM_ENTRIES_LEN * 8 !=
6231 EFX_WORD_1_WIDTH);
6232 EFX_POPULATE_DWORD_2(flags_and_num_entries,
6233 MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_UNLOADING,
6234 !!unloading,
6235 EFX_WORD_1, num_entries);
6236 *_MCDI_DWORD(inbuf, SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS) =
6237 flags_and_num_entries;
6238
6239 inlen = MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LEN(num_entries);
6240
6241 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS,
6242 inbuf, inlen, outbuf, sizeof(outbuf), &outlen);
6243 if (rc == -EIO) {
6244 /* Most likely the MC rebooted due to another function also
6245 * setting its tunnel port list. Mark the tunnel port list as
6246 * dirty, so it will be pushed upon coming up from the reboot.
6247 */
6248 nic_data->udp_tunnels_dirty = true;
6249 return 0;
6250 }
6251
6252 if (rc) {
6253 /* expected not available on unprivileged functions */
6254 if (rc != -EPERM)
6255 netif_warn(efx, drv, efx->net_dev,
6256 "Unable to set UDP tunnel ports; rc=%d.\n", rc);
6257 } else if (MCDI_DWORD(outbuf, SET_TUNNEL_ENCAP_UDP_PORTS_OUT_FLAGS) &
6258 (1 << MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_RESETTING_LBN)) {
6259 netif_info(efx, drv, efx->net_dev,
6260 "Rebooting MC due to UDP tunnel port list change\n");
6261 will_reset = true;
6262 if (unloading)
6263 /* Delay for the MC reset to complete. This will make
6264 * unloading other functions a bit smoother. This is a
6265 * race, but the other unload will work whichever way
6266 * it goes, this just avoids an unnecessary error
6267 * message.
6268 */
6269 msleep(100);
6270 }
6271 if (!will_reset && !unloading) {
6272 /* The caller will have detached, relying on the MC reset to
6273 * trigger a re-attach. Since there won't be an MC reset, we
6274 * have to do the attach ourselves.
6275 */
9c568fd8 6276 efx_device_attach_if_not_resetting(efx);
e5fbd977
JC		 6277 }
6278
6279 return rc;
6280}
6281
6282static int efx_ef10_udp_tnl_push_ports(struct efx_nic *efx)
6283{
6284 struct efx_ef10_nic_data *nic_data = efx->nic_data;
6285 int rc = 0;
6286
6287 mutex_lock(&nic_data->udp_tunnels_lock);
6288 if (nic_data->udp_tunnels_dirty) {
6289 /* Make sure all TX are stopped while we modify the table, else
6290 * we might race against an efx_features_check().
6291 */
6292 efx_device_detach_sync(efx);
6293 rc = efx_ef10_set_udp_tnl_ports(efx, false);
6294 }
6295 mutex_unlock(&nic_data->udp_tunnels_lock);
6296 return rc;
6297}
6298
6299static struct efx_udp_tunnel *__efx_ef10_udp_tnl_lookup_port(struct efx_nic *efx,
6300 __be16 port)
6301{
6302 struct efx_ef10_nic_data *nic_data = efx->nic_data;
6303 size_t i;
6304
6305 for (i = 0; i < ARRAY_SIZE(nic_data->udp_tunnels); ++i) {
6306 if (!nic_data->udp_tunnels[i].count)
6307 continue;
6308 if (nic_data->udp_tunnels[i].port == port)
6309 return &nic_data->udp_tunnels[i];
6310 }
6311 return NULL;
6312}
6313
6314static int efx_ef10_udp_tnl_add_port(struct efx_nic *efx,
6315 struct efx_udp_tunnel tnl)
6316{
6317 struct efx_ef10_nic_data *nic_data = efx->nic_data;
6318 struct efx_udp_tunnel *match;
6319 char typebuf[8];
6320 size_t i;
6321 int rc;
6322
6323 if (!(nic_data->datapath_caps &
6324 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN)))
6325 return 0;
6326
6327 efx_get_udp_tunnel_type_name(tnl.type, typebuf, sizeof(typebuf));
6328 netif_dbg(efx, drv, efx->net_dev, "Adding UDP tunnel (%s) port %d\n",
6329 typebuf, ntohs(tnl.port));
6330
6331 mutex_lock(&nic_data->udp_tunnels_lock);
6332 /* Make sure all TX are stopped while we add to the table, else we
6333 * might race against an efx_features_check().
6334 */
6335 efx_device_detach_sync(efx);
6336
6337 match = __efx_ef10_udp_tnl_lookup_port(efx, tnl.port);
6338 if (match != NULL) {
6339 if (match->type == tnl.type) {
6340 netif_dbg(efx, drv, efx->net_dev,
6341 "Referencing existing tunnel entry\n");
6342 match->count++;
6343 /* No need to cause an MCDI update */
6344 rc = 0;
6345 goto unlock_out;
6346 }
6347 efx_get_udp_tunnel_type_name(match->type,
6348 typebuf, sizeof(typebuf));
6349 netif_dbg(efx, drv, efx->net_dev,
6350 "UDP port %d is already in use by %s\n",
6351 ntohs(tnl.port), typebuf);
6352 rc = -EEXIST;
6353 goto unlock_out;
6354 }
6355
6356 for (i = 0; i < ARRAY_SIZE(nic_data->udp_tunnels); ++i)
6357 if (!nic_data->udp_tunnels[i].count) {
6358 nic_data->udp_tunnels[i] = tnl;
6359 nic_data->udp_tunnels[i].count = 1;
6360 rc = efx_ef10_set_udp_tnl_ports(efx, false);
6361 goto unlock_out;
6362 }
6363
6364 netif_dbg(efx, drv, efx->net_dev,
6365 "Unable to add UDP tunnel (%s) port %d; insufficient resources.\n",
6366 typebuf, ntohs(tnl.port));
6367
6368 rc = -ENOMEM;
6369
6370unlock_out:
6371 mutex_unlock(&nic_data->udp_tunnels_lock);
6372 return rc;
6373}
6374
6375/* Called under the TX lock with the TX queue running, hence no-one can be
6376 * in the middle of updating the UDP tunnels table. However, they could
6377 * have tried and failed the MCDI, in which case they'll have set the dirty
6378 * flag before dropping their locks.
6379 */
6380static bool efx_ef10_udp_tnl_has_port(struct efx_nic *efx, __be16 port)
6381{
6382 struct efx_ef10_nic_data *nic_data = efx->nic_data;
6383
6384 if (!(nic_data->datapath_caps &
6385 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN)))
6386 return false;
6387
6388 if (nic_data->udp_tunnels_dirty)
6389 /* SW table may not match HW state, so just assume we can't
6390 * use any UDP tunnel offloads.
6391 */
6392 return false;
6393
6394 return __efx_ef10_udp_tnl_lookup_port(efx, port) != NULL;
6395}
6396
6397static int efx_ef10_udp_tnl_del_port(struct efx_nic *efx,
6398 struct efx_udp_tunnel tnl)
6399{
6400 struct efx_ef10_nic_data *nic_data = efx->nic_data;
6401 struct efx_udp_tunnel *match;
6402 char typebuf[8];
6403 int rc;
6404
6405 if (!(nic_data->datapath_caps &
6406 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN)))
6407 return 0;
6408
6409 efx_get_udp_tunnel_type_name(tnl.type, typebuf, sizeof(typebuf));
6410 netif_dbg(efx, drv, efx->net_dev, "Removing UDP tunnel (%s) port %d\n",
6411 typebuf, ntohs(tnl.port));
6412
6413 mutex_lock(&nic_data->udp_tunnels_lock);
6414 /* Make sure all TX are stopped while we remove from the table, else we
6415 * might race against an efx_features_check().
6416 */
6417 efx_device_detach_sync(efx);
6418
6419 match = __efx_ef10_udp_tnl_lookup_port(efx, tnl.port);
6420 if (match != NULL) {
6421 if (match->type == tnl.type) {
6422 if (--match->count) {
6423 /* Port is still in use, so nothing to do */
6424 netif_dbg(efx, drv, efx->net_dev,
6425 "UDP tunnel port %d remains active\n",
6426 ntohs(tnl.port));
6427 rc = 0;
6428 goto out_unlock;
6429 }
6430 rc = efx_ef10_set_udp_tnl_ports(efx, false);
6431 goto out_unlock;
6432 }
6433 efx_get_udp_tunnel_type_name(match->type,
6434 typebuf, sizeof(typebuf));
6435 netif_warn(efx, drv, efx->net_dev,
6436 "UDP port %d is actually in use by %s, not removing\n",
6437 ntohs(tnl.port), typebuf);
6438 }
6439 rc = -ENOENT;
6440
6441out_unlock:
6442 mutex_unlock(&nic_data->udp_tunnels_lock);
6443 return rc;
6444}
6445
100a9db5
AR		 6446#define EF10_OFFLOAD_FEATURES \
6447 (NETIF_F_IP_CSUM | \
4a53ea8a 6448 NETIF_F_HW_VLAN_CTAG_FILTER | \
100a9db5
AR		 6449 NETIF_F_IPV6_CSUM | \
6450 NETIF_F_RXHASH | \
6451 NETIF_F_NTUPLE)
6452
02246a7f 6453const struct efx_nic_type efx_hunt_a0_vf_nic_type = {
6f7f8aa6 6454 .is_vf = true,
03714bbb 6455 .mem_bar = efx_ef10_vf_mem_bar,
02246a7f
SS		 6456 .mem_map_size = efx_ef10_mem_map_size,
6457 .probe = efx_ef10_probe_vf,
6458 .remove = efx_ef10_remove,
6459 .dimension_resources = efx_ef10_dimension_resources,
6460 .init = efx_ef10_init_nic,
6461 .fini = efx_port_dummy_op_void,
087e9025 6462 .map_reset_reason = efx_ef10_map_reset_reason,
02246a7f
SS		 6463 .map_reset_flags = efx_ef10_map_reset_flags,
6464 .reset = efx_ef10_reset,
6465 .probe_port = efx_mcdi_port_probe,
6466 .remove_port = efx_mcdi_port_remove,
6467 .fini_dmaq = efx_ef10_fini_dmaq,
6468 .prepare_flr = efx_ef10_prepare_flr,
6469 .finish_flr = efx_port_dummy_op_void,
6470 .describe_stats = efx_ef10_describe_stats,
d7788196 6471 .update_stats = efx_ef10_update_stats_vf,
02246a7f
SS		 6472 .start_stats = efx_port_dummy_op_void,
6473 .pull_stats = efx_port_dummy_op_void,
6474 .stop_stats = efx_port_dummy_op_void,
6475 .set_id_led = efx_mcdi_set_id_led,
6476 .push_irq_moderation = efx_ef10_push_irq_moderation,
862f894c 6477 .reconfigure_mac = efx_ef10_mac_reconfigure_vf,
02246a7f
SS		 6478 .check_mac_fault = efx_mcdi_mac_check_fault,
6479 .reconfigure_port = efx_mcdi_port_reconfigure,
6480 .get_wol = efx_ef10_get_wol_vf,
6481 .set_wol = efx_ef10_set_wol_vf,
6482 .resume_wol = efx_port_dummy_op_void,
6483 .mcdi_request = efx_ef10_mcdi_request,
6484 .mcdi_poll_response = efx_ef10_mcdi_poll_response,
6485 .mcdi_read_response = efx_ef10_mcdi_read_response,
6486 .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot,
c577e59e 6487 .mcdi_reboot_detected = efx_ef10_mcdi_reboot_detected,
02246a7f
SS		 6488 .irq_enable_master = efx_port_dummy_op_void,
6489 .irq_test_generate = efx_ef10_irq_test_generate,
6490 .irq_disable_non_ev = efx_port_dummy_op_void,
6491 .irq_handle_msi = efx_ef10_msi_interrupt,
6492 .irq_handle_legacy = efx_ef10_legacy_interrupt,
6493 .tx_probe = efx_ef10_tx_probe,
6494 .tx_init = efx_ef10_tx_init,
6495 .tx_remove = efx_ef10_tx_remove,
6496 .tx_write = efx_ef10_tx_write,
e9117e50 6497 .tx_limit_len = efx_ef10_tx_limit_len,
267c0157 6498 .rx_push_rss_config = efx_ef10_vf_rx_push_rss_config,
a707d188 6499 .rx_pull_rss_config = efx_ef10_rx_pull_rss_config,
02246a7f
SS		 6500 .rx_probe = efx_ef10_rx_probe,
6501 .rx_init = efx_ef10_rx_init,
6502 .rx_remove = efx_ef10_rx_remove,
6503 .rx_write = efx_ef10_rx_write,
6504 .rx_defer_refill = efx_ef10_rx_defer_refill,
6505 .ev_probe = efx_ef10_ev_probe,
6506 .ev_init = efx_ef10_ev_init,
6507 .ev_fini = efx_ef10_ev_fini,
6508 .ev_remove = efx_ef10_ev_remove,
6509 .ev_process = efx_ef10_ev_process,
6510 .ev_read_ack = efx_ef10_ev_read_ack,
6511 .ev_test_generate = efx_ef10_ev_test_generate,
6512 .filter_table_probe = efx_ef10_filter_table_probe,
6513 .filter_table_restore = efx_ef10_filter_table_restore,
6514 .filter_table_remove = efx_ef10_filter_table_remove,
6515 .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter,
6516 .filter_insert = efx_ef10_filter_insert,
6517 .filter_remove_safe = efx_ef10_filter_remove_safe,
6518 .filter_get_safe = efx_ef10_filter_get_safe,
6519 .filter_clear_rx = efx_ef10_filter_clear_rx,
6520 .filter_count_rx_used = efx_ef10_filter_count_rx_used,
6521 .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit,
6522 .filter_get_rx_ids = efx_ef10_filter_get_rx_ids,
6523#ifdef CONFIG_RFS_ACCEL
6524 .filter_rfs_insert = efx_ef10_filter_rfs_insert,
6525 .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one,
6526#endif
6527#ifdef CONFIG_SFC_MTD
6528 .mtd_probe = efx_port_dummy_op_int,
6529#endif
6530 .ptp_write_host_time = efx_ef10_ptp_write_host_time_vf,
6531 .ptp_set_ts_config = efx_ef10_ptp_set_ts_config_vf,
4a53ea8a
AR		 6532 .vlan_rx_add_vid = efx_ef10_vlan_rx_add_vid,
6533 .vlan_rx_kill_vid = efx_ef10_vlan_rx_kill_vid,
02246a7f 6534#ifdef CONFIG_SFC_SRIOV
7b8c7b54
SS		 6535 .vswitching_probe = efx_ef10_vswitching_probe_vf,
6536 .vswitching_restore = efx_ef10_vswitching_restore_vf,
6537 .vswitching_remove = efx_ef10_vswitching_remove_vf,
02246a7f 6538#endif
0d5e0fbb 6539 .get_mac_address = efx_ef10_get_mac_address_vf,
910c8789 6540 .set_mac_address = efx_ef10_set_mac_address,
0d5e0fbb 6541
08a7b29b 6542 .get_phys_port_id = efx_ef10_get_phys_port_id,
02246a7f
SS		 6543 .revision = EFX_REV_HUNT_A0,
6544 .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH),
6545 .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE,
6546 .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST,
6547 .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST,
6548 .can_rx_scatter = true,
6549 .always_rx_scatter = true,
6f9f6ec2 6550 .min_interrupt_mode = EFX_INT_MODE_MSIX,
02246a7f
SS		 6551 .max_interrupt_mode = EFX_INT_MODE_MSIX,
6552 .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH,
100a9db5 6553 .offload_features = EF10_OFFLOAD_FEATURES,
02246a7f
SS		 6554 .mcdi_max_ver = 2,
6555 .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS,
6556 .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE |
6557 1 << HWTSTAMP_FILTER_ALL,
f74d1995 6558 .rx_hash_key_size = 40,
02246a7f
SS		 6559};
6560
8127d661 6561const struct efx_nic_type efx_hunt_a0_nic_type = {
6f7f8aa6 6562 .is_vf = false,
03714bbb 6563 .mem_bar = efx_ef10_pf_mem_bar,
8127d661 6564 .mem_map_size = efx_ef10_mem_map_size,
02246a7f 6565 .probe = efx_ef10_probe_pf,
8127d661
BH		 6566 .remove = efx_ef10_remove,
6567 .dimension_resources = efx_ef10_dimension_resources,
6568 .init = efx_ef10_init_nic,
6569 .fini = efx_port_dummy_op_void,
087e9025 6570 .map_reset_reason = efx_ef10_map_reset_reason,
8127d661 6571 .map_reset_flags = efx_ef10_map_reset_flags,
3e336261 6572 .reset = efx_ef10_reset,
8127d661
BH		 6573 .probe_port = efx_mcdi_port_probe,
6574 .remove_port = efx_mcdi_port_remove,
6575 .fini_dmaq = efx_ef10_fini_dmaq,
e283546c
EC		 6576 .prepare_flr = efx_ef10_prepare_flr,
6577 .finish_flr = efx_port_dummy_op_void,
8127d661 6578 .describe_stats = efx_ef10_describe_stats,
d7788196 6579 .update_stats = efx_ef10_update_stats_pf,
8127d661 6580 .start_stats = efx_mcdi_mac_start_stats,
f8f3b5ae 6581 .pull_stats = efx_mcdi_mac_pull_stats,
8127d661
BH		 6582 .stop_stats = efx_mcdi_mac_stop_stats,
6583 .set_id_led = efx_mcdi_set_id_led,
6584 .push_irq_moderation = efx_ef10_push_irq_moderation,
6585 .reconfigure_mac = efx_ef10_mac_reconfigure,
6586 .check_mac_fault = efx_mcdi_mac_check_fault,
6587 .reconfigure_port = efx_mcdi_port_reconfigure,
6588 .get_wol = efx_ef10_get_wol,
6589 .set_wol = efx_ef10_set_wol,
6590 .resume_wol = efx_port_dummy_op_void,
74cd60a4 6591 .test_chip = efx_ef10_test_chip,
8127d661
BH		 6592 .test_nvram = efx_mcdi_nvram_test_all,
6593 .mcdi_request = efx_ef10_mcdi_request,
6594 .mcdi_poll_response = efx_ef10_mcdi_poll_response,
6595 .mcdi_read_response = efx_ef10_mcdi_read_response,
6596 .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot,
c577e59e 6597 .mcdi_reboot_detected = efx_ef10_mcdi_reboot_detected,
8127d661
BH		 6598 .irq_enable_master = efx_port_dummy_op_void,
6599 .irq_test_generate = efx_ef10_irq_test_generate,
6600 .irq_disable_non_ev = efx_port_dummy_op_void,
6601 .irq_handle_msi = efx_ef10_msi_interrupt,
6602 .irq_handle_legacy = efx_ef10_legacy_interrupt,
6603 .tx_probe = efx_ef10_tx_probe,
6604 .tx_init = efx_ef10_tx_init,
6605 .tx_remove = efx_ef10_tx_remove,
6606 .tx_write = efx_ef10_tx_write,
e9117e50 6607 .tx_limit_len = efx_ef10_tx_limit_len,
267c0157 6608 .rx_push_rss_config = efx_ef10_pf_rx_push_rss_config,
a707d188 6609 .rx_pull_rss_config = efx_ef10_rx_pull_rss_config,
8127d661
BH		 6610 .rx_probe = efx_ef10_rx_probe,
6611 .rx_init = efx_ef10_rx_init,
6612 .rx_remove = efx_ef10_rx_remove,
6613 .rx_write = efx_ef10_rx_write,
6614 .rx_defer_refill = efx_ef10_rx_defer_refill,
6615 .ev_probe = efx_ef10_ev_probe,
6616 .ev_init = efx_ef10_ev_init,
6617 .ev_fini = efx_ef10_ev_fini,
6618 .ev_remove = efx_ef10_ev_remove,
6619 .ev_process = efx_ef10_ev_process,
6620 .ev_read_ack = efx_ef10_ev_read_ack,
6621 .ev_test_generate = efx_ef10_ev_test_generate,
6622 .filter_table_probe = efx_ef10_filter_table_probe,
6623 .filter_table_restore = efx_ef10_filter_table_restore,
6624 .filter_table_remove = efx_ef10_filter_table_remove,
6625 .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter,
6626 .filter_insert = efx_ef10_filter_insert,
6627 .filter_remove_safe = efx_ef10_filter_remove_safe,
6628 .filter_get_safe = efx_ef10_filter_get_safe,
6629 .filter_clear_rx = efx_ef10_filter_clear_rx,
6630 .filter_count_rx_used = efx_ef10_filter_count_rx_used,
6631 .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit,
6632 .filter_get_rx_ids = efx_ef10_filter_get_rx_ids,
6633#ifdef CONFIG_RFS_ACCEL
6634 .filter_rfs_insert = efx_ef10_filter_rfs_insert,
6635 .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one,
6636#endif
6637#ifdef CONFIG_SFC_MTD
6638 .mtd_probe = efx_ef10_mtd_probe,
6639 .mtd_rename = efx_mcdi_mtd_rename,
6640 .mtd_read = efx_mcdi_mtd_read,
6641 .mtd_erase = efx_mcdi_mtd_erase,
6642 .mtd_write = efx_mcdi_mtd_write,
6643 .mtd_sync = efx_mcdi_mtd_sync,
6644#endif
6645 .ptp_write_host_time = efx_ef10_ptp_write_host_time,
bd9a265d
JC		 6646 .ptp_set_ts_sync_events = efx_ef10_ptp_set_ts_sync_events,
6647 .ptp_set_ts_config = efx_ef10_ptp_set_ts_config,
4a53ea8a
AR		 6648 .vlan_rx_add_vid = efx_ef10_vlan_rx_add_vid,
6649 .vlan_rx_kill_vid = efx_ef10_vlan_rx_kill_vid,
e5fbd977
JC		 6650 .udp_tnl_push_ports = efx_ef10_udp_tnl_push_ports,
6651 .udp_tnl_add_port = efx_ef10_udp_tnl_add_port,
6652 .udp_tnl_has_port = efx_ef10_udp_tnl_has_port,
6653 .udp_tnl_del_port = efx_ef10_udp_tnl_del_port,
7fa8d547 6654#ifdef CONFIG_SFC_SRIOV
834e23dd 6655 .sriov_configure = efx_ef10_sriov_configure,
d98a4ffe
SS		 6656 .sriov_init = efx_ef10_sriov_init,
6657 .sriov_fini = efx_ef10_sriov_fini,
d98a4ffe
SS		 6658 .sriov_wanted = efx_ef10_sriov_wanted,
6659 .sriov_reset = efx_ef10_sriov_reset,
7fa8d547
SS		 6660 .sriov_flr = efx_ef10_sriov_flr,
6661 .sriov_set_vf_mac = efx_ef10_sriov_set_vf_mac,
6662 .sriov_set_vf_vlan = efx_ef10_sriov_set_vf_vlan,
6663 .sriov_set_vf_spoofchk = efx_ef10_sriov_set_vf_spoofchk,
6664 .sriov_get_vf_config = efx_ef10_sriov_get_vf_config,
4392dc69 6665 .sriov_set_vf_link_state = efx_ef10_sriov_set_vf_link_state,
7b8c7b54
SS		 6666 .vswitching_probe = efx_ef10_vswitching_probe_pf,
6667 .vswitching_restore = efx_ef10_vswitching_restore_pf,
6668 .vswitching_remove = efx_ef10_vswitching_remove_pf,
7fa8d547 6669#endif
0d5e0fbb 6670 .get_mac_address = efx_ef10_get_mac_address_pf,
910c8789 6671 .set_mac_address = efx_ef10_set_mac_address,
46d1efd8 6672 .tso_versions = efx_ef10_tso_versions,
8127d661 6673
08a7b29b 6674 .get_phys_port_id = efx_ef10_get_phys_port_id,
8127d661
BH		 6675 .revision = EFX_REV_HUNT_A0,
6676 .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH),
6677 .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE,
6678 .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST,
bd9a265d 6679 .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST,
8127d661
BH		 6680 .can_rx_scatter = true,
6681 .always_rx_scatter = true,
de1deff9 6682 .option_descriptors = true,
6f9f6ec2 6683 .min_interrupt_mode = EFX_INT_MODE_LEGACY,
8127d661
BH		 6684 .max_interrupt_mode = EFX_INT_MODE_MSIX,
6685 .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH,
100a9db5 6686 .offload_features = EF10_OFFLOAD_FEATURES,
8127d661
BH		 6687 .mcdi_max_ver = 2,
6688 .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS,
bd9a265d
JC		 6689 .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE |
6690 1 << HWTSTAMP_FILTER_ALL,
f74d1995 6691 .rx_hash_key_size = 40,
8127d661 6692};
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