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[mirror_ubuntu-focal-kernel.git] / drivers / net / ethernet / sfc / ef10.c
CommitLineData
8127d661
BH		 1/****************************************************************************
2 * Driver for Solarflare network controllers and boards
3 * Copyright 2012-2013 Solarflare Communications Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published
7 * by the Free Software Foundation, incorporated herein by reference.
8 */
9
10#include "net_driver.h"
11#include "ef10_regs.h"
12#include "io.h"
13#include "mcdi.h"
14#include "mcdi_pcol.h"
15#include "nic.h"
16#include "workarounds.h"
74cd60a4 17#include "selftest.h"
7fa8d547 18#include "ef10_sriov.h"
8127d661
BH		 19#include <linux/in.h>
20#include <linux/jhash.h>
21#include <linux/wait.h>
22#include <linux/workqueue.h>
23
24/* Hardware control for EF10 architecture including 'Huntington'. */
25
26#define EFX_EF10_DRVGEN_EV 7
27enum {
28 EFX_EF10_TEST = 1,
29 EFX_EF10_REFILL,
30};
31
32/* The reserved RSS context value */
33#define EFX_EF10_RSS_CONTEXT_INVALID 0xffffffff
267c0157
JC		 34/* The maximum size of a shared RSS context */
35/* TODO: this should really be from the mcdi protocol export */
36#define EFX_EF10_MAX_SHARED_RSS_CONTEXT_SIZE 64UL
8127d661
BH		 37
38/* The filter table(s) are managed by firmware and we have write-only
39 * access. When removing filters we must identify them to the
40 * firmware by a 64-bit handle, but this is too wide for Linux kernel
41 * interfaces (32-bit for RX NFC, 16-bit for RFS). Also, we need to
42 * be able to tell in advance whether a requested insertion will
43 * replace an existing filter. Therefore we maintain a software hash
44 * table, which should be at least as large as the hardware hash
45 * table.
46 *
47 * Huntington has a single 8K filter table shared between all filter
48 * types and both ports.
49 */
50#define HUNT_FILTER_TBL_ROWS 8192
51
12fb0da4 52#define EFX_EF10_FILTER_ID_INVALID 0xffff
dc3273e0
AR		 53
54#define EFX_EF10_FILTER_DEV_UC_MAX 32
55#define EFX_EF10_FILTER_DEV_MC_MAX 256
56
34813fe2
AR		 57/* VLAN list entry */
58struct efx_ef10_vlan {
59 struct list_head list;
60 u16 vid;
61};
62
9b410801
EC		 63enum efx_ef10_default_filters {
64 EFX_EF10_BCAST,
65 EFX_EF10_UCDEF,
66 EFX_EF10_MCDEF,
67 EFX_EF10_VXLAN4_UCDEF,
68 EFX_EF10_VXLAN4_MCDEF,
69 EFX_EF10_VXLAN6_UCDEF,
70 EFX_EF10_VXLAN6_MCDEF,
71 EFX_EF10_NVGRE4_UCDEF,
72 EFX_EF10_NVGRE4_MCDEF,
73 EFX_EF10_NVGRE6_UCDEF,
74 EFX_EF10_NVGRE6_MCDEF,
75 EFX_EF10_GENEVE4_UCDEF,
76 EFX_EF10_GENEVE4_MCDEF,
77 EFX_EF10_GENEVE6_UCDEF,
78 EFX_EF10_GENEVE6_MCDEF,
79
80 EFX_EF10_NUM_DEFAULT_FILTERS
81};
82
dc3273e0
AR		 83/* Per-VLAN filters information */
84struct efx_ef10_filter_vlan {
34813fe2 85 struct list_head list;
b3a3c03c 86 u16 vid;
dc3273e0
AR		 87 u16 uc[EFX_EF10_FILTER_DEV_UC_MAX];
88 u16 mc[EFX_EF10_FILTER_DEV_MC_MAX];
9b410801 89 u16 default_filters[EFX_EF10_NUM_DEFAULT_FILTERS];
dc3273e0
AR		 90};
91
822b96f8
DP		 92struct efx_ef10_dev_addr {
93 u8 addr[ETH_ALEN];
822b96f8
DP		 94};
95
8127d661 96struct efx_ef10_filter_table {
7ac0dd9d
AR		 97/* The MCDI match masks supported by this fw & hw, in order of priority */
98 u32 rx_match_mcdi_flags[
9b410801 99 MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM * 2];
8127d661
BH		 100 unsigned int rx_match_count;
101
102 struct {
103 unsigned long spec; /* pointer to spec plus flag bits */
b59e6ef8
BH		 104/* BUSY flag indicates that an update is in progress. AUTO_OLD is
105 * used to mark and sweep MAC filters for the device address lists.
8127d661
BH		 106 */
107#define EFX_EF10_FILTER_FLAG_BUSY 1UL
b59e6ef8 108#define EFX_EF10_FILTER_FLAG_AUTO_OLD 2UL
8127d661
BH		 109#define EFX_EF10_FILTER_FLAGS 3UL
110 u64 handle; /* firmware handle */
111 } *entry;
112 wait_queue_head_t waitq;
113/* Shadow of net_device address lists, guarded by mac_lock */
822b96f8
DP		 114 struct efx_ef10_dev_addr dev_uc_list[EFX_EF10_FILTER_DEV_UC_MAX];
115 struct efx_ef10_dev_addr dev_mc_list[EFX_EF10_FILTER_DEV_MC_MAX];
12fb0da4
EC		 116 int dev_uc_count;
117 int dev_mc_count;
afa4ce12
AR		 118 bool uc_promisc;
119 bool mc_promisc;
b071c3a2
AR		 120/* Whether in multicast promiscuous mode when last changed */
121 bool mc_promisc_last;
4a53ea8a 122 bool vlan_filter;
34813fe2 123 struct list_head vlan_list;
8127d661
BH		 124};
125
126/* An arbitrary search limit for the software hash table */
127#define EFX_EF10_FILTER_SEARCH_LIMIT 200
128
8127d661
BH		 129static void efx_ef10_rx_free_indir_table(struct efx_nic *efx);
130static void efx_ef10_filter_table_remove(struct efx_nic *efx);
34813fe2
AR		 131static int efx_ef10_filter_add_vlan(struct efx_nic *efx, u16 vid);
132static void efx_ef10_filter_del_vlan_internal(struct efx_nic *efx,
133 struct efx_ef10_filter_vlan *vlan);
134static void efx_ef10_filter_del_vlan(struct efx_nic *efx, u16 vid);
8127d661
BH		 135
136static int efx_ef10_get_warm_boot_count(struct efx_nic *efx)
137{
138 efx_dword_t reg;
139
140 efx_readd(efx, &reg, ER_DZ_BIU_MC_SFT_STATUS);
141 return EFX_DWORD_FIELD(reg, EFX_WORD_1) == 0xb007 ?
142 EFX_DWORD_FIELD(reg, EFX_WORD_0) : -EIO;
143}
144
145static unsigned int efx_ef10_mem_map_size(struct efx_nic *efx)
146{
02246a7f
SS		 147 int bar;
148
149 bar = efx->type->mem_bar;
150 return resource_size(&efx->pci_dev->resource[bar]);
8127d661
BH		 151}
152
7a186f47
DP		 153static bool efx_ef10_is_vf(struct efx_nic *efx)
154{
155 return efx->type->is_vf;
156}
157
1cd9ecbb
DP		 158static int efx_ef10_get_pf_index(struct efx_nic *efx)
159{
160 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN);
161 struct efx_ef10_nic_data *nic_data = efx->nic_data;
162 size_t outlen;
163 int rc;
164
165 rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf,
166 sizeof(outbuf), &outlen);
167 if (rc)
168 return rc;
169 if (outlen < sizeof(outbuf))
170 return -EIO;
171
172 nic_data->pf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_PF);
173 return 0;
174}
175
88a37de6
SS		 176#ifdef CONFIG_SFC_SRIOV
177static int efx_ef10_get_vf_index(struct efx_nic *efx)
178{
179 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN);
180 struct efx_ef10_nic_data *nic_data = efx->nic_data;
181 size_t outlen;
182 int rc;
183
184 rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf,
185 sizeof(outbuf), &outlen);
186 if (rc)
187 return rc;
188 if (outlen < sizeof(outbuf))
189 return -EIO;
190
191 nic_data->vf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_VF);
192 return 0;
193}
194#endif
195
e5a2538a 196static int efx_ef10_init_datapath_caps(struct efx_nic *efx)
8127d661 197{
ca889a05 198 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CAPABILITIES_V2_OUT_LEN);
8127d661
BH		 199 struct efx_ef10_nic_data *nic_data = efx->nic_data;
200 size_t outlen;
201 int rc;
202
203 BUILD_BUG_ON(MC_CMD_GET_CAPABILITIES_IN_LEN != 0);
204
205 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CAPABILITIES, NULL, 0,
206 outbuf, sizeof(outbuf), &outlen);
207 if (rc)
208 return rc;
ca889a05 209 if (outlen < MC_CMD_GET_CAPABILITIES_OUT_LEN) {
e5a2538a
BH		 210 netif_err(efx, drv, efx->net_dev,
211 "unable to read datapath firmware capabilities\n");
212 return -EIO;
213 }
214
215 nic_data->datapath_caps =
216 MCDI_DWORD(outbuf, GET_CAPABILITIES_OUT_FLAGS1);
8127d661 217
c634700f 218 if (outlen >= MC_CMD_GET_CAPABILITIES_V2_OUT_LEN) {
ca889a05
BK		 219 nic_data->datapath_caps2 = MCDI_DWORD(outbuf,
220 GET_CAPABILITIES_V2_OUT_FLAGS2);
c634700f
EC		 221 nic_data->piobuf_size = MCDI_WORD(outbuf,
222 GET_CAPABILITIES_V2_OUT_SIZE_PIO_BUFF);
223 } else {
ca889a05 224 nic_data->datapath_caps2 = 0;
c634700f
EC		 225 nic_data->piobuf_size = ER_DZ_TX_PIOBUF_SIZE;
226 }
ca889a05 227
8d9f9dd4
DP		 228 /* record the DPCPU firmware IDs to determine VEB vswitching support.
229 */
230 nic_data->rx_dpcpu_fw_id =
231 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID);
232 nic_data->tx_dpcpu_fw_id =
233 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID);
234
e5a2538a
BH		 235 if (!(nic_data->datapath_caps &
236 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN))) {
237 netif_err(efx, probe, efx->net_dev,
238 "current firmware does not support an RX prefix\n");
239 return -ENODEV;
8127d661
BH		 240 }
241
242 return 0;
243}
244
245static int efx_ef10_get_sysclk_freq(struct efx_nic *efx)
246{
247 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CLOCK_OUT_LEN);
248 int rc;
249
250 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CLOCK, NULL, 0,
251 outbuf, sizeof(outbuf), NULL);
252 if (rc)
253 return rc;
254 rc = MCDI_DWORD(outbuf, GET_CLOCK_OUT_SYS_FREQ);
255 return rc > 0 ? rc : -ERANGE;
256}
257
d95e329a
BK		 258static int efx_ef10_get_timer_workarounds(struct efx_nic *efx)
259{
260 struct efx_ef10_nic_data *nic_data = efx->nic_data;
261 unsigned int implemented;
262 unsigned int enabled;
263 int rc;
264
265 nic_data->workaround_35388 = false;
266 nic_data->workaround_61265 = false;
267
268 rc = efx_mcdi_get_workarounds(efx, &implemented, &enabled);
269
270 if (rc == -ENOSYS) {
271 /* Firmware without GET_WORKAROUNDS - not a problem. */
272 rc = 0;
273 } else if (rc == 0) {
274 /* Bug61265 workaround is always enabled if implemented. */
275 if (enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG61265)
276 nic_data->workaround_61265 = true;
277
278 if (enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG35388) {
279 nic_data->workaround_35388 = true;
280 } else if (implemented & MC_CMD_GET_WORKAROUNDS_OUT_BUG35388) {
281 /* Workaround is implemented but not enabled.
282 * Try to enable it.
283 */
284 rc = efx_mcdi_set_workaround(efx,
285 MC_CMD_WORKAROUND_BUG35388,
286 true, NULL);
287 if (rc == 0)
288 nic_data->workaround_35388 = true;
289 /* If we failed to set the workaround just carry on. */
290 rc = 0;
291 }
292 }
293
294 netif_dbg(efx, probe, efx->net_dev,
295 "workaround for bug 35388 is %sabled\n",
296 nic_data->workaround_35388 ? "en" : "dis");
297 netif_dbg(efx, probe, efx->net_dev,
298 "workaround for bug 61265 is %sabled\n",
299 nic_data->workaround_61265 ? "en" : "dis");
300
301 return rc;
302}
303
304static void efx_ef10_process_timer_config(struct efx_nic *efx,
305 const efx_dword_t *data)
306{
307 unsigned int max_count;
308
309 if (EFX_EF10_WORKAROUND_61265(efx)) {
310 efx->timer_quantum_ns = MCDI_DWORD(data,
311 GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_STEP_NS);
312 efx->timer_max_ns = MCDI_DWORD(data,
313 GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_MAX_NS);
314 } else if (EFX_EF10_WORKAROUND_35388(efx)) {
315 efx->timer_quantum_ns = MCDI_DWORD(data,
316 GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_NS_PER_COUNT);
317 max_count = MCDI_DWORD(data,
318 GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_MAX_COUNT);
319 efx->timer_max_ns = max_count * efx->timer_quantum_ns;
320 } else {
321 efx->timer_quantum_ns = MCDI_DWORD(data,
322 GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_NS_PER_COUNT);
323 max_count = MCDI_DWORD(data,
324 GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_MAX_COUNT);
325 efx->timer_max_ns = max_count * efx->timer_quantum_ns;
326 }
327
328 netif_dbg(efx, probe, efx->net_dev,
329 "got timer properties from MC: quantum %u ns; max %u ns\n",
330 efx->timer_quantum_ns, efx->timer_max_ns);
331}
332
333static int efx_ef10_get_timer_config(struct efx_nic *efx)
334{
335 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_LEN);
336 int rc;
337
338 rc = efx_ef10_get_timer_workarounds(efx);
339 if (rc)
340 return rc;
341
342 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_GET_EVQ_TMR_PROPERTIES, NULL, 0,
343 outbuf, sizeof(outbuf), NULL);
344
345 if (rc == 0) {
346 efx_ef10_process_timer_config(efx, outbuf);
347 } else if (rc == -ENOSYS || rc == -EPERM) {
348 /* Not available - fall back to Huntington defaults. */
349 unsigned int quantum;
350
351 rc = efx_ef10_get_sysclk_freq(efx);
352 if (rc < 0)
353 return rc;
354
355 quantum = 1536000 / rc; /* 1536 cycles */
356 efx->timer_quantum_ns = quantum;
357 efx->timer_max_ns = efx->type->timer_period_max * quantum;
358 rc = 0;
359 } else {
360 efx_mcdi_display_error(efx, MC_CMD_GET_EVQ_TMR_PROPERTIES,
361 MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_LEN,
362 NULL, 0, rc);
363 }
364
365 return rc;
366}
367
0d5e0fbb 368static int efx_ef10_get_mac_address_pf(struct efx_nic *efx, u8 *mac_address)
8127d661
BH		 369{
370 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_MAC_ADDRESSES_OUT_LEN);
371 size_t outlen;
372 int rc;
373
374 BUILD_BUG_ON(MC_CMD_GET_MAC_ADDRESSES_IN_LEN != 0);
375
376 rc = efx_mcdi_rpc(efx, MC_CMD_GET_MAC_ADDRESSES, NULL, 0,
377 outbuf, sizeof(outbuf), &outlen);
378 if (rc)
379 return rc;
380 if (outlen < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN)
381 return -EIO;
382
cd84ff4d
EC		 383 ether_addr_copy(mac_address,
384 MCDI_PTR(outbuf, GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE));
8127d661
BH		 385 return 0;
386}
387
0d5e0fbb
DP		 388static int efx_ef10_get_mac_address_vf(struct efx_nic *efx, u8 *mac_address)
389{
390 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN);
391 MCDI_DECLARE_BUF(outbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX);
392 size_t outlen;
393 int num_addrs, rc;
394
395 MCDI_SET_DWORD(inbuf, VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID,
396 EVB_PORT_ID_ASSIGNED);
397 rc = efx_mcdi_rpc(efx, MC_CMD_VPORT_GET_MAC_ADDRESSES, inbuf,
398 sizeof(inbuf), outbuf, sizeof(outbuf), &outlen);
399
400 if (rc)
401 return rc;
402 if (outlen < MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN)
403 return -EIO;
404
405 num_addrs = MCDI_DWORD(outbuf,
406 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT);
407
408 WARN_ON(num_addrs != 1);
409
410 ether_addr_copy(mac_address,
411 MCDI_PTR(outbuf, VPORT_GET_MAC_ADDRESSES_OUT_MACADDR));
412
413 return 0;
414}
415
0f5c0845
SS		 416static ssize_t efx_ef10_show_link_control_flag(struct device *dev,
417 struct device_attribute *attr,
418 char *buf)
419{
420 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
421
422 return sprintf(buf, "%d\n",
423 ((efx->mcdi->fn_flags) &
424 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL))
425 ? 1 : 0);
426}
427
428static ssize_t efx_ef10_show_primary_flag(struct device *dev,
429 struct device_attribute *attr,
430 char *buf)
431{
432 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
433
434 return sprintf(buf, "%d\n",
435 ((efx->mcdi->fn_flags) &
436 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY))
437 ? 1 : 0);
438}
439
34813fe2
AR		 440static struct efx_ef10_vlan *efx_ef10_find_vlan(struct efx_nic *efx, u16 vid)
441{
442 struct efx_ef10_nic_data *nic_data = efx->nic_data;
443 struct efx_ef10_vlan *vlan;
444
445 WARN_ON(!mutex_is_locked(&nic_data->vlan_lock));
446
447 list_for_each_entry(vlan, &nic_data->vlan_list, list) {
448 if (vlan->vid == vid)
449 return vlan;
450 }
451
452 return NULL;
453}
454
455static int efx_ef10_add_vlan(struct efx_nic *efx, u16 vid)
456{
457 struct efx_ef10_nic_data *nic_data = efx->nic_data;
458 struct efx_ef10_vlan *vlan;
459 int rc;
460
461 mutex_lock(&nic_data->vlan_lock);
462
463 vlan = efx_ef10_find_vlan(efx, vid);
464 if (vlan) {
4a53ea8a
AR		 465 /* We add VID 0 on init. 8021q adds it on module init
466 * for all interfaces with VLAN filtring feature.
467 */
468 if (vid == 0)
469 goto done_unlock;
34813fe2
AR		 470 netif_warn(efx, drv, efx->net_dev,
471 "VLAN %u already added\n", vid);
472 rc = -EALREADY;
473 goto fail_exist;
474 }
475
476 rc = -ENOMEM;
477 vlan = kzalloc(sizeof(*vlan), GFP_KERNEL);
478 if (!vlan)
479 goto fail_alloc;
480
481 vlan->vid = vid;
482
483 list_add_tail(&vlan->list, &nic_data->vlan_list);
484
485 if (efx->filter_state) {
486 mutex_lock(&efx->mac_lock);
487 down_write(&efx->filter_sem);
488 rc = efx_ef10_filter_add_vlan(efx, vlan->vid);
489 up_write(&efx->filter_sem);
490 mutex_unlock(&efx->mac_lock);
491 if (rc)
492 goto fail_filter_add_vlan;
493 }
494
4a53ea8a 495done_unlock:
34813fe2
AR		 496 mutex_unlock(&nic_data->vlan_lock);
497 return 0;
498
499fail_filter_add_vlan:
500 list_del(&vlan->list);
501 kfree(vlan);
502fail_alloc:
503fail_exist:
504 mutex_unlock(&nic_data->vlan_lock);
505 return rc;
506}
507
508static void efx_ef10_del_vlan_internal(struct efx_nic *efx,
509 struct efx_ef10_vlan *vlan)
510{
511 struct efx_ef10_nic_data *nic_data = efx->nic_data;
512
513 WARN_ON(!mutex_is_locked(&nic_data->vlan_lock));
514
515 if (efx->filter_state) {
516 down_write(&efx->filter_sem);
517 efx_ef10_filter_del_vlan(efx, vlan->vid);
518 up_write(&efx->filter_sem);
519 }
520
521 list_del(&vlan->list);
522 kfree(vlan);
523}
524
4a53ea8a
AR		 525static int efx_ef10_del_vlan(struct efx_nic *efx, u16 vid)
526{
527 struct efx_ef10_nic_data *nic_data = efx->nic_data;
528 struct efx_ef10_vlan *vlan;
529 int rc = 0;
530
531 /* 8021q removes VID 0 on module unload for all interfaces
532 * with VLAN filtering feature. We need to keep it to receive
533 * untagged traffic.
534 */
535 if (vid == 0)
536 return 0;
537
538 mutex_lock(&nic_data->vlan_lock);
539
540 vlan = efx_ef10_find_vlan(efx, vid);
541 if (!vlan) {
542 netif_err(efx, drv, efx->net_dev,
543 "VLAN %u to be deleted not found\n", vid);
544 rc = -ENOENT;
545 } else {
546 efx_ef10_del_vlan_internal(efx, vlan);
547 }
548
549 mutex_unlock(&nic_data->vlan_lock);
550
551 return rc;
552}
553
34813fe2
AR		 554static void efx_ef10_cleanup_vlans(struct efx_nic *efx)
555{
556 struct efx_ef10_nic_data *nic_data = efx->nic_data;
557 struct efx_ef10_vlan *vlan, *next_vlan;
558
559 mutex_lock(&nic_data->vlan_lock);
560 list_for_each_entry_safe(vlan, next_vlan, &nic_data->vlan_list, list)
561 efx_ef10_del_vlan_internal(efx, vlan);
562 mutex_unlock(&nic_data->vlan_lock);
563}
564
0f5c0845
SS		 565static DEVICE_ATTR(link_control_flag, 0444, efx_ef10_show_link_control_flag,
566 NULL);
567static DEVICE_ATTR(primary_flag, 0444, efx_ef10_show_primary_flag, NULL);
568
8127d661
BH		 569static int efx_ef10_probe(struct efx_nic *efx)
570{
571 struct efx_ef10_nic_data *nic_data;
572 int i, rc;
573
aa3930ee
BH		 574 /* We can have one VI for each 8K region. However, until we
575 * use TX option descriptors we need two TX queues per channel.
8127d661 576 */
b0fbdae1
SS		 577 efx->max_channels = min_t(unsigned int,
578 EFX_MAX_CHANNELS,
579 efx_ef10_mem_map_size(efx) /
580 (EFX_VI_PAGE_SIZE * EFX_TXQ_TYPES));
581 efx->max_tx_channels = efx->max_channels;
9fd3d3a4
EC		 582 if (WARN_ON(efx->max_channels == 0))
583 return -EIO;
8127d661
BH		 584
585 nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
586 if (!nic_data)
587 return -ENOMEM;
588 efx->nic_data = nic_data;
589
75aba2a5
EC		 590 /* we assume later that we can copy from this buffer in dwords */
591 BUILD_BUG_ON(MCDI_CTL_SDU_LEN_MAX_V2 % 4);
592
8127d661
BH		 593 rc = efx_nic_alloc_buffer(efx, &nic_data->mcdi_buf,
594 8 + MCDI_CTL_SDU_LEN_MAX_V2, GFP_KERNEL);
595 if (rc)
596 goto fail1;
597
598 /* Get the MC's warm boot count. In case it's rebooting right
599 * now, be prepared to retry.
600 */
601 i = 0;
602 for (;;) {
603 rc = efx_ef10_get_warm_boot_count(efx);
604 if (rc >= 0)
605 break;
606 if (++i == 5)
607 goto fail2;
608 ssleep(1);
609 }
610 nic_data->warm_boot_count = rc;
611
612 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
613
45b2449e
DP		 614 nic_data->vport_id = EVB_PORT_ID_ASSIGNED;
615
8127d661
BH		 616 /* In case we're recovering from a crash (kexec), we want to
617 * cancel any outstanding request by the previous user of this
618 * function. We send a special message using the least
619 * significant bits of the 'high' (doorbell) register.
620 */
621 _efx_writed(efx, cpu_to_le32(1), ER_DZ_MC_DB_HWRD);
622
623 rc = efx_mcdi_init(efx);
624 if (rc)
625 goto fail2;
626
627 /* Reset (most) configuration for this function */
628 rc = efx_mcdi_reset(efx, RESET_TYPE_ALL);
629 if (rc)
630 goto fail3;
631
632 /* Enable event logging */
633 rc = efx_mcdi_log_ctrl(efx, true, false, 0);
634 if (rc)
635 goto fail3;
636
0f5c0845
SS		 637 rc = device_create_file(&efx->pci_dev->dev,
638 &dev_attr_link_control_flag);
1cd9ecbb
DP		 639 if (rc)
640 goto fail3;
641
0f5c0845
SS		 642 rc = device_create_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
643 if (rc)
644 goto fail4;
645
646 rc = efx_ef10_get_pf_index(efx);
647 if (rc)
648 goto fail5;
649
e5a2538a 650 rc = efx_ef10_init_datapath_caps(efx);
8127d661 651 if (rc < 0)
0f5c0845 652 goto fail5;
8127d661
BH		 653
654 efx->rx_packet_len_offset =
655 ES_DZ_RX_PREFIX_PKTLEN_OFST - ES_DZ_RX_PREFIX_SIZE;
656
8127d661
BH		 657 rc = efx_mcdi_port_get_number(efx);
658 if (rc < 0)
0f5c0845 659 goto fail5;
8127d661
BH		 660 efx->port_num = rc;
661
0d5e0fbb 662 rc = efx->type->get_mac_address(efx, efx->net_dev->perm_addr);
8127d661 663 if (rc)
0f5c0845 664 goto fail5;
8127d661 665
d95e329a 666 rc = efx_ef10_get_timer_config(efx);
8127d661 667 if (rc < 0)
0f5c0845 668 goto fail5;
8127d661 669
8127d661 670 rc = efx_mcdi_mon_probe(efx);
267d9d73 671 if (rc && rc != -EPERM)
0f5c0845 672 goto fail5;
8127d661 673
9aecda95
BH		 674 efx_ptp_probe(efx, NULL);
675
1d051e00
SS		 676#ifdef CONFIG_SFC_SRIOV
677 if ((efx->pci_dev->physfn) && (!efx->pci_dev->is_physfn)) {
678 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn;
679 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
680
681 efx_pf->type->get_mac_address(efx_pf, nic_data->port_id);
682 } else
683#endif
684 ether_addr_copy(nic_data->port_id, efx->net_dev->perm_addr);
685
34813fe2
AR		 686 INIT_LIST_HEAD(&nic_data->vlan_list);
687 mutex_init(&nic_data->vlan_lock);
688
689 /* Add unspecified VID to support VLAN filtering being disabled */
690 rc = efx_ef10_add_vlan(efx, EFX_FILTER_VID_UNSPEC);
691 if (rc)
692 goto fail_add_vid_unspec;
693
4a53ea8a
AR		 694 /* If VLAN filtering is enabled, we need VID 0 to get untagged
695 * traffic. It is added automatically if 8021q module is loaded,
696 * but we can't rely on it since module may be not loaded.
697 */
698 rc = efx_ef10_add_vlan(efx, 0);
699 if (rc)
700 goto fail_add_vid_0;
701
8127d661
BH		 702 return 0;
703
4a53ea8a
AR		 704fail_add_vid_0:
705 efx_ef10_cleanup_vlans(efx);
34813fe2
AR		 706fail_add_vid_unspec:
707 mutex_destroy(&nic_data->vlan_lock);
708 efx_ptp_remove(efx);
709 efx_mcdi_mon_remove(efx);
0f5c0845
SS		 710fail5:
711 device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
712fail4:
713 device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag);
8127d661
BH		 714fail3:
715 efx_mcdi_fini(efx);
716fail2:
717 efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
718fail1:
719 kfree(nic_data);
720 efx->nic_data = NULL;
721 return rc;
722}
723
724static int efx_ef10_free_vis(struct efx_nic *efx)
725{
aa09a3da 726 MCDI_DECLARE_BUF_ERR(outbuf);
1e0b8120
EC		 727 size_t outlen;
728 int rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FREE_VIS, NULL, 0,
729 outbuf, sizeof(outbuf), &outlen);
8127d661
BH		 730
731 /* -EALREADY means nothing to free, so ignore */
732 if (rc == -EALREADY)
733 rc = 0;
1e0b8120
EC		 734 if (rc)
735 efx_mcdi_display_error(efx, MC_CMD_FREE_VIS, 0, outbuf, outlen,
736 rc);
8127d661
BH		 737 return rc;
738}
739
183233be
BH		 740#ifdef EFX_USE_PIO
741
742static void efx_ef10_free_piobufs(struct efx_nic *efx)
743{
744 struct efx_ef10_nic_data *nic_data = efx->nic_data;
745 MCDI_DECLARE_BUF(inbuf, MC_CMD_FREE_PIOBUF_IN_LEN);
746 unsigned int i;
747 int rc;
748
749 BUILD_BUG_ON(MC_CMD_FREE_PIOBUF_OUT_LEN != 0);
750
751 for (i = 0; i < nic_data->n_piobufs; i++) {
752 MCDI_SET_DWORD(inbuf, FREE_PIOBUF_IN_PIOBUF_HANDLE,
753 nic_data->piobuf_handle[i]);
754 rc = efx_mcdi_rpc(efx, MC_CMD_FREE_PIOBUF, inbuf, sizeof(inbuf),
755 NULL, 0, NULL);
756 WARN_ON(rc);
757 }
758
759 nic_data->n_piobufs = 0;
760}
761
762static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
763{
764 struct efx_ef10_nic_data *nic_data = efx->nic_data;
765 MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_PIOBUF_OUT_LEN);
766 unsigned int i;
767 size_t outlen;
768 int rc = 0;
769
770 BUILD_BUG_ON(MC_CMD_ALLOC_PIOBUF_IN_LEN != 0);
771
772 for (i = 0; i < n; i++) {
09a04204
BK		 773 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_ALLOC_PIOBUF, NULL, 0,
774 outbuf, sizeof(outbuf), &outlen);
775 if (rc) {
776 /* Don't display the MC error if we didn't have space
777 * for a VF.
778 */
779 if (!(efx_ef10_is_vf(efx) && rc == -ENOSPC))
780 efx_mcdi_display_error(efx, MC_CMD_ALLOC_PIOBUF,
781 0, outbuf, outlen, rc);
183233be 782 break;
09a04204 783 }
183233be
BH		 784 if (outlen < MC_CMD_ALLOC_PIOBUF_OUT_LEN) {
785 rc = -EIO;
786 break;
787 }
788 nic_data->piobuf_handle[i] =
789 MCDI_DWORD(outbuf, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE);
790 netif_dbg(efx, probe, efx->net_dev,
791 "allocated PIO buffer %u handle %x\n", i,
792 nic_data->piobuf_handle[i]);
793 }
794
795 nic_data->n_piobufs = i;
796 if (rc)
797 efx_ef10_free_piobufs(efx);
798 return rc;
799}
800
801static int efx_ef10_link_piobufs(struct efx_nic *efx)
802{
803 struct efx_ef10_nic_data *nic_data = efx->nic_data;
aa09a3da
JC		 804 _MCDI_DECLARE_BUF(inbuf,
805 max(MC_CMD_LINK_PIOBUF_IN_LEN,
806 MC_CMD_UNLINK_PIOBUF_IN_LEN));
183233be
BH		 807 struct efx_channel *channel;
808 struct efx_tx_queue *tx_queue;
809 unsigned int offset, index;
810 int rc;
811
812 BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_OUT_LEN != 0);
813 BUILD_BUG_ON(MC_CMD_UNLINK_PIOBUF_OUT_LEN != 0);
814
aa09a3da
JC		 815 memset(inbuf, 0, sizeof(inbuf));
816
183233be
BH		 817 /* Link a buffer to each VI in the write-combining mapping */
818 for (index = 0; index < nic_data->n_piobufs; ++index) {
819 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_PIOBUF_HANDLE,
820 nic_data->piobuf_handle[index]);
821 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_TXQ_INSTANCE,
822 nic_data->pio_write_vi_base + index);
823 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
824 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
825 NULL, 0, NULL);
826 if (rc) {
827 netif_err(efx, drv, efx->net_dev,
828 "failed to link VI %u to PIO buffer %u (%d)\n",
829 nic_data->pio_write_vi_base + index, index,
830 rc);
831 goto fail;
832 }
833 netif_dbg(efx, probe, efx->net_dev,
834 "linked VI %u to PIO buffer %u\n",
835 nic_data->pio_write_vi_base + index, index);
836 }
837
838 /* Link a buffer to each TX queue */
839 efx_for_each_channel(channel, efx) {
840 efx_for_each_channel_tx_queue(tx_queue, channel) {
841 /* We assign the PIO buffers to queues in
842 * reverse order to allow for the following
843 * special case.
844 */
845 offset = ((efx->tx_channel_offset + efx->n_tx_channels -
846 tx_queue->channel->channel - 1) *
847 efx_piobuf_size);
c634700f
EC		 848 index = offset / nic_data->piobuf_size;
849 offset = offset % nic_data->piobuf_size;
183233be
BH		 850
851 /* When the host page size is 4K, the first
852 * host page in the WC mapping may be within
853 * the same VI page as the last TX queue. We
854 * can only link one buffer to each VI.
855 */
856 if (tx_queue->queue == nic_data->pio_write_vi_base) {
857 BUG_ON(index != 0);
858 rc = 0;
859 } else {
860 MCDI_SET_DWORD(inbuf,
861 LINK_PIOBUF_IN_PIOBUF_HANDLE,
862 nic_data->piobuf_handle[index]);
863 MCDI_SET_DWORD(inbuf,
864 LINK_PIOBUF_IN_TXQ_INSTANCE,
865 tx_queue->queue);
866 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
867 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
868 NULL, 0, NULL);
869 }
870
871 if (rc) {
872 /* This is non-fatal; the TX path just
873 * won't use PIO for this queue
874 */
875 netif_err(efx, drv, efx->net_dev,
876 "failed to link VI %u to PIO buffer %u (%d)\n",
877 tx_queue->queue, index, rc);
878 tx_queue->piobuf = NULL;
879 } else {
880 tx_queue->piobuf =
881 nic_data->pio_write_base +
882 index * EFX_VI_PAGE_SIZE + offset;
883 tx_queue->piobuf_offset = offset;
884 netif_dbg(efx, probe, efx->net_dev,
885 "linked VI %u to PIO buffer %u offset %x addr %p\n",
886 tx_queue->queue, index,
887 tx_queue->piobuf_offset,
888 tx_queue->piobuf);
889 }
890 }
891 }
892
893 return 0;
894
895fail:
896 while (index--) {
897 MCDI_SET_DWORD(inbuf, UNLINK_PIOBUF_IN_TXQ_INSTANCE,
898 nic_data->pio_write_vi_base + index);
899 efx_mcdi_rpc(efx, MC_CMD_UNLINK_PIOBUF,
900 inbuf, MC_CMD_UNLINK_PIOBUF_IN_LEN,
901 NULL, 0, NULL);
902 }
903 return rc;
904}
905
c0795bf6
EC		 906static void efx_ef10_forget_old_piobufs(struct efx_nic *efx)
907{
908 struct efx_channel *channel;
909 struct efx_tx_queue *tx_queue;
910
911 /* All our existing PIO buffers went away */
912 efx_for_each_channel(channel, efx)
913 efx_for_each_channel_tx_queue(tx_queue, channel)
914 tx_queue->piobuf = NULL;
915}
916
183233be
BH		 917#else /* !EFX_USE_PIO */
918
919static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
920{
921 return n == 0 ? 0 : -ENOBUFS;
922}
923
924static int efx_ef10_link_piobufs(struct efx_nic *efx)
925{
926 return 0;
927}
928
929static void efx_ef10_free_piobufs(struct efx_nic *efx)
930{
931}
932
c0795bf6
EC		 933static void efx_ef10_forget_old_piobufs(struct efx_nic *efx)
934{
935}
936
183233be
BH		 937#endif /* EFX_USE_PIO */
938
8127d661
BH		 939static void efx_ef10_remove(struct efx_nic *efx)
940{
941 struct efx_ef10_nic_data *nic_data = efx->nic_data;
942 int rc;
943
f1122a34
SS		 944#ifdef CONFIG_SFC_SRIOV
945 struct efx_ef10_nic_data *nic_data_pf;
946 struct pci_dev *pci_dev_pf;
947 struct efx_nic *efx_pf;
948 struct ef10_vf *vf;
949
950 if (efx->pci_dev->is_virtfn) {
951 pci_dev_pf = efx->pci_dev->physfn;
952 if (pci_dev_pf) {
953 efx_pf = pci_get_drvdata(pci_dev_pf);
954 nic_data_pf = efx_pf->nic_data;
955 vf = nic_data_pf->vf + nic_data->vf_index;
956 vf->efx = NULL;
957 } else
958 netif_info(efx, drv, efx->net_dev,
959 "Could not get the PF id from VF\n");
960 }
961#endif
962
34813fe2
AR		 963 efx_ef10_cleanup_vlans(efx);
964 mutex_destroy(&nic_data->vlan_lock);
965
9aecda95
BH		 966 efx_ptp_remove(efx);
967
8127d661
BH		 968 efx_mcdi_mon_remove(efx);
969
8127d661
BH		 970 efx_ef10_rx_free_indir_table(efx);
971
183233be
BH		 972 if (nic_data->wc_membase)
973 iounmap(nic_data->wc_membase);
974
8127d661
BH		 975 rc = efx_ef10_free_vis(efx);
976 WARN_ON(rc != 0);
977
183233be
BH		 978 if (!nic_data->must_restore_piobufs)
979 efx_ef10_free_piobufs(efx);
980
0f5c0845
SS		 981 device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
982 device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag);
983
8127d661
BH		 984 efx_mcdi_fini(efx);
985 efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
986 kfree(nic_data);
987}
988
88a37de6
SS		 989static int efx_ef10_probe_pf(struct efx_nic *efx)
990{
991 return efx_ef10_probe(efx);
992}
993
38d27f38
AR		 994int efx_ef10_vadaptor_query(struct efx_nic *efx, unsigned int port_id,
995 u32 *port_flags, u32 *vadaptor_flags,
996 unsigned int *vlan_tags)
997{
998 struct efx_ef10_nic_data *nic_data = efx->nic_data;
999 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_QUERY_IN_LEN);
1000 MCDI_DECLARE_BUF(outbuf, MC_CMD_VADAPTOR_QUERY_OUT_LEN);
1001 size_t outlen;
1002 int rc;
1003
1004 if (nic_data->datapath_caps &
1005 (1 << MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_LBN)) {
1006 MCDI_SET_DWORD(inbuf, VADAPTOR_QUERY_IN_UPSTREAM_PORT_ID,
1007 port_id);
1008
1009 rc = efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_QUERY, inbuf, sizeof(inbuf),
1010 outbuf, sizeof(outbuf), &outlen);
1011 if (rc)
1012 return rc;
1013
1014 if (outlen < sizeof(outbuf)) {
1015 rc = -EIO;
1016 return rc;
1017 }
1018 }
1019
1020 if (port_flags)
1021 *port_flags = MCDI_DWORD(outbuf, VADAPTOR_QUERY_OUT_PORT_FLAGS);
1022 if (vadaptor_flags)
1023 *vadaptor_flags =
1024 MCDI_DWORD(outbuf, VADAPTOR_QUERY_OUT_VADAPTOR_FLAGS);
1025 if (vlan_tags)
1026 *vlan_tags =
1027 MCDI_DWORD(outbuf,
1028 VADAPTOR_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS);
1029
1030 return 0;
1031}
1032
7a186f47
DP		 1033int efx_ef10_vadaptor_alloc(struct efx_nic *efx, unsigned int port_id)
1034{
1035 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_ALLOC_IN_LEN);
1036
1037 MCDI_SET_DWORD(inbuf, VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID, port_id);
1038 return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_ALLOC, inbuf, sizeof(inbuf),
1039 NULL, 0, NULL);
1040}
1041
1042int efx_ef10_vadaptor_free(struct efx_nic *efx, unsigned int port_id)
1043{
1044 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_FREE_IN_LEN);
1045
1046 MCDI_SET_DWORD(inbuf, VADAPTOR_FREE_IN_UPSTREAM_PORT_ID, port_id);
1047 return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_FREE, inbuf, sizeof(inbuf),
1048 NULL, 0, NULL);
1049}
1050
1051int efx_ef10_vport_add_mac(struct efx_nic *efx,
1052 unsigned int port_id, u8 *mac)
1053{
1054 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_LEN);
1055
1056 MCDI_SET_DWORD(inbuf, VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID, port_id);
1057 ether_addr_copy(MCDI_PTR(inbuf, VPORT_ADD_MAC_ADDRESS_IN_MACADDR), mac);
1058
1059 return efx_mcdi_rpc(efx, MC_CMD_VPORT_ADD_MAC_ADDRESS, inbuf,
1060 sizeof(inbuf), NULL, 0, NULL);
1061}
1062
1063int efx_ef10_vport_del_mac(struct efx_nic *efx,
1064 unsigned int port_id, u8 *mac)
1065{
1066 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_LEN);
1067
1068 MCDI_SET_DWORD(inbuf, VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID, port_id);
1069 ether_addr_copy(MCDI_PTR(inbuf, VPORT_DEL_MAC_ADDRESS_IN_MACADDR), mac);
1070
1071 return efx_mcdi_rpc(efx, MC_CMD_VPORT_DEL_MAC_ADDRESS, inbuf,
1072 sizeof(inbuf), NULL, 0, NULL);
1073}
1074
88a37de6
SS		 1075#ifdef CONFIG_SFC_SRIOV
1076static int efx_ef10_probe_vf(struct efx_nic *efx)
1077{
1078 int rc;
6598dad2
DP		 1079 struct pci_dev *pci_dev_pf;
1080
1081 /* If the parent PF has no VF data structure, it doesn't know about this
1082 * VF so fail probe. The VF needs to be re-created. This can happen
1083 * if the PF driver is unloaded while the VF is assigned to a guest.
1084 */
1085 pci_dev_pf = efx->pci_dev->physfn;
1086 if (pci_dev_pf) {
1087 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
1088 struct efx_ef10_nic_data *nic_data_pf = efx_pf->nic_data;
1089
1090 if (!nic_data_pf->vf) {
1091 netif_info(efx, drv, efx->net_dev,
1092 "The VF cannot link to its parent PF; "
1093 "please destroy and re-create the VF\n");
1094 return -EBUSY;
1095 }
1096 }
88a37de6
SS		 1097
1098 rc = efx_ef10_probe(efx);
1099 if (rc)
1100 return rc;
1101
1102 rc = efx_ef10_get_vf_index(efx);
1103 if (rc)
1104 goto fail;
1105
f1122a34
SS		 1106 if (efx->pci_dev->is_virtfn) {
1107 if (efx->pci_dev->physfn) {
1108 struct efx_nic *efx_pf =
1109 pci_get_drvdata(efx->pci_dev->physfn);
1110 struct efx_ef10_nic_data *nic_data_p = efx_pf->nic_data;
1111 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1112
1113 nic_data_p->vf[nic_data->vf_index].efx = efx;
6598dad2
DP		 1114 nic_data_p->vf[nic_data->vf_index].pci_dev =
1115 efx->pci_dev;
f1122a34
SS		 1116 } else
1117 netif_info(efx, drv, efx->net_dev,
1118 "Could not get the PF id from VF\n");
1119 }
1120
88a37de6
SS		 1121 return 0;
1122
1123fail:
1124 efx_ef10_remove(efx);
1125 return rc;
1126}
1127#else
1128static int efx_ef10_probe_vf(struct efx_nic *efx __attribute__ ((unused)))
1129{
1130 return 0;
1131}
1132#endif
1133
8127d661
BH		 1134static int efx_ef10_alloc_vis(struct efx_nic *efx,
1135 unsigned int min_vis, unsigned int max_vis)
1136{
1137 MCDI_DECLARE_BUF(inbuf, MC_CMD_ALLOC_VIS_IN_LEN);
1138 MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_VIS_OUT_LEN);
1139 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1140 size_t outlen;
1141 int rc;
1142
1143 MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MIN_VI_COUNT, min_vis);
1144 MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MAX_VI_COUNT, max_vis);
1145 rc = efx_mcdi_rpc(efx, MC_CMD_ALLOC_VIS, inbuf, sizeof(inbuf),
1146 outbuf, sizeof(outbuf), &outlen);
1147 if (rc != 0)
1148 return rc;
1149
1150 if (outlen < MC_CMD_ALLOC_VIS_OUT_LEN)
1151 return -EIO;
1152
1153 netif_dbg(efx, drv, efx->net_dev, "base VI is A0x%03x\n",
1154 MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE));
1155
1156 nic_data->vi_base = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE);
1157 nic_data->n_allocated_vis = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_COUNT);
1158 return 0;
1159}
1160
183233be
BH		 1161/* Note that the failure path of this function does not free
1162 * resources, as this will be done by efx_ef10_remove().
1163 */
8127d661
BH		 1164static int efx_ef10_dimension_resources(struct efx_nic *efx)
1165{
183233be
BH		 1166 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1167 unsigned int uc_mem_map_size, wc_mem_map_size;
b0fbdae1
SS		 1168 unsigned int min_vis = max(EFX_TXQ_TYPES,
1169 efx_separate_tx_channels ? 2 : 1);
1170 unsigned int channel_vis, pio_write_vi_base, max_vis;
183233be
BH		 1171 void __iomem *membase;
1172 int rc;
1173
b0fbdae1 1174 channel_vis = max(efx->n_channels, efx->n_tx_channels * EFX_TXQ_TYPES);
8127d661 1175
183233be
BH		 1176#ifdef EFX_USE_PIO
1177 /* Try to allocate PIO buffers if wanted and if the full
1178 * number of PIO buffers would be sufficient to allocate one
1179 * copy-buffer per TX channel. Failure is non-fatal, as there
1180 * are only a small number of PIO buffers shared between all
1181 * functions of the controller.
1182 */
1183 if (efx_piobuf_size != 0 &&
c634700f 1184 nic_data->piobuf_size / efx_piobuf_size * EF10_TX_PIOBUF_COUNT >=
183233be
BH		 1185 efx->n_tx_channels) {
1186 unsigned int n_piobufs =
1187 DIV_ROUND_UP(efx->n_tx_channels,
c634700f 1188 nic_data->piobuf_size / efx_piobuf_size);
183233be
BH		 1189
1190 rc = efx_ef10_alloc_piobufs(efx, n_piobufs);
6eacfb54
TP		 1191 if (rc == -ENOSPC)
1192 netif_dbg(efx, probe, efx->net_dev,
1193 "out of PIO buffers; cannot allocate more\n");
1194 else if (rc == -EPERM)
1195 netif_dbg(efx, probe, efx->net_dev,
1196 "not permitted to allocate PIO buffers\n");
1197 else if (rc)
183233be
BH		 1198 netif_err(efx, probe, efx->net_dev,
1199 "failed to allocate PIO buffers (%d)\n", rc);
1200 else
1201 netif_dbg(efx, probe, efx->net_dev,
1202 "allocated %u PIO buffers\n", n_piobufs);
1203 }
1204#else
1205 nic_data->n_piobufs = 0;
1206#endif
1207
1208 /* PIO buffers should be mapped with write-combining enabled,
1209 * and we want to make single UC and WC mappings rather than
1210 * several of each (in fact that's the only option if host
1211 * page size is >4K). So we may allocate some extra VIs just
1212 * for writing PIO buffers through.
52ad762b 1213 *
b0fbdae1 1214 * The UC mapping contains (channel_vis - 1) complete VIs and the
52ad762b
DP		 1215 * first half of the next VI. Then the WC mapping begins with
1216 * the second half of this last VI.
183233be 1217 */
b0fbdae1 1218 uc_mem_map_size = PAGE_ALIGN((channel_vis - 1) * EFX_VI_PAGE_SIZE +
183233be
BH		 1219 ER_DZ_TX_PIOBUF);
1220 if (nic_data->n_piobufs) {
52ad762b
DP		 1221 /* pio_write_vi_base rounds down to give the number of complete
1222 * VIs inside the UC mapping.
1223 */
183233be
BH		 1224 pio_write_vi_base = uc_mem_map_size / EFX_VI_PAGE_SIZE;
1225 wc_mem_map_size = (PAGE_ALIGN((pio_write_vi_base +
1226 nic_data->n_piobufs) *
1227 EFX_VI_PAGE_SIZE) -
1228 uc_mem_map_size);
1229 max_vis = pio_write_vi_base + nic_data->n_piobufs;
1230 } else {
1231 pio_write_vi_base = 0;
1232 wc_mem_map_size = 0;
b0fbdae1 1233 max_vis = channel_vis;
183233be
BH		 1234 }
1235
1236 /* In case the last attached driver failed to free VIs, do it now */
1237 rc = efx_ef10_free_vis(efx);
1238 if (rc != 0)
1239 return rc;
1240
1241 rc = efx_ef10_alloc_vis(efx, min_vis, max_vis);
1242 if (rc != 0)
1243 return rc;
1244
b0fbdae1
SS		 1245 if (nic_data->n_allocated_vis < channel_vis) {
1246 netif_info(efx, drv, efx->net_dev,
1247 "Could not allocate enough VIs to satisfy RSS"
1248 " requirements. Performance may not be optimal.\n");
1249 /* We didn't get the VIs to populate our channels.
1250 * We could keep what we got but then we'd have more
1251 * interrupts than we need.
1252 * Instead calculate new max_channels and restart
1253 */
1254 efx->max_channels = nic_data->n_allocated_vis;
1255 efx->max_tx_channels =
1256 nic_data->n_allocated_vis / EFX_TXQ_TYPES;
1257
1258 efx_ef10_free_vis(efx);
1259 return -EAGAIN;
1260 }
1261
183233be
BH		 1262 /* If we didn't get enough VIs to map all the PIO buffers, free the
1263 * PIO buffers
1264 */
1265 if (nic_data->n_piobufs &&
1266 nic_data->n_allocated_vis <
1267 pio_write_vi_base + nic_data->n_piobufs) {
1268 netif_dbg(efx, probe, efx->net_dev,
1269 "%u VIs are not sufficient to map %u PIO buffers\n",
1270 nic_data->n_allocated_vis, nic_data->n_piobufs);
1271 efx_ef10_free_piobufs(efx);
1272 }
1273
1274 /* Shrink the original UC mapping of the memory BAR */
1275 membase = ioremap_nocache(efx->membase_phys, uc_mem_map_size);
1276 if (!membase) {
1277 netif_err(efx, probe, efx->net_dev,
1278 "could not shrink memory BAR to %x\n",
1279 uc_mem_map_size);
1280 return -ENOMEM;
1281 }
1282 iounmap(efx->membase);
1283 efx->membase = membase;
1284
1285 /* Set up the WC mapping if needed */
1286 if (wc_mem_map_size) {
1287 nic_data->wc_membase = ioremap_wc(efx->membase_phys +
1288 uc_mem_map_size,
1289 wc_mem_map_size);
1290 if (!nic_data->wc_membase) {
1291 netif_err(efx, probe, efx->net_dev,
1292 "could not allocate WC mapping of size %x\n",
1293 wc_mem_map_size);
1294 return -ENOMEM;
1295 }
1296 nic_data->pio_write_vi_base = pio_write_vi_base;
1297 nic_data->pio_write_base =
1298 nic_data->wc_membase +
1299 (pio_write_vi_base * EFX_VI_PAGE_SIZE + ER_DZ_TX_PIOBUF -
1300 uc_mem_map_size);
1301
1302 rc = efx_ef10_link_piobufs(efx);
1303 if (rc)
1304 efx_ef10_free_piobufs(efx);
1305 }
1306
1307 netif_dbg(efx, probe, efx->net_dev,
1308 "memory BAR at %pa (virtual %p+%x UC, %p+%x WC)\n",
1309 &efx->membase_phys, efx->membase, uc_mem_map_size,
1310 nic_data->wc_membase, wc_mem_map_size);
1311
1312 return 0;
8127d661
BH		 1313}
1314
1315static int efx_ef10_init_nic(struct efx_nic *efx)
1316{
1317 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1318 int rc;
1319
a915ccc9
BH		 1320 if (nic_data->must_check_datapath_caps) {
1321 rc = efx_ef10_init_datapath_caps(efx);
1322 if (rc)
1323 return rc;
1324 nic_data->must_check_datapath_caps = false;
1325 }
1326
8127d661
BH		 1327 if (nic_data->must_realloc_vis) {
1328 /* We cannot let the number of VIs change now */
1329 rc = efx_ef10_alloc_vis(efx, nic_data->n_allocated_vis,
1330 nic_data->n_allocated_vis);
1331 if (rc)
1332 return rc;
1333 nic_data->must_realloc_vis = false;
1334 }
1335
183233be
BH		 1336 if (nic_data->must_restore_piobufs && nic_data->n_piobufs) {
1337 rc = efx_ef10_alloc_piobufs(efx, nic_data->n_piobufs);
1338 if (rc == 0) {
1339 rc = efx_ef10_link_piobufs(efx);
1340 if (rc)
1341 efx_ef10_free_piobufs(efx);
1342 }
1343
6eacfb54
TP		 1344 /* Log an error on failure, but this is non-fatal.
1345 * Permission errors are less important - we've presumably
1346 * had the PIO buffer licence removed.
1347 */
1348 if (rc == -EPERM)
1349 netif_dbg(efx, drv, efx->net_dev,
1350 "not permitted to restore PIO buffers\n");
1351 else if (rc)
183233be
BH		 1352 netif_err(efx, drv, efx->net_dev,
1353 "failed to restore PIO buffers (%d)\n", rc);
1354 nic_data->must_restore_piobufs = false;
1355 }
1356
267c0157 1357 /* don't fail init if RSS setup doesn't work */
f74d1995 1358 rc = efx->type->rx_push_rss_config(efx, false, efx->rx_indir_table, NULL);
4fdda958 1359 efx->rss_active = (rc == 0);
267c0157 1360
8127d661
BH		 1361 return 0;
1362}
1363
3e336261
JC		 1364static void efx_ef10_reset_mc_allocations(struct efx_nic *efx)
1365{
1366 struct efx_ef10_nic_data *nic_data = efx->nic_data;
774ad031
DP		 1367#ifdef CONFIG_SFC_SRIOV
1368 unsigned int i;
1369#endif
3e336261
JC		 1370
1371 /* All our allocations have been reset */
1372 nic_data->must_realloc_vis = true;
1373 nic_data->must_restore_filters = true;
1374 nic_data->must_restore_piobufs = true;
c0795bf6 1375 efx_ef10_forget_old_piobufs(efx);
3e336261 1376 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
774ad031
DP		 1377
1378 /* Driver-created vswitches and vports must be re-created */
1379 nic_data->must_probe_vswitching = true;
1380 nic_data->vport_id = EVB_PORT_ID_ASSIGNED;
1381#ifdef CONFIG_SFC_SRIOV
1382 if (nic_data->vf)
1383 for (i = 0; i < efx->vf_count; i++)
1384 nic_data->vf[i].vport_id = 0;
1385#endif
3e336261
JC		 1386}
1387
087e9025
JC		 1388static enum reset_type efx_ef10_map_reset_reason(enum reset_type reason)
1389{
1390 if (reason == RESET_TYPE_MC_FAILURE)
1391 return RESET_TYPE_DATAPATH;
1392
1393 return efx_mcdi_map_reset_reason(reason);
1394}
1395
8127d661
BH		 1396static int efx_ef10_map_reset_flags(u32 *flags)
1397{
1398 enum {
1399 EF10_RESET_PORT = ((ETH_RESET_MAC | ETH_RESET_PHY) <<
1400 ETH_RESET_SHARED_SHIFT),
1401 EF10_RESET_MC = ((ETH_RESET_DMA | ETH_RESET_FILTER |
1402 ETH_RESET_OFFLOAD | ETH_RESET_MAC |
1403 ETH_RESET_PHY | ETH_RESET_MGMT) <<
1404 ETH_RESET_SHARED_SHIFT)
1405 };
1406
1407 /* We assume for now that our PCI function is permitted to
1408 * reset everything.
1409 */
1410
1411 if ((*flags & EF10_RESET_MC) == EF10_RESET_MC) {
1412 *flags &= ~EF10_RESET_MC;
1413 return RESET_TYPE_WORLD;
1414 }
1415
1416 if ((*flags & EF10_RESET_PORT) == EF10_RESET_PORT) {
1417 *flags &= ~EF10_RESET_PORT;
1418 return RESET_TYPE_ALL;
1419 }
1420
1421 /* no invisible reset implemented */
1422
1423 return -EINVAL;
1424}
1425
3e336261
JC		 1426static int efx_ef10_reset(struct efx_nic *efx, enum reset_type reset_type)
1427{
1428 int rc = efx_mcdi_reset(efx, reset_type);
1429
27324820
DP		 1430 /* Unprivileged functions return -EPERM, but need to return success
1431 * here so that the datapath is brought back up.
1432 */
1433 if (reset_type == RESET_TYPE_WORLD && rc == -EPERM)
1434 rc = 0;
1435
3e336261
JC		 1436 /* If it was a port reset, trigger reallocation of MC resources.
1437 * Note that on an MC reset nothing needs to be done now because we'll
1438 * detect the MC reset later and handle it then.
e283546c
EC		 1439 * For an FLR, we never get an MC reset event, but the MC has reset all
1440 * resources assigned to us, so we have to trigger reallocation now.
3e336261 1441 */
e283546c
EC		 1442 if ((reset_type == RESET_TYPE_ALL ||
1443 reset_type == RESET_TYPE_MCDI_TIMEOUT) && !rc)
3e336261
JC		 1444 efx_ef10_reset_mc_allocations(efx);
1445 return rc;
1446}
1447
8127d661
BH		 1448#define EF10_DMA_STAT(ext_name, mcdi_name) \
1449 [EF10_STAT_ ## ext_name] = \
1450 { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
1451#define EF10_DMA_INVIS_STAT(int_name, mcdi_name) \
1452 [EF10_STAT_ ## int_name] = \
1453 { NULL, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
1454#define EF10_OTHER_STAT(ext_name) \
1455 [EF10_STAT_ ## ext_name] = { #ext_name, 0, 0 }
e4d112e4
EC		 1456#define GENERIC_SW_STAT(ext_name) \
1457 [GENERIC_STAT_ ## ext_name] = { #ext_name, 0, 0 }
8127d661
BH		 1458
1459static const struct efx_hw_stat_desc efx_ef10_stat_desc[EF10_STAT_COUNT] = {
e80ca013
DP		 1460 EF10_DMA_STAT(port_tx_bytes, TX_BYTES),
1461 EF10_DMA_STAT(port_tx_packets, TX_PKTS),
1462 EF10_DMA_STAT(port_tx_pause, TX_PAUSE_PKTS),
1463 EF10_DMA_STAT(port_tx_control, TX_CONTROL_PKTS),
1464 EF10_DMA_STAT(port_tx_unicast, TX_UNICAST_PKTS),
1465 EF10_DMA_STAT(port_tx_multicast, TX_MULTICAST_PKTS),
1466 EF10_DMA_STAT(port_tx_broadcast, TX_BROADCAST_PKTS),
1467 EF10_DMA_STAT(port_tx_lt64, TX_LT64_PKTS),
1468 EF10_DMA_STAT(port_tx_64, TX_64_PKTS),
1469 EF10_DMA_STAT(port_tx_65_to_127, TX_65_TO_127_PKTS),
1470 EF10_DMA_STAT(port_tx_128_to_255, TX_128_TO_255_PKTS),
1471 EF10_DMA_STAT(port_tx_256_to_511, TX_256_TO_511_PKTS),
1472 EF10_DMA_STAT(port_tx_512_to_1023, TX_512_TO_1023_PKTS),
1473 EF10_DMA_STAT(port_tx_1024_to_15xx, TX_1024_TO_15XX_PKTS),
1474 EF10_DMA_STAT(port_tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS),
1475 EF10_DMA_STAT(port_rx_bytes, RX_BYTES),
1476 EF10_DMA_INVIS_STAT(port_rx_bytes_minus_good_bytes, RX_BAD_BYTES),
1477 EF10_OTHER_STAT(port_rx_good_bytes),
1478 EF10_OTHER_STAT(port_rx_bad_bytes),
1479 EF10_DMA_STAT(port_rx_packets, RX_PKTS),
1480 EF10_DMA_STAT(port_rx_good, RX_GOOD_PKTS),
1481 EF10_DMA_STAT(port_rx_bad, RX_BAD_FCS_PKTS),
1482 EF10_DMA_STAT(port_rx_pause, RX_PAUSE_PKTS),
1483 EF10_DMA_STAT(port_rx_control, RX_CONTROL_PKTS),
1484 EF10_DMA_STAT(port_rx_unicast, RX_UNICAST_PKTS),
1485 EF10_DMA_STAT(port_rx_multicast, RX_MULTICAST_PKTS),
1486 EF10_DMA_STAT(port_rx_broadcast, RX_BROADCAST_PKTS),
1487 EF10_DMA_STAT(port_rx_lt64, RX_UNDERSIZE_PKTS),
1488 EF10_DMA_STAT(port_rx_64, RX_64_PKTS),
1489 EF10_DMA_STAT(port_rx_65_to_127, RX_65_TO_127_PKTS),
1490 EF10_DMA_STAT(port_rx_128_to_255, RX_128_TO_255_PKTS),
1491 EF10_DMA_STAT(port_rx_256_to_511, RX_256_TO_511_PKTS),
1492 EF10_DMA_STAT(port_rx_512_to_1023, RX_512_TO_1023_PKTS),
1493 EF10_DMA_STAT(port_rx_1024_to_15xx, RX_1024_TO_15XX_PKTS),
1494 EF10_DMA_STAT(port_rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS),
1495 EF10_DMA_STAT(port_rx_gtjumbo, RX_GTJUMBO_PKTS),
1496 EF10_DMA_STAT(port_rx_bad_gtjumbo, RX_JABBER_PKTS),
1497 EF10_DMA_STAT(port_rx_overflow, RX_OVERFLOW_PKTS),
1498 EF10_DMA_STAT(port_rx_align_error, RX_ALIGN_ERROR_PKTS),
1499 EF10_DMA_STAT(port_rx_length_error, RX_LENGTH_ERROR_PKTS),
1500 EF10_DMA_STAT(port_rx_nodesc_drops, RX_NODESC_DROPS),
e4d112e4
EC		 1501 GENERIC_SW_STAT(rx_nodesc_trunc),
1502 GENERIC_SW_STAT(rx_noskb_drops),
e80ca013
DP		 1503 EF10_DMA_STAT(port_rx_pm_trunc_bb_overflow, PM_TRUNC_BB_OVERFLOW),
1504 EF10_DMA_STAT(port_rx_pm_discard_bb_overflow, PM_DISCARD_BB_OVERFLOW),
1505 EF10_DMA_STAT(port_rx_pm_trunc_vfifo_full, PM_TRUNC_VFIFO_FULL),
1506 EF10_DMA_STAT(port_rx_pm_discard_vfifo_full, PM_DISCARD_VFIFO_FULL),
1507 EF10_DMA_STAT(port_rx_pm_trunc_qbb, PM_TRUNC_QBB),
1508 EF10_DMA_STAT(port_rx_pm_discard_qbb, PM_DISCARD_QBB),
1509 EF10_DMA_STAT(port_rx_pm_discard_mapping, PM_DISCARD_MAPPING),
1510 EF10_DMA_STAT(port_rx_dp_q_disabled_packets, RXDP_Q_DISABLED_PKTS),
1511 EF10_DMA_STAT(port_rx_dp_di_dropped_packets, RXDP_DI_DROPPED_PKTS),
1512 EF10_DMA_STAT(port_rx_dp_streaming_packets, RXDP_STREAMING_PKTS),
1513 EF10_DMA_STAT(port_rx_dp_hlb_fetch, RXDP_HLB_FETCH_CONDITIONS),
1514 EF10_DMA_STAT(port_rx_dp_hlb_wait, RXDP_HLB_WAIT_CONDITIONS),
3c36a2ad
DP		 1515 EF10_DMA_STAT(rx_unicast, VADAPTER_RX_UNICAST_PACKETS),
1516 EF10_DMA_STAT(rx_unicast_bytes, VADAPTER_RX_UNICAST_BYTES),
1517 EF10_DMA_STAT(rx_multicast, VADAPTER_RX_MULTICAST_PACKETS),
1518 EF10_DMA_STAT(rx_multicast_bytes, VADAPTER_RX_MULTICAST_BYTES),
1519 EF10_DMA_STAT(rx_broadcast, VADAPTER_RX_BROADCAST_PACKETS),
1520 EF10_DMA_STAT(rx_broadcast_bytes, VADAPTER_RX_BROADCAST_BYTES),
1521 EF10_DMA_STAT(rx_bad, VADAPTER_RX_BAD_PACKETS),
1522 EF10_DMA_STAT(rx_bad_bytes, VADAPTER_RX_BAD_BYTES),
1523 EF10_DMA_STAT(rx_overflow, VADAPTER_RX_OVERFLOW),
1524 EF10_DMA_STAT(tx_unicast, VADAPTER_TX_UNICAST_PACKETS),
1525 EF10_DMA_STAT(tx_unicast_bytes, VADAPTER_TX_UNICAST_BYTES),
1526 EF10_DMA_STAT(tx_multicast, VADAPTER_TX_MULTICAST_PACKETS),
1527 EF10_DMA_STAT(tx_multicast_bytes, VADAPTER_TX_MULTICAST_BYTES),
1528 EF10_DMA_STAT(tx_broadcast, VADAPTER_TX_BROADCAST_PACKETS),
1529 EF10_DMA_STAT(tx_broadcast_bytes, VADAPTER_TX_BROADCAST_BYTES),
1530 EF10_DMA_STAT(tx_bad, VADAPTER_TX_BAD_PACKETS),
1531 EF10_DMA_STAT(tx_bad_bytes, VADAPTER_TX_BAD_BYTES),
1532 EF10_DMA_STAT(tx_overflow, VADAPTER_TX_OVERFLOW),
8127d661
BH		 1533};
1534
e80ca013
DP		 1535#define HUNT_COMMON_STAT_MASK ((1ULL << EF10_STAT_port_tx_bytes) | \
1536 (1ULL << EF10_STAT_port_tx_packets) | \
1537 (1ULL << EF10_STAT_port_tx_pause) | \
1538 (1ULL << EF10_STAT_port_tx_unicast) | \
1539 (1ULL << EF10_STAT_port_tx_multicast) | \
1540 (1ULL << EF10_STAT_port_tx_broadcast) | \
1541 (1ULL << EF10_STAT_port_rx_bytes) | \
1542 (1ULL << \
1543 EF10_STAT_port_rx_bytes_minus_good_bytes) | \
1544 (1ULL << EF10_STAT_port_rx_good_bytes) | \
1545 (1ULL << EF10_STAT_port_rx_bad_bytes) | \
1546 (1ULL << EF10_STAT_port_rx_packets) | \
1547 (1ULL << EF10_STAT_port_rx_good) | \
1548 (1ULL << EF10_STAT_port_rx_bad) | \
1549 (1ULL << EF10_STAT_port_rx_pause) | \
1550 (1ULL << EF10_STAT_port_rx_control) | \
1551 (1ULL << EF10_STAT_port_rx_unicast) | \
1552 (1ULL << EF10_STAT_port_rx_multicast) | \
1553 (1ULL << EF10_STAT_port_rx_broadcast) | \
1554 (1ULL << EF10_STAT_port_rx_lt64) | \
1555 (1ULL << EF10_STAT_port_rx_64) | \
1556 (1ULL << EF10_STAT_port_rx_65_to_127) | \
1557 (1ULL << EF10_STAT_port_rx_128_to_255) | \
1558 (1ULL << EF10_STAT_port_rx_256_to_511) | \
1559 (1ULL << EF10_STAT_port_rx_512_to_1023) |\
1560 (1ULL << EF10_STAT_port_rx_1024_to_15xx) |\
1561 (1ULL << EF10_STAT_port_rx_15xx_to_jumbo) |\
1562 (1ULL << EF10_STAT_port_rx_gtjumbo) | \
1563 (1ULL << EF10_STAT_port_rx_bad_gtjumbo) |\
1564 (1ULL << EF10_STAT_port_rx_overflow) | \
1565 (1ULL << EF10_STAT_port_rx_nodesc_drops) |\
e4d112e4
EC		 1566 (1ULL << GENERIC_STAT_rx_nodesc_trunc) | \
1567 (1ULL << GENERIC_STAT_rx_noskb_drops))
8127d661 1568
69b365c3
EC		 1569/* On 7000 series NICs, these statistics are only provided by the 10G MAC.
1570 * For a 10G/40G switchable port we do not expose these because they might
1571 * not include all the packets they should.
1572 * On 8000 series NICs these statistics are always provided.
8127d661 1573 */
e80ca013
DP		 1574#define HUNT_10G_ONLY_STAT_MASK ((1ULL << EF10_STAT_port_tx_control) | \
1575 (1ULL << EF10_STAT_port_tx_lt64) | \
1576 (1ULL << EF10_STAT_port_tx_64) | \
1577 (1ULL << EF10_STAT_port_tx_65_to_127) |\
1578 (1ULL << EF10_STAT_port_tx_128_to_255) |\
1579 (1ULL << EF10_STAT_port_tx_256_to_511) |\
1580 (1ULL << EF10_STAT_port_tx_512_to_1023) |\
1581 (1ULL << EF10_STAT_port_tx_1024_to_15xx) |\
1582 (1ULL << EF10_STAT_port_tx_15xx_to_jumbo))
8127d661
BH		 1583
1584/* These statistics are only provided by the 40G MAC. For a 10G/40G
1585 * switchable port we do expose these because the errors will otherwise
1586 * be silent.
1587 */
e80ca013
DP		 1588#define HUNT_40G_EXTRA_STAT_MASK ((1ULL << EF10_STAT_port_rx_align_error) |\
1589 (1ULL << EF10_STAT_port_rx_length_error))
8127d661 1590
568d7a00
EC		 1591/* These statistics are only provided if the firmware supports the
1592 * capability PM_AND_RXDP_COUNTERS.
1593 */
1594#define HUNT_PM_AND_RXDP_STAT_MASK ( \
e80ca013
DP		 1595 (1ULL << EF10_STAT_port_rx_pm_trunc_bb_overflow) | \
1596 (1ULL << EF10_STAT_port_rx_pm_discard_bb_overflow) | \
1597 (1ULL << EF10_STAT_port_rx_pm_trunc_vfifo_full) | \
1598 (1ULL << EF10_STAT_port_rx_pm_discard_vfifo_full) | \
1599 (1ULL << EF10_STAT_port_rx_pm_trunc_qbb) | \
1600 (1ULL << EF10_STAT_port_rx_pm_discard_qbb) | \
1601 (1ULL << EF10_STAT_port_rx_pm_discard_mapping) | \
1602 (1ULL << EF10_STAT_port_rx_dp_q_disabled_packets) | \
1603 (1ULL << EF10_STAT_port_rx_dp_di_dropped_packets) | \
1604 (1ULL << EF10_STAT_port_rx_dp_streaming_packets) | \
1605 (1ULL << EF10_STAT_port_rx_dp_hlb_fetch) | \
1606 (1ULL << EF10_STAT_port_rx_dp_hlb_wait))
568d7a00 1607
4bae913b 1608static u64 efx_ef10_raw_stat_mask(struct efx_nic *efx)
8127d661 1609{
4bae913b 1610 u64 raw_mask = HUNT_COMMON_STAT_MASK;
8127d661 1611 u32 port_caps = efx_mcdi_phy_get_caps(efx);
568d7a00 1612 struct efx_ef10_nic_data *nic_data = efx->nic_data;
8127d661 1613
3c36a2ad
DP		 1614 if (!(efx->mcdi->fn_flags &
1615 1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL))
1616 return 0;
1617
69b365c3 1618 if (port_caps & (1 << MC_CMD_PHY_CAP_40000FDX_LBN)) {
4bae913b 1619 raw_mask |= HUNT_40G_EXTRA_STAT_MASK;
69b365c3
EC		 1620 /* 8000 series have everything even at 40G */
1621 if (nic_data->datapath_caps2 &
1622 (1 << MC_CMD_GET_CAPABILITIES_V2_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN))
1623 raw_mask |= HUNT_10G_ONLY_STAT_MASK;
1624 } else {
4bae913b 1625 raw_mask |= HUNT_10G_ONLY_STAT_MASK;
69b365c3 1626 }
568d7a00
EC		 1627
1628 if (nic_data->datapath_caps &
1629 (1 << MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN))
1630 raw_mask |= HUNT_PM_AND_RXDP_STAT_MASK;
1631
4bae913b
EC		 1632 return raw_mask;
1633}
1634
1635static void efx_ef10_get_stat_mask(struct efx_nic *efx, unsigned long *mask)
1636{
d94619cd 1637 struct efx_ef10_nic_data *nic_data = efx->nic_data;
3c36a2ad
DP		 1638 u64 raw_mask[2];
1639
1640 raw_mask[0] = efx_ef10_raw_stat_mask(efx);
1641
d94619cd
DP		 1642 /* Only show vadaptor stats when EVB capability is present */
1643 if (nic_data->datapath_caps &
1644 (1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN)) {
1645 raw_mask[0] |= ~((1ULL << EF10_STAT_rx_unicast) - 1);
1646 raw_mask[1] = (1ULL << (EF10_STAT_COUNT - 63)) - 1;
1647 } else {
1648 raw_mask[1] = 0;
1649 }
4bae913b
EC		 1650
1651#if BITS_PER_LONG == 64
e70c70c3 1652 BUILD_BUG_ON(BITS_TO_LONGS(EF10_STAT_COUNT) != 2);
3c36a2ad
DP		 1653 mask[0] = raw_mask[0];
1654 mask[1] = raw_mask[1];
4bae913b 1655#else
e70c70c3 1656 BUILD_BUG_ON(BITS_TO_LONGS(EF10_STAT_COUNT) != 3);
3c36a2ad
DP		 1657 mask[0] = raw_mask[0] & 0xffffffff;
1658 mask[1] = raw_mask[0] >> 32;
1659 mask[2] = raw_mask[1] & 0xffffffff;
4bae913b 1660#endif
8127d661
BH		 1661}
1662
1663static size_t efx_ef10_describe_stats(struct efx_nic *efx, u8 *names)
1664{
4bae913b
EC		 1665 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1666
1667 efx_ef10_get_stat_mask(efx, mask);
8127d661 1668 return efx_nic_describe_stats(efx_ef10_stat_desc, EF10_STAT_COUNT,
4bae913b 1669 mask, names);
8127d661
BH		 1670}
1671
d7788196
DP		 1672static size_t efx_ef10_update_stats_common(struct efx_nic *efx, u64 *full_stats,
1673 struct rtnl_link_stats64 *core_stats)
1674{
1675 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1676 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1677 u64 *stats = nic_data->stats;
1678 size_t stats_count = 0, index;
1679
1680 efx_ef10_get_stat_mask(efx, mask);
1681
1682 if (full_stats) {
1683 for_each_set_bit(index, mask, EF10_STAT_COUNT) {
1684 if (efx_ef10_stat_desc[index].name) {
1685 *full_stats++ = stats[index];
1686 ++stats_count;
1687 }
1688 }
1689 }
1690
fbe4307e
BK		 1691 if (!core_stats)
1692 return stats_count;
1693
1694 if (nic_data->datapath_caps &
1695 1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN) {
1696 /* Use vadaptor stats. */
0fc95fca
DP		 1697 core_stats->rx_packets = stats[EF10_STAT_rx_unicast] +
1698 stats[EF10_STAT_rx_multicast] +
1699 stats[EF10_STAT_rx_broadcast];
1700 core_stats->tx_packets = stats[EF10_STAT_tx_unicast] +
1701 stats[EF10_STAT_tx_multicast] +
1702 stats[EF10_STAT_tx_broadcast];
1703 core_stats->rx_bytes = stats[EF10_STAT_rx_unicast_bytes] +
1704 stats[EF10_STAT_rx_multicast_bytes] +
1705 stats[EF10_STAT_rx_broadcast_bytes];
1706 core_stats->tx_bytes = stats[EF10_STAT_tx_unicast_bytes] +
1707 stats[EF10_STAT_tx_multicast_bytes] +
1708 stats[EF10_STAT_tx_broadcast_bytes];
1709 core_stats->rx_dropped = stats[GENERIC_STAT_rx_nodesc_trunc] +
d7788196 1710 stats[GENERIC_STAT_rx_noskb_drops];
0fc95fca
DP		 1711 core_stats->multicast = stats[EF10_STAT_rx_multicast];
1712 core_stats->rx_crc_errors = stats[EF10_STAT_rx_bad];
1713 core_stats->rx_fifo_errors = stats[EF10_STAT_rx_overflow];
1714 core_stats->rx_errors = core_stats->rx_crc_errors;
1715 core_stats->tx_errors = stats[EF10_STAT_tx_bad];
fbe4307e
BK		 1716 } else {
1717 /* Use port stats. */
1718 core_stats->rx_packets = stats[EF10_STAT_port_rx_packets];
1719 core_stats->tx_packets = stats[EF10_STAT_port_tx_packets];
1720 core_stats->rx_bytes = stats[EF10_STAT_port_rx_bytes];
1721 core_stats->tx_bytes = stats[EF10_STAT_port_tx_bytes];
1722 core_stats->rx_dropped = stats[EF10_STAT_port_rx_nodesc_drops] +
1723 stats[GENERIC_STAT_rx_nodesc_trunc] +
1724 stats[GENERIC_STAT_rx_noskb_drops];
1725 core_stats->multicast = stats[EF10_STAT_port_rx_multicast];
1726 core_stats->rx_length_errors =
1727 stats[EF10_STAT_port_rx_gtjumbo] +
1728 stats[EF10_STAT_port_rx_length_error];
1729 core_stats->rx_crc_errors = stats[EF10_STAT_port_rx_bad];
1730 core_stats->rx_frame_errors =
1731 stats[EF10_STAT_port_rx_align_error];
1732 core_stats->rx_fifo_errors = stats[EF10_STAT_port_rx_overflow];
1733 core_stats->rx_errors = (core_stats->rx_length_errors +
1734 core_stats->rx_crc_errors +
1735 core_stats->rx_frame_errors);
d7788196
DP		 1736 }
1737
1738 return stats_count;
1739}
1740
1741static int efx_ef10_try_update_nic_stats_pf(struct efx_nic *efx)
8127d661
BH		 1742{
1743 struct efx_ef10_nic_data *nic_data = efx->nic_data;
4bae913b 1744 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
8127d661
BH		 1745 __le64 generation_start, generation_end;
1746 u64 *stats = nic_data->stats;
1747 __le64 *dma_stats;
1748
4bae913b
EC		 1749 efx_ef10_get_stat_mask(efx, mask);
1750
8127d661 1751 dma_stats = efx->stats_buffer.addr;
8127d661
BH		 1752
1753 generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
1754 if (generation_end == EFX_MC_STATS_GENERATION_INVALID)
1755 return 0;
1756 rmb();
4bae913b 1757 efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask,
8127d661 1758 stats, efx->stats_buffer.addr, false);
d546a893 1759 rmb();
8127d661
BH		 1760 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
1761 if (generation_end != generation_start)
1762 return -EAGAIN;
1763
1764 /* Update derived statistics */
e80ca013
DP		 1765 efx_nic_fix_nodesc_drop_stat(efx,
1766 &stats[EF10_STAT_port_rx_nodesc_drops]);
1767 stats[EF10_STAT_port_rx_good_bytes] =
1768 stats[EF10_STAT_port_rx_bytes] -
1769 stats[EF10_STAT_port_rx_bytes_minus_good_bytes];
1770 efx_update_diff_stat(&stats[EF10_STAT_port_rx_bad_bytes],
1771 stats[EF10_STAT_port_rx_bytes_minus_good_bytes]);
e4d112e4 1772 efx_update_sw_stats(efx, stats);
8127d661
BH		 1773 return 0;
1774}
1775
1776
d7788196
DP		 1777static size_t efx_ef10_update_stats_pf(struct efx_nic *efx, u64 *full_stats,
1778 struct rtnl_link_stats64 *core_stats)
8127d661 1779{
8127d661
BH		 1780 int retry;
1781
1782 /* If we're unlucky enough to read statistics during the DMA, wait
1783 * up to 10ms for it to finish (typically takes <500us)
1784 */
1785 for (retry = 0; retry < 100; ++retry) {
d7788196 1786 if (efx_ef10_try_update_nic_stats_pf(efx) == 0)
8127d661
BH		 1787 break;
1788 udelay(100);
1789 }
1790
d7788196
DP		 1791 return efx_ef10_update_stats_common(efx, full_stats, core_stats);
1792}
8127d661 1793
d7788196
DP		 1794static int efx_ef10_try_update_nic_stats_vf(struct efx_nic *efx)
1795{
1796 MCDI_DECLARE_BUF(inbuf, MC_CMD_MAC_STATS_IN_LEN);
1797 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1798 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1799 __le64 generation_start, generation_end;
1800 u64 *stats = nic_data->stats;
1801 u32 dma_len = MC_CMD_MAC_NSTATS * sizeof(u64);
1802 struct efx_buffer stats_buf;
1803 __le64 *dma_stats;
1804 int rc;
1805
f00bf230
DP		 1806 spin_unlock_bh(&efx->stats_lock);
1807
1808 if (in_interrupt()) {
1809 /* If in atomic context, cannot update stats. Just update the
1810 * software stats and return so the caller can continue.
1811 */
1812 spin_lock_bh(&efx->stats_lock);
1813 efx_update_sw_stats(efx, stats);
1814 return 0;
1815 }
1816
d7788196
DP		 1817 efx_ef10_get_stat_mask(efx, mask);
1818
1819 rc = efx_nic_alloc_buffer(efx, &stats_buf, dma_len, GFP_ATOMIC);
f00bf230
DP		 1820 if (rc) {
1821 spin_lock_bh(&efx->stats_lock);
d7788196 1822 return rc;
f00bf230 1823 }
d7788196
DP		 1824
1825 dma_stats = stats_buf.addr;
1826 dma_stats[MC_CMD_MAC_GENERATION_END] = EFX_MC_STATS_GENERATION_INVALID;
1827
1828 MCDI_SET_QWORD(inbuf, MAC_STATS_IN_DMA_ADDR, stats_buf.dma_addr);
1829 MCDI_POPULATE_DWORD_1(inbuf, MAC_STATS_IN_CMD,
0fc95fca 1830 MAC_STATS_IN_DMA, 1);
d7788196
DP		 1831 MCDI_SET_DWORD(inbuf, MAC_STATS_IN_DMA_LEN, dma_len);
1832 MCDI_SET_DWORD(inbuf, MAC_STATS_IN_PORT_ID, EVB_PORT_ID_ASSIGNED);
1833
6dd4859b
DP		 1834 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_MAC_STATS, inbuf, sizeof(inbuf),
1835 NULL, 0, NULL);
d7788196 1836 spin_lock_bh(&efx->stats_lock);
6dd4859b
DP		 1837 if (rc) {
1838 /* Expect ENOENT if DMA queues have not been set up */
1839 if (rc != -ENOENT || atomic_read(&efx->active_queues))
1840 efx_mcdi_display_error(efx, MC_CMD_MAC_STATS,
1841 sizeof(inbuf), NULL, 0, rc);
d7788196 1842 goto out;
6dd4859b 1843 }
d7788196
DP		 1844
1845 generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
0fc95fca
DP		 1846 if (generation_end == EFX_MC_STATS_GENERATION_INVALID) {
1847 WARN_ON_ONCE(1);
d7788196 1848 goto out;
0fc95fca 1849 }
d7788196
DP		 1850 rmb();
1851 efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask,
1852 stats, stats_buf.addr, false);
1853 rmb();
1854 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
1855 if (generation_end != generation_start) {
1856 rc = -EAGAIN;
1857 goto out;
8127d661
BH		 1858 }
1859
d7788196
DP		 1860 efx_update_sw_stats(efx, stats);
1861out:
1862 efx_nic_free_buffer(efx, &stats_buf);
1863 return rc;
1864}
1865
1866static size_t efx_ef10_update_stats_vf(struct efx_nic *efx, u64 *full_stats,
1867 struct rtnl_link_stats64 *core_stats)
1868{
1869 if (efx_ef10_try_update_nic_stats_vf(efx))
1870 return 0;
1871
1872 return efx_ef10_update_stats_common(efx, full_stats, core_stats);
8127d661
BH		 1873}
1874
1875static void efx_ef10_push_irq_moderation(struct efx_channel *channel)
1876{
1877 struct efx_nic *efx = channel->efx;
539de7c5 1878 unsigned int mode, usecs;
8127d661
BH		 1879 efx_dword_t timer_cmd;
1880
539de7c5 1881 if (channel->irq_moderation_us) {
8127d661 1882 mode = 3;
539de7c5 1883 usecs = channel->irq_moderation_us;
8127d661
BH		 1884 } else {
1885 mode = 0;
539de7c5 1886 usecs = 0;
8127d661
BH		 1887 }
1888
539de7c5
BK		 1889 if (EFX_EF10_WORKAROUND_61265(efx)) {
1890 MCDI_DECLARE_BUF(inbuf, MC_CMD_SET_EVQ_TMR_IN_LEN);
1891 unsigned int ns = usecs * 1000;
1892
1893 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_INSTANCE,
1894 channel->channel);
1895 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_LOAD_REQ_NS, ns);
1896 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_RELOAD_REQ_NS, ns);
1897 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_MODE, mode);
1898
1899 efx_mcdi_rpc_async(efx, MC_CMD_SET_EVQ_TMR,
1900 inbuf, sizeof(inbuf), 0, NULL, 0);
1901 } else if (EFX_EF10_WORKAROUND_35388(efx)) {
1902 unsigned int ticks = efx_usecs_to_ticks(efx, usecs);
1903
8127d661
BH		 1904 EFX_POPULATE_DWORD_3(timer_cmd, ERF_DD_EVQ_IND_TIMER_FLAGS,
1905 EFE_DD_EVQ_IND_TIMER_FLAGS,
1906 ERF_DD_EVQ_IND_TIMER_MODE, mode,
539de7c5 1907 ERF_DD_EVQ_IND_TIMER_VAL, ticks);
8127d661
BH		 1908 efx_writed_page(efx, &timer_cmd, ER_DD_EVQ_INDIRECT,
1909 channel->channel);
1910 } else {
539de7c5
BK		 1911 unsigned int ticks = efx_usecs_to_ticks(efx, usecs);
1912
8127d661 1913 EFX_POPULATE_DWORD_2(timer_cmd, ERF_DZ_TC_TIMER_MODE, mode,
539de7c5 1914 ERF_DZ_TC_TIMER_VAL, ticks);
8127d661
BH		 1915 efx_writed_page(efx, &timer_cmd, ER_DZ_EVQ_TMR,
1916 channel->channel);
1917 }
1918}
1919
02246a7f
SS		 1920static void efx_ef10_get_wol_vf(struct efx_nic *efx,
1921 struct ethtool_wolinfo *wol) {}
1922
1923static int efx_ef10_set_wol_vf(struct efx_nic *efx, u32 type)
1924{
1925 return -EOPNOTSUPP;
1926}
1927
8127d661
BH		 1928static void efx_ef10_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
1929{
1930 wol->supported = 0;
1931 wol->wolopts = 0;
1932 memset(&wol->sopass, 0, sizeof(wol->sopass));
1933}
1934
1935static int efx_ef10_set_wol(struct efx_nic *efx, u32 type)
1936{
1937 if (type != 0)
1938 return -EINVAL;
1939 return 0;
1940}
1941
1942static void efx_ef10_mcdi_request(struct efx_nic *efx,
1943 const efx_dword_t *hdr, size_t hdr_len,
1944 const efx_dword_t *sdu, size_t sdu_len)
1945{
1946 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1947 u8 *pdu = nic_data->mcdi_buf.addr;
1948
1949 memcpy(pdu, hdr, hdr_len);
1950 memcpy(pdu + hdr_len, sdu, sdu_len);
1951 wmb();
1952
1953 /* The hardware provides 'low' and 'high' (doorbell) registers
1954 * for passing the 64-bit address of an MCDI request to
1955 * firmware. However the dwords are swapped by firmware. The
1956 * least significant bits of the doorbell are then 0 for all
1957 * MCDI requests due to alignment.
1958 */
1959 _efx_writed(efx, cpu_to_le32((u64)nic_data->mcdi_buf.dma_addr >> 32),
1960 ER_DZ_MC_DB_LWRD);
1961 _efx_writed(efx, cpu_to_le32((u32)nic_data->mcdi_buf.dma_addr),
1962 ER_DZ_MC_DB_HWRD);
1963}
1964
1965static bool efx_ef10_mcdi_poll_response(struct efx_nic *efx)
1966{
1967 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1968 const efx_dword_t hdr = *(const efx_dword_t *)nic_data->mcdi_buf.addr;
1969
1970 rmb();
1971 return EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE);
1972}
1973
1974static void
1975efx_ef10_mcdi_read_response(struct efx_nic *efx, efx_dword_t *outbuf,
1976 size_t offset, size_t outlen)
1977{
1978 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1979 const u8 *pdu = nic_data->mcdi_buf.addr;
1980
1981 memcpy(outbuf, pdu + offset, outlen);
1982}
1983
c577e59e
DP		 1984static void efx_ef10_mcdi_reboot_detected(struct efx_nic *efx)
1985{
1986 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1987
1988 /* All our allocations have been reset */
1989 efx_ef10_reset_mc_allocations(efx);
1990
1991 /* The datapath firmware might have been changed */
1992 nic_data->must_check_datapath_caps = true;
1993
1994 /* MAC statistics have been cleared on the NIC; clear the local
1995 * statistic that we update with efx_update_diff_stat().
1996 */
1997 nic_data->stats[EF10_STAT_port_rx_bad_bytes] = 0;
1998}
1999
8127d661
BH		 2000static int efx_ef10_mcdi_poll_reboot(struct efx_nic *efx)
2001{
2002 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2003 int rc;
2004
2005 rc = efx_ef10_get_warm_boot_count(efx);
2006 if (rc < 0) {
2007 /* The firmware is presumably in the process of
2008 * rebooting. However, we are supposed to report each
2009 * reboot just once, so we must only do that once we
2010 * can read and store the updated warm boot count.
2011 */
2012 return 0;
2013 }
2014
2015 if (rc == nic_data->warm_boot_count)
2016 return 0;
2017
2018 nic_data->warm_boot_count = rc;
c577e59e 2019 efx_ef10_mcdi_reboot_detected(efx);
869070c5 2020
8127d661
BH		 2021 return -EIO;
2022}
2023
2024/* Handle an MSI interrupt
2025 *
2026 * Handle an MSI hardware interrupt. This routine schedules event
2027 * queue processing. No interrupt acknowledgement cycle is necessary.
2028 * Also, we never need to check that the interrupt is for us, since
2029 * MSI interrupts cannot be shared.
2030 */
2031static irqreturn_t efx_ef10_msi_interrupt(int irq, void *dev_id)
2032{
2033 struct efx_msi_context *context = dev_id;
2034 struct efx_nic *efx = context->efx;
2035
2036 netif_vdbg(efx, intr, efx->net_dev,
2037 "IRQ %d on CPU %d\n", irq, raw_smp_processor_id());
2038
2039 if (likely(ACCESS_ONCE(efx->irq_soft_enabled))) {
2040 /* Note test interrupts */
2041 if (context->index == efx->irq_level)
2042 efx->last_irq_cpu = raw_smp_processor_id();
2043
2044 /* Schedule processing of the channel */
2045 efx_schedule_channel_irq(efx->channel[context->index]);
2046 }
2047
2048 return IRQ_HANDLED;
2049}
2050
2051static irqreturn_t efx_ef10_legacy_interrupt(int irq, void *dev_id)
2052{
2053 struct efx_nic *efx = dev_id;
2054 bool soft_enabled = ACCESS_ONCE(efx->irq_soft_enabled);
2055 struct efx_channel *channel;
2056 efx_dword_t reg;
2057 u32 queues;
2058
2059 /* Read the ISR which also ACKs the interrupts */
2060 efx_readd(efx, &reg, ER_DZ_BIU_INT_ISR);
2061 queues = EFX_DWORD_FIELD(reg, ERF_DZ_ISR_REG);
2062
2063 if (queues == 0)
2064 return IRQ_NONE;
2065
2066 if (likely(soft_enabled)) {
2067 /* Note test interrupts */
2068 if (queues & (1U << efx->irq_level))
2069 efx->last_irq_cpu = raw_smp_processor_id();
2070
2071 efx_for_each_channel(channel, efx) {
2072 if (queues & 1)
2073 efx_schedule_channel_irq(channel);
2074 queues >>= 1;
2075 }
2076 }
2077
2078 netif_vdbg(efx, intr, efx->net_dev,
2079 "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
2080 irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
2081
2082 return IRQ_HANDLED;
2083}
2084
942e298e 2085static int efx_ef10_irq_test_generate(struct efx_nic *efx)
8127d661
BH		 2086{
2087 MCDI_DECLARE_BUF(inbuf, MC_CMD_TRIGGER_INTERRUPT_IN_LEN);
2088
942e298e
JC		 2089 if (efx_mcdi_set_workaround(efx, MC_CMD_WORKAROUND_BUG41750, true,
2090 NULL) == 0)
2091 return -ENOTSUPP;
2092
8127d661
BH		 2093 BUILD_BUG_ON(MC_CMD_TRIGGER_INTERRUPT_OUT_LEN != 0);
2094
2095 MCDI_SET_DWORD(inbuf, TRIGGER_INTERRUPT_IN_INTR_LEVEL, efx->irq_level);
942e298e 2096 return efx_mcdi_rpc(efx, MC_CMD_TRIGGER_INTERRUPT,
8127d661
BH		 2097 inbuf, sizeof(inbuf), NULL, 0, NULL);
2098}
2099
2100static int efx_ef10_tx_probe(struct efx_tx_queue *tx_queue)
2101{
2102 return efx_nic_alloc_buffer(tx_queue->efx, &tx_queue->txd.buf,
2103 (tx_queue->ptr_mask + 1) *
2104 sizeof(efx_qword_t),
2105 GFP_KERNEL);
2106}
2107
2108/* This writes to the TX_DESC_WPTR and also pushes data */
2109static inline void efx_ef10_push_tx_desc(struct efx_tx_queue *tx_queue,
2110 const efx_qword_t *txd)
2111{
2112 unsigned int write_ptr;
2113 efx_oword_t reg;
2114
2115 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
2116 EFX_POPULATE_OWORD_1(reg, ERF_DZ_TX_DESC_WPTR, write_ptr);
2117 reg.qword[0] = *txd;
2118 efx_writeo_page(tx_queue->efx, &reg,
2119 ER_DZ_TX_DESC_UPD, tx_queue->queue);
2120}
2121
e9117e50
BK		 2122/* Add Firmware-Assisted TSO v2 option descriptors to a queue.
2123 */
2124static int efx_ef10_tx_tso_desc(struct efx_tx_queue *tx_queue,
2125 struct sk_buff *skb,
2126 bool *data_mapped)
2127{
2128 struct efx_tx_buffer *buffer;
2129 struct tcphdr *tcp;
2130 struct iphdr *ip;
2131
2132 u16 ipv4_id;
2133 u32 seqnum;
2134 u32 mss;
2135
e01b16a7 2136 EFX_WARN_ON_ONCE_PARANOID(tx_queue->tso_version != 2);
e9117e50
BK		 2137
2138 mss = skb_shinfo(skb)->gso_size;
2139
2140 if (unlikely(mss < 4)) {
2141 WARN_ONCE(1, "MSS of %u is too small for TSO v2\n", mss);
2142 return -EINVAL;
2143 }
2144
2145 ip = ip_hdr(skb);
2146 if (ip->version == 4) {
2147 /* Modify IPv4 header if needed. */
2148 ip->tot_len = 0;
2149 ip->check = 0;
2150 ipv4_id = ip->id;
2151 } else {
2152 /* Modify IPv6 header if needed. */
2153 struct ipv6hdr *ipv6 = ipv6_hdr(skb);
2154
2155 ipv6->payload_len = 0;
2156 ipv4_id = 0;
2157 }
2158
2159 tcp = tcp_hdr(skb);
2160 seqnum = ntohl(tcp->seq);
2161
2162 buffer = efx_tx_queue_get_insert_buffer(tx_queue);
2163
2164 buffer->flags = EFX_TX_BUF_OPTION;
2165 buffer->len = 0;
2166 buffer->unmap_len = 0;
2167 EFX_POPULATE_QWORD_5(buffer->option,
2168 ESF_DZ_TX_DESC_IS_OPT, 1,
2169 ESF_DZ_TX_OPTION_TYPE, ESE_DZ_TX_OPTION_DESC_TSO,
2170 ESF_DZ_TX_TSO_OPTION_TYPE,
2171 ESE_DZ_TX_TSO_OPTION_DESC_FATSO2A,
2172 ESF_DZ_TX_TSO_IP_ID, ipv4_id,
2173 ESF_DZ_TX_TSO_TCP_SEQNO, seqnum
2174 );
2175 ++tx_queue->insert_count;
2176
2177 buffer = efx_tx_queue_get_insert_buffer(tx_queue);
2178
2179 buffer->flags = EFX_TX_BUF_OPTION;
2180 buffer->len = 0;
2181 buffer->unmap_len = 0;
2182 EFX_POPULATE_QWORD_4(buffer->option,
2183 ESF_DZ_TX_DESC_IS_OPT, 1,
2184 ESF_DZ_TX_OPTION_TYPE, ESE_DZ_TX_OPTION_DESC_TSO,
2185 ESF_DZ_TX_TSO_OPTION_TYPE,
2186 ESE_DZ_TX_TSO_OPTION_DESC_FATSO2B,
2187 ESF_DZ_TX_TSO_TCP_MSS, mss
2188 );
2189 ++tx_queue->insert_count;
2190
2191 return 0;
2192}
2193
46d1efd8
EC		 2194static u32 efx_ef10_tso_versions(struct efx_nic *efx)
2195{
2196 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2197 u32 tso_versions = 0;
2198
2199 if (nic_data->datapath_caps &
2200 (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN))
2201 tso_versions |= BIT(1);
2202 if (nic_data->datapath_caps2 &
2203 (1 << MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_LBN))
2204 tso_versions |= BIT(2);
2205 return tso_versions;
2206}
2207
8127d661
BH		 2208static void efx_ef10_tx_init(struct efx_tx_queue *tx_queue)
2209{
2210 MCDI_DECLARE_BUF(inbuf, MC_CMD_INIT_TXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
2211 EFX_BUF_SIZE));
8127d661
BH		 2212 bool csum_offload = tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD;
2213 size_t entries = tx_queue->txd.buf.len / EFX_BUF_SIZE;
2214 struct efx_channel *channel = tx_queue->channel;
2215 struct efx_nic *efx = tx_queue->efx;
45b2449e 2216 struct efx_ef10_nic_data *nic_data = efx->nic_data;
e9117e50 2217 bool tso_v2 = false;
aa09a3da 2218 size_t inlen;
8127d661
BH		 2219 dma_addr_t dma_addr;
2220 efx_qword_t *txd;
2221 int rc;
2222 int i;
aa09a3da 2223 BUILD_BUG_ON(MC_CMD_INIT_TXQ_OUT_LEN != 0);
8127d661 2224
e9117e50
BK		 2225 /* TSOv2 is a limited resource that can only be configured on a limited
2226 * number of queues. TSO without checksum offload is not really a thing,
2227 * so we only enable it for those queues.
e9117e50
BK		 2228 */
2229 if (csum_offload && (nic_data->datapath_caps2 &
2230 (1 << MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_LBN))) {
2231 tso_v2 = true;
2232 netif_dbg(efx, hw, efx->net_dev, "Using TSOv2 for channel %u\n",
2233 channel->channel);
2234 }
2235
8127d661
BH		 2236 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_SIZE, tx_queue->ptr_mask + 1);
2237 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_TARGET_EVQ, channel->channel);
2238 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_LABEL, tx_queue->queue);
2239 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_INSTANCE, tx_queue->queue);
8127d661 2240 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_OWNER_ID, 0);
45b2449e 2241 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_PORT_ID, nic_data->vport_id);
8127d661
BH		 2242
2243 dma_addr = tx_queue->txd.buf.dma_addr;
2244
2245 netif_dbg(efx, hw, efx->net_dev, "pushing TXQ %d. %zu entries (%llx)\n",
2246 tx_queue->queue, entries, (u64)dma_addr);
2247
2248 for (i = 0; i < entries; ++i) {
2249 MCDI_SET_ARRAY_QWORD(inbuf, INIT_TXQ_IN_DMA_ADDR, i, dma_addr);
2250 dma_addr += EFX_BUF_SIZE;
2251 }
2252
2253 inlen = MC_CMD_INIT_TXQ_IN_LEN(entries);
2254
e638ee1d
EC		 2255 do {
2256 MCDI_POPULATE_DWORD_3(inbuf, INIT_TXQ_IN_FLAGS,
2257 /* This flag was removed from mcdi_pcol.h for
2258 * the non-_EXT version of INIT_TXQ. However,
2259 * firmware still honours it.
2260 */
2261 INIT_TXQ_EXT_IN_FLAG_TSOV2_EN, tso_v2,
2262 INIT_TXQ_IN_FLAG_IP_CSUM_DIS, !csum_offload,
2263 INIT_TXQ_IN_FLAG_TCP_CSUM_DIS, !csum_offload);
2264
2265 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_INIT_TXQ, inbuf, inlen,
2266 NULL, 0, NULL);
2267 if (rc == -ENOSPC && tso_v2) {
2268 /* Retry without TSOv2 if we're short on contexts. */
2269 tso_v2 = false;
2270 netif_warn(efx, probe, efx->net_dev,
2271 "TSOv2 context not available to segment in hardware. TCP performance may be reduced.\n");
2272 } else if (rc) {
2273 efx_mcdi_display_error(efx, MC_CMD_INIT_TXQ,
2274 MC_CMD_INIT_TXQ_EXT_IN_LEN,
2275 NULL, 0, rc);
2276 goto fail;
2277 }
2278 } while (rc);
8127d661
BH		 2279
2280 /* A previous user of this TX queue might have set us up the
2281 * bomb by writing a descriptor to the TX push collector but
2282 * not the doorbell. (Each collector belongs to a port, not a
2283 * queue or function, so cannot easily be reset.) We must
2284 * attempt to push a no-op descriptor in its place.
2285 */
2286 tx_queue->buffer[0].flags = EFX_TX_BUF_OPTION;
2287 tx_queue->insert_count = 1;
2288 txd = efx_tx_desc(tx_queue, 0);
2289 EFX_POPULATE_QWORD_4(*txd,
2290 ESF_DZ_TX_DESC_IS_OPT, true,
2291 ESF_DZ_TX_OPTION_TYPE,
2292 ESE_DZ_TX_OPTION_DESC_CRC_CSUM,
2293 ESF_DZ_TX_OPTION_UDP_TCP_CSUM, csum_offload,
2294 ESF_DZ_TX_OPTION_IP_CSUM, csum_offload);
2295 tx_queue->write_count = 1;
93171b14 2296
e9117e50
BK		 2297 if (tso_v2) {
2298 tx_queue->handle_tso = efx_ef10_tx_tso_desc;
2299 tx_queue->tso_version = 2;
2300 } else if (nic_data->datapath_caps &
2301 (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN)) {
93171b14
BK		 2302 tx_queue->tso_version = 1;
2303 }
2304
8127d661
BH		 2305 wmb();
2306 efx_ef10_push_tx_desc(tx_queue, txd);
2307
2308 return;
2309
2310fail:
48ce5634
BH		 2311 netdev_WARN(efx->net_dev, "failed to initialise TXQ %d\n",
2312 tx_queue->queue);
8127d661
BH		 2313}
2314
2315static void efx_ef10_tx_fini(struct efx_tx_queue *tx_queue)
2316{
2317 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_TXQ_IN_LEN);
aa09a3da 2318 MCDI_DECLARE_BUF_ERR(outbuf);
8127d661
BH		 2319 struct efx_nic *efx = tx_queue->efx;
2320 size_t outlen;
2321 int rc;
2322
2323 MCDI_SET_DWORD(inbuf, FINI_TXQ_IN_INSTANCE,
2324 tx_queue->queue);
2325
1e0b8120 2326 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_TXQ, inbuf, sizeof(inbuf),
8127d661
BH		 2327 outbuf, sizeof(outbuf), &outlen);
2328
2329 if (rc && rc != -EALREADY)
2330 goto fail;
2331
2332 return;
2333
2334fail:
1e0b8120
EC		 2335 efx_mcdi_display_error(efx, MC_CMD_FINI_TXQ, MC_CMD_FINI_TXQ_IN_LEN,
2336 outbuf, outlen, rc);
8127d661
BH		 2337}
2338
2339static void efx_ef10_tx_remove(struct efx_tx_queue *tx_queue)
2340{
2341 efx_nic_free_buffer(tx_queue->efx, &tx_queue->txd.buf);
2342}
2343
2344/* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
2345static inline void efx_ef10_notify_tx_desc(struct efx_tx_queue *tx_queue)
2346{
2347 unsigned int write_ptr;
2348 efx_dword_t reg;
2349
2350 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
2351 EFX_POPULATE_DWORD_1(reg, ERF_DZ_TX_DESC_WPTR_DWORD, write_ptr);
2352 efx_writed_page(tx_queue->efx, &reg,
2353 ER_DZ_TX_DESC_UPD_DWORD, tx_queue->queue);
2354}
2355
e9117e50
BK		 2356#define EFX_EF10_MAX_TX_DESCRIPTOR_LEN 0x3fff
2357
2358static unsigned int efx_ef10_tx_limit_len(struct efx_tx_queue *tx_queue,
2359 dma_addr_t dma_addr, unsigned int len)
2360{
2361 if (len > EFX_EF10_MAX_TX_DESCRIPTOR_LEN) {
2362 /* If we need to break across multiple descriptors we should
2363 * stop at a page boundary. This assumes the length limit is
2364 * greater than the page size.
2365 */
2366 dma_addr_t end = dma_addr + EFX_EF10_MAX_TX_DESCRIPTOR_LEN;
2367
2368 BUILD_BUG_ON(EFX_EF10_MAX_TX_DESCRIPTOR_LEN < EFX_PAGE_SIZE);
2369 len = (end & (~(EFX_PAGE_SIZE - 1))) - dma_addr;
2370 }
2371
2372 return len;
2373}
2374
8127d661
BH		 2375static void efx_ef10_tx_write(struct efx_tx_queue *tx_queue)
2376{
2377 unsigned int old_write_count = tx_queue->write_count;
2378 struct efx_tx_buffer *buffer;
2379 unsigned int write_ptr;
2380 efx_qword_t *txd;
2381
b2663a4f
MH		 2382 tx_queue->xmit_more_available = false;
2383 if (unlikely(tx_queue->write_count == tx_queue->insert_count))
2384 return;
8127d661
BH		 2385
2386 do {
2387 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
2388 buffer = &tx_queue->buffer[write_ptr];
2389 txd = efx_tx_desc(tx_queue, write_ptr);
2390 ++tx_queue->write_count;
2391
2392 /* Create TX descriptor ring entry */
2393 if (buffer->flags & EFX_TX_BUF_OPTION) {
2394 *txd = buffer->option;
de1deff9
EC		 2395 if (EFX_QWORD_FIELD(*txd, ESF_DZ_TX_OPTION_TYPE) == 1)
2396 /* PIO descriptor */
2397 tx_queue->packet_write_count = tx_queue->write_count;
8127d661 2398 } else {
de1deff9 2399 tx_queue->packet_write_count = tx_queue->write_count;
8127d661
BH		 2400 BUILD_BUG_ON(EFX_TX_BUF_CONT != 1);
2401 EFX_POPULATE_QWORD_3(
2402 *txd,
2403 ESF_DZ_TX_KER_CONT,
2404 buffer->flags & EFX_TX_BUF_CONT,
2405 ESF_DZ_TX_KER_BYTE_CNT, buffer->len,
2406 ESF_DZ_TX_KER_BUF_ADDR, buffer->dma_addr);
2407 }
2408 } while (tx_queue->write_count != tx_queue->insert_count);
2409
2410 wmb(); /* Ensure descriptors are written before they are fetched */
2411
2412 if (efx_nic_may_push_tx_desc(tx_queue, old_write_count)) {
2413 txd = efx_tx_desc(tx_queue,
2414 old_write_count & tx_queue->ptr_mask);
2415 efx_ef10_push_tx_desc(tx_queue, txd);
2416 ++tx_queue->pushes;
2417 } else {
2418 efx_ef10_notify_tx_desc(tx_queue);
2419 }
2420}
2421
a33a4c73
EC		 2422#define RSS_MODE_HASH_ADDRS (1 << RSS_MODE_HASH_SRC_ADDR_LBN |\
2423 1 << RSS_MODE_HASH_DST_ADDR_LBN)
2424#define RSS_MODE_HASH_PORTS (1 << RSS_MODE_HASH_SRC_PORT_LBN |\
2425 1 << RSS_MODE_HASH_DST_PORT_LBN)
2426#define RSS_CONTEXT_FLAGS_DEFAULT (1 << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_LBN |\
2427 1 << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_LBN |\
2428 1 << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_LBN |\
2429 1 << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_LBN |\
2430 (RSS_MODE_HASH_ADDRS | RSS_MODE_HASH_PORTS) << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV4_RSS_MODE_LBN |\
2431 RSS_MODE_HASH_ADDRS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_LBN |\
2432 RSS_MODE_HASH_ADDRS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV4_RSS_MODE_LBN |\
2433 (RSS_MODE_HASH_ADDRS | RSS_MODE_HASH_PORTS) << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV6_RSS_MODE_LBN |\
2434 RSS_MODE_HASH_ADDRS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_LBN |\
2435 RSS_MODE_HASH_ADDRS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV6_RSS_MODE_LBN)
2436
2437static int efx_ef10_get_rss_flags(struct efx_nic *efx, u32 context, u32 *flags)
2438{
2439 /* Firmware had a bug (sfc bug 61952) where it would not actually
2440 * fill in the flags field in the response to MC_CMD_RSS_CONTEXT_GET_FLAGS.
2441 * This meant that it would always contain whatever was previously
2442 * in the MCDI buffer. Fortunately, all firmware versions with
2443 * this bug have the same default flags value for a newly-allocated
2444 * RSS context, and the only time we want to get the flags is just
2445 * after allocating. Moreover, the response has a 32-bit hole
2446 * where the context ID would be in the request, so we can use an
2447 * overlength buffer in the request and pre-fill the flags field
2448 * with what we believe the default to be. Thus if the firmware
2449 * has the bug, it will leave our pre-filled value in the flags
2450 * field of the response, and we will get the right answer.
2451 *
2452 * However, this does mean that this function should NOT be used if
2453 * the RSS context flags might not be their defaults - it is ONLY
2454 * reliably correct for a newly-allocated RSS context.
2455 */
2456 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_LEN);
2457 MCDI_DECLARE_BUF(outbuf, MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_LEN);
2458 size_t outlen;
2459 int rc;
2460
2461 /* Check we have a hole for the context ID */
2462 BUILD_BUG_ON(MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_LEN != MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_FLAGS_OFST);
2463 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_GET_FLAGS_IN_RSS_CONTEXT_ID, context);
2464 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_GET_FLAGS_OUT_FLAGS,
2465 RSS_CONTEXT_FLAGS_DEFAULT);
2466 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_GET_FLAGS, inbuf,
2467 sizeof(inbuf), outbuf, sizeof(outbuf), &outlen);
2468 if (rc == 0) {
2469 if (outlen < MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_LEN)
2470 rc = -EIO;
2471 else
2472 *flags = MCDI_DWORD(outbuf, RSS_CONTEXT_GET_FLAGS_OUT_FLAGS);
2473 }
2474 return rc;
2475}
2476
2477/* Attempt to enable 4-tuple UDP hashing on the specified RSS context.
2478 * If we fail, we just leave the RSS context at its default hash settings,
2479 * which is safe but may slightly reduce performance.
2480 * Defaults are 4-tuple for TCP and 2-tuple for UDP and other-IP, so we
2481 * just need to set the UDP ports flags (for both IP versions).
2482 */
2483static void efx_ef10_set_rss_flags(struct efx_nic *efx, u32 context)
2484{
2485 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_LEN);
2486 u32 flags;
2487
2488 BUILD_BUG_ON(MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT_LEN != 0);
2489
2490 if (efx_ef10_get_rss_flags(efx, context, &flags) != 0)
2491 return;
2492 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_SET_FLAGS_IN_RSS_CONTEXT_ID, context);
2493 flags |= RSS_MODE_HASH_PORTS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_LBN;
2494 flags |= RSS_MODE_HASH_PORTS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_LBN;
2495 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_SET_FLAGS_IN_FLAGS, flags);
b718c88a
EC		 2496 if (!efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_FLAGS, inbuf, sizeof(inbuf),
2497 NULL, 0, NULL))
2498 /* Succeeded, so UDP 4-tuple is now enabled */
2499 efx->rx_hash_udp_4tuple = true;
a33a4c73
EC		 2500}
2501
267c0157
JC		 2502static int efx_ef10_alloc_rss_context(struct efx_nic *efx, u32 *context,
2503 bool exclusive, unsigned *context_size)
8127d661
BH		 2504{
2505 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN);
2506 MCDI_DECLARE_BUF(outbuf, MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN);
45b2449e 2507 struct efx_ef10_nic_data *nic_data = efx->nic_data;
8127d661
BH		 2508 size_t outlen;
2509 int rc;
267c0157
JC		 2510 u32 alloc_type = exclusive ?
2511 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE :
2512 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED;
2513 unsigned rss_spread = exclusive ?
2514 efx->rss_spread :
2515 min(rounddown_pow_of_two(efx->rss_spread),
2516 EFX_EF10_MAX_SHARED_RSS_CONTEXT_SIZE);
2517
2518 if (!exclusive && rss_spread == 1) {
2519 *context = EFX_EF10_RSS_CONTEXT_INVALID;
2520 if (context_size)
2521 *context_size = 1;
2522 return 0;
2523 }
8127d661 2524
dcb4123c
JC		 2525 if (nic_data->datapath_caps &
2526 1 << MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_LBN)
2527 return -EOPNOTSUPP;
2528
8127d661 2529 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID,
45b2449e 2530 nic_data->vport_id);
267c0157
JC		 2531 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_TYPE, alloc_type);
2532 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_NUM_QUEUES, rss_spread);
8127d661
BH		 2533
2534 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_ALLOC, inbuf, sizeof(inbuf),
2535 outbuf, sizeof(outbuf), &outlen);
2536 if (rc != 0)
2537 return rc;
2538
2539 if (outlen < MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN)
2540 return -EIO;
2541
2542 *context = MCDI_DWORD(outbuf, RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID);
2543
267c0157
JC		 2544 if (context_size)
2545 *context_size = rss_spread;
2546
a33a4c73
EC		 2547 if (nic_data->datapath_caps &
2548 1 << MC_CMD_GET_CAPABILITIES_OUT_ADDITIONAL_RSS_MODES_LBN)
2549 efx_ef10_set_rss_flags(efx, *context);
2550
8127d661
BH		 2551 return 0;
2552}
2553
2554static void efx_ef10_free_rss_context(struct efx_nic *efx, u32 context)
2555{
2556 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_FREE_IN_LEN);
2557 int rc;
2558
2559 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID,
2560 context);
2561
2562 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_FREE, inbuf, sizeof(inbuf),
2563 NULL, 0, NULL);
2564 WARN_ON(rc != 0);
2565}
2566
267c0157 2567static int efx_ef10_populate_rss_table(struct efx_nic *efx, u32 context,
f74d1995 2568 const u32 *rx_indir_table, const u8 *key)
8127d661
BH		 2569{
2570 MCDI_DECLARE_BUF(tablebuf, MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN);
2571 MCDI_DECLARE_BUF(keybuf, MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN);
2572 int i, rc;
2573
2574 MCDI_SET_DWORD(tablebuf, RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID,
2575 context);
2576 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_indir_table) !=
2577 MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN);
2578
f74d1995
EC		 2579 /* This iterates over the length of efx->rx_indir_table, but copies
2580 * bytes from rx_indir_table. That's because the latter is a pointer
2581 * rather than an array, but should have the same length.
2582 * The efx->rx_hash_key loop below is similar.
2583 */
8127d661
BH		 2584 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); ++i)
2585 MCDI_PTR(tablebuf,
2586 RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE)[i] =
267c0157 2587 (u8) rx_indir_table[i];
8127d661
BH		 2588
2589 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_TABLE, tablebuf,
2590 sizeof(tablebuf), NULL, 0, NULL);
2591 if (rc != 0)
2592 return rc;
2593
2594 MCDI_SET_DWORD(keybuf, RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID,
2595 context);
2596 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_hash_key) !=
2597 MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN);
2598 for (i = 0; i < ARRAY_SIZE(efx->rx_hash_key); ++i)
f74d1995 2599 MCDI_PTR(keybuf, RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY)[i] = key[i];
8127d661
BH		 2600
2601 return efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_KEY, keybuf,
2602 sizeof(keybuf), NULL, 0, NULL);
2603}
2604
2605static void efx_ef10_rx_free_indir_table(struct efx_nic *efx)
2606{
2607 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2608
2609 if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID)
2610 efx_ef10_free_rss_context(efx, nic_data->rx_rss_context);
2611 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
2612}
2613
267c0157
JC		 2614static int efx_ef10_rx_push_shared_rss_config(struct efx_nic *efx,
2615 unsigned *context_size)
8127d661 2616{
267c0157 2617 u32 new_rx_rss_context;
8127d661 2618 struct efx_ef10_nic_data *nic_data = efx->nic_data;
267c0157
JC		 2619 int rc = efx_ef10_alloc_rss_context(efx, &new_rx_rss_context,
2620 false, context_size);
2621
2622 if (rc != 0)
2623 return rc;
8127d661 2624
267c0157
JC		 2625 nic_data->rx_rss_context = new_rx_rss_context;
2626 nic_data->rx_rss_context_exclusive = false;
2627 efx_set_default_rx_indir_table(efx);
2628 return 0;
2629}
8127d661 2630
267c0157 2631static int efx_ef10_rx_push_exclusive_rss_config(struct efx_nic *efx,
f74d1995
EC		 2632 const u32 *rx_indir_table,
2633 const u8 *key)
267c0157
JC		 2634{
2635 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2636 int rc;
2637 u32 new_rx_rss_context;
2638
2639 if (nic_data->rx_rss_context == EFX_EF10_RSS_CONTEXT_INVALID ||
2640 !nic_data->rx_rss_context_exclusive) {
2641 rc = efx_ef10_alloc_rss_context(efx, &new_rx_rss_context,
2642 true, NULL);
2643 if (rc == -EOPNOTSUPP)
2644 return rc;
2645 else if (rc != 0)
2646 goto fail1;
2647 } else {
2648 new_rx_rss_context = nic_data->rx_rss_context;
8127d661
BH		 2649 }
2650
267c0157 2651 rc = efx_ef10_populate_rss_table(efx, new_rx_rss_context,
f74d1995 2652 rx_indir_table, key);
8127d661 2653 if (rc != 0)
267c0157 2654 goto fail2;
8127d661 2655
267c0157
JC		 2656 if (nic_data->rx_rss_context != new_rx_rss_context)
2657 efx_ef10_rx_free_indir_table(efx);
2658 nic_data->rx_rss_context = new_rx_rss_context;
2659 nic_data->rx_rss_context_exclusive = true;
2660 if (rx_indir_table != efx->rx_indir_table)
2661 memcpy(efx->rx_indir_table, rx_indir_table,
2662 sizeof(efx->rx_indir_table));
f74d1995
EC		 2663 if (key != efx->rx_hash_key)
2664 memcpy(efx->rx_hash_key, key, efx->type->rx_hash_key_size);
2665
267c0157 2666 return 0;
8127d661 2667
267c0157
JC		 2668fail2:
2669 if (new_rx_rss_context != nic_data->rx_rss_context)
2670 efx_ef10_free_rss_context(efx, new_rx_rss_context);
2671fail1:
8127d661 2672 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
267c0157
JC		 2673 return rc;
2674}
2675
a707d188
EC		 2676static int efx_ef10_rx_pull_rss_config(struct efx_nic *efx)
2677{
2678 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2679 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_GET_TABLE_IN_LEN);
2680 MCDI_DECLARE_BUF(tablebuf, MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_LEN);
2681 MCDI_DECLARE_BUF(keybuf, MC_CMD_RSS_CONTEXT_GET_KEY_OUT_LEN);
2682 size_t outlen;
2683 int rc, i;
2684
2685 BUILD_BUG_ON(MC_CMD_RSS_CONTEXT_GET_TABLE_IN_LEN !=
2686 MC_CMD_RSS_CONTEXT_GET_KEY_IN_LEN);
2687
2688 if (nic_data->rx_rss_context == EFX_EF10_RSS_CONTEXT_INVALID)
2689 return -ENOENT;
2690
2691 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_GET_TABLE_IN_RSS_CONTEXT_ID,
2692 nic_data->rx_rss_context);
2693 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_indir_table) !=
2694 MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE_LEN);
2695 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_GET_TABLE, inbuf, sizeof(inbuf),
2696 tablebuf, sizeof(tablebuf), &outlen);
2697 if (rc != 0)
2698 return rc;
2699
2700 if (WARN_ON(outlen != MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_LEN))
2701 return -EIO;
2702
2703 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); i++)
2704 efx->rx_indir_table[i] = MCDI_PTR(tablebuf,
2705 RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE)[i];
2706
2707 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_GET_KEY_IN_RSS_CONTEXT_ID,
2708 nic_data->rx_rss_context);
2709 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_hash_key) !=
2710 MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN);
2711 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_GET_KEY, inbuf, sizeof(inbuf),
2712 keybuf, sizeof(keybuf), &outlen);
2713 if (rc != 0)
2714 return rc;
2715
2716 if (WARN_ON(outlen != MC_CMD_RSS_CONTEXT_GET_KEY_OUT_LEN))
2717 return -EIO;
2718
2719 for (i = 0; i < ARRAY_SIZE(efx->rx_hash_key); ++i)
2720 efx->rx_hash_key[i] = MCDI_PTR(
2721 keybuf, RSS_CONTEXT_GET_KEY_OUT_TOEPLITZ_KEY)[i];
2722
2723 return 0;
2724}
2725
267c0157 2726static int efx_ef10_pf_rx_push_rss_config(struct efx_nic *efx, bool user,
f74d1995
EC		 2727 const u32 *rx_indir_table,
2728 const u8 *key)
267c0157
JC		 2729{
2730 int rc;
2731
2732 if (efx->rss_spread == 1)
2733 return 0;
2734
f74d1995
EC		 2735 if (!key)
2736 key = efx->rx_hash_key;
2737
2738 rc = efx_ef10_rx_push_exclusive_rss_config(efx, rx_indir_table, key);
267c0157
JC		 2739
2740 if (rc == -ENOBUFS && !user) {
2741 unsigned context_size;
2742 bool mismatch = false;
2743 size_t i;
2744
2745 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table) && !mismatch;
2746 i++)
2747 mismatch = rx_indir_table[i] !=
2748 ethtool_rxfh_indir_default(i, efx->rss_spread);
2749
2750 rc = efx_ef10_rx_push_shared_rss_config(efx, &context_size);
2751 if (rc == 0) {
2752 if (context_size != efx->rss_spread)
2753 netif_warn(efx, probe, efx->net_dev,
2754 "Could not allocate an exclusive RSS"
2755 " context; allocated a shared one of"
2756 " different size."
2757 " Wanted %u, got %u.\n",
2758 efx->rss_spread, context_size);
2759 else if (mismatch)
2760 netif_warn(efx, probe, efx->net_dev,
2761 "Could not allocate an exclusive RSS"
2762 " context; allocated a shared one but"
2763 " could not apply custom"
2764 " indirection.\n");
2765 else
2766 netif_info(efx, probe, efx->net_dev,
2767 "Could not allocate an exclusive RSS"
2768 " context; allocated a shared one.\n");
2769 }
2770 }
2771 return rc;
2772}
2773
2774static int efx_ef10_vf_rx_push_rss_config(struct efx_nic *efx, bool user,
2775 const u32 *rx_indir_table
f74d1995
EC		 2776 __attribute__ ((unused)),
2777 const u8 *key
267c0157
JC		 2778 __attribute__ ((unused)))
2779{
2780 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2781
2782 if (user)
2783 return -EOPNOTSUPP;
2784 if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID)
2785 return 0;
2786 return efx_ef10_rx_push_shared_rss_config(efx, NULL);
8127d661
BH		 2787}
2788
2789static int efx_ef10_rx_probe(struct efx_rx_queue *rx_queue)
2790{
2791 return efx_nic_alloc_buffer(rx_queue->efx, &rx_queue->rxd.buf,
2792 (rx_queue->ptr_mask + 1) *
2793 sizeof(efx_qword_t),
2794 GFP_KERNEL);
2795}
2796
2797static void efx_ef10_rx_init(struct efx_rx_queue *rx_queue)
2798{
2799 MCDI_DECLARE_BUF(inbuf,
2800 MC_CMD_INIT_RXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
2801 EFX_BUF_SIZE));
8127d661
BH		 2802 struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
2803 size_t entries = rx_queue->rxd.buf.len / EFX_BUF_SIZE;
2804 struct efx_nic *efx = rx_queue->efx;
45b2449e 2805 struct efx_ef10_nic_data *nic_data = efx->nic_data;
aa09a3da 2806 size_t inlen;
8127d661
BH		 2807 dma_addr_t dma_addr;
2808 int rc;
2809 int i;
aa09a3da 2810 BUILD_BUG_ON(MC_CMD_INIT_RXQ_OUT_LEN != 0);
8127d661
BH		 2811
2812 rx_queue->scatter_n = 0;
2813 rx_queue->scatter_len = 0;
2814
2815 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_SIZE, rx_queue->ptr_mask + 1);
2816 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_TARGET_EVQ, channel->channel);
2817 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_LABEL, efx_rx_queue_index(rx_queue));
2818 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_INSTANCE,
2819 efx_rx_queue_index(rx_queue));
bd9a265d
JC		 2820 MCDI_POPULATE_DWORD_2(inbuf, INIT_RXQ_IN_FLAGS,
2821 INIT_RXQ_IN_FLAG_PREFIX, 1,
2822 INIT_RXQ_IN_FLAG_TIMESTAMP, 1);
8127d661 2823 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_OWNER_ID, 0);
45b2449e 2824 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_PORT_ID, nic_data->vport_id);
8127d661
BH		 2825
2826 dma_addr = rx_queue->rxd.buf.dma_addr;
2827
2828 netif_dbg(efx, hw, efx->net_dev, "pushing RXQ %d. %zu entries (%llx)\n",
2829 efx_rx_queue_index(rx_queue), entries, (u64)dma_addr);
2830
2831 for (i = 0; i < entries; ++i) {
2832 MCDI_SET_ARRAY_QWORD(inbuf, INIT_RXQ_IN_DMA_ADDR, i, dma_addr);
2833 dma_addr += EFX_BUF_SIZE;
2834 }
2835
2836 inlen = MC_CMD_INIT_RXQ_IN_LEN(entries);
2837
2838 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_RXQ, inbuf, inlen,
aa09a3da 2839 NULL, 0, NULL);
48ce5634
BH		 2840 if (rc)
2841 netdev_WARN(efx->net_dev, "failed to initialise RXQ %d\n",
2842 efx_rx_queue_index(rx_queue));
8127d661
BH		 2843}
2844
2845static void efx_ef10_rx_fini(struct efx_rx_queue *rx_queue)
2846{
2847 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_RXQ_IN_LEN);
aa09a3da 2848 MCDI_DECLARE_BUF_ERR(outbuf);
8127d661
BH		 2849 struct efx_nic *efx = rx_queue->efx;
2850 size_t outlen;
2851 int rc;
2852
2853 MCDI_SET_DWORD(inbuf, FINI_RXQ_IN_INSTANCE,
2854 efx_rx_queue_index(rx_queue));
2855
1e0b8120 2856 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_RXQ, inbuf, sizeof(inbuf),
8127d661
BH		 2857 outbuf, sizeof(outbuf), &outlen);
2858
2859 if (rc && rc != -EALREADY)
2860 goto fail;
2861
2862 return;
2863
2864fail:
1e0b8120
EC		 2865 efx_mcdi_display_error(efx, MC_CMD_FINI_RXQ, MC_CMD_FINI_RXQ_IN_LEN,
2866 outbuf, outlen, rc);
8127d661
BH		 2867}
2868
2869static void efx_ef10_rx_remove(struct efx_rx_queue *rx_queue)
2870{
2871 efx_nic_free_buffer(rx_queue->efx, &rx_queue->rxd.buf);
2872}
2873
2874/* This creates an entry in the RX descriptor queue */
2875static inline void
2876efx_ef10_build_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index)
2877{
2878 struct efx_rx_buffer *rx_buf;
2879 efx_qword_t *rxd;
2880
2881 rxd = efx_rx_desc(rx_queue, index);
2882 rx_buf = efx_rx_buffer(rx_queue, index);
2883 EFX_POPULATE_QWORD_2(*rxd,
2884 ESF_DZ_RX_KER_BYTE_CNT, rx_buf->len,
2885 ESF_DZ_RX_KER_BUF_ADDR, rx_buf->dma_addr);
2886}
2887
2888static void efx_ef10_rx_write(struct efx_rx_queue *rx_queue)
2889{
2890 struct efx_nic *efx = rx_queue->efx;
2891 unsigned int write_count;
2892 efx_dword_t reg;
2893
2894 /* Firmware requires that RX_DESC_WPTR be a multiple of 8 */
2895 write_count = rx_queue->added_count & ~7;
2896 if (rx_queue->notified_count == write_count)
2897 return;
2898
2899 do
2900 efx_ef10_build_rx_desc(
2901 rx_queue,
2902 rx_queue->notified_count & rx_queue->ptr_mask);
2903 while (++rx_queue->notified_count != write_count);
2904
2905 wmb();
2906 EFX_POPULATE_DWORD_1(reg, ERF_DZ_RX_DESC_WPTR,
2907 write_count & rx_queue->ptr_mask);
2908 efx_writed_page(efx, &reg, ER_DZ_RX_DESC_UPD,
2909 efx_rx_queue_index(rx_queue));
2910}
2911
2912static efx_mcdi_async_completer efx_ef10_rx_defer_refill_complete;
2913
2914static void efx_ef10_rx_defer_refill(struct efx_rx_queue *rx_queue)
2915{
2916 struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
2917 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
2918 efx_qword_t event;
2919
2920 EFX_POPULATE_QWORD_2(event,
2921 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
2922 ESF_DZ_EV_DATA, EFX_EF10_REFILL);
2923
2924 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
2925
2926 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
2927 * already swapped the data to little-endian order.
2928 */
2929 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
2930 sizeof(efx_qword_t));
2931
2932 efx_mcdi_rpc_async(channel->efx, MC_CMD_DRIVER_EVENT,
2933 inbuf, sizeof(inbuf), 0,
2934 efx_ef10_rx_defer_refill_complete, 0);
2935}
2936
2937static void
2938efx_ef10_rx_defer_refill_complete(struct efx_nic *efx, unsigned long cookie,
2939 int rc, efx_dword_t *outbuf,
2940 size_t outlen_actual)
2941{
2942 /* nothing to do */
2943}
2944
2945static int efx_ef10_ev_probe(struct efx_channel *channel)
2946{
2947 return efx_nic_alloc_buffer(channel->efx, &channel->eventq.buf,
2948 (channel->eventq_mask + 1) *
2949 sizeof(efx_qword_t),
2950 GFP_KERNEL);
2951}
2952
46e612b0
DP		 2953static void efx_ef10_ev_fini(struct efx_channel *channel)
2954{
2955 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_EVQ_IN_LEN);
2956 MCDI_DECLARE_BUF_ERR(outbuf);
2957 struct efx_nic *efx = channel->efx;
2958 size_t outlen;
2959 int rc;
2960
2961 MCDI_SET_DWORD(inbuf, FINI_EVQ_IN_INSTANCE, channel->channel);
2962
2963 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_EVQ, inbuf, sizeof(inbuf),
2964 outbuf, sizeof(outbuf), &outlen);
2965
2966 if (rc && rc != -EALREADY)
2967 goto fail;
2968
2969 return;
2970
2971fail:
2972 efx_mcdi_display_error(efx, MC_CMD_FINI_EVQ, MC_CMD_FINI_EVQ_IN_LEN,
2973 outbuf, outlen, rc);
2974}
2975
8127d661
BH		 2976static int efx_ef10_ev_init(struct efx_channel *channel)
2977{
2978 MCDI_DECLARE_BUF(inbuf,
a995560a
BK		 2979 MC_CMD_INIT_EVQ_V2_IN_LEN(EFX_MAX_EVQ_SIZE * 8 /
2980 EFX_BUF_SIZE));
2981 MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_EVQ_V2_OUT_LEN);
8127d661
BH		 2982 size_t entries = channel->eventq.buf.len / EFX_BUF_SIZE;
2983 struct efx_nic *efx = channel->efx;
2984 struct efx_ef10_nic_data *nic_data;
8127d661 2985 size_t inlen, outlen;
46e612b0 2986 unsigned int enabled, implemented;
8127d661
BH		 2987 dma_addr_t dma_addr;
2988 int rc;
2989 int i;
2990
2991 nic_data = efx->nic_data;
8127d661
BH		 2992
2993 /* Fill event queue with all ones (i.e. empty events) */
2994 memset(channel->eventq.buf.addr, 0xff, channel->eventq.buf.len);
2995
2996 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_SIZE, channel->eventq_mask + 1);
2997 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_INSTANCE, channel->channel);
2998 /* INIT_EVQ expects index in vector table, not absolute */
2999 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_IRQ_NUM, channel->channel);
8127d661
BH		 3000 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_MODE,
3001 MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS);
3002 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_LOAD, 0);
3003 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_RELOAD, 0);
3004 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_MODE,
3005 MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS);
3006 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_THRSHLD, 0);
3007
a995560a
BK		 3008 if (nic_data->datapath_caps2 &
3009 1 << MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_V2_LBN) {
3010 /* Use the new generic approach to specifying event queue
3011 * configuration, requesting lower latency or higher throughput.
3012 * The options that actually get used appear in the output.
3013 */
3014 MCDI_POPULATE_DWORD_2(inbuf, INIT_EVQ_V2_IN_FLAGS,
3015 INIT_EVQ_V2_IN_FLAG_INTERRUPTING, 1,
3016 INIT_EVQ_V2_IN_FLAG_TYPE,
3017 MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_AUTO);
3018 } else {
3019 bool cut_thru = !(nic_data->datapath_caps &
3020 1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN);
3021
3022 MCDI_POPULATE_DWORD_4(inbuf, INIT_EVQ_IN_FLAGS,
3023 INIT_EVQ_IN_FLAG_INTERRUPTING, 1,
3024 INIT_EVQ_IN_FLAG_RX_MERGE, 1,
3025 INIT_EVQ_IN_FLAG_TX_MERGE, 1,
3026 INIT_EVQ_IN_FLAG_CUT_THRU, cut_thru);
3027 }
3028
8127d661
BH		 3029 dma_addr = channel->eventq.buf.dma_addr;
3030 for (i = 0; i < entries; ++i) {
3031 MCDI_SET_ARRAY_QWORD(inbuf, INIT_EVQ_IN_DMA_ADDR, i, dma_addr);
3032 dma_addr += EFX_BUF_SIZE;
3033 }
3034
3035 inlen = MC_CMD_INIT_EVQ_IN_LEN(entries);
3036
3037 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_EVQ, inbuf, inlen,
3038 outbuf, sizeof(outbuf), &outlen);
a995560a
BK		 3039
3040 if (outlen >= MC_CMD_INIT_EVQ_V2_OUT_LEN)
3041 netif_dbg(efx, drv, efx->net_dev,
3042 "Channel %d using event queue flags %08x\n",
3043 channel->channel,
3044 MCDI_DWORD(outbuf, INIT_EVQ_V2_OUT_FLAGS));
3045
8127d661 3046 /* IRQ return is ignored */
46e612b0
DP		 3047 if (channel->channel || rc)
3048 return rc;
8127d661 3049
46e612b0
DP		 3050 /* Successfully created event queue on channel 0 */
3051 rc = efx_mcdi_get_workarounds(efx, &implemented, &enabled);
832dc9ed 3052 if (rc == -ENOSYS) {
d95e329a
BK		 3053 /* GET_WORKAROUNDS was implemented before this workaround,
3054 * thus it must be unavailable in this firmware.
832dc9ed
EC		 3055 */
3056 nic_data->workaround_26807 = false;
3057 rc = 0;
3058 } else if (rc) {
8127d661 3059 goto fail;
832dc9ed
EC		 3060 } else {
3061 nic_data->workaround_26807 =
3062 !!(enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807);
3063
3064 if (implemented & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807 &&
3065 !nic_data->workaround_26807) {
5a55a72a
DP		 3066 unsigned int flags;
3067
34ccfe6f
DP		 3068 rc = efx_mcdi_set_workaround(efx,
3069 MC_CMD_WORKAROUND_BUG26807,
5a55a72a
DP		 3070 true, &flags);
3071
3072 if (!rc) {
3073 if (flags &
3074 1 << MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN) {
3075 netif_info(efx, drv, efx->net_dev,
3076 "other functions on NIC have been reset\n");
abd86a55
DP		 3077
3078 /* With MCFW v4.6.x and earlier, the
3079 * boot count will have incremented,
3080 * so re-read the warm_boot_count
3081 * value now to ensure this function
3082 * doesn't think it has changed next
3083 * time it checks.
3084 */
3085 rc = efx_ef10_get_warm_boot_count(efx);
3086 if (rc >= 0) {
3087 nic_data->warm_boot_count = rc;
3088 rc = 0;
3089 }
5a55a72a 3090 }
832dc9ed 3091 nic_data->workaround_26807 = true;
5a55a72a 3092 } else if (rc == -EPERM) {
832dc9ed 3093 rc = 0;
5a55a72a 3094 }
832dc9ed 3095 }
46e612b0
DP		 3096 }
3097
3098 if (!rc)
3099 return 0;
8127d661
BH		 3100
3101fail:
46e612b0
DP		 3102 efx_ef10_ev_fini(channel);
3103 return rc;
8127d661
BH		 3104}
3105
3106static void efx_ef10_ev_remove(struct efx_channel *channel)
3107{
3108 efx_nic_free_buffer(channel->efx, &channel->eventq.buf);
3109}
3110
3111static void efx_ef10_handle_rx_wrong_queue(struct efx_rx_queue *rx_queue,
3112 unsigned int rx_queue_label)
3113{
3114 struct efx_nic *efx = rx_queue->efx;
3115
3116 netif_info(efx, hw, efx->net_dev,
3117 "rx event arrived on queue %d labeled as queue %u\n",
3118 efx_rx_queue_index(rx_queue), rx_queue_label);
3119
3120 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
3121}
3122
3123static void
3124efx_ef10_handle_rx_bad_lbits(struct efx_rx_queue *rx_queue,
3125 unsigned int actual, unsigned int expected)
3126{
3127 unsigned int dropped = (actual - expected) & rx_queue->ptr_mask;
3128 struct efx_nic *efx = rx_queue->efx;
3129
3130 netif_info(efx, hw, efx->net_dev,
3131 "dropped %d events (index=%d expected=%d)\n",
3132 dropped, actual, expected);
3133
3134 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
3135}
3136
3137/* partially received RX was aborted. clean up. */
3138static void efx_ef10_handle_rx_abort(struct efx_rx_queue *rx_queue)
3139{
3140 unsigned int rx_desc_ptr;
3141
8127d661
BH		 3142 netif_dbg(rx_queue->efx, hw, rx_queue->efx->net_dev,
3143 "scattered RX aborted (dropping %u buffers)\n",
3144 rx_queue->scatter_n);
3145
3146 rx_desc_ptr = rx_queue->removed_count & rx_queue->ptr_mask;
3147
3148 efx_rx_packet(rx_queue, rx_desc_ptr, rx_queue->scatter_n,
3149 0, EFX_RX_PKT_DISCARD);
3150
3151 rx_queue->removed_count += rx_queue->scatter_n;
3152 rx_queue->scatter_n = 0;
3153 rx_queue->scatter_len = 0;
3154 ++efx_rx_queue_channel(rx_queue)->n_rx_nodesc_trunc;
3155}
3156
3157static int efx_ef10_handle_rx_event(struct efx_channel *channel,
3158 const efx_qword_t *event)
3159{
3160 unsigned int rx_bytes, next_ptr_lbits, rx_queue_label, rx_l4_class;
3161 unsigned int n_descs, n_packets, i;
3162 struct efx_nic *efx = channel->efx;
3163 struct efx_rx_queue *rx_queue;
3164 bool rx_cont;
3165 u16 flags = 0;
3166
3167 if (unlikely(ACCESS_ONCE(efx->reset_pending)))
3168 return 0;
3169
3170 /* Basic packet information */
3171 rx_bytes = EFX_QWORD_FIELD(*event, ESF_DZ_RX_BYTES);
3172 next_ptr_lbits = EFX_QWORD_FIELD(*event, ESF_DZ_RX_DSC_PTR_LBITS);
3173 rx_queue_label = EFX_QWORD_FIELD(*event, ESF_DZ_RX_QLABEL);
3174 rx_l4_class = EFX_QWORD_FIELD(*event, ESF_DZ_RX_L4_CLASS);
3175 rx_cont = EFX_QWORD_FIELD(*event, ESF_DZ_RX_CONT);
3176
48ce5634
BH		 3177 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_DROP_EVENT))
3178 netdev_WARN(efx->net_dev, "saw RX_DROP_EVENT: event="
3179 EFX_QWORD_FMT "\n",
3180 EFX_QWORD_VAL(*event));
8127d661
BH		 3181
3182 rx_queue = efx_channel_get_rx_queue(channel);
3183
3184 if (unlikely(rx_queue_label != efx_rx_queue_index(rx_queue)))
3185 efx_ef10_handle_rx_wrong_queue(rx_queue, rx_queue_label);
3186
3187 n_descs = ((next_ptr_lbits - rx_queue->removed_count) &
3188 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
3189
3190 if (n_descs != rx_queue->scatter_n + 1) {
92a04168
BH		 3191 struct efx_ef10_nic_data *nic_data = efx->nic_data;
3192
8127d661
BH		 3193 /* detect rx abort */
3194 if (unlikely(n_descs == rx_queue->scatter_n)) {
48ce5634
BH		 3195 if (rx_queue->scatter_n == 0 || rx_bytes != 0)
3196 netdev_WARN(efx->net_dev,
3197 "invalid RX abort: scatter_n=%u event="
3198 EFX_QWORD_FMT "\n",
3199 rx_queue->scatter_n,
3200 EFX_QWORD_VAL(*event));
8127d661
BH		 3201 efx_ef10_handle_rx_abort(rx_queue);
3202 return 0;
3203 }
3204
92a04168
BH		 3205 /* Check that RX completion merging is valid, i.e.
3206 * the current firmware supports it and this is a
3207 * non-scattered packet.
3208 */
3209 if (!(nic_data->datapath_caps &
3210 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN)) ||
3211 rx_queue->scatter_n != 0 || rx_cont) {
8127d661
BH		 3212 efx_ef10_handle_rx_bad_lbits(
3213 rx_queue, next_ptr_lbits,
3214 (rx_queue->removed_count +
3215 rx_queue->scatter_n + 1) &
3216 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
3217 return 0;
3218 }
3219
3220 /* Merged completion for multiple non-scattered packets */
3221 rx_queue->scatter_n = 1;
3222 rx_queue->scatter_len = 0;
3223 n_packets = n_descs;
3224 ++channel->n_rx_merge_events;
3225 channel->n_rx_merge_packets += n_packets;
3226 flags |= EFX_RX_PKT_PREFIX_LEN;
3227 } else {
3228 ++rx_queue->scatter_n;
3229 rx_queue->scatter_len += rx_bytes;
3230 if (rx_cont)
3231 return 0;
3232 n_packets = 1;
3233 }
3234
3235 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_ECRC_ERR)))
3236 flags |= EFX_RX_PKT_DISCARD;
3237
3238 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_IPCKSUM_ERR))) {
3239 channel->n_rx_ip_hdr_chksum_err += n_packets;
3240 } else if (unlikely(EFX_QWORD_FIELD(*event,
3241 ESF_DZ_RX_TCPUDP_CKSUM_ERR))) {
3242 channel->n_rx_tcp_udp_chksum_err += n_packets;
3243 } else if (rx_l4_class == ESE_DZ_L4_CLASS_TCP ||
3244 rx_l4_class == ESE_DZ_L4_CLASS_UDP) {
3245 flags |= EFX_RX_PKT_CSUMMED;
3246 }
3247
3248 if (rx_l4_class == ESE_DZ_L4_CLASS_TCP)
3249 flags |= EFX_RX_PKT_TCP;
3250
3251 channel->irq_mod_score += 2 * n_packets;
3252
3253 /* Handle received packet(s) */
3254 for (i = 0; i < n_packets; i++) {
3255 efx_rx_packet(rx_queue,
3256 rx_queue->removed_count & rx_queue->ptr_mask,
3257 rx_queue->scatter_n, rx_queue->scatter_len,
3258 flags);
3259 rx_queue->removed_count += rx_queue->scatter_n;
3260 }
3261
3262 rx_queue->scatter_n = 0;
3263 rx_queue->scatter_len = 0;
3264
3265 return n_packets;
3266}
3267
3268static int
3269efx_ef10_handle_tx_event(struct efx_channel *channel, efx_qword_t *event)
3270{
3271 struct efx_nic *efx = channel->efx;
3272 struct efx_tx_queue *tx_queue;
3273 unsigned int tx_ev_desc_ptr;
3274 unsigned int tx_ev_q_label;
3275 int tx_descs = 0;
3276
3277 if (unlikely(ACCESS_ONCE(efx->reset_pending)))
3278 return 0;
3279
3280 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_TX_DROP_EVENT)))
3281 return 0;
3282
3283 /* Transmit completion */
3284 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, ESF_DZ_TX_DESCR_INDX);
3285 tx_ev_q_label = EFX_QWORD_FIELD(*event, ESF_DZ_TX_QLABEL);
3286 tx_queue = efx_channel_get_tx_queue(channel,
3287 tx_ev_q_label % EFX_TXQ_TYPES);
3288 tx_descs = ((tx_ev_desc_ptr + 1 - tx_queue->read_count) &
3289 tx_queue->ptr_mask);
3290 efx_xmit_done(tx_queue, tx_ev_desc_ptr & tx_queue->ptr_mask);
3291
3292 return tx_descs;
3293}
3294
3295static void
3296efx_ef10_handle_driver_event(struct efx_channel *channel, efx_qword_t *event)
3297{
3298 struct efx_nic *efx = channel->efx;
3299 int subcode;
3300
3301 subcode = EFX_QWORD_FIELD(*event, ESF_DZ_DRV_SUB_CODE);
3302
3303 switch (subcode) {
3304 case ESE_DZ_DRV_TIMER_EV:
3305 case ESE_DZ_DRV_WAKE_UP_EV:
3306 break;
3307 case ESE_DZ_DRV_START_UP_EV:
3308 /* event queue init complete. ok. */
3309 break;
3310 default:
3311 netif_err(efx, hw, efx->net_dev,
3312 "channel %d unknown driver event type %d"
3313 " (data " EFX_QWORD_FMT ")\n",
3314 channel->channel, subcode,
3315 EFX_QWORD_VAL(*event));
3316
3317 }
3318}
3319
3320static void efx_ef10_handle_driver_generated_event(struct efx_channel *channel,
3321 efx_qword_t *event)
3322{
3323 struct efx_nic *efx = channel->efx;
3324 u32 subcode;
3325
3326 subcode = EFX_QWORD_FIELD(*event, EFX_DWORD_0);
3327
3328 switch (subcode) {
3329 case EFX_EF10_TEST:
3330 channel->event_test_cpu = raw_smp_processor_id();
3331 break;
3332 case EFX_EF10_REFILL:
3333 /* The queue must be empty, so we won't receive any rx
3334 * events, so efx_process_channel() won't refill the
3335 * queue. Refill it here
3336 */
cce28794 3337 efx_fast_push_rx_descriptors(&channel->rx_queue, true);
8127d661
BH		 3338 break;
3339 default:
3340 netif_err(efx, hw, efx->net_dev,
3341 "channel %d unknown driver event type %u"
3342 " (data " EFX_QWORD_FMT ")\n",
3343 channel->channel, (unsigned) subcode,
3344 EFX_QWORD_VAL(*event));
3345 }
3346}
3347
3348static int efx_ef10_ev_process(struct efx_channel *channel, int quota)
3349{
3350 struct efx_nic *efx = channel->efx;
3351 efx_qword_t event, *p_event;
3352 unsigned int read_ptr;
3353 int ev_code;
3354 int tx_descs = 0;
3355 int spent = 0;
3356
75363a46
EB		 3357 if (quota <= 0)
3358 return spent;
3359
8127d661
BH		 3360 read_ptr = channel->eventq_read_ptr;
3361
3362 for (;;) {
3363 p_event = efx_event(channel, read_ptr);
3364 event = *p_event;
3365
3366 if (!efx_event_present(&event))
3367 break;
3368
3369 EFX_SET_QWORD(*p_event);
3370
3371 ++read_ptr;
3372
3373 ev_code = EFX_QWORD_FIELD(event, ESF_DZ_EV_CODE);
3374
3375 netif_vdbg(efx, drv, efx->net_dev,
3376 "processing event on %d " EFX_QWORD_FMT "\n",
3377 channel->channel, EFX_QWORD_VAL(event));
3378
3379 switch (ev_code) {
3380 case ESE_DZ_EV_CODE_MCDI_EV:
3381 efx_mcdi_process_event(channel, &event);
3382 break;
3383 case ESE_DZ_EV_CODE_RX_EV:
3384 spent += efx_ef10_handle_rx_event(channel, &event);
3385 if (spent >= quota) {
3386 /* XXX can we split a merged event to
3387 * avoid going over-quota?
3388 */
3389 spent = quota;
3390 goto out;
3391 }
3392 break;
3393 case ESE_DZ_EV_CODE_TX_EV:
3394 tx_descs += efx_ef10_handle_tx_event(channel, &event);
3395 if (tx_descs > efx->txq_entries) {
3396 spent = quota;
3397 goto out;
3398 } else if (++spent == quota) {
3399 goto out;
3400 }
3401 break;
3402 case ESE_DZ_EV_CODE_DRIVER_EV:
3403 efx_ef10_handle_driver_event(channel, &event);
3404 if (++spent == quota)
3405 goto out;
3406 break;
3407 case EFX_EF10_DRVGEN_EV:
3408 efx_ef10_handle_driver_generated_event(channel, &event);
3409 break;
3410 default:
3411 netif_err(efx, hw, efx->net_dev,
3412 "channel %d unknown event type %d"
3413 " (data " EFX_QWORD_FMT ")\n",
3414 channel->channel, ev_code,
3415 EFX_QWORD_VAL(event));
3416 }
3417 }
3418
3419out:
3420 channel->eventq_read_ptr = read_ptr;
3421 return spent;
3422}
3423
3424static void efx_ef10_ev_read_ack(struct efx_channel *channel)
3425{
3426 struct efx_nic *efx = channel->efx;
3427 efx_dword_t rptr;
3428
3429 if (EFX_EF10_WORKAROUND_35388(efx)) {
3430 BUILD_BUG_ON(EFX_MIN_EVQ_SIZE <
3431 (1 << ERF_DD_EVQ_IND_RPTR_WIDTH));
3432 BUILD_BUG_ON(EFX_MAX_EVQ_SIZE >
3433 (1 << 2 * ERF_DD_EVQ_IND_RPTR_WIDTH));
3434
3435 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
3436 EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH,
3437 ERF_DD_EVQ_IND_RPTR,
3438 (channel->eventq_read_ptr &
3439 channel->eventq_mask) >>
3440 ERF_DD_EVQ_IND_RPTR_WIDTH);
3441 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
3442 channel->channel);
3443 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
3444 EFE_DD_EVQ_IND_RPTR_FLAGS_LOW,
3445 ERF_DD_EVQ_IND_RPTR,
3446 channel->eventq_read_ptr &
3447 ((1 << ERF_DD_EVQ_IND_RPTR_WIDTH) - 1));
3448 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
3449 channel->channel);
3450 } else {
3451 EFX_POPULATE_DWORD_1(rptr, ERF_DZ_EVQ_RPTR,
3452 channel->eventq_read_ptr &
3453 channel->eventq_mask);
3454 efx_writed_page(efx, &rptr, ER_DZ_EVQ_RPTR, channel->channel);
3455 }
3456}
3457
3458static void efx_ef10_ev_test_generate(struct efx_channel *channel)
3459{
3460 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
3461 struct efx_nic *efx = channel->efx;
3462 efx_qword_t event;
3463 int rc;
3464
3465 EFX_POPULATE_QWORD_2(event,
3466 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
3467 ESF_DZ_EV_DATA, EFX_EF10_TEST);
3468
3469 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
3470
3471 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
3472 * already swapped the data to little-endian order.
3473 */
3474 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
3475 sizeof(efx_qword_t));
3476
3477 rc = efx_mcdi_rpc(efx, MC_CMD_DRIVER_EVENT, inbuf, sizeof(inbuf),
3478 NULL, 0, NULL);
3479 if (rc != 0)
3480 goto fail;
3481
3482 return;
3483
3484fail:
3485 WARN_ON(true);
3486 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
3487}
3488
3489void efx_ef10_handle_drain_event(struct efx_nic *efx)
3490{
3491 if (atomic_dec_and_test(&efx->active_queues))
3492 wake_up(&efx->flush_wq);
3493
3494 WARN_ON(atomic_read(&efx->active_queues) < 0);
3495}
3496
3497static int efx_ef10_fini_dmaq(struct efx_nic *efx)
3498{
3499 struct efx_ef10_nic_data *nic_data = efx->nic_data;
3500 struct efx_channel *channel;
3501 struct efx_tx_queue *tx_queue;
3502 struct efx_rx_queue *rx_queue;
3503 int pending;
3504
3505 /* If the MC has just rebooted, the TX/RX queues will have already been
3506 * torn down, but efx->active_queues needs to be set to zero.
3507 */
3508 if (nic_data->must_realloc_vis) {
3509 atomic_set(&efx->active_queues, 0);
3510 return 0;
3511 }
3512
3513 /* Do not attempt to write to the NIC during EEH recovery */
3514 if (efx->state != STATE_RECOVERY) {
3515 efx_for_each_channel(channel, efx) {
3516 efx_for_each_channel_rx_queue(rx_queue, channel)
3517 efx_ef10_rx_fini(rx_queue);
3518 efx_for_each_channel_tx_queue(tx_queue, channel)
3519 efx_ef10_tx_fini(tx_queue);
3520 }
3521
3522 wait_event_timeout(efx->flush_wq,
3523 atomic_read(&efx->active_queues) == 0,
3524 msecs_to_jiffies(EFX_MAX_FLUSH_TIME));
3525 pending = atomic_read(&efx->active_queues);
3526 if (pending) {
3527 netif_err(efx, hw, efx->net_dev, "failed to flush %d queues\n",
3528 pending);
3529 return -ETIMEDOUT;
3530 }
3531 }
3532
3533 return 0;
3534}
3535
e283546c
EC		 3536static void efx_ef10_prepare_flr(struct efx_nic *efx)
3537{
3538 atomic_set(&efx->active_queues, 0);
3539}
3540
8127d661
BH		 3541static bool efx_ef10_filter_equal(const struct efx_filter_spec *left,
3542 const struct efx_filter_spec *right)
3543{
3544 if ((left->match_flags ^ right->match_flags) |
3545 ((left->flags ^ right->flags) &
3546 (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)))
3547 return false;
3548
3549 return memcmp(&left->outer_vid, &right->outer_vid,
3550 sizeof(struct efx_filter_spec) -
3551 offsetof(struct efx_filter_spec, outer_vid)) == 0;
3552}
3553
3554static unsigned int efx_ef10_filter_hash(const struct efx_filter_spec *spec)
3555{
3556 BUILD_BUG_ON(offsetof(struct efx_filter_spec, outer_vid) & 3);
3557 return jhash2((const u32 *)&spec->outer_vid,
3558 (sizeof(struct efx_filter_spec) -
3559 offsetof(struct efx_filter_spec, outer_vid)) / 4,
3560 0);
3561 /* XXX should we randomise the initval? */
3562}
3563
3564/* Decide whether a filter should be exclusive or else should allow
3565 * delivery to additional recipients. Currently we decide that
3566 * filters for specific local unicast MAC and IP addresses are
3567 * exclusive.
3568 */
3569static bool efx_ef10_filter_is_exclusive(const struct efx_filter_spec *spec)
3570{
3571 if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC &&
3572 !is_multicast_ether_addr(spec->loc_mac))
3573 return true;
3574
3575 if ((spec->match_flags &
3576 (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) ==
3577 (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) {
3578 if (spec->ether_type == htons(ETH_P_IP) &&
3579 !ipv4_is_multicast(spec->loc_host[0]))
3580 return true;
3581 if (spec->ether_type == htons(ETH_P_IPV6) &&
3582 ((const u8 *)spec->loc_host)[0] != 0xff)
3583 return true;
3584 }
3585
3586 return false;
3587}
3588
3589static struct efx_filter_spec *
3590efx_ef10_filter_entry_spec(const struct efx_ef10_filter_table *table,
3591 unsigned int filter_idx)
3592{
3593 return (struct efx_filter_spec *)(table->entry[filter_idx].spec &
3594 ~EFX_EF10_FILTER_FLAGS);
3595}
3596
3597static unsigned int
3598efx_ef10_filter_entry_flags(const struct efx_ef10_filter_table *table,
3599 unsigned int filter_idx)
3600{
3601 return table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAGS;
3602}
3603
3604static void
3605efx_ef10_filter_set_entry(struct efx_ef10_filter_table *table,
3606 unsigned int filter_idx,
3607 const struct efx_filter_spec *spec,
3608 unsigned int flags)
3609{
3610 table->entry[filter_idx].spec = (unsigned long)spec | flags;
3611}
3612
9b410801
EC		 3613static void
3614efx_ef10_filter_push_prep_set_match_fields(struct efx_nic *efx,
3615 const struct efx_filter_spec *spec,
3616 efx_dword_t *inbuf)
3617{
3618 enum efx_encap_type encap_type = efx_filter_get_encap_type(spec);
3619 u32 match_fields = 0, uc_match, mc_match;
3620
3621 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3622 efx_ef10_filter_is_exclusive(spec) ?
3623 MC_CMD_FILTER_OP_IN_OP_INSERT :
3624 MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE);
3625
3626 /* Convert match flags and values. Unlike almost
3627 * everything else in MCDI, these fields are in
3628 * network byte order.
3629 */
3630#define COPY_VALUE(value, mcdi_field) \
3631 do { \
3632 match_fields |= \
3633 1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \
3634 mcdi_field ## _LBN; \
3635 BUILD_BUG_ON( \
3636 MC_CMD_FILTER_OP_IN_ ## mcdi_field ## _LEN < \
3637 sizeof(value)); \
3638 memcpy(MCDI_PTR(inbuf, FILTER_OP_IN_ ## mcdi_field), \
3639 &value, sizeof(value)); \
3640 } while (0)
3641#define COPY_FIELD(gen_flag, gen_field, mcdi_field) \
3642 if (spec->match_flags & EFX_FILTER_MATCH_ ## gen_flag) { \
3643 COPY_VALUE(spec->gen_field, mcdi_field); \
3644 }
3645 /* Handle encap filters first. They will always be mismatch
3646 * (unknown UC or MC) filters
3647 */
3648 if (encap_type) {
3649 /* ether_type and outer_ip_proto need to be variables
3650 * because COPY_VALUE wants to memcpy them
3651 */
3652 __be16 ether_type =
3653 htons(encap_type & EFX_ENCAP_FLAG_IPV6 ?
3654 ETH_P_IPV6 : ETH_P_IP);
3655 u8 vni_type = MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_GENEVE;
3656 u8 outer_ip_proto;
3657
3658 switch (encap_type & EFX_ENCAP_TYPES_MASK) {
3659 case EFX_ENCAP_TYPE_VXLAN:
3660 vni_type = MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_VXLAN;
3661 /* fallthrough */
3662 case EFX_ENCAP_TYPE_GENEVE:
3663 COPY_VALUE(ether_type, ETHER_TYPE);
3664 outer_ip_proto = IPPROTO_UDP;
3665 COPY_VALUE(outer_ip_proto, IP_PROTO);
3666 /* We always need to set the type field, even
3667 * though we're not matching on the TNI.
3668 */
3669 MCDI_POPULATE_DWORD_1(inbuf,
3670 FILTER_OP_EXT_IN_VNI_OR_VSID,
3671 FILTER_OP_EXT_IN_VNI_TYPE,
3672 vni_type);
3673 break;
3674 case EFX_ENCAP_TYPE_NVGRE:
3675 COPY_VALUE(ether_type, ETHER_TYPE);
3676 outer_ip_proto = IPPROTO_GRE;
3677 COPY_VALUE(outer_ip_proto, IP_PROTO);
3678 break;
3679 default:
3680 WARN_ON(1);
3681 }
3682
3683 uc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_LBN;
3684 mc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_LBN;
3685 } else {
3686 uc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_LBN;
3687 mc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_LBN;
3688 }
3689
3690 if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC_IG)
3691 match_fields |=
3692 is_multicast_ether_addr(spec->loc_mac) ?
3693 1 << mc_match :
3694 1 << uc_match;
3695 COPY_FIELD(REM_HOST, rem_host, SRC_IP);
3696 COPY_FIELD(LOC_HOST, loc_host, DST_IP);
3697 COPY_FIELD(REM_MAC, rem_mac, SRC_MAC);
3698 COPY_FIELD(REM_PORT, rem_port, SRC_PORT);
3699 COPY_FIELD(LOC_MAC, loc_mac, DST_MAC);
3700 COPY_FIELD(LOC_PORT, loc_port, DST_PORT);
3701 COPY_FIELD(ETHER_TYPE, ether_type, ETHER_TYPE);
3702 COPY_FIELD(INNER_VID, inner_vid, INNER_VLAN);
3703 COPY_FIELD(OUTER_VID, outer_vid, OUTER_VLAN);
3704 COPY_FIELD(IP_PROTO, ip_proto, IP_PROTO);
3705#undef COPY_FIELD
3706#undef COPY_VALUE
3707 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_MATCH_FIELDS,
3708 match_fields);
3709}
3710
8127d661
BH		 3711static void efx_ef10_filter_push_prep(struct efx_nic *efx,
3712 const struct efx_filter_spec *spec,
3713 efx_dword_t *inbuf, u64 handle,
3714 bool replacing)
3715{
3716 struct efx_ef10_nic_data *nic_data = efx->nic_data;
dcb4123c 3717 u32 flags = spec->flags;
8127d661 3718
9b410801 3719 memset(inbuf, 0, MC_CMD_FILTER_OP_EXT_IN_LEN);
8127d661 3720
dcb4123c
JC		 3721 /* Remove RSS flag if we don't have an RSS context. */
3722 if (flags & EFX_FILTER_FLAG_RX_RSS &&
3723 spec->rss_context == EFX_FILTER_RSS_CONTEXT_DEFAULT &&
3724 nic_data->rx_rss_context == EFX_EF10_RSS_CONTEXT_INVALID)
3725 flags &= ~EFX_FILTER_FLAG_RX_RSS;
3726
8127d661
BH		 3727 if (replacing) {
3728 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3729 MC_CMD_FILTER_OP_IN_OP_REPLACE);
3730 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, handle);
3731 } else {
9b410801 3732 efx_ef10_filter_push_prep_set_match_fields(efx, spec, inbuf);
8127d661
BH		 3733 }
3734
45b2449e 3735 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_PORT_ID, nic_data->vport_id);
8127d661
BH		 3736 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_DEST,
3737 spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ?
3738 MC_CMD_FILTER_OP_IN_RX_DEST_DROP :
3739 MC_CMD_FILTER_OP_IN_RX_DEST_HOST);
e3d36293 3740 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DOMAIN, 0);
8127d661
BH		 3741 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DEST,
3742 MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT);
a0bc3487
BH		 3743 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_QUEUE,
3744 spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ?
3745 0 : spec->dmaq_id);
8127d661 3746 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_MODE,
dcb4123c 3747 (flags & EFX_FILTER_FLAG_RX_RSS) ?
8127d661
BH		 3748 MC_CMD_FILTER_OP_IN_RX_MODE_RSS :
3749 MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE);
dcb4123c 3750 if (flags & EFX_FILTER_FLAG_RX_RSS)
8127d661
BH		 3751 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_CONTEXT,
3752 spec->rss_context !=
3753 EFX_FILTER_RSS_CONTEXT_DEFAULT ?
3754 spec->rss_context : nic_data->rx_rss_context);
3755}
3756
3757static int efx_ef10_filter_push(struct efx_nic *efx,
3758 const struct efx_filter_spec *spec,
3759 u64 *handle, bool replacing)
3760{
9b410801
EC		 3761 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_EXT_IN_LEN);
3762 MCDI_DECLARE_BUF(outbuf, MC_CMD_FILTER_OP_EXT_OUT_LEN);
8127d661
BH		 3763 int rc;
3764
3765 efx_ef10_filter_push_prep(efx, spec, inbuf, *handle, replacing);
3766 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
3767 outbuf, sizeof(outbuf), NULL);
3768 if (rc == 0)
3769 *handle = MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE);
065e64c4
BH		 3770 if (rc == -ENOSPC)
3771 rc = -EBUSY; /* to match efx_farch_filter_insert() */
8127d661
BH		 3772 return rc;
3773}
3774
7ac0dd9d 3775static u32 efx_ef10_filter_mcdi_flags_from_spec(const struct efx_filter_spec *spec)
8127d661 3776{
9b410801 3777 enum efx_encap_type encap_type = efx_filter_get_encap_type(spec);
7ac0dd9d 3778 unsigned int match_flags = spec->match_flags;
9b410801 3779 unsigned int uc_match, mc_match;
7ac0dd9d
AR		 3780 u32 mcdi_flags = 0;
3781
9b410801
EC		 3782#define MAP_FILTER_TO_MCDI_FLAG(gen_flag, mcdi_field, encap) { \
3783 unsigned int old_match_flags = match_flags; \
7ac0dd9d
AR		 3784 match_flags &= ~EFX_FILTER_MATCH_ ## gen_flag; \
3785 if (match_flags != old_match_flags) \
3786 mcdi_flags |= \
9b410801
EC		 3787 (1 << ((encap) ? \
3788 MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_ ## \
3789 mcdi_field ## _LBN : \
3790 MC_CMD_FILTER_OP_EXT_IN_MATCH_ ##\
3791 mcdi_field ## _LBN)); \
7ac0dd9d 3792 }
9b410801
EC		 3793 /* inner or outer based on encap type */
3794 MAP_FILTER_TO_MCDI_FLAG(REM_HOST, SRC_IP, encap_type);
3795 MAP_FILTER_TO_MCDI_FLAG(LOC_HOST, DST_IP, encap_type);
3796 MAP_FILTER_TO_MCDI_FLAG(REM_MAC, SRC_MAC, encap_type);
3797 MAP_FILTER_TO_MCDI_FLAG(REM_PORT, SRC_PORT, encap_type);
3798 MAP_FILTER_TO_MCDI_FLAG(LOC_MAC, DST_MAC, encap_type);
3799 MAP_FILTER_TO_MCDI_FLAG(LOC_PORT, DST_PORT, encap_type);
3800 MAP_FILTER_TO_MCDI_FLAG(ETHER_TYPE, ETHER_TYPE, encap_type);
3801 MAP_FILTER_TO_MCDI_FLAG(IP_PROTO, IP_PROTO, encap_type);
3802 /* always outer */
3803 MAP_FILTER_TO_MCDI_FLAG(INNER_VID, INNER_VLAN, false);
3804 MAP_FILTER_TO_MCDI_FLAG(OUTER_VID, OUTER_VLAN, false);
7ac0dd9d
AR		 3805#undef MAP_FILTER_TO_MCDI_FLAG
3806
9b410801
EC		 3807 /* special handling for encap type, and mismatch */
3808 if (encap_type) {
3809 match_flags &= ~EFX_FILTER_MATCH_ENCAP_TYPE;
3810 mcdi_flags |=
3811 (1 << MC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_LBN);
3812 mcdi_flags |= (1 << MC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_LBN);
3813
3814 uc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_LBN;
3815 mc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_LBN;
3816 } else {
3817 uc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_LBN;
3818 mc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_LBN;
3819 }
3820
3821 if (match_flags & EFX_FILTER_MATCH_LOC_MAC_IG) {
3822 match_flags &= ~EFX_FILTER_MATCH_LOC_MAC_IG;
3823 mcdi_flags |=
3824 is_multicast_ether_addr(spec->loc_mac) ?
3825 1 << mc_match :
3826 1 << uc_match;
3827 }
3828
7ac0dd9d
AR		 3829 /* Did we map them all? */
3830 WARN_ON_ONCE(match_flags);
3831
3832 return mcdi_flags;
3833}
3834
3835static int efx_ef10_filter_pri(struct efx_ef10_filter_table *table,
3836 const struct efx_filter_spec *spec)
3837{
3838 u32 mcdi_flags = efx_ef10_filter_mcdi_flags_from_spec(spec);
8127d661
BH		 3839 unsigned int match_pri;
3840
3841 for (match_pri = 0;
3842 match_pri < table->rx_match_count;
3843 match_pri++)
7ac0dd9d 3844 if (table->rx_match_mcdi_flags[match_pri] == mcdi_flags)
8127d661
BH		 3845 return match_pri;
3846
3847 return -EPROTONOSUPPORT;
3848}
3849
3850static s32 efx_ef10_filter_insert(struct efx_nic *efx,
3851 struct efx_filter_spec *spec,
3852 bool replace_equal)
3853{
3854 struct efx_ef10_filter_table *table = efx->filter_state;
3855 DECLARE_BITMAP(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
3856 struct efx_filter_spec *saved_spec;
3857 unsigned int match_pri, hash;
3858 unsigned int priv_flags;
3859 bool replacing = false;
3860 int ins_index = -1;
3861 DEFINE_WAIT(wait);
3862 bool is_mc_recip;
3863 s32 rc;
3864
3865 /* For now, only support RX filters */
3866 if ((spec->flags & (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)) !=
3867 EFX_FILTER_FLAG_RX)
3868 return -EINVAL;
3869
7ac0dd9d 3870 rc = efx_ef10_filter_pri(table, spec);
8127d661
BH		 3871 if (rc < 0)
3872 return rc;
3873 match_pri = rc;
3874
3875 hash = efx_ef10_filter_hash(spec);
3876 is_mc_recip = efx_filter_is_mc_recipient(spec);
3877 if (is_mc_recip)
3878 bitmap_zero(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
3879
3880 /* Find any existing filters with the same match tuple or
3881 * else a free slot to insert at. If any of them are busy,
3882 * we have to wait and retry.
3883 */
3884 for (;;) {
3885 unsigned int depth = 1;
3886 unsigned int i;
3887
3888 spin_lock_bh(&efx->filter_lock);
3889
3890 for (;;) {
3891 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
3892 saved_spec = efx_ef10_filter_entry_spec(table, i);
3893
3894 if (!saved_spec) {
3895 if (ins_index < 0)
3896 ins_index = i;
3897 } else if (efx_ef10_filter_equal(spec, saved_spec)) {
3898 if (table->entry[i].spec &
3899 EFX_EF10_FILTER_FLAG_BUSY)
3900 break;
3901 if (spec->priority < saved_spec->priority &&
7665d1ab 3902 spec->priority != EFX_FILTER_PRI_AUTO) {
8127d661
BH		 3903 rc = -EPERM;
3904 goto out_unlock;
3905 }
3906 if (!is_mc_recip) {
3907 /* This is the only one */
3908 if (spec->priority ==
3909 saved_spec->priority &&
3910 !replace_equal) {
3911 rc = -EEXIST;
3912 goto out_unlock;
3913 }
3914 ins_index = i;
3915 goto found;
3916 } else if (spec->priority >
3917 saved_spec->priority ||
3918 (spec->priority ==
3919 saved_spec->priority &&
3920 replace_equal)) {
3921 if (ins_index < 0)
3922 ins_index = i;
3923 else
3924 __set_bit(depth, mc_rem_map);
3925 }
3926 }
3927
3928 /* Once we reach the maximum search depth, use
3929 * the first suitable slot or return -EBUSY if
3930 * there was none
3931 */
3932 if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) {
3933 if (ins_index < 0) {
3934 rc = -EBUSY;
3935 goto out_unlock;
3936 }
3937 goto found;
3938 }
3939
3940 ++depth;
3941 }
3942
3943 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE);
3944 spin_unlock_bh(&efx->filter_lock);
3945 schedule();
3946 }
3947
3948found:
3949 /* Create a software table entry if necessary, and mark it
3950 * busy. We might yet fail to insert, but any attempt to
3951 * insert a conflicting filter while we're waiting for the
3952 * firmware must find the busy entry.
3953 */
3954 saved_spec = efx_ef10_filter_entry_spec(table, ins_index);
3955 if (saved_spec) {
7665d1ab
BH		 3956 if (spec->priority == EFX_FILTER_PRI_AUTO &&
3957 saved_spec->priority >= EFX_FILTER_PRI_AUTO) {
8127d661 3958 /* Just make sure it won't be removed */
7665d1ab
BH		 3959 if (saved_spec->priority > EFX_FILTER_PRI_AUTO)
3960 saved_spec->flags |= EFX_FILTER_FLAG_RX_OVER_AUTO;
8127d661 3961 table->entry[ins_index].spec &=
b59e6ef8 3962 ~EFX_EF10_FILTER_FLAG_AUTO_OLD;
8127d661
BH		 3963 rc = ins_index;
3964 goto out_unlock;
3965 }
3966 replacing = true;
3967 priv_flags = efx_ef10_filter_entry_flags(table, ins_index);
3968 } else {
3969 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC);
3970 if (!saved_spec) {
3971 rc = -ENOMEM;
3972 goto out_unlock;
3973 }
3974 *saved_spec = *spec;
3975 priv_flags = 0;
3976 }
3977 efx_ef10_filter_set_entry(table, ins_index, saved_spec,
3978 priv_flags | EFX_EF10_FILTER_FLAG_BUSY);
3979
3980 /* Mark lower-priority multicast recipients busy prior to removal */
3981 if (is_mc_recip) {
3982 unsigned int depth, i;
3983
3984 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
3985 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
3986 if (test_bit(depth, mc_rem_map))
3987 table->entry[i].spec |=
3988 EFX_EF10_FILTER_FLAG_BUSY;
3989 }
3990 }
3991
3992 spin_unlock_bh(&efx->filter_lock);
3993
3994 rc = efx_ef10_filter_push(efx, spec, &table->entry[ins_index].handle,
3995 replacing);
3996
3997 /* Finalise the software table entry */
3998 spin_lock_bh(&efx->filter_lock);
3999 if (rc == 0) {
4000 if (replacing) {
4001 /* Update the fields that may differ */
7665d1ab
BH		 4002 if (saved_spec->priority == EFX_FILTER_PRI_AUTO)
4003 saved_spec->flags |=
4004 EFX_FILTER_FLAG_RX_OVER_AUTO;
8127d661 4005 saved_spec->priority = spec->priority;
7665d1ab 4006 saved_spec->flags &= EFX_FILTER_FLAG_RX_OVER_AUTO;
8127d661
BH		 4007 saved_spec->flags |= spec->flags;
4008 saved_spec->rss_context = spec->rss_context;
4009 saved_spec->dmaq_id = spec->dmaq_id;
4010 }
4011 } else if (!replacing) {
4012 kfree(saved_spec);
4013 saved_spec = NULL;
4014 }
4015 efx_ef10_filter_set_entry(table, ins_index, saved_spec, priv_flags);
4016
4017 /* Remove and finalise entries for lower-priority multicast
4018 * recipients
4019 */
4020 if (is_mc_recip) {
4021 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
4022 unsigned int depth, i;
4023
4024 memset(inbuf, 0, sizeof(inbuf));
4025
4026 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
4027 if (!test_bit(depth, mc_rem_map))
4028 continue;
4029
4030 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
4031 saved_spec = efx_ef10_filter_entry_spec(table, i);
4032 priv_flags = efx_ef10_filter_entry_flags(table, i);
4033
4034 if (rc == 0) {
4035 spin_unlock_bh(&efx->filter_lock);
4036 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
4037 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
4038 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
4039 table->entry[i].handle);
4040 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP,
4041 inbuf, sizeof(inbuf),
4042 NULL, 0, NULL);
4043 spin_lock_bh(&efx->filter_lock);
4044 }
4045
4046 if (rc == 0) {
4047 kfree(saved_spec);
4048 saved_spec = NULL;
4049 priv_flags = 0;
4050 } else {
4051 priv_flags &= ~EFX_EF10_FILTER_FLAG_BUSY;
4052 }
4053 efx_ef10_filter_set_entry(table, i, saved_spec,
4054 priv_flags);
4055 }
4056 }
4057
4058 /* If successful, return the inserted filter ID */
4059 if (rc == 0)
4060 rc = match_pri * HUNT_FILTER_TBL_ROWS + ins_index;
4061
4062 wake_up_all(&table->waitq);
4063out_unlock:
4064 spin_unlock_bh(&efx->filter_lock);
4065 finish_wait(&table->waitq, &wait);
4066 return rc;
4067}
4068
9fd8095d 4069static void efx_ef10_filter_update_rx_scatter(struct efx_nic *efx)
8127d661
BH		 4070{
4071 /* no need to do anything here on EF10 */
4072}
4073
4074/* Remove a filter.
b59e6ef8
BH		 4075 * If !by_index, remove by ID
4076 * If by_index, remove by index
8127d661
BH		 4077 * Filter ID may come from userland and must be range-checked.
4078 */
4079static int efx_ef10_filter_remove_internal(struct efx_nic *efx,
fbd79120 4080 unsigned int priority_mask,
b59e6ef8 4081 u32 filter_id, bool by_index)
8127d661
BH		 4082{
4083 unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS;
4084 struct efx_ef10_filter_table *table = efx->filter_state;
4085 MCDI_DECLARE_BUF(inbuf,
4086 MC_CMD_FILTER_OP_IN_HANDLE_OFST +
4087 MC_CMD_FILTER_OP_IN_HANDLE_LEN);
4088 struct efx_filter_spec *spec;
4089 DEFINE_WAIT(wait);
4090 int rc;
4091
4092 /* Find the software table entry and mark it busy. Don't
4093 * remove it yet; any attempt to update while we're waiting
4094 * for the firmware must find the busy entry.
4095 */
4096 for (;;) {
4097 spin_lock_bh(&efx->filter_lock);
4098 if (!(table->entry[filter_idx].spec &
4099 EFX_EF10_FILTER_FLAG_BUSY))
4100 break;
4101 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE);
4102 spin_unlock_bh(&efx->filter_lock);
4103 schedule();
4104 }
7665d1ab 4105
8127d661 4106 spec = efx_ef10_filter_entry_spec(table, filter_idx);
7665d1ab 4107 if (!spec ||
b59e6ef8 4108 (!by_index &&
7ac0dd9d 4109 efx_ef10_filter_pri(table, spec) !=
8127d661
BH		 4110 filter_id / HUNT_FILTER_TBL_ROWS)) {
4111 rc = -ENOENT;
4112 goto out_unlock;
4113 }
7665d1ab
BH		 4114
4115 if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO &&
fbd79120 4116 priority_mask == (1U << EFX_FILTER_PRI_AUTO)) {
7665d1ab
BH		 4117 /* Just remove flags */
4118 spec->flags &= ~EFX_FILTER_FLAG_RX_OVER_AUTO;
b59e6ef8 4119 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_AUTO_OLD;
7665d1ab
BH		 4120 rc = 0;
4121 goto out_unlock;
4122 }
4123
fbd79120 4124 if (!(priority_mask & (1U << spec->priority))) {
7665d1ab
BH		 4125 rc = -ENOENT;
4126 goto out_unlock;
4127 }
4128
8127d661
BH		 4129 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
4130 spin_unlock_bh(&efx->filter_lock);
4131
7665d1ab 4132 if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO) {
b59e6ef8 4133 /* Reset to an automatic filter */
8127d661
BH		 4134
4135 struct efx_filter_spec new_spec = *spec;
4136
7665d1ab 4137 new_spec.priority = EFX_FILTER_PRI_AUTO;
8127d661 4138 new_spec.flags = (EFX_FILTER_FLAG_RX |
f1c2ef40
BK		 4139 (efx_rss_enabled(efx) ?
4140 EFX_FILTER_FLAG_RX_RSS : 0));
8127d661
BH		 4141 new_spec.dmaq_id = 0;
4142 new_spec.rss_context = EFX_FILTER_RSS_CONTEXT_DEFAULT;
4143 rc = efx_ef10_filter_push(efx, &new_spec,
4144 &table->entry[filter_idx].handle,
4145 true);
4146
4147 spin_lock_bh(&efx->filter_lock);
4148 if (rc == 0)
4149 *spec = new_spec;
4150 } else {
4151 /* Really remove the filter */
4152
4153 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
4154 efx_ef10_filter_is_exclusive(spec) ?
4155 MC_CMD_FILTER_OP_IN_OP_REMOVE :
4156 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
4157 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
4158 table->entry[filter_idx].handle);
4159 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP,
4160 inbuf, sizeof(inbuf), NULL, 0, NULL);
4161
4162 spin_lock_bh(&efx->filter_lock);
4163 if (rc == 0) {
4164 kfree(spec);
4165 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
4166 }
4167 }
7665d1ab 4168
8127d661
BH		 4169 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY;
4170 wake_up_all(&table->waitq);
4171out_unlock:
4172 spin_unlock_bh(&efx->filter_lock);
4173 finish_wait(&table->waitq, &wait);
4174 return rc;
4175}
4176
4177static int efx_ef10_filter_remove_safe(struct efx_nic *efx,
4178 enum efx_filter_priority priority,
4179 u32 filter_id)
4180{
fbd79120
BH		 4181 return efx_ef10_filter_remove_internal(efx, 1U << priority,
4182 filter_id, false);
8127d661
BH		 4183}
4184
12fb0da4
EC		 4185static u32 efx_ef10_filter_get_unsafe_id(struct efx_nic *efx, u32 filter_id)
4186{
4187 return filter_id % HUNT_FILTER_TBL_ROWS;
4188}
4189
8c915620
EC		 4190static void efx_ef10_filter_remove_unsafe(struct efx_nic *efx,
4191 enum efx_filter_priority priority,
4192 u32 filter_id)
12fb0da4 4193{
8c915620
EC		 4194 if (filter_id == EFX_EF10_FILTER_ID_INVALID)
4195 return;
4196 efx_ef10_filter_remove_internal(efx, 1U << priority, filter_id, true);
12fb0da4
EC		 4197}
4198
8127d661
BH		 4199static int efx_ef10_filter_get_safe(struct efx_nic *efx,
4200 enum efx_filter_priority priority,
4201 u32 filter_id, struct efx_filter_spec *spec)
4202{
4203 unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS;
4204 struct efx_ef10_filter_table *table = efx->filter_state;
4205 const struct efx_filter_spec *saved_spec;
4206 int rc;
4207
4208 spin_lock_bh(&efx->filter_lock);
4209 saved_spec = efx_ef10_filter_entry_spec(table, filter_idx);
4210 if (saved_spec && saved_spec->priority == priority &&
7ac0dd9d 4211 efx_ef10_filter_pri(table, saved_spec) ==
8127d661
BH		 4212 filter_id / HUNT_FILTER_TBL_ROWS) {
4213 *spec = *saved_spec;
4214 rc = 0;
4215 } else {
4216 rc = -ENOENT;
4217 }
4218 spin_unlock_bh(&efx->filter_lock);
4219 return rc;
4220}
4221
fbd79120 4222static int efx_ef10_filter_clear_rx(struct efx_nic *efx,
8127d661
BH		 4223 enum efx_filter_priority priority)
4224{
fbd79120
BH		 4225 unsigned int priority_mask;
4226 unsigned int i;
4227 int rc;
4228
4229 priority_mask = (((1U << (priority + 1)) - 1) &
4230 ~(1U << EFX_FILTER_PRI_AUTO));
4231
4232 for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) {
4233 rc = efx_ef10_filter_remove_internal(efx, priority_mask,
4234 i, true);
4235 if (rc && rc != -ENOENT)
4236 return rc;
4237 }
4238
4239 return 0;
8127d661
BH		 4240}
4241
4242static u32 efx_ef10_filter_count_rx_used(struct efx_nic *efx,
4243 enum efx_filter_priority priority)
4244{
4245 struct efx_ef10_filter_table *table = efx->filter_state;
4246 unsigned int filter_idx;
4247 s32 count = 0;
4248
4249 spin_lock_bh(&efx->filter_lock);
4250 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
4251 if (table->entry[filter_idx].spec &&
4252 efx_ef10_filter_entry_spec(table, filter_idx)->priority ==
4253 priority)
4254 ++count;
4255 }
4256 spin_unlock_bh(&efx->filter_lock);
4257 return count;
4258}
4259
4260static u32 efx_ef10_filter_get_rx_id_limit(struct efx_nic *efx)
4261{
4262 struct efx_ef10_filter_table *table = efx->filter_state;
4263
4264 return table->rx_match_count * HUNT_FILTER_TBL_ROWS;
4265}
4266
4267static s32 efx_ef10_filter_get_rx_ids(struct efx_nic *efx,
4268 enum efx_filter_priority priority,
4269 u32 *buf, u32 size)
4270{
4271 struct efx_ef10_filter_table *table = efx->filter_state;
4272 struct efx_filter_spec *spec;
4273 unsigned int filter_idx;
4274 s32 count = 0;
4275
4276 spin_lock_bh(&efx->filter_lock);
4277 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
4278 spec = efx_ef10_filter_entry_spec(table, filter_idx);
4279 if (spec && spec->priority == priority) {
4280 if (count == size) {
4281 count = -EMSGSIZE;
4282 break;
4283 }
7ac0dd9d 4284 buf[count++] = (efx_ef10_filter_pri(table, spec) *
8127d661
BH		 4285 HUNT_FILTER_TBL_ROWS +
4286 filter_idx);
4287 }
4288 }
4289 spin_unlock_bh(&efx->filter_lock);
4290 return count;
4291}
4292
4293#ifdef CONFIG_RFS_ACCEL
4294
4295static efx_mcdi_async_completer efx_ef10_filter_rfs_insert_complete;
4296
4297static s32 efx_ef10_filter_rfs_insert(struct efx_nic *efx,
4298 struct efx_filter_spec *spec)
4299{
4300 struct efx_ef10_filter_table *table = efx->filter_state;
4301 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
4302 struct efx_filter_spec *saved_spec;
4303 unsigned int hash, i, depth = 1;
4304 bool replacing = false;
4305 int ins_index = -1;
4306 u64 cookie;
4307 s32 rc;
4308
4309 /* Must be an RX filter without RSS and not for a multicast
4310 * destination address (RFS only works for connected sockets).
4311 * These restrictions allow us to pass only a tiny amount of
4312 * data through to the completion function.
4313 */
4314 EFX_WARN_ON_PARANOID(spec->flags !=
4315 (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_RX_SCATTER));
4316 EFX_WARN_ON_PARANOID(spec->priority != EFX_FILTER_PRI_HINT);
4317 EFX_WARN_ON_PARANOID(efx_filter_is_mc_recipient(spec));
4318
4319 hash = efx_ef10_filter_hash(spec);
4320
4321 spin_lock_bh(&efx->filter_lock);
4322
4323 /* Find any existing filter with the same match tuple or else
4324 * a free slot to insert at. If an existing filter is busy,
4325 * we have to give up.
4326 */
4327 for (;;) {
4328 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
4329 saved_spec = efx_ef10_filter_entry_spec(table, i);
4330
4331 if (!saved_spec) {
4332 if (ins_index < 0)
4333 ins_index = i;
4334 } else if (efx_ef10_filter_equal(spec, saved_spec)) {
4335 if (table->entry[i].spec & EFX_EF10_FILTER_FLAG_BUSY) {
4336 rc = -EBUSY;
4337 goto fail_unlock;
4338 }
8127d661
BH		 4339 if (spec->priority < saved_spec->priority) {
4340 rc = -EPERM;
4341 goto fail_unlock;
4342 }
4343 ins_index = i;
4344 break;
4345 }
4346
4347 /* Once we reach the maximum search depth, use the
4348 * first suitable slot or return -EBUSY if there was
4349 * none
4350 */
4351 if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) {
4352 if (ins_index < 0) {
4353 rc = -EBUSY;
4354 goto fail_unlock;
4355 }
4356 break;
4357 }
4358
4359 ++depth;
4360 }
4361
4362 /* Create a software table entry if necessary, and mark it
4363 * busy. We might yet fail to insert, but any attempt to
4364 * insert a conflicting filter while we're waiting for the
4365 * firmware must find the busy entry.
4366 */
4367 saved_spec = efx_ef10_filter_entry_spec(table, ins_index);
4368 if (saved_spec) {
4369 replacing = true;
4370 } else {
4371 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC);
4372 if (!saved_spec) {
4373 rc = -ENOMEM;
4374 goto fail_unlock;
4375 }
4376 *saved_spec = *spec;
4377 }
4378 efx_ef10_filter_set_entry(table, ins_index, saved_spec,
4379 EFX_EF10_FILTER_FLAG_BUSY);
4380
4381 spin_unlock_bh(&efx->filter_lock);
4382
4383 /* Pack up the variables needed on completion */
4384 cookie = replacing << 31 | ins_index << 16 | spec->dmaq_id;
4385
4386 efx_ef10_filter_push_prep(efx, spec, inbuf,
4387 table->entry[ins_index].handle, replacing);
4388 efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
4389 MC_CMD_FILTER_OP_OUT_LEN,
4390 efx_ef10_filter_rfs_insert_complete, cookie);
4391
4392 return ins_index;
4393
4394fail_unlock:
4395 spin_unlock_bh(&efx->filter_lock);
4396 return rc;
4397}
4398
4399static void
4400efx_ef10_filter_rfs_insert_complete(struct efx_nic *efx, unsigned long cookie,
4401 int rc, efx_dword_t *outbuf,
4402 size_t outlen_actual)
4403{
4404 struct efx_ef10_filter_table *table = efx->filter_state;
4405 unsigned int ins_index, dmaq_id;
4406 struct efx_filter_spec *spec;
4407 bool replacing;
4408
4409 /* Unpack the cookie */
4410 replacing = cookie >> 31;
4411 ins_index = (cookie >> 16) & (HUNT_FILTER_TBL_ROWS - 1);
4412 dmaq_id = cookie & 0xffff;
4413
4414 spin_lock_bh(&efx->filter_lock);
4415 spec = efx_ef10_filter_entry_spec(table, ins_index);
4416 if (rc == 0) {
4417 table->entry[ins_index].handle =
4418 MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE);
4419 if (replacing)
4420 spec->dmaq_id = dmaq_id;
4421 } else if (!replacing) {
4422 kfree(spec);
4423 spec = NULL;
4424 }
4425 efx_ef10_filter_set_entry(table, ins_index, spec, 0);
4426 spin_unlock_bh(&efx->filter_lock);
4427
4428 wake_up_all(&table->waitq);
4429}
4430
4431static void
4432efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx,
4433 unsigned long filter_idx,
4434 int rc, efx_dword_t *outbuf,
4435 size_t outlen_actual);
4436
4437static bool efx_ef10_filter_rfs_expire_one(struct efx_nic *efx, u32 flow_id,
4438 unsigned int filter_idx)
4439{
4440 struct efx_ef10_filter_table *table = efx->filter_state;
4441 struct efx_filter_spec *spec =
4442 efx_ef10_filter_entry_spec(table, filter_idx);
4443 MCDI_DECLARE_BUF(inbuf,
4444 MC_CMD_FILTER_OP_IN_HANDLE_OFST +
4445 MC_CMD_FILTER_OP_IN_HANDLE_LEN);
4446
4447 if (!spec ||
4448 (table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAG_BUSY) ||
4449 spec->priority != EFX_FILTER_PRI_HINT ||
4450 !rps_may_expire_flow(efx->net_dev, spec->dmaq_id,
4451 flow_id, filter_idx))
4452 return false;
4453
4454 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
4455 MC_CMD_FILTER_OP_IN_OP_REMOVE);
4456 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
4457 table->entry[filter_idx].handle);
4458 if (efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf), 0,
4459 efx_ef10_filter_rfs_expire_complete, filter_idx))
4460 return false;
4461
4462 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
4463 return true;
4464}
4465
4466static void
4467efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx,
4468 unsigned long filter_idx,
4469 int rc, efx_dword_t *outbuf,
4470 size_t outlen_actual)
4471{
4472 struct efx_ef10_filter_table *table = efx->filter_state;
4473 struct efx_filter_spec *spec =
4474 efx_ef10_filter_entry_spec(table, filter_idx);
4475
4476 spin_lock_bh(&efx->filter_lock);
4477 if (rc == 0) {
4478 kfree(spec);
4479 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
4480 }
4481 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY;
4482 wake_up_all(&table->waitq);
4483 spin_unlock_bh(&efx->filter_lock);
4484}
4485
4486#endif /* CONFIG_RFS_ACCEL */
4487
9b410801 4488static int efx_ef10_filter_match_flags_from_mcdi(bool encap, u32 mcdi_flags)
8127d661
BH		 4489{
4490 int match_flags = 0;
4491
9b410801 4492#define MAP_FLAG(gen_flag, mcdi_field) do { \
8127d661 4493 u32 old_mcdi_flags = mcdi_flags; \
9b410801
EC		 4494 mcdi_flags &= ~(1 << MC_CMD_FILTER_OP_EXT_IN_MATCH_ ## \
4495 mcdi_field ## _LBN); \
8127d661
BH		 4496 if (mcdi_flags != old_mcdi_flags) \
4497 match_flags |= EFX_FILTER_MATCH_ ## gen_flag; \
9b410801
EC		 4498 } while (0)
4499
4500 if (encap) {
4501 /* encap filters must specify encap type */
4502 match_flags |= EFX_FILTER_MATCH_ENCAP_TYPE;
4503 /* and imply ethertype and ip proto */
4504 mcdi_flags &=
4505 ~(1 << MC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_LBN);
4506 mcdi_flags &=
4507 ~(1 << MC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_LBN);
4508 /* VLAN tags refer to the outer packet */
4509 MAP_FLAG(INNER_VID, INNER_VLAN);
4510 MAP_FLAG(OUTER_VID, OUTER_VLAN);
4511 /* everything else refers to the inner packet */
4512 MAP_FLAG(LOC_MAC_IG, IFRM_UNKNOWN_UCAST_DST);
4513 MAP_FLAG(LOC_MAC_IG, IFRM_UNKNOWN_MCAST_DST);
4514 MAP_FLAG(REM_HOST, IFRM_SRC_IP);
4515 MAP_FLAG(LOC_HOST, IFRM_DST_IP);
4516 MAP_FLAG(REM_MAC, IFRM_SRC_MAC);
4517 MAP_FLAG(REM_PORT, IFRM_SRC_PORT);
4518 MAP_FLAG(LOC_MAC, IFRM_DST_MAC);
4519 MAP_FLAG(LOC_PORT, IFRM_DST_PORT);
4520 MAP_FLAG(ETHER_TYPE, IFRM_ETHER_TYPE);
4521 MAP_FLAG(IP_PROTO, IFRM_IP_PROTO);
4522 } else {
4523 MAP_FLAG(LOC_MAC_IG, UNKNOWN_UCAST_DST);
4524 MAP_FLAG(LOC_MAC_IG, UNKNOWN_MCAST_DST);
4525 MAP_FLAG(REM_HOST, SRC_IP);
4526 MAP_FLAG(LOC_HOST, DST_IP);
4527 MAP_FLAG(REM_MAC, SRC_MAC);
4528 MAP_FLAG(REM_PORT, SRC_PORT);
4529 MAP_FLAG(LOC_MAC, DST_MAC);
4530 MAP_FLAG(LOC_PORT, DST_PORT);
4531 MAP_FLAG(ETHER_TYPE, ETHER_TYPE);
4532 MAP_FLAG(INNER_VID, INNER_VLAN);
4533 MAP_FLAG(OUTER_VID, OUTER_VLAN);
4534 MAP_FLAG(IP_PROTO, IP_PROTO);
8127d661 4535 }
8127d661
BH		 4536#undef MAP_FLAG
4537
4538 /* Did we map them all? */
4539 if (mcdi_flags)
4540 return -EINVAL;
4541
4542 return match_flags;
4543}
4544
34813fe2
AR		 4545static void efx_ef10_filter_cleanup_vlans(struct efx_nic *efx)
4546{
4547 struct efx_ef10_filter_table *table = efx->filter_state;
4548 struct efx_ef10_filter_vlan *vlan, *next_vlan;
4549
4550 /* See comment in efx_ef10_filter_table_remove() */
4551 if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
4552 return;
4553
4554 if (!table)
4555 return;
4556
4557 list_for_each_entry_safe(vlan, next_vlan, &table->vlan_list, list)
4558 efx_ef10_filter_del_vlan_internal(efx, vlan);
4559}
4560
7ac0dd9d 4561static bool efx_ef10_filter_match_supported(struct efx_ef10_filter_table *table,
9b410801 4562 bool encap,
7ac0dd9d
AR		 4563 enum efx_filter_match_flags match_flags)
4564{
4565 unsigned int match_pri;
4566 int mf;
4567
4568 for (match_pri = 0;
4569 match_pri < table->rx_match_count;
4570 match_pri++) {
9b410801 4571 mf = efx_ef10_filter_match_flags_from_mcdi(encap,
7ac0dd9d
AR		 4572 table->rx_match_mcdi_flags[match_pri]);
4573 if (mf == match_flags)
4574 return true;
4575 }
4576
4577 return false;
4578}
4579
9b410801
EC		 4580static int
4581efx_ef10_filter_table_probe_matches(struct efx_nic *efx,
4582 struct efx_ef10_filter_table *table,
4583 bool encap)
8127d661
BH		 4584{
4585 MCDI_DECLARE_BUF(inbuf, MC_CMD_GET_PARSER_DISP_INFO_IN_LEN);
4586 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX);
4587 unsigned int pd_match_pri, pd_match_count;
8127d661
BH		 4588 size_t outlen;
4589 int rc;
4590
8127d661
BH		 4591 /* Find out which RX filter types are supported, and their priorities */
4592 MCDI_SET_DWORD(inbuf, GET_PARSER_DISP_INFO_IN_OP,
9b410801
EC		 4593 encap ?
4594 MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_ENCAP_RX_MATCHES :
8127d661
BH		 4595 MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES);
4596 rc = efx_mcdi_rpc(efx, MC_CMD_GET_PARSER_DISP_INFO,
4597 inbuf, sizeof(inbuf), outbuf, sizeof(outbuf),
4598 &outlen);
4599 if (rc)
9b410801
EC		 4600 return rc;
4601
8127d661
BH		 4602 pd_match_count = MCDI_VAR_ARRAY_LEN(
4603 outlen, GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES);
8127d661
BH		 4604
4605 for (pd_match_pri = 0; pd_match_pri < pd_match_count; pd_match_pri++) {
4606 u32 mcdi_flags =
4607 MCDI_ARRAY_DWORD(
4608 outbuf,
4609 GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES,
4610 pd_match_pri);
9b410801 4611 rc = efx_ef10_filter_match_flags_from_mcdi(encap, mcdi_flags);
8127d661
BH		 4612 if (rc < 0) {
4613 netif_dbg(efx, probe, efx->net_dev,
4614 "%s: fw flags %#x pri %u not supported in driver\n",
4615 __func__, mcdi_flags, pd_match_pri);
4616 } else {
4617 netif_dbg(efx, probe, efx->net_dev,
4618 "%s: fw flags %#x pri %u supported as driver flags %#x pri %u\n",
4619 __func__, mcdi_flags, pd_match_pri,
4620 rc, table->rx_match_count);
7ac0dd9d
AR		 4621 table->rx_match_mcdi_flags[table->rx_match_count] = mcdi_flags;
4622 table->rx_match_count++;
8127d661
BH		 4623 }
4624 }
4625
9b410801
EC		 4626 return 0;
4627}
4628
4629static int efx_ef10_filter_table_probe(struct efx_nic *efx)
4630{
4631 struct efx_ef10_nic_data *nic_data = efx->nic_data;
4632 struct net_device *net_dev = efx->net_dev;
4633 struct efx_ef10_filter_table *table;
4634 struct efx_ef10_vlan *vlan;
4635 int rc;
4636
4637 if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
4638 return -EINVAL;
4639
4640 if (efx->filter_state) /* already probed */
4641 return 0;
4642
4643 table = kzalloc(sizeof(*table), GFP_KERNEL);
4644 if (!table)
4645 return -ENOMEM;
4646
4647 table->rx_match_count = 0;
4648 rc = efx_ef10_filter_table_probe_matches(efx, table, false);
4649 if (rc)
4650 goto fail;
4651 if (nic_data->datapath_caps &
4652 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN))
4653 rc = efx_ef10_filter_table_probe_matches(efx, table, true);
4654 if (rc)
4655 goto fail;
e4478ad1 4656 if ((efx_supported_features(efx) & NETIF_F_HW_VLAN_CTAG_FILTER) &&
9b410801 4657 !(efx_ef10_filter_match_supported(table, false,
e4478ad1 4658 (EFX_FILTER_MATCH_OUTER_VID | EFX_FILTER_MATCH_LOC_MAC)) &&
9b410801 4659 efx_ef10_filter_match_supported(table, false,
e4478ad1
MH		 4660 (EFX_FILTER_MATCH_OUTER_VID | EFX_FILTER_MATCH_LOC_MAC_IG)))) {
4661 netif_info(efx, probe, net_dev,
4662 "VLAN filters are not supported in this firmware variant\n");
4663 net_dev->features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
4664 efx->fixed_features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
4665 net_dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
4666 }
4667
8127d661
BH		 4668 table->entry = vzalloc(HUNT_FILTER_TBL_ROWS * sizeof(*table->entry));
4669 if (!table->entry) {
4670 rc = -ENOMEM;
4671 goto fail;
4672 }
4673
b071c3a2 4674 table->mc_promisc_last = false;
4a53ea8a
AR		 4675 table->vlan_filter =
4676 !!(efx->net_dev->features & NETIF_F_HW_VLAN_CTAG_FILTER);
34813fe2 4677 INIT_LIST_HEAD(&table->vlan_list);
12fb0da4 4678
8127d661
BH		 4679 efx->filter_state = table;
4680 init_waitqueue_head(&table->waitq);
34813fe2
AR		 4681
4682 list_for_each_entry(vlan, &nic_data->vlan_list, list) {
4683 rc = efx_ef10_filter_add_vlan(efx, vlan->vid);
4684 if (rc)
4685 goto fail_add_vlan;
4686 }
4687
8127d661
BH		 4688 return 0;
4689
34813fe2
AR		 4690fail_add_vlan:
4691 efx_ef10_filter_cleanup_vlans(efx);
4692 efx->filter_state = NULL;
8127d661
BH		 4693fail:
4694 kfree(table);
4695 return rc;
4696}
4697
0d322413
EC		 4698/* Caller must hold efx->filter_sem for read if race against
4699 * efx_ef10_filter_table_remove() is possible
4700 */
8127d661
BH		 4701static void efx_ef10_filter_table_restore(struct efx_nic *efx)
4702{
4703 struct efx_ef10_filter_table *table = efx->filter_state;
4704 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2d3d4ec0
JC		 4705 unsigned int invalid_filters = 0, failed = 0;
4706 struct efx_ef10_filter_vlan *vlan;
8127d661
BH		 4707 struct efx_filter_spec *spec;
4708 unsigned int filter_idx;
2d3d4ec0
JC		 4709 u32 mcdi_flags;
4710 int match_pri;
9b410801 4711 int rc, i;
8127d661 4712
0d322413
EC		 4713 WARN_ON(!rwsem_is_locked(&efx->filter_sem));
4714
8127d661
BH		 4715 if (!nic_data->must_restore_filters)
4716 return;
4717
0d322413
EC		 4718 if (!table)
4719 return;
4720
8127d661
BH		 4721 spin_lock_bh(&efx->filter_lock);
4722
4723 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
4724 spec = efx_ef10_filter_entry_spec(table, filter_idx);
4725 if (!spec)
4726 continue;
4727
2d3d4ec0
JC		 4728 mcdi_flags = efx_ef10_filter_mcdi_flags_from_spec(spec);
4729 match_pri = 0;
4730 while (match_pri < table->rx_match_count &&
4731 table->rx_match_mcdi_flags[match_pri] != mcdi_flags)
4732 ++match_pri;
4733 if (match_pri >= table->rx_match_count) {
4734 invalid_filters++;
4735 goto not_restored;
4736 }
4737 if (spec->rss_context != EFX_FILTER_RSS_CONTEXT_DEFAULT &&
4738 spec->rss_context != nic_data->rx_rss_context)
4739 netif_warn(efx, drv, efx->net_dev,
4740 "Warning: unable to restore a filter with specific RSS context.\n");
4741
8127d661
BH		 4742 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
4743 spin_unlock_bh(&efx->filter_lock);
4744
4745 rc = efx_ef10_filter_push(efx, spec,
4746 &table->entry[filter_idx].handle,
4747 false);
4748 if (rc)
2d3d4ec0 4749 failed++;
8127d661 4750 spin_lock_bh(&efx->filter_lock);
2d3d4ec0 4751
8127d661 4752 if (rc) {
2d3d4ec0 4753not_restored:
9b410801
EC		 4754 list_for_each_entry(vlan, &table->vlan_list, list)
4755 for (i = 0; i < EFX_EF10_NUM_DEFAULT_FILTERS; ++i)
4756 if (vlan->default_filters[i] == filter_idx)
4757 vlan->default_filters[i] =
4758 EFX_EF10_FILTER_ID_INVALID;
4759
8127d661
BH		 4760 kfree(spec);
4761 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
4762 } else {
4763 table->entry[filter_idx].spec &=
4764 ~EFX_EF10_FILTER_FLAG_BUSY;
4765 }
4766 }
4767
4768 spin_unlock_bh(&efx->filter_lock);
4769
2d3d4ec0
JC		 4770 /* This can happen validly if the MC's capabilities have changed, so
4771 * is not an error.
4772 */
4773 if (invalid_filters)
4774 netif_dbg(efx, drv, efx->net_dev,
4775 "Did not restore %u filters that are now unsupported.\n",
4776 invalid_filters);
4777
8127d661
BH		 4778 if (failed)
4779 netif_err(efx, hw, efx->net_dev,
2d3d4ec0 4780 "unable to restore %u filters\n", failed);
8127d661
BH		 4781 else
4782 nic_data->must_restore_filters = false;
4783}
4784
4785static void efx_ef10_filter_table_remove(struct efx_nic *efx)
4786{
4787 struct efx_ef10_filter_table *table = efx->filter_state;
4788 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
4789 struct efx_filter_spec *spec;
4790 unsigned int filter_idx;
4791 int rc;
4792
34813fe2 4793 efx_ef10_filter_cleanup_vlans(efx);
0d322413 4794 efx->filter_state = NULL;
dd98708c
EC		 4795 /* If we were called without locking, then it's not safe to free
4796 * the table as others might be using it. So we just WARN, leak
4797 * the memory, and potentially get an inconsistent filter table
4798 * state.
4799 * This should never actually happen.
4800 */
4801 if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
4802 return;
4803
0d322413
EC		 4804 if (!table)
4805 return;
4806
8127d661
BH		 4807 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
4808 spec = efx_ef10_filter_entry_spec(table, filter_idx);
4809 if (!spec)
4810 continue;
4811
4812 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
4813 efx_ef10_filter_is_exclusive(spec) ?
4814 MC_CMD_FILTER_OP_IN_OP_REMOVE :
4815 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
4816 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
4817 table->entry[filter_idx].handle);
e65a5109
BK		 4818 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FILTER_OP, inbuf,
4819 sizeof(inbuf), NULL, 0, NULL);
48ce5634 4820 if (rc)
e65a5109
BK		 4821 netif_info(efx, drv, efx->net_dev,
4822 "%s: filter %04x remove failed\n",
4823 __func__, filter_idx);
8127d661
BH		 4824 kfree(spec);
4825 }
4826
4827 vfree(table->entry);
4828 kfree(table);
4829}
4830
6a37958b
AR		 4831static void efx_ef10_filter_mark_one_old(struct efx_nic *efx, uint16_t *id)
4832{
4833 struct efx_ef10_filter_table *table = efx->filter_state;
4834 unsigned int filter_idx;
4835
4836 if (*id != EFX_EF10_FILTER_ID_INVALID) {
4837 filter_idx = efx_ef10_filter_get_unsafe_id(efx, *id);
4838 if (!table->entry[filter_idx].spec)
4839 netif_dbg(efx, drv, efx->net_dev,
4840 "marked null spec old %04x:%04x\n", *id,
4841 filter_idx);
4842 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_AUTO_OLD;
4843 *id = EFX_EF10_FILTER_ID_INVALID;
e65a5109 4844 }
6a37958b
AR		 4845}
4846
b3a3c03c
AR		 4847/* Mark old per-VLAN filters that may need to be removed */
4848static void _efx_ef10_filter_vlan_mark_old(struct efx_nic *efx,
4849 struct efx_ef10_filter_vlan *vlan)
8127d661
BH		 4850{
4851 struct efx_ef10_filter_table *table = efx->filter_state;
6a37958b 4852 unsigned int i;
8127d661 4853
12fb0da4 4854 for (i = 0; i < table->dev_uc_count; i++)
dc3273e0 4855 efx_ef10_filter_mark_one_old(efx, &vlan->uc[i]);
12fb0da4 4856 for (i = 0; i < table->dev_mc_count; i++)
dc3273e0 4857 efx_ef10_filter_mark_one_old(efx, &vlan->mc[i]);
9b410801
EC		 4858 for (i = 0; i < EFX_EF10_NUM_DEFAULT_FILTERS; i++)
4859 efx_ef10_filter_mark_one_old(efx, &vlan->default_filters[i]);
b3a3c03c
AR		 4860}
4861
34813fe2
AR		 4862/* Mark old filters that may need to be removed.
4863 * Caller must hold efx->filter_sem for read if race against
4864 * efx_ef10_filter_table_remove() is possible
4865 */
b3a3c03c
AR		 4866static void efx_ef10_filter_mark_old(struct efx_nic *efx)
4867{
4868 struct efx_ef10_filter_table *table = efx->filter_state;
34813fe2 4869 struct efx_ef10_filter_vlan *vlan;
b3a3c03c
AR		 4870
4871 spin_lock_bh(&efx->filter_lock);
34813fe2
AR		 4872 list_for_each_entry(vlan, &table->vlan_list, list)
4873 _efx_ef10_filter_vlan_mark_old(efx, vlan);
8127d661 4874 spin_unlock_bh(&efx->filter_lock);
822b96f8
DP		 4875}
4876
afa4ce12 4877static void efx_ef10_filter_uc_addr_list(struct efx_nic *efx)
822b96f8
DP		 4878{
4879 struct efx_ef10_filter_table *table = efx->filter_state;
4880 struct net_device *net_dev = efx->net_dev;
4881 struct netdev_hw_addr *uc;
12fb0da4 4882 int addr_count;
822b96f8 4883 unsigned int i;
8127d661 4884
12fb0da4 4885 addr_count = netdev_uc_count(net_dev);
afa4ce12 4886 table->uc_promisc = !!(net_dev->flags & IFF_PROMISC);
12fb0da4 4887 table->dev_uc_count = 1 + addr_count;
822b96f8
DP		 4888 ether_addr_copy(table->dev_uc_list[0].addr, net_dev->dev_addr);
4889 i = 1;
4890 netdev_for_each_uc_addr(uc, net_dev) {
12fb0da4 4891 if (i >= EFX_EF10_FILTER_DEV_UC_MAX) {
afa4ce12 4892 table->uc_promisc = true;
12fb0da4
EC		 4893 break;
4894 }
822b96f8
DP		 4895 ether_addr_copy(table->dev_uc_list[i].addr, uc->addr);
4896 i++;
4897 }
4898}
4899
afa4ce12 4900static void efx_ef10_filter_mc_addr_list(struct efx_nic *efx)
822b96f8
DP		 4901{
4902 struct efx_ef10_filter_table *table = efx->filter_state;
4903 struct net_device *net_dev = efx->net_dev;
4904 struct netdev_hw_addr *mc;
ab8b1f7c 4905 unsigned int i, addr_count;
822b96f8 4906
afa4ce12 4907 table->mc_promisc = !!(net_dev->flags & (IFF_PROMISC | IFF_ALLMULTI));
ab8b1f7c 4908
12fb0da4
EC		 4909 addr_count = netdev_mc_count(net_dev);
4910 i = 0;
ab8b1f7c 4911 netdev_for_each_mc_addr(mc, net_dev) {
12fb0da4 4912 if (i >= EFX_EF10_FILTER_DEV_MC_MAX) {
afa4ce12 4913 table->mc_promisc = true;
12fb0da4
EC		 4914 break;
4915 }
ab8b1f7c
DP		 4916 ether_addr_copy(table->dev_mc_list[i].addr, mc->addr);
4917 i++;
8127d661 4918 }
12fb0da4
EC		 4919
4920 table->dev_mc_count = i;
822b96f8 4921}
8127d661 4922
12fb0da4 4923static int efx_ef10_filter_insert_addr_list(struct efx_nic *efx,
b3a3c03c
AR		 4924 struct efx_ef10_filter_vlan *vlan,
4925 bool multicast, bool rollback)
822b96f8
DP		 4926{
4927 struct efx_ef10_filter_table *table = efx->filter_state;
4928 struct efx_ef10_dev_addr *addr_list;
f1c2ef40 4929 enum efx_filter_flags filter_flags;
822b96f8 4930 struct efx_filter_spec spec;
12fb0da4
EC		 4931 u8 baddr[ETH_ALEN];
4932 unsigned int i, j;
4933 int addr_count;
dc3273e0 4934 u16 *ids;
822b96f8
DP		 4935 int rc;
4936
4937 if (multicast) {
4938 addr_list = table->dev_mc_list;
12fb0da4 4939 addr_count = table->dev_mc_count;
dc3273e0 4940 ids = vlan->mc;
822b96f8
DP		 4941 } else {
4942 addr_list = table->dev_uc_list;
12fb0da4 4943 addr_count = table->dev_uc_count;
dc3273e0 4944 ids = vlan->uc;
8127d661
BH		 4945 }
4946
f1c2ef40
BK		 4947 filter_flags = efx_rss_enabled(efx) ? EFX_FILTER_FLAG_RX_RSS : 0;
4948
822b96f8 4949 /* Insert/renew filters */
12fb0da4 4950 for (i = 0; i < addr_count; i++) {
f1c2ef40 4951 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, 0);
b3a3c03c 4952 efx_filter_set_eth_local(&spec, vlan->vid, addr_list[i].addr);
b6f568e2
JC		 4953 rc = efx_ef10_filter_insert(efx, &spec, true);
4954 if (rc < 0) {
12fb0da4
EC		 4955 if (rollback) {
4956 netif_info(efx, drv, efx->net_dev,
4957 "efx_ef10_filter_insert failed rc=%d\n",
4958 rc);
4959 /* Fall back to promiscuous */
4960 for (j = 0; j < i; j++) {
12fb0da4
EC		 4961 efx_ef10_filter_remove_unsafe(
4962 efx, EFX_FILTER_PRI_AUTO,
dc3273e0
AR		 4963 ids[j]);
4964 ids[j] = EFX_EF10_FILTER_ID_INVALID;
12fb0da4
EC		 4965 }
4966 return rc;
4967 } else {
4968 /* mark as not inserted, and carry on */
4969 rc = EFX_EF10_FILTER_ID_INVALID;
822b96f8 4970 }
8127d661 4971 }
dc3273e0 4972 ids[i] = efx_ef10_filter_get_unsafe_id(efx, rc);
8127d661 4973 }
822b96f8 4974
12fb0da4
EC		 4975 if (multicast && rollback) {
4976 /* Also need an Ethernet broadcast filter */
9b410801
EC		 4977 EFX_WARN_ON_PARANOID(vlan->default_filters[EFX_EF10_BCAST] !=
4978 EFX_EF10_FILTER_ID_INVALID);
f1c2ef40 4979 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, 0);
12fb0da4 4980 eth_broadcast_addr(baddr);
b3a3c03c 4981 efx_filter_set_eth_local(&spec, vlan->vid, baddr);
8127d661 4982 rc = efx_ef10_filter_insert(efx, &spec, true);
12fb0da4 4983 if (rc < 0) {
822b96f8 4984 netif_warn(efx, drv, efx->net_dev,
12fb0da4
EC		 4985 "Broadcast filter insert failed rc=%d\n", rc);
4986 /* Fall back to promiscuous */
4987 for (j = 0; j < i; j++) {
12fb0da4
EC		 4988 efx_ef10_filter_remove_unsafe(
4989 efx, EFX_FILTER_PRI_AUTO,
dc3273e0
AR		 4990 ids[j]);
4991 ids[j] = EFX_EF10_FILTER_ID_INVALID;
12fb0da4
EC		 4992 }
4993 return rc;
4994 } else {
9b410801
EC		 4995 vlan->default_filters[EFX_EF10_BCAST] =
4996 efx_ef10_filter_get_unsafe_id(efx, rc);
12fb0da4 4997 }
8127d661 4998 }
12fb0da4
EC		 4999
5000 return 0;
5001}
5002
b3a3c03c
AR		 5003static int efx_ef10_filter_insert_def(struct efx_nic *efx,
5004 struct efx_ef10_filter_vlan *vlan,
9b410801 5005 enum efx_encap_type encap_type,
b3a3c03c 5006 bool multicast, bool rollback)
12fb0da4 5007{
12fb0da4 5008 struct efx_ef10_nic_data *nic_data = efx->nic_data;
f1c2ef40 5009 enum efx_filter_flags filter_flags;
12fb0da4
EC		 5010 struct efx_filter_spec spec;
5011 u8 baddr[ETH_ALEN];
5012 int rc;
9b410801 5013 u16 *id;
12fb0da4 5014
f1c2ef40
BK		 5015 filter_flags = efx_rss_enabled(efx) ? EFX_FILTER_FLAG_RX_RSS : 0;
5016
5017 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, 0);
12fb0da4
EC		 5018
5019 if (multicast)
5020 efx_filter_set_mc_def(&spec);
5021 else
5022 efx_filter_set_uc_def(&spec);
5023
9b410801
EC		 5024 if (encap_type) {
5025 if (nic_data->datapath_caps &
5026 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN))
5027 efx_filter_set_encap_type(&spec, encap_type);
5028 else
5029 /* don't insert encap filters on non-supporting
5030 * platforms. ID will be left as INVALID.
5031 */
5032 return 0;
5033 }
5034
b3a3c03c
AR		 5035 if (vlan->vid != EFX_FILTER_VID_UNSPEC)
5036 efx_filter_set_eth_local(&spec, vlan->vid, NULL);
5037
12fb0da4
EC		 5038 rc = efx_ef10_filter_insert(efx, &spec, true);
5039 if (rc < 0) {
9b410801
EC		 5040 const char *um = multicast ? "Multicast" : "Unicast";
5041 const char *encap_name = "";
5042 const char *encap_ipv = "";
5043
5044 if ((encap_type & EFX_ENCAP_TYPES_MASK) ==
5045 EFX_ENCAP_TYPE_VXLAN)
5046 encap_name = "VXLAN ";
5047 else if ((encap_type & EFX_ENCAP_TYPES_MASK) ==
5048 EFX_ENCAP_TYPE_NVGRE)
5049 encap_name = "NVGRE ";
5050 else if ((encap_type & EFX_ENCAP_TYPES_MASK) ==
5051 EFX_ENCAP_TYPE_GENEVE)
5052 encap_name = "GENEVE ";
5053 if (encap_type & EFX_ENCAP_FLAG_IPV6)
5054 encap_ipv = "IPv6 ";
5055 else if (encap_type)
5056 encap_ipv = "IPv4 ";
5057
5058 /* unprivileged functions can't insert mismatch filters
5059 * for encapsulated or unicast traffic, so downgrade
5060 * those warnings to debug.
5061 */
34e7aefb 5062 netif_cond_dbg(efx, drv, efx->net_dev,
9b410801
EC		 5063 rc == -EPERM && (encap_type || !multicast), warn,
5064 "%s%s%s mismatch filter insert failed rc=%d\n",
5065 encap_name, encap_ipv, um, rc);
12fb0da4 5066 } else if (multicast) {
9b410801
EC		 5067 /* mapping from encap types to default filter IDs (multicast) */
5068 static enum efx_ef10_default_filters map[] = {
5069 [EFX_ENCAP_TYPE_NONE] = EFX_EF10_MCDEF,
5070 [EFX_ENCAP_TYPE_VXLAN] = EFX_EF10_VXLAN4_MCDEF,
5071 [EFX_ENCAP_TYPE_NVGRE] = EFX_EF10_NVGRE4_MCDEF,
5072 [EFX_ENCAP_TYPE_GENEVE] = EFX_EF10_GENEVE4_MCDEF,
5073 [EFX_ENCAP_TYPE_VXLAN | EFX_ENCAP_FLAG_IPV6] =
5074 EFX_EF10_VXLAN6_MCDEF,
5075 [EFX_ENCAP_TYPE_NVGRE | EFX_ENCAP_FLAG_IPV6] =
5076 EFX_EF10_NVGRE6_MCDEF,
5077 [EFX_ENCAP_TYPE_GENEVE | EFX_ENCAP_FLAG_IPV6] =
5078 EFX_EF10_GENEVE6_MCDEF,
5079 };
5080
5081 /* quick bounds check (BCAST result impossible) */
5082 BUILD_BUG_ON(EFX_EF10_BCAST != 0);
e9904990 5083 if (encap_type >= ARRAY_SIZE(map) || map[encap_type] == 0) {
9b410801
EC		 5084 WARN_ON(1);
5085 return -EINVAL;
5086 }
5087 /* then follow map */
5088 id = &vlan->default_filters[map[encap_type]];
5089
5090 EFX_WARN_ON_PARANOID(*id != EFX_EF10_FILTER_ID_INVALID);
5091 *id = efx_ef10_filter_get_unsafe_id(efx, rc);
5092 if (!nic_data->workaround_26807 && !encap_type) {
12fb0da4
EC		 5093 /* Also need an Ethernet broadcast filter */
5094 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
f1c2ef40 5095 filter_flags, 0);
12fb0da4 5096 eth_broadcast_addr(baddr);
b3a3c03c 5097 efx_filter_set_eth_local(&spec, vlan->vid, baddr);
12fb0da4
EC		 5098 rc = efx_ef10_filter_insert(efx, &spec, true);
5099 if (rc < 0) {
5100 netif_warn(efx, drv, efx->net_dev,
5101 "Broadcast filter insert failed rc=%d\n",
5102 rc);
5103 if (rollback) {
5104 /* Roll back the mc_def filter */
5105 efx_ef10_filter_remove_unsafe(
5106 efx, EFX_FILTER_PRI_AUTO,
9b410801
EC		 5107 *id);
5108 *id = EFX_EF10_FILTER_ID_INVALID;
12fb0da4
EC		 5109 return rc;
5110 }
5111 } else {
9b410801
EC		 5112 EFX_WARN_ON_PARANOID(
5113 vlan->default_filters[EFX_EF10_BCAST] !=
5114 EFX_EF10_FILTER_ID_INVALID);
5115 vlan->default_filters[EFX_EF10_BCAST] =
5116 efx_ef10_filter_get_unsafe_id(efx, rc);
12fb0da4
EC		 5117 }
5118 }
5119 rc = 0;
5120 } else {
9b410801
EC		 5121 /* mapping from encap types to default filter IDs (unicast) */
5122 static enum efx_ef10_default_filters map[] = {
5123 [EFX_ENCAP_TYPE_NONE] = EFX_EF10_UCDEF,
5124 [EFX_ENCAP_TYPE_VXLAN] = EFX_EF10_VXLAN4_UCDEF,
5125 [EFX_ENCAP_TYPE_NVGRE] = EFX_EF10_NVGRE4_UCDEF,
5126 [EFX_ENCAP_TYPE_GENEVE] = EFX_EF10_GENEVE4_UCDEF,
5127 [EFX_ENCAP_TYPE_VXLAN | EFX_ENCAP_FLAG_IPV6] =
5128 EFX_EF10_VXLAN6_UCDEF,
5129 [EFX_ENCAP_TYPE_NVGRE | EFX_ENCAP_FLAG_IPV6] =
5130 EFX_EF10_NVGRE6_UCDEF,
5131 [EFX_ENCAP_TYPE_GENEVE | EFX_ENCAP_FLAG_IPV6] =
5132 EFX_EF10_GENEVE6_UCDEF,
5133 };
5134
5135 /* quick bounds check (BCAST result impossible) */
5136 BUILD_BUG_ON(EFX_EF10_BCAST != 0);
ee467fba 5137 if (encap_type >= ARRAY_SIZE(map) || map[encap_type] == 0) {
9b410801
EC		 5138 WARN_ON(1);
5139 return -EINVAL;
5140 }
5141 /* then follow map */
5142 id = &vlan->default_filters[map[encap_type]];
5143 EFX_WARN_ON_PARANOID(*id != EFX_EF10_FILTER_ID_INVALID);
5144 *id = rc;
12fb0da4
EC		 5145 rc = 0;
5146 }
5147 return rc;
822b96f8
DP		 5148}
5149
5150/* Remove filters that weren't renewed. Since nothing else changes the AUTO_OLD
5151 * flag or removes these filters, we don't need to hold the filter_lock while
5152 * scanning for these filters.
5153 */
5154static void efx_ef10_filter_remove_old(struct efx_nic *efx)
5155{
5156 struct efx_ef10_filter_table *table = efx->filter_state;
e65a5109
BK		 5157 int remove_failed = 0;
5158 int remove_noent = 0;
5159 int rc;
822b96f8 5160 int i;
8127d661 5161
8127d661
BH		 5162 for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) {
5163 if (ACCESS_ONCE(table->entry[i].spec) &
b59e6ef8 5164 EFX_EF10_FILTER_FLAG_AUTO_OLD) {
e65a5109
BK		 5165 rc = efx_ef10_filter_remove_internal(efx,
5166 1U << EFX_FILTER_PRI_AUTO, i, true);
5167 if (rc == -ENOENT)
5168 remove_noent++;
5169 else if (rc)
5170 remove_failed++;
8127d661
BH		 5171 }
5172 }
e65a5109
BK		 5173
5174 if (remove_failed)
5175 netif_info(efx, drv, efx->net_dev,
5176 "%s: failed to remove %d filters\n",
5177 __func__, remove_failed);
5178 if (remove_noent)
5179 netif_info(efx, drv, efx->net_dev,
5180 "%s: failed to remove %d non-existent filters\n",
5181 __func__, remove_noent);
8127d661
BH		 5182}
5183
7a186f47
DP		 5184static int efx_ef10_vport_set_mac_address(struct efx_nic *efx)
5185{
5186 struct efx_ef10_nic_data *nic_data = efx->nic_data;
5187 u8 mac_old[ETH_ALEN];
5188 int rc, rc2;
5189
5190 /* Only reconfigure a PF-created vport */
5191 if (is_zero_ether_addr(nic_data->vport_mac))
5192 return 0;
5193
5194 efx_device_detach_sync(efx);
5195 efx_net_stop(efx->net_dev);
5196 down_write(&efx->filter_sem);
5197 efx_ef10_filter_table_remove(efx);
5198 up_write(&efx->filter_sem);
5199
5200 rc = efx_ef10_vadaptor_free(efx, nic_data->vport_id);
5201 if (rc)
5202 goto restore_filters;
5203
5204 ether_addr_copy(mac_old, nic_data->vport_mac);
5205 rc = efx_ef10_vport_del_mac(efx, nic_data->vport_id,
5206 nic_data->vport_mac);
5207 if (rc)
5208 goto restore_vadaptor;
5209
5210 rc = efx_ef10_vport_add_mac(efx, nic_data->vport_id,
5211 efx->net_dev->dev_addr);
5212 if (!rc) {
5213 ether_addr_copy(nic_data->vport_mac, efx->net_dev->dev_addr);
5214 } else {
5215 rc2 = efx_ef10_vport_add_mac(efx, nic_data->vport_id, mac_old);
5216 if (rc2) {
5217 /* Failed to add original MAC, so clear vport_mac */
5218 eth_zero_addr(nic_data->vport_mac);
5219 goto reset_nic;
5220 }
5221 }
5222
5223restore_vadaptor:
5224 rc2 = efx_ef10_vadaptor_alloc(efx, nic_data->vport_id);
5225 if (rc2)
5226 goto reset_nic;
5227restore_filters:
5228 down_write(&efx->filter_sem);
5229 rc2 = efx_ef10_filter_table_probe(efx);
5230 up_write(&efx->filter_sem);
5231 if (rc2)
5232 goto reset_nic;
5233
5234 rc2 = efx_net_open(efx->net_dev);
5235 if (rc2)
5236 goto reset_nic;
5237
5238 netif_device_attach(efx->net_dev);
5239
5240 return rc;
5241
5242reset_nic:
5243 netif_err(efx, drv, efx->net_dev,
5244 "Failed to restore when changing MAC address - scheduling reset\n");
5245 efx_schedule_reset(efx, RESET_TYPE_DATAPATH);
5246
5247 return rc ? rc : rc2;
5248}
5249
822b96f8
DP		 5250/* Caller must hold efx->filter_sem for read if race against
5251 * efx_ef10_filter_table_remove() is possible
5252 */
34813fe2
AR		 5253static void efx_ef10_filter_vlan_sync_rx_mode(struct efx_nic *efx,
5254 struct efx_ef10_filter_vlan *vlan)
822b96f8
DP		 5255{
5256 struct efx_ef10_filter_table *table = efx->filter_state;
ab8b1f7c 5257 struct efx_ef10_nic_data *nic_data = efx->nic_data;
b3a3c03c 5258
4a53ea8a
AR		 5259 /* Do not install unspecified VID if VLAN filtering is enabled.
5260 * Do not install all specified VIDs if VLAN filtering is disabled.
5261 */
5262 if ((vlan->vid == EFX_FILTER_VID_UNSPEC) == table->vlan_filter)
5263 return;
5264
12fb0da4 5265 /* Insert/renew unicast filters */
afa4ce12 5266 if (table->uc_promisc) {
9b410801
EC		 5267 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_NONE,
5268 false, false);
b3a3c03c 5269 efx_ef10_filter_insert_addr_list(efx, vlan, false, false);
12fb0da4
EC		 5270 } else {
5271 /* If any of the filters failed to insert, fall back to
5272 * promiscuous mode - add in the uc_def filter. But keep
5273 * our individual unicast filters.
5274 */
b3a3c03c 5275 if (efx_ef10_filter_insert_addr_list(efx, vlan, false, false))
9b410801
EC		 5276 efx_ef10_filter_insert_def(efx, vlan,
5277 EFX_ENCAP_TYPE_NONE,
5278 false, false);
12fb0da4 5279 }
9b410801
EC		 5280 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_VXLAN,
5281 false, false);
5282 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_VXLAN |
5283 EFX_ENCAP_FLAG_IPV6,
5284 false, false);
5285 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_NVGRE,
5286 false, false);
5287 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_NVGRE |
5288 EFX_ENCAP_FLAG_IPV6,
5289 false, false);
5290 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_GENEVE,
5291 false, false);
5292 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_GENEVE |
5293 EFX_ENCAP_FLAG_IPV6,
5294 false, false);
ab8b1f7c 5295
12fb0da4 5296 /* Insert/renew multicast filters */
ab8b1f7c
DP		 5297 /* If changing promiscuous state with cascaded multicast filters, remove
5298 * old filters first, so that packets are dropped rather than duplicated
5299 */
afa4ce12
AR		 5300 if (nic_data->workaround_26807 &&
5301 table->mc_promisc_last != table->mc_promisc)
ab8b1f7c 5302 efx_ef10_filter_remove_old(efx);
afa4ce12 5303 if (table->mc_promisc) {
12fb0da4
EC		 5304 if (nic_data->workaround_26807) {
5305 /* If we failed to insert promiscuous filters, rollback
5306 * and fall back to individual multicast filters
5307 */
9b410801
EC		 5308 if (efx_ef10_filter_insert_def(efx, vlan,
5309 EFX_ENCAP_TYPE_NONE,
5310 true, true)) {
12fb0da4
EC		 5311 /* Changing promisc state, so remove old filters */
5312 efx_ef10_filter_remove_old(efx);
b3a3c03c
AR		 5313 efx_ef10_filter_insert_addr_list(efx, vlan,
5314 true, false);
12fb0da4
EC		 5315 }
5316 } else {
5317 /* If we failed to insert promiscuous filters, don't
5318 * rollback. Regardless, also insert the mc_list
5319 */
9b410801
EC		 5320 efx_ef10_filter_insert_def(efx, vlan,
5321 EFX_ENCAP_TYPE_NONE,
5322 true, false);
b3a3c03c 5323 efx_ef10_filter_insert_addr_list(efx, vlan, true, false);
12fb0da4
EC		 5324 }
5325 } else {
5326 /* If any filters failed to insert, rollback and fall back to
5327 * promiscuous mode - mc_def filter and maybe broadcast. If
5328 * that fails, roll back again and insert as many of our
5329 * individual multicast filters as we can.
5330 */
b3a3c03c 5331 if (efx_ef10_filter_insert_addr_list(efx, vlan, true, true)) {
12fb0da4
EC		 5332 /* Changing promisc state, so remove old filters */
5333 if (nic_data->workaround_26807)
5334 efx_ef10_filter_remove_old(efx);
9b410801
EC		 5335 if (efx_ef10_filter_insert_def(efx, vlan,
5336 EFX_ENCAP_TYPE_NONE,
5337 true, true))
b3a3c03c
AR		 5338 efx_ef10_filter_insert_addr_list(efx, vlan,
5339 true, false);
12fb0da4
EC		 5340 }
5341 }
9b410801
EC		 5342 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_VXLAN,
5343 true, false);
5344 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_VXLAN |
5345 EFX_ENCAP_FLAG_IPV6,
5346 true, false);
5347 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_NVGRE,
5348 true, false);
5349 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_NVGRE |
5350 EFX_ENCAP_FLAG_IPV6,
5351 true, false);
5352 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_GENEVE,
5353 true, false);
5354 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_GENEVE |
5355 EFX_ENCAP_FLAG_IPV6,
5356 true, false);
34813fe2
AR		 5357}
5358
5359/* Caller must hold efx->filter_sem for read if race against
5360 * efx_ef10_filter_table_remove() is possible
5361 */
5362static void efx_ef10_filter_sync_rx_mode(struct efx_nic *efx)
5363{
5364 struct efx_ef10_filter_table *table = efx->filter_state;
5365 struct net_device *net_dev = efx->net_dev;
5366 struct efx_ef10_filter_vlan *vlan;
4a53ea8a 5367 bool vlan_filter;
34813fe2
AR		 5368
5369 if (!efx_dev_registered(efx))
5370 return;
5371
5372 if (!table)
5373 return;
5374
5375 efx_ef10_filter_mark_old(efx);
5376
5377 /* Copy/convert the address lists; add the primary station
5378 * address and broadcast address
5379 */
5380 netif_addr_lock_bh(net_dev);
5381 efx_ef10_filter_uc_addr_list(efx);
5382 efx_ef10_filter_mc_addr_list(efx);
5383 netif_addr_unlock_bh(net_dev);
5384
4a53ea8a
AR		 5385 /* If VLAN filtering changes, all old filters are finally removed.
5386 * Do it in advance to avoid conflicts for unicast untagged and
5387 * VLAN 0 tagged filters.
5388 */
5389 vlan_filter = !!(net_dev->features & NETIF_F_HW_VLAN_CTAG_FILTER);
5390 if (table->vlan_filter != vlan_filter) {
5391 table->vlan_filter = vlan_filter;
5392 efx_ef10_filter_remove_old(efx);
5393 }
5394
34813fe2
AR		 5395 list_for_each_entry(vlan, &table->vlan_list, list)
5396 efx_ef10_filter_vlan_sync_rx_mode(efx, vlan);
822b96f8
DP		 5397
5398 efx_ef10_filter_remove_old(efx);
afa4ce12 5399 table->mc_promisc_last = table->mc_promisc;
822b96f8
DP		 5400}
5401
34813fe2
AR		 5402static struct efx_ef10_filter_vlan *efx_ef10_filter_find_vlan(struct efx_nic *efx, u16 vid)
5403{
5404 struct efx_ef10_filter_table *table = efx->filter_state;
5405 struct efx_ef10_filter_vlan *vlan;
5406
5407 WARN_ON(!rwsem_is_locked(&efx->filter_sem));
5408
5409 list_for_each_entry(vlan, &table->vlan_list, list) {
5410 if (vlan->vid == vid)
5411 return vlan;
5412 }
5413
5414 return NULL;
5415}
5416
5417static int efx_ef10_filter_add_vlan(struct efx_nic *efx, u16 vid)
5418{
5419 struct efx_ef10_filter_table *table = efx->filter_state;
5420 struct efx_ef10_filter_vlan *vlan;
5421 unsigned int i;
5422
5423 if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
5424 return -EINVAL;
5425
5426 vlan = efx_ef10_filter_find_vlan(efx, vid);
5427 if (WARN_ON(vlan)) {
5428 netif_err(efx, drv, efx->net_dev,
5429 "VLAN %u already added\n", vid);
5430 return -EALREADY;
5431 }
5432
5433 vlan = kzalloc(sizeof(*vlan), GFP_KERNEL);
5434 if (!vlan)
5435 return -ENOMEM;
5436
5437 vlan->vid = vid;
5438
5439 for (i = 0; i < ARRAY_SIZE(vlan->uc); i++)
5440 vlan->uc[i] = EFX_EF10_FILTER_ID_INVALID;
5441 for (i = 0; i < ARRAY_SIZE(vlan->mc); i++)
5442 vlan->mc[i] = EFX_EF10_FILTER_ID_INVALID;
9b410801
EC		 5443 for (i = 0; i < EFX_EF10_NUM_DEFAULT_FILTERS; i++)
5444 vlan->default_filters[i] = EFX_EF10_FILTER_ID_INVALID;
34813fe2
AR		 5445
5446 list_add_tail(&vlan->list, &table->vlan_list);
5447
5448 if (efx_dev_registered(efx))
5449 efx_ef10_filter_vlan_sync_rx_mode(efx, vlan);
5450
5451 return 0;
5452}
5453
5454static void efx_ef10_filter_del_vlan_internal(struct efx_nic *efx,
5455 struct efx_ef10_filter_vlan *vlan)
5456{
5457 unsigned int i;
5458
5459 /* See comment in efx_ef10_filter_table_remove() */
5460 if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
5461 return;
5462
5463 list_del(&vlan->list);
5464
8c915620 5465 for (i = 0; i < ARRAY_SIZE(vlan->uc); i++)
34813fe2 5466 efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO,
8c915620
EC		 5467 vlan->uc[i]);
5468 for (i = 0; i < ARRAY_SIZE(vlan->mc); i++)
34813fe2 5469 efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO,
8c915620 5470 vlan->mc[i]);
9b410801
EC		 5471 for (i = 0; i < EFX_EF10_NUM_DEFAULT_FILTERS; i++)
5472 if (vlan->default_filters[i] != EFX_EF10_FILTER_ID_INVALID)
5473 efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO,
5474 vlan->default_filters[i]);
34813fe2
AR		 5475
5476 kfree(vlan);
5477}
5478
5479static void efx_ef10_filter_del_vlan(struct efx_nic *efx, u16 vid)
5480{
5481 struct efx_ef10_filter_vlan *vlan;
5482
5483 /* See comment in efx_ef10_filter_table_remove() */
5484 if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
5485 return;
5486
5487 vlan = efx_ef10_filter_find_vlan(efx, vid);
5488 if (!vlan) {
5489 netif_err(efx, drv, efx->net_dev,
5490 "VLAN %u not found in filter state\n", vid);
5491 return;
5492 }
5493
5494 efx_ef10_filter_del_vlan_internal(efx, vlan);
5495}
5496
910c8789
SS		 5497static int efx_ef10_set_mac_address(struct efx_nic *efx)
5498{
5499 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_SET_MAC_IN_LEN);
5500 struct efx_ef10_nic_data *nic_data = efx->nic_data;
5501 bool was_enabled = efx->port_enabled;
5502 int rc;
5503
5504 efx_device_detach_sync(efx);
5505 efx_net_stop(efx->net_dev);
d248953a
MH		 5506
5507 mutex_lock(&efx->mac_lock);
910c8789
SS		 5508 down_write(&efx->filter_sem);
5509 efx_ef10_filter_table_remove(efx);
5510
5511 ether_addr_copy(MCDI_PTR(inbuf, VADAPTOR_SET_MAC_IN_MACADDR),
5512 efx->net_dev->dev_addr);
5513 MCDI_SET_DWORD(inbuf, VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID,
5514 nic_data->vport_id);
535a6177
DP		 5515 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_VADAPTOR_SET_MAC, inbuf,
5516 sizeof(inbuf), NULL, 0, NULL);
910c8789
SS		 5517
5518 efx_ef10_filter_table_probe(efx);
5519 up_write(&efx->filter_sem);
d248953a
MH		 5520 mutex_unlock(&efx->mac_lock);
5521
910c8789
SS		 5522 if (was_enabled)
5523 efx_net_open(efx->net_dev);
5524 netif_device_attach(efx->net_dev);
5525
9e9f665a
DP		 5526#ifdef CONFIG_SFC_SRIOV
5527 if (efx->pci_dev->is_virtfn && efx->pci_dev->physfn) {
910c8789
SS		 5528 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn;
5529
9e9f665a
DP		 5530 if (rc == -EPERM) {
5531 struct efx_nic *efx_pf;
910c8789 5532
9e9f665a
DP		 5533 /* Switch to PF and change MAC address on vport */
5534 efx_pf = pci_get_drvdata(pci_dev_pf);
910c8789 5535
9e9f665a
DP		 5536 rc = efx_ef10_sriov_set_vf_mac(efx_pf,
5537 nic_data->vf_index,
5538 efx->net_dev->dev_addr);
5539 } else if (!rc) {
910c8789
SS		 5540 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
5541 struct efx_ef10_nic_data *nic_data = efx_pf->nic_data;
5542 unsigned int i;
5543
9e9f665a
DP		 5544 /* MAC address successfully changed by VF (with MAC
5545 * spoofing) so update the parent PF if possible.
5546 */
910c8789
SS		 5547 for (i = 0; i < efx_pf->vf_count; ++i) {
5548 struct ef10_vf *vf = nic_data->vf + i;
5549
5550 if (vf->efx == efx) {
5551 ether_addr_copy(vf->mac,
5552 efx->net_dev->dev_addr);
5553 return 0;
5554 }
5555 }
5556 }
9e9f665a 5557 } else
910c8789 5558#endif
9e9f665a
DP		 5559 if (rc == -EPERM) {
5560 netif_err(efx, drv, efx->net_dev,
5561 "Cannot change MAC address; use sfboot to enable"
5562 " mac-spoofing on this interface\n");
7a186f47
DP		 5563 } else if (rc == -ENOSYS && !efx_ef10_is_vf(efx)) {
5564 /* If the active MCFW does not support MC_CMD_VADAPTOR_SET_MAC
5565 * fall-back to the method of changing the MAC address on the
5566 * vport. This only applies to PFs because such versions of
5567 * MCFW do not support VFs.
5568 */
5569 rc = efx_ef10_vport_set_mac_address(efx);
535a6177
DP		 5570 } else {
5571 efx_mcdi_display_error(efx, MC_CMD_VADAPTOR_SET_MAC,
5572 sizeof(inbuf), NULL, 0, rc);
9e9f665a
DP		 5573 }
5574
910c8789
SS		 5575 return rc;
5576}
5577
8127d661
BH		 5578static int efx_ef10_mac_reconfigure(struct efx_nic *efx)
5579{
5580 efx_ef10_filter_sync_rx_mode(efx);
5581
5582 return efx_mcdi_set_mac(efx);
5583}
5584
862f894c
SS		 5585static int efx_ef10_mac_reconfigure_vf(struct efx_nic *efx)
5586{
5587 efx_ef10_filter_sync_rx_mode(efx);
5588
5589 return 0;
5590}
5591
74cd60a4
JC		 5592static int efx_ef10_start_bist(struct efx_nic *efx, u32 bist_type)
5593{
5594 MCDI_DECLARE_BUF(inbuf, MC_CMD_START_BIST_IN_LEN);
5595
5596 MCDI_SET_DWORD(inbuf, START_BIST_IN_TYPE, bist_type);
5597 return efx_mcdi_rpc(efx, MC_CMD_START_BIST, inbuf, sizeof(inbuf),
5598 NULL, 0, NULL);
5599}
5600
5601/* MC BISTs follow a different poll mechanism to phy BISTs.
5602 * The BIST is done in the poll handler on the MC, and the MCDI command
5603 * will block until the BIST is done.
5604 */
5605static int efx_ef10_poll_bist(struct efx_nic *efx)
5606{
5607 int rc;
5608 MCDI_DECLARE_BUF(outbuf, MC_CMD_POLL_BIST_OUT_LEN);
5609 size_t outlen;
5610 u32 result;
5611
5612 rc = efx_mcdi_rpc(efx, MC_CMD_POLL_BIST, NULL, 0,
5613 outbuf, sizeof(outbuf), &outlen);
5614 if (rc != 0)
5615 return rc;
5616
5617 if (outlen < MC_CMD_POLL_BIST_OUT_LEN)
5618 return -EIO;
5619
5620 result = MCDI_DWORD(outbuf, POLL_BIST_OUT_RESULT);
5621 switch (result) {
5622 case MC_CMD_POLL_BIST_PASSED:
5623 netif_dbg(efx, hw, efx->net_dev, "BIST passed.\n");
5624 return 0;
5625 case MC_CMD_POLL_BIST_TIMEOUT:
5626 netif_err(efx, hw, efx->net_dev, "BIST timed out\n");
5627 return -EIO;
5628 case MC_CMD_POLL_BIST_FAILED:
5629 netif_err(efx, hw, efx->net_dev, "BIST failed.\n");
5630 return -EIO;
5631 default:
5632 netif_err(efx, hw, efx->net_dev,
5633 "BIST returned unknown result %u", result);
5634 return -EIO;
5635 }
5636}
5637
5638static int efx_ef10_run_bist(struct efx_nic *efx, u32 bist_type)
5639{
5640 int rc;
5641
5642 netif_dbg(efx, drv, efx->net_dev, "starting BIST type %u\n", bist_type);
5643
5644 rc = efx_ef10_start_bist(efx, bist_type);
5645 if (rc != 0)
5646 return rc;
5647
5648 return efx_ef10_poll_bist(efx);
5649}
5650
5651static int
5652efx_ef10_test_chip(struct efx_nic *efx, struct efx_self_tests *tests)
5653{
5654 int rc, rc2;
5655
5656 efx_reset_down(efx, RESET_TYPE_WORLD);
5657
5658 rc = efx_mcdi_rpc(efx, MC_CMD_ENABLE_OFFLINE_BIST,
5659 NULL, 0, NULL, 0, NULL);
5660 if (rc != 0)
5661 goto out;
5662
5663 tests->memory = efx_ef10_run_bist(efx, MC_CMD_MC_MEM_BIST) ? -1 : 1;
5664 tests->registers = efx_ef10_run_bist(efx, MC_CMD_REG_BIST) ? -1 : 1;
5665
5666 rc = efx_mcdi_reset(efx, RESET_TYPE_WORLD);
5667
5668out:
27324820
DP		 5669 if (rc == -EPERM)
5670 rc = 0;
74cd60a4
JC		 5671 rc2 = efx_reset_up(efx, RESET_TYPE_WORLD, rc == 0);
5672 return rc ? rc : rc2;
5673}
5674
8127d661
BH		 5675#ifdef CONFIG_SFC_MTD
5676
5677struct efx_ef10_nvram_type_info {
5678 u16 type, type_mask;
5679 u8 port;
5680 const char *name;
5681};
5682
5683static const struct efx_ef10_nvram_type_info efx_ef10_nvram_types[] = {
5684 { NVRAM_PARTITION_TYPE_MC_FIRMWARE, 0, 0, "sfc_mcfw" },
5685 { NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 0, 0, "sfc_mcfw_backup" },
5686 { NVRAM_PARTITION_TYPE_EXPANSION_ROM, 0, 0, "sfc_exp_rom" },
5687 { NVRAM_PARTITION_TYPE_STATIC_CONFIG, 0, 0, "sfc_static_cfg" },
5688 { NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG, 0, 0, "sfc_dynamic_cfg" },
5689 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0, 0, 0, "sfc_exp_rom_cfg" },
5690 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1, 0, 1, "sfc_exp_rom_cfg" },
5691 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2, 0, 2, "sfc_exp_rom_cfg" },
5692 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3, 0, 3, "sfc_exp_rom_cfg" },
a84f3bf9 5693 { NVRAM_PARTITION_TYPE_LICENSE, 0, 0, "sfc_license" },
8127d661
BH		 5694 { NVRAM_PARTITION_TYPE_PHY_MIN, 0xff, 0, "sfc_phy_fw" },
5695};
5696
5697static int efx_ef10_mtd_probe_partition(struct efx_nic *efx,
5698 struct efx_mcdi_mtd_partition *part,
5699 unsigned int type)
5700{
5701 MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_METADATA_IN_LEN);
5702 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_METADATA_OUT_LENMAX);
5703 const struct efx_ef10_nvram_type_info *info;
5704 size_t size, erase_size, outlen;
5705 bool protected;
5706 int rc;
5707
5708 for (info = efx_ef10_nvram_types; ; info++) {
5709 if (info ==
5710 efx_ef10_nvram_types + ARRAY_SIZE(efx_ef10_nvram_types))
5711 return -ENODEV;
5712 if ((type & ~info->type_mask) == info->type)
5713 break;
5714 }
5715 if (info->port != efx_port_num(efx))
5716 return -ENODEV;
5717
5718 rc = efx_mcdi_nvram_info(efx, type, &size, &erase_size, &protected);
5719 if (rc)
5720 return rc;
5721 if (protected)
5722 return -ENODEV; /* hide it */
5723
5724 part->nvram_type = type;
5725
5726 MCDI_SET_DWORD(inbuf, NVRAM_METADATA_IN_TYPE, type);
5727 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_METADATA, inbuf, sizeof(inbuf),
5728 outbuf, sizeof(outbuf), &outlen);
5729 if (rc)
5730 return rc;
5731 if (outlen < MC_CMD_NVRAM_METADATA_OUT_LENMIN)
5732 return -EIO;
5733 if (MCDI_DWORD(outbuf, NVRAM_METADATA_OUT_FLAGS) &
5734 (1 << MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN))
5735 part->fw_subtype = MCDI_DWORD(outbuf,
5736 NVRAM_METADATA_OUT_SUBTYPE);
5737
5738 part->common.dev_type_name = "EF10 NVRAM manager";
5739 part->common.type_name = info->name;
5740
5741 part->common.mtd.type = MTD_NORFLASH;
5742 part->common.mtd.flags = MTD_CAP_NORFLASH;
5743 part->common.mtd.size = size;
5744 part->common.mtd.erasesize = erase_size;
5745
5746 return 0;
5747}
5748
5749static int efx_ef10_mtd_probe(struct efx_nic *efx)
5750{
5751 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX);
5752 struct efx_mcdi_mtd_partition *parts;
5753 size_t outlen, n_parts_total, i, n_parts;
5754 unsigned int type;
5755 int rc;
5756
5757 ASSERT_RTNL();
5758
5759 BUILD_BUG_ON(MC_CMD_NVRAM_PARTITIONS_IN_LEN != 0);
5760 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_PARTITIONS, NULL, 0,
5761 outbuf, sizeof(outbuf), &outlen);
5762 if (rc)
5763 return rc;
5764 if (outlen < MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN)
5765 return -EIO;
5766
5767 n_parts_total = MCDI_DWORD(outbuf, NVRAM_PARTITIONS_OUT_NUM_PARTITIONS);
5768 if (n_parts_total >
5769 MCDI_VAR_ARRAY_LEN(outlen, NVRAM_PARTITIONS_OUT_TYPE_ID))
5770 return -EIO;
5771
5772 parts = kcalloc(n_parts_total, sizeof(*parts), GFP_KERNEL);
5773 if (!parts)
5774 return -ENOMEM;
5775
5776 n_parts = 0;
5777 for (i = 0; i < n_parts_total; i++) {
5778 type = MCDI_ARRAY_DWORD(outbuf, NVRAM_PARTITIONS_OUT_TYPE_ID,
5779 i);
5780 rc = efx_ef10_mtd_probe_partition(efx, &parts[n_parts], type);
5781 if (rc == 0)
5782 n_parts++;
5783 else if (rc != -ENODEV)
5784 goto fail;
5785 }
5786
5787 rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts));
5788fail:
5789 if (rc)
5790 kfree(parts);
5791 return rc;
5792}
5793
5794#endif /* CONFIG_SFC_MTD */
5795
5796static void efx_ef10_ptp_write_host_time(struct efx_nic *efx, u32 host_time)
5797{
5798 _efx_writed(efx, cpu_to_le32(host_time), ER_DZ_MC_DB_LWRD);
5799}
5800
02246a7f
SS		 5801static void efx_ef10_ptp_write_host_time_vf(struct efx_nic *efx,
5802 u32 host_time) {}
5803
bd9a265d
JC		 5804static int efx_ef10_rx_enable_timestamping(struct efx_channel *channel,
5805 bool temp)
5806{
5807 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN);
5808 int rc;
5809
5810 if (channel->sync_events_state == SYNC_EVENTS_REQUESTED ||
5811 channel->sync_events_state == SYNC_EVENTS_VALID ||
5812 (temp && channel->sync_events_state == SYNC_EVENTS_DISABLED))
5813 return 0;
5814 channel->sync_events_state = SYNC_EVENTS_REQUESTED;
5815
5816 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE);
5817 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
5818 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE,
5819 channel->channel);
5820
5821 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
5822 inbuf, sizeof(inbuf), NULL, 0, NULL);
5823
5824 if (rc != 0)
5825 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
5826 SYNC_EVENTS_DISABLED;
5827
5828 return rc;
5829}
5830
5831static int efx_ef10_rx_disable_timestamping(struct efx_channel *channel,
5832 bool temp)
5833{
5834 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN);
5835 int rc;
5836
5837 if (channel->sync_events_state == SYNC_EVENTS_DISABLED ||
5838 (temp && channel->sync_events_state == SYNC_EVENTS_QUIESCENT))
5839 return 0;
5840 if (channel->sync_events_state == SYNC_EVENTS_QUIESCENT) {
5841 channel->sync_events_state = SYNC_EVENTS_DISABLED;
5842 return 0;
5843 }
5844 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
5845 SYNC_EVENTS_DISABLED;
5846
5847 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE);
5848 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
5849 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL,
5850 MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE);
5851 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE,
5852 channel->channel);
5853
5854 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
5855 inbuf, sizeof(inbuf), NULL, 0, NULL);
5856
5857 return rc;
5858}
5859
5860static int efx_ef10_ptp_set_ts_sync_events(struct efx_nic *efx, bool en,
5861 bool temp)
5862{
5863 int (*set)(struct efx_channel *channel, bool temp);
5864 struct efx_channel *channel;
5865
5866 set = en ?
5867 efx_ef10_rx_enable_timestamping :
5868 efx_ef10_rx_disable_timestamping;
5869
5870 efx_for_each_channel(channel, efx) {
5871 int rc = set(channel, temp);
5872 if (en && rc != 0) {
5873 efx_ef10_ptp_set_ts_sync_events(efx, false, temp);
5874 return rc;
5875 }
5876 }
5877
5878 return 0;
5879}
5880
02246a7f
SS		 5881static int efx_ef10_ptp_set_ts_config_vf(struct efx_nic *efx,
5882 struct hwtstamp_config *init)
5883{
5884 return -EOPNOTSUPP;
5885}
5886
bd9a265d
JC		 5887static int efx_ef10_ptp_set_ts_config(struct efx_nic *efx,
5888 struct hwtstamp_config *init)
5889{
5890 int rc;
5891
5892 switch (init->rx_filter) {
5893 case HWTSTAMP_FILTER_NONE:
5894 efx_ef10_ptp_set_ts_sync_events(efx, false, false);
5895 /* if TX timestamping is still requested then leave PTP on */
5896 return efx_ptp_change_mode(efx,
5897 init->tx_type != HWTSTAMP_TX_OFF, 0);
5898 case HWTSTAMP_FILTER_ALL:
5899 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
5900 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
5901 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
5902 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
5903 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
5904 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
5905 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
5906 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
5907 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
5908 case HWTSTAMP_FILTER_PTP_V2_EVENT:
5909 case HWTSTAMP_FILTER_PTP_V2_SYNC:
5910 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
5911 init->rx_filter = HWTSTAMP_FILTER_ALL;
5912 rc = efx_ptp_change_mode(efx, true, 0);
5913 if (!rc)
5914 rc = efx_ef10_ptp_set_ts_sync_events(efx, true, false);
5915 if (rc)
5916 efx_ptp_change_mode(efx, false, 0);
5917 return rc;
5918 default:
5919 return -ERANGE;
5920 }
5921}
5922
08a7b29b
BK		 5923static int efx_ef10_get_phys_port_id(struct efx_nic *efx,
5924 struct netdev_phys_item_id *ppid)
5925{
5926 struct efx_ef10_nic_data *nic_data = efx->nic_data;
5927
5928 if (!is_valid_ether_addr(nic_data->port_id))
5929 return -EOPNOTSUPP;
5930
5931 ppid->id_len = ETH_ALEN;
5932 memcpy(ppid->id, nic_data->port_id, ppid->id_len);
5933
5934 return 0;
5935}
5936
4a53ea8a
AR		 5937static int efx_ef10_vlan_rx_add_vid(struct efx_nic *efx, __be16 proto, u16 vid)
5938{
5939 if (proto != htons(ETH_P_8021Q))
5940 return -EINVAL;
5941
5942 return efx_ef10_add_vlan(efx, vid);
5943}
5944
5945static int efx_ef10_vlan_rx_kill_vid(struct efx_nic *efx, __be16 proto, u16 vid)
5946{
5947 if (proto != htons(ETH_P_8021Q))
5948 return -EINVAL;
5949
5950 return efx_ef10_del_vlan(efx, vid);
5951}
5952
100a9db5
AR		 5953#define EF10_OFFLOAD_FEATURES \
5954 (NETIF_F_IP_CSUM | \
4a53ea8a 5955 NETIF_F_HW_VLAN_CTAG_FILTER | \
100a9db5
AR		 5956 NETIF_F_IPV6_CSUM | \
5957 NETIF_F_RXHASH | \
5958 NETIF_F_NTUPLE)
5959
02246a7f 5960const struct efx_nic_type efx_hunt_a0_vf_nic_type = {
6f7f8aa6 5961 .is_vf = true,
02246a7f
SS		 5962 .mem_bar = EFX_MEM_VF_BAR,
5963 .mem_map_size = efx_ef10_mem_map_size,
5964 .probe = efx_ef10_probe_vf,
5965 .remove = efx_ef10_remove,
5966 .dimension_resources = efx_ef10_dimension_resources,
5967 .init = efx_ef10_init_nic,
5968 .fini = efx_port_dummy_op_void,
087e9025 5969 .map_reset_reason = efx_ef10_map_reset_reason,
02246a7f
SS		 5970 .map_reset_flags = efx_ef10_map_reset_flags,
5971 .reset = efx_ef10_reset,
5972 .probe_port = efx_mcdi_port_probe,
5973 .remove_port = efx_mcdi_port_remove,
5974 .fini_dmaq = efx_ef10_fini_dmaq,
5975 .prepare_flr = efx_ef10_prepare_flr,
5976 .finish_flr = efx_port_dummy_op_void,
5977 .describe_stats = efx_ef10_describe_stats,
d7788196 5978 .update_stats = efx_ef10_update_stats_vf,
02246a7f
SS		 5979 .start_stats = efx_port_dummy_op_void,
5980 .pull_stats = efx_port_dummy_op_void,
5981 .stop_stats = efx_port_dummy_op_void,
5982 .set_id_led = efx_mcdi_set_id_led,
5983 .push_irq_moderation = efx_ef10_push_irq_moderation,
862f894c 5984 .reconfigure_mac = efx_ef10_mac_reconfigure_vf,
02246a7f
SS		 5985 .check_mac_fault = efx_mcdi_mac_check_fault,
5986 .reconfigure_port = efx_mcdi_port_reconfigure,
5987 .get_wol = efx_ef10_get_wol_vf,
5988 .set_wol = efx_ef10_set_wol_vf,
5989 .resume_wol = efx_port_dummy_op_void,
5990 .mcdi_request = efx_ef10_mcdi_request,
5991 .mcdi_poll_response = efx_ef10_mcdi_poll_response,
5992 .mcdi_read_response = efx_ef10_mcdi_read_response,
5993 .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot,
c577e59e 5994 .mcdi_reboot_detected = efx_ef10_mcdi_reboot_detected,
02246a7f
SS		 5995 .irq_enable_master = efx_port_dummy_op_void,
5996 .irq_test_generate = efx_ef10_irq_test_generate,
5997 .irq_disable_non_ev = efx_port_dummy_op_void,
5998 .irq_handle_msi = efx_ef10_msi_interrupt,
5999 .irq_handle_legacy = efx_ef10_legacy_interrupt,
6000 .tx_probe = efx_ef10_tx_probe,
6001 .tx_init = efx_ef10_tx_init,
6002 .tx_remove = efx_ef10_tx_remove,
6003 .tx_write = efx_ef10_tx_write,
e9117e50 6004 .tx_limit_len = efx_ef10_tx_limit_len,
267c0157 6005 .rx_push_rss_config = efx_ef10_vf_rx_push_rss_config,
a707d188 6006 .rx_pull_rss_config = efx_ef10_rx_pull_rss_config,
02246a7f
SS		 6007 .rx_probe = efx_ef10_rx_probe,
6008 .rx_init = efx_ef10_rx_init,
6009 .rx_remove = efx_ef10_rx_remove,
6010 .rx_write = efx_ef10_rx_write,
6011 .rx_defer_refill = efx_ef10_rx_defer_refill,
6012 .ev_probe = efx_ef10_ev_probe,
6013 .ev_init = efx_ef10_ev_init,
6014 .ev_fini = efx_ef10_ev_fini,
6015 .ev_remove = efx_ef10_ev_remove,
6016 .ev_process = efx_ef10_ev_process,
6017 .ev_read_ack = efx_ef10_ev_read_ack,
6018 .ev_test_generate = efx_ef10_ev_test_generate,
6019 .filter_table_probe = efx_ef10_filter_table_probe,
6020 .filter_table_restore = efx_ef10_filter_table_restore,
6021 .filter_table_remove = efx_ef10_filter_table_remove,
6022 .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter,
6023 .filter_insert = efx_ef10_filter_insert,
6024 .filter_remove_safe = efx_ef10_filter_remove_safe,
6025 .filter_get_safe = efx_ef10_filter_get_safe,
6026 .filter_clear_rx = efx_ef10_filter_clear_rx,
6027 .filter_count_rx_used = efx_ef10_filter_count_rx_used,
6028 .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit,
6029 .filter_get_rx_ids = efx_ef10_filter_get_rx_ids,
6030#ifdef CONFIG_RFS_ACCEL
6031 .filter_rfs_insert = efx_ef10_filter_rfs_insert,
6032 .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one,
6033#endif
6034#ifdef CONFIG_SFC_MTD
6035 .mtd_probe = efx_port_dummy_op_int,
6036#endif
6037 .ptp_write_host_time = efx_ef10_ptp_write_host_time_vf,
6038 .ptp_set_ts_config = efx_ef10_ptp_set_ts_config_vf,
4a53ea8a
AR		 6039 .vlan_rx_add_vid = efx_ef10_vlan_rx_add_vid,
6040 .vlan_rx_kill_vid = efx_ef10_vlan_rx_kill_vid,
02246a7f 6041#ifdef CONFIG_SFC_SRIOV
7b8c7b54
SS		 6042 .vswitching_probe = efx_ef10_vswitching_probe_vf,
6043 .vswitching_restore = efx_ef10_vswitching_restore_vf,
6044 .vswitching_remove = efx_ef10_vswitching_remove_vf,
02246a7f 6045#endif
0d5e0fbb 6046 .get_mac_address = efx_ef10_get_mac_address_vf,
910c8789 6047 .set_mac_address = efx_ef10_set_mac_address,
0d5e0fbb 6048
08a7b29b 6049 .get_phys_port_id = efx_ef10_get_phys_port_id,
02246a7f
SS		 6050 .revision = EFX_REV_HUNT_A0,
6051 .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH),
6052 .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE,
6053 .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST,
6054 .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST,
6055 .can_rx_scatter = true,
6056 .always_rx_scatter = true,
6057 .max_interrupt_mode = EFX_INT_MODE_MSIX,
6058 .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH,
100a9db5 6059 .offload_features = EF10_OFFLOAD_FEATURES,
02246a7f
SS		 6060 .mcdi_max_ver = 2,
6061 .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS,
6062 .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE |
6063 1 << HWTSTAMP_FILTER_ALL,
f74d1995 6064 .rx_hash_key_size = 40,
02246a7f
SS		 6065};
6066
8127d661 6067const struct efx_nic_type efx_hunt_a0_nic_type = {
6f7f8aa6 6068 .is_vf = false,
02246a7f 6069 .mem_bar = EFX_MEM_BAR,
8127d661 6070 .mem_map_size = efx_ef10_mem_map_size,
02246a7f 6071 .probe = efx_ef10_probe_pf,
8127d661
BH		 6072 .remove = efx_ef10_remove,
6073 .dimension_resources = efx_ef10_dimension_resources,
6074 .init = efx_ef10_init_nic,
6075 .fini = efx_port_dummy_op_void,
087e9025 6076 .map_reset_reason = efx_ef10_map_reset_reason,
8127d661 6077 .map_reset_flags = efx_ef10_map_reset_flags,
3e336261 6078 .reset = efx_ef10_reset,
8127d661
BH		 6079 .probe_port = efx_mcdi_port_probe,
6080 .remove_port = efx_mcdi_port_remove,
6081 .fini_dmaq = efx_ef10_fini_dmaq,
e283546c
EC		 6082 .prepare_flr = efx_ef10_prepare_flr,
6083 .finish_flr = efx_port_dummy_op_void,
8127d661 6084 .describe_stats = efx_ef10_describe_stats,
d7788196 6085 .update_stats = efx_ef10_update_stats_pf,
8127d661 6086 .start_stats = efx_mcdi_mac_start_stats,
f8f3b5ae 6087 .pull_stats = efx_mcdi_mac_pull_stats,
8127d661
BH		 6088 .stop_stats = efx_mcdi_mac_stop_stats,
6089 .set_id_led = efx_mcdi_set_id_led,
6090 .push_irq_moderation = efx_ef10_push_irq_moderation,
6091 .reconfigure_mac = efx_ef10_mac_reconfigure,
6092 .check_mac_fault = efx_mcdi_mac_check_fault,
6093 .reconfigure_port = efx_mcdi_port_reconfigure,
6094 .get_wol = efx_ef10_get_wol,
6095 .set_wol = efx_ef10_set_wol,
6096 .resume_wol = efx_port_dummy_op_void,
74cd60a4 6097 .test_chip = efx_ef10_test_chip,
8127d661
BH		 6098 .test_nvram = efx_mcdi_nvram_test_all,
6099 .mcdi_request = efx_ef10_mcdi_request,
6100 .mcdi_poll_response = efx_ef10_mcdi_poll_response,
6101 .mcdi_read_response = efx_ef10_mcdi_read_response,
6102 .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot,
c577e59e 6103 .mcdi_reboot_detected = efx_ef10_mcdi_reboot_detected,
8127d661
BH		 6104 .irq_enable_master = efx_port_dummy_op_void,
6105 .irq_test_generate = efx_ef10_irq_test_generate,
6106 .irq_disable_non_ev = efx_port_dummy_op_void,
6107 .irq_handle_msi = efx_ef10_msi_interrupt,
6108 .irq_handle_legacy = efx_ef10_legacy_interrupt,
6109 .tx_probe = efx_ef10_tx_probe,
6110 .tx_init = efx_ef10_tx_init,
6111 .tx_remove = efx_ef10_tx_remove,
6112 .tx_write = efx_ef10_tx_write,
e9117e50 6113 .tx_limit_len = efx_ef10_tx_limit_len,
267c0157 6114 .rx_push_rss_config = efx_ef10_pf_rx_push_rss_config,
a707d188 6115 .rx_pull_rss_config = efx_ef10_rx_pull_rss_config,
8127d661
BH		 6116 .rx_probe = efx_ef10_rx_probe,
6117 .rx_init = efx_ef10_rx_init,
6118 .rx_remove = efx_ef10_rx_remove,
6119 .rx_write = efx_ef10_rx_write,
6120 .rx_defer_refill = efx_ef10_rx_defer_refill,
6121 .ev_probe = efx_ef10_ev_probe,
6122 .ev_init = efx_ef10_ev_init,
6123 .ev_fini = efx_ef10_ev_fini,
6124 .ev_remove = efx_ef10_ev_remove,
6125 .ev_process = efx_ef10_ev_process,
6126 .ev_read_ack = efx_ef10_ev_read_ack,
6127 .ev_test_generate = efx_ef10_ev_test_generate,
6128 .filter_table_probe = efx_ef10_filter_table_probe,
6129 .filter_table_restore = efx_ef10_filter_table_restore,
6130 .filter_table_remove = efx_ef10_filter_table_remove,
6131 .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter,
6132 .filter_insert = efx_ef10_filter_insert,
6133 .filter_remove_safe = efx_ef10_filter_remove_safe,
6134 .filter_get_safe = efx_ef10_filter_get_safe,
6135 .filter_clear_rx = efx_ef10_filter_clear_rx,
6136 .filter_count_rx_used = efx_ef10_filter_count_rx_used,
6137 .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit,
6138 .filter_get_rx_ids = efx_ef10_filter_get_rx_ids,
6139#ifdef CONFIG_RFS_ACCEL
6140 .filter_rfs_insert = efx_ef10_filter_rfs_insert,
6141 .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one,
6142#endif
6143#ifdef CONFIG_SFC_MTD
6144 .mtd_probe = efx_ef10_mtd_probe,
6145 .mtd_rename = efx_mcdi_mtd_rename,
6146 .mtd_read = efx_mcdi_mtd_read,
6147 .mtd_erase = efx_mcdi_mtd_erase,
6148 .mtd_write = efx_mcdi_mtd_write,
6149 .mtd_sync = efx_mcdi_mtd_sync,
6150#endif
6151 .ptp_write_host_time = efx_ef10_ptp_write_host_time,
bd9a265d
JC		 6152 .ptp_set_ts_sync_events = efx_ef10_ptp_set_ts_sync_events,
6153 .ptp_set_ts_config = efx_ef10_ptp_set_ts_config,
4a53ea8a
AR		 6154 .vlan_rx_add_vid = efx_ef10_vlan_rx_add_vid,
6155 .vlan_rx_kill_vid = efx_ef10_vlan_rx_kill_vid,
7fa8d547 6156#ifdef CONFIG_SFC_SRIOV
834e23dd 6157 .sriov_configure = efx_ef10_sriov_configure,
d98a4ffe
SS		 6158 .sriov_init = efx_ef10_sriov_init,
6159 .sriov_fini = efx_ef10_sriov_fini,
d98a4ffe
SS		 6160 .sriov_wanted = efx_ef10_sriov_wanted,
6161 .sriov_reset = efx_ef10_sriov_reset,
7fa8d547
SS		 6162 .sriov_flr = efx_ef10_sriov_flr,
6163 .sriov_set_vf_mac = efx_ef10_sriov_set_vf_mac,
6164 .sriov_set_vf_vlan = efx_ef10_sriov_set_vf_vlan,
6165 .sriov_set_vf_spoofchk = efx_ef10_sriov_set_vf_spoofchk,
6166 .sriov_get_vf_config = efx_ef10_sriov_get_vf_config,
4392dc69 6167 .sriov_set_vf_link_state = efx_ef10_sriov_set_vf_link_state,
7b8c7b54
SS		 6168 .vswitching_probe = efx_ef10_vswitching_probe_pf,
6169 .vswitching_restore = efx_ef10_vswitching_restore_pf,
6170 .vswitching_remove = efx_ef10_vswitching_remove_pf,
7fa8d547 6171#endif
0d5e0fbb 6172 .get_mac_address = efx_ef10_get_mac_address_pf,
910c8789 6173 .set_mac_address = efx_ef10_set_mac_address,
46d1efd8 6174 .tso_versions = efx_ef10_tso_versions,
8127d661 6175
08a7b29b 6176 .get_phys_port_id = efx_ef10_get_phys_port_id,
8127d661
BH		 6177 .revision = EFX_REV_HUNT_A0,
6178 .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH),
6179 .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE,
6180 .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST,
bd9a265d 6181 .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST,
8127d661
BH		 6182 .can_rx_scatter = true,
6183 .always_rx_scatter = true,
de1deff9 6184 .option_descriptors = true,
8127d661
BH		 6185 .max_interrupt_mode = EFX_INT_MODE_MSIX,
6186 .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH,
100a9db5 6187 .offload_features = EF10_OFFLOAD_FEATURES,
8127d661
BH		 6188 .mcdi_max_ver = 2,
6189 .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS,
bd9a265d
JC		 6190 .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE |
6191 1 << HWTSTAMP_FILTER_ALL,
f74d1995 6192 .rx_hash_key_size = 40,
8127d661 6193};
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