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[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / sfc / efx.c
CommitLineData
8ceee660 1/****************************************************************************
f7a6d2c4 2 * Driver for Solarflare network controllers and boards
8ceee660 3 * Copyright 2005-2006 Fen Systems Ltd.
f7a6d2c4 4 * Copyright 2005-2013 Solarflare Communications Inc.
8ceee660
BH		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
10
11#include <linux/module.h>
12#include <linux/pci.h>
13#include <linux/netdevice.h>
14#include <linux/etherdevice.h>
15#include <linux/delay.h>
16#include <linux/notifier.h>
17#include <linux/ip.h>
18#include <linux/tcp.h>
19#include <linux/in.h>
8ceee660 20#include <linux/ethtool.h>
aa6ef27e 21#include <linux/topology.h>
5a0e3ad6 22#include <linux/gfp.h>
626950db 23#include <linux/aer.h>
b28405b0 24#include <linux/interrupt.h>
8ceee660 25#include "net_driver.h"
8ceee660 26#include "efx.h"
744093c9 27#include "nic.h"
dd40781e 28#include "selftest.h"
7fa8d547 29#include "sriov.h"
8ceee660 30
8880f4ec 31#include "mcdi.h"
fd371e32 32#include "workarounds.h"
8880f4ec 33
c459302d
BH		 34/**************************************************************************
35 *
36 * Type name strings
37 *
38 **************************************************************************
39 */
40
41/* Loopback mode names (see LOOPBACK_MODE()) */
42const unsigned int efx_loopback_mode_max = LOOPBACK_MAX;
18e83e4c 43const char *const efx_loopback_mode_names[] = {
c459302d 44 [LOOPBACK_NONE] = "NONE",
e58f69f4 45 [LOOPBACK_DATA] = "DATAPATH",
c459302d
BH		 46 [LOOPBACK_GMAC] = "GMAC",
47 [LOOPBACK_XGMII] = "XGMII",
48 [LOOPBACK_XGXS] = "XGXS",
9c636baf
BH		 49 [LOOPBACK_XAUI] = "XAUI",
50 [LOOPBACK_GMII] = "GMII",
51 [LOOPBACK_SGMII] = "SGMII",
e58f69f4
BH		 52 [LOOPBACK_XGBR] = "XGBR",
53 [LOOPBACK_XFI] = "XFI",
54 [LOOPBACK_XAUI_FAR] = "XAUI_FAR",
55 [LOOPBACK_GMII_FAR] = "GMII_FAR",
56 [LOOPBACK_SGMII_FAR] = "SGMII_FAR",
57 [LOOPBACK_XFI_FAR] = "XFI_FAR",
c459302d
BH		 58 [LOOPBACK_GPHY] = "GPHY",
59 [LOOPBACK_PHYXS] = "PHYXS",
9c636baf
BH		 60 [LOOPBACK_PCS] = "PCS",
61 [LOOPBACK_PMAPMD] = "PMA/PMD",
e58f69f4
BH		 62 [LOOPBACK_XPORT] = "XPORT",
63 [LOOPBACK_XGMII_WS] = "XGMII_WS",
9c636baf 64 [LOOPBACK_XAUI_WS] = "XAUI_WS",
e58f69f4
BH		 65 [LOOPBACK_XAUI_WS_FAR] = "XAUI_WS_FAR",
66 [LOOPBACK_XAUI_WS_NEAR] = "XAUI_WS_NEAR",
9c636baf 67 [LOOPBACK_GMII_WS] = "GMII_WS",
e58f69f4
BH		 68 [LOOPBACK_XFI_WS] = "XFI_WS",
69 [LOOPBACK_XFI_WS_FAR] = "XFI_WS_FAR",
9c636baf 70 [LOOPBACK_PHYXS_WS] = "PHYXS_WS",
c459302d
BH		 71};
72
c459302d 73const unsigned int efx_reset_type_max = RESET_TYPE_MAX;
18e83e4c 74const char *const efx_reset_type_names[] = {
626950db
AR		 75 [RESET_TYPE_INVISIBLE] = "INVISIBLE",
76 [RESET_TYPE_ALL] = "ALL",
77 [RESET_TYPE_RECOVER_OR_ALL] = "RECOVER_OR_ALL",
78 [RESET_TYPE_WORLD] = "WORLD",
79 [RESET_TYPE_RECOVER_OR_DISABLE] = "RECOVER_OR_DISABLE",
087e9025 80 [RESET_TYPE_DATAPATH] = "DATAPATH",
e283546c 81 [RESET_TYPE_MC_BIST] = "MC_BIST",
626950db
AR		 82 [RESET_TYPE_DISABLE] = "DISABLE",
83 [RESET_TYPE_TX_WATCHDOG] = "TX_WATCHDOG",
84 [RESET_TYPE_INT_ERROR] = "INT_ERROR",
3de82b91 85 [RESET_TYPE_DMA_ERROR] = "DMA_ERROR",
626950db
AR		 86 [RESET_TYPE_TX_SKIP] = "TX_SKIP",
87 [RESET_TYPE_MC_FAILURE] = "MC_FAILURE",
e283546c 88 [RESET_TYPE_MCDI_TIMEOUT] = "MCDI_TIMEOUT (FLR)",
c459302d
BH		 89};
90
1ab00629
SH		 91/* Reset workqueue. If any NIC has a hardware failure then a reset will be
92 * queued onto this work queue. This is not a per-nic work queue, because
93 * efx_reset_work() acquires the rtnl lock, so resets are naturally serialised.
94 */
95static struct workqueue_struct *reset_workqueue;
96
74cd60a4
JC		 97/* How often and how many times to poll for a reset while waiting for a
98 * BIST that another function started to complete.
99 */
100#define BIST_WAIT_DELAY_MS 100
101#define BIST_WAIT_DELAY_COUNT 100
102
8ceee660
BH		 103/**************************************************************************
104 *
105 * Configurable values
106 *
107 *************************************************************************/
108
8ceee660
BH		 109/*
110 * Use separate channels for TX and RX events
111 *
28b581ab
NT		 112 * Set this to 1 to use separate channels for TX and RX. It allows us
113 * to control interrupt affinity separately for TX and RX.
8ceee660 114 *
28b581ab 115 * This is only used in MSI-X interrupt mode
8ceee660 116 */
b0fbdae1
SS		 117bool efx_separate_tx_channels;
118module_param(efx_separate_tx_channels, bool, 0444);
119MODULE_PARM_DESC(efx_separate_tx_channels,
28b581ab 120 "Use separate channels for TX and RX");
8ceee660
BH		 121
122/* This is the weight assigned to each of the (per-channel) virtual
123 * NAPI devices.
124 */
125static int napi_weight = 64;
126
127/* This is the time (in jiffies) between invocations of the hardware
626950db
AR		 128 * monitor.
129 * On Falcon-based NICs, this will:
e254c274
BH		 130 * - Check the on-board hardware monitor;
131 * - Poll the link state and reconfigure the hardware as necessary.
626950db
AR		 132 * On Siena-based NICs for power systems with EEH support, this will give EEH a
133 * chance to start.
8ceee660 134 */
d215697f 135static unsigned int efx_monitor_interval = 1 * HZ;
8ceee660 136
8ceee660
BH		 137/* Initial interrupt moderation settings. They can be modified after
138 * module load with ethtool.
139 *
140 * The default for RX should strike a balance between increasing the
141 * round-trip latency and reducing overhead.
142 */
143static unsigned int rx_irq_mod_usec = 60;
144
145/* Initial interrupt moderation settings. They can be modified after
146 * module load with ethtool.
147 *
148 * This default is chosen to ensure that a 10G link does not go idle
149 * while a TX queue is stopped after it has become full. A queue is
150 * restarted when it drops below half full. The time this takes (assuming
151 * worst case 3 descriptors per packet and 1024 descriptors) is
152 * 512 / 3 * 1.2 = 205 usec.
153 */
154static unsigned int tx_irq_mod_usec = 150;
155
156/* This is the first interrupt mode to try out of:
157 * 0 => MSI-X
158 * 1 => MSI
159 * 2 => legacy
160 */
161static unsigned int interrupt_mode;
162
163/* This is the requested number of CPUs to use for Receive-Side Scaling (RSS),
164 * i.e. the number of CPUs among which we may distribute simultaneous
165 * interrupt handling.
166 *
167 * Cards without MSI-X will only target one CPU via legacy or MSI interrupt.
cdb08f8f 168 * The default (0) means to assign an interrupt to each core.
8ceee660
BH		 169 */
170static unsigned int rss_cpus;
171module_param(rss_cpus, uint, 0444);
172MODULE_PARM_DESC(rss_cpus, "Number of CPUs to use for Receive-Side Scaling");
173
b9cc977d
BH		 174static bool phy_flash_cfg;
175module_param(phy_flash_cfg, bool, 0644);
84ae48fe
BH		 176MODULE_PARM_DESC(phy_flash_cfg, "Set PHYs into reflash mode initially");
177
e7bed9c8 178static unsigned irq_adapt_low_thresh = 8000;
6fb70fd1
BH		 179module_param(irq_adapt_low_thresh, uint, 0644);
180MODULE_PARM_DESC(irq_adapt_low_thresh,
181 "Threshold score for reducing IRQ moderation");
182
e7bed9c8 183static unsigned irq_adapt_high_thresh = 16000;
6fb70fd1
BH		 184module_param(irq_adapt_high_thresh, uint, 0644);
185MODULE_PARM_DESC(irq_adapt_high_thresh,
186 "Threshold score for increasing IRQ moderation");
187
62776d03
BH		 188static unsigned debug = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
189 NETIF_MSG_LINK | NETIF_MSG_IFDOWN |
190 NETIF_MSG_IFUP | NETIF_MSG_RX_ERR |
191 NETIF_MSG_TX_ERR | NETIF_MSG_HW);
192module_param(debug, uint, 0);
193MODULE_PARM_DESC(debug, "Bitmapped debugging message enable value");
194
8ceee660
BH		 195/**************************************************************************
196 *
197 * Utility functions and prototypes
198 *
199 *************************************************************************/
4642610c 200
261e4d96 201static int efx_soft_enable_interrupts(struct efx_nic *efx);
d8291187 202static void efx_soft_disable_interrupts(struct efx_nic *efx);
7f967c01 203static void efx_remove_channel(struct efx_channel *channel);
4642610c 204static void efx_remove_channels(struct efx_nic *efx);
7f967c01 205static const struct efx_channel_type efx_default_channel_type;
8ceee660 206static void efx_remove_port(struct efx_nic *efx);
7f967c01 207static void efx_init_napi_channel(struct efx_channel *channel);
8ceee660 208static void efx_fini_napi(struct efx_nic *efx);
e8f14992 209static void efx_fini_napi_channel(struct efx_channel *channel);
4642610c
BH		 210static void efx_fini_struct(struct efx_nic *efx);
211static void efx_start_all(struct efx_nic *efx);
212static void efx_stop_all(struct efx_nic *efx);
8ceee660
BH		 213
214#define EFX_ASSERT_RESET_SERIALISED(efx) \
215 do { \
f16aeea0 216 if ((efx->state == STATE_READY) || \
626950db 217 (efx->state == STATE_RECOVERY) || \
332c1ce9 218 (efx->state == STATE_DISABLED)) \
8ceee660
BH		 219 ASSERT_RTNL(); \
220 } while (0)
221
8b7325b4
BH		 222static int efx_check_disabled(struct efx_nic *efx)
223{
626950db 224 if (efx->state == STATE_DISABLED || efx->state == STATE_RECOVERY) {
8b7325b4
BH		 225 netif_err(efx, drv, efx->net_dev,
226 "device is disabled due to earlier errors\n");
227 return -EIO;
228 }
229 return 0;
230}
231
8ceee660
BH		 232/**************************************************************************
233 *
234 * Event queue processing
235 *
236 *************************************************************************/
237
238/* Process channel's event queue
239 *
240 * This function is responsible for processing the event queue of a
241 * single channel. The caller must guarantee that this function will
242 * never be concurrently called more than once on the same channel,
243 * though different channels may be being processed concurrently.
244 */
fa236e18 245static int efx_process_channel(struct efx_channel *channel, int budget)
8ceee660 246{
c936835c 247 struct efx_tx_queue *tx_queue;
fa236e18 248 int spent;
8ceee660 249
9f2cb71c 250 if (unlikely(!channel->enabled))
42cbe2d7 251 return 0;
8ceee660 252
c936835c
PD		 253 efx_for_each_channel_tx_queue(tx_queue, channel) {
254 tx_queue->pkts_compl = 0;
255 tx_queue->bytes_compl = 0;
256 }
257
fa236e18 258 spent = efx_nic_process_eventq(channel, budget);
d9ab7007
BH		 259 if (spent && efx_channel_has_rx_queue(channel)) {
260 struct efx_rx_queue *rx_queue =
261 efx_channel_get_rx_queue(channel);
262
ff734ef4 263 efx_rx_flush_packet(channel);
cce28794 264 efx_fast_push_rx_descriptors(rx_queue, true);
8ceee660
BH		 265 }
266
c936835c
PD		 267 /* Update BQL */
268 efx_for_each_channel_tx_queue(tx_queue, channel) {
269 if (tx_queue->bytes_compl) {
270 netdev_tx_completed_queue(tx_queue->core_txq,
271 tx_queue->pkts_compl, tx_queue->bytes_compl);
272 }
273 }
274
fa236e18 275 return spent;
8ceee660
BH		 276}
277
8ceee660
BH		 278/* NAPI poll handler
279 *
280 * NAPI guarantees serialisation of polls of the same device, which
281 * provides the guarantee required by efx_process_channel().
282 */
539de7c5
BK		 283static void efx_update_irq_mod(struct efx_nic *efx, struct efx_channel *channel)
284{
285 int step = efx->irq_mod_step_us;
286
287 if (channel->irq_mod_score < irq_adapt_low_thresh) {
288 if (channel->irq_moderation_us > step) {
289 channel->irq_moderation_us -= step;
290 efx->type->push_irq_moderation(channel);
291 }
292 } else if (channel->irq_mod_score > irq_adapt_high_thresh) {
293 if (channel->irq_moderation_us <
294 efx->irq_rx_moderation_us) {
295 channel->irq_moderation_us += step;
296 efx->type->push_irq_moderation(channel);
297 }
298 }
299
300 channel->irq_count = 0;
301 channel->irq_mod_score = 0;
302}
303
8ceee660
BH		 304static int efx_poll(struct napi_struct *napi, int budget)
305{
306 struct efx_channel *channel =
307 container_of(napi, struct efx_channel, napi_str);
62776d03 308 struct efx_nic *efx = channel->efx;
fa236e18 309 int spent;
8ceee660 310
36763266
AR		 311 if (!efx_channel_lock_napi(channel))
312 return budget;
313
62776d03
BH		 314 netif_vdbg(efx, intr, efx->net_dev,
315 "channel %d NAPI poll executing on CPU %d\n",
316 channel->channel, raw_smp_processor_id());
8ceee660 317
fa236e18 318 spent = efx_process_channel(channel, budget);
8ceee660 319
fa236e18 320 if (spent < budget) {
9d9a6973 321 if (efx_channel_has_rx_queue(channel) &&
6fb70fd1
BH		 322 efx->irq_rx_adaptive &&
323 unlikely(++channel->irq_count == 1000)) {
539de7c5 324 efx_update_irq_mod(efx, channel);
6fb70fd1
BH		 325 }
326
64d8ad6d
BH		 327 efx_filter_rfs_expire(channel);
328
8ceee660 329 /* There is no race here; although napi_disable() will
288379f0 330 * only wait for napi_complete(), this isn't a problem
514bedbc 331 * since efx_nic_eventq_read_ack() will have no effect if
8ceee660
BH		 332 * interrupts have already been disabled.
333 */
288379f0 334 napi_complete(napi);
514bedbc 335 efx_nic_eventq_read_ack(channel);
8ceee660
BH		 336 }
337
36763266 338 efx_channel_unlock_napi(channel);
fa236e18 339 return spent;
8ceee660
BH		 340}
341
8ceee660
BH		 342/* Create event queue
343 * Event queue memory allocations are done only once. If the channel
344 * is reset, the memory buffer will be reused; this guards against
345 * errors during channel reset and also simplifies interrupt handling.
346 */
347static int efx_probe_eventq(struct efx_channel *channel)
348{
ecc910f5
SH		 349 struct efx_nic *efx = channel->efx;
350 unsigned long entries;
351
86ee5302 352 netif_dbg(efx, probe, efx->net_dev,
62776d03 353 "chan %d create event queue\n", channel->channel);
8ceee660 354
ecc910f5
SH		 355 /* Build an event queue with room for one event per tx and rx buffer,
356 * plus some extra for link state events and MCDI completions. */
357 entries = roundup_pow_of_two(efx->rxq_entries + efx->txq_entries + 128);
e01b16a7 358 EFX_WARN_ON_PARANOID(entries > EFX_MAX_EVQ_SIZE);
ecc910f5
SH		 359 channel->eventq_mask = max(entries, EFX_MIN_EVQ_SIZE) - 1;
360
152b6a62 361 return efx_nic_probe_eventq(channel);
8ceee660
BH		 362}
363
364/* Prepare channel's event queue */
261e4d96 365static int efx_init_eventq(struct efx_channel *channel)
8ceee660 366{
15acb1ce 367 struct efx_nic *efx = channel->efx;
261e4d96
JC		 368 int rc;
369
370 EFX_WARN_ON_PARANOID(channel->eventq_init);
371
15acb1ce 372 netif_dbg(efx, drv, efx->net_dev,
62776d03 373 "chan %d init event queue\n", channel->channel);
8ceee660 374
261e4d96
JC		 375 rc = efx_nic_init_eventq(channel);
376 if (rc == 0) {
15acb1ce 377 efx->type->push_irq_moderation(channel);
261e4d96
JC		 378 channel->eventq_read_ptr = 0;
379 channel->eventq_init = true;
380 }
381 return rc;
8ceee660
BH		 382}
383
9f2cb71c 384/* Enable event queue processing and NAPI */
36763266 385void efx_start_eventq(struct efx_channel *channel)
9f2cb71c
BH		 386{
387 netif_dbg(channel->efx, ifup, channel->efx->net_dev,
388 "chan %d start event queue\n", channel->channel);
389
514bedbc 390 /* Make sure the NAPI handler sees the enabled flag set */
9f2cb71c
BH		 391 channel->enabled = true;
392 smp_wmb();
393
36763266 394 efx_channel_enable(channel);
9f2cb71c
BH		 395 napi_enable(&channel->napi_str);
396 efx_nic_eventq_read_ack(channel);
397}
398
399/* Disable event queue processing and NAPI */
36763266 400void efx_stop_eventq(struct efx_channel *channel)
9f2cb71c
BH		 401{
402 if (!channel->enabled)
403 return;
404
405 napi_disable(&channel->napi_str);
36763266
AR		 406 while (!efx_channel_disable(channel))
407 usleep_range(1000, 20000);
9f2cb71c
BH		 408 channel->enabled = false;
409}
410
8ceee660
BH		 411static void efx_fini_eventq(struct efx_channel *channel)
412{
be3fc09c
BH		 413 if (!channel->eventq_init)
414 return;
415
62776d03
BH		 416 netif_dbg(channel->efx, drv, channel->efx->net_dev,
417 "chan %d fini event queue\n", channel->channel);
8ceee660 418
152b6a62 419 efx_nic_fini_eventq(channel);
be3fc09c 420 channel->eventq_init = false;
8ceee660
BH		 421}
422
423static void efx_remove_eventq(struct efx_channel *channel)
424{
62776d03
BH		 425 netif_dbg(channel->efx, drv, channel->efx->net_dev,
426 "chan %d remove event queue\n", channel->channel);
8ceee660 427
152b6a62 428 efx_nic_remove_eventq(channel);
8ceee660
BH		 429}
430
431/**************************************************************************
432 *
433 * Channel handling
434 *
435 *************************************************************************/
436
7f967c01 437/* Allocate and initialise a channel structure. */
4642610c
BH		 438static struct efx_channel *
439efx_alloc_channel(struct efx_nic *efx, int i, struct efx_channel *old_channel)
440{
441 struct efx_channel *channel;
442 struct efx_rx_queue *rx_queue;
443 struct efx_tx_queue *tx_queue;
444 int j;
445
7f967c01
BH		 446 channel = kzalloc(sizeof(*channel), GFP_KERNEL);
447 if (!channel)
448 return NULL;
4642610c 449
7f967c01
BH		 450 channel->efx = efx;
451 channel->channel = i;
452 channel->type = &efx_default_channel_type;
4642610c 453
7f967c01
BH		 454 for (j = 0; j < EFX_TXQ_TYPES; j++) {
455 tx_queue = &channel->tx_queue[j];
456 tx_queue->efx = efx;
457 tx_queue->queue = i * EFX_TXQ_TYPES + j;
458 tx_queue->channel = channel;
459 }
4642610c 460
7f967c01
BH		 461 rx_queue = &channel->rx_queue;
462 rx_queue->efx = efx;
463 setup_timer(&rx_queue->slow_fill, efx_rx_slow_fill,
464 (unsigned long)rx_queue);
4642610c 465
7f967c01
BH		 466 return channel;
467}
468
469/* Allocate and initialise a channel structure, copying parameters
470 * (but not resources) from an old channel structure.
471 */
472static struct efx_channel *
473efx_copy_channel(const struct efx_channel *old_channel)
474{
475 struct efx_channel *channel;
476 struct efx_rx_queue *rx_queue;
477 struct efx_tx_queue *tx_queue;
478 int j;
4642610c 479
7f967c01
BH		 480 channel = kmalloc(sizeof(*channel), GFP_KERNEL);
481 if (!channel)
482 return NULL;
483
484 *channel = *old_channel;
485
486 channel->napi_dev = NULL;
46d054f8
BK		 487 INIT_HLIST_NODE(&channel->napi_str.napi_hash_node);
488 channel->napi_str.napi_id = 0;
489 channel->napi_str.state = 0;
7f967c01 490 memset(&channel->eventq, 0, sizeof(channel->eventq));
4642610c 491
7f967c01
BH		 492 for (j = 0; j < EFX_TXQ_TYPES; j++) {
493 tx_queue = &channel->tx_queue[j];
494 if (tx_queue->channel)
4642610c 495 tx_queue->channel = channel;
7f967c01
BH		 496 tx_queue->buffer = NULL;
497 memset(&tx_queue->txd, 0, sizeof(tx_queue->txd));
4642610c
BH		 498 }
499
4642610c 500 rx_queue = &channel->rx_queue;
7f967c01
BH		 501 rx_queue->buffer = NULL;
502 memset(&rx_queue->rxd, 0, sizeof(rx_queue->rxd));
4642610c
BH		 503 setup_timer(&rx_queue->slow_fill, efx_rx_slow_fill,
504 (unsigned long)rx_queue);
505
506 return channel;
507}
508
8ceee660
BH		 509static int efx_probe_channel(struct efx_channel *channel)
510{
511 struct efx_tx_queue *tx_queue;
512 struct efx_rx_queue *rx_queue;
513 int rc;
514
62776d03
BH		 515 netif_dbg(channel->efx, probe, channel->efx->net_dev,
516 "creating channel %d\n", channel->channel);
8ceee660 517
7f967c01
BH		 518 rc = channel->type->pre_probe(channel);
519 if (rc)
520 goto fail;
521
8ceee660
BH		 522 rc = efx_probe_eventq(channel);
523 if (rc)
7f967c01 524 goto fail;
8ceee660
BH		 525
526 efx_for_each_channel_tx_queue(tx_queue, channel) {
527 rc = efx_probe_tx_queue(tx_queue);
528 if (rc)
7f967c01 529 goto fail;
8ceee660
BH		 530 }
531
532 efx_for_each_channel_rx_queue(rx_queue, channel) {
533 rc = efx_probe_rx_queue(rx_queue);
534 if (rc)
7f967c01 535 goto fail;
8ceee660
BH		 536 }
537
8ceee660
BH		 538 return 0;
539
7f967c01
BH		 540fail:
541 efx_remove_channel(channel);
8ceee660
BH		 542 return rc;
543}
544
7f967c01
BH		 545static void
546efx_get_channel_name(struct efx_channel *channel, char *buf, size_t len)
547{
548 struct efx_nic *efx = channel->efx;
549 const char *type;
550 int number;
551
552 number = channel->channel;
553 if (efx->tx_channel_offset == 0) {
554 type = "";
555 } else if (channel->channel < efx->tx_channel_offset) {
556 type = "-rx";
557 } else {
558 type = "-tx";
559 number -= efx->tx_channel_offset;
560 }
561 snprintf(buf, len, "%s%s-%d", efx->name, type, number);
562}
8ceee660 563
56536e9c
BH		 564static void efx_set_channel_names(struct efx_nic *efx)
565{
566 struct efx_channel *channel;
56536e9c 567
7f967c01
BH		 568 efx_for_each_channel(channel, efx)
569 channel->type->get_name(channel,
d8291187
BH		 570 efx->msi_context[channel->channel].name,
571 sizeof(efx->msi_context[0].name));
56536e9c
BH		 572}
573
4642610c
BH		 574static int efx_probe_channels(struct efx_nic *efx)
575{
576 struct efx_channel *channel;
577 int rc;
578
579 /* Restart special buffer allocation */
580 efx->next_buffer_table = 0;
581
c92aaff1
BH		 582 /* Probe channels in reverse, so that any 'extra' channels
583 * use the start of the buffer table. This allows the traffic
584 * channels to be resized without moving them or wasting the
585 * entries before them.
586 */
587 efx_for_each_channel_rev(channel, efx) {
4642610c
BH		 588 rc = efx_probe_channel(channel);
589 if (rc) {
590 netif_err(efx, probe, efx->net_dev,
591 "failed to create channel %d\n",
592 channel->channel);
593 goto fail;
594 }
595 }
596 efx_set_channel_names(efx);
597
598 return 0;
599
600fail:
601 efx_remove_channels(efx);
602 return rc;
603}
604
8ceee660
BH		 605/* Channels are shutdown and reinitialised whilst the NIC is running
606 * to propagate configuration changes (mtu, checksum offload), or
607 * to clear hardware error conditions
608 */
9f2cb71c 609static void efx_start_datapath(struct efx_nic *efx)
8ceee660 610{
ebfcd0fd 611 netdev_features_t old_features = efx->net_dev->features;
85740cdf 612 bool old_rx_scatter = efx->rx_scatter;
8ceee660
BH		 613 struct efx_tx_queue *tx_queue;
614 struct efx_rx_queue *rx_queue;
615 struct efx_channel *channel;
85740cdf 616 size_t rx_buf_len;
8ceee660 617
f7f13b0b
BH		 618 /* Calculate the rx buffer allocation parameters required to
619 * support the current MTU, including padding for header
620 * alignment and overruns.
621 */
43a3739d 622 efx->rx_dma_len = (efx->rx_prefix_size +
272baeeb
BH		 623 EFX_MAX_FRAME_LEN(efx->net_dev->mtu) +
624 efx->type->rx_buffer_padding);
85740cdf 625 rx_buf_len = (sizeof(struct efx_rx_page_state) +
2ec03014 626 efx->rx_ip_align + efx->rx_dma_len);
85740cdf 627 if (rx_buf_len <= PAGE_SIZE) {
e8c68c0a 628 efx->rx_scatter = efx->type->always_rx_scatter;
85740cdf 629 efx->rx_buffer_order = 0;
85740cdf 630 } else if (efx->type->can_rx_scatter) {
950c54df 631 BUILD_BUG_ON(EFX_RX_USR_BUF_SIZE % L1_CACHE_BYTES);
85740cdf 632 BUILD_BUG_ON(sizeof(struct efx_rx_page_state) +
950c54df
BH		 633 2 * ALIGN(NET_IP_ALIGN + EFX_RX_USR_BUF_SIZE,
634 EFX_RX_BUF_ALIGNMENT) >
635 PAGE_SIZE);
85740cdf
BH		 636 efx->rx_scatter = true;
637 efx->rx_dma_len = EFX_RX_USR_BUF_SIZE;
638 efx->rx_buffer_order = 0;
85740cdf
BH		 639 } else {
640 efx->rx_scatter = false;
641 efx->rx_buffer_order = get_order(rx_buf_len);
85740cdf
BH		 642 }
643
1648a23f
DP		 644 efx_rx_config_page_split(efx);
645 if (efx->rx_buffer_order)
646 netif_dbg(efx, drv, efx->net_dev,
647 "RX buf len=%u; page order=%u batch=%u\n",
648 efx->rx_dma_len, efx->rx_buffer_order,
649 efx->rx_pages_per_batch);
650 else
651 netif_dbg(efx, drv, efx->net_dev,
652 "RX buf len=%u step=%u bpp=%u; page batch=%u\n",
653 efx->rx_dma_len, efx->rx_page_buf_step,
654 efx->rx_bufs_per_page, efx->rx_pages_per_batch);
2768935a 655
ebfcd0fd
AR		 656 /* Restore previously fixed features in hw_features and remove
657 * features which are fixed now
658 */
659 efx->net_dev->hw_features |= efx->net_dev->features;
660 efx->net_dev->hw_features &= ~efx->fixed_features;
661 efx->net_dev->features |= efx->fixed_features;
662 if (efx->net_dev->features != old_features)
663 netdev_features_change(efx->net_dev);
664
e8c68c0a 665 /* RX filters may also have scatter-enabled flags */
85740cdf 666 if (efx->rx_scatter != old_rx_scatter)
add72477 667 efx->type->filter_update_rx_scatter(efx);
8ceee660 668
14bf718f
BH		 669 /* We must keep at least one descriptor in a TX ring empty.
670 * We could avoid this when the queue size does not exactly
671 * match the hardware ring size, but it's not that important.
672 * Therefore we stop the queue when one more skb might fill
673 * the ring completely. We wake it when half way back to
674 * empty.
675 */
676 efx->txq_stop_thresh = efx->txq_entries - efx_tx_max_skb_descs(efx);
677 efx->txq_wake_thresh = efx->txq_stop_thresh / 2;
678
8ceee660
BH		 679 /* Initialise the channels */
680 efx_for_each_channel(channel, efx) {
3881d8ab 681 efx_for_each_channel_tx_queue(tx_queue, channel) {
bc3c90a2 682 efx_init_tx_queue(tx_queue);
3881d8ab
AR		 683 atomic_inc(&efx->active_queues);
684 }
8ceee660 685
9f2cb71c 686 efx_for_each_channel_rx_queue(rx_queue, channel) {
bc3c90a2 687 efx_init_rx_queue(rx_queue);
3881d8ab 688 atomic_inc(&efx->active_queues);
cce28794
JC		 689 efx_stop_eventq(channel);
690 efx_fast_push_rx_descriptors(rx_queue, false);
691 efx_start_eventq(channel);
9f2cb71c 692 }
8ceee660 693
85740cdf 694 WARN_ON(channel->rx_pkt_n_frags);
8ceee660 695 }
8ceee660 696
2ea4dc28
AR		 697 efx_ptp_start_datapath(efx);
698
9f2cb71c
BH		 699 if (netif_device_present(efx->net_dev))
700 netif_tx_wake_all_queues(efx->net_dev);
8ceee660
BH		 701}
702
9f2cb71c 703static void efx_stop_datapath(struct efx_nic *efx)
8ceee660
BH		 704{
705 struct efx_channel *channel;
706 struct efx_tx_queue *tx_queue;
707 struct efx_rx_queue *rx_queue;
6bc5d3a9 708 int rc;
8ceee660
BH		 709
710 EFX_ASSERT_RESET_SERIALISED(efx);
711 BUG_ON(efx->port_enabled);
712
2ea4dc28
AR		 713 efx_ptp_stop_datapath(efx);
714
d8aec745
BH		 715 /* Stop RX refill */
716 efx_for_each_channel(channel, efx) {
717 efx_for_each_channel_rx_queue(rx_queue, channel)
718 rx_queue->refill_enabled = false;
719 }
720
8ceee660 721 efx_for_each_channel(channel, efx) {
9f2cb71c
BH		 722 /* RX packet processing is pipelined, so wait for the
723 * NAPI handler to complete. At least event queue 0
724 * might be kept active by non-data events, so don't
725 * use napi_synchronize() but actually disable NAPI
726 * temporarily.
727 */
728 if (efx_channel_has_rx_queue(channel)) {
729 efx_stop_eventq(channel);
730 efx_start_eventq(channel);
731 }
e42c3d85 732 }
8ceee660 733
e42c3d85 734 rc = efx->type->fini_dmaq(efx);
5a6681e2 735 if (rc) {
e42c3d85
BH		 736 netif_err(efx, drv, efx->net_dev, "failed to flush queues\n");
737 } else {
738 netif_dbg(efx, drv, efx->net_dev,
739 "successfully flushed all queues\n");
740 }
741
742 efx_for_each_channel(channel, efx) {
8ceee660
BH		 743 efx_for_each_channel_rx_queue(rx_queue, channel)
744 efx_fini_rx_queue(rx_queue);
94b274bf 745 efx_for_each_possible_channel_tx_queue(tx_queue, channel)
8ceee660 746 efx_fini_tx_queue(tx_queue);
8ceee660
BH		 747 }
748}
749
750static void efx_remove_channel(struct efx_channel *channel)
751{
752 struct efx_tx_queue *tx_queue;
753 struct efx_rx_queue *rx_queue;
754
62776d03
BH		 755 netif_dbg(channel->efx, drv, channel->efx->net_dev,
756 "destroy chan %d\n", channel->channel);
8ceee660
BH		 757
758 efx_for_each_channel_rx_queue(rx_queue, channel)
759 efx_remove_rx_queue(rx_queue);
94b274bf 760 efx_for_each_possible_channel_tx_queue(tx_queue, channel)
8ceee660
BH		 761 efx_remove_tx_queue(tx_queue);
762 efx_remove_eventq(channel);
c31e5f9f 763 channel->type->post_remove(channel);
8ceee660
BH		 764}
765
4642610c
BH		 766static void efx_remove_channels(struct efx_nic *efx)
767{
768 struct efx_channel *channel;
769
770 efx_for_each_channel(channel, efx)
771 efx_remove_channel(channel);
772}
773
774int
775efx_realloc_channels(struct efx_nic *efx, u32 rxq_entries, u32 txq_entries)
776{
777 struct efx_channel *other_channel[EFX_MAX_CHANNELS], *channel;
778 u32 old_rxq_entries, old_txq_entries;
7f967c01 779 unsigned i, next_buffer_table = 0;
261e4d96 780 int rc, rc2;
8b7325b4
BH		 781
782 rc = efx_check_disabled(efx);
783 if (rc)
784 return rc;
7f967c01
BH		 785
786 /* Not all channels should be reallocated. We must avoid
787 * reallocating their buffer table entries.
788 */
789 efx_for_each_channel(channel, efx) {
790 struct efx_rx_queue *rx_queue;
791 struct efx_tx_queue *tx_queue;
792
793 if (channel->type->copy)
794 continue;
795 next_buffer_table = max(next_buffer_table,
796 channel->eventq.index +
797 channel->eventq.entries);
798 efx_for_each_channel_rx_queue(rx_queue, channel)
799 next_buffer_table = max(next_buffer_table,
800 rx_queue->rxd.index +
801 rx_queue->rxd.entries);
802 efx_for_each_channel_tx_queue(tx_queue, channel)
803 next_buffer_table = max(next_buffer_table,
804 tx_queue->txd.index +
805 tx_queue->txd.entries);
806 }
4642610c 807
29c69a48 808 efx_device_detach_sync(efx);
4642610c 809 efx_stop_all(efx);
d8291187 810 efx_soft_disable_interrupts(efx);
4642610c 811
7f967c01 812 /* Clone channels (where possible) */
4642610c
BH		 813 memset(other_channel, 0, sizeof(other_channel));
814 for (i = 0; i < efx->n_channels; i++) {
7f967c01
BH		 815 channel = efx->channel[i];
816 if (channel->type->copy)
817 channel = channel->type->copy(channel);
4642610c
BH		 818 if (!channel) {
819 rc = -ENOMEM;
820 goto out;
821 }
822 other_channel[i] = channel;
823 }
824
825 /* Swap entry counts and channel pointers */
826 old_rxq_entries = efx->rxq_entries;
827 old_txq_entries = efx->txq_entries;
828 efx->rxq_entries = rxq_entries;
829 efx->txq_entries = txq_entries;
830 for (i = 0; i < efx->n_channels; i++) {
831 channel = efx->channel[i];
832 efx->channel[i] = other_channel[i];
833 other_channel[i] = channel;
834 }
835
7f967c01
BH		 836 /* Restart buffer table allocation */
837 efx->next_buffer_table = next_buffer_table;
e8f14992 838
e8f14992 839 for (i = 0; i < efx->n_channels; i++) {
7f967c01
BH		 840 channel = efx->channel[i];
841 if (!channel->type->copy)
842 continue;
843 rc = efx_probe_channel(channel);
844 if (rc)
845 goto rollback;
846 efx_init_napi_channel(efx->channel[i]);
e8f14992 847 }
7f967c01 848
4642610c 849out:
7f967c01
BH		 850 /* Destroy unused channel structures */
851 for (i = 0; i < efx->n_channels; i++) {
852 channel = other_channel[i];
853 if (channel && channel->type->copy) {
854 efx_fini_napi_channel(channel);
855 efx_remove_channel(channel);
856 kfree(channel);
857 }
858 }
4642610c 859
261e4d96
JC		 860 rc2 = efx_soft_enable_interrupts(efx);
861 if (rc2) {
862 rc = rc ? rc : rc2;
863 netif_err(efx, drv, efx->net_dev,
864 "unable to restart interrupts on channel reallocation\n");
865 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
866 } else {
867 efx_start_all(efx);
868 netif_device_attach(efx->net_dev);
869 }
4642610c
BH		 870 return rc;
871
872rollback:
873 /* Swap back */
874 efx->rxq_entries = old_rxq_entries;
875 efx->txq_entries = old_txq_entries;
876 for (i = 0; i < efx->n_channels; i++) {
877 channel = efx->channel[i];
878 efx->channel[i] = other_channel[i];
879 other_channel[i] = channel;
880 }
881 goto out;
882}
883
90d683af 884void efx_schedule_slow_fill(struct efx_rx_queue *rx_queue)
8ceee660 885{
90d683af 886 mod_timer(&rx_queue->slow_fill, jiffies + msecs_to_jiffies(100));
8ceee660
BH		 887}
888
7f967c01
BH		 889static const struct efx_channel_type efx_default_channel_type = {
890 .pre_probe = efx_channel_dummy_op_int,
c31e5f9f 891 .post_remove = efx_channel_dummy_op_void,
7f967c01
BH		 892 .get_name = efx_get_channel_name,
893 .copy = efx_copy_channel,
894 .keep_eventq = false,
895};
896
897int efx_channel_dummy_op_int(struct efx_channel *channel)
898{
899 return 0;
900}
901
c31e5f9f
SH		 902void efx_channel_dummy_op_void(struct efx_channel *channel)
903{
904}
905
8ceee660
BH		 906/**************************************************************************
907 *
908 * Port handling
909 *
910 **************************************************************************/
911
912/* This ensures that the kernel is kept informed (via
913 * netif_carrier_on/off) of the link status, and also maintains the
914 * link status's stop on the port's TX queue.
915 */
fdaa9aed 916void efx_link_status_changed(struct efx_nic *efx)
8ceee660 917{
eb50c0d6
BH		 918 struct efx_link_state *link_state = &efx->link_state;
919
8ceee660
BH		 920 /* SFC Bug 5356: A net_dev notifier is registered, so we must ensure
921 * that no events are triggered between unregister_netdev() and the
922 * driver unloading. A more general condition is that NETDEV_CHANGE
923 * can only be generated between NETDEV_UP and NETDEV_DOWN */
924 if (!netif_running(efx->net_dev))
925 return;
926
eb50c0d6 927 if (link_state->up != netif_carrier_ok(efx->net_dev)) {
8ceee660
BH		 928 efx->n_link_state_changes++;
929
eb50c0d6 930 if (link_state->up)
8ceee660
BH		 931 netif_carrier_on(efx->net_dev);
932 else
933 netif_carrier_off(efx->net_dev);
934 }
935
936 /* Status message for kernel log */
2aa9ef11 937 if (link_state->up)
62776d03 938 netif_info(efx, link, efx->net_dev,
964e6135 939 "link up at %uMbps %s-duplex (MTU %d)\n",
62776d03 940 link_state->speed, link_state->fd ? "full" : "half",
964e6135 941 efx->net_dev->mtu);
2aa9ef11 942 else
62776d03 943 netif_info(efx, link, efx->net_dev, "link down\n");
8ceee660
BH		 944}
945
d3245b28
BH		 946void efx_link_set_advertising(struct efx_nic *efx, u32 advertising)
947{
948 efx->link_advertising = advertising;
949 if (advertising) {
950 if (advertising & ADVERTISED_Pause)
951 efx->wanted_fc |= (EFX_FC_TX | EFX_FC_RX);
952 else
953 efx->wanted_fc &= ~(EFX_FC_TX | EFX_FC_RX);
954 if (advertising & ADVERTISED_Asym_Pause)
955 efx->wanted_fc ^= EFX_FC_TX;
956 }
957}
958
b5626946 959void efx_link_set_wanted_fc(struct efx_nic *efx, u8 wanted_fc)
d3245b28
BH		 960{
961 efx->wanted_fc = wanted_fc;
962 if (efx->link_advertising) {
963 if (wanted_fc & EFX_FC_RX)
964 efx->link_advertising |= (ADVERTISED_Pause |
965 ADVERTISED_Asym_Pause);
966 else
967 efx->link_advertising &= ~(ADVERTISED_Pause |
968 ADVERTISED_Asym_Pause);
969 if (wanted_fc & EFX_FC_TX)
970 efx->link_advertising ^= ADVERTISED_Asym_Pause;
971 }
972}
973
115122af
BH		 974static void efx_fini_port(struct efx_nic *efx);
975
0d322413
EC		 976/* We assume that efx->type->reconfigure_mac will always try to sync RX
977 * filters and therefore needs to read-lock the filter table against freeing
978 */
979void efx_mac_reconfigure(struct efx_nic *efx)
980{
981 down_read(&efx->filter_sem);
982 efx->type->reconfigure_mac(efx);
983 up_read(&efx->filter_sem);
984}
985
d3245b28
BH		 986/* Push loopback/power/transmit disable settings to the PHY, and reconfigure
987 * the MAC appropriately. All other PHY configuration changes are pushed
988 * through phy_op->set_settings(), and pushed asynchronously to the MAC
989 * through efx_monitor().
990 *
991 * Callers must hold the mac_lock
992 */
993int __efx_reconfigure_port(struct efx_nic *efx)
8ceee660 994{
d3245b28
BH		 995 enum efx_phy_mode phy_mode;
996 int rc;
8ceee660 997
d3245b28 998 WARN_ON(!mutex_is_locked(&efx->mac_lock));
8ceee660 999
d3245b28
BH		 1000 /* Disable PHY transmit in mac level loopbacks */
1001 phy_mode = efx->phy_mode;
177dfcd8
BH		 1002 if (LOOPBACK_INTERNAL(efx))
1003 efx->phy_mode |= PHY_MODE_TX_DISABLED;
1004 else
1005 efx->phy_mode &= ~PHY_MODE_TX_DISABLED;
177dfcd8 1006
d3245b28 1007 rc = efx->type->reconfigure_port(efx);
8ceee660 1008
d3245b28
BH		 1009 if (rc)
1010 efx->phy_mode = phy_mode;
177dfcd8 1011
d3245b28 1012 return rc;
8ceee660
BH		 1013}
1014
1015/* Reinitialise the MAC to pick up new PHY settings, even if the port is
1016 * disabled. */
d3245b28 1017int efx_reconfigure_port(struct efx_nic *efx)
8ceee660 1018{
d3245b28
BH		 1019 int rc;
1020
8ceee660
BH		 1021 EFX_ASSERT_RESET_SERIALISED(efx);
1022
1023 mutex_lock(&efx->mac_lock);
d3245b28 1024 rc = __efx_reconfigure_port(efx);
8ceee660 1025 mutex_unlock(&efx->mac_lock);
d3245b28
BH		 1026
1027 return rc;
8ceee660
BH		 1028}
1029
8be4f3e6
BH		 1030/* Asynchronous work item for changing MAC promiscuity and multicast
1031 * hash. Avoid a drain/rx_ingress enable by reconfiguring the current
1032 * MAC directly. */
766ca0fa
BH		 1033static void efx_mac_work(struct work_struct *data)
1034{
1035 struct efx_nic *efx = container_of(data, struct efx_nic, mac_work);
1036
1037 mutex_lock(&efx->mac_lock);
30b81cda 1038 if (efx->port_enabled)
0d322413 1039 efx_mac_reconfigure(efx);
766ca0fa
BH		 1040 mutex_unlock(&efx->mac_lock);
1041}
1042
8ceee660
BH		 1043static int efx_probe_port(struct efx_nic *efx)
1044{
1045 int rc;
1046
62776d03 1047 netif_dbg(efx, probe, efx->net_dev, "create port\n");
8ceee660 1048
ff3b00a0
SH		 1049 if (phy_flash_cfg)
1050 efx->phy_mode = PHY_MODE_SPECIAL;
1051
ef2b90ee
BH		 1052 /* Connect up MAC/PHY operations table */
1053 rc = efx->type->probe_port(efx);
8ceee660 1054 if (rc)
e42de262 1055 return rc;
8ceee660 1056
e332bcb3 1057 /* Initialise MAC address to permanent address */
cd84ff4d 1058 ether_addr_copy(efx->net_dev->dev_addr, efx->net_dev->perm_addr);
8ceee660
BH		 1059
1060 return 0;
8ceee660
BH		 1061}
1062
1063static int efx_init_port(struct efx_nic *efx)
1064{
1065 int rc;
1066
62776d03 1067 netif_dbg(efx, drv, efx->net_dev, "init port\n");
8ceee660 1068
1dfc5cea
BH		 1069 mutex_lock(&efx->mac_lock);
1070
177dfcd8 1071 rc = efx->phy_op->init(efx);
8ceee660 1072 if (rc)
1dfc5cea 1073 goto fail1;
8ceee660 1074
dc8cfa55 1075 efx->port_initialized = true;
1dfc5cea 1076
d3245b28
BH		 1077 /* Reconfigure the MAC before creating dma queues (required for
1078 * Falcon/A1 where RX_INGR_EN/TX_DRAIN_EN isn't supported) */
0d322413 1079 efx_mac_reconfigure(efx);
d3245b28
BH		 1080
1081 /* Ensure the PHY advertises the correct flow control settings */
1082 rc = efx->phy_op->reconfigure(efx);
267d9d73 1083 if (rc && rc != -EPERM)
d3245b28
BH		 1084 goto fail2;
1085
1dfc5cea 1086 mutex_unlock(&efx->mac_lock);
8ceee660 1087 return 0;
177dfcd8 1088
1dfc5cea 1089fail2:
177dfcd8 1090 efx->phy_op->fini(efx);
1dfc5cea
BH		 1091fail1:
1092 mutex_unlock(&efx->mac_lock);
177dfcd8 1093 return rc;
8ceee660
BH		 1094}
1095
8ceee660
BH		 1096static void efx_start_port(struct efx_nic *efx)
1097{
62776d03 1098 netif_dbg(efx, ifup, efx->net_dev, "start port\n");
8ceee660
BH		 1099 BUG_ON(efx->port_enabled);
1100
1101 mutex_lock(&efx->mac_lock);
dc8cfa55 1102 efx->port_enabled = true;
8be4f3e6 1103
d615c039 1104 /* Ensure MAC ingress/egress is enabled */
0d322413 1105 efx_mac_reconfigure(efx);
8be4f3e6 1106
8ceee660
BH		 1107 mutex_unlock(&efx->mac_lock);
1108}
1109
d615c039
BH		 1110/* Cancel work for MAC reconfiguration, periodic hardware monitoring
1111 * and the async self-test, wait for them to finish and prevent them
1112 * being scheduled again. This doesn't cover online resets, which
1113 * should only be cancelled when removing the device.
1114 */
8ceee660
BH		 1115static void efx_stop_port(struct efx_nic *efx)
1116{
62776d03 1117 netif_dbg(efx, ifdown, efx->net_dev, "stop port\n");
8ceee660 1118
d615c039
BH		 1119 EFX_ASSERT_RESET_SERIALISED(efx);
1120
8ceee660 1121 mutex_lock(&efx->mac_lock);
dc8cfa55 1122 efx->port_enabled = false;
8ceee660
BH		 1123 mutex_unlock(&efx->mac_lock);
1124
1125 /* Serialise against efx_set_multicast_list() */
73ba7b68
BH		 1126 netif_addr_lock_bh(efx->net_dev);
1127 netif_addr_unlock_bh(efx->net_dev);
d615c039
BH		 1128
1129 cancel_delayed_work_sync(&efx->monitor_work);
1130 efx_selftest_async_cancel(efx);
1131 cancel_work_sync(&efx->mac_work);
8ceee660
BH		 1132}
1133
1134static void efx_fini_port(struct efx_nic *efx)
1135{
62776d03 1136 netif_dbg(efx, drv, efx->net_dev, "shut down port\n");
8ceee660
BH		 1137
1138 if (!efx->port_initialized)
1139 return;
1140
177dfcd8 1141 efx->phy_op->fini(efx);
dc8cfa55 1142 efx->port_initialized = false;
8ceee660 1143
eb50c0d6 1144 efx->link_state.up = false;
8ceee660
BH		 1145 efx_link_status_changed(efx);
1146}
1147
1148static void efx_remove_port(struct efx_nic *efx)
1149{
62776d03 1150 netif_dbg(efx, drv, efx->net_dev, "destroying port\n");
8ceee660 1151
ef2b90ee 1152 efx->type->remove_port(efx);
8ceee660
BH		 1153}
1154
1155/**************************************************************************
1156 *
1157 * NIC handling
1158 *
1159 **************************************************************************/
1160
0bcf4a64
BH		 1161static LIST_HEAD(efx_primary_list);
1162static LIST_HEAD(efx_unassociated_list);
1163
1164static bool efx_same_controller(struct efx_nic *left, struct efx_nic *right)
1165{
1166 return left->type == right->type &&
1167 left->vpd_sn && right->vpd_sn &&
1168 !strcmp(left->vpd_sn, right->vpd_sn);
1169}
1170
1171static void efx_associate(struct efx_nic *efx)
1172{
1173 struct efx_nic *other, *next;
1174
1175 if (efx->primary == efx) {
1176 /* Adding primary function; look for secondaries */
1177
1178 netif_dbg(efx, probe, efx->net_dev, "adding to primary list\n");
1179 list_add_tail(&efx->node, &efx_primary_list);
1180
1181 list_for_each_entry_safe(other, next, &efx_unassociated_list,
1182 node) {
1183 if (efx_same_controller(efx, other)) {
1184 list_del(&other->node);
1185 netif_dbg(other, probe, other->net_dev,
1186 "moving to secondary list of %s %s\n",
1187 pci_name(efx->pci_dev),
1188 efx->net_dev->name);
1189 list_add_tail(&other->node,
1190 &efx->secondary_list);
1191 other->primary = efx;
1192 }
1193 }
1194 } else {
1195 /* Adding secondary function; look for primary */
1196
1197 list_for_each_entry(other, &efx_primary_list, node) {
1198 if (efx_same_controller(efx, other)) {
1199 netif_dbg(efx, probe, efx->net_dev,
1200 "adding to secondary list of %s %s\n",
1201 pci_name(other->pci_dev),
1202 other->net_dev->name);
1203 list_add_tail(&efx->node,
1204 &other->secondary_list);
1205 efx->primary = other;
1206 return;
1207 }
1208 }
1209
1210 netif_dbg(efx, probe, efx->net_dev,
1211 "adding to unassociated list\n");
1212 list_add_tail(&efx->node, &efx_unassociated_list);
1213 }
1214}
1215
1216static void efx_dissociate(struct efx_nic *efx)
1217{
1218 struct efx_nic *other, *next;
1219
1220 list_del(&efx->node);
1221 efx->primary = NULL;
1222
1223 list_for_each_entry_safe(other, next, &efx->secondary_list, node) {
1224 list_del(&other->node);
1225 netif_dbg(other, probe, other->net_dev,
1226 "moving to unassociated list\n");
1227 list_add_tail(&other->node, &efx_unassociated_list);
1228 other->primary = NULL;
1229 }
1230}
1231
8ceee660
BH		 1232/* This configures the PCI device to enable I/O and DMA. */
1233static int efx_init_io(struct efx_nic *efx)
1234{
1235 struct pci_dev *pci_dev = efx->pci_dev;
1236 dma_addr_t dma_mask = efx->type->max_dma_mask;
b105798f 1237 unsigned int mem_map_size = efx->type->mem_map_size(efx);
02246a7f 1238 int rc, bar;
8ceee660 1239
62776d03 1240 netif_dbg(efx, probe, efx->net_dev, "initialising I/O\n");
8ceee660 1241
02246a7f
SS		 1242 bar = efx->type->mem_bar;
1243
8ceee660
BH		 1244 rc = pci_enable_device(pci_dev);
1245 if (rc) {
62776d03
BH		 1246 netif_err(efx, probe, efx->net_dev,
1247 "failed to enable PCI device\n");
8ceee660
BH		 1248 goto fail1;
1249 }
1250
1251 pci_set_master(pci_dev);
1252
1253 /* Set the PCI DMA mask. Try all possibilities from our
1254 * genuine mask down to 32 bits, because some architectures
1255 * (e.g. x86_64 with iommu_sac_force set) will allow 40 bit
1256 * masks event though they reject 46 bit masks.
1257 */
1258 while (dma_mask > 0x7fffffffUL) {
8722b8fb
CH		 1259 rc = dma_set_mask_and_coherent(&pci_dev->dev, dma_mask);
1260 if (rc == 0)
1261 break;
8ceee660
BH		 1262 dma_mask >>= 1;
1263 }
1264 if (rc) {
62776d03
BH		 1265 netif_err(efx, probe, efx->net_dev,
1266 "could not find a suitable DMA mask\n");
8ceee660
BH		 1267 goto fail2;
1268 }
62776d03
BH		 1269 netif_dbg(efx, probe, efx->net_dev,
1270 "using DMA mask %llx\n", (unsigned long long) dma_mask);
8ceee660 1271
02246a7f
SS		 1272 efx->membase_phys = pci_resource_start(efx->pci_dev, bar);
1273 rc = pci_request_region(pci_dev, bar, "sfc");
8ceee660 1274 if (rc) {
62776d03
BH		 1275 netif_err(efx, probe, efx->net_dev,
1276 "request for memory BAR failed\n");
8ceee660
BH		 1277 rc = -EIO;
1278 goto fail3;
1279 }
b105798f 1280 efx->membase = ioremap_nocache(efx->membase_phys, mem_map_size);
8ceee660 1281 if (!efx->membase) {
62776d03
BH		 1282 netif_err(efx, probe, efx->net_dev,
1283 "could not map memory BAR at %llx+%x\n",
b105798f 1284 (unsigned long long)efx->membase_phys, mem_map_size);
8ceee660
BH		 1285 rc = -ENOMEM;
1286 goto fail4;
1287 }
62776d03
BH		 1288 netif_dbg(efx, probe, efx->net_dev,
1289 "memory BAR at %llx+%x (virtual %p)\n",
b105798f
BH		 1290 (unsigned long long)efx->membase_phys, mem_map_size,
1291 efx->membase);
8ceee660
BH		 1292
1293 return 0;
1294
1295 fail4:
02246a7f 1296 pci_release_region(efx->pci_dev, bar);
8ceee660 1297 fail3:
2c118e0f 1298 efx->membase_phys = 0;
8ceee660
BH		 1299 fail2:
1300 pci_disable_device(efx->pci_dev);
1301 fail1:
1302 return rc;
1303}
1304
1305static void efx_fini_io(struct efx_nic *efx)
1306{
02246a7f
SS		 1307 int bar;
1308
62776d03 1309 netif_dbg(efx, drv, efx->net_dev, "shutting down I/O\n");
8ceee660
BH		 1310
1311 if (efx->membase) {
1312 iounmap(efx->membase);
1313 efx->membase = NULL;
1314 }
1315
1316 if (efx->membase_phys) {
02246a7f
SS		 1317 bar = efx->type->mem_bar;
1318 pci_release_region(efx->pci_dev, bar);
2c118e0f 1319 efx->membase_phys = 0;
8ceee660
BH		 1320 }
1321
6598dad2
DP		 1322 /* Don't disable bus-mastering if VFs are assigned */
1323 if (!pci_vfs_assigned(efx->pci_dev))
1324 pci_disable_device(efx->pci_dev);
8ceee660
BH		 1325}
1326
267c0157
JC		 1327void efx_set_default_rx_indir_table(struct efx_nic *efx)
1328{
1329 size_t i;
1330
1331 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); i++)
1332 efx->rx_indir_table[i] =
1333 ethtool_rxfh_indir_default(i, efx->rss_spread);
8ceee660
BH		 1334}
1335
a9a52506 1336static unsigned int efx_wanted_parallelism(struct efx_nic *efx)
46123d04 1337{
cdb08f8f 1338 cpumask_var_t thread_mask;
a16e5b24 1339 unsigned int count;
46123d04 1340 int cpu;
5b874e25 1341
cd2d5b52
BH		 1342 if (rss_cpus) {
1343 count = rss_cpus;
1344 } else {
1345 if (unlikely(!zalloc_cpumask_var(&thread_mask, GFP_KERNEL))) {
1346 netif_warn(efx, probe, efx->net_dev,
1347 "RSS disabled due to allocation failure\n");
1348 return 1;
1349 }
46123d04 1350
cd2d5b52
BH		 1351 count = 0;
1352 for_each_online_cpu(cpu) {
1353 if (!cpumask_test_cpu(cpu, thread_mask)) {
1354 ++count;
1355 cpumask_or(thread_mask, thread_mask,
06931e62 1356 topology_sibling_cpumask(cpu));
cd2d5b52
BH		 1357 }
1358 }
1359
1360 free_cpumask_var(thread_mask);
2f8975fb
RR		 1361 }
1362
cd2d5b52
BH		 1363 /* If RSS is requested for the PF *and* VFs then we can't write RSS
1364 * table entries that are inaccessible to VFs
1365 */
7fa8d547
SS		 1366#ifdef CONFIG_SFC_SRIOV
1367 if (efx->type->sriov_wanted) {
1368 if (efx->type->sriov_wanted(efx) && efx_vf_size(efx) > 1 &&
1369 count > efx_vf_size(efx)) {
1370 netif_warn(efx, probe, efx->net_dev,
1371 "Reducing number of RSS channels from %u to %u for "
1372 "VF support. Increase vf-msix-limit to use more "
1373 "channels on the PF.\n",
1374 count, efx_vf_size(efx));
1375 count = efx_vf_size(efx);
1376 }
46123d04 1377 }
7fa8d547 1378#endif
46123d04
BH		 1379
1380 return count;
1381}
1382
1383/* Probe the number and type of interrupts we are able to obtain, and
1384 * the resulting numbers of channels and RX queues.
1385 */
64d8ad6d 1386static int efx_probe_interrupts(struct efx_nic *efx)
8ceee660 1387{
7f967c01
BH		 1388 unsigned int extra_channels = 0;
1389 unsigned int i, j;
a16e5b24 1390 int rc;
8ceee660 1391
7f967c01
BH		 1392 for (i = 0; i < EFX_MAX_EXTRA_CHANNELS; i++)
1393 if (efx->extra_channel_type[i])
1394 ++extra_channels;
1395
8ceee660 1396 if (efx->interrupt_mode == EFX_INT_MODE_MSIX) {
46123d04 1397 struct msix_entry xentries[EFX_MAX_CHANNELS];
a16e5b24 1398 unsigned int n_channels;
aa6ef27e 1399
a9a52506 1400 n_channels = efx_wanted_parallelism(efx);
b0fbdae1 1401 if (efx_separate_tx_channels)
a4900ac9 1402 n_channels *= 2;
7f967c01 1403 n_channels += extra_channels;
b105798f 1404 n_channels = min(n_channels, efx->max_channels);
8ceee660 1405
a4900ac9 1406 for (i = 0; i < n_channels; i++)
8ceee660 1407 xentries[i].entry = i;
184603d8
AG		 1408 rc = pci_enable_msix_range(efx->pci_dev,
1409 xentries, 1, n_channels);
1410 if (rc < 0) {
1411 /* Fall back to single channel MSI */
1412 efx->interrupt_mode = EFX_INT_MODE_MSI;
1413 netif_err(efx, drv, efx->net_dev,
1414 "could not enable MSI-X\n");
1415 } else if (rc < n_channels) {
62776d03
BH		 1416 netif_err(efx, drv, efx->net_dev,
1417 "WARNING: Insufficient MSI-X vectors"
a16e5b24 1418 " available (%d < %u).\n", rc, n_channels);
62776d03
BH		 1419 netif_err(efx, drv, efx->net_dev,
1420 "WARNING: Performance may be reduced.\n");
a4900ac9 1421 n_channels = rc;
8ceee660
BH		 1422 }
1423
184603d8 1424 if (rc > 0) {
a4900ac9 1425 efx->n_channels = n_channels;
7f967c01
BH		 1426 if (n_channels > extra_channels)
1427 n_channels -= extra_channels;
b0fbdae1
SS		 1428 if (efx_separate_tx_channels) {
1429 efx->n_tx_channels = min(max(n_channels / 2,
1430 1U),
1431 efx->max_tx_channels);
7f967c01
BH		 1432 efx->n_rx_channels = max(n_channels -
1433 efx->n_tx_channels,
1434 1U);
a4900ac9 1435 } else {
b0fbdae1
SS		 1436 efx->n_tx_channels = min(n_channels,
1437 efx->max_tx_channels);
7f967c01 1438 efx->n_rx_channels = n_channels;
a4900ac9 1439 }
7f967c01 1440 for (i = 0; i < efx->n_channels; i++)
f7d12cdc
BH		 1441 efx_get_channel(efx, i)->irq =
1442 xentries[i].vector;
8ceee660
BH		 1443 }
1444 }
1445
1446 /* Try single interrupt MSI */
1447 if (efx->interrupt_mode == EFX_INT_MODE_MSI) {
28b581ab 1448 efx->n_channels = 1;
a4900ac9
BH		 1449 efx->n_rx_channels = 1;
1450 efx->n_tx_channels = 1;
8ceee660
BH		 1451 rc = pci_enable_msi(efx->pci_dev);
1452 if (rc == 0) {
f7d12cdc 1453 efx_get_channel(efx, 0)->irq = efx->pci_dev->irq;
8ceee660 1454 } else {
62776d03
BH		 1455 netif_err(efx, drv, efx->net_dev,
1456 "could not enable MSI\n");
8ceee660
BH		 1457 efx->interrupt_mode = EFX_INT_MODE_LEGACY;
1458 }
1459 }
1460
1461 /* Assume legacy interrupts */
1462 if (efx->interrupt_mode == EFX_INT_MODE_LEGACY) {
b0fbdae1 1463 efx->n_channels = 1 + (efx_separate_tx_channels ? 1 : 0);
a4900ac9
BH		 1464 efx->n_rx_channels = 1;
1465 efx->n_tx_channels = 1;
8ceee660
BH		 1466 efx->legacy_irq = efx->pci_dev->irq;
1467 }
64d8ad6d 1468
7f967c01
BH		 1469 /* Assign extra channels if possible */
1470 j = efx->n_channels;
1471 for (i = 0; i < EFX_MAX_EXTRA_CHANNELS; i++) {
1472 if (!efx->extra_channel_type[i])
1473 continue;
1474 if (efx->interrupt_mode != EFX_INT_MODE_MSIX ||
1475 efx->n_channels <= extra_channels) {
1476 efx->extra_channel_type[i]->handle_no_channel(efx);
1477 } else {
1478 --j;
1479 efx_get_channel(efx, j)->type =
1480 efx->extra_channel_type[i];
1481 }
1482 }
1483
cd2d5b52 1484 /* RSS might be usable on VFs even if it is disabled on the PF */
7fa8d547
SS		 1485#ifdef CONFIG_SFC_SRIOV
1486 if (efx->type->sriov_wanted) {
1487 efx->rss_spread = ((efx->n_rx_channels > 1 ||
1488 !efx->type->sriov_wanted(efx)) ?
1489 efx->n_rx_channels : efx_vf_size(efx));
1490 return 0;
1491 }
1492#endif
1493 efx->rss_spread = efx->n_rx_channels;
cd2d5b52 1494
64d8ad6d 1495 return 0;
8ceee660
BH		 1496}
1497
261e4d96 1498static int efx_soft_enable_interrupts(struct efx_nic *efx)
9f2cb71c 1499{
261e4d96
JC		 1500 struct efx_channel *channel, *end_channel;
1501 int rc;
9f2cb71c 1502
8b7325b4
BH		 1503 BUG_ON(efx->state == STATE_DISABLED);
1504
d8291187
BH		 1505 efx->irq_soft_enabled = true;
1506 smp_wmb();
9f2cb71c
BH		 1507
1508 efx_for_each_channel(channel, efx) {
261e4d96
JC		 1509 if (!channel->type->keep_eventq) {
1510 rc = efx_init_eventq(channel);
1511 if (rc)
1512 goto fail;
1513 }
9f2cb71c
BH		 1514 efx_start_eventq(channel);
1515 }
1516
1517 efx_mcdi_mode_event(efx);
261e4d96
JC		 1518
1519 return 0;
1520fail:
1521 end_channel = channel;
1522 efx_for_each_channel(channel, efx) {
1523 if (channel == end_channel)
1524 break;
1525 efx_stop_eventq(channel);
1526 if (!channel->type->keep_eventq)
1527 efx_fini_eventq(channel);
1528 }
1529
1530 return rc;
9f2cb71c
BH		 1531}
1532
d8291187 1533static void efx_soft_disable_interrupts(struct efx_nic *efx)
9f2cb71c
BH		 1534{
1535 struct efx_channel *channel;
1536
8b7325b4
BH		 1537 if (efx->state == STATE_DISABLED)
1538 return;
1539
9f2cb71c
BH		 1540 efx_mcdi_mode_poll(efx);
1541
d8291187
BH		 1542 efx->irq_soft_enabled = false;
1543 smp_wmb();
1544
1545 if (efx->legacy_irq)
9f2cb71c 1546 synchronize_irq(efx->legacy_irq);
9f2cb71c
BH		 1547
1548 efx_for_each_channel(channel, efx) {
1549 if (channel->irq)
1550 synchronize_irq(channel->irq);
1551
1552 efx_stop_eventq(channel);
d8291187 1553 if (!channel->type->keep_eventq)
7f967c01 1554 efx_fini_eventq(channel);
9f2cb71c 1555 }
cade715f
BH		 1556
1557 /* Flush the asynchronous MCDI request queue */
1558 efx_mcdi_flush_async(efx);
9f2cb71c
BH		 1559}
1560
261e4d96 1561static int efx_enable_interrupts(struct efx_nic *efx)
d8291187 1562{
261e4d96
JC		 1563 struct efx_channel *channel, *end_channel;
1564 int rc;
d8291187
BH		 1565
1566 BUG_ON(efx->state == STATE_DISABLED);
1567
1568 if (efx->eeh_disabled_legacy_irq) {
1569 enable_irq(efx->legacy_irq);
1570 efx->eeh_disabled_legacy_irq = false;
1571 }
1572
86094f7f 1573 efx->type->irq_enable_master(efx);
d8291187
BH		 1574
1575 efx_for_each_channel(channel, efx) {
261e4d96
JC		 1576 if (channel->type->keep_eventq) {
1577 rc = efx_init_eventq(channel);
1578 if (rc)
1579 goto fail;
1580 }
1581 }
1582
1583 rc = efx_soft_enable_interrupts(efx);
1584 if (rc)
1585 goto fail;
1586
1587 return 0;
1588
1589fail:
1590 end_channel = channel;
1591 efx_for_each_channel(channel, efx) {
1592 if (channel == end_channel)
1593 break;
d8291187 1594 if (channel->type->keep_eventq)
261e4d96 1595 efx_fini_eventq(channel);
d8291187
BH		 1596 }
1597
261e4d96
JC		 1598 efx->type->irq_disable_non_ev(efx);
1599
1600 return rc;
d8291187
BH		 1601}
1602
1603static void efx_disable_interrupts(struct efx_nic *efx)
1604{
1605 struct efx_channel *channel;
1606
1607 efx_soft_disable_interrupts(efx);
1608
1609 efx_for_each_channel(channel, efx) {
1610 if (channel->type->keep_eventq)
1611 efx_fini_eventq(channel);
1612 }
1613
86094f7f 1614 efx->type->irq_disable_non_ev(efx);
d8291187
BH		 1615}
1616
8ceee660
BH		 1617static void efx_remove_interrupts(struct efx_nic *efx)
1618{
1619 struct efx_channel *channel;
1620
1621 /* Remove MSI/MSI-X interrupts */
64ee3120 1622 efx_for_each_channel(channel, efx)
8ceee660
BH		 1623 channel->irq = 0;
1624 pci_disable_msi(efx->pci_dev);
1625 pci_disable_msix(efx->pci_dev);
1626
1627 /* Remove legacy interrupt */
1628 efx->legacy_irq = 0;
1629}
1630
8831da7b 1631static void efx_set_channels(struct efx_nic *efx)
8ceee660 1632{
602a5322
BH		 1633 struct efx_channel *channel;
1634 struct efx_tx_queue *tx_queue;
1635
97653431 1636 efx->tx_channel_offset =
b0fbdae1
SS		 1637 efx_separate_tx_channels ?
1638 efx->n_channels - efx->n_tx_channels : 0;
602a5322 1639
79d68b37
SH		 1640 /* We need to mark which channels really have RX and TX
1641 * queues, and adjust the TX queue numbers if we have separate
602a5322
BH		 1642 * RX-only and TX-only channels.
1643 */
1644 efx_for_each_channel(channel, efx) {
79d68b37
SH		 1645 if (channel->channel < efx->n_rx_channels)
1646 channel->rx_queue.core_index = channel->channel;
1647 else
1648 channel->rx_queue.core_index = -1;
1649
602a5322
BH		 1650 efx_for_each_channel_tx_queue(tx_queue, channel)
1651 tx_queue->queue -= (efx->tx_channel_offset *
1652 EFX_TXQ_TYPES);
1653 }
8ceee660
BH		 1654}
1655
1656static int efx_probe_nic(struct efx_nic *efx)
1657{
1658 int rc;
1659
62776d03 1660 netif_dbg(efx, probe, efx->net_dev, "creating NIC\n");
8ceee660
BH		 1661
1662 /* Carry out hardware-type specific initialisation */
ef2b90ee 1663 rc = efx->type->probe(efx);
8ceee660
BH		 1664 if (rc)
1665 return rc;
1666
b0fbdae1
SS		 1667 do {
1668 if (!efx->max_channels || !efx->max_tx_channels) {
1669 netif_err(efx, drv, efx->net_dev,
1670 "Insufficient resources to allocate"
1671 " any channels\n");
1672 rc = -ENOSPC;
1673 goto fail1;
1674 }
8ceee660 1675
b0fbdae1
SS		 1676 /* Determine the number of channels and queues by trying
1677 * to hook in MSI-X interrupts.
1678 */
1679 rc = efx_probe_interrupts(efx);
1680 if (rc)
1681 goto fail1;
52ad762b 1682
b0fbdae1
SS		 1683 efx_set_channels(efx);
1684
1685 /* dimension_resources can fail with EAGAIN */
1686 rc = efx->type->dimension_resources(efx);
1687 if (rc != 0 && rc != -EAGAIN)
1688 goto fail2;
1689
1690 if (rc == -EAGAIN)
1691 /* try again with new max_channels */
1692 efx_remove_interrupts(efx);
1693
1694 } while (rc == -EAGAIN);
28e47c49 1695
5d3a6fca 1696 if (efx->n_channels > 1)
267c0157
JC		 1697 netdev_rss_key_fill(&efx->rx_hash_key,
1698 sizeof(efx->rx_hash_key));
1699 efx_set_default_rx_indir_table(efx);
5d3a6fca 1700
c4f4adc7
BH		 1701 netif_set_real_num_tx_queues(efx->net_dev, efx->n_tx_channels);
1702 netif_set_real_num_rx_queues(efx->net_dev, efx->n_rx_channels);
8ceee660
BH		 1703
1704 /* Initialise the interrupt moderation settings */
539de7c5 1705 efx->irq_mod_step_us = DIV_ROUND_UP(efx->timer_quantum_ns, 1000);
9e393b30
BH		 1706 efx_init_irq_moderation(efx, tx_irq_mod_usec, rx_irq_mod_usec, true,
1707 true);
8ceee660
BH		 1708
1709 return 0;
64d8ad6d 1710
c15eed22
BH		 1711fail2:
1712 efx_remove_interrupts(efx);
1713fail1:
64d8ad6d
BH		 1714 efx->type->remove(efx);
1715 return rc;
8ceee660
BH		 1716}
1717
1718static void efx_remove_nic(struct efx_nic *efx)
1719{
62776d03 1720 netif_dbg(efx, drv, efx->net_dev, "destroying NIC\n");
8ceee660
BH		 1721
1722 efx_remove_interrupts(efx);
ef2b90ee 1723 efx->type->remove(efx);
8ceee660
BH		 1724}
1725
add72477
BH		 1726static int efx_probe_filters(struct efx_nic *efx)
1727{
1728 int rc;
1729
1730 spin_lock_init(&efx->filter_lock);
0d322413 1731 init_rwsem(&efx->filter_sem);
d248953a 1732 mutex_lock(&efx->mac_lock);
0d322413 1733 down_write(&efx->filter_sem);
add72477
BH		 1734 rc = efx->type->filter_table_probe(efx);
1735 if (rc)
0d322413 1736 goto out_unlock;
add72477
BH		 1737
1738#ifdef CONFIG_RFS_ACCEL
1739 if (efx->type->offload_features & NETIF_F_NTUPLE) {
faf8dcc1
JC		 1740 struct efx_channel *channel;
1741 int i, success = 1;
1742
1743 efx_for_each_channel(channel, efx) {
1744 channel->rps_flow_id =
1745 kcalloc(efx->type->max_rx_ip_filters,
1746 sizeof(*channel->rps_flow_id),
1747 GFP_KERNEL);
1748 if (!channel->rps_flow_id)
1749 success = 0;
1750 else
1751 for (i = 0;
1752 i < efx->type->max_rx_ip_filters;
1753 ++i)
1754 channel->rps_flow_id[i] =
1755 RPS_FLOW_ID_INVALID;
1756 }
1757
1758 if (!success) {
1759 efx_for_each_channel(channel, efx)
1760 kfree(channel->rps_flow_id);
add72477 1761 efx->type->filter_table_remove(efx);
0d322413
EC		 1762 rc = -ENOMEM;
1763 goto out_unlock;
add72477 1764 }
faf8dcc1
JC		 1765
1766 efx->rps_expire_index = efx->rps_expire_channel = 0;
add72477
BH		 1767 }
1768#endif
0d322413
EC		 1769out_unlock:
1770 up_write(&efx->filter_sem);
d248953a 1771 mutex_unlock(&efx->mac_lock);
0d322413 1772 return rc;
add72477
BH		 1773}
1774
1775static void efx_remove_filters(struct efx_nic *efx)
1776{
1777#ifdef CONFIG_RFS_ACCEL
faf8dcc1
JC		 1778 struct efx_channel *channel;
1779
1780 efx_for_each_channel(channel, efx)
1781 kfree(channel->rps_flow_id);
add72477 1782#endif
0d322413 1783 down_write(&efx->filter_sem);
add72477 1784 efx->type->filter_table_remove(efx);
0d322413 1785 up_write(&efx->filter_sem);
add72477
BH		 1786}
1787
1788static void efx_restore_filters(struct efx_nic *efx)
1789{
0d322413 1790 down_read(&efx->filter_sem);
add72477 1791 efx->type->filter_table_restore(efx);
0d322413 1792 up_read(&efx->filter_sem);
add72477
BH		 1793}
1794
8ceee660
BH		 1795/**************************************************************************
1796 *
1797 * NIC startup/shutdown
1798 *
1799 *************************************************************************/
1800
1801static int efx_probe_all(struct efx_nic *efx)
1802{
8ceee660
BH		 1803 int rc;
1804
8ceee660
BH		 1805 rc = efx_probe_nic(efx);
1806 if (rc) {
62776d03 1807 netif_err(efx, probe, efx->net_dev, "failed to create NIC\n");
8ceee660
BH		 1808 goto fail1;
1809 }
1810
8ceee660
BH		 1811 rc = efx_probe_port(efx);
1812 if (rc) {
62776d03 1813 netif_err(efx, probe, efx->net_dev, "failed to create port\n");
8ceee660
BH		 1814 goto fail2;
1815 }
1816
7e6d06f0
BH		 1817 BUILD_BUG_ON(EFX_DEFAULT_DMAQ_SIZE < EFX_RXQ_MIN_ENT);
1818 if (WARN_ON(EFX_DEFAULT_DMAQ_SIZE < EFX_TXQ_MIN_ENT(efx))) {
1819 rc = -EINVAL;
1820 goto fail3;
1821 }
ecc910f5 1822 efx->rxq_entries = efx->txq_entries = EFX_DEFAULT_DMAQ_SIZE;
8ceee660 1823
6d8aaaf6
DP		 1824#ifdef CONFIG_SFC_SRIOV
1825 rc = efx->type->vswitching_probe(efx);
1826 if (rc) /* not fatal; the PF will still work fine */
1827 netif_warn(efx, probe, efx->net_dev,
1828 "failed to setup vswitching rc=%d;"
1829 " VFs may not function\n", rc);
1830#endif
1831
64eebcfd
BH		 1832 rc = efx_probe_filters(efx);
1833 if (rc) {
1834 netif_err(efx, probe, efx->net_dev,
1835 "failed to create filter tables\n");
6d8aaaf6 1836 goto fail4;
64eebcfd
BH		 1837 }
1838
7f967c01
BH		 1839 rc = efx_probe_channels(efx);
1840 if (rc)
6d8aaaf6 1841 goto fail5;
7f967c01 1842
8ceee660
BH		 1843 return 0;
1844
6d8aaaf6 1845 fail5:
7f967c01 1846 efx_remove_filters(efx);
6d8aaaf6
DP		 1847 fail4:
1848#ifdef CONFIG_SFC_SRIOV
1849 efx->type->vswitching_remove(efx);
1850#endif
8ceee660 1851 fail3:
8ceee660
BH		 1852 efx_remove_port(efx);
1853 fail2:
1854 efx_remove_nic(efx);
1855 fail1:
1856 return rc;
1857}
1858
8b7325b4
BH		 1859/* If the interface is supposed to be running but is not, start
1860 * the hardware and software data path, regular activity for the port
1861 * (MAC statistics, link polling, etc.) and schedule the port to be
1862 * reconfigured. Interrupts must already be enabled. This function
1863 * is safe to call multiple times, so long as the NIC is not disabled.
1864 * Requires the RTNL lock.
9f2cb71c 1865 */
8ceee660
BH		 1866static void efx_start_all(struct efx_nic *efx)
1867{
8ceee660 1868 EFX_ASSERT_RESET_SERIALISED(efx);
8b7325b4 1869 BUG_ON(efx->state == STATE_DISABLED);
8ceee660
BH		 1870
1871 /* Check that it is appropriate to restart the interface. All
1872 * of these flags are safe to read under just the rtnl lock */
e283546c
EC		 1873 if (efx->port_enabled || !netif_running(efx->net_dev) ||
1874 efx->reset_pending)
8ceee660
BH		 1875 return;
1876
8ceee660 1877 efx_start_port(efx);
9f2cb71c 1878 efx_start_datapath(efx);
8880f4ec 1879
626950db
AR		 1880 /* Start the hardware monitor if there is one */
1881 if (efx->type->monitor != NULL)
8ceee660
BH		 1882 queue_delayed_work(efx->workqueue, &efx->monitor_work,
1883 efx_monitor_interval);
626950db 1884
5a6681e2 1885 /* Link state detection is normally event-driven; we have
626950db
AR		 1886 * to poll now because we could have missed a change
1887 */
5a6681e2
EC		 1888 mutex_lock(&efx->mac_lock);
1889 if (efx->phy_op->poll(efx))
1890 efx_link_status_changed(efx);
1891 mutex_unlock(&efx->mac_lock);
55edc6e6 1892
ef2b90ee 1893 efx->type->start_stats(efx);
f8f3b5ae
JC		 1894 efx->type->pull_stats(efx);
1895 spin_lock_bh(&efx->stats_lock);
1896 efx->type->update_stats(efx, NULL, NULL);
1897 spin_unlock_bh(&efx->stats_lock);
8ceee660
BH		 1898}
1899
8b7325b4
BH		 1900/* Quiesce the hardware and software data path, and regular activity
1901 * for the port without bringing the link down. Safe to call multiple
1902 * times with the NIC in almost any state, but interrupts should be
1903 * enabled. Requires the RTNL lock.
1904 */
8ceee660
BH		 1905static void efx_stop_all(struct efx_nic *efx)
1906{
8ceee660
BH		 1907 EFX_ASSERT_RESET_SERIALISED(efx);
1908
1909 /* port_enabled can be read safely under the rtnl lock */
1910 if (!efx->port_enabled)
1911 return;
1912
f8f3b5ae
JC		 1913 /* update stats before we go down so we can accurately count
1914 * rx_nodesc_drops
1915 */
1916 efx->type->pull_stats(efx);
1917 spin_lock_bh(&efx->stats_lock);
1918 efx->type->update_stats(efx, NULL, NULL);
1919 spin_unlock_bh(&efx->stats_lock);
ef2b90ee 1920 efx->type->stop_stats(efx);
8ceee660
BH		 1921 efx_stop_port(efx);
1922
29c69a48
BH		 1923 /* Stop the kernel transmit interface. This is only valid if
1924 * the device is stopped or detached; otherwise the watchdog
1925 * may fire immediately.
1926 */
1927 WARN_ON(netif_running(efx->net_dev) &&
1928 netif_device_present(efx->net_dev));
9f2cb71c
BH		 1929 netif_tx_disable(efx->net_dev);
1930
1931 efx_stop_datapath(efx);
8ceee660
BH		 1932}
1933
1934static void efx_remove_all(struct efx_nic *efx)
1935{
4642610c 1936 efx_remove_channels(efx);
7f967c01 1937 efx_remove_filters(efx);
6d8aaaf6
DP		 1938#ifdef CONFIG_SFC_SRIOV
1939 efx->type->vswitching_remove(efx);
1940#endif
8ceee660
BH		 1941 efx_remove_port(efx);
1942 efx_remove_nic(efx);
1943}
1944
8ceee660
BH		 1945/**************************************************************************
1946 *
1947 * Interrupt moderation
1948 *
1949 **************************************************************************/
539de7c5 1950unsigned int efx_usecs_to_ticks(struct efx_nic *efx, unsigned int usecs)
0d86ebd8 1951{
b548f976
BH		 1952 if (usecs == 0)
1953 return 0;
539de7c5 1954 if (usecs * 1000 < efx->timer_quantum_ns)
0d86ebd8 1955 return 1; /* never round down to 0 */
539de7c5
BK		 1956 return usecs * 1000 / efx->timer_quantum_ns;
1957}
1958
1959unsigned int efx_ticks_to_usecs(struct efx_nic *efx, unsigned int ticks)
1960{
1961 /* We must round up when converting ticks to microseconds
1962 * because we round down when converting the other way.
1963 */
1964 return DIV_ROUND_UP(ticks * efx->timer_quantum_ns, 1000);
0d86ebd8
BH		 1965}
1966
8ceee660 1967/* Set interrupt moderation parameters */
9e393b30
BH		 1968int efx_init_irq_moderation(struct efx_nic *efx, unsigned int tx_usecs,
1969 unsigned int rx_usecs, bool rx_adaptive,
1970 bool rx_may_override_tx)
8ceee660 1971{
f7d12cdc 1972 struct efx_channel *channel;
d95e329a
BK		 1973 unsigned int timer_max_us;
1974
8ceee660
BH		 1975 EFX_ASSERT_RESET_SERIALISED(efx);
1976
d95e329a
BK		 1977 timer_max_us = efx->timer_max_ns / 1000;
1978
1979 if (tx_usecs > timer_max_us || rx_usecs > timer_max_us)
9e393b30
BH		 1980 return -EINVAL;
1981
539de7c5 1982 if (tx_usecs != rx_usecs && efx->tx_channel_offset == 0 &&
9e393b30
BH		 1983 !rx_may_override_tx) {
1984 netif_err(efx, drv, efx->net_dev, "Channels are shared. "
1985 "RX and TX IRQ moderation must be equal\n");
1986 return -EINVAL;
1987 }
1988
6fb70fd1 1989 efx->irq_rx_adaptive = rx_adaptive;
539de7c5 1990 efx->irq_rx_moderation_us = rx_usecs;
f7d12cdc 1991 efx_for_each_channel(channel, efx) {
525da907 1992 if (efx_channel_has_rx_queue(channel))
539de7c5 1993 channel->irq_moderation_us = rx_usecs;
525da907 1994 else if (efx_channel_has_tx_queues(channel))
539de7c5 1995 channel->irq_moderation_us = tx_usecs;
f7d12cdc 1996 }
9e393b30
BH		 1997
1998 return 0;
8ceee660
BH		 1999}
2000
a0c4faf5
BH		 2001void efx_get_irq_moderation(struct efx_nic *efx, unsigned int *tx_usecs,
2002 unsigned int *rx_usecs, bool *rx_adaptive)
2003{
2004 *rx_adaptive = efx->irq_rx_adaptive;
539de7c5 2005 *rx_usecs = efx->irq_rx_moderation_us;
a0c4faf5
BH		 2006
2007 /* If channels are shared between RX and TX, so is IRQ
2008 * moderation. Otherwise, IRQ moderation is the same for all
2009 * TX channels and is not adaptive.
2010 */
539de7c5 2011 if (efx->tx_channel_offset == 0) {
a0c4faf5 2012 *tx_usecs = *rx_usecs;
539de7c5
BK		 2013 } else {
2014 struct efx_channel *tx_channel;
2015
2016 tx_channel = efx->channel[efx->tx_channel_offset];
2017 *tx_usecs = tx_channel->irq_moderation_us;
2018 }
a0c4faf5
BH		 2019}
2020
8ceee660
BH		 2021/**************************************************************************
2022 *
2023 * Hardware monitor
2024 *
2025 **************************************************************************/
2026
e254c274 2027/* Run periodically off the general workqueue */
8ceee660
BH		 2028static void efx_monitor(struct work_struct *data)
2029{
2030 struct efx_nic *efx = container_of(data, struct efx_nic,
2031 monitor_work.work);
8ceee660 2032
62776d03
BH		 2033 netif_vdbg(efx, timer, efx->net_dev,
2034 "hardware monitor executing on CPU %d\n",
2035 raw_smp_processor_id());
ef2b90ee 2036 BUG_ON(efx->type->monitor == NULL);
8ceee660 2037
8ceee660
BH		 2038 /* If the mac_lock is already held then it is likely a port
2039 * reconfiguration is already in place, which will likely do
e254c274
BH		 2040 * most of the work of monitor() anyway. */
2041 if (mutex_trylock(&efx->mac_lock)) {
2042 if (efx->port_enabled)
2043 efx->type->monitor(efx);
2044 mutex_unlock(&efx->mac_lock);
2045 }
8ceee660 2046
8ceee660
BH		 2047 queue_delayed_work(efx->workqueue, &efx->monitor_work,
2048 efx_monitor_interval);
2049}
2050
2051/**************************************************************************
2052 *
2053 * ioctls
2054 *
2055 *************************************************************************/
2056
2057/* Net device ioctl
2058 * Context: process, rtnl_lock() held.
2059 */
2060static int efx_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd)
2061{
767e468c 2062 struct efx_nic *efx = netdev_priv(net_dev);
68e7f45e 2063 struct mii_ioctl_data *data = if_mii(ifr);
8ceee660 2064
7c236c43 2065 if (cmd == SIOCSHWTSTAMP)
433dc9b3
BH		 2066 return efx_ptp_set_ts_config(efx, ifr);
2067 if (cmd == SIOCGHWTSTAMP)
2068 return efx_ptp_get_ts_config(efx, ifr);
7c236c43 2069
68e7f45e
BH		 2070 /* Convert phy_id from older PRTAD/DEVAD format */
2071 if ((cmd == SIOCGMIIREG || cmd == SIOCSMIIREG) &&
2072 (data->phy_id & 0xfc00) == 0x0400)
2073 data->phy_id ^= MDIO_PHY_ID_C45 | 0x0400;
2074
2075 return mdio_mii_ioctl(&efx->mdio, data, cmd);
8ceee660
BH		 2076}
2077
2078/**************************************************************************
2079 *
2080 * NAPI interface
2081 *
2082 **************************************************************************/
2083
7f967c01
BH		 2084static void efx_init_napi_channel(struct efx_channel *channel)
2085{
2086 struct efx_nic *efx = channel->efx;
2087
2088 channel->napi_dev = efx->net_dev;
2089 netif_napi_add(channel->napi_dev, &channel->napi_str,
2090 efx_poll, napi_weight);
c0f9c7e4 2091 efx_channel_busy_poll_init(channel);
7f967c01
BH		 2092}
2093
e8f14992 2094static void efx_init_napi(struct efx_nic *efx)
8ceee660
BH		 2095{
2096 struct efx_channel *channel;
8ceee660 2097
7f967c01
BH		 2098 efx_for_each_channel(channel, efx)
2099 efx_init_napi_channel(channel);
e8f14992
BH		 2100}
2101
2102static void efx_fini_napi_channel(struct efx_channel *channel)
2103{
973334a1 2104 if (channel->napi_dev)
e8f14992 2105 netif_napi_del(&channel->napi_str);
973334a1 2106
e8f14992 2107 channel->napi_dev = NULL;
8ceee660
BH		 2108}
2109
2110static void efx_fini_napi(struct efx_nic *efx)
2111{
2112 struct efx_channel *channel;
2113
e8f14992
BH		 2114 efx_for_each_channel(channel, efx)
2115 efx_fini_napi_channel(channel);
8ceee660
BH		 2116}
2117
2118/**************************************************************************
2119 *
2120 * Kernel netpoll interface
2121 *
2122 *************************************************************************/
2123
2124#ifdef CONFIG_NET_POLL_CONTROLLER
2125
2126/* Although in the common case interrupts will be disabled, this is not
2127 * guaranteed. However, all our work happens inside the NAPI callback,
2128 * so no locking is required.
2129 */
2130static void efx_netpoll(struct net_device *net_dev)
2131{
767e468c 2132 struct efx_nic *efx = netdev_priv(net_dev);
8ceee660
BH		 2133 struct efx_channel *channel;
2134
64ee3120 2135 efx_for_each_channel(channel, efx)
8ceee660
BH		 2136 efx_schedule_channel(channel);
2137}
2138
2139#endif
2140
36763266
AR		 2141#ifdef CONFIG_NET_RX_BUSY_POLL
2142static int efx_busy_poll(struct napi_struct *napi)
2143{
2144 struct efx_channel *channel =
2145 container_of(napi, struct efx_channel, napi_str);
2146 struct efx_nic *efx = channel->efx;
2147 int budget = 4;
2148 int old_rx_packets, rx_packets;
2149
2150 if (!netif_running(efx->net_dev))
2151 return LL_FLUSH_FAILED;
2152
c0f9c7e4 2153 if (!efx_channel_try_lock_poll(channel))
36763266
AR		 2154 return LL_FLUSH_BUSY;
2155
2156 old_rx_packets = channel->rx_queue.rx_packets;
2157 efx_process_channel(channel, budget);
2158
2159 rx_packets = channel->rx_queue.rx_packets - old_rx_packets;
2160
2161 /* There is no race condition with NAPI here.
2162 * NAPI will automatically be rescheduled if it yielded during busy
2163 * polling, because it was not able to take the lock and thus returned
2164 * the full budget.
2165 */
2166 efx_channel_unlock_poll(channel);
2167
2168 return rx_packets;
2169}
2170#endif
2171
8ceee660
BH		 2172/**************************************************************************
2173 *
2174 * Kernel net device interface
2175 *
2176 *************************************************************************/
2177
2178/* Context: process, rtnl_lock() held. */
e340be92 2179int efx_net_open(struct net_device *net_dev)
8ceee660 2180{
767e468c 2181 struct efx_nic *efx = netdev_priv(net_dev);
8b7325b4
BH		 2182 int rc;
2183
62776d03
BH		 2184 netif_dbg(efx, ifup, efx->net_dev, "opening device on CPU %d\n",
2185 raw_smp_processor_id());
8ceee660 2186
8b7325b4
BH		 2187 rc = efx_check_disabled(efx);
2188 if (rc)
2189 return rc;
f8b87c17
BH		 2190 if (efx->phy_mode & PHY_MODE_SPECIAL)
2191 return -EBUSY;
8880f4ec
BH		 2192 if (efx_mcdi_poll_reboot(efx) && efx_reset(efx, RESET_TYPE_ALL))
2193 return -EIO;
f8b87c17 2194
78c1f0a0
SH		 2195 /* Notify the kernel of the link state polled during driver load,
2196 * before the monitor starts running */
2197 efx_link_status_changed(efx);
2198
8ceee660 2199 efx_start_all(efx);
dd40781e 2200 efx_selftest_async_start(efx);
8ceee660
BH		 2201 return 0;
2202}
2203
2204/* Context: process, rtnl_lock() held.
2205 * Note that the kernel will ignore our return code; this method
2206 * should really be a void.
2207 */
e340be92 2208int efx_net_stop(struct net_device *net_dev)
8ceee660 2209{
767e468c 2210 struct efx_nic *efx = netdev_priv(net_dev);
8ceee660 2211
62776d03
BH		 2212 netif_dbg(efx, ifdown, efx->net_dev, "closing on CPU %d\n",
2213 raw_smp_processor_id());
8ceee660 2214
8b7325b4
BH		 2215 /* Stop the device and flush all the channels */
2216 efx_stop_all(efx);
8ceee660
BH		 2217
2218 return 0;
2219}
2220
5b9e207c 2221/* Context: process, dev_base_lock or RTNL held, non-blocking. */
bc1f4470 2222static void efx_net_stats(struct net_device *net_dev,
2223 struct rtnl_link_stats64 *stats)
8ceee660 2224{
767e468c 2225 struct efx_nic *efx = netdev_priv(net_dev);
8ceee660 2226
55edc6e6 2227 spin_lock_bh(&efx->stats_lock);
cd0ecc9a 2228 efx->type->update_stats(efx, NULL, stats);
1cb34522 2229 spin_unlock_bh(&efx->stats_lock);
8ceee660
BH		 2230}
2231
2232/* Context: netif_tx_lock held, BHs disabled. */
2233static void efx_watchdog(struct net_device *net_dev)
2234{
767e468c 2235 struct efx_nic *efx = netdev_priv(net_dev);
8ceee660 2236
62776d03
BH		 2237 netif_err(efx, tx_err, efx->net_dev,
2238 "TX stuck with port_enabled=%d: resetting channels\n",
2239 efx->port_enabled);
8ceee660 2240
739bb23d 2241 efx_schedule_reset(efx, RESET_TYPE_TX_WATCHDOG);
8ceee660
BH		 2242}
2243
2244
2245/* Context: process, rtnl_lock() held. */
2246static int efx_change_mtu(struct net_device *net_dev, int new_mtu)
2247{
767e468c 2248 struct efx_nic *efx = netdev_priv(net_dev);
8b7325b4 2249 int rc;
8ceee660 2250
8b7325b4
BH		 2251 rc = efx_check_disabled(efx);
2252 if (rc)
2253 return rc;
8ceee660 2254
62776d03 2255 netif_dbg(efx, drv, efx->net_dev, "changing MTU to %d\n", new_mtu);
8ceee660 2256
29c69a48
BH		 2257 efx_device_detach_sync(efx);
2258 efx_stop_all(efx);
2259
d3245b28 2260 mutex_lock(&efx->mac_lock);
8ceee660 2261 net_dev->mtu = new_mtu;
0d322413 2262 efx_mac_reconfigure(efx);
d3245b28
BH		 2263 mutex_unlock(&efx->mac_lock);
2264
8ceee660 2265 efx_start_all(efx);
29c69a48 2266 netif_device_attach(efx->net_dev);
6c8eef4a 2267 return 0;
8ceee660
BH		 2268}
2269
2270static int efx_set_mac_address(struct net_device *net_dev, void *data)
2271{
767e468c 2272 struct efx_nic *efx = netdev_priv(net_dev);
8ceee660 2273 struct sockaddr *addr = data;
e0b3ae30 2274 u8 *new_addr = addr->sa_data;
cfc77c2f
SS		 2275 u8 old_addr[6];
2276 int rc;
8ceee660 2277
8ceee660 2278 if (!is_valid_ether_addr(new_addr)) {
62776d03
BH		 2279 netif_err(efx, drv, efx->net_dev,
2280 "invalid ethernet MAC address requested: %pM\n",
2281 new_addr);
504f9b5a 2282 return -EADDRNOTAVAIL;
8ceee660
BH		 2283 }
2284
cfc77c2f
SS		 2285 /* save old address */
2286 ether_addr_copy(old_addr, net_dev->dev_addr);
cd84ff4d 2287 ether_addr_copy(net_dev->dev_addr, new_addr);
910c8789
SS		 2288 if (efx->type->set_mac_address) {
2289 rc = efx->type->set_mac_address(efx);
cfc77c2f
SS		 2290 if (rc) {
2291 ether_addr_copy(net_dev->dev_addr, old_addr);
2292 return rc;
2293 }
2294 }
8ceee660
BH		 2295
2296 /* Reconfigure the MAC */
d3245b28 2297 mutex_lock(&efx->mac_lock);
0d322413 2298 efx_mac_reconfigure(efx);
d3245b28 2299 mutex_unlock(&efx->mac_lock);
8ceee660
BH		 2300
2301 return 0;
2302}
2303
a816f75a 2304/* Context: netif_addr_lock held, BHs disabled. */
0fca8c97 2305static void efx_set_rx_mode(struct net_device *net_dev)
8ceee660 2306{
767e468c 2307 struct efx_nic *efx = netdev_priv(net_dev);
a816f75a 2308
8be4f3e6
BH		 2309 if (efx->port_enabled)
2310 queue_work(efx->workqueue, &efx->mac_work);
2311 /* Otherwise efx_start_port() will do this */
8ceee660
BH		 2312}
2313
c8f44aff 2314static int efx_set_features(struct net_device *net_dev, netdev_features_t data)
abfe9039
BH		 2315{
2316 struct efx_nic *efx = netdev_priv(net_dev);
4a53ea8a 2317 int rc;
abfe9039
BH		 2318
2319 /* If disabling RX n-tuple filtering, clear existing filters */
4a53ea8a
AR		 2320 if (net_dev->features & ~data & NETIF_F_NTUPLE) {
2321 rc = efx->type->filter_clear_rx(efx, EFX_FILTER_PRI_MANUAL);
2322 if (rc)
2323 return rc;
2324 }
2325
2326 /* If Rx VLAN filter is changed, update filters via mac_reconfigure */
2327 if ((net_dev->features ^ data) & NETIF_F_HW_VLAN_CTAG_FILTER) {
2328 /* efx_set_rx_mode() will schedule MAC work to update filters
2329 * when a new features are finally set in net_dev.
2330 */
2331 efx_set_rx_mode(net_dev);
2332 }
abfe9039
BH		 2333
2334 return 0;
2335}
2336
08a7b29b
BK		 2337int efx_get_phys_port_id(struct net_device *net_dev,
2338 struct netdev_phys_item_id *ppid)
2339{
2340 struct efx_nic *efx = netdev_priv(net_dev);
2341
2342 if (efx->type->get_phys_port_id)
2343 return efx->type->get_phys_port_id(efx, ppid);
2344 else
2345 return -EOPNOTSUPP;
2346}
2347
ac019f08
BK		 2348static int efx_get_phys_port_name(struct net_device *net_dev,
2349 char *name, size_t len)
2350{
2351 struct efx_nic *efx = netdev_priv(net_dev);
2352
2353 if (snprintf(name, len, "p%u", efx->port_num) >= len)
2354 return -EINVAL;
2355 return 0;
2356}
2357
4a53ea8a
AR		 2358static int efx_vlan_rx_add_vid(struct net_device *net_dev, __be16 proto, u16 vid)
2359{
2360 struct efx_nic *efx = netdev_priv(net_dev);
2361
2362 if (efx->type->vlan_rx_add_vid)
2363 return efx->type->vlan_rx_add_vid(efx, proto, vid);
2364 else
2365 return -EOPNOTSUPP;
2366}
2367
2368static int efx_vlan_rx_kill_vid(struct net_device *net_dev, __be16 proto, u16 vid)
2369{
2370 struct efx_nic *efx = netdev_priv(net_dev);
2371
2372 if (efx->type->vlan_rx_kill_vid)
2373 return efx->type->vlan_rx_kill_vid(efx, proto, vid);
2374 else
2375 return -EOPNOTSUPP;
2376}
2377
7fa8d547 2378static const struct net_device_ops efx_netdev_ops = {
c3ecb9f3
SH		 2379 .ndo_open = efx_net_open,
2380 .ndo_stop = efx_net_stop,
4472702e 2381 .ndo_get_stats64 = efx_net_stats,
c3ecb9f3
SH		 2382 .ndo_tx_timeout = efx_watchdog,
2383 .ndo_start_xmit = efx_hard_start_xmit,
2384 .ndo_validate_addr = eth_validate_addr,
2385 .ndo_do_ioctl = efx_ioctl,
2386 .ndo_change_mtu = efx_change_mtu,
2387 .ndo_set_mac_address = efx_set_mac_address,
0fca8c97 2388 .ndo_set_rx_mode = efx_set_rx_mode,
abfe9039 2389 .ndo_set_features = efx_set_features,
4a53ea8a
AR		 2390 .ndo_vlan_rx_add_vid = efx_vlan_rx_add_vid,
2391 .ndo_vlan_rx_kill_vid = efx_vlan_rx_kill_vid,
cd2d5b52 2392#ifdef CONFIG_SFC_SRIOV
7fa8d547
SS		 2393 .ndo_set_vf_mac = efx_sriov_set_vf_mac,
2394 .ndo_set_vf_vlan = efx_sriov_set_vf_vlan,
2395 .ndo_set_vf_spoofchk = efx_sriov_set_vf_spoofchk,
2396 .ndo_get_vf_config = efx_sriov_get_vf_config,
4392dc69 2397 .ndo_set_vf_link_state = efx_sriov_set_vf_link_state,
cd2d5b52 2398#endif
08a7b29b 2399 .ndo_get_phys_port_id = efx_get_phys_port_id,
ac019f08 2400 .ndo_get_phys_port_name = efx_get_phys_port_name,
c3ecb9f3
SH		 2401#ifdef CONFIG_NET_POLL_CONTROLLER
2402 .ndo_poll_controller = efx_netpoll,
2403#endif
94b274bf 2404 .ndo_setup_tc = efx_setup_tc,
36763266
AR		 2405#ifdef CONFIG_NET_RX_BUSY_POLL
2406 .ndo_busy_poll = efx_busy_poll,
2407#endif
64d8ad6d
BH		 2408#ifdef CONFIG_RFS_ACCEL
2409 .ndo_rx_flow_steer = efx_filter_rfs,
2410#endif
c3ecb9f3
SH		 2411};
2412
7dde596e
BH		 2413static void efx_update_name(struct efx_nic *efx)
2414{
2415 strcpy(efx->name, efx->net_dev->name);
2416 efx_mtd_rename(efx);
2417 efx_set_channel_names(efx);
2418}
2419
8ceee660
BH		 2420static int efx_netdev_event(struct notifier_block *this,
2421 unsigned long event, void *ptr)
2422{
351638e7 2423 struct net_device *net_dev = netdev_notifier_info_to_dev(ptr);
8ceee660 2424
7fa8d547 2425 if ((net_dev->netdev_ops == &efx_netdev_ops) &&
7dde596e
BH		 2426 event == NETDEV_CHANGENAME)
2427 efx_update_name(netdev_priv(net_dev));
8ceee660
BH		 2428
2429 return NOTIFY_DONE;
2430}
2431
2432static struct notifier_block efx_netdev_notifier = {
2433 .notifier_call = efx_netdev_event,
2434};
2435
06d5e193
BH		 2436static ssize_t
2437show_phy_type(struct device *dev, struct device_attribute *attr, char *buf)
2438{
2439 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
2440 return sprintf(buf, "%d\n", efx->phy_type);
2441}
776fbcc9 2442static DEVICE_ATTR(phy_type, 0444, show_phy_type, NULL);
06d5e193 2443
e7fef9b4
EC		 2444#ifdef CONFIG_SFC_MCDI_LOGGING
2445static ssize_t show_mcdi_log(struct device *dev, struct device_attribute *attr,
2446 char *buf)
2447{
2448 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
2449 struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
2450
2451 return scnprintf(buf, PAGE_SIZE, "%d\n", mcdi->logging_enabled);
2452}
2453static ssize_t set_mcdi_log(struct device *dev, struct device_attribute *attr,
2454 const char *buf, size_t count)
2455{
2456 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
2457 struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
2458 bool enable = count > 0 && *buf != '0';
2459
2460 mcdi->logging_enabled = enable;
2461 return count;
2462}
2463static DEVICE_ATTR(mcdi_logging, 0644, show_mcdi_log, set_mcdi_log);
2464#endif
2465
8ceee660
BH		 2466static int efx_register_netdev(struct efx_nic *efx)
2467{
2468 struct net_device *net_dev = efx->net_dev;
c04bfc6b 2469 struct efx_channel *channel;
8ceee660
BH		 2470 int rc;
2471
2472 net_dev->watchdog_timeo = 5 * HZ;
2473 net_dev->irq = efx->pci_dev->irq;
7fa8d547
SS		 2474 net_dev->netdev_ops = &efx_netdev_ops;
2475 if (efx_nic_rev(efx) >= EFX_REV_HUNT_A0)
8127d661 2476 net_dev->priv_flags |= IFF_UNICAST_FLT;
7ad24ea4 2477 net_dev->ethtool_ops = &efx_ethtool_ops;
7e6d06f0 2478 net_dev->gso_max_segs = EFX_TSO_MAX_SEGS;
cd94e519
BK		 2479 net_dev->min_mtu = EFX_MIN_MTU;
2480 net_dev->max_mtu = EFX_MAX_MTU;
8ceee660 2481
7dde596e 2482 rtnl_lock();
aed0628d 2483
7153f623
BH		 2484 /* Enable resets to be scheduled and check whether any were
2485 * already requested. If so, the NIC is probably hosed so we
2486 * abort.
2487 */
2488 efx->state = STATE_READY;
2489 smp_mb(); /* ensure we change state before checking reset_pending */
2490 if (efx->reset_pending) {
2491 netif_err(efx, probe, efx->net_dev,
2492 "aborting probe due to scheduled reset\n");
2493 rc = -EIO;
2494 goto fail_locked;
2495 }
2496
aed0628d
BH		 2497 rc = dev_alloc_name(net_dev, net_dev->name);
2498 if (rc < 0)
2499 goto fail_locked;
7dde596e 2500 efx_update_name(efx);
aed0628d 2501
8f8b3d51
BH		 2502 /* Always start with carrier off; PHY events will detect the link */
2503 netif_carrier_off(net_dev);
2504
aed0628d
BH		 2505 rc = register_netdevice(net_dev);
2506 if (rc)
2507 goto fail_locked;
2508
c04bfc6b
BH		 2509 efx_for_each_channel(channel, efx) {
2510 struct efx_tx_queue *tx_queue;
60031fcc
BH		 2511 efx_for_each_channel_tx_queue(tx_queue, channel)
2512 efx_init_tx_queue_core_txq(tx_queue);
c04bfc6b
BH		 2513 }
2514
0bcf4a64
BH		 2515 efx_associate(efx);
2516
7dde596e 2517 rtnl_unlock();
8ceee660 2518
06d5e193
BH		 2519 rc = device_create_file(&efx->pci_dev->dev, &dev_attr_phy_type);
2520 if (rc) {
62776d03
BH		 2521 netif_err(efx, drv, efx->net_dev,
2522 "failed to init net dev attributes\n");
06d5e193
BH		 2523 goto fail_registered;
2524 }
e7fef9b4
EC		 2525#ifdef CONFIG_SFC_MCDI_LOGGING
2526 rc = device_create_file(&efx->pci_dev->dev, &dev_attr_mcdi_logging);
2527 if (rc) {
2528 netif_err(efx, drv, efx->net_dev,
2529 "failed to init net dev attributes\n");
2530 goto fail_attr_mcdi_logging;
2531 }
2532#endif
06d5e193 2533
8ceee660 2534 return 0;
06d5e193 2535
e7fef9b4
EC		 2536#ifdef CONFIG_SFC_MCDI_LOGGING
2537fail_attr_mcdi_logging:
2538 device_remove_file(&efx->pci_dev->dev, &dev_attr_phy_type);
2539#endif
7153f623
BH		 2540fail_registered:
2541 rtnl_lock();
0bcf4a64 2542 efx_dissociate(efx);
7153f623 2543 unregister_netdevice(net_dev);
aed0628d 2544fail_locked:
7153f623 2545 efx->state = STATE_UNINIT;
aed0628d 2546 rtnl_unlock();
62776d03 2547 netif_err(efx, drv, efx->net_dev, "could not register net dev\n");
aed0628d 2548 return rc;
8ceee660
BH		 2549}
2550
2551static void efx_unregister_netdev(struct efx_nic *efx)
2552{
8ceee660
BH		 2553 if (!efx->net_dev)
2554 return;
2555
767e468c 2556 BUG_ON(netdev_priv(efx->net_dev) != efx);
8ceee660 2557
e7fef9b4
EC		 2558 if (efx_dev_registered(efx)) {
2559 strlcpy(efx->name, pci_name(efx->pci_dev), sizeof(efx->name));
2560#ifdef CONFIG_SFC_MCDI_LOGGING
2561 device_remove_file(&efx->pci_dev->dev, &dev_attr_mcdi_logging);
2562#endif
2563 device_remove_file(&efx->pci_dev->dev, &dev_attr_phy_type);
2564 unregister_netdev(efx->net_dev);
2565 }
8ceee660
BH		 2566}
2567
2568/**************************************************************************
2569 *
2570 * Device reset and suspend
2571 *
2572 **************************************************************************/
2573
2467ca46
BH		 2574/* Tears down the entire software state and most of the hardware state
2575 * before reset. */
d3245b28 2576void efx_reset_down(struct efx_nic *efx, enum reset_type method)
8ceee660 2577{
8ceee660
BH		 2578 EFX_ASSERT_RESET_SERIALISED(efx);
2579
e283546c
EC		 2580 if (method == RESET_TYPE_MCDI_TIMEOUT)
2581 efx->type->prepare_flr(efx);
2582
2467ca46 2583 efx_stop_all(efx);
d8291187 2584 efx_disable_interrupts(efx);
5642ceef
BH		 2585
2586 mutex_lock(&efx->mac_lock);
087e9025
JC		 2587 if (efx->port_initialized && method != RESET_TYPE_INVISIBLE &&
2588 method != RESET_TYPE_DATAPATH)
4b988280 2589 efx->phy_op->fini(efx);
ef2b90ee 2590 efx->type->fini(efx);
8ceee660
BH		 2591}
2592
2467ca46
BH		 2593/* This function will always ensure that the locks acquired in
2594 * efx_reset_down() are released. A failure return code indicates
2595 * that we were unable to reinitialise the hardware, and the
2596 * driver should be disabled. If ok is false, then the rx and tx
2597 * engines are not restarted, pending a RESET_DISABLE. */
d3245b28 2598int efx_reset_up(struct efx_nic *efx, enum reset_type method, bool ok)
8ceee660
BH		 2599{
2600 int rc;
2601
2467ca46 2602 EFX_ASSERT_RESET_SERIALISED(efx);
8ceee660 2603
e283546c
EC		 2604 if (method == RESET_TYPE_MCDI_TIMEOUT)
2605 efx->type->finish_flr(efx);
2606
2607 /* Ensure that SRAM is initialised even if we're disabling the device */
ef2b90ee 2608 rc = efx->type->init(efx);
8ceee660 2609 if (rc) {
62776d03 2610 netif_err(efx, drv, efx->net_dev, "failed to initialise NIC\n");
eb9f6744 2611 goto fail;
8ceee660
BH		 2612 }
2613
eb9f6744
BH		 2614 if (!ok)
2615 goto fail;
2616
087e9025
JC		 2617 if (efx->port_initialized && method != RESET_TYPE_INVISIBLE &&
2618 method != RESET_TYPE_DATAPATH) {
eb9f6744
BH		 2619 rc = efx->phy_op->init(efx);
2620 if (rc)
2621 goto fail;
267d9d73
EC		 2622 rc = efx->phy_op->reconfigure(efx);
2623 if (rc && rc != -EPERM)
62776d03
BH		 2624 netif_err(efx, drv, efx->net_dev,
2625 "could not restore PHY settings\n");
4b988280
SH		 2626 }
2627
261e4d96
JC		 2628 rc = efx_enable_interrupts(efx);
2629 if (rc)
2630 goto fail;
6d8aaaf6
DP		 2631
2632#ifdef CONFIG_SFC_SRIOV
2633 rc = efx->type->vswitching_restore(efx);
2634 if (rc) /* not fatal; the PF will still work fine */
2635 netif_warn(efx, probe, efx->net_dev,
2636 "failed to restore vswitching rc=%d;"
2637 " VFs may not function\n", rc);
2638#endif
2639
0d322413 2640 down_read(&efx->filter_sem);
64eebcfd 2641 efx_restore_filters(efx);
0d322413 2642 up_read(&efx->filter_sem);
7fa8d547
SS		 2643 if (efx->type->sriov_reset)
2644 efx->type->sriov_reset(efx);
eb9f6744 2645
eb9f6744
BH		 2646 mutex_unlock(&efx->mac_lock);
2647
2648 efx_start_all(efx);
2649
2650 return 0;
2651
2652fail:
2653 efx->port_initialized = false;
2467ca46
BH		 2654
2655 mutex_unlock(&efx->mac_lock);
2656
8ceee660
BH		 2657 return rc;
2658}
2659
eb9f6744
BH		 2660/* Reset the NIC using the specified method. Note that the reset may
2661 * fail, in which case the card will be left in an unusable state.
8ceee660 2662 *
eb9f6744 2663 * Caller must hold the rtnl_lock.
8ceee660 2664 */
eb9f6744 2665int efx_reset(struct efx_nic *efx, enum reset_type method)
8ceee660 2666{
eb9f6744
BH		 2667 int rc, rc2;
2668 bool disabled;
8ceee660 2669
62776d03
BH		 2670 netif_info(efx, drv, efx->net_dev, "resetting (%s)\n",
2671 RESET_TYPE(method));
8ceee660 2672
c2f3b8e3 2673 efx_device_detach_sync(efx);
d3245b28 2674 efx_reset_down(efx, method);
8ceee660 2675
ef2b90ee 2676 rc = efx->type->reset(efx, method);
8ceee660 2677 if (rc) {
62776d03 2678 netif_err(efx, drv, efx->net_dev, "failed to reset hardware\n");
eb9f6744 2679 goto out;
8ceee660
BH		 2680 }
2681
a7d529ae
BH		 2682 /* Clear flags for the scopes we covered. We assume the NIC and
2683 * driver are now quiescent so that there is no race here.
2684 */
e283546c
EC		 2685 if (method < RESET_TYPE_MAX_METHOD)
2686 efx->reset_pending &= -(1 << (method + 1));
2687 else /* it doesn't fit into the well-ordered scope hierarchy */
2688 __clear_bit(method, &efx->reset_pending);
8ceee660
BH		 2689
2690 /* Reinitialise bus-mastering, which may have been turned off before
2691 * the reset was scheduled. This is still appropriate, even in the
2692 * RESET_TYPE_DISABLE since this driver generally assumes the hardware
2693 * can respond to requests. */
2694 pci_set_master(efx->pci_dev);
2695
eb9f6744 2696out:
8ceee660 2697 /* Leave device stopped if necessary */
626950db
AR		 2698 disabled = rc ||
2699 method == RESET_TYPE_DISABLE ||
2700 method == RESET_TYPE_RECOVER_OR_DISABLE;
eb9f6744
BH		 2701 rc2 = efx_reset_up(efx, method, !disabled);
2702 if (rc2) {
2703 disabled = true;
2704 if (!rc)
2705 rc = rc2;
8ceee660
BH		 2706 }
2707
eb9f6744 2708 if (disabled) {
f49a4589 2709 dev_close(efx->net_dev);
62776d03 2710 netif_err(efx, drv, efx->net_dev, "has been disabled\n");
f4bd954e 2711 efx->state = STATE_DISABLED;
f4bd954e 2712 } else {
62776d03 2713 netif_dbg(efx, drv, efx->net_dev, "reset complete\n");
e4abce85 2714 netif_device_attach(efx->net_dev);
f4bd954e 2715 }
8ceee660
BH		 2716 return rc;
2717}
2718
626950db
AR		 2719/* Try recovery mechanisms.
2720 * For now only EEH is supported.
2721 * Returns 0 if the recovery mechanisms are unsuccessful.
2722 * Returns a non-zero value otherwise.
2723 */
b28405b0 2724int efx_try_recovery(struct efx_nic *efx)
626950db
AR		 2725{
2726#ifdef CONFIG_EEH
2727 /* A PCI error can occur and not be seen by EEH because nothing
2728 * happens on the PCI bus. In this case the driver may fail and
2729 * schedule a 'recover or reset', leading to this recovery handler.
2730 * Manually call the eeh failure check function.
2731 */
12a89dba 2732 struct eeh_dev *eehdev = pci_dev_to_eeh_dev(efx->pci_dev);
626950db
AR		 2733 if (eeh_dev_check_failure(eehdev)) {
2734 /* The EEH mechanisms will handle the error and reset the
2735 * device if necessary.
2736 */
2737 return 1;
2738 }
2739#endif
2740 return 0;
2741}
2742
74cd60a4
JC		 2743static void efx_wait_for_bist_end(struct efx_nic *efx)
2744{
2745 int i;
2746
2747 for (i = 0; i < BIST_WAIT_DELAY_COUNT; ++i) {
2748 if (efx_mcdi_poll_reboot(efx))
2749 goto out;
2750 msleep(BIST_WAIT_DELAY_MS);
2751 }
2752
2753 netif_err(efx, drv, efx->net_dev, "Warning: No MC reboot after BIST mode\n");
2754out:
2755 /* Either way unset the BIST flag. If we found no reboot we probably
2756 * won't recover, but we should try.
2757 */
2758 efx->mc_bist_for_other_fn = false;
2759}
2760
8ceee660
BH		 2761/* The worker thread exists so that code that cannot sleep can
2762 * schedule a reset for later.
2763 */
2764static void efx_reset_work(struct work_struct *data)
2765{
eb9f6744 2766 struct efx_nic *efx = container_of(data, struct efx_nic, reset_work);
626950db
AR		 2767 unsigned long pending;
2768 enum reset_type method;
2769
2770 pending = ACCESS_ONCE(efx->reset_pending);
2771 method = fls(pending) - 1;
2772
74cd60a4
JC		 2773 if (method == RESET_TYPE_MC_BIST)
2774 efx_wait_for_bist_end(efx);
2775
626950db
AR		 2776 if ((method == RESET_TYPE_RECOVER_OR_DISABLE ||
2777 method == RESET_TYPE_RECOVER_OR_ALL) &&
2778 efx_try_recovery(efx))
2779 return;
8ceee660 2780
a7d529ae 2781 if (!pending)
319ba649
SH		 2782 return;
2783
eb9f6744 2784 rtnl_lock();
7153f623
BH		 2785
2786 /* We checked the state in efx_schedule_reset() but it may
2787 * have changed by now. Now that we have the RTNL lock,
2788 * it cannot change again.
2789 */
2790 if (efx->state == STATE_READY)
626950db 2791 (void)efx_reset(efx, method);
7153f623 2792
eb9f6744 2793 rtnl_unlock();
8ceee660
BH		 2794}
2795
2796void efx_schedule_reset(struct efx_nic *efx, enum reset_type type)
2797{
2798 enum reset_type method;
2799
626950db
AR		 2800 if (efx->state == STATE_RECOVERY) {
2801 netif_dbg(efx, drv, efx->net_dev,
2802 "recovering: skip scheduling %s reset\n",
2803 RESET_TYPE(type));
2804 return;
2805 }
2806
8ceee660
BH		 2807 switch (type) {
2808 case RESET_TYPE_INVISIBLE:
2809 case RESET_TYPE_ALL:
626950db 2810 case RESET_TYPE_RECOVER_OR_ALL:
8ceee660
BH		 2811 case RESET_TYPE_WORLD:
2812 case RESET_TYPE_DISABLE:
626950db 2813 case RESET_TYPE_RECOVER_OR_DISABLE:
087e9025 2814 case RESET_TYPE_DATAPATH:
74cd60a4 2815 case RESET_TYPE_MC_BIST:
e283546c 2816 case RESET_TYPE_MCDI_TIMEOUT:
8ceee660 2817 method = type;
0e2a9c7c
BH		 2818 netif_dbg(efx, drv, efx->net_dev, "scheduling %s reset\n",
2819 RESET_TYPE(method));
8ceee660 2820 break;
8ceee660 2821 default:
0e2a9c7c 2822 method = efx->type->map_reset_reason(type);
62776d03
BH		 2823 netif_dbg(efx, drv, efx->net_dev,
2824 "scheduling %s reset for %s\n",
2825 RESET_TYPE(method), RESET_TYPE(type));
0e2a9c7c
BH		 2826 break;
2827 }
8ceee660 2828
a7d529ae 2829 set_bit(method, &efx->reset_pending);
7153f623
BH		 2830 smp_mb(); /* ensure we change reset_pending before checking state */
2831
2832 /* If we're not READY then just leave the flags set as the cue
2833 * to abort probing or reschedule the reset later.
2834 */
2835 if (ACCESS_ONCE(efx->state) != STATE_READY)
2836 return;
8ceee660 2837
8880f4ec
BH		 2838 /* efx_process_channel() will no longer read events once a
2839 * reset is scheduled. So switch back to poll'd MCDI completions. */
2840 efx_mcdi_mode_poll(efx);
2841
1ab00629 2842 queue_work(reset_workqueue, &efx->reset_work);
8ceee660
BH		 2843}
2844
2845/**************************************************************************
2846 *
2847 * List of NICs we support
2848 *
2849 **************************************************************************/
2850
2851/* PCI device ID table */
9baa3c34 2852static const struct pci_device_id efx_pci_table[] = {
547c474f 2853 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0803), /* SFC9020 */
8880f4ec 2854 .driver_data = (unsigned long) &siena_a0_nic_type},
547c474f 2855 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0813), /* SFL9021 */
8880f4ec 2856 .driver_data = (unsigned long) &siena_a0_nic_type},
8127d661
BH		 2857 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0903), /* SFC9120 PF */
2858 .driver_data = (unsigned long) &efx_hunt_a0_nic_type},
6f7f8aa6
SS		 2859 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x1903), /* SFC9120 VF */
2860 .driver_data = (unsigned long) &efx_hunt_a0_vf_nic_type},
3b06a00e
MW		 2861 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0923), /* SFC9140 PF */
2862 .driver_data = (unsigned long) &efx_hunt_a0_nic_type},
dd248f1b
BK		 2863 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x1923), /* SFC9140 VF */
2864 .driver_data = (unsigned long) &efx_hunt_a0_vf_nic_type},
2865 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0a03), /* SFC9220 PF */
2866 .driver_data = (unsigned long) &efx_hunt_a0_nic_type},
2867 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x1a03), /* SFC9220 VF */
2868 .driver_data = (unsigned long) &efx_hunt_a0_vf_nic_type},
8ceee660
BH		 2869 {0} /* end of list */
2870};
2871
2872/**************************************************************************
2873 *
3759433d 2874 * Dummy PHY/MAC operations
8ceee660 2875 *
01aad7b6 2876 * Can be used for some unimplemented operations
8ceee660
BH		 2877 * Needed so all function pointers are valid and do not have to be tested
2878 * before use
2879 *
2880 **************************************************************************/
2881int efx_port_dummy_op_int(struct efx_nic *efx)
2882{
2883 return 0;
2884}
2885void efx_port_dummy_op_void(struct efx_nic *efx) {}
d215697f 2886
2887static bool efx_port_dummy_op_poll(struct efx_nic *efx)
fdaa9aed
SH		 2888{
2889 return false;
2890}
8ceee660 2891
6c8c2513 2892static const struct efx_phy_operations efx_dummy_phy_operations = {
8ceee660 2893 .init = efx_port_dummy_op_int,
d3245b28 2894 .reconfigure = efx_port_dummy_op_int,
fdaa9aed 2895 .poll = efx_port_dummy_op_poll,
8ceee660 2896 .fini = efx_port_dummy_op_void,
8ceee660
BH		 2897};
2898
8ceee660
BH		 2899/**************************************************************************
2900 *
2901 * Data housekeeping
2902 *
2903 **************************************************************************/
2904
2905/* This zeroes out and then fills in the invariants in a struct
2906 * efx_nic (including all sub-structures).
2907 */
adeb15aa 2908static int efx_init_struct(struct efx_nic *efx,
8ceee660
BH		 2909 struct pci_dev *pci_dev, struct net_device *net_dev)
2910{
4642610c 2911 int i;
8ceee660
BH		 2912
2913 /* Initialise common structures */
0bcf4a64
BH		 2914 INIT_LIST_HEAD(&efx->node);
2915 INIT_LIST_HEAD(&efx->secondary_list);
8ceee660 2916 spin_lock_init(&efx->biu_lock);
76884835
BH		 2917#ifdef CONFIG_SFC_MTD
2918 INIT_LIST_HEAD(&efx->mtd_list);
2919#endif
8ceee660
BH		 2920 INIT_WORK(&efx->reset_work, efx_reset_work);
2921 INIT_DELAYED_WORK(&efx->monitor_work, efx_monitor);
dd40781e 2922 INIT_DELAYED_WORK(&efx->selftest_work, efx_selftest_async_work);
8ceee660 2923 efx->pci_dev = pci_dev;
62776d03 2924 efx->msg_enable = debug;
f16aeea0 2925 efx->state = STATE_UNINIT;
8ceee660 2926 strlcpy(efx->name, pci_name(pci_dev), sizeof(efx->name));
8ceee660
BH		 2927
2928 efx->net_dev = net_dev;
43a3739d 2929 efx->rx_prefix_size = efx->type->rx_prefix_size;
2ec03014
AR		 2930 efx->rx_ip_align =
2931 NET_IP_ALIGN ? (efx->rx_prefix_size + NET_IP_ALIGN) % 4 : 0;
43a3739d
JC		 2932 efx->rx_packet_hash_offset =
2933 efx->type->rx_hash_offset - efx->type->rx_prefix_size;
bd9a265d
JC		 2934 efx->rx_packet_ts_offset =
2935 efx->type->rx_ts_offset - efx->type->rx_prefix_size;
8ceee660
BH		 2936 spin_lock_init(&efx->stats_lock);
2937 mutex_init(&efx->mac_lock);
2938 efx->phy_op = &efx_dummy_phy_operations;
68e7f45e 2939 efx->mdio.dev = net_dev;
766ca0fa 2940 INIT_WORK(&efx->mac_work, efx_mac_work);
9f2cb71c 2941 init_waitqueue_head(&efx->flush_wq);
8ceee660
BH		 2942
2943 for (i = 0; i < EFX_MAX_CHANNELS; i++) {
4642610c
BH		 2944 efx->channel[i] = efx_alloc_channel(efx, i, NULL);
2945 if (!efx->channel[i])
2946 goto fail;
d8291187
BH		 2947 efx->msi_context[i].efx = efx;
2948 efx->msi_context[i].index = i;
8ceee660
BH		 2949 }
2950
8ceee660
BH		 2951 /* Higher numbered interrupt modes are less capable! */
2952 efx->interrupt_mode = max(efx->type->max_interrupt_mode,
2953 interrupt_mode);
2954
6977dc63
BH		 2955 /* Would be good to use the net_dev name, but we're too early */
2956 snprintf(efx->workqueue_name, sizeof(efx->workqueue_name), "sfc%s",
2957 pci_name(pci_dev));
2958 efx->workqueue = create_singlethread_workqueue(efx->workqueue_name);
1ab00629 2959 if (!efx->workqueue)
4642610c 2960 goto fail;
8d9853d9 2961
8ceee660 2962 return 0;
4642610c
BH		 2963
2964fail:
2965 efx_fini_struct(efx);
2966 return -ENOMEM;
8ceee660
BH		 2967}
2968
2969static void efx_fini_struct(struct efx_nic *efx)
2970{
8313aca3
BH		 2971 int i;
2972
2973 for (i = 0; i < EFX_MAX_CHANNELS; i++)
2974 kfree(efx->channel[i]);
2975
ef215e64
BH		 2976 kfree(efx->vpd_sn);
2977
8ceee660
BH		 2978 if (efx->workqueue) {
2979 destroy_workqueue(efx->workqueue);
2980 efx->workqueue = NULL;
2981 }
2982}
2983
e4d112e4
EC		 2984void efx_update_sw_stats(struct efx_nic *efx, u64 *stats)
2985{
2986 u64 n_rx_nodesc_trunc = 0;
2987 struct efx_channel *channel;
2988
2989 efx_for_each_channel(channel, efx)
2990 n_rx_nodesc_trunc += channel->n_rx_nodesc_trunc;
2991 stats[GENERIC_STAT_rx_nodesc_trunc] = n_rx_nodesc_trunc;
2992 stats[GENERIC_STAT_rx_noskb_drops] = atomic_read(&efx->n_rx_noskb_drops);
2993}
2994
8ceee660
BH		 2995/**************************************************************************
2996 *
2997 * PCI interface
2998 *
2999 **************************************************************************/
3000
3001/* Main body of final NIC shutdown code
3002 * This is called only at module unload (or hotplug removal).
3003 */
3004static void efx_pci_remove_main(struct efx_nic *efx)
3005{
7153f623
BH		 3006 /* Flush reset_work. It can no longer be scheduled since we
3007 * are not READY.
3008 */
3009 BUG_ON(efx->state == STATE_READY);
3010 cancel_work_sync(&efx->reset_work);
3011
d8291187 3012 efx_disable_interrupts(efx);
152b6a62 3013 efx_nic_fini_interrupt(efx);
8ceee660 3014 efx_fini_port(efx);
ef2b90ee 3015 efx->type->fini(efx);
8ceee660
BH		 3016 efx_fini_napi(efx);
3017 efx_remove_all(efx);
3018}
3019
3020/* Final NIC shutdown
2a3fc311
DP		 3021 * This is called only at module unload (or hotplug removal). A PF can call
3022 * this on its VFs to ensure they are unbound first.
8ceee660
BH		 3023 */
3024static void efx_pci_remove(struct pci_dev *pci_dev)
3025{
3026 struct efx_nic *efx;
3027
3028 efx = pci_get_drvdata(pci_dev);
3029 if (!efx)
3030 return;
3031
3032 /* Mark the NIC as fini, then stop the interface */
3033 rtnl_lock();
0bcf4a64 3034 efx_dissociate(efx);
8ceee660 3035 dev_close(efx->net_dev);
d8291187 3036 efx_disable_interrupts(efx);
ea6bb99e 3037 efx->state = STATE_UNINIT;
8ceee660
BH		 3038 rtnl_unlock();
3039
7fa8d547
SS		 3040 if (efx->type->sriov_fini)
3041 efx->type->sriov_fini(efx);
3042
8ceee660
BH		 3043 efx_unregister_netdev(efx);
3044
7dde596e
BH		 3045 efx_mtd_remove(efx);
3046
8ceee660
BH		 3047 efx_pci_remove_main(efx);
3048
8ceee660 3049 efx_fini_io(efx);
62776d03 3050 netif_dbg(efx, drv, efx->net_dev, "shutdown successful\n");
8ceee660 3051
8ceee660
BH		 3052 efx_fini_struct(efx);
3053 free_netdev(efx->net_dev);
626950db
AR		 3054
3055 pci_disable_pcie_error_reporting(pci_dev);
8ceee660
BH		 3056};
3057
460eeaa0
BH		 3058/* NIC VPD information
3059 * Called during probe to display the part number of the
3060 * installed NIC. VPD is potentially very large but this should
3061 * always appear within the first 512 bytes.
3062 */
3063#define SFC_VPD_LEN 512
ef215e64 3064static void efx_probe_vpd_strings(struct efx_nic *efx)
460eeaa0
BH		 3065{
3066 struct pci_dev *dev = efx->pci_dev;
3067 char vpd_data[SFC_VPD_LEN];
3068 ssize_t vpd_size;
ef215e64 3069 int ro_start, ro_size, i, j;
460eeaa0
BH		 3070
3071 /* Get the vpd data from the device */
3072 vpd_size = pci_read_vpd(dev, 0, sizeof(vpd_data), vpd_data);
3073 if (vpd_size <= 0) {
3074 netif_err(efx, drv, efx->net_dev, "Unable to read VPD\n");
3075 return;
3076 }
3077
3078 /* Get the Read only section */
ef215e64
BH		 3079 ro_start = pci_vpd_find_tag(vpd_data, 0, vpd_size, PCI_VPD_LRDT_RO_DATA);
3080 if (ro_start < 0) {
460eeaa0
BH		 3081 netif_err(efx, drv, efx->net_dev, "VPD Read-only not found\n");
3082 return;
3083 }
3084
ef215e64
BH		 3085 ro_size = pci_vpd_lrdt_size(&vpd_data[ro_start]);
3086 j = ro_size;
3087 i = ro_start + PCI_VPD_LRDT_TAG_SIZE;
460eeaa0
BH		 3088 if (i + j > vpd_size)
3089 j = vpd_size - i;
3090
3091 /* Get the Part number */
3092 i = pci_vpd_find_info_keyword(vpd_data, i, j, "PN");
3093 if (i < 0) {
3094 netif_err(efx, drv, efx->net_dev, "Part number not found\n");
3095 return;
3096 }
3097
3098 j = pci_vpd_info_field_size(&vpd_data[i]);
3099 i += PCI_VPD_INFO_FLD_HDR_SIZE;
3100 if (i + j > vpd_size) {
3101 netif_err(efx, drv, efx->net_dev, "Incomplete part number\n");
3102 return;
3103 }
3104
3105 netif_info(efx, drv, efx->net_dev,
3106 "Part Number : %.*s\n", j, &vpd_data[i]);
ef215e64
BH		 3107
3108 i = ro_start + PCI_VPD_LRDT_TAG_SIZE;
3109 j = ro_size;
3110 i = pci_vpd_find_info_keyword(vpd_data, i, j, "SN");
3111 if (i < 0) {
3112 netif_err(efx, drv, efx->net_dev, "Serial number not found\n");
3113 return;
3114 }
3115
3116 j = pci_vpd_info_field_size(&vpd_data[i]);
3117 i += PCI_VPD_INFO_FLD_HDR_SIZE;
3118 if (i + j > vpd_size) {
3119 netif_err(efx, drv, efx->net_dev, "Incomplete serial number\n");
3120 return;
3121 }
3122
3123 efx->vpd_sn = kmalloc(j + 1, GFP_KERNEL);
3124 if (!efx->vpd_sn)
3125 return;
3126
3127 snprintf(efx->vpd_sn, j + 1, "%s", &vpd_data[i]);
460eeaa0
BH		 3128}
3129
3130
8ceee660
BH		 3131/* Main body of NIC initialisation
3132 * This is called at module load (or hotplug insertion, theoretically).
3133 */
3134static int efx_pci_probe_main(struct efx_nic *efx)
3135{
3136 int rc;
3137
3138 /* Do start-of-day initialisation */
3139 rc = efx_probe_all(efx);
3140 if (rc)
3141 goto fail1;
3142
e8f14992 3143 efx_init_napi(efx);
8ceee660 3144
ef2b90ee 3145 rc = efx->type->init(efx);
8ceee660 3146 if (rc) {
62776d03
BH		 3147 netif_err(efx, probe, efx->net_dev,
3148 "failed to initialise NIC\n");
278c0621 3149 goto fail3;
8ceee660
BH		 3150 }
3151
3152 rc = efx_init_port(efx);
3153 if (rc) {
62776d03
BH		 3154 netif_err(efx, probe, efx->net_dev,
3155 "failed to initialise port\n");
278c0621 3156 goto fail4;
8ceee660
BH		 3157 }
3158
152b6a62 3159 rc = efx_nic_init_interrupt(efx);
8ceee660 3160 if (rc)
278c0621 3161 goto fail5;
261e4d96
JC		 3162 rc = efx_enable_interrupts(efx);
3163 if (rc)
3164 goto fail6;
8ceee660
BH		 3165
3166 return 0;
3167
261e4d96
JC		 3168 fail6:
3169 efx_nic_fini_interrupt(efx);
278c0621 3170 fail5:
8ceee660 3171 efx_fini_port(efx);
8ceee660 3172 fail4:
ef2b90ee 3173 efx->type->fini(efx);
8ceee660
BH		 3174 fail3:
3175 efx_fini_napi(efx);
8ceee660
BH		 3176 efx_remove_all(efx);
3177 fail1:
3178 return rc;
3179}
3180
3181/* NIC initialisation
3182 *
3183 * This is called at module load (or hotplug insertion,
73ba7b68 3184 * theoretically). It sets up PCI mappings, resets the NIC,
8ceee660
BH		 3185 * sets up and registers the network devices with the kernel and hooks
3186 * the interrupt service routine. It does not prepare the device for
3187 * transmission; this is left to the first time one of the network
3188 * interfaces is brought up (i.e. efx_net_open).
3189 */
87d1fc11 3190static int efx_pci_probe(struct pci_dev *pci_dev,
1dd06ae8 3191 const struct pci_device_id *entry)
8ceee660 3192{
8ceee660
BH		 3193 struct net_device *net_dev;
3194 struct efx_nic *efx;
fadac6aa 3195 int rc;
8ceee660
BH		 3196
3197 /* Allocate and initialise a struct net_device and struct efx_nic */
94b274bf
BH		 3198 net_dev = alloc_etherdev_mqs(sizeof(*efx), EFX_MAX_CORE_TX_QUEUES,
3199 EFX_MAX_RX_QUEUES);
8ceee660
BH		 3200 if (!net_dev)
3201 return -ENOMEM;
adeb15aa
BH		 3202 efx = netdev_priv(net_dev);
3203 efx->type = (const struct efx_nic_type *) entry->driver_data;
ebfcd0fd 3204 efx->fixed_features |= NETIF_F_HIGHDMA;
eb7cfd8c 3205
8ceee660 3206 pci_set_drvdata(pci_dev, efx);
62776d03 3207 SET_NETDEV_DEV(net_dev, &pci_dev->dev);
adeb15aa 3208 rc = efx_init_struct(efx, pci_dev, net_dev);
8ceee660
BH		 3209 if (rc)
3210 goto fail1;
3211
62776d03 3212 netif_info(efx, probe, efx->net_dev,
ff79c8ac 3213 "Solarflare NIC detected\n");
8ceee660 3214
6f7f8aa6
SS		 3215 if (!efx->type->is_vf)
3216 efx_probe_vpd_strings(efx);
460eeaa0 3217
8ceee660
BH		 3218 /* Set up basic I/O (BAR mappings etc) */
3219 rc = efx_init_io(efx);
3220 if (rc)
3221 goto fail2;
3222
fadac6aa 3223 rc = efx_pci_probe_main(efx);
fadac6aa
BH		 3224 if (rc)
3225 goto fail3;
8ceee660 3226
46d1efd8
EC		 3227 net_dev->features |= (efx->type->offload_features | NETIF_F_SG |
3228 NETIF_F_TSO | NETIF_F_RXCSUM);
3229 if (efx->type->offload_features & (NETIF_F_IPV6_CSUM | NETIF_F_HW_CSUM))
3230 net_dev->features |= NETIF_F_TSO6;
3231 /* Check whether device supports TSO */
3232 if (!efx->type->tso_versions || !efx->type->tso_versions(efx))
3233 net_dev->features &= ~NETIF_F_ALL_TSO;
3234 /* Mask for features that also apply to VLAN devices */
3235 net_dev->vlan_features |= (NETIF_F_HW_CSUM | NETIF_F_SG |
3236 NETIF_F_HIGHDMA | NETIF_F_ALL_TSO |
3237 NETIF_F_RXCSUM);
3238
3239 net_dev->hw_features = net_dev->features & ~efx->fixed_features;
3240
3241 /* Disable VLAN filtering by default. It may be enforced if
3242 * the feature is fixed (i.e. VLAN filters are required to
3243 * receive VLAN tagged packets due to vPort restrictions).
3244 */
3245 net_dev->features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
3246 net_dev->features |= efx->fixed_features;
3247
8ceee660
BH		 3248 rc = efx_register_netdev(efx);
3249 if (rc)
fadac6aa 3250 goto fail4;
8ceee660 3251
7fa8d547
SS		 3252 if (efx->type->sriov_init) {
3253 rc = efx->type->sriov_init(efx);
3254 if (rc)
3255 netif_err(efx, probe, efx->net_dev,
3256 "SR-IOV can't be enabled rc %d\n", rc);
3257 }
cd2d5b52 3258
62776d03 3259 netif_dbg(efx, probe, efx->net_dev, "initialisation successful\n");
a5211bb5 3260
7c43161c 3261 /* Try to create MTDs, but allow this to fail */
a5211bb5 3262 rtnl_lock();
7c43161c 3263 rc = efx_mtd_probe(efx);
a5211bb5 3264 rtnl_unlock();
09a04204 3265 if (rc && rc != -EPERM)
7c43161c
BH		 3266 netif_warn(efx, probe, efx->net_dev,
3267 "failed to create MTDs (%d)\n", rc);
3268
626950db
AR		 3269 rc = pci_enable_pcie_error_reporting(pci_dev);
3270 if (rc && rc != -EINVAL)
09a04204
BK		 3271 netif_notice(efx, probe, efx->net_dev,
3272 "PCIE error reporting unavailable (%d).\n",
3273 rc);
626950db 3274
8ceee660
BH		 3275 return 0;
3276
8ceee660 3277 fail4:
fadac6aa 3278 efx_pci_remove_main(efx);
8ceee660
BH		 3279 fail3:
3280 efx_fini_io(efx);
3281 fail2:
3282 efx_fini_struct(efx);
3283 fail1:
5e2a911c 3284 WARN_ON(rc > 0);
62776d03 3285 netif_dbg(efx, drv, efx->net_dev, "initialisation failed. rc=%d\n", rc);
8ceee660
BH		 3286 free_netdev(net_dev);
3287 return rc;
3288}
3289
834e23dd
SS		 3290/* efx_pci_sriov_configure returns the actual number of Virtual Functions
3291 * enabled on success
3292 */
3293#ifdef CONFIG_SFC_SRIOV
3294static int efx_pci_sriov_configure(struct pci_dev *dev, int num_vfs)
3295{
3296 int rc;
3297 struct efx_nic *efx = pci_get_drvdata(dev);
3298
3299 if (efx->type->sriov_configure) {
3300 rc = efx->type->sriov_configure(efx, num_vfs);
3301 if (rc)
3302 return rc;
3303 else
3304 return num_vfs;
3305 } else
3306 return -EOPNOTSUPP;
3307}
3308#endif
3309
89c758fa
BH		 3310static int efx_pm_freeze(struct device *dev)
3311{
3312 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
3313
61da026d
BH		 3314 rtnl_lock();
3315
6032fb56
BH		 3316 if (efx->state != STATE_DISABLED) {
3317 efx->state = STATE_UNINIT;
89c758fa 3318
c2f3b8e3 3319 efx_device_detach_sync(efx);
89c758fa 3320
6032fb56 3321 efx_stop_all(efx);
d8291187 3322 efx_disable_interrupts(efx);
6032fb56 3323 }
89c758fa 3324
61da026d
BH		 3325 rtnl_unlock();
3326
89c758fa
BH		 3327 return 0;
3328}
3329
3330static int efx_pm_thaw(struct device *dev)
3331{
261e4d96 3332 int rc;
89c758fa
BH		 3333 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
3334
61da026d
BH		 3335 rtnl_lock();
3336
6032fb56 3337 if (efx->state != STATE_DISABLED) {
261e4d96
JC		 3338 rc = efx_enable_interrupts(efx);
3339 if (rc)
3340 goto fail;
89c758fa 3341
6032fb56
BH		 3342 mutex_lock(&efx->mac_lock);
3343 efx->phy_op->reconfigure(efx);
3344 mutex_unlock(&efx->mac_lock);
89c758fa 3345
6032fb56 3346 efx_start_all(efx);
89c758fa 3347
6032fb56 3348 netif_device_attach(efx->net_dev);
89c758fa 3349
6032fb56 3350 efx->state = STATE_READY;
89c758fa 3351
6032fb56
BH		 3352 efx->type->resume_wol(efx);
3353 }
89c758fa 3354
61da026d
BH		 3355 rtnl_unlock();
3356
319ba649
SH		 3357 /* Reschedule any quenched resets scheduled during efx_pm_freeze() */
3358 queue_work(reset_workqueue, &efx->reset_work);
3359
89c758fa 3360 return 0;
261e4d96
JC		 3361
3362fail:
3363 rtnl_unlock();
3364
3365 return rc;
89c758fa
BH		 3366}
3367
3368static int efx_pm_poweroff(struct device *dev)
3369{
3370 struct pci_dev *pci_dev = to_pci_dev(dev);
3371 struct efx_nic *efx = pci_get_drvdata(pci_dev);
3372
3373 efx->type->fini(efx);
3374
a7d529ae 3375 efx->reset_pending = 0;
89c758fa
BH		 3376
3377 pci_save_state(pci_dev);
3378 return pci_set_power_state(pci_dev, PCI_D3hot);
3379}
3380
3381/* Used for both resume and restore */
3382static int efx_pm_resume(struct device *dev)
3383{
3384 struct pci_dev *pci_dev = to_pci_dev(dev);
3385 struct efx_nic *efx = pci_get_drvdata(pci_dev);
3386 int rc;
3387
3388 rc = pci_set_power_state(pci_dev, PCI_D0);
3389 if (rc)
3390 return rc;
3391 pci_restore_state(pci_dev);
3392 rc = pci_enable_device(pci_dev);
3393 if (rc)
3394 return rc;
3395 pci_set_master(efx->pci_dev);
3396 rc = efx->type->reset(efx, RESET_TYPE_ALL);
3397 if (rc)
3398 return rc;
3399 rc = efx->type->init(efx);
3400 if (rc)
3401 return rc;
261e4d96
JC		 3402 rc = efx_pm_thaw(dev);
3403 return rc;
89c758fa
BH		 3404}
3405
3406static int efx_pm_suspend(struct device *dev)
3407{
3408 int rc;
3409
3410 efx_pm_freeze(dev);
3411 rc = efx_pm_poweroff(dev);
3412 if (rc)
3413 efx_pm_resume(dev);
3414 return rc;
3415}
3416
18e83e4c 3417static const struct dev_pm_ops efx_pm_ops = {
89c758fa
BH		 3418 .suspend = efx_pm_suspend,
3419 .resume = efx_pm_resume,
3420 .freeze = efx_pm_freeze,
3421 .thaw = efx_pm_thaw,
3422 .poweroff = efx_pm_poweroff,
3423 .restore = efx_pm_resume,
3424};
3425
626950db
AR		 3426/* A PCI error affecting this device was detected.
3427 * At this point MMIO and DMA may be disabled.
3428 * Stop the software path and request a slot reset.
3429 */
debd0034 3430static pci_ers_result_t efx_io_error_detected(struct pci_dev *pdev,
3431 enum pci_channel_state state)
626950db
AR		 3432{
3433 pci_ers_result_t status = PCI_ERS_RESULT_RECOVERED;
3434 struct efx_nic *efx = pci_get_drvdata(pdev);
3435
3436 if (state == pci_channel_io_perm_failure)
3437 return PCI_ERS_RESULT_DISCONNECT;
3438
3439 rtnl_lock();
3440
3441 if (efx->state != STATE_DISABLED) {
3442 efx->state = STATE_RECOVERY;
3443 efx->reset_pending = 0;
3444
3445 efx_device_detach_sync(efx);
3446
3447 efx_stop_all(efx);
d8291187 3448 efx_disable_interrupts(efx);
626950db
AR		 3449
3450 status = PCI_ERS_RESULT_NEED_RESET;
3451 } else {
3452 /* If the interface is disabled we don't want to do anything
3453 * with it.
3454 */
3455 status = PCI_ERS_RESULT_RECOVERED;
3456 }
3457
3458 rtnl_unlock();
3459
3460 pci_disable_device(pdev);
3461
3462 return status;
3463}
3464
dbedd44e 3465/* Fake a successful reset, which will be performed later in efx_io_resume. */
debd0034 3466static pci_ers_result_t efx_io_slot_reset(struct pci_dev *pdev)
626950db
AR		 3467{
3468 struct efx_nic *efx = pci_get_drvdata(pdev);
3469 pci_ers_result_t status = PCI_ERS_RESULT_RECOVERED;
3470 int rc;
3471
3472 if (pci_enable_device(pdev)) {
3473 netif_err(efx, hw, efx->net_dev,
3474 "Cannot re-enable PCI device after reset.\n");
3475 status = PCI_ERS_RESULT_DISCONNECT;
3476 }
3477
3478 rc = pci_cleanup_aer_uncorrect_error_status(pdev);
3479 if (rc) {
3480 netif_err(efx, hw, efx->net_dev,
3481 "pci_cleanup_aer_uncorrect_error_status failed (%d)\n", rc);
3482 /* Non-fatal error. Continue. */
3483 }
3484
3485 return status;
3486}
3487
3488/* Perform the actual reset and resume I/O operations. */
3489static void efx_io_resume(struct pci_dev *pdev)
3490{
3491 struct efx_nic *efx = pci_get_drvdata(pdev);
3492 int rc;
3493
3494 rtnl_lock();
3495
3496 if (efx->state == STATE_DISABLED)
3497 goto out;
3498
3499 rc = efx_reset(efx, RESET_TYPE_ALL);
3500 if (rc) {
3501 netif_err(efx, hw, efx->net_dev,
3502 "efx_reset failed after PCI error (%d)\n", rc);
3503 } else {
3504 efx->state = STATE_READY;
3505 netif_dbg(efx, hw, efx->net_dev,
3506 "Done resetting and resuming IO after PCI error.\n");
3507 }
3508
3509out:
3510 rtnl_unlock();
3511}
3512
3513/* For simplicity and reliability, we always require a slot reset and try to
3514 * reset the hardware when a pci error affecting the device is detected.
3515 * We leave both the link_reset and mmio_enabled callback unimplemented:
3516 * with our request for slot reset the mmio_enabled callback will never be
3517 * called, and the link_reset callback is not used by AER or EEH mechanisms.
3518 */
c300366b 3519static const struct pci_error_handlers efx_err_handlers = {
626950db
AR		 3520 .error_detected = efx_io_error_detected,
3521 .slot_reset = efx_io_slot_reset,
3522 .resume = efx_io_resume,
3523};
3524
8ceee660 3525static struct pci_driver efx_pci_driver = {
c5d5f5fd 3526 .name = KBUILD_MODNAME,
8ceee660
BH		 3527 .id_table = efx_pci_table,
3528 .probe = efx_pci_probe,
3529 .remove = efx_pci_remove,
89c758fa 3530 .driver.pm = &efx_pm_ops,
626950db 3531 .err_handler = &efx_err_handlers,
834e23dd
SS		 3532#ifdef CONFIG_SFC_SRIOV
3533 .sriov_configure = efx_pci_sriov_configure,
3534#endif
8ceee660
BH		 3535};
3536
3537/**************************************************************************
3538 *
3539 * Kernel module interface
3540 *
3541 *************************************************************************/
3542
3543module_param(interrupt_mode, uint, 0444);
3544MODULE_PARM_DESC(interrupt_mode,
3545 "Interrupt mode (0=>MSIX 1=>MSI 2=>legacy)");
3546
3547static int __init efx_init_module(void)
3548{
3549 int rc;
3550
3551 printk(KERN_INFO "Solarflare NET driver v" EFX_DRIVER_VERSION "\n");
3552
3553 rc = register_netdevice_notifier(&efx_netdev_notifier);
3554 if (rc)
3555 goto err_notifier;
3556
7fa8d547 3557#ifdef CONFIG_SFC_SRIOV
cd2d5b52
BH		 3558 rc = efx_init_sriov();
3559 if (rc)
3560 goto err_sriov;
7fa8d547 3561#endif
cd2d5b52 3562
1ab00629
SH		 3563 reset_workqueue = create_singlethread_workqueue("sfc_reset");
3564 if (!reset_workqueue) {
3565 rc = -ENOMEM;
3566 goto err_reset;
3567 }
8ceee660
BH		 3568
3569 rc = pci_register_driver(&efx_pci_driver);
3570 if (rc < 0)
3571 goto err_pci;
3572
3573 return 0;
3574
3575 err_pci:
1ab00629
SH		 3576 destroy_workqueue(reset_workqueue);
3577 err_reset:
7fa8d547 3578#ifdef CONFIG_SFC_SRIOV
cd2d5b52
BH		 3579 efx_fini_sriov();
3580 err_sriov:
7fa8d547 3581#endif
8ceee660
BH		 3582 unregister_netdevice_notifier(&efx_netdev_notifier);
3583 err_notifier:
3584 return rc;
3585}
3586
3587static void __exit efx_exit_module(void)
3588{
3589 printk(KERN_INFO "Solarflare NET driver unloading\n");
3590
3591 pci_unregister_driver(&efx_pci_driver);
1ab00629 3592 destroy_workqueue(reset_workqueue);
7fa8d547 3593#ifdef CONFIG_SFC_SRIOV
cd2d5b52 3594 efx_fini_sriov();
7fa8d547 3595#endif
8ceee660
BH		 3596 unregister_netdevice_notifier(&efx_netdev_notifier);
3597
3598}
3599
3600module_init(efx_init_module);
3601module_exit(efx_exit_module);
3602
906bb26c
BH		 3603MODULE_AUTHOR("Solarflare Communications and "
3604 "Michael Brown <mbrown@fensystems.co.uk>");
6a350fdb 3605MODULE_DESCRIPTION("Solarflare network driver");
8ceee660
BH		 3606MODULE_LICENSE("GPL");
3607MODULE_DEVICE_TABLE(pci, efx_pci_table);
14077e9e 3608MODULE_VERSION(EFX_DRIVER_VERSION);
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