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8ceee660 BH |
1 | /**************************************************************************** |
2 | * Driver for Solarflare Solarstorm network controllers and boards | |
3 | * Copyright 2005-2006 Fen Systems Ltd. | |
0a6f40c6 | 4 | * Copyright 2005-2011 Solarflare Communications Inc. |
8ceee660 BH |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation, incorporated herein by reference. | |
9 | */ | |
10 | ||
11 | #include <linux/module.h> | |
12 | #include <linux/pci.h> | |
13 | #include <linux/netdevice.h> | |
14 | #include <linux/etherdevice.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/notifier.h> | |
17 | #include <linux/ip.h> | |
18 | #include <linux/tcp.h> | |
19 | #include <linux/in.h> | |
20 | #include <linux/crc32.h> | |
21 | #include <linux/ethtool.h> | |
aa6ef27e | 22 | #include <linux/topology.h> |
5a0e3ad6 | 23 | #include <linux/gfp.h> |
64d8ad6d | 24 | #include <linux/cpu_rmap.h> |
8ceee660 | 25 | #include "net_driver.h" |
8ceee660 | 26 | #include "efx.h" |
744093c9 | 27 | #include "nic.h" |
dd40781e | 28 | #include "selftest.h" |
8ceee660 | 29 | |
8880f4ec | 30 | #include "mcdi.h" |
fd371e32 | 31 | #include "workarounds.h" |
8880f4ec | 32 | |
c459302d BH |
33 | /************************************************************************** |
34 | * | |
35 | * Type name strings | |
36 | * | |
37 | ************************************************************************** | |
38 | */ | |
39 | ||
40 | /* Loopback mode names (see LOOPBACK_MODE()) */ | |
41 | const unsigned int efx_loopback_mode_max = LOOPBACK_MAX; | |
18e83e4c | 42 | const char *const efx_loopback_mode_names[] = { |
c459302d | 43 | [LOOPBACK_NONE] = "NONE", |
e58f69f4 | 44 | [LOOPBACK_DATA] = "DATAPATH", |
c459302d BH |
45 | [LOOPBACK_GMAC] = "GMAC", |
46 | [LOOPBACK_XGMII] = "XGMII", | |
47 | [LOOPBACK_XGXS] = "XGXS", | |
9c636baf BH |
48 | [LOOPBACK_XAUI] = "XAUI", |
49 | [LOOPBACK_GMII] = "GMII", | |
50 | [LOOPBACK_SGMII] = "SGMII", | |
e58f69f4 BH |
51 | [LOOPBACK_XGBR] = "XGBR", |
52 | [LOOPBACK_XFI] = "XFI", | |
53 | [LOOPBACK_XAUI_FAR] = "XAUI_FAR", | |
54 | [LOOPBACK_GMII_FAR] = "GMII_FAR", | |
55 | [LOOPBACK_SGMII_FAR] = "SGMII_FAR", | |
56 | [LOOPBACK_XFI_FAR] = "XFI_FAR", | |
c459302d BH |
57 | [LOOPBACK_GPHY] = "GPHY", |
58 | [LOOPBACK_PHYXS] = "PHYXS", | |
9c636baf BH |
59 | [LOOPBACK_PCS] = "PCS", |
60 | [LOOPBACK_PMAPMD] = "PMA/PMD", | |
e58f69f4 BH |
61 | [LOOPBACK_XPORT] = "XPORT", |
62 | [LOOPBACK_XGMII_WS] = "XGMII_WS", | |
9c636baf | 63 | [LOOPBACK_XAUI_WS] = "XAUI_WS", |
e58f69f4 BH |
64 | [LOOPBACK_XAUI_WS_FAR] = "XAUI_WS_FAR", |
65 | [LOOPBACK_XAUI_WS_NEAR] = "XAUI_WS_NEAR", | |
9c636baf | 66 | [LOOPBACK_GMII_WS] = "GMII_WS", |
e58f69f4 BH |
67 | [LOOPBACK_XFI_WS] = "XFI_WS", |
68 | [LOOPBACK_XFI_WS_FAR] = "XFI_WS_FAR", | |
9c636baf | 69 | [LOOPBACK_PHYXS_WS] = "PHYXS_WS", |
c459302d BH |
70 | }; |
71 | ||
c459302d | 72 | const unsigned int efx_reset_type_max = RESET_TYPE_MAX; |
18e83e4c | 73 | const char *const efx_reset_type_names[] = { |
c459302d BH |
74 | [RESET_TYPE_INVISIBLE] = "INVISIBLE", |
75 | [RESET_TYPE_ALL] = "ALL", | |
76 | [RESET_TYPE_WORLD] = "WORLD", | |
77 | [RESET_TYPE_DISABLE] = "DISABLE", | |
78 | [RESET_TYPE_TX_WATCHDOG] = "TX_WATCHDOG", | |
79 | [RESET_TYPE_INT_ERROR] = "INT_ERROR", | |
80 | [RESET_TYPE_RX_RECOVERY] = "RX_RECOVERY", | |
81 | [RESET_TYPE_RX_DESC_FETCH] = "RX_DESC_FETCH", | |
82 | [RESET_TYPE_TX_DESC_FETCH] = "TX_DESC_FETCH", | |
83 | [RESET_TYPE_TX_SKIP] = "TX_SKIP", | |
8880f4ec | 84 | [RESET_TYPE_MC_FAILURE] = "MC_FAILURE", |
c459302d BH |
85 | }; |
86 | ||
8ceee660 BH |
87 | #define EFX_MAX_MTU (9 * 1024) |
88 | ||
1ab00629 SH |
89 | /* Reset workqueue. If any NIC has a hardware failure then a reset will be |
90 | * queued onto this work queue. This is not a per-nic work queue, because | |
91 | * efx_reset_work() acquires the rtnl lock, so resets are naturally serialised. | |
92 | */ | |
93 | static struct workqueue_struct *reset_workqueue; | |
94 | ||
8ceee660 BH |
95 | /************************************************************************** |
96 | * | |
97 | * Configurable values | |
98 | * | |
99 | *************************************************************************/ | |
100 | ||
8ceee660 BH |
101 | /* |
102 | * Use separate channels for TX and RX events | |
103 | * | |
28b581ab NT |
104 | * Set this to 1 to use separate channels for TX and RX. It allows us |
105 | * to control interrupt affinity separately for TX and RX. | |
8ceee660 | 106 | * |
28b581ab | 107 | * This is only used in MSI-X interrupt mode |
8ceee660 | 108 | */ |
28b581ab | 109 | static unsigned int separate_tx_channels; |
8313aca3 | 110 | module_param(separate_tx_channels, uint, 0444); |
28b581ab NT |
111 | MODULE_PARM_DESC(separate_tx_channels, |
112 | "Use separate channels for TX and RX"); | |
8ceee660 BH |
113 | |
114 | /* This is the weight assigned to each of the (per-channel) virtual | |
115 | * NAPI devices. | |
116 | */ | |
117 | static int napi_weight = 64; | |
118 | ||
119 | /* This is the time (in jiffies) between invocations of the hardware | |
e254c274 BH |
120 | * monitor. On Falcon-based NICs, this will: |
121 | * - Check the on-board hardware monitor; | |
122 | * - Poll the link state and reconfigure the hardware as necessary. | |
8ceee660 | 123 | */ |
d215697f | 124 | static unsigned int efx_monitor_interval = 1 * HZ; |
8ceee660 | 125 | |
8ceee660 BH |
126 | /* Initial interrupt moderation settings. They can be modified after |
127 | * module load with ethtool. | |
128 | * | |
129 | * The default for RX should strike a balance between increasing the | |
130 | * round-trip latency and reducing overhead. | |
131 | */ | |
132 | static unsigned int rx_irq_mod_usec = 60; | |
133 | ||
134 | /* Initial interrupt moderation settings. They can be modified after | |
135 | * module load with ethtool. | |
136 | * | |
137 | * This default is chosen to ensure that a 10G link does not go idle | |
138 | * while a TX queue is stopped after it has become full. A queue is | |
139 | * restarted when it drops below half full. The time this takes (assuming | |
140 | * worst case 3 descriptors per packet and 1024 descriptors) is | |
141 | * 512 / 3 * 1.2 = 205 usec. | |
142 | */ | |
143 | static unsigned int tx_irq_mod_usec = 150; | |
144 | ||
145 | /* This is the first interrupt mode to try out of: | |
146 | * 0 => MSI-X | |
147 | * 1 => MSI | |
148 | * 2 => legacy | |
149 | */ | |
150 | static unsigned int interrupt_mode; | |
151 | ||
152 | /* This is the requested number of CPUs to use for Receive-Side Scaling (RSS), | |
153 | * i.e. the number of CPUs among which we may distribute simultaneous | |
154 | * interrupt handling. | |
155 | * | |
156 | * Cards without MSI-X will only target one CPU via legacy or MSI interrupt. | |
cdb08f8f | 157 | * The default (0) means to assign an interrupt to each core. |
8ceee660 BH |
158 | */ |
159 | static unsigned int rss_cpus; | |
160 | module_param(rss_cpus, uint, 0444); | |
161 | MODULE_PARM_DESC(rss_cpus, "Number of CPUs to use for Receive-Side Scaling"); | |
162 | ||
84ae48fe BH |
163 | static int phy_flash_cfg; |
164 | module_param(phy_flash_cfg, int, 0644); | |
165 | MODULE_PARM_DESC(phy_flash_cfg, "Set PHYs into reflash mode initially"); | |
166 | ||
e7bed9c8 | 167 | static unsigned irq_adapt_low_thresh = 8000; |
6fb70fd1 BH |
168 | module_param(irq_adapt_low_thresh, uint, 0644); |
169 | MODULE_PARM_DESC(irq_adapt_low_thresh, | |
170 | "Threshold score for reducing IRQ moderation"); | |
171 | ||
e7bed9c8 | 172 | static unsigned irq_adapt_high_thresh = 16000; |
6fb70fd1 BH |
173 | module_param(irq_adapt_high_thresh, uint, 0644); |
174 | MODULE_PARM_DESC(irq_adapt_high_thresh, | |
175 | "Threshold score for increasing IRQ moderation"); | |
176 | ||
62776d03 BH |
177 | static unsigned debug = (NETIF_MSG_DRV | NETIF_MSG_PROBE | |
178 | NETIF_MSG_LINK | NETIF_MSG_IFDOWN | | |
179 | NETIF_MSG_IFUP | NETIF_MSG_RX_ERR | | |
180 | NETIF_MSG_TX_ERR | NETIF_MSG_HW); | |
181 | module_param(debug, uint, 0); | |
182 | MODULE_PARM_DESC(debug, "Bitmapped debugging message enable value"); | |
183 | ||
8ceee660 BH |
184 | /************************************************************************** |
185 | * | |
186 | * Utility functions and prototypes | |
187 | * | |
188 | *************************************************************************/ | |
4642610c | 189 | |
7f967c01 BH |
190 | static void efx_start_interrupts(struct efx_nic *efx, bool may_keep_eventq); |
191 | static void efx_stop_interrupts(struct efx_nic *efx, bool may_keep_eventq); | |
192 | static void efx_remove_channel(struct efx_channel *channel); | |
4642610c | 193 | static void efx_remove_channels(struct efx_nic *efx); |
7f967c01 | 194 | static const struct efx_channel_type efx_default_channel_type; |
8ceee660 | 195 | static void efx_remove_port(struct efx_nic *efx); |
7f967c01 | 196 | static void efx_init_napi_channel(struct efx_channel *channel); |
8ceee660 | 197 | static void efx_fini_napi(struct efx_nic *efx); |
e8f14992 | 198 | static void efx_fini_napi_channel(struct efx_channel *channel); |
4642610c BH |
199 | static void efx_fini_struct(struct efx_nic *efx); |
200 | static void efx_start_all(struct efx_nic *efx); | |
201 | static void efx_stop_all(struct efx_nic *efx); | |
8ceee660 BH |
202 | |
203 | #define EFX_ASSERT_RESET_SERIALISED(efx) \ | |
204 | do { \ | |
f16aeea0 | 205 | if ((efx->state == STATE_READY) || \ |
332c1ce9 | 206 | (efx->state == STATE_DISABLED)) \ |
8ceee660 BH |
207 | ASSERT_RTNL(); \ |
208 | } while (0) | |
209 | ||
8b7325b4 BH |
210 | static int efx_check_disabled(struct efx_nic *efx) |
211 | { | |
212 | if (efx->state == STATE_DISABLED) { | |
213 | netif_err(efx, drv, efx->net_dev, | |
214 | "device is disabled due to earlier errors\n"); | |
215 | return -EIO; | |
216 | } | |
217 | return 0; | |
218 | } | |
219 | ||
8ceee660 BH |
220 | /************************************************************************** |
221 | * | |
222 | * Event queue processing | |
223 | * | |
224 | *************************************************************************/ | |
225 | ||
226 | /* Process channel's event queue | |
227 | * | |
228 | * This function is responsible for processing the event queue of a | |
229 | * single channel. The caller must guarantee that this function will | |
230 | * never be concurrently called more than once on the same channel, | |
231 | * though different channels may be being processed concurrently. | |
232 | */ | |
fa236e18 | 233 | static int efx_process_channel(struct efx_channel *channel, int budget) |
8ceee660 | 234 | { |
fa236e18 | 235 | int spent; |
8ceee660 | 236 | |
9f2cb71c | 237 | if (unlikely(!channel->enabled)) |
42cbe2d7 | 238 | return 0; |
8ceee660 | 239 | |
fa236e18 | 240 | spent = efx_nic_process_eventq(channel, budget); |
d9ab7007 BH |
241 | if (spent && efx_channel_has_rx_queue(channel)) { |
242 | struct efx_rx_queue *rx_queue = | |
243 | efx_channel_get_rx_queue(channel); | |
244 | ||
245 | /* Deliver last RX packet. */ | |
246 | if (channel->rx_pkt) { | |
247 | __efx_rx_packet(channel, channel->rx_pkt); | |
248 | channel->rx_pkt = NULL; | |
249 | } | |
9f2cb71c BH |
250 | if (rx_queue->enabled) { |
251 | efx_rx_strategy(channel); | |
252 | efx_fast_push_rx_descriptors(rx_queue); | |
253 | } | |
8ceee660 BH |
254 | } |
255 | ||
fa236e18 | 256 | return spent; |
8ceee660 BH |
257 | } |
258 | ||
259 | /* Mark channel as finished processing | |
260 | * | |
261 | * Note that since we will not receive further interrupts for this | |
262 | * channel before we finish processing and call the eventq_read_ack() | |
263 | * method, there is no need to use the interrupt hold-off timers. | |
264 | */ | |
265 | static inline void efx_channel_processed(struct efx_channel *channel) | |
266 | { | |
5b9e207c BH |
267 | /* The interrupt handler for this channel may set work_pending |
268 | * as soon as we acknowledge the events we've seen. Make sure | |
269 | * it's cleared before then. */ | |
dc8cfa55 | 270 | channel->work_pending = false; |
5b9e207c BH |
271 | smp_wmb(); |
272 | ||
152b6a62 | 273 | efx_nic_eventq_read_ack(channel); |
8ceee660 BH |
274 | } |
275 | ||
276 | /* NAPI poll handler | |
277 | * | |
278 | * NAPI guarantees serialisation of polls of the same device, which | |
279 | * provides the guarantee required by efx_process_channel(). | |
280 | */ | |
281 | static int efx_poll(struct napi_struct *napi, int budget) | |
282 | { | |
283 | struct efx_channel *channel = | |
284 | container_of(napi, struct efx_channel, napi_str); | |
62776d03 | 285 | struct efx_nic *efx = channel->efx; |
fa236e18 | 286 | int spent; |
8ceee660 | 287 | |
62776d03 BH |
288 | netif_vdbg(efx, intr, efx->net_dev, |
289 | "channel %d NAPI poll executing on CPU %d\n", | |
290 | channel->channel, raw_smp_processor_id()); | |
8ceee660 | 291 | |
fa236e18 | 292 | spent = efx_process_channel(channel, budget); |
8ceee660 | 293 | |
fa236e18 | 294 | if (spent < budget) { |
9d9a6973 | 295 | if (efx_channel_has_rx_queue(channel) && |
6fb70fd1 BH |
296 | efx->irq_rx_adaptive && |
297 | unlikely(++channel->irq_count == 1000)) { | |
6fb70fd1 BH |
298 | if (unlikely(channel->irq_mod_score < |
299 | irq_adapt_low_thresh)) { | |
0d86ebd8 BH |
300 | if (channel->irq_moderation > 1) { |
301 | channel->irq_moderation -= 1; | |
ef2b90ee | 302 | efx->type->push_irq_moderation(channel); |
0d86ebd8 | 303 | } |
6fb70fd1 BH |
304 | } else if (unlikely(channel->irq_mod_score > |
305 | irq_adapt_high_thresh)) { | |
0d86ebd8 BH |
306 | if (channel->irq_moderation < |
307 | efx->irq_rx_moderation) { | |
308 | channel->irq_moderation += 1; | |
ef2b90ee | 309 | efx->type->push_irq_moderation(channel); |
0d86ebd8 | 310 | } |
6fb70fd1 | 311 | } |
6fb70fd1 BH |
312 | channel->irq_count = 0; |
313 | channel->irq_mod_score = 0; | |
314 | } | |
315 | ||
64d8ad6d BH |
316 | efx_filter_rfs_expire(channel); |
317 | ||
8ceee660 | 318 | /* There is no race here; although napi_disable() will |
288379f0 | 319 | * only wait for napi_complete(), this isn't a problem |
8ceee660 BH |
320 | * since efx_channel_processed() will have no effect if |
321 | * interrupts have already been disabled. | |
322 | */ | |
288379f0 | 323 | napi_complete(napi); |
8ceee660 BH |
324 | efx_channel_processed(channel); |
325 | } | |
326 | ||
fa236e18 | 327 | return spent; |
8ceee660 BH |
328 | } |
329 | ||
330 | /* Process the eventq of the specified channel immediately on this CPU | |
331 | * | |
332 | * Disable hardware generated interrupts, wait for any existing | |
333 | * processing to finish, then directly poll (and ack ) the eventq. | |
334 | * Finally reenable NAPI and interrupts. | |
335 | * | |
d4fabcc8 BH |
336 | * This is for use only during a loopback self-test. It must not |
337 | * deliver any packets up the stack as this can result in deadlock. | |
8ceee660 BH |
338 | */ |
339 | void efx_process_channel_now(struct efx_channel *channel) | |
340 | { | |
341 | struct efx_nic *efx = channel->efx; | |
342 | ||
8313aca3 | 343 | BUG_ON(channel->channel >= efx->n_channels); |
8ceee660 | 344 | BUG_ON(!channel->enabled); |
d4fabcc8 | 345 | BUG_ON(!efx->loopback_selftest); |
8ceee660 BH |
346 | |
347 | /* Disable interrupts and wait for ISRs to complete */ | |
152b6a62 | 348 | efx_nic_disable_interrupts(efx); |
94dec6a2 | 349 | if (efx->legacy_irq) { |
8ceee660 | 350 | synchronize_irq(efx->legacy_irq); |
94dec6a2 BH |
351 | efx->legacy_irq_enabled = false; |
352 | } | |
64ee3120 | 353 | if (channel->irq) |
8ceee660 BH |
354 | synchronize_irq(channel->irq); |
355 | ||
356 | /* Wait for any NAPI processing to complete */ | |
357 | napi_disable(&channel->napi_str); | |
358 | ||
359 | /* Poll the channel */ | |
ecc910f5 | 360 | efx_process_channel(channel, channel->eventq_mask + 1); |
8ceee660 BH |
361 | |
362 | /* Ack the eventq. This may cause an interrupt to be generated | |
363 | * when they are reenabled */ | |
364 | efx_channel_processed(channel); | |
365 | ||
366 | napi_enable(&channel->napi_str); | |
94dec6a2 BH |
367 | if (efx->legacy_irq) |
368 | efx->legacy_irq_enabled = true; | |
152b6a62 | 369 | efx_nic_enable_interrupts(efx); |
8ceee660 BH |
370 | } |
371 | ||
372 | /* Create event queue | |
373 | * Event queue memory allocations are done only once. If the channel | |
374 | * is reset, the memory buffer will be reused; this guards against | |
375 | * errors during channel reset and also simplifies interrupt handling. | |
376 | */ | |
377 | static int efx_probe_eventq(struct efx_channel *channel) | |
378 | { | |
ecc910f5 SH |
379 | struct efx_nic *efx = channel->efx; |
380 | unsigned long entries; | |
381 | ||
86ee5302 | 382 | netif_dbg(efx, probe, efx->net_dev, |
62776d03 | 383 | "chan %d create event queue\n", channel->channel); |
8ceee660 | 384 | |
ecc910f5 SH |
385 | /* Build an event queue with room for one event per tx and rx buffer, |
386 | * plus some extra for link state events and MCDI completions. */ | |
387 | entries = roundup_pow_of_two(efx->rxq_entries + efx->txq_entries + 128); | |
388 | EFX_BUG_ON_PARANOID(entries > EFX_MAX_EVQ_SIZE); | |
389 | channel->eventq_mask = max(entries, EFX_MIN_EVQ_SIZE) - 1; | |
390 | ||
152b6a62 | 391 | return efx_nic_probe_eventq(channel); |
8ceee660 BH |
392 | } |
393 | ||
394 | /* Prepare channel's event queue */ | |
bc3c90a2 | 395 | static void efx_init_eventq(struct efx_channel *channel) |
8ceee660 | 396 | { |
62776d03 BH |
397 | netif_dbg(channel->efx, drv, channel->efx->net_dev, |
398 | "chan %d init event queue\n", channel->channel); | |
8ceee660 BH |
399 | |
400 | channel->eventq_read_ptr = 0; | |
401 | ||
152b6a62 | 402 | efx_nic_init_eventq(channel); |
8ceee660 BH |
403 | } |
404 | ||
9f2cb71c BH |
405 | /* Enable event queue processing and NAPI */ |
406 | static void efx_start_eventq(struct efx_channel *channel) | |
407 | { | |
408 | netif_dbg(channel->efx, ifup, channel->efx->net_dev, | |
409 | "chan %d start event queue\n", channel->channel); | |
410 | ||
411 | /* The interrupt handler for this channel may set work_pending | |
412 | * as soon as we enable it. Make sure it's cleared before | |
413 | * then. Similarly, make sure it sees the enabled flag set. | |
414 | */ | |
415 | channel->work_pending = false; | |
416 | channel->enabled = true; | |
417 | smp_wmb(); | |
418 | ||
419 | napi_enable(&channel->napi_str); | |
420 | efx_nic_eventq_read_ack(channel); | |
421 | } | |
422 | ||
423 | /* Disable event queue processing and NAPI */ | |
424 | static void efx_stop_eventq(struct efx_channel *channel) | |
425 | { | |
426 | if (!channel->enabled) | |
427 | return; | |
428 | ||
429 | napi_disable(&channel->napi_str); | |
430 | channel->enabled = false; | |
431 | } | |
432 | ||
8ceee660 BH |
433 | static void efx_fini_eventq(struct efx_channel *channel) |
434 | { | |
62776d03 BH |
435 | netif_dbg(channel->efx, drv, channel->efx->net_dev, |
436 | "chan %d fini event queue\n", channel->channel); | |
8ceee660 | 437 | |
152b6a62 | 438 | efx_nic_fini_eventq(channel); |
8ceee660 BH |
439 | } |
440 | ||
441 | static void efx_remove_eventq(struct efx_channel *channel) | |
442 | { | |
62776d03 BH |
443 | netif_dbg(channel->efx, drv, channel->efx->net_dev, |
444 | "chan %d remove event queue\n", channel->channel); | |
8ceee660 | 445 | |
152b6a62 | 446 | efx_nic_remove_eventq(channel); |
8ceee660 BH |
447 | } |
448 | ||
449 | /************************************************************************** | |
450 | * | |
451 | * Channel handling | |
452 | * | |
453 | *************************************************************************/ | |
454 | ||
7f967c01 | 455 | /* Allocate and initialise a channel structure. */ |
4642610c BH |
456 | static struct efx_channel * |
457 | efx_alloc_channel(struct efx_nic *efx, int i, struct efx_channel *old_channel) | |
458 | { | |
459 | struct efx_channel *channel; | |
460 | struct efx_rx_queue *rx_queue; | |
461 | struct efx_tx_queue *tx_queue; | |
462 | int j; | |
463 | ||
7f967c01 BH |
464 | channel = kzalloc(sizeof(*channel), GFP_KERNEL); |
465 | if (!channel) | |
466 | return NULL; | |
4642610c | 467 | |
7f967c01 BH |
468 | channel->efx = efx; |
469 | channel->channel = i; | |
470 | channel->type = &efx_default_channel_type; | |
4642610c | 471 | |
7f967c01 BH |
472 | for (j = 0; j < EFX_TXQ_TYPES; j++) { |
473 | tx_queue = &channel->tx_queue[j]; | |
474 | tx_queue->efx = efx; | |
475 | tx_queue->queue = i * EFX_TXQ_TYPES + j; | |
476 | tx_queue->channel = channel; | |
477 | } | |
4642610c | 478 | |
7f967c01 BH |
479 | rx_queue = &channel->rx_queue; |
480 | rx_queue->efx = efx; | |
481 | setup_timer(&rx_queue->slow_fill, efx_rx_slow_fill, | |
482 | (unsigned long)rx_queue); | |
4642610c | 483 | |
7f967c01 BH |
484 | return channel; |
485 | } | |
486 | ||
487 | /* Allocate and initialise a channel structure, copying parameters | |
488 | * (but not resources) from an old channel structure. | |
489 | */ | |
490 | static struct efx_channel * | |
491 | efx_copy_channel(const struct efx_channel *old_channel) | |
492 | { | |
493 | struct efx_channel *channel; | |
494 | struct efx_rx_queue *rx_queue; | |
495 | struct efx_tx_queue *tx_queue; | |
496 | int j; | |
4642610c | 497 | |
7f967c01 BH |
498 | channel = kmalloc(sizeof(*channel), GFP_KERNEL); |
499 | if (!channel) | |
500 | return NULL; | |
501 | ||
502 | *channel = *old_channel; | |
503 | ||
504 | channel->napi_dev = NULL; | |
505 | memset(&channel->eventq, 0, sizeof(channel->eventq)); | |
4642610c | 506 | |
7f967c01 BH |
507 | for (j = 0; j < EFX_TXQ_TYPES; j++) { |
508 | tx_queue = &channel->tx_queue[j]; | |
509 | if (tx_queue->channel) | |
4642610c | 510 | tx_queue->channel = channel; |
7f967c01 BH |
511 | tx_queue->buffer = NULL; |
512 | memset(&tx_queue->txd, 0, sizeof(tx_queue->txd)); | |
4642610c BH |
513 | } |
514 | ||
4642610c | 515 | rx_queue = &channel->rx_queue; |
7f967c01 BH |
516 | rx_queue->buffer = NULL; |
517 | memset(&rx_queue->rxd, 0, sizeof(rx_queue->rxd)); | |
4642610c BH |
518 | setup_timer(&rx_queue->slow_fill, efx_rx_slow_fill, |
519 | (unsigned long)rx_queue); | |
520 | ||
521 | return channel; | |
522 | } | |
523 | ||
8ceee660 BH |
524 | static int efx_probe_channel(struct efx_channel *channel) |
525 | { | |
526 | struct efx_tx_queue *tx_queue; | |
527 | struct efx_rx_queue *rx_queue; | |
528 | int rc; | |
529 | ||
62776d03 BH |
530 | netif_dbg(channel->efx, probe, channel->efx->net_dev, |
531 | "creating channel %d\n", channel->channel); | |
8ceee660 | 532 | |
7f967c01 BH |
533 | rc = channel->type->pre_probe(channel); |
534 | if (rc) | |
535 | goto fail; | |
536 | ||
8ceee660 BH |
537 | rc = efx_probe_eventq(channel); |
538 | if (rc) | |
7f967c01 | 539 | goto fail; |
8ceee660 BH |
540 | |
541 | efx_for_each_channel_tx_queue(tx_queue, channel) { | |
542 | rc = efx_probe_tx_queue(tx_queue); | |
543 | if (rc) | |
7f967c01 | 544 | goto fail; |
8ceee660 BH |
545 | } |
546 | ||
547 | efx_for_each_channel_rx_queue(rx_queue, channel) { | |
548 | rc = efx_probe_rx_queue(rx_queue); | |
549 | if (rc) | |
7f967c01 | 550 | goto fail; |
8ceee660 BH |
551 | } |
552 | ||
553 | channel->n_rx_frm_trunc = 0; | |
554 | ||
555 | return 0; | |
556 | ||
7f967c01 BH |
557 | fail: |
558 | efx_remove_channel(channel); | |
8ceee660 BH |
559 | return rc; |
560 | } | |
561 | ||
7f967c01 BH |
562 | static void |
563 | efx_get_channel_name(struct efx_channel *channel, char *buf, size_t len) | |
564 | { | |
565 | struct efx_nic *efx = channel->efx; | |
566 | const char *type; | |
567 | int number; | |
568 | ||
569 | number = channel->channel; | |
570 | if (efx->tx_channel_offset == 0) { | |
571 | type = ""; | |
572 | } else if (channel->channel < efx->tx_channel_offset) { | |
573 | type = "-rx"; | |
574 | } else { | |
575 | type = "-tx"; | |
576 | number -= efx->tx_channel_offset; | |
577 | } | |
578 | snprintf(buf, len, "%s%s-%d", efx->name, type, number); | |
579 | } | |
8ceee660 | 580 | |
56536e9c BH |
581 | static void efx_set_channel_names(struct efx_nic *efx) |
582 | { | |
583 | struct efx_channel *channel; | |
56536e9c | 584 | |
7f967c01 BH |
585 | efx_for_each_channel(channel, efx) |
586 | channel->type->get_name(channel, | |
587 | efx->channel_name[channel->channel], | |
588 | sizeof(efx->channel_name[0])); | |
56536e9c BH |
589 | } |
590 | ||
4642610c BH |
591 | static int efx_probe_channels(struct efx_nic *efx) |
592 | { | |
593 | struct efx_channel *channel; | |
594 | int rc; | |
595 | ||
596 | /* Restart special buffer allocation */ | |
597 | efx->next_buffer_table = 0; | |
598 | ||
c92aaff1 BH |
599 | /* Probe channels in reverse, so that any 'extra' channels |
600 | * use the start of the buffer table. This allows the traffic | |
601 | * channels to be resized without moving them or wasting the | |
602 | * entries before them. | |
603 | */ | |
604 | efx_for_each_channel_rev(channel, efx) { | |
4642610c BH |
605 | rc = efx_probe_channel(channel); |
606 | if (rc) { | |
607 | netif_err(efx, probe, efx->net_dev, | |
608 | "failed to create channel %d\n", | |
609 | channel->channel); | |
610 | goto fail; | |
611 | } | |
612 | } | |
613 | efx_set_channel_names(efx); | |
614 | ||
615 | return 0; | |
616 | ||
617 | fail: | |
618 | efx_remove_channels(efx); | |
619 | return rc; | |
620 | } | |
621 | ||
8ceee660 BH |
622 | /* Channels are shutdown and reinitialised whilst the NIC is running |
623 | * to propagate configuration changes (mtu, checksum offload), or | |
624 | * to clear hardware error conditions | |
625 | */ | |
9f2cb71c | 626 | static void efx_start_datapath(struct efx_nic *efx) |
8ceee660 BH |
627 | { |
628 | struct efx_tx_queue *tx_queue; | |
629 | struct efx_rx_queue *rx_queue; | |
630 | struct efx_channel *channel; | |
8ceee660 | 631 | |
f7f13b0b BH |
632 | /* Calculate the rx buffer allocation parameters required to |
633 | * support the current MTU, including padding for header | |
634 | * alignment and overruns. | |
635 | */ | |
636 | efx->rx_buffer_len = (max(EFX_PAGE_IP_ALIGN, NET_IP_ALIGN) + | |
637 | EFX_MAX_FRAME_LEN(efx->net_dev->mtu) + | |
39c9cf07 | 638 | efx->type->rx_buffer_hash_size + |
f7f13b0b | 639 | efx->type->rx_buffer_padding); |
62b330ba SH |
640 | efx->rx_buffer_order = get_order(efx->rx_buffer_len + |
641 | sizeof(struct efx_rx_page_state)); | |
8ceee660 | 642 | |
14bf718f BH |
643 | /* We must keep at least one descriptor in a TX ring empty. |
644 | * We could avoid this when the queue size does not exactly | |
645 | * match the hardware ring size, but it's not that important. | |
646 | * Therefore we stop the queue when one more skb might fill | |
647 | * the ring completely. We wake it when half way back to | |
648 | * empty. | |
649 | */ | |
650 | efx->txq_stop_thresh = efx->txq_entries - efx_tx_max_skb_descs(efx); | |
651 | efx->txq_wake_thresh = efx->txq_stop_thresh / 2; | |
652 | ||
8ceee660 BH |
653 | /* Initialise the channels */ |
654 | efx_for_each_channel(channel, efx) { | |
bc3c90a2 BH |
655 | efx_for_each_channel_tx_queue(tx_queue, channel) |
656 | efx_init_tx_queue(tx_queue); | |
8ceee660 BH |
657 | |
658 | /* The rx buffer allocation strategy is MTU dependent */ | |
659 | efx_rx_strategy(channel); | |
660 | ||
9f2cb71c | 661 | efx_for_each_channel_rx_queue(rx_queue, channel) { |
bc3c90a2 | 662 | efx_init_rx_queue(rx_queue); |
9f2cb71c BH |
663 | efx_nic_generate_fill_event(rx_queue); |
664 | } | |
8ceee660 BH |
665 | |
666 | WARN_ON(channel->rx_pkt != NULL); | |
667 | efx_rx_strategy(channel); | |
668 | } | |
8ceee660 | 669 | |
9f2cb71c BH |
670 | if (netif_device_present(efx->net_dev)) |
671 | netif_tx_wake_all_queues(efx->net_dev); | |
8ceee660 BH |
672 | } |
673 | ||
9f2cb71c | 674 | static void efx_stop_datapath(struct efx_nic *efx) |
8ceee660 BH |
675 | { |
676 | struct efx_channel *channel; | |
677 | struct efx_tx_queue *tx_queue; | |
678 | struct efx_rx_queue *rx_queue; | |
3dca9d2d | 679 | struct pci_dev *dev = efx->pci_dev; |
6bc5d3a9 | 680 | int rc; |
8ceee660 BH |
681 | |
682 | EFX_ASSERT_RESET_SERIALISED(efx); | |
683 | BUG_ON(efx->port_enabled); | |
684 | ||
3dca9d2d SH |
685 | /* Only perform flush if dma is enabled */ |
686 | if (dev->is_busmaster) { | |
687 | rc = efx_nic_flush_queues(efx); | |
688 | ||
689 | if (rc && EFX_WORKAROUND_7803(efx)) { | |
690 | /* Schedule a reset to recover from the flush failure. The | |
691 | * descriptor caches reference memory we're about to free, | |
692 | * but falcon_reconfigure_mac_wrapper() won't reconnect | |
693 | * the MACs because of the pending reset. */ | |
694 | netif_err(efx, drv, efx->net_dev, | |
695 | "Resetting to recover from flush failure\n"); | |
696 | efx_schedule_reset(efx, RESET_TYPE_ALL); | |
697 | } else if (rc) { | |
698 | netif_err(efx, drv, efx->net_dev, "failed to flush queues\n"); | |
699 | } else { | |
700 | netif_dbg(efx, drv, efx->net_dev, | |
701 | "successfully flushed all queues\n"); | |
702 | } | |
fd371e32 | 703 | } |
6bc5d3a9 | 704 | |
8ceee660 | 705 | efx_for_each_channel(channel, efx) { |
9f2cb71c BH |
706 | /* RX packet processing is pipelined, so wait for the |
707 | * NAPI handler to complete. At least event queue 0 | |
708 | * might be kept active by non-data events, so don't | |
709 | * use napi_synchronize() but actually disable NAPI | |
710 | * temporarily. | |
711 | */ | |
712 | if (efx_channel_has_rx_queue(channel)) { | |
713 | efx_stop_eventq(channel); | |
714 | efx_start_eventq(channel); | |
715 | } | |
8ceee660 BH |
716 | |
717 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
718 | efx_fini_rx_queue(rx_queue); | |
94b274bf | 719 | efx_for_each_possible_channel_tx_queue(tx_queue, channel) |
8ceee660 | 720 | efx_fini_tx_queue(tx_queue); |
8ceee660 BH |
721 | } |
722 | } | |
723 | ||
724 | static void efx_remove_channel(struct efx_channel *channel) | |
725 | { | |
726 | struct efx_tx_queue *tx_queue; | |
727 | struct efx_rx_queue *rx_queue; | |
728 | ||
62776d03 BH |
729 | netif_dbg(channel->efx, drv, channel->efx->net_dev, |
730 | "destroy chan %d\n", channel->channel); | |
8ceee660 BH |
731 | |
732 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
733 | efx_remove_rx_queue(rx_queue); | |
94b274bf | 734 | efx_for_each_possible_channel_tx_queue(tx_queue, channel) |
8ceee660 BH |
735 | efx_remove_tx_queue(tx_queue); |
736 | efx_remove_eventq(channel); | |
8ceee660 BH |
737 | } |
738 | ||
4642610c BH |
739 | static void efx_remove_channels(struct efx_nic *efx) |
740 | { | |
741 | struct efx_channel *channel; | |
742 | ||
743 | efx_for_each_channel(channel, efx) | |
744 | efx_remove_channel(channel); | |
745 | } | |
746 | ||
747 | int | |
748 | efx_realloc_channels(struct efx_nic *efx, u32 rxq_entries, u32 txq_entries) | |
749 | { | |
750 | struct efx_channel *other_channel[EFX_MAX_CHANNELS], *channel; | |
751 | u32 old_rxq_entries, old_txq_entries; | |
7f967c01 | 752 | unsigned i, next_buffer_table = 0; |
8b7325b4 BH |
753 | int rc; |
754 | ||
755 | rc = efx_check_disabled(efx); | |
756 | if (rc) | |
757 | return rc; | |
7f967c01 BH |
758 | |
759 | /* Not all channels should be reallocated. We must avoid | |
760 | * reallocating their buffer table entries. | |
761 | */ | |
762 | efx_for_each_channel(channel, efx) { | |
763 | struct efx_rx_queue *rx_queue; | |
764 | struct efx_tx_queue *tx_queue; | |
765 | ||
766 | if (channel->type->copy) | |
767 | continue; | |
768 | next_buffer_table = max(next_buffer_table, | |
769 | channel->eventq.index + | |
770 | channel->eventq.entries); | |
771 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
772 | next_buffer_table = max(next_buffer_table, | |
773 | rx_queue->rxd.index + | |
774 | rx_queue->rxd.entries); | |
775 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
776 | next_buffer_table = max(next_buffer_table, | |
777 | tx_queue->txd.index + | |
778 | tx_queue->txd.entries); | |
779 | } | |
4642610c BH |
780 | |
781 | efx_stop_all(efx); | |
7f967c01 | 782 | efx_stop_interrupts(efx, true); |
4642610c | 783 | |
7f967c01 | 784 | /* Clone channels (where possible) */ |
4642610c BH |
785 | memset(other_channel, 0, sizeof(other_channel)); |
786 | for (i = 0; i < efx->n_channels; i++) { | |
7f967c01 BH |
787 | channel = efx->channel[i]; |
788 | if (channel->type->copy) | |
789 | channel = channel->type->copy(channel); | |
4642610c BH |
790 | if (!channel) { |
791 | rc = -ENOMEM; | |
792 | goto out; | |
793 | } | |
794 | other_channel[i] = channel; | |
795 | } | |
796 | ||
797 | /* Swap entry counts and channel pointers */ | |
798 | old_rxq_entries = efx->rxq_entries; | |
799 | old_txq_entries = efx->txq_entries; | |
800 | efx->rxq_entries = rxq_entries; | |
801 | efx->txq_entries = txq_entries; | |
802 | for (i = 0; i < efx->n_channels; i++) { | |
803 | channel = efx->channel[i]; | |
804 | efx->channel[i] = other_channel[i]; | |
805 | other_channel[i] = channel; | |
806 | } | |
807 | ||
7f967c01 BH |
808 | /* Restart buffer table allocation */ |
809 | efx->next_buffer_table = next_buffer_table; | |
e8f14992 | 810 | |
e8f14992 | 811 | for (i = 0; i < efx->n_channels; i++) { |
7f967c01 BH |
812 | channel = efx->channel[i]; |
813 | if (!channel->type->copy) | |
814 | continue; | |
815 | rc = efx_probe_channel(channel); | |
816 | if (rc) | |
817 | goto rollback; | |
818 | efx_init_napi_channel(efx->channel[i]); | |
e8f14992 | 819 | } |
7f967c01 | 820 | |
4642610c | 821 | out: |
7f967c01 BH |
822 | /* Destroy unused channel structures */ |
823 | for (i = 0; i < efx->n_channels; i++) { | |
824 | channel = other_channel[i]; | |
825 | if (channel && channel->type->copy) { | |
826 | efx_fini_napi_channel(channel); | |
827 | efx_remove_channel(channel); | |
828 | kfree(channel); | |
829 | } | |
830 | } | |
4642610c | 831 | |
7f967c01 | 832 | efx_start_interrupts(efx, true); |
4642610c BH |
833 | efx_start_all(efx); |
834 | return rc; | |
835 | ||
836 | rollback: | |
837 | /* Swap back */ | |
838 | efx->rxq_entries = old_rxq_entries; | |
839 | efx->txq_entries = old_txq_entries; | |
840 | for (i = 0; i < efx->n_channels; i++) { | |
841 | channel = efx->channel[i]; | |
842 | efx->channel[i] = other_channel[i]; | |
843 | other_channel[i] = channel; | |
844 | } | |
845 | goto out; | |
846 | } | |
847 | ||
90d683af | 848 | void efx_schedule_slow_fill(struct efx_rx_queue *rx_queue) |
8ceee660 | 849 | { |
90d683af | 850 | mod_timer(&rx_queue->slow_fill, jiffies + msecs_to_jiffies(100)); |
8ceee660 BH |
851 | } |
852 | ||
7f967c01 BH |
853 | static const struct efx_channel_type efx_default_channel_type = { |
854 | .pre_probe = efx_channel_dummy_op_int, | |
855 | .get_name = efx_get_channel_name, | |
856 | .copy = efx_copy_channel, | |
857 | .keep_eventq = false, | |
858 | }; | |
859 | ||
860 | int efx_channel_dummy_op_int(struct efx_channel *channel) | |
861 | { | |
862 | return 0; | |
863 | } | |
864 | ||
8ceee660 BH |
865 | /************************************************************************** |
866 | * | |
867 | * Port handling | |
868 | * | |
869 | **************************************************************************/ | |
870 | ||
871 | /* This ensures that the kernel is kept informed (via | |
872 | * netif_carrier_on/off) of the link status, and also maintains the | |
873 | * link status's stop on the port's TX queue. | |
874 | */ | |
fdaa9aed | 875 | void efx_link_status_changed(struct efx_nic *efx) |
8ceee660 | 876 | { |
eb50c0d6 BH |
877 | struct efx_link_state *link_state = &efx->link_state; |
878 | ||
8ceee660 BH |
879 | /* SFC Bug 5356: A net_dev notifier is registered, so we must ensure |
880 | * that no events are triggered between unregister_netdev() and the | |
881 | * driver unloading. A more general condition is that NETDEV_CHANGE | |
882 | * can only be generated between NETDEV_UP and NETDEV_DOWN */ | |
883 | if (!netif_running(efx->net_dev)) | |
884 | return; | |
885 | ||
eb50c0d6 | 886 | if (link_state->up != netif_carrier_ok(efx->net_dev)) { |
8ceee660 BH |
887 | efx->n_link_state_changes++; |
888 | ||
eb50c0d6 | 889 | if (link_state->up) |
8ceee660 BH |
890 | netif_carrier_on(efx->net_dev); |
891 | else | |
892 | netif_carrier_off(efx->net_dev); | |
893 | } | |
894 | ||
895 | /* Status message for kernel log */ | |
2aa9ef11 | 896 | if (link_state->up) |
62776d03 BH |
897 | netif_info(efx, link, efx->net_dev, |
898 | "link up at %uMbps %s-duplex (MTU %d)%s\n", | |
899 | link_state->speed, link_state->fd ? "full" : "half", | |
900 | efx->net_dev->mtu, | |
901 | (efx->promiscuous ? " [PROMISC]" : "")); | |
2aa9ef11 | 902 | else |
62776d03 | 903 | netif_info(efx, link, efx->net_dev, "link down\n"); |
8ceee660 BH |
904 | } |
905 | ||
d3245b28 BH |
906 | void efx_link_set_advertising(struct efx_nic *efx, u32 advertising) |
907 | { | |
908 | efx->link_advertising = advertising; | |
909 | if (advertising) { | |
910 | if (advertising & ADVERTISED_Pause) | |
911 | efx->wanted_fc |= (EFX_FC_TX | EFX_FC_RX); | |
912 | else | |
913 | efx->wanted_fc &= ~(EFX_FC_TX | EFX_FC_RX); | |
914 | if (advertising & ADVERTISED_Asym_Pause) | |
915 | efx->wanted_fc ^= EFX_FC_TX; | |
916 | } | |
917 | } | |
918 | ||
b5626946 | 919 | void efx_link_set_wanted_fc(struct efx_nic *efx, u8 wanted_fc) |
d3245b28 BH |
920 | { |
921 | efx->wanted_fc = wanted_fc; | |
922 | if (efx->link_advertising) { | |
923 | if (wanted_fc & EFX_FC_RX) | |
924 | efx->link_advertising |= (ADVERTISED_Pause | | |
925 | ADVERTISED_Asym_Pause); | |
926 | else | |
927 | efx->link_advertising &= ~(ADVERTISED_Pause | | |
928 | ADVERTISED_Asym_Pause); | |
929 | if (wanted_fc & EFX_FC_TX) | |
930 | efx->link_advertising ^= ADVERTISED_Asym_Pause; | |
931 | } | |
932 | } | |
933 | ||
115122af BH |
934 | static void efx_fini_port(struct efx_nic *efx); |
935 | ||
d3245b28 BH |
936 | /* Push loopback/power/transmit disable settings to the PHY, and reconfigure |
937 | * the MAC appropriately. All other PHY configuration changes are pushed | |
938 | * through phy_op->set_settings(), and pushed asynchronously to the MAC | |
939 | * through efx_monitor(). | |
940 | * | |
941 | * Callers must hold the mac_lock | |
942 | */ | |
943 | int __efx_reconfigure_port(struct efx_nic *efx) | |
8ceee660 | 944 | { |
d3245b28 BH |
945 | enum efx_phy_mode phy_mode; |
946 | int rc; | |
8ceee660 | 947 | |
d3245b28 | 948 | WARN_ON(!mutex_is_locked(&efx->mac_lock)); |
8ceee660 | 949 | |
0fca8c97 | 950 | /* Serialise the promiscuous flag with efx_set_rx_mode. */ |
73ba7b68 BH |
951 | netif_addr_lock_bh(efx->net_dev); |
952 | netif_addr_unlock_bh(efx->net_dev); | |
a816f75a | 953 | |
d3245b28 BH |
954 | /* Disable PHY transmit in mac level loopbacks */ |
955 | phy_mode = efx->phy_mode; | |
177dfcd8 BH |
956 | if (LOOPBACK_INTERNAL(efx)) |
957 | efx->phy_mode |= PHY_MODE_TX_DISABLED; | |
958 | else | |
959 | efx->phy_mode &= ~PHY_MODE_TX_DISABLED; | |
177dfcd8 | 960 | |
d3245b28 | 961 | rc = efx->type->reconfigure_port(efx); |
8ceee660 | 962 | |
d3245b28 BH |
963 | if (rc) |
964 | efx->phy_mode = phy_mode; | |
177dfcd8 | 965 | |
d3245b28 | 966 | return rc; |
8ceee660 BH |
967 | } |
968 | ||
969 | /* Reinitialise the MAC to pick up new PHY settings, even if the port is | |
970 | * disabled. */ | |
d3245b28 | 971 | int efx_reconfigure_port(struct efx_nic *efx) |
8ceee660 | 972 | { |
d3245b28 BH |
973 | int rc; |
974 | ||
8ceee660 BH |
975 | EFX_ASSERT_RESET_SERIALISED(efx); |
976 | ||
977 | mutex_lock(&efx->mac_lock); | |
d3245b28 | 978 | rc = __efx_reconfigure_port(efx); |
8ceee660 | 979 | mutex_unlock(&efx->mac_lock); |
d3245b28 BH |
980 | |
981 | return rc; | |
8ceee660 BH |
982 | } |
983 | ||
8be4f3e6 BH |
984 | /* Asynchronous work item for changing MAC promiscuity and multicast |
985 | * hash. Avoid a drain/rx_ingress enable by reconfiguring the current | |
986 | * MAC directly. */ | |
766ca0fa BH |
987 | static void efx_mac_work(struct work_struct *data) |
988 | { | |
989 | struct efx_nic *efx = container_of(data, struct efx_nic, mac_work); | |
990 | ||
991 | mutex_lock(&efx->mac_lock); | |
30b81cda | 992 | if (efx->port_enabled) |
710b208d | 993 | efx->type->reconfigure_mac(efx); |
766ca0fa BH |
994 | mutex_unlock(&efx->mac_lock); |
995 | } | |
996 | ||
8ceee660 BH |
997 | static int efx_probe_port(struct efx_nic *efx) |
998 | { | |
999 | int rc; | |
1000 | ||
62776d03 | 1001 | netif_dbg(efx, probe, efx->net_dev, "create port\n"); |
8ceee660 | 1002 | |
ff3b00a0 SH |
1003 | if (phy_flash_cfg) |
1004 | efx->phy_mode = PHY_MODE_SPECIAL; | |
1005 | ||
ef2b90ee BH |
1006 | /* Connect up MAC/PHY operations table */ |
1007 | rc = efx->type->probe_port(efx); | |
8ceee660 | 1008 | if (rc) |
e42de262 | 1009 | return rc; |
8ceee660 | 1010 | |
e332bcb3 BH |
1011 | /* Initialise MAC address to permanent address */ |
1012 | memcpy(efx->net_dev->dev_addr, efx->net_dev->perm_addr, ETH_ALEN); | |
8ceee660 BH |
1013 | |
1014 | return 0; | |
8ceee660 BH |
1015 | } |
1016 | ||
1017 | static int efx_init_port(struct efx_nic *efx) | |
1018 | { | |
1019 | int rc; | |
1020 | ||
62776d03 | 1021 | netif_dbg(efx, drv, efx->net_dev, "init port\n"); |
8ceee660 | 1022 | |
1dfc5cea BH |
1023 | mutex_lock(&efx->mac_lock); |
1024 | ||
177dfcd8 | 1025 | rc = efx->phy_op->init(efx); |
8ceee660 | 1026 | if (rc) |
1dfc5cea | 1027 | goto fail1; |
8ceee660 | 1028 | |
dc8cfa55 | 1029 | efx->port_initialized = true; |
1dfc5cea | 1030 | |
d3245b28 BH |
1031 | /* Reconfigure the MAC before creating dma queues (required for |
1032 | * Falcon/A1 where RX_INGR_EN/TX_DRAIN_EN isn't supported) */ | |
710b208d | 1033 | efx->type->reconfigure_mac(efx); |
d3245b28 BH |
1034 | |
1035 | /* Ensure the PHY advertises the correct flow control settings */ | |
1036 | rc = efx->phy_op->reconfigure(efx); | |
1037 | if (rc) | |
1038 | goto fail2; | |
1039 | ||
1dfc5cea | 1040 | mutex_unlock(&efx->mac_lock); |
8ceee660 | 1041 | return 0; |
177dfcd8 | 1042 | |
1dfc5cea | 1043 | fail2: |
177dfcd8 | 1044 | efx->phy_op->fini(efx); |
1dfc5cea BH |
1045 | fail1: |
1046 | mutex_unlock(&efx->mac_lock); | |
177dfcd8 | 1047 | return rc; |
8ceee660 BH |
1048 | } |
1049 | ||
8ceee660 BH |
1050 | static void efx_start_port(struct efx_nic *efx) |
1051 | { | |
62776d03 | 1052 | netif_dbg(efx, ifup, efx->net_dev, "start port\n"); |
8ceee660 BH |
1053 | BUG_ON(efx->port_enabled); |
1054 | ||
1055 | mutex_lock(&efx->mac_lock); | |
dc8cfa55 | 1056 | efx->port_enabled = true; |
8be4f3e6 BH |
1057 | |
1058 | /* efx_mac_work() might have been scheduled after efx_stop_port(), | |
1059 | * and then cancelled by efx_flush_all() */ | |
710b208d | 1060 | efx->type->reconfigure_mac(efx); |
8be4f3e6 | 1061 | |
8ceee660 BH |
1062 | mutex_unlock(&efx->mac_lock); |
1063 | } | |
1064 | ||
fdaa9aed | 1065 | /* Prevent efx_mac_work() and efx_monitor() from working */ |
8ceee660 BH |
1066 | static void efx_stop_port(struct efx_nic *efx) |
1067 | { | |
62776d03 | 1068 | netif_dbg(efx, ifdown, efx->net_dev, "stop port\n"); |
8ceee660 BH |
1069 | |
1070 | mutex_lock(&efx->mac_lock); | |
dc8cfa55 | 1071 | efx->port_enabled = false; |
8ceee660 BH |
1072 | mutex_unlock(&efx->mac_lock); |
1073 | ||
1074 | /* Serialise against efx_set_multicast_list() */ | |
73ba7b68 BH |
1075 | netif_addr_lock_bh(efx->net_dev); |
1076 | netif_addr_unlock_bh(efx->net_dev); | |
8ceee660 BH |
1077 | } |
1078 | ||
1079 | static void efx_fini_port(struct efx_nic *efx) | |
1080 | { | |
62776d03 | 1081 | netif_dbg(efx, drv, efx->net_dev, "shut down port\n"); |
8ceee660 BH |
1082 | |
1083 | if (!efx->port_initialized) | |
1084 | return; | |
1085 | ||
177dfcd8 | 1086 | efx->phy_op->fini(efx); |
dc8cfa55 | 1087 | efx->port_initialized = false; |
8ceee660 | 1088 | |
eb50c0d6 | 1089 | efx->link_state.up = false; |
8ceee660 BH |
1090 | efx_link_status_changed(efx); |
1091 | } | |
1092 | ||
1093 | static void efx_remove_port(struct efx_nic *efx) | |
1094 | { | |
62776d03 | 1095 | netif_dbg(efx, drv, efx->net_dev, "destroying port\n"); |
8ceee660 | 1096 | |
ef2b90ee | 1097 | efx->type->remove_port(efx); |
8ceee660 BH |
1098 | } |
1099 | ||
1100 | /************************************************************************** | |
1101 | * | |
1102 | * NIC handling | |
1103 | * | |
1104 | **************************************************************************/ | |
1105 | ||
1106 | /* This configures the PCI device to enable I/O and DMA. */ | |
1107 | static int efx_init_io(struct efx_nic *efx) | |
1108 | { | |
1109 | struct pci_dev *pci_dev = efx->pci_dev; | |
1110 | dma_addr_t dma_mask = efx->type->max_dma_mask; | |
1111 | int rc; | |
1112 | ||
62776d03 | 1113 | netif_dbg(efx, probe, efx->net_dev, "initialising I/O\n"); |
8ceee660 BH |
1114 | |
1115 | rc = pci_enable_device(pci_dev); | |
1116 | if (rc) { | |
62776d03 BH |
1117 | netif_err(efx, probe, efx->net_dev, |
1118 | "failed to enable PCI device\n"); | |
8ceee660 BH |
1119 | goto fail1; |
1120 | } | |
1121 | ||
1122 | pci_set_master(pci_dev); | |
1123 | ||
1124 | /* Set the PCI DMA mask. Try all possibilities from our | |
1125 | * genuine mask down to 32 bits, because some architectures | |
1126 | * (e.g. x86_64 with iommu_sac_force set) will allow 40 bit | |
1127 | * masks event though they reject 46 bit masks. | |
1128 | */ | |
1129 | while (dma_mask > 0x7fffffffUL) { | |
0e33d870 BH |
1130 | if (dma_supported(&pci_dev->dev, dma_mask)) { |
1131 | rc = dma_set_mask(&pci_dev->dev, dma_mask); | |
e9e01846 BH |
1132 | if (rc == 0) |
1133 | break; | |
1134 | } | |
8ceee660 BH |
1135 | dma_mask >>= 1; |
1136 | } | |
1137 | if (rc) { | |
62776d03 BH |
1138 | netif_err(efx, probe, efx->net_dev, |
1139 | "could not find a suitable DMA mask\n"); | |
8ceee660 BH |
1140 | goto fail2; |
1141 | } | |
62776d03 BH |
1142 | netif_dbg(efx, probe, efx->net_dev, |
1143 | "using DMA mask %llx\n", (unsigned long long) dma_mask); | |
0e33d870 | 1144 | rc = dma_set_coherent_mask(&pci_dev->dev, dma_mask); |
8ceee660 | 1145 | if (rc) { |
0e33d870 BH |
1146 | /* dma_set_coherent_mask() is not *allowed* to |
1147 | * fail with a mask that dma_set_mask() accepted, | |
8ceee660 BH |
1148 | * but just in case... |
1149 | */ | |
62776d03 BH |
1150 | netif_err(efx, probe, efx->net_dev, |
1151 | "failed to set consistent DMA mask\n"); | |
8ceee660 BH |
1152 | goto fail2; |
1153 | } | |
1154 | ||
dc803df8 BH |
1155 | efx->membase_phys = pci_resource_start(efx->pci_dev, EFX_MEM_BAR); |
1156 | rc = pci_request_region(pci_dev, EFX_MEM_BAR, "sfc"); | |
8ceee660 | 1157 | if (rc) { |
62776d03 BH |
1158 | netif_err(efx, probe, efx->net_dev, |
1159 | "request for memory BAR failed\n"); | |
8ceee660 BH |
1160 | rc = -EIO; |
1161 | goto fail3; | |
1162 | } | |
86c432ca BH |
1163 | efx->membase = ioremap_nocache(efx->membase_phys, |
1164 | efx->type->mem_map_size); | |
8ceee660 | 1165 | if (!efx->membase) { |
62776d03 BH |
1166 | netif_err(efx, probe, efx->net_dev, |
1167 | "could not map memory BAR at %llx+%x\n", | |
1168 | (unsigned long long)efx->membase_phys, | |
1169 | efx->type->mem_map_size); | |
8ceee660 BH |
1170 | rc = -ENOMEM; |
1171 | goto fail4; | |
1172 | } | |
62776d03 BH |
1173 | netif_dbg(efx, probe, efx->net_dev, |
1174 | "memory BAR at %llx+%x (virtual %p)\n", | |
1175 | (unsigned long long)efx->membase_phys, | |
1176 | efx->type->mem_map_size, efx->membase); | |
8ceee660 BH |
1177 | |
1178 | return 0; | |
1179 | ||
1180 | fail4: | |
dc803df8 | 1181 | pci_release_region(efx->pci_dev, EFX_MEM_BAR); |
8ceee660 | 1182 | fail3: |
2c118e0f | 1183 | efx->membase_phys = 0; |
8ceee660 BH |
1184 | fail2: |
1185 | pci_disable_device(efx->pci_dev); | |
1186 | fail1: | |
1187 | return rc; | |
1188 | } | |
1189 | ||
1190 | static void efx_fini_io(struct efx_nic *efx) | |
1191 | { | |
62776d03 | 1192 | netif_dbg(efx, drv, efx->net_dev, "shutting down I/O\n"); |
8ceee660 BH |
1193 | |
1194 | if (efx->membase) { | |
1195 | iounmap(efx->membase); | |
1196 | efx->membase = NULL; | |
1197 | } | |
1198 | ||
1199 | if (efx->membase_phys) { | |
dc803df8 | 1200 | pci_release_region(efx->pci_dev, EFX_MEM_BAR); |
2c118e0f | 1201 | efx->membase_phys = 0; |
8ceee660 BH |
1202 | } |
1203 | ||
1204 | pci_disable_device(efx->pci_dev); | |
1205 | } | |
1206 | ||
a9a52506 | 1207 | static unsigned int efx_wanted_parallelism(struct efx_nic *efx) |
46123d04 | 1208 | { |
cdb08f8f | 1209 | cpumask_var_t thread_mask; |
a16e5b24 | 1210 | unsigned int count; |
46123d04 | 1211 | int cpu; |
5b874e25 | 1212 | |
cd2d5b52 BH |
1213 | if (rss_cpus) { |
1214 | count = rss_cpus; | |
1215 | } else { | |
1216 | if (unlikely(!zalloc_cpumask_var(&thread_mask, GFP_KERNEL))) { | |
1217 | netif_warn(efx, probe, efx->net_dev, | |
1218 | "RSS disabled due to allocation failure\n"); | |
1219 | return 1; | |
1220 | } | |
46123d04 | 1221 | |
cd2d5b52 BH |
1222 | count = 0; |
1223 | for_each_online_cpu(cpu) { | |
1224 | if (!cpumask_test_cpu(cpu, thread_mask)) { | |
1225 | ++count; | |
1226 | cpumask_or(thread_mask, thread_mask, | |
1227 | topology_thread_cpumask(cpu)); | |
1228 | } | |
1229 | } | |
1230 | ||
1231 | free_cpumask_var(thread_mask); | |
2f8975fb RR |
1232 | } |
1233 | ||
cd2d5b52 BH |
1234 | /* If RSS is requested for the PF *and* VFs then we can't write RSS |
1235 | * table entries that are inaccessible to VFs | |
1236 | */ | |
1237 | if (efx_sriov_wanted(efx) && efx_vf_size(efx) > 1 && | |
1238 | count > efx_vf_size(efx)) { | |
1239 | netif_warn(efx, probe, efx->net_dev, | |
1240 | "Reducing number of RSS channels from %u to %u for " | |
1241 | "VF support. Increase vf-msix-limit to use more " | |
1242 | "channels on the PF.\n", | |
1243 | count, efx_vf_size(efx)); | |
1244 | count = efx_vf_size(efx); | |
46123d04 BH |
1245 | } |
1246 | ||
1247 | return count; | |
1248 | } | |
1249 | ||
64d8ad6d BH |
1250 | static int |
1251 | efx_init_rx_cpu_rmap(struct efx_nic *efx, struct msix_entry *xentries) | |
1252 | { | |
1253 | #ifdef CONFIG_RFS_ACCEL | |
a16e5b24 BH |
1254 | unsigned int i; |
1255 | int rc; | |
64d8ad6d BH |
1256 | |
1257 | efx->net_dev->rx_cpu_rmap = alloc_irq_cpu_rmap(efx->n_rx_channels); | |
1258 | if (!efx->net_dev->rx_cpu_rmap) | |
1259 | return -ENOMEM; | |
1260 | for (i = 0; i < efx->n_rx_channels; i++) { | |
1261 | rc = irq_cpu_rmap_add(efx->net_dev->rx_cpu_rmap, | |
1262 | xentries[i].vector); | |
1263 | if (rc) { | |
1264 | free_irq_cpu_rmap(efx->net_dev->rx_cpu_rmap); | |
1265 | efx->net_dev->rx_cpu_rmap = NULL; | |
1266 | return rc; | |
1267 | } | |
1268 | } | |
1269 | #endif | |
1270 | return 0; | |
1271 | } | |
1272 | ||
46123d04 BH |
1273 | /* Probe the number and type of interrupts we are able to obtain, and |
1274 | * the resulting numbers of channels and RX queues. | |
1275 | */ | |
64d8ad6d | 1276 | static int efx_probe_interrupts(struct efx_nic *efx) |
8ceee660 | 1277 | { |
a16e5b24 BH |
1278 | unsigned int max_channels = |
1279 | min(efx->type->phys_addr_channels, EFX_MAX_CHANNELS); | |
7f967c01 BH |
1280 | unsigned int extra_channels = 0; |
1281 | unsigned int i, j; | |
a16e5b24 | 1282 | int rc; |
8ceee660 | 1283 | |
7f967c01 BH |
1284 | for (i = 0; i < EFX_MAX_EXTRA_CHANNELS; i++) |
1285 | if (efx->extra_channel_type[i]) | |
1286 | ++extra_channels; | |
1287 | ||
8ceee660 | 1288 | if (efx->interrupt_mode == EFX_INT_MODE_MSIX) { |
46123d04 | 1289 | struct msix_entry xentries[EFX_MAX_CHANNELS]; |
a16e5b24 | 1290 | unsigned int n_channels; |
aa6ef27e | 1291 | |
a9a52506 | 1292 | n_channels = efx_wanted_parallelism(efx); |
a4900ac9 BH |
1293 | if (separate_tx_channels) |
1294 | n_channels *= 2; | |
7f967c01 | 1295 | n_channels += extra_channels; |
a4900ac9 | 1296 | n_channels = min(n_channels, max_channels); |
8ceee660 | 1297 | |
a4900ac9 | 1298 | for (i = 0; i < n_channels; i++) |
8ceee660 | 1299 | xentries[i].entry = i; |
a4900ac9 | 1300 | rc = pci_enable_msix(efx->pci_dev, xentries, n_channels); |
8ceee660 | 1301 | if (rc > 0) { |
62776d03 BH |
1302 | netif_err(efx, drv, efx->net_dev, |
1303 | "WARNING: Insufficient MSI-X vectors" | |
a16e5b24 | 1304 | " available (%d < %u).\n", rc, n_channels); |
62776d03 BH |
1305 | netif_err(efx, drv, efx->net_dev, |
1306 | "WARNING: Performance may be reduced.\n"); | |
a4900ac9 BH |
1307 | EFX_BUG_ON_PARANOID(rc >= n_channels); |
1308 | n_channels = rc; | |
8ceee660 | 1309 | rc = pci_enable_msix(efx->pci_dev, xentries, |
a4900ac9 | 1310 | n_channels); |
8ceee660 BH |
1311 | } |
1312 | ||
1313 | if (rc == 0) { | |
a4900ac9 | 1314 | efx->n_channels = n_channels; |
7f967c01 BH |
1315 | if (n_channels > extra_channels) |
1316 | n_channels -= extra_channels; | |
a4900ac9 | 1317 | if (separate_tx_channels) { |
7f967c01 BH |
1318 | efx->n_tx_channels = max(n_channels / 2, 1U); |
1319 | efx->n_rx_channels = max(n_channels - | |
1320 | efx->n_tx_channels, | |
1321 | 1U); | |
a4900ac9 | 1322 | } else { |
7f967c01 BH |
1323 | efx->n_tx_channels = n_channels; |
1324 | efx->n_rx_channels = n_channels; | |
a4900ac9 | 1325 | } |
64d8ad6d BH |
1326 | rc = efx_init_rx_cpu_rmap(efx, xentries); |
1327 | if (rc) { | |
1328 | pci_disable_msix(efx->pci_dev); | |
1329 | return rc; | |
1330 | } | |
7f967c01 | 1331 | for (i = 0; i < efx->n_channels; i++) |
f7d12cdc BH |
1332 | efx_get_channel(efx, i)->irq = |
1333 | xentries[i].vector; | |
8ceee660 BH |
1334 | } else { |
1335 | /* Fall back to single channel MSI */ | |
1336 | efx->interrupt_mode = EFX_INT_MODE_MSI; | |
62776d03 BH |
1337 | netif_err(efx, drv, efx->net_dev, |
1338 | "could not enable MSI-X\n"); | |
8ceee660 BH |
1339 | } |
1340 | } | |
1341 | ||
1342 | /* Try single interrupt MSI */ | |
1343 | if (efx->interrupt_mode == EFX_INT_MODE_MSI) { | |
28b581ab | 1344 | efx->n_channels = 1; |
a4900ac9 BH |
1345 | efx->n_rx_channels = 1; |
1346 | efx->n_tx_channels = 1; | |
8ceee660 BH |
1347 | rc = pci_enable_msi(efx->pci_dev); |
1348 | if (rc == 0) { | |
f7d12cdc | 1349 | efx_get_channel(efx, 0)->irq = efx->pci_dev->irq; |
8ceee660 | 1350 | } else { |
62776d03 BH |
1351 | netif_err(efx, drv, efx->net_dev, |
1352 | "could not enable MSI\n"); | |
8ceee660 BH |
1353 | efx->interrupt_mode = EFX_INT_MODE_LEGACY; |
1354 | } | |
1355 | } | |
1356 | ||
1357 | /* Assume legacy interrupts */ | |
1358 | if (efx->interrupt_mode == EFX_INT_MODE_LEGACY) { | |
28b581ab | 1359 | efx->n_channels = 1 + (separate_tx_channels ? 1 : 0); |
a4900ac9 BH |
1360 | efx->n_rx_channels = 1; |
1361 | efx->n_tx_channels = 1; | |
8ceee660 BH |
1362 | efx->legacy_irq = efx->pci_dev->irq; |
1363 | } | |
64d8ad6d | 1364 | |
7f967c01 BH |
1365 | /* Assign extra channels if possible */ |
1366 | j = efx->n_channels; | |
1367 | for (i = 0; i < EFX_MAX_EXTRA_CHANNELS; i++) { | |
1368 | if (!efx->extra_channel_type[i]) | |
1369 | continue; | |
1370 | if (efx->interrupt_mode != EFX_INT_MODE_MSIX || | |
1371 | efx->n_channels <= extra_channels) { | |
1372 | efx->extra_channel_type[i]->handle_no_channel(efx); | |
1373 | } else { | |
1374 | --j; | |
1375 | efx_get_channel(efx, j)->type = | |
1376 | efx->extra_channel_type[i]; | |
1377 | } | |
1378 | } | |
1379 | ||
cd2d5b52 | 1380 | /* RSS might be usable on VFs even if it is disabled on the PF */ |
3132d282 | 1381 | efx->rss_spread = ((efx->n_rx_channels > 1 || !efx_sriov_wanted(efx)) ? |
cd2d5b52 BH |
1382 | efx->n_rx_channels : efx_vf_size(efx)); |
1383 | ||
64d8ad6d | 1384 | return 0; |
8ceee660 BH |
1385 | } |
1386 | ||
9f2cb71c | 1387 | /* Enable interrupts, then probe and start the event queues */ |
7f967c01 | 1388 | static void efx_start_interrupts(struct efx_nic *efx, bool may_keep_eventq) |
9f2cb71c BH |
1389 | { |
1390 | struct efx_channel *channel; | |
1391 | ||
8b7325b4 BH |
1392 | BUG_ON(efx->state == STATE_DISABLED); |
1393 | ||
9f2cb71c BH |
1394 | if (efx->legacy_irq) |
1395 | efx->legacy_irq_enabled = true; | |
1396 | efx_nic_enable_interrupts(efx); | |
1397 | ||
1398 | efx_for_each_channel(channel, efx) { | |
7f967c01 BH |
1399 | if (!channel->type->keep_eventq || !may_keep_eventq) |
1400 | efx_init_eventq(channel); | |
9f2cb71c BH |
1401 | efx_start_eventq(channel); |
1402 | } | |
1403 | ||
1404 | efx_mcdi_mode_event(efx); | |
1405 | } | |
1406 | ||
7f967c01 | 1407 | static void efx_stop_interrupts(struct efx_nic *efx, bool may_keep_eventq) |
9f2cb71c BH |
1408 | { |
1409 | struct efx_channel *channel; | |
1410 | ||
8b7325b4 BH |
1411 | if (efx->state == STATE_DISABLED) |
1412 | return; | |
1413 | ||
9f2cb71c BH |
1414 | efx_mcdi_mode_poll(efx); |
1415 | ||
1416 | efx_nic_disable_interrupts(efx); | |
1417 | if (efx->legacy_irq) { | |
1418 | synchronize_irq(efx->legacy_irq); | |
1419 | efx->legacy_irq_enabled = false; | |
1420 | } | |
1421 | ||
1422 | efx_for_each_channel(channel, efx) { | |
1423 | if (channel->irq) | |
1424 | synchronize_irq(channel->irq); | |
1425 | ||
1426 | efx_stop_eventq(channel); | |
7f967c01 BH |
1427 | if (!channel->type->keep_eventq || !may_keep_eventq) |
1428 | efx_fini_eventq(channel); | |
9f2cb71c BH |
1429 | } |
1430 | } | |
1431 | ||
8ceee660 BH |
1432 | static void efx_remove_interrupts(struct efx_nic *efx) |
1433 | { | |
1434 | struct efx_channel *channel; | |
1435 | ||
1436 | /* Remove MSI/MSI-X interrupts */ | |
64ee3120 | 1437 | efx_for_each_channel(channel, efx) |
8ceee660 BH |
1438 | channel->irq = 0; |
1439 | pci_disable_msi(efx->pci_dev); | |
1440 | pci_disable_msix(efx->pci_dev); | |
1441 | ||
1442 | /* Remove legacy interrupt */ | |
1443 | efx->legacy_irq = 0; | |
1444 | } | |
1445 | ||
8831da7b | 1446 | static void efx_set_channels(struct efx_nic *efx) |
8ceee660 | 1447 | { |
602a5322 BH |
1448 | struct efx_channel *channel; |
1449 | struct efx_tx_queue *tx_queue; | |
1450 | ||
97653431 | 1451 | efx->tx_channel_offset = |
a4900ac9 | 1452 | separate_tx_channels ? efx->n_channels - efx->n_tx_channels : 0; |
602a5322 BH |
1453 | |
1454 | /* We need to adjust the TX queue numbers if we have separate | |
1455 | * RX-only and TX-only channels. | |
1456 | */ | |
1457 | efx_for_each_channel(channel, efx) { | |
1458 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
1459 | tx_queue->queue -= (efx->tx_channel_offset * | |
1460 | EFX_TXQ_TYPES); | |
1461 | } | |
8ceee660 BH |
1462 | } |
1463 | ||
1464 | static int efx_probe_nic(struct efx_nic *efx) | |
1465 | { | |
765c9f46 | 1466 | size_t i; |
8ceee660 BH |
1467 | int rc; |
1468 | ||
62776d03 | 1469 | netif_dbg(efx, probe, efx->net_dev, "creating NIC\n"); |
8ceee660 BH |
1470 | |
1471 | /* Carry out hardware-type specific initialisation */ | |
ef2b90ee | 1472 | rc = efx->type->probe(efx); |
8ceee660 BH |
1473 | if (rc) |
1474 | return rc; | |
1475 | ||
a4900ac9 | 1476 | /* Determine the number of channels and queues by trying to hook |
8ceee660 | 1477 | * in MSI-X interrupts. */ |
64d8ad6d BH |
1478 | rc = efx_probe_interrupts(efx); |
1479 | if (rc) | |
1480 | goto fail; | |
8ceee660 | 1481 | |
28e47c49 BH |
1482 | efx->type->dimension_resources(efx); |
1483 | ||
5d3a6fca BH |
1484 | if (efx->n_channels > 1) |
1485 | get_random_bytes(&efx->rx_hash_key, sizeof(efx->rx_hash_key)); | |
765c9f46 | 1486 | for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); i++) |
278bc429 | 1487 | efx->rx_indir_table[i] = |
cd2d5b52 | 1488 | ethtool_rxfh_indir_default(i, efx->rss_spread); |
5d3a6fca | 1489 | |
8831da7b | 1490 | efx_set_channels(efx); |
c4f4adc7 BH |
1491 | netif_set_real_num_tx_queues(efx->net_dev, efx->n_tx_channels); |
1492 | netif_set_real_num_rx_queues(efx->net_dev, efx->n_rx_channels); | |
8ceee660 BH |
1493 | |
1494 | /* Initialise the interrupt moderation settings */ | |
9e393b30 BH |
1495 | efx_init_irq_moderation(efx, tx_irq_mod_usec, rx_irq_mod_usec, true, |
1496 | true); | |
8ceee660 BH |
1497 | |
1498 | return 0; | |
64d8ad6d BH |
1499 | |
1500 | fail: | |
1501 | efx->type->remove(efx); | |
1502 | return rc; | |
8ceee660 BH |
1503 | } |
1504 | ||
1505 | static void efx_remove_nic(struct efx_nic *efx) | |
1506 | { | |
62776d03 | 1507 | netif_dbg(efx, drv, efx->net_dev, "destroying NIC\n"); |
8ceee660 BH |
1508 | |
1509 | efx_remove_interrupts(efx); | |
ef2b90ee | 1510 | efx->type->remove(efx); |
8ceee660 BH |
1511 | } |
1512 | ||
1513 | /************************************************************************** | |
1514 | * | |
1515 | * NIC startup/shutdown | |
1516 | * | |
1517 | *************************************************************************/ | |
1518 | ||
1519 | static int efx_probe_all(struct efx_nic *efx) | |
1520 | { | |
8ceee660 BH |
1521 | int rc; |
1522 | ||
8ceee660 BH |
1523 | rc = efx_probe_nic(efx); |
1524 | if (rc) { | |
62776d03 | 1525 | netif_err(efx, probe, efx->net_dev, "failed to create NIC\n"); |
8ceee660 BH |
1526 | goto fail1; |
1527 | } | |
1528 | ||
8ceee660 BH |
1529 | rc = efx_probe_port(efx); |
1530 | if (rc) { | |
62776d03 | 1531 | netif_err(efx, probe, efx->net_dev, "failed to create port\n"); |
8ceee660 BH |
1532 | goto fail2; |
1533 | } | |
1534 | ||
7e6d06f0 BH |
1535 | BUILD_BUG_ON(EFX_DEFAULT_DMAQ_SIZE < EFX_RXQ_MIN_ENT); |
1536 | if (WARN_ON(EFX_DEFAULT_DMAQ_SIZE < EFX_TXQ_MIN_ENT(efx))) { | |
1537 | rc = -EINVAL; | |
1538 | goto fail3; | |
1539 | } | |
ecc910f5 | 1540 | efx->rxq_entries = efx->txq_entries = EFX_DEFAULT_DMAQ_SIZE; |
8ceee660 | 1541 | |
64eebcfd BH |
1542 | rc = efx_probe_filters(efx); |
1543 | if (rc) { | |
1544 | netif_err(efx, probe, efx->net_dev, | |
1545 | "failed to create filter tables\n"); | |
7f967c01 | 1546 | goto fail3; |
64eebcfd BH |
1547 | } |
1548 | ||
7f967c01 BH |
1549 | rc = efx_probe_channels(efx); |
1550 | if (rc) | |
1551 | goto fail4; | |
1552 | ||
8ceee660 BH |
1553 | return 0; |
1554 | ||
64eebcfd | 1555 | fail4: |
7f967c01 | 1556 | efx_remove_filters(efx); |
8ceee660 | 1557 | fail3: |
8ceee660 BH |
1558 | efx_remove_port(efx); |
1559 | fail2: | |
1560 | efx_remove_nic(efx); | |
1561 | fail1: | |
1562 | return rc; | |
1563 | } | |
1564 | ||
8b7325b4 BH |
1565 | /* If the interface is supposed to be running but is not, start |
1566 | * the hardware and software data path, regular activity for the port | |
1567 | * (MAC statistics, link polling, etc.) and schedule the port to be | |
1568 | * reconfigured. Interrupts must already be enabled. This function | |
1569 | * is safe to call multiple times, so long as the NIC is not disabled. | |
1570 | * Requires the RTNL lock. | |
9f2cb71c | 1571 | */ |
8ceee660 BH |
1572 | static void efx_start_all(struct efx_nic *efx) |
1573 | { | |
8ceee660 | 1574 | EFX_ASSERT_RESET_SERIALISED(efx); |
8b7325b4 | 1575 | BUG_ON(efx->state == STATE_DISABLED); |
8ceee660 BH |
1576 | |
1577 | /* Check that it is appropriate to restart the interface. All | |
1578 | * of these flags are safe to read under just the rtnl lock */ | |
8b7325b4 | 1579 | if (efx->port_enabled || !netif_running(efx->net_dev)) |
8ceee660 BH |
1580 | return; |
1581 | ||
8ceee660 | 1582 | efx_start_port(efx); |
9f2cb71c | 1583 | efx_start_datapath(efx); |
8880f4ec | 1584 | |
78c1f0a0 SH |
1585 | /* Start the hardware monitor if there is one. Otherwise (we're link |
1586 | * event driven), we have to poll the PHY because after an event queue | |
1587 | * flush, we could have a missed a link state change */ | |
1588 | if (efx->type->monitor != NULL) { | |
8ceee660 BH |
1589 | queue_delayed_work(efx->workqueue, &efx->monitor_work, |
1590 | efx_monitor_interval); | |
78c1f0a0 SH |
1591 | } else { |
1592 | mutex_lock(&efx->mac_lock); | |
1593 | if (efx->phy_op->poll(efx)) | |
1594 | efx_link_status_changed(efx); | |
1595 | mutex_unlock(&efx->mac_lock); | |
1596 | } | |
55edc6e6 | 1597 | |
ef2b90ee | 1598 | efx->type->start_stats(efx); |
8ceee660 BH |
1599 | } |
1600 | ||
1601 | /* Flush all delayed work. Should only be called when no more delayed work | |
1602 | * will be scheduled. This doesn't flush pending online resets (efx_reset), | |
1603 | * since we're holding the rtnl_lock at this point. */ | |
1604 | static void efx_flush_all(struct efx_nic *efx) | |
1605 | { | |
dd40781e | 1606 | /* Make sure the hardware monitor and event self-test are stopped */ |
8ceee660 | 1607 | cancel_delayed_work_sync(&efx->monitor_work); |
dd40781e | 1608 | efx_selftest_async_cancel(efx); |
8ceee660 | 1609 | /* Stop scheduled port reconfigurations */ |
766ca0fa | 1610 | cancel_work_sync(&efx->mac_work); |
8ceee660 BH |
1611 | } |
1612 | ||
8b7325b4 BH |
1613 | /* Quiesce the hardware and software data path, and regular activity |
1614 | * for the port without bringing the link down. Safe to call multiple | |
1615 | * times with the NIC in almost any state, but interrupts should be | |
1616 | * enabled. Requires the RTNL lock. | |
1617 | */ | |
8ceee660 BH |
1618 | static void efx_stop_all(struct efx_nic *efx) |
1619 | { | |
8ceee660 BH |
1620 | EFX_ASSERT_RESET_SERIALISED(efx); |
1621 | ||
1622 | /* port_enabled can be read safely under the rtnl lock */ | |
1623 | if (!efx->port_enabled) | |
1624 | return; | |
1625 | ||
ef2b90ee | 1626 | efx->type->stop_stats(efx); |
8ceee660 BH |
1627 | efx_stop_port(efx); |
1628 | ||
fdaa9aed | 1629 | /* Flush efx_mac_work(), refill_workqueue, monitor_work */ |
8ceee660 BH |
1630 | efx_flush_all(efx); |
1631 | ||
8ceee660 BH |
1632 | /* Stop the kernel transmit interface late, so the watchdog |
1633 | * timer isn't ticking over the flush */ | |
9f2cb71c BH |
1634 | netif_tx_disable(efx->net_dev); |
1635 | ||
1636 | efx_stop_datapath(efx); | |
8ceee660 BH |
1637 | } |
1638 | ||
1639 | static void efx_remove_all(struct efx_nic *efx) | |
1640 | { | |
4642610c | 1641 | efx_remove_channels(efx); |
7f967c01 | 1642 | efx_remove_filters(efx); |
8ceee660 BH |
1643 | efx_remove_port(efx); |
1644 | efx_remove_nic(efx); | |
1645 | } | |
1646 | ||
8ceee660 BH |
1647 | /************************************************************************** |
1648 | * | |
1649 | * Interrupt moderation | |
1650 | * | |
1651 | **************************************************************************/ | |
1652 | ||
cc180b69 | 1653 | static unsigned int irq_mod_ticks(unsigned int usecs, unsigned int quantum_ns) |
0d86ebd8 | 1654 | { |
b548f976 BH |
1655 | if (usecs == 0) |
1656 | return 0; | |
cc180b69 | 1657 | if (usecs * 1000 < quantum_ns) |
0d86ebd8 | 1658 | return 1; /* never round down to 0 */ |
cc180b69 | 1659 | return usecs * 1000 / quantum_ns; |
0d86ebd8 BH |
1660 | } |
1661 | ||
8ceee660 | 1662 | /* Set interrupt moderation parameters */ |
9e393b30 BH |
1663 | int efx_init_irq_moderation(struct efx_nic *efx, unsigned int tx_usecs, |
1664 | unsigned int rx_usecs, bool rx_adaptive, | |
1665 | bool rx_may_override_tx) | |
8ceee660 | 1666 | { |
f7d12cdc | 1667 | struct efx_channel *channel; |
cc180b69 BH |
1668 | unsigned int irq_mod_max = DIV_ROUND_UP(efx->type->timer_period_max * |
1669 | efx->timer_quantum_ns, | |
1670 | 1000); | |
1671 | unsigned int tx_ticks; | |
1672 | unsigned int rx_ticks; | |
8ceee660 BH |
1673 | |
1674 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1675 | ||
cc180b69 | 1676 | if (tx_usecs > irq_mod_max || rx_usecs > irq_mod_max) |
9e393b30 BH |
1677 | return -EINVAL; |
1678 | ||
cc180b69 BH |
1679 | tx_ticks = irq_mod_ticks(tx_usecs, efx->timer_quantum_ns); |
1680 | rx_ticks = irq_mod_ticks(rx_usecs, efx->timer_quantum_ns); | |
1681 | ||
9e393b30 BH |
1682 | if (tx_ticks != rx_ticks && efx->tx_channel_offset == 0 && |
1683 | !rx_may_override_tx) { | |
1684 | netif_err(efx, drv, efx->net_dev, "Channels are shared. " | |
1685 | "RX and TX IRQ moderation must be equal\n"); | |
1686 | return -EINVAL; | |
1687 | } | |
1688 | ||
6fb70fd1 | 1689 | efx->irq_rx_adaptive = rx_adaptive; |
0d86ebd8 | 1690 | efx->irq_rx_moderation = rx_ticks; |
f7d12cdc | 1691 | efx_for_each_channel(channel, efx) { |
525da907 | 1692 | if (efx_channel_has_rx_queue(channel)) |
f7d12cdc | 1693 | channel->irq_moderation = rx_ticks; |
525da907 | 1694 | else if (efx_channel_has_tx_queues(channel)) |
f7d12cdc BH |
1695 | channel->irq_moderation = tx_ticks; |
1696 | } | |
9e393b30 BH |
1697 | |
1698 | return 0; | |
8ceee660 BH |
1699 | } |
1700 | ||
a0c4faf5 BH |
1701 | void efx_get_irq_moderation(struct efx_nic *efx, unsigned int *tx_usecs, |
1702 | unsigned int *rx_usecs, bool *rx_adaptive) | |
1703 | { | |
cc180b69 BH |
1704 | /* We must round up when converting ticks to microseconds |
1705 | * because we round down when converting the other way. | |
1706 | */ | |
1707 | ||
a0c4faf5 | 1708 | *rx_adaptive = efx->irq_rx_adaptive; |
cc180b69 BH |
1709 | *rx_usecs = DIV_ROUND_UP(efx->irq_rx_moderation * |
1710 | efx->timer_quantum_ns, | |
1711 | 1000); | |
a0c4faf5 BH |
1712 | |
1713 | /* If channels are shared between RX and TX, so is IRQ | |
1714 | * moderation. Otherwise, IRQ moderation is the same for all | |
1715 | * TX channels and is not adaptive. | |
1716 | */ | |
1717 | if (efx->tx_channel_offset == 0) | |
1718 | *tx_usecs = *rx_usecs; | |
1719 | else | |
cc180b69 | 1720 | *tx_usecs = DIV_ROUND_UP( |
a0c4faf5 | 1721 | efx->channel[efx->tx_channel_offset]->irq_moderation * |
cc180b69 BH |
1722 | efx->timer_quantum_ns, |
1723 | 1000); | |
a0c4faf5 BH |
1724 | } |
1725 | ||
8ceee660 BH |
1726 | /************************************************************************** |
1727 | * | |
1728 | * Hardware monitor | |
1729 | * | |
1730 | **************************************************************************/ | |
1731 | ||
e254c274 | 1732 | /* Run periodically off the general workqueue */ |
8ceee660 BH |
1733 | static void efx_monitor(struct work_struct *data) |
1734 | { | |
1735 | struct efx_nic *efx = container_of(data, struct efx_nic, | |
1736 | monitor_work.work); | |
8ceee660 | 1737 | |
62776d03 BH |
1738 | netif_vdbg(efx, timer, efx->net_dev, |
1739 | "hardware monitor executing on CPU %d\n", | |
1740 | raw_smp_processor_id()); | |
ef2b90ee | 1741 | BUG_ON(efx->type->monitor == NULL); |
8ceee660 | 1742 | |
8ceee660 BH |
1743 | /* If the mac_lock is already held then it is likely a port |
1744 | * reconfiguration is already in place, which will likely do | |
e254c274 BH |
1745 | * most of the work of monitor() anyway. */ |
1746 | if (mutex_trylock(&efx->mac_lock)) { | |
1747 | if (efx->port_enabled) | |
1748 | efx->type->monitor(efx); | |
1749 | mutex_unlock(&efx->mac_lock); | |
1750 | } | |
8ceee660 | 1751 | |
8ceee660 BH |
1752 | queue_delayed_work(efx->workqueue, &efx->monitor_work, |
1753 | efx_monitor_interval); | |
1754 | } | |
1755 | ||
1756 | /************************************************************************** | |
1757 | * | |
1758 | * ioctls | |
1759 | * | |
1760 | *************************************************************************/ | |
1761 | ||
1762 | /* Net device ioctl | |
1763 | * Context: process, rtnl_lock() held. | |
1764 | */ | |
1765 | static int efx_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd) | |
1766 | { | |
767e468c | 1767 | struct efx_nic *efx = netdev_priv(net_dev); |
68e7f45e | 1768 | struct mii_ioctl_data *data = if_mii(ifr); |
8ceee660 | 1769 | |
68e7f45e BH |
1770 | /* Convert phy_id from older PRTAD/DEVAD format */ |
1771 | if ((cmd == SIOCGMIIREG || cmd == SIOCSMIIREG) && | |
1772 | (data->phy_id & 0xfc00) == 0x0400) | |
1773 | data->phy_id ^= MDIO_PHY_ID_C45 | 0x0400; | |
1774 | ||
1775 | return mdio_mii_ioctl(&efx->mdio, data, cmd); | |
8ceee660 BH |
1776 | } |
1777 | ||
1778 | /************************************************************************** | |
1779 | * | |
1780 | * NAPI interface | |
1781 | * | |
1782 | **************************************************************************/ | |
1783 | ||
7f967c01 BH |
1784 | static void efx_init_napi_channel(struct efx_channel *channel) |
1785 | { | |
1786 | struct efx_nic *efx = channel->efx; | |
1787 | ||
1788 | channel->napi_dev = efx->net_dev; | |
1789 | netif_napi_add(channel->napi_dev, &channel->napi_str, | |
1790 | efx_poll, napi_weight); | |
1791 | } | |
1792 | ||
e8f14992 | 1793 | static void efx_init_napi(struct efx_nic *efx) |
8ceee660 BH |
1794 | { |
1795 | struct efx_channel *channel; | |
8ceee660 | 1796 | |
7f967c01 BH |
1797 | efx_for_each_channel(channel, efx) |
1798 | efx_init_napi_channel(channel); | |
e8f14992 BH |
1799 | } |
1800 | ||
1801 | static void efx_fini_napi_channel(struct efx_channel *channel) | |
1802 | { | |
1803 | if (channel->napi_dev) | |
1804 | netif_napi_del(&channel->napi_str); | |
1805 | channel->napi_dev = NULL; | |
8ceee660 BH |
1806 | } |
1807 | ||
1808 | static void efx_fini_napi(struct efx_nic *efx) | |
1809 | { | |
1810 | struct efx_channel *channel; | |
1811 | ||
e8f14992 BH |
1812 | efx_for_each_channel(channel, efx) |
1813 | efx_fini_napi_channel(channel); | |
8ceee660 BH |
1814 | } |
1815 | ||
1816 | /************************************************************************** | |
1817 | * | |
1818 | * Kernel netpoll interface | |
1819 | * | |
1820 | *************************************************************************/ | |
1821 | ||
1822 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1823 | ||
1824 | /* Although in the common case interrupts will be disabled, this is not | |
1825 | * guaranteed. However, all our work happens inside the NAPI callback, | |
1826 | * so no locking is required. | |
1827 | */ | |
1828 | static void efx_netpoll(struct net_device *net_dev) | |
1829 | { | |
767e468c | 1830 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1831 | struct efx_channel *channel; |
1832 | ||
64ee3120 | 1833 | efx_for_each_channel(channel, efx) |
8ceee660 BH |
1834 | efx_schedule_channel(channel); |
1835 | } | |
1836 | ||
1837 | #endif | |
1838 | ||
1839 | /************************************************************************** | |
1840 | * | |
1841 | * Kernel net device interface | |
1842 | * | |
1843 | *************************************************************************/ | |
1844 | ||
1845 | /* Context: process, rtnl_lock() held. */ | |
1846 | static int efx_net_open(struct net_device *net_dev) | |
1847 | { | |
767e468c | 1848 | struct efx_nic *efx = netdev_priv(net_dev); |
8b7325b4 BH |
1849 | int rc; |
1850 | ||
62776d03 BH |
1851 | netif_dbg(efx, ifup, efx->net_dev, "opening device on CPU %d\n", |
1852 | raw_smp_processor_id()); | |
8ceee660 | 1853 | |
8b7325b4 BH |
1854 | rc = efx_check_disabled(efx); |
1855 | if (rc) | |
1856 | return rc; | |
f8b87c17 BH |
1857 | if (efx->phy_mode & PHY_MODE_SPECIAL) |
1858 | return -EBUSY; | |
8880f4ec BH |
1859 | if (efx_mcdi_poll_reboot(efx) && efx_reset(efx, RESET_TYPE_ALL)) |
1860 | return -EIO; | |
f8b87c17 | 1861 | |
78c1f0a0 SH |
1862 | /* Notify the kernel of the link state polled during driver load, |
1863 | * before the monitor starts running */ | |
1864 | efx_link_status_changed(efx); | |
1865 | ||
8ceee660 | 1866 | efx_start_all(efx); |
dd40781e | 1867 | efx_selftest_async_start(efx); |
8ceee660 BH |
1868 | return 0; |
1869 | } | |
1870 | ||
1871 | /* Context: process, rtnl_lock() held. | |
1872 | * Note that the kernel will ignore our return code; this method | |
1873 | * should really be a void. | |
1874 | */ | |
1875 | static int efx_net_stop(struct net_device *net_dev) | |
1876 | { | |
767e468c | 1877 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 | 1878 | |
62776d03 BH |
1879 | netif_dbg(efx, ifdown, efx->net_dev, "closing on CPU %d\n", |
1880 | raw_smp_processor_id()); | |
8ceee660 | 1881 | |
8b7325b4 BH |
1882 | /* Stop the device and flush all the channels */ |
1883 | efx_stop_all(efx); | |
8ceee660 BH |
1884 | |
1885 | return 0; | |
1886 | } | |
1887 | ||
5b9e207c | 1888 | /* Context: process, dev_base_lock or RTNL held, non-blocking. */ |
2aa9ef11 BH |
1889 | static struct rtnl_link_stats64 *efx_net_stats(struct net_device *net_dev, |
1890 | struct rtnl_link_stats64 *stats) | |
8ceee660 | 1891 | { |
767e468c | 1892 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 | 1893 | struct efx_mac_stats *mac_stats = &efx->mac_stats; |
8ceee660 | 1894 | |
55edc6e6 | 1895 | spin_lock_bh(&efx->stats_lock); |
1cb34522 | 1896 | |
ef2b90ee | 1897 | efx->type->update_stats(efx); |
8ceee660 BH |
1898 | |
1899 | stats->rx_packets = mac_stats->rx_packets; | |
1900 | stats->tx_packets = mac_stats->tx_packets; | |
1901 | stats->rx_bytes = mac_stats->rx_bytes; | |
1902 | stats->tx_bytes = mac_stats->tx_bytes; | |
80485d34 | 1903 | stats->rx_dropped = efx->n_rx_nodesc_drop_cnt; |
8ceee660 BH |
1904 | stats->multicast = mac_stats->rx_multicast; |
1905 | stats->collisions = mac_stats->tx_collision; | |
1906 | stats->rx_length_errors = (mac_stats->rx_gtjumbo + | |
1907 | mac_stats->rx_length_error); | |
8ceee660 BH |
1908 | stats->rx_crc_errors = mac_stats->rx_bad; |
1909 | stats->rx_frame_errors = mac_stats->rx_align_error; | |
1910 | stats->rx_fifo_errors = mac_stats->rx_overflow; | |
1911 | stats->rx_missed_errors = mac_stats->rx_missed; | |
1912 | stats->tx_window_errors = mac_stats->tx_late_collision; | |
1913 | ||
1914 | stats->rx_errors = (stats->rx_length_errors + | |
8ceee660 BH |
1915 | stats->rx_crc_errors + |
1916 | stats->rx_frame_errors + | |
8ceee660 BH |
1917 | mac_stats->rx_symbol_error); |
1918 | stats->tx_errors = (stats->tx_window_errors + | |
1919 | mac_stats->tx_bad); | |
1920 | ||
1cb34522 BH |
1921 | spin_unlock_bh(&efx->stats_lock); |
1922 | ||
8ceee660 BH |
1923 | return stats; |
1924 | } | |
1925 | ||
1926 | /* Context: netif_tx_lock held, BHs disabled. */ | |
1927 | static void efx_watchdog(struct net_device *net_dev) | |
1928 | { | |
767e468c | 1929 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 | 1930 | |
62776d03 BH |
1931 | netif_err(efx, tx_err, efx->net_dev, |
1932 | "TX stuck with port_enabled=%d: resetting channels\n", | |
1933 | efx->port_enabled); | |
8ceee660 | 1934 | |
739bb23d | 1935 | efx_schedule_reset(efx, RESET_TYPE_TX_WATCHDOG); |
8ceee660 BH |
1936 | } |
1937 | ||
1938 | ||
1939 | /* Context: process, rtnl_lock() held. */ | |
1940 | static int efx_change_mtu(struct net_device *net_dev, int new_mtu) | |
1941 | { | |
767e468c | 1942 | struct efx_nic *efx = netdev_priv(net_dev); |
8b7325b4 | 1943 | int rc; |
8ceee660 | 1944 | |
8b7325b4 BH |
1945 | rc = efx_check_disabled(efx); |
1946 | if (rc) | |
1947 | return rc; | |
8ceee660 BH |
1948 | if (new_mtu > EFX_MAX_MTU) |
1949 | return -EINVAL; | |
1950 | ||
1951 | efx_stop_all(efx); | |
1952 | ||
62776d03 | 1953 | netif_dbg(efx, drv, efx->net_dev, "changing MTU to %d\n", new_mtu); |
8ceee660 | 1954 | |
d3245b28 | 1955 | mutex_lock(&efx->mac_lock); |
8ceee660 | 1956 | net_dev->mtu = new_mtu; |
710b208d | 1957 | efx->type->reconfigure_mac(efx); |
d3245b28 BH |
1958 | mutex_unlock(&efx->mac_lock); |
1959 | ||
8ceee660 | 1960 | efx_start_all(efx); |
6c8eef4a | 1961 | return 0; |
8ceee660 BH |
1962 | } |
1963 | ||
1964 | static int efx_set_mac_address(struct net_device *net_dev, void *data) | |
1965 | { | |
767e468c | 1966 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1967 | struct sockaddr *addr = data; |
1968 | char *new_addr = addr->sa_data; | |
1969 | ||
8ceee660 | 1970 | if (!is_valid_ether_addr(new_addr)) { |
62776d03 BH |
1971 | netif_err(efx, drv, efx->net_dev, |
1972 | "invalid ethernet MAC address requested: %pM\n", | |
1973 | new_addr); | |
504f9b5a | 1974 | return -EADDRNOTAVAIL; |
8ceee660 BH |
1975 | } |
1976 | ||
1977 | memcpy(net_dev->dev_addr, new_addr, net_dev->addr_len); | |
cd2d5b52 | 1978 | efx_sriov_mac_address_changed(efx); |
8ceee660 BH |
1979 | |
1980 | /* Reconfigure the MAC */ | |
d3245b28 | 1981 | mutex_lock(&efx->mac_lock); |
710b208d | 1982 | efx->type->reconfigure_mac(efx); |
d3245b28 | 1983 | mutex_unlock(&efx->mac_lock); |
8ceee660 BH |
1984 | |
1985 | return 0; | |
1986 | } | |
1987 | ||
a816f75a | 1988 | /* Context: netif_addr_lock held, BHs disabled. */ |
0fca8c97 | 1989 | static void efx_set_rx_mode(struct net_device *net_dev) |
8ceee660 | 1990 | { |
767e468c | 1991 | struct efx_nic *efx = netdev_priv(net_dev); |
22bedad3 | 1992 | struct netdev_hw_addr *ha; |
8ceee660 | 1993 | union efx_multicast_hash *mc_hash = &efx->multicast_hash; |
8ceee660 BH |
1994 | u32 crc; |
1995 | int bit; | |
8ceee660 | 1996 | |
8be4f3e6 | 1997 | efx->promiscuous = !!(net_dev->flags & IFF_PROMISC); |
8ceee660 BH |
1998 | |
1999 | /* Build multicast hash table */ | |
8be4f3e6 | 2000 | if (efx->promiscuous || (net_dev->flags & IFF_ALLMULTI)) { |
8ceee660 BH |
2001 | memset(mc_hash, 0xff, sizeof(*mc_hash)); |
2002 | } else { | |
2003 | memset(mc_hash, 0x00, sizeof(*mc_hash)); | |
22bedad3 JP |
2004 | netdev_for_each_mc_addr(ha, net_dev) { |
2005 | crc = ether_crc_le(ETH_ALEN, ha->addr); | |
8ceee660 BH |
2006 | bit = crc & (EFX_MCAST_HASH_ENTRIES - 1); |
2007 | set_bit_le(bit, mc_hash->byte); | |
8ceee660 | 2008 | } |
8ceee660 | 2009 | |
8be4f3e6 BH |
2010 | /* Broadcast packets go through the multicast hash filter. |
2011 | * ether_crc_le() of the broadcast address is 0xbe2612ff | |
2012 | * so we always add bit 0xff to the mask. | |
2013 | */ | |
2014 | set_bit_le(0xff, mc_hash->byte); | |
2015 | } | |
a816f75a | 2016 | |
8be4f3e6 BH |
2017 | if (efx->port_enabled) |
2018 | queue_work(efx->workqueue, &efx->mac_work); | |
2019 | /* Otherwise efx_start_port() will do this */ | |
8ceee660 BH |
2020 | } |
2021 | ||
c8f44aff | 2022 | static int efx_set_features(struct net_device *net_dev, netdev_features_t data) |
abfe9039 BH |
2023 | { |
2024 | struct efx_nic *efx = netdev_priv(net_dev); | |
2025 | ||
2026 | /* If disabling RX n-tuple filtering, clear existing filters */ | |
2027 | if (net_dev->features & ~data & NETIF_F_NTUPLE) | |
2028 | efx_filter_clear_rx(efx, EFX_FILTER_PRI_MANUAL); | |
2029 | ||
2030 | return 0; | |
2031 | } | |
2032 | ||
c3ecb9f3 SH |
2033 | static const struct net_device_ops efx_netdev_ops = { |
2034 | .ndo_open = efx_net_open, | |
2035 | .ndo_stop = efx_net_stop, | |
4472702e | 2036 | .ndo_get_stats64 = efx_net_stats, |
c3ecb9f3 SH |
2037 | .ndo_tx_timeout = efx_watchdog, |
2038 | .ndo_start_xmit = efx_hard_start_xmit, | |
2039 | .ndo_validate_addr = eth_validate_addr, | |
2040 | .ndo_do_ioctl = efx_ioctl, | |
2041 | .ndo_change_mtu = efx_change_mtu, | |
2042 | .ndo_set_mac_address = efx_set_mac_address, | |
0fca8c97 | 2043 | .ndo_set_rx_mode = efx_set_rx_mode, |
abfe9039 | 2044 | .ndo_set_features = efx_set_features, |
cd2d5b52 BH |
2045 | #ifdef CONFIG_SFC_SRIOV |
2046 | .ndo_set_vf_mac = efx_sriov_set_vf_mac, | |
2047 | .ndo_set_vf_vlan = efx_sriov_set_vf_vlan, | |
2048 | .ndo_set_vf_spoofchk = efx_sriov_set_vf_spoofchk, | |
2049 | .ndo_get_vf_config = efx_sriov_get_vf_config, | |
2050 | #endif | |
c3ecb9f3 SH |
2051 | #ifdef CONFIG_NET_POLL_CONTROLLER |
2052 | .ndo_poll_controller = efx_netpoll, | |
2053 | #endif | |
94b274bf | 2054 | .ndo_setup_tc = efx_setup_tc, |
64d8ad6d BH |
2055 | #ifdef CONFIG_RFS_ACCEL |
2056 | .ndo_rx_flow_steer = efx_filter_rfs, | |
2057 | #endif | |
c3ecb9f3 SH |
2058 | }; |
2059 | ||
7dde596e BH |
2060 | static void efx_update_name(struct efx_nic *efx) |
2061 | { | |
2062 | strcpy(efx->name, efx->net_dev->name); | |
2063 | efx_mtd_rename(efx); | |
2064 | efx_set_channel_names(efx); | |
2065 | } | |
2066 | ||
8ceee660 BH |
2067 | static int efx_netdev_event(struct notifier_block *this, |
2068 | unsigned long event, void *ptr) | |
2069 | { | |
d3208b5e | 2070 | struct net_device *net_dev = ptr; |
8ceee660 | 2071 | |
7dde596e BH |
2072 | if (net_dev->netdev_ops == &efx_netdev_ops && |
2073 | event == NETDEV_CHANGENAME) | |
2074 | efx_update_name(netdev_priv(net_dev)); | |
8ceee660 BH |
2075 | |
2076 | return NOTIFY_DONE; | |
2077 | } | |
2078 | ||
2079 | static struct notifier_block efx_netdev_notifier = { | |
2080 | .notifier_call = efx_netdev_event, | |
2081 | }; | |
2082 | ||
06d5e193 BH |
2083 | static ssize_t |
2084 | show_phy_type(struct device *dev, struct device_attribute *attr, char *buf) | |
2085 | { | |
2086 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); | |
2087 | return sprintf(buf, "%d\n", efx->phy_type); | |
2088 | } | |
2089 | static DEVICE_ATTR(phy_type, 0644, show_phy_type, NULL); | |
2090 | ||
8ceee660 BH |
2091 | static int efx_register_netdev(struct efx_nic *efx) |
2092 | { | |
2093 | struct net_device *net_dev = efx->net_dev; | |
c04bfc6b | 2094 | struct efx_channel *channel; |
8ceee660 BH |
2095 | int rc; |
2096 | ||
2097 | net_dev->watchdog_timeo = 5 * HZ; | |
2098 | net_dev->irq = efx->pci_dev->irq; | |
c3ecb9f3 | 2099 | net_dev->netdev_ops = &efx_netdev_ops; |
8ceee660 | 2100 | SET_ETHTOOL_OPS(net_dev, &efx_ethtool_ops); |
7e6d06f0 | 2101 | net_dev->gso_max_segs = EFX_TSO_MAX_SEGS; |
8ceee660 | 2102 | |
7dde596e | 2103 | rtnl_lock(); |
aed0628d | 2104 | |
7153f623 BH |
2105 | /* Enable resets to be scheduled and check whether any were |
2106 | * already requested. If so, the NIC is probably hosed so we | |
2107 | * abort. | |
2108 | */ | |
2109 | efx->state = STATE_READY; | |
2110 | smp_mb(); /* ensure we change state before checking reset_pending */ | |
2111 | if (efx->reset_pending) { | |
2112 | netif_err(efx, probe, efx->net_dev, | |
2113 | "aborting probe due to scheduled reset\n"); | |
2114 | rc = -EIO; | |
2115 | goto fail_locked; | |
2116 | } | |
2117 | ||
aed0628d BH |
2118 | rc = dev_alloc_name(net_dev, net_dev->name); |
2119 | if (rc < 0) | |
2120 | goto fail_locked; | |
7dde596e | 2121 | efx_update_name(efx); |
aed0628d | 2122 | |
8f8b3d51 BH |
2123 | /* Always start with carrier off; PHY events will detect the link */ |
2124 | netif_carrier_off(net_dev); | |
2125 | ||
aed0628d BH |
2126 | rc = register_netdevice(net_dev); |
2127 | if (rc) | |
2128 | goto fail_locked; | |
2129 | ||
c04bfc6b BH |
2130 | efx_for_each_channel(channel, efx) { |
2131 | struct efx_tx_queue *tx_queue; | |
60031fcc BH |
2132 | efx_for_each_channel_tx_queue(tx_queue, channel) |
2133 | efx_init_tx_queue_core_txq(tx_queue); | |
c04bfc6b BH |
2134 | } |
2135 | ||
7dde596e | 2136 | rtnl_unlock(); |
8ceee660 | 2137 | |
06d5e193 BH |
2138 | rc = device_create_file(&efx->pci_dev->dev, &dev_attr_phy_type); |
2139 | if (rc) { | |
62776d03 BH |
2140 | netif_err(efx, drv, efx->net_dev, |
2141 | "failed to init net dev attributes\n"); | |
06d5e193 BH |
2142 | goto fail_registered; |
2143 | } | |
2144 | ||
8ceee660 | 2145 | return 0; |
06d5e193 | 2146 | |
7153f623 BH |
2147 | fail_registered: |
2148 | rtnl_lock(); | |
2149 | unregister_netdevice(net_dev); | |
aed0628d | 2150 | fail_locked: |
7153f623 | 2151 | efx->state = STATE_UNINIT; |
aed0628d | 2152 | rtnl_unlock(); |
62776d03 | 2153 | netif_err(efx, drv, efx->net_dev, "could not register net dev\n"); |
aed0628d | 2154 | return rc; |
8ceee660 BH |
2155 | } |
2156 | ||
2157 | static void efx_unregister_netdev(struct efx_nic *efx) | |
2158 | { | |
f7d12cdc | 2159 | struct efx_channel *channel; |
8ceee660 BH |
2160 | struct efx_tx_queue *tx_queue; |
2161 | ||
2162 | if (!efx->net_dev) | |
2163 | return; | |
2164 | ||
767e468c | 2165 | BUG_ON(netdev_priv(efx->net_dev) != efx); |
8ceee660 BH |
2166 | |
2167 | /* Free up any skbs still remaining. This has to happen before | |
2168 | * we try to unregister the netdev as running their destructors | |
2169 | * may be needed to get the device ref. count to 0. */ | |
f7d12cdc BH |
2170 | efx_for_each_channel(channel, efx) { |
2171 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
2172 | efx_release_tx_buffers(tx_queue); | |
2173 | } | |
8ceee660 | 2174 | |
73ba7b68 BH |
2175 | strlcpy(efx->name, pci_name(efx->pci_dev), sizeof(efx->name)); |
2176 | device_remove_file(&efx->pci_dev->dev, &dev_attr_phy_type); | |
7153f623 BH |
2177 | |
2178 | rtnl_lock(); | |
2179 | unregister_netdevice(efx->net_dev); | |
2180 | efx->state = STATE_UNINIT; | |
2181 | rtnl_unlock(); | |
8ceee660 BH |
2182 | } |
2183 | ||
2184 | /************************************************************************** | |
2185 | * | |
2186 | * Device reset and suspend | |
2187 | * | |
2188 | **************************************************************************/ | |
2189 | ||
2467ca46 BH |
2190 | /* Tears down the entire software state and most of the hardware state |
2191 | * before reset. */ | |
d3245b28 | 2192 | void efx_reset_down(struct efx_nic *efx, enum reset_type method) |
8ceee660 | 2193 | { |
8ceee660 BH |
2194 | EFX_ASSERT_RESET_SERIALISED(efx); |
2195 | ||
2467ca46 | 2196 | efx_stop_all(efx); |
7f967c01 | 2197 | efx_stop_interrupts(efx, false); |
5642ceef BH |
2198 | |
2199 | mutex_lock(&efx->mac_lock); | |
4b988280 SH |
2200 | if (efx->port_initialized && method != RESET_TYPE_INVISIBLE) |
2201 | efx->phy_op->fini(efx); | |
ef2b90ee | 2202 | efx->type->fini(efx); |
8ceee660 BH |
2203 | } |
2204 | ||
2467ca46 BH |
2205 | /* This function will always ensure that the locks acquired in |
2206 | * efx_reset_down() are released. A failure return code indicates | |
2207 | * that we were unable to reinitialise the hardware, and the | |
2208 | * driver should be disabled. If ok is false, then the rx and tx | |
2209 | * engines are not restarted, pending a RESET_DISABLE. */ | |
d3245b28 | 2210 | int efx_reset_up(struct efx_nic *efx, enum reset_type method, bool ok) |
8ceee660 BH |
2211 | { |
2212 | int rc; | |
2213 | ||
2467ca46 | 2214 | EFX_ASSERT_RESET_SERIALISED(efx); |
8ceee660 | 2215 | |
ef2b90ee | 2216 | rc = efx->type->init(efx); |
8ceee660 | 2217 | if (rc) { |
62776d03 | 2218 | netif_err(efx, drv, efx->net_dev, "failed to initialise NIC\n"); |
eb9f6744 | 2219 | goto fail; |
8ceee660 BH |
2220 | } |
2221 | ||
eb9f6744 BH |
2222 | if (!ok) |
2223 | goto fail; | |
2224 | ||
4b988280 | 2225 | if (efx->port_initialized && method != RESET_TYPE_INVISIBLE) { |
eb9f6744 BH |
2226 | rc = efx->phy_op->init(efx); |
2227 | if (rc) | |
2228 | goto fail; | |
2229 | if (efx->phy_op->reconfigure(efx)) | |
62776d03 BH |
2230 | netif_err(efx, drv, efx->net_dev, |
2231 | "could not restore PHY settings\n"); | |
4b988280 SH |
2232 | } |
2233 | ||
710b208d | 2234 | efx->type->reconfigure_mac(efx); |
8ceee660 | 2235 | |
7f967c01 | 2236 | efx_start_interrupts(efx, false); |
64eebcfd | 2237 | efx_restore_filters(efx); |
cd2d5b52 | 2238 | efx_sriov_reset(efx); |
eb9f6744 | 2239 | |
eb9f6744 BH |
2240 | mutex_unlock(&efx->mac_lock); |
2241 | ||
2242 | efx_start_all(efx); | |
2243 | ||
2244 | return 0; | |
2245 | ||
2246 | fail: | |
2247 | efx->port_initialized = false; | |
2467ca46 BH |
2248 | |
2249 | mutex_unlock(&efx->mac_lock); | |
2250 | ||
8ceee660 BH |
2251 | return rc; |
2252 | } | |
2253 | ||
eb9f6744 BH |
2254 | /* Reset the NIC using the specified method. Note that the reset may |
2255 | * fail, in which case the card will be left in an unusable state. | |
8ceee660 | 2256 | * |
eb9f6744 | 2257 | * Caller must hold the rtnl_lock. |
8ceee660 | 2258 | */ |
eb9f6744 | 2259 | int efx_reset(struct efx_nic *efx, enum reset_type method) |
8ceee660 | 2260 | { |
eb9f6744 BH |
2261 | int rc, rc2; |
2262 | bool disabled; | |
8ceee660 | 2263 | |
62776d03 BH |
2264 | netif_info(efx, drv, efx->net_dev, "resetting (%s)\n", |
2265 | RESET_TYPE(method)); | |
8ceee660 | 2266 | |
e4abce85 | 2267 | netif_device_detach(efx->net_dev); |
d3245b28 | 2268 | efx_reset_down(efx, method); |
8ceee660 | 2269 | |
ef2b90ee | 2270 | rc = efx->type->reset(efx, method); |
8ceee660 | 2271 | if (rc) { |
62776d03 | 2272 | netif_err(efx, drv, efx->net_dev, "failed to reset hardware\n"); |
eb9f6744 | 2273 | goto out; |
8ceee660 BH |
2274 | } |
2275 | ||
a7d529ae BH |
2276 | /* Clear flags for the scopes we covered. We assume the NIC and |
2277 | * driver are now quiescent so that there is no race here. | |
2278 | */ | |
2279 | efx->reset_pending &= -(1 << (method + 1)); | |
8ceee660 BH |
2280 | |
2281 | /* Reinitialise bus-mastering, which may have been turned off before | |
2282 | * the reset was scheduled. This is still appropriate, even in the | |
2283 | * RESET_TYPE_DISABLE since this driver generally assumes the hardware | |
2284 | * can respond to requests. */ | |
2285 | pci_set_master(efx->pci_dev); | |
2286 | ||
eb9f6744 | 2287 | out: |
8ceee660 | 2288 | /* Leave device stopped if necessary */ |
eb9f6744 BH |
2289 | disabled = rc || method == RESET_TYPE_DISABLE; |
2290 | rc2 = efx_reset_up(efx, method, !disabled); | |
2291 | if (rc2) { | |
2292 | disabled = true; | |
2293 | if (!rc) | |
2294 | rc = rc2; | |
8ceee660 BH |
2295 | } |
2296 | ||
eb9f6744 | 2297 | if (disabled) { |
f49a4589 | 2298 | dev_close(efx->net_dev); |
62776d03 | 2299 | netif_err(efx, drv, efx->net_dev, "has been disabled\n"); |
f4bd954e | 2300 | efx->state = STATE_DISABLED; |
f4bd954e | 2301 | } else { |
62776d03 | 2302 | netif_dbg(efx, drv, efx->net_dev, "reset complete\n"); |
e4abce85 | 2303 | netif_device_attach(efx->net_dev); |
f4bd954e | 2304 | } |
8ceee660 BH |
2305 | return rc; |
2306 | } | |
2307 | ||
2308 | /* The worker thread exists so that code that cannot sleep can | |
2309 | * schedule a reset for later. | |
2310 | */ | |
2311 | static void efx_reset_work(struct work_struct *data) | |
2312 | { | |
eb9f6744 | 2313 | struct efx_nic *efx = container_of(data, struct efx_nic, reset_work); |
a7d529ae | 2314 | unsigned long pending = ACCESS_ONCE(efx->reset_pending); |
8ceee660 | 2315 | |
a7d529ae | 2316 | if (!pending) |
319ba649 SH |
2317 | return; |
2318 | ||
eb9f6744 | 2319 | rtnl_lock(); |
7153f623 BH |
2320 | |
2321 | /* We checked the state in efx_schedule_reset() but it may | |
2322 | * have changed by now. Now that we have the RTNL lock, | |
2323 | * it cannot change again. | |
2324 | */ | |
2325 | if (efx->state == STATE_READY) | |
2326 | (void)efx_reset(efx, fls(pending) - 1); | |
2327 | ||
eb9f6744 | 2328 | rtnl_unlock(); |
8ceee660 BH |
2329 | } |
2330 | ||
2331 | void efx_schedule_reset(struct efx_nic *efx, enum reset_type type) | |
2332 | { | |
2333 | enum reset_type method; | |
2334 | ||
8ceee660 BH |
2335 | switch (type) { |
2336 | case RESET_TYPE_INVISIBLE: | |
2337 | case RESET_TYPE_ALL: | |
2338 | case RESET_TYPE_WORLD: | |
2339 | case RESET_TYPE_DISABLE: | |
2340 | method = type; | |
0e2a9c7c BH |
2341 | netif_dbg(efx, drv, efx->net_dev, "scheduling %s reset\n", |
2342 | RESET_TYPE(method)); | |
8ceee660 | 2343 | break; |
8ceee660 | 2344 | default: |
0e2a9c7c | 2345 | method = efx->type->map_reset_reason(type); |
62776d03 BH |
2346 | netif_dbg(efx, drv, efx->net_dev, |
2347 | "scheduling %s reset for %s\n", | |
2348 | RESET_TYPE(method), RESET_TYPE(type)); | |
0e2a9c7c BH |
2349 | break; |
2350 | } | |
8ceee660 | 2351 | |
a7d529ae | 2352 | set_bit(method, &efx->reset_pending); |
7153f623 BH |
2353 | smp_mb(); /* ensure we change reset_pending before checking state */ |
2354 | ||
2355 | /* If we're not READY then just leave the flags set as the cue | |
2356 | * to abort probing or reschedule the reset later. | |
2357 | */ | |
2358 | if (ACCESS_ONCE(efx->state) != STATE_READY) | |
2359 | return; | |
8ceee660 | 2360 | |
8880f4ec BH |
2361 | /* efx_process_channel() will no longer read events once a |
2362 | * reset is scheduled. So switch back to poll'd MCDI completions. */ | |
2363 | efx_mcdi_mode_poll(efx); | |
2364 | ||
1ab00629 | 2365 | queue_work(reset_workqueue, &efx->reset_work); |
8ceee660 BH |
2366 | } |
2367 | ||
2368 | /************************************************************************** | |
2369 | * | |
2370 | * List of NICs we support | |
2371 | * | |
2372 | **************************************************************************/ | |
2373 | ||
2374 | /* PCI device ID table */ | |
a3aa1884 | 2375 | static DEFINE_PCI_DEVICE_TABLE(efx_pci_table) = { |
937383a5 BH |
2376 | {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, |
2377 | PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0), | |
daeda630 | 2378 | .driver_data = (unsigned long) &falcon_a1_nic_type}, |
937383a5 BH |
2379 | {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, |
2380 | PCI_DEVICE_ID_SOLARFLARE_SFC4000B), | |
daeda630 | 2381 | .driver_data = (unsigned long) &falcon_b0_nic_type}, |
547c474f | 2382 | {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0803), /* SFC9020 */ |
8880f4ec | 2383 | .driver_data = (unsigned long) &siena_a0_nic_type}, |
547c474f | 2384 | {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0813), /* SFL9021 */ |
8880f4ec | 2385 | .driver_data = (unsigned long) &siena_a0_nic_type}, |
8ceee660 BH |
2386 | {0} /* end of list */ |
2387 | }; | |
2388 | ||
2389 | /************************************************************************** | |
2390 | * | |
3759433d | 2391 | * Dummy PHY/MAC operations |
8ceee660 | 2392 | * |
01aad7b6 | 2393 | * Can be used for some unimplemented operations |
8ceee660 BH |
2394 | * Needed so all function pointers are valid and do not have to be tested |
2395 | * before use | |
2396 | * | |
2397 | **************************************************************************/ | |
2398 | int efx_port_dummy_op_int(struct efx_nic *efx) | |
2399 | { | |
2400 | return 0; | |
2401 | } | |
2402 | void efx_port_dummy_op_void(struct efx_nic *efx) {} | |
d215697f | 2403 | |
2404 | static bool efx_port_dummy_op_poll(struct efx_nic *efx) | |
fdaa9aed SH |
2405 | { |
2406 | return false; | |
2407 | } | |
8ceee660 | 2408 | |
6c8c2513 | 2409 | static const struct efx_phy_operations efx_dummy_phy_operations = { |
8ceee660 | 2410 | .init = efx_port_dummy_op_int, |
d3245b28 | 2411 | .reconfigure = efx_port_dummy_op_int, |
fdaa9aed | 2412 | .poll = efx_port_dummy_op_poll, |
8ceee660 | 2413 | .fini = efx_port_dummy_op_void, |
8ceee660 BH |
2414 | }; |
2415 | ||
8ceee660 BH |
2416 | /************************************************************************** |
2417 | * | |
2418 | * Data housekeeping | |
2419 | * | |
2420 | **************************************************************************/ | |
2421 | ||
2422 | /* This zeroes out and then fills in the invariants in a struct | |
2423 | * efx_nic (including all sub-structures). | |
2424 | */ | |
adeb15aa | 2425 | static int efx_init_struct(struct efx_nic *efx, |
8ceee660 BH |
2426 | struct pci_dev *pci_dev, struct net_device *net_dev) |
2427 | { | |
4642610c | 2428 | int i; |
8ceee660 BH |
2429 | |
2430 | /* Initialise common structures */ | |
8ceee660 | 2431 | spin_lock_init(&efx->biu_lock); |
76884835 BH |
2432 | #ifdef CONFIG_SFC_MTD |
2433 | INIT_LIST_HEAD(&efx->mtd_list); | |
2434 | #endif | |
8ceee660 BH |
2435 | INIT_WORK(&efx->reset_work, efx_reset_work); |
2436 | INIT_DELAYED_WORK(&efx->monitor_work, efx_monitor); | |
dd40781e | 2437 | INIT_DELAYED_WORK(&efx->selftest_work, efx_selftest_async_work); |
8ceee660 | 2438 | efx->pci_dev = pci_dev; |
62776d03 | 2439 | efx->msg_enable = debug; |
f16aeea0 | 2440 | efx->state = STATE_UNINIT; |
8ceee660 | 2441 | strlcpy(efx->name, pci_name(pci_dev), sizeof(efx->name)); |
8ceee660 BH |
2442 | |
2443 | efx->net_dev = net_dev; | |
8ceee660 BH |
2444 | spin_lock_init(&efx->stats_lock); |
2445 | mutex_init(&efx->mac_lock); | |
2446 | efx->phy_op = &efx_dummy_phy_operations; | |
68e7f45e | 2447 | efx->mdio.dev = net_dev; |
766ca0fa | 2448 | INIT_WORK(&efx->mac_work, efx_mac_work); |
9f2cb71c | 2449 | init_waitqueue_head(&efx->flush_wq); |
8ceee660 BH |
2450 | |
2451 | for (i = 0; i < EFX_MAX_CHANNELS; i++) { | |
4642610c BH |
2452 | efx->channel[i] = efx_alloc_channel(efx, i, NULL); |
2453 | if (!efx->channel[i]) | |
2454 | goto fail; | |
8ceee660 BH |
2455 | } |
2456 | ||
8ceee660 BH |
2457 | EFX_BUG_ON_PARANOID(efx->type->phys_addr_channels > EFX_MAX_CHANNELS); |
2458 | ||
2459 | /* Higher numbered interrupt modes are less capable! */ | |
2460 | efx->interrupt_mode = max(efx->type->max_interrupt_mode, | |
2461 | interrupt_mode); | |
2462 | ||
6977dc63 BH |
2463 | /* Would be good to use the net_dev name, but we're too early */ |
2464 | snprintf(efx->workqueue_name, sizeof(efx->workqueue_name), "sfc%s", | |
2465 | pci_name(pci_dev)); | |
2466 | efx->workqueue = create_singlethread_workqueue(efx->workqueue_name); | |
1ab00629 | 2467 | if (!efx->workqueue) |
4642610c | 2468 | goto fail; |
8d9853d9 | 2469 | |
8ceee660 | 2470 | return 0; |
4642610c BH |
2471 | |
2472 | fail: | |
2473 | efx_fini_struct(efx); | |
2474 | return -ENOMEM; | |
8ceee660 BH |
2475 | } |
2476 | ||
2477 | static void efx_fini_struct(struct efx_nic *efx) | |
2478 | { | |
8313aca3 BH |
2479 | int i; |
2480 | ||
2481 | for (i = 0; i < EFX_MAX_CHANNELS; i++) | |
2482 | kfree(efx->channel[i]); | |
2483 | ||
8ceee660 BH |
2484 | if (efx->workqueue) { |
2485 | destroy_workqueue(efx->workqueue); | |
2486 | efx->workqueue = NULL; | |
2487 | } | |
2488 | } | |
2489 | ||
2490 | /************************************************************************** | |
2491 | * | |
2492 | * PCI interface | |
2493 | * | |
2494 | **************************************************************************/ | |
2495 | ||
2496 | /* Main body of final NIC shutdown code | |
2497 | * This is called only at module unload (or hotplug removal). | |
2498 | */ | |
2499 | static void efx_pci_remove_main(struct efx_nic *efx) | |
2500 | { | |
7153f623 BH |
2501 | /* Flush reset_work. It can no longer be scheduled since we |
2502 | * are not READY. | |
2503 | */ | |
2504 | BUG_ON(efx->state == STATE_READY); | |
2505 | cancel_work_sync(&efx->reset_work); | |
2506 | ||
64d8ad6d BH |
2507 | #ifdef CONFIG_RFS_ACCEL |
2508 | free_irq_cpu_rmap(efx->net_dev->rx_cpu_rmap); | |
2509 | efx->net_dev->rx_cpu_rmap = NULL; | |
2510 | #endif | |
7f967c01 | 2511 | efx_stop_interrupts(efx, false); |
152b6a62 | 2512 | efx_nic_fini_interrupt(efx); |
8ceee660 | 2513 | efx_fini_port(efx); |
ef2b90ee | 2514 | efx->type->fini(efx); |
8ceee660 BH |
2515 | efx_fini_napi(efx); |
2516 | efx_remove_all(efx); | |
2517 | } | |
2518 | ||
2519 | /* Final NIC shutdown | |
2520 | * This is called only at module unload (or hotplug removal). | |
2521 | */ | |
2522 | static void efx_pci_remove(struct pci_dev *pci_dev) | |
2523 | { | |
2524 | struct efx_nic *efx; | |
2525 | ||
2526 | efx = pci_get_drvdata(pci_dev); | |
2527 | if (!efx) | |
2528 | return; | |
2529 | ||
2530 | /* Mark the NIC as fini, then stop the interface */ | |
2531 | rtnl_lock(); | |
8ceee660 | 2532 | dev_close(efx->net_dev); |
5642ceef | 2533 | efx_stop_interrupts(efx, false); |
8ceee660 BH |
2534 | rtnl_unlock(); |
2535 | ||
cd2d5b52 | 2536 | efx_sriov_fini(efx); |
8ceee660 BH |
2537 | efx_unregister_netdev(efx); |
2538 | ||
7dde596e BH |
2539 | efx_mtd_remove(efx); |
2540 | ||
8ceee660 BH |
2541 | efx_pci_remove_main(efx); |
2542 | ||
8ceee660 | 2543 | efx_fini_io(efx); |
62776d03 | 2544 | netif_dbg(efx, drv, efx->net_dev, "shutdown successful\n"); |
8ceee660 | 2545 | |
8ceee660 | 2546 | efx_fini_struct(efx); |
3de4e301 | 2547 | pci_set_drvdata(pci_dev, NULL); |
8ceee660 BH |
2548 | free_netdev(efx->net_dev); |
2549 | }; | |
2550 | ||
460eeaa0 BH |
2551 | /* NIC VPD information |
2552 | * Called during probe to display the part number of the | |
2553 | * installed NIC. VPD is potentially very large but this should | |
2554 | * always appear within the first 512 bytes. | |
2555 | */ | |
2556 | #define SFC_VPD_LEN 512 | |
2557 | static void efx_print_product_vpd(struct efx_nic *efx) | |
2558 | { | |
2559 | struct pci_dev *dev = efx->pci_dev; | |
2560 | char vpd_data[SFC_VPD_LEN]; | |
2561 | ssize_t vpd_size; | |
2562 | int i, j; | |
2563 | ||
2564 | /* Get the vpd data from the device */ | |
2565 | vpd_size = pci_read_vpd(dev, 0, sizeof(vpd_data), vpd_data); | |
2566 | if (vpd_size <= 0) { | |
2567 | netif_err(efx, drv, efx->net_dev, "Unable to read VPD\n"); | |
2568 | return; | |
2569 | } | |
2570 | ||
2571 | /* Get the Read only section */ | |
2572 | i = pci_vpd_find_tag(vpd_data, 0, vpd_size, PCI_VPD_LRDT_RO_DATA); | |
2573 | if (i < 0) { | |
2574 | netif_err(efx, drv, efx->net_dev, "VPD Read-only not found\n"); | |
2575 | return; | |
2576 | } | |
2577 | ||
2578 | j = pci_vpd_lrdt_size(&vpd_data[i]); | |
2579 | i += PCI_VPD_LRDT_TAG_SIZE; | |
2580 | if (i + j > vpd_size) | |
2581 | j = vpd_size - i; | |
2582 | ||
2583 | /* Get the Part number */ | |
2584 | i = pci_vpd_find_info_keyword(vpd_data, i, j, "PN"); | |
2585 | if (i < 0) { | |
2586 | netif_err(efx, drv, efx->net_dev, "Part number not found\n"); | |
2587 | return; | |
2588 | } | |
2589 | ||
2590 | j = pci_vpd_info_field_size(&vpd_data[i]); | |
2591 | i += PCI_VPD_INFO_FLD_HDR_SIZE; | |
2592 | if (i + j > vpd_size) { | |
2593 | netif_err(efx, drv, efx->net_dev, "Incomplete part number\n"); | |
2594 | return; | |
2595 | } | |
2596 | ||
2597 | netif_info(efx, drv, efx->net_dev, | |
2598 | "Part Number : %.*s\n", j, &vpd_data[i]); | |
2599 | } | |
2600 | ||
2601 | ||
8ceee660 BH |
2602 | /* Main body of NIC initialisation |
2603 | * This is called at module load (or hotplug insertion, theoretically). | |
2604 | */ | |
2605 | static int efx_pci_probe_main(struct efx_nic *efx) | |
2606 | { | |
2607 | int rc; | |
2608 | ||
2609 | /* Do start-of-day initialisation */ | |
2610 | rc = efx_probe_all(efx); | |
2611 | if (rc) | |
2612 | goto fail1; | |
2613 | ||
e8f14992 | 2614 | efx_init_napi(efx); |
8ceee660 | 2615 | |
ef2b90ee | 2616 | rc = efx->type->init(efx); |
8ceee660 | 2617 | if (rc) { |
62776d03 BH |
2618 | netif_err(efx, probe, efx->net_dev, |
2619 | "failed to initialise NIC\n"); | |
278c0621 | 2620 | goto fail3; |
8ceee660 BH |
2621 | } |
2622 | ||
2623 | rc = efx_init_port(efx); | |
2624 | if (rc) { | |
62776d03 BH |
2625 | netif_err(efx, probe, efx->net_dev, |
2626 | "failed to initialise port\n"); | |
278c0621 | 2627 | goto fail4; |
8ceee660 BH |
2628 | } |
2629 | ||
152b6a62 | 2630 | rc = efx_nic_init_interrupt(efx); |
8ceee660 | 2631 | if (rc) |
278c0621 | 2632 | goto fail5; |
7f967c01 | 2633 | efx_start_interrupts(efx, false); |
8ceee660 BH |
2634 | |
2635 | return 0; | |
2636 | ||
278c0621 | 2637 | fail5: |
8ceee660 | 2638 | efx_fini_port(efx); |
8ceee660 | 2639 | fail4: |
ef2b90ee | 2640 | efx->type->fini(efx); |
8ceee660 BH |
2641 | fail3: |
2642 | efx_fini_napi(efx); | |
8ceee660 BH |
2643 | efx_remove_all(efx); |
2644 | fail1: | |
2645 | return rc; | |
2646 | } | |
2647 | ||
2648 | /* NIC initialisation | |
2649 | * | |
2650 | * This is called at module load (or hotplug insertion, | |
73ba7b68 | 2651 | * theoretically). It sets up PCI mappings, resets the NIC, |
8ceee660 BH |
2652 | * sets up and registers the network devices with the kernel and hooks |
2653 | * the interrupt service routine. It does not prepare the device for | |
2654 | * transmission; this is left to the first time one of the network | |
2655 | * interfaces is brought up (i.e. efx_net_open). | |
2656 | */ | |
2657 | static int __devinit efx_pci_probe(struct pci_dev *pci_dev, | |
2658 | const struct pci_device_id *entry) | |
2659 | { | |
8ceee660 BH |
2660 | struct net_device *net_dev; |
2661 | struct efx_nic *efx; | |
fadac6aa | 2662 | int rc; |
8ceee660 BH |
2663 | |
2664 | /* Allocate and initialise a struct net_device and struct efx_nic */ | |
94b274bf BH |
2665 | net_dev = alloc_etherdev_mqs(sizeof(*efx), EFX_MAX_CORE_TX_QUEUES, |
2666 | EFX_MAX_RX_QUEUES); | |
8ceee660 BH |
2667 | if (!net_dev) |
2668 | return -ENOMEM; | |
adeb15aa BH |
2669 | efx = netdev_priv(net_dev); |
2670 | efx->type = (const struct efx_nic_type *) entry->driver_data; | |
2671 | net_dev->features |= (efx->type->offload_features | NETIF_F_SG | | |
97bc5415 | 2672 | NETIF_F_HIGHDMA | NETIF_F_TSO | |
abfe9039 | 2673 | NETIF_F_RXCSUM); |
adeb15aa | 2674 | if (efx->type->offload_features & NETIF_F_V6_CSUM) |
738a8f4b | 2675 | net_dev->features |= NETIF_F_TSO6; |
28506563 BH |
2676 | /* Mask for features that also apply to VLAN devices */ |
2677 | net_dev->vlan_features |= (NETIF_F_ALL_CSUM | NETIF_F_SG | | |
abfe9039 BH |
2678 | NETIF_F_HIGHDMA | NETIF_F_ALL_TSO | |
2679 | NETIF_F_RXCSUM); | |
2680 | /* All offloads can be toggled */ | |
2681 | net_dev->hw_features = net_dev->features & ~NETIF_F_HIGHDMA; | |
8ceee660 | 2682 | pci_set_drvdata(pci_dev, efx); |
62776d03 | 2683 | SET_NETDEV_DEV(net_dev, &pci_dev->dev); |
adeb15aa | 2684 | rc = efx_init_struct(efx, pci_dev, net_dev); |
8ceee660 BH |
2685 | if (rc) |
2686 | goto fail1; | |
2687 | ||
62776d03 | 2688 | netif_info(efx, probe, efx->net_dev, |
ff79c8ac | 2689 | "Solarflare NIC detected\n"); |
8ceee660 | 2690 | |
460eeaa0 BH |
2691 | efx_print_product_vpd(efx); |
2692 | ||
8ceee660 BH |
2693 | /* Set up basic I/O (BAR mappings etc) */ |
2694 | rc = efx_init_io(efx); | |
2695 | if (rc) | |
2696 | goto fail2; | |
2697 | ||
fadac6aa | 2698 | rc = efx_pci_probe_main(efx); |
fadac6aa BH |
2699 | if (rc) |
2700 | goto fail3; | |
8ceee660 | 2701 | |
8ceee660 BH |
2702 | rc = efx_register_netdev(efx); |
2703 | if (rc) | |
fadac6aa | 2704 | goto fail4; |
8ceee660 | 2705 | |
cd2d5b52 BH |
2706 | rc = efx_sriov_init(efx); |
2707 | if (rc) | |
2708 | netif_err(efx, probe, efx->net_dev, | |
2709 | "SR-IOV can't be enabled rc %d\n", rc); | |
2710 | ||
62776d03 | 2711 | netif_dbg(efx, probe, efx->net_dev, "initialisation successful\n"); |
a5211bb5 | 2712 | |
7c43161c | 2713 | /* Try to create MTDs, but allow this to fail */ |
a5211bb5 | 2714 | rtnl_lock(); |
7c43161c | 2715 | rc = efx_mtd_probe(efx); |
a5211bb5 | 2716 | rtnl_unlock(); |
7c43161c BH |
2717 | if (rc) |
2718 | netif_warn(efx, probe, efx->net_dev, | |
2719 | "failed to create MTDs (%d)\n", rc); | |
2720 | ||
8ceee660 BH |
2721 | return 0; |
2722 | ||
8ceee660 | 2723 | fail4: |
fadac6aa | 2724 | efx_pci_remove_main(efx); |
8ceee660 BH |
2725 | fail3: |
2726 | efx_fini_io(efx); | |
2727 | fail2: | |
2728 | efx_fini_struct(efx); | |
2729 | fail1: | |
3de4e301 | 2730 | pci_set_drvdata(pci_dev, NULL); |
5e2a911c | 2731 | WARN_ON(rc > 0); |
62776d03 | 2732 | netif_dbg(efx, drv, efx->net_dev, "initialisation failed. rc=%d\n", rc); |
8ceee660 BH |
2733 | free_netdev(net_dev); |
2734 | return rc; | |
2735 | } | |
2736 | ||
89c758fa BH |
2737 | static int efx_pm_freeze(struct device *dev) |
2738 | { | |
2739 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); | |
2740 | ||
61da026d BH |
2741 | rtnl_lock(); |
2742 | ||
6032fb56 BH |
2743 | if (efx->state != STATE_DISABLED) { |
2744 | efx->state = STATE_UNINIT; | |
89c758fa | 2745 | |
6032fb56 | 2746 | netif_device_detach(efx->net_dev); |
89c758fa | 2747 | |
6032fb56 BH |
2748 | efx_stop_all(efx); |
2749 | efx_stop_interrupts(efx, false); | |
2750 | } | |
89c758fa | 2751 | |
61da026d BH |
2752 | rtnl_unlock(); |
2753 | ||
89c758fa BH |
2754 | return 0; |
2755 | } | |
2756 | ||
2757 | static int efx_pm_thaw(struct device *dev) | |
2758 | { | |
2759 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); | |
2760 | ||
61da026d BH |
2761 | rtnl_lock(); |
2762 | ||
6032fb56 BH |
2763 | if (efx->state != STATE_DISABLED) { |
2764 | efx_start_interrupts(efx, false); | |
89c758fa | 2765 | |
6032fb56 BH |
2766 | mutex_lock(&efx->mac_lock); |
2767 | efx->phy_op->reconfigure(efx); | |
2768 | mutex_unlock(&efx->mac_lock); | |
89c758fa | 2769 | |
6032fb56 | 2770 | efx_start_all(efx); |
89c758fa | 2771 | |
6032fb56 | 2772 | netif_device_attach(efx->net_dev); |
89c758fa | 2773 | |
6032fb56 | 2774 | efx->state = STATE_READY; |
89c758fa | 2775 | |
6032fb56 BH |
2776 | efx->type->resume_wol(efx); |
2777 | } | |
89c758fa | 2778 | |
61da026d BH |
2779 | rtnl_unlock(); |
2780 | ||
319ba649 SH |
2781 | /* Reschedule any quenched resets scheduled during efx_pm_freeze() */ |
2782 | queue_work(reset_workqueue, &efx->reset_work); | |
2783 | ||
89c758fa BH |
2784 | return 0; |
2785 | } | |
2786 | ||
2787 | static int efx_pm_poweroff(struct device *dev) | |
2788 | { | |
2789 | struct pci_dev *pci_dev = to_pci_dev(dev); | |
2790 | struct efx_nic *efx = pci_get_drvdata(pci_dev); | |
2791 | ||
2792 | efx->type->fini(efx); | |
2793 | ||
a7d529ae | 2794 | efx->reset_pending = 0; |
89c758fa BH |
2795 | |
2796 | pci_save_state(pci_dev); | |
2797 | return pci_set_power_state(pci_dev, PCI_D3hot); | |
2798 | } | |
2799 | ||
2800 | /* Used for both resume and restore */ | |
2801 | static int efx_pm_resume(struct device *dev) | |
2802 | { | |
2803 | struct pci_dev *pci_dev = to_pci_dev(dev); | |
2804 | struct efx_nic *efx = pci_get_drvdata(pci_dev); | |
2805 | int rc; | |
2806 | ||
2807 | rc = pci_set_power_state(pci_dev, PCI_D0); | |
2808 | if (rc) | |
2809 | return rc; | |
2810 | pci_restore_state(pci_dev); | |
2811 | rc = pci_enable_device(pci_dev); | |
2812 | if (rc) | |
2813 | return rc; | |
2814 | pci_set_master(efx->pci_dev); | |
2815 | rc = efx->type->reset(efx, RESET_TYPE_ALL); | |
2816 | if (rc) | |
2817 | return rc; | |
2818 | rc = efx->type->init(efx); | |
2819 | if (rc) | |
2820 | return rc; | |
2821 | efx_pm_thaw(dev); | |
2822 | return 0; | |
2823 | } | |
2824 | ||
2825 | static int efx_pm_suspend(struct device *dev) | |
2826 | { | |
2827 | int rc; | |
2828 | ||
2829 | efx_pm_freeze(dev); | |
2830 | rc = efx_pm_poweroff(dev); | |
2831 | if (rc) | |
2832 | efx_pm_resume(dev); | |
2833 | return rc; | |
2834 | } | |
2835 | ||
18e83e4c | 2836 | static const struct dev_pm_ops efx_pm_ops = { |
89c758fa BH |
2837 | .suspend = efx_pm_suspend, |
2838 | .resume = efx_pm_resume, | |
2839 | .freeze = efx_pm_freeze, | |
2840 | .thaw = efx_pm_thaw, | |
2841 | .poweroff = efx_pm_poweroff, | |
2842 | .restore = efx_pm_resume, | |
2843 | }; | |
2844 | ||
8ceee660 | 2845 | static struct pci_driver efx_pci_driver = { |
c5d5f5fd | 2846 | .name = KBUILD_MODNAME, |
8ceee660 BH |
2847 | .id_table = efx_pci_table, |
2848 | .probe = efx_pci_probe, | |
2849 | .remove = efx_pci_remove, | |
89c758fa | 2850 | .driver.pm = &efx_pm_ops, |
8ceee660 BH |
2851 | }; |
2852 | ||
2853 | /************************************************************************** | |
2854 | * | |
2855 | * Kernel module interface | |
2856 | * | |
2857 | *************************************************************************/ | |
2858 | ||
2859 | module_param(interrupt_mode, uint, 0444); | |
2860 | MODULE_PARM_DESC(interrupt_mode, | |
2861 | "Interrupt mode (0=>MSIX 1=>MSI 2=>legacy)"); | |
2862 | ||
2863 | static int __init efx_init_module(void) | |
2864 | { | |
2865 | int rc; | |
2866 | ||
2867 | printk(KERN_INFO "Solarflare NET driver v" EFX_DRIVER_VERSION "\n"); | |
2868 | ||
2869 | rc = register_netdevice_notifier(&efx_netdev_notifier); | |
2870 | if (rc) | |
2871 | goto err_notifier; | |
2872 | ||
cd2d5b52 BH |
2873 | rc = efx_init_sriov(); |
2874 | if (rc) | |
2875 | goto err_sriov; | |
2876 | ||
1ab00629 SH |
2877 | reset_workqueue = create_singlethread_workqueue("sfc_reset"); |
2878 | if (!reset_workqueue) { | |
2879 | rc = -ENOMEM; | |
2880 | goto err_reset; | |
2881 | } | |
8ceee660 BH |
2882 | |
2883 | rc = pci_register_driver(&efx_pci_driver); | |
2884 | if (rc < 0) | |
2885 | goto err_pci; | |
2886 | ||
2887 | return 0; | |
2888 | ||
2889 | err_pci: | |
1ab00629 SH |
2890 | destroy_workqueue(reset_workqueue); |
2891 | err_reset: | |
cd2d5b52 BH |
2892 | efx_fini_sriov(); |
2893 | err_sriov: | |
8ceee660 BH |
2894 | unregister_netdevice_notifier(&efx_netdev_notifier); |
2895 | err_notifier: | |
2896 | return rc; | |
2897 | } | |
2898 | ||
2899 | static void __exit efx_exit_module(void) | |
2900 | { | |
2901 | printk(KERN_INFO "Solarflare NET driver unloading\n"); | |
2902 | ||
2903 | pci_unregister_driver(&efx_pci_driver); | |
1ab00629 | 2904 | destroy_workqueue(reset_workqueue); |
cd2d5b52 | 2905 | efx_fini_sriov(); |
8ceee660 BH |
2906 | unregister_netdevice_notifier(&efx_netdev_notifier); |
2907 | ||
2908 | } | |
2909 | ||
2910 | module_init(efx_init_module); | |
2911 | module_exit(efx_exit_module); | |
2912 | ||
906bb26c BH |
2913 | MODULE_AUTHOR("Solarflare Communications and " |
2914 | "Michael Brown <mbrown@fensystems.co.uk>"); | |
8ceee660 BH |
2915 | MODULE_DESCRIPTION("Solarflare Communications network driver"); |
2916 | MODULE_LICENSE("GPL"); | |
2917 | MODULE_DEVICE_TABLE(pci, efx_pci_table); |