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sfc: Remove efx_process_channel_now()
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / sfc / efx.c
CommitLineData
8ceee660
BH		 1/****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
0a6f40c6 4 * Copyright 2005-2011 Solarflare Communications Inc.
8ceee660
BH		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
10
11#include <linux/module.h>
12#include <linux/pci.h>
13#include <linux/netdevice.h>
14#include <linux/etherdevice.h>
15#include <linux/delay.h>
16#include <linux/notifier.h>
17#include <linux/ip.h>
18#include <linux/tcp.h>
19#include <linux/in.h>
20#include <linux/crc32.h>
21#include <linux/ethtool.h>
aa6ef27e 22#include <linux/topology.h>
5a0e3ad6 23#include <linux/gfp.h>
626950db 24#include <linux/aer.h>
b28405b0 25#include <linux/interrupt.h>
8ceee660 26#include "net_driver.h"
8ceee660 27#include "efx.h"
744093c9 28#include "nic.h"
dd40781e 29#include "selftest.h"
8ceee660 30
8880f4ec 31#include "mcdi.h"
fd371e32 32#include "workarounds.h"
8880f4ec 33
c459302d
BH		 34/**************************************************************************
35 *
36 * Type name strings
37 *
38 **************************************************************************
39 */
40
41/* Loopback mode names (see LOOPBACK_MODE()) */
42const unsigned int efx_loopback_mode_max = LOOPBACK_MAX;
18e83e4c 43const char *const efx_loopback_mode_names[] = {
c459302d 44 [LOOPBACK_NONE] = "NONE",
e58f69f4 45 [LOOPBACK_DATA] = "DATAPATH",
c459302d
BH		 46 [LOOPBACK_GMAC] = "GMAC",
47 [LOOPBACK_XGMII] = "XGMII",
48 [LOOPBACK_XGXS] = "XGXS",
9c636baf
BH		 49 [LOOPBACK_XAUI] = "XAUI",
50 [LOOPBACK_GMII] = "GMII",
51 [LOOPBACK_SGMII] = "SGMII",
e58f69f4
BH		 52 [LOOPBACK_XGBR] = "XGBR",
53 [LOOPBACK_XFI] = "XFI",
54 [LOOPBACK_XAUI_FAR] = "XAUI_FAR",
55 [LOOPBACK_GMII_FAR] = "GMII_FAR",
56 [LOOPBACK_SGMII_FAR] = "SGMII_FAR",
57 [LOOPBACK_XFI_FAR] = "XFI_FAR",
c459302d
BH		 58 [LOOPBACK_GPHY] = "GPHY",
59 [LOOPBACK_PHYXS] = "PHYXS",
9c636baf
BH		 60 [LOOPBACK_PCS] = "PCS",
61 [LOOPBACK_PMAPMD] = "PMA/PMD",
e58f69f4
BH		 62 [LOOPBACK_XPORT] = "XPORT",
63 [LOOPBACK_XGMII_WS] = "XGMII_WS",
9c636baf 64 [LOOPBACK_XAUI_WS] = "XAUI_WS",
e58f69f4
BH		 65 [LOOPBACK_XAUI_WS_FAR] = "XAUI_WS_FAR",
66 [LOOPBACK_XAUI_WS_NEAR] = "XAUI_WS_NEAR",
9c636baf 67 [LOOPBACK_GMII_WS] = "GMII_WS",
e58f69f4
BH		 68 [LOOPBACK_XFI_WS] = "XFI_WS",
69 [LOOPBACK_XFI_WS_FAR] = "XFI_WS_FAR",
9c636baf 70 [LOOPBACK_PHYXS_WS] = "PHYXS_WS",
c459302d
BH		 71};
72
c459302d 73const unsigned int efx_reset_type_max = RESET_TYPE_MAX;
18e83e4c 74const char *const efx_reset_type_names[] = {
626950db
AR		 75 [RESET_TYPE_INVISIBLE] = "INVISIBLE",
76 [RESET_TYPE_ALL] = "ALL",
77 [RESET_TYPE_RECOVER_OR_ALL] = "RECOVER_OR_ALL",
78 [RESET_TYPE_WORLD] = "WORLD",
79 [RESET_TYPE_RECOVER_OR_DISABLE] = "RECOVER_OR_DISABLE",
80 [RESET_TYPE_DISABLE] = "DISABLE",
81 [RESET_TYPE_TX_WATCHDOG] = "TX_WATCHDOG",
82 [RESET_TYPE_INT_ERROR] = "INT_ERROR",
83 [RESET_TYPE_RX_RECOVERY] = "RX_RECOVERY",
84 [RESET_TYPE_RX_DESC_FETCH] = "RX_DESC_FETCH",
85 [RESET_TYPE_TX_DESC_FETCH] = "TX_DESC_FETCH",
86 [RESET_TYPE_TX_SKIP] = "TX_SKIP",
87 [RESET_TYPE_MC_FAILURE] = "MC_FAILURE",
c459302d
BH		 88};
89
1ab00629
SH		 90/* Reset workqueue. If any NIC has a hardware failure then a reset will be
91 * queued onto this work queue. This is not a per-nic work queue, because
92 * efx_reset_work() acquires the rtnl lock, so resets are naturally serialised.
93 */
94static struct workqueue_struct *reset_workqueue;
95
8ceee660
BH		 96/**************************************************************************
97 *
98 * Configurable values
99 *
100 *************************************************************************/
101
8ceee660
BH		 102/*
103 * Use separate channels for TX and RX events
104 *
28b581ab
NT		 105 * Set this to 1 to use separate channels for TX and RX. It allows us
106 * to control interrupt affinity separately for TX and RX.
8ceee660 107 *
28b581ab 108 * This is only used in MSI-X interrupt mode
8ceee660 109 */
b9cc977d
BH		 110static bool separate_tx_channels;
111module_param(separate_tx_channels, bool, 0444);
28b581ab
NT		 112MODULE_PARM_DESC(separate_tx_channels,
113 "Use separate channels for TX and RX");
8ceee660
BH		 114
115/* This is the weight assigned to each of the (per-channel) virtual
116 * NAPI devices.
117 */
118static int napi_weight = 64;
119
120/* This is the time (in jiffies) between invocations of the hardware
626950db
AR		 121 * monitor.
122 * On Falcon-based NICs, this will:
e254c274
BH		 123 * - Check the on-board hardware monitor;
124 * - Poll the link state and reconfigure the hardware as necessary.
626950db
AR		 125 * On Siena-based NICs for power systems with EEH support, this will give EEH a
126 * chance to start.
8ceee660 127 */
d215697f 128static unsigned int efx_monitor_interval = 1 * HZ;
8ceee660 129
8ceee660
BH		 130/* Initial interrupt moderation settings. They can be modified after
131 * module load with ethtool.
132 *
133 * The default for RX should strike a balance between increasing the
134 * round-trip latency and reducing overhead.
135 */
136static unsigned int rx_irq_mod_usec = 60;
137
138/* Initial interrupt moderation settings. They can be modified after
139 * module load with ethtool.
140 *
141 * This default is chosen to ensure that a 10G link does not go idle
142 * while a TX queue is stopped after it has become full. A queue is
143 * restarted when it drops below half full. The time this takes (assuming
144 * worst case 3 descriptors per packet and 1024 descriptors) is
145 * 512 / 3 * 1.2 = 205 usec.
146 */
147static unsigned int tx_irq_mod_usec = 150;
148
149/* This is the first interrupt mode to try out of:
150 * 0 => MSI-X
151 * 1 => MSI
152 * 2 => legacy
153 */
154static unsigned int interrupt_mode;
155
156/* This is the requested number of CPUs to use for Receive-Side Scaling (RSS),
157 * i.e. the number of CPUs among which we may distribute simultaneous
158 * interrupt handling.
159 *
160 * Cards without MSI-X will only target one CPU via legacy or MSI interrupt.
cdb08f8f 161 * The default (0) means to assign an interrupt to each core.
8ceee660
BH		 162 */
163static unsigned int rss_cpus;
164module_param(rss_cpus, uint, 0444);
165MODULE_PARM_DESC(rss_cpus, "Number of CPUs to use for Receive-Side Scaling");
166
b9cc977d
BH		 167static bool phy_flash_cfg;
168module_param(phy_flash_cfg, bool, 0644);
84ae48fe
BH		 169MODULE_PARM_DESC(phy_flash_cfg, "Set PHYs into reflash mode initially");
170
e7bed9c8 171static unsigned irq_adapt_low_thresh = 8000;
6fb70fd1
BH		 172module_param(irq_adapt_low_thresh, uint, 0644);
173MODULE_PARM_DESC(irq_adapt_low_thresh,
174 "Threshold score for reducing IRQ moderation");
175
e7bed9c8 176static unsigned irq_adapt_high_thresh = 16000;
6fb70fd1
BH		 177module_param(irq_adapt_high_thresh, uint, 0644);
178MODULE_PARM_DESC(irq_adapt_high_thresh,
179 "Threshold score for increasing IRQ moderation");
180
62776d03
BH		 181static unsigned debug = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
182 NETIF_MSG_LINK | NETIF_MSG_IFDOWN |
183 NETIF_MSG_IFUP | NETIF_MSG_RX_ERR |
184 NETIF_MSG_TX_ERR | NETIF_MSG_HW);
185module_param(debug, uint, 0);
186MODULE_PARM_DESC(debug, "Bitmapped debugging message enable value");
187
8ceee660
BH		 188/**************************************************************************
189 *
190 * Utility functions and prototypes
191 *
192 *************************************************************************/
4642610c 193
7f967c01
BH		 194static void efx_start_interrupts(struct efx_nic *efx, bool may_keep_eventq);
195static void efx_stop_interrupts(struct efx_nic *efx, bool may_keep_eventq);
196static void efx_remove_channel(struct efx_channel *channel);
4642610c 197static void efx_remove_channels(struct efx_nic *efx);
7f967c01 198static const struct efx_channel_type efx_default_channel_type;
8ceee660 199static void efx_remove_port(struct efx_nic *efx);
7f967c01 200static void efx_init_napi_channel(struct efx_channel *channel);
8ceee660 201static void efx_fini_napi(struct efx_nic *efx);
e8f14992 202static void efx_fini_napi_channel(struct efx_channel *channel);
4642610c
BH		 203static void efx_fini_struct(struct efx_nic *efx);
204static void efx_start_all(struct efx_nic *efx);
205static void efx_stop_all(struct efx_nic *efx);
8ceee660
BH		 206
207#define EFX_ASSERT_RESET_SERIALISED(efx) \
208 do { \
f16aeea0 209 if ((efx->state == STATE_READY) || \
626950db 210 (efx->state == STATE_RECOVERY) || \
332c1ce9 211 (efx->state == STATE_DISABLED)) \
8ceee660
BH		 212 ASSERT_RTNL(); \
213 } while (0)
214
8b7325b4
BH		 215static int efx_check_disabled(struct efx_nic *efx)
216{
626950db 217 if (efx->state == STATE_DISABLED || efx->state == STATE_RECOVERY) {
8b7325b4
BH		 218 netif_err(efx, drv, efx->net_dev,
219 "device is disabled due to earlier errors\n");
220 return -EIO;
221 }
222 return 0;
223}
224
8ceee660
BH		 225/**************************************************************************
226 *
227 * Event queue processing
228 *
229 *************************************************************************/
230
231/* Process channel's event queue
232 *
233 * This function is responsible for processing the event queue of a
234 * single channel. The caller must guarantee that this function will
235 * never be concurrently called more than once on the same channel,
236 * though different channels may be being processed concurrently.
237 */
fa236e18 238static int efx_process_channel(struct efx_channel *channel, int budget)
8ceee660 239{
fa236e18 240 int spent;
8ceee660 241
9f2cb71c 242 if (unlikely(!channel->enabled))
42cbe2d7 243 return 0;
8ceee660 244
fa236e18 245 spent = efx_nic_process_eventq(channel, budget);
d9ab7007
BH		 246 if (spent && efx_channel_has_rx_queue(channel)) {
247 struct efx_rx_queue *rx_queue =
248 efx_channel_get_rx_queue(channel);
249
ff734ef4 250 efx_rx_flush_packet(channel);
97d48a10 251 if (rx_queue->enabled)
9f2cb71c 252 efx_fast_push_rx_descriptors(rx_queue);
8ceee660
BH		 253 }
254
fa236e18 255 return spent;
8ceee660
BH		 256}
257
8ceee660
BH		 258/* NAPI poll handler
259 *
260 * NAPI guarantees serialisation of polls of the same device, which
261 * provides the guarantee required by efx_process_channel().
262 */
263static int efx_poll(struct napi_struct *napi, int budget)
264{
265 struct efx_channel *channel =
266 container_of(napi, struct efx_channel, napi_str);
62776d03 267 struct efx_nic *efx = channel->efx;
fa236e18 268 int spent;
8ceee660 269
62776d03
BH		 270 netif_vdbg(efx, intr, efx->net_dev,
271 "channel %d NAPI poll executing on CPU %d\n",
272 channel->channel, raw_smp_processor_id());
8ceee660 273
fa236e18 274 spent = efx_process_channel(channel, budget);
8ceee660 275
fa236e18 276 if (spent < budget) {
9d9a6973 277 if (efx_channel_has_rx_queue(channel) &&
6fb70fd1
BH		 278 efx->irq_rx_adaptive &&
279 unlikely(++channel->irq_count == 1000)) {
6fb70fd1
BH		 280 if (unlikely(channel->irq_mod_score <
281 irq_adapt_low_thresh)) {
0d86ebd8
BH		 282 if (channel->irq_moderation > 1) {
283 channel->irq_moderation -= 1;
ef2b90ee 284 efx->type->push_irq_moderation(channel);
0d86ebd8 285 }
6fb70fd1
BH		 286 } else if (unlikely(channel->irq_mod_score >
287 irq_adapt_high_thresh)) {
0d86ebd8
BH		 288 if (channel->irq_moderation <
289 efx->irq_rx_moderation) {
290 channel->irq_moderation += 1;
ef2b90ee 291 efx->type->push_irq_moderation(channel);
0d86ebd8 292 }
6fb70fd1 293 }
6fb70fd1
BH		 294 channel->irq_count = 0;
295 channel->irq_mod_score = 0;
296 }
297
64d8ad6d
BH		 298 efx_filter_rfs_expire(channel);
299
8ceee660 300 /* There is no race here; although napi_disable() will
288379f0 301 * only wait for napi_complete(), this isn't a problem
514bedbc 302 * since efx_nic_eventq_read_ack() will have no effect if
8ceee660
BH		 303 * interrupts have already been disabled.
304 */
288379f0 305 napi_complete(napi);
514bedbc 306 efx_nic_eventq_read_ack(channel);
8ceee660
BH		 307 }
308
fa236e18 309 return spent;
8ceee660
BH		 310}
311
8ceee660
BH		 312/* Create event queue
313 * Event queue memory allocations are done only once. If the channel
314 * is reset, the memory buffer will be reused; this guards against
315 * errors during channel reset and also simplifies interrupt handling.
316 */
317static int efx_probe_eventq(struct efx_channel *channel)
318{
ecc910f5
SH		 319 struct efx_nic *efx = channel->efx;
320 unsigned long entries;
321
86ee5302 322 netif_dbg(efx, probe, efx->net_dev,
62776d03 323 "chan %d create event queue\n", channel->channel);
8ceee660 324
ecc910f5
SH		 325 /* Build an event queue with room for one event per tx and rx buffer,
326 * plus some extra for link state events and MCDI completions. */
327 entries = roundup_pow_of_two(efx->rxq_entries + efx->txq_entries + 128);
328 EFX_BUG_ON_PARANOID(entries > EFX_MAX_EVQ_SIZE);
329 channel->eventq_mask = max(entries, EFX_MIN_EVQ_SIZE) - 1;
330
152b6a62 331 return efx_nic_probe_eventq(channel);
8ceee660
BH		 332}
333
334/* Prepare channel's event queue */
bc3c90a2 335static void efx_init_eventq(struct efx_channel *channel)
8ceee660 336{
62776d03
BH		 337 netif_dbg(channel->efx, drv, channel->efx->net_dev,
338 "chan %d init event queue\n", channel->channel);
8ceee660
BH		 339
340 channel->eventq_read_ptr = 0;
341
152b6a62 342 efx_nic_init_eventq(channel);
8ceee660
BH		 343}
344
9f2cb71c
BH		 345/* Enable event queue processing and NAPI */
346static void efx_start_eventq(struct efx_channel *channel)
347{
348 netif_dbg(channel->efx, ifup, channel->efx->net_dev,
349 "chan %d start event queue\n", channel->channel);
350
514bedbc 351 /* Make sure the NAPI handler sees the enabled flag set */
9f2cb71c
BH		 352 channel->enabled = true;
353 smp_wmb();
354
355 napi_enable(&channel->napi_str);
356 efx_nic_eventq_read_ack(channel);
357}
358
359/* Disable event queue processing and NAPI */
360static void efx_stop_eventq(struct efx_channel *channel)
361{
362 if (!channel->enabled)
363 return;
364
365 napi_disable(&channel->napi_str);
366 channel->enabled = false;
367}
368
8ceee660
BH		 369static void efx_fini_eventq(struct efx_channel *channel)
370{
62776d03
BH		 371 netif_dbg(channel->efx, drv, channel->efx->net_dev,
372 "chan %d fini event queue\n", channel->channel);
8ceee660 373
152b6a62 374 efx_nic_fini_eventq(channel);
8ceee660
BH		 375}
376
377static void efx_remove_eventq(struct efx_channel *channel)
378{
62776d03
BH		 379 netif_dbg(channel->efx, drv, channel->efx->net_dev,
380 "chan %d remove event queue\n", channel->channel);
8ceee660 381
152b6a62 382 efx_nic_remove_eventq(channel);
8ceee660
BH		 383}
384
385/**************************************************************************
386 *
387 * Channel handling
388 *
389 *************************************************************************/
390
7f967c01 391/* Allocate and initialise a channel structure. */
4642610c
BH		 392static struct efx_channel *
393efx_alloc_channel(struct efx_nic *efx, int i, struct efx_channel *old_channel)
394{
395 struct efx_channel *channel;
396 struct efx_rx_queue *rx_queue;
397 struct efx_tx_queue *tx_queue;
398 int j;
399
7f967c01
BH		 400 channel = kzalloc(sizeof(*channel), GFP_KERNEL);
401 if (!channel)
402 return NULL;
4642610c 403
7f967c01
BH		 404 channel->efx = efx;
405 channel->channel = i;
406 channel->type = &efx_default_channel_type;
4642610c 407
7f967c01
BH		 408 for (j = 0; j < EFX_TXQ_TYPES; j++) {
409 tx_queue = &channel->tx_queue[j];
410 tx_queue->efx = efx;
411 tx_queue->queue = i * EFX_TXQ_TYPES + j;
412 tx_queue->channel = channel;
413 }
4642610c 414
7f967c01
BH		 415 rx_queue = &channel->rx_queue;
416 rx_queue->efx = efx;
417 setup_timer(&rx_queue->slow_fill, efx_rx_slow_fill,
418 (unsigned long)rx_queue);
4642610c 419
7f967c01
BH		 420 return channel;
421}
422
423/* Allocate and initialise a channel structure, copying parameters
424 * (but not resources) from an old channel structure.
425 */
426static struct efx_channel *
427efx_copy_channel(const struct efx_channel *old_channel)
428{
429 struct efx_channel *channel;
430 struct efx_rx_queue *rx_queue;
431 struct efx_tx_queue *tx_queue;
432 int j;
4642610c 433
7f967c01
BH		 434 channel = kmalloc(sizeof(*channel), GFP_KERNEL);
435 if (!channel)
436 return NULL;
437
438 *channel = *old_channel;
439
440 channel->napi_dev = NULL;
441 memset(&channel->eventq, 0, sizeof(channel->eventq));
4642610c 442
7f967c01
BH		 443 for (j = 0; j < EFX_TXQ_TYPES; j++) {
444 tx_queue = &channel->tx_queue[j];
445 if (tx_queue->channel)
4642610c 446 tx_queue->channel = channel;
7f967c01
BH		 447 tx_queue->buffer = NULL;
448 memset(&tx_queue->txd, 0, sizeof(tx_queue->txd));
4642610c
BH		 449 }
450
4642610c 451 rx_queue = &channel->rx_queue;
7f967c01
BH		 452 rx_queue->buffer = NULL;
453 memset(&rx_queue->rxd, 0, sizeof(rx_queue->rxd));
4642610c
BH		 454 setup_timer(&rx_queue->slow_fill, efx_rx_slow_fill,
455 (unsigned long)rx_queue);
456
457 return channel;
458}
459
8ceee660
BH		 460static int efx_probe_channel(struct efx_channel *channel)
461{
462 struct efx_tx_queue *tx_queue;
463 struct efx_rx_queue *rx_queue;
464 int rc;
465
62776d03
BH		 466 netif_dbg(channel->efx, probe, channel->efx->net_dev,
467 "creating channel %d\n", channel->channel);
8ceee660 468
7f967c01
BH		 469 rc = channel->type->pre_probe(channel);
470 if (rc)
471 goto fail;
472
8ceee660
BH		 473 rc = efx_probe_eventq(channel);
474 if (rc)
7f967c01 475 goto fail;
8ceee660
BH		 476
477 efx_for_each_channel_tx_queue(tx_queue, channel) {
478 rc = efx_probe_tx_queue(tx_queue);
479 if (rc)
7f967c01 480 goto fail;
8ceee660
BH		 481 }
482
483 efx_for_each_channel_rx_queue(rx_queue, channel) {
484 rc = efx_probe_rx_queue(rx_queue);
485 if (rc)
7f967c01 486 goto fail;
8ceee660
BH		 487 }
488
489 channel->n_rx_frm_trunc = 0;
490
491 return 0;
492
7f967c01
BH		 493fail:
494 efx_remove_channel(channel);
8ceee660
BH		 495 return rc;
496}
497
7f967c01
BH		 498static void
499efx_get_channel_name(struct efx_channel *channel, char *buf, size_t len)
500{
501 struct efx_nic *efx = channel->efx;
502 const char *type;
503 int number;
504
505 number = channel->channel;
506 if (efx->tx_channel_offset == 0) {
507 type = "";
508 } else if (channel->channel < efx->tx_channel_offset) {
509 type = "-rx";
510 } else {
511 type = "-tx";
512 number -= efx->tx_channel_offset;
513 }
514 snprintf(buf, len, "%s%s-%d", efx->name, type, number);
515}
8ceee660 516
56536e9c
BH		 517static void efx_set_channel_names(struct efx_nic *efx)
518{
519 struct efx_channel *channel;
56536e9c 520
7f967c01
BH		 521 efx_for_each_channel(channel, efx)
522 channel->type->get_name(channel,
523 efx->channel_name[channel->channel],
524 sizeof(efx->channel_name[0]));
56536e9c
BH		 525}
526
4642610c
BH		 527static int efx_probe_channels(struct efx_nic *efx)
528{
529 struct efx_channel *channel;
530 int rc;
531
532 /* Restart special buffer allocation */
533 efx->next_buffer_table = 0;
534
c92aaff1
BH		 535 /* Probe channels in reverse, so that any 'extra' channels
536 * use the start of the buffer table. This allows the traffic
537 * channels to be resized without moving them or wasting the
538 * entries before them.
539 */
540 efx_for_each_channel_rev(channel, efx) {
4642610c
BH		 541 rc = efx_probe_channel(channel);
542 if (rc) {
543 netif_err(efx, probe, efx->net_dev,
544 "failed to create channel %d\n",
545 channel->channel);
546 goto fail;
547 }
548 }
549 efx_set_channel_names(efx);
550
551 return 0;
552
553fail:
554 efx_remove_channels(efx);
555 return rc;
556}
557
8ceee660
BH		 558/* Channels are shutdown and reinitialised whilst the NIC is running
559 * to propagate configuration changes (mtu, checksum offload), or
560 * to clear hardware error conditions
561 */
9f2cb71c 562static void efx_start_datapath(struct efx_nic *efx)
8ceee660 563{
85740cdf 564 bool old_rx_scatter = efx->rx_scatter;
8ceee660
BH		 565 struct efx_tx_queue *tx_queue;
566 struct efx_rx_queue *rx_queue;
567 struct efx_channel *channel;
85740cdf 568 size_t rx_buf_len;
8ceee660 569
f7f13b0b
BH		 570 /* Calculate the rx buffer allocation parameters required to
571 * support the current MTU, including padding for header
572 * alignment and overruns.
573 */
272baeeb
BH		 574 efx->rx_dma_len = (efx->type->rx_buffer_hash_size +
575 EFX_MAX_FRAME_LEN(efx->net_dev->mtu) +
576 efx->type->rx_buffer_padding);
85740cdf 577 rx_buf_len = (sizeof(struct efx_rx_page_state) +
c14ff2ea 578 NET_IP_ALIGN + efx->rx_dma_len);
85740cdf
BH		 579 if (rx_buf_len <= PAGE_SIZE) {
580 efx->rx_scatter = false;
581 efx->rx_buffer_order = 0;
85740cdf 582 } else if (efx->type->can_rx_scatter) {
950c54df 583 BUILD_BUG_ON(EFX_RX_USR_BUF_SIZE % L1_CACHE_BYTES);
85740cdf 584 BUILD_BUG_ON(sizeof(struct efx_rx_page_state) +
950c54df
BH		 585 2 * ALIGN(NET_IP_ALIGN + EFX_RX_USR_BUF_SIZE,
586 EFX_RX_BUF_ALIGNMENT) >
587 PAGE_SIZE);
85740cdf
BH		 588 efx->rx_scatter = true;
589 efx->rx_dma_len = EFX_RX_USR_BUF_SIZE;
590 efx->rx_buffer_order = 0;
85740cdf
BH		 591 } else {
592 efx->rx_scatter = false;
593 efx->rx_buffer_order = get_order(rx_buf_len);
85740cdf
BH		 594 }
595
1648a23f
DP		 596 efx_rx_config_page_split(efx);
597 if (efx->rx_buffer_order)
598 netif_dbg(efx, drv, efx->net_dev,
599 "RX buf len=%u; page order=%u batch=%u\n",
600 efx->rx_dma_len, efx->rx_buffer_order,
601 efx->rx_pages_per_batch);
602 else
603 netif_dbg(efx, drv, efx->net_dev,
604 "RX buf len=%u step=%u bpp=%u; page batch=%u\n",
605 efx->rx_dma_len, efx->rx_page_buf_step,
606 efx->rx_bufs_per_page, efx->rx_pages_per_batch);
2768935a 607
85740cdf
BH		 608 /* RX filters also have scatter-enabled flags */
609 if (efx->rx_scatter != old_rx_scatter)
610 efx_filter_update_rx_scatter(efx);
8ceee660 611
14bf718f
BH		 612 /* We must keep at least one descriptor in a TX ring empty.
613 * We could avoid this when the queue size does not exactly
614 * match the hardware ring size, but it's not that important.
615 * Therefore we stop the queue when one more skb might fill
616 * the ring completely. We wake it when half way back to
617 * empty.
618 */
619 efx->txq_stop_thresh = efx->txq_entries - efx_tx_max_skb_descs(efx);
620 efx->txq_wake_thresh = efx->txq_stop_thresh / 2;
621
8ceee660
BH		 622 /* Initialise the channels */
623 efx_for_each_channel(channel, efx) {
bc3c90a2
BH		 624 efx_for_each_channel_tx_queue(tx_queue, channel)
625 efx_init_tx_queue(tx_queue);
8ceee660 626
9f2cb71c 627 efx_for_each_channel_rx_queue(rx_queue, channel) {
bc3c90a2 628 efx_init_rx_queue(rx_queue);
9f2cb71c
BH		 629 efx_nic_generate_fill_event(rx_queue);
630 }
8ceee660 631
85740cdf 632 WARN_ON(channel->rx_pkt_n_frags);
8ceee660 633 }
8ceee660 634
9f2cb71c
BH		 635 if (netif_device_present(efx->net_dev))
636 netif_tx_wake_all_queues(efx->net_dev);
8ceee660
BH		 637}
638
9f2cb71c 639static void efx_stop_datapath(struct efx_nic *efx)
8ceee660
BH		 640{
641 struct efx_channel *channel;
642 struct efx_tx_queue *tx_queue;
643 struct efx_rx_queue *rx_queue;
3dca9d2d 644 struct pci_dev *dev = efx->pci_dev;
6bc5d3a9 645 int rc;
8ceee660
BH		 646
647 EFX_ASSERT_RESET_SERIALISED(efx);
648 BUG_ON(efx->port_enabled);
649
3dca9d2d 650 /* Only perform flush if dma is enabled */
626950db 651 if (dev->is_busmaster && efx->state != STATE_RECOVERY) {
3dca9d2d
SH		 652 rc = efx_nic_flush_queues(efx);
653
654 if (rc && EFX_WORKAROUND_7803(efx)) {
655 /* Schedule a reset to recover from the flush failure. The
656 * descriptor caches reference memory we're about to free,
657 * but falcon_reconfigure_mac_wrapper() won't reconnect
658 * the MACs because of the pending reset. */
659 netif_err(efx, drv, efx->net_dev,
660 "Resetting to recover from flush failure\n");
661 efx_schedule_reset(efx, RESET_TYPE_ALL);
662 } else if (rc) {
663 netif_err(efx, drv, efx->net_dev, "failed to flush queues\n");
664 } else {
665 netif_dbg(efx, drv, efx->net_dev,
666 "successfully flushed all queues\n");
667 }
fd371e32 668 }
6bc5d3a9 669
8ceee660 670 efx_for_each_channel(channel, efx) {
9f2cb71c
BH		 671 /* RX packet processing is pipelined, so wait for the
672 * NAPI handler to complete. At least event queue 0
673 * might be kept active by non-data events, so don't
674 * use napi_synchronize() but actually disable NAPI
675 * temporarily.
676 */
677 if (efx_channel_has_rx_queue(channel)) {
678 efx_stop_eventq(channel);
679 efx_start_eventq(channel);
680 }
8ceee660
BH		 681
682 efx_for_each_channel_rx_queue(rx_queue, channel)
683 efx_fini_rx_queue(rx_queue);
94b274bf 684 efx_for_each_possible_channel_tx_queue(tx_queue, channel)
8ceee660 685 efx_fini_tx_queue(tx_queue);
8ceee660
BH		 686 }
687}
688
689static void efx_remove_channel(struct efx_channel *channel)
690{
691 struct efx_tx_queue *tx_queue;
692 struct efx_rx_queue *rx_queue;
693
62776d03
BH		 694 netif_dbg(channel->efx, drv, channel->efx->net_dev,
695 "destroy chan %d\n", channel->channel);
8ceee660
BH		 696
697 efx_for_each_channel_rx_queue(rx_queue, channel)
698 efx_remove_rx_queue(rx_queue);
94b274bf 699 efx_for_each_possible_channel_tx_queue(tx_queue, channel)
8ceee660
BH		 700 efx_remove_tx_queue(tx_queue);
701 efx_remove_eventq(channel);
c31e5f9f 702 channel->type->post_remove(channel);
8ceee660
BH		 703}
704
4642610c
BH		 705static void efx_remove_channels(struct efx_nic *efx)
706{
707 struct efx_channel *channel;
708
709 efx_for_each_channel(channel, efx)
710 efx_remove_channel(channel);
711}
712
713int
714efx_realloc_channels(struct efx_nic *efx, u32 rxq_entries, u32 txq_entries)
715{
716 struct efx_channel *other_channel[EFX_MAX_CHANNELS], *channel;
717 u32 old_rxq_entries, old_txq_entries;
7f967c01 718 unsigned i, next_buffer_table = 0;
8b7325b4
BH		 719 int rc;
720
721 rc = efx_check_disabled(efx);
722 if (rc)
723 return rc;
7f967c01
BH		 724
725 /* Not all channels should be reallocated. We must avoid
726 * reallocating their buffer table entries.
727 */
728 efx_for_each_channel(channel, efx) {
729 struct efx_rx_queue *rx_queue;
730 struct efx_tx_queue *tx_queue;
731
732 if (channel->type->copy)
733 continue;
734 next_buffer_table = max(next_buffer_table,
735 channel->eventq.index +
736 channel->eventq.entries);
737 efx_for_each_channel_rx_queue(rx_queue, channel)
738 next_buffer_table = max(next_buffer_table,
739 rx_queue->rxd.index +
740 rx_queue->rxd.entries);
741 efx_for_each_channel_tx_queue(tx_queue, channel)
742 next_buffer_table = max(next_buffer_table,
743 tx_queue->txd.index +
744 tx_queue->txd.entries);
745 }
4642610c 746
29c69a48 747 efx_device_detach_sync(efx);
4642610c 748 efx_stop_all(efx);
7f967c01 749 efx_stop_interrupts(efx, true);
4642610c 750
7f967c01 751 /* Clone channels (where possible) */
4642610c
BH		 752 memset(other_channel, 0, sizeof(other_channel));
753 for (i = 0; i < efx->n_channels; i++) {
7f967c01
BH		 754 channel = efx->channel[i];
755 if (channel->type->copy)
756 channel = channel->type->copy(channel);
4642610c
BH		 757 if (!channel) {
758 rc = -ENOMEM;
759 goto out;
760 }
761 other_channel[i] = channel;
762 }
763
764 /* Swap entry counts and channel pointers */
765 old_rxq_entries = efx->rxq_entries;
766 old_txq_entries = efx->txq_entries;
767 efx->rxq_entries = rxq_entries;
768 efx->txq_entries = txq_entries;
769 for (i = 0; i < efx->n_channels; i++) {
770 channel = efx->channel[i];
771 efx->channel[i] = other_channel[i];
772 other_channel[i] = channel;
773 }
774
7f967c01
BH		 775 /* Restart buffer table allocation */
776 efx->next_buffer_table = next_buffer_table;
e8f14992 777
e8f14992 778 for (i = 0; i < efx->n_channels; i++) {
7f967c01
BH		 779 channel = efx->channel[i];
780 if (!channel->type->copy)
781 continue;
782 rc = efx_probe_channel(channel);
783 if (rc)
784 goto rollback;
785 efx_init_napi_channel(efx->channel[i]);
e8f14992 786 }
7f967c01 787
4642610c 788out:
7f967c01
BH		 789 /* Destroy unused channel structures */
790 for (i = 0; i < efx->n_channels; i++) {
791 channel = other_channel[i];
792 if (channel && channel->type->copy) {
793 efx_fini_napi_channel(channel);
794 efx_remove_channel(channel);
795 kfree(channel);
796 }
797 }
4642610c 798
7f967c01 799 efx_start_interrupts(efx, true);
4642610c 800 efx_start_all(efx);
29c69a48 801 netif_device_attach(efx->net_dev);
4642610c
BH		 802 return rc;
803
804rollback:
805 /* Swap back */
806 efx->rxq_entries = old_rxq_entries;
807 efx->txq_entries = old_txq_entries;
808 for (i = 0; i < efx->n_channels; i++) {
809 channel = efx->channel[i];
810 efx->channel[i] = other_channel[i];
811 other_channel[i] = channel;
812 }
813 goto out;
814}
815
90d683af 816void efx_schedule_slow_fill(struct efx_rx_queue *rx_queue)
8ceee660 817{
90d683af 818 mod_timer(&rx_queue->slow_fill, jiffies + msecs_to_jiffies(100));
8ceee660
BH		 819}
820
7f967c01
BH		 821static const struct efx_channel_type efx_default_channel_type = {
822 .pre_probe = efx_channel_dummy_op_int,
c31e5f9f 823 .post_remove = efx_channel_dummy_op_void,
7f967c01
BH		 824 .get_name = efx_get_channel_name,
825 .copy = efx_copy_channel,
826 .keep_eventq = false,
827};
828
829int efx_channel_dummy_op_int(struct efx_channel *channel)
830{
831 return 0;
832}
833
c31e5f9f
SH		 834void efx_channel_dummy_op_void(struct efx_channel *channel)
835{
836}
837
8ceee660
BH		 838/**************************************************************************
839 *
840 * Port handling
841 *
842 **************************************************************************/
843
844/* This ensures that the kernel is kept informed (via
845 * netif_carrier_on/off) of the link status, and also maintains the
846 * link status's stop on the port's TX queue.
847 */
fdaa9aed 848void efx_link_status_changed(struct efx_nic *efx)
8ceee660 849{
eb50c0d6
BH		 850 struct efx_link_state *link_state = &efx->link_state;
851
8ceee660
BH		 852 /* SFC Bug 5356: A net_dev notifier is registered, so we must ensure
853 * that no events are triggered between unregister_netdev() and the
854 * driver unloading. A more general condition is that NETDEV_CHANGE
855 * can only be generated between NETDEV_UP and NETDEV_DOWN */
856 if (!netif_running(efx->net_dev))
857 return;
858
eb50c0d6 859 if (link_state->up != netif_carrier_ok(efx->net_dev)) {
8ceee660
BH		 860 efx->n_link_state_changes++;
861
eb50c0d6 862 if (link_state->up)
8ceee660
BH		 863 netif_carrier_on(efx->net_dev);
864 else
865 netif_carrier_off(efx->net_dev);
866 }
867
868 /* Status message for kernel log */
2aa9ef11 869 if (link_state->up)
62776d03
BH		 870 netif_info(efx, link, efx->net_dev,
871 "link up at %uMbps %s-duplex (MTU %d)%s\n",
872 link_state->speed, link_state->fd ? "full" : "half",
873 efx->net_dev->mtu,
874 (efx->promiscuous ? " [PROMISC]" : ""));
2aa9ef11 875 else
62776d03 876 netif_info(efx, link, efx->net_dev, "link down\n");
8ceee660
BH		 877}
878
d3245b28
BH		 879void efx_link_set_advertising(struct efx_nic *efx, u32 advertising)
880{
881 efx->link_advertising = advertising;
882 if (advertising) {
883 if (advertising & ADVERTISED_Pause)
884 efx->wanted_fc |= (EFX_FC_TX | EFX_FC_RX);
885 else
886 efx->wanted_fc &= ~(EFX_FC_TX | EFX_FC_RX);
887 if (advertising & ADVERTISED_Asym_Pause)
888 efx->wanted_fc ^= EFX_FC_TX;
889 }
890}
891
b5626946 892void efx_link_set_wanted_fc(struct efx_nic *efx, u8 wanted_fc)
d3245b28
BH		 893{
894 efx->wanted_fc = wanted_fc;
895 if (efx->link_advertising) {
896 if (wanted_fc & EFX_FC_RX)
897 efx->link_advertising |= (ADVERTISED_Pause |
898 ADVERTISED_Asym_Pause);
899 else
900 efx->link_advertising &= ~(ADVERTISED_Pause |
901 ADVERTISED_Asym_Pause);
902 if (wanted_fc & EFX_FC_TX)
903 efx->link_advertising ^= ADVERTISED_Asym_Pause;
904 }
905}
906
115122af
BH		 907static void efx_fini_port(struct efx_nic *efx);
908
d3245b28
BH		 909/* Push loopback/power/transmit disable settings to the PHY, and reconfigure
910 * the MAC appropriately. All other PHY configuration changes are pushed
911 * through phy_op->set_settings(), and pushed asynchronously to the MAC
912 * through efx_monitor().
913 *
914 * Callers must hold the mac_lock
915 */
916int __efx_reconfigure_port(struct efx_nic *efx)
8ceee660 917{
d3245b28
BH		 918 enum efx_phy_mode phy_mode;
919 int rc;
8ceee660 920
d3245b28 921 WARN_ON(!mutex_is_locked(&efx->mac_lock));
8ceee660 922
0fca8c97 923 /* Serialise the promiscuous flag with efx_set_rx_mode. */
73ba7b68
BH		 924 netif_addr_lock_bh(efx->net_dev);
925 netif_addr_unlock_bh(efx->net_dev);
a816f75a 926
d3245b28
BH		 927 /* Disable PHY transmit in mac level loopbacks */
928 phy_mode = efx->phy_mode;
177dfcd8
BH		 929 if (LOOPBACK_INTERNAL(efx))
930 efx->phy_mode |= PHY_MODE_TX_DISABLED;
931 else
932 efx->phy_mode &= ~PHY_MODE_TX_DISABLED;
177dfcd8 933
d3245b28 934 rc = efx->type->reconfigure_port(efx);
8ceee660 935
d3245b28
BH		 936 if (rc)
937 efx->phy_mode = phy_mode;
177dfcd8 938
d3245b28 939 return rc;
8ceee660
BH		 940}
941
942/* Reinitialise the MAC to pick up new PHY settings, even if the port is
943 * disabled. */
d3245b28 944int efx_reconfigure_port(struct efx_nic *efx)
8ceee660 945{
d3245b28
BH		 946 int rc;
947
8ceee660
BH		 948 EFX_ASSERT_RESET_SERIALISED(efx);
949
950 mutex_lock(&efx->mac_lock);
d3245b28 951 rc = __efx_reconfigure_port(efx);
8ceee660 952 mutex_unlock(&efx->mac_lock);
d3245b28
BH		 953
954 return rc;
8ceee660
BH		 955}
956
8be4f3e6
BH		 957/* Asynchronous work item for changing MAC promiscuity and multicast
958 * hash. Avoid a drain/rx_ingress enable by reconfiguring the current
959 * MAC directly. */
766ca0fa
BH		 960static void efx_mac_work(struct work_struct *data)
961{
962 struct efx_nic *efx = container_of(data, struct efx_nic, mac_work);
963
964 mutex_lock(&efx->mac_lock);
30b81cda 965 if (efx->port_enabled)
710b208d 966 efx->type->reconfigure_mac(efx);
766ca0fa
BH		 967 mutex_unlock(&efx->mac_lock);
968}
969
8ceee660
BH		 970static int efx_probe_port(struct efx_nic *efx)
971{
972 int rc;
973
62776d03 974 netif_dbg(efx, probe, efx->net_dev, "create port\n");
8ceee660 975
ff3b00a0
SH		 976 if (phy_flash_cfg)
977 efx->phy_mode = PHY_MODE_SPECIAL;
978
ef2b90ee
BH		 979 /* Connect up MAC/PHY operations table */
980 rc = efx->type->probe_port(efx);
8ceee660 981 if (rc)
e42de262 982 return rc;
8ceee660 983
e332bcb3
BH		 984 /* Initialise MAC address to permanent address */
985 memcpy(efx->net_dev->dev_addr, efx->net_dev->perm_addr, ETH_ALEN);
8ceee660
BH		 986
987 return 0;
8ceee660
BH		 988}
989
990static int efx_init_port(struct efx_nic *efx)
991{
992 int rc;
993
62776d03 994 netif_dbg(efx, drv, efx->net_dev, "init port\n");
8ceee660 995
1dfc5cea
BH		 996 mutex_lock(&efx->mac_lock);
997
177dfcd8 998 rc = efx->phy_op->init(efx);
8ceee660 999 if (rc)
1dfc5cea 1000 goto fail1;
8ceee660 1001
dc8cfa55 1002 efx->port_initialized = true;
1dfc5cea 1003
d3245b28
BH		 1004 /* Reconfigure the MAC before creating dma queues (required for
1005 * Falcon/A1 where RX_INGR_EN/TX_DRAIN_EN isn't supported) */
710b208d 1006 efx->type->reconfigure_mac(efx);
d3245b28
BH		 1007
1008 /* Ensure the PHY advertises the correct flow control settings */
1009 rc = efx->phy_op->reconfigure(efx);
1010 if (rc)
1011 goto fail2;
1012
1dfc5cea 1013 mutex_unlock(&efx->mac_lock);
8ceee660 1014 return 0;
177dfcd8 1015
1dfc5cea 1016fail2:
177dfcd8 1017 efx->phy_op->fini(efx);
1dfc5cea
BH		 1018fail1:
1019 mutex_unlock(&efx->mac_lock);
177dfcd8 1020 return rc;
8ceee660
BH		 1021}
1022
8ceee660
BH		 1023static void efx_start_port(struct efx_nic *efx)
1024{
62776d03 1025 netif_dbg(efx, ifup, efx->net_dev, "start port\n");
8ceee660
BH		 1026 BUG_ON(efx->port_enabled);
1027
1028 mutex_lock(&efx->mac_lock);
dc8cfa55 1029 efx->port_enabled = true;
8be4f3e6
BH		 1030
1031 /* efx_mac_work() might have been scheduled after efx_stop_port(),
1032 * and then cancelled by efx_flush_all() */
710b208d 1033 efx->type->reconfigure_mac(efx);
8be4f3e6 1034
8ceee660
BH		 1035 mutex_unlock(&efx->mac_lock);
1036}
1037
fdaa9aed 1038/* Prevent efx_mac_work() and efx_monitor() from working */
8ceee660
BH		 1039static void efx_stop_port(struct efx_nic *efx)
1040{
62776d03 1041 netif_dbg(efx, ifdown, efx->net_dev, "stop port\n");
8ceee660
BH		 1042
1043 mutex_lock(&efx->mac_lock);
dc8cfa55 1044 efx->port_enabled = false;
8ceee660
BH		 1045 mutex_unlock(&efx->mac_lock);
1046
1047 /* Serialise against efx_set_multicast_list() */
73ba7b68
BH		 1048 netif_addr_lock_bh(efx->net_dev);
1049 netif_addr_unlock_bh(efx->net_dev);
8ceee660
BH		 1050}
1051
1052static void efx_fini_port(struct efx_nic *efx)
1053{
62776d03 1054 netif_dbg(efx, drv, efx->net_dev, "shut down port\n");
8ceee660
BH		 1055
1056 if (!efx->port_initialized)
1057 return;
1058
177dfcd8 1059 efx->phy_op->fini(efx);
dc8cfa55 1060 efx->port_initialized = false;
8ceee660 1061
eb50c0d6 1062 efx->link_state.up = false;
8ceee660
BH		 1063 efx_link_status_changed(efx);
1064}
1065
1066static void efx_remove_port(struct efx_nic *efx)
1067{
62776d03 1068 netif_dbg(efx, drv, efx->net_dev, "destroying port\n");
8ceee660 1069
ef2b90ee 1070 efx->type->remove_port(efx);
8ceee660
BH		 1071}
1072
1073/**************************************************************************
1074 *
1075 * NIC handling
1076 *
1077 **************************************************************************/
1078
1079/* This configures the PCI device to enable I/O and DMA. */
1080static int efx_init_io(struct efx_nic *efx)
1081{
1082 struct pci_dev *pci_dev = efx->pci_dev;
1083 dma_addr_t dma_mask = efx->type->max_dma_mask;
1084 int rc;
1085
62776d03 1086 netif_dbg(efx, probe, efx->net_dev, "initialising I/O\n");
8ceee660
BH		 1087
1088 rc = pci_enable_device(pci_dev);
1089 if (rc) {
62776d03
BH		 1090 netif_err(efx, probe, efx->net_dev,
1091 "failed to enable PCI device\n");
8ceee660
BH		 1092 goto fail1;
1093 }
1094
1095 pci_set_master(pci_dev);
1096
1097 /* Set the PCI DMA mask. Try all possibilities from our
1098 * genuine mask down to 32 bits, because some architectures
1099 * (e.g. x86_64 with iommu_sac_force set) will allow 40 bit
1100 * masks event though they reject 46 bit masks.
1101 */
1102 while (dma_mask > 0x7fffffffUL) {
0e33d870
BH		 1103 if (dma_supported(&pci_dev->dev, dma_mask)) {
1104 rc = dma_set_mask(&pci_dev->dev, dma_mask);
e9e01846
BH		 1105 if (rc == 0)
1106 break;
1107 }
8ceee660
BH		 1108 dma_mask >>= 1;
1109 }
1110 if (rc) {
62776d03
BH		 1111 netif_err(efx, probe, efx->net_dev,
1112 "could not find a suitable DMA mask\n");
8ceee660
BH		 1113 goto fail2;
1114 }
62776d03
BH		 1115 netif_dbg(efx, probe, efx->net_dev,
1116 "using DMA mask %llx\n", (unsigned long long) dma_mask);
0e33d870 1117 rc = dma_set_coherent_mask(&pci_dev->dev, dma_mask);
8ceee660 1118 if (rc) {
0e33d870
BH		 1119 /* dma_set_coherent_mask() is not *allowed* to
1120 * fail with a mask that dma_set_mask() accepted,
8ceee660
BH		 1121 * but just in case...
1122 */
62776d03
BH		 1123 netif_err(efx, probe, efx->net_dev,
1124 "failed to set consistent DMA mask\n");
8ceee660
BH		 1125 goto fail2;
1126 }
1127
dc803df8
BH		 1128 efx->membase_phys = pci_resource_start(efx->pci_dev, EFX_MEM_BAR);
1129 rc = pci_request_region(pci_dev, EFX_MEM_BAR, "sfc");
8ceee660 1130 if (rc) {
62776d03
BH		 1131 netif_err(efx, probe, efx->net_dev,
1132 "request for memory BAR failed\n");
8ceee660
BH		 1133 rc = -EIO;
1134 goto fail3;
1135 }
86c432ca
BH		 1136 efx->membase = ioremap_nocache(efx->membase_phys,
1137 efx->type->mem_map_size);
8ceee660 1138 if (!efx->membase) {
62776d03
BH		 1139 netif_err(efx, probe, efx->net_dev,
1140 "could not map memory BAR at %llx+%x\n",
1141 (unsigned long long)efx->membase_phys,
1142 efx->type->mem_map_size);
8ceee660
BH		 1143 rc = -ENOMEM;
1144 goto fail4;
1145 }
62776d03
BH		 1146 netif_dbg(efx, probe, efx->net_dev,
1147 "memory BAR at %llx+%x (virtual %p)\n",
1148 (unsigned long long)efx->membase_phys,
1149 efx->type->mem_map_size, efx->membase);
8ceee660
BH		 1150
1151 return 0;
1152
1153 fail4:
dc803df8 1154 pci_release_region(efx->pci_dev, EFX_MEM_BAR);
8ceee660 1155 fail3:
2c118e0f 1156 efx->membase_phys = 0;
8ceee660
BH		 1157 fail2:
1158 pci_disable_device(efx->pci_dev);
1159 fail1:
1160 return rc;
1161}
1162
1163static void efx_fini_io(struct efx_nic *efx)
1164{
62776d03 1165 netif_dbg(efx, drv, efx->net_dev, "shutting down I/O\n");
8ceee660
BH		 1166
1167 if (efx->membase) {
1168 iounmap(efx->membase);
1169 efx->membase = NULL;
1170 }
1171
1172 if (efx->membase_phys) {
dc803df8 1173 pci_release_region(efx->pci_dev, EFX_MEM_BAR);
2c118e0f 1174 efx->membase_phys = 0;
8ceee660
BH		 1175 }
1176
1177 pci_disable_device(efx->pci_dev);
1178}
1179
a9a52506 1180static unsigned int efx_wanted_parallelism(struct efx_nic *efx)
46123d04 1181{
cdb08f8f 1182 cpumask_var_t thread_mask;
a16e5b24 1183 unsigned int count;
46123d04 1184 int cpu;
5b874e25 1185
cd2d5b52
BH		 1186 if (rss_cpus) {
1187 count = rss_cpus;
1188 } else {
1189 if (unlikely(!zalloc_cpumask_var(&thread_mask, GFP_KERNEL))) {
1190 netif_warn(efx, probe, efx->net_dev,
1191 "RSS disabled due to allocation failure\n");
1192 return 1;
1193 }
46123d04 1194
cd2d5b52
BH		 1195 count = 0;
1196 for_each_online_cpu(cpu) {
1197 if (!cpumask_test_cpu(cpu, thread_mask)) {
1198 ++count;
1199 cpumask_or(thread_mask, thread_mask,
1200 topology_thread_cpumask(cpu));
1201 }
1202 }
1203
1204 free_cpumask_var(thread_mask);
2f8975fb
RR		 1205 }
1206
cd2d5b52
BH		 1207 /* If RSS is requested for the PF *and* VFs then we can't write RSS
1208 * table entries that are inaccessible to VFs
1209 */
1210 if (efx_sriov_wanted(efx) && efx_vf_size(efx) > 1 &&
1211 count > efx_vf_size(efx)) {
1212 netif_warn(efx, probe, efx->net_dev,
1213 "Reducing number of RSS channels from %u to %u for "
1214 "VF support. Increase vf-msix-limit to use more "
1215 "channels on the PF.\n",
1216 count, efx_vf_size(efx));
1217 count = efx_vf_size(efx);
46123d04
BH		 1218 }
1219
1220 return count;
1221}
1222
1223/* Probe the number and type of interrupts we are able to obtain, and
1224 * the resulting numbers of channels and RX queues.
1225 */
64d8ad6d 1226static int efx_probe_interrupts(struct efx_nic *efx)
8ceee660 1227{
a16e5b24
BH		 1228 unsigned int max_channels =
1229 min(efx->type->phys_addr_channels, EFX_MAX_CHANNELS);
7f967c01
BH		 1230 unsigned int extra_channels = 0;
1231 unsigned int i, j;
a16e5b24 1232 int rc;
8ceee660 1233
7f967c01
BH		 1234 for (i = 0; i < EFX_MAX_EXTRA_CHANNELS; i++)
1235 if (efx->extra_channel_type[i])
1236 ++extra_channels;
1237
8ceee660 1238 if (efx->interrupt_mode == EFX_INT_MODE_MSIX) {
46123d04 1239 struct msix_entry xentries[EFX_MAX_CHANNELS];
a16e5b24 1240 unsigned int n_channels;
aa6ef27e 1241
a9a52506 1242 n_channels = efx_wanted_parallelism(efx);
a4900ac9
BH		 1243 if (separate_tx_channels)
1244 n_channels *= 2;
7f967c01 1245 n_channels += extra_channels;
a4900ac9 1246 n_channels = min(n_channels, max_channels);
8ceee660 1247
a4900ac9 1248 for (i = 0; i < n_channels; i++)
8ceee660 1249 xentries[i].entry = i;
a4900ac9 1250 rc = pci_enable_msix(efx->pci_dev, xentries, n_channels);
8ceee660 1251 if (rc > 0) {
62776d03
BH		 1252 netif_err(efx, drv, efx->net_dev,
1253 "WARNING: Insufficient MSI-X vectors"
a16e5b24 1254 " available (%d < %u).\n", rc, n_channels);
62776d03
BH		 1255 netif_err(efx, drv, efx->net_dev,
1256 "WARNING: Performance may be reduced.\n");
a4900ac9
BH		 1257 EFX_BUG_ON_PARANOID(rc >= n_channels);
1258 n_channels = rc;
8ceee660 1259 rc = pci_enable_msix(efx->pci_dev, xentries,
a4900ac9 1260 n_channels);
8ceee660
BH		 1261 }
1262
1263 if (rc == 0) {
a4900ac9 1264 efx->n_channels = n_channels;
7f967c01
BH		 1265 if (n_channels > extra_channels)
1266 n_channels -= extra_channels;
a4900ac9 1267 if (separate_tx_channels) {
7f967c01
BH		 1268 efx->n_tx_channels = max(n_channels / 2, 1U);
1269 efx->n_rx_channels = max(n_channels -
1270 efx->n_tx_channels,
1271 1U);
a4900ac9 1272 } else {
7f967c01
BH		 1273 efx->n_tx_channels = n_channels;
1274 efx->n_rx_channels = n_channels;
a4900ac9 1275 }
7f967c01 1276 for (i = 0; i < efx->n_channels; i++)
f7d12cdc
BH		 1277 efx_get_channel(efx, i)->irq =
1278 xentries[i].vector;
8ceee660
BH		 1279 } else {
1280 /* Fall back to single channel MSI */
1281 efx->interrupt_mode = EFX_INT_MODE_MSI;
62776d03
BH		 1282 netif_err(efx, drv, efx->net_dev,
1283 "could not enable MSI-X\n");
8ceee660
BH		 1284 }
1285 }
1286
1287 /* Try single interrupt MSI */
1288 if (efx->interrupt_mode == EFX_INT_MODE_MSI) {
28b581ab 1289 efx->n_channels = 1;
a4900ac9
BH		 1290 efx->n_rx_channels = 1;
1291 efx->n_tx_channels = 1;
8ceee660
BH		 1292 rc = pci_enable_msi(efx->pci_dev);
1293 if (rc == 0) {
f7d12cdc 1294 efx_get_channel(efx, 0)->irq = efx->pci_dev->irq;
8ceee660 1295 } else {
62776d03
BH		 1296 netif_err(efx, drv, efx->net_dev,
1297 "could not enable MSI\n");
8ceee660
BH		 1298 efx->interrupt_mode = EFX_INT_MODE_LEGACY;
1299 }
1300 }
1301
1302 /* Assume legacy interrupts */
1303 if (efx->interrupt_mode == EFX_INT_MODE_LEGACY) {
28b581ab 1304 efx->n_channels = 1 + (separate_tx_channels ? 1 : 0);
a4900ac9
BH		 1305 efx->n_rx_channels = 1;
1306 efx->n_tx_channels = 1;
8ceee660
BH		 1307 efx->legacy_irq = efx->pci_dev->irq;
1308 }
64d8ad6d 1309
7f967c01
BH		 1310 /* Assign extra channels if possible */
1311 j = efx->n_channels;
1312 for (i = 0; i < EFX_MAX_EXTRA_CHANNELS; i++) {
1313 if (!efx->extra_channel_type[i])
1314 continue;
1315 if (efx->interrupt_mode != EFX_INT_MODE_MSIX ||
1316 efx->n_channels <= extra_channels) {
1317 efx->extra_channel_type[i]->handle_no_channel(efx);
1318 } else {
1319 --j;
1320 efx_get_channel(efx, j)->type =
1321 efx->extra_channel_type[i];
1322 }
1323 }
1324
cd2d5b52 1325 /* RSS might be usable on VFs even if it is disabled on the PF */
3132d282 1326 efx->rss_spread = ((efx->n_rx_channels > 1 || !efx_sriov_wanted(efx)) ?
cd2d5b52
BH		 1327 efx->n_rx_channels : efx_vf_size(efx));
1328
64d8ad6d 1329 return 0;
8ceee660
BH		 1330}
1331
9f2cb71c 1332/* Enable interrupts, then probe and start the event queues */
7f967c01 1333static void efx_start_interrupts(struct efx_nic *efx, bool may_keep_eventq)
9f2cb71c
BH		 1334{
1335 struct efx_channel *channel;
1336
8b7325b4
BH		 1337 BUG_ON(efx->state == STATE_DISABLED);
1338
b28405b0
AR		 1339 if (efx->eeh_disabled_legacy_irq) {
1340 enable_irq(efx->legacy_irq);
1341 efx->eeh_disabled_legacy_irq = false;
1342 }
9f2cb71c
BH		 1343 if (efx->legacy_irq)
1344 efx->legacy_irq_enabled = true;
1345 efx_nic_enable_interrupts(efx);
1346
1347 efx_for_each_channel(channel, efx) {
7f967c01
BH		 1348 if (!channel->type->keep_eventq || !may_keep_eventq)
1349 efx_init_eventq(channel);
9f2cb71c
BH		 1350 efx_start_eventq(channel);
1351 }
1352
1353 efx_mcdi_mode_event(efx);
1354}
1355
7f967c01 1356static void efx_stop_interrupts(struct efx_nic *efx, bool may_keep_eventq)
9f2cb71c
BH		 1357{
1358 struct efx_channel *channel;
1359
8b7325b4
BH		 1360 if (efx->state == STATE_DISABLED)
1361 return;
1362
9f2cb71c
BH		 1363 efx_mcdi_mode_poll(efx);
1364
1365 efx_nic_disable_interrupts(efx);
1366 if (efx->legacy_irq) {
1367 synchronize_irq(efx->legacy_irq);
1368 efx->legacy_irq_enabled = false;
1369 }
1370
1371 efx_for_each_channel(channel, efx) {
1372 if (channel->irq)
1373 synchronize_irq(channel->irq);
1374
1375 efx_stop_eventq(channel);
7f967c01
BH		 1376 if (!channel->type->keep_eventq || !may_keep_eventq)
1377 efx_fini_eventq(channel);
9f2cb71c
BH		 1378 }
1379}
1380
8ceee660
BH		 1381static void efx_remove_interrupts(struct efx_nic *efx)
1382{
1383 struct efx_channel *channel;
1384
1385 /* Remove MSI/MSI-X interrupts */
64ee3120 1386 efx_for_each_channel(channel, efx)
8ceee660
BH		 1387 channel->irq = 0;
1388 pci_disable_msi(efx->pci_dev);
1389 pci_disable_msix(efx->pci_dev);
1390
1391 /* Remove legacy interrupt */
1392 efx->legacy_irq = 0;
1393}
1394
8831da7b 1395static void efx_set_channels(struct efx_nic *efx)
8ceee660 1396{
602a5322
BH		 1397 struct efx_channel *channel;
1398 struct efx_tx_queue *tx_queue;
1399
97653431 1400 efx->tx_channel_offset =
a4900ac9 1401 separate_tx_channels ? efx->n_channels - efx->n_tx_channels : 0;
602a5322 1402
79d68b37
SH		 1403 /* We need to mark which channels really have RX and TX
1404 * queues, and adjust the TX queue numbers if we have separate
602a5322
BH		 1405 * RX-only and TX-only channels.
1406 */
1407 efx_for_each_channel(channel, efx) {
79d68b37
SH		 1408 if (channel->channel < efx->n_rx_channels)
1409 channel->rx_queue.core_index = channel->channel;
1410 else
1411 channel->rx_queue.core_index = -1;
1412
602a5322
BH		 1413 efx_for_each_channel_tx_queue(tx_queue, channel)
1414 tx_queue->queue -= (efx->tx_channel_offset *
1415 EFX_TXQ_TYPES);
1416 }
8ceee660
BH		 1417}
1418
1419static int efx_probe_nic(struct efx_nic *efx)
1420{
765c9f46 1421 size_t i;
8ceee660
BH		 1422 int rc;
1423
62776d03 1424 netif_dbg(efx, probe, efx->net_dev, "creating NIC\n");
8ceee660
BH		 1425
1426 /* Carry out hardware-type specific initialisation */
ef2b90ee 1427 rc = efx->type->probe(efx);
8ceee660
BH		 1428 if (rc)
1429 return rc;
1430
a4900ac9 1431 /* Determine the number of channels and queues by trying to hook
8ceee660 1432 * in MSI-X interrupts. */
64d8ad6d
BH		 1433 rc = efx_probe_interrupts(efx);
1434 if (rc)
1435 goto fail;
8ceee660 1436
28e47c49
BH		 1437 efx->type->dimension_resources(efx);
1438
5d3a6fca
BH		 1439 if (efx->n_channels > 1)
1440 get_random_bytes(&efx->rx_hash_key, sizeof(efx->rx_hash_key));
765c9f46 1441 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); i++)
278bc429 1442 efx->rx_indir_table[i] =
cd2d5b52 1443 ethtool_rxfh_indir_default(i, efx->rss_spread);
5d3a6fca 1444
8831da7b 1445 efx_set_channels(efx);
c4f4adc7
BH		 1446 netif_set_real_num_tx_queues(efx->net_dev, efx->n_tx_channels);
1447 netif_set_real_num_rx_queues(efx->net_dev, efx->n_rx_channels);
8ceee660
BH		 1448
1449 /* Initialise the interrupt moderation settings */
9e393b30
BH		 1450 efx_init_irq_moderation(efx, tx_irq_mod_usec, rx_irq_mod_usec, true,
1451 true);
8ceee660
BH		 1452
1453 return 0;
64d8ad6d
BH		 1454
1455fail:
1456 efx->type->remove(efx);
1457 return rc;
8ceee660
BH		 1458}
1459
1460static void efx_remove_nic(struct efx_nic *efx)
1461{
62776d03 1462 netif_dbg(efx, drv, efx->net_dev, "destroying NIC\n");
8ceee660
BH		 1463
1464 efx_remove_interrupts(efx);
ef2b90ee 1465 efx->type->remove(efx);
8ceee660
BH		 1466}
1467
1468/**************************************************************************
1469 *
1470 * NIC startup/shutdown
1471 *
1472 *************************************************************************/
1473
1474static int efx_probe_all(struct efx_nic *efx)
1475{
8ceee660
BH		 1476 int rc;
1477
8ceee660
BH		 1478 rc = efx_probe_nic(efx);
1479 if (rc) {
62776d03 1480 netif_err(efx, probe, efx->net_dev, "failed to create NIC\n");
8ceee660
BH		 1481 goto fail1;
1482 }
1483
8ceee660
BH		 1484 rc = efx_probe_port(efx);
1485 if (rc) {
62776d03 1486 netif_err(efx, probe, efx->net_dev, "failed to create port\n");
8ceee660
BH		 1487 goto fail2;
1488 }
1489
7e6d06f0
BH		 1490 BUILD_BUG_ON(EFX_DEFAULT_DMAQ_SIZE < EFX_RXQ_MIN_ENT);
1491 if (WARN_ON(EFX_DEFAULT_DMAQ_SIZE < EFX_TXQ_MIN_ENT(efx))) {
1492 rc = -EINVAL;
1493 goto fail3;
1494 }
ecc910f5 1495 efx->rxq_entries = efx->txq_entries = EFX_DEFAULT_DMAQ_SIZE;
8ceee660 1496
64eebcfd
BH		 1497 rc = efx_probe_filters(efx);
1498 if (rc) {
1499 netif_err(efx, probe, efx->net_dev,
1500 "failed to create filter tables\n");
7f967c01 1501 goto fail3;
64eebcfd
BH		 1502 }
1503
7f967c01
BH		 1504 rc = efx_probe_channels(efx);
1505 if (rc)
1506 goto fail4;
1507
8ceee660
BH		 1508 return 0;
1509
64eebcfd 1510 fail4:
7f967c01 1511 efx_remove_filters(efx);
8ceee660 1512 fail3:
8ceee660
BH		 1513 efx_remove_port(efx);
1514 fail2:
1515 efx_remove_nic(efx);
1516 fail1:
1517 return rc;
1518}
1519
8b7325b4
BH		 1520/* If the interface is supposed to be running but is not, start
1521 * the hardware and software data path, regular activity for the port
1522 * (MAC statistics, link polling, etc.) and schedule the port to be
1523 * reconfigured. Interrupts must already be enabled. This function
1524 * is safe to call multiple times, so long as the NIC is not disabled.
1525 * Requires the RTNL lock.
9f2cb71c 1526 */
8ceee660
BH		 1527static void efx_start_all(struct efx_nic *efx)
1528{
8ceee660 1529 EFX_ASSERT_RESET_SERIALISED(efx);
8b7325b4 1530 BUG_ON(efx->state == STATE_DISABLED);
8ceee660
BH		 1531
1532 /* Check that it is appropriate to restart the interface. All
1533 * of these flags are safe to read under just the rtnl lock */
8b7325b4 1534 if (efx->port_enabled || !netif_running(efx->net_dev))
8ceee660
BH		 1535 return;
1536
8ceee660 1537 efx_start_port(efx);
9f2cb71c 1538 efx_start_datapath(efx);
8880f4ec 1539
626950db
AR		 1540 /* Start the hardware monitor if there is one */
1541 if (efx->type->monitor != NULL)
8ceee660
BH		 1542 queue_delayed_work(efx->workqueue, &efx->monitor_work,
1543 efx_monitor_interval);
626950db
AR		 1544
1545 /* If link state detection is normally event-driven, we have
1546 * to poll now because we could have missed a change
1547 */
1548 if (efx_nic_rev(efx) >= EFX_REV_SIENA_A0) {
78c1f0a0
SH		 1549 mutex_lock(&efx->mac_lock);
1550 if (efx->phy_op->poll(efx))
1551 efx_link_status_changed(efx);
1552 mutex_unlock(&efx->mac_lock);
1553 }
55edc6e6 1554
ef2b90ee 1555 efx->type->start_stats(efx);
8ceee660
BH		 1556}
1557
1558/* Flush all delayed work. Should only be called when no more delayed work
1559 * will be scheduled. This doesn't flush pending online resets (efx_reset),
1560 * since we're holding the rtnl_lock at this point. */
1561static void efx_flush_all(struct efx_nic *efx)
1562{
dd40781e 1563 /* Make sure the hardware monitor and event self-test are stopped */
8ceee660 1564 cancel_delayed_work_sync(&efx->monitor_work);
dd40781e 1565 efx_selftest_async_cancel(efx);
8ceee660 1566 /* Stop scheduled port reconfigurations */
766ca0fa 1567 cancel_work_sync(&efx->mac_work);
8ceee660
BH		 1568}
1569
8b7325b4
BH		 1570/* Quiesce the hardware and software data path, and regular activity
1571 * for the port without bringing the link down. Safe to call multiple
1572 * times with the NIC in almost any state, but interrupts should be
1573 * enabled. Requires the RTNL lock.
1574 */
8ceee660
BH		 1575static void efx_stop_all(struct efx_nic *efx)
1576{
8ceee660
BH		 1577 EFX_ASSERT_RESET_SERIALISED(efx);
1578
1579 /* port_enabled can be read safely under the rtnl lock */
1580 if (!efx->port_enabled)
1581 return;
1582
ef2b90ee 1583 efx->type->stop_stats(efx);
8ceee660
BH		 1584 efx_stop_port(efx);
1585
fdaa9aed 1586 /* Flush efx_mac_work(), refill_workqueue, monitor_work */
8ceee660
BH		 1587 efx_flush_all(efx);
1588
29c69a48
BH		 1589 /* Stop the kernel transmit interface. This is only valid if
1590 * the device is stopped or detached; otherwise the watchdog
1591 * may fire immediately.
1592 */
1593 WARN_ON(netif_running(efx->net_dev) &&
1594 netif_device_present(efx->net_dev));
9f2cb71c
BH		 1595 netif_tx_disable(efx->net_dev);
1596
1597 efx_stop_datapath(efx);
8ceee660
BH		 1598}
1599
1600static void efx_remove_all(struct efx_nic *efx)
1601{
4642610c 1602 efx_remove_channels(efx);
7f967c01 1603 efx_remove_filters(efx);
8ceee660
BH		 1604 efx_remove_port(efx);
1605 efx_remove_nic(efx);
1606}
1607
8ceee660
BH		 1608/**************************************************************************
1609 *
1610 * Interrupt moderation
1611 *
1612 **************************************************************************/
1613
cc180b69 1614static unsigned int irq_mod_ticks(unsigned int usecs, unsigned int quantum_ns)
0d86ebd8 1615{
b548f976
BH		 1616 if (usecs == 0)
1617 return 0;
cc180b69 1618 if (usecs * 1000 < quantum_ns)
0d86ebd8 1619 return 1; /* never round down to 0 */
cc180b69 1620 return usecs * 1000 / quantum_ns;
0d86ebd8
BH		 1621}
1622
8ceee660 1623/* Set interrupt moderation parameters */
9e393b30
BH		 1624int efx_init_irq_moderation(struct efx_nic *efx, unsigned int tx_usecs,
1625 unsigned int rx_usecs, bool rx_adaptive,
1626 bool rx_may_override_tx)
8ceee660 1627{
f7d12cdc 1628 struct efx_channel *channel;
cc180b69
BH		 1629 unsigned int irq_mod_max = DIV_ROUND_UP(efx->type->timer_period_max *
1630 efx->timer_quantum_ns,
1631 1000);
1632 unsigned int tx_ticks;
1633 unsigned int rx_ticks;
8ceee660
BH		 1634
1635 EFX_ASSERT_RESET_SERIALISED(efx);
1636
cc180b69 1637 if (tx_usecs > irq_mod_max || rx_usecs > irq_mod_max)
9e393b30
BH		 1638 return -EINVAL;
1639
cc180b69
BH		 1640 tx_ticks = irq_mod_ticks(tx_usecs, efx->timer_quantum_ns);
1641 rx_ticks = irq_mod_ticks(rx_usecs, efx->timer_quantum_ns);
1642
9e393b30
BH		 1643 if (tx_ticks != rx_ticks && efx->tx_channel_offset == 0 &&
1644 !rx_may_override_tx) {
1645 netif_err(efx, drv, efx->net_dev, "Channels are shared. "
1646 "RX and TX IRQ moderation must be equal\n");
1647 return -EINVAL;
1648 }
1649
6fb70fd1 1650 efx->irq_rx_adaptive = rx_adaptive;
0d86ebd8 1651 efx->irq_rx_moderation = rx_ticks;
f7d12cdc 1652 efx_for_each_channel(channel, efx) {
525da907 1653 if (efx_channel_has_rx_queue(channel))
f7d12cdc 1654 channel->irq_moderation = rx_ticks;
525da907 1655 else if (efx_channel_has_tx_queues(channel))
f7d12cdc
BH		 1656 channel->irq_moderation = tx_ticks;
1657 }
9e393b30
BH		 1658
1659 return 0;
8ceee660
BH		 1660}
1661
a0c4faf5
BH		 1662void efx_get_irq_moderation(struct efx_nic *efx, unsigned int *tx_usecs,
1663 unsigned int *rx_usecs, bool *rx_adaptive)
1664{
cc180b69
BH		 1665 /* We must round up when converting ticks to microseconds
1666 * because we round down when converting the other way.
1667 */
1668
a0c4faf5 1669 *rx_adaptive = efx->irq_rx_adaptive;
cc180b69
BH		 1670 *rx_usecs = DIV_ROUND_UP(efx->irq_rx_moderation *
1671 efx->timer_quantum_ns,
1672 1000);
a0c4faf5
BH		 1673
1674 /* If channels are shared between RX and TX, so is IRQ
1675 * moderation. Otherwise, IRQ moderation is the same for all
1676 * TX channels and is not adaptive.
1677 */
1678 if (efx->tx_channel_offset == 0)
1679 *tx_usecs = *rx_usecs;
1680 else
cc180b69 1681 *tx_usecs = DIV_ROUND_UP(
a0c4faf5 1682 efx->channel[efx->tx_channel_offset]->irq_moderation *
cc180b69
BH		 1683 efx->timer_quantum_ns,
1684 1000);
a0c4faf5
BH		 1685}
1686
8ceee660
BH		 1687/**************************************************************************
1688 *
1689 * Hardware monitor
1690 *
1691 **************************************************************************/
1692
e254c274 1693/* Run periodically off the general workqueue */
8ceee660
BH		 1694static void efx_monitor(struct work_struct *data)
1695{
1696 struct efx_nic *efx = container_of(data, struct efx_nic,
1697 monitor_work.work);
8ceee660 1698
62776d03
BH		 1699 netif_vdbg(efx, timer, efx->net_dev,
1700 "hardware monitor executing on CPU %d\n",
1701 raw_smp_processor_id());
ef2b90ee 1702 BUG_ON(efx->type->monitor == NULL);
8ceee660 1703
8ceee660
BH		 1704 /* If the mac_lock is already held then it is likely a port
1705 * reconfiguration is already in place, which will likely do
e254c274
BH		 1706 * most of the work of monitor() anyway. */
1707 if (mutex_trylock(&efx->mac_lock)) {
1708 if (efx->port_enabled)
1709 efx->type->monitor(efx);
1710 mutex_unlock(&efx->mac_lock);
1711 }
8ceee660 1712
8ceee660
BH		 1713 queue_delayed_work(efx->workqueue, &efx->monitor_work,
1714 efx_monitor_interval);
1715}
1716
1717/**************************************************************************
1718 *
1719 * ioctls
1720 *
1721 *************************************************************************/
1722
1723/* Net device ioctl
1724 * Context: process, rtnl_lock() held.
1725 */
1726static int efx_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd)
1727{
767e468c 1728 struct efx_nic *efx = netdev_priv(net_dev);
68e7f45e 1729 struct mii_ioctl_data *data = if_mii(ifr);
8ceee660 1730
7c236c43
SH		 1731 if (cmd == SIOCSHWTSTAMP)
1732 return efx_ptp_ioctl(efx, ifr, cmd);
1733
68e7f45e
BH		 1734 /* Convert phy_id from older PRTAD/DEVAD format */
1735 if ((cmd == SIOCGMIIREG || cmd == SIOCSMIIREG) &&
1736 (data->phy_id & 0xfc00) == 0x0400)
1737 data->phy_id ^= MDIO_PHY_ID_C45 | 0x0400;
1738
1739 return mdio_mii_ioctl(&efx->mdio, data, cmd);
8ceee660
BH		 1740}
1741
1742/**************************************************************************
1743 *
1744 * NAPI interface
1745 *
1746 **************************************************************************/
1747
7f967c01
BH		 1748static void efx_init_napi_channel(struct efx_channel *channel)
1749{
1750 struct efx_nic *efx = channel->efx;
1751
1752 channel->napi_dev = efx->net_dev;
1753 netif_napi_add(channel->napi_dev, &channel->napi_str,
1754 efx_poll, napi_weight);
1755}
1756
e8f14992 1757static void efx_init_napi(struct efx_nic *efx)
8ceee660
BH		 1758{
1759 struct efx_channel *channel;
8ceee660 1760
7f967c01
BH		 1761 efx_for_each_channel(channel, efx)
1762 efx_init_napi_channel(channel);
e8f14992
BH		 1763}
1764
1765static void efx_fini_napi_channel(struct efx_channel *channel)
1766{
1767 if (channel->napi_dev)
1768 netif_napi_del(&channel->napi_str);
1769 channel->napi_dev = NULL;
8ceee660
BH		 1770}
1771
1772static void efx_fini_napi(struct efx_nic *efx)
1773{
1774 struct efx_channel *channel;
1775
e8f14992
BH		 1776 efx_for_each_channel(channel, efx)
1777 efx_fini_napi_channel(channel);
8ceee660
BH		 1778}
1779
1780/**************************************************************************
1781 *
1782 * Kernel netpoll interface
1783 *
1784 *************************************************************************/
1785
1786#ifdef CONFIG_NET_POLL_CONTROLLER
1787
1788/* Although in the common case interrupts will be disabled, this is not
1789 * guaranteed. However, all our work happens inside the NAPI callback,
1790 * so no locking is required.
1791 */
1792static void efx_netpoll(struct net_device *net_dev)
1793{
767e468c 1794 struct efx_nic *efx = netdev_priv(net_dev);
8ceee660
BH		 1795 struct efx_channel *channel;
1796
64ee3120 1797 efx_for_each_channel(channel, efx)
8ceee660
BH		 1798 efx_schedule_channel(channel);
1799}
1800
1801#endif
1802
1803/**************************************************************************
1804 *
1805 * Kernel net device interface
1806 *
1807 *************************************************************************/
1808
1809/* Context: process, rtnl_lock() held. */
1810static int efx_net_open(struct net_device *net_dev)
1811{
767e468c 1812 struct efx_nic *efx = netdev_priv(net_dev);
8b7325b4
BH		 1813 int rc;
1814
62776d03
BH		 1815 netif_dbg(efx, ifup, efx->net_dev, "opening device on CPU %d\n",
1816 raw_smp_processor_id());
8ceee660 1817
8b7325b4
BH		 1818 rc = efx_check_disabled(efx);
1819 if (rc)
1820 return rc;
f8b87c17
BH		 1821 if (efx->phy_mode & PHY_MODE_SPECIAL)
1822 return -EBUSY;
8880f4ec
BH		 1823 if (efx_mcdi_poll_reboot(efx) && efx_reset(efx, RESET_TYPE_ALL))
1824 return -EIO;
f8b87c17 1825
78c1f0a0
SH		 1826 /* Notify the kernel of the link state polled during driver load,
1827 * before the monitor starts running */
1828 efx_link_status_changed(efx);
1829
8ceee660 1830 efx_start_all(efx);
dd40781e 1831 efx_selftest_async_start(efx);
8ceee660
BH		 1832 return 0;
1833}
1834
1835/* Context: process, rtnl_lock() held.
1836 * Note that the kernel will ignore our return code; this method
1837 * should really be a void.
1838 */
1839static int efx_net_stop(struct net_device *net_dev)
1840{
767e468c 1841 struct efx_nic *efx = netdev_priv(net_dev);
8ceee660 1842
62776d03
BH		 1843 netif_dbg(efx, ifdown, efx->net_dev, "closing on CPU %d\n",
1844 raw_smp_processor_id());
8ceee660 1845
8b7325b4
BH		 1846 /* Stop the device and flush all the channels */
1847 efx_stop_all(efx);
8ceee660
BH		 1848
1849 return 0;
1850}
1851
5b9e207c 1852/* Context: process, dev_base_lock or RTNL held, non-blocking. */
2aa9ef11
BH		 1853static struct rtnl_link_stats64 *efx_net_stats(struct net_device *net_dev,
1854 struct rtnl_link_stats64 *stats)
8ceee660 1855{
767e468c 1856 struct efx_nic *efx = netdev_priv(net_dev);
8ceee660 1857 struct efx_mac_stats *mac_stats = &efx->mac_stats;
8ceee660 1858
55edc6e6 1859 spin_lock_bh(&efx->stats_lock);
1cb34522 1860
ef2b90ee 1861 efx->type->update_stats(efx);
8ceee660
BH		 1862
1863 stats->rx_packets = mac_stats->rx_packets;
1864 stats->tx_packets = mac_stats->tx_packets;
1865 stats->rx_bytes = mac_stats->rx_bytes;
1866 stats->tx_bytes = mac_stats->tx_bytes;
80485d34 1867 stats->rx_dropped = efx->n_rx_nodesc_drop_cnt;
8ceee660
BH		 1868 stats->multicast = mac_stats->rx_multicast;
1869 stats->collisions = mac_stats->tx_collision;
1870 stats->rx_length_errors = (mac_stats->rx_gtjumbo +
1871 mac_stats->rx_length_error);
8ceee660
BH		 1872 stats->rx_crc_errors = mac_stats->rx_bad;
1873 stats->rx_frame_errors = mac_stats->rx_align_error;
1874 stats->rx_fifo_errors = mac_stats->rx_overflow;
1875 stats->rx_missed_errors = mac_stats->rx_missed;
1876 stats->tx_window_errors = mac_stats->tx_late_collision;
1877
1878 stats->rx_errors = (stats->rx_length_errors +
8ceee660
BH		 1879 stats->rx_crc_errors +
1880 stats->rx_frame_errors +
8ceee660
BH		 1881 mac_stats->rx_symbol_error);
1882 stats->tx_errors = (stats->tx_window_errors +
1883 mac_stats->tx_bad);
1884
1cb34522
BH		 1885 spin_unlock_bh(&efx->stats_lock);
1886
8ceee660
BH		 1887 return stats;
1888}
1889
1890/* Context: netif_tx_lock held, BHs disabled. */
1891static void efx_watchdog(struct net_device *net_dev)
1892{
767e468c 1893 struct efx_nic *efx = netdev_priv(net_dev);
8ceee660 1894
62776d03
BH		 1895 netif_err(efx, tx_err, efx->net_dev,
1896 "TX stuck with port_enabled=%d: resetting channels\n",
1897 efx->port_enabled);
8ceee660 1898
739bb23d 1899 efx_schedule_reset(efx, RESET_TYPE_TX_WATCHDOG);
8ceee660
BH		 1900}
1901
1902
1903/* Context: process, rtnl_lock() held. */
1904static int efx_change_mtu(struct net_device *net_dev, int new_mtu)
1905{
767e468c 1906 struct efx_nic *efx = netdev_priv(net_dev);
8b7325b4 1907 int rc;
8ceee660 1908
8b7325b4
BH		 1909 rc = efx_check_disabled(efx);
1910 if (rc)
1911 return rc;
8ceee660
BH		 1912 if (new_mtu > EFX_MAX_MTU)
1913 return -EINVAL;
1914
62776d03 1915 netif_dbg(efx, drv, efx->net_dev, "changing MTU to %d\n", new_mtu);
8ceee660 1916
29c69a48
BH		 1917 efx_device_detach_sync(efx);
1918 efx_stop_all(efx);
1919
d3245b28 1920 mutex_lock(&efx->mac_lock);
8ceee660 1921 net_dev->mtu = new_mtu;
710b208d 1922 efx->type->reconfigure_mac(efx);
d3245b28
BH		 1923 mutex_unlock(&efx->mac_lock);
1924
8ceee660 1925 efx_start_all(efx);
29c69a48 1926 netif_device_attach(efx->net_dev);
6c8eef4a 1927 return 0;
8ceee660
BH		 1928}
1929
1930static int efx_set_mac_address(struct net_device *net_dev, void *data)
1931{
767e468c 1932 struct efx_nic *efx = netdev_priv(net_dev);
8ceee660
BH		 1933 struct sockaddr *addr = data;
1934 char *new_addr = addr->sa_data;
1935
8ceee660 1936 if (!is_valid_ether_addr(new_addr)) {
62776d03
BH		 1937 netif_err(efx, drv, efx->net_dev,
1938 "invalid ethernet MAC address requested: %pM\n",
1939 new_addr);
504f9b5a 1940 return -EADDRNOTAVAIL;
8ceee660
BH		 1941 }
1942
1943 memcpy(net_dev->dev_addr, new_addr, net_dev->addr_len);
cd2d5b52 1944 efx_sriov_mac_address_changed(efx);
8ceee660
BH		 1945
1946 /* Reconfigure the MAC */
d3245b28 1947 mutex_lock(&efx->mac_lock);
710b208d 1948 efx->type->reconfigure_mac(efx);
d3245b28 1949 mutex_unlock(&efx->mac_lock);
8ceee660
BH		 1950
1951 return 0;
1952}
1953
a816f75a 1954/* Context: netif_addr_lock held, BHs disabled. */
0fca8c97 1955static void efx_set_rx_mode(struct net_device *net_dev)
8ceee660 1956{
767e468c 1957 struct efx_nic *efx = netdev_priv(net_dev);
22bedad3 1958 struct netdev_hw_addr *ha;
8ceee660 1959 union efx_multicast_hash *mc_hash = &efx->multicast_hash;
8ceee660
BH		 1960 u32 crc;
1961 int bit;
8ceee660 1962
8be4f3e6 1963 efx->promiscuous = !!(net_dev->flags & IFF_PROMISC);
8ceee660
BH		 1964
1965 /* Build multicast hash table */
8be4f3e6 1966 if (efx->promiscuous || (net_dev->flags & IFF_ALLMULTI)) {
8ceee660
BH		 1967 memset(mc_hash, 0xff, sizeof(*mc_hash));
1968 } else {
1969 memset(mc_hash, 0x00, sizeof(*mc_hash));
22bedad3
JP		 1970 netdev_for_each_mc_addr(ha, net_dev) {
1971 crc = ether_crc_le(ETH_ALEN, ha->addr);
8ceee660 1972 bit = crc & (EFX_MCAST_HASH_ENTRIES - 1);
32766ec8 1973 __set_bit_le(bit, mc_hash);
8ceee660 1974 }
8ceee660 1975
8be4f3e6
BH		 1976 /* Broadcast packets go through the multicast hash filter.
1977 * ether_crc_le() of the broadcast address is 0xbe2612ff
1978 * so we always add bit 0xff to the mask.
1979 */
32766ec8 1980 __set_bit_le(0xff, mc_hash);
8be4f3e6 1981 }
a816f75a 1982
8be4f3e6
BH		 1983 if (efx->port_enabled)
1984 queue_work(efx->workqueue, &efx->mac_work);
1985 /* Otherwise efx_start_port() will do this */
8ceee660
BH		 1986}
1987
c8f44aff 1988static int efx_set_features(struct net_device *net_dev, netdev_features_t data)
abfe9039
BH		 1989{
1990 struct efx_nic *efx = netdev_priv(net_dev);
1991
1992 /* If disabling RX n-tuple filtering, clear existing filters */
1993 if (net_dev->features & ~data & NETIF_F_NTUPLE)
1994 efx_filter_clear_rx(efx, EFX_FILTER_PRI_MANUAL);
1995
1996 return 0;
1997}
1998
c3ecb9f3
SH		 1999static const struct net_device_ops efx_netdev_ops = {
2000 .ndo_open = efx_net_open,
2001 .ndo_stop = efx_net_stop,
4472702e 2002 .ndo_get_stats64 = efx_net_stats,
c3ecb9f3
SH		 2003 .ndo_tx_timeout = efx_watchdog,
2004 .ndo_start_xmit = efx_hard_start_xmit,
2005 .ndo_validate_addr = eth_validate_addr,
2006 .ndo_do_ioctl = efx_ioctl,
2007 .ndo_change_mtu = efx_change_mtu,
2008 .ndo_set_mac_address = efx_set_mac_address,
0fca8c97 2009 .ndo_set_rx_mode = efx_set_rx_mode,
abfe9039 2010 .ndo_set_features = efx_set_features,
cd2d5b52
BH		 2011#ifdef CONFIG_SFC_SRIOV
2012 .ndo_set_vf_mac = efx_sriov_set_vf_mac,
2013 .ndo_set_vf_vlan = efx_sriov_set_vf_vlan,
2014 .ndo_set_vf_spoofchk = efx_sriov_set_vf_spoofchk,
2015 .ndo_get_vf_config = efx_sriov_get_vf_config,
2016#endif
c3ecb9f3
SH		 2017#ifdef CONFIG_NET_POLL_CONTROLLER
2018 .ndo_poll_controller = efx_netpoll,
2019#endif
94b274bf 2020 .ndo_setup_tc = efx_setup_tc,
64d8ad6d
BH		 2021#ifdef CONFIG_RFS_ACCEL
2022 .ndo_rx_flow_steer = efx_filter_rfs,
2023#endif
c3ecb9f3
SH		 2024};
2025
7dde596e
BH		 2026static void efx_update_name(struct efx_nic *efx)
2027{
2028 strcpy(efx->name, efx->net_dev->name);
2029 efx_mtd_rename(efx);
2030 efx_set_channel_names(efx);
2031}
2032
8ceee660
BH		 2033static int efx_netdev_event(struct notifier_block *this,
2034 unsigned long event, void *ptr)
2035{
351638e7 2036 struct net_device *net_dev = netdev_notifier_info_to_dev(ptr);
8ceee660 2037
7dde596e
BH		 2038 if (net_dev->netdev_ops == &efx_netdev_ops &&
2039 event == NETDEV_CHANGENAME)
2040 efx_update_name(netdev_priv(net_dev));
8ceee660
BH		 2041
2042 return NOTIFY_DONE;
2043}
2044
2045static struct notifier_block efx_netdev_notifier = {
2046 .notifier_call = efx_netdev_event,
2047};
2048
06d5e193
BH		 2049static ssize_t
2050show_phy_type(struct device *dev, struct device_attribute *attr, char *buf)
2051{
2052 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
2053 return sprintf(buf, "%d\n", efx->phy_type);
2054}
776fbcc9 2055static DEVICE_ATTR(phy_type, 0444, show_phy_type, NULL);
06d5e193 2056
8ceee660
BH		 2057static int efx_register_netdev(struct efx_nic *efx)
2058{
2059 struct net_device *net_dev = efx->net_dev;
c04bfc6b 2060 struct efx_channel *channel;
8ceee660
BH		 2061 int rc;
2062
2063 net_dev->watchdog_timeo = 5 * HZ;
2064 net_dev->irq = efx->pci_dev->irq;
c3ecb9f3 2065 net_dev->netdev_ops = &efx_netdev_ops;
8ceee660 2066 SET_ETHTOOL_OPS(net_dev, &efx_ethtool_ops);
7e6d06f0 2067 net_dev->gso_max_segs = EFX_TSO_MAX_SEGS;
8ceee660 2068
7dde596e 2069 rtnl_lock();
aed0628d 2070
7153f623
BH		 2071 /* Enable resets to be scheduled and check whether any were
2072 * already requested. If so, the NIC is probably hosed so we
2073 * abort.
2074 */
2075 efx->state = STATE_READY;
2076 smp_mb(); /* ensure we change state before checking reset_pending */
2077 if (efx->reset_pending) {
2078 netif_err(efx, probe, efx->net_dev,
2079 "aborting probe due to scheduled reset\n");
2080 rc = -EIO;
2081 goto fail_locked;
2082 }
2083
aed0628d
BH		 2084 rc = dev_alloc_name(net_dev, net_dev->name);
2085 if (rc < 0)
2086 goto fail_locked;
7dde596e 2087 efx_update_name(efx);
aed0628d 2088
8f8b3d51
BH		 2089 /* Always start with carrier off; PHY events will detect the link */
2090 netif_carrier_off(net_dev);
2091
aed0628d
BH		 2092 rc = register_netdevice(net_dev);
2093 if (rc)
2094 goto fail_locked;
2095
c04bfc6b
BH		 2096 efx_for_each_channel(channel, efx) {
2097 struct efx_tx_queue *tx_queue;
60031fcc
BH		 2098 efx_for_each_channel_tx_queue(tx_queue, channel)
2099 efx_init_tx_queue_core_txq(tx_queue);
c04bfc6b
BH		 2100 }
2101
7dde596e 2102 rtnl_unlock();
8ceee660 2103
06d5e193
BH		 2104 rc = device_create_file(&efx->pci_dev->dev, &dev_attr_phy_type);
2105 if (rc) {
62776d03
BH		 2106 netif_err(efx, drv, efx->net_dev,
2107 "failed to init net dev attributes\n");
06d5e193
BH		 2108 goto fail_registered;
2109 }
2110
8ceee660 2111 return 0;
06d5e193 2112
7153f623
BH		 2113fail_registered:
2114 rtnl_lock();
2115 unregister_netdevice(net_dev);
aed0628d 2116fail_locked:
7153f623 2117 efx->state = STATE_UNINIT;
aed0628d 2118 rtnl_unlock();
62776d03 2119 netif_err(efx, drv, efx->net_dev, "could not register net dev\n");
aed0628d 2120 return rc;
8ceee660
BH		 2121}
2122
2123static void efx_unregister_netdev(struct efx_nic *efx)
2124{
f7d12cdc 2125 struct efx_channel *channel;
8ceee660
BH		 2126 struct efx_tx_queue *tx_queue;
2127
2128 if (!efx->net_dev)
2129 return;
2130
767e468c 2131 BUG_ON(netdev_priv(efx->net_dev) != efx);
8ceee660
BH		 2132
2133 /* Free up any skbs still remaining. This has to happen before
2134 * we try to unregister the netdev as running their destructors
2135 * may be needed to get the device ref. count to 0. */
f7d12cdc
BH		 2136 efx_for_each_channel(channel, efx) {
2137 efx_for_each_channel_tx_queue(tx_queue, channel)
2138 efx_release_tx_buffers(tx_queue);
2139 }
8ceee660 2140
73ba7b68
BH		 2141 strlcpy(efx->name, pci_name(efx->pci_dev), sizeof(efx->name));
2142 device_remove_file(&efx->pci_dev->dev, &dev_attr_phy_type);
7153f623
BH		 2143
2144 rtnl_lock();
2145 unregister_netdevice(efx->net_dev);
2146 efx->state = STATE_UNINIT;
2147 rtnl_unlock();
8ceee660
BH		 2148}
2149
2150/**************************************************************************
2151 *
2152 * Device reset and suspend
2153 *
2154 **************************************************************************/
2155
2467ca46
BH		 2156/* Tears down the entire software state and most of the hardware state
2157 * before reset. */
d3245b28 2158void efx_reset_down(struct efx_nic *efx, enum reset_type method)
8ceee660 2159{
8ceee660
BH		 2160 EFX_ASSERT_RESET_SERIALISED(efx);
2161
2467ca46 2162 efx_stop_all(efx);
7f967c01 2163 efx_stop_interrupts(efx, false);
5642ceef
BH		 2164
2165 mutex_lock(&efx->mac_lock);
4b988280
SH		 2166 if (efx->port_initialized && method != RESET_TYPE_INVISIBLE)
2167 efx->phy_op->fini(efx);
ef2b90ee 2168 efx->type->fini(efx);
8ceee660
BH		 2169}
2170
2467ca46
BH		 2171/* This function will always ensure that the locks acquired in
2172 * efx_reset_down() are released. A failure return code indicates
2173 * that we were unable to reinitialise the hardware, and the
2174 * driver should be disabled. If ok is false, then the rx and tx
2175 * engines are not restarted, pending a RESET_DISABLE. */
d3245b28 2176int efx_reset_up(struct efx_nic *efx, enum reset_type method, bool ok)
8ceee660
BH		 2177{
2178 int rc;
2179
2467ca46 2180 EFX_ASSERT_RESET_SERIALISED(efx);
8ceee660 2181
ef2b90ee 2182 rc = efx->type->init(efx);
8ceee660 2183 if (rc) {
62776d03 2184 netif_err(efx, drv, efx->net_dev, "failed to initialise NIC\n");
eb9f6744 2185 goto fail;
8ceee660
BH		 2186 }
2187
eb9f6744
BH		 2188 if (!ok)
2189 goto fail;
2190
4b988280 2191 if (efx->port_initialized && method != RESET_TYPE_INVISIBLE) {
eb9f6744
BH		 2192 rc = efx->phy_op->init(efx);
2193 if (rc)
2194 goto fail;
2195 if (efx->phy_op->reconfigure(efx))
62776d03
BH		 2196 netif_err(efx, drv, efx->net_dev,
2197 "could not restore PHY settings\n");
4b988280
SH		 2198 }
2199
710b208d 2200 efx->type->reconfigure_mac(efx);
8ceee660 2201
7f967c01 2202 efx_start_interrupts(efx, false);
64eebcfd 2203 efx_restore_filters(efx);
cd2d5b52 2204 efx_sriov_reset(efx);
eb9f6744 2205
eb9f6744
BH		 2206 mutex_unlock(&efx->mac_lock);
2207
2208 efx_start_all(efx);
2209
2210 return 0;
2211
2212fail:
2213 efx->port_initialized = false;
2467ca46
BH		 2214
2215 mutex_unlock(&efx->mac_lock);
2216
8ceee660
BH		 2217 return rc;
2218}
2219
eb9f6744
BH		 2220/* Reset the NIC using the specified method. Note that the reset may
2221 * fail, in which case the card will be left in an unusable state.
8ceee660 2222 *
eb9f6744 2223 * Caller must hold the rtnl_lock.
8ceee660 2224 */
eb9f6744 2225int efx_reset(struct efx_nic *efx, enum reset_type method)
8ceee660 2226{
eb9f6744
BH		 2227 int rc, rc2;
2228 bool disabled;
8ceee660 2229
62776d03
BH		 2230 netif_info(efx, drv, efx->net_dev, "resetting (%s)\n",
2231 RESET_TYPE(method));
8ceee660 2232
c2f3b8e3 2233 efx_device_detach_sync(efx);
d3245b28 2234 efx_reset_down(efx, method);
8ceee660 2235
ef2b90ee 2236 rc = efx->type->reset(efx, method);
8ceee660 2237 if (rc) {
62776d03 2238 netif_err(efx, drv, efx->net_dev, "failed to reset hardware\n");
eb9f6744 2239 goto out;
8ceee660
BH		 2240 }
2241
a7d529ae
BH		 2242 /* Clear flags for the scopes we covered. We assume the NIC and
2243 * driver are now quiescent so that there is no race here.
2244 */
2245 efx->reset_pending &= -(1 << (method + 1));
8ceee660
BH		 2246
2247 /* Reinitialise bus-mastering, which may have been turned off before
2248 * the reset was scheduled. This is still appropriate, even in the
2249 * RESET_TYPE_DISABLE since this driver generally assumes the hardware
2250 * can respond to requests. */
2251 pci_set_master(efx->pci_dev);
2252
eb9f6744 2253out:
8ceee660 2254 /* Leave device stopped if necessary */
626950db
AR		 2255 disabled = rc ||
2256 method == RESET_TYPE_DISABLE ||
2257 method == RESET_TYPE_RECOVER_OR_DISABLE;
eb9f6744
BH		 2258 rc2 = efx_reset_up(efx, method, !disabled);
2259 if (rc2) {
2260 disabled = true;
2261 if (!rc)
2262 rc = rc2;
8ceee660
BH		 2263 }
2264
eb9f6744 2265 if (disabled) {
f49a4589 2266 dev_close(efx->net_dev);
62776d03 2267 netif_err(efx, drv, efx->net_dev, "has been disabled\n");
f4bd954e 2268 efx->state = STATE_DISABLED;
f4bd954e 2269 } else {
62776d03 2270 netif_dbg(efx, drv, efx->net_dev, "reset complete\n");
e4abce85 2271 netif_device_attach(efx->net_dev);
f4bd954e 2272 }
8ceee660
BH		 2273 return rc;
2274}
2275
626950db
AR		 2276/* Try recovery mechanisms.
2277 * For now only EEH is supported.
2278 * Returns 0 if the recovery mechanisms are unsuccessful.
2279 * Returns a non-zero value otherwise.
2280 */
b28405b0 2281int efx_try_recovery(struct efx_nic *efx)
626950db
AR		 2282{
2283#ifdef CONFIG_EEH
2284 /* A PCI error can occur and not be seen by EEH because nothing
2285 * happens on the PCI bus. In this case the driver may fail and
2286 * schedule a 'recover or reset', leading to this recovery handler.
2287 * Manually call the eeh failure check function.
2288 */
2289 struct eeh_dev *eehdev =
2290 of_node_to_eeh_dev(pci_device_to_OF_node(efx->pci_dev));
2291
2292 if (eeh_dev_check_failure(eehdev)) {
2293 /* The EEH mechanisms will handle the error and reset the
2294 * device if necessary.
2295 */
2296 return 1;
2297 }
2298#endif
2299 return 0;
2300}
2301
8ceee660
BH		 2302/* The worker thread exists so that code that cannot sleep can
2303 * schedule a reset for later.
2304 */
2305static void efx_reset_work(struct work_struct *data)
2306{
eb9f6744 2307 struct efx_nic *efx = container_of(data, struct efx_nic, reset_work);
626950db
AR		 2308 unsigned long pending;
2309 enum reset_type method;
2310
2311 pending = ACCESS_ONCE(efx->reset_pending);
2312 method = fls(pending) - 1;
2313
2314 if ((method == RESET_TYPE_RECOVER_OR_DISABLE ||
2315 method == RESET_TYPE_RECOVER_OR_ALL) &&
2316 efx_try_recovery(efx))
2317 return;
8ceee660 2318
a7d529ae 2319 if (!pending)
319ba649
SH		 2320 return;
2321
eb9f6744 2322 rtnl_lock();
7153f623
BH		 2323
2324 /* We checked the state in efx_schedule_reset() but it may
2325 * have changed by now. Now that we have the RTNL lock,
2326 * it cannot change again.
2327 */
2328 if (efx->state == STATE_READY)
626950db 2329 (void)efx_reset(efx, method);
7153f623 2330
eb9f6744 2331 rtnl_unlock();
8ceee660
BH		 2332}
2333
2334void efx_schedule_reset(struct efx_nic *efx, enum reset_type type)
2335{
2336 enum reset_type method;
2337
626950db
AR		 2338 if (efx->state == STATE_RECOVERY) {
2339 netif_dbg(efx, drv, efx->net_dev,
2340 "recovering: skip scheduling %s reset\n",
2341 RESET_TYPE(type));
2342 return;
2343 }
2344
8ceee660
BH		 2345 switch (type) {
2346 case RESET_TYPE_INVISIBLE:
2347 case RESET_TYPE_ALL:
626950db 2348 case RESET_TYPE_RECOVER_OR_ALL:
8ceee660
BH		 2349 case RESET_TYPE_WORLD:
2350 case RESET_TYPE_DISABLE:
626950db 2351 case RESET_TYPE_RECOVER_OR_DISABLE:
8ceee660 2352 method = type;
0e2a9c7c
BH		 2353 netif_dbg(efx, drv, efx->net_dev, "scheduling %s reset\n",
2354 RESET_TYPE(method));
8ceee660 2355 break;
8ceee660 2356 default:
0e2a9c7c 2357 method = efx->type->map_reset_reason(type);
62776d03
BH		 2358 netif_dbg(efx, drv, efx->net_dev,
2359 "scheduling %s reset for %s\n",
2360 RESET_TYPE(method), RESET_TYPE(type));
0e2a9c7c
BH		 2361 break;
2362 }
8ceee660 2363
a7d529ae 2364 set_bit(method, &efx->reset_pending);
7153f623
BH		 2365 smp_mb(); /* ensure we change reset_pending before checking state */
2366
2367 /* If we're not READY then just leave the flags set as the cue
2368 * to abort probing or reschedule the reset later.
2369 */
2370 if (ACCESS_ONCE(efx->state) != STATE_READY)
2371 return;
8ceee660 2372
8880f4ec
BH		 2373 /* efx_process_channel() will no longer read events once a
2374 * reset is scheduled. So switch back to poll'd MCDI completions. */
2375 efx_mcdi_mode_poll(efx);
2376
1ab00629 2377 queue_work(reset_workqueue, &efx->reset_work);
8ceee660
BH		 2378}
2379
2380/**************************************************************************
2381 *
2382 * List of NICs we support
2383 *
2384 **************************************************************************/
2385
2386/* PCI device ID table */
a3aa1884 2387static DEFINE_PCI_DEVICE_TABLE(efx_pci_table) = {
937383a5
BH		 2388 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE,
2389 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0),
daeda630 2390 .driver_data = (unsigned long) &falcon_a1_nic_type},
937383a5
BH		 2391 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE,
2392 PCI_DEVICE_ID_SOLARFLARE_SFC4000B),
daeda630 2393 .driver_data = (unsigned long) &falcon_b0_nic_type},
547c474f 2394 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0803), /* SFC9020 */
8880f4ec 2395 .driver_data = (unsigned long) &siena_a0_nic_type},
547c474f 2396 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0813), /* SFL9021 */
8880f4ec 2397 .driver_data = (unsigned long) &siena_a0_nic_type},
8ceee660
BH		 2398 {0} /* end of list */
2399};
2400
2401/**************************************************************************
2402 *
3759433d 2403 * Dummy PHY/MAC operations
8ceee660 2404 *
01aad7b6 2405 * Can be used for some unimplemented operations
8ceee660
BH		 2406 * Needed so all function pointers are valid and do not have to be tested
2407 * before use
2408 *
2409 **************************************************************************/
2410int efx_port_dummy_op_int(struct efx_nic *efx)
2411{
2412 return 0;
2413}
2414void efx_port_dummy_op_void(struct efx_nic *efx) {}
d215697f 2415
2416static bool efx_port_dummy_op_poll(struct efx_nic *efx)
fdaa9aed
SH		 2417{
2418 return false;
2419}
8ceee660 2420
6c8c2513 2421static const struct efx_phy_operations efx_dummy_phy_operations = {
8ceee660 2422 .init = efx_port_dummy_op_int,
d3245b28 2423 .reconfigure = efx_port_dummy_op_int,
fdaa9aed 2424 .poll = efx_port_dummy_op_poll,
8ceee660 2425 .fini = efx_port_dummy_op_void,
8ceee660
BH		 2426};
2427
8ceee660
BH		 2428/**************************************************************************
2429 *
2430 * Data housekeeping
2431 *
2432 **************************************************************************/
2433
2434/* This zeroes out and then fills in the invariants in a struct
2435 * efx_nic (including all sub-structures).
2436 */
adeb15aa 2437static int efx_init_struct(struct efx_nic *efx,
8ceee660
BH		 2438 struct pci_dev *pci_dev, struct net_device *net_dev)
2439{
4642610c 2440 int i;
8ceee660
BH		 2441
2442 /* Initialise common structures */
8ceee660 2443 spin_lock_init(&efx->biu_lock);
76884835
BH		 2444#ifdef CONFIG_SFC_MTD
2445 INIT_LIST_HEAD(&efx->mtd_list);
2446#endif
8ceee660
BH		 2447 INIT_WORK(&efx->reset_work, efx_reset_work);
2448 INIT_DELAYED_WORK(&efx->monitor_work, efx_monitor);
dd40781e 2449 INIT_DELAYED_WORK(&efx->selftest_work, efx_selftest_async_work);
8ceee660 2450 efx->pci_dev = pci_dev;
62776d03 2451 efx->msg_enable = debug;
f16aeea0 2452 efx->state = STATE_UNINIT;
8ceee660 2453 strlcpy(efx->name, pci_name(pci_dev), sizeof(efx->name));
8ceee660
BH		 2454
2455 efx->net_dev = net_dev;
8ceee660
BH		 2456 spin_lock_init(&efx->stats_lock);
2457 mutex_init(&efx->mac_lock);
2458 efx->phy_op = &efx_dummy_phy_operations;
68e7f45e 2459 efx->mdio.dev = net_dev;
766ca0fa 2460 INIT_WORK(&efx->mac_work, efx_mac_work);
9f2cb71c 2461 init_waitqueue_head(&efx->flush_wq);
8ceee660
BH		 2462
2463 for (i = 0; i < EFX_MAX_CHANNELS; i++) {
4642610c
BH		 2464 efx->channel[i] = efx_alloc_channel(efx, i, NULL);
2465 if (!efx->channel[i])
2466 goto fail;
8ceee660
BH		 2467 }
2468
8ceee660
BH		 2469 EFX_BUG_ON_PARANOID(efx->type->phys_addr_channels > EFX_MAX_CHANNELS);
2470
2471 /* Higher numbered interrupt modes are less capable! */
2472 efx->interrupt_mode = max(efx->type->max_interrupt_mode,
2473 interrupt_mode);
2474
6977dc63
BH		 2475 /* Would be good to use the net_dev name, but we're too early */
2476 snprintf(efx->workqueue_name, sizeof(efx->workqueue_name), "sfc%s",
2477 pci_name(pci_dev));
2478 efx->workqueue = create_singlethread_workqueue(efx->workqueue_name);
1ab00629 2479 if (!efx->workqueue)
4642610c 2480 goto fail;
8d9853d9 2481
8ceee660 2482 return 0;
4642610c
BH		 2483
2484fail:
2485 efx_fini_struct(efx);
2486 return -ENOMEM;
8ceee660
BH		 2487}
2488
2489static void efx_fini_struct(struct efx_nic *efx)
2490{
8313aca3
BH		 2491 int i;
2492
2493 for (i = 0; i < EFX_MAX_CHANNELS; i++)
2494 kfree(efx->channel[i]);
2495
8ceee660
BH		 2496 if (efx->workqueue) {
2497 destroy_workqueue(efx->workqueue);
2498 efx->workqueue = NULL;
2499 }
2500}
2501
2502/**************************************************************************
2503 *
2504 * PCI interface
2505 *
2506 **************************************************************************/
2507
2508/* Main body of final NIC shutdown code
2509 * This is called only at module unload (or hotplug removal).
2510 */
2511static void efx_pci_remove_main(struct efx_nic *efx)
2512{
7153f623
BH		 2513 /* Flush reset_work. It can no longer be scheduled since we
2514 * are not READY.
2515 */
2516 BUG_ON(efx->state == STATE_READY);
2517 cancel_work_sync(&efx->reset_work);
2518
7f967c01 2519 efx_stop_interrupts(efx, false);
152b6a62 2520 efx_nic_fini_interrupt(efx);
8ceee660 2521 efx_fini_port(efx);
ef2b90ee 2522 efx->type->fini(efx);
8ceee660
BH		 2523 efx_fini_napi(efx);
2524 efx_remove_all(efx);
2525}
2526
2527/* Final NIC shutdown
2528 * This is called only at module unload (or hotplug removal).
2529 */
2530static void efx_pci_remove(struct pci_dev *pci_dev)
2531{
2532 struct efx_nic *efx;
2533
2534 efx = pci_get_drvdata(pci_dev);
2535 if (!efx)
2536 return;
2537
2538 /* Mark the NIC as fini, then stop the interface */
2539 rtnl_lock();
8ceee660 2540 dev_close(efx->net_dev);
5642ceef 2541 efx_stop_interrupts(efx, false);
8ceee660
BH		 2542 rtnl_unlock();
2543
cd2d5b52 2544 efx_sriov_fini(efx);
8ceee660
BH		 2545 efx_unregister_netdev(efx);
2546
7dde596e
BH		 2547 efx_mtd_remove(efx);
2548
8ceee660
BH		 2549 efx_pci_remove_main(efx);
2550
8ceee660 2551 efx_fini_io(efx);
62776d03 2552 netif_dbg(efx, drv, efx->net_dev, "shutdown successful\n");
8ceee660 2553
8ceee660 2554 efx_fini_struct(efx);
3de4e301 2555 pci_set_drvdata(pci_dev, NULL);
8ceee660 2556 free_netdev(efx->net_dev);
626950db
AR		 2557
2558 pci_disable_pcie_error_reporting(pci_dev);
8ceee660
BH		 2559};
2560
460eeaa0
BH		 2561/* NIC VPD information
2562 * Called during probe to display the part number of the
2563 * installed NIC. VPD is potentially very large but this should
2564 * always appear within the first 512 bytes.
2565 */
2566#define SFC_VPD_LEN 512
2567static void efx_print_product_vpd(struct efx_nic *efx)
2568{
2569 struct pci_dev *dev = efx->pci_dev;
2570 char vpd_data[SFC_VPD_LEN];
2571 ssize_t vpd_size;
2572 int i, j;
2573
2574 /* Get the vpd data from the device */
2575 vpd_size = pci_read_vpd(dev, 0, sizeof(vpd_data), vpd_data);
2576 if (vpd_size <= 0) {
2577 netif_err(efx, drv, efx->net_dev, "Unable to read VPD\n");
2578 return;
2579 }
2580
2581 /* Get the Read only section */
2582 i = pci_vpd_find_tag(vpd_data, 0, vpd_size, PCI_VPD_LRDT_RO_DATA);
2583 if (i < 0) {
2584 netif_err(efx, drv, efx->net_dev, "VPD Read-only not found\n");
2585 return;
2586 }
2587
2588 j = pci_vpd_lrdt_size(&vpd_data[i]);
2589 i += PCI_VPD_LRDT_TAG_SIZE;
2590 if (i + j > vpd_size)
2591 j = vpd_size - i;
2592
2593 /* Get the Part number */
2594 i = pci_vpd_find_info_keyword(vpd_data, i, j, "PN");
2595 if (i < 0) {
2596 netif_err(efx, drv, efx->net_dev, "Part number not found\n");
2597 return;
2598 }
2599
2600 j = pci_vpd_info_field_size(&vpd_data[i]);
2601 i += PCI_VPD_INFO_FLD_HDR_SIZE;
2602 if (i + j > vpd_size) {
2603 netif_err(efx, drv, efx->net_dev, "Incomplete part number\n");
2604 return;
2605 }
2606
2607 netif_info(efx, drv, efx->net_dev,
2608 "Part Number : %.*s\n", j, &vpd_data[i]);
2609}
2610
2611
8ceee660
BH		 2612/* Main body of NIC initialisation
2613 * This is called at module load (or hotplug insertion, theoretically).
2614 */
2615static int efx_pci_probe_main(struct efx_nic *efx)
2616{
2617 int rc;
2618
2619 /* Do start-of-day initialisation */
2620 rc = efx_probe_all(efx);
2621 if (rc)
2622 goto fail1;
2623
e8f14992 2624 efx_init_napi(efx);
8ceee660 2625
ef2b90ee 2626 rc = efx->type->init(efx);
8ceee660 2627 if (rc) {
62776d03
BH		 2628 netif_err(efx, probe, efx->net_dev,
2629 "failed to initialise NIC\n");
278c0621 2630 goto fail3;
8ceee660
BH		 2631 }
2632
2633 rc = efx_init_port(efx);
2634 if (rc) {
62776d03
BH		 2635 netif_err(efx, probe, efx->net_dev,
2636 "failed to initialise port\n");
278c0621 2637 goto fail4;
8ceee660
BH		 2638 }
2639
152b6a62 2640 rc = efx_nic_init_interrupt(efx);
8ceee660 2641 if (rc)
278c0621 2642 goto fail5;
7f967c01 2643 efx_start_interrupts(efx, false);
8ceee660
BH		 2644
2645 return 0;
2646
278c0621 2647 fail5:
8ceee660 2648 efx_fini_port(efx);
8ceee660 2649 fail4:
ef2b90ee 2650 efx->type->fini(efx);
8ceee660
BH		 2651 fail3:
2652 efx_fini_napi(efx);
8ceee660
BH		 2653 efx_remove_all(efx);
2654 fail1:
2655 return rc;
2656}
2657
2658/* NIC initialisation
2659 *
2660 * This is called at module load (or hotplug insertion,
73ba7b68 2661 * theoretically). It sets up PCI mappings, resets the NIC,
8ceee660
BH		 2662 * sets up and registers the network devices with the kernel and hooks
2663 * the interrupt service routine. It does not prepare the device for
2664 * transmission; this is left to the first time one of the network
2665 * interfaces is brought up (i.e. efx_net_open).
2666 */
87d1fc11 2667static int efx_pci_probe(struct pci_dev *pci_dev,
1dd06ae8 2668 const struct pci_device_id *entry)
8ceee660 2669{
8ceee660
BH		 2670 struct net_device *net_dev;
2671 struct efx_nic *efx;
fadac6aa 2672 int rc;
8ceee660
BH		 2673
2674 /* Allocate and initialise a struct net_device and struct efx_nic */
94b274bf
BH		 2675 net_dev = alloc_etherdev_mqs(sizeof(*efx), EFX_MAX_CORE_TX_QUEUES,
2676 EFX_MAX_RX_QUEUES);
8ceee660
BH		 2677 if (!net_dev)
2678 return -ENOMEM;
adeb15aa
BH		 2679 efx = netdev_priv(net_dev);
2680 efx->type = (const struct efx_nic_type *) entry->driver_data;
2681 net_dev->features |= (efx->type->offload_features | NETIF_F_SG |
97bc5415 2682 NETIF_F_HIGHDMA | NETIF_F_TSO |
abfe9039 2683 NETIF_F_RXCSUM);
adeb15aa 2684 if (efx->type->offload_features & NETIF_F_V6_CSUM)
738a8f4b 2685 net_dev->features |= NETIF_F_TSO6;
28506563
BH		 2686 /* Mask for features that also apply to VLAN devices */
2687 net_dev->vlan_features |= (NETIF_F_ALL_CSUM | NETIF_F_SG |
abfe9039
BH		 2688 NETIF_F_HIGHDMA | NETIF_F_ALL_TSO |
2689 NETIF_F_RXCSUM);
2690 /* All offloads can be toggled */
2691 net_dev->hw_features = net_dev->features & ~NETIF_F_HIGHDMA;
8ceee660 2692 pci_set_drvdata(pci_dev, efx);
62776d03 2693 SET_NETDEV_DEV(net_dev, &pci_dev->dev);
adeb15aa 2694 rc = efx_init_struct(efx, pci_dev, net_dev);
8ceee660
BH		 2695 if (rc)
2696 goto fail1;
2697
62776d03 2698 netif_info(efx, probe, efx->net_dev,
ff79c8ac 2699 "Solarflare NIC detected\n");
8ceee660 2700
460eeaa0
BH		 2701 efx_print_product_vpd(efx);
2702
8ceee660
BH		 2703 /* Set up basic I/O (BAR mappings etc) */
2704 rc = efx_init_io(efx);
2705 if (rc)
2706 goto fail2;
2707
fadac6aa 2708 rc = efx_pci_probe_main(efx);
fadac6aa
BH		 2709 if (rc)
2710 goto fail3;
8ceee660 2711
8ceee660
BH		 2712 rc = efx_register_netdev(efx);
2713 if (rc)
fadac6aa 2714 goto fail4;
8ceee660 2715
cd2d5b52
BH		 2716 rc = efx_sriov_init(efx);
2717 if (rc)
2718 netif_err(efx, probe, efx->net_dev,
2719 "SR-IOV can't be enabled rc %d\n", rc);
2720
62776d03 2721 netif_dbg(efx, probe, efx->net_dev, "initialisation successful\n");
a5211bb5 2722
7c43161c 2723 /* Try to create MTDs, but allow this to fail */
a5211bb5 2724 rtnl_lock();
7c43161c 2725 rc = efx_mtd_probe(efx);
a5211bb5 2726 rtnl_unlock();
7c43161c
BH		 2727 if (rc)
2728 netif_warn(efx, probe, efx->net_dev,
2729 "failed to create MTDs (%d)\n", rc);
2730
626950db
AR		 2731 rc = pci_enable_pcie_error_reporting(pci_dev);
2732 if (rc && rc != -EINVAL)
2733 netif_warn(efx, probe, efx->net_dev,
2734 "pci_enable_pcie_error_reporting failed (%d)\n", rc);
2735
8ceee660
BH		 2736 return 0;
2737
8ceee660 2738 fail4:
fadac6aa 2739 efx_pci_remove_main(efx);
8ceee660
BH		 2740 fail3:
2741 efx_fini_io(efx);
2742 fail2:
2743 efx_fini_struct(efx);
2744 fail1:
3de4e301 2745 pci_set_drvdata(pci_dev, NULL);
5e2a911c 2746 WARN_ON(rc > 0);
62776d03 2747 netif_dbg(efx, drv, efx->net_dev, "initialisation failed. rc=%d\n", rc);
8ceee660
BH		 2748 free_netdev(net_dev);
2749 return rc;
2750}
2751
89c758fa
BH		 2752static int efx_pm_freeze(struct device *dev)
2753{
2754 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
2755
61da026d
BH		 2756 rtnl_lock();
2757
6032fb56
BH		 2758 if (efx->state != STATE_DISABLED) {
2759 efx->state = STATE_UNINIT;
89c758fa 2760
c2f3b8e3 2761 efx_device_detach_sync(efx);
89c758fa 2762
6032fb56
BH		 2763 efx_stop_all(efx);
2764 efx_stop_interrupts(efx, false);
2765 }
89c758fa 2766
61da026d
BH		 2767 rtnl_unlock();
2768
89c758fa
BH		 2769 return 0;
2770}
2771
2772static int efx_pm_thaw(struct device *dev)
2773{
2774 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
2775
61da026d
BH		 2776 rtnl_lock();
2777
6032fb56
BH		 2778 if (efx->state != STATE_DISABLED) {
2779 efx_start_interrupts(efx, false);
89c758fa 2780
6032fb56
BH		 2781 mutex_lock(&efx->mac_lock);
2782 efx->phy_op->reconfigure(efx);
2783 mutex_unlock(&efx->mac_lock);
89c758fa 2784
6032fb56 2785 efx_start_all(efx);
89c758fa 2786
6032fb56 2787 netif_device_attach(efx->net_dev);
89c758fa 2788
6032fb56 2789 efx->state = STATE_READY;
89c758fa 2790
6032fb56
BH		 2791 efx->type->resume_wol(efx);
2792 }
89c758fa 2793
61da026d
BH		 2794 rtnl_unlock();
2795
319ba649
SH		 2796 /* Reschedule any quenched resets scheduled during efx_pm_freeze() */
2797 queue_work(reset_workqueue, &efx->reset_work);
2798
89c758fa
BH		 2799 return 0;
2800}
2801
2802static int efx_pm_poweroff(struct device *dev)
2803{
2804 struct pci_dev *pci_dev = to_pci_dev(dev);
2805 struct efx_nic *efx = pci_get_drvdata(pci_dev);
2806
2807 efx->type->fini(efx);
2808
a7d529ae 2809 efx->reset_pending = 0;
89c758fa
BH		 2810
2811 pci_save_state(pci_dev);
2812 return pci_set_power_state(pci_dev, PCI_D3hot);
2813}
2814
2815/* Used for both resume and restore */
2816static int efx_pm_resume(struct device *dev)
2817{
2818 struct pci_dev *pci_dev = to_pci_dev(dev);
2819 struct efx_nic *efx = pci_get_drvdata(pci_dev);
2820 int rc;
2821
2822 rc = pci_set_power_state(pci_dev, PCI_D0);
2823 if (rc)
2824 return rc;
2825 pci_restore_state(pci_dev);
2826 rc = pci_enable_device(pci_dev);
2827 if (rc)
2828 return rc;
2829 pci_set_master(efx->pci_dev);
2830 rc = efx->type->reset(efx, RESET_TYPE_ALL);
2831 if (rc)
2832 return rc;
2833 rc = efx->type->init(efx);
2834 if (rc)
2835 return rc;
2836 efx_pm_thaw(dev);
2837 return 0;
2838}
2839
2840static int efx_pm_suspend(struct device *dev)
2841{
2842 int rc;
2843
2844 efx_pm_freeze(dev);
2845 rc = efx_pm_poweroff(dev);
2846 if (rc)
2847 efx_pm_resume(dev);
2848 return rc;
2849}
2850
18e83e4c 2851static const struct dev_pm_ops efx_pm_ops = {
89c758fa
BH		 2852 .suspend = efx_pm_suspend,
2853 .resume = efx_pm_resume,
2854 .freeze = efx_pm_freeze,
2855 .thaw = efx_pm_thaw,
2856 .poweroff = efx_pm_poweroff,
2857 .restore = efx_pm_resume,
2858};
2859
626950db
AR		 2860/* A PCI error affecting this device was detected.
2861 * At this point MMIO and DMA may be disabled.
2862 * Stop the software path and request a slot reset.
2863 */
debd0034 2864static pci_ers_result_t efx_io_error_detected(struct pci_dev *pdev,
2865 enum pci_channel_state state)
626950db
AR		 2866{
2867 pci_ers_result_t status = PCI_ERS_RESULT_RECOVERED;
2868 struct efx_nic *efx = pci_get_drvdata(pdev);
2869
2870 if (state == pci_channel_io_perm_failure)
2871 return PCI_ERS_RESULT_DISCONNECT;
2872
2873 rtnl_lock();
2874
2875 if (efx->state != STATE_DISABLED) {
2876 efx->state = STATE_RECOVERY;
2877 efx->reset_pending = 0;
2878
2879 efx_device_detach_sync(efx);
2880
2881 efx_stop_all(efx);
2882 efx_stop_interrupts(efx, false);
2883
2884 status = PCI_ERS_RESULT_NEED_RESET;
2885 } else {
2886 /* If the interface is disabled we don't want to do anything
2887 * with it.
2888 */
2889 status = PCI_ERS_RESULT_RECOVERED;
2890 }
2891
2892 rtnl_unlock();
2893
2894 pci_disable_device(pdev);
2895
2896 return status;
2897}
2898
2899/* Fake a successfull reset, which will be performed later in efx_io_resume. */
debd0034 2900static pci_ers_result_t efx_io_slot_reset(struct pci_dev *pdev)
626950db
AR		 2901{
2902 struct efx_nic *efx = pci_get_drvdata(pdev);
2903 pci_ers_result_t status = PCI_ERS_RESULT_RECOVERED;
2904 int rc;
2905
2906 if (pci_enable_device(pdev)) {
2907 netif_err(efx, hw, efx->net_dev,
2908 "Cannot re-enable PCI device after reset.\n");
2909 status = PCI_ERS_RESULT_DISCONNECT;
2910 }
2911
2912 rc = pci_cleanup_aer_uncorrect_error_status(pdev);
2913 if (rc) {
2914 netif_err(efx, hw, efx->net_dev,
2915 "pci_cleanup_aer_uncorrect_error_status failed (%d)\n", rc);
2916 /* Non-fatal error. Continue. */
2917 }
2918
2919 return status;
2920}
2921
2922/* Perform the actual reset and resume I/O operations. */
2923static void efx_io_resume(struct pci_dev *pdev)
2924{
2925 struct efx_nic *efx = pci_get_drvdata(pdev);
2926 int rc;
2927
2928 rtnl_lock();
2929
2930 if (efx->state == STATE_DISABLED)
2931 goto out;
2932
2933 rc = efx_reset(efx, RESET_TYPE_ALL);
2934 if (rc) {
2935 netif_err(efx, hw, efx->net_dev,
2936 "efx_reset failed after PCI error (%d)\n", rc);
2937 } else {
2938 efx->state = STATE_READY;
2939 netif_dbg(efx, hw, efx->net_dev,
2940 "Done resetting and resuming IO after PCI error.\n");
2941 }
2942
2943out:
2944 rtnl_unlock();
2945}
2946
2947/* For simplicity and reliability, we always require a slot reset and try to
2948 * reset the hardware when a pci error affecting the device is detected.
2949 * We leave both the link_reset and mmio_enabled callback unimplemented:
2950 * with our request for slot reset the mmio_enabled callback will never be
2951 * called, and the link_reset callback is not used by AER or EEH mechanisms.
2952 */
2953static struct pci_error_handlers efx_err_handlers = {
2954 .error_detected = efx_io_error_detected,
2955 .slot_reset = efx_io_slot_reset,
2956 .resume = efx_io_resume,
2957};
2958
8ceee660 2959static struct pci_driver efx_pci_driver = {
c5d5f5fd 2960 .name = KBUILD_MODNAME,
8ceee660
BH		 2961 .id_table = efx_pci_table,
2962 .probe = efx_pci_probe,
2963 .remove = efx_pci_remove,
89c758fa 2964 .driver.pm = &efx_pm_ops,
626950db 2965 .err_handler = &efx_err_handlers,
8ceee660
BH		 2966};
2967
2968/**************************************************************************
2969 *
2970 * Kernel module interface
2971 *
2972 *************************************************************************/
2973
2974module_param(interrupt_mode, uint, 0444);
2975MODULE_PARM_DESC(interrupt_mode,
2976 "Interrupt mode (0=>MSIX 1=>MSI 2=>legacy)");
2977
2978static int __init efx_init_module(void)
2979{
2980 int rc;
2981
2982 printk(KERN_INFO "Solarflare NET driver v" EFX_DRIVER_VERSION "\n");
2983
2984 rc = register_netdevice_notifier(&efx_netdev_notifier);
2985 if (rc)
2986 goto err_notifier;
2987
cd2d5b52
BH		 2988 rc = efx_init_sriov();
2989 if (rc)
2990 goto err_sriov;
2991
1ab00629
SH		 2992 reset_workqueue = create_singlethread_workqueue("sfc_reset");
2993 if (!reset_workqueue) {
2994 rc = -ENOMEM;
2995 goto err_reset;
2996 }
8ceee660
BH		 2997
2998 rc = pci_register_driver(&efx_pci_driver);
2999 if (rc < 0)
3000 goto err_pci;
3001
3002 return 0;
3003
3004 err_pci:
1ab00629
SH		 3005 destroy_workqueue(reset_workqueue);
3006 err_reset:
cd2d5b52
BH		 3007 efx_fini_sriov();
3008 err_sriov:
8ceee660
BH		 3009 unregister_netdevice_notifier(&efx_netdev_notifier);
3010 err_notifier:
3011 return rc;
3012}
3013
3014static void __exit efx_exit_module(void)
3015{
3016 printk(KERN_INFO "Solarflare NET driver unloading\n");
3017
3018 pci_unregister_driver(&efx_pci_driver);
1ab00629 3019 destroy_workqueue(reset_workqueue);
cd2d5b52 3020 efx_fini_sriov();
8ceee660
BH		 3021 unregister_netdevice_notifier(&efx_netdev_notifier);
3022
3023}
3024
3025module_init(efx_init_module);
3026module_exit(efx_exit_module);
3027
906bb26c
BH		 3028MODULE_AUTHOR("Solarflare Communications and "
3029 "Michael Brown <mbrown@fensystems.co.uk>");
8ceee660
BH		 3030MODULE_DESCRIPTION("Solarflare Communications network driver");
3031MODULE_LICENSE("GPL");
3032MODULE_DEVICE_TABLE(pci, efx_pci_table);
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