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8ceee660 | 1 | /**************************************************************************** |
f7a6d2c4 | 2 | * Driver for Solarflare network controllers and boards |
8ceee660 | 3 | * Copyright 2005-2006 Fen Systems Ltd. |
f7a6d2c4 | 4 | * Copyright 2005-2013 Solarflare Communications Inc. |
8ceee660 BH |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation, incorporated herein by reference. | |
9 | */ | |
10 | ||
11 | #include <linux/module.h> | |
12 | #include <linux/pci.h> | |
13 | #include <linux/netdevice.h> | |
14 | #include <linux/etherdevice.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/notifier.h> | |
17 | #include <linux/ip.h> | |
18 | #include <linux/tcp.h> | |
19 | #include <linux/in.h> | |
8ceee660 | 20 | #include <linux/ethtool.h> |
aa6ef27e | 21 | #include <linux/topology.h> |
5a0e3ad6 | 22 | #include <linux/gfp.h> |
626950db | 23 | #include <linux/aer.h> |
b28405b0 | 24 | #include <linux/interrupt.h> |
8ceee660 | 25 | #include "net_driver.h" |
8ceee660 | 26 | #include "efx.h" |
744093c9 | 27 | #include "nic.h" |
dd40781e | 28 | #include "selftest.h" |
8ceee660 | 29 | |
8880f4ec | 30 | #include "mcdi.h" |
fd371e32 | 31 | #include "workarounds.h" |
8880f4ec | 32 | |
c459302d BH |
33 | /************************************************************************** |
34 | * | |
35 | * Type name strings | |
36 | * | |
37 | ************************************************************************** | |
38 | */ | |
39 | ||
40 | /* Loopback mode names (see LOOPBACK_MODE()) */ | |
41 | const unsigned int efx_loopback_mode_max = LOOPBACK_MAX; | |
18e83e4c | 42 | const char *const efx_loopback_mode_names[] = { |
c459302d | 43 | [LOOPBACK_NONE] = "NONE", |
e58f69f4 | 44 | [LOOPBACK_DATA] = "DATAPATH", |
c459302d BH |
45 | [LOOPBACK_GMAC] = "GMAC", |
46 | [LOOPBACK_XGMII] = "XGMII", | |
47 | [LOOPBACK_XGXS] = "XGXS", | |
9c636baf BH |
48 | [LOOPBACK_XAUI] = "XAUI", |
49 | [LOOPBACK_GMII] = "GMII", | |
50 | [LOOPBACK_SGMII] = "SGMII", | |
e58f69f4 BH |
51 | [LOOPBACK_XGBR] = "XGBR", |
52 | [LOOPBACK_XFI] = "XFI", | |
53 | [LOOPBACK_XAUI_FAR] = "XAUI_FAR", | |
54 | [LOOPBACK_GMII_FAR] = "GMII_FAR", | |
55 | [LOOPBACK_SGMII_FAR] = "SGMII_FAR", | |
56 | [LOOPBACK_XFI_FAR] = "XFI_FAR", | |
c459302d BH |
57 | [LOOPBACK_GPHY] = "GPHY", |
58 | [LOOPBACK_PHYXS] = "PHYXS", | |
9c636baf BH |
59 | [LOOPBACK_PCS] = "PCS", |
60 | [LOOPBACK_PMAPMD] = "PMA/PMD", | |
e58f69f4 BH |
61 | [LOOPBACK_XPORT] = "XPORT", |
62 | [LOOPBACK_XGMII_WS] = "XGMII_WS", | |
9c636baf | 63 | [LOOPBACK_XAUI_WS] = "XAUI_WS", |
e58f69f4 BH |
64 | [LOOPBACK_XAUI_WS_FAR] = "XAUI_WS_FAR", |
65 | [LOOPBACK_XAUI_WS_NEAR] = "XAUI_WS_NEAR", | |
9c636baf | 66 | [LOOPBACK_GMII_WS] = "GMII_WS", |
e58f69f4 BH |
67 | [LOOPBACK_XFI_WS] = "XFI_WS", |
68 | [LOOPBACK_XFI_WS_FAR] = "XFI_WS_FAR", | |
9c636baf | 69 | [LOOPBACK_PHYXS_WS] = "PHYXS_WS", |
c459302d BH |
70 | }; |
71 | ||
c459302d | 72 | const unsigned int efx_reset_type_max = RESET_TYPE_MAX; |
18e83e4c | 73 | const char *const efx_reset_type_names[] = { |
626950db AR |
74 | [RESET_TYPE_INVISIBLE] = "INVISIBLE", |
75 | [RESET_TYPE_ALL] = "ALL", | |
76 | [RESET_TYPE_RECOVER_OR_ALL] = "RECOVER_OR_ALL", | |
77 | [RESET_TYPE_WORLD] = "WORLD", | |
78 | [RESET_TYPE_RECOVER_OR_DISABLE] = "RECOVER_OR_DISABLE", | |
e283546c | 79 | [RESET_TYPE_MC_BIST] = "MC_BIST", |
626950db AR |
80 | [RESET_TYPE_DISABLE] = "DISABLE", |
81 | [RESET_TYPE_TX_WATCHDOG] = "TX_WATCHDOG", | |
82 | [RESET_TYPE_INT_ERROR] = "INT_ERROR", | |
83 | [RESET_TYPE_RX_RECOVERY] = "RX_RECOVERY", | |
3de82b91 | 84 | [RESET_TYPE_DMA_ERROR] = "DMA_ERROR", |
626950db AR |
85 | [RESET_TYPE_TX_SKIP] = "TX_SKIP", |
86 | [RESET_TYPE_MC_FAILURE] = "MC_FAILURE", | |
e283546c | 87 | [RESET_TYPE_MCDI_TIMEOUT] = "MCDI_TIMEOUT (FLR)", |
c459302d BH |
88 | }; |
89 | ||
1ab00629 SH |
90 | /* Reset workqueue. If any NIC has a hardware failure then a reset will be |
91 | * queued onto this work queue. This is not a per-nic work queue, because | |
92 | * efx_reset_work() acquires the rtnl lock, so resets are naturally serialised. | |
93 | */ | |
94 | static struct workqueue_struct *reset_workqueue; | |
95 | ||
74cd60a4 JC |
96 | /* How often and how many times to poll for a reset while waiting for a |
97 | * BIST that another function started to complete. | |
98 | */ | |
99 | #define BIST_WAIT_DELAY_MS 100 | |
100 | #define BIST_WAIT_DELAY_COUNT 100 | |
101 | ||
8ceee660 BH |
102 | /************************************************************************** |
103 | * | |
104 | * Configurable values | |
105 | * | |
106 | *************************************************************************/ | |
107 | ||
8ceee660 BH |
108 | /* |
109 | * Use separate channels for TX and RX events | |
110 | * | |
28b581ab NT |
111 | * Set this to 1 to use separate channels for TX and RX. It allows us |
112 | * to control interrupt affinity separately for TX and RX. | |
8ceee660 | 113 | * |
28b581ab | 114 | * This is only used in MSI-X interrupt mode |
8ceee660 | 115 | */ |
b9cc977d BH |
116 | static bool separate_tx_channels; |
117 | module_param(separate_tx_channels, bool, 0444); | |
28b581ab NT |
118 | MODULE_PARM_DESC(separate_tx_channels, |
119 | "Use separate channels for TX and RX"); | |
8ceee660 BH |
120 | |
121 | /* This is the weight assigned to each of the (per-channel) virtual | |
122 | * NAPI devices. | |
123 | */ | |
124 | static int napi_weight = 64; | |
125 | ||
126 | /* This is the time (in jiffies) between invocations of the hardware | |
626950db AR |
127 | * monitor. |
128 | * On Falcon-based NICs, this will: | |
e254c274 BH |
129 | * - Check the on-board hardware monitor; |
130 | * - Poll the link state and reconfigure the hardware as necessary. | |
626950db AR |
131 | * On Siena-based NICs for power systems with EEH support, this will give EEH a |
132 | * chance to start. | |
8ceee660 | 133 | */ |
d215697f | 134 | static unsigned int efx_monitor_interval = 1 * HZ; |
8ceee660 | 135 | |
8ceee660 BH |
136 | /* Initial interrupt moderation settings. They can be modified after |
137 | * module load with ethtool. | |
138 | * | |
139 | * The default for RX should strike a balance between increasing the | |
140 | * round-trip latency and reducing overhead. | |
141 | */ | |
142 | static unsigned int rx_irq_mod_usec = 60; | |
143 | ||
144 | /* Initial interrupt moderation settings. They can be modified after | |
145 | * module load with ethtool. | |
146 | * | |
147 | * This default is chosen to ensure that a 10G link does not go idle | |
148 | * while a TX queue is stopped after it has become full. A queue is | |
149 | * restarted when it drops below half full. The time this takes (assuming | |
150 | * worst case 3 descriptors per packet and 1024 descriptors) is | |
151 | * 512 / 3 * 1.2 = 205 usec. | |
152 | */ | |
153 | static unsigned int tx_irq_mod_usec = 150; | |
154 | ||
155 | /* This is the first interrupt mode to try out of: | |
156 | * 0 => MSI-X | |
157 | * 1 => MSI | |
158 | * 2 => legacy | |
159 | */ | |
160 | static unsigned int interrupt_mode; | |
161 | ||
162 | /* This is the requested number of CPUs to use for Receive-Side Scaling (RSS), | |
163 | * i.e. the number of CPUs among which we may distribute simultaneous | |
164 | * interrupt handling. | |
165 | * | |
166 | * Cards without MSI-X will only target one CPU via legacy or MSI interrupt. | |
cdb08f8f | 167 | * The default (0) means to assign an interrupt to each core. |
8ceee660 BH |
168 | */ |
169 | static unsigned int rss_cpus; | |
170 | module_param(rss_cpus, uint, 0444); | |
171 | MODULE_PARM_DESC(rss_cpus, "Number of CPUs to use for Receive-Side Scaling"); | |
172 | ||
b9cc977d BH |
173 | static bool phy_flash_cfg; |
174 | module_param(phy_flash_cfg, bool, 0644); | |
84ae48fe BH |
175 | MODULE_PARM_DESC(phy_flash_cfg, "Set PHYs into reflash mode initially"); |
176 | ||
e7bed9c8 | 177 | static unsigned irq_adapt_low_thresh = 8000; |
6fb70fd1 BH |
178 | module_param(irq_adapt_low_thresh, uint, 0644); |
179 | MODULE_PARM_DESC(irq_adapt_low_thresh, | |
180 | "Threshold score for reducing IRQ moderation"); | |
181 | ||
e7bed9c8 | 182 | static unsigned irq_adapt_high_thresh = 16000; |
6fb70fd1 BH |
183 | module_param(irq_adapt_high_thresh, uint, 0644); |
184 | MODULE_PARM_DESC(irq_adapt_high_thresh, | |
185 | "Threshold score for increasing IRQ moderation"); | |
186 | ||
62776d03 BH |
187 | static unsigned debug = (NETIF_MSG_DRV | NETIF_MSG_PROBE | |
188 | NETIF_MSG_LINK | NETIF_MSG_IFDOWN | | |
189 | NETIF_MSG_IFUP | NETIF_MSG_RX_ERR | | |
190 | NETIF_MSG_TX_ERR | NETIF_MSG_HW); | |
191 | module_param(debug, uint, 0); | |
192 | MODULE_PARM_DESC(debug, "Bitmapped debugging message enable value"); | |
193 | ||
8ceee660 BH |
194 | /************************************************************************** |
195 | * | |
196 | * Utility functions and prototypes | |
197 | * | |
198 | *************************************************************************/ | |
4642610c | 199 | |
261e4d96 | 200 | static int efx_soft_enable_interrupts(struct efx_nic *efx); |
d8291187 | 201 | static void efx_soft_disable_interrupts(struct efx_nic *efx); |
7f967c01 | 202 | static void efx_remove_channel(struct efx_channel *channel); |
4642610c | 203 | static void efx_remove_channels(struct efx_nic *efx); |
7f967c01 | 204 | static const struct efx_channel_type efx_default_channel_type; |
8ceee660 | 205 | static void efx_remove_port(struct efx_nic *efx); |
7f967c01 | 206 | static void efx_init_napi_channel(struct efx_channel *channel); |
8ceee660 | 207 | static void efx_fini_napi(struct efx_nic *efx); |
e8f14992 | 208 | static void efx_fini_napi_channel(struct efx_channel *channel); |
4642610c BH |
209 | static void efx_fini_struct(struct efx_nic *efx); |
210 | static void efx_start_all(struct efx_nic *efx); | |
211 | static void efx_stop_all(struct efx_nic *efx); | |
8ceee660 BH |
212 | |
213 | #define EFX_ASSERT_RESET_SERIALISED(efx) \ | |
214 | do { \ | |
f16aeea0 | 215 | if ((efx->state == STATE_READY) || \ |
626950db | 216 | (efx->state == STATE_RECOVERY) || \ |
332c1ce9 | 217 | (efx->state == STATE_DISABLED)) \ |
8ceee660 BH |
218 | ASSERT_RTNL(); \ |
219 | } while (0) | |
220 | ||
8b7325b4 BH |
221 | static int efx_check_disabled(struct efx_nic *efx) |
222 | { | |
626950db | 223 | if (efx->state == STATE_DISABLED || efx->state == STATE_RECOVERY) { |
8b7325b4 BH |
224 | netif_err(efx, drv, efx->net_dev, |
225 | "device is disabled due to earlier errors\n"); | |
226 | return -EIO; | |
227 | } | |
228 | return 0; | |
229 | } | |
230 | ||
8ceee660 BH |
231 | /************************************************************************** |
232 | * | |
233 | * Event queue processing | |
234 | * | |
235 | *************************************************************************/ | |
236 | ||
237 | /* Process channel's event queue | |
238 | * | |
239 | * This function is responsible for processing the event queue of a | |
240 | * single channel. The caller must guarantee that this function will | |
241 | * never be concurrently called more than once on the same channel, | |
242 | * though different channels may be being processed concurrently. | |
243 | */ | |
fa236e18 | 244 | static int efx_process_channel(struct efx_channel *channel, int budget) |
8ceee660 | 245 | { |
fa236e18 | 246 | int spent; |
8ceee660 | 247 | |
9f2cb71c | 248 | if (unlikely(!channel->enabled)) |
42cbe2d7 | 249 | return 0; |
8ceee660 | 250 | |
fa236e18 | 251 | spent = efx_nic_process_eventq(channel, budget); |
d9ab7007 BH |
252 | if (spent && efx_channel_has_rx_queue(channel)) { |
253 | struct efx_rx_queue *rx_queue = | |
254 | efx_channel_get_rx_queue(channel); | |
255 | ||
ff734ef4 | 256 | efx_rx_flush_packet(channel); |
cce28794 | 257 | efx_fast_push_rx_descriptors(rx_queue, true); |
8ceee660 BH |
258 | } |
259 | ||
fa236e18 | 260 | return spent; |
8ceee660 BH |
261 | } |
262 | ||
8ceee660 BH |
263 | /* NAPI poll handler |
264 | * | |
265 | * NAPI guarantees serialisation of polls of the same device, which | |
266 | * provides the guarantee required by efx_process_channel(). | |
267 | */ | |
268 | static int efx_poll(struct napi_struct *napi, int budget) | |
269 | { | |
270 | struct efx_channel *channel = | |
271 | container_of(napi, struct efx_channel, napi_str); | |
62776d03 | 272 | struct efx_nic *efx = channel->efx; |
fa236e18 | 273 | int spent; |
8ceee660 | 274 | |
36763266 AR |
275 | if (!efx_channel_lock_napi(channel)) |
276 | return budget; | |
277 | ||
62776d03 BH |
278 | netif_vdbg(efx, intr, efx->net_dev, |
279 | "channel %d NAPI poll executing on CPU %d\n", | |
280 | channel->channel, raw_smp_processor_id()); | |
8ceee660 | 281 | |
fa236e18 | 282 | spent = efx_process_channel(channel, budget); |
8ceee660 | 283 | |
fa236e18 | 284 | if (spent < budget) { |
9d9a6973 | 285 | if (efx_channel_has_rx_queue(channel) && |
6fb70fd1 BH |
286 | efx->irq_rx_adaptive && |
287 | unlikely(++channel->irq_count == 1000)) { | |
6fb70fd1 BH |
288 | if (unlikely(channel->irq_mod_score < |
289 | irq_adapt_low_thresh)) { | |
0d86ebd8 BH |
290 | if (channel->irq_moderation > 1) { |
291 | channel->irq_moderation -= 1; | |
ef2b90ee | 292 | efx->type->push_irq_moderation(channel); |
0d86ebd8 | 293 | } |
6fb70fd1 BH |
294 | } else if (unlikely(channel->irq_mod_score > |
295 | irq_adapt_high_thresh)) { | |
0d86ebd8 BH |
296 | if (channel->irq_moderation < |
297 | efx->irq_rx_moderation) { | |
298 | channel->irq_moderation += 1; | |
ef2b90ee | 299 | efx->type->push_irq_moderation(channel); |
0d86ebd8 | 300 | } |
6fb70fd1 | 301 | } |
6fb70fd1 BH |
302 | channel->irq_count = 0; |
303 | channel->irq_mod_score = 0; | |
304 | } | |
305 | ||
64d8ad6d BH |
306 | efx_filter_rfs_expire(channel); |
307 | ||
8ceee660 | 308 | /* There is no race here; although napi_disable() will |
288379f0 | 309 | * only wait for napi_complete(), this isn't a problem |
514bedbc | 310 | * since efx_nic_eventq_read_ack() will have no effect if |
8ceee660 BH |
311 | * interrupts have already been disabled. |
312 | */ | |
288379f0 | 313 | napi_complete(napi); |
514bedbc | 314 | efx_nic_eventq_read_ack(channel); |
8ceee660 BH |
315 | } |
316 | ||
36763266 | 317 | efx_channel_unlock_napi(channel); |
fa236e18 | 318 | return spent; |
8ceee660 BH |
319 | } |
320 | ||
8ceee660 BH |
321 | /* Create event queue |
322 | * Event queue memory allocations are done only once. If the channel | |
323 | * is reset, the memory buffer will be reused; this guards against | |
324 | * errors during channel reset and also simplifies interrupt handling. | |
325 | */ | |
326 | static int efx_probe_eventq(struct efx_channel *channel) | |
327 | { | |
ecc910f5 SH |
328 | struct efx_nic *efx = channel->efx; |
329 | unsigned long entries; | |
330 | ||
86ee5302 | 331 | netif_dbg(efx, probe, efx->net_dev, |
62776d03 | 332 | "chan %d create event queue\n", channel->channel); |
8ceee660 | 333 | |
ecc910f5 SH |
334 | /* Build an event queue with room for one event per tx and rx buffer, |
335 | * plus some extra for link state events and MCDI completions. */ | |
336 | entries = roundup_pow_of_two(efx->rxq_entries + efx->txq_entries + 128); | |
337 | EFX_BUG_ON_PARANOID(entries > EFX_MAX_EVQ_SIZE); | |
338 | channel->eventq_mask = max(entries, EFX_MIN_EVQ_SIZE) - 1; | |
339 | ||
152b6a62 | 340 | return efx_nic_probe_eventq(channel); |
8ceee660 BH |
341 | } |
342 | ||
343 | /* Prepare channel's event queue */ | |
261e4d96 | 344 | static int efx_init_eventq(struct efx_channel *channel) |
8ceee660 | 345 | { |
15acb1ce | 346 | struct efx_nic *efx = channel->efx; |
261e4d96 JC |
347 | int rc; |
348 | ||
349 | EFX_WARN_ON_PARANOID(channel->eventq_init); | |
350 | ||
15acb1ce | 351 | netif_dbg(efx, drv, efx->net_dev, |
62776d03 | 352 | "chan %d init event queue\n", channel->channel); |
8ceee660 | 353 | |
261e4d96 JC |
354 | rc = efx_nic_init_eventq(channel); |
355 | if (rc == 0) { | |
15acb1ce | 356 | efx->type->push_irq_moderation(channel); |
261e4d96 JC |
357 | channel->eventq_read_ptr = 0; |
358 | channel->eventq_init = true; | |
359 | } | |
360 | return rc; | |
8ceee660 BH |
361 | } |
362 | ||
9f2cb71c | 363 | /* Enable event queue processing and NAPI */ |
36763266 | 364 | void efx_start_eventq(struct efx_channel *channel) |
9f2cb71c BH |
365 | { |
366 | netif_dbg(channel->efx, ifup, channel->efx->net_dev, | |
367 | "chan %d start event queue\n", channel->channel); | |
368 | ||
514bedbc | 369 | /* Make sure the NAPI handler sees the enabled flag set */ |
9f2cb71c BH |
370 | channel->enabled = true; |
371 | smp_wmb(); | |
372 | ||
36763266 | 373 | efx_channel_enable(channel); |
9f2cb71c BH |
374 | napi_enable(&channel->napi_str); |
375 | efx_nic_eventq_read_ack(channel); | |
376 | } | |
377 | ||
378 | /* Disable event queue processing and NAPI */ | |
36763266 | 379 | void efx_stop_eventq(struct efx_channel *channel) |
9f2cb71c BH |
380 | { |
381 | if (!channel->enabled) | |
382 | return; | |
383 | ||
384 | napi_disable(&channel->napi_str); | |
36763266 AR |
385 | while (!efx_channel_disable(channel)) |
386 | usleep_range(1000, 20000); | |
9f2cb71c BH |
387 | channel->enabled = false; |
388 | } | |
389 | ||
8ceee660 BH |
390 | static void efx_fini_eventq(struct efx_channel *channel) |
391 | { | |
be3fc09c BH |
392 | if (!channel->eventq_init) |
393 | return; | |
394 | ||
62776d03 BH |
395 | netif_dbg(channel->efx, drv, channel->efx->net_dev, |
396 | "chan %d fini event queue\n", channel->channel); | |
8ceee660 | 397 | |
152b6a62 | 398 | efx_nic_fini_eventq(channel); |
be3fc09c | 399 | channel->eventq_init = false; |
8ceee660 BH |
400 | } |
401 | ||
402 | static void efx_remove_eventq(struct efx_channel *channel) | |
403 | { | |
62776d03 BH |
404 | netif_dbg(channel->efx, drv, channel->efx->net_dev, |
405 | "chan %d remove event queue\n", channel->channel); | |
8ceee660 | 406 | |
152b6a62 | 407 | efx_nic_remove_eventq(channel); |
8ceee660 BH |
408 | } |
409 | ||
410 | /************************************************************************** | |
411 | * | |
412 | * Channel handling | |
413 | * | |
414 | *************************************************************************/ | |
415 | ||
7f967c01 | 416 | /* Allocate and initialise a channel structure. */ |
4642610c BH |
417 | static struct efx_channel * |
418 | efx_alloc_channel(struct efx_nic *efx, int i, struct efx_channel *old_channel) | |
419 | { | |
420 | struct efx_channel *channel; | |
421 | struct efx_rx_queue *rx_queue; | |
422 | struct efx_tx_queue *tx_queue; | |
423 | int j; | |
424 | ||
7f967c01 BH |
425 | channel = kzalloc(sizeof(*channel), GFP_KERNEL); |
426 | if (!channel) | |
427 | return NULL; | |
4642610c | 428 | |
7f967c01 BH |
429 | channel->efx = efx; |
430 | channel->channel = i; | |
431 | channel->type = &efx_default_channel_type; | |
4642610c | 432 | |
7f967c01 BH |
433 | for (j = 0; j < EFX_TXQ_TYPES; j++) { |
434 | tx_queue = &channel->tx_queue[j]; | |
435 | tx_queue->efx = efx; | |
436 | tx_queue->queue = i * EFX_TXQ_TYPES + j; | |
437 | tx_queue->channel = channel; | |
438 | } | |
4642610c | 439 | |
7f967c01 BH |
440 | rx_queue = &channel->rx_queue; |
441 | rx_queue->efx = efx; | |
442 | setup_timer(&rx_queue->slow_fill, efx_rx_slow_fill, | |
443 | (unsigned long)rx_queue); | |
4642610c | 444 | |
7f967c01 BH |
445 | return channel; |
446 | } | |
447 | ||
448 | /* Allocate and initialise a channel structure, copying parameters | |
449 | * (but not resources) from an old channel structure. | |
450 | */ | |
451 | static struct efx_channel * | |
452 | efx_copy_channel(const struct efx_channel *old_channel) | |
453 | { | |
454 | struct efx_channel *channel; | |
455 | struct efx_rx_queue *rx_queue; | |
456 | struct efx_tx_queue *tx_queue; | |
457 | int j; | |
4642610c | 458 | |
7f967c01 BH |
459 | channel = kmalloc(sizeof(*channel), GFP_KERNEL); |
460 | if (!channel) | |
461 | return NULL; | |
462 | ||
463 | *channel = *old_channel; | |
464 | ||
465 | channel->napi_dev = NULL; | |
466 | memset(&channel->eventq, 0, sizeof(channel->eventq)); | |
4642610c | 467 | |
7f967c01 BH |
468 | for (j = 0; j < EFX_TXQ_TYPES; j++) { |
469 | tx_queue = &channel->tx_queue[j]; | |
470 | if (tx_queue->channel) | |
4642610c | 471 | tx_queue->channel = channel; |
7f967c01 BH |
472 | tx_queue->buffer = NULL; |
473 | memset(&tx_queue->txd, 0, sizeof(tx_queue->txd)); | |
4642610c BH |
474 | } |
475 | ||
4642610c | 476 | rx_queue = &channel->rx_queue; |
7f967c01 BH |
477 | rx_queue->buffer = NULL; |
478 | memset(&rx_queue->rxd, 0, sizeof(rx_queue->rxd)); | |
4642610c BH |
479 | setup_timer(&rx_queue->slow_fill, efx_rx_slow_fill, |
480 | (unsigned long)rx_queue); | |
481 | ||
482 | return channel; | |
483 | } | |
484 | ||
8ceee660 BH |
485 | static int efx_probe_channel(struct efx_channel *channel) |
486 | { | |
487 | struct efx_tx_queue *tx_queue; | |
488 | struct efx_rx_queue *rx_queue; | |
489 | int rc; | |
490 | ||
62776d03 BH |
491 | netif_dbg(channel->efx, probe, channel->efx->net_dev, |
492 | "creating channel %d\n", channel->channel); | |
8ceee660 | 493 | |
7f967c01 BH |
494 | rc = channel->type->pre_probe(channel); |
495 | if (rc) | |
496 | goto fail; | |
497 | ||
8ceee660 BH |
498 | rc = efx_probe_eventq(channel); |
499 | if (rc) | |
7f967c01 | 500 | goto fail; |
8ceee660 BH |
501 | |
502 | efx_for_each_channel_tx_queue(tx_queue, channel) { | |
503 | rc = efx_probe_tx_queue(tx_queue); | |
504 | if (rc) | |
7f967c01 | 505 | goto fail; |
8ceee660 BH |
506 | } |
507 | ||
508 | efx_for_each_channel_rx_queue(rx_queue, channel) { | |
509 | rc = efx_probe_rx_queue(rx_queue); | |
510 | if (rc) | |
7f967c01 | 511 | goto fail; |
8ceee660 BH |
512 | } |
513 | ||
8ceee660 BH |
514 | return 0; |
515 | ||
7f967c01 BH |
516 | fail: |
517 | efx_remove_channel(channel); | |
8ceee660 BH |
518 | return rc; |
519 | } | |
520 | ||
7f967c01 BH |
521 | static void |
522 | efx_get_channel_name(struct efx_channel *channel, char *buf, size_t len) | |
523 | { | |
524 | struct efx_nic *efx = channel->efx; | |
525 | const char *type; | |
526 | int number; | |
527 | ||
528 | number = channel->channel; | |
529 | if (efx->tx_channel_offset == 0) { | |
530 | type = ""; | |
531 | } else if (channel->channel < efx->tx_channel_offset) { | |
532 | type = "-rx"; | |
533 | } else { | |
534 | type = "-tx"; | |
535 | number -= efx->tx_channel_offset; | |
536 | } | |
537 | snprintf(buf, len, "%s%s-%d", efx->name, type, number); | |
538 | } | |
8ceee660 | 539 | |
56536e9c BH |
540 | static void efx_set_channel_names(struct efx_nic *efx) |
541 | { | |
542 | struct efx_channel *channel; | |
56536e9c | 543 | |
7f967c01 BH |
544 | efx_for_each_channel(channel, efx) |
545 | channel->type->get_name(channel, | |
d8291187 BH |
546 | efx->msi_context[channel->channel].name, |
547 | sizeof(efx->msi_context[0].name)); | |
56536e9c BH |
548 | } |
549 | ||
4642610c BH |
550 | static int efx_probe_channels(struct efx_nic *efx) |
551 | { | |
552 | struct efx_channel *channel; | |
553 | int rc; | |
554 | ||
555 | /* Restart special buffer allocation */ | |
556 | efx->next_buffer_table = 0; | |
557 | ||
c92aaff1 BH |
558 | /* Probe channels in reverse, so that any 'extra' channels |
559 | * use the start of the buffer table. This allows the traffic | |
560 | * channels to be resized without moving them or wasting the | |
561 | * entries before them. | |
562 | */ | |
563 | efx_for_each_channel_rev(channel, efx) { | |
4642610c BH |
564 | rc = efx_probe_channel(channel); |
565 | if (rc) { | |
566 | netif_err(efx, probe, efx->net_dev, | |
567 | "failed to create channel %d\n", | |
568 | channel->channel); | |
569 | goto fail; | |
570 | } | |
571 | } | |
572 | efx_set_channel_names(efx); | |
573 | ||
574 | return 0; | |
575 | ||
576 | fail: | |
577 | efx_remove_channels(efx); | |
578 | return rc; | |
579 | } | |
580 | ||
8ceee660 BH |
581 | /* Channels are shutdown and reinitialised whilst the NIC is running |
582 | * to propagate configuration changes (mtu, checksum offload), or | |
583 | * to clear hardware error conditions | |
584 | */ | |
9f2cb71c | 585 | static void efx_start_datapath(struct efx_nic *efx) |
8ceee660 | 586 | { |
85740cdf | 587 | bool old_rx_scatter = efx->rx_scatter; |
8ceee660 BH |
588 | struct efx_tx_queue *tx_queue; |
589 | struct efx_rx_queue *rx_queue; | |
590 | struct efx_channel *channel; | |
85740cdf | 591 | size_t rx_buf_len; |
8ceee660 | 592 | |
f7f13b0b BH |
593 | /* Calculate the rx buffer allocation parameters required to |
594 | * support the current MTU, including padding for header | |
595 | * alignment and overruns. | |
596 | */ | |
43a3739d | 597 | efx->rx_dma_len = (efx->rx_prefix_size + |
272baeeb BH |
598 | EFX_MAX_FRAME_LEN(efx->net_dev->mtu) + |
599 | efx->type->rx_buffer_padding); | |
85740cdf | 600 | rx_buf_len = (sizeof(struct efx_rx_page_state) + |
2ec03014 | 601 | efx->rx_ip_align + efx->rx_dma_len); |
85740cdf | 602 | if (rx_buf_len <= PAGE_SIZE) { |
e8c68c0a | 603 | efx->rx_scatter = efx->type->always_rx_scatter; |
85740cdf | 604 | efx->rx_buffer_order = 0; |
85740cdf | 605 | } else if (efx->type->can_rx_scatter) { |
950c54df | 606 | BUILD_BUG_ON(EFX_RX_USR_BUF_SIZE % L1_CACHE_BYTES); |
85740cdf | 607 | BUILD_BUG_ON(sizeof(struct efx_rx_page_state) + |
950c54df BH |
608 | 2 * ALIGN(NET_IP_ALIGN + EFX_RX_USR_BUF_SIZE, |
609 | EFX_RX_BUF_ALIGNMENT) > | |
610 | PAGE_SIZE); | |
85740cdf BH |
611 | efx->rx_scatter = true; |
612 | efx->rx_dma_len = EFX_RX_USR_BUF_SIZE; | |
613 | efx->rx_buffer_order = 0; | |
85740cdf BH |
614 | } else { |
615 | efx->rx_scatter = false; | |
616 | efx->rx_buffer_order = get_order(rx_buf_len); | |
85740cdf BH |
617 | } |
618 | ||
1648a23f DP |
619 | efx_rx_config_page_split(efx); |
620 | if (efx->rx_buffer_order) | |
621 | netif_dbg(efx, drv, efx->net_dev, | |
622 | "RX buf len=%u; page order=%u batch=%u\n", | |
623 | efx->rx_dma_len, efx->rx_buffer_order, | |
624 | efx->rx_pages_per_batch); | |
625 | else | |
626 | netif_dbg(efx, drv, efx->net_dev, | |
627 | "RX buf len=%u step=%u bpp=%u; page batch=%u\n", | |
628 | efx->rx_dma_len, efx->rx_page_buf_step, | |
629 | efx->rx_bufs_per_page, efx->rx_pages_per_batch); | |
2768935a | 630 | |
e8c68c0a | 631 | /* RX filters may also have scatter-enabled flags */ |
85740cdf | 632 | if (efx->rx_scatter != old_rx_scatter) |
add72477 | 633 | efx->type->filter_update_rx_scatter(efx); |
8ceee660 | 634 | |
14bf718f BH |
635 | /* We must keep at least one descriptor in a TX ring empty. |
636 | * We could avoid this when the queue size does not exactly | |
637 | * match the hardware ring size, but it's not that important. | |
638 | * Therefore we stop the queue when one more skb might fill | |
639 | * the ring completely. We wake it when half way back to | |
640 | * empty. | |
641 | */ | |
642 | efx->txq_stop_thresh = efx->txq_entries - efx_tx_max_skb_descs(efx); | |
643 | efx->txq_wake_thresh = efx->txq_stop_thresh / 2; | |
644 | ||
8ceee660 BH |
645 | /* Initialise the channels */ |
646 | efx_for_each_channel(channel, efx) { | |
3881d8ab | 647 | efx_for_each_channel_tx_queue(tx_queue, channel) { |
bc3c90a2 | 648 | efx_init_tx_queue(tx_queue); |
3881d8ab AR |
649 | atomic_inc(&efx->active_queues); |
650 | } | |
8ceee660 | 651 | |
9f2cb71c | 652 | efx_for_each_channel_rx_queue(rx_queue, channel) { |
bc3c90a2 | 653 | efx_init_rx_queue(rx_queue); |
3881d8ab | 654 | atomic_inc(&efx->active_queues); |
cce28794 JC |
655 | efx_stop_eventq(channel); |
656 | efx_fast_push_rx_descriptors(rx_queue, false); | |
657 | efx_start_eventq(channel); | |
9f2cb71c | 658 | } |
8ceee660 | 659 | |
85740cdf | 660 | WARN_ON(channel->rx_pkt_n_frags); |
8ceee660 | 661 | } |
8ceee660 | 662 | |
2ea4dc28 AR |
663 | efx_ptp_start_datapath(efx); |
664 | ||
9f2cb71c BH |
665 | if (netif_device_present(efx->net_dev)) |
666 | netif_tx_wake_all_queues(efx->net_dev); | |
8ceee660 BH |
667 | } |
668 | ||
9f2cb71c | 669 | static void efx_stop_datapath(struct efx_nic *efx) |
8ceee660 BH |
670 | { |
671 | struct efx_channel *channel; | |
672 | struct efx_tx_queue *tx_queue; | |
673 | struct efx_rx_queue *rx_queue; | |
6bc5d3a9 | 674 | int rc; |
8ceee660 BH |
675 | |
676 | EFX_ASSERT_RESET_SERIALISED(efx); | |
677 | BUG_ON(efx->port_enabled); | |
678 | ||
2ea4dc28 AR |
679 | efx_ptp_stop_datapath(efx); |
680 | ||
d8aec745 BH |
681 | /* Stop RX refill */ |
682 | efx_for_each_channel(channel, efx) { | |
683 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
684 | rx_queue->refill_enabled = false; | |
685 | } | |
686 | ||
8ceee660 | 687 | efx_for_each_channel(channel, efx) { |
9f2cb71c BH |
688 | /* RX packet processing is pipelined, so wait for the |
689 | * NAPI handler to complete. At least event queue 0 | |
690 | * might be kept active by non-data events, so don't | |
691 | * use napi_synchronize() but actually disable NAPI | |
692 | * temporarily. | |
693 | */ | |
694 | if (efx_channel_has_rx_queue(channel)) { | |
695 | efx_stop_eventq(channel); | |
696 | efx_start_eventq(channel); | |
697 | } | |
e42c3d85 | 698 | } |
8ceee660 | 699 | |
e42c3d85 BH |
700 | rc = efx->type->fini_dmaq(efx); |
701 | if (rc && EFX_WORKAROUND_7803(efx)) { | |
702 | /* Schedule a reset to recover from the flush failure. The | |
703 | * descriptor caches reference memory we're about to free, | |
704 | * but falcon_reconfigure_mac_wrapper() won't reconnect | |
705 | * the MACs because of the pending reset. | |
706 | */ | |
707 | netif_err(efx, drv, efx->net_dev, | |
708 | "Resetting to recover from flush failure\n"); | |
709 | efx_schedule_reset(efx, RESET_TYPE_ALL); | |
710 | } else if (rc) { | |
711 | netif_err(efx, drv, efx->net_dev, "failed to flush queues\n"); | |
712 | } else { | |
713 | netif_dbg(efx, drv, efx->net_dev, | |
714 | "successfully flushed all queues\n"); | |
715 | } | |
716 | ||
717 | efx_for_each_channel(channel, efx) { | |
8ceee660 BH |
718 | efx_for_each_channel_rx_queue(rx_queue, channel) |
719 | efx_fini_rx_queue(rx_queue); | |
94b274bf | 720 | efx_for_each_possible_channel_tx_queue(tx_queue, channel) |
8ceee660 | 721 | efx_fini_tx_queue(tx_queue); |
8ceee660 BH |
722 | } |
723 | } | |
724 | ||
725 | static void efx_remove_channel(struct efx_channel *channel) | |
726 | { | |
727 | struct efx_tx_queue *tx_queue; | |
728 | struct efx_rx_queue *rx_queue; | |
729 | ||
62776d03 BH |
730 | netif_dbg(channel->efx, drv, channel->efx->net_dev, |
731 | "destroy chan %d\n", channel->channel); | |
8ceee660 BH |
732 | |
733 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
734 | efx_remove_rx_queue(rx_queue); | |
94b274bf | 735 | efx_for_each_possible_channel_tx_queue(tx_queue, channel) |
8ceee660 BH |
736 | efx_remove_tx_queue(tx_queue); |
737 | efx_remove_eventq(channel); | |
c31e5f9f | 738 | channel->type->post_remove(channel); |
8ceee660 BH |
739 | } |
740 | ||
4642610c BH |
741 | static void efx_remove_channels(struct efx_nic *efx) |
742 | { | |
743 | struct efx_channel *channel; | |
744 | ||
745 | efx_for_each_channel(channel, efx) | |
746 | efx_remove_channel(channel); | |
747 | } | |
748 | ||
749 | int | |
750 | efx_realloc_channels(struct efx_nic *efx, u32 rxq_entries, u32 txq_entries) | |
751 | { | |
752 | struct efx_channel *other_channel[EFX_MAX_CHANNELS], *channel; | |
753 | u32 old_rxq_entries, old_txq_entries; | |
7f967c01 | 754 | unsigned i, next_buffer_table = 0; |
261e4d96 | 755 | int rc, rc2; |
8b7325b4 BH |
756 | |
757 | rc = efx_check_disabled(efx); | |
758 | if (rc) | |
759 | return rc; | |
7f967c01 BH |
760 | |
761 | /* Not all channels should be reallocated. We must avoid | |
762 | * reallocating their buffer table entries. | |
763 | */ | |
764 | efx_for_each_channel(channel, efx) { | |
765 | struct efx_rx_queue *rx_queue; | |
766 | struct efx_tx_queue *tx_queue; | |
767 | ||
768 | if (channel->type->copy) | |
769 | continue; | |
770 | next_buffer_table = max(next_buffer_table, | |
771 | channel->eventq.index + | |
772 | channel->eventq.entries); | |
773 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
774 | next_buffer_table = max(next_buffer_table, | |
775 | rx_queue->rxd.index + | |
776 | rx_queue->rxd.entries); | |
777 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
778 | next_buffer_table = max(next_buffer_table, | |
779 | tx_queue->txd.index + | |
780 | tx_queue->txd.entries); | |
781 | } | |
4642610c | 782 | |
29c69a48 | 783 | efx_device_detach_sync(efx); |
4642610c | 784 | efx_stop_all(efx); |
d8291187 | 785 | efx_soft_disable_interrupts(efx); |
4642610c | 786 | |
7f967c01 | 787 | /* Clone channels (where possible) */ |
4642610c BH |
788 | memset(other_channel, 0, sizeof(other_channel)); |
789 | for (i = 0; i < efx->n_channels; i++) { | |
7f967c01 BH |
790 | channel = efx->channel[i]; |
791 | if (channel->type->copy) | |
792 | channel = channel->type->copy(channel); | |
4642610c BH |
793 | if (!channel) { |
794 | rc = -ENOMEM; | |
795 | goto out; | |
796 | } | |
797 | other_channel[i] = channel; | |
798 | } | |
799 | ||
800 | /* Swap entry counts and channel pointers */ | |
801 | old_rxq_entries = efx->rxq_entries; | |
802 | old_txq_entries = efx->txq_entries; | |
803 | efx->rxq_entries = rxq_entries; | |
804 | efx->txq_entries = txq_entries; | |
805 | for (i = 0; i < efx->n_channels; i++) { | |
806 | channel = efx->channel[i]; | |
807 | efx->channel[i] = other_channel[i]; | |
808 | other_channel[i] = channel; | |
809 | } | |
810 | ||
7f967c01 BH |
811 | /* Restart buffer table allocation */ |
812 | efx->next_buffer_table = next_buffer_table; | |
e8f14992 | 813 | |
e8f14992 | 814 | for (i = 0; i < efx->n_channels; i++) { |
7f967c01 BH |
815 | channel = efx->channel[i]; |
816 | if (!channel->type->copy) | |
817 | continue; | |
818 | rc = efx_probe_channel(channel); | |
819 | if (rc) | |
820 | goto rollback; | |
821 | efx_init_napi_channel(efx->channel[i]); | |
e8f14992 | 822 | } |
7f967c01 | 823 | |
4642610c | 824 | out: |
7f967c01 BH |
825 | /* Destroy unused channel structures */ |
826 | for (i = 0; i < efx->n_channels; i++) { | |
827 | channel = other_channel[i]; | |
828 | if (channel && channel->type->copy) { | |
829 | efx_fini_napi_channel(channel); | |
830 | efx_remove_channel(channel); | |
831 | kfree(channel); | |
832 | } | |
833 | } | |
4642610c | 834 | |
261e4d96 JC |
835 | rc2 = efx_soft_enable_interrupts(efx); |
836 | if (rc2) { | |
837 | rc = rc ? rc : rc2; | |
838 | netif_err(efx, drv, efx->net_dev, | |
839 | "unable to restart interrupts on channel reallocation\n"); | |
840 | efx_schedule_reset(efx, RESET_TYPE_DISABLE); | |
841 | } else { | |
842 | efx_start_all(efx); | |
843 | netif_device_attach(efx->net_dev); | |
844 | } | |
4642610c BH |
845 | return rc; |
846 | ||
847 | rollback: | |
848 | /* Swap back */ | |
849 | efx->rxq_entries = old_rxq_entries; | |
850 | efx->txq_entries = old_txq_entries; | |
851 | for (i = 0; i < efx->n_channels; i++) { | |
852 | channel = efx->channel[i]; | |
853 | efx->channel[i] = other_channel[i]; | |
854 | other_channel[i] = channel; | |
855 | } | |
856 | goto out; | |
857 | } | |
858 | ||
90d683af | 859 | void efx_schedule_slow_fill(struct efx_rx_queue *rx_queue) |
8ceee660 | 860 | { |
90d683af | 861 | mod_timer(&rx_queue->slow_fill, jiffies + msecs_to_jiffies(100)); |
8ceee660 BH |
862 | } |
863 | ||
7f967c01 BH |
864 | static const struct efx_channel_type efx_default_channel_type = { |
865 | .pre_probe = efx_channel_dummy_op_int, | |
c31e5f9f | 866 | .post_remove = efx_channel_dummy_op_void, |
7f967c01 BH |
867 | .get_name = efx_get_channel_name, |
868 | .copy = efx_copy_channel, | |
869 | .keep_eventq = false, | |
870 | }; | |
871 | ||
872 | int efx_channel_dummy_op_int(struct efx_channel *channel) | |
873 | { | |
874 | return 0; | |
875 | } | |
876 | ||
c31e5f9f SH |
877 | void efx_channel_dummy_op_void(struct efx_channel *channel) |
878 | { | |
879 | } | |
880 | ||
8ceee660 BH |
881 | /************************************************************************** |
882 | * | |
883 | * Port handling | |
884 | * | |
885 | **************************************************************************/ | |
886 | ||
887 | /* This ensures that the kernel is kept informed (via | |
888 | * netif_carrier_on/off) of the link status, and also maintains the | |
889 | * link status's stop on the port's TX queue. | |
890 | */ | |
fdaa9aed | 891 | void efx_link_status_changed(struct efx_nic *efx) |
8ceee660 | 892 | { |
eb50c0d6 BH |
893 | struct efx_link_state *link_state = &efx->link_state; |
894 | ||
8ceee660 BH |
895 | /* SFC Bug 5356: A net_dev notifier is registered, so we must ensure |
896 | * that no events are triggered between unregister_netdev() and the | |
897 | * driver unloading. A more general condition is that NETDEV_CHANGE | |
898 | * can only be generated between NETDEV_UP and NETDEV_DOWN */ | |
899 | if (!netif_running(efx->net_dev)) | |
900 | return; | |
901 | ||
eb50c0d6 | 902 | if (link_state->up != netif_carrier_ok(efx->net_dev)) { |
8ceee660 BH |
903 | efx->n_link_state_changes++; |
904 | ||
eb50c0d6 | 905 | if (link_state->up) |
8ceee660 BH |
906 | netif_carrier_on(efx->net_dev); |
907 | else | |
908 | netif_carrier_off(efx->net_dev); | |
909 | } | |
910 | ||
911 | /* Status message for kernel log */ | |
2aa9ef11 | 912 | if (link_state->up) |
62776d03 | 913 | netif_info(efx, link, efx->net_dev, |
964e6135 | 914 | "link up at %uMbps %s-duplex (MTU %d)\n", |
62776d03 | 915 | link_state->speed, link_state->fd ? "full" : "half", |
964e6135 | 916 | efx->net_dev->mtu); |
2aa9ef11 | 917 | else |
62776d03 | 918 | netif_info(efx, link, efx->net_dev, "link down\n"); |
8ceee660 BH |
919 | } |
920 | ||
d3245b28 BH |
921 | void efx_link_set_advertising(struct efx_nic *efx, u32 advertising) |
922 | { | |
923 | efx->link_advertising = advertising; | |
924 | if (advertising) { | |
925 | if (advertising & ADVERTISED_Pause) | |
926 | efx->wanted_fc |= (EFX_FC_TX | EFX_FC_RX); | |
927 | else | |
928 | efx->wanted_fc &= ~(EFX_FC_TX | EFX_FC_RX); | |
929 | if (advertising & ADVERTISED_Asym_Pause) | |
930 | efx->wanted_fc ^= EFX_FC_TX; | |
931 | } | |
932 | } | |
933 | ||
b5626946 | 934 | void efx_link_set_wanted_fc(struct efx_nic *efx, u8 wanted_fc) |
d3245b28 BH |
935 | { |
936 | efx->wanted_fc = wanted_fc; | |
937 | if (efx->link_advertising) { | |
938 | if (wanted_fc & EFX_FC_RX) | |
939 | efx->link_advertising |= (ADVERTISED_Pause | | |
940 | ADVERTISED_Asym_Pause); | |
941 | else | |
942 | efx->link_advertising &= ~(ADVERTISED_Pause | | |
943 | ADVERTISED_Asym_Pause); | |
944 | if (wanted_fc & EFX_FC_TX) | |
945 | efx->link_advertising ^= ADVERTISED_Asym_Pause; | |
946 | } | |
947 | } | |
948 | ||
115122af BH |
949 | static void efx_fini_port(struct efx_nic *efx); |
950 | ||
d3245b28 BH |
951 | /* Push loopback/power/transmit disable settings to the PHY, and reconfigure |
952 | * the MAC appropriately. All other PHY configuration changes are pushed | |
953 | * through phy_op->set_settings(), and pushed asynchronously to the MAC | |
954 | * through efx_monitor(). | |
955 | * | |
956 | * Callers must hold the mac_lock | |
957 | */ | |
958 | int __efx_reconfigure_port(struct efx_nic *efx) | |
8ceee660 | 959 | { |
d3245b28 BH |
960 | enum efx_phy_mode phy_mode; |
961 | int rc; | |
8ceee660 | 962 | |
d3245b28 | 963 | WARN_ON(!mutex_is_locked(&efx->mac_lock)); |
8ceee660 | 964 | |
d3245b28 BH |
965 | /* Disable PHY transmit in mac level loopbacks */ |
966 | phy_mode = efx->phy_mode; | |
177dfcd8 BH |
967 | if (LOOPBACK_INTERNAL(efx)) |
968 | efx->phy_mode |= PHY_MODE_TX_DISABLED; | |
969 | else | |
970 | efx->phy_mode &= ~PHY_MODE_TX_DISABLED; | |
177dfcd8 | 971 | |
d3245b28 | 972 | rc = efx->type->reconfigure_port(efx); |
8ceee660 | 973 | |
d3245b28 BH |
974 | if (rc) |
975 | efx->phy_mode = phy_mode; | |
177dfcd8 | 976 | |
d3245b28 | 977 | return rc; |
8ceee660 BH |
978 | } |
979 | ||
980 | /* Reinitialise the MAC to pick up new PHY settings, even if the port is | |
981 | * disabled. */ | |
d3245b28 | 982 | int efx_reconfigure_port(struct efx_nic *efx) |
8ceee660 | 983 | { |
d3245b28 BH |
984 | int rc; |
985 | ||
8ceee660 BH |
986 | EFX_ASSERT_RESET_SERIALISED(efx); |
987 | ||
988 | mutex_lock(&efx->mac_lock); | |
d3245b28 | 989 | rc = __efx_reconfigure_port(efx); |
8ceee660 | 990 | mutex_unlock(&efx->mac_lock); |
d3245b28 BH |
991 | |
992 | return rc; | |
8ceee660 BH |
993 | } |
994 | ||
8be4f3e6 BH |
995 | /* Asynchronous work item for changing MAC promiscuity and multicast |
996 | * hash. Avoid a drain/rx_ingress enable by reconfiguring the current | |
997 | * MAC directly. */ | |
766ca0fa BH |
998 | static void efx_mac_work(struct work_struct *data) |
999 | { | |
1000 | struct efx_nic *efx = container_of(data, struct efx_nic, mac_work); | |
1001 | ||
1002 | mutex_lock(&efx->mac_lock); | |
30b81cda | 1003 | if (efx->port_enabled) |
710b208d | 1004 | efx->type->reconfigure_mac(efx); |
766ca0fa BH |
1005 | mutex_unlock(&efx->mac_lock); |
1006 | } | |
1007 | ||
8ceee660 BH |
1008 | static int efx_probe_port(struct efx_nic *efx) |
1009 | { | |
1010 | int rc; | |
1011 | ||
62776d03 | 1012 | netif_dbg(efx, probe, efx->net_dev, "create port\n"); |
8ceee660 | 1013 | |
ff3b00a0 SH |
1014 | if (phy_flash_cfg) |
1015 | efx->phy_mode = PHY_MODE_SPECIAL; | |
1016 | ||
ef2b90ee BH |
1017 | /* Connect up MAC/PHY operations table */ |
1018 | rc = efx->type->probe_port(efx); | |
8ceee660 | 1019 | if (rc) |
e42de262 | 1020 | return rc; |
8ceee660 | 1021 | |
e332bcb3 | 1022 | /* Initialise MAC address to permanent address */ |
cd84ff4d | 1023 | ether_addr_copy(efx->net_dev->dev_addr, efx->net_dev->perm_addr); |
8ceee660 BH |
1024 | |
1025 | return 0; | |
8ceee660 BH |
1026 | } |
1027 | ||
1028 | static int efx_init_port(struct efx_nic *efx) | |
1029 | { | |
1030 | int rc; | |
1031 | ||
62776d03 | 1032 | netif_dbg(efx, drv, efx->net_dev, "init port\n"); |
8ceee660 | 1033 | |
1dfc5cea BH |
1034 | mutex_lock(&efx->mac_lock); |
1035 | ||
177dfcd8 | 1036 | rc = efx->phy_op->init(efx); |
8ceee660 | 1037 | if (rc) |
1dfc5cea | 1038 | goto fail1; |
8ceee660 | 1039 | |
dc8cfa55 | 1040 | efx->port_initialized = true; |
1dfc5cea | 1041 | |
d3245b28 BH |
1042 | /* Reconfigure the MAC before creating dma queues (required for |
1043 | * Falcon/A1 where RX_INGR_EN/TX_DRAIN_EN isn't supported) */ | |
710b208d | 1044 | efx->type->reconfigure_mac(efx); |
d3245b28 BH |
1045 | |
1046 | /* Ensure the PHY advertises the correct flow control settings */ | |
1047 | rc = efx->phy_op->reconfigure(efx); | |
1048 | if (rc) | |
1049 | goto fail2; | |
1050 | ||
1dfc5cea | 1051 | mutex_unlock(&efx->mac_lock); |
8ceee660 | 1052 | return 0; |
177dfcd8 | 1053 | |
1dfc5cea | 1054 | fail2: |
177dfcd8 | 1055 | efx->phy_op->fini(efx); |
1dfc5cea BH |
1056 | fail1: |
1057 | mutex_unlock(&efx->mac_lock); | |
177dfcd8 | 1058 | return rc; |
8ceee660 BH |
1059 | } |
1060 | ||
8ceee660 BH |
1061 | static void efx_start_port(struct efx_nic *efx) |
1062 | { | |
62776d03 | 1063 | netif_dbg(efx, ifup, efx->net_dev, "start port\n"); |
8ceee660 BH |
1064 | BUG_ON(efx->port_enabled); |
1065 | ||
1066 | mutex_lock(&efx->mac_lock); | |
dc8cfa55 | 1067 | efx->port_enabled = true; |
8be4f3e6 | 1068 | |
d615c039 | 1069 | /* Ensure MAC ingress/egress is enabled */ |
710b208d | 1070 | efx->type->reconfigure_mac(efx); |
8be4f3e6 | 1071 | |
8ceee660 BH |
1072 | mutex_unlock(&efx->mac_lock); |
1073 | } | |
1074 | ||
d615c039 BH |
1075 | /* Cancel work for MAC reconfiguration, periodic hardware monitoring |
1076 | * and the async self-test, wait for them to finish and prevent them | |
1077 | * being scheduled again. This doesn't cover online resets, which | |
1078 | * should only be cancelled when removing the device. | |
1079 | */ | |
8ceee660 BH |
1080 | static void efx_stop_port(struct efx_nic *efx) |
1081 | { | |
62776d03 | 1082 | netif_dbg(efx, ifdown, efx->net_dev, "stop port\n"); |
8ceee660 | 1083 | |
d615c039 BH |
1084 | EFX_ASSERT_RESET_SERIALISED(efx); |
1085 | ||
8ceee660 | 1086 | mutex_lock(&efx->mac_lock); |
dc8cfa55 | 1087 | efx->port_enabled = false; |
8ceee660 BH |
1088 | mutex_unlock(&efx->mac_lock); |
1089 | ||
1090 | /* Serialise against efx_set_multicast_list() */ | |
73ba7b68 BH |
1091 | netif_addr_lock_bh(efx->net_dev); |
1092 | netif_addr_unlock_bh(efx->net_dev); | |
d615c039 BH |
1093 | |
1094 | cancel_delayed_work_sync(&efx->monitor_work); | |
1095 | efx_selftest_async_cancel(efx); | |
1096 | cancel_work_sync(&efx->mac_work); | |
8ceee660 BH |
1097 | } |
1098 | ||
1099 | static void efx_fini_port(struct efx_nic *efx) | |
1100 | { | |
62776d03 | 1101 | netif_dbg(efx, drv, efx->net_dev, "shut down port\n"); |
8ceee660 BH |
1102 | |
1103 | if (!efx->port_initialized) | |
1104 | return; | |
1105 | ||
177dfcd8 | 1106 | efx->phy_op->fini(efx); |
dc8cfa55 | 1107 | efx->port_initialized = false; |
8ceee660 | 1108 | |
eb50c0d6 | 1109 | efx->link_state.up = false; |
8ceee660 BH |
1110 | efx_link_status_changed(efx); |
1111 | } | |
1112 | ||
1113 | static void efx_remove_port(struct efx_nic *efx) | |
1114 | { | |
62776d03 | 1115 | netif_dbg(efx, drv, efx->net_dev, "destroying port\n"); |
8ceee660 | 1116 | |
ef2b90ee | 1117 | efx->type->remove_port(efx); |
8ceee660 BH |
1118 | } |
1119 | ||
1120 | /************************************************************************** | |
1121 | * | |
1122 | * NIC handling | |
1123 | * | |
1124 | **************************************************************************/ | |
1125 | ||
0bcf4a64 BH |
1126 | static LIST_HEAD(efx_primary_list); |
1127 | static LIST_HEAD(efx_unassociated_list); | |
1128 | ||
1129 | static bool efx_same_controller(struct efx_nic *left, struct efx_nic *right) | |
1130 | { | |
1131 | return left->type == right->type && | |
1132 | left->vpd_sn && right->vpd_sn && | |
1133 | !strcmp(left->vpd_sn, right->vpd_sn); | |
1134 | } | |
1135 | ||
1136 | static void efx_associate(struct efx_nic *efx) | |
1137 | { | |
1138 | struct efx_nic *other, *next; | |
1139 | ||
1140 | if (efx->primary == efx) { | |
1141 | /* Adding primary function; look for secondaries */ | |
1142 | ||
1143 | netif_dbg(efx, probe, efx->net_dev, "adding to primary list\n"); | |
1144 | list_add_tail(&efx->node, &efx_primary_list); | |
1145 | ||
1146 | list_for_each_entry_safe(other, next, &efx_unassociated_list, | |
1147 | node) { | |
1148 | if (efx_same_controller(efx, other)) { | |
1149 | list_del(&other->node); | |
1150 | netif_dbg(other, probe, other->net_dev, | |
1151 | "moving to secondary list of %s %s\n", | |
1152 | pci_name(efx->pci_dev), | |
1153 | efx->net_dev->name); | |
1154 | list_add_tail(&other->node, | |
1155 | &efx->secondary_list); | |
1156 | other->primary = efx; | |
1157 | } | |
1158 | } | |
1159 | } else { | |
1160 | /* Adding secondary function; look for primary */ | |
1161 | ||
1162 | list_for_each_entry(other, &efx_primary_list, node) { | |
1163 | if (efx_same_controller(efx, other)) { | |
1164 | netif_dbg(efx, probe, efx->net_dev, | |
1165 | "adding to secondary list of %s %s\n", | |
1166 | pci_name(other->pci_dev), | |
1167 | other->net_dev->name); | |
1168 | list_add_tail(&efx->node, | |
1169 | &other->secondary_list); | |
1170 | efx->primary = other; | |
1171 | return; | |
1172 | } | |
1173 | } | |
1174 | ||
1175 | netif_dbg(efx, probe, efx->net_dev, | |
1176 | "adding to unassociated list\n"); | |
1177 | list_add_tail(&efx->node, &efx_unassociated_list); | |
1178 | } | |
1179 | } | |
1180 | ||
1181 | static void efx_dissociate(struct efx_nic *efx) | |
1182 | { | |
1183 | struct efx_nic *other, *next; | |
1184 | ||
1185 | list_del(&efx->node); | |
1186 | efx->primary = NULL; | |
1187 | ||
1188 | list_for_each_entry_safe(other, next, &efx->secondary_list, node) { | |
1189 | list_del(&other->node); | |
1190 | netif_dbg(other, probe, other->net_dev, | |
1191 | "moving to unassociated list\n"); | |
1192 | list_add_tail(&other->node, &efx_unassociated_list); | |
1193 | other->primary = NULL; | |
1194 | } | |
1195 | } | |
1196 | ||
8ceee660 BH |
1197 | /* This configures the PCI device to enable I/O and DMA. */ |
1198 | static int efx_init_io(struct efx_nic *efx) | |
1199 | { | |
1200 | struct pci_dev *pci_dev = efx->pci_dev; | |
1201 | dma_addr_t dma_mask = efx->type->max_dma_mask; | |
b105798f | 1202 | unsigned int mem_map_size = efx->type->mem_map_size(efx); |
8ceee660 BH |
1203 | int rc; |
1204 | ||
62776d03 | 1205 | netif_dbg(efx, probe, efx->net_dev, "initialising I/O\n"); |
8ceee660 BH |
1206 | |
1207 | rc = pci_enable_device(pci_dev); | |
1208 | if (rc) { | |
62776d03 BH |
1209 | netif_err(efx, probe, efx->net_dev, |
1210 | "failed to enable PCI device\n"); | |
8ceee660 BH |
1211 | goto fail1; |
1212 | } | |
1213 | ||
1214 | pci_set_master(pci_dev); | |
1215 | ||
1216 | /* Set the PCI DMA mask. Try all possibilities from our | |
1217 | * genuine mask down to 32 bits, because some architectures | |
1218 | * (e.g. x86_64 with iommu_sac_force set) will allow 40 bit | |
1219 | * masks event though they reject 46 bit masks. | |
1220 | */ | |
1221 | while (dma_mask > 0x7fffffffUL) { | |
0e33d870 | 1222 | if (dma_supported(&pci_dev->dev, dma_mask)) { |
9663deda | 1223 | rc = dma_set_mask_and_coherent(&pci_dev->dev, dma_mask); |
e9e01846 BH |
1224 | if (rc == 0) |
1225 | break; | |
1226 | } | |
8ceee660 BH |
1227 | dma_mask >>= 1; |
1228 | } | |
1229 | if (rc) { | |
62776d03 BH |
1230 | netif_err(efx, probe, efx->net_dev, |
1231 | "could not find a suitable DMA mask\n"); | |
8ceee660 BH |
1232 | goto fail2; |
1233 | } | |
62776d03 BH |
1234 | netif_dbg(efx, probe, efx->net_dev, |
1235 | "using DMA mask %llx\n", (unsigned long long) dma_mask); | |
8ceee660 | 1236 | |
dc803df8 BH |
1237 | efx->membase_phys = pci_resource_start(efx->pci_dev, EFX_MEM_BAR); |
1238 | rc = pci_request_region(pci_dev, EFX_MEM_BAR, "sfc"); | |
8ceee660 | 1239 | if (rc) { |
62776d03 BH |
1240 | netif_err(efx, probe, efx->net_dev, |
1241 | "request for memory BAR failed\n"); | |
8ceee660 BH |
1242 | rc = -EIO; |
1243 | goto fail3; | |
1244 | } | |
b105798f | 1245 | efx->membase = ioremap_nocache(efx->membase_phys, mem_map_size); |
8ceee660 | 1246 | if (!efx->membase) { |
62776d03 BH |
1247 | netif_err(efx, probe, efx->net_dev, |
1248 | "could not map memory BAR at %llx+%x\n", | |
b105798f | 1249 | (unsigned long long)efx->membase_phys, mem_map_size); |
8ceee660 BH |
1250 | rc = -ENOMEM; |
1251 | goto fail4; | |
1252 | } | |
62776d03 BH |
1253 | netif_dbg(efx, probe, efx->net_dev, |
1254 | "memory BAR at %llx+%x (virtual %p)\n", | |
b105798f BH |
1255 | (unsigned long long)efx->membase_phys, mem_map_size, |
1256 | efx->membase); | |
8ceee660 BH |
1257 | |
1258 | return 0; | |
1259 | ||
1260 | fail4: | |
dc803df8 | 1261 | pci_release_region(efx->pci_dev, EFX_MEM_BAR); |
8ceee660 | 1262 | fail3: |
2c118e0f | 1263 | efx->membase_phys = 0; |
8ceee660 BH |
1264 | fail2: |
1265 | pci_disable_device(efx->pci_dev); | |
1266 | fail1: | |
1267 | return rc; | |
1268 | } | |
1269 | ||
1270 | static void efx_fini_io(struct efx_nic *efx) | |
1271 | { | |
62776d03 | 1272 | netif_dbg(efx, drv, efx->net_dev, "shutting down I/O\n"); |
8ceee660 BH |
1273 | |
1274 | if (efx->membase) { | |
1275 | iounmap(efx->membase); | |
1276 | efx->membase = NULL; | |
1277 | } | |
1278 | ||
1279 | if (efx->membase_phys) { | |
dc803df8 | 1280 | pci_release_region(efx->pci_dev, EFX_MEM_BAR); |
2c118e0f | 1281 | efx->membase_phys = 0; |
8ceee660 BH |
1282 | } |
1283 | ||
1284 | pci_disable_device(efx->pci_dev); | |
1285 | } | |
1286 | ||
a9a52506 | 1287 | static unsigned int efx_wanted_parallelism(struct efx_nic *efx) |
46123d04 | 1288 | { |
cdb08f8f | 1289 | cpumask_var_t thread_mask; |
a16e5b24 | 1290 | unsigned int count; |
46123d04 | 1291 | int cpu; |
5b874e25 | 1292 | |
cd2d5b52 BH |
1293 | if (rss_cpus) { |
1294 | count = rss_cpus; | |
1295 | } else { | |
1296 | if (unlikely(!zalloc_cpumask_var(&thread_mask, GFP_KERNEL))) { | |
1297 | netif_warn(efx, probe, efx->net_dev, | |
1298 | "RSS disabled due to allocation failure\n"); | |
1299 | return 1; | |
1300 | } | |
46123d04 | 1301 | |
cd2d5b52 BH |
1302 | count = 0; |
1303 | for_each_online_cpu(cpu) { | |
1304 | if (!cpumask_test_cpu(cpu, thread_mask)) { | |
1305 | ++count; | |
1306 | cpumask_or(thread_mask, thread_mask, | |
1307 | topology_thread_cpumask(cpu)); | |
1308 | } | |
1309 | } | |
1310 | ||
1311 | free_cpumask_var(thread_mask); | |
2f8975fb RR |
1312 | } |
1313 | ||
cd2d5b52 BH |
1314 | /* If RSS is requested for the PF *and* VFs then we can't write RSS |
1315 | * table entries that are inaccessible to VFs | |
1316 | */ | |
1317 | if (efx_sriov_wanted(efx) && efx_vf_size(efx) > 1 && | |
1318 | count > efx_vf_size(efx)) { | |
1319 | netif_warn(efx, probe, efx->net_dev, | |
1320 | "Reducing number of RSS channels from %u to %u for " | |
1321 | "VF support. Increase vf-msix-limit to use more " | |
1322 | "channels on the PF.\n", | |
1323 | count, efx_vf_size(efx)); | |
1324 | count = efx_vf_size(efx); | |
46123d04 BH |
1325 | } |
1326 | ||
1327 | return count; | |
1328 | } | |
1329 | ||
1330 | /* Probe the number and type of interrupts we are able to obtain, and | |
1331 | * the resulting numbers of channels and RX queues. | |
1332 | */ | |
64d8ad6d | 1333 | static int efx_probe_interrupts(struct efx_nic *efx) |
8ceee660 | 1334 | { |
7f967c01 BH |
1335 | unsigned int extra_channels = 0; |
1336 | unsigned int i, j; | |
a16e5b24 | 1337 | int rc; |
8ceee660 | 1338 | |
7f967c01 BH |
1339 | for (i = 0; i < EFX_MAX_EXTRA_CHANNELS; i++) |
1340 | if (efx->extra_channel_type[i]) | |
1341 | ++extra_channels; | |
1342 | ||
8ceee660 | 1343 | if (efx->interrupt_mode == EFX_INT_MODE_MSIX) { |
46123d04 | 1344 | struct msix_entry xentries[EFX_MAX_CHANNELS]; |
a16e5b24 | 1345 | unsigned int n_channels; |
aa6ef27e | 1346 | |
a9a52506 | 1347 | n_channels = efx_wanted_parallelism(efx); |
a4900ac9 BH |
1348 | if (separate_tx_channels) |
1349 | n_channels *= 2; | |
7f967c01 | 1350 | n_channels += extra_channels; |
b105798f | 1351 | n_channels = min(n_channels, efx->max_channels); |
8ceee660 | 1352 | |
a4900ac9 | 1353 | for (i = 0; i < n_channels; i++) |
8ceee660 | 1354 | xentries[i].entry = i; |
184603d8 AG |
1355 | rc = pci_enable_msix_range(efx->pci_dev, |
1356 | xentries, 1, n_channels); | |
1357 | if (rc < 0) { | |
1358 | /* Fall back to single channel MSI */ | |
1359 | efx->interrupt_mode = EFX_INT_MODE_MSI; | |
1360 | netif_err(efx, drv, efx->net_dev, | |
1361 | "could not enable MSI-X\n"); | |
1362 | } else if (rc < n_channels) { | |
62776d03 BH |
1363 | netif_err(efx, drv, efx->net_dev, |
1364 | "WARNING: Insufficient MSI-X vectors" | |
a16e5b24 | 1365 | " available (%d < %u).\n", rc, n_channels); |
62776d03 BH |
1366 | netif_err(efx, drv, efx->net_dev, |
1367 | "WARNING: Performance may be reduced.\n"); | |
a4900ac9 | 1368 | n_channels = rc; |
8ceee660 BH |
1369 | } |
1370 | ||
184603d8 | 1371 | if (rc > 0) { |
a4900ac9 | 1372 | efx->n_channels = n_channels; |
7f967c01 BH |
1373 | if (n_channels > extra_channels) |
1374 | n_channels -= extra_channels; | |
a4900ac9 | 1375 | if (separate_tx_channels) { |
7f967c01 BH |
1376 | efx->n_tx_channels = max(n_channels / 2, 1U); |
1377 | efx->n_rx_channels = max(n_channels - | |
1378 | efx->n_tx_channels, | |
1379 | 1U); | |
a4900ac9 | 1380 | } else { |
7f967c01 BH |
1381 | efx->n_tx_channels = n_channels; |
1382 | efx->n_rx_channels = n_channels; | |
a4900ac9 | 1383 | } |
7f967c01 | 1384 | for (i = 0; i < efx->n_channels; i++) |
f7d12cdc BH |
1385 | efx_get_channel(efx, i)->irq = |
1386 | xentries[i].vector; | |
8ceee660 BH |
1387 | } |
1388 | } | |
1389 | ||
1390 | /* Try single interrupt MSI */ | |
1391 | if (efx->interrupt_mode == EFX_INT_MODE_MSI) { | |
28b581ab | 1392 | efx->n_channels = 1; |
a4900ac9 BH |
1393 | efx->n_rx_channels = 1; |
1394 | efx->n_tx_channels = 1; | |
8ceee660 BH |
1395 | rc = pci_enable_msi(efx->pci_dev); |
1396 | if (rc == 0) { | |
f7d12cdc | 1397 | efx_get_channel(efx, 0)->irq = efx->pci_dev->irq; |
8ceee660 | 1398 | } else { |
62776d03 BH |
1399 | netif_err(efx, drv, efx->net_dev, |
1400 | "could not enable MSI\n"); | |
8ceee660 BH |
1401 | efx->interrupt_mode = EFX_INT_MODE_LEGACY; |
1402 | } | |
1403 | } | |
1404 | ||
1405 | /* Assume legacy interrupts */ | |
1406 | if (efx->interrupt_mode == EFX_INT_MODE_LEGACY) { | |
28b581ab | 1407 | efx->n_channels = 1 + (separate_tx_channels ? 1 : 0); |
a4900ac9 BH |
1408 | efx->n_rx_channels = 1; |
1409 | efx->n_tx_channels = 1; | |
8ceee660 BH |
1410 | efx->legacy_irq = efx->pci_dev->irq; |
1411 | } | |
64d8ad6d | 1412 | |
7f967c01 BH |
1413 | /* Assign extra channels if possible */ |
1414 | j = efx->n_channels; | |
1415 | for (i = 0; i < EFX_MAX_EXTRA_CHANNELS; i++) { | |
1416 | if (!efx->extra_channel_type[i]) | |
1417 | continue; | |
1418 | if (efx->interrupt_mode != EFX_INT_MODE_MSIX || | |
1419 | efx->n_channels <= extra_channels) { | |
1420 | efx->extra_channel_type[i]->handle_no_channel(efx); | |
1421 | } else { | |
1422 | --j; | |
1423 | efx_get_channel(efx, j)->type = | |
1424 | efx->extra_channel_type[i]; | |
1425 | } | |
1426 | } | |
1427 | ||
cd2d5b52 | 1428 | /* RSS might be usable on VFs even if it is disabled on the PF */ |
3132d282 | 1429 | efx->rss_spread = ((efx->n_rx_channels > 1 || !efx_sriov_wanted(efx)) ? |
cd2d5b52 BH |
1430 | efx->n_rx_channels : efx_vf_size(efx)); |
1431 | ||
64d8ad6d | 1432 | return 0; |
8ceee660 BH |
1433 | } |
1434 | ||
261e4d96 | 1435 | static int efx_soft_enable_interrupts(struct efx_nic *efx) |
9f2cb71c | 1436 | { |
261e4d96 JC |
1437 | struct efx_channel *channel, *end_channel; |
1438 | int rc; | |
9f2cb71c | 1439 | |
8b7325b4 BH |
1440 | BUG_ON(efx->state == STATE_DISABLED); |
1441 | ||
d8291187 BH |
1442 | efx->irq_soft_enabled = true; |
1443 | smp_wmb(); | |
9f2cb71c BH |
1444 | |
1445 | efx_for_each_channel(channel, efx) { | |
261e4d96 JC |
1446 | if (!channel->type->keep_eventq) { |
1447 | rc = efx_init_eventq(channel); | |
1448 | if (rc) | |
1449 | goto fail; | |
1450 | } | |
9f2cb71c BH |
1451 | efx_start_eventq(channel); |
1452 | } | |
1453 | ||
1454 | efx_mcdi_mode_event(efx); | |
261e4d96 JC |
1455 | |
1456 | return 0; | |
1457 | fail: | |
1458 | end_channel = channel; | |
1459 | efx_for_each_channel(channel, efx) { | |
1460 | if (channel == end_channel) | |
1461 | break; | |
1462 | efx_stop_eventq(channel); | |
1463 | if (!channel->type->keep_eventq) | |
1464 | efx_fini_eventq(channel); | |
1465 | } | |
1466 | ||
1467 | return rc; | |
9f2cb71c BH |
1468 | } |
1469 | ||
d8291187 | 1470 | static void efx_soft_disable_interrupts(struct efx_nic *efx) |
9f2cb71c BH |
1471 | { |
1472 | struct efx_channel *channel; | |
1473 | ||
8b7325b4 BH |
1474 | if (efx->state == STATE_DISABLED) |
1475 | return; | |
1476 | ||
9f2cb71c BH |
1477 | efx_mcdi_mode_poll(efx); |
1478 | ||
d8291187 BH |
1479 | efx->irq_soft_enabled = false; |
1480 | smp_wmb(); | |
1481 | ||
1482 | if (efx->legacy_irq) | |
9f2cb71c | 1483 | synchronize_irq(efx->legacy_irq); |
9f2cb71c BH |
1484 | |
1485 | efx_for_each_channel(channel, efx) { | |
1486 | if (channel->irq) | |
1487 | synchronize_irq(channel->irq); | |
1488 | ||
1489 | efx_stop_eventq(channel); | |
d8291187 | 1490 | if (!channel->type->keep_eventq) |
7f967c01 | 1491 | efx_fini_eventq(channel); |
9f2cb71c | 1492 | } |
cade715f BH |
1493 | |
1494 | /* Flush the asynchronous MCDI request queue */ | |
1495 | efx_mcdi_flush_async(efx); | |
9f2cb71c BH |
1496 | } |
1497 | ||
261e4d96 | 1498 | static int efx_enable_interrupts(struct efx_nic *efx) |
d8291187 | 1499 | { |
261e4d96 JC |
1500 | struct efx_channel *channel, *end_channel; |
1501 | int rc; | |
d8291187 BH |
1502 | |
1503 | BUG_ON(efx->state == STATE_DISABLED); | |
1504 | ||
1505 | if (efx->eeh_disabled_legacy_irq) { | |
1506 | enable_irq(efx->legacy_irq); | |
1507 | efx->eeh_disabled_legacy_irq = false; | |
1508 | } | |
1509 | ||
86094f7f | 1510 | efx->type->irq_enable_master(efx); |
d8291187 BH |
1511 | |
1512 | efx_for_each_channel(channel, efx) { | |
261e4d96 JC |
1513 | if (channel->type->keep_eventq) { |
1514 | rc = efx_init_eventq(channel); | |
1515 | if (rc) | |
1516 | goto fail; | |
1517 | } | |
1518 | } | |
1519 | ||
1520 | rc = efx_soft_enable_interrupts(efx); | |
1521 | if (rc) | |
1522 | goto fail; | |
1523 | ||
1524 | return 0; | |
1525 | ||
1526 | fail: | |
1527 | end_channel = channel; | |
1528 | efx_for_each_channel(channel, efx) { | |
1529 | if (channel == end_channel) | |
1530 | break; | |
d8291187 | 1531 | if (channel->type->keep_eventq) |
261e4d96 | 1532 | efx_fini_eventq(channel); |
d8291187 BH |
1533 | } |
1534 | ||
261e4d96 JC |
1535 | efx->type->irq_disable_non_ev(efx); |
1536 | ||
1537 | return rc; | |
d8291187 BH |
1538 | } |
1539 | ||
1540 | static void efx_disable_interrupts(struct efx_nic *efx) | |
1541 | { | |
1542 | struct efx_channel *channel; | |
1543 | ||
1544 | efx_soft_disable_interrupts(efx); | |
1545 | ||
1546 | efx_for_each_channel(channel, efx) { | |
1547 | if (channel->type->keep_eventq) | |
1548 | efx_fini_eventq(channel); | |
1549 | } | |
1550 | ||
86094f7f | 1551 | efx->type->irq_disable_non_ev(efx); |
d8291187 BH |
1552 | } |
1553 | ||
8ceee660 BH |
1554 | static void efx_remove_interrupts(struct efx_nic *efx) |
1555 | { | |
1556 | struct efx_channel *channel; | |
1557 | ||
1558 | /* Remove MSI/MSI-X interrupts */ | |
64ee3120 | 1559 | efx_for_each_channel(channel, efx) |
8ceee660 BH |
1560 | channel->irq = 0; |
1561 | pci_disable_msi(efx->pci_dev); | |
1562 | pci_disable_msix(efx->pci_dev); | |
1563 | ||
1564 | /* Remove legacy interrupt */ | |
1565 | efx->legacy_irq = 0; | |
1566 | } | |
1567 | ||
8831da7b | 1568 | static void efx_set_channels(struct efx_nic *efx) |
8ceee660 | 1569 | { |
602a5322 BH |
1570 | struct efx_channel *channel; |
1571 | struct efx_tx_queue *tx_queue; | |
1572 | ||
97653431 | 1573 | efx->tx_channel_offset = |
a4900ac9 | 1574 | separate_tx_channels ? efx->n_channels - efx->n_tx_channels : 0; |
602a5322 | 1575 | |
79d68b37 SH |
1576 | /* We need to mark which channels really have RX and TX |
1577 | * queues, and adjust the TX queue numbers if we have separate | |
602a5322 BH |
1578 | * RX-only and TX-only channels. |
1579 | */ | |
1580 | efx_for_each_channel(channel, efx) { | |
79d68b37 SH |
1581 | if (channel->channel < efx->n_rx_channels) |
1582 | channel->rx_queue.core_index = channel->channel; | |
1583 | else | |
1584 | channel->rx_queue.core_index = -1; | |
1585 | ||
602a5322 BH |
1586 | efx_for_each_channel_tx_queue(tx_queue, channel) |
1587 | tx_queue->queue -= (efx->tx_channel_offset * | |
1588 | EFX_TXQ_TYPES); | |
1589 | } | |
8ceee660 BH |
1590 | } |
1591 | ||
1592 | static int efx_probe_nic(struct efx_nic *efx) | |
1593 | { | |
765c9f46 | 1594 | size_t i; |
8ceee660 BH |
1595 | int rc; |
1596 | ||
62776d03 | 1597 | netif_dbg(efx, probe, efx->net_dev, "creating NIC\n"); |
8ceee660 BH |
1598 | |
1599 | /* Carry out hardware-type specific initialisation */ | |
ef2b90ee | 1600 | rc = efx->type->probe(efx); |
8ceee660 BH |
1601 | if (rc) |
1602 | return rc; | |
1603 | ||
a4900ac9 | 1604 | /* Determine the number of channels and queues by trying to hook |
8ceee660 | 1605 | * in MSI-X interrupts. */ |
64d8ad6d BH |
1606 | rc = efx_probe_interrupts(efx); |
1607 | if (rc) | |
c15eed22 | 1608 | goto fail1; |
8ceee660 | 1609 | |
52ad762b DP |
1610 | efx_set_channels(efx); |
1611 | ||
c15eed22 BH |
1612 | rc = efx->type->dimension_resources(efx); |
1613 | if (rc) | |
1614 | goto fail2; | |
28e47c49 | 1615 | |
5d3a6fca BH |
1616 | if (efx->n_channels > 1) |
1617 | get_random_bytes(&efx->rx_hash_key, sizeof(efx->rx_hash_key)); | |
765c9f46 | 1618 | for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); i++) |
278bc429 | 1619 | efx->rx_indir_table[i] = |
cd2d5b52 | 1620 | ethtool_rxfh_indir_default(i, efx->rss_spread); |
5d3a6fca | 1621 | |
c4f4adc7 BH |
1622 | netif_set_real_num_tx_queues(efx->net_dev, efx->n_tx_channels); |
1623 | netif_set_real_num_rx_queues(efx->net_dev, efx->n_rx_channels); | |
8ceee660 BH |
1624 | |
1625 | /* Initialise the interrupt moderation settings */ | |
9e393b30 BH |
1626 | efx_init_irq_moderation(efx, tx_irq_mod_usec, rx_irq_mod_usec, true, |
1627 | true); | |
8ceee660 BH |
1628 | |
1629 | return 0; | |
64d8ad6d | 1630 | |
c15eed22 BH |
1631 | fail2: |
1632 | efx_remove_interrupts(efx); | |
1633 | fail1: | |
64d8ad6d BH |
1634 | efx->type->remove(efx); |
1635 | return rc; | |
8ceee660 BH |
1636 | } |
1637 | ||
1638 | static void efx_remove_nic(struct efx_nic *efx) | |
1639 | { | |
62776d03 | 1640 | netif_dbg(efx, drv, efx->net_dev, "destroying NIC\n"); |
8ceee660 BH |
1641 | |
1642 | efx_remove_interrupts(efx); | |
ef2b90ee | 1643 | efx->type->remove(efx); |
8ceee660 BH |
1644 | } |
1645 | ||
add72477 BH |
1646 | static int efx_probe_filters(struct efx_nic *efx) |
1647 | { | |
1648 | int rc; | |
1649 | ||
1650 | spin_lock_init(&efx->filter_lock); | |
1651 | ||
1652 | rc = efx->type->filter_table_probe(efx); | |
1653 | if (rc) | |
1654 | return rc; | |
1655 | ||
1656 | #ifdef CONFIG_RFS_ACCEL | |
1657 | if (efx->type->offload_features & NETIF_F_NTUPLE) { | |
1658 | efx->rps_flow_id = kcalloc(efx->type->max_rx_ip_filters, | |
1659 | sizeof(*efx->rps_flow_id), | |
1660 | GFP_KERNEL); | |
1661 | if (!efx->rps_flow_id) { | |
1662 | efx->type->filter_table_remove(efx); | |
1663 | return -ENOMEM; | |
1664 | } | |
1665 | } | |
1666 | #endif | |
1667 | ||
1668 | return 0; | |
1669 | } | |
1670 | ||
1671 | static void efx_remove_filters(struct efx_nic *efx) | |
1672 | { | |
1673 | #ifdef CONFIG_RFS_ACCEL | |
1674 | kfree(efx->rps_flow_id); | |
1675 | #endif | |
1676 | efx->type->filter_table_remove(efx); | |
1677 | } | |
1678 | ||
1679 | static void efx_restore_filters(struct efx_nic *efx) | |
1680 | { | |
1681 | efx->type->filter_table_restore(efx); | |
1682 | } | |
1683 | ||
8ceee660 BH |
1684 | /************************************************************************** |
1685 | * | |
1686 | * NIC startup/shutdown | |
1687 | * | |
1688 | *************************************************************************/ | |
1689 | ||
1690 | static int efx_probe_all(struct efx_nic *efx) | |
1691 | { | |
8ceee660 BH |
1692 | int rc; |
1693 | ||
8ceee660 BH |
1694 | rc = efx_probe_nic(efx); |
1695 | if (rc) { | |
62776d03 | 1696 | netif_err(efx, probe, efx->net_dev, "failed to create NIC\n"); |
8ceee660 BH |
1697 | goto fail1; |
1698 | } | |
1699 | ||
8ceee660 BH |
1700 | rc = efx_probe_port(efx); |
1701 | if (rc) { | |
62776d03 | 1702 | netif_err(efx, probe, efx->net_dev, "failed to create port\n"); |
8ceee660 BH |
1703 | goto fail2; |
1704 | } | |
1705 | ||
7e6d06f0 BH |
1706 | BUILD_BUG_ON(EFX_DEFAULT_DMAQ_SIZE < EFX_RXQ_MIN_ENT); |
1707 | if (WARN_ON(EFX_DEFAULT_DMAQ_SIZE < EFX_TXQ_MIN_ENT(efx))) { | |
1708 | rc = -EINVAL; | |
1709 | goto fail3; | |
1710 | } | |
ecc910f5 | 1711 | efx->rxq_entries = efx->txq_entries = EFX_DEFAULT_DMAQ_SIZE; |
8ceee660 | 1712 | |
64eebcfd BH |
1713 | rc = efx_probe_filters(efx); |
1714 | if (rc) { | |
1715 | netif_err(efx, probe, efx->net_dev, | |
1716 | "failed to create filter tables\n"); | |
7f967c01 | 1717 | goto fail3; |
64eebcfd BH |
1718 | } |
1719 | ||
7f967c01 BH |
1720 | rc = efx_probe_channels(efx); |
1721 | if (rc) | |
1722 | goto fail4; | |
1723 | ||
8ceee660 BH |
1724 | return 0; |
1725 | ||
64eebcfd | 1726 | fail4: |
7f967c01 | 1727 | efx_remove_filters(efx); |
8ceee660 | 1728 | fail3: |
8ceee660 BH |
1729 | efx_remove_port(efx); |
1730 | fail2: | |
1731 | efx_remove_nic(efx); | |
1732 | fail1: | |
1733 | return rc; | |
1734 | } | |
1735 | ||
8b7325b4 BH |
1736 | /* If the interface is supposed to be running but is not, start |
1737 | * the hardware and software data path, regular activity for the port | |
1738 | * (MAC statistics, link polling, etc.) and schedule the port to be | |
1739 | * reconfigured. Interrupts must already be enabled. This function | |
1740 | * is safe to call multiple times, so long as the NIC is not disabled. | |
1741 | * Requires the RTNL lock. | |
9f2cb71c | 1742 | */ |
8ceee660 BH |
1743 | static void efx_start_all(struct efx_nic *efx) |
1744 | { | |
8ceee660 | 1745 | EFX_ASSERT_RESET_SERIALISED(efx); |
8b7325b4 | 1746 | BUG_ON(efx->state == STATE_DISABLED); |
8ceee660 BH |
1747 | |
1748 | /* Check that it is appropriate to restart the interface. All | |
1749 | * of these flags are safe to read under just the rtnl lock */ | |
e283546c EC |
1750 | if (efx->port_enabled || !netif_running(efx->net_dev) || |
1751 | efx->reset_pending) | |
8ceee660 BH |
1752 | return; |
1753 | ||
8ceee660 | 1754 | efx_start_port(efx); |
9f2cb71c | 1755 | efx_start_datapath(efx); |
8880f4ec | 1756 | |
626950db AR |
1757 | /* Start the hardware monitor if there is one */ |
1758 | if (efx->type->monitor != NULL) | |
8ceee660 BH |
1759 | queue_delayed_work(efx->workqueue, &efx->monitor_work, |
1760 | efx_monitor_interval); | |
626950db AR |
1761 | |
1762 | /* If link state detection is normally event-driven, we have | |
1763 | * to poll now because we could have missed a change | |
1764 | */ | |
1765 | if (efx_nic_rev(efx) >= EFX_REV_SIENA_A0) { | |
78c1f0a0 SH |
1766 | mutex_lock(&efx->mac_lock); |
1767 | if (efx->phy_op->poll(efx)) | |
1768 | efx_link_status_changed(efx); | |
1769 | mutex_unlock(&efx->mac_lock); | |
1770 | } | |
55edc6e6 | 1771 | |
ef2b90ee | 1772 | efx->type->start_stats(efx); |
f8f3b5ae JC |
1773 | efx->type->pull_stats(efx); |
1774 | spin_lock_bh(&efx->stats_lock); | |
1775 | efx->type->update_stats(efx, NULL, NULL); | |
1776 | spin_unlock_bh(&efx->stats_lock); | |
8ceee660 BH |
1777 | } |
1778 | ||
8b7325b4 BH |
1779 | /* Quiesce the hardware and software data path, and regular activity |
1780 | * for the port without bringing the link down. Safe to call multiple | |
1781 | * times with the NIC in almost any state, but interrupts should be | |
1782 | * enabled. Requires the RTNL lock. | |
1783 | */ | |
8ceee660 BH |
1784 | static void efx_stop_all(struct efx_nic *efx) |
1785 | { | |
8ceee660 BH |
1786 | EFX_ASSERT_RESET_SERIALISED(efx); |
1787 | ||
1788 | /* port_enabled can be read safely under the rtnl lock */ | |
1789 | if (!efx->port_enabled) | |
1790 | return; | |
1791 | ||
f8f3b5ae JC |
1792 | /* update stats before we go down so we can accurately count |
1793 | * rx_nodesc_drops | |
1794 | */ | |
1795 | efx->type->pull_stats(efx); | |
1796 | spin_lock_bh(&efx->stats_lock); | |
1797 | efx->type->update_stats(efx, NULL, NULL); | |
1798 | spin_unlock_bh(&efx->stats_lock); | |
ef2b90ee | 1799 | efx->type->stop_stats(efx); |
8ceee660 BH |
1800 | efx_stop_port(efx); |
1801 | ||
29c69a48 BH |
1802 | /* Stop the kernel transmit interface. This is only valid if |
1803 | * the device is stopped or detached; otherwise the watchdog | |
1804 | * may fire immediately. | |
1805 | */ | |
1806 | WARN_ON(netif_running(efx->net_dev) && | |
1807 | netif_device_present(efx->net_dev)); | |
9f2cb71c BH |
1808 | netif_tx_disable(efx->net_dev); |
1809 | ||
1810 | efx_stop_datapath(efx); | |
8ceee660 BH |
1811 | } |
1812 | ||
1813 | static void efx_remove_all(struct efx_nic *efx) | |
1814 | { | |
4642610c | 1815 | efx_remove_channels(efx); |
7f967c01 | 1816 | efx_remove_filters(efx); |
8ceee660 BH |
1817 | efx_remove_port(efx); |
1818 | efx_remove_nic(efx); | |
1819 | } | |
1820 | ||
8ceee660 BH |
1821 | /************************************************************************** |
1822 | * | |
1823 | * Interrupt moderation | |
1824 | * | |
1825 | **************************************************************************/ | |
1826 | ||
cc180b69 | 1827 | static unsigned int irq_mod_ticks(unsigned int usecs, unsigned int quantum_ns) |
0d86ebd8 | 1828 | { |
b548f976 BH |
1829 | if (usecs == 0) |
1830 | return 0; | |
cc180b69 | 1831 | if (usecs * 1000 < quantum_ns) |
0d86ebd8 | 1832 | return 1; /* never round down to 0 */ |
cc180b69 | 1833 | return usecs * 1000 / quantum_ns; |
0d86ebd8 BH |
1834 | } |
1835 | ||
8ceee660 | 1836 | /* Set interrupt moderation parameters */ |
9e393b30 BH |
1837 | int efx_init_irq_moderation(struct efx_nic *efx, unsigned int tx_usecs, |
1838 | unsigned int rx_usecs, bool rx_adaptive, | |
1839 | bool rx_may_override_tx) | |
8ceee660 | 1840 | { |
f7d12cdc | 1841 | struct efx_channel *channel; |
cc180b69 BH |
1842 | unsigned int irq_mod_max = DIV_ROUND_UP(efx->type->timer_period_max * |
1843 | efx->timer_quantum_ns, | |
1844 | 1000); | |
1845 | unsigned int tx_ticks; | |
1846 | unsigned int rx_ticks; | |
8ceee660 BH |
1847 | |
1848 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1849 | ||
cc180b69 | 1850 | if (tx_usecs > irq_mod_max || rx_usecs > irq_mod_max) |
9e393b30 BH |
1851 | return -EINVAL; |
1852 | ||
cc180b69 BH |
1853 | tx_ticks = irq_mod_ticks(tx_usecs, efx->timer_quantum_ns); |
1854 | rx_ticks = irq_mod_ticks(rx_usecs, efx->timer_quantum_ns); | |
1855 | ||
9e393b30 BH |
1856 | if (tx_ticks != rx_ticks && efx->tx_channel_offset == 0 && |
1857 | !rx_may_override_tx) { | |
1858 | netif_err(efx, drv, efx->net_dev, "Channels are shared. " | |
1859 | "RX and TX IRQ moderation must be equal\n"); | |
1860 | return -EINVAL; | |
1861 | } | |
1862 | ||
6fb70fd1 | 1863 | efx->irq_rx_adaptive = rx_adaptive; |
0d86ebd8 | 1864 | efx->irq_rx_moderation = rx_ticks; |
f7d12cdc | 1865 | efx_for_each_channel(channel, efx) { |
525da907 | 1866 | if (efx_channel_has_rx_queue(channel)) |
f7d12cdc | 1867 | channel->irq_moderation = rx_ticks; |
525da907 | 1868 | else if (efx_channel_has_tx_queues(channel)) |
f7d12cdc BH |
1869 | channel->irq_moderation = tx_ticks; |
1870 | } | |
9e393b30 BH |
1871 | |
1872 | return 0; | |
8ceee660 BH |
1873 | } |
1874 | ||
a0c4faf5 BH |
1875 | void efx_get_irq_moderation(struct efx_nic *efx, unsigned int *tx_usecs, |
1876 | unsigned int *rx_usecs, bool *rx_adaptive) | |
1877 | { | |
cc180b69 BH |
1878 | /* We must round up when converting ticks to microseconds |
1879 | * because we round down when converting the other way. | |
1880 | */ | |
1881 | ||
a0c4faf5 | 1882 | *rx_adaptive = efx->irq_rx_adaptive; |
cc180b69 BH |
1883 | *rx_usecs = DIV_ROUND_UP(efx->irq_rx_moderation * |
1884 | efx->timer_quantum_ns, | |
1885 | 1000); | |
a0c4faf5 BH |
1886 | |
1887 | /* If channels are shared between RX and TX, so is IRQ | |
1888 | * moderation. Otherwise, IRQ moderation is the same for all | |
1889 | * TX channels and is not adaptive. | |
1890 | */ | |
1891 | if (efx->tx_channel_offset == 0) | |
1892 | *tx_usecs = *rx_usecs; | |
1893 | else | |
cc180b69 | 1894 | *tx_usecs = DIV_ROUND_UP( |
a0c4faf5 | 1895 | efx->channel[efx->tx_channel_offset]->irq_moderation * |
cc180b69 BH |
1896 | efx->timer_quantum_ns, |
1897 | 1000); | |
a0c4faf5 BH |
1898 | } |
1899 | ||
8ceee660 BH |
1900 | /************************************************************************** |
1901 | * | |
1902 | * Hardware monitor | |
1903 | * | |
1904 | **************************************************************************/ | |
1905 | ||
e254c274 | 1906 | /* Run periodically off the general workqueue */ |
8ceee660 BH |
1907 | static void efx_monitor(struct work_struct *data) |
1908 | { | |
1909 | struct efx_nic *efx = container_of(data, struct efx_nic, | |
1910 | monitor_work.work); | |
8ceee660 | 1911 | |
62776d03 BH |
1912 | netif_vdbg(efx, timer, efx->net_dev, |
1913 | "hardware monitor executing on CPU %d\n", | |
1914 | raw_smp_processor_id()); | |
ef2b90ee | 1915 | BUG_ON(efx->type->monitor == NULL); |
8ceee660 | 1916 | |
8ceee660 BH |
1917 | /* If the mac_lock is already held then it is likely a port |
1918 | * reconfiguration is already in place, which will likely do | |
e254c274 BH |
1919 | * most of the work of monitor() anyway. */ |
1920 | if (mutex_trylock(&efx->mac_lock)) { | |
1921 | if (efx->port_enabled) | |
1922 | efx->type->monitor(efx); | |
1923 | mutex_unlock(&efx->mac_lock); | |
1924 | } | |
8ceee660 | 1925 | |
8ceee660 BH |
1926 | queue_delayed_work(efx->workqueue, &efx->monitor_work, |
1927 | efx_monitor_interval); | |
1928 | } | |
1929 | ||
1930 | /************************************************************************** | |
1931 | * | |
1932 | * ioctls | |
1933 | * | |
1934 | *************************************************************************/ | |
1935 | ||
1936 | /* Net device ioctl | |
1937 | * Context: process, rtnl_lock() held. | |
1938 | */ | |
1939 | static int efx_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd) | |
1940 | { | |
767e468c | 1941 | struct efx_nic *efx = netdev_priv(net_dev); |
68e7f45e | 1942 | struct mii_ioctl_data *data = if_mii(ifr); |
8ceee660 | 1943 | |
7c236c43 | 1944 | if (cmd == SIOCSHWTSTAMP) |
433dc9b3 BH |
1945 | return efx_ptp_set_ts_config(efx, ifr); |
1946 | if (cmd == SIOCGHWTSTAMP) | |
1947 | return efx_ptp_get_ts_config(efx, ifr); | |
7c236c43 | 1948 | |
68e7f45e BH |
1949 | /* Convert phy_id from older PRTAD/DEVAD format */ |
1950 | if ((cmd == SIOCGMIIREG || cmd == SIOCSMIIREG) && | |
1951 | (data->phy_id & 0xfc00) == 0x0400) | |
1952 | data->phy_id ^= MDIO_PHY_ID_C45 | 0x0400; | |
1953 | ||
1954 | return mdio_mii_ioctl(&efx->mdio, data, cmd); | |
8ceee660 BH |
1955 | } |
1956 | ||
1957 | /************************************************************************** | |
1958 | * | |
1959 | * NAPI interface | |
1960 | * | |
1961 | **************************************************************************/ | |
1962 | ||
7f967c01 BH |
1963 | static void efx_init_napi_channel(struct efx_channel *channel) |
1964 | { | |
1965 | struct efx_nic *efx = channel->efx; | |
1966 | ||
1967 | channel->napi_dev = efx->net_dev; | |
1968 | netif_napi_add(channel->napi_dev, &channel->napi_str, | |
1969 | efx_poll, napi_weight); | |
36763266 AR |
1970 | napi_hash_add(&channel->napi_str); |
1971 | efx_channel_init_lock(channel); | |
7f967c01 BH |
1972 | } |
1973 | ||
e8f14992 | 1974 | static void efx_init_napi(struct efx_nic *efx) |
8ceee660 BH |
1975 | { |
1976 | struct efx_channel *channel; | |
8ceee660 | 1977 | |
7f967c01 BH |
1978 | efx_for_each_channel(channel, efx) |
1979 | efx_init_napi_channel(channel); | |
e8f14992 BH |
1980 | } |
1981 | ||
1982 | static void efx_fini_napi_channel(struct efx_channel *channel) | |
1983 | { | |
36763266 | 1984 | if (channel->napi_dev) { |
e8f14992 | 1985 | netif_napi_del(&channel->napi_str); |
36763266 AR |
1986 | napi_hash_del(&channel->napi_str); |
1987 | } | |
e8f14992 | 1988 | channel->napi_dev = NULL; |
8ceee660 BH |
1989 | } |
1990 | ||
1991 | static void efx_fini_napi(struct efx_nic *efx) | |
1992 | { | |
1993 | struct efx_channel *channel; | |
1994 | ||
e8f14992 BH |
1995 | efx_for_each_channel(channel, efx) |
1996 | efx_fini_napi_channel(channel); | |
8ceee660 BH |
1997 | } |
1998 | ||
1999 | /************************************************************************** | |
2000 | * | |
2001 | * Kernel netpoll interface | |
2002 | * | |
2003 | *************************************************************************/ | |
2004 | ||
2005 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
2006 | ||
2007 | /* Although in the common case interrupts will be disabled, this is not | |
2008 | * guaranteed. However, all our work happens inside the NAPI callback, | |
2009 | * so no locking is required. | |
2010 | */ | |
2011 | static void efx_netpoll(struct net_device *net_dev) | |
2012 | { | |
767e468c | 2013 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
2014 | struct efx_channel *channel; |
2015 | ||
64ee3120 | 2016 | efx_for_each_channel(channel, efx) |
8ceee660 BH |
2017 | efx_schedule_channel(channel); |
2018 | } | |
2019 | ||
2020 | #endif | |
2021 | ||
36763266 AR |
2022 | #ifdef CONFIG_NET_RX_BUSY_POLL |
2023 | static int efx_busy_poll(struct napi_struct *napi) | |
2024 | { | |
2025 | struct efx_channel *channel = | |
2026 | container_of(napi, struct efx_channel, napi_str); | |
2027 | struct efx_nic *efx = channel->efx; | |
2028 | int budget = 4; | |
2029 | int old_rx_packets, rx_packets; | |
2030 | ||
2031 | if (!netif_running(efx->net_dev)) | |
2032 | return LL_FLUSH_FAILED; | |
2033 | ||
2034 | if (!efx_channel_lock_poll(channel)) | |
2035 | return LL_FLUSH_BUSY; | |
2036 | ||
2037 | old_rx_packets = channel->rx_queue.rx_packets; | |
2038 | efx_process_channel(channel, budget); | |
2039 | ||
2040 | rx_packets = channel->rx_queue.rx_packets - old_rx_packets; | |
2041 | ||
2042 | /* There is no race condition with NAPI here. | |
2043 | * NAPI will automatically be rescheduled if it yielded during busy | |
2044 | * polling, because it was not able to take the lock and thus returned | |
2045 | * the full budget. | |
2046 | */ | |
2047 | efx_channel_unlock_poll(channel); | |
2048 | ||
2049 | return rx_packets; | |
2050 | } | |
2051 | #endif | |
2052 | ||
8ceee660 BH |
2053 | /************************************************************************** |
2054 | * | |
2055 | * Kernel net device interface | |
2056 | * | |
2057 | *************************************************************************/ | |
2058 | ||
2059 | /* Context: process, rtnl_lock() held. */ | |
2060 | static int efx_net_open(struct net_device *net_dev) | |
2061 | { | |
767e468c | 2062 | struct efx_nic *efx = netdev_priv(net_dev); |
8b7325b4 BH |
2063 | int rc; |
2064 | ||
62776d03 BH |
2065 | netif_dbg(efx, ifup, efx->net_dev, "opening device on CPU %d\n", |
2066 | raw_smp_processor_id()); | |
8ceee660 | 2067 | |
8b7325b4 BH |
2068 | rc = efx_check_disabled(efx); |
2069 | if (rc) | |
2070 | return rc; | |
f8b87c17 BH |
2071 | if (efx->phy_mode & PHY_MODE_SPECIAL) |
2072 | return -EBUSY; | |
8880f4ec BH |
2073 | if (efx_mcdi_poll_reboot(efx) && efx_reset(efx, RESET_TYPE_ALL)) |
2074 | return -EIO; | |
f8b87c17 | 2075 | |
78c1f0a0 SH |
2076 | /* Notify the kernel of the link state polled during driver load, |
2077 | * before the monitor starts running */ | |
2078 | efx_link_status_changed(efx); | |
2079 | ||
8ceee660 | 2080 | efx_start_all(efx); |
dd40781e | 2081 | efx_selftest_async_start(efx); |
8ceee660 BH |
2082 | return 0; |
2083 | } | |
2084 | ||
2085 | /* Context: process, rtnl_lock() held. | |
2086 | * Note that the kernel will ignore our return code; this method | |
2087 | * should really be a void. | |
2088 | */ | |
2089 | static int efx_net_stop(struct net_device *net_dev) | |
2090 | { | |
767e468c | 2091 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 | 2092 | |
62776d03 BH |
2093 | netif_dbg(efx, ifdown, efx->net_dev, "closing on CPU %d\n", |
2094 | raw_smp_processor_id()); | |
8ceee660 | 2095 | |
8b7325b4 BH |
2096 | /* Stop the device and flush all the channels */ |
2097 | efx_stop_all(efx); | |
8ceee660 BH |
2098 | |
2099 | return 0; | |
2100 | } | |
2101 | ||
5b9e207c | 2102 | /* Context: process, dev_base_lock or RTNL held, non-blocking. */ |
2aa9ef11 BH |
2103 | static struct rtnl_link_stats64 *efx_net_stats(struct net_device *net_dev, |
2104 | struct rtnl_link_stats64 *stats) | |
8ceee660 | 2105 | { |
767e468c | 2106 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 | 2107 | |
55edc6e6 | 2108 | spin_lock_bh(&efx->stats_lock); |
cd0ecc9a | 2109 | efx->type->update_stats(efx, NULL, stats); |
1cb34522 BH |
2110 | spin_unlock_bh(&efx->stats_lock); |
2111 | ||
8ceee660 BH |
2112 | return stats; |
2113 | } | |
2114 | ||
2115 | /* Context: netif_tx_lock held, BHs disabled. */ | |
2116 | static void efx_watchdog(struct net_device *net_dev) | |
2117 | { | |
767e468c | 2118 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 | 2119 | |
62776d03 BH |
2120 | netif_err(efx, tx_err, efx->net_dev, |
2121 | "TX stuck with port_enabled=%d: resetting channels\n", | |
2122 | efx->port_enabled); | |
8ceee660 | 2123 | |
739bb23d | 2124 | efx_schedule_reset(efx, RESET_TYPE_TX_WATCHDOG); |
8ceee660 BH |
2125 | } |
2126 | ||
2127 | ||
2128 | /* Context: process, rtnl_lock() held. */ | |
2129 | static int efx_change_mtu(struct net_device *net_dev, int new_mtu) | |
2130 | { | |
767e468c | 2131 | struct efx_nic *efx = netdev_priv(net_dev); |
8b7325b4 | 2132 | int rc; |
8ceee660 | 2133 | |
8b7325b4 BH |
2134 | rc = efx_check_disabled(efx); |
2135 | if (rc) | |
2136 | return rc; | |
8ceee660 BH |
2137 | if (new_mtu > EFX_MAX_MTU) |
2138 | return -EINVAL; | |
2139 | ||
62776d03 | 2140 | netif_dbg(efx, drv, efx->net_dev, "changing MTU to %d\n", new_mtu); |
8ceee660 | 2141 | |
29c69a48 BH |
2142 | efx_device_detach_sync(efx); |
2143 | efx_stop_all(efx); | |
2144 | ||
d3245b28 | 2145 | mutex_lock(&efx->mac_lock); |
8ceee660 | 2146 | net_dev->mtu = new_mtu; |
710b208d | 2147 | efx->type->reconfigure_mac(efx); |
d3245b28 BH |
2148 | mutex_unlock(&efx->mac_lock); |
2149 | ||
8ceee660 | 2150 | efx_start_all(efx); |
29c69a48 | 2151 | netif_device_attach(efx->net_dev); |
6c8eef4a | 2152 | return 0; |
8ceee660 BH |
2153 | } |
2154 | ||
2155 | static int efx_set_mac_address(struct net_device *net_dev, void *data) | |
2156 | { | |
767e468c | 2157 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 | 2158 | struct sockaddr *addr = data; |
e0b3ae30 | 2159 | u8 *new_addr = addr->sa_data; |
8ceee660 | 2160 | |
8ceee660 | 2161 | if (!is_valid_ether_addr(new_addr)) { |
62776d03 BH |
2162 | netif_err(efx, drv, efx->net_dev, |
2163 | "invalid ethernet MAC address requested: %pM\n", | |
2164 | new_addr); | |
504f9b5a | 2165 | return -EADDRNOTAVAIL; |
8ceee660 BH |
2166 | } |
2167 | ||
cd84ff4d | 2168 | ether_addr_copy(net_dev->dev_addr, new_addr); |
cd2d5b52 | 2169 | efx_sriov_mac_address_changed(efx); |
8ceee660 BH |
2170 | |
2171 | /* Reconfigure the MAC */ | |
d3245b28 | 2172 | mutex_lock(&efx->mac_lock); |
710b208d | 2173 | efx->type->reconfigure_mac(efx); |
d3245b28 | 2174 | mutex_unlock(&efx->mac_lock); |
8ceee660 BH |
2175 | |
2176 | return 0; | |
2177 | } | |
2178 | ||
a816f75a | 2179 | /* Context: netif_addr_lock held, BHs disabled. */ |
0fca8c97 | 2180 | static void efx_set_rx_mode(struct net_device *net_dev) |
8ceee660 | 2181 | { |
767e468c | 2182 | struct efx_nic *efx = netdev_priv(net_dev); |
a816f75a | 2183 | |
8be4f3e6 BH |
2184 | if (efx->port_enabled) |
2185 | queue_work(efx->workqueue, &efx->mac_work); | |
2186 | /* Otherwise efx_start_port() will do this */ | |
8ceee660 BH |
2187 | } |
2188 | ||
c8f44aff | 2189 | static int efx_set_features(struct net_device *net_dev, netdev_features_t data) |
abfe9039 BH |
2190 | { |
2191 | struct efx_nic *efx = netdev_priv(net_dev); | |
2192 | ||
2193 | /* If disabling RX n-tuple filtering, clear existing filters */ | |
2194 | if (net_dev->features & ~data & NETIF_F_NTUPLE) | |
fbd79120 | 2195 | return efx->type->filter_clear_rx(efx, EFX_FILTER_PRI_MANUAL); |
abfe9039 BH |
2196 | |
2197 | return 0; | |
2198 | } | |
2199 | ||
8127d661 | 2200 | static const struct net_device_ops efx_farch_netdev_ops = { |
c3ecb9f3 SH |
2201 | .ndo_open = efx_net_open, |
2202 | .ndo_stop = efx_net_stop, | |
4472702e | 2203 | .ndo_get_stats64 = efx_net_stats, |
c3ecb9f3 SH |
2204 | .ndo_tx_timeout = efx_watchdog, |
2205 | .ndo_start_xmit = efx_hard_start_xmit, | |
2206 | .ndo_validate_addr = eth_validate_addr, | |
2207 | .ndo_do_ioctl = efx_ioctl, | |
2208 | .ndo_change_mtu = efx_change_mtu, | |
2209 | .ndo_set_mac_address = efx_set_mac_address, | |
0fca8c97 | 2210 | .ndo_set_rx_mode = efx_set_rx_mode, |
abfe9039 | 2211 | .ndo_set_features = efx_set_features, |
cd2d5b52 BH |
2212 | #ifdef CONFIG_SFC_SRIOV |
2213 | .ndo_set_vf_mac = efx_sriov_set_vf_mac, | |
2214 | .ndo_set_vf_vlan = efx_sriov_set_vf_vlan, | |
2215 | .ndo_set_vf_spoofchk = efx_sriov_set_vf_spoofchk, | |
2216 | .ndo_get_vf_config = efx_sriov_get_vf_config, | |
2217 | #endif | |
c3ecb9f3 SH |
2218 | #ifdef CONFIG_NET_POLL_CONTROLLER |
2219 | .ndo_poll_controller = efx_netpoll, | |
2220 | #endif | |
94b274bf | 2221 | .ndo_setup_tc = efx_setup_tc, |
36763266 AR |
2222 | #ifdef CONFIG_NET_RX_BUSY_POLL |
2223 | .ndo_busy_poll = efx_busy_poll, | |
2224 | #endif | |
64d8ad6d BH |
2225 | #ifdef CONFIG_RFS_ACCEL |
2226 | .ndo_rx_flow_steer = efx_filter_rfs, | |
2227 | #endif | |
c3ecb9f3 SH |
2228 | }; |
2229 | ||
8127d661 BH |
2230 | static const struct net_device_ops efx_ef10_netdev_ops = { |
2231 | .ndo_open = efx_net_open, | |
2232 | .ndo_stop = efx_net_stop, | |
2233 | .ndo_get_stats64 = efx_net_stats, | |
2234 | .ndo_tx_timeout = efx_watchdog, | |
2235 | .ndo_start_xmit = efx_hard_start_xmit, | |
2236 | .ndo_validate_addr = eth_validate_addr, | |
2237 | .ndo_do_ioctl = efx_ioctl, | |
2238 | .ndo_change_mtu = efx_change_mtu, | |
2239 | .ndo_set_mac_address = efx_set_mac_address, | |
2240 | .ndo_set_rx_mode = efx_set_rx_mode, | |
2241 | .ndo_set_features = efx_set_features, | |
2242 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
2243 | .ndo_poll_controller = efx_netpoll, | |
2244 | #endif | |
36763266 AR |
2245 | #ifdef CONFIG_NET_RX_BUSY_POLL |
2246 | .ndo_busy_poll = efx_busy_poll, | |
2247 | #endif | |
8127d661 BH |
2248 | #ifdef CONFIG_RFS_ACCEL |
2249 | .ndo_rx_flow_steer = efx_filter_rfs, | |
2250 | #endif | |
2251 | }; | |
2252 | ||
7dde596e BH |
2253 | static void efx_update_name(struct efx_nic *efx) |
2254 | { | |
2255 | strcpy(efx->name, efx->net_dev->name); | |
2256 | efx_mtd_rename(efx); | |
2257 | efx_set_channel_names(efx); | |
2258 | } | |
2259 | ||
8ceee660 BH |
2260 | static int efx_netdev_event(struct notifier_block *this, |
2261 | unsigned long event, void *ptr) | |
2262 | { | |
351638e7 | 2263 | struct net_device *net_dev = netdev_notifier_info_to_dev(ptr); |
8ceee660 | 2264 | |
8127d661 BH |
2265 | if ((net_dev->netdev_ops == &efx_farch_netdev_ops || |
2266 | net_dev->netdev_ops == &efx_ef10_netdev_ops) && | |
7dde596e BH |
2267 | event == NETDEV_CHANGENAME) |
2268 | efx_update_name(netdev_priv(net_dev)); | |
8ceee660 BH |
2269 | |
2270 | return NOTIFY_DONE; | |
2271 | } | |
2272 | ||
2273 | static struct notifier_block efx_netdev_notifier = { | |
2274 | .notifier_call = efx_netdev_event, | |
2275 | }; | |
2276 | ||
06d5e193 BH |
2277 | static ssize_t |
2278 | show_phy_type(struct device *dev, struct device_attribute *attr, char *buf) | |
2279 | { | |
2280 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); | |
2281 | return sprintf(buf, "%d\n", efx->phy_type); | |
2282 | } | |
776fbcc9 | 2283 | static DEVICE_ATTR(phy_type, 0444, show_phy_type, NULL); |
06d5e193 | 2284 | |
8ceee660 BH |
2285 | static int efx_register_netdev(struct efx_nic *efx) |
2286 | { | |
2287 | struct net_device *net_dev = efx->net_dev; | |
c04bfc6b | 2288 | struct efx_channel *channel; |
8ceee660 BH |
2289 | int rc; |
2290 | ||
2291 | net_dev->watchdog_timeo = 5 * HZ; | |
2292 | net_dev->irq = efx->pci_dev->irq; | |
8127d661 BH |
2293 | if (efx_nic_rev(efx) >= EFX_REV_HUNT_A0) { |
2294 | net_dev->netdev_ops = &efx_ef10_netdev_ops; | |
2295 | net_dev->priv_flags |= IFF_UNICAST_FLT; | |
2296 | } else { | |
2297 | net_dev->netdev_ops = &efx_farch_netdev_ops; | |
2298 | } | |
7ad24ea4 | 2299 | net_dev->ethtool_ops = &efx_ethtool_ops; |
7e6d06f0 | 2300 | net_dev->gso_max_segs = EFX_TSO_MAX_SEGS; |
8ceee660 | 2301 | |
7dde596e | 2302 | rtnl_lock(); |
aed0628d | 2303 | |
7153f623 BH |
2304 | /* Enable resets to be scheduled and check whether any were |
2305 | * already requested. If so, the NIC is probably hosed so we | |
2306 | * abort. | |
2307 | */ | |
2308 | efx->state = STATE_READY; | |
2309 | smp_mb(); /* ensure we change state before checking reset_pending */ | |
2310 | if (efx->reset_pending) { | |
2311 | netif_err(efx, probe, efx->net_dev, | |
2312 | "aborting probe due to scheduled reset\n"); | |
2313 | rc = -EIO; | |
2314 | goto fail_locked; | |
2315 | } | |
2316 | ||
aed0628d BH |
2317 | rc = dev_alloc_name(net_dev, net_dev->name); |
2318 | if (rc < 0) | |
2319 | goto fail_locked; | |
7dde596e | 2320 | efx_update_name(efx); |
aed0628d | 2321 | |
8f8b3d51 BH |
2322 | /* Always start with carrier off; PHY events will detect the link */ |
2323 | netif_carrier_off(net_dev); | |
2324 | ||
aed0628d BH |
2325 | rc = register_netdevice(net_dev); |
2326 | if (rc) | |
2327 | goto fail_locked; | |
2328 | ||
c04bfc6b BH |
2329 | efx_for_each_channel(channel, efx) { |
2330 | struct efx_tx_queue *tx_queue; | |
60031fcc BH |
2331 | efx_for_each_channel_tx_queue(tx_queue, channel) |
2332 | efx_init_tx_queue_core_txq(tx_queue); | |
c04bfc6b BH |
2333 | } |
2334 | ||
0bcf4a64 BH |
2335 | efx_associate(efx); |
2336 | ||
7dde596e | 2337 | rtnl_unlock(); |
8ceee660 | 2338 | |
06d5e193 BH |
2339 | rc = device_create_file(&efx->pci_dev->dev, &dev_attr_phy_type); |
2340 | if (rc) { | |
62776d03 BH |
2341 | netif_err(efx, drv, efx->net_dev, |
2342 | "failed to init net dev attributes\n"); | |
06d5e193 BH |
2343 | goto fail_registered; |
2344 | } | |
2345 | ||
8ceee660 | 2346 | return 0; |
06d5e193 | 2347 | |
7153f623 BH |
2348 | fail_registered: |
2349 | rtnl_lock(); | |
0bcf4a64 | 2350 | efx_dissociate(efx); |
7153f623 | 2351 | unregister_netdevice(net_dev); |
aed0628d | 2352 | fail_locked: |
7153f623 | 2353 | efx->state = STATE_UNINIT; |
aed0628d | 2354 | rtnl_unlock(); |
62776d03 | 2355 | netif_err(efx, drv, efx->net_dev, "could not register net dev\n"); |
aed0628d | 2356 | return rc; |
8ceee660 BH |
2357 | } |
2358 | ||
2359 | static void efx_unregister_netdev(struct efx_nic *efx) | |
2360 | { | |
8ceee660 BH |
2361 | if (!efx->net_dev) |
2362 | return; | |
2363 | ||
767e468c | 2364 | BUG_ON(netdev_priv(efx->net_dev) != efx); |
8ceee660 | 2365 | |
73ba7b68 BH |
2366 | strlcpy(efx->name, pci_name(efx->pci_dev), sizeof(efx->name)); |
2367 | device_remove_file(&efx->pci_dev->dev, &dev_attr_phy_type); | |
7153f623 BH |
2368 | |
2369 | rtnl_lock(); | |
2370 | unregister_netdevice(efx->net_dev); | |
2371 | efx->state = STATE_UNINIT; | |
2372 | rtnl_unlock(); | |
8ceee660 BH |
2373 | } |
2374 | ||
2375 | /************************************************************************** | |
2376 | * | |
2377 | * Device reset and suspend | |
2378 | * | |
2379 | **************************************************************************/ | |
2380 | ||
2467ca46 BH |
2381 | /* Tears down the entire software state and most of the hardware state |
2382 | * before reset. */ | |
d3245b28 | 2383 | void efx_reset_down(struct efx_nic *efx, enum reset_type method) |
8ceee660 | 2384 | { |
8ceee660 BH |
2385 | EFX_ASSERT_RESET_SERIALISED(efx); |
2386 | ||
e283546c EC |
2387 | if (method == RESET_TYPE_MCDI_TIMEOUT) |
2388 | efx->type->prepare_flr(efx); | |
2389 | ||
2467ca46 | 2390 | efx_stop_all(efx); |
d8291187 | 2391 | efx_disable_interrupts(efx); |
5642ceef BH |
2392 | |
2393 | mutex_lock(&efx->mac_lock); | |
4b988280 SH |
2394 | if (efx->port_initialized && method != RESET_TYPE_INVISIBLE) |
2395 | efx->phy_op->fini(efx); | |
ef2b90ee | 2396 | efx->type->fini(efx); |
8ceee660 BH |
2397 | } |
2398 | ||
2467ca46 BH |
2399 | /* This function will always ensure that the locks acquired in |
2400 | * efx_reset_down() are released. A failure return code indicates | |
2401 | * that we were unable to reinitialise the hardware, and the | |
2402 | * driver should be disabled. If ok is false, then the rx and tx | |
2403 | * engines are not restarted, pending a RESET_DISABLE. */ | |
d3245b28 | 2404 | int efx_reset_up(struct efx_nic *efx, enum reset_type method, bool ok) |
8ceee660 BH |
2405 | { |
2406 | int rc; | |
2407 | ||
2467ca46 | 2408 | EFX_ASSERT_RESET_SERIALISED(efx); |
8ceee660 | 2409 | |
e283546c EC |
2410 | if (method == RESET_TYPE_MCDI_TIMEOUT) |
2411 | efx->type->finish_flr(efx); | |
2412 | ||
2413 | /* Ensure that SRAM is initialised even if we're disabling the device */ | |
ef2b90ee | 2414 | rc = efx->type->init(efx); |
8ceee660 | 2415 | if (rc) { |
62776d03 | 2416 | netif_err(efx, drv, efx->net_dev, "failed to initialise NIC\n"); |
eb9f6744 | 2417 | goto fail; |
8ceee660 BH |
2418 | } |
2419 | ||
eb9f6744 BH |
2420 | if (!ok) |
2421 | goto fail; | |
2422 | ||
4b988280 | 2423 | if (efx->port_initialized && method != RESET_TYPE_INVISIBLE) { |
eb9f6744 BH |
2424 | rc = efx->phy_op->init(efx); |
2425 | if (rc) | |
2426 | goto fail; | |
2427 | if (efx->phy_op->reconfigure(efx)) | |
62776d03 BH |
2428 | netif_err(efx, drv, efx->net_dev, |
2429 | "could not restore PHY settings\n"); | |
4b988280 SH |
2430 | } |
2431 | ||
261e4d96 JC |
2432 | rc = efx_enable_interrupts(efx); |
2433 | if (rc) | |
2434 | goto fail; | |
64eebcfd | 2435 | efx_restore_filters(efx); |
cd2d5b52 | 2436 | efx_sriov_reset(efx); |
eb9f6744 | 2437 | |
eb9f6744 BH |
2438 | mutex_unlock(&efx->mac_lock); |
2439 | ||
2440 | efx_start_all(efx); | |
2441 | ||
2442 | return 0; | |
2443 | ||
2444 | fail: | |
2445 | efx->port_initialized = false; | |
2467ca46 BH |
2446 | |
2447 | mutex_unlock(&efx->mac_lock); | |
2448 | ||
8ceee660 BH |
2449 | return rc; |
2450 | } | |
2451 | ||
eb9f6744 BH |
2452 | /* Reset the NIC using the specified method. Note that the reset may |
2453 | * fail, in which case the card will be left in an unusable state. | |
8ceee660 | 2454 | * |
eb9f6744 | 2455 | * Caller must hold the rtnl_lock. |
8ceee660 | 2456 | */ |
eb9f6744 | 2457 | int efx_reset(struct efx_nic *efx, enum reset_type method) |
8ceee660 | 2458 | { |
eb9f6744 BH |
2459 | int rc, rc2; |
2460 | bool disabled; | |
8ceee660 | 2461 | |
62776d03 BH |
2462 | netif_info(efx, drv, efx->net_dev, "resetting (%s)\n", |
2463 | RESET_TYPE(method)); | |
8ceee660 | 2464 | |
c2f3b8e3 | 2465 | efx_device_detach_sync(efx); |
d3245b28 | 2466 | efx_reset_down(efx, method); |
8ceee660 | 2467 | |
ef2b90ee | 2468 | rc = efx->type->reset(efx, method); |
8ceee660 | 2469 | if (rc) { |
62776d03 | 2470 | netif_err(efx, drv, efx->net_dev, "failed to reset hardware\n"); |
eb9f6744 | 2471 | goto out; |
8ceee660 BH |
2472 | } |
2473 | ||
a7d529ae BH |
2474 | /* Clear flags for the scopes we covered. We assume the NIC and |
2475 | * driver are now quiescent so that there is no race here. | |
2476 | */ | |
e283546c EC |
2477 | if (method < RESET_TYPE_MAX_METHOD) |
2478 | efx->reset_pending &= -(1 << (method + 1)); | |
2479 | else /* it doesn't fit into the well-ordered scope hierarchy */ | |
2480 | __clear_bit(method, &efx->reset_pending); | |
8ceee660 BH |
2481 | |
2482 | /* Reinitialise bus-mastering, which may have been turned off before | |
2483 | * the reset was scheduled. This is still appropriate, even in the | |
2484 | * RESET_TYPE_DISABLE since this driver generally assumes the hardware | |
2485 | * can respond to requests. */ | |
2486 | pci_set_master(efx->pci_dev); | |
2487 | ||
eb9f6744 | 2488 | out: |
8ceee660 | 2489 | /* Leave device stopped if necessary */ |
626950db AR |
2490 | disabled = rc || |
2491 | method == RESET_TYPE_DISABLE || | |
2492 | method == RESET_TYPE_RECOVER_OR_DISABLE; | |
eb9f6744 BH |
2493 | rc2 = efx_reset_up(efx, method, !disabled); |
2494 | if (rc2) { | |
2495 | disabled = true; | |
2496 | if (!rc) | |
2497 | rc = rc2; | |
8ceee660 BH |
2498 | } |
2499 | ||
eb9f6744 | 2500 | if (disabled) { |
f49a4589 | 2501 | dev_close(efx->net_dev); |
62776d03 | 2502 | netif_err(efx, drv, efx->net_dev, "has been disabled\n"); |
f4bd954e | 2503 | efx->state = STATE_DISABLED; |
f4bd954e | 2504 | } else { |
62776d03 | 2505 | netif_dbg(efx, drv, efx->net_dev, "reset complete\n"); |
e4abce85 | 2506 | netif_device_attach(efx->net_dev); |
f4bd954e | 2507 | } |
8ceee660 BH |
2508 | return rc; |
2509 | } | |
2510 | ||
626950db AR |
2511 | /* Try recovery mechanisms. |
2512 | * For now only EEH is supported. | |
2513 | * Returns 0 if the recovery mechanisms are unsuccessful. | |
2514 | * Returns a non-zero value otherwise. | |
2515 | */ | |
b28405b0 | 2516 | int efx_try_recovery(struct efx_nic *efx) |
626950db AR |
2517 | { |
2518 | #ifdef CONFIG_EEH | |
2519 | /* A PCI error can occur and not be seen by EEH because nothing | |
2520 | * happens on the PCI bus. In this case the driver may fail and | |
2521 | * schedule a 'recover or reset', leading to this recovery handler. | |
2522 | * Manually call the eeh failure check function. | |
2523 | */ | |
2524 | struct eeh_dev *eehdev = | |
2525 | of_node_to_eeh_dev(pci_device_to_OF_node(efx->pci_dev)); | |
2526 | ||
2527 | if (eeh_dev_check_failure(eehdev)) { | |
2528 | /* The EEH mechanisms will handle the error and reset the | |
2529 | * device if necessary. | |
2530 | */ | |
2531 | return 1; | |
2532 | } | |
2533 | #endif | |
2534 | return 0; | |
2535 | } | |
2536 | ||
74cd60a4 JC |
2537 | static void efx_wait_for_bist_end(struct efx_nic *efx) |
2538 | { | |
2539 | int i; | |
2540 | ||
2541 | for (i = 0; i < BIST_WAIT_DELAY_COUNT; ++i) { | |
2542 | if (efx_mcdi_poll_reboot(efx)) | |
2543 | goto out; | |
2544 | msleep(BIST_WAIT_DELAY_MS); | |
2545 | } | |
2546 | ||
2547 | netif_err(efx, drv, efx->net_dev, "Warning: No MC reboot after BIST mode\n"); | |
2548 | out: | |
2549 | /* Either way unset the BIST flag. If we found no reboot we probably | |
2550 | * won't recover, but we should try. | |
2551 | */ | |
2552 | efx->mc_bist_for_other_fn = false; | |
2553 | } | |
2554 | ||
8ceee660 BH |
2555 | /* The worker thread exists so that code that cannot sleep can |
2556 | * schedule a reset for later. | |
2557 | */ | |
2558 | static void efx_reset_work(struct work_struct *data) | |
2559 | { | |
eb9f6744 | 2560 | struct efx_nic *efx = container_of(data, struct efx_nic, reset_work); |
626950db AR |
2561 | unsigned long pending; |
2562 | enum reset_type method; | |
2563 | ||
2564 | pending = ACCESS_ONCE(efx->reset_pending); | |
2565 | method = fls(pending) - 1; | |
2566 | ||
74cd60a4 JC |
2567 | if (method == RESET_TYPE_MC_BIST) |
2568 | efx_wait_for_bist_end(efx); | |
2569 | ||
626950db AR |
2570 | if ((method == RESET_TYPE_RECOVER_OR_DISABLE || |
2571 | method == RESET_TYPE_RECOVER_OR_ALL) && | |
2572 | efx_try_recovery(efx)) | |
2573 | return; | |
8ceee660 | 2574 | |
a7d529ae | 2575 | if (!pending) |
319ba649 SH |
2576 | return; |
2577 | ||
eb9f6744 | 2578 | rtnl_lock(); |
7153f623 BH |
2579 | |
2580 | /* We checked the state in efx_schedule_reset() but it may | |
2581 | * have changed by now. Now that we have the RTNL lock, | |
2582 | * it cannot change again. | |
2583 | */ | |
2584 | if (efx->state == STATE_READY) | |
626950db | 2585 | (void)efx_reset(efx, method); |
7153f623 | 2586 | |
eb9f6744 | 2587 | rtnl_unlock(); |
8ceee660 BH |
2588 | } |
2589 | ||
2590 | void efx_schedule_reset(struct efx_nic *efx, enum reset_type type) | |
2591 | { | |
2592 | enum reset_type method; | |
2593 | ||
626950db AR |
2594 | if (efx->state == STATE_RECOVERY) { |
2595 | netif_dbg(efx, drv, efx->net_dev, | |
2596 | "recovering: skip scheduling %s reset\n", | |
2597 | RESET_TYPE(type)); | |
2598 | return; | |
2599 | } | |
2600 | ||
8ceee660 BH |
2601 | switch (type) { |
2602 | case RESET_TYPE_INVISIBLE: | |
2603 | case RESET_TYPE_ALL: | |
626950db | 2604 | case RESET_TYPE_RECOVER_OR_ALL: |
8ceee660 BH |
2605 | case RESET_TYPE_WORLD: |
2606 | case RESET_TYPE_DISABLE: | |
626950db | 2607 | case RESET_TYPE_RECOVER_OR_DISABLE: |
74cd60a4 | 2608 | case RESET_TYPE_MC_BIST: |
e283546c | 2609 | case RESET_TYPE_MCDI_TIMEOUT: |
8ceee660 | 2610 | method = type; |
0e2a9c7c BH |
2611 | netif_dbg(efx, drv, efx->net_dev, "scheduling %s reset\n", |
2612 | RESET_TYPE(method)); | |
8ceee660 | 2613 | break; |
8ceee660 | 2614 | default: |
0e2a9c7c | 2615 | method = efx->type->map_reset_reason(type); |
62776d03 BH |
2616 | netif_dbg(efx, drv, efx->net_dev, |
2617 | "scheduling %s reset for %s\n", | |
2618 | RESET_TYPE(method), RESET_TYPE(type)); | |
0e2a9c7c BH |
2619 | break; |
2620 | } | |
8ceee660 | 2621 | |
a7d529ae | 2622 | set_bit(method, &efx->reset_pending); |
7153f623 BH |
2623 | smp_mb(); /* ensure we change reset_pending before checking state */ |
2624 | ||
2625 | /* If we're not READY then just leave the flags set as the cue | |
2626 | * to abort probing or reschedule the reset later. | |
2627 | */ | |
2628 | if (ACCESS_ONCE(efx->state) != STATE_READY) | |
2629 | return; | |
8ceee660 | 2630 | |
8880f4ec BH |
2631 | /* efx_process_channel() will no longer read events once a |
2632 | * reset is scheduled. So switch back to poll'd MCDI completions. */ | |
2633 | efx_mcdi_mode_poll(efx); | |
2634 | ||
1ab00629 | 2635 | queue_work(reset_workqueue, &efx->reset_work); |
8ceee660 BH |
2636 | } |
2637 | ||
2638 | /************************************************************************** | |
2639 | * | |
2640 | * List of NICs we support | |
2641 | * | |
2642 | **************************************************************************/ | |
2643 | ||
2644 | /* PCI device ID table */ | |
9baa3c34 | 2645 | static const struct pci_device_id efx_pci_table[] = { |
937383a5 BH |
2646 | {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, |
2647 | PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0), | |
daeda630 | 2648 | .driver_data = (unsigned long) &falcon_a1_nic_type}, |
937383a5 BH |
2649 | {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, |
2650 | PCI_DEVICE_ID_SOLARFLARE_SFC4000B), | |
daeda630 | 2651 | .driver_data = (unsigned long) &falcon_b0_nic_type}, |
547c474f | 2652 | {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0803), /* SFC9020 */ |
8880f4ec | 2653 | .driver_data = (unsigned long) &siena_a0_nic_type}, |
547c474f | 2654 | {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0813), /* SFL9021 */ |
8880f4ec | 2655 | .driver_data = (unsigned long) &siena_a0_nic_type}, |
8127d661 BH |
2656 | {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0903), /* SFC9120 PF */ |
2657 | .driver_data = (unsigned long) &efx_hunt_a0_nic_type}, | |
3b06a00e MW |
2658 | {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0923), /* SFC9140 PF */ |
2659 | .driver_data = (unsigned long) &efx_hunt_a0_nic_type}, | |
8ceee660 BH |
2660 | {0} /* end of list */ |
2661 | }; | |
2662 | ||
2663 | /************************************************************************** | |
2664 | * | |
3759433d | 2665 | * Dummy PHY/MAC operations |
8ceee660 | 2666 | * |
01aad7b6 | 2667 | * Can be used for some unimplemented operations |
8ceee660 BH |
2668 | * Needed so all function pointers are valid and do not have to be tested |
2669 | * before use | |
2670 | * | |
2671 | **************************************************************************/ | |
2672 | int efx_port_dummy_op_int(struct efx_nic *efx) | |
2673 | { | |
2674 | return 0; | |
2675 | } | |
2676 | void efx_port_dummy_op_void(struct efx_nic *efx) {} | |
d215697f | 2677 | |
2678 | static bool efx_port_dummy_op_poll(struct efx_nic *efx) | |
fdaa9aed SH |
2679 | { |
2680 | return false; | |
2681 | } | |
8ceee660 | 2682 | |
6c8c2513 | 2683 | static const struct efx_phy_operations efx_dummy_phy_operations = { |
8ceee660 | 2684 | .init = efx_port_dummy_op_int, |
d3245b28 | 2685 | .reconfigure = efx_port_dummy_op_int, |
fdaa9aed | 2686 | .poll = efx_port_dummy_op_poll, |
8ceee660 | 2687 | .fini = efx_port_dummy_op_void, |
8ceee660 BH |
2688 | }; |
2689 | ||
8ceee660 BH |
2690 | /************************************************************************** |
2691 | * | |
2692 | * Data housekeeping | |
2693 | * | |
2694 | **************************************************************************/ | |
2695 | ||
2696 | /* This zeroes out and then fills in the invariants in a struct | |
2697 | * efx_nic (including all sub-structures). | |
2698 | */ | |
adeb15aa | 2699 | static int efx_init_struct(struct efx_nic *efx, |
8ceee660 BH |
2700 | struct pci_dev *pci_dev, struct net_device *net_dev) |
2701 | { | |
4642610c | 2702 | int i; |
8ceee660 BH |
2703 | |
2704 | /* Initialise common structures */ | |
0bcf4a64 BH |
2705 | INIT_LIST_HEAD(&efx->node); |
2706 | INIT_LIST_HEAD(&efx->secondary_list); | |
8ceee660 | 2707 | spin_lock_init(&efx->biu_lock); |
76884835 BH |
2708 | #ifdef CONFIG_SFC_MTD |
2709 | INIT_LIST_HEAD(&efx->mtd_list); | |
2710 | #endif | |
8ceee660 BH |
2711 | INIT_WORK(&efx->reset_work, efx_reset_work); |
2712 | INIT_DELAYED_WORK(&efx->monitor_work, efx_monitor); | |
dd40781e | 2713 | INIT_DELAYED_WORK(&efx->selftest_work, efx_selftest_async_work); |
8ceee660 | 2714 | efx->pci_dev = pci_dev; |
62776d03 | 2715 | efx->msg_enable = debug; |
f16aeea0 | 2716 | efx->state = STATE_UNINIT; |
8ceee660 | 2717 | strlcpy(efx->name, pci_name(pci_dev), sizeof(efx->name)); |
8ceee660 BH |
2718 | |
2719 | efx->net_dev = net_dev; | |
43a3739d | 2720 | efx->rx_prefix_size = efx->type->rx_prefix_size; |
2ec03014 AR |
2721 | efx->rx_ip_align = |
2722 | NET_IP_ALIGN ? (efx->rx_prefix_size + NET_IP_ALIGN) % 4 : 0; | |
43a3739d JC |
2723 | efx->rx_packet_hash_offset = |
2724 | efx->type->rx_hash_offset - efx->type->rx_prefix_size; | |
bd9a265d JC |
2725 | efx->rx_packet_ts_offset = |
2726 | efx->type->rx_ts_offset - efx->type->rx_prefix_size; | |
8ceee660 BH |
2727 | spin_lock_init(&efx->stats_lock); |
2728 | mutex_init(&efx->mac_lock); | |
2729 | efx->phy_op = &efx_dummy_phy_operations; | |
68e7f45e | 2730 | efx->mdio.dev = net_dev; |
766ca0fa | 2731 | INIT_WORK(&efx->mac_work, efx_mac_work); |
9f2cb71c | 2732 | init_waitqueue_head(&efx->flush_wq); |
8ceee660 BH |
2733 | |
2734 | for (i = 0; i < EFX_MAX_CHANNELS; i++) { | |
4642610c BH |
2735 | efx->channel[i] = efx_alloc_channel(efx, i, NULL); |
2736 | if (!efx->channel[i]) | |
2737 | goto fail; | |
d8291187 BH |
2738 | efx->msi_context[i].efx = efx; |
2739 | efx->msi_context[i].index = i; | |
8ceee660 BH |
2740 | } |
2741 | ||
8ceee660 BH |
2742 | /* Higher numbered interrupt modes are less capable! */ |
2743 | efx->interrupt_mode = max(efx->type->max_interrupt_mode, | |
2744 | interrupt_mode); | |
2745 | ||
6977dc63 BH |
2746 | /* Would be good to use the net_dev name, but we're too early */ |
2747 | snprintf(efx->workqueue_name, sizeof(efx->workqueue_name), "sfc%s", | |
2748 | pci_name(pci_dev)); | |
2749 | efx->workqueue = create_singlethread_workqueue(efx->workqueue_name); | |
1ab00629 | 2750 | if (!efx->workqueue) |
4642610c | 2751 | goto fail; |
8d9853d9 | 2752 | |
8ceee660 | 2753 | return 0; |
4642610c BH |
2754 | |
2755 | fail: | |
2756 | efx_fini_struct(efx); | |
2757 | return -ENOMEM; | |
8ceee660 BH |
2758 | } |
2759 | ||
2760 | static void efx_fini_struct(struct efx_nic *efx) | |
2761 | { | |
8313aca3 BH |
2762 | int i; |
2763 | ||
2764 | for (i = 0; i < EFX_MAX_CHANNELS; i++) | |
2765 | kfree(efx->channel[i]); | |
2766 | ||
ef215e64 BH |
2767 | kfree(efx->vpd_sn); |
2768 | ||
8ceee660 BH |
2769 | if (efx->workqueue) { |
2770 | destroy_workqueue(efx->workqueue); | |
2771 | efx->workqueue = NULL; | |
2772 | } | |
2773 | } | |
2774 | ||
e4d112e4 EC |
2775 | void efx_update_sw_stats(struct efx_nic *efx, u64 *stats) |
2776 | { | |
2777 | u64 n_rx_nodesc_trunc = 0; | |
2778 | struct efx_channel *channel; | |
2779 | ||
2780 | efx_for_each_channel(channel, efx) | |
2781 | n_rx_nodesc_trunc += channel->n_rx_nodesc_trunc; | |
2782 | stats[GENERIC_STAT_rx_nodesc_trunc] = n_rx_nodesc_trunc; | |
2783 | stats[GENERIC_STAT_rx_noskb_drops] = atomic_read(&efx->n_rx_noskb_drops); | |
2784 | } | |
2785 | ||
8ceee660 BH |
2786 | /************************************************************************** |
2787 | * | |
2788 | * PCI interface | |
2789 | * | |
2790 | **************************************************************************/ | |
2791 | ||
2792 | /* Main body of final NIC shutdown code | |
2793 | * This is called only at module unload (or hotplug removal). | |
2794 | */ | |
2795 | static void efx_pci_remove_main(struct efx_nic *efx) | |
2796 | { | |
7153f623 BH |
2797 | /* Flush reset_work. It can no longer be scheduled since we |
2798 | * are not READY. | |
2799 | */ | |
2800 | BUG_ON(efx->state == STATE_READY); | |
2801 | cancel_work_sync(&efx->reset_work); | |
2802 | ||
d8291187 | 2803 | efx_disable_interrupts(efx); |
152b6a62 | 2804 | efx_nic_fini_interrupt(efx); |
8ceee660 | 2805 | efx_fini_port(efx); |
ef2b90ee | 2806 | efx->type->fini(efx); |
8ceee660 BH |
2807 | efx_fini_napi(efx); |
2808 | efx_remove_all(efx); | |
2809 | } | |
2810 | ||
2811 | /* Final NIC shutdown | |
2812 | * This is called only at module unload (or hotplug removal). | |
2813 | */ | |
2814 | static void efx_pci_remove(struct pci_dev *pci_dev) | |
2815 | { | |
2816 | struct efx_nic *efx; | |
2817 | ||
2818 | efx = pci_get_drvdata(pci_dev); | |
2819 | if (!efx) | |
2820 | return; | |
2821 | ||
2822 | /* Mark the NIC as fini, then stop the interface */ | |
2823 | rtnl_lock(); | |
0bcf4a64 | 2824 | efx_dissociate(efx); |
8ceee660 | 2825 | dev_close(efx->net_dev); |
d8291187 | 2826 | efx_disable_interrupts(efx); |
8ceee660 BH |
2827 | rtnl_unlock(); |
2828 | ||
cd2d5b52 | 2829 | efx_sriov_fini(efx); |
8ceee660 BH |
2830 | efx_unregister_netdev(efx); |
2831 | ||
7dde596e BH |
2832 | efx_mtd_remove(efx); |
2833 | ||
8ceee660 BH |
2834 | efx_pci_remove_main(efx); |
2835 | ||
8ceee660 | 2836 | efx_fini_io(efx); |
62776d03 | 2837 | netif_dbg(efx, drv, efx->net_dev, "shutdown successful\n"); |
8ceee660 | 2838 | |
8ceee660 BH |
2839 | efx_fini_struct(efx); |
2840 | free_netdev(efx->net_dev); | |
626950db AR |
2841 | |
2842 | pci_disable_pcie_error_reporting(pci_dev); | |
8ceee660 BH |
2843 | }; |
2844 | ||
460eeaa0 BH |
2845 | /* NIC VPD information |
2846 | * Called during probe to display the part number of the | |
2847 | * installed NIC. VPD is potentially very large but this should | |
2848 | * always appear within the first 512 bytes. | |
2849 | */ | |
2850 | #define SFC_VPD_LEN 512 | |
ef215e64 | 2851 | static void efx_probe_vpd_strings(struct efx_nic *efx) |
460eeaa0 BH |
2852 | { |
2853 | struct pci_dev *dev = efx->pci_dev; | |
2854 | char vpd_data[SFC_VPD_LEN]; | |
2855 | ssize_t vpd_size; | |
ef215e64 | 2856 | int ro_start, ro_size, i, j; |
460eeaa0 BH |
2857 | |
2858 | /* Get the vpd data from the device */ | |
2859 | vpd_size = pci_read_vpd(dev, 0, sizeof(vpd_data), vpd_data); | |
2860 | if (vpd_size <= 0) { | |
2861 | netif_err(efx, drv, efx->net_dev, "Unable to read VPD\n"); | |
2862 | return; | |
2863 | } | |
2864 | ||
2865 | /* Get the Read only section */ | |
ef215e64 BH |
2866 | ro_start = pci_vpd_find_tag(vpd_data, 0, vpd_size, PCI_VPD_LRDT_RO_DATA); |
2867 | if (ro_start < 0) { | |
460eeaa0 BH |
2868 | netif_err(efx, drv, efx->net_dev, "VPD Read-only not found\n"); |
2869 | return; | |
2870 | } | |
2871 | ||
ef215e64 BH |
2872 | ro_size = pci_vpd_lrdt_size(&vpd_data[ro_start]); |
2873 | j = ro_size; | |
2874 | i = ro_start + PCI_VPD_LRDT_TAG_SIZE; | |
460eeaa0 BH |
2875 | if (i + j > vpd_size) |
2876 | j = vpd_size - i; | |
2877 | ||
2878 | /* Get the Part number */ | |
2879 | i = pci_vpd_find_info_keyword(vpd_data, i, j, "PN"); | |
2880 | if (i < 0) { | |
2881 | netif_err(efx, drv, efx->net_dev, "Part number not found\n"); | |
2882 | return; | |
2883 | } | |
2884 | ||
2885 | j = pci_vpd_info_field_size(&vpd_data[i]); | |
2886 | i += PCI_VPD_INFO_FLD_HDR_SIZE; | |
2887 | if (i + j > vpd_size) { | |
2888 | netif_err(efx, drv, efx->net_dev, "Incomplete part number\n"); | |
2889 | return; | |
2890 | } | |
2891 | ||
2892 | netif_info(efx, drv, efx->net_dev, | |
2893 | "Part Number : %.*s\n", j, &vpd_data[i]); | |
ef215e64 BH |
2894 | |
2895 | i = ro_start + PCI_VPD_LRDT_TAG_SIZE; | |
2896 | j = ro_size; | |
2897 | i = pci_vpd_find_info_keyword(vpd_data, i, j, "SN"); | |
2898 | if (i < 0) { | |
2899 | netif_err(efx, drv, efx->net_dev, "Serial number not found\n"); | |
2900 | return; | |
2901 | } | |
2902 | ||
2903 | j = pci_vpd_info_field_size(&vpd_data[i]); | |
2904 | i += PCI_VPD_INFO_FLD_HDR_SIZE; | |
2905 | if (i + j > vpd_size) { | |
2906 | netif_err(efx, drv, efx->net_dev, "Incomplete serial number\n"); | |
2907 | return; | |
2908 | } | |
2909 | ||
2910 | efx->vpd_sn = kmalloc(j + 1, GFP_KERNEL); | |
2911 | if (!efx->vpd_sn) | |
2912 | return; | |
2913 | ||
2914 | snprintf(efx->vpd_sn, j + 1, "%s", &vpd_data[i]); | |
460eeaa0 BH |
2915 | } |
2916 | ||
2917 | ||
8ceee660 BH |
2918 | /* Main body of NIC initialisation |
2919 | * This is called at module load (or hotplug insertion, theoretically). | |
2920 | */ | |
2921 | static int efx_pci_probe_main(struct efx_nic *efx) | |
2922 | { | |
2923 | int rc; | |
2924 | ||
2925 | /* Do start-of-day initialisation */ | |
2926 | rc = efx_probe_all(efx); | |
2927 | if (rc) | |
2928 | goto fail1; | |
2929 | ||
e8f14992 | 2930 | efx_init_napi(efx); |
8ceee660 | 2931 | |
ef2b90ee | 2932 | rc = efx->type->init(efx); |
8ceee660 | 2933 | if (rc) { |
62776d03 BH |
2934 | netif_err(efx, probe, efx->net_dev, |
2935 | "failed to initialise NIC\n"); | |
278c0621 | 2936 | goto fail3; |
8ceee660 BH |
2937 | } |
2938 | ||
2939 | rc = efx_init_port(efx); | |
2940 | if (rc) { | |
62776d03 BH |
2941 | netif_err(efx, probe, efx->net_dev, |
2942 | "failed to initialise port\n"); | |
278c0621 | 2943 | goto fail4; |
8ceee660 BH |
2944 | } |
2945 | ||
152b6a62 | 2946 | rc = efx_nic_init_interrupt(efx); |
8ceee660 | 2947 | if (rc) |
278c0621 | 2948 | goto fail5; |
261e4d96 JC |
2949 | rc = efx_enable_interrupts(efx); |
2950 | if (rc) | |
2951 | goto fail6; | |
8ceee660 BH |
2952 | |
2953 | return 0; | |
2954 | ||
261e4d96 JC |
2955 | fail6: |
2956 | efx_nic_fini_interrupt(efx); | |
278c0621 | 2957 | fail5: |
8ceee660 | 2958 | efx_fini_port(efx); |
8ceee660 | 2959 | fail4: |
ef2b90ee | 2960 | efx->type->fini(efx); |
8ceee660 BH |
2961 | fail3: |
2962 | efx_fini_napi(efx); | |
8ceee660 BH |
2963 | efx_remove_all(efx); |
2964 | fail1: | |
2965 | return rc; | |
2966 | } | |
2967 | ||
2968 | /* NIC initialisation | |
2969 | * | |
2970 | * This is called at module load (or hotplug insertion, | |
73ba7b68 | 2971 | * theoretically). It sets up PCI mappings, resets the NIC, |
8ceee660 BH |
2972 | * sets up and registers the network devices with the kernel and hooks |
2973 | * the interrupt service routine. It does not prepare the device for | |
2974 | * transmission; this is left to the first time one of the network | |
2975 | * interfaces is brought up (i.e. efx_net_open). | |
2976 | */ | |
87d1fc11 | 2977 | static int efx_pci_probe(struct pci_dev *pci_dev, |
1dd06ae8 | 2978 | const struct pci_device_id *entry) |
8ceee660 | 2979 | { |
8ceee660 BH |
2980 | struct net_device *net_dev; |
2981 | struct efx_nic *efx; | |
fadac6aa | 2982 | int rc; |
8ceee660 BH |
2983 | |
2984 | /* Allocate and initialise a struct net_device and struct efx_nic */ | |
94b274bf BH |
2985 | net_dev = alloc_etherdev_mqs(sizeof(*efx), EFX_MAX_CORE_TX_QUEUES, |
2986 | EFX_MAX_RX_QUEUES); | |
8ceee660 BH |
2987 | if (!net_dev) |
2988 | return -ENOMEM; | |
adeb15aa BH |
2989 | efx = netdev_priv(net_dev); |
2990 | efx->type = (const struct efx_nic_type *) entry->driver_data; | |
2991 | net_dev->features |= (efx->type->offload_features | NETIF_F_SG | | |
97bc5415 | 2992 | NETIF_F_HIGHDMA | NETIF_F_TSO | |
abfe9039 | 2993 | NETIF_F_RXCSUM); |
adeb15aa | 2994 | if (efx->type->offload_features & NETIF_F_V6_CSUM) |
738a8f4b | 2995 | net_dev->features |= NETIF_F_TSO6; |
28506563 BH |
2996 | /* Mask for features that also apply to VLAN devices */ |
2997 | net_dev->vlan_features |= (NETIF_F_ALL_CSUM | NETIF_F_SG | | |
abfe9039 BH |
2998 | NETIF_F_HIGHDMA | NETIF_F_ALL_TSO | |
2999 | NETIF_F_RXCSUM); | |
3000 | /* All offloads can be toggled */ | |
3001 | net_dev->hw_features = net_dev->features & ~NETIF_F_HIGHDMA; | |
8ceee660 | 3002 | pci_set_drvdata(pci_dev, efx); |
62776d03 | 3003 | SET_NETDEV_DEV(net_dev, &pci_dev->dev); |
adeb15aa | 3004 | rc = efx_init_struct(efx, pci_dev, net_dev); |
8ceee660 BH |
3005 | if (rc) |
3006 | goto fail1; | |
3007 | ||
62776d03 | 3008 | netif_info(efx, probe, efx->net_dev, |
ff79c8ac | 3009 | "Solarflare NIC detected\n"); |
8ceee660 | 3010 | |
ef215e64 | 3011 | efx_probe_vpd_strings(efx); |
460eeaa0 | 3012 | |
8ceee660 BH |
3013 | /* Set up basic I/O (BAR mappings etc) */ |
3014 | rc = efx_init_io(efx); | |
3015 | if (rc) | |
3016 | goto fail2; | |
3017 | ||
fadac6aa | 3018 | rc = efx_pci_probe_main(efx); |
fadac6aa BH |
3019 | if (rc) |
3020 | goto fail3; | |
8ceee660 | 3021 | |
8ceee660 BH |
3022 | rc = efx_register_netdev(efx); |
3023 | if (rc) | |
fadac6aa | 3024 | goto fail4; |
8ceee660 | 3025 | |
cd2d5b52 BH |
3026 | rc = efx_sriov_init(efx); |
3027 | if (rc) | |
3028 | netif_err(efx, probe, efx->net_dev, | |
3029 | "SR-IOV can't be enabled rc %d\n", rc); | |
3030 | ||
62776d03 | 3031 | netif_dbg(efx, probe, efx->net_dev, "initialisation successful\n"); |
a5211bb5 | 3032 | |
7c43161c | 3033 | /* Try to create MTDs, but allow this to fail */ |
a5211bb5 | 3034 | rtnl_lock(); |
7c43161c | 3035 | rc = efx_mtd_probe(efx); |
a5211bb5 | 3036 | rtnl_unlock(); |
7c43161c BH |
3037 | if (rc) |
3038 | netif_warn(efx, probe, efx->net_dev, | |
3039 | "failed to create MTDs (%d)\n", rc); | |
3040 | ||
626950db AR |
3041 | rc = pci_enable_pcie_error_reporting(pci_dev); |
3042 | if (rc && rc != -EINVAL) | |
3043 | netif_warn(efx, probe, efx->net_dev, | |
3044 | "pci_enable_pcie_error_reporting failed (%d)\n", rc); | |
3045 | ||
8ceee660 BH |
3046 | return 0; |
3047 | ||
8ceee660 | 3048 | fail4: |
fadac6aa | 3049 | efx_pci_remove_main(efx); |
8ceee660 BH |
3050 | fail3: |
3051 | efx_fini_io(efx); | |
3052 | fail2: | |
3053 | efx_fini_struct(efx); | |
3054 | fail1: | |
5e2a911c | 3055 | WARN_ON(rc > 0); |
62776d03 | 3056 | netif_dbg(efx, drv, efx->net_dev, "initialisation failed. rc=%d\n", rc); |
8ceee660 BH |
3057 | free_netdev(net_dev); |
3058 | return rc; | |
3059 | } | |
3060 | ||
89c758fa BH |
3061 | static int efx_pm_freeze(struct device *dev) |
3062 | { | |
3063 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); | |
3064 | ||
61da026d BH |
3065 | rtnl_lock(); |
3066 | ||
6032fb56 BH |
3067 | if (efx->state != STATE_DISABLED) { |
3068 | efx->state = STATE_UNINIT; | |
89c758fa | 3069 | |
c2f3b8e3 | 3070 | efx_device_detach_sync(efx); |
89c758fa | 3071 | |
6032fb56 | 3072 | efx_stop_all(efx); |
d8291187 | 3073 | efx_disable_interrupts(efx); |
6032fb56 | 3074 | } |
89c758fa | 3075 | |
61da026d BH |
3076 | rtnl_unlock(); |
3077 | ||
89c758fa BH |
3078 | return 0; |
3079 | } | |
3080 | ||
3081 | static int efx_pm_thaw(struct device *dev) | |
3082 | { | |
261e4d96 | 3083 | int rc; |
89c758fa BH |
3084 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); |
3085 | ||
61da026d BH |
3086 | rtnl_lock(); |
3087 | ||
6032fb56 | 3088 | if (efx->state != STATE_DISABLED) { |
261e4d96 JC |
3089 | rc = efx_enable_interrupts(efx); |
3090 | if (rc) | |
3091 | goto fail; | |
89c758fa | 3092 | |
6032fb56 BH |
3093 | mutex_lock(&efx->mac_lock); |
3094 | efx->phy_op->reconfigure(efx); | |
3095 | mutex_unlock(&efx->mac_lock); | |
89c758fa | 3096 | |
6032fb56 | 3097 | efx_start_all(efx); |
89c758fa | 3098 | |
6032fb56 | 3099 | netif_device_attach(efx->net_dev); |
89c758fa | 3100 | |
6032fb56 | 3101 | efx->state = STATE_READY; |
89c758fa | 3102 | |
6032fb56 BH |
3103 | efx->type->resume_wol(efx); |
3104 | } | |
89c758fa | 3105 | |
61da026d BH |
3106 | rtnl_unlock(); |
3107 | ||
319ba649 SH |
3108 | /* Reschedule any quenched resets scheduled during efx_pm_freeze() */ |
3109 | queue_work(reset_workqueue, &efx->reset_work); | |
3110 | ||
89c758fa | 3111 | return 0; |
261e4d96 JC |
3112 | |
3113 | fail: | |
3114 | rtnl_unlock(); | |
3115 | ||
3116 | return rc; | |
89c758fa BH |
3117 | } |
3118 | ||
3119 | static int efx_pm_poweroff(struct device *dev) | |
3120 | { | |
3121 | struct pci_dev *pci_dev = to_pci_dev(dev); | |
3122 | struct efx_nic *efx = pci_get_drvdata(pci_dev); | |
3123 | ||
3124 | efx->type->fini(efx); | |
3125 | ||
a7d529ae | 3126 | efx->reset_pending = 0; |
89c758fa BH |
3127 | |
3128 | pci_save_state(pci_dev); | |
3129 | return pci_set_power_state(pci_dev, PCI_D3hot); | |
3130 | } | |
3131 | ||
3132 | /* Used for both resume and restore */ | |
3133 | static int efx_pm_resume(struct device *dev) | |
3134 | { | |
3135 | struct pci_dev *pci_dev = to_pci_dev(dev); | |
3136 | struct efx_nic *efx = pci_get_drvdata(pci_dev); | |
3137 | int rc; | |
3138 | ||
3139 | rc = pci_set_power_state(pci_dev, PCI_D0); | |
3140 | if (rc) | |
3141 | return rc; | |
3142 | pci_restore_state(pci_dev); | |
3143 | rc = pci_enable_device(pci_dev); | |
3144 | if (rc) | |
3145 | return rc; | |
3146 | pci_set_master(efx->pci_dev); | |
3147 | rc = efx->type->reset(efx, RESET_TYPE_ALL); | |
3148 | if (rc) | |
3149 | return rc; | |
3150 | rc = efx->type->init(efx); | |
3151 | if (rc) | |
3152 | return rc; | |
261e4d96 JC |
3153 | rc = efx_pm_thaw(dev); |
3154 | return rc; | |
89c758fa BH |
3155 | } |
3156 | ||
3157 | static int efx_pm_suspend(struct device *dev) | |
3158 | { | |
3159 | int rc; | |
3160 | ||
3161 | efx_pm_freeze(dev); | |
3162 | rc = efx_pm_poweroff(dev); | |
3163 | if (rc) | |
3164 | efx_pm_resume(dev); | |
3165 | return rc; | |
3166 | } | |
3167 | ||
18e83e4c | 3168 | static const struct dev_pm_ops efx_pm_ops = { |
89c758fa BH |
3169 | .suspend = efx_pm_suspend, |
3170 | .resume = efx_pm_resume, | |
3171 | .freeze = efx_pm_freeze, | |
3172 | .thaw = efx_pm_thaw, | |
3173 | .poweroff = efx_pm_poweroff, | |
3174 | .restore = efx_pm_resume, | |
3175 | }; | |
3176 | ||
626950db AR |
3177 | /* A PCI error affecting this device was detected. |
3178 | * At this point MMIO and DMA may be disabled. | |
3179 | * Stop the software path and request a slot reset. | |
3180 | */ | |
debd0034 | 3181 | static pci_ers_result_t efx_io_error_detected(struct pci_dev *pdev, |
3182 | enum pci_channel_state state) | |
626950db AR |
3183 | { |
3184 | pci_ers_result_t status = PCI_ERS_RESULT_RECOVERED; | |
3185 | struct efx_nic *efx = pci_get_drvdata(pdev); | |
3186 | ||
3187 | if (state == pci_channel_io_perm_failure) | |
3188 | return PCI_ERS_RESULT_DISCONNECT; | |
3189 | ||
3190 | rtnl_lock(); | |
3191 | ||
3192 | if (efx->state != STATE_DISABLED) { | |
3193 | efx->state = STATE_RECOVERY; | |
3194 | efx->reset_pending = 0; | |
3195 | ||
3196 | efx_device_detach_sync(efx); | |
3197 | ||
3198 | efx_stop_all(efx); | |
d8291187 | 3199 | efx_disable_interrupts(efx); |
626950db AR |
3200 | |
3201 | status = PCI_ERS_RESULT_NEED_RESET; | |
3202 | } else { | |
3203 | /* If the interface is disabled we don't want to do anything | |
3204 | * with it. | |
3205 | */ | |
3206 | status = PCI_ERS_RESULT_RECOVERED; | |
3207 | } | |
3208 | ||
3209 | rtnl_unlock(); | |
3210 | ||
3211 | pci_disable_device(pdev); | |
3212 | ||
3213 | return status; | |
3214 | } | |
3215 | ||
3216 | /* Fake a successfull reset, which will be performed later in efx_io_resume. */ | |
debd0034 | 3217 | static pci_ers_result_t efx_io_slot_reset(struct pci_dev *pdev) |
626950db AR |
3218 | { |
3219 | struct efx_nic *efx = pci_get_drvdata(pdev); | |
3220 | pci_ers_result_t status = PCI_ERS_RESULT_RECOVERED; | |
3221 | int rc; | |
3222 | ||
3223 | if (pci_enable_device(pdev)) { | |
3224 | netif_err(efx, hw, efx->net_dev, | |
3225 | "Cannot re-enable PCI device after reset.\n"); | |
3226 | status = PCI_ERS_RESULT_DISCONNECT; | |
3227 | } | |
3228 | ||
3229 | rc = pci_cleanup_aer_uncorrect_error_status(pdev); | |
3230 | if (rc) { | |
3231 | netif_err(efx, hw, efx->net_dev, | |
3232 | "pci_cleanup_aer_uncorrect_error_status failed (%d)\n", rc); | |
3233 | /* Non-fatal error. Continue. */ | |
3234 | } | |
3235 | ||
3236 | return status; | |
3237 | } | |
3238 | ||
3239 | /* Perform the actual reset and resume I/O operations. */ | |
3240 | static void efx_io_resume(struct pci_dev *pdev) | |
3241 | { | |
3242 | struct efx_nic *efx = pci_get_drvdata(pdev); | |
3243 | int rc; | |
3244 | ||
3245 | rtnl_lock(); | |
3246 | ||
3247 | if (efx->state == STATE_DISABLED) | |
3248 | goto out; | |
3249 | ||
3250 | rc = efx_reset(efx, RESET_TYPE_ALL); | |
3251 | if (rc) { | |
3252 | netif_err(efx, hw, efx->net_dev, | |
3253 | "efx_reset failed after PCI error (%d)\n", rc); | |
3254 | } else { | |
3255 | efx->state = STATE_READY; | |
3256 | netif_dbg(efx, hw, efx->net_dev, | |
3257 | "Done resetting and resuming IO after PCI error.\n"); | |
3258 | } | |
3259 | ||
3260 | out: | |
3261 | rtnl_unlock(); | |
3262 | } | |
3263 | ||
3264 | /* For simplicity and reliability, we always require a slot reset and try to | |
3265 | * reset the hardware when a pci error affecting the device is detected. | |
3266 | * We leave both the link_reset and mmio_enabled callback unimplemented: | |
3267 | * with our request for slot reset the mmio_enabled callback will never be | |
3268 | * called, and the link_reset callback is not used by AER or EEH mechanisms. | |
3269 | */ | |
3270 | static struct pci_error_handlers efx_err_handlers = { | |
3271 | .error_detected = efx_io_error_detected, | |
3272 | .slot_reset = efx_io_slot_reset, | |
3273 | .resume = efx_io_resume, | |
3274 | }; | |
3275 | ||
8ceee660 | 3276 | static struct pci_driver efx_pci_driver = { |
c5d5f5fd | 3277 | .name = KBUILD_MODNAME, |
8ceee660 BH |
3278 | .id_table = efx_pci_table, |
3279 | .probe = efx_pci_probe, | |
3280 | .remove = efx_pci_remove, | |
89c758fa | 3281 | .driver.pm = &efx_pm_ops, |
626950db | 3282 | .err_handler = &efx_err_handlers, |
8ceee660 BH |
3283 | }; |
3284 | ||
3285 | /************************************************************************** | |
3286 | * | |
3287 | * Kernel module interface | |
3288 | * | |
3289 | *************************************************************************/ | |
3290 | ||
3291 | module_param(interrupt_mode, uint, 0444); | |
3292 | MODULE_PARM_DESC(interrupt_mode, | |
3293 | "Interrupt mode (0=>MSIX 1=>MSI 2=>legacy)"); | |
3294 | ||
3295 | static int __init efx_init_module(void) | |
3296 | { | |
3297 | int rc; | |
3298 | ||
3299 | printk(KERN_INFO "Solarflare NET driver v" EFX_DRIVER_VERSION "\n"); | |
3300 | ||
3301 | rc = register_netdevice_notifier(&efx_netdev_notifier); | |
3302 | if (rc) | |
3303 | goto err_notifier; | |
3304 | ||
cd2d5b52 BH |
3305 | rc = efx_init_sriov(); |
3306 | if (rc) | |
3307 | goto err_sriov; | |
3308 | ||
1ab00629 SH |
3309 | reset_workqueue = create_singlethread_workqueue("sfc_reset"); |
3310 | if (!reset_workqueue) { | |
3311 | rc = -ENOMEM; | |
3312 | goto err_reset; | |
3313 | } | |
8ceee660 BH |
3314 | |
3315 | rc = pci_register_driver(&efx_pci_driver); | |
3316 | if (rc < 0) | |
3317 | goto err_pci; | |
3318 | ||
3319 | return 0; | |
3320 | ||
3321 | err_pci: | |
1ab00629 SH |
3322 | destroy_workqueue(reset_workqueue); |
3323 | err_reset: | |
cd2d5b52 BH |
3324 | efx_fini_sriov(); |
3325 | err_sriov: | |
8ceee660 BH |
3326 | unregister_netdevice_notifier(&efx_netdev_notifier); |
3327 | err_notifier: | |
3328 | return rc; | |
3329 | } | |
3330 | ||
3331 | static void __exit efx_exit_module(void) | |
3332 | { | |
3333 | printk(KERN_INFO "Solarflare NET driver unloading\n"); | |
3334 | ||
3335 | pci_unregister_driver(&efx_pci_driver); | |
1ab00629 | 3336 | destroy_workqueue(reset_workqueue); |
cd2d5b52 | 3337 | efx_fini_sriov(); |
8ceee660 BH |
3338 | unregister_netdevice_notifier(&efx_netdev_notifier); |
3339 | ||
3340 | } | |
3341 | ||
3342 | module_init(efx_init_module); | |
3343 | module_exit(efx_exit_module); | |
3344 | ||
906bb26c BH |
3345 | MODULE_AUTHOR("Solarflare Communications and " |
3346 | "Michael Brown <mbrown@fensystems.co.uk>"); | |
6a350fdb | 3347 | MODULE_DESCRIPTION("Solarflare network driver"); |
8ceee660 BH |
3348 | MODULE_LICENSE("GPL"); |
3349 | MODULE_DEVICE_TABLE(pci, efx_pci_table); |