[mirror_ubuntu-jammy-kernel.git] / drivers / net / ethernet / sfc / falcon / tenxpress.c

// SPDX-License-Identifier: GPL-2.0-only
/****************************************************************************
 * Driver for Solarflare network controllers and boards
 * Copyright 2007-2011 Solarflare Communications Inc.
 */

#include <linux/delay.h>
#include <linux/rtnetlink.h>
#include <linux/seq_file.h>
#include <linux/slab.h>
#include "efx.h"
#include "mdio_10g.h"
#include "nic.h"
#include "phy.h"
#include "workarounds.h"

/* We expect these MMDs to be in the package. */
#define TENXPRESS_REQUIRED_DEVS (MDIO_DEVS_PMAPMD	| \
				 MDIO_DEVS_PCS		| \
				 MDIO_DEVS_PHYXS	| \
				 MDIO_DEVS_AN)

#define SFX7101_LOOPBACKS ((1 << LOOPBACK_PHYXS) |	\
			   (1 << LOOPBACK_PCS) |	\
			   (1 << LOOPBACK_PMAPMD) |	\
			   (1 << LOOPBACK_PHYXS_WS))

/* We complain if we fail to see the link partner as 10G capable this many
 * times in a row (must be > 1 as sampling the autoneg. registers is racy)
 */
#define MAX_BAD_LP_TRIES	(5)

/* Extended control register */
#define PMA_PMD_XCONTROL_REG	49152
#define PMA_PMD_EXT_GMII_EN_LBN	1
#define PMA_PMD_EXT_GMII_EN_WIDTH 1
#define PMA_PMD_EXT_CLK_OUT_LBN	2
#define PMA_PMD_EXT_CLK_OUT_WIDTH 1
#define PMA_PMD_LNPGA_POWERDOWN_LBN 8
#define PMA_PMD_LNPGA_POWERDOWN_WIDTH 1
#define PMA_PMD_EXT_CLK312_WIDTH 1
#define PMA_PMD_EXT_LPOWER_LBN  12
#define PMA_PMD_EXT_LPOWER_WIDTH 1
#define PMA_PMD_EXT_ROBUST_LBN	14
#define PMA_PMD_EXT_ROBUST_WIDTH 1
#define PMA_PMD_EXT_SSR_LBN	15
#define PMA_PMD_EXT_SSR_WIDTH	1

/* extended status register */
#define PMA_PMD_XSTATUS_REG	49153
#define PMA_PMD_XSTAT_MDIX_LBN	14
#define PMA_PMD_XSTAT_FLP_LBN   (12)

/* LED control register */
#define PMA_PMD_LED_CTRL_REG	49159
#define PMA_PMA_LED_ACTIVITY_LBN	(3)

/* LED function override register */
#define PMA_PMD_LED_OVERR_REG	49161
/* Bit positions for different LEDs (there are more but not wired on SFE4001)*/
#define PMA_PMD_LED_LINK_LBN	(0)
#define PMA_PMD_LED_SPEED_LBN	(2)
#define PMA_PMD_LED_TX_LBN	(4)
#define PMA_PMD_LED_RX_LBN	(6)
/* Override settings */
#define	PMA_PMD_LED_AUTO	(0)	/* H/W control */
#define	PMA_PMD_LED_ON		(1)
#define	PMA_PMD_LED_OFF		(2)
#define PMA_PMD_LED_FLASH	(3)
#define PMA_PMD_LED_MASK	3
/* All LEDs under hardware control */
/* Green and Amber under hardware control, Red off */
#define SFX7101_PMA_PMD_LED_DEFAULT (PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN)

#define PMA_PMD_SPEED_ENABLE_REG 49192
#define PMA_PMD_100TX_ADV_LBN    1
#define PMA_PMD_100TX_ADV_WIDTH  1
#define PMA_PMD_1000T_ADV_LBN    2
#define PMA_PMD_1000T_ADV_WIDTH  1
#define PMA_PMD_10000T_ADV_LBN   3
#define PMA_PMD_10000T_ADV_WIDTH 1
#define PMA_PMD_SPEED_LBN        4
#define PMA_PMD_SPEED_WIDTH      4

/* Misc register defines */
#define PCS_CLOCK_CTRL_REG	55297
#define PLL312_RST_N_LBN 2

#define PCS_SOFT_RST2_REG	55302
#define SERDES_RST_N_LBN 13
#define XGXS_RST_N_LBN 12

#define	PCS_TEST_SELECT_REG	55303	/* PRM 10.5.8 */
#define	CLK312_EN_LBN 3

/* PHYXS registers */
#define PHYXS_XCONTROL_REG	49152
#define PHYXS_RESET_LBN		15
#define PHYXS_RESET_WIDTH	1

#define PHYXS_TEST1         (49162)
#define LOOPBACK_NEAR_LBN   (8)
#define LOOPBACK_NEAR_WIDTH (1)

/* Boot status register */
#define PCS_BOOT_STATUS_REG		53248
#define PCS_BOOT_FATAL_ERROR_LBN	0
#define PCS_BOOT_PROGRESS_LBN		1
#define PCS_BOOT_PROGRESS_WIDTH		2
#define PCS_BOOT_PROGRESS_INIT		0
#define PCS_BOOT_PROGRESS_WAIT_MDIO	1
#define PCS_BOOT_PROGRESS_CHECKSUM	2
#define PCS_BOOT_PROGRESS_JUMP		3
#define PCS_BOOT_DOWNLOAD_WAIT_LBN	3
#define PCS_BOOT_CODE_STARTED_LBN	4

/* 100M/1G PHY registers */
#define GPHY_XCONTROL_REG	49152
#define GPHY_ISOLATE_LBN	10
#define GPHY_ISOLATE_WIDTH	1
#define GPHY_DUPLEX_LBN		8
#define GPHY_DUPLEX_WIDTH	1
#define GPHY_LOOPBACK_NEAR_LBN	14
#define GPHY_LOOPBACK_NEAR_WIDTH 1

#define C22EXT_STATUS_REG       49153
#define C22EXT_STATUS_LINK_LBN  2
#define C22EXT_STATUS_LINK_WIDTH 1

#define C22EXT_MSTSLV_CTRL			49161
#define C22EXT_MSTSLV_CTRL_ADV_1000_HD_LBN	8
#define C22EXT_MSTSLV_CTRL_ADV_1000_FD_LBN	9

#define C22EXT_MSTSLV_STATUS			49162
#define C22EXT_MSTSLV_STATUS_LP_1000_HD_LBN	10
#define C22EXT_MSTSLV_STATUS_LP_1000_FD_LBN	11

/* Time to wait between powering down the LNPGA and turning off the power
 * rails */
#define LNPGA_PDOWN_WAIT	(HZ / 5)

struct tenxpress_phy_data {
	enum ef4_loopback_mode loopback_mode;
	enum ef4_phy_mode phy_mode;
	int bad_lp_tries;
};

static int tenxpress_init(struct ef4_nic *efx)
{
	/* Enable 312.5 MHz clock */
	ef4_mdio_write(efx, MDIO_MMD_PCS, PCS_TEST_SELECT_REG,
		       1 << CLK312_EN_LBN);

	/* Set the LEDs up as: Green = Link, Amber = Link/Act, Red = Off */
	ef4_mdio_set_flag(efx, MDIO_MMD_PMAPMD, PMA_PMD_LED_CTRL_REG,
			  1 << PMA_PMA_LED_ACTIVITY_LBN, true);
	ef4_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_LED_OVERR_REG,
		       SFX7101_PMA_PMD_LED_DEFAULT);

	return 0;
}

static int tenxpress_phy_probe(struct ef4_nic *efx)
{
	struct tenxpress_phy_data *phy_data;

	/* Allocate phy private storage */
	phy_data = kzalloc(sizeof(*phy_data), GFP_KERNEL);
	if (!phy_data)
		return -ENOMEM;
	efx->phy_data = phy_data;
	phy_data->phy_mode = efx->phy_mode;

	efx->mdio.mmds = TENXPRESS_REQUIRED_DEVS;
	efx->mdio.mode_support = MDIO_SUPPORTS_C45;

	efx->loopback_modes = SFX7101_LOOPBACKS | FALCON_XMAC_LOOPBACKS;

	efx->link_advertising = (ADVERTISED_TP | ADVERTISED_Autoneg |
				 ADVERTISED_10000baseT_Full);

	return 0;
}

static int tenxpress_phy_init(struct ef4_nic *efx)
{
	int rc;

	falcon_board(efx)->type->init_phy(efx);

	if (!(efx->phy_mode & PHY_MODE_SPECIAL)) {
		rc = ef4_mdio_wait_reset_mmds(efx, TENXPRESS_REQUIRED_DEVS);
		if (rc < 0)
			return rc;

		rc = ef4_mdio_check_mmds(efx, TENXPRESS_REQUIRED_DEVS);
		if (rc < 0)
			return rc;
	}

	rc = tenxpress_init(efx);
	if (rc < 0)
		return rc;

	/* Reinitialise flow control settings */
	ef4_link_set_wanted_fc(efx, efx->wanted_fc);
	ef4_mdio_an_reconfigure(efx);

	schedule_timeout_uninterruptible(HZ / 5); /* 200ms */

	/* Let XGXS and SerDes out of reset */
	falcon_reset_xaui(efx);

	return 0;
}

/* Perform a "special software reset" on the PHY. The caller is
 * responsible for saving and restoring the PHY hardware registers
 * properly, and masking/unmasking LASI */
static int tenxpress_special_reset(struct ef4_nic *efx)
{
	int rc, reg;

	/* The XGMAC clock is driven from the SFX7101 312MHz clock, so
	 * a special software reset can glitch the XGMAC sufficiently for stats
	 * requests to fail. */
	falcon_stop_nic_stats(efx);

	/* Initiate reset */
	reg = ef4_mdio_read(efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG);
	reg |= (1 << PMA_PMD_EXT_SSR_LBN);
	ef4_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG, reg);

	mdelay(200);

	/* Wait for the blocks to come out of reset */
	rc = ef4_mdio_wait_reset_mmds(efx, TENXPRESS_REQUIRED_DEVS);
	if (rc < 0)
		goto out;

	/* Try and reconfigure the device */
	rc = tenxpress_init(efx);
	if (rc < 0)
		goto out;

	/* Wait for the XGXS state machine to churn */
	mdelay(10);
out:
	falcon_start_nic_stats(efx);
	return rc;
}

static void sfx7101_check_bad_lp(struct ef4_nic *efx, bool link_ok)
{
	struct tenxpress_phy_data *pd = efx->phy_data;
	bool bad_lp;
	int reg;

	if (link_ok) {
		bad_lp = false;
	} else {
		/* Check that AN has started but not completed. */
		reg = ef4_mdio_read(efx, MDIO_MMD_AN, MDIO_STAT1);
		if (!(reg & MDIO_AN_STAT1_LPABLE))
			return; /* LP status is unknown */
		bad_lp = !(reg & MDIO_AN_STAT1_COMPLETE);
		if (bad_lp)
			pd->bad_lp_tries++;
	}

	/* Nothing to do if all is well and was previously so. */
	if (!pd->bad_lp_tries)
		return;

	/* Use the RX (red) LED as an error indicator once we've seen AN
	 * failure several times in a row, and also log a message. */
	if (!bad_lp || pd->bad_lp_tries == MAX_BAD_LP_TRIES) {
		reg = ef4_mdio_read(efx, MDIO_MMD_PMAPMD,
				    PMA_PMD_LED_OVERR_REG);
		reg &= ~(PMA_PMD_LED_MASK << PMA_PMD_LED_RX_LBN);
		if (!bad_lp) {
			reg |= PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN;
		} else {
			reg |= PMA_PMD_LED_FLASH << PMA_PMD_LED_RX_LBN;
			netif_err(efx, link, efx->net_dev,
				  "appears to be plugged into a port"
				  " that is not 10GBASE-T capable. The PHY"
				  " supports 10GBASE-T ONLY, so no link can"
				  " be established\n");
		}
		ef4_mdio_write(efx, MDIO_MMD_PMAPMD,
			       PMA_PMD_LED_OVERR_REG, reg);
		pd->bad_lp_tries = bad_lp;
	}
}

static bool sfx7101_link_ok(struct ef4_nic *efx)
{
	return ef4_mdio_links_ok(efx,
				 MDIO_DEVS_PMAPMD |
				 MDIO_DEVS_PCS |
				 MDIO_DEVS_PHYXS);
}

static void tenxpress_ext_loopback(struct ef4_nic *efx)
{
	ef4_mdio_set_flag(efx, MDIO_MMD_PHYXS, PHYXS_TEST1,
			  1 << LOOPBACK_NEAR_LBN,
			  efx->loopback_mode == LOOPBACK_PHYXS);
}

static void tenxpress_low_power(struct ef4_nic *efx)
{
	ef4_mdio_set_mmds_lpower(
		efx, !!(efx->phy_mode & PHY_MODE_LOW_POWER),
		TENXPRESS_REQUIRED_DEVS);
}

static int tenxpress_phy_reconfigure(struct ef4_nic *efx)
{
	struct tenxpress_phy_data *phy_data = efx->phy_data;
	bool phy_mode_change, loop_reset;

	if (efx->phy_mode & (PHY_MODE_OFF | PHY_MODE_SPECIAL)) {
		phy_data->phy_mode = efx->phy_mode;
		return 0;
	}

	phy_mode_change = (efx->phy_mode == PHY_MODE_NORMAL &&
			   phy_data->phy_mode != PHY_MODE_NORMAL);
	loop_reset = (LOOPBACK_OUT_OF(phy_data, efx, LOOPBACKS_EXTERNAL(efx)) ||
		      LOOPBACK_CHANGED(phy_data, efx, 1 << LOOPBACK_GPHY));

	if (loop_reset || phy_mode_change) {
		tenxpress_special_reset(efx);
		falcon_reset_xaui(efx);
	}

	tenxpress_low_power(efx);
	ef4_mdio_transmit_disable(efx);
	ef4_mdio_phy_reconfigure(efx);
	tenxpress_ext_loopback(efx);
	ef4_mdio_an_reconfigure(efx);

	phy_data->loopback_mode = efx->loopback_mode;
	phy_data->phy_mode = efx->phy_mode;

	return 0;
}

/* Poll for link state changes */
static bool tenxpress_phy_poll(struct ef4_nic *efx)
{
	struct ef4_link_state old_state = efx->link_state;

	efx->link_state.up = sfx7101_link_ok(efx);
	efx->link_state.speed = 10000;
	efx->link_state.fd = true;
	efx->link_state.fc = ef4_mdio_get_pause(efx);

	sfx7101_check_bad_lp(efx, efx->link_state.up);

	return !ef4_link_state_equal(&efx->link_state, &old_state);
}

static void sfx7101_phy_fini(struct ef4_nic *efx)
{
	int reg;

	/* Power down the LNPGA */
	reg = (1 << PMA_PMD_LNPGA_POWERDOWN_LBN);
	ef4_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG, reg);

	/* Waiting here ensures that the board fini, which can turn
	 * off the power to the PHY, won't get run until the LNPGA
	 * powerdown has been given long enough to complete. */
	schedule_timeout_uninterruptible(LNPGA_PDOWN_WAIT); /* 200 ms */
}

static void tenxpress_phy_remove(struct ef4_nic *efx)
{
	kfree(efx->phy_data);
	efx->phy_data = NULL;
}


/* Override the RX, TX and link LEDs */
void tenxpress_set_id_led(struct ef4_nic *efx, enum ef4_led_mode mode)
{
	int reg;

	switch (mode) {
	case EF4_LED_OFF:
		reg = (PMA_PMD_LED_OFF << PMA_PMD_LED_TX_LBN) |
			(PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN) |
			(PMA_PMD_LED_OFF << PMA_PMD_LED_LINK_LBN);
		break;
	case EF4_LED_ON:
		reg = (PMA_PMD_LED_ON << PMA_PMD_LED_TX_LBN) |
			(PMA_PMD_LED_ON << PMA_PMD_LED_RX_LBN) |
			(PMA_PMD_LED_ON << PMA_PMD_LED_LINK_LBN);
		break;
	default:
		reg = SFX7101_PMA_PMD_LED_DEFAULT;
		break;
	}

	ef4_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_LED_OVERR_REG, reg);
}

static const char *const sfx7101_test_names[] = {
	"bist"
};

static const char *sfx7101_test_name(struct ef4_nic *efx, unsigned int index)
{
	if (index < ARRAY_SIZE(sfx7101_test_names))
		return sfx7101_test_names[index];
	return NULL;
}

static int
sfx7101_run_tests(struct ef4_nic *efx, int *results, unsigned flags)
{
	int rc;

	if (!(flags & ETH_TEST_FL_OFFLINE))
		return 0;

	/* BIST is automatically run after a special software reset */
	rc = tenxpress_special_reset(efx);
	results[0] = rc ? -1 : 1;

	ef4_mdio_an_reconfigure(efx);

	return rc;
}

static void
tenxpress_get_link_ksettings(struct ef4_nic *efx,
			     struct ethtool_link_ksettings *cmd)
{
	u32 adv = 0, lpa = 0;
	int reg;

	reg = ef4_mdio_read(efx, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL);
	if (reg & MDIO_AN_10GBT_CTRL_ADV10G)
		adv |= ADVERTISED_10000baseT_Full;
	reg = ef4_mdio_read(efx, MDIO_MMD_AN, MDIO_AN_10GBT_STAT);
	if (reg & MDIO_AN_10GBT_STAT_LP10G)
		lpa |= ADVERTISED_10000baseT_Full;

	mdio45_ethtool_ksettings_get_npage(&efx->mdio, cmd, adv, lpa);

	/* In loopback, the PHY automatically brings up the correct interface,
	 * but doesn't advertise the correct speed. So override it */
	if (LOOPBACK_EXTERNAL(efx))
		cmd->base.speed = SPEED_10000;
}

static int
tenxpress_set_link_ksettings(struct ef4_nic *efx,
			     const struct ethtool_link_ksettings *cmd)
{
	if (!cmd->base.autoneg)
		return -EINVAL;

	return ef4_mdio_set_link_ksettings(efx, cmd);
}

static void sfx7101_set_npage_adv(struct ef4_nic *efx, u32 advertising)
{
	ef4_mdio_set_flag(efx, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
			  MDIO_AN_10GBT_CTRL_ADV10G,
			  advertising & ADVERTISED_10000baseT_Full);
}

const struct ef4_phy_operations falcon_sfx7101_phy_ops = {
	.probe		  = tenxpress_phy_probe,
	.init             = tenxpress_phy_init,
	.reconfigure      = tenxpress_phy_reconfigure,
	.poll             = tenxpress_phy_poll,
	.fini             = sfx7101_phy_fini,
	.remove		  = tenxpress_phy_remove,
	.get_link_ksettings = tenxpress_get_link_ksettings,
	.set_link_ksettings = tenxpress_set_link_ksettings,
	.set_npage_adv    = sfx7101_set_npage_adv,
	.test_alive	  = ef4_mdio_test_alive,
	.test_name	  = sfx7101_test_name,
	.run_tests	  = sfx7101_run_tests,
};
Commit	Line	Data
d2912cb1	1	// SPDX-License-Identifier: GPL-2.0-only
8ceee660	2	/****************************************************************************
f7a6d2c4	3	* Driver for Solarflare network controllers and boards
0a6f40c6	4	* Copyright 2007-2011 Solarflare Communications Inc.
8ceee660 BH	5	*/
	6
	7	#include <linux/delay.h>
da3bc071	8	#include <linux/rtnetlink.h>
8ceee660	9	#include <linux/seq_file.h>
5a0e3ad6	10	#include <linux/slab.h>
8ceee660	11	#include "efx.h"
8ceee660	12	#include "mdio_10g.h"
744093c9	13	#include "nic.h"
8ceee660	14	#include "phy.h"
e6fa2eb7	15	#include "workarounds.h"
8ceee660	16
8fbca791	17	/* We expect these MMDs to be in the package. */
68e7f45e BH	18	#define TENXPRESS_REQUIRED_DEVS (MDIO_DEVS_PMAPMD \| \
	19	MDIO_DEVS_PCS \| \
	20	MDIO_DEVS_PHYXS \| \
	21	MDIO_DEVS_AN)
8ceee660	22
e6fa2eb7 BH	23	#define SFX7101_LOOPBACKS ((1 << LOOPBACK_PHYXS) \| \
	24	(1 << LOOPBACK_PCS) \| \
	25	(1 << LOOPBACK_PMAPMD) \| \
e58f69f4	26	(1 << LOOPBACK_PHYXS_WS))
e6fa2eb7	27
8ceee660 BH	28	/* We complain if we fail to see the link partner as 10G capable this many
	29	* times in a row (must be > 1 as sampling the autoneg. registers is racy)
	30	*/
	31	#define MAX_BAD_LP_TRIES (5)
	32
	33	/* Extended control register */
e6fa2eb7 BH	34	#define PMA_PMD_XCONTROL_REG 49152
	35	#define PMA_PMD_EXT_GMII_EN_LBN 1
	36	#define PMA_PMD_EXT_GMII_EN_WIDTH 1
	37	#define PMA_PMD_EXT_CLK_OUT_LBN 2
	38	#define PMA_PMD_EXT_CLK_OUT_WIDTH 1
8fbca791	39	#define PMA_PMD_LNPGA_POWERDOWN_LBN 8
e6fa2eb7	40	#define PMA_PMD_LNPGA_POWERDOWN_WIDTH 1
e6fa2eb7 BH	41	#define PMA_PMD_EXT_CLK312_WIDTH 1
	42	#define PMA_PMD_EXT_LPOWER_LBN 12
	43	#define PMA_PMD_EXT_LPOWER_WIDTH 1
869b5b38 SH	44	#define PMA_PMD_EXT_ROBUST_LBN 14
869b5b38 SH	45	#define PMA_PMD_EXT_ROBUST_WIDTH 1
e6fa2eb7 BH	46	#define PMA_PMD_EXT_SSR_LBN 15
e6fa2eb7 BH	47	#define PMA_PMD_EXT_SSR_WIDTH 1
8ceee660 BH	48
8ceee660 BH	49	/* extended status register */
e6fa2eb7	50	#define PMA_PMD_XSTATUS_REG 49153
e762cd70	51	#define PMA_PMD_XSTAT_MDIX_LBN 14
8ceee660 BH	52	#define PMA_PMD_XSTAT_FLP_LBN (12)
	53
	54	/* LED control register */
e6fa2eb7	55	#define PMA_PMD_LED_CTRL_REG 49159
8ceee660 BH	56	#define PMA_PMA_LED_ACTIVITY_LBN (3)
	57
	58	/* LED function override register */
e6fa2eb7	59	#define PMA_PMD_LED_OVERR_REG 49161
8ceee660 BH	60	/* Bit positions for different LEDs (there are more but not wired on SFE4001)*/
	61	#define PMA_PMD_LED_LINK_LBN (0)
	62	#define PMA_PMD_LED_SPEED_LBN (2)
	63	#define PMA_PMD_LED_TX_LBN (4)
	64	#define PMA_PMD_LED_RX_LBN (6)
	65	/* Override settings */
	66	#define PMA_PMD_LED_AUTO (0) /* H/W control */
	67	#define PMA_PMD_LED_ON (1)
	68	#define PMA_PMD_LED_OFF (2)
	69	#define PMA_PMD_LED_FLASH (3)
04cc8cac	70	#define PMA_PMD_LED_MASK 3
8ceee660	71	/* All LEDs under hardware control */
8ceee660	72	/* Green and Amber under hardware control, Red off */
dcf477b2	73	#define SFX7101_PMA_PMD_LED_DEFAULT (PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN)
8ceee660	74
e6fa2eb7 BH	75	#define PMA_PMD_SPEED_ENABLE_REG 49192
	76	#define PMA_PMD_100TX_ADV_LBN 1
	77	#define PMA_PMD_100TX_ADV_WIDTH 1
	78	#define PMA_PMD_1000T_ADV_LBN 2
	79	#define PMA_PMD_1000T_ADV_WIDTH 1
	80	#define PMA_PMD_10000T_ADV_LBN 3
	81	#define PMA_PMD_10000T_ADV_WIDTH 1
	82	#define PMA_PMD_SPEED_LBN 4
	83	#define PMA_PMD_SPEED_WIDTH 4
	84
8fbca791	85	/* Misc register defines */
e6fa2eb7	86	#define PCS_CLOCK_CTRL_REG 55297
8ceee660 BH	87	#define PLL312_RST_N_LBN 2
8ceee660 BH	88
e6fa2eb7	89	#define PCS_SOFT_RST2_REG 55302
8ceee660 BH	90	#define SERDES_RST_N_LBN 13
	91	#define XGXS_RST_N_LBN 12
	92
e6fa2eb7	93	#define PCS_TEST_SELECT_REG 55303 /* PRM 10.5.8 */
8ceee660 BH	94	#define CLK312_EN_LBN 3
8ceee660 BH	95
3273c2e8	96	/* PHYXS registers */
e6fa2eb7 BH	97	#define PHYXS_XCONTROL_REG 49152
	98	#define PHYXS_RESET_LBN 15
	99	#define PHYXS_RESET_WIDTH 1
	100
3273c2e8 BH	101	#define PHYXS_TEST1 (49162)
	102	#define LOOPBACK_NEAR_LBN (8)
	103	#define LOOPBACK_NEAR_WIDTH (1)
	104
8ceee660	105	/* Boot status register */
190dbcfd BH	106	#define PCS_BOOT_STATUS_REG 53248
	107	#define PCS_BOOT_FATAL_ERROR_LBN 0
	108	#define PCS_BOOT_PROGRESS_LBN 1
	109	#define PCS_BOOT_PROGRESS_WIDTH 2
	110	#define PCS_BOOT_PROGRESS_INIT 0
	111	#define PCS_BOOT_PROGRESS_WAIT_MDIO 1
	112	#define PCS_BOOT_PROGRESS_CHECKSUM 2
	113	#define PCS_BOOT_PROGRESS_JUMP 3
	114	#define PCS_BOOT_DOWNLOAD_WAIT_LBN 3
	115	#define PCS_BOOT_CODE_STARTED_LBN 4
8ceee660	116
e6fa2eb7 BH	117	/* 100M/1G PHY registers */
	118	#define GPHY_XCONTROL_REG 49152
	119	#define GPHY_ISOLATE_LBN 10
	120	#define GPHY_ISOLATE_WIDTH 1
9c636baf	121	#define GPHY_DUPLEX_LBN 8
e6fa2eb7 BH	122	#define GPHY_DUPLEX_WIDTH 1
	123	#define GPHY_LOOPBACK_NEAR_LBN 14
	124	#define GPHY_LOOPBACK_NEAR_WIDTH 1
	125
	126	#define C22EXT_STATUS_REG 49153
	127	#define C22EXT_STATUS_LINK_LBN 2
	128	#define C22EXT_STATUS_LINK_WIDTH 1
	129
af4ad9bc BH	130	#define C22EXT_MSTSLV_CTRL 49161
	131	#define C22EXT_MSTSLV_CTRL_ADV_1000_HD_LBN 8
	132	#define C22EXT_MSTSLV_CTRL_ADV_1000_FD_LBN 9
	133
	134	#define C22EXT_MSTSLV_STATUS 49162
	135	#define C22EXT_MSTSLV_STATUS_LP_1000_HD_LBN 10
	136	#define C22EXT_MSTSLV_STATUS_LP_1000_FD_LBN 11
e6fa2eb7	137
8ceee660 BH	138	/* Time to wait between powering down the LNPGA and turning off the power
	139	* rails */
	140	#define LNPGA_PDOWN_WAIT (HZ / 5)
	141
8ceee660	142	struct tenxpress_phy_data {
5a6681e2 EC	143	enum ef4_loopback_mode loopback_mode;
5a6681e2 EC	144	enum ef4_phy_mode phy_mode;
8ceee660 BH	145	int bad_lp_tries;
	146	};
	147
5a6681e2	148	static int tenxpress_init(struct ef4_nic *efx)
8ceee660	149	{
8fbca791	150	/* Enable 312.5 MHz clock */
5a6681e2	151	ef4_mdio_write(efx, MDIO_MMD_PCS, PCS_TEST_SELECT_REG,
8fbca791	152	1 << CLK312_EN_LBN);
8ceee660	153
8ceee660	154	/* Set the LEDs up as: Green = Link, Amber = Link/Act, Red = Off */
5a6681e2	155	ef4_mdio_set_flag(efx, MDIO_MMD_PMAPMD, PMA_PMD_LED_CTRL_REG,
8fbca791	156	1 << PMA_PMA_LED_ACTIVITY_LBN, true);
5a6681e2	157	ef4_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_LED_OVERR_REG,
8fbca791	158	SFX7101_PMA_PMD_LED_DEFAULT);
8ceee660	159
190dbcfd	160	return 0;
8ceee660 BH	161	}
8ceee660 BH	162
5a6681e2	163	static int tenxpress_phy_probe(struct ef4_nic *efx)
c1c4f453	164	{
ff3b00a0	165	struct tenxpress_phy_data *phy_data;
ff3b00a0 SH	166
	167	/* Allocate phy private storage */
	168	phy_data = kzalloc(sizeof(*phy_data), GFP_KERNEL);
	169	if (!phy_data)
	170	return -ENOMEM;
	171	efx->phy_data = phy_data;
	172	phy_data->phy_mode = efx->phy_mode;
	173
8fbca791 BH	174	efx->mdio.mmds = TENXPRESS_REQUIRED_DEVS;
8fbca791 BH	175	efx->mdio.mode_support = MDIO_SUPPORTS_C45;
ff3b00a0	176
8fbca791	177	efx->loopback_modes = SFX7101_LOOPBACKS \| FALCON_XMAC_LOOPBACKS;
ff3b00a0	178
8fbca791 BH	179	efx->link_advertising = (ADVERTISED_TP \| ADVERTISED_Autoneg \|
8fbca791 BH	180	ADVERTISED_10000baseT_Full);
c1c4f453	181
c1c4f453 BH	182	return 0;
	183	}
	184
5a6681e2	185	static int tenxpress_phy_init(struct ef4_nic *efx)
8ceee660	186	{
ff3b00a0	187	int rc;
8ceee660	188
44838a44	189	falcon_board(efx)->type->init_phy(efx);
981fc1b4	190
e6fa2eb7	191	if (!(efx->phy_mode & PHY_MODE_SPECIAL)) {
5a6681e2	192	rc = ef4_mdio_wait_reset_mmds(efx, TENXPRESS_REQUIRED_DEVS);
e6fa2eb7	193	if (rc < 0)
ff3b00a0	194	return rc;
e6fa2eb7	195
5a6681e2	196	rc = ef4_mdio_check_mmds(efx, TENXPRESS_REQUIRED_DEVS);
e6fa2eb7	197	if (rc < 0)
ff3b00a0	198	return rc;
e6fa2eb7	199	}
8ceee660 BH	200
	201	rc = tenxpress_init(efx);
	202	if (rc < 0)
ff3b00a0	203	return rc;
8ceee660	204
ff3b00a0	205	/* Reinitialise flow control settings */
5a6681e2 EC	206	ef4_link_set_wanted_fc(efx, efx->wanted_fc);
5a6681e2 EC	207	ef4_mdio_an_reconfigure(efx);
c634263d	208
8ceee660 BH	209	schedule_timeout_uninterruptible(HZ / 5); /* 200ms */
8ceee660 BH	210
e6fa2eb7	211	/* Let XGXS and SerDes out of reset */
8ceee660 BH	212	falcon_reset_xaui(efx);
	213
	214	return 0;
8ceee660 BH	215	}
8ceee660 BH	216
e6fa2eb7 BH	217	/* Perform a "special software reset" on the PHY. The caller is
	218	* responsible for saving and restoring the PHY hardware registers
	219	* properly, and masking/unmasking LASI */
5a6681e2	220	static int tenxpress_special_reset(struct ef4_nic *efx)
3273c2e8 BH	221	{
	222	int rc, reg;
	223
8fbca791	224	/* The XGMAC clock is driven from the SFX7101 312MHz clock, so
c8fcc49c	225	* a special software reset can glitch the XGMAC sufficiently for stats
1974cc20	226	* requests to fail. */
55edc6e6	227	falcon_stop_nic_stats(efx);
3273c2e8 BH	228
3273c2e8 BH	229	/* Initiate reset */
5a6681e2	230	reg = ef4_mdio_read(efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG);
3273c2e8	231	reg \|= (1 << PMA_PMD_EXT_SSR_LBN);
5a6681e2	232	ef4_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG, reg);
3273c2e8	233
c8fcc49c	234	mdelay(200);
3273c2e8 BH	235
3273c2e8 BH	236	/* Wait for the blocks to come out of reset */
5a6681e2	237	rc = ef4_mdio_wait_reset_mmds(efx, TENXPRESS_REQUIRED_DEVS);
3273c2e8	238	if (rc < 0)
1974cc20	239	goto out;
3273c2e8 BH	240
	241	/* Try and reconfigure the device */
	242	rc = tenxpress_init(efx);
	243	if (rc < 0)
1974cc20	244	goto out;
3273c2e8	245
e6fa2eb7 BH	246	/* Wait for the XGXS state machine to churn */
e6fa2eb7 BH	247	mdelay(10);
1974cc20	248	out:
55edc6e6	249	falcon_start_nic_stats(efx);
c8fcc49c	250	return rc;
3273c2e8 BH	251	}
3273c2e8 BH	252
5a6681e2	253	static void sfx7101_check_bad_lp(struct ef4_nic *efx, bool link_ok)
8ceee660 BH	254	{
8ceee660 BH	255	struct tenxpress_phy_data *pd = efx->phy_data;
04cc8cac	256	bool bad_lp;
8ceee660 BH	257	int reg;
8ceee660 BH	258
04cc8cac BH	259	if (link_ok) {
	260	bad_lp = false;
	261	} else {
	262	/* Check that AN has started but not completed. */
5a6681e2	263	reg = ef4_mdio_read(efx, MDIO_MMD_AN, MDIO_STAT1);
68e7f45e	264	if (!(reg & MDIO_AN_STAT1_LPABLE))
04cc8cac	265	return; /* LP status is unknown */
68e7f45e	266	bad_lp = !(reg & MDIO_AN_STAT1_COMPLETE);
04cc8cac BH	267	if (bad_lp)
	268	pd->bad_lp_tries++;
	269	}
	270
8ceee660	271	/* Nothing to do if all is well and was previously so. */
04cc8cac	272	if (!pd->bad_lp_tries)
8ceee660 BH	273	return;
8ceee660 BH	274
04cc8cac BH	275	/* Use the RX (red) LED as an error indicator once we've seen AN
	276	* failure several times in a row, and also log a message. */
	277	if (!bad_lp \|\| pd->bad_lp_tries == MAX_BAD_LP_TRIES) {
5a6681e2	278	reg = ef4_mdio_read(efx, MDIO_MMD_PMAPMD,
68e7f45e	279	PMA_PMD_LED_OVERR_REG);
04cc8cac BH	280	reg &= ~(PMA_PMD_LED_MASK << PMA_PMD_LED_RX_LBN);
	281	if (!bad_lp) {
	282	reg \|= PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN;
	283	} else {
	284	reg \|= PMA_PMD_LED_FLASH << PMA_PMD_LED_RX_LBN;
62776d03 BH	285	netif_err(efx, link, efx->net_dev,
	286	"appears to be plugged into a port"
	287	" that is not 10GBASE-T capable. The PHY"
	288	" supports 10GBASE-T ONLY, so no link can"
	289	" be established\n");
04cc8cac	290	}
5a6681e2	291	ef4_mdio_write(efx, MDIO_MMD_PMAPMD,
68e7f45e	292	PMA_PMD_LED_OVERR_REG, reg);
04cc8cac	293	pd->bad_lp_tries = bad_lp;
8ceee660	294	}
8ceee660 BH	295	}
8ceee660 BH	296
5a6681e2	297	static bool sfx7101_link_ok(struct ef4_nic *efx)
8ceee660	298	{
5a6681e2	299	return ef4_mdio_links_ok(efx,
68e7f45e BH	300	MDIO_DEVS_PMAPMD \|
	301	MDIO_DEVS_PCS \|
	302	MDIO_DEVS_PHYXS);
e6fa2eb7 BH	303	}
e6fa2eb7 BH	304
5a6681e2	305	static void tenxpress_ext_loopback(struct ef4_nic *efx)
3273c2e8	306	{
5a6681e2	307	ef4_mdio_set_flag(efx, MDIO_MMD_PHYXS, PHYXS_TEST1,
68e7f45e BH	308	1 << LOOPBACK_NEAR_LBN,
68e7f45e BH	309	efx->loopback_mode == LOOPBACK_PHYXS);
e6fa2eb7 BH	310	}
e6fa2eb7 BH	311
5a6681e2	312	static void tenxpress_low_power(struct ef4_nic *efx)
e6fa2eb7	313	{
5a6681e2	314	ef4_mdio_set_mmds_lpower(
8fbca791 BH	315	efx, !!(efx->phy_mode & PHY_MODE_LOW_POWER),
8fbca791 BH	316	TENXPRESS_REQUIRED_DEVS);
3273c2e8 BH	317	}
3273c2e8 BH	318
5a6681e2	319	static int tenxpress_phy_reconfigure(struct ef4_nic *efx)
8ceee660	320	{
3273c2e8	321	struct tenxpress_phy_data *phy_data = efx->phy_data;
8b9dc8dd	322	bool phy_mode_change, loop_reset;
3273c2e8	323
e6fa2eb7	324	if (efx->phy_mode & (PHY_MODE_OFF \| PHY_MODE_SPECIAL)) {
f8b87c17	325	phy_data->phy_mode = efx->phy_mode;
d3245b28	326	return 0;
f8b87c17	327	}
8ceee660	328
e6fa2eb7 BH	329	phy_mode_change = (efx->phy_mode == PHY_MODE_NORMAL &&
e6fa2eb7 BH	330	phy_data->phy_mode != PHY_MODE_NORMAL);
c1c4f453	331	loop_reset = (LOOPBACK_OUT_OF(phy_data, efx, LOOPBACKS_EXTERNAL(efx)) \|\|
e6fa2eb7 BH	332	LOOPBACK_CHANGED(phy_data, efx, 1 << LOOPBACK_GPHY));
e6fa2eb7 BH	333
8b9dc8dd	334	if (loop_reset \|\| phy_mode_change) {
d3245b28	335	tenxpress_special_reset(efx);
8fbca791	336	falcon_reset_xaui(efx);
3273c2e8 BH	337	}
3273c2e8 BH	338
d3245b28	339	tenxpress_low_power(efx);
5a6681e2 EC	340	ef4_mdio_transmit_disable(efx);
5a6681e2 EC	341	ef4_mdio_phy_reconfigure(efx);
e6fa2eb7	342	tenxpress_ext_loopback(efx);
5a6681e2	343	ef4_mdio_an_reconfigure(efx);
3273c2e8	344
3273c2e8	345	phy_data->loopback_mode = efx->loopback_mode;
f8b87c17	346	phy_data->phy_mode = efx->phy_mode;
d3245b28 BH	347
d3245b28 BH	348	return 0;
8ceee660 BH	349	}
8ceee660 BH	350
fdaa9aed	351	/* Poll for link state changes */
5a6681e2	352	static bool tenxpress_phy_poll(struct ef4_nic *efx)
8ceee660	353	{
5a6681e2	354	struct ef4_link_state old_state = efx->link_state;
8ceee660	355
8fbca791 BH	356	efx->link_state.up = sfx7101_link_ok(efx);
	357	efx->link_state.speed = 10000;
	358	efx->link_state.fd = true;
5a6681e2	359	efx->link_state.fc = ef4_mdio_get_pause(efx);
8ceee660	360
8fbca791	361	sfx7101_check_bad_lp(efx, efx->link_state.up);
fdaa9aed	362
5a6681e2	363	return !ef4_link_state_equal(&efx->link_state, &old_state);
8ceee660 BH	364	}
8ceee660 BH	365
5a6681e2	366	static void sfx7101_phy_fini(struct ef4_nic *efx)
8ceee660 BH	367	{
	368	int reg;
	369
ff3b00a0 SH	370	/* Power down the LNPGA */
ff3b00a0 SH	371	reg = (1 << PMA_PMD_LNPGA_POWERDOWN_LBN);
5a6681e2	372	ef4_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG, reg);
ff3b00a0 SH	373
	374	/* Waiting here ensures that the board fini, which can turn
	375	* off the power to the PHY, won't get run until the LNPGA
	376	* powerdown has been given long enough to complete. */
	377	schedule_timeout_uninterruptible(LNPGA_PDOWN_WAIT); /* 200 ms */
	378	}
	379
5a6681e2	380	static void tenxpress_phy_remove(struct ef4_nic *efx)
ff3b00a0	381	{
8ceee660 BH	382	kfree(efx->phy_data);
	383	efx->phy_data = NULL;
	384	}
	385
	386
398468ed	387	/* Override the RX, TX and link LEDs */
5a6681e2	388	void tenxpress_set_id_led(struct ef4_nic *efx, enum ef4_led_mode mode)
8ceee660 BH	389	{
	390	int reg;
	391
398468ed	392	switch (mode) {
5a6681e2	393	case EF4_LED_OFF:
398468ed BH	394	reg = (PMA_PMD_LED_OFF << PMA_PMD_LED_TX_LBN) \|
	395	(PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN) \|
	396	(PMA_PMD_LED_OFF << PMA_PMD_LED_LINK_LBN);
	397	break;
5a6681e2	398	case EF4_LED_ON:
398468ed BH	399	reg = (PMA_PMD_LED_ON << PMA_PMD_LED_TX_LBN) \|
	400	(PMA_PMD_LED_ON << PMA_PMD_LED_RX_LBN) \|
	401	(PMA_PMD_LED_ON << PMA_PMD_LED_LINK_LBN);
	402	break;
	403	default:
8fbca791	404	reg = SFX7101_PMA_PMD_LED_DEFAULT;
398468ed BH	405	break;
398468ed BH	406	}
8ceee660	407
5a6681e2	408	ef4_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_LED_OVERR_REG, reg);
8ceee660 BH	409	}
8ceee660 BH	410
307505e9	411	static const char *const sfx7101_test_names[] = {
1796721a BH	412	"bist"
	413	};
	414
5a6681e2	415	static const char sfx7101_test_name(struct ef4_nic efx, unsigned int index)
c1c4f453 BH	416	{
	417	if (index < ARRAY_SIZE(sfx7101_test_names))
	418	return sfx7101_test_names[index];
	419	return NULL;
	420	}
	421
1796721a	422	static int
5a6681e2	423	sfx7101_run_tests(struct ef4_nic efx, int results, unsigned flags)
8c8661e4	424	{
1796721a BH	425	int rc;
	426
	427	if (!(flags & ETH_TEST_FL_OFFLINE))
	428	return 0;
	429
8c8661e4	430	/* BIST is automatically run after a special software reset */
1796721a BH	431	rc = tenxpress_special_reset(efx);
1796721a BH	432	results[0] = rc ? -1 : 1;
d3245b28	433
5a6681e2	434	ef4_mdio_an_reconfigure(efx);
d3245b28	435
1796721a	436	return rc;
8c8661e4 BH	437	}
8c8661e4 BH	438
af4ad9bc	439	static void
e938ed15 PR	440	tenxpress_get_link_ksettings(struct ef4_nic *efx,
e938ed15 PR	441	struct ethtool_link_ksettings *cmd)
04cc8cac	442	{
af4ad9bc	443	u32 adv = 0, lpa = 0;
04cc8cac BH	444	int reg;
04cc8cac BH	445
5a6681e2	446	reg = ef4_mdio_read(efx, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL);
68e7f45e	447	if (reg & MDIO_AN_10GBT_CTRL_ADV10G)
af4ad9bc	448	adv \|= ADVERTISED_10000baseT_Full;
5a6681e2	449	reg = ef4_mdio_read(efx, MDIO_MMD_AN, MDIO_AN_10GBT_STAT);
68e7f45e	450	if (reg & MDIO_AN_10GBT_STAT_LP10G)
04cc8cac	451	lpa \|= ADVERTISED_10000baseT_Full;
04cc8cac	452
e938ed15	453	mdio45_ethtool_ksettings_get_npage(&efx->mdio, cmd, adv, lpa);
e6fa2eb7	454
8b9dc8dd SH	455	/* In loopback, the PHY automatically brings up the correct interface,
8b9dc8dd SH	456	* but doesn't advertise the correct speed. So override it */
8fbca791	457	if (LOOPBACK_EXTERNAL(efx))
e938ed15	458	cmd->base.speed = SPEED_10000;
04cc8cac BH	459	}
04cc8cac BH	460
e938ed15 PR	461	static int
	462	tenxpress_set_link_ksettings(struct ef4_nic *efx,
	463	const struct ethtool_link_ksettings *cmd)
e6fa2eb7	464	{
e938ed15	465	if (!cmd->base.autoneg)
af4ad9bc	466	return -EINVAL;
e6fa2eb7	467
e938ed15	468	return ef4_mdio_set_link_ksettings(efx, cmd);
e6fa2eb7 BH	469	}
e6fa2eb7 BH	470
5a6681e2	471	static void sfx7101_set_npage_adv(struct ef4_nic *efx, u32 advertising)
e6fa2eb7	472	{
5a6681e2	473	ef4_mdio_set_flag(efx, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
68e7f45e BH	474	MDIO_AN_10GBT_CTRL_ADV10G,
68e7f45e BH	475	advertising & ADVERTISED_10000baseT_Full);
e6fa2eb7 BH	476	}
e6fa2eb7 BH	477
5a6681e2	478	const struct ef4_phy_operations falcon_sfx7101_phy_ops = {
ff3b00a0	479	.probe = tenxpress_phy_probe,
8ceee660 BH	480	.init = tenxpress_phy_init,
8ceee660 BH	481	.reconfigure = tenxpress_phy_reconfigure,
766ca0fa	482	.poll = tenxpress_phy_poll,
ff3b00a0 SH	483	.fini = sfx7101_phy_fini,
ff3b00a0 SH	484	.remove = tenxpress_phy_remove,
e938ed15 PR	485	.get_link_ksettings = tenxpress_get_link_ksettings,
e938ed15 PR	486	.set_link_ksettings = tenxpress_set_link_ksettings,
af4ad9bc	487	.set_npage_adv = sfx7101_set_npage_adv,
5a6681e2	488	.test_alive = ef4_mdio_test_alive,
c1c4f453	489	.test_name = sfx7101_test_name,
307505e9	490	.run_tests = sfx7101_run_tests,
e6fa2eb7	491	};