]>
Commit | Line | Data |
---|---|---|
8ceee660 BH |
1 | /**************************************************************************** |
2 | * Driver for Solarflare Solarstorm network controllers and boards | |
3 | * Copyright 2005-2006 Fen Systems Ltd. | |
0a6f40c6 | 4 | * Copyright 2006-2010 Solarflare Communications Inc. |
8ceee660 BH |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation, incorporated herein by reference. | |
9 | */ | |
10 | ||
11 | #include <linux/bitops.h> | |
12 | #include <linux/delay.h> | |
13 | #include <linux/pci.h> | |
14 | #include <linux/module.h> | |
15 | #include <linux/seq_file.h> | |
37b5a603 | 16 | #include <linux/i2c.h> |
f31a45d2 | 17 | #include <linux/mii.h> |
5a0e3ad6 | 18 | #include <linux/slab.h> |
8ceee660 BH |
19 | #include "net_driver.h" |
20 | #include "bitfield.h" | |
21 | #include "efx.h" | |
8ceee660 | 22 | #include "spi.h" |
744093c9 | 23 | #include "nic.h" |
3e6c4538 | 24 | #include "regs.h" |
12d00cad | 25 | #include "io.h" |
8ceee660 | 26 | #include "phy.h" |
8ceee660 | 27 | #include "workarounds.h" |
d4f2cecc | 28 | #include "selftest.h" |
8ceee660 | 29 | |
8986352a | 30 | /* Hardware control for SFC4000 (aka Falcon). */ |
8ceee660 | 31 | |
d4f2cecc BH |
32 | static int falcon_reset_hw(struct efx_nic *efx, enum reset_type method); |
33 | ||
2f7f5730 BH |
34 | static const unsigned int |
35 | /* "Large" EEPROM device: Atmel AT25640 or similar | |
36 | * 8 KB, 16-bit address, 32 B write block */ | |
37 | large_eeprom_type = ((13 << SPI_DEV_TYPE_SIZE_LBN) | |
38 | | (2 << SPI_DEV_TYPE_ADDR_LEN_LBN) | |
39 | | (5 << SPI_DEV_TYPE_BLOCK_SIZE_LBN)), | |
40 | /* Default flash device: Atmel AT25F1024 | |
41 | * 128 KB, 24-bit address, 32 KB erase block, 256 B write block */ | |
42 | default_flash_type = ((17 << SPI_DEV_TYPE_SIZE_LBN) | |
43 | | (3 << SPI_DEV_TYPE_ADDR_LEN_LBN) | |
44 | | (0x52 << SPI_DEV_TYPE_ERASE_CMD_LBN) | |
45 | | (15 << SPI_DEV_TYPE_ERASE_SIZE_LBN) | |
46 | | (8 << SPI_DEV_TYPE_BLOCK_SIZE_LBN)); | |
47 | ||
8ceee660 BH |
48 | /************************************************************************** |
49 | * | |
50 | * I2C bus - this is a bit-bashing interface using GPIO pins | |
51 | * Note that it uses the output enables to tristate the outputs | |
52 | * SDA is the data pin and SCL is the clock | |
53 | * | |
54 | ************************************************************************** | |
55 | */ | |
37b5a603 | 56 | static void falcon_setsda(void *data, int state) |
8ceee660 | 57 | { |
37b5a603 | 58 | struct efx_nic *efx = (struct efx_nic *)data; |
8ceee660 BH |
59 | efx_oword_t reg; |
60 | ||
12d00cad | 61 | efx_reado(efx, ®, FR_AB_GPIO_CTL); |
3e6c4538 | 62 | EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO3_OEN, !state); |
12d00cad | 63 | efx_writeo(efx, ®, FR_AB_GPIO_CTL); |
8ceee660 BH |
64 | } |
65 | ||
37b5a603 | 66 | static void falcon_setscl(void *data, int state) |
8ceee660 | 67 | { |
37b5a603 | 68 | struct efx_nic *efx = (struct efx_nic *)data; |
8ceee660 BH |
69 | efx_oword_t reg; |
70 | ||
12d00cad | 71 | efx_reado(efx, ®, FR_AB_GPIO_CTL); |
3e6c4538 | 72 | EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO0_OEN, !state); |
12d00cad | 73 | efx_writeo(efx, ®, FR_AB_GPIO_CTL); |
37b5a603 BH |
74 | } |
75 | ||
8e730c15 BH |
76 | static int falcon_getsda(void *data) |
77 | { | |
78 | struct efx_nic *efx = (struct efx_nic *)data; | |
79 | efx_oword_t reg; | |
8ceee660 | 80 | |
8e730c15 BH |
81 | efx_reado(efx, ®, FR_AB_GPIO_CTL); |
82 | return EFX_OWORD_FIELD(reg, FRF_AB_GPIO3_IN); | |
83 | } | |
8ceee660 | 84 | |
8e730c15 BH |
85 | static int falcon_getscl(void *data) |
86 | { | |
87 | struct efx_nic *efx = (struct efx_nic *)data; | |
88 | efx_oword_t reg; | |
8ceee660 | 89 | |
8e730c15 BH |
90 | efx_reado(efx, ®, FR_AB_GPIO_CTL); |
91 | return EFX_OWORD_FIELD(reg, FRF_AB_GPIO0_IN); | |
8ceee660 BH |
92 | } |
93 | ||
18e83e4c | 94 | static const struct i2c_algo_bit_data falcon_i2c_bit_operations = { |
8e730c15 BH |
95 | .setsda = falcon_setsda, |
96 | .setscl = falcon_setscl, | |
97 | .getsda = falcon_getsda, | |
98 | .getscl = falcon_getscl, | |
99 | .udelay = 5, | |
100 | /* Wait up to 50 ms for slave to let us pull SCL high */ | |
101 | .timeout = DIV_ROUND_UP(HZ, 20), | |
102 | }; | |
103 | ||
ef2b90ee | 104 | static void falcon_push_irq_moderation(struct efx_channel *channel) |
8ceee660 BH |
105 | { |
106 | efx_dword_t timer_cmd; | |
107 | struct efx_nic *efx = channel->efx; | |
108 | ||
109 | /* Set timer register */ | |
110 | if (channel->irq_moderation) { | |
8ceee660 | 111 | EFX_POPULATE_DWORD_2(timer_cmd, |
3e6c4538 BH |
112 | FRF_AB_TC_TIMER_MODE, |
113 | FFE_BB_TIMER_MODE_INT_HLDOFF, | |
114 | FRF_AB_TC_TIMER_VAL, | |
0d86ebd8 | 115 | channel->irq_moderation - 1); |
8ceee660 BH |
116 | } else { |
117 | EFX_POPULATE_DWORD_2(timer_cmd, | |
3e6c4538 BH |
118 | FRF_AB_TC_TIMER_MODE, |
119 | FFE_BB_TIMER_MODE_DIS, | |
120 | FRF_AB_TC_TIMER_VAL, 0); | |
8ceee660 | 121 | } |
3e6c4538 | 122 | BUILD_BUG_ON(FR_AA_TIMER_COMMAND_KER != FR_BZ_TIMER_COMMAND_P0); |
12d00cad BH |
123 | efx_writed_page_locked(efx, &timer_cmd, FR_BZ_TIMER_COMMAND_P0, |
124 | channel->channel); | |
127e6e10 BH |
125 | } |
126 | ||
d3245b28 BH |
127 | static void falcon_deconfigure_mac_wrapper(struct efx_nic *efx); |
128 | ||
127e6e10 BH |
129 | static void falcon_prepare_flush(struct efx_nic *efx) |
130 | { | |
131 | falcon_deconfigure_mac_wrapper(efx); | |
132 | ||
133 | /* Wait for the tx and rx fifo's to get to the next packet boundary | |
134 | * (~1ms without back-pressure), then to drain the remainder of the | |
135 | * fifo's at data path speeds (negligible), with a healthy margin. */ | |
136 | msleep(10); | |
6bc5d3a9 BH |
137 | } |
138 | ||
8ceee660 BH |
139 | /* Acknowledge a legacy interrupt from Falcon |
140 | * | |
141 | * This acknowledges a legacy (not MSI) interrupt via INT_ACK_KER_REG. | |
142 | * | |
143 | * Due to SFC bug 3706 (silicon revision <=A1) reads can be duplicated in the | |
144 | * BIU. Interrupt acknowledge is read sensitive so must write instead | |
145 | * (then read to ensure the BIU collector is flushed) | |
146 | * | |
147 | * NB most hardware supports MSI interrupts | |
148 | */ | |
152b6a62 | 149 | inline void falcon_irq_ack_a1(struct efx_nic *efx) |
8ceee660 BH |
150 | { |
151 | efx_dword_t reg; | |
152 | ||
3e6c4538 | 153 | EFX_POPULATE_DWORD_1(reg, FRF_AA_INT_ACK_KER_FIELD, 0xb7eb7e); |
12d00cad BH |
154 | efx_writed(efx, ®, FR_AA_INT_ACK_KER); |
155 | efx_readd(efx, ®, FR_AA_WORK_AROUND_BROKEN_PCI_READS); | |
8ceee660 BH |
156 | } |
157 | ||
8ceee660 | 158 | |
152b6a62 | 159 | irqreturn_t falcon_legacy_interrupt_a1(int irq, void *dev_id) |
8ceee660 | 160 | { |
d3208b5e BH |
161 | struct efx_nic *efx = dev_id; |
162 | efx_oword_t *int_ker = efx->irq_status.addr; | |
8ceee660 BH |
163 | int syserr; |
164 | int queues; | |
165 | ||
166 | /* Check to see if this is our interrupt. If it isn't, we | |
167 | * exit without having touched the hardware. | |
168 | */ | |
169 | if (unlikely(EFX_OWORD_IS_ZERO(*int_ker))) { | |
62776d03 BH |
170 | netif_vdbg(efx, intr, efx->net_dev, |
171 | "IRQ %d on CPU %d not for me\n", irq, | |
172 | raw_smp_processor_id()); | |
8ceee660 BH |
173 | return IRQ_NONE; |
174 | } | |
175 | efx->last_irq_cpu = raw_smp_processor_id(); | |
62776d03 BH |
176 | netif_vdbg(efx, intr, efx->net_dev, |
177 | "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n", | |
178 | irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker)); | |
8ceee660 | 179 | |
f70d1847 BH |
180 | /* Check to see if we have a serious error condition */ |
181 | syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT); | |
182 | if (unlikely(syserr)) | |
183 | return efx_nic_fatal_interrupt(efx); | |
184 | ||
8ceee660 BH |
185 | /* Determine interrupting queues, clear interrupt status |
186 | * register and acknowledge the device interrupt. | |
187 | */ | |
674979d3 BH |
188 | BUILD_BUG_ON(FSF_AZ_NET_IVEC_INT_Q_WIDTH > EFX_MAX_CHANNELS); |
189 | queues = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_INT_Q); | |
8ceee660 BH |
190 | EFX_ZERO_OWORD(*int_ker); |
191 | wmb(); /* Ensure the vector is cleared before interrupt ack */ | |
192 | falcon_irq_ack_a1(efx); | |
193 | ||
8313aca3 | 194 | if (queues & 1) |
1646a6f3 | 195 | efx_schedule_channel_irq(efx_get_channel(efx, 0)); |
8313aca3 | 196 | if (queues & 2) |
1646a6f3 | 197 | efx_schedule_channel_irq(efx_get_channel(efx, 1)); |
8ceee660 BH |
198 | return IRQ_HANDLED; |
199 | } | |
8ceee660 BH |
200 | /************************************************************************** |
201 | * | |
202 | * EEPROM/flash | |
203 | * | |
204 | ************************************************************************** | |
205 | */ | |
206 | ||
23d30f02 | 207 | #define FALCON_SPI_MAX_LEN sizeof(efx_oword_t) |
8ceee660 | 208 | |
be4ea89c BH |
209 | static int falcon_spi_poll(struct efx_nic *efx) |
210 | { | |
211 | efx_oword_t reg; | |
12d00cad | 212 | efx_reado(efx, ®, FR_AB_EE_SPI_HCMD); |
3e6c4538 | 213 | return EFX_OWORD_FIELD(reg, FRF_AB_EE_SPI_HCMD_CMD_EN) ? -EBUSY : 0; |
be4ea89c BH |
214 | } |
215 | ||
8ceee660 BH |
216 | /* Wait for SPI command completion */ |
217 | static int falcon_spi_wait(struct efx_nic *efx) | |
218 | { | |
be4ea89c BH |
219 | /* Most commands will finish quickly, so we start polling at |
220 | * very short intervals. Sometimes the command may have to | |
221 | * wait for VPD or expansion ROM access outside of our | |
222 | * control, so we allow up to 100 ms. */ | |
223 | unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 10); | |
224 | int i; | |
225 | ||
226 | for (i = 0; i < 10; i++) { | |
227 | if (!falcon_spi_poll(efx)) | |
228 | return 0; | |
229 | udelay(10); | |
230 | } | |
8ceee660 | 231 | |
4a5b504d | 232 | for (;;) { |
be4ea89c | 233 | if (!falcon_spi_poll(efx)) |
8ceee660 | 234 | return 0; |
4a5b504d | 235 | if (time_after_eq(jiffies, timeout)) { |
62776d03 BH |
236 | netif_err(efx, hw, efx->net_dev, |
237 | "timed out waiting for SPI\n"); | |
4a5b504d BH |
238 | return -ETIMEDOUT; |
239 | } | |
be4ea89c | 240 | schedule_timeout_uninterruptible(1); |
4a5b504d | 241 | } |
8ceee660 BH |
242 | } |
243 | ||
76884835 | 244 | int falcon_spi_cmd(struct efx_nic *efx, const struct efx_spi_device *spi, |
f4150724 | 245 | unsigned int command, int address, |
23d30f02 | 246 | const void *in, void *out, size_t len) |
8ceee660 | 247 | { |
4a5b504d BH |
248 | bool addressed = (address >= 0); |
249 | bool reading = (out != NULL); | |
8ceee660 BH |
250 | efx_oword_t reg; |
251 | int rc; | |
252 | ||
4a5b504d BH |
253 | /* Input validation */ |
254 | if (len > FALCON_SPI_MAX_LEN) | |
255 | return -EINVAL; | |
8ceee660 | 256 | |
be4ea89c BH |
257 | /* Check that previous command is not still running */ |
258 | rc = falcon_spi_poll(efx); | |
8ceee660 BH |
259 | if (rc) |
260 | return rc; | |
261 | ||
4a5b504d BH |
262 | /* Program address register, if we have an address */ |
263 | if (addressed) { | |
3e6c4538 | 264 | EFX_POPULATE_OWORD_1(reg, FRF_AB_EE_SPI_HADR_ADR, address); |
12d00cad | 265 | efx_writeo(efx, ®, FR_AB_EE_SPI_HADR); |
4a5b504d BH |
266 | } |
267 | ||
268 | /* Program data register, if we have data */ | |
269 | if (in != NULL) { | |
270 | memcpy(®, in, len); | |
12d00cad | 271 | efx_writeo(efx, ®, FR_AB_EE_SPI_HDATA); |
4a5b504d | 272 | } |
8ceee660 | 273 | |
4a5b504d | 274 | /* Issue read/write command */ |
8ceee660 | 275 | EFX_POPULATE_OWORD_7(reg, |
3e6c4538 BH |
276 | FRF_AB_EE_SPI_HCMD_CMD_EN, 1, |
277 | FRF_AB_EE_SPI_HCMD_SF_SEL, spi->device_id, | |
278 | FRF_AB_EE_SPI_HCMD_DABCNT, len, | |
279 | FRF_AB_EE_SPI_HCMD_READ, reading, | |
280 | FRF_AB_EE_SPI_HCMD_DUBCNT, 0, | |
281 | FRF_AB_EE_SPI_HCMD_ADBCNT, | |
4a5b504d | 282 | (addressed ? spi->addr_len : 0), |
3e6c4538 | 283 | FRF_AB_EE_SPI_HCMD_ENC, command); |
12d00cad | 284 | efx_writeo(efx, ®, FR_AB_EE_SPI_HCMD); |
8ceee660 | 285 | |
4a5b504d | 286 | /* Wait for read/write to complete */ |
8ceee660 BH |
287 | rc = falcon_spi_wait(efx); |
288 | if (rc) | |
289 | return rc; | |
290 | ||
291 | /* Read data */ | |
4a5b504d | 292 | if (out != NULL) { |
12d00cad | 293 | efx_reado(efx, ®, FR_AB_EE_SPI_HDATA); |
4a5b504d BH |
294 | memcpy(out, ®, len); |
295 | } | |
296 | ||
8ceee660 BH |
297 | return 0; |
298 | } | |
299 | ||
23d30f02 BH |
300 | static size_t |
301 | falcon_spi_write_limit(const struct efx_spi_device *spi, size_t start) | |
4a5b504d BH |
302 | { |
303 | return min(FALCON_SPI_MAX_LEN, | |
304 | (spi->block_size - (start & (spi->block_size - 1)))); | |
305 | } | |
306 | ||
307 | static inline u8 | |
308 | efx_spi_munge_command(const struct efx_spi_device *spi, | |
309 | const u8 command, const unsigned int address) | |
310 | { | |
311 | return command | (((address >> 8) & spi->munge_address) << 3); | |
312 | } | |
313 | ||
be4ea89c | 314 | /* Wait up to 10 ms for buffered write completion */ |
76884835 BH |
315 | int |
316 | falcon_spi_wait_write(struct efx_nic *efx, const struct efx_spi_device *spi) | |
4a5b504d | 317 | { |
be4ea89c | 318 | unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 100); |
4a5b504d | 319 | u8 status; |
be4ea89c | 320 | int rc; |
4a5b504d | 321 | |
be4ea89c | 322 | for (;;) { |
76884835 | 323 | rc = falcon_spi_cmd(efx, spi, SPI_RDSR, -1, NULL, |
4a5b504d BH |
324 | &status, sizeof(status)); |
325 | if (rc) | |
326 | return rc; | |
327 | if (!(status & SPI_STATUS_NRDY)) | |
328 | return 0; | |
be4ea89c | 329 | if (time_after_eq(jiffies, timeout)) { |
62776d03 BH |
330 | netif_err(efx, hw, efx->net_dev, |
331 | "SPI write timeout on device %d" | |
332 | " last status=0x%02x\n", | |
333 | spi->device_id, status); | |
be4ea89c BH |
334 | return -ETIMEDOUT; |
335 | } | |
336 | schedule_timeout_uninterruptible(1); | |
4a5b504d | 337 | } |
4a5b504d BH |
338 | } |
339 | ||
76884835 BH |
340 | int falcon_spi_read(struct efx_nic *efx, const struct efx_spi_device *spi, |
341 | loff_t start, size_t len, size_t *retlen, u8 *buffer) | |
4a5b504d | 342 | { |
23d30f02 BH |
343 | size_t block_len, pos = 0; |
344 | unsigned int command; | |
4a5b504d BH |
345 | int rc = 0; |
346 | ||
347 | while (pos < len) { | |
23d30f02 | 348 | block_len = min(len - pos, FALCON_SPI_MAX_LEN); |
4a5b504d BH |
349 | |
350 | command = efx_spi_munge_command(spi, SPI_READ, start + pos); | |
76884835 | 351 | rc = falcon_spi_cmd(efx, spi, command, start + pos, NULL, |
4a5b504d BH |
352 | buffer + pos, block_len); |
353 | if (rc) | |
354 | break; | |
355 | pos += block_len; | |
356 | ||
357 | /* Avoid locking up the system */ | |
358 | cond_resched(); | |
359 | if (signal_pending(current)) { | |
360 | rc = -EINTR; | |
361 | break; | |
362 | } | |
363 | } | |
364 | ||
365 | if (retlen) | |
366 | *retlen = pos; | |
367 | return rc; | |
368 | } | |
369 | ||
76884835 BH |
370 | int |
371 | falcon_spi_write(struct efx_nic *efx, const struct efx_spi_device *spi, | |
372 | loff_t start, size_t len, size_t *retlen, const u8 *buffer) | |
4a5b504d BH |
373 | { |
374 | u8 verify_buffer[FALCON_SPI_MAX_LEN]; | |
23d30f02 BH |
375 | size_t block_len, pos = 0; |
376 | unsigned int command; | |
4a5b504d BH |
377 | int rc = 0; |
378 | ||
379 | while (pos < len) { | |
76884835 | 380 | rc = falcon_spi_cmd(efx, spi, SPI_WREN, -1, NULL, NULL, 0); |
4a5b504d BH |
381 | if (rc) |
382 | break; | |
383 | ||
23d30f02 | 384 | block_len = min(len - pos, |
4a5b504d BH |
385 | falcon_spi_write_limit(spi, start + pos)); |
386 | command = efx_spi_munge_command(spi, SPI_WRITE, start + pos); | |
76884835 | 387 | rc = falcon_spi_cmd(efx, spi, command, start + pos, |
4a5b504d BH |
388 | buffer + pos, NULL, block_len); |
389 | if (rc) | |
390 | break; | |
391 | ||
76884835 | 392 | rc = falcon_spi_wait_write(efx, spi); |
4a5b504d BH |
393 | if (rc) |
394 | break; | |
395 | ||
396 | command = efx_spi_munge_command(spi, SPI_READ, start + pos); | |
76884835 | 397 | rc = falcon_spi_cmd(efx, spi, command, start + pos, |
4a5b504d BH |
398 | NULL, verify_buffer, block_len); |
399 | if (memcmp(verify_buffer, buffer + pos, block_len)) { | |
400 | rc = -EIO; | |
401 | break; | |
402 | } | |
403 | ||
404 | pos += block_len; | |
405 | ||
406 | /* Avoid locking up the system */ | |
407 | cond_resched(); | |
408 | if (signal_pending(current)) { | |
409 | rc = -EINTR; | |
410 | break; | |
411 | } | |
412 | } | |
413 | ||
414 | if (retlen) | |
415 | *retlen = pos; | |
416 | return rc; | |
417 | } | |
418 | ||
8ceee660 BH |
419 | /************************************************************************** |
420 | * | |
421 | * MAC wrapper | |
422 | * | |
423 | ************************************************************************** | |
424 | */ | |
177dfcd8 | 425 | |
ef2b90ee BH |
426 | static void falcon_push_multicast_hash(struct efx_nic *efx) |
427 | { | |
428 | union efx_multicast_hash *mc_hash = &efx->multicast_hash; | |
429 | ||
430 | WARN_ON(!mutex_is_locked(&efx->mac_lock)); | |
431 | ||
432 | efx_writeo(efx, &mc_hash->oword[0], FR_AB_MAC_MC_HASH_REG0); | |
433 | efx_writeo(efx, &mc_hash->oword[1], FR_AB_MAC_MC_HASH_REG1); | |
434 | } | |
435 | ||
d3245b28 | 436 | static void falcon_reset_macs(struct efx_nic *efx) |
8ceee660 | 437 | { |
d3245b28 BH |
438 | struct falcon_nic_data *nic_data = efx->nic_data; |
439 | efx_oword_t reg, mac_ctrl; | |
8ceee660 BH |
440 | int count; |
441 | ||
daeda630 | 442 | if (efx_nic_rev(efx) < EFX_REV_FALCON_B0) { |
177dfcd8 BH |
443 | /* It's not safe to use GLB_CTL_REG to reset the |
444 | * macs, so instead use the internal MAC resets | |
445 | */ | |
8fbca791 BH |
446 | EFX_POPULATE_OWORD_1(reg, FRF_AB_XM_CORE_RST, 1); |
447 | efx_writeo(efx, ®, FR_AB_XM_GLB_CFG); | |
448 | ||
449 | for (count = 0; count < 10000; count++) { | |
450 | efx_reado(efx, ®, FR_AB_XM_GLB_CFG); | |
451 | if (EFX_OWORD_FIELD(reg, FRF_AB_XM_CORE_RST) == | |
452 | 0) | |
453 | return; | |
454 | udelay(10); | |
177dfcd8 | 455 | } |
8fbca791 BH |
456 | |
457 | netif_err(efx, hw, efx->net_dev, | |
458 | "timed out waiting for XMAC core reset\n"); | |
177dfcd8 | 459 | } |
8ceee660 | 460 | |
d3245b28 BH |
461 | /* Mac stats will fail whist the TX fifo is draining */ |
462 | WARN_ON(nic_data->stats_disable_count == 0); | |
8ceee660 | 463 | |
d3245b28 BH |
464 | efx_reado(efx, &mac_ctrl, FR_AB_MAC_CTRL); |
465 | EFX_SET_OWORD_FIELD(mac_ctrl, FRF_BB_TXFIFO_DRAIN_EN, 1); | |
466 | efx_writeo(efx, &mac_ctrl, FR_AB_MAC_CTRL); | |
8ceee660 | 467 | |
12d00cad | 468 | efx_reado(efx, ®, FR_AB_GLB_CTL); |
3e6c4538 BH |
469 | EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGTX, 1); |
470 | EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGRX, 1); | |
471 | EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_EM, 1); | |
12d00cad | 472 | efx_writeo(efx, ®, FR_AB_GLB_CTL); |
8ceee660 BH |
473 | |
474 | count = 0; | |
475 | while (1) { | |
12d00cad | 476 | efx_reado(efx, ®, FR_AB_GLB_CTL); |
3e6c4538 BH |
477 | if (!EFX_OWORD_FIELD(reg, FRF_AB_RST_XGTX) && |
478 | !EFX_OWORD_FIELD(reg, FRF_AB_RST_XGRX) && | |
479 | !EFX_OWORD_FIELD(reg, FRF_AB_RST_EM)) { | |
62776d03 BH |
480 | netif_dbg(efx, hw, efx->net_dev, |
481 | "Completed MAC reset after %d loops\n", | |
482 | count); | |
8ceee660 BH |
483 | break; |
484 | } | |
485 | if (count > 20) { | |
62776d03 | 486 | netif_err(efx, hw, efx->net_dev, "MAC reset failed\n"); |
8ceee660 BH |
487 | break; |
488 | } | |
489 | count++; | |
490 | udelay(10); | |
491 | } | |
492 | ||
d3245b28 BH |
493 | /* Ensure the correct MAC is selected before statistics |
494 | * are re-enabled by the caller */ | |
495 | efx_writeo(efx, &mac_ctrl, FR_AB_MAC_CTRL); | |
b7b40eeb | 496 | |
b7b40eeb | 497 | falcon_setup_xaui(efx); |
177dfcd8 BH |
498 | } |
499 | ||
500 | void falcon_drain_tx_fifo(struct efx_nic *efx) | |
501 | { | |
502 | efx_oword_t reg; | |
503 | ||
daeda630 | 504 | if ((efx_nic_rev(efx) < EFX_REV_FALCON_B0) || |
177dfcd8 BH |
505 | (efx->loopback_mode != LOOPBACK_NONE)) |
506 | return; | |
507 | ||
12d00cad | 508 | efx_reado(efx, ®, FR_AB_MAC_CTRL); |
177dfcd8 | 509 | /* There is no point in draining more than once */ |
3e6c4538 | 510 | if (EFX_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN)) |
177dfcd8 BH |
511 | return; |
512 | ||
513 | falcon_reset_macs(efx); | |
8ceee660 BH |
514 | } |
515 | ||
d3245b28 | 516 | static void falcon_deconfigure_mac_wrapper(struct efx_nic *efx) |
8ceee660 | 517 | { |
177dfcd8 | 518 | efx_oword_t reg; |
8ceee660 | 519 | |
daeda630 | 520 | if (efx_nic_rev(efx) < EFX_REV_FALCON_B0) |
8ceee660 BH |
521 | return; |
522 | ||
523 | /* Isolate the MAC -> RX */ | |
12d00cad | 524 | efx_reado(efx, ®, FR_AZ_RX_CFG); |
3e6c4538 | 525 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 0); |
12d00cad | 526 | efx_writeo(efx, ®, FR_AZ_RX_CFG); |
8ceee660 | 527 | |
d3245b28 BH |
528 | /* Isolate TX -> MAC */ |
529 | falcon_drain_tx_fifo(efx); | |
8ceee660 BH |
530 | } |
531 | ||
532 | void falcon_reconfigure_mac_wrapper(struct efx_nic *efx) | |
533 | { | |
eb50c0d6 | 534 | struct efx_link_state *link_state = &efx->link_state; |
8ceee660 | 535 | efx_oword_t reg; |
fd371e32 SH |
536 | int link_speed, isolate; |
537 | ||
a7d529ae | 538 | isolate = !!ACCESS_ONCE(efx->reset_pending); |
8ceee660 | 539 | |
eb50c0d6 | 540 | switch (link_state->speed) { |
f31a45d2 BH |
541 | case 10000: link_speed = 3; break; |
542 | case 1000: link_speed = 2; break; | |
543 | case 100: link_speed = 1; break; | |
544 | default: link_speed = 0; break; | |
545 | } | |
8ceee660 BH |
546 | /* MAC_LINK_STATUS controls MAC backpressure but doesn't work |
547 | * as advertised. Disable to ensure packets are not | |
548 | * indefinitely held and TX queue can be flushed at any point | |
549 | * while the link is down. */ | |
550 | EFX_POPULATE_OWORD_5(reg, | |
3e6c4538 BH |
551 | FRF_AB_MAC_XOFF_VAL, 0xffff /* max pause time */, |
552 | FRF_AB_MAC_BCAD_ACPT, 1, | |
553 | FRF_AB_MAC_UC_PROM, efx->promiscuous, | |
554 | FRF_AB_MAC_LINK_STATUS, 1, /* always set */ | |
555 | FRF_AB_MAC_SPEED, link_speed); | |
8ceee660 BH |
556 | /* On B0, MAC backpressure can be disabled and packets get |
557 | * discarded. */ | |
daeda630 | 558 | if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) { |
3e6c4538 | 559 | EFX_SET_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN, |
fd371e32 | 560 | !link_state->up || isolate); |
8ceee660 BH |
561 | } |
562 | ||
12d00cad | 563 | efx_writeo(efx, ®, FR_AB_MAC_CTRL); |
8ceee660 BH |
564 | |
565 | /* Restore the multicast hash registers. */ | |
8be4f3e6 | 566 | falcon_push_multicast_hash(efx); |
8ceee660 | 567 | |
12d00cad | 568 | efx_reado(efx, ®, FR_AZ_RX_CFG); |
4b0d29dc BH |
569 | /* Enable XOFF signal from RX FIFO (we enabled it during NIC |
570 | * initialisation but it may read back as 0) */ | |
571 | EFX_SET_OWORD_FIELD(reg, FRF_AZ_RX_XOFF_MAC_EN, 1); | |
8ceee660 | 572 | /* Unisolate the MAC -> RX */ |
daeda630 | 573 | if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) |
fd371e32 | 574 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, !isolate); |
12d00cad | 575 | efx_writeo(efx, ®, FR_AZ_RX_CFG); |
8ceee660 BH |
576 | } |
577 | ||
55edc6e6 | 578 | static void falcon_stats_request(struct efx_nic *efx) |
8ceee660 | 579 | { |
55edc6e6 | 580 | struct falcon_nic_data *nic_data = efx->nic_data; |
8ceee660 | 581 | efx_oword_t reg; |
8ceee660 | 582 | |
55edc6e6 BH |
583 | WARN_ON(nic_data->stats_pending); |
584 | WARN_ON(nic_data->stats_disable_count); | |
8ceee660 | 585 | |
55edc6e6 BH |
586 | if (nic_data->stats_dma_done == NULL) |
587 | return; /* no mac selected */ | |
8ceee660 | 588 | |
55edc6e6 BH |
589 | *nic_data->stats_dma_done = FALCON_STATS_NOT_DONE; |
590 | nic_data->stats_pending = true; | |
8ceee660 BH |
591 | wmb(); /* ensure done flag is clear */ |
592 | ||
593 | /* Initiate DMA transfer of stats */ | |
594 | EFX_POPULATE_OWORD_2(reg, | |
3e6c4538 BH |
595 | FRF_AB_MAC_STAT_DMA_CMD, 1, |
596 | FRF_AB_MAC_STAT_DMA_ADR, | |
8ceee660 | 597 | efx->stats_buffer.dma_addr); |
12d00cad | 598 | efx_writeo(efx, ®, FR_AB_MAC_STAT_DMA); |
8ceee660 | 599 | |
55edc6e6 BH |
600 | mod_timer(&nic_data->stats_timer, round_jiffies_up(jiffies + HZ / 2)); |
601 | } | |
602 | ||
603 | static void falcon_stats_complete(struct efx_nic *efx) | |
604 | { | |
605 | struct falcon_nic_data *nic_data = efx->nic_data; | |
606 | ||
607 | if (!nic_data->stats_pending) | |
608 | return; | |
609 | ||
3db1cd5c | 610 | nic_data->stats_pending = false; |
55edc6e6 BH |
611 | if (*nic_data->stats_dma_done == FALCON_STATS_DONE) { |
612 | rmb(); /* read the done flag before the stats */ | |
710b208d | 613 | falcon_update_stats_xmac(efx); |
55edc6e6 | 614 | } else { |
62776d03 BH |
615 | netif_err(efx, hw, efx->net_dev, |
616 | "timed out waiting for statistics\n"); | |
8ceee660 | 617 | } |
55edc6e6 | 618 | } |
8ceee660 | 619 | |
55edc6e6 BH |
620 | static void falcon_stats_timer_func(unsigned long context) |
621 | { | |
622 | struct efx_nic *efx = (struct efx_nic *)context; | |
623 | struct falcon_nic_data *nic_data = efx->nic_data; | |
624 | ||
625 | spin_lock(&efx->stats_lock); | |
626 | ||
627 | falcon_stats_complete(efx); | |
628 | if (nic_data->stats_disable_count == 0) | |
629 | falcon_stats_request(efx); | |
630 | ||
631 | spin_unlock(&efx->stats_lock); | |
8ceee660 BH |
632 | } |
633 | ||
fdaa9aed SH |
634 | static bool falcon_loopback_link_poll(struct efx_nic *efx) |
635 | { | |
636 | struct efx_link_state old_state = efx->link_state; | |
637 | ||
638 | WARN_ON(!mutex_is_locked(&efx->mac_lock)); | |
639 | WARN_ON(!LOOPBACK_INTERNAL(efx)); | |
640 | ||
641 | efx->link_state.fd = true; | |
642 | efx->link_state.fc = efx->wanted_fc; | |
643 | efx->link_state.up = true; | |
8fbca791 | 644 | efx->link_state.speed = 10000; |
fdaa9aed SH |
645 | |
646 | return !efx_link_state_equal(&efx->link_state, &old_state); | |
647 | } | |
648 | ||
d3245b28 BH |
649 | static int falcon_reconfigure_port(struct efx_nic *efx) |
650 | { | |
651 | int rc; | |
652 | ||
653 | WARN_ON(efx_nic_rev(efx) > EFX_REV_FALCON_B0); | |
654 | ||
655 | /* Poll the PHY link state *before* reconfiguring it. This means we | |
656 | * will pick up the correct speed (in loopback) to select the correct | |
657 | * MAC. | |
658 | */ | |
659 | if (LOOPBACK_INTERNAL(efx)) | |
660 | falcon_loopback_link_poll(efx); | |
661 | else | |
662 | efx->phy_op->poll(efx); | |
663 | ||
664 | falcon_stop_nic_stats(efx); | |
665 | falcon_deconfigure_mac_wrapper(efx); | |
666 | ||
8fbca791 | 667 | falcon_reset_macs(efx); |
d3245b28 BH |
668 | |
669 | efx->phy_op->reconfigure(efx); | |
710b208d | 670 | rc = falcon_reconfigure_xmac(efx); |
d3245b28 BH |
671 | BUG_ON(rc); |
672 | ||
673 | falcon_start_nic_stats(efx); | |
674 | ||
675 | /* Synchronise efx->link_state with the kernel */ | |
676 | efx_link_status_changed(efx); | |
677 | ||
678 | return 0; | |
679 | } | |
680 | ||
8ceee660 BH |
681 | /************************************************************************** |
682 | * | |
683 | * PHY access via GMII | |
684 | * | |
685 | ************************************************************************** | |
686 | */ | |
687 | ||
8ceee660 BH |
688 | /* Wait for GMII access to complete */ |
689 | static int falcon_gmii_wait(struct efx_nic *efx) | |
690 | { | |
80cb9a0f | 691 | efx_oword_t md_stat; |
8ceee660 BH |
692 | int count; |
693 | ||
25985edc | 694 | /* wait up to 50ms - taken max from datasheet */ |
177dfcd8 | 695 | for (count = 0; count < 5000; count++) { |
80cb9a0f BH |
696 | efx_reado(efx, &md_stat, FR_AB_MD_STAT); |
697 | if (EFX_OWORD_FIELD(md_stat, FRF_AB_MD_BSY) == 0) { | |
698 | if (EFX_OWORD_FIELD(md_stat, FRF_AB_MD_LNFL) != 0 || | |
699 | EFX_OWORD_FIELD(md_stat, FRF_AB_MD_BSERR) != 0) { | |
62776d03 BH |
700 | netif_err(efx, hw, efx->net_dev, |
701 | "error from GMII access " | |
702 | EFX_OWORD_FMT"\n", | |
703 | EFX_OWORD_VAL(md_stat)); | |
8ceee660 BH |
704 | return -EIO; |
705 | } | |
706 | return 0; | |
707 | } | |
708 | udelay(10); | |
709 | } | |
62776d03 | 710 | netif_err(efx, hw, efx->net_dev, "timed out waiting for GMII\n"); |
8ceee660 BH |
711 | return -ETIMEDOUT; |
712 | } | |
713 | ||
68e7f45e BH |
714 | /* Write an MDIO register of a PHY connected to Falcon. */ |
715 | static int falcon_mdio_write(struct net_device *net_dev, | |
716 | int prtad, int devad, u16 addr, u16 value) | |
8ceee660 | 717 | { |
767e468c | 718 | struct efx_nic *efx = netdev_priv(net_dev); |
4833f02a | 719 | struct falcon_nic_data *nic_data = efx->nic_data; |
8ceee660 | 720 | efx_oword_t reg; |
68e7f45e | 721 | int rc; |
8ceee660 | 722 | |
62776d03 BH |
723 | netif_vdbg(efx, hw, efx->net_dev, |
724 | "writing MDIO %d register %d.%d with 0x%04x\n", | |
68e7f45e | 725 | prtad, devad, addr, value); |
8ceee660 | 726 | |
4833f02a | 727 | mutex_lock(&nic_data->mdio_lock); |
8ceee660 | 728 | |
68e7f45e BH |
729 | /* Check MDIO not currently being accessed */ |
730 | rc = falcon_gmii_wait(efx); | |
731 | if (rc) | |
8ceee660 BH |
732 | goto out; |
733 | ||
734 | /* Write the address/ID register */ | |
3e6c4538 | 735 | EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr); |
12d00cad | 736 | efx_writeo(efx, ®, FR_AB_MD_PHY_ADR); |
8ceee660 | 737 | |
3e6c4538 BH |
738 | EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad, |
739 | FRF_AB_MD_DEV_ADR, devad); | |
12d00cad | 740 | efx_writeo(efx, ®, FR_AB_MD_ID); |
8ceee660 BH |
741 | |
742 | /* Write data */ | |
3e6c4538 | 743 | EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_TXD, value); |
12d00cad | 744 | efx_writeo(efx, ®, FR_AB_MD_TXD); |
8ceee660 BH |
745 | |
746 | EFX_POPULATE_OWORD_2(reg, | |
3e6c4538 BH |
747 | FRF_AB_MD_WRC, 1, |
748 | FRF_AB_MD_GC, 0); | |
12d00cad | 749 | efx_writeo(efx, ®, FR_AB_MD_CS); |
8ceee660 BH |
750 | |
751 | /* Wait for data to be written */ | |
68e7f45e BH |
752 | rc = falcon_gmii_wait(efx); |
753 | if (rc) { | |
8ceee660 BH |
754 | /* Abort the write operation */ |
755 | EFX_POPULATE_OWORD_2(reg, | |
3e6c4538 BH |
756 | FRF_AB_MD_WRC, 0, |
757 | FRF_AB_MD_GC, 1); | |
12d00cad | 758 | efx_writeo(efx, ®, FR_AB_MD_CS); |
8ceee660 BH |
759 | udelay(10); |
760 | } | |
761 | ||
ab867461 | 762 | out: |
4833f02a | 763 | mutex_unlock(&nic_data->mdio_lock); |
68e7f45e | 764 | return rc; |
8ceee660 BH |
765 | } |
766 | ||
68e7f45e BH |
767 | /* Read an MDIO register of a PHY connected to Falcon. */ |
768 | static int falcon_mdio_read(struct net_device *net_dev, | |
769 | int prtad, int devad, u16 addr) | |
8ceee660 | 770 | { |
767e468c | 771 | struct efx_nic *efx = netdev_priv(net_dev); |
4833f02a | 772 | struct falcon_nic_data *nic_data = efx->nic_data; |
8ceee660 | 773 | efx_oword_t reg; |
68e7f45e | 774 | int rc; |
8ceee660 | 775 | |
4833f02a | 776 | mutex_lock(&nic_data->mdio_lock); |
8ceee660 | 777 | |
68e7f45e BH |
778 | /* Check MDIO not currently being accessed */ |
779 | rc = falcon_gmii_wait(efx); | |
780 | if (rc) | |
8ceee660 BH |
781 | goto out; |
782 | ||
3e6c4538 | 783 | EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr); |
12d00cad | 784 | efx_writeo(efx, ®, FR_AB_MD_PHY_ADR); |
8ceee660 | 785 | |
3e6c4538 BH |
786 | EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad, |
787 | FRF_AB_MD_DEV_ADR, devad); | |
12d00cad | 788 | efx_writeo(efx, ®, FR_AB_MD_ID); |
8ceee660 BH |
789 | |
790 | /* Request data to be read */ | |
3e6c4538 | 791 | EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_RDC, 1, FRF_AB_MD_GC, 0); |
12d00cad | 792 | efx_writeo(efx, ®, FR_AB_MD_CS); |
8ceee660 BH |
793 | |
794 | /* Wait for data to become available */ | |
68e7f45e BH |
795 | rc = falcon_gmii_wait(efx); |
796 | if (rc == 0) { | |
12d00cad | 797 | efx_reado(efx, ®, FR_AB_MD_RXD); |
3e6c4538 | 798 | rc = EFX_OWORD_FIELD(reg, FRF_AB_MD_RXD); |
62776d03 BH |
799 | netif_vdbg(efx, hw, efx->net_dev, |
800 | "read from MDIO %d register %d.%d, got %04x\n", | |
801 | prtad, devad, addr, rc); | |
8ceee660 BH |
802 | } else { |
803 | /* Abort the read operation */ | |
804 | EFX_POPULATE_OWORD_2(reg, | |
3e6c4538 BH |
805 | FRF_AB_MD_RIC, 0, |
806 | FRF_AB_MD_GC, 1); | |
12d00cad | 807 | efx_writeo(efx, ®, FR_AB_MD_CS); |
8ceee660 | 808 | |
62776d03 BH |
809 | netif_dbg(efx, hw, efx->net_dev, |
810 | "read from MDIO %d register %d.%d, got error %d\n", | |
811 | prtad, devad, addr, rc); | |
8ceee660 BH |
812 | } |
813 | ||
ab867461 | 814 | out: |
4833f02a | 815 | mutex_unlock(&nic_data->mdio_lock); |
68e7f45e | 816 | return rc; |
8ceee660 BH |
817 | } |
818 | ||
8ceee660 | 819 | /* This call is responsible for hooking in the MAC and PHY operations */ |
ef2b90ee | 820 | static int falcon_probe_port(struct efx_nic *efx) |
8ceee660 | 821 | { |
8fbca791 | 822 | struct falcon_nic_data *nic_data = efx->nic_data; |
8ceee660 BH |
823 | int rc; |
824 | ||
96c45726 BH |
825 | switch (efx->phy_type) { |
826 | case PHY_TYPE_SFX7101: | |
827 | efx->phy_op = &falcon_sfx7101_phy_ops; | |
828 | break; | |
96c45726 BH |
829 | case PHY_TYPE_QT2022C2: |
830 | case PHY_TYPE_QT2025C: | |
b37b62fe | 831 | efx->phy_op = &falcon_qt202x_phy_ops; |
96c45726 | 832 | break; |
7e51b439 BH |
833 | case PHY_TYPE_TXC43128: |
834 | efx->phy_op = &falcon_txc_phy_ops; | |
835 | break; | |
96c45726 | 836 | default: |
62776d03 BH |
837 | netif_err(efx, probe, efx->net_dev, "Unknown PHY type %d\n", |
838 | efx->phy_type); | |
96c45726 BH |
839 | return -ENODEV; |
840 | } | |
841 | ||
c1c4f453 | 842 | /* Fill out MDIO structure and loopback modes */ |
4833f02a | 843 | mutex_init(&nic_data->mdio_lock); |
68e7f45e BH |
844 | efx->mdio.mdio_read = falcon_mdio_read; |
845 | efx->mdio.mdio_write = falcon_mdio_write; | |
c1c4f453 BH |
846 | rc = efx->phy_op->probe(efx); |
847 | if (rc != 0) | |
848 | return rc; | |
8ceee660 | 849 | |
b895d73e SH |
850 | /* Initial assumption */ |
851 | efx->link_state.speed = 10000; | |
852 | efx->link_state.fd = true; | |
853 | ||
8ceee660 | 854 | /* Hardware flow ctrl. FalconA RX FIFO too small for pause generation */ |
daeda630 | 855 | if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) |
04cc8cac | 856 | efx->wanted_fc = EFX_FC_RX | EFX_FC_TX; |
8ceee660 | 857 | else |
04cc8cac | 858 | efx->wanted_fc = EFX_FC_RX; |
7a6b8f6f SH |
859 | if (efx->mdio.mmds & MDIO_DEVS_AN) |
860 | efx->wanted_fc |= EFX_FC_AUTO; | |
8ceee660 BH |
861 | |
862 | /* Allocate buffer for stats */ | |
152b6a62 BH |
863 | rc = efx_nic_alloc_buffer(efx, &efx->stats_buffer, |
864 | FALCON_MAC_STATS_SIZE); | |
8ceee660 BH |
865 | if (rc) |
866 | return rc; | |
62776d03 BH |
867 | netif_dbg(efx, probe, efx->net_dev, |
868 | "stats buffer at %llx (virt %p phys %llx)\n", | |
869 | (u64)efx->stats_buffer.dma_addr, | |
870 | efx->stats_buffer.addr, | |
871 | (u64)virt_to_phys(efx->stats_buffer.addr)); | |
8fbca791 | 872 | nic_data->stats_dma_done = efx->stats_buffer.addr + XgDmaDone_offset; |
8ceee660 BH |
873 | |
874 | return 0; | |
875 | } | |
876 | ||
ef2b90ee | 877 | static void falcon_remove_port(struct efx_nic *efx) |
8ceee660 | 878 | { |
ff3b00a0 | 879 | efx->phy_op->remove(efx); |
152b6a62 | 880 | efx_nic_free_buffer(efx, &efx->stats_buffer); |
8ceee660 BH |
881 | } |
882 | ||
40641ed9 BH |
883 | /* Global events are basically PHY events */ |
884 | static bool | |
885 | falcon_handle_global_event(struct efx_channel *channel, efx_qword_t *event) | |
886 | { | |
887 | struct efx_nic *efx = channel->efx; | |
cef68bde | 888 | struct falcon_nic_data *nic_data = efx->nic_data; |
40641ed9 BH |
889 | |
890 | if (EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_G_PHY0_INTR) || | |
891 | EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_XG_PHY0_INTR) || | |
892 | EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_XFP_PHY0_INTR)) | |
893 | /* Ignored */ | |
894 | return true; | |
895 | ||
896 | if ((efx_nic_rev(efx) == EFX_REV_FALCON_B0) && | |
897 | EFX_QWORD_FIELD(*event, FSF_BB_GLB_EV_XG_MGT_INTR)) { | |
cef68bde | 898 | nic_data->xmac_poll_required = true; |
40641ed9 BH |
899 | return true; |
900 | } | |
901 | ||
902 | if (efx_nic_rev(efx) <= EFX_REV_FALCON_A1 ? | |
903 | EFX_QWORD_FIELD(*event, FSF_AA_GLB_EV_RX_RECOVERY) : | |
904 | EFX_QWORD_FIELD(*event, FSF_BB_GLB_EV_RX_RECOVERY)) { | |
905 | netif_err(efx, rx_err, efx->net_dev, | |
906 | "channel %d seen global RX_RESET event. Resetting.\n", | |
907 | channel->channel); | |
908 | ||
909 | atomic_inc(&efx->rx_reset); | |
910 | efx_schedule_reset(efx, EFX_WORKAROUND_6555(efx) ? | |
911 | RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE); | |
912 | return true; | |
913 | } | |
914 | ||
915 | return false; | |
916 | } | |
917 | ||
8c8661e4 BH |
918 | /************************************************************************** |
919 | * | |
920 | * Falcon test code | |
921 | * | |
922 | **************************************************************************/ | |
923 | ||
0aa3fbaa BH |
924 | static int |
925 | falcon_read_nvram(struct efx_nic *efx, struct falcon_nvconfig *nvconfig_out) | |
8c8661e4 | 926 | { |
4de92180 | 927 | struct falcon_nic_data *nic_data = efx->nic_data; |
8c8661e4 BH |
928 | struct falcon_nvconfig *nvconfig; |
929 | struct efx_spi_device *spi; | |
930 | void *region; | |
931 | int rc, magic_num, struct_ver; | |
932 | __le16 *word, *limit; | |
933 | u32 csum; | |
934 | ||
4de92180 BH |
935 | if (efx_spi_present(&nic_data->spi_flash)) |
936 | spi = &nic_data->spi_flash; | |
937 | else if (efx_spi_present(&nic_data->spi_eeprom)) | |
938 | spi = &nic_data->spi_eeprom; | |
939 | else | |
2f7f5730 BH |
940 | return -EINVAL; |
941 | ||
0a95f563 | 942 | region = kmalloc(FALCON_NVCONFIG_END, GFP_KERNEL); |
8c8661e4 BH |
943 | if (!region) |
944 | return -ENOMEM; | |
3e6c4538 | 945 | nvconfig = region + FALCON_NVCONFIG_OFFSET; |
8c8661e4 | 946 | |
4de92180 | 947 | mutex_lock(&nic_data->spi_lock); |
76884835 | 948 | rc = falcon_spi_read(efx, spi, 0, FALCON_NVCONFIG_END, NULL, region); |
4de92180 | 949 | mutex_unlock(&nic_data->spi_lock); |
8c8661e4 | 950 | if (rc) { |
62776d03 | 951 | netif_err(efx, hw, efx->net_dev, "Failed to read %s\n", |
4de92180 BH |
952 | efx_spi_present(&nic_data->spi_flash) ? |
953 | "flash" : "EEPROM"); | |
8c8661e4 BH |
954 | rc = -EIO; |
955 | goto out; | |
956 | } | |
957 | ||
958 | magic_num = le16_to_cpu(nvconfig->board_magic_num); | |
959 | struct_ver = le16_to_cpu(nvconfig->board_struct_ver); | |
960 | ||
961 | rc = -EINVAL; | |
3e6c4538 | 962 | if (magic_num != FALCON_NVCONFIG_BOARD_MAGIC_NUM) { |
62776d03 BH |
963 | netif_err(efx, hw, efx->net_dev, |
964 | "NVRAM bad magic 0x%x\n", magic_num); | |
8c8661e4 BH |
965 | goto out; |
966 | } | |
967 | if (struct_ver < 2) { | |
62776d03 BH |
968 | netif_err(efx, hw, efx->net_dev, |
969 | "NVRAM has ancient version 0x%x\n", struct_ver); | |
8c8661e4 BH |
970 | goto out; |
971 | } else if (struct_ver < 4) { | |
972 | word = &nvconfig->board_magic_num; | |
973 | limit = (__le16 *) (nvconfig + 1); | |
974 | } else { | |
975 | word = region; | |
0a95f563 | 976 | limit = region + FALCON_NVCONFIG_END; |
8c8661e4 BH |
977 | } |
978 | for (csum = 0; word < limit; ++word) | |
979 | csum += le16_to_cpu(*word); | |
980 | ||
981 | if (~csum & 0xffff) { | |
62776d03 BH |
982 | netif_err(efx, hw, efx->net_dev, |
983 | "NVRAM has incorrect checksum\n"); | |
8c8661e4 BH |
984 | goto out; |
985 | } | |
986 | ||
987 | rc = 0; | |
988 | if (nvconfig_out) | |
989 | memcpy(nvconfig_out, nvconfig, sizeof(*nvconfig)); | |
990 | ||
991 | out: | |
992 | kfree(region); | |
993 | return rc; | |
994 | } | |
995 | ||
0aa3fbaa BH |
996 | static int falcon_test_nvram(struct efx_nic *efx) |
997 | { | |
998 | return falcon_read_nvram(efx, NULL); | |
999 | } | |
1000 | ||
152b6a62 | 1001 | static const struct efx_nic_register_test falcon_b0_register_tests[] = { |
3e6c4538 | 1002 | { FR_AZ_ADR_REGION, |
4cddca54 | 1003 | EFX_OWORD32(0x0003FFFF, 0x0003FFFF, 0x0003FFFF, 0x0003FFFF) }, |
3e6c4538 | 1004 | { FR_AZ_RX_CFG, |
8c8661e4 | 1005 | EFX_OWORD32(0xFFFFFFFE, 0x00017FFF, 0x00000000, 0x00000000) }, |
3e6c4538 | 1006 | { FR_AZ_TX_CFG, |
8c8661e4 | 1007 | EFX_OWORD32(0x7FFF0037, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 1008 | { FR_AZ_TX_RESERVED, |
8c8661e4 | 1009 | EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) }, |
3e6c4538 | 1010 | { FR_AB_MAC_CTRL, |
8c8661e4 | 1011 | EFX_OWORD32(0xFFFF0000, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 1012 | { FR_AZ_SRM_TX_DC_CFG, |
8c8661e4 | 1013 | EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 1014 | { FR_AZ_RX_DC_CFG, |
8c8661e4 | 1015 | EFX_OWORD32(0x0000000F, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 1016 | { FR_AZ_RX_DC_PF_WM, |
8c8661e4 | 1017 | EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 1018 | { FR_BZ_DP_CTRL, |
8c8661e4 | 1019 | EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 1020 | { FR_AB_GM_CFG2, |
177dfcd8 | 1021 | EFX_OWORD32(0x00007337, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 1022 | { FR_AB_GMF_CFG0, |
177dfcd8 | 1023 | EFX_OWORD32(0x00001F1F, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 1024 | { FR_AB_XM_GLB_CFG, |
8c8661e4 | 1025 | EFX_OWORD32(0x00000C68, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 1026 | { FR_AB_XM_TX_CFG, |
8c8661e4 | 1027 | EFX_OWORD32(0x00080164, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 1028 | { FR_AB_XM_RX_CFG, |
8c8661e4 | 1029 | EFX_OWORD32(0x07100A0C, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 1030 | { FR_AB_XM_RX_PARAM, |
8c8661e4 | 1031 | EFX_OWORD32(0x00001FF8, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 1032 | { FR_AB_XM_FC, |
8c8661e4 | 1033 | EFX_OWORD32(0xFFFF0001, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 1034 | { FR_AB_XM_ADR_LO, |
8c8661e4 | 1035 | EFX_OWORD32(0xFFFFFFFF, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 1036 | { FR_AB_XX_SD_CTL, |
8c8661e4 BH |
1037 | EFX_OWORD32(0x0003FF0F, 0x00000000, 0x00000000, 0x00000000) }, |
1038 | }; | |
1039 | ||
d4f2cecc BH |
1040 | static int |
1041 | falcon_b0_test_chip(struct efx_nic *efx, struct efx_self_tests *tests) | |
152b6a62 | 1042 | { |
d4f2cecc BH |
1043 | enum reset_type reset_method = RESET_TYPE_INVISIBLE; |
1044 | int rc, rc2; | |
1045 | ||
1046 | mutex_lock(&efx->mac_lock); | |
1047 | if (efx->loopback_modes) { | |
1048 | /* We need the 312 clock from the PHY to test the XMAC | |
1049 | * registers, so move into XGMII loopback if available */ | |
1050 | if (efx->loopback_modes & (1 << LOOPBACK_XGMII)) | |
1051 | efx->loopback_mode = LOOPBACK_XGMII; | |
1052 | else | |
1053 | efx->loopback_mode = __ffs(efx->loopback_modes); | |
1054 | } | |
1055 | __efx_reconfigure_port(efx); | |
1056 | mutex_unlock(&efx->mac_lock); | |
1057 | ||
1058 | efx_reset_down(efx, reset_method); | |
1059 | ||
1060 | tests->registers = | |
1061 | efx_nic_test_registers(efx, falcon_b0_register_tests, | |
1062 | ARRAY_SIZE(falcon_b0_register_tests)) | |
1063 | ? -1 : 1; | |
1064 | ||
1065 | rc = falcon_reset_hw(efx, reset_method); | |
1066 | rc2 = efx_reset_up(efx, reset_method, rc == 0); | |
1067 | return rc ? rc : rc2; | |
152b6a62 BH |
1068 | } |
1069 | ||
8ceee660 BH |
1070 | /************************************************************************** |
1071 | * | |
1072 | * Device reset | |
1073 | * | |
1074 | ************************************************************************** | |
1075 | */ | |
1076 | ||
0e2a9c7c BH |
1077 | static enum reset_type falcon_map_reset_reason(enum reset_type reason) |
1078 | { | |
1079 | switch (reason) { | |
1080 | case RESET_TYPE_RX_RECOVERY: | |
1081 | case RESET_TYPE_RX_DESC_FETCH: | |
1082 | case RESET_TYPE_TX_DESC_FETCH: | |
1083 | case RESET_TYPE_TX_SKIP: | |
1084 | /* These can occasionally occur due to hardware bugs. | |
1085 | * We try to reset without disrupting the link. | |
1086 | */ | |
1087 | return RESET_TYPE_INVISIBLE; | |
1088 | default: | |
1089 | return RESET_TYPE_ALL; | |
1090 | } | |
1091 | } | |
1092 | ||
1093 | static int falcon_map_reset_flags(u32 *flags) | |
1094 | { | |
1095 | enum { | |
1096 | FALCON_RESET_INVISIBLE = (ETH_RESET_DMA | ETH_RESET_FILTER | | |
1097 | ETH_RESET_OFFLOAD | ETH_RESET_MAC), | |
1098 | FALCON_RESET_ALL = FALCON_RESET_INVISIBLE | ETH_RESET_PHY, | |
1099 | FALCON_RESET_WORLD = FALCON_RESET_ALL | ETH_RESET_IRQ, | |
1100 | }; | |
1101 | ||
1102 | if ((*flags & FALCON_RESET_WORLD) == FALCON_RESET_WORLD) { | |
1103 | *flags &= ~FALCON_RESET_WORLD; | |
1104 | return RESET_TYPE_WORLD; | |
1105 | } | |
1106 | ||
1107 | if ((*flags & FALCON_RESET_ALL) == FALCON_RESET_ALL) { | |
1108 | *flags &= ~FALCON_RESET_ALL; | |
1109 | return RESET_TYPE_ALL; | |
1110 | } | |
1111 | ||
1112 | if ((*flags & FALCON_RESET_INVISIBLE) == FALCON_RESET_INVISIBLE) { | |
1113 | *flags &= ~FALCON_RESET_INVISIBLE; | |
1114 | return RESET_TYPE_INVISIBLE; | |
1115 | } | |
1116 | ||
1117 | return -EINVAL; | |
1118 | } | |
1119 | ||
8ceee660 BH |
1120 | /* Resets NIC to known state. This routine must be called in process |
1121 | * context and is allowed to sleep. */ | |
4de92180 | 1122 | static int __falcon_reset_hw(struct efx_nic *efx, enum reset_type method) |
8ceee660 BH |
1123 | { |
1124 | struct falcon_nic_data *nic_data = efx->nic_data; | |
1125 | efx_oword_t glb_ctl_reg_ker; | |
1126 | int rc; | |
1127 | ||
62776d03 BH |
1128 | netif_dbg(efx, hw, efx->net_dev, "performing %s hardware reset\n", |
1129 | RESET_TYPE(method)); | |
8ceee660 BH |
1130 | |
1131 | /* Initiate device reset */ | |
1132 | if (method == RESET_TYPE_WORLD) { | |
1133 | rc = pci_save_state(efx->pci_dev); | |
1134 | if (rc) { | |
62776d03 BH |
1135 | netif_err(efx, drv, efx->net_dev, |
1136 | "failed to backup PCI state of primary " | |
1137 | "function prior to hardware reset\n"); | |
8ceee660 BH |
1138 | goto fail1; |
1139 | } | |
152b6a62 | 1140 | if (efx_nic_is_dual_func(efx)) { |
8ceee660 BH |
1141 | rc = pci_save_state(nic_data->pci_dev2); |
1142 | if (rc) { | |
62776d03 BH |
1143 | netif_err(efx, drv, efx->net_dev, |
1144 | "failed to backup PCI state of " | |
1145 | "secondary function prior to " | |
1146 | "hardware reset\n"); | |
8ceee660 BH |
1147 | goto fail2; |
1148 | } | |
1149 | } | |
1150 | ||
1151 | EFX_POPULATE_OWORD_2(glb_ctl_reg_ker, | |
3e6c4538 BH |
1152 | FRF_AB_EXT_PHY_RST_DUR, |
1153 | FFE_AB_EXT_PHY_RST_DUR_10240US, | |
1154 | FRF_AB_SWRST, 1); | |
8ceee660 | 1155 | } else { |
8ceee660 | 1156 | EFX_POPULATE_OWORD_7(glb_ctl_reg_ker, |
3e6c4538 BH |
1157 | /* exclude PHY from "invisible" reset */ |
1158 | FRF_AB_EXT_PHY_RST_CTL, | |
1159 | method == RESET_TYPE_INVISIBLE, | |
1160 | /* exclude EEPROM/flash and PCIe */ | |
1161 | FRF_AB_PCIE_CORE_RST_CTL, 1, | |
1162 | FRF_AB_PCIE_NSTKY_RST_CTL, 1, | |
1163 | FRF_AB_PCIE_SD_RST_CTL, 1, | |
1164 | FRF_AB_EE_RST_CTL, 1, | |
1165 | FRF_AB_EXT_PHY_RST_DUR, | |
1166 | FFE_AB_EXT_PHY_RST_DUR_10240US, | |
1167 | FRF_AB_SWRST, 1); | |
1168 | } | |
12d00cad | 1169 | efx_writeo(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL); |
8ceee660 | 1170 | |
62776d03 | 1171 | netif_dbg(efx, hw, efx->net_dev, "waiting for hardware reset\n"); |
8ceee660 BH |
1172 | schedule_timeout_uninterruptible(HZ / 20); |
1173 | ||
1174 | /* Restore PCI configuration if needed */ | |
1175 | if (method == RESET_TYPE_WORLD) { | |
1d3c16a8 JM |
1176 | if (efx_nic_is_dual_func(efx)) |
1177 | pci_restore_state(nic_data->pci_dev2); | |
1178 | pci_restore_state(efx->pci_dev); | |
62776d03 BH |
1179 | netif_dbg(efx, drv, efx->net_dev, |
1180 | "successfully restored PCI config\n"); | |
8ceee660 BH |
1181 | } |
1182 | ||
1183 | /* Assert that reset complete */ | |
12d00cad | 1184 | efx_reado(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL); |
3e6c4538 | 1185 | if (EFX_OWORD_FIELD(glb_ctl_reg_ker, FRF_AB_SWRST) != 0) { |
8ceee660 | 1186 | rc = -ETIMEDOUT; |
62776d03 BH |
1187 | netif_err(efx, hw, efx->net_dev, |
1188 | "timed out waiting for hardware reset\n"); | |
1d3c16a8 | 1189 | goto fail3; |
8ceee660 | 1190 | } |
62776d03 | 1191 | netif_dbg(efx, hw, efx->net_dev, "hardware reset complete\n"); |
8ceee660 BH |
1192 | |
1193 | return 0; | |
1194 | ||
1195 | /* pci_save_state() and pci_restore_state() MUST be called in pairs */ | |
1196 | fail2: | |
8ceee660 BH |
1197 | pci_restore_state(efx->pci_dev); |
1198 | fail1: | |
1d3c16a8 | 1199 | fail3: |
8ceee660 BH |
1200 | return rc; |
1201 | } | |
1202 | ||
4de92180 BH |
1203 | static int falcon_reset_hw(struct efx_nic *efx, enum reset_type method) |
1204 | { | |
1205 | struct falcon_nic_data *nic_data = efx->nic_data; | |
1206 | int rc; | |
1207 | ||
1208 | mutex_lock(&nic_data->spi_lock); | |
1209 | rc = __falcon_reset_hw(efx, method); | |
1210 | mutex_unlock(&nic_data->spi_lock); | |
1211 | ||
1212 | return rc; | |
1213 | } | |
1214 | ||
ef2b90ee | 1215 | static void falcon_monitor(struct efx_nic *efx) |
fe75820b | 1216 | { |
fdaa9aed | 1217 | bool link_changed; |
fe75820b BH |
1218 | int rc; |
1219 | ||
fdaa9aed SH |
1220 | BUG_ON(!mutex_is_locked(&efx->mac_lock)); |
1221 | ||
fe75820b BH |
1222 | rc = falcon_board(efx)->type->monitor(efx); |
1223 | if (rc) { | |
62776d03 BH |
1224 | netif_err(efx, hw, efx->net_dev, |
1225 | "Board sensor %s; shutting down PHY\n", | |
1226 | (rc == -ERANGE) ? "reported fault" : "failed"); | |
fe75820b | 1227 | efx->phy_mode |= PHY_MODE_LOW_POWER; |
d3245b28 BH |
1228 | rc = __efx_reconfigure_port(efx); |
1229 | WARN_ON(rc); | |
fe75820b | 1230 | } |
fdaa9aed SH |
1231 | |
1232 | if (LOOPBACK_INTERNAL(efx)) | |
1233 | link_changed = falcon_loopback_link_poll(efx); | |
1234 | else | |
1235 | link_changed = efx->phy_op->poll(efx); | |
1236 | ||
1237 | if (link_changed) { | |
1238 | falcon_stop_nic_stats(efx); | |
1239 | falcon_deconfigure_mac_wrapper(efx); | |
1240 | ||
8fbca791 | 1241 | falcon_reset_macs(efx); |
710b208d | 1242 | rc = falcon_reconfigure_xmac(efx); |
d3245b28 | 1243 | BUG_ON(rc); |
fdaa9aed SH |
1244 | |
1245 | falcon_start_nic_stats(efx); | |
1246 | ||
1247 | efx_link_status_changed(efx); | |
1248 | } | |
1249 | ||
8fbca791 | 1250 | falcon_poll_xmac(efx); |
fe75820b BH |
1251 | } |
1252 | ||
8ceee660 BH |
1253 | /* Zeroes out the SRAM contents. This routine must be called in |
1254 | * process context and is allowed to sleep. | |
1255 | */ | |
1256 | static int falcon_reset_sram(struct efx_nic *efx) | |
1257 | { | |
1258 | efx_oword_t srm_cfg_reg_ker, gpio_cfg_reg_ker; | |
1259 | int count; | |
1260 | ||
1261 | /* Set the SRAM wake/sleep GPIO appropriately. */ | |
12d00cad | 1262 | efx_reado(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL); |
3e6c4538 BH |
1263 | EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OEN, 1); |
1264 | EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OUT, 1); | |
12d00cad | 1265 | efx_writeo(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL); |
8ceee660 BH |
1266 | |
1267 | /* Initiate SRAM reset */ | |
1268 | EFX_POPULATE_OWORD_2(srm_cfg_reg_ker, | |
3e6c4538 BH |
1269 | FRF_AZ_SRM_INIT_EN, 1, |
1270 | FRF_AZ_SRM_NB_SZ, 0); | |
12d00cad | 1271 | efx_writeo(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG); |
8ceee660 BH |
1272 | |
1273 | /* Wait for SRAM reset to complete */ | |
1274 | count = 0; | |
1275 | do { | |
62776d03 BH |
1276 | netif_dbg(efx, hw, efx->net_dev, |
1277 | "waiting for SRAM reset (attempt %d)...\n", count); | |
8ceee660 BH |
1278 | |
1279 | /* SRAM reset is slow; expect around 16ms */ | |
1280 | schedule_timeout_uninterruptible(HZ / 50); | |
1281 | ||
1282 | /* Check for reset complete */ | |
12d00cad | 1283 | efx_reado(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG); |
3e6c4538 | 1284 | if (!EFX_OWORD_FIELD(srm_cfg_reg_ker, FRF_AZ_SRM_INIT_EN)) { |
62776d03 BH |
1285 | netif_dbg(efx, hw, efx->net_dev, |
1286 | "SRAM reset complete\n"); | |
8ceee660 BH |
1287 | |
1288 | return 0; | |
1289 | } | |
25985edc | 1290 | } while (++count < 20); /* wait up to 0.4 sec */ |
8ceee660 | 1291 | |
62776d03 | 1292 | netif_err(efx, hw, efx->net_dev, "timed out waiting for SRAM reset\n"); |
8ceee660 BH |
1293 | return -ETIMEDOUT; |
1294 | } | |
1295 | ||
4de92180 BH |
1296 | static void falcon_spi_device_init(struct efx_nic *efx, |
1297 | struct efx_spi_device *spi_device, | |
4a5b504d BH |
1298 | unsigned int device_id, u32 device_type) |
1299 | { | |
4a5b504d | 1300 | if (device_type != 0) { |
4a5b504d BH |
1301 | spi_device->device_id = device_id; |
1302 | spi_device->size = | |
1303 | 1 << SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_SIZE); | |
1304 | spi_device->addr_len = | |
1305 | SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ADDR_LEN); | |
1306 | spi_device->munge_address = (spi_device->size == 1 << 9 && | |
1307 | spi_device->addr_len == 1); | |
f4150724 BH |
1308 | spi_device->erase_command = |
1309 | SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ERASE_CMD); | |
1310 | spi_device->erase_size = | |
1311 | 1 << SPI_DEV_TYPE_FIELD(device_type, | |
1312 | SPI_DEV_TYPE_ERASE_SIZE); | |
4a5b504d BH |
1313 | spi_device->block_size = |
1314 | 1 << SPI_DEV_TYPE_FIELD(device_type, | |
1315 | SPI_DEV_TYPE_BLOCK_SIZE); | |
4a5b504d | 1316 | } else { |
4de92180 | 1317 | spi_device->size = 0; |
4a5b504d | 1318 | } |
4a5b504d BH |
1319 | } |
1320 | ||
8ceee660 BH |
1321 | /* Extract non-volatile configuration */ |
1322 | static int falcon_probe_nvconfig(struct efx_nic *efx) | |
1323 | { | |
4de92180 | 1324 | struct falcon_nic_data *nic_data = efx->nic_data; |
8ceee660 | 1325 | struct falcon_nvconfig *nvconfig; |
8ceee660 BH |
1326 | int rc; |
1327 | ||
8ceee660 | 1328 | nvconfig = kmalloc(sizeof(*nvconfig), GFP_KERNEL); |
4a5b504d BH |
1329 | if (!nvconfig) |
1330 | return -ENOMEM; | |
8ceee660 | 1331 | |
8c8661e4 | 1332 | rc = falcon_read_nvram(efx, nvconfig); |
6c88b0b6 | 1333 | if (rc) |
4de92180 | 1334 | goto out; |
6c88b0b6 BH |
1335 | |
1336 | efx->phy_type = nvconfig->board_v2.port0_phy_type; | |
1337 | efx->mdio.prtad = nvconfig->board_v2.port0_phy_addr; | |
1338 | ||
1339 | if (le16_to_cpu(nvconfig->board_struct_ver) >= 3) { | |
4de92180 BH |
1340 | falcon_spi_device_init( |
1341 | efx, &nic_data->spi_flash, FFE_AB_SPI_DEVICE_FLASH, | |
6c88b0b6 BH |
1342 | le32_to_cpu(nvconfig->board_v3 |
1343 | .spi_device_type[FFE_AB_SPI_DEVICE_FLASH])); | |
4de92180 BH |
1344 | falcon_spi_device_init( |
1345 | efx, &nic_data->spi_eeprom, FFE_AB_SPI_DEVICE_EEPROM, | |
6c88b0b6 BH |
1346 | le32_to_cpu(nvconfig->board_v3 |
1347 | .spi_device_type[FFE_AB_SPI_DEVICE_EEPROM])); | |
8ceee660 BH |
1348 | } |
1349 | ||
8c8661e4 | 1350 | /* Read the MAC addresses */ |
7e300bc8 | 1351 | memcpy(efx->net_dev->perm_addr, nvconfig->mac_address[0], ETH_ALEN); |
8c8661e4 | 1352 | |
62776d03 BH |
1353 | netif_dbg(efx, probe, efx->net_dev, "PHY is %d phy_id %d\n", |
1354 | efx->phy_type, efx->mdio.prtad); | |
8ceee660 | 1355 | |
6c88b0b6 BH |
1356 | rc = falcon_probe_board(efx, |
1357 | le16_to_cpu(nvconfig->board_v2.board_revision)); | |
4de92180 | 1358 | out: |
8ceee660 BH |
1359 | kfree(nvconfig); |
1360 | return rc; | |
1361 | } | |
1362 | ||
28e47c49 BH |
1363 | static void falcon_dimension_resources(struct efx_nic *efx) |
1364 | { | |
1365 | efx->rx_dc_base = 0x20000; | |
1366 | efx->tx_dc_base = 0x26000; | |
1367 | } | |
1368 | ||
4a5b504d BH |
1369 | /* Probe all SPI devices on the NIC */ |
1370 | static void falcon_probe_spi_devices(struct efx_nic *efx) | |
1371 | { | |
4de92180 | 1372 | struct falcon_nic_data *nic_data = efx->nic_data; |
4a5b504d | 1373 | efx_oword_t nic_stat, gpio_ctl, ee_vpd_cfg; |
2f7f5730 | 1374 | int boot_dev; |
4a5b504d | 1375 | |
12d00cad BH |
1376 | efx_reado(efx, &gpio_ctl, FR_AB_GPIO_CTL); |
1377 | efx_reado(efx, &nic_stat, FR_AB_NIC_STAT); | |
1378 | efx_reado(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0); | |
4a5b504d | 1379 | |
3e6c4538 BH |
1380 | if (EFX_OWORD_FIELD(gpio_ctl, FRF_AB_GPIO3_PWRUP_VALUE)) { |
1381 | boot_dev = (EFX_OWORD_FIELD(nic_stat, FRF_AB_SF_PRST) ? | |
1382 | FFE_AB_SPI_DEVICE_FLASH : FFE_AB_SPI_DEVICE_EEPROM); | |
62776d03 BH |
1383 | netif_dbg(efx, probe, efx->net_dev, "Booted from %s\n", |
1384 | boot_dev == FFE_AB_SPI_DEVICE_FLASH ? | |
1385 | "flash" : "EEPROM"); | |
2f7f5730 BH |
1386 | } else { |
1387 | /* Disable VPD and set clock dividers to safe | |
1388 | * values for initial programming. */ | |
1389 | boot_dev = -1; | |
62776d03 BH |
1390 | netif_dbg(efx, probe, efx->net_dev, |
1391 | "Booted from internal ASIC settings;" | |
1392 | " setting SPI config\n"); | |
3e6c4538 | 1393 | EFX_POPULATE_OWORD_3(ee_vpd_cfg, FRF_AB_EE_VPD_EN, 0, |
2f7f5730 | 1394 | /* 125 MHz / 7 ~= 20 MHz */ |
3e6c4538 | 1395 | FRF_AB_EE_SF_CLOCK_DIV, 7, |
2f7f5730 | 1396 | /* 125 MHz / 63 ~= 2 MHz */ |
3e6c4538 | 1397 | FRF_AB_EE_EE_CLOCK_DIV, 63); |
12d00cad | 1398 | efx_writeo(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0); |
4a5b504d BH |
1399 | } |
1400 | ||
4de92180 BH |
1401 | mutex_init(&nic_data->spi_lock); |
1402 | ||
3e6c4538 | 1403 | if (boot_dev == FFE_AB_SPI_DEVICE_FLASH) |
4de92180 | 1404 | falcon_spi_device_init(efx, &nic_data->spi_flash, |
3e6c4538 | 1405 | FFE_AB_SPI_DEVICE_FLASH, |
2f7f5730 | 1406 | default_flash_type); |
3e6c4538 | 1407 | if (boot_dev == FFE_AB_SPI_DEVICE_EEPROM) |
4de92180 | 1408 | falcon_spi_device_init(efx, &nic_data->spi_eeprom, |
3e6c4538 | 1409 | FFE_AB_SPI_DEVICE_EEPROM, |
2f7f5730 | 1410 | large_eeprom_type); |
4a5b504d BH |
1411 | } |
1412 | ||
ef2b90ee | 1413 | static int falcon_probe_nic(struct efx_nic *efx) |
8ceee660 BH |
1414 | { |
1415 | struct falcon_nic_data *nic_data; | |
e775fb93 | 1416 | struct falcon_board *board; |
8ceee660 BH |
1417 | int rc; |
1418 | ||
8ceee660 BH |
1419 | /* Allocate storage for hardware specific data */ |
1420 | nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL); | |
88c59425 BH |
1421 | if (!nic_data) |
1422 | return -ENOMEM; | |
5daab96d | 1423 | efx->nic_data = nic_data; |
8ceee660 | 1424 | |
57849460 BH |
1425 | rc = -ENODEV; |
1426 | ||
1427 | if (efx_nic_fpga_ver(efx) != 0) { | |
62776d03 BH |
1428 | netif_err(efx, probe, efx->net_dev, |
1429 | "Falcon FPGA not supported\n"); | |
8ceee660 | 1430 | goto fail1; |
57849460 BH |
1431 | } |
1432 | ||
1433 | if (efx_nic_rev(efx) <= EFX_REV_FALCON_A1) { | |
1434 | efx_oword_t nic_stat; | |
1435 | struct pci_dev *dev; | |
1436 | u8 pci_rev = efx->pci_dev->revision; | |
8ceee660 | 1437 | |
57849460 | 1438 | if ((pci_rev == 0xff) || (pci_rev == 0)) { |
62776d03 BH |
1439 | netif_err(efx, probe, efx->net_dev, |
1440 | "Falcon rev A0 not supported\n"); | |
57849460 BH |
1441 | goto fail1; |
1442 | } | |
1443 | efx_reado(efx, &nic_stat, FR_AB_NIC_STAT); | |
1444 | if (EFX_OWORD_FIELD(nic_stat, FRF_AB_STRAP_10G) == 0) { | |
62776d03 BH |
1445 | netif_err(efx, probe, efx->net_dev, |
1446 | "Falcon rev A1 1G not supported\n"); | |
57849460 BH |
1447 | goto fail1; |
1448 | } | |
1449 | if (EFX_OWORD_FIELD(nic_stat, FRF_AA_STRAP_PCIE) == 0) { | |
62776d03 BH |
1450 | netif_err(efx, probe, efx->net_dev, |
1451 | "Falcon rev A1 PCI-X not supported\n"); | |
57849460 BH |
1452 | goto fail1; |
1453 | } | |
8ceee660 | 1454 | |
57849460 | 1455 | dev = pci_dev_get(efx->pci_dev); |
937383a5 BH |
1456 | while ((dev = pci_get_device(PCI_VENDOR_ID_SOLARFLARE, |
1457 | PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, | |
8ceee660 BH |
1458 | dev))) { |
1459 | if (dev->bus == efx->pci_dev->bus && | |
1460 | dev->devfn == efx->pci_dev->devfn + 1) { | |
1461 | nic_data->pci_dev2 = dev; | |
1462 | break; | |
1463 | } | |
1464 | } | |
1465 | if (!nic_data->pci_dev2) { | |
62776d03 BH |
1466 | netif_err(efx, probe, efx->net_dev, |
1467 | "failed to find secondary function\n"); | |
8ceee660 BH |
1468 | rc = -ENODEV; |
1469 | goto fail2; | |
1470 | } | |
1471 | } | |
1472 | ||
1473 | /* Now we can reset the NIC */ | |
4de92180 | 1474 | rc = __falcon_reset_hw(efx, RESET_TYPE_ALL); |
8ceee660 | 1475 | if (rc) { |
62776d03 | 1476 | netif_err(efx, probe, efx->net_dev, "failed to reset NIC\n"); |
8ceee660 BH |
1477 | goto fail3; |
1478 | } | |
1479 | ||
1480 | /* Allocate memory for INT_KER */ | |
152b6a62 | 1481 | rc = efx_nic_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t)); |
8ceee660 BH |
1482 | if (rc) |
1483 | goto fail4; | |
1484 | BUG_ON(efx->irq_status.dma_addr & 0x0f); | |
1485 | ||
62776d03 BH |
1486 | netif_dbg(efx, probe, efx->net_dev, |
1487 | "INT_KER at %llx (virt %p phys %llx)\n", | |
1488 | (u64)efx->irq_status.dma_addr, | |
1489 | efx->irq_status.addr, | |
1490 | (u64)virt_to_phys(efx->irq_status.addr)); | |
8ceee660 | 1491 | |
4a5b504d BH |
1492 | falcon_probe_spi_devices(efx); |
1493 | ||
8ceee660 BH |
1494 | /* Read in the non-volatile configuration */ |
1495 | rc = falcon_probe_nvconfig(efx); | |
6c88b0b6 BH |
1496 | if (rc) { |
1497 | if (rc == -EINVAL) | |
1498 | netif_err(efx, probe, efx->net_dev, "NVRAM is invalid\n"); | |
8ceee660 | 1499 | goto fail5; |
6c88b0b6 | 1500 | } |
8ceee660 | 1501 | |
cc180b69 BH |
1502 | efx->timer_quantum_ns = 4968; /* 621 cycles */ |
1503 | ||
37b5a603 | 1504 | /* Initialise I2C adapter */ |
e775fb93 BH |
1505 | board = falcon_board(efx); |
1506 | board->i2c_adap.owner = THIS_MODULE; | |
1507 | board->i2c_data = falcon_i2c_bit_operations; | |
1508 | board->i2c_data.data = efx; | |
1509 | board->i2c_adap.algo_data = &board->i2c_data; | |
1510 | board->i2c_adap.dev.parent = &efx->pci_dev->dev; | |
1511 | strlcpy(board->i2c_adap.name, "SFC4000 GPIO", | |
1512 | sizeof(board->i2c_adap.name)); | |
1513 | rc = i2c_bit_add_bus(&board->i2c_adap); | |
37b5a603 BH |
1514 | if (rc) |
1515 | goto fail5; | |
1516 | ||
44838a44 | 1517 | rc = falcon_board(efx)->type->init(efx); |
278c0621 | 1518 | if (rc) { |
62776d03 BH |
1519 | netif_err(efx, probe, efx->net_dev, |
1520 | "failed to initialise board\n"); | |
278c0621 BH |
1521 | goto fail6; |
1522 | } | |
1523 | ||
55edc6e6 BH |
1524 | nic_data->stats_disable_count = 1; |
1525 | setup_timer(&nic_data->stats_timer, &falcon_stats_timer_func, | |
1526 | (unsigned long)efx); | |
1527 | ||
8ceee660 BH |
1528 | return 0; |
1529 | ||
278c0621 | 1530 | fail6: |
bf51a8c5 | 1531 | i2c_del_adapter(&board->i2c_adap); |
e775fb93 | 1532 | memset(&board->i2c_adap, 0, sizeof(board->i2c_adap)); |
8ceee660 | 1533 | fail5: |
152b6a62 | 1534 | efx_nic_free_buffer(efx, &efx->irq_status); |
8ceee660 | 1535 | fail4: |
8ceee660 BH |
1536 | fail3: |
1537 | if (nic_data->pci_dev2) { | |
1538 | pci_dev_put(nic_data->pci_dev2); | |
1539 | nic_data->pci_dev2 = NULL; | |
1540 | } | |
1541 | fail2: | |
8ceee660 BH |
1542 | fail1: |
1543 | kfree(efx->nic_data); | |
1544 | return rc; | |
1545 | } | |
1546 | ||
56241ceb BH |
1547 | static void falcon_init_rx_cfg(struct efx_nic *efx) |
1548 | { | |
56241ceb BH |
1549 | /* RX control FIFO thresholds (32 entries) */ |
1550 | const unsigned ctrl_xon_thr = 20; | |
1551 | const unsigned ctrl_xoff_thr = 25; | |
56241ceb BH |
1552 | efx_oword_t reg; |
1553 | ||
12d00cad | 1554 | efx_reado(efx, ®, FR_AZ_RX_CFG); |
daeda630 | 1555 | if (efx_nic_rev(efx) <= EFX_REV_FALCON_A1) { |
85740cdf BH |
1556 | /* Data FIFO size is 5.5K. The RX DMA engine only |
1557 | * supports scattering for user-mode queues, but will | |
1558 | * split DMA writes at intervals of RX_USR_BUF_SIZE | |
1559 | * (32-byte units) even for kernel-mode queues. We | |
1560 | * set it to be so large that that never happens. | |
1561 | */ | |
3e6c4538 BH |
1562 | EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_DESC_PUSH_EN, 0); |
1563 | EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_USR_BUF_SIZE, | |
85740cdf | 1564 | (3 * 4096) >> 5); |
5fb6b06d BH |
1565 | EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_MAC_TH, 512 >> 8); |
1566 | EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_MAC_TH, 2048 >> 8); | |
3e6c4538 BH |
1567 | EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_TX_TH, ctrl_xon_thr); |
1568 | EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_TX_TH, ctrl_xoff_thr); | |
56241ceb | 1569 | } else { |
625b4514 | 1570 | /* Data FIFO size is 80K; register fields moved */ |
3e6c4538 BH |
1571 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_DESC_PUSH_EN, 0); |
1572 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_USR_BUF_SIZE, | |
85740cdf | 1573 | EFX_RX_USR_BUF_SIZE >> 5); |
5fb6b06d BH |
1574 | /* Send XON and XOFF at ~3 * max MTU away from empty/full */ |
1575 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_MAC_TH, 27648 >> 8); | |
1576 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_MAC_TH, 54272 >> 8); | |
3e6c4538 BH |
1577 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_TX_TH, ctrl_xon_thr); |
1578 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_TX_TH, ctrl_xoff_thr); | |
1579 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 1); | |
477e54eb BH |
1580 | |
1581 | /* Enable hash insertion. This is broken for the | |
1582 | * 'Falcon' hash so also select Toeplitz TCP/IPv4 and | |
1583 | * IPv4 hashes. */ | |
1584 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_HASH_INSRT_HDR, 1); | |
1585 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_HASH_ALG, 1); | |
1586 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_IP_HASH, 1); | |
56241ceb | 1587 | } |
4b0d29dc BH |
1588 | /* Always enable XOFF signal from RX FIFO. We enable |
1589 | * or disable transmission of pause frames at the MAC. */ | |
1590 | EFX_SET_OWORD_FIELD(reg, FRF_AZ_RX_XOFF_MAC_EN, 1); | |
12d00cad | 1591 | efx_writeo(efx, ®, FR_AZ_RX_CFG); |
56241ceb BH |
1592 | } |
1593 | ||
152b6a62 BH |
1594 | /* This call performs hardware-specific global initialisation, such as |
1595 | * defining the descriptor cache sizes and number of RSS channels. | |
1596 | * It does not set up any buffers, descriptor rings or event queues. | |
1597 | */ | |
1598 | static int falcon_init_nic(struct efx_nic *efx) | |
1599 | { | |
1600 | efx_oword_t temp; | |
1601 | int rc; | |
1602 | ||
1603 | /* Use on-chip SRAM */ | |
1604 | efx_reado(efx, &temp, FR_AB_NIC_STAT); | |
1605 | EFX_SET_OWORD_FIELD(temp, FRF_AB_ONCHIP_SRAM, 1); | |
1606 | efx_writeo(efx, &temp, FR_AB_NIC_STAT); | |
1607 | ||
152b6a62 BH |
1608 | rc = falcon_reset_sram(efx); |
1609 | if (rc) | |
1610 | return rc; | |
1611 | ||
1612 | /* Clear the parity enables on the TX data fifos as | |
1613 | * they produce false parity errors because of timing issues | |
1614 | */ | |
1615 | if (EFX_WORKAROUND_5129(efx)) { | |
1616 | efx_reado(efx, &temp, FR_AZ_CSR_SPARE); | |
1617 | EFX_SET_OWORD_FIELD(temp, FRF_AB_MEM_PERR_EN_TX_DATA, 0); | |
1618 | efx_writeo(efx, &temp, FR_AZ_CSR_SPARE); | |
1619 | } | |
1620 | ||
8ceee660 | 1621 | if (EFX_WORKAROUND_7244(efx)) { |
12d00cad | 1622 | efx_reado(efx, &temp, FR_BZ_RX_FILTER_CTL); |
3e6c4538 BH |
1623 | EFX_SET_OWORD_FIELD(temp, FRF_BZ_UDP_FULL_SRCH_LIMIT, 8); |
1624 | EFX_SET_OWORD_FIELD(temp, FRF_BZ_UDP_WILD_SRCH_LIMIT, 8); | |
1625 | EFX_SET_OWORD_FIELD(temp, FRF_BZ_TCP_FULL_SRCH_LIMIT, 8); | |
1626 | EFX_SET_OWORD_FIELD(temp, FRF_BZ_TCP_WILD_SRCH_LIMIT, 8); | |
12d00cad | 1627 | efx_writeo(efx, &temp, FR_BZ_RX_FILTER_CTL); |
8ceee660 | 1628 | } |
8ceee660 | 1629 | |
3e6c4538 | 1630 | /* XXX This is documented only for Falcon A0/A1 */ |
8ceee660 BH |
1631 | /* Setup RX. Wait for descriptor is broken and must |
1632 | * be disabled. RXDP recovery shouldn't be needed, but is. | |
1633 | */ | |
12d00cad | 1634 | efx_reado(efx, &temp, FR_AA_RX_SELF_RST); |
3e6c4538 BH |
1635 | EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_NODESC_WAIT_DIS, 1); |
1636 | EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_SELF_RST_EN, 1); | |
8ceee660 | 1637 | if (EFX_WORKAROUND_5583(efx)) |
3e6c4538 | 1638 | EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_ISCSI_DIS, 1); |
12d00cad | 1639 | efx_writeo(efx, &temp, FR_AA_RX_SELF_RST); |
8ceee660 | 1640 | |
8ceee660 BH |
1641 | /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16 |
1642 | * descriptors (which is bad). | |
1643 | */ | |
12d00cad | 1644 | efx_reado(efx, &temp, FR_AZ_TX_CFG); |
3e6c4538 | 1645 | EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_NO_EOP_DISC_EN, 0); |
12d00cad | 1646 | efx_writeo(efx, &temp, FR_AZ_TX_CFG); |
8ceee660 | 1647 | |
56241ceb | 1648 | falcon_init_rx_cfg(efx); |
8ceee660 | 1649 | |
daeda630 | 1650 | if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) { |
477e54eb BH |
1651 | /* Set hash key for IPv4 */ |
1652 | memcpy(&temp, efx->rx_hash_key, sizeof(temp)); | |
1653 | efx_writeo(efx, &temp, FR_BZ_RX_RSS_TKEY); | |
1654 | ||
1655 | /* Set destination of both TX and RX Flush events */ | |
3e6c4538 | 1656 | EFX_POPULATE_OWORD_1(temp, FRF_BZ_FLS_EVQ_ID, 0); |
12d00cad | 1657 | efx_writeo(efx, &temp, FR_BZ_DP_CTRL); |
8ceee660 BH |
1658 | } |
1659 | ||
152b6a62 BH |
1660 | efx_nic_init_common(efx); |
1661 | ||
8ceee660 BH |
1662 | return 0; |
1663 | } | |
1664 | ||
ef2b90ee | 1665 | static void falcon_remove_nic(struct efx_nic *efx) |
8ceee660 BH |
1666 | { |
1667 | struct falcon_nic_data *nic_data = efx->nic_data; | |
e775fb93 | 1668 | struct falcon_board *board = falcon_board(efx); |
37b5a603 | 1669 | |
44838a44 | 1670 | board->type->fini(efx); |
278c0621 | 1671 | |
8c870379 | 1672 | /* Remove I2C adapter and clear it in preparation for a retry */ |
bf51a8c5 | 1673 | i2c_del_adapter(&board->i2c_adap); |
e775fb93 | 1674 | memset(&board->i2c_adap, 0, sizeof(board->i2c_adap)); |
8ceee660 | 1675 | |
152b6a62 | 1676 | efx_nic_free_buffer(efx, &efx->irq_status); |
8ceee660 | 1677 | |
4de92180 | 1678 | __falcon_reset_hw(efx, RESET_TYPE_ALL); |
8ceee660 BH |
1679 | |
1680 | /* Release the second function after the reset */ | |
1681 | if (nic_data->pci_dev2) { | |
1682 | pci_dev_put(nic_data->pci_dev2); | |
1683 | nic_data->pci_dev2 = NULL; | |
1684 | } | |
1685 | ||
1686 | /* Tear down the private nic state */ | |
1687 | kfree(efx->nic_data); | |
1688 | efx->nic_data = NULL; | |
1689 | } | |
1690 | ||
ef2b90ee | 1691 | static void falcon_update_nic_stats(struct efx_nic *efx) |
8ceee660 | 1692 | { |
55edc6e6 | 1693 | struct falcon_nic_data *nic_data = efx->nic_data; |
8ceee660 BH |
1694 | efx_oword_t cnt; |
1695 | ||
55edc6e6 BH |
1696 | if (nic_data->stats_disable_count) |
1697 | return; | |
1698 | ||
12d00cad | 1699 | efx_reado(efx, &cnt, FR_AZ_RX_NODESC_DROP); |
3e6c4538 BH |
1700 | efx->n_rx_nodesc_drop_cnt += |
1701 | EFX_OWORD_FIELD(cnt, FRF_AB_RX_NODESC_DROP_CNT); | |
55edc6e6 BH |
1702 | |
1703 | if (nic_data->stats_pending && | |
1704 | *nic_data->stats_dma_done == FALCON_STATS_DONE) { | |
1705 | nic_data->stats_pending = false; | |
1706 | rmb(); /* read the done flag before the stats */ | |
710b208d | 1707 | falcon_update_stats_xmac(efx); |
55edc6e6 BH |
1708 | } |
1709 | } | |
1710 | ||
1711 | void falcon_start_nic_stats(struct efx_nic *efx) | |
1712 | { | |
1713 | struct falcon_nic_data *nic_data = efx->nic_data; | |
1714 | ||
1715 | spin_lock_bh(&efx->stats_lock); | |
1716 | if (--nic_data->stats_disable_count == 0) | |
1717 | falcon_stats_request(efx); | |
1718 | spin_unlock_bh(&efx->stats_lock); | |
1719 | } | |
1720 | ||
1721 | void falcon_stop_nic_stats(struct efx_nic *efx) | |
1722 | { | |
1723 | struct falcon_nic_data *nic_data = efx->nic_data; | |
1724 | int i; | |
1725 | ||
1726 | might_sleep(); | |
1727 | ||
1728 | spin_lock_bh(&efx->stats_lock); | |
1729 | ++nic_data->stats_disable_count; | |
1730 | spin_unlock_bh(&efx->stats_lock); | |
1731 | ||
1732 | del_timer_sync(&nic_data->stats_timer); | |
1733 | ||
1734 | /* Wait enough time for the most recent transfer to | |
1735 | * complete. */ | |
1736 | for (i = 0; i < 4 && nic_data->stats_pending; i++) { | |
1737 | if (*nic_data->stats_dma_done == FALCON_STATS_DONE) | |
1738 | break; | |
1739 | msleep(1); | |
1740 | } | |
1741 | ||
1742 | spin_lock_bh(&efx->stats_lock); | |
1743 | falcon_stats_complete(efx); | |
1744 | spin_unlock_bh(&efx->stats_lock); | |
8ceee660 BH |
1745 | } |
1746 | ||
06629f07 BH |
1747 | static void falcon_set_id_led(struct efx_nic *efx, enum efx_led_mode mode) |
1748 | { | |
1749 | falcon_board(efx)->type->set_id_led(efx, mode); | |
1750 | } | |
1751 | ||
89c758fa BH |
1752 | /************************************************************************** |
1753 | * | |
1754 | * Wake on LAN | |
1755 | * | |
1756 | ************************************************************************** | |
1757 | */ | |
1758 | ||
1759 | static void falcon_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol) | |
1760 | { | |
1761 | wol->supported = 0; | |
1762 | wol->wolopts = 0; | |
1763 | memset(&wol->sopass, 0, sizeof(wol->sopass)); | |
1764 | } | |
1765 | ||
1766 | static int falcon_set_wol(struct efx_nic *efx, u32 type) | |
1767 | { | |
1768 | if (type != 0) | |
1769 | return -EINVAL; | |
1770 | return 0; | |
1771 | } | |
1772 | ||
8ceee660 BH |
1773 | /************************************************************************** |
1774 | * | |
754c653a | 1775 | * Revision-dependent attributes used by efx.c and nic.c |
8ceee660 BH |
1776 | * |
1777 | ************************************************************************** | |
1778 | */ | |
1779 | ||
6c8c2513 | 1780 | const struct efx_nic_type falcon_a1_nic_type = { |
ef2b90ee BH |
1781 | .probe = falcon_probe_nic, |
1782 | .remove = falcon_remove_nic, | |
1783 | .init = falcon_init_nic, | |
28e47c49 | 1784 | .dimension_resources = falcon_dimension_resources, |
ef2b90ee BH |
1785 | .fini = efx_port_dummy_op_void, |
1786 | .monitor = falcon_monitor, | |
0e2a9c7c BH |
1787 | .map_reset_reason = falcon_map_reset_reason, |
1788 | .map_reset_flags = falcon_map_reset_flags, | |
ef2b90ee BH |
1789 | .reset = falcon_reset_hw, |
1790 | .probe_port = falcon_probe_port, | |
1791 | .remove_port = falcon_remove_port, | |
40641ed9 | 1792 | .handle_global_event = falcon_handle_global_event, |
ef2b90ee | 1793 | .prepare_flush = falcon_prepare_flush, |
d5e8cc6c | 1794 | .finish_flush = efx_port_dummy_op_void, |
ef2b90ee BH |
1795 | .update_stats = falcon_update_nic_stats, |
1796 | .start_stats = falcon_start_nic_stats, | |
1797 | .stop_stats = falcon_stop_nic_stats, | |
06629f07 | 1798 | .set_id_led = falcon_set_id_led, |
ef2b90ee | 1799 | .push_irq_moderation = falcon_push_irq_moderation, |
d3245b28 | 1800 | .reconfigure_port = falcon_reconfigure_port, |
710b208d BH |
1801 | .reconfigure_mac = falcon_reconfigure_xmac, |
1802 | .check_mac_fault = falcon_xmac_check_fault, | |
89c758fa BH |
1803 | .get_wol = falcon_get_wol, |
1804 | .set_wol = falcon_set_wol, | |
1805 | .resume_wol = efx_port_dummy_op_void, | |
0aa3fbaa | 1806 | .test_nvram = falcon_test_nvram, |
b895d73e | 1807 | |
daeda630 | 1808 | .revision = EFX_REV_FALCON_A1, |
8ceee660 | 1809 | .mem_map_size = 0x20000, |
3e6c4538 BH |
1810 | .txd_ptr_tbl_base = FR_AA_TX_DESC_PTR_TBL_KER, |
1811 | .rxd_ptr_tbl_base = FR_AA_RX_DESC_PTR_TBL_KER, | |
1812 | .buf_tbl_base = FR_AA_BUF_FULL_TBL_KER, | |
1813 | .evq_ptr_tbl_base = FR_AA_EVQ_PTR_TBL_KER, | |
1814 | .evq_rptr_tbl_base = FR_AA_EVQ_RPTR_KER, | |
6d51d307 | 1815 | .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH), |
8ceee660 | 1816 | .rx_buffer_padding = 0x24, |
85740cdf | 1817 | .can_rx_scatter = false, |
8ceee660 BH |
1818 | .max_interrupt_mode = EFX_INT_MODE_MSI, |
1819 | .phys_addr_channels = 4, | |
cc180b69 | 1820 | .timer_period_max = 1 << FRF_AB_TC_TIMER_VAL_WIDTH, |
c383b537 | 1821 | .offload_features = NETIF_F_IP_CSUM, |
8ceee660 BH |
1822 | }; |
1823 | ||
6c8c2513 | 1824 | const struct efx_nic_type falcon_b0_nic_type = { |
ef2b90ee BH |
1825 | .probe = falcon_probe_nic, |
1826 | .remove = falcon_remove_nic, | |
1827 | .init = falcon_init_nic, | |
28e47c49 | 1828 | .dimension_resources = falcon_dimension_resources, |
ef2b90ee BH |
1829 | .fini = efx_port_dummy_op_void, |
1830 | .monitor = falcon_monitor, | |
0e2a9c7c BH |
1831 | .map_reset_reason = falcon_map_reset_reason, |
1832 | .map_reset_flags = falcon_map_reset_flags, | |
ef2b90ee BH |
1833 | .reset = falcon_reset_hw, |
1834 | .probe_port = falcon_probe_port, | |
1835 | .remove_port = falcon_remove_port, | |
40641ed9 | 1836 | .handle_global_event = falcon_handle_global_event, |
ef2b90ee | 1837 | .prepare_flush = falcon_prepare_flush, |
d5e8cc6c | 1838 | .finish_flush = efx_port_dummy_op_void, |
ef2b90ee BH |
1839 | .update_stats = falcon_update_nic_stats, |
1840 | .start_stats = falcon_start_nic_stats, | |
1841 | .stop_stats = falcon_stop_nic_stats, | |
06629f07 | 1842 | .set_id_led = falcon_set_id_led, |
ef2b90ee | 1843 | .push_irq_moderation = falcon_push_irq_moderation, |
d3245b28 | 1844 | .reconfigure_port = falcon_reconfigure_port, |
710b208d BH |
1845 | .reconfigure_mac = falcon_reconfigure_xmac, |
1846 | .check_mac_fault = falcon_xmac_check_fault, | |
89c758fa BH |
1847 | .get_wol = falcon_get_wol, |
1848 | .set_wol = falcon_set_wol, | |
1849 | .resume_wol = efx_port_dummy_op_void, | |
d4f2cecc | 1850 | .test_chip = falcon_b0_test_chip, |
0aa3fbaa | 1851 | .test_nvram = falcon_test_nvram, |
b895d73e | 1852 | |
daeda630 | 1853 | .revision = EFX_REV_FALCON_B0, |
8ceee660 BH |
1854 | /* Map everything up to and including the RSS indirection |
1855 | * table. Don't map MSI-X table, MSI-X PBA since Linux | |
1856 | * requires that they not be mapped. */ | |
3e6c4538 BH |
1857 | .mem_map_size = (FR_BZ_RX_INDIRECTION_TBL + |
1858 | FR_BZ_RX_INDIRECTION_TBL_STEP * | |
1859 | FR_BZ_RX_INDIRECTION_TBL_ROWS), | |
1860 | .txd_ptr_tbl_base = FR_BZ_TX_DESC_PTR_TBL, | |
1861 | .rxd_ptr_tbl_base = FR_BZ_RX_DESC_PTR_TBL, | |
1862 | .buf_tbl_base = FR_BZ_BUF_FULL_TBL, | |
1863 | .evq_ptr_tbl_base = FR_BZ_EVQ_PTR_TBL, | |
1864 | .evq_rptr_tbl_base = FR_BZ_EVQ_RPTR, | |
6d51d307 | 1865 | .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH), |
39c9cf07 | 1866 | .rx_buffer_hash_size = 0x10, |
8ceee660 | 1867 | .rx_buffer_padding = 0, |
85740cdf | 1868 | .can_rx_scatter = true, |
8ceee660 BH |
1869 | .max_interrupt_mode = EFX_INT_MODE_MSIX, |
1870 | .phys_addr_channels = 32, /* Hardware limit is 64, but the legacy | |
1871 | * interrupt handler only supports 32 | |
1872 | * channels */ | |
cc180b69 | 1873 | .timer_period_max = 1 << FRF_AB_TC_TIMER_VAL_WIDTH, |
b4187e42 | 1874 | .offload_features = NETIF_F_IP_CSUM | NETIF_F_RXHASH | NETIF_F_NTUPLE, |
8ceee660 BH |
1875 | }; |
1876 |