[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / sfc / nic.c

/****************************************************************************
 * Driver for Solarflare network controllers and boards
 * Copyright 2005-2006 Fen Systems Ltd.
 * Copyright 2006-2013 Solarflare Communications Inc.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published
 * by the Free Software Foundation, incorporated herein by reference.
 */

#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/pci.h>
#include <linux/module.h>
#include <linux/seq_file.h>
#include <linux/cpu_rmap.h>
#include "net_driver.h"
#include "bitfield.h"
#include "efx.h"
#include "nic.h"
#include "ef10_regs.h"
#include "farch_regs.h"
#include "io.h"
#include "workarounds.h"

/**************************************************************************
 *
 * Generic buffer handling
 * These buffers are used for interrupt status, MAC stats, etc.
 *
 **************************************************************************/

int efx_nic_alloc_buffer(struct efx_nic *efx, struct efx_buffer *buffer,
			 unsigned int len, gfp_t gfp_flags)
{
	buffer->addr = dma_zalloc_coherent(&efx->pci_dev->dev, len,
					   &buffer->dma_addr, gfp_flags);
	if (!buffer->addr)
		return -ENOMEM;
	buffer->len = len;
	return 0;
}

void efx_nic_free_buffer(struct efx_nic *efx, struct efx_buffer *buffer)
{
	if (buffer->addr) {
		dma_free_coherent(&efx->pci_dev->dev, buffer->len,
				  buffer->addr, buffer->dma_addr);
		buffer->addr = NULL;
	}
}

/* Check whether an event is present in the eventq at the current
 * read pointer.  Only useful for self-test.
 */
bool efx_nic_event_present(struct efx_channel *channel)
{
	return efx_event_present(efx_event(channel, channel->eventq_read_ptr));
}

void efx_nic_event_test_start(struct efx_channel *channel)
{
	channel->event_test_cpu = -1;
	smp_wmb();
	channel->efx->type->ev_test_generate(channel);
}

void efx_nic_irq_test_start(struct efx_nic *efx)
{
	efx->last_irq_cpu = -1;
	smp_wmb();
	efx->type->irq_test_generate(efx);
}

/* Hook interrupt handler(s)
 * Try MSI and then legacy interrupts.
 */
int efx_nic_init_interrupt(struct efx_nic *efx)
{
	struct efx_channel *channel;
	unsigned int n_irqs;
	int rc;

	if (!EFX_INT_MODE_USE_MSI(efx)) {
		rc = request_irq(efx->legacy_irq,
				 efx->type->irq_handle_legacy, IRQF_SHARED,
				 efx->name, efx);
		if (rc) {
			netif_err(efx, drv, efx->net_dev,
				  "failed to hook legacy IRQ %d\n",
				  efx->pci_dev->irq);
			goto fail1;
		}
		return 0;
	}

#ifdef CONFIG_RFS_ACCEL
	if (efx->interrupt_mode == EFX_INT_MODE_MSIX) {
		efx->net_dev->rx_cpu_rmap =
			alloc_irq_cpu_rmap(efx->n_rx_channels);
		if (!efx->net_dev->rx_cpu_rmap) {
			rc = -ENOMEM;
			goto fail1;
		}
	}
#endif

	/* Hook MSI or MSI-X interrupt */
	n_irqs = 0;
	efx_for_each_channel(channel, efx) {
		rc = request_irq(channel->irq, efx->type->irq_handle_msi,
				 IRQF_PROBE_SHARED, /* Not shared */
				 efx->msi_context[channel->channel].name,
				 &efx->msi_context[channel->channel]);
		if (rc) {
			netif_err(efx, drv, efx->net_dev,
				  "failed to hook IRQ %d\n", channel->irq);
			goto fail2;
		}
		++n_irqs;

#ifdef CONFIG_RFS_ACCEL
		if (efx->interrupt_mode == EFX_INT_MODE_MSIX &&
		    channel->channel < efx->n_rx_channels) {
			rc = irq_cpu_rmap_add(efx->net_dev->rx_cpu_rmap,
					      channel->irq);
			if (rc)
				goto fail2;
		}
#endif
	}

	return 0;

 fail2:
#ifdef CONFIG_RFS_ACCEL
	free_irq_cpu_rmap(efx->net_dev->rx_cpu_rmap);
	efx->net_dev->rx_cpu_rmap = NULL;
#endif
	efx_for_each_channel(channel, efx) {
		if (n_irqs-- == 0)
			break;
		free_irq(channel->irq, &efx->msi_context[channel->channel]);
	}
 fail1:
	return rc;
}

void efx_nic_fini_interrupt(struct efx_nic *efx)
{
	struct efx_channel *channel;

#ifdef CONFIG_RFS_ACCEL
	free_irq_cpu_rmap(efx->net_dev->rx_cpu_rmap);
	efx->net_dev->rx_cpu_rmap = NULL;
#endif

	/* Disable MSI/MSI-X interrupts */
	efx_for_each_channel(channel, efx)
		free_irq(channel->irq, &efx->msi_context[channel->channel]);

	/* Disable legacy interrupt */
	if (efx->legacy_irq)
		free_irq(efx->legacy_irq, efx);
}

/* Register dump */

#define REGISTER_REVISION_FA	1
#define REGISTER_REVISION_FB	2
#define REGISTER_REVISION_FC	3
#define REGISTER_REVISION_FZ	3	/* last Falcon arch revision */
#define REGISTER_REVISION_ED	4
#define REGISTER_REVISION_EZ	4	/* latest EF10 revision */

struct efx_nic_reg {
	u32 offset:24;
	u32 min_revision:3, max_revision:3;
};

#define REGISTER(name, arch, min_rev, max_rev) {			\
	arch ## R_ ## min_rev ## max_rev ## _ ## name,			\
	REGISTER_REVISION_ ## arch ## min_rev,				\
	REGISTER_REVISION_ ## arch ## max_rev				\
}
#define REGISTER_AA(name) REGISTER(name, F, A, A)
#define REGISTER_AB(name) REGISTER(name, F, A, B)
#define REGISTER_AZ(name) REGISTER(name, F, A, Z)
#define REGISTER_BB(name) REGISTER(name, F, B, B)
#define REGISTER_BZ(name) REGISTER(name, F, B, Z)
#define REGISTER_CZ(name) REGISTER(name, F, C, Z)
#define REGISTER_DZ(name) REGISTER(name, E, D, Z)

static const struct efx_nic_reg efx_nic_regs[] = {
	REGISTER_AZ(ADR_REGION),
	REGISTER_AZ(INT_EN_KER),
	REGISTER_BZ(INT_EN_CHAR),
	REGISTER_AZ(INT_ADR_KER),
	REGISTER_BZ(INT_ADR_CHAR),
	/* INT_ACK_KER is WO */
	/* INT_ISR0 is RC */
	REGISTER_AZ(HW_INIT),
	REGISTER_CZ(USR_EV_CFG),
	REGISTER_AB(EE_SPI_HCMD),
	REGISTER_AB(EE_SPI_HADR),
	REGISTER_AB(EE_SPI_HDATA),
	REGISTER_AB(EE_BASE_PAGE),
	REGISTER_AB(EE_VPD_CFG0),
	/* EE_VPD_SW_CNTL and EE_VPD_SW_DATA are not used */
	/* PMBX_DBG_IADDR and PBMX_DBG_IDATA are indirect */
	/* PCIE_CORE_INDIRECT is indirect */
	REGISTER_AB(NIC_STAT),
	REGISTER_AB(GPIO_CTL),
	REGISTER_AB(GLB_CTL),
	/* FATAL_INTR_KER and FATAL_INTR_CHAR are partly RC */
	REGISTER_BZ(DP_CTRL),
	REGISTER_AZ(MEM_STAT),
	REGISTER_AZ(CS_DEBUG),
	REGISTER_AZ(ALTERA_BUILD),
	REGISTER_AZ(CSR_SPARE),
	REGISTER_AB(PCIE_SD_CTL0123),
	REGISTER_AB(PCIE_SD_CTL45),
	REGISTER_AB(PCIE_PCS_CTL_STAT),
	/* DEBUG_DATA_OUT is not used */
	/* DRV_EV is WO */
	REGISTER_AZ(EVQ_CTL),
	REGISTER_AZ(EVQ_CNT1),
	REGISTER_AZ(EVQ_CNT2),
	REGISTER_AZ(BUF_TBL_CFG),
	REGISTER_AZ(SRM_RX_DC_CFG),
	REGISTER_AZ(SRM_TX_DC_CFG),
	REGISTER_AZ(SRM_CFG),
	/* BUF_TBL_UPD is WO */
	REGISTER_AZ(SRM_UPD_EVQ),
	REGISTER_AZ(SRAM_PARITY),
	REGISTER_AZ(RX_CFG),
	REGISTER_BZ(RX_FILTER_CTL),
	/* RX_FLUSH_DESCQ is WO */
	REGISTER_AZ(RX_DC_CFG),
	REGISTER_AZ(RX_DC_PF_WM),
	REGISTER_BZ(RX_RSS_TKEY),
	/* RX_NODESC_DROP is RC */
	REGISTER_AA(RX_SELF_RST),
	/* RX_DEBUG, RX_PUSH_DROP are not used */
	REGISTER_CZ(RX_RSS_IPV6_REG1),
	REGISTER_CZ(RX_RSS_IPV6_REG2),
	REGISTER_CZ(RX_RSS_IPV6_REG3),
	/* TX_FLUSH_DESCQ is WO */
	REGISTER_AZ(TX_DC_CFG),
	REGISTER_AA(TX_CHKSM_CFG),
	REGISTER_AZ(TX_CFG),
	/* TX_PUSH_DROP is not used */
	REGISTER_AZ(TX_RESERVED),
	REGISTER_BZ(TX_PACE),
	/* TX_PACE_DROP_QID is RC */
	REGISTER_BB(TX_VLAN),
	REGISTER_BZ(TX_IPFIL_PORTEN),
	REGISTER_AB(MD_TXD),
	REGISTER_AB(MD_RXD),
	REGISTER_AB(MD_CS),
	REGISTER_AB(MD_PHY_ADR),
	REGISTER_AB(MD_ID),
	/* MD_STAT is RC */
	REGISTER_AB(MAC_STAT_DMA),
	REGISTER_AB(MAC_CTRL),
	REGISTER_BB(GEN_MODE),
	REGISTER_AB(MAC_MC_HASH_REG0),
	REGISTER_AB(MAC_MC_HASH_REG1),
	REGISTER_AB(GM_CFG1),
	REGISTER_AB(GM_CFG2),
	/* GM_IPG and GM_HD are not used */
	REGISTER_AB(GM_MAX_FLEN),
	/* GM_TEST is not used */
	REGISTER_AB(GM_ADR1),
	REGISTER_AB(GM_ADR2),
	REGISTER_AB(GMF_CFG0),
	REGISTER_AB(GMF_CFG1),
	REGISTER_AB(GMF_CFG2),
	REGISTER_AB(GMF_CFG3),
	REGISTER_AB(GMF_CFG4),
	REGISTER_AB(GMF_CFG5),
	REGISTER_BB(TX_SRC_MAC_CTL),
	REGISTER_AB(XM_ADR_LO),
	REGISTER_AB(XM_ADR_HI),
	REGISTER_AB(XM_GLB_CFG),
	REGISTER_AB(XM_TX_CFG),
	REGISTER_AB(XM_RX_CFG),
	REGISTER_AB(XM_MGT_INT_MASK),
	REGISTER_AB(XM_FC),
	REGISTER_AB(XM_PAUSE_TIME),
	REGISTER_AB(XM_TX_PARAM),
	REGISTER_AB(XM_RX_PARAM),
	/* XM_MGT_INT_MSK (note no 'A') is RC */
	REGISTER_AB(XX_PWR_RST),
	REGISTER_AB(XX_SD_CTL),
	REGISTER_AB(XX_TXDRV_CTL),
	/* XX_PRBS_CTL, XX_PRBS_CHK and XX_PRBS_ERR are not used */
	/* XX_CORE_STAT is partly RC */
	REGISTER_DZ(BIU_HW_REV_ID),
	REGISTER_DZ(MC_DB_LWRD),
	REGISTER_DZ(MC_DB_HWRD),
};

struct efx_nic_reg_table {
	u32 offset:24;
	u32 min_revision:3, max_revision:3;
	u32 step:6, rows:21;
};

#define REGISTER_TABLE_DIMENSIONS(_, offset, arch, min_rev, max_rev, step, rows) { \
	offset,								\
	REGISTER_REVISION_ ## arch ## min_rev,				\
	REGISTER_REVISION_ ## arch ## max_rev,				\
	step, rows							\
}
#define REGISTER_TABLE(name, arch, min_rev, max_rev)			\
	REGISTER_TABLE_DIMENSIONS(					\
		name, arch ## R_ ## min_rev ## max_rev ## _ ## name,	\
		arch, min_rev, max_rev,					\
		arch ## R_ ## min_rev ## max_rev ## _ ## name ## _STEP,	\
		arch ## R_ ## min_rev ## max_rev ## _ ## name ## _ROWS)
#define REGISTER_TABLE_AA(name) REGISTER_TABLE(name, F, A, A)
#define REGISTER_TABLE_AZ(name) REGISTER_TABLE(name, F, A, Z)
#define REGISTER_TABLE_BB(name) REGISTER_TABLE(name, F, B, B)
#define REGISTER_TABLE_BZ(name) REGISTER_TABLE(name, F, B, Z)
#define REGISTER_TABLE_BB_CZ(name)					\
	REGISTER_TABLE_DIMENSIONS(name, FR_BZ_ ## name, F, B, B,	\
				  FR_BZ_ ## name ## _STEP,		\
				  FR_BB_ ## name ## _ROWS),		\
	REGISTER_TABLE_DIMENSIONS(name, FR_BZ_ ## name, F, C, Z,	\
				  FR_BZ_ ## name ## _STEP,		\
				  FR_CZ_ ## name ## _ROWS)
#define REGISTER_TABLE_CZ(name) REGISTER_TABLE(name, F, C, Z)
#define REGISTER_TABLE_DZ(name) REGISTER_TABLE(name, E, D, Z)

static const struct efx_nic_reg_table efx_nic_reg_tables[] = {
	/* DRIVER is not used */
	/* EVQ_RPTR, TIMER_COMMAND, USR_EV and {RX,TX}_DESC_UPD are WO */
	REGISTER_TABLE_BB(TX_IPFIL_TBL),
	REGISTER_TABLE_BB(TX_SRC_MAC_TBL),
	REGISTER_TABLE_AA(RX_DESC_PTR_TBL_KER),
	REGISTER_TABLE_BB_CZ(RX_DESC_PTR_TBL),
	REGISTER_TABLE_AA(TX_DESC_PTR_TBL_KER),
	REGISTER_TABLE_BB_CZ(TX_DESC_PTR_TBL),
	REGISTER_TABLE_AA(EVQ_PTR_TBL_KER),
	REGISTER_TABLE_BB_CZ(EVQ_PTR_TBL),
	/* We can't reasonably read all of the buffer table (up to 8MB!).
	 * However this driver will only use a few entries.  Reading
	 * 1K entries allows for some expansion of queue count and
	 * size before we need to change the version. */
	REGISTER_TABLE_DIMENSIONS(BUF_FULL_TBL_KER, FR_AA_BUF_FULL_TBL_KER,
				  F, A, A, 8, 1024),
	REGISTER_TABLE_DIMENSIONS(BUF_FULL_TBL, FR_BZ_BUF_FULL_TBL,
				  F, B, Z, 8, 1024),
	REGISTER_TABLE_CZ(RX_MAC_FILTER_TBL0),
	REGISTER_TABLE_BB_CZ(TIMER_TBL),
	REGISTER_TABLE_BB_CZ(TX_PACE_TBL),
	REGISTER_TABLE_BZ(RX_INDIRECTION_TBL),
	/* TX_FILTER_TBL0 is huge and not used by this driver */
	REGISTER_TABLE_CZ(TX_MAC_FILTER_TBL0),
	REGISTER_TABLE_CZ(MC_TREG_SMEM),
	/* MSIX_PBA_TABLE is not mapped */
	/* SRM_DBG is not mapped (and is redundant with BUF_FLL_TBL) */
	REGISTER_TABLE_BZ(RX_FILTER_TBL0),
	REGISTER_TABLE_DZ(BIU_MC_SFT_STATUS),
};

size_t efx_nic_get_regs_len(struct efx_nic *efx)
{
	const struct efx_nic_reg *reg;
	const struct efx_nic_reg_table *table;
	size_t len = 0;

	for (reg = efx_nic_regs;
	     reg < efx_nic_regs + ARRAY_SIZE(efx_nic_regs);
	     reg++)
		if (efx->type->revision >= reg->min_revision &&
		    efx->type->revision <= reg->max_revision)
			len += sizeof(efx_oword_t);

	for (table = efx_nic_reg_tables;
	     table < efx_nic_reg_tables + ARRAY_SIZE(efx_nic_reg_tables);
	     table++)
		if (efx->type->revision >= table->min_revision &&
		    efx->type->revision <= table->max_revision)
			len += table->rows * min_t(size_t, table->step, 16);

	return len;
}

void efx_nic_get_regs(struct efx_nic *efx, void *buf)
{
	const struct efx_nic_reg *reg;
	const struct efx_nic_reg_table *table;

	for (reg = efx_nic_regs;
	     reg < efx_nic_regs + ARRAY_SIZE(efx_nic_regs);
	     reg++) {
		if (efx->type->revision >= reg->min_revision &&
		    efx->type->revision <= reg->max_revision) {
			efx_reado(efx, (efx_oword_t *)buf, reg->offset);
			buf += sizeof(efx_oword_t);
		}
	}

	for (table = efx_nic_reg_tables;
	     table < efx_nic_reg_tables + ARRAY_SIZE(efx_nic_reg_tables);
	     table++) {
		size_t size, i;

		if (!(efx->type->revision >= table->min_revision &&
		      efx->type->revision <= table->max_revision))
			continue;

		size = min_t(size_t, table->step, 16);

		for (i = 0; i < table->rows; i++) {
			switch (table->step) {
			case 4: /* 32-bit SRAM */
				efx_readd(efx, buf, table->offset + 4 * i);
				break;
			case 8: /* 64-bit SRAM */
				efx_sram_readq(efx,
					       efx->membase + table->offset,
					       buf, i);
				break;
			case 16: /* 128-bit-readable register */
				efx_reado_table(efx, buf, table->offset, i);
				break;
			case 32: /* 128-bit register, interleaved */
				efx_reado_table(efx, buf, table->offset, 2 * i);
				break;
			default:
				WARN_ON(1);
				return;
			}
			buf += size;
		}
	}
}

/**
 * efx_nic_describe_stats - Describe supported statistics for ethtool
 * @desc: Array of &struct efx_hw_stat_desc describing the statistics
 * @count: Length of the @desc array
 * @mask: Bitmask of which elements of @desc are enabled
 * @names: Buffer to copy names to, or %NULL.  The names are copied
 *	starting at intervals of %ETH_GSTRING_LEN bytes.
 *
 * Returns the number of visible statistics, i.e. the number of set
 * bits in the first @count bits of @mask for which a name is defined.
 */
size_t efx_nic_describe_stats(const struct efx_hw_stat_desc *desc, size_t count,
			      const unsigned long *mask, u8 *names)
{
	size_t visible = 0;
	size_t index;

	for_each_set_bit(index, mask, count) {
		if (desc[index].name) {
			if (names) {
				strlcpy(names, desc[index].name,
					ETH_GSTRING_LEN);
				names += ETH_GSTRING_LEN;
			}
			++visible;
		}
	}

	return visible;
}

/**
 * efx_nic_update_stats - Convert statistics DMA buffer to array of u64
 * @desc: Array of &struct efx_hw_stat_desc describing the DMA buffer
 *	layout.  DMA widths of 0, 16, 32 and 64 are supported; where
 *	the width is specified as 0 the corresponding element of
 *	@stats is not updated.
 * @count: Length of the @desc array
 * @mask: Bitmask of which elements of @desc are enabled
 * @stats: Buffer to update with the converted statistics.  The length
 *	of this array must be at least @count.
 * @dma_buf: DMA buffer containing hardware statistics
 * @accumulate: If set, the converted values will be added rather than
 *	directly stored to the corresponding elements of @stats
 */
void efx_nic_update_stats(const struct efx_hw_stat_desc *desc, size_t count,
			  const unsigned long *mask,
			  u64 *stats, const void *dma_buf, bool accumulate)
{
	size_t index;

	for_each_set_bit(index, mask, count) {
		if (desc[index].dma_width) {
			const void *addr = dma_buf + desc[index].offset;
			u64 val;

			switch (desc[index].dma_width) {
			case 16:
				val = le16_to_cpup((__le16 *)addr);
				break;
			case 32:
				val = le32_to_cpup((__le32 *)addr);
				break;
			case 64:
				val = le64_to_cpup((__le64 *)addr);
				break;
			default:
				WARN_ON(1);
				val = 0;
				break;
			}

			if (accumulate)
				stats[index] += val;
			else
				stats[index] = val;
		}
	}
}

void efx_nic_fix_nodesc_drop_stat(struct efx_nic *efx, u64 *rx_nodesc_drops)
{
	/* if down, or this is the first update after coming up */
	if (!(efx->net_dev->flags & IFF_UP) || !efx->rx_nodesc_drops_prev_state)
		efx->rx_nodesc_drops_while_down +=
			*rx_nodesc_drops - efx->rx_nodesc_drops_total;
	efx->rx_nodesc_drops_total = *rx_nodesc_drops;
	efx->rx_nodesc_drops_prev_state = !!(efx->net_dev->flags & IFF_UP);
	*rx_nodesc_drops -= efx->rx_nodesc_drops_while_down;
}
Commit	Line	Data
8e730c15	1	/****************************************************************************
f7a6d2c4	2	* Driver for Solarflare network controllers and boards
8e730c15	3	* Copyright 2005-2006 Fen Systems Ltd.
f7a6d2c4	4	* Copyright 2006-2013 Solarflare Communications Inc.
8e730c15 BH	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms of the GNU General Public License version 2 as published
	8	* by the Free Software Foundation, incorporated herein by reference.
	9	*/
	10
	11	#include <linux/bitops.h>
	12	#include <linux/delay.h>
a6b7a407	13	#include <linux/interrupt.h>
8e730c15 BH	14	#include <linux/pci.h>
	15	#include <linux/module.h>
	16	#include <linux/seq_file.h>
1899c111	17	#include <linux/cpu_rmap.h>
8e730c15 BH	18	#include "net_driver.h"
	19	#include "bitfield.h"
	20	#include "efx.h"
	21	#include "nic.h"
137b7922	22	#include "ef10_regs.h"
8b8a95a1	23	#include "farch_regs.h"
8e730c15 BH	24	#include "io.h"
	25	#include "workarounds.h"
	26
8e730c15 BH	27	/**************************************************************************
	28	*
	29	* Generic buffer handling
f7251a9c	30	* These buffers are used for interrupt status, MAC stats, etc.
8e730c15 BH	31	*
	32	**************************************************************************/
	33
	34	int efx_nic_alloc_buffer(struct efx_nic efx, struct efx_buffer buffer,
0d19a540	35	unsigned int len, gfp_t gfp_flags)
8e730c15	36	{
ede23fa8 JP	37	buffer->addr = dma_zalloc_coherent(&efx->pci_dev->dev, len,
ede23fa8 JP	38	&buffer->dma_addr, gfp_flags);
8e730c15 BH	39	if (!buffer->addr)
	40	return -ENOMEM;
	41	buffer->len = len;
8e730c15 BH	42	return 0;
	43	}
	44
	45	void efx_nic_free_buffer(struct efx_nic efx, struct efx_buffer buffer)
	46	{
	47	if (buffer->addr) {
0e33d870 BH	48	dma_free_coherent(&efx->pci_dev->dev, buffer->len,
0e33d870 BH	49	buffer->addr, buffer->dma_addr);
8e730c15 BH	50	buffer->addr = NULL;
	51	}
	52	}
	53
d4fabcc8 BH	54	/* Check whether an event is present in the eventq at the current
	55	* read pointer. Only useful for self-test.
	56	*/
	57	bool efx_nic_event_present(struct efx_channel *channel)
	58	{
	59	return efx_event_present(efx_event(channel, channel->eventq_read_ptr));
	60	}
8e730c15	61
eee6f6a9	62	void efx_nic_event_test_start(struct efx_channel *channel)
8e730c15	63	{
dd40781e	64	channel->event_test_cpu = -1;
eee6f6a9	65	smp_wmb();
86094f7f	66	channel->efx->type->ev_test_generate(channel);
8e730c15 BH	67	}
8e730c15 BH	68
eee6f6a9	69	void efx_nic_irq_test_start(struct efx_nic *efx)
8e730c15	70	{
eee6f6a9 BH	71	efx->last_irq_cpu = -1;
eee6f6a9 BH	72	smp_wmb();
86094f7f	73	efx->type->irq_test_generate(efx);
8e730c15 BH	74	}
	75
	76	/* Hook interrupt handler(s)
	77	* Try MSI and then legacy interrupts.
	78	*/
	79	int efx_nic_init_interrupt(struct efx_nic *efx)
	80	{
	81	struct efx_channel *channel;
1899c111	82	unsigned int n_irqs;
8e730c15 BH	83	int rc;
	84
	85	if (!EFX_INT_MODE_USE_MSI(efx)) {
86094f7f BH	86	rc = request_irq(efx->legacy_irq,
86094f7f BH	87	efx->type->irq_handle_legacy, IRQF_SHARED,
8e730c15 BH	88	efx->name, efx);
8e730c15 BH	89	if (rc) {
62776d03 BH	90	netif_err(efx, drv, efx->net_dev,
	91	"failed to hook legacy IRQ %d\n",
	92	efx->pci_dev->irq);
8e730c15 BH	93	goto fail1;
	94	}
	95	return 0;
	96	}
	97
1899c111 BH	98	#ifdef CONFIG_RFS_ACCEL
	99	if (efx->interrupt_mode == EFX_INT_MODE_MSIX) {
	100	efx->net_dev->rx_cpu_rmap =
	101	alloc_irq_cpu_rmap(efx->n_rx_channels);
	102	if (!efx->net_dev->rx_cpu_rmap) {
	103	rc = -ENOMEM;
	104	goto fail1;
	105	}
	106	}
	107	#endif
	108
8e730c15	109	/* Hook MSI or MSI-X interrupt */
1899c111	110	n_irqs = 0;
8e730c15	111	efx_for_each_channel(channel, efx) {
86094f7f	112	rc = request_irq(channel->irq, efx->type->irq_handle_msi,
8e730c15	113	IRQF_PROBE_SHARED, /* Not shared */
d8291187 BH	114	efx->msi_context[channel->channel].name,
d8291187 BH	115	&efx->msi_context[channel->channel]);
8e730c15	116	if (rc) {
62776d03 BH	117	netif_err(efx, drv, efx->net_dev,
62776d03 BH	118	"failed to hook IRQ %d\n", channel->irq);
8e730c15 BH	119	goto fail2;
8e730c15 BH	120	}
1899c111 BH	121	++n_irqs;
	122
	123	#ifdef CONFIG_RFS_ACCEL
	124	if (efx->interrupt_mode == EFX_INT_MODE_MSIX &&
	125	channel->channel < efx->n_rx_channels) {
	126	rc = irq_cpu_rmap_add(efx->net_dev->rx_cpu_rmap,
	127	channel->irq);
	128	if (rc)
	129	goto fail2;
	130	}
	131	#endif
8e730c15 BH	132	}
	133
	134	return 0;
	135
	136	fail2:
1899c111 BH	137	#ifdef CONFIG_RFS_ACCEL
	138	free_irq_cpu_rmap(efx->net_dev->rx_cpu_rmap);
	139	efx->net_dev->rx_cpu_rmap = NULL;
	140	#endif
	141	efx_for_each_channel(channel, efx) {
	142	if (n_irqs-- == 0)
	143	break;
d8291187	144	free_irq(channel->irq, &efx->msi_context[channel->channel]);
1899c111	145	}
8e730c15 BH	146	fail1:
	147	return rc;
	148	}
	149
	150	void efx_nic_fini_interrupt(struct efx_nic *efx)
	151	{
	152	struct efx_channel *channel;
8e730c15	153
1899c111 BH	154	#ifdef CONFIG_RFS_ACCEL
	155	free_irq_cpu_rmap(efx->net_dev->rx_cpu_rmap);
	156	efx->net_dev->rx_cpu_rmap = NULL;
	157	#endif
	158
8e730c15	159	/* Disable MSI/MSI-X interrupts */
1899c111	160	efx_for_each_channel(channel, efx)
d8291187	161	free_irq(channel->irq, &efx->msi_context[channel->channel]);
8e730c15	162
8e730c15 BH	163	/* Disable legacy interrupt */
	164	if (efx->legacy_irq)
	165	free_irq(efx->legacy_irq, efx);
	166	}
	167
5b98c1bf BH	168	/* Register dump */
5b98c1bf BH	169
137b7922 BH	170	#define REGISTER_REVISION_FA 1
	171	#define REGISTER_REVISION_FB 2
	172	#define REGISTER_REVISION_FC 3
	173	#define REGISTER_REVISION_FZ 3 /* last Falcon arch revision */
	174	#define REGISTER_REVISION_ED 4
	175	#define REGISTER_REVISION_EZ 4 /* latest EF10 revision */
5b98c1bf BH	176
	177	struct efx_nic_reg {
	178	u32 offset:24;
137b7922	179	u32 min_revision:3, max_revision:3;
5b98c1bf BH	180	};
5b98c1bf BH	181
137b7922 BH	182	#define REGISTER(name, arch, min_rev, max_rev) { \
	183	arch ## R_ ## min_rev ## max_rev ## _ ## name, \
	184	REGISTER_REVISION_ ## arch ## min_rev, \
	185	REGISTER_REVISION_ ## arch ## max_rev \
5b98c1bf	186	}
137b7922 BH	187	#define REGISTER_AA(name) REGISTER(name, F, A, A)
	188	#define REGISTER_AB(name) REGISTER(name, F, A, B)
	189	#define REGISTER_AZ(name) REGISTER(name, F, A, Z)
	190	#define REGISTER_BB(name) REGISTER(name, F, B, B)
	191	#define REGISTER_BZ(name) REGISTER(name, F, B, Z)
	192	#define REGISTER_CZ(name) REGISTER(name, F, C, Z)
	193	#define REGISTER_DZ(name) REGISTER(name, E, D, Z)
5b98c1bf BH	194
	195	static const struct efx_nic_reg efx_nic_regs[] = {
	196	REGISTER_AZ(ADR_REGION),
	197	REGISTER_AZ(INT_EN_KER),
	198	REGISTER_BZ(INT_EN_CHAR),
	199	REGISTER_AZ(INT_ADR_KER),
	200	REGISTER_BZ(INT_ADR_CHAR),
	201	/* INT_ACK_KER is WO */
	202	/* INT_ISR0 is RC */
	203	REGISTER_AZ(HW_INIT),
	204	REGISTER_CZ(USR_EV_CFG),
	205	REGISTER_AB(EE_SPI_HCMD),
	206	REGISTER_AB(EE_SPI_HADR),
	207	REGISTER_AB(EE_SPI_HDATA),
	208	REGISTER_AB(EE_BASE_PAGE),
	209	REGISTER_AB(EE_VPD_CFG0),
	210	/* EE_VPD_SW_CNTL and EE_VPD_SW_DATA are not used */
	211	/* PMBX_DBG_IADDR and PBMX_DBG_IDATA are indirect */
	212	/* PCIE_CORE_INDIRECT is indirect */
	213	REGISTER_AB(NIC_STAT),
	214	REGISTER_AB(GPIO_CTL),
	215	REGISTER_AB(GLB_CTL),
	216	/* FATAL_INTR_KER and FATAL_INTR_CHAR are partly RC */
	217	REGISTER_BZ(DP_CTRL),
	218	REGISTER_AZ(MEM_STAT),
	219	REGISTER_AZ(CS_DEBUG),
	220	REGISTER_AZ(ALTERA_BUILD),
	221	REGISTER_AZ(CSR_SPARE),
	222	REGISTER_AB(PCIE_SD_CTL0123),
	223	REGISTER_AB(PCIE_SD_CTL45),
	224	REGISTER_AB(PCIE_PCS_CTL_STAT),
	225	/* DEBUG_DATA_OUT is not used */
	226	/* DRV_EV is WO */
	227	REGISTER_AZ(EVQ_CTL),
	228	REGISTER_AZ(EVQ_CNT1),
	229	REGISTER_AZ(EVQ_CNT2),
	230	REGISTER_AZ(BUF_TBL_CFG),
	231	REGISTER_AZ(SRM_RX_DC_CFG),
	232	REGISTER_AZ(SRM_TX_DC_CFG),
	233	REGISTER_AZ(SRM_CFG),
	234	/* BUF_TBL_UPD is WO */
	235	REGISTER_AZ(SRM_UPD_EVQ),
	236	REGISTER_AZ(SRAM_PARITY),
	237	REGISTER_AZ(RX_CFG),
	238	REGISTER_BZ(RX_FILTER_CTL),
	239	/* RX_FLUSH_DESCQ is WO */
	240	REGISTER_AZ(RX_DC_CFG),
	241	REGISTER_AZ(RX_DC_PF_WM),
	242	REGISTER_BZ(RX_RSS_TKEY),
	243	/* RX_NODESC_DROP is RC */
	244	REGISTER_AA(RX_SELF_RST),
	245	/* RX_DEBUG, RX_PUSH_DROP are not used */
	246	REGISTER_CZ(RX_RSS_IPV6_REG1),
	247	REGISTER_CZ(RX_RSS_IPV6_REG2),
	248	REGISTER_CZ(RX_RSS_IPV6_REG3),
	249	/* TX_FLUSH_DESCQ is WO */
	250	REGISTER_AZ(TX_DC_CFG),
	251	REGISTER_AA(TX_CHKSM_CFG),
	252	REGISTER_AZ(TX_CFG),
	253	/* TX_PUSH_DROP is not used */
	254	REGISTER_AZ(TX_RESERVED),
	255	REGISTER_BZ(TX_PACE),
	256	/* TX_PACE_DROP_QID is RC */
	257	REGISTER_BB(TX_VLAN),
258	REGISTER_BZ(TX_IPFIL_PORTEN),
259	REGISTER_AB(MD_TXD),
260	REGISTER_AB(MD_RXD),
261	REGISTER_AB(MD_CS),
262	REGISTER_AB(MD_PHY_ADR),
263	REGISTER_AB(MD_ID),
264	/* MD_STAT is RC */
265	REGISTER_AB(MAC_STAT_DMA),
266	REGISTER_AB(MAC_CTRL),
267	REGISTER_BB(GEN_MODE),
268	REGISTER_AB(MAC_MC_HASH_REG0),
269	REGISTER_AB(MAC_MC_HASH_REG1),
270	REGISTER_AB(GM_CFG1),
271	REGISTER_AB(GM_CFG2),
272	/* GM_IPG and GM_HD are not used */
273	REGISTER_AB(GM_MAX_FLEN),
274	/* GM_TEST is not used */
275	REGISTER_AB(GM_ADR1),
276	REGISTER_AB(GM_ADR2),
277	REGISTER_AB(GMF_CFG0),
278	REGISTER_AB(GMF_CFG1),
279	REGISTER_AB(GMF_CFG2),
280	REGISTER_AB(GMF_CFG3),
281	REGISTER_AB(GMF_CFG4),
282	REGISTER_AB(GMF_CFG5),
283	REGISTER_BB(TX_SRC_MAC_CTL),
284	REGISTER_AB(XM_ADR_LO),
285	REGISTER_AB(XM_ADR_HI),
286	REGISTER_AB(XM_GLB_CFG),
287	REGISTER_AB(XM_TX_CFG),
288	REGISTER_AB(XM_RX_CFG),
289	REGISTER_AB(XM_MGT_INT_MASK),
290	REGISTER_AB(XM_FC),
291	REGISTER_AB(XM_PAUSE_TIME),
292	REGISTER_AB(XM_TX_PARAM),
293	REGISTER_AB(XM_RX_PARAM),
294	/* XM_MGT_INT_MSK (note no 'A') is RC */
295	REGISTER_AB(XX_PWR_RST),
296	REGISTER_AB(XX_SD_CTL),
297	REGISTER_AB(XX_TXDRV_CTL),
298	/* XX_PRBS_CTL, XX_PRBS_CHK and XX_PRBS_ERR are not used */
299	/* XX_CORE_STAT is partly RC */
137b7922 BH	300	REGISTER_DZ(BIU_HW_REV_ID),
	301	REGISTER_DZ(MC_DB_LWRD),
	302	REGISTER_DZ(MC_DB_HWRD),
5b98c1bf BH	303	};
	304
	305	struct efx_nic_reg_table {
	306	u32 offset:24;
137b7922	307	u32 min_revision:3, max_revision:3;
5b98c1bf BH	308	u32 step:6, rows:21;
	309	};
	310
137b7922	311	#define REGISTER_TABLE_DIMENSIONS(_, offset, arch, min_rev, max_rev, step, rows) { \
5b98c1bf	312	offset, \
137b7922 BH	313	REGISTER_REVISION_ ## arch ## min_rev, \
137b7922 BH	314	REGISTER_REVISION_ ## arch ## max_rev, \
5b98c1bf BH	315	step, rows \
5b98c1bf BH	316	}
137b7922	317	#define REGISTER_TABLE(name, arch, min_rev, max_rev) \
5b98c1bf	318	REGISTER_TABLE_DIMENSIONS( \
137b7922 BH	319	name, arch ## R_ ## min_rev ## max_rev ## _ ## name, \
	320	arch, min_rev, max_rev, \
	321	arch ## R_ ## min_rev ## max_rev ## _ ## name ## _STEP, \
	322	arch ## R_ ## min_rev ## max_rev ## _ ## name ## _ROWS)
	323	#define REGISTER_TABLE_AA(name) REGISTER_TABLE(name, F, A, A)
	324	#define REGISTER_TABLE_AZ(name) REGISTER_TABLE(name, F, A, Z)
	325	#define REGISTER_TABLE_BB(name) REGISTER_TABLE(name, F, B, B)
	326	#define REGISTER_TABLE_BZ(name) REGISTER_TABLE(name, F, B, Z)
5b98c1bf	327	#define REGISTER_TABLE_BB_CZ(name) \
137b7922	328	REGISTER_TABLE_DIMENSIONS(name, FR_BZ_ ## name, F, B, B, \
5b98c1bf BH	329	FR_BZ_ ## name ## _STEP, \
5b98c1bf BH	330	FR_BB_ ## name ## _ROWS), \
137b7922	331	REGISTER_TABLE_DIMENSIONS(name, FR_BZ_ ## name, F, C, Z, \
5b98c1bf BH	332	FR_BZ_ ## name ## _STEP, \
5b98c1bf BH	333	FR_CZ_ ## name ## _ROWS)
137b7922 BH	334	#define REGISTER_TABLE_CZ(name) REGISTER_TABLE(name, F, C, Z)
137b7922 BH	335	#define REGISTER_TABLE_DZ(name) REGISTER_TABLE(name, E, D, Z)
5b98c1bf BH	336
	337	static const struct efx_nic_reg_table efx_nic_reg_tables[] = {
	338	/* DRIVER is not used */
	339	/* EVQ_RPTR, TIMER_COMMAND, USR_EV and {RX,TX}_DESC_UPD are WO */
	340	REGISTER_TABLE_BB(TX_IPFIL_TBL),
	341	REGISTER_TABLE_BB(TX_SRC_MAC_TBL),
	342	REGISTER_TABLE_AA(RX_DESC_PTR_TBL_KER),
	343	REGISTER_TABLE_BB_CZ(RX_DESC_PTR_TBL),
	344	REGISTER_TABLE_AA(TX_DESC_PTR_TBL_KER),
	345	REGISTER_TABLE_BB_CZ(TX_DESC_PTR_TBL),
	346	REGISTER_TABLE_AA(EVQ_PTR_TBL_KER),
	347	REGISTER_TABLE_BB_CZ(EVQ_PTR_TBL),
75abc51c	348	/* We can't reasonably read all of the buffer table (up to 8MB!).
5b98c1bf BH	349	* However this driver will only use a few entries. Reading
	350	* 1K entries allows for some expansion of queue count and
	351	* size before we need to change the version. */
	352	REGISTER_TABLE_DIMENSIONS(BUF_FULL_TBL_KER, FR_AA_BUF_FULL_TBL_KER,
137b7922	353	F, A, A, 8, 1024),
5b98c1bf	354	REGISTER_TABLE_DIMENSIONS(BUF_FULL_TBL, FR_BZ_BUF_FULL_TBL,
137b7922	355	F, B, Z, 8, 1024),
5b98c1bf BH	356	REGISTER_TABLE_CZ(RX_MAC_FILTER_TBL0),
	357	REGISTER_TABLE_BB_CZ(TIMER_TBL),
	358	REGISTER_TABLE_BB_CZ(TX_PACE_TBL),
	359	REGISTER_TABLE_BZ(RX_INDIRECTION_TBL),
	360	/* TX_FILTER_TBL0 is huge and not used by this driver */
	361	REGISTER_TABLE_CZ(TX_MAC_FILTER_TBL0),
	362	REGISTER_TABLE_CZ(MC_TREG_SMEM),
	363	/* MSIX_PBA_TABLE is not mapped */
	364	/* SRM_DBG is not mapped (and is redundant with BUF_FLL_TBL) */
75abc51c	365	REGISTER_TABLE_BZ(RX_FILTER_TBL0),
137b7922	366	REGISTER_TABLE_DZ(BIU_MC_SFT_STATUS),
5b98c1bf BH	367	};
	368
	369	size_t efx_nic_get_regs_len(struct efx_nic *efx)
	370	{
	371	const struct efx_nic_reg *reg;
	372	const struct efx_nic_reg_table *table;
	373	size_t len = 0;
	374
	375	for (reg = efx_nic_regs;
	376	reg < efx_nic_regs + ARRAY_SIZE(efx_nic_regs);
	377	reg++)
	378	if (efx->type->revision >= reg->min_revision &&
	379	efx->type->revision <= reg->max_revision)
	380	len += sizeof(efx_oword_t);
	381
	382	for (table = efx_nic_reg_tables;
	383	table < efx_nic_reg_tables + ARRAY_SIZE(efx_nic_reg_tables);
	384	table++)
	385	if (efx->type->revision >= table->min_revision &&
	386	efx->type->revision <= table->max_revision)
	387	len += table->rows * min_t(size_t, table->step, 16);
	388
	389	return len;
	390	}
	391
	392	void efx_nic_get_regs(struct efx_nic efx, void buf)
	393	{
	394	const struct efx_nic_reg *reg;
	395	const struct efx_nic_reg_table *table;
	396
	397	for (reg = efx_nic_regs;
	398	reg < efx_nic_regs + ARRAY_SIZE(efx_nic_regs);
	399	reg++) {
	400	if (efx->type->revision >= reg->min_revision &&
	401	efx->type->revision <= reg->max_revision) {
	402	efx_reado(efx, (efx_oword_t *)buf, reg->offset);
	403	buf += sizeof(efx_oword_t);
	404	}
	405	}
	406
	407	for (table = efx_nic_reg_tables;
	408	table < efx_nic_reg_tables + ARRAY_SIZE(efx_nic_reg_tables);
	409	table++) {
	410	size_t size, i;
	411
	412	if (!(efx->type->revision >= table->min_revision &&
	413	efx->type->revision <= table->max_revision))
	414	continue;
	415
	416	size = min_t(size_t, table->step, 16);
	417
	418	for (i = 0; i < table->rows; i++) {
	419	switch (table->step) {
778cdaf6 BH	420	case 4: /* 32-bit SRAM */
778cdaf6 BH	421	efx_readd(efx, buf, table->offset + 4 * i);
5b98c1bf BH	422	break;
	423	case 8: /* 64-bit SRAM */
	424	efx_sram_readq(efx,
	425	efx->membase + table->offset,
	426	buf, i);
	427	break;
778cdaf6	428	case 16: /* 128-bit-readable register */
5b98c1bf BH	429	efx_reado_table(efx, buf, table->offset, i);
	430	break;
	431	case 32: /* 128-bit register, interleaved */
	432	efx_reado_table(efx, buf, table->offset, 2 * i);
	433	break;
	434	default:
	435	WARN_ON(1);
	436	return;
	437	}
	438	buf += size;
	439	}
	440	}
	441	}
cd0ecc9a BH	442
	443	/**
	444	* efx_nic_describe_stats - Describe supported statistics for ethtool
	445	* @desc: Array of &struct efx_hw_stat_desc describing the statistics
	446	* @count: Length of the @desc array
	447	* @mask: Bitmask of which elements of @desc are enabled
	448	* @names: Buffer to copy names to, or %NULL. The names are copied
	449	* starting at intervals of %ETH_GSTRING_LEN bytes.
	450	*
	451	* Returns the number of visible statistics, i.e. the number of set
	452	* bits in the first @count bits of @mask for which a name is defined.
	453	*/
	454	size_t efx_nic_describe_stats(const struct efx_hw_stat_desc *desc, size_t count,
	455	const unsigned long mask, u8 names)
	456	{
	457	size_t visible = 0;
	458	size_t index;
	459
	460	for_each_set_bit(index, mask, count) {
	461	if (desc[index].name) {
	462	if (names) {
	463	strlcpy(names, desc[index].name,
	464	ETH_GSTRING_LEN);
	465	names += ETH_GSTRING_LEN;
	466	}
	467	++visible;
	468	}
	469	}
	470
	471	return visible;
	472	}
	473
	474	/**
	475	* efx_nic_update_stats - Convert statistics DMA buffer to array of u64
	476	* @desc: Array of &struct efx_hw_stat_desc describing the DMA buffer
	477	* layout. DMA widths of 0, 16, 32 and 64 are supported; where
	478	* the width is specified as 0 the corresponding element of
	479	* @stats is not updated.
	480	* @count: Length of the @desc array
	481	* @mask: Bitmask of which elements of @desc are enabled
	482	* @stats: Buffer to update with the converted statistics. The length
87648cc9	483	* of this array must be at least @count.
cd0ecc9a BH	484	* @dma_buf: DMA buffer containing hardware statistics
	485	* @accumulate: If set, the converted values will be added rather than
	486	* directly stored to the corresponding elements of @stats
	487	*/
	488	void efx_nic_update_stats(const struct efx_hw_stat_desc *desc, size_t count,
	489	const unsigned long *mask,
	490	u64 stats, const void dma_buf, bool accumulate)
	491	{
	492	size_t index;
	493
	494	for_each_set_bit(index, mask, count) {
	495	if (desc[index].dma_width) {
	496	const void *addr = dma_buf + desc[index].offset;
	497	u64 val;
	498
	499	switch (desc[index].dma_width) {
	500	case 16:
	501	val = le16_to_cpup((__le16 *)addr);
	502	break;
	503	case 32:
	504	val = le32_to_cpup((__le32 *)addr);
	505	break;
	506	case 64:
	507	val = le64_to_cpup((__le64 *)addr);
	508	break;
	509	default:
	510	WARN_ON(1);
	511	val = 0;
	512	break;
	513	}
	514
	515	if (accumulate)
87648cc9	516	stats[index] += val;
cd0ecc9a	517	else
87648cc9	518	stats[index] = val;
cd0ecc9a	519	}
cd0ecc9a BH	520	}
cd0ecc9a BH	521	}
f8f3b5ae JC	522
	523	void efx_nic_fix_nodesc_drop_stat(struct efx_nic efx, u64 rx_nodesc_drops)
	524	{
	525	/* if down, or this is the first update after coming up */
	526	if (!(efx->net_dev->flags & IFF_UP) \|\| !efx->rx_nodesc_drops_prev_state)
	527	efx->rx_nodesc_drops_while_down +=
	528	*rx_nodesc_drops - efx->rx_nodesc_drops_total;
	529	efx->rx_nodesc_drops_total = *rx_nodesc_drops;
	530	efx->rx_nodesc_drops_prev_state = !!(efx->net_dev->flags & IFF_UP);
	531	*rx_nodesc_drops -= efx->rx_nodesc_drops_while_down;
	532	}
	533